1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steven McGeady, Intel Corp.
5 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
6 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
48 #include "target-def.h"
50 /* Save the operands last given to a compare for use when we
51 generate a scc or bcc insn. */
53 rtx i960_compare_op0, i960_compare_op1;
55 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
58 int i960_maxbitalignment;
59 int i960_last_maxbitalignment;
61 /* Used to implement switching between MEM and ALU insn types, for better
62 C series performance. */
64 enum insn_types i960_last_insn_type;
66 /* The leaf-procedure return register. Set only if this is a leaf routine. */
68 static int i960_leaf_ret_reg;
70 /* True if replacing tail calls with jumps is OK. */
72 static int tail_call_ok;
74 /* A string containing a list of insns to emit in the epilogue so as to
75 restore all registers saved by the prologue. Created by the prologue
76 code as it saves registers away. */
78 char epilogue_string[1000];
80 /* A unique number (per function) for return labels. */
82 static int ret_label = 0;
84 /* This is true if FNDECL is either a varargs or a stdarg function.
85 This is used to help identify functions that use an argument block. */
87 #define VARARGS_STDARG_FUNCTION(FNDECL) \
88 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
89 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
90 || current_function_varargs)
92 /* Initialize the GCC target structure. */
94 struct gcc_target target = TARGET_INITIALIZER;
96 /* Initialize variables before compiling any files. */
101 if (TARGET_IC_COMPAT2_0)
103 i960_maxbitalignment = 8;
104 i960_last_maxbitalignment = 128;
108 i960_maxbitalignment = 128;
109 i960_last_maxbitalignment = 8;
113 /* Return true if OP can be used as the source of an fp move insn. */
116 fpmove_src_operand (op, mode)
118 enum machine_mode mode;
120 return (GET_CODE (op) == CONST_DOUBLE || general_operand (op, mode));
124 /* Return true if OP is a register or zero. */
127 reg_or_zero_operand (op, mode)
129 enum machine_mode mode;
131 return register_operand (op, mode) || op == const0_rtx;
135 /* Return truth value of whether OP can be used as an operands in a three
136 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
139 arith_operand (op, mode)
141 enum machine_mode mode;
143 return (register_operand (op, mode) || literal (op, mode));
146 /* Return truth value of whether OP can be used as an operands in a three
147 address logic insn, possibly complementing OP, of mode MODE. */
150 logic_operand (op, mode)
152 enum machine_mode mode;
154 return (register_operand (op, mode)
155 || (GET_CODE (op) == CONST_INT
156 && INTVAL(op) >= -32 && INTVAL(op) < 32));
159 /* Return true if OP is a register or a valid floating point literal. */
162 fp_arith_operand (op, mode)
164 enum machine_mode mode;
166 return (register_operand (op, mode) || fp_literal (op, mode));
169 /* Return true if OP is a register or a valid signed integer literal. */
172 signed_arith_operand (op, mode)
174 enum machine_mode mode;
176 return (register_operand (op, mode) || signed_literal (op, mode));
179 /* Return truth value of whether OP is a integer which fits the
180 range constraining immediate operands in three-address insns. */
185 enum machine_mode mode ATTRIBUTE_UNUSED;
187 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) >= 0 && INTVAL(op) < 32);
190 /* Return true if OP is a float constant of 1. */
193 fp_literal_one (op, mode)
195 enum machine_mode mode;
197 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST1_RTX (mode));
200 /* Return true if OP is a float constant of 0. */
203 fp_literal_zero (op, mode)
205 enum machine_mode mode;
207 return (TARGET_NUMERICS && mode == GET_MODE (op) && op == CONST0_RTX (mode));
210 /* Return true if OP is a valid floating point literal. */
215 enum machine_mode mode;
217 return fp_literal_zero (op, mode) || fp_literal_one (op, mode);
220 /* Return true if OP is a valid signed immediate constant. */
223 signed_literal(op, mode)
225 enum machine_mode mode ATTRIBUTE_UNUSED;
227 return ((GET_CODE (op) == CONST_INT) && INTVAL(op) > -32 && INTVAL(op) < 32);
230 /* Return truth value of statement that OP is a symbolic memory
231 operand of mode MODE. */
234 symbolic_memory_operand (op, mode)
236 enum machine_mode mode ATTRIBUTE_UNUSED;
238 if (GET_CODE (op) == SUBREG)
239 op = SUBREG_REG (op);
240 if (GET_CODE (op) != MEM)
243 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
244 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
247 /* Return truth value of whether OP is EQ or NE. */
252 enum machine_mode mode ATTRIBUTE_UNUSED;
254 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
257 /* OP is an integer register or a constant. */
260 arith32_operand (op, mode)
262 enum machine_mode mode;
264 if (register_operand (op, mode))
266 return (CONSTANT_P (op));
269 /* Return true if OP is an integer constant which is a power of 2. */
272 power2_operand (op,mode)
274 enum machine_mode mode ATTRIBUTE_UNUSED;
276 if (GET_CODE (op) != CONST_INT)
279 return exact_log2 (INTVAL (op)) >= 0;
282 /* Return true if OP is an integer constant which is the complement of a
286 cmplpower2_operand (op, mode)
288 enum machine_mode mode ATTRIBUTE_UNUSED;
290 if (GET_CODE (op) != CONST_INT)
293 return exact_log2 (~ INTVAL (op)) >= 0;
296 /* If VAL has only one bit set, return the index of that bit. Otherwise
305 for (i = 0; val != 0; i++, val >>= 1)
317 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
318 The return value indicates how many consecutive non-zero bits exist
319 if this is a mask. This is the same as the next function, except that
320 it does not indicate what the start and stop bit positions are. */
326 register int start, end, i;
329 for (i = 0; val != 0; val >>= 1, i++)
339 /* Still looking for the first bit. */
343 /* We've seen the start of a bit sequence, and now a zero. There
344 must be more one bits, otherwise we would have exited the loop.
345 Therefore, it is not a mask. */
350 /* The bit string has ones from START to END bit positions only. */
351 return end - start + 1;
354 /* If VAL is a mask, then return nonzero, with S set to the starting bit
355 position and E set to the ending bit position of the mask. The return
356 value indicates how many consecutive bits exist in the mask. This is
357 the same as the previous function, except that it also indicates the
358 start and end bit positions of the mask. */
365 register int start, end, i;
369 for (i = 0; val != 0; val >>= 1, i++)
380 /* Still looking for the first bit. */
384 /* We've seen the start of a bit sequence, and now a zero. There
385 must be more one bits, otherwise we would have exited the loop.
386 Therefor, it is not a mask. */
395 /* The bit string has ones from START to END bit positions only. */
398 return ((start < 0) ? 0 : end - start + 1);
401 /* Return the machine mode to use for a comparison. */
404 select_cc_mode (op, x)
406 rtx x ATTRIBUTE_UNUSED;
408 if (op == GTU || op == LTU || op == GEU || op == LEU)
413 /* X and Y are two things to compare using CODE. Emit the compare insn and
414 return the rtx for register 36 in the proper mode. */
417 gen_compare_reg (code, x, y)
422 enum machine_mode ccmode = SELECT_CC_MODE (code, x, y);
423 enum machine_mode mode
424 = GET_MODE (x) == VOIDmode ? GET_MODE (y) : GET_MODE (x);
428 if (! arith_operand (x, mode))
429 x = force_reg (SImode, x);
430 if (! arith_operand (y, mode))
431 y = force_reg (SImode, y);
434 cc_reg = gen_rtx_REG (ccmode, 36);
435 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
436 gen_rtx_COMPARE (ccmode, x, y)));
441 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
442 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
443 are 4. Indexed addresses are cost 6. */
445 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
448 i960_address_cost (x)
452 /* Handled before calling here. */
453 if (GET_CODE (x) == REG)
456 /* This is a MEMA operand -- it's free. */
457 if (GET_CODE (x) == CONST_INT
459 && INTVAL (x) < 4096)
462 if (GET_CODE (x) == PLUS)
464 rtx base = XEXP (x, 0);
465 rtx offset = XEXP (x, 1);
467 if (GET_CODE (base) == SUBREG)
468 base = SUBREG_REG (base);
469 if (GET_CODE (offset) == SUBREG)
470 offset = SUBREG_REG (offset);
472 if (GET_CODE (base) == REG)
474 if (GET_CODE (offset) == REG)
476 if (GET_CODE (offset) == CONST_INT)
478 if ((unsigned)INTVAL (offset) < 2047)
482 if (CONSTANT_P (offset))
485 if (GET_CODE (base) == PLUS || GET_CODE (base) == MULT)
488 /* This is an invalid address. The return value doesn't matter, but
489 for convenience we make this more expensive than anything else. */
492 if (GET_CODE (x) == MULT)
495 /* Symbol_refs and other unrecognized addresses are cost 4. */
499 /* Emit insns to move operands[1] into operands[0].
501 Return 1 if we have written out everything that needs to be done to
502 do the move. Otherwise, return 0 and the caller will emit the move
506 emit_move_sequence (operands, mode)
508 enum machine_mode mode;
510 /* We can only store registers to memory. */
512 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG
513 && (operands[1] != const0_rtx || current_function_args_size
514 || current_function_varargs || current_function_stdarg
515 || rtx_equal_function_value_matters))
516 /* Here we use the same test as movsi+1 pattern -- see i960.md. */
517 operands[1] = force_reg (mode, operands[1]);
519 /* Storing multi-word values in unaligned hard registers to memory may
520 require a scratch since we have to store them a register at a time and
521 adding 4 to the memory address may not yield a valid insn. */
522 /* ??? We don't always need the scratch, but that would complicate things.
524 /* ??? We must also handle stores to pseudos here, because the pseudo may be
525 replaced with a MEM later. This would be cleaner if we didn't have
526 a separate pattern for unaligned DImode/TImode stores. */
527 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
528 && (GET_CODE (operands[0]) == MEM
529 || (GET_CODE (operands[0]) == REG
530 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
531 && GET_CODE (operands[1]) == REG
532 && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
533 && ! HARD_REGNO_MODE_OK (REGNO (operands[1]), mode))
535 emit_insn (gen_rtx_PARALLEL
538 gen_rtx_SET (VOIDmode, operands[0], operands[1]),
539 gen_rtx_CLOBBER (VOIDmode,
540 gen_rtx_SCRATCH (Pmode)))));
547 /* Output assembler to move a double word value. */
550 i960_output_move_double (dst, src)
555 if (GET_CODE (dst) == REG
556 && GET_CODE (src) == REG)
558 if ((REGNO (src) & 1)
559 || (REGNO (dst) & 1))
561 /* We normally copy the low-numbered register first. However, if
562 the second source register is the same as the first destination
563 register, we must copy in the opposite order. */
564 if (REGNO (src) + 1 == REGNO (dst))
565 return "mov %D1,%D0\n\tmov %1,%0";
567 return "mov %1,%0\n\tmov %D1,%D0";
572 else if (GET_CODE (dst) == REG
573 && GET_CODE (src) == CONST_INT
574 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
577 return "mov %1,%0\n\tmov 0,%D0";
581 else if (GET_CODE (dst) == REG
582 && GET_CODE (src) == MEM)
586 /* One can optimize a few cases here, but you have to be
587 careful of clobbering registers used in the address and
591 operands[2] = gen_rtx_REG (Pmode, REGNO (dst) + 1);
592 operands[3] = gen_rtx_MEM (word_mode, operands[2]);
593 operands[4] = adjust_address (operands[3], word_mode,
596 ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands);
602 else if (GET_CODE (dst) == MEM
603 && GET_CODE (src) == REG)
608 operands[1] = adjust_address (dst, word_mode, UNITS_PER_WORD);
609 if (! memory_address_p (word_mode, XEXP (operands[1], 0)))
612 output_asm_insn ("st %2,%0\n\tst %D2,%1", operands);
621 /* Output assembler to move a double word zero. */
624 i960_output_move_double_zero (dst)
631 operands[1] = adjust_address (dst, word_mode, 4);
632 output_asm_insn ("st g14,%0\n\tst g14,%1", operands);
637 /* Output assembler to move a quad word value. */
640 i960_output_move_quad (dst, src)
645 if (GET_CODE (dst) == REG
646 && GET_CODE (src) == REG)
648 if ((REGNO (src) & 3)
649 || (REGNO (dst) & 3))
651 /* We normally copy starting with the low numbered register.
652 However, if there is an overlap such that the first dest reg
653 is <= the last source reg but not < the first source reg, we
654 must copy in the opposite order. */
655 if (REGNO (dst) <= REGNO (src) + 3
656 && REGNO (dst) >= REGNO (src))
657 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
659 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
664 else if (GET_CODE (dst) == REG
665 && GET_CODE (src) == CONST_INT
666 && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
669 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
673 else if (GET_CODE (dst) == REG
674 && GET_CODE (src) == MEM)
678 /* One can optimize a few cases here, but you have to be
679 careful of clobbering registers used in the address and
683 operands[2] = gen_rtx_REG (Pmode, REGNO (dst) + 3);
684 operands[3] = gen_rtx_MEM (word_mode, operands[2]);
686 = adjust_address (operands[3], word_mode, UNITS_PER_WORD);
688 = adjust_address (operands[4], word_mode, UNITS_PER_WORD);
690 = adjust_address (operands[5], word_mode, UNITS_PER_WORD);
691 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands);
697 else if (GET_CODE (dst) == MEM
698 && GET_CODE (src) == REG)
703 operands[1] = adjust_address (dst, word_mode, UNITS_PER_WORD);
704 operands[2] = adjust_address (dst, word_mode, 2 * UNITS_PER_WORD);
705 operands[3] = adjust_address (dst, word_mode, 3 * UNITS_PER_WORD);
706 if (! memory_address_p (word_mode, XEXP (operands[3], 0)))
709 output_asm_insn ("st %4,%0\n\tst %D4,%1\n\tst %E4,%2\n\tst %F4,%3", operands);
718 /* Output assembler to move a quad word zero. */
721 i960_output_move_quad_zero (dst)
728 operands[1] = adjust_address (dst, word_mode, 4);
729 operands[2] = adjust_address (dst, word_mode, 8);
730 operands[3] = adjust_address (dst, word_mode, 12);
731 output_asm_insn ("st g14,%0\n\tst g14,%1\n\tst g14,%2\n\tst g14,%3", operands);
737 /* Emit insns to load a constant to non-floating point registers.
738 Uses several strategies to try to use as few insns as possible. */
741 i960_output_ldconst (dst, src)
742 register rtx dst, src;
745 register unsigned rsrc2;
746 enum machine_mode mode = GET_MODE (dst);
749 operands[0] = operands[2] = dst;
750 operands[1] = operands[3] = src;
752 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
753 must be a ldconst insn. */
755 if (GET_CODE (src) != CONST_INT && GET_CODE (src) != CONST_DOUBLE)
757 output_asm_insn ("ldconst %1,%0", operands);
760 else if (mode == XFmode)
766 if (fp_literal_zero (src, XFmode))
769 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
770 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d, value_long);
772 output_asm_insn ("# ldconst %1,%0",operands);
774 for (i = 0; i < 3; i++)
776 operands[0] = gen_rtx_REG (SImode, REGNO (dst) + i);
777 operands[1] = GEN_INT (value_long[i]);
778 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
784 else if (mode == DFmode)
788 if (fp_literal_zero (src, DFmode))
791 split_double (src, &first, &second);
793 output_asm_insn ("# ldconst %1,%0",operands);
795 operands[0] = gen_rtx_REG (SImode, REGNO (dst));
797 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
799 operands[0] = gen_rtx_REG (SImode, REGNO (dst) + 1);
800 operands[1] = second;
801 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
805 else if (mode == SFmode)
810 REAL_VALUE_FROM_CONST_DOUBLE (d, src);
811 REAL_VALUE_TO_TARGET_SINGLE (d, value);
813 output_asm_insn ("# ldconst %1,%0",operands);
814 operands[0] = gen_rtx_REG (SImode, REGNO (dst));
815 operands[1] = GEN_INT (value);
816 output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
820 else if (mode == TImode)
822 /* ??? This is currently not handled at all. */
825 /* Note: lowest order word goes in lowest numbered reg. */
826 rsrc1 = INTVAL (src);
827 if (rsrc1 >= 0 && rsrc1 < 32)
830 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands);
831 /* Go pick up the low-order word. */
833 else if (mode == DImode)
835 rtx upperhalf, lowerhalf, xoperands[2];
837 if (GET_CODE (src) == CONST_DOUBLE || GET_CODE (src) == CONST_INT)
838 split_double (src, &lowerhalf, &upperhalf);
843 /* Note: lowest order word goes in lowest numbered reg. */
844 /* Numbers from 0 to 31 can be handled with a single insn. */
845 rsrc1 = INTVAL (lowerhalf);
846 if (upperhalf == const0_rtx && rsrc1 >= 0 && rsrc1 < 32)
849 /* Output the upper half with a recursive call. */
850 xoperands[0] = gen_rtx_REG (SImode, REGNO (dst) + 1);
851 xoperands[1] = upperhalf;
852 output_asm_insn (i960_output_ldconst (xoperands[0], xoperands[1]),
854 /* The lower word is emitted as normally. */
858 rsrc1 = INTVAL (src);
864 else if (mode == HImode)
873 /* ldconst 0..31,X -> mov 0..31,X */
876 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
881 /* ldconst 32..63,X -> add 31,nn,X */
884 if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
886 operands[1] = GEN_INT (rsrc1 - 31);
887 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands);
893 /* ldconst -1..-31 -> sub 0,0..31,X */
896 /* return 'sub -(%1),0,%0' */
897 operands[1] = GEN_INT (- rsrc1);
898 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands);
902 /* ldconst -32 -> not 31,X */
905 operands[1] = GEN_INT (~rsrc1);
906 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands);
911 /* If const is a single bit. */
912 if (bitpos (rsrc1) >= 0)
914 operands[1] = GEN_INT (bitpos (rsrc1));
915 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands);
919 /* If const is a bit string of less than 6 bits (1..31 shifted). */
924 if (bitstr (rsrc1, &s, &e) < 6)
926 rsrc2 = ((unsigned int) rsrc1) >> s;
927 operands[1] = GEN_INT (rsrc2);
928 operands[2] = GEN_INT (s);
929 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands);
934 /* Unimplemented cases:
935 const is in range 0..31 but rotated around end of word:
936 ror 31,3,g0 -> ldconst 0xe0000003,g0
938 and any 2 instruction cases that might be worthwhile */
940 output_asm_insn ("ldconst %1,%0", operands);
944 /* Determine if there is an opportunity for a bypass optimization.
945 Bypass succeeds on the 960K* if the destination of the previous
946 instruction is the second operand of the current instruction.
947 Bypass always succeeds on the C*.
949 Return 1 if the pattern should interchange the operands.
951 CMPBR_FLAG is true if this is for a compare-and-branch insn.
952 OP1 and OP2 are the two source operands of a 3 operand insn. */
955 i960_bypass (insn, op1, op2, cmpbr_flag)
956 register rtx insn, op1, op2;
959 register rtx prev_insn, prev_dest;
964 /* Can't do this if op1 isn't a register. */
968 /* Can't do this for a compare-and-branch if both ops aren't regs. */
969 if (cmpbr_flag && ! REG_P (op2))
972 prev_insn = prev_real_insn (insn);
974 if (prev_insn && GET_CODE (prev_insn) == INSN
975 && GET_CODE (PATTERN (prev_insn)) == SET)
977 prev_dest = SET_DEST (PATTERN (prev_insn));
978 if ((GET_CODE (prev_dest) == REG && REGNO (prev_dest) == REGNO (op1))
979 || (GET_CODE (prev_dest) == SUBREG
980 && GET_CODE (SUBREG_REG (prev_dest)) == REG
981 && REGNO (SUBREG_REG (prev_dest)) == REGNO (op1)))
987 /* Output the code which declares the function name. This also handles
988 leaf routines, which have special requirements, and initializes some
992 i960_function_name_declare (file, name, fndecl)
1001 /* Increment global return label. */
1005 /* Compute whether tail calls and leaf routine optimizations can be performed
1006 for this function. */
1008 if (TARGET_TAILCALL)
1013 if (TARGET_LEAFPROC)
1018 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1019 argblock, because argblock uses g14 implicitly. */
1021 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
1027 /* See if caller passes in an address to return value. */
1029 if (aggregate_value_p (DECL_RESULT (fndecl)))
1035 /* Can not use tail calls or make this a leaf routine if there is a non
1038 if (get_frame_size () != 0)
1041 /* I don't understand this condition, and do not think that it is correct.
1042 Apparently this is just checking whether the frame pointer is used, and
1043 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1046 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1047 if (GET_CODE (insn) == INSN
1048 && reg_mentioned_p (frame_pointer_rtx, insn))
1054 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1057 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1058 if (GET_CODE (insn) == CALL_INSN)
1064 /* Can not be a leaf routine if any non-call clobbered registers are
1065 used in this function. */
1068 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
1069 if (regs_ever_live[i]
1070 && ((! call_used_regs[i]) || (i > 7 && i < 12)))
1072 /* Global registers. */
1073 if (i < 16 && i > 7 && i != 13)
1075 /* Local registers. */
1080 /* Now choose a leaf return register, if we can find one, and if it is
1081 OK for this to be a leaf routine. */
1083 i960_leaf_ret_reg = -1;
1085 if (optimize && leaf_proc_ok)
1087 for (i960_leaf_ret_reg = -1, i = 0; i < 8; i++)
1088 if (regs_ever_live[i] == 0)
1090 i960_leaf_ret_reg = i;
1091 regs_ever_live[i] = 1;
1096 /* Do this after choosing the leaf return register, so it will be listed
1097 if one was chosen. */
1099 fprintf (file, "\t# Function '%s'\n", (name[0] == '*' ? &name[1] : name));
1100 fprintf (file, "\t# Registers used: ");
1102 for (i = 0, j = 0; i < FIRST_PSEUDO_REGISTER; i++)
1104 if (regs_ever_live[i])
1106 fprintf (file, "%s%s ", reg_names[i], call_used_regs[i] ? "" : "*");
1108 if (i > 15 && j == 0)
1110 fprintf (file,"\n\t#\t\t ");
1116 fprintf (file, "\n");
1118 if (i960_leaf_ret_reg >= 0)
1120 /* Make it a leaf procedure. */
1122 if (TREE_PUBLIC (fndecl))
1123 fprintf (file,"\t.globl\t%s.lf\n", (name[0] == '*' ? &name[1] : name));
1125 fprintf (file, "\t.leafproc\t");
1126 assemble_name (file, name);
1127 fprintf (file, ",%s.lf\n", (name[0] == '*' ? &name[1] : name));
1128 ASM_OUTPUT_LABEL (file, name);
1129 fprintf (file, "\tlda Li960R%d,g14\n", ret_label);
1130 fprintf (file, "%s.lf:\n", (name[0] == '*' ? &name[1] : name));
1131 fprintf (file, "\tmov g14,g%d\n", i960_leaf_ret_reg);
1133 if (TARGET_C_SERIES)
1135 fprintf (file, "\tlda 0,g14\n");
1136 i960_last_insn_type = I_TYPE_MEM;
1140 fprintf (file, "\tmov 0,g14\n");
1141 i960_last_insn_type = I_TYPE_REG;
1146 ASM_OUTPUT_LABEL (file, name);
1147 i960_last_insn_type = I_TYPE_CTRL;
1151 /* Compute and return the frame size. */
1154 compute_frame_size (size)
1158 int outgoing_args_size = current_function_outgoing_args_size;
1160 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1161 as size is concerned. */
1162 actual_fsize = (size + 15) & -16;
1163 actual_fsize += (outgoing_args_size + 15) & -16;
1165 return actual_fsize;
1168 /* Here register group is range of registers which can be moved by
1169 one i960 instruction. */
1177 static int i960_form_reg_groups PARAMS ((int, int, int *, int, struct reg_group *));
1178 static int i960_reg_group_compare PARAMS ((const void *, const void *));
1179 static int i960_split_reg_group PARAMS ((struct reg_group *, int, int));
1180 static void i960_arg_size_and_align PARAMS ((enum machine_mode, tree, int *, int *));
1182 /* The following functions forms the biggest as possible register
1183 groups with registers in STATE. REGS contain states of the
1184 registers in range [start, finish_reg). The function returns the
1185 number of groups formed. */
1187 i960_form_reg_groups (start_reg, finish_reg, regs, state, reg_groups)
1192 struct reg_group *reg_groups;
1197 for (i = start_reg; i < finish_reg; )
1199 if (regs [i] != state)
1204 else if (i % 2 != 0 || regs [i + 1] != state)
1205 reg_groups [nw].length = 1;
1206 else if (i % 4 != 0 || regs [i + 2] != state)
1207 reg_groups [nw].length = 2;
1208 else if (regs [i + 3] != state)
1209 reg_groups [nw].length = 3;
1211 reg_groups [nw].length = 4;
1212 reg_groups [nw].start_reg = i;
1213 i += reg_groups [nw].length;
1219 /* We sort register winodws in descending order by length. */
1221 i960_reg_group_compare (group1, group2)
1225 const struct reg_group *w1 = group1;
1226 const struct reg_group *w2 = group2;
1228 if (w1->length > w2->length)
1230 else if (w1->length < w2->length)
1236 /* Split the first register group in REG_GROUPS on subgroups one of
1237 which will contain SUBGROUP_LENGTH registers. The function
1238 returns new number of winodws. */
1240 i960_split_reg_group (reg_groups, nw, subgroup_length)
1241 struct reg_group *reg_groups;
1243 int subgroup_length;
1245 if (subgroup_length < reg_groups->length - subgroup_length)
1246 /* This guarantees correct alignments of the two subgroups for
1247 i960 (see spliting for the group length 2, 3, 4). More
1248 generalized algorithm would require splitting the group more
1250 subgroup_length = reg_groups->length - subgroup_length;
1251 /* More generalized algorithm would require to try merging
1252 subgroups here. But in case i960 it always results in failure
1253 because of register group alignment. */
1254 reg_groups[nw].length = reg_groups->length - subgroup_length;
1255 reg_groups[nw].start_reg = reg_groups->start_reg + subgroup_length;
1257 reg_groups->length = subgroup_length;
1258 qsort (reg_groups, nw, sizeof (struct reg_group), i960_reg_group_compare);
1262 /* Output code for the function prologue. */
1265 i960_function_prologue (file, size)
1269 register int i, j, nr;
1270 int n_saved_regs = 0;
1271 int n_remaining_saved_regs;
1273 int actual_fsize, offset;
1275 struct reg_group *g, *l;
1277 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1279 int regs[FIRST_PSEUDO_REGISTER];
1280 /* All global registers (which must be saved) divided by groups. */
1281 struct reg_group global_reg_groups [16];
1282 /* All local registers (which are available) divided by groups. */
1283 struct reg_group local_reg_groups [16];
1286 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1287 if (regs_ever_live[i]
1288 && ((! call_used_regs[i]) || (i > 7 && i < 12))
1289 /* No need to save the static chain pointer. */
1290 && ! (i == STATIC_CHAIN_REGNUM && current_function_needs_context))
1293 /* Count global registers that need saving. */
1300 n_remaining_saved_regs = n_saved_regs;
1302 epilogue_string[0] = '\0';
1304 if (profile_flag || profile_block_flag)
1306 /* When profiling, we may use registers 20 to 27 to save arguments, so
1307 they can't be used here for saving globals. J is the number of
1308 argument registers the mcount call will save. */
1309 for (j = 7; j >= 0 && ! regs_ever_live[j]; j--)
1312 for (i = 20; i <= j + 20; i++)
1316 gnw = i960_form_reg_groups (0, 16, regs, -1, global_reg_groups);
1317 lnw = i960_form_reg_groups (19, 32, regs, 0, local_reg_groups);
1318 qsort (global_reg_groups, gnw, sizeof (struct reg_group),
1319 i960_reg_group_compare);
1320 qsort (local_reg_groups, lnw, sizeof (struct reg_group),
1321 i960_reg_group_compare);
1322 for (g = global_reg_groups, l = local_reg_groups; lnw != 0 && gnw != 0;)
1324 if (g->length == l->length)
1326 fprintf (file, "\tmov%s %s,%s\n",
1327 ((g->length == 4) ? "q" :
1328 (g->length == 3) ? "t" :
1329 (g->length == 2) ? "l" : ""),
1330 reg_names[(unsigned char) g->start_reg],
1331 reg_names[(unsigned char) l->start_reg]);
1332 sprintf (tmpstr, "\tmov%s %s,%s\n",
1333 ((g->length == 4) ? "q" :
1334 (g->length == 3) ? "t" :
1335 (g->length == 2) ? "l" : ""),
1336 reg_names[(unsigned char) l->start_reg],
1337 reg_names[(unsigned char) g->start_reg]);
1338 strcat (epilogue_string, tmpstr);
1339 n_remaining_saved_regs -= g->length;
1340 for (i = 0; i < g->length; i++)
1342 regs [i + g->start_reg] = 1;
1343 regs [i + l->start_reg] = -1;
1344 regs_ever_live [i + l->start_reg] = 1;
1351 else if (g->length > l->length)
1352 gnw = i960_split_reg_group (g, gnw, l->length);
1354 lnw = i960_split_reg_group (l, lnw, g->length);
1357 actual_fsize = compute_frame_size (size) + 4 * n_remaining_saved_regs;
1359 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1360 size up to the nearest multiple of 16. I don't know whether this is
1361 necessary, or even desirable.
1363 The frame pointer must be aligned, but the call instruction takes care of
1364 that. If we leave the stack pointer unaligned, we may save a little on
1365 dynamic stack allocation. And we don't lose, at least according to the
1367 actual_fsize = (actual_fsize + 15) & ~0xF;
1370 /* Check stack limit if necessary. */
1371 if (current_function_limit_stack)
1373 rtx min_stack = stack_limit_rtx;
1374 if (actual_fsize != 0)
1375 min_stack = plus_constant (stack_limit_rtx, -actual_fsize);
1377 /* Now, emulate a little bit of reload. We want to turn 'min_stack'
1378 into an arith_operand. Use register 20 as the temporary. */
1379 if (legitimate_address_p (Pmode, min_stack, 1)
1380 && !arith_operand (min_stack, Pmode))
1382 rtx tmp = gen_rtx_MEM (Pmode, min_stack);
1383 fputs ("\tlda\t", file);
1384 i960_print_operand (file, tmp, 0);
1385 fputs (",r4\n", file);
1386 min_stack = gen_rtx_REG (Pmode, 20);
1388 if (arith_operand (min_stack, Pmode))
1390 fputs ("\tcmpo\tsp,", file);
1391 i960_print_operand (file, min_stack, 0);
1392 fputs ("\n\tfaultge.f\n", file);
1395 warning ("stack limit expression is not supported");
1398 /* Allocate space for register save and locals. */
1399 if (actual_fsize > 0)
1401 if (actual_fsize < 32)
1402 fprintf (file, "\taddo %d,sp,sp\n", actual_fsize);
1404 fprintf (file, "\tlda\t%d(sp),sp\n", actual_fsize);
1407 /* Take hardware register save area created by the call instruction
1408 into account, but store them before the argument block area. */
1409 lvar_size = actual_fsize - compute_frame_size (0) - n_remaining_saved_regs * 4;
1410 offset = STARTING_FRAME_OFFSET + lvar_size;
1411 /* Save registers on stack if needed. */
1412 /* ??? Is it worth to use the same algorithm as one for saving
1413 global registers in local registers? */
1414 for (i = 0, j = n_remaining_saved_regs; j > 0 && i < 16; i++)
1421 if (i <= 14 && i % 2 == 0 && regs[i+1] == -1 && offset % 2 == 0)
1424 if (nr == 2 && i <= 12 && i % 4 == 0 && regs[i+2] == -1
1428 if (nr == 3 && regs[i+3] == -1)
1431 fprintf (file,"\tst%s %s,%d(fp)\n",
1434 (nr == 2) ? "l" : ""),
1435 reg_names[i], offset);
1436 sprintf (tmpstr,"\tld%s %d(fp),%s\n",
1439 (nr == 2) ? "l" : ""),
1440 offset, reg_names[i]);
1441 strcat (epilogue_string, tmpstr);
1447 if (actual_fsize == 0)
1450 fprintf (file, "\t#Prologue stats:\n");
1451 fprintf (file, "\t# Total Frame Size: %d bytes\n", actual_fsize);
1454 fprintf (file, "\t# Local Variable Size: %d bytes\n", lvar_size);
1456 fprintf (file, "\t# Register Save Size: %d regs, %d bytes\n",
1457 n_saved_regs, n_saved_regs * 4);
1458 fprintf (file, "\t#End Prologue#\n");
1461 /* Output code for the function profiler. */
1464 output_function_profiler (file, labelno)
1468 /* The last used parameter register. */
1470 int i, j, increment;
1471 int varargs_stdarg_function
1472 = VARARGS_STDARG_FUNCTION (current_function_decl);
1474 /* Figure out the last used parameter register. The proper thing to do
1475 is to walk incoming args of the function. A function might have live
1476 parameter registers even if it has no incoming args. Note that we
1477 don't have to save parameter registers g8 to g11 because they are
1480 /* See also output_function_prologue, which tries to use local registers
1481 for preserved call-saved global registers. */
1483 for (last_parm_reg = 7;
1484 last_parm_reg >= 0 && ! regs_ever_live[last_parm_reg];
1488 /* Save parameter registers in regs r4 (20) to r11 (27). */
1490 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1492 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1494 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1496 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1501 fprintf (file, "\tmov%s g%d,r%d\n",
1502 (increment == 4 ? "q" : increment == 3 ? "t"
1503 : increment == 2 ? "l": ""), i, j);
1506 /* If this function uses the arg pointer, then save it in r3 and then
1509 if (current_function_args_size != 0 || varargs_stdarg_function)
1510 fprintf (file, "\tmov g14,r3\n\tmov 0,g14\n");
1512 /* Load location address into g0 and call mcount. */
1514 fprintf (file, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno);
1516 /* If this function uses the arg pointer, restore it. */
1518 if (current_function_args_size != 0 || varargs_stdarg_function)
1519 fprintf (file, "\tmov r3,g14\n");
1521 /* Restore parameter registers. */
1523 for (i = 0, j = 4; i <= last_parm_reg; i += increment, j += increment)
1525 if (i % 4 == 0 && (last_parm_reg - i) >= 3)
1527 else if (i % 4 == 0 && (last_parm_reg - i) >= 2)
1529 else if (i % 2 == 0 && (last_parm_reg - i) >= 1)
1534 fprintf (file, "\tmov%s r%d,g%d\n",
1535 (increment == 4 ? "q" : increment == 3 ? "t"
1536 : increment == 2 ? "l": ""), j, i);
1540 /* Output code for the function epilogue. */
1543 i960_function_epilogue (file, size)
1545 unsigned int size ATTRIBUTE_UNUSED;
1547 if (i960_leaf_ret_reg >= 0)
1549 fprintf (file, "Li960R%d: ret\n", ret_label);
1553 if (*epilogue_string == 0)
1557 /* Emit a return insn, but only if control can fall through to here. */
1559 tmp = get_last_insn ();
1562 if (GET_CODE (tmp) == BARRIER)
1564 if (GET_CODE (tmp) == CODE_LABEL)
1566 if (GET_CODE (tmp) == JUMP_INSN)
1568 if (GET_CODE (PATTERN (tmp)) == RETURN)
1572 if (GET_CODE (tmp) == NOTE)
1574 tmp = PREV_INSN (tmp);
1579 fprintf (file, "Li960R%d: ret\n", ret_label);
1583 fprintf (file, "Li960R%d:\n", ret_label);
1585 fprintf (file, "\t#EPILOGUE#\n");
1587 /* Output the string created by the prologue which will restore all
1588 registers saved by the prologue. */
1590 if (epilogue_string[0] != '\0')
1591 fprintf (file, "%s", epilogue_string);
1593 /* Must clear g14 on return if this function set it.
1594 Only varargs/stdarg functions modify g14. */
1596 if (VARARGS_STDARG_FUNCTION (current_function_decl))
1597 fprintf (file, "\tmov 0,g14\n");
1599 fprintf (file, "\tret\n");
1600 fprintf (file, "\t#End Epilogue#\n");
1603 /* Output code for a call insn. */
1606 i960_output_call_insn (target, argsize_rtx, arg_pointer, insn)
1607 register rtx target, argsize_rtx, arg_pointer, insn;
1609 int argsize = INTVAL (argsize_rtx);
1610 rtx nexti = next_real_insn (insn);
1612 int varargs_stdarg_function
1613 = VARARGS_STDARG_FUNCTION (current_function_decl);
1615 operands[0] = target;
1616 operands[1] = arg_pointer;
1618 if (current_function_args_size != 0 || varargs_stdarg_function)
1619 output_asm_insn ("mov g14,r3", operands);
1622 output_asm_insn ("lda %a1,g14", operands);
1623 else if (current_function_args_size != 0 || varargs_stdarg_function)
1624 output_asm_insn ("mov 0,g14", operands);
1626 /* The code used to assume that calls to SYMBOL_REFs could not be more
1627 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1628 feature is now implemented by relaxing in the GNU linker. It can convert
1629 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1631 /* Nexti could be zero if the called routine is volatile. */
1632 if (optimize && (*epilogue_string == 0) && argsize == 0 && tail_call_ok
1633 && (nexti == 0 || GET_CODE (PATTERN (nexti)) == RETURN))
1635 /* Delete following return insn. */
1636 if (nexti && no_labels_between_p (insn, nexti))
1637 delete_insn (nexti);
1638 output_asm_insn ("bx %0", operands);
1639 return "# notreached";
1642 output_asm_insn ("callx %0", operands);
1644 /* If the caller sets g14 to the address of the argblock, then the caller
1645 must clear it after the return. */
1647 if (current_function_args_size != 0 || varargs_stdarg_function)
1648 output_asm_insn ("mov r3,g14", operands);
1649 else if (argsize > 48)
1650 output_asm_insn ("mov 0,g14", operands);
1655 /* Output code for a return insn. */
1658 i960_output_ret_insn (insn)
1661 static char lbuf[20];
1663 if (*epilogue_string != 0)
1665 if (! TARGET_CODE_ALIGN && next_real_insn (insn) == 0)
1668 sprintf (lbuf, "b Li960R%d", ret_label);
1672 /* Must clear g14 on return if this function set it.
1673 Only varargs/stdarg functions modify g14. */
1675 if (VARARGS_STDARG_FUNCTION (current_function_decl))
1676 output_asm_insn ("mov 0,g14", 0);
1678 if (i960_leaf_ret_reg >= 0)
1680 sprintf (lbuf, "bx (%s)", reg_names[i960_leaf_ret_reg]);
1686 /* Print the operand represented by rtx X formatted by code CODE. */
1689 i960_print_operand (file, x, code)
1694 enum rtx_code rtxcode = x ? GET_CODE (x) : NIL;
1701 /* Second reg of a double or quad. */
1702 fprintf (file, "%s", reg_names[REGNO (x)+1]);
1706 /* Third reg of a quad. */
1707 fprintf (file, "%s", reg_names[REGNO (x)+2]);
1711 /* Fourth reg of a quad. */
1712 fprintf (file, "%s", reg_names[REGNO (x)+3]);
1716 fprintf (file, "%s", reg_names[REGNO (x)]);
1724 else if (rtxcode == MEM)
1726 output_address (XEXP (x, 0));
1729 else if (rtxcode == CONST_INT)
1731 HOST_WIDE_INT val = INTVAL (x);
1734 if (val > 9999 || val < -999)
1735 fprintf (file, "0x%x", val);
1737 fprintf (file, "%d", val);
1740 else if (rtxcode == CONST_DOUBLE)
1745 if (x == CONST0_RTX (GET_MODE (x)))
1747 fprintf (file, "0f0.0");
1750 else if (x == CONST1_RTX (GET_MODE (x)))
1752 fprintf (file, "0f1.0");
1756 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1757 REAL_VALUE_TO_DECIMAL (d, "%#g", dstr);
1758 fprintf (file, "0f%s", dstr);
1765 /* Branch or jump, depending on assembler. */
1766 if (TARGET_ASM_COMPAT)
1773 /* Sign of condition. */
1774 if ((rtxcode == EQ) || (rtxcode == NE) || (rtxcode == GTU)
1775 || (rtxcode == LTU) || (rtxcode == GEU) || (rtxcode == LEU))
1777 else if ((rtxcode == GT) || (rtxcode == LT)
1778 || (rtxcode == GE) || (rtxcode == LE))
1785 /* Inverted condition. */
1786 rtxcode = reverse_condition (rtxcode);
1790 /* Inverted condition w/ reversed operands. */
1791 rtxcode = reverse_condition (rtxcode);
1795 /* Reversed operand condition. */
1796 rtxcode = swap_condition (rtxcode);
1800 /* Normal condition. */
1802 if (rtxcode == EQ) { fputs ("e", file); return; }
1803 else if (rtxcode == NE) { fputs ("ne", file); return; }
1804 else if (rtxcode == GT) { fputs ("g", file); return; }
1805 else if (rtxcode == GTU) { fputs ("g", file); return; }
1806 else if (rtxcode == LT) { fputs ("l", file); return; }
1807 else if (rtxcode == LTU) { fputs ("l", file); return; }
1808 else if (rtxcode == GE) { fputs ("ge", file); return; }
1809 else if (rtxcode == GEU) { fputs ("ge", file); return; }
1810 else if (rtxcode == LE) { fputs ("le", file); return; }
1811 else if (rtxcode == LEU) { fputs ("le", file); return; }
1816 /* For conditional branches, substitute ".t" or ".f". */
1817 if (TARGET_BRANCH_PREDICT)
1819 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1822 int pred_val = INTVAL (XEXP (x, 0));
1823 fputs ((pred_val < REG_BR_PROB_BASE / 2 ? ".f" : ".t"), file);
1829 output_addr_const (file, x);
1839 /* Print a memory address as an operand to reference that memory location.
1841 This is exactly the same as legitimate_address_p, except that it the prints
1842 addresses instead of recognizing them. */
1845 i960_print_operand_addr (file, addr)
1857 if (GET_CODE (addr) == REG)
1859 else if (CONSTANT_P (addr))
1861 else if (GET_CODE (addr) == PLUS)
1865 op0 = XEXP (addr, 0);
1866 op1 = XEXP (addr, 1);
1868 if (GET_CODE (op0) == REG)
1871 if (GET_CODE (op1) == REG)
1873 else if (CONSTANT_P (op1))
1878 else if (GET_CODE (op0) == PLUS)
1880 if (GET_CODE (XEXP (op0, 0)) == MULT)
1882 ireg = XEXP (XEXP (op0, 0), 0);
1883 scale = XEXP (XEXP (op0, 0), 1);
1884 if (GET_CODE (XEXP (op0, 1)) == REG)
1886 breg = XEXP (op0, 1);
1892 else if (GET_CODE (XEXP (op0, 0)) == REG)
1894 breg = XEXP (op0, 0);
1895 if (GET_CODE (XEXP (op0, 1)) == REG)
1897 ireg = XEXP (op0, 1);
1906 else if (GET_CODE (op0) == MULT)
1908 ireg = XEXP (op0, 0);
1909 scale = XEXP (op0, 1);
1910 if (GET_CODE (op1) == REG)
1912 else if (CONSTANT_P (op1))
1920 else if (GET_CODE (addr) == MULT)
1922 ireg = XEXP (addr, 0);
1923 scale = XEXP (addr, 1);
1929 output_addr_const (file, offset);
1931 fprintf (file, "(%s)", reg_names[REGNO (breg)]);
1933 fprintf (file, "[%s*%d]", reg_names[REGNO (ireg)], INTVAL (scale));
1936 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1937 that is a valid memory address for an instruction.
1938 The MODE argument is the machine mode for the MEM expression
1939 that wants to use this address.
1941 On 80960, legitimate addresses are:
1943 disp (12 or 32 bit) ld foo,r0
1944 base + index ld (g0)[g1*1],r0
1945 base + displ ld 0xf00(g0),r0
1946 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1947 index*scale + base ld (g0)[g1*4],r0
1948 index*scale + displ ld 0xf00[g1*4],r0
1949 index*scale ld [g1*4],r0
1950 index + base + displ ld 0xf00(g0)[g1*1],r0
1952 In each case, scale can be 1, 2, 4, 8, or 16. */
1954 /* This is exactly the same as i960_print_operand_addr, except that
1955 it recognizes addresses instead of printing them.
1957 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1958 convert common non-canonical forms to canonical form so that they will
1961 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1962 where a register is valid. */
1964 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1965 ((GET_CODE (X) == REG \
1966 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1967 || (GET_CODE (X) == SUBREG \
1968 && GET_CODE (SUBREG_REG (X)) == REG \
1969 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1970 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1972 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1973 ((GET_CODE (X) == REG \
1974 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1975 || (GET_CODE (X) == SUBREG \
1976 && GET_CODE (SUBREG_REG (X)) == REG \
1977 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1978 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1981 legitimate_address_p (mode, addr, strict)
1982 enum machine_mode mode ATTRIBUTE_UNUSED;
1986 if (RTX_OK_FOR_BASE_P (addr, strict))
1988 else if (CONSTANT_P (addr))
1990 else if (GET_CODE (addr) == PLUS)
1994 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
1997 op0 = XEXP (addr, 0);
1998 op1 = XEXP (addr, 1);
2000 if (RTX_OK_FOR_BASE_P (op0, strict))
2002 if (RTX_OK_FOR_INDEX_P (op1, strict))
2004 else if (CONSTANT_P (op1))
2009 else if (GET_CODE (op0) == PLUS)
2011 if (GET_CODE (XEXP (op0, 0)) == MULT)
2013 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0, 0), 0), strict)
2014 && SCALE_TERM_P (XEXP (XEXP (op0, 0), 1))))
2017 if (RTX_OK_FOR_BASE_P (XEXP (op0, 1), strict)
2018 && CONSTANT_P (op1))
2023 else if (RTX_OK_FOR_BASE_P (XEXP (op0, 0), strict))
2025 if (RTX_OK_FOR_INDEX_P (XEXP (op0, 1), strict)
2026 && CONSTANT_P (op1))
2034 else if (GET_CODE (op0) == MULT)
2036 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0, 0), strict)
2037 && SCALE_TERM_P (XEXP (op0, 1))))
2040 if (RTX_OK_FOR_BASE_P (op1, strict))
2042 else if (CONSTANT_P (op1))
2050 else if (GET_CODE (addr) == MULT)
2052 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
2055 return (RTX_OK_FOR_INDEX_P (XEXP (addr, 0), strict)
2056 && SCALE_TERM_P (XEXP (addr, 1)));
2062 /* Try machine-dependent ways of modifying an illegitimate address
2063 to be legitimate. If we find one, return the new, valid address.
2064 This macro is used in only one place: `memory_address' in explow.c.
2066 This converts some non-canonical addresses to canonical form so they
2067 can be recognized. */
2070 legitimize_address (x, oldx, mode)
2072 register rtx oldx ATTRIBUTE_UNUSED;
2073 enum machine_mode mode ATTRIBUTE_UNUSED;
2075 if (GET_CODE (x) == SYMBOL_REF)
2078 x = copy_to_reg (x);
2081 if (! TARGET_COMPLEX_ADDR && ! reload_completed)
2084 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2085 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2086 created by virtual register instantiation, register elimination, and
2087 similar optimizations. */
2088 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
2089 && GET_CODE (XEXP (x, 1)) == PLUS)
2090 x = gen_rtx_PLUS (Pmode,
2091 gen_rtx_PLUS (Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)),
2092 XEXP (XEXP (x, 1), 1));
2094 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2095 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2096 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
2097 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2098 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
2099 && CONSTANT_P (XEXP (x, 1)))
2101 rtx constant, other;
2103 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2105 constant = XEXP (x, 1);
2106 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
2108 else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
2110 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
2111 other = XEXP (x, 1);
2117 x = gen_rtx_PLUS (Pmode,
2118 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
2119 XEXP (XEXP (XEXP (x, 0), 1), 0)),
2120 plus_constant (other, INTVAL (constant)));
2127 /* Return the most stringent alignment that we are willing to consider
2128 objects of size SIZE and known alignment ALIGN as having. */
2131 i960_alignment (size, align)
2137 if (! TARGET_STRICT_ALIGN)
2138 if (TARGET_IC_COMPAT2_0 || align >= 4)
2140 i = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
2151 hard_regno_mode_ok (regno, mode)
2153 enum machine_mode mode;
2159 case CCmode: case CC_UNSmode: case CC_CHKmode:
2162 case DImode: case DFmode:
2163 return (regno & 1) == 0;
2165 case TImode: case XFmode:
2166 return (regno & 3) == 0;
2172 else if (regno >= 32 && regno < 36)
2176 case SFmode: case DFmode: case XFmode:
2177 case SCmode: case DCmode:
2184 else if (regno == 36)
2188 case CCmode: case CC_UNSmode: case CC_CHKmode:
2195 else if (regno == 37)
2202 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2203 advantage of machine specific facts, such as knowing that the frame pointer
2204 is always 16 byte aligned. */
2207 i960_expr_alignment (x, size)
2216 switch (GET_CODE(x))
2221 if ((align & 0xf) == 0)
2223 else if ((align & 0x7) == 0)
2225 else if ((align & 0x3) == 0)
2227 else if ((align & 0x1) == 0)
2234 align = MIN (i960_expr_alignment (XEXP (x, 0), size),
2235 i960_expr_alignment (XEXP (x, 1), size));
2239 /* If this is a valid program, objects are guaranteed to be
2240 correctly aligned for whatever size the reference actually is. */
2241 align = i960_object_bytes_bitalign (size) / BITS_PER_UNIT;
2245 if (REGNO (x) == FRAME_POINTER_REGNUM)
2250 align = i960_expr_alignment (XEXP (x, 0), size);
2252 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2254 align = align << INTVAL (XEXP (x, 1));
2255 align = MIN (align, 16);
2260 align = (i960_expr_alignment (XEXP (x, 0), size) *
2261 i960_expr_alignment (XEXP (x, 1), size));
2263 align = MIN (align, 16);
2272 /* Return true if it is possible to reference both BASE and OFFSET, which
2273 have alignment at least as great as 4 byte, as if they had alignment valid
2274 for an object of size SIZE. */
2277 i960_improve_align (base, offset, size)
2284 /* We have at least a word reference to the object, so we know it has to
2285 be aligned at least to 4 bytes. */
2287 i = MIN (i960_expr_alignment (base, 4),
2288 i960_expr_alignment (offset, 4));
2292 /* We know the size of the request. If strict align is not enabled, we
2293 can guess that the alignment is OK for the requested size. */
2295 if (! TARGET_STRICT_ALIGN)
2296 if ((j = (i960_object_bytes_bitalign (size) / BITS_PER_UNIT)) > i)
2302 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2303 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2306 i960_si_ti (base, offset)
2310 return i960_improve_align (base, offset, 16);
2313 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2314 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2317 i960_si_di (base, offset)
2321 return i960_improve_align (base, offset, 8);
2324 /* Return raw values of size and alignment (in words) for the data
2325 type being accessed. These values will be rounded by the caller. */
2328 i960_arg_size_and_align (mode, type, size_out, align_out)
2329 enum machine_mode mode;
2336 /* Use formal alignment requirements of type being passed, except make
2337 it at least a word. If we don't have a type, this is a library call,
2338 and the parm has to be of scalar type. In this case, consider its
2339 formal alignment requirement to be its size in words. */
2341 if (mode == BLKmode)
2342 size = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2343 else if (mode == VOIDmode)
2345 /* End of parm list. */
2346 if (type == 0 || TYPE_MODE (type) != VOIDmode)
2351 size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2355 /* ??? This is a hack to properly correct the alignment of XFmode
2356 values without affecting anything else. */
2362 else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
2363 align = TYPE_ALIGN (type) / BITS_PER_WORD;
2371 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2372 Any arg that is bigger than 4 words is placed on the stack and all
2373 subsequent arguments are placed on the stack.
2375 Additionally, parameters with an alignment requirement stronger than
2376 a word must be aligned appropriately. Note that this means that a
2377 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2378 passed in an odd/even register pair. */
2380 /* Update CUM to advance past an argument described by MODE and TYPE. */
2383 i960_function_arg_advance (cum, mode, type, named)
2384 CUMULATIVE_ARGS *cum;
2385 enum machine_mode mode;
2387 int named ATTRIBUTE_UNUSED;
2391 i960_arg_size_and_align (mode, type, &size, &align);
2393 if (size > 4 || cum->ca_nstackparms != 0
2394 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2395 || MUST_PASS_IN_STACK (mode, type))
2397 /* Indicate that all the registers are in use, even if all are not,
2398 so va_start will compute the right value. */
2399 cum->ca_nregparms = NPARM_REGS;
2400 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align) + size;
2403 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align) + size;
2406 /* Return the register that the argument described by MODE and TYPE is
2407 passed in, or else return 0 if it is passed on the stack. */
2410 i960_function_arg (cum, mode, type, named)
2411 CUMULATIVE_ARGS *cum;
2412 enum machine_mode mode;
2414 int named ATTRIBUTE_UNUSED;
2419 if (mode == VOIDmode)
2422 i960_arg_size_and_align (mode, type, &size, &align);
2424 if (size > 4 || cum->ca_nstackparms != 0
2425 || (size + ROUND_PARM (cum->ca_nregparms, align)) > NPARM_REGS
2426 || MUST_PASS_IN_STACK (mode, type))
2428 cum->ca_nstackparms = ROUND_PARM (cum->ca_nstackparms, align);
2433 cum->ca_nregparms = ROUND_PARM (cum->ca_nregparms, align);
2434 ret = gen_rtx_REG (mode, cum->ca_nregparms);
2440 /* Floating-point support. */
2443 i960_output_long_double (file, value)
2445 REAL_VALUE_TYPE value;
2450 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value, value_long);
2451 REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr);
2454 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2455 value_long[0], dstr, value_long[1], value_long[2]);
2456 fprintf (file, "\t.word\t0x0\n");
2460 i960_output_double (file, value)
2462 REAL_VALUE_TYPE value;
2467 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
2468 REAL_VALUE_TO_DECIMAL (value, "%.20g", dstr);
2470 fprintf (file, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2471 value_long[0], dstr, value_long[1]);
2475 i960_output_float (file, value)
2477 REAL_VALUE_TYPE value;
2482 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
2483 REAL_VALUE_TO_DECIMAL (value, "%.12g", dstr);
2485 fprintf (file, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long, dstr);
2488 /* Return the number of bits that an object of size N bytes is aligned to. */
2491 i960_object_bytes_bitalign (n)
2495 else if (n > 4) n = 64;
2496 else if (n > 2) n = 32;
2497 else if (n > 1) n = 16;
2503 /* Compute the alignment for an aggregate type TSIZE.
2504 Alignment is MAX (greatest member alignment,
2505 MIN (pragma align, structure size alignment)). */
2508 i960_round_align (align, tsize)
2514 if (! tsize || TREE_CODE (tsize) != INTEGER_CST)
2517 new_align = i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize)
2519 /* Handle #pragma align. */
2520 if (new_align > i960_maxbitalignment)
2521 new_align = i960_maxbitalignment;
2523 if (align < new_align)
2529 /* Do any needed setup for a varargs function. For the i960, we must
2530 create a register parameter block if one doesn't exist, and then copy
2531 all register parameters to memory. */
2534 i960_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
2535 CUMULATIVE_ARGS *cum;
2536 enum machine_mode mode ATTRIBUTE_UNUSED;
2537 tree type ATTRIBUTE_UNUSED;
2538 int *pretend_size ATTRIBUTE_UNUSED;
2541 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2542 int first_reg = cum->ca_nregparms;
2544 /* Copy only unnamed register arguments to memory. If there are
2545 any stack parms, there are no unnamed arguments in registers, and
2546 an argument block was already allocated by the caller.
2547 Remember that any arg bigger than 4 words is passed on the stack as
2548 are all subsequent args.
2550 If there are no stack arguments but there are exactly NPARM_REGS
2551 registers, either there were no extra arguments or the caller
2552 allocated an argument block. */
2554 if (cum->ca_nstackparms == 0 && first_reg < NPARM_REGS && !no_rtl)
2556 rtx label = gen_label_rtx ();
2559 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2560 and we need to allocate a chunk to save the registers (if any
2561 arguments were passed on the stack the caller would allocate the
2562 48 bytes as well). We must allocate all 48 bytes (12*4) because
2563 va_start assumes it. */
2564 emit_insn (gen_cmpsi (arg_pointer_rtx, const0_rtx));
2565 emit_jump_insn (gen_bne (label));
2566 emit_insn (gen_rtx_SET (VOIDmode, arg_pointer_rtx,
2567 stack_pointer_rtx));
2568 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
2569 memory_address (SImode,
2570 plus_constant (stack_pointer_rtx,
2574 /* ??? Note that we unnecessarily store one extra register for stdarg
2575 fns. We could optimize this, but it's kept as for now. */
2576 regblock = gen_rtx_MEM (BLKmode,
2577 plus_constant (arg_pointer_rtx,
2579 MEM_ALIAS_SET (regblock) = get_varargs_alias_set ();
2580 move_block_from_reg (first_reg, regblock,
2581 NPARM_REGS - first_reg,
2582 (NPARM_REGS - first_reg) * UNITS_PER_WORD);
2586 /* Define the `__builtin_va_list' type for the ABI. */
2589 i960_build_va_list ()
2591 return build_array_type (unsigned_type_node,
2592 build_index_type (size_one_node));
2595 /* Implement `va_start' for varargs and stdarg. */
2598 i960_va_start (stdarg_p, valist, nextarg)
2599 int stdarg_p ATTRIBUTE_UNUSED;
2601 rtx nextarg ATTRIBUTE_UNUSED;
2603 tree s, t, base, num;
2605 /* The array type always decays to a pointer before we get here, so we
2606 can't use ARRAY_REF. */
2607 base = build1 (INDIRECT_REF, unsigned_type_node, valist);
2608 num = build1 (INDIRECT_REF, unsigned_type_node,
2609 build (PLUS_EXPR, unsigned_type_node, valist,
2610 TYPE_SIZE_UNIT (TREE_TYPE (valist))));
2612 s = make_tree (unsigned_type_node, arg_pointer_rtx);
2613 t = build (MODIFY_EXPR, unsigned_type_node, base, s);
2614 TREE_SIDE_EFFECTS (t) = 1;
2615 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2617 s = build_int_2 ((current_function_args_info.ca_nregparms
2618 + current_function_args_info.ca_nstackparms) * 4, 0);
2619 t = build (MODIFY_EXPR, unsigned_type_node, num, s);
2620 TREE_SIDE_EFFECTS (t) = 1;
2621 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2624 /* Implement `va_arg'. */
2627 i960_va_arg (valist, type)
2630 HOST_WIDE_INT siz, ali;
2631 tree base, num, pad, next, this, t1, t2, int48;
2634 /* The array type always decays to a pointer before we get here, so we
2635 can't use ARRAY_REF. */
2636 base = build1 (INDIRECT_REF, unsigned_type_node, valist);
2637 num = build1 (INDIRECT_REF, unsigned_type_node,
2638 build (PLUS_EXPR, unsigned_type_node, valist,
2639 TYPE_SIZE_UNIT (TREE_TYPE (valist))));
2641 /* Round up sizeof(type) to a word. */
2642 siz = (int_size_in_bytes (type) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
2644 /* Round up alignment to a word. */
2645 ali = TYPE_ALIGN (type);
2646 if (ali < BITS_PER_WORD)
2647 ali = BITS_PER_WORD;
2648 ali /= BITS_PER_UNIT;
2650 /* Align NUM appropriate for the argument. */
2651 pad = fold (build (PLUS_EXPR, unsigned_type_node, num,
2652 build_int_2 (ali - 1, 0)));
2653 pad = fold (build (BIT_AND_EXPR, unsigned_type_node, pad,
2654 build_int_2 (-ali, -1)));
2655 pad = save_expr (pad);
2657 /* Increment VPAD past this argument. */
2658 next = fold (build (PLUS_EXPR, unsigned_type_node, pad,
2659 build_int_2 (siz, 0)));
2660 next = save_expr (next);
2662 /* Find the offset for the current argument. Mind peculiar overflow
2663 from registers to stack. */
2664 int48 = build_int_2 (48, 0);
2666 t2 = integer_one_node;
2668 t2 = fold (build (GT_EXPR, integer_type_node, next, int48));
2669 t1 = fold (build (LE_EXPR, integer_type_node, num, int48));
2670 t1 = fold (build (TRUTH_AND_EXPR, integer_type_node, t1, t2));
2671 this = fold (build (COND_EXPR, unsigned_type_node, t1, int48, pad));
2673 /* Find the address for the current argument. */
2674 t1 = fold (build (PLUS_EXPR, unsigned_type_node, base, this));
2675 t1 = build1 (NOP_EXPR, ptr_type_node, t1);
2676 addr_rtx = expand_expr (t1, NULL_RTX, Pmode, EXPAND_NORMAL);
2678 /* Increment NUM. */
2679 t1 = build (MODIFY_EXPR, unsigned_type_node, num, next);
2680 TREE_SIDE_EFFECTS (t1) = 1;
2681 expand_expr (t1, const0_rtx, VOIDmode, EXPAND_NORMAL);
2686 /* Calculate the final size of the reg parm stack space for the current
2687 function, based on how many bytes would be allocated on the stack. */
2690 i960_final_reg_parm_stack_space (const_size, var_size)
2694 if (var_size || const_size > 48)
2700 /* Calculate the size of the reg parm stack space. This is a bit complicated
2704 i960_reg_parm_stack_space (fndecl)
2707 /* In this case, we are called from emit_library_call, and we don't need
2708 to pretend we have more space for parameters than what's apparent. */
2712 /* In this case, we are called from locate_and_pad_parms when we're
2713 not IN_REGS, so we have an arg block. */
2714 if (fndecl != current_function_decl)
2717 /* Otherwise, we have an arg block if the current function has more than
2718 48 bytes of parameters. */
2719 if (current_function_args_size != 0 || VARARGS_STDARG_FUNCTION (fndecl))
2725 /* Return the register class of a scratch register needed to copy IN into
2726 or out of a register in CLASS in MODE. If it can be done directly,
2727 NO_REGS is returned. */
2730 secondary_reload_class (class, mode, in)
2731 enum reg_class class;
2732 enum machine_mode mode;
2737 if (GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
2738 regno = true_regnum (in);
2740 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2741 LOCAL_OR_GLOBAL_REGS into anything. */
2742 if (class == LOCAL_OR_GLOBAL_REGS || class == LOCAL_REGS
2743 || class == GLOBAL_REGS || (regno >= 0 && regno < 32))
2746 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2747 if (class == FP_REGS
2748 && ((regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
2749 || in == CONST0_RTX (mode) || in == CONST1_RTX (mode)))
2752 return LOCAL_OR_GLOBAL_REGS;
2755 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2756 function unit it executed on. */
2758 /* ??? This would make more sense as an attribute. */
2761 i960_scan_opcode (p)
2773 /* Ret is not actually of type REG, but it won't matter, because no
2774 insn will ever follow it. */
2777 i960_last_insn_type = I_TYPE_REG;
2781 if (p[1] == 'x' || p[3] == 'x')
2782 i960_last_insn_type = I_TYPE_MEM;
2783 i960_last_insn_type = I_TYPE_CTRL;
2788 i960_last_insn_type = I_TYPE_CTRL;
2795 i960_last_insn_type = I_TYPE_MEM;
2797 i960_last_insn_type = I_TYPE_CTRL;
2799 else if (p[1] == 'm')
2802 i960_last_insn_type = I_TYPE_REG;
2803 else if (p[4] == 'b' || p[4] == 'j')
2804 i960_last_insn_type = I_TYPE_CTRL;
2806 i960_last_insn_type = I_TYPE_REG;
2809 i960_last_insn_type = I_TYPE_REG;
2813 i960_last_insn_type = I_TYPE_MEM;
2818 i960_last_insn_type = I_TYPE_MEM;
2820 i960_last_insn_type = I_TYPE_REG;