1 /* Definitions of target machine for GNU compiler, for Intel 860.
2 Copyright (C) 1989, 1991, 1993, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4 Hacked substantially by Ron Guilmette (rfg@monkeys.com) to cater to
5 the whims of the System V Release 4 assembler.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
25 /* Note that some other tm.h files include this one and then override
26 many of the definitions that relate to assembler syntax. */
29 /* Names to predefine in the preprocessor for this target machine. */
31 #define CPP_PREDEFINES "-Di860 -Dunix -Asystem=unix -Asystem=svr4 -Acpu=i860 -Amachine=i860"
33 /* Print subsidiary information on the compiler version in use. */
34 #define TARGET_VERSION fprintf (stderr, " (i860)");
36 /* Run-time compilation parameters selecting different hardware subsets
39 On the i860, we have one: TARGET_XP. This option allows gcc to generate
40 additional instructions available only on the newer i860 XP (but not on
44 extern int target_flags;
46 /* Nonzero if we should generate code to use the fpu. */
47 #define TARGET_XP (target_flags & 1)
49 /* Macro to define tables used to set the flags.
50 This is a list in braces of pairs in braces,
51 each pair being { "NAME", VALUE }
52 where VALUE is the bits to set or minus the bits to clear.
53 An empty string NAME is used to identify the default VALUE. */
55 #define TARGET_SWITCHES \
56 { {"xp", 1, N_("Generate code which uses the FPU")}, \
57 {"noxp", -1, N_("Do not generate code which uses the FPU")}, \
58 {"xr", -1, N_("Do not generate code which uses the FPU")}, \
59 { "", TARGET_DEFAULT, NULL}}
61 #define TARGET_DEFAULT 0
63 /* target machine storage layout */
65 /* Define this if most significant bit is lowest numbered
66 in instructions that operate on numbered bit-fields.
67 This is a moot question on the i860 due to the lack of bit-field insns. */
68 #define BITS_BIG_ENDIAN 0
70 /* Define this if most significant byte of a word is the lowest numbered. */
71 /* That is not true on i860 in the mode we will use. */
72 #define BYTES_BIG_ENDIAN 0
74 /* Define this if most significant word of a multiword number is the lowest
76 /* For the i860 this goes with BYTES_BIG_ENDIAN. */
77 /* NOTE: GCC probably cannot support a big-endian i860
78 because GCC fundamentally assumes that the order of words
79 in memory as the same as the order in registers.
80 That's not true for the big-endian i860.
81 The big-endian i860 isn't important enough to
82 justify the trouble of changing this assumption. */
83 #define WORDS_BIG_ENDIAN 0
85 /* number of bits in an addressable storage unit */
86 #define BITS_PER_UNIT 8
88 /* Width in bits of a "word", which is the contents of a machine register.
89 Note that this is not necessarily the width of data type `int';
90 if using 16-bit ints on a 68000, this would still be 32.
91 But on a machine with 16-bit registers, this would be 16. */
92 #define BITS_PER_WORD 32
94 /* Width of a word, in units (bytes). */
95 #define UNITS_PER_WORD 4
97 /* Width in bits of a pointer.
98 See also the macro `Pmode' defined below. */
99 #define POINTER_SIZE 32
101 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
102 #define PARM_BOUNDARY 32
104 /* Boundary (in *bits*) on which stack pointer should be aligned. */
105 #define STACK_BOUNDARY 128
107 /* Allocation boundary (in *bits*) for the code of a function. */
108 #define FUNCTION_BOUNDARY 64
110 /* Alignment of field after `int : 0' in a structure. */
111 #define EMPTY_FIELD_BOUNDARY 32
113 /* Every structure's size must be a multiple of this. */
114 #define STRUCTURE_SIZE_BOUNDARY 8
116 /* Minimum size in bits of the largest boundary to which any
117 and all fundamental data types supported by the hardware
118 might need to be aligned. No data type wants to be aligned
119 rounder than this. The i860 supports 128-bit (long double)
120 floating point quantities, and the System V Release 4 i860
121 ABI requires these to be aligned to 16-byte (128-bit)
123 #define BIGGEST_ALIGNMENT 128
125 /* Set this nonzero if move instructions will actually fail to work
126 when given unaligned data. */
127 #define STRICT_ALIGNMENT 1
129 /* If bit field type is int, don't let it cross an int,
130 and give entire struct the alignment of an int. */
131 #define PCC_BITFIELD_TYPE_MATTERS 1
133 /* Standard register usage. */
135 /* Number of actual hardware registers.
136 The hardware registers are assigned numbers for the compiler
137 from 0 to just below FIRST_PSEUDO_REGISTER.
138 All registers that the compiler knows about must be given numbers,
139 even those that are not normally considered general registers.
141 i860 has 32 fullword registers and 32 floating point registers. */
143 #define FIRST_PSEUDO_REGISTER 64
145 /* 1 for registers that have pervasive standard uses
146 and are not available for the register allocator.
147 On the i860, this includes the always-0 registers
148 and fp, sp, arg pointer, and the return address.
149 Also r31, used for special purposes for constant addresses. */
150 #define FIXED_REGISTERS \
151 {1, 1, 1, 1, 0, 0, 0, 0, \
152 0, 0, 0, 0, 0, 0, 0, 0, \
153 0, 0, 0, 0, 0, 0, 0, 0, \
154 0, 0, 0, 0, 0, 0, 0, 1, \
155 1, 1, 0, 0, 0, 0, 0, 0, \
156 0, 0, 0, 0, 0, 0, 0, 0, \
157 0, 0, 0, 0, 0, 0, 0, 0, \
158 0, 0, 0, 0, 0, 0, 0, 0}
160 /* 1 for registers not available across function calls.
161 These must include the FIXED_REGISTERS and also any
162 registers that can be used without being saved.
163 On the i860, these are r0-r3, r16-r31, f0, f1, and f16-f31. */
164 #define CALL_USED_REGISTERS \
165 {1, 1, 1, 1, 0, 0, 0, 0, \
166 0, 0, 0, 0, 0, 0, 0, 0, \
167 1, 1, 1, 1, 1, 1, 1, 1, \
168 1, 1, 1, 1, 1, 1, 1, 1, \
169 1, 1, 0, 0, 0, 0, 0, 0, \
170 1, 1, 1, 1, 1, 1, 1, 1, \
171 1, 1, 1, 1, 1, 1, 1, 1, \
172 1, 1, 1, 1, 1, 1, 1, 1}
174 /* Try to get a non-preserved register before trying to get one we will
175 have to preserve. Try to get an FP register only *after* trying to
176 get a general register, because it is relatively expensive to move
177 into or out of an FP register. */
179 #define REG_ALLOC_ORDER \
180 {31, 30, 29, 28, 27, 26, 25, 24, \
181 23, 22, 21, 20, 19, 18, 17, 16, \
182 15, 14, 13, 12, 11, 10, 9, 8, \
183 7, 6, 5, 4, 3, 2, 1, 0, \
184 63, 62, 61, 60, 59, 58, 57, 56, \
185 55, 54, 53, 52, 51, 50, 49, 48, \
186 47, 46, 45, 44, 43, 42, 41, 40, \
187 39, 38, 37, 36, 35, 34, 33, 32}
189 /* Return number of consecutive hard regs needed starting at reg REGNO
190 to hold something of mode MODE.
191 This is ordinarily the length in words of a value of mode MODE
192 but can be less for certain modes in special long registers.
194 On the i860, all registers hold 32 bits worth. */
195 #define HARD_REGNO_NREGS(REGNO, MODE) \
196 (((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
198 #define REGNO_MODE_ALIGNED(REGNO, MODE) \
199 (((REGNO) % ((GET_MODE_UNIT_SIZE (MODE) + 3) / 4)) == 0)
201 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
203 On the i860, we allow anything to go into any registers, but we require
204 any sort of value going into the FP registers to be properly aligned
205 (based on its size) within the FP register set.
207 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
209 || (MODE) == VOIDmode || (MODE) == BLKmode \
210 || REGNO_MODE_ALIGNED (REGNO, MODE))
212 /* Value is 1 if it is a good idea to tie two pseudo registers
213 when one has mode MODE1 and one has mode MODE2.
214 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
215 for any hard reg, then this must be 0 for correct output. */
216 /* I think that is not always true; alignment restrictions for doubles
217 should not prevent tying them with singles. So try allowing that.
218 On the other hand, don't let fixed and floating be tied;
219 this restriction is not necessary, but may make better code. */
220 #define MODES_TIEABLE_P(MODE1, MODE2) \
221 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
222 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
223 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
224 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
226 /* Specify the registers used for certain standard purposes.
227 The values of these macros are register numbers. */
229 /* i860 pc isn't overloaded on a register that the compiler knows about. */
230 /* #define PC_REGNUM */
232 /* Register to use for pushing function arguments. */
233 #define STACK_POINTER_REGNUM 2
235 /* Base register for access to local variables of the function. */
236 #define FRAME_POINTER_REGNUM 3
238 /* Value should be nonzero if functions must have frame pointers.
239 Zero means the frame pointer need not be set up (and parms
240 may be accessed via the stack pointer) in functions that seem suitable.
241 This is computed in `reload', in reload1.c. */
242 #define FRAME_POINTER_REQUIRED 1
244 /* Base register for access to arguments of the function. */
245 #define ARG_POINTER_REGNUM 28
247 /* Register in which static-chain is passed to a function. */
248 #define STATIC_CHAIN_REGNUM 29
250 /* Register in which address to store a structure value
251 is passed to a function. */
252 #define STRUCT_VALUE_REGNUM 16
254 /* Register to use when a source of a floating-point zero is needed. */
257 /* Define the classes of registers for register constraints in the
258 machine description. Also define ranges of constants.
260 One of the classes must always be named ALL_REGS and include all hard regs.
261 If there is more than one class, another class must be named NO_REGS
262 and contain no registers.
264 The name GENERAL_REGS must be the name of a class (or an alias for
265 another name such as ALL_REGS). This is the class of registers
266 that is allowed by "g" or "r" in a register constraint.
267 Also, registers outside this class are allocated only when
268 instructions express preferences for them.
270 The classes must be numbered in nondecreasing order; that is,
271 a larger-numbered class must never be contained completely
272 in a smaller-numbered class.
274 For any two classes, it is very desirable that there be another
275 class that represents their union. */
277 /* The i860 has two kinds of registers, hence four classes. */
279 enum reg_class { NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES };
281 #define N_REG_CLASSES (int) LIM_REG_CLASSES
283 /* Give names of register classes as strings for dump file. */
285 #define REG_CLASS_NAMES \
286 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
288 /* Define which registers fit in which classes.
289 This is an initializer for a vector of HARD_REG_SET
290 of length N_REG_CLASSES. */
292 #define REG_CLASS_CONTENTS \
293 {{0, 0}, {0xffffffff, 0}, \
294 {0, 0xffffffff}, {0xffffffff, 0xffffffff}}
296 /* The same information, inverted:
297 Return the class number of the smallest class containing
298 reg number REGNO. This could be a conditional expression
299 or could index an array. */
301 #define REGNO_REG_CLASS(REGNO) \
302 ((REGNO) >= 32 ? FP_REGS : GENERAL_REGS)
304 /* The class value for index registers, and the one for base regs. */
305 #define INDEX_REG_CLASS GENERAL_REGS
306 #define BASE_REG_CLASS GENERAL_REGS
308 /* Get reg_class from a letter such as appears in the machine description. */
310 #define REG_CLASS_FROM_LETTER(C) \
311 ((C) == 'f' ? FP_REGS : NO_REGS)
313 /* The letters I, J, K, L and M in a register constraint string
314 can be used to stand for particular ranges of immediate operands.
315 This macro defines what the ranges are.
316 C is the letter, and VALUE is a constant value.
317 Return 1 if VALUE is in the range specified by C.
319 For the i860, `I' is used for the range of constants
320 an add/subtract insn can actually contain.
321 But not including -0x8000, since we need
322 to negate the constant sometimes.
323 `J' is used for the range which is just zero (since that is R0).
324 `K' is used for the range allowed in bte.
325 `L' is used for the range allowed in logical insns. */
327 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x7fff) < 0xffff)
329 #define LOGIC_INT(X) ((unsigned) INTVAL (X) < 0x10000)
331 #define SMALL_INTVAL(X) ((unsigned) ((X) + 0x7fff) < 0xffff)
333 #define LOGIC_INTVAL(X) ((unsigned) (X) < 0x10000)
335 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
336 ((C) == 'I' ? ((unsigned) (VALUE) + 0x7fff) < 0xffff \
337 : (C) == 'J' ? (VALUE) == 0 \
338 : (C) == 'K' ? (unsigned) (VALUE) < 0x20 \
339 : (C) == 'L' ? (unsigned) (VALUE) < 0x10000 \
342 /* Return non-zero if the given VALUE is acceptable for the
343 constraint letter C. For the i860, constraint letter 'G'
344 permits only a floating-point zero value. */
345 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
346 ((C) == 'G' && CONST_DOUBLE_LOW ((VALUE)) == 0 \
347 && CONST_DOUBLE_HIGH ((VALUE)) == 0)
349 /* Given an rtx X being reloaded into a reg required to be
350 in class CLASS, return the class of reg to actually use.
351 In general this is just CLASS; but on some machines
352 in some cases it is preferable to use a more restrictive class.
354 If we are trying to put an integer constant into some register, prefer an
355 integer register to an FP register. If we are trying to put a
356 non-zero floating-point constant into some register, use an integer
357 register if the constant is SFmode and GENERAL_REGS is one of our options.
358 Otherwise, put the constant into memory.
360 When reloading something smaller than a word, use a general reg
361 rather than an FP reg. */
363 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
364 ((CLASS) == ALL_REGS && GET_CODE (X) == CONST_INT ? GENERAL_REGS \
365 : ((GET_MODE (X) == HImode || GET_MODE (X) == QImode) \
366 && (CLASS) == ALL_REGS) \
368 : (GET_CODE (X) == CONST_DOUBLE \
369 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
370 && ! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G')) \
371 ? ((CLASS) == ALL_REGS && GET_MODE (X) == SFmode ? GENERAL_REGS \
372 : (CLASS) == GENERAL_REGS && GET_MODE (X) == SFmode ? (CLASS) \
376 /* Return the register class of a scratch register needed to copy IN into
377 a register in CLASS in MODE. If it can be done directly, NO_REGS is
380 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
381 ((CLASS) == FP_REGS && CONSTANT_P (IN) ? GENERAL_REGS : NO_REGS)
383 /* Return the maximum number of consecutive registers
384 needed to represent mode MODE in a register of class CLASS. */
385 /* On the i860, this is the size of MODE in words. */
386 #define CLASS_MAX_NREGS(CLASS, MODE) \
387 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
389 /* Stack layout; function entry, exit and calling. */
391 /* Define this if pushing a word on the stack
392 makes the stack pointer a smaller address. */
393 #define STACK_GROWS_DOWNWARD
395 /* Define this if the nominal address of the stack frame
396 is at the high-address end of the local variables;
397 that is, each additional local variable allocated
398 goes at a more negative offset in the frame. */
399 #define FRAME_GROWS_DOWNWARD
401 /* Offset within stack frame to start allocating local variables at.
402 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
403 first local allocated. Otherwise, it is the offset to the BEGINNING
404 of the first local allocated. */
405 #define STARTING_FRAME_OFFSET 0
407 /* If we generate an insn to push BYTES bytes,
408 this says how many the stack pointer really advances by.
409 On the i860, don't define this because there are no push insns. */
410 /* #define PUSH_ROUNDING(BYTES) */
412 /* Offset of first parameter from the argument pointer register value. */
413 #define FIRST_PARM_OFFSET(FNDECL) 0
415 /* Value is the number of bytes of arguments automatically
416 popped when returning from a subroutine call.
417 FUNDECL is the declaration node of the function (as a tree),
418 FUNTYPE is the data type of the function (as a tree),
419 or for a library call it is an identifier node for the subroutine name.
420 SIZE is the number of bytes of arguments passed on the stack. */
422 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
424 /* Define how to find the value returned by a function.
425 VALTYPE is the data type of the value (as a tree).
426 If the precise function being called is known, FUNC is its FUNCTION_DECL;
427 otherwise, FUNC is 0. */
429 /* On the i860, the value register depends on the mode. */
431 #define FUNCTION_VALUE(VALTYPE, FUNC) \
432 gen_rtx_REG (TYPE_MODE (VALTYPE), \
433 (GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_FLOAT \
436 /* Define how to find the value returned by a library function
437 assuming the value has mode MODE. */
439 #define LIBCALL_VALUE(MODE) \
441 (GET_MODE_CLASS ((MODE)) == MODE_FLOAT \
444 /* 1 if N is a possible register number for a function value
445 as seen by the caller. */
447 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 40 || (N) == 16)
449 /* 1 if N is a possible register number for function argument passing.
450 On the i860, these are r16-r27 and f8-f15. */
452 #define FUNCTION_ARG_REGNO_P(N) \
453 (((N) < 28 && (N) > 15) || ((N) < 48 && (N) >= 40))
455 /* Define a data type for recording info about an argument list
456 during the scan of that argument list. This data type should
457 hold all necessary information about the function itself
458 and about the args processed so far, enough to enable macros
459 such as FUNCTION_ARG to determine where the next arg should go.
461 On the i860, we must count separately the number of general registers used
462 and the number of float registers used. */
464 struct cumulative_args { int ints, floats; };
465 #define CUMULATIVE_ARGS struct cumulative_args
467 /* Initialize a variable CUM of type CUMULATIVE_ARGS
468 for a call to a function whose data type is FNTYPE.
469 For a library call, FNTYPE is 0.
471 On the i860, the general-reg offset normally starts at 0,
472 but starts at 4 bytes
473 when the function gets a structure-value-address as an
474 invisible first argument. */
476 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
477 ((CUM).ints = ((FNTYPE) != 0 && aggregate_value_p (TREE_TYPE ((FNTYPE))) \
481 /* Machine-specific subroutines of the following macros. */
482 #define CEILING(X,Y) (((X) + (Y) - 1) / (Y))
483 #define ROUNDUP(X,Y) (CEILING ((X), (Y)) * (Y))
485 /* Update the data in CUM to advance over an argument
486 of mode MODE and data type TYPE.
487 (TYPE is null for libcalls where that information may not be available.)
488 Floats, and doubleword ints, are returned in f regs;
489 other ints, in r regs.
490 Aggregates, even short ones, are passed in memory. */
492 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
493 ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \
494 || TREE_CODE ((TYPE)) == UNION_TYPE) \
496 : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \
497 ? ((CUM).floats = (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) \
498 + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \
499 : GET_MODE_CLASS ((MODE)) == MODE_INT \
500 ? ((CUM).ints = (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) \
501 + ROUNDUP (GET_MODE_SIZE (MODE), 4))) \
504 /* Determine where to put an argument to a function.
505 Value is zero to push the argument on the stack,
506 or a hard register in which to store the argument.
508 MODE is the argument's machine mode.
509 TYPE is the data type of the argument (as a tree).
510 This is null for libcalls where that information may
512 CUM is a variable of type CUMULATIVE_ARGS which gives info about
513 the preceding args and about the function being called.
514 NAMED is nonzero if this argument is a named parameter
515 (otherwise it is an extra parameter matching an ellipsis). */
517 /* On the i860, the first 12 words of integer arguments go in r16-r27,
518 and the first 8 words of floating arguments go in f8-f15.
519 DImode values are treated as floats. */
521 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
522 ((TYPE) != 0 && (TREE_CODE ((TYPE)) == RECORD_TYPE \
523 || TREE_CODE ((TYPE)) == UNION_TYPE) \
525 : GET_MODE_CLASS ((MODE)) == MODE_FLOAT || (MODE) == DImode \
526 ? (ROUNDUP ((CUM).floats, GET_MODE_SIZE ((MODE))) < 32 \
527 ? gen_rtx_REG ((MODE), \
528 40 + (ROUNDUP ((CUM).floats, \
529 GET_MODE_SIZE ((MODE))) \
532 : GET_MODE_CLASS ((MODE)) == MODE_INT \
533 ? (ROUNDUP ((CUM).ints, GET_MODE_SIZE ((MODE))) < 48 \
534 ? gen_rtx_REG ((MODE), \
535 16 + (ROUNDUP ((CUM).ints, \
536 GET_MODE_SIZE ((MODE))) \
541 /* For an arg passed partly in registers and partly in memory,
542 this is the number of registers used.
543 For args passed entirely in registers or entirely in memory, zero. */
545 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
547 /* If defined, a C expression that gives the alignment boundary, in
548 bits, of an argument with the specified mode and type. If it is
549 not defined, `PARM_BOUNDARY' is used for all arguments. */
551 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
553 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
555 : TYPE_ALIGN(TYPE)) \
556 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
558 : GET_MODE_ALIGNMENT(MODE)))
560 /* Output a no-op just before the beginning of the function,
561 to ensure that there does not appear to be a delayed branch there.
562 Such a thing would confuse interrupt recovery. */
563 #define ASM_OUTPUT_FUNCTION_PREFIX(FILE,NAME) \
564 fprintf (FILE, "\tnop\n")
566 /* Output assembler code to FILE to increment profiler label # LABELNO
567 for profiling a function entry. */
569 #define FUNCTION_PROFILER(FILE, LABELNO) \
572 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
573 the stack pointer does not matter. The value is tested only in
574 functions that have frame pointers.
575 No definition is equivalent to always zero. */
577 #define EXIT_IGNORE_STACK 1
579 /* Generate necessary RTL for __builtin_saveregs(). */
580 #define EXPAND_BUILTIN_SAVEREGS() \
583 /* Define the `__builtin_va_list' type for the ABI. */
584 #define BUILD_VA_LIST_TYPE(VALIST) \
585 (VALIST) = i860_build_va_list ()
587 /* Implement `va_start' for varargs and stdarg. */
588 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
589 i860_va_start (stdarg, valist, nextarg)
591 /* Implement `va_arg'. */
592 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
593 i860_va_arg (valist, type)
595 /* Store in the variable DEPTH the initial difference between the
596 frame pointer reg contents and the stack pointer reg contents,
597 as of the start of the function body. This depends on the layout
598 of the fixed parts of the stack frame and on how registers are saved.
600 On the i860, FRAME_POINTER_REQUIRED is always 1, so the definition of this
601 macro doesn't matter. But it must be defined. */
603 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
604 do { (DEPTH) = 0; } while (0)
606 /* Output assembler code for a block containing the constant parts
607 of a trampoline, leaving space for the variable parts. */
609 /* On the i860, the trampoline contains five instructions:
610 orh #TOP_OF_FUNCTION,r0,r31
611 or #BOTTOM_OF_FUNCTION,r31,r31
612 orh #TOP_OF_STATIC,r0,r29
614 or #BOTTOM_OF_STATIC,r29,r29 */
615 #define TRAMPOLINE_TEMPLATE(FILE) \
617 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xec1f0000)); \
618 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xe7ff0000)); \
619 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xec1d0000)); \
620 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0x4000f800)); \
621 assemble_aligned_integer (UNITS_PER_WORD, GEN_INT (0xe7bd0000)); \
624 /* Length in units of the trampoline for entering a nested function. */
626 #define TRAMPOLINE_SIZE 20
628 /* Emit RTL insns to initialize the variable parts of a trampoline.
629 FNADDR is an RTX for the address of the function's pure code.
630 CXT is an RTX for the static chain value for the function.
632 Store hi function at +0, low function at +4,
633 hi static at +8, low static at +16 */
635 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
637 rtx cxt = force_reg (Pmode, CXT); \
638 rtx fn = force_reg (Pmode, FNADDR); \
639 rtx hi_cxt = expand_shift (RSHIFT_EXPR, SImode, cxt, \
640 size_int (16), 0, 0); \
641 rtx hi_fn = expand_shift (RSHIFT_EXPR, SImode, fn, \
642 size_int (16), 0, 0); \
643 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 16)), \
644 gen_lowpart (HImode, cxt)); \
645 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 4)), \
646 gen_lowpart (HImode, fn)); \
647 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 8)), \
648 gen_lowpart (HImode, hi_cxt)); \
649 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 0)), \
650 gen_lowpart (HImode, hi_fn)); \
653 /* Addressing modes, and classification of registers for them. */
655 /* #define HAVE_POST_INCREMENT 0 */
656 /* #define HAVE_POST_DECREMENT 0 */
658 /* #define HAVE_PRE_DECREMENT 0 */
659 /* #define HAVE_PRE_INCREMENT 0 */
661 /* Macros to check register numbers against specific register classes. */
663 /* These assume that REGNO is a hard or pseudo reg number.
664 They give nonzero only if REGNO is a hard reg of the suitable class
665 or a pseudo reg currently allocated to a suitable hard reg.
666 Since they use reg_renumber, they are safe only once reg_renumber
667 has been allocated, which happens in local-alloc.c. */
669 #define REGNO_OK_FOR_INDEX_P(REGNO) \
670 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
671 #define REGNO_OK_FOR_BASE_P(REGNO) \
672 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
673 #define REGNO_OK_FOR_FP_P(REGNO) \
674 (((REGNO) ^ 0x20) < 32 || (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32)
676 /* Now macros that check whether X is a register and also,
677 strictly, whether it is in a specified class.
679 These macros are specific to the i860, and may be used only
680 in code for printing assembler insns and in conditions for
681 define_optimization. */
683 /* 1 if X is an fp register. */
685 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
687 /* Maximum number of registers that can appear in a valid memory address. */
689 #define MAX_REGS_PER_ADDRESS 2
691 /* Recognize any constant value that is a valid address. */
693 #define CONSTANT_ADDRESS_P(X) \
694 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
695 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
696 || GET_CODE (X) == HIGH)
698 /* Nonzero if the constant value X is a legitimate general operand.
699 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
701 On the Sparc, this is anything but a CONST_DOUBLE.
702 Let's try permitting CONST_DOUBLEs and see what happens. */
704 #define LEGITIMATE_CONSTANT_P(X) 1
706 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
707 and check its validity for a certain class.
708 We have two alternate definitions for each of them.
709 The usual definition accepts all pseudo regs; the other rejects
710 them unless they have been allocated suitable hard regs.
711 The symbol REG_OK_STRICT causes the latter definition to be used.
713 Most source files want to accept pseudo regs in the hope that
714 they will get allocated to the class that the insn wants them to be in.
715 Source files for reload pass need to be strict.
716 After reload, it makes no difference, since pseudo regs have
717 been eliminated by then. */
719 #ifndef REG_OK_STRICT
721 /* Nonzero if X is a hard reg that can be used as an index
722 or if it is a pseudo reg. */
723 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
724 /* Nonzero if X is a hard reg that can be used as a base reg
725 or if it is a pseudo reg. */
726 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 14)
730 /* Nonzero if X is a hard reg that can be used as an index. */
731 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
732 /* Nonzero if X is a hard reg that can be used as a base reg. */
733 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
737 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
738 that is a valid memory address for an instruction.
739 The MODE argument is the machine mode for the MEM expression
740 that wants to use this address.
742 On the i860, the actual addresses must be REG+REG or REG+SMALLINT.
743 But we can treat a SYMBOL_REF as legitimate if it is part of this
744 function's constant-pool, because such addresses can actually
745 be output as REG+SMALLINT.
747 The displacement in an address must be a multiple of the alignment.
749 Try making SYMBOL_REF (and other things which are CONSTANT_ADDRESS_P)
750 a legitimate address, regardless. Because the only insns which can use
751 memory are load or store insns, the added hair in the machine description
752 is not that bad. It should also speed up the compiler by halving the number
753 of insns it must manage for each (MEM (SYMBOL_REF ...)) involved. */
755 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
756 { if (GET_CODE (X) == REG) \
757 { if (REG_OK_FOR_BASE_P (X)) goto ADDR; } \
758 else if (GET_CODE (X) == PLUS) \
760 if (GET_CODE (XEXP (X, 0)) == REG \
761 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
763 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
764 && INTVAL (XEXP (X, 1)) >= -0x8000 \
765 && INTVAL (XEXP (X, 1)) < 0x8000 \
766 && (INTVAL (XEXP (X, 1)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
769 else if (GET_CODE (XEXP (X, 1)) == REG \
770 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
772 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
773 && INTVAL (XEXP (X, 0)) >= -0x8000 \
774 && INTVAL (XEXP (X, 0)) < 0x8000 \
775 && (INTVAL (XEXP (X, 0)) & (GET_MODE_SIZE (MODE) - 1)) == 0) \
779 else if (CONSTANT_ADDRESS_P (X)) \
783 /* Try machine-dependent ways of modifying an illegitimate address
784 to be legitimate. If we find one, return the new, valid address.
785 This macro is used in only one place: `memory_address' in explow.c.
787 OLDX is the address as it was before break_out_memory_refs was called.
788 In some cases it is useful to look at this to decide what needs to be done.
790 MODE and WIN are passed so that this macro can use
791 GO_IF_LEGITIMATE_ADDRESS.
793 It is always safe for this macro to do nothing. It exists to recognize
794 opportunities to optimize the output. */
796 /* On the i860, change COMPLICATED + CONSTANT to REG+CONSTANT.
797 Also change a symbolic constant to a REG,
798 though that may not be necessary. */
800 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
801 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
802 (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
803 force_operand (XEXP (X, 0), 0)); \
804 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
805 (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
806 force_operand (XEXP (X, 1), 0)); \
807 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
808 (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
809 force_operand (XEXP (X, 0), 0)); \
810 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
811 (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
812 force_operand (XEXP (X, 1), 0)); \
813 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) != REG \
814 && GET_CODE (XEXP (X, 0)) != CONST_INT) \
815 (X) = gen_rtx_PLUS (SImode, XEXP (X, 1), \
816 copy_to_mode_reg (SImode, XEXP (X, 0))); \
817 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) != REG \
818 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
819 (X) = gen_rtx_PLUS (SImode, XEXP (X, 0), \
820 copy_to_mode_reg (SImode, XEXP (X, 1))); \
821 if (GET_CODE (x) == SYMBOL_REF) \
822 (X) = copy_to_reg (X); \
823 if (GET_CODE (x) == CONST) \
824 (X) = copy_to_reg (X); \
825 if (memory_address_p (MODE, X)) \
828 /* Go to LABEL if ADDR (a legitimate address expression)
829 has an effect that depends on the machine mode it is used for.
830 On the i860 this is never true.
831 There are some addresses that are invalid in wide modes
832 but valid for narrower modes, but they shouldn't affect
833 the places that use this macro. */
835 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
837 /* Specify the machine mode that this machine uses
838 for the index in the tablejump instruction. */
839 #define CASE_VECTOR_MODE SImode
841 /* Define as C expression which evaluates to nonzero if the tablejump
842 instruction expects the table to contain offsets from the address of the
844 Do not define this if the table should contain absolute addresses. */
845 /* #define CASE_VECTOR_PC_RELATIVE 1 */
847 /* Must pass floats to libgcc functions as doubles. */
848 #define LIBGCC_NEEDS_DOUBLE 1
850 #define DIVSI3_LIBCALL "*.div"
851 #define UDIVSI3_LIBCALL "*.udiv"
852 #define REMSI3_LIBCALL "*.rem"
853 #define UREMSI3_LIBCALL "*.urem"
855 /* Define this as 1 if `char' should by default be signed; else as 0. */
856 #define DEFAULT_SIGNED_CHAR 1
858 /* Max number of bytes we can move from memory to memory
859 in one reasonably fast instruction. */
862 /* Nonzero if access to memory by bytes is slow and undesirable. */
863 #define SLOW_BYTE_ACCESS 0
865 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
866 is done just by pretending it is already truncated. */
867 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
869 /* Value is 1 if it generates better code to perform an unsigned comparison
870 on the given literal integer value in the given mode when we are only
871 looking for an equal/non-equal result. */
872 /* For the i860, if the immediate value has its high-order 27 bits zero,
873 then we want to engineer an unsigned comparison for EQ/NE because
874 such values can fit in the 5-bit immediate field of a bte or btne
875 instruction (which gets zero extended before comparing). For all
876 other immediate values on the i860, we will use signed compares
877 because that avoids the need for doing explicit xor's to zero_extend
878 the non-constant operand in cases where it was (mem:QI ...) or a
879 (mem:HI ...) which always gets automatically sign-extended by the
880 hardware upon loading. */
882 #define LITERAL_COMPARE_BETTER_UNSIGNED(intval, mode) \
883 (((unsigned) (intval) & 0x1f) == (unsigned) (intval))
885 /* Specify the machine mode that pointers have.
886 After generation of rtl, the compiler makes no further distinction
887 between pointers and any other objects of this machine mode. */
890 /* A function address in a call instruction
891 is a byte address (for indexing purposes)
892 so give the MEM rtx a byte's mode. */
893 #define FUNCTION_MODE SImode
895 /* Define this if addresses of constant functions
896 shouldn't be put through pseudo regs where they can be cse'd.
897 Desirable on machines where ordinary constants are expensive
898 but a CALL with constant address is cheap. */
899 #define NO_FUNCTION_CSE
901 /* Compute the cost of computing a constant rtl expression RTX
902 whose rtx-code is CODE. The body of this macro is a portion
903 of a switch statement. If the code is computed here,
904 return it with a return statement. Otherwise, break from the switch. */
906 #define CONST_COSTS(RTX,CODE, OUTER_CODE) \
908 if (INTVAL (RTX) == 0) \
910 if (INTVAL (RTX) < 0x2000 && INTVAL (RTX) >= -0x2000) return 1; \
918 /* Specify the cost of a branch insn; roughly the number of extra insns that
919 should be added to avoid a branch.
921 Set this to 3 on the i860 since branches may often take three cycles. */
923 #define BRANCH_COST 3
925 /* Tell final.c how to eliminate redundant test instructions. */
927 /* Here we define machine-dependent flags and fields in cc_status
928 (see `conditions.h'). */
930 /* This holds the value sourcing h%r31. We keep this info
931 around so that mem/mem ops, such as increment and decrement,
932 etc, can be performed reasonably. */
933 #define CC_STATUS_MDEP rtx
935 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
937 #define CC_NEGATED 01000
939 /* We use this macro in those places in the i860.md file where we would
940 normally just do a CC_STATUS_INIT (for other machines). This macro
941 differs from CC_STATUS_INIT in that it doesn't mess with the special
942 bits or fields which describe what is currently in the special r31
943 scratch register, but it does clear out everything that actually
944 relates to the condition code bit of the i860. */
946 #define CC_STATUS_PARTIAL_INIT \
947 (cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ), \
948 cc_status.value1 = 0, \
949 cc_status.value2 = 0)
951 /* Nonzero if we know the value of h%r31. */
952 #define CC_KNOW_HI_R31 0100000
954 /* Nonzero if h%r31 is actually ha%something, rather than h%something. */
955 #define CC_HI_R31_ADJ 0200000
957 /* Store in cc_status the expressions
958 that the condition codes will describe
959 after execution of an instruction whose pattern is EXP.
960 Do not alter them if the instruction would not alter the cc's. */
962 /* On the i860, only compare insns set a useful condition code. */
964 #define NOTICE_UPDATE_CC(EXP, INSN) \
965 { cc_status.flags &= (CC_KNOW_HI_R31 | CC_HI_R31_ADJ); \
966 cc_status.value1 = 0; cc_status.value2 = 0; }
968 /* Control the assembler format that we output. */
970 /* Assembler pseudos to introduce constants of various size. */
972 #define ASM_DOUBLE "\t.double"
974 /* Output at beginning of assembler file. */
975 /* The .file command should always begin the output. */
977 #define ASM_FILE_START(FILE)
979 #define ASM_FILE_START(FILE) \
980 do { output_file_directive ((FILE), main_input_filename); \
981 if (optimize) ASM_FILE_START_1 (FILE); \
985 #define ASM_FILE_START_1(FILE)
987 /* Output to assembler file text saying following lines
988 may contain character constants, extra white space, comments, etc. */
990 #define ASM_APP_ON ""
992 /* Output to assembler file text saying following lines
993 no longer contain unusual constructs. */
995 #define ASM_APP_OFF ""
997 /* Output before read-only data. */
999 #define TEXT_SECTION_ASM_OP "\t.text"
1001 /* Output before writable data. */
1003 #define DATA_SECTION_ASM_OP "\t.data"
1005 /* How to refer to registers in assembler output.
1006 This sequence is indexed by compiler's hard-register-number (see above). */
1008 #define REGISTER_NAMES \
1009 {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", "r8", "r9", \
1010 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \
1011 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \
1013 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \
1014 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \
1015 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \
1018 /* This is how to output the definition of a user-level label named NAME,
1019 such as the label on a static function or variable NAME. */
1021 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1022 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1024 /* This is how to output a command to make the user-level label named NAME
1025 defined for reference from other files. */
1027 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1028 do { fputs (".globl ", FILE); \
1029 assemble_name (FILE, NAME); \
1030 fputs ("\n", FILE); \
1033 /* The prefix to add to user-visible assembler symbols.
1035 This definition is overridden in i860v4.h because under System V
1036 Release 4, user-level symbols are *not* prefixed with underscores in
1037 the generated assembly code. */
1039 #define USER_LABEL_PREFIX "_"
1041 /* This is how to output an internal numbered label where
1042 PREFIX is the class of label and NUM is the number within the class. */
1044 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1045 fprintf (FILE, ".%s%d:\n", PREFIX, NUM)
1047 /* This is how to output an internal numbered label which
1048 labels a jump table. */
1050 #undef ASM_OUTPUT_CASE_LABEL
1051 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
1052 do { ASM_OUTPUT_ALIGN ((FILE), 2); \
1053 ASM_OUTPUT_INTERNAL_LABEL ((FILE), PREFIX, NUM); \
1056 /* Output at the end of a jump table. */
1058 #define ASM_OUTPUT_CASE_END(FILE,NUM,INSN) \
1059 fprintf (FILE, ".text\n")
1061 /* This is how to store into the string LABEL
1062 the symbol_ref name of an internal numbered label where
1063 PREFIX is the class of label and NUM is the number within the class.
1064 This is suitable for output with `assemble_name'. */
1066 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1067 sprintf (LABEL, "*.%s%d", PREFIX, NUM)
1069 /* This is how to output code to push a register on the stack.
1070 It need not be very fast code. */
1072 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1073 fprintf (FILE, "\taddu -16,%ssp,%ssp\n\t%sst.l %s%s,0(%ssp)\n", \
1074 i860_reg_prefix, i860_reg_prefix, \
1075 ((REGNO) < 32 ? "" : "f"), \
1076 i860_reg_prefix, reg_names[REGNO], \
1079 /* This is how to output an insn to pop a register from the stack.
1080 It need not be very fast code. */
1082 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1083 fprintf (FILE, "\t%sld.l 0(%ssp),%s%s\n\taddu 16,%ssp,%ssp\n", \
1084 ((REGNO) < 32 ? "" : "f"), \
1086 i860_reg_prefix, reg_names[REGNO], \
1087 i860_reg_prefix, i860_reg_prefix)
1089 /* This is how to output an element of a case-vector that is absolute. */
1091 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1092 fprintf (FILE, "\t.long .L%d\n", VALUE)
1094 /* This is how to output an element of a case-vector that is relative.
1095 (The i860 does not use such vectors,
1096 but we must define this macro anyway.) */
1098 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1099 fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL)
1101 /* This is how to output an assembler line
1102 that says to advance the location counter
1103 to a multiple of 2**LOG bytes. */
1105 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1107 fprintf (FILE, "\t.align %d\n", 1 << (LOG))
1109 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1110 fprintf (FILE, "\t.blkb %u\n", (SIZE))
1112 /* This says how to output an assembler line
1113 to define a global common symbol. */
1115 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1116 ( fputs (".comm ", (FILE)), \
1117 assemble_name ((FILE), (NAME)), \
1118 fprintf ((FILE), ",%u\n", (ROUNDED)))
1120 /* This says how to output an assembler line
1121 to define a local common symbol. */
1123 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1124 ( fputs (".lcomm ", (FILE)), \
1125 assemble_name ((FILE), (NAME)), \
1126 fprintf ((FILE), ",%u\n", (ROUNDED)))
1128 /* Store in OUTPUT a string (made with alloca) containing
1129 an assembler-name for a local static variable named NAME.
1130 LABELNO is an integer which is different for each call. */
1132 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1133 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1134 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1136 /* Print operand X (an rtx) in assembler syntax to file FILE.
1137 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1138 For `%' followed by punctuation, CODE is the punctuation and X is null.
1140 In the following comments, the term "constant address" is used frequently.
1141 For an exact definition of what constitutes a "constant address" see the
1142 output_addr_const routine in final.c
1144 On the i860, the following target-specific special codes are recognized:
1146 `r' The operand can be anything, but if it is an immediate zero
1147 value (either integer or floating point) then it will be
1148 represented as `r0' or as `f0' (respectively).
1150 `m' The operand is a memory ref (to a constant address) but print
1151 its address as a constant.
1153 `L' The operand is a numeric constant, a constant address, or
1154 a memory ref to a constant address. Print the correct
1155 notation to yield the low part of the given value or
1156 address or the low part of the address of the referred
1159 `H' The operand is a numeric constant, a constant address, or
1160 a memory ref to a constant address. Print the correct
1161 notation to yield the high part of the given value or
1162 address or the high part of the address of the referred
1165 `h' The operand is a numeric constant, a constant address, or
1166 a memory ref to a constant address. Either print the
1167 correct notation to yield the plain high part of the
1168 given value or address (or the plain high part of the
1169 address of the memory object) or else print the correct
1170 notation to yield the "adjusted" high part of the given
1171 address (or of the address of the referred to memory object).
1173 The choice of what to print depends upon whether the address
1174 in question is relocatable or not. If it is relocatable,
1175 print the notation to get the adjusted high part. Otherwise
1176 just print the notation to get the plain high part. Note
1177 that "adjusted" high parts are generally used *only* when
1178 the next following instruction uses the low part of the
1179 address as an offset, as in `offset(reg)'.
1181 `R' The operand is a floating-pointer register. Print the
1182 name of the next following (32-bit) floating-point register.
1183 (This is used when moving a value into just the most
1184 significant part of a floating-point register pair.)
1186 `?' (takes no operand) Substitute the value of i860_reg_prefix
1187 at this point. The value of i860_reg_prefix is typically
1188 a null string for most i860 targets, but for System V
1189 Release 4 the i860 assembler syntax requires that all
1190 names of registers be prefixed with a percent-sign, so
1191 for SVR4, the value of i860_reg_prefix is initialized to
1195 extern const char *i860_reg_prefix;
1197 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '?')
1199 /* The following macro definition is overridden in i860v4.h
1200 because the svr4 i860 assembler required a different syntax
1201 for getting parts of constant/relocatable values. */
1203 #define PRINT_OPERAND_PART(FILE, X, PART_CODE) \
1204 do { fprintf (FILE, "%s%%", PART_CODE); \
1205 output_address (X); \
1208 #define OPERAND_LOW_PART "l"
1209 #define OPERAND_HIGH_PART "h"
1210 /* NOTE: All documentation available for the i860 sez that you must
1211 use "ha" to get the relocated high part of a relocatable, but
1212 reality sez different. */
1213 #define OPERAND_HIGH_ADJ_PART "ha"
1215 #define PRINT_OPERAND(FILE, X, CODE) \
1216 { if ((CODE) == '?') \
1217 fprintf (FILE, "%s", i860_reg_prefix); \
1218 else if (CODE == 'R') \
1219 fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X) + 1]); \
1220 else if (GET_CODE (X) == REG) \
1221 fprintf (FILE, "%s%s", i860_reg_prefix, reg_names[REGNO (X)]); \
1222 else if ((CODE) == 'm') \
1223 output_address (XEXP (X, 0)); \
1224 else if ((CODE) == 'L') \
1226 if (GET_CODE (X) == MEM) \
1227 PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_LOW_PART); \
1229 PRINT_OPERAND_PART (FILE, X, OPERAND_LOW_PART); \
1231 else if ((CODE) == 'H') \
1233 if (GET_CODE (X) == MEM) \
1234 PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_PART); \
1236 PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_PART); \
1238 else if ((CODE) == 'h') \
1240 if (GET_CODE (X) == MEM) \
1241 PRINT_OPERAND_PART (FILE, XEXP (X, 0), OPERAND_HIGH_ADJ_PART); \
1243 PRINT_OPERAND_PART (FILE, X, OPERAND_HIGH_ADJ_PART); \
1245 else if (GET_CODE (X) == MEM) \
1246 output_address (XEXP (X, 0)); \
1247 else if ((CODE) == 'r' && (X) == const0_rtx) \
1248 fprintf (FILE, "%sr0", i860_reg_prefix); \
1249 else if ((CODE) == 'r' && (X) == CONST0_RTX (GET_MODE (X))) \
1250 fprintf (FILE, "%sf0", i860_reg_prefix); \
1251 else if (GET_CODE (X) == CONST_DOUBLE) \
1252 fprintf (FILE, "0x%lx", sfmode_constant_to_ulong (X)); \
1254 output_addr_const (FILE, X); }
1256 /* Print a memory address as an operand to reference that memory location. */
1258 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1259 { register rtx addr = ADDR; \
1260 if (GET_CODE (addr) == REG) \
1262 fprintf (FILE, "0(%s%s)", \
1263 i860_reg_prefix, reg_names[REGNO (addr)]); \
1265 else if (GET_CODE (addr) == CONST_DOUBLE \
1266 && GET_MODE (addr) == SFmode) \
1267 fprintf (FILE, "0x%lx", sfmode_constant_to_ulong (addr)); \
1268 else if (GET_CODE (addr) == PLUS) \
1270 if ((GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1271 && (GET_CODE (XEXP (addr, 1)) == REG)) \
1272 fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 0)), \
1273 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
1274 else if ((GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1275 && (GET_CODE (XEXP (addr, 0)) == REG)) \
1276 fprintf (FILE, "%d(%s%s)", INTVAL (XEXP (addr, 1)), \
1277 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))]);\
1278 else if ((GET_CODE (XEXP (addr, 0)) == REG) \
1279 && (GET_CODE (XEXP (addr, 1)) == REG)) \
1280 fprintf (FILE, "%s%s(%s%s)", \
1281 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 0))], \
1282 i860_reg_prefix, reg_names[REGNO (XEXP (addr, 1))]);\
1284 output_addr_const (FILE, addr); \
1288 output_addr_const (FILE, addr); \
1292 /* Optionally define this if you have added predicates to
1293 `MACHINE.c'. This macro is called within an initializer of an
1294 array of structures. The first field in the structure is the
1295 name of a predicate and the second field is an array of rtl
1296 codes. For each predicate, list all rtl codes that can be in
1297 expressions matched by the predicate. The list should have a
1298 trailing comma. Here is an example of two entries in the list
1299 for a typical RISC machine:
1301 #define PREDICATE_CODES \
1302 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
1303 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
1305 Defining this macro does not affect the generated code (however,
1306 incorrect definitions that omit an rtl code that may be matched
1307 by the predicate can cause the compiler to malfunction).
1308 Instead, it allows the table built by `genrecog' to be more
1309 compact and efficient, thus speeding up the compiler. The most
1310 important predicates to include in the list specified by this
1311 macro are thoses used in the most insn patterns. */
1313 #define PREDICATE_CODES \
1314 {"reg_or_0_operand", {REG, SUBREG, CONST_INT}}, \
1315 {"arith_operand", {REG, SUBREG, CONST_INT}}, \
1316 {"logic_operand", {REG, SUBREG, CONST_INT}}, \
1317 {"shift_operand", {REG, SUBREG, CONST_INT}}, \
1318 {"compare_operand", {REG, SUBREG, CONST_INT}}, \
1319 {"arith_const_operand", {CONST_INT}}, \
1320 {"logic_const_operand", {CONST_INT}}, \
1321 {"bte_operand", {REG, SUBREG, CONST_INT}}, \
1322 {"indexed_operand", {MEM}}, \
1323 {"load_operand", {MEM}}, \
1324 {"small_int", {CONST_INT}}, \
1325 {"logic_int", {CONST_INT}}, \
1326 {"call_insn_operand", {MEM}},
1328 /* Define the information needed to generate branch insns. This is stored
1329 from the compare operation. Note that we can't use "rtx" here since it
1330 hasn't been defined! */
1332 extern struct rtx_def *i860_compare_op0, *i860_compare_op1;