1 /* Subroutines for insn-output.c for Intel i860
2 Copyright (C) 1989, 1991, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
6 Written by Richard Stallman (rms@ai.mit.edu).
8 Hacked substantially by Ron Guilmette (rfg@netcom.com) to cater
9 to the whims of the System V Release 4 assembler.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING. If not, write to
25 the Free Software Foundation, 59 Temple Place - Suite 330,
26 Boston, MA 02111-1307, USA. */
31 #include "coretypes.h"
37 #include "hard-reg-set.h"
39 #include "insn-config.h"
40 #include "conditions.h"
43 #include "insn-attr.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 static rtx find_addr_reg (rtx);
55 #ifndef I860_REG_PREFIX
56 #define I860_REG_PREFIX ""
59 const char *i860_reg_prefix = I860_REG_PREFIX;
61 /* Save information from a "cmpxx" operation until the branch is emitted. */
63 rtx i860_compare_op0, i860_compare_op1;
65 /* Return nonzero if this pattern, can be evaluated safely, even if it
68 safe_insn_src_p (rtx op, enum machine_mode mode)
70 /* Just experimenting. */
72 /* No floating point source is safe if it contains an arithmetic
73 operation, since that operation may trap. */
74 switch (GET_CODE (op))
86 return CONSTANT_ADDRESS_P (XEXP (op, 0));
88 /* We never need to negate or complement constants. */
90 return (mode != SFmode && mode != DFmode);
107 return (mode != SFmode && mode != DFmode);
114 if ((GET_CODE (XEXP (op, 0)) == CONST_INT && ! SMALL_INT (XEXP (op, 0)))
115 || (GET_CODE (XEXP (op, 1)) == CONST_INT && ! SMALL_INT (XEXP (op, 1))))
124 /* Return 1 if REG is clobbered in IN.
125 Return 2 if REG is used in IN.
126 Return 3 if REG is both used and clobbered in IN.
127 Return 0 if none of the above. */
130 reg_clobbered_p (rtx reg, rtx in)
132 register enum rtx_code code;
137 code = GET_CODE (in);
139 if (code == SET || code == CLOBBER)
141 rtx dest = SET_DEST (in);
145 while (GET_CODE (dest) == STRICT_LOW_PART
146 || GET_CODE (dest) == SUBREG
147 || GET_CODE (dest) == SIGN_EXTRACT
148 || GET_CODE (dest) == ZERO_EXTRACT)
149 dest = XEXP (dest, 0);
153 else if (GET_CODE (dest) == REG
154 && refers_to_regno_p (REGNO (reg),
155 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
159 /* Anything that sets just part of the register
160 is considered using as well as setting it.
161 But note that a straight SUBREG of a single-word value
162 clobbers the entire value. */
163 if (dest != SET_DEST (in)
164 && ! (GET_CODE (SET_DEST (in)) == SUBREG
165 || UNITS_PER_WORD >= GET_MODE_SIZE (GET_MODE (dest))))
172 used = refers_to_regno_p (REGNO (reg),
173 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
176 used = refers_to_regno_p (REGNO (reg),
177 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
181 return set + used * 2;
184 if (refers_to_regno_p (REGNO (reg),
185 REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
191 /* Return nonzero if OP can be written to without screwing up
192 GCC's model of what's going on. It is assumed that this operand
193 appears in the dest position of a SET insn in a conditional
194 branch's delay slot. AFTER is the label to start looking from. */
196 operand_clobbered_before_used_after (rtx op, rtx after)
198 /* Just experimenting. */
199 if (GET_CODE (op) == CC0)
201 if (GET_CODE (op) == REG)
205 if (op == stack_pointer_rtx)
208 /* Scan forward from the label, to see if the value of OP
209 is clobbered before the first use. */
211 for (insn = NEXT_INSN (after); insn; insn = NEXT_INSN (insn))
213 if (GET_CODE (insn) == NOTE)
215 if (GET_CODE (insn) == INSN
216 || GET_CODE (insn) == JUMP_INSN
217 || GET_CODE (insn) == CALL_INSN)
219 switch (reg_clobbered_p (op, PATTERN (insn)))
229 /* If we reach another label without clobbering OP,
230 then we cannot safely write it here. */
231 else if (GET_CODE (insn) == CODE_LABEL)
233 if (GET_CODE (insn) == JUMP_INSN)
235 if (condjump_p (insn))
237 /* This is a jump insn which has already
238 been mangled. We can't tell what it does. */
239 if (GET_CODE (PATTERN (insn)) == PARALLEL)
241 if (! JUMP_LABEL (insn))
243 /* Keep following jumps. */
244 insn = JUMP_LABEL (insn);
250 /* In both of these cases, the first insn executed
251 for this op will be a orh whatever%h,%r0,%r31,
252 which is tolerable. */
253 if (GET_CODE (op) == MEM)
254 return (CONSTANT_ADDRESS_P (XEXP (op, 0)));
260 /* Return nonzero only if OP is a register of mode MODE,
263 reg_or_0_operand (rtx op, enum machine_mode mode)
265 return (op == const0_rtx || register_operand (op, mode)
266 || op == CONST0_RTX (mode));
269 /* Return truth value of whether OP can be used as an operands in a three
270 address add/subtract insn (such as add %o1,7,%l2) of mode MODE. */
273 arith_operand (rtx op, enum machine_mode mode)
275 return (register_operand (op, mode)
276 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
279 /* Return 1 if OP is a valid first operand for a logical insn of mode MODE. */
282 logic_operand (rtx op, enum machine_mode mode)
284 return (register_operand (op, mode)
285 || (GET_CODE (op) == CONST_INT && LOGIC_INT (op)));
288 /* Return 1 if OP is a valid first operand for a shift insn of mode MODE. */
291 shift_operand (rtx op, enum machine_mode mode)
293 return (register_operand (op, mode)
294 || (GET_CODE (op) == CONST_INT));
297 /* Return 1 if OP is a valid first operand for either a logical insn
298 or an add insn of mode MODE. */
301 compare_operand (rtx op, enum machine_mode mode)
303 return (register_operand (op, mode)
304 || (GET_CODE (op) == CONST_INT && SMALL_INT (op) && LOGIC_INT (op)));
307 /* Return truth value of whether OP can be used as the 5-bit immediate
308 operand of a bte or btne insn. */
311 bte_operand (rtx op, enum machine_mode mode)
313 return (register_operand (op, mode)
314 || (GET_CODE (op) == CONST_INT
315 && (unsigned) INTVAL (op) < 0x20));
318 /* Return 1 if OP is an indexed memory reference of mode MODE. */
321 indexed_operand (rtx op, enum machine_mode mode)
323 return (GET_CODE (op) == MEM && GET_MODE (op) == mode
324 && GET_CODE (XEXP (op, 0)) == PLUS
325 && GET_MODE (XEXP (op, 0)) == SImode
326 && register_operand (XEXP (XEXP (op, 0), 0), SImode)
327 && register_operand (XEXP (XEXP (op, 0), 1), SImode));
330 /* Return 1 if OP is a suitable source operand for a load insn
334 load_operand (rtx op, enum machine_mode mode)
336 return (memory_operand (op, mode) || indexed_operand (op, mode));
339 /* Return truth value of whether OP is an integer which fits the
340 range constraining immediate operands in add/subtract insns. */
343 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
345 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
348 /* Return truth value of whether OP is an integer which fits the
349 range constraining immediate operands in logic insns. */
352 logic_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
354 return (GET_CODE (op) == CONST_INT && LOGIC_INT (op));
357 /* Test for a valid operand for a call instruction.
358 Don't allow the arg pointer register or virtual regs
359 since they may change into reg + const, which the patterns
363 call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
365 if (GET_CODE (op) == MEM
366 && (CONSTANT_ADDRESS_P (XEXP (op, 0))
367 || (GET_CODE (XEXP (op, 0)) == REG
368 && XEXP (op, 0) != arg_pointer_rtx
369 && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
370 && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
375 /* Return the best assembler insn template
376 for moving operands[1] into operands[0] as a fullword. */
379 singlemove_string (rtx *operands)
381 if (GET_CODE (operands[0]) == MEM)
383 if (GET_CODE (operands[1]) != MEM)
384 if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
386 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
387 && (cc_prev_status.flags & CC_HI_R31_ADJ)
388 && cc_prev_status.mdep == XEXP (operands[0], 0)))
391 output_asm_insn ("orh %h0,%?r0,%?r31", operands);
393 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
394 cc_status.mdep = XEXP (operands[0], 0);
395 return "st.l %r1,%L0(%?r31)";
398 return "st.l %r1,%0";
405 cc_status.flags &= ~CC_F0_IS_0;
406 xoperands[0] = gen_rtx_REG (SFmode, 32);
407 xoperands[1] = operands[1];
408 output_asm_insn (singlemove_string (xoperands), xoperands);
409 xoperands[1] = xoperands[0];
410 xoperands[0] = operands[0];
411 output_asm_insn (singlemove_string (xoperands), xoperands);
416 if (GET_CODE (operands[1]) == MEM)
418 if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
420 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
421 && (cc_prev_status.flags & CC_HI_R31_ADJ)
422 && cc_prev_status.mdep == XEXP (operands[1], 0)))
425 output_asm_insn ("orh %h1,%?r0,%?r31", operands);
427 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
428 cc_status.mdep = XEXP (operands[1], 0);
429 return "ld.l %L1(%?r31),%0";
431 return "ld.l %m1,%0";
433 if (GET_CODE (operands[1]) == CONST_INT)
435 if (operands[1] == const0_rtx)
436 return "mov %?r0,%0";
437 if((INTVAL (operands[1]) & 0xffff0000) == 0)
438 return "or %L1,%?r0,%0";
439 if((INTVAL (operands[1]) & 0xffff8000) == 0xffff8000)
440 return "adds %1,%?r0,%0";
441 if((INTVAL (operands[1]) & 0x0000ffff) == 0)
442 return "orh %H1,%?r0,%0";
444 return "orh %H1,%?r0,%0\n\tor %L1,%0,%0";
449 /* Output assembler code to perform a doubleword move insn
450 with operands OPERANDS. */
453 output_move_double (rtx *operands)
455 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
457 rtx addreg0 = 0, addreg1 = 0;
458 int highest_first = 0;
459 int no_addreg1_decrement = 0;
461 /* First classify both operands. */
463 if (REG_P (operands[0]))
465 else if (offsettable_memref_p (operands[0]))
467 else if (GET_CODE (operands[0]) == MEM)
472 if (REG_P (operands[1]))
474 else if (CONSTANT_P (operands[1]))
476 else if (offsettable_memref_p (operands[1]))
478 else if (GET_CODE (operands[1]) == MEM)
483 /* Check for the cases that the operand constraints are not
484 supposed to allow to happen. Abort if we get one,
485 because generating code for these cases is painful. */
487 if (optype0 == RNDOP || optype1 == RNDOP)
490 /* If an operand is an unoffsettable memory reference, find a register
491 we can increment temporarily to make it refer to the second word. */
493 if (optype0 == MEMOP)
494 addreg0 = find_addr_reg (XEXP (operands[0], 0));
496 if (optype1 == MEMOP)
497 addreg1 = find_addr_reg (XEXP (operands[1], 0));
499 /* ??? Perhaps in some cases move double words
500 if there is a spare pair of floating regs. */
502 /* Ok, we can do one word at a time.
503 Normally we do the low-numbered word first,
504 but if either operand is autodecrementing then we
505 do the high-numbered word first.
507 In either case, set up in LATEHALF the operands to use
508 for the high-numbered word and in some cases alter the
509 operands in OPERANDS to be suitable for the low-numbered word. */
511 if (optype0 == REGOP)
512 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
513 else if (optype0 == OFFSOP)
514 latehalf[0] = adjust_address (operands[0], SImode, 4);
516 latehalf[0] = operands[0];
518 if (optype1 == REGOP)
519 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
520 else if (optype1 == OFFSOP)
521 latehalf[1] = adjust_address (operands[1], SImode, 4);
522 else if (optype1 == CNSTOP)
524 if (GET_CODE (operands[1]) == CONST_DOUBLE)
525 split_double (operands[1], &operands[1], &latehalf[1]);
527 else if (CONSTANT_P (operands[1]))
528 latehalf[1] = const0_rtx;
530 else if (CONSTANT_P (operands[1]))
531 split_double (operands[1], &operands[1], &latehalf[1]);
535 latehalf[1] = operands[1];
537 /* If the first move would clobber the source of the second one,
538 do them in the other order.
540 RMS says "This happens only for registers;
541 such overlap can't happen in memory unless the user explicitly
542 sets it up, and that is an undefined circumstance."
544 But it happens on the sparc when loading parameter registers,
545 so I am going to define that circumstance, and make it work
548 if (optype0 == REGOP && optype1 == REGOP
549 && REGNO (operands[0]) == REGNO (latehalf[1]))
551 CC_STATUS_PARTIAL_INIT;
552 /* Make any unoffsettable addresses point at high-numbered word. */
554 output_asm_insn ("adds 0x4,%0,%0", &addreg0);
556 output_asm_insn ("adds 0x4,%0,%0", &addreg1);
559 output_asm_insn (singlemove_string (latehalf), latehalf);
561 /* Undo the adds we just did. */
563 output_asm_insn ("adds -0x4,%0,%0", &addreg0);
565 output_asm_insn ("adds -0x4,%0,%0", &addreg1);
567 /* Do low-numbered word. */
568 return singlemove_string (operands);
570 else if (optype0 == REGOP && optype1 != REGOP
571 && reg_overlap_mentioned_p (operands[0], operands[1]))
573 /* If both halves of dest are used in the src memory address,
574 add the two regs and put them in the low reg (operands[0]).
575 Then it works to load latehalf first. */
576 if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
577 && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
580 xops[0] = latehalf[0];
581 xops[1] = operands[0];
582 output_asm_insn ("adds %1,%0,%1", xops);
583 operands[1] = gen_rtx_MEM (DImode, operands[0]);
584 latehalf[1] = adjust_address (operands[1], SImode, 4);
588 /* Only one register in the dest is used in the src memory address,
589 and this is the first register of the dest, so we want to do
590 the late half first here also. */
591 else if (! reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
593 /* Only one register in the dest is used in the src memory address,
594 and this is the second register of the dest, so we want to do
595 the late half last. If addreg1 is set, and addreg1 is the same
596 register as latehalf, then we must suppress the trailing decrement,
597 because it would clobber the value just loaded. */
598 else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0]))
599 no_addreg1_decrement = 1;
602 /* Normal case: do the two words, low-numbered first.
603 Overlap case (highest_first set): do high-numbered word first. */
606 output_asm_insn (singlemove_string (operands), operands);
608 CC_STATUS_PARTIAL_INIT;
609 /* Make any unoffsettable addresses point at high-numbered word. */
611 output_asm_insn ("adds 0x4,%0,%0", &addreg0);
613 output_asm_insn ("adds 0x4,%0,%0", &addreg1);
616 output_asm_insn (singlemove_string (latehalf), latehalf);
618 /* Undo the adds we just did. */
620 output_asm_insn ("adds -0x4,%0,%0", &addreg0);
621 if (addreg1 && !no_addreg1_decrement)
622 output_asm_insn ("adds -0x4,%0,%0", &addreg1);
625 output_asm_insn (singlemove_string (operands), operands);
631 output_fp_move_double (rtx *operands)
633 /* If the source operand is any sort of zero, use f0 instead. */
635 if (operands[1] == CONST0_RTX (GET_MODE (operands[1])))
636 operands[1] = gen_rtx_REG (DFmode, F0_REGNUM);
638 if (FP_REG_P (operands[0]))
640 if (FP_REG_P (operands[1]))
641 return "fmov.dd %1,%0";
642 if (GET_CODE (operands[1]) == REG)
644 output_asm_insn ("ixfr %1,%0", operands);
645 operands[0] = gen_rtx_REG (VOIDmode, REGNO (operands[0]) + 1);
646 operands[1] = gen_rtx_REG (VOIDmode, REGNO (operands[1]) + 1);
649 if (operands[1] == CONST0_RTX (DFmode))
650 return "fmov.dd f0,%0";
651 if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
653 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
654 && (cc_prev_status.flags & CC_HI_R31_ADJ)
655 && cc_prev_status.mdep == XEXP (operands[1], 0)))
658 output_asm_insn ("orh %h1,%?r0,%?r31", operands);
660 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
661 cc_status.mdep = XEXP (operands[1], 0);
662 return "fld.d %L1(%?r31),%0";
664 return "fld.d %1,%0";
666 else if (FP_REG_P (operands[1]))
668 if (GET_CODE (operands[0]) == REG)
670 output_asm_insn ("fxfr %1,%0", operands);
671 operands[0] = gen_rtx_REG (VOIDmode, REGNO (operands[0]) + 1);
672 operands[1] = gen_rtx_REG (VOIDmode, REGNO (operands[1]) + 1);
675 if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
677 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
678 && (cc_prev_status.flags & CC_HI_R31_ADJ)
679 && cc_prev_status.mdep == XEXP (operands[0], 0)))
682 output_asm_insn ("orh %h0,%?r0,%?r31", operands);
684 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
685 cc_status.mdep = XEXP (operands[0], 0);
686 return "fst.d %1,%L0(%?r31)";
688 return "fst.d %1,%0";
696 /* Return a REG that occurs in ADDR with coefficient 1.
697 ADDR can be effectively incremented by incrementing REG. */
700 find_addr_reg (rtx addr)
702 while (GET_CODE (addr) == PLUS)
704 if (GET_CODE (XEXP (addr, 0)) == REG)
705 addr = XEXP (addr, 0);
706 else if (GET_CODE (XEXP (addr, 1)) == REG)
707 addr = XEXP (addr, 1);
708 else if (CONSTANT_P (XEXP (addr, 0)))
709 addr = XEXP (addr, 1);
710 else if (CONSTANT_P (XEXP (addr, 1)))
711 addr = XEXP (addr, 0);
715 if (GET_CODE (addr) == REG)
722 /* Return a template for a load instruction with mode MODE and
723 arguments from the string ARGS.
725 This string is in static storage. */
728 load_opcode (enum machine_mode mode, const char *args, rtx reg)
762 sprintf (buf, "%s %s", opcode, args);
766 /* Return a template for a store instruction with mode MODE and
767 arguments from the string ARGS.
769 This string is in static storage. */
772 store_opcode (enum machine_mode mode, const char *args, rtx reg)
806 sprintf (buf, "%s %s", opcode, args);
810 /* Output a store-in-memory whose operands are OPERANDS[0,1].
811 OPERANDS[0] is a MEM, and OPERANDS[1] is a reg or zero.
813 This function returns a template for an insn.
814 This is in static storage.
816 It may also output some insns directly.
817 It may alter the values of operands[0] and operands[1]. */
820 output_store (rtx *operands)
822 enum machine_mode mode = GET_MODE (operands[0]);
823 rtx address = XEXP (operands[0], 0);
825 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
826 cc_status.mdep = address;
828 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
829 && (cc_prev_status.flags & CC_HI_R31_ADJ)
830 && address == cc_prev_status.mdep))
833 output_asm_insn ("orh %h0,%?r0,%?r31", operands);
834 cc_prev_status.mdep = address;
837 /* Store zero in two parts when appropriate. */
838 if (mode == DFmode && operands[1] == CONST0_RTX (DFmode))
839 return store_opcode (DFmode, "%r1,%L0(%?r31)", operands[1]);
841 /* Code below isn't smart enough to move a doubleword in two parts,
842 so use output_move_double to do that in the cases that require it. */
843 if ((mode == DImode || mode == DFmode)
844 && ! FP_REG_P (operands[1]))
845 return output_move_double (operands);
847 return store_opcode (mode, "%r1,%L0(%?r31)", operands[1]);
850 /* Output a load-from-memory whose operands are OPERANDS[0,1].
851 OPERANDS[0] is a reg, and OPERANDS[1] is a mem.
853 This function returns a template for an insn.
854 This is in static storage.
856 It may also output some insns directly.
857 It may alter the values of operands[0] and operands[1]. */
860 output_load (rtx *operands)
862 enum machine_mode mode = GET_MODE (operands[0]);
863 rtx address = XEXP (operands[1], 0);
865 /* We don't bother trying to see if we know %hi(address).
866 This is because we are doing a load, and if we know the
867 %hi value, we probably also know that value in memory. */
868 cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
869 cc_status.mdep = address;
871 if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
872 && (cc_prev_status.flags & CC_HI_R31_ADJ)
873 && address == cc_prev_status.mdep
874 && cc_prev_status.mdep == cc_status.mdep))
877 output_asm_insn ("orh %h1,%?r0,%?r31", operands);
878 cc_prev_status.mdep = address;
881 /* Code below isn't smart enough to move a doubleword in two parts,
882 so use output_move_double to do that in the cases that require it. */
883 if ((mode == DImode || mode == DFmode)
884 && ! FP_REG_P (operands[0]))
885 return output_move_double (operands);
887 return load_opcode (mode, "%L1(%?r31),%0", operands[0]);
891 /* Load the address specified by OPERANDS[3] into the register
892 specified by OPERANDS[0].
894 OPERANDS[3] may be the result of a sum, hence it could either be:
899 (3) REG + REG + CONST_INT
900 (4) REG + REG (special case of 3).
902 Note that (3) is not a legitimate address.
903 All cases are handled here. */
906 output_load_address (rtx *operands)
910 if (CONSTANT_P (operands[3]))
912 output_asm_insn ("mov %3,%0", operands);
916 if (REG_P (operands[3]))
918 if (REGNO (operands[0]) != REGNO (operands[3]))
919 output_asm_insn ("shl %?r0,%3,%0", operands);
923 if (GET_CODE (operands[3]) != PLUS)
926 base = XEXP (operands[3], 0);
927 offset = XEXP (operands[3], 1);
929 if (GET_CODE (base) == CONST_INT)
936 if (GET_CODE (offset) != CONST_INT)
938 /* Operand is (PLUS (REG) (REG)). */
946 operands[7] = offset;
947 CC_STATUS_PARTIAL_INIT;
948 if (SMALL_INT (offset))
949 output_asm_insn ("adds %7,%6,%0", operands);
951 output_asm_insn ("mov %7,%0\n\tadds %0,%6,%0", operands);
953 else if (GET_CODE (base) == PLUS)
955 operands[6] = XEXP (base, 0);
956 operands[7] = XEXP (base, 1);
957 operands[8] = offset;
959 CC_STATUS_PARTIAL_INIT;
960 if (SMALL_INT (offset))
961 output_asm_insn ("adds %6,%7,%0\n\tadds %8,%0,%0", operands);
963 output_asm_insn ("mov %8,%0\n\tadds %0,%6,%0\n\tadds %0,%7,%0", operands);
970 /* Output code to place a size count SIZE in register REG.
971 Because block moves are pipelined, we don't include the
972 first element in the transfer of SIZE to REG.
973 For this, we subtract ALIGN. (Actually, I think it is not
974 right to subtract on this machine, so right now we don't.) */
977 output_size_for_block_move (rtx size, rtx reg, rtx align)
983 xoperands[2] = align;
986 cc_status.flags &= ~ CC_KNOW_HI_R31;
987 output_asm_insn (singlemove_string (xoperands), xoperands);
989 if (GET_CODE (size) == REG)
990 output_asm_insn ("sub %2,%1,%0", xoperands);
993 xoperands[1] = GEN_INT (INTVAL (size) - INTVAL (align));
994 cc_status.flags &= ~ CC_KNOW_HI_R31;
995 output_asm_insn ("mov %1,%0", xoperands);
1000 /* Emit code to perform a block move.
1002 OPERANDS[0] is the destination.
1003 OPERANDS[1] is the source.
1004 OPERANDS[2] is the size.
1005 OPERANDS[3] is the known safe alignment.
1006 OPERANDS[4..6] are pseudos we can safely clobber as temps. */
1009 output_block_move (rtx *operands)
1011 /* A vector for our computed operands. Note that load_output_address
1012 makes use of (and can clobber) up to the 8th element of this vector. */
1017 static int movstrsi_label = 0;
1019 rtx temp1 = operands[4];
1020 rtx alignrtx = operands[3];
1021 int align = INTVAL (alignrtx);
1024 xoperands[0] = operands[0];
1025 xoperands[1] = operands[1];
1026 xoperands[2] = temp1;
1028 /* We can't move more than four bytes at a time
1029 because we have only one register to move them through. */
1033 alignrtx = GEN_INT (4);
1036 /* Recognize special cases of block moves. These occur
1037 when GNU C++ is forced to treat something as BLKmode
1038 to keep it in memory, when its mode could be represented
1039 with something smaller.
1041 We cannot do this for global variables, since we don't know
1042 what pages they don't cross. Sigh. */
1043 if (GET_CODE (operands[2]) == CONST_INT
1044 && ! CONSTANT_ADDRESS_P (operands[0])
1045 && ! CONSTANT_ADDRESS_P (operands[1]))
1047 int size = INTVAL (operands[2]);
1048 rtx op0 = xoperands[0];
1049 rtx op1 = xoperands[1];
1051 if ((align & 3) == 0 && (size & 3) == 0 && (size >> 2) <= 16)
1053 if (memory_address_p (SImode, plus_constant (op0, size))
1054 && memory_address_p (SImode, plus_constant (op1, size)))
1056 cc_status.flags &= ~CC_KNOW_HI_R31;
1057 for (i = (size>>2)-1; i >= 0; i--)
1059 xoperands[0] = plus_constant (op0, i * 4);
1060 xoperands[1] = plus_constant (op1, i * 4);
1061 output_asm_insn ("ld.l %a1,%?r31\n\tst.l %?r31,%a0",
1067 else if ((align & 1) == 0 && (size & 1) == 0 && (size >> 1) <= 16)
1069 if (memory_address_p (HImode, plus_constant (op0, size))
1070 && memory_address_p (HImode, plus_constant (op1, size)))
1072 cc_status.flags &= ~CC_KNOW_HI_R31;
1073 for (i = (size>>1)-1; i >= 0; i--)
1075 xoperands[0] = plus_constant (op0, i * 2);
1076 xoperands[1] = plus_constant (op1, i * 2);
1077 output_asm_insn ("ld.s %a1,%?r31\n\tst.s %?r31,%a0",
1083 else if (size <= 16)
1085 if (memory_address_p (QImode, plus_constant (op0, size))
1086 && memory_address_p (QImode, plus_constant (op1, size)))
1088 cc_status.flags &= ~CC_KNOW_HI_R31;
1089 for (i = size-1; i >= 0; i--)
1091 xoperands[0] = plus_constant (op0, i);
1092 xoperands[1] = plus_constant (op1, i);
1093 output_asm_insn ("ld.b %a1,%?r31\n\tst.b %?r31,%a0",
1101 /* Since we clobber untold things, nix the condition codes. */
1104 /* This is the size of the transfer.
1105 Either use the register which already contains the size,
1106 or use a free register (used by no operands). */
1107 output_size_for_block_move (operands[2], operands[4], alignrtx);
1110 /* Also emit code to decrement the size value by ALIGN. */
1111 zoperands[0] = operands[0];
1112 zoperands[3] = plus_constant (operands[0], align);
1113 output_load_address (zoperands);
1116 /* Generate number for unique label. */
1118 xoperands[3] = GEN_INT (movstrsi_label++);
1120 /* Calculate the size of the chunks we will be trying to move first. */
1123 if ((align & 3) == 0)
1125 else if ((align & 1) == 0)
1131 /* Copy the increment (negative) to a register for bla insn. */
1133 xoperands[4] = GEN_INT (- chunk_size);
1134 xoperands[5] = operands[5];
1135 output_asm_insn ("adds %4,%?r0,%5", xoperands);
1137 /* Predecrement the loop counter. This happens again also in the `bla'
1138 instruction which precedes the loop, but we need to have it done
1139 two times before we enter the loop because of the bizarre semantics
1140 of the bla instruction. */
1142 output_asm_insn ("adds %5,%2,%2", xoperands);
1144 /* Check for the case where the original count was less than or equal to
1145 zero. Avoid going through the loop at all if the original count was
1146 indeed less than or equal to zero. Note that we treat the count as
1147 if it were a signed 32-bit quantity here, rather than an unsigned one,
1148 even though we really shouldn't. We have to do this because of the
1149 semantics of the `ble' instruction, which assume that the count is
1150 a signed 32-bit value. Anyway, in practice it won't matter because
1151 nobody is going to try to do a memcpy() of more than half of the
1152 entire address space (i.e. 2 gigabytes) anyway. */
1154 output_asm_insn ("bc .Le%3", xoperands);
1156 /* Make available a register which is a temporary. */
1158 xoperands[6] = operands[6];
1160 /* Now the actual loop.
1161 In xoperands, elements 1 and 0 are the input and output vectors.
1162 Element 2 is the loop index. Element 5 is the increment. */
1164 output_asm_insn ("subs %1,%5,%1", xoperands);
1165 output_asm_insn ("bla %5,%2,.Lm%3", xoperands);
1166 output_asm_insn ("adds %0,%2,%6", xoperands);
1167 output_asm_insn ("\n.Lm%3:", xoperands); /* Label for bla above. */
1168 output_asm_insn ("\n.Ls%3:", xoperands); /* Loop start label. */
1169 output_asm_insn ("adds %5,%6,%6", xoperands);
1171 /* NOTE: The code here which is supposed to handle the cases where the
1172 sources and destinations are known to start on a 4 or 2 byte boundary
1173 are currently broken. They fail to do anything about the overflow
1174 bytes which might still need to be copied even after we have copied
1175 some number of words or halfwords. Thus, for now we use the lowest
1176 common denominator, i.e. the code which just copies some number of
1177 totally unaligned individual bytes. (See the calculation of
1178 chunk_size above. */
1180 if (chunk_size == 4)
1182 output_asm_insn ("ld.l %2(%1),%?r31", xoperands);
1183 output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1184 output_asm_insn ("st.l %?r31,8(%6)", xoperands);
1186 else if (chunk_size == 2)
1188 output_asm_insn ("ld.s %2(%1),%?r31", xoperands);
1189 output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1190 output_asm_insn ("st.s %?r31,4(%6)", xoperands);
1192 else /* chunk_size == 1 */
1194 output_asm_insn ("ld.b %2(%1),%?r31", xoperands);
1195 output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1196 output_asm_insn ("st.b %?r31,2(%6)", xoperands);
1198 output_asm_insn ("\n.Le%3:", xoperands); /* Here if count <= 0. */
1203 /* Special routine to convert an SFmode value represented as a
1204 CONST_DOUBLE into its equivalent unsigned long bit pattern.
1205 We convert the value from a double precision floating-point
1206 value to single precision first, and thence to a bit-wise
1207 equivalent unsigned long value. This routine is used when
1208 generating an immediate move of an SFmode value directly
1209 into a general register because the SVR4 assembler doesn't
1210 grok floating literals in instruction operand contexts. */
1213 sfmode_constant_to_ulong (rtx x)
1218 if (GET_CODE (x) != CONST_DOUBLE || GET_MODE (x) != SFmode)
1221 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1222 REAL_VALUE_TO_TARGET_SINGLE (d, l);
1226 /* This function generates the assembly code for function entry.
1228 ASM_FILE is a stdio stream to output the code to.
1229 SIZE is an int: how many units of temporary storage to allocate.
1231 Refer to the array `regs_ever_live' to determine which registers
1232 to save; `regs_ever_live[I]' is nonzero if register number I
1233 is ever used in the function. This macro is responsible for
1234 knowing which registers should not be saved even if used.
1236 NOTE: `frame_lower_bytes' is the count of bytes which will lie
1237 between the new `fp' value and the new `sp' value after the
1238 prologue is done. `frame_upper_bytes' is the count of bytes
1239 that will lie between the new `fp' and the *old* `sp' value
1240 after the new `fp' is setup (in the prologue). The upper
1241 part of each frame always includes at least 2 words (8 bytes)
1242 to hold the saved frame pointer and the saved return address.
1244 The SVR4 ABI for the i860 now requires that the values of the
1245 stack pointer and frame pointer registers be kept aligned to
1246 16-byte boundaries at all times. We obey that restriction here.
1248 The SVR4 ABI for the i860 is entirely vague when it comes to specifying
1249 exactly where the "preserved" registers should be saved. The native
1250 SVR4 C compiler I now have doesn't help to clarify the requirements
1251 very much because it is plainly out-of-date and non-ABI-compliant
1252 (in at least one important way, i.e. how it generates function
1255 The native SVR4 C compiler saves the "preserved" registers (i.e.
1256 r4-r15 and f2-f7) in the lower part of a frame (i.e. at negative
1257 offsets from the frame pointer).
1259 Previous versions of GCC also saved the "preserved" registers in the
1260 "negative" part of the frame, but they saved them using positive
1261 offsets from the (adjusted) stack pointer (after it had been adjusted
1262 to allocate space for the new frame). That's just plain wrong
1263 because if the current function calls alloca(), the stack pointer
1264 will get moved, and it will be impossible to restore the registers
1265 properly again after that.
1267 Both compilers handled parameter registers (i.e. r16-r27 and f8-f15)
1268 by copying their values either into various "preserved" registers or
1269 into stack slots in the lower part of the current frame (as seemed
1270 appropriate, depending upon subsequent usage of these values).
1272 Here we want to save the preserved registers at some offset from the
1273 frame pointer register so as to avoid any possible problems arising
1274 from calls to alloca(). We can either save them at small positive
1275 offsets from the frame pointer, or at small negative offsets from
1276 the frame pointer. If we save them at small negative offsets from
1277 the frame pointer (i.e. in the lower part of the frame) then we
1278 must tell the rest of GCC (via STARTING_FRAME_OFFSET) exactly how
1279 many bytes of space we plan to use in the lower part of the frame
1280 for this purpose. Since other parts of the compiler reference the
1281 value of STARTING_FRAME_OFFSET long before final() calls this function,
1282 we would have to go ahead and assume the worst-case storage requirements
1283 for saving all of the "preserved" registers (and use that number, i.e.
1284 `80', to define STARTING_FRAME_OFFSET) if we wanted to save them in
1285 the lower part of the frame. That could potentially be very wasteful,
1286 and that wastefulness could really hamper people compiling for embedded
1287 i860 targets with very tight limits on stack space. Thus, we choose
1288 here to save the preserved registers in the upper part of the
1289 frame, so that we can decide at the very last minute how much (or how
1290 little) space we must allocate for this purpose.
1292 To satisfy the needs of the SVR4 ABI "tdesc" scheme, preserved
1293 registers must always be saved so that the saved values of registers
1294 with higher numbers are at higher addresses. We obey that restriction
1297 There are two somewhat different ways that you can generate prologues
1298 here... i.e. pedantically ABI-compliant, and the "other" way. The
1299 "other" way is more consistent with what is currently generated by the
1300 "native" SVR4 C compiler for the i860. That's important if you want
1301 to use the current (as of 8/91) incarnation of SVR4 SDB for the i860.
1302 The SVR4 SDB for the i860 insists on having function prologues be
1305 To get fully ABI-compliant prologues, define I860_STRICT_ABI_PROLOGUES
1306 in the i860/sysv4.h file. (By default this is *not* defined).
1308 The differences between the ABI-compliant and non-ABI-compliant prologues
1309 are that (a) the ABI version seems to require the use of *signed*
1310 (rather than unsigned) adds and subtracts, and (b) the ordering of
1311 the various steps (e.g. saving preserved registers, saving the
1312 return address, setting up the new frame pointer value) is different.
1314 For strict ABI compliance, it seems to be the case that the very last
1315 thing that is supposed to happen in the prologue is getting the frame
1316 pointer set to its new value (but only after everything else has
1317 already been properly setup). We do that here, but only if the symbol
1318 I860_STRICT_ABI_PROLOGUES is defined. */
1320 #ifndef STACK_ALIGNMENT
1321 #define STACK_ALIGNMENT 16
1324 const char *current_function_original_name;
1326 static int must_preserve_r1;
1327 static unsigned must_preserve_bytes;
1330 i860_output_function_prologue (FILE *asm_file, HOST_WIDE_INT local_bytes)
1332 register HOST_WIDE_INT frame_lower_bytes;
1333 register HOST_WIDE_INT frame_upper_bytes;
1334 register HOST_WIDE_INT total_fsize;
1335 register unsigned preserved_reg_bytes = 0;
1336 register unsigned i;
1337 register unsigned preserved_so_far = 0;
1339 must_preserve_r1 = (optimize < 2 || ! leaf_function_p ());
1340 must_preserve_bytes = 4 + (must_preserve_r1 ? 4 : 0);
1342 /* Count registers that need preserving. Ignore r0. It never needs
1345 for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
1347 if (regs_ever_live[i] && ! call_used_regs[i])
1348 preserved_reg_bytes += 4;
1351 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1353 frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1355 /* The upper part of each frame will contain the saved fp,
1356 the saved r1, and stack slots for all of the other "preserved"
1357 registers that we find we will need to save & restore. */
1359 frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
1361 /* Round-up the frame_upper_bytes so that it's a multiple of 16. */
1364 = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1366 total_fsize = frame_upper_bytes + frame_lower_bytes;
1368 #ifndef I860_STRICT_ABI_PROLOGUES
1370 /* There are two kinds of function prologues.
1371 You use the "small" version if the total frame size is
1372 small enough so that it can fit into an immediate 16-bit
1373 value in one instruction. Otherwise, you use the "large"
1374 version of the function prologue. */
1376 if (total_fsize > 0x7fff)
1378 /* Adjust the stack pointer. The ABI specifies using `adds' for
1379 this, but the native C compiler on SVR4 uses `addu'. */
1381 fprintf (asm_file, "\taddu -" HOST_WIDE_INT_PRINT_DEC ",%ssp,%ssp\n",
1382 frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
1384 /* Save the old frame pointer. */
1386 fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
1387 i860_reg_prefix, i860_reg_prefix);
1389 /* Setup the new frame pointer. The ABI specifies that this is to
1390 be done after preserving registers (using `adds'), but that's not
1391 what the native C compiler on SVR4 does. */
1393 fprintf (asm_file, "\taddu 0,%ssp,%sfp\n",
1394 i860_reg_prefix, i860_reg_prefix);
1396 /* Get the value of frame_lower_bytes into r31. */
1398 fprintf (asm_file, "\torh " HOST_WIDE_INT_PRINT_DEC ",%sr0,%sr31\n",
1399 frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
1400 fprintf (asm_file, "\tor " HOST_WIDE_INT_PRINT_DEC ",%sr31,%sr31\n",
1401 frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
1403 /* Now re-adjust the stack pointer using the value in r31.
1404 The ABI specifies that this is done with `subs' but SDB may
1407 fprintf (asm_file, "\tsubu %ssp,%sr31,%ssp\n",
1408 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1410 /* Preserve registers. The ABI specifies that this is to be done
1411 before setting up the new frame pointer, but that's not what the
1412 native C compiler on SVR4 does. */
1414 for (i = 1; i < 32; i++)
1415 if (regs_ever_live[i] && ! call_used_regs[i])
1416 fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
1417 i860_reg_prefix, reg_names[i],
1418 must_preserve_bytes + (4 * preserved_so_far++),
1421 for (i = 32; i < 64; i++)
1422 if (regs_ever_live[i] && ! call_used_regs[i])
1423 fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
1424 i860_reg_prefix, reg_names[i],
1425 must_preserve_bytes + (4 * preserved_so_far++),
1428 /* Save the return address. */
1430 if (must_preserve_r1)
1431 fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
1432 i860_reg_prefix, i860_reg_prefix);
1436 /* Adjust the stack pointer. The ABI specifies using `adds' for this,
1437 but the native C compiler on SVR4 uses `addu'. */
1439 fprintf (asm_file, "\taddu -" HOST_WIDE_INT_PRINT_DEC ",%ssp,%ssp\n",
1440 total_fsize, i860_reg_prefix, i860_reg_prefix);
1442 /* Save the old frame pointer. */
1444 fprintf (asm_file, "\tst.l %sfp," HOST_WIDE_INT_PRINT_DEC "(%ssp)\n",
1445 i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
1447 /* Setup the new frame pointer. The ABI specifies that this is to be
1448 done after preserving registers and after saving the return address,
1449 (and to do it using `adds'), but that's not what the native C
1450 compiler on SVR4 does. */
1452 fprintf (asm_file, "\taddu " HOST_WIDE_INT_PRINT_DEC ",%ssp,%sfp\n",
1453 frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
1455 /* Preserve registers. The ABI specifies that this is to be done
1456 before setting up the new frame pointer, but that's not what the
1457 native compiler on SVR4 does. */
1459 for (i = 1; i < 32; i++)
1460 if (regs_ever_live[i] && ! call_used_regs[i])
1461 fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
1462 i860_reg_prefix, reg_names[i],
1463 must_preserve_bytes + (4 * preserved_so_far++),
1466 for (i = 32; i < 64; i++)
1467 if (regs_ever_live[i] && ! call_used_regs[i])
1468 fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
1469 i860_reg_prefix, reg_names[i],
1470 must_preserve_bytes + (4 * preserved_so_far++),
1473 /* Save the return address. The ABI specifies that this is to be
1474 done earlier, and also via an offset from %sp, but the native C
1475 compiler on SVR4 does it later (i.e. now) and uses an offset from
1478 if (must_preserve_r1)
1479 fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
1480 i860_reg_prefix, i860_reg_prefix);
1483 #else /* defined(I860_STRICT_ABI_PROLOGUES) */
1485 /* There are two kinds of function prologues.
1486 You use the "small" version if the total frame size is
1487 small enough so that it can fit into an immediate 16-bit
1488 value in one instruction. Otherwise, you use the "large"
1489 version of the function prologue. */
1491 if (total_fsize > 0x7fff)
1493 /* Adjust the stack pointer (thereby allocating a new frame). */
1495 fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
1496 frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
1498 /* Save the caller's frame pointer. */
1500 fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
1501 i860_reg_prefix, i860_reg_prefix);
1503 /* Save return address. */
1505 if (must_preserve_r1)
1506 fprintf (asm_file, "\tst.l %sr1,4(%ssp)\n",
1507 i860_reg_prefix, i860_reg_prefix);
1509 /* Get the value of frame_lower_bytes into r31 for later use. */
1511 fprintf (asm_file, "\torh %d,%sr0,%sr31\n",
1512 frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
1513 fprintf (asm_file, "\tor %d,%sr31,%sr31\n",
1514 frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
1516 /* Now re-adjust the stack pointer using the value in r31. */
1518 fprintf (asm_file, "\tsubs %ssp,%sr31,%ssp\n",
1519 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1521 /* Pre-compute value to be used as the new frame pointer. */
1523 fprintf (asm_file, "\tadds %ssp,%sr31,%sr31\n",
1524 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1526 /* Preserve registers. */
1528 for (i = 1; i < 32; i++)
1529 if (regs_ever_live[i] && ! call_used_regs[i])
1530 fprintf (asm_file, "\tst.l %s%s,%d(%sr31)\n",
1531 i860_reg_prefix, reg_names[i],
1532 must_preserve_bytes + (4 * preserved_so_far++),
1535 for (i = 32; i < 64; i++)
1536 if (regs_ever_live[i] && ! call_used_regs[i])
1537 fprintf (asm_file, "\tfst.l %s%s,%d(%sr31)\n",
1538 i860_reg_prefix, reg_names[i],
1539 must_preserve_bytes + (4 * preserved_so_far++),
1542 /* Actually set the new value of the frame pointer. */
1544 fprintf (asm_file, "\tmov %sr31,%sfp\n",
1545 i860_reg_prefix, i860_reg_prefix);
1549 /* Adjust the stack pointer. */
1551 fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
1552 total_fsize, i860_reg_prefix, i860_reg_prefix);
1554 /* Save the caller's frame pointer. */
1556 fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n",
1557 i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
1559 /* Save the return address. */
1561 if (must_preserve_r1)
1562 fprintf (asm_file, "\tst.l %sr1,%d(%ssp)\n",
1563 i860_reg_prefix, frame_lower_bytes + 4, i860_reg_prefix);
1565 /* Preserve registers. */
1567 for (i = 1; i < 32; i++)
1568 if (regs_ever_live[i] && ! call_used_regs[i])
1569 fprintf (asm_file, "\tst.l %s%s,%d(%ssp)\n",
1570 i860_reg_prefix, reg_names[i],
1571 frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
1574 for (i = 32; i < 64; i++)
1575 if (regs_ever_live[i] && ! call_used_regs[i])
1576 fprintf (asm_file, "\tfst.l %s%s,%d(%ssp)\n",
1577 i860_reg_prefix, reg_names[i],
1578 frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
1581 /* Setup the new frame pointer. */
1583 fprintf (asm_file, "\tadds %d,%ssp,%sfp\n",
1584 frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
1586 #endif /* defined(I860_STRICT_ABI_PROLOGUES) */
1588 #ifdef ASM_OUTPUT_PROLOGUE_SUFFIX
1589 ASM_OUTPUT_PROLOGUE_SUFFIX (asm_file);
1590 #endif /* defined(ASM_OUTPUT_PROLOGUE_SUFFIX) */
1593 /* This function generates the assembly code for function exit.
1595 ASM_FILE is a stdio stream to output the code to.
1596 SIZE is an int: how many units of temporary storage to allocate.
1598 The function epilogue should not depend on the current stack pointer!
1599 It should use the frame pointer only. This is mandatory because
1600 of alloca; we also take advantage of it to omit stack adjustments
1603 Note that when we go to restore the preserved register values we must
1604 not try to address their slots by using offsets from the stack pointer.
1605 That's because the stack pointer may have been moved during the function
1606 execution due to a call to alloca(). Rather, we must restore all
1607 preserved registers via offsets from the frame pointer value.
1609 Note also that when the current frame is being "popped" (by adjusting
1610 the value of the stack pointer) on function exit, we must (for the
1611 sake of alloca) set the new value of the stack pointer based upon
1612 the current value of the frame pointer. We can't just add what we
1613 believe to be the (static) frame size to the stack pointer because
1614 if we did that, and alloca() had been called during this function,
1615 we would end up returning *without* having fully deallocated all of
1616 the space grabbed by alloca. If that happened, and a function
1617 containing one or more alloca() calls was called over and over again,
1618 then the stack would grow without limit!
1620 Finally note that the epilogues generated here are completely ABI
1621 compliant. They go out of their way to insure that the value in
1622 the frame pointer register is never less than the value in the stack
1623 pointer register. It's not clear why this relationship needs to be
1624 maintained at all times, but maintaining it only costs one extra
1625 instruction, so what the hell. */
1627 /* This corresponds to a version 4 TDESC structure. Lower numbered
1628 versions successively omit the last word of the structure. We
1629 don't try to handle version 5 here. */
1631 typedef struct TDESC_flags {
1634 int callable_block:1;
1636 int fregs:6; /* fp regs 2-7 */
1637 int iregs:16; /* regs 0-15 */
1640 typedef struct TDESC {
1642 int integer_reg_offset; /* same as must_preserve_bytes */
1643 int floating_point_reg_offset;
1644 unsigned int positive_frame_size; /* same as frame_upper_bytes */
1645 unsigned int negative_frame_size; /* same as frame_lower_bytes */
1649 i860_output_function_epilogue (FILE *asm_file, HOST_WIDE_INT local_bytes)
1651 register HOST_WIDE_INT frame_upper_bytes;
1652 register HOST_WIDE_INT frame_lower_bytes;
1653 register HOST_WIDE_INT preserved_reg_bytes = 0;
1654 register unsigned i;
1655 register unsigned restored_so_far = 0;
1656 register unsigned int_restored;
1657 register unsigned mask;
1658 unsigned intflags=0;
1659 register TDESC_flags *flags = (TDESC_flags *) &intflags;
1660 #ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry */
1661 const char *long_op = integer_asm_op (4, TRUE);
1665 flags->reg_packing = 1;
1666 flags->iregs = 8; /* old fp always gets saved */
1668 /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1670 frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1672 /* Count the number of registers that were preserved in the prologue.
1673 Ignore r0. It is never preserved. */
1675 for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
1677 if (regs_ever_live[i] && ! call_used_regs[i])
1678 preserved_reg_bytes += 4;
1681 /* The upper part of each frame will contain only saved fp,
1682 the saved r1, and stack slots for all of the other "preserved"
1683 registers that we find we will need to save & restore. */
1685 frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
1687 /* Round-up frame_upper_bytes so that t is a multiple of 16. */
1690 = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1692 /* Restore all of the "preserved" registers that need restoring. */
1696 for (i = 1; i < 32; i++, mask<<=1)
1697 if (regs_ever_live[i] && ! call_used_regs[i]) {
1698 fprintf (asm_file, "\tld.l %d(%sfp),%s%s\n",
1699 must_preserve_bytes + (4 * restored_so_far++),
1700 i860_reg_prefix, i860_reg_prefix, reg_names[i]);
1701 if (i > 3 && i < 16)
1702 flags->iregs |= mask;
1705 int_restored = restored_so_far;
1708 for (i = 32; i < 64; i++) {
1709 if (regs_ever_live[i] && ! call_used_regs[i]) {
1710 fprintf (asm_file, "\tfld.l %d(%sfp),%s%s\n",
1711 must_preserve_bytes + (4 * restored_so_far++),
1712 i860_reg_prefix, i860_reg_prefix, reg_names[i]);
1713 if (i > 33 && i < 40)
1714 flags->fregs |= mask;
1716 if (i > 33 && i < 40)
1720 /* Get the value we plan to use to restore the stack pointer into r31. */
1722 fprintf (asm_file, "\tadds " HOST_WIDE_INT_PRINT_DEC ",%sfp,%sr31\n",
1723 frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
1725 /* Restore the return address and the old frame pointer. */
1727 if (must_preserve_r1) {
1728 fprintf (asm_file, "\tld.l 4(%sfp),%sr1\n",
1729 i860_reg_prefix, i860_reg_prefix);
1733 fprintf (asm_file, "\tld.l 0(%sfp),%sfp\n",
1734 i860_reg_prefix, i860_reg_prefix);
1736 /* Return and restore the old stack pointer value. */
1738 fprintf (asm_file, "\tbri %sr1\n\tmov %sr31,%ssp\n",
1739 i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1741 #ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry. */
1742 if (! frame_lower_bytes) {
1744 if (! frame_upper_bytes) {
1746 if (restored_so_far == int_restored) /* No FP saves. */
1750 assemble_name(asm_file,current_function_original_name);
1751 fputs(".TDESC:\n", asm_file);
1752 fprintf(asm_file, "%s 0x%0x\n", long_op, intflags);
1753 fprintf(asm_file, "%s %d\n", long_op,
1754 int_restored ? must_preserve_bytes : 0);
1755 if (flags->version > 1) {
1756 fprintf(asm_file, "%s %d\n", long_op,
1757 (restored_so_far == int_restored) ? 0 : must_preserve_bytes +
1758 (4 * int_restored));
1759 if (flags->version > 2) {
1760 fprintf(asm_file, "%s %d\n", long_op, frame_upper_bytes);
1761 if (flags->version > 3)
1762 fprintf(asm_file, "%s %d\n", long_op, frame_lower_bytes);
1766 fprintf(asm_file, "%s ", long_op);
1767 assemble_name(asm_file, current_function_original_name);
1768 fprintf(asm_file, "\n%s ", long_op);
1769 assemble_name(asm_file, current_function_original_name);
1770 fputs(".TDESC\n", asm_file);
1776 /* Expand a library call to __builtin_saveregs. */
1779 i860_saveregs (void)
1781 rtx fn = gen_rtx_SYMBOL_REF (Pmode, "__builtin_saveregs");
1782 rtx save = gen_reg_rtx (Pmode);
1783 rtx valreg = LIBCALL_VALUE (Pmode);
1786 /* The return value register overlaps the first argument register.
1787 Save and restore it around the call. */
1788 emit_move_insn (save, valreg);
1789 ret = emit_library_call_value (fn, NULL_RTX, 1, Pmode, 0);
1790 if (GET_CODE (ret) != REG || REGNO (ret) < FIRST_PSEUDO_REGISTER)
1791 ret = copy_to_reg (ret);
1792 emit_move_insn (valreg, save);
1797 /* Create the va_list data type.
1798 The SVR4 ABI requires the following structure:
1800 unsigned long ireg_used;
1801 unsigned long freg_used;
1806 Otherwise, this structure is used:
1810 unsigned long ireg_used;
1811 unsigned long freg_used;
1814 The tree representing the va_list declaration is returned. */
1817 i860_build_builtin_va_list (void)
1819 tree f_gpr, f_fpr, f_mem, f_sav, record, type_decl;
1821 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
1822 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
1824 f_gpr = build_decl (FIELD_DECL, get_identifier ("__ireg_used"),
1825 unsigned_type_node);
1826 f_fpr = build_decl (FIELD_DECL, get_identifier ("__freg_used"),
1827 unsigned_type_node);
1828 f_sav = build_decl (FIELD_DECL, get_identifier ("__reg_base"),
1830 f_mem = build_decl (FIELD_DECL, get_identifier ("__mem_ptr"),
1833 DECL_FIELD_CONTEXT (f_gpr) = record;
1834 DECL_FIELD_CONTEXT (f_fpr) = record;
1835 DECL_FIELD_CONTEXT (f_sav) = record;
1836 DECL_FIELD_CONTEXT (f_mem) = record;
1838 TREE_CHAIN (record) = type_decl;
1839 TYPE_NAME (record) = type_decl;
1841 #ifdef I860_SVR4_VA_LIST
1842 TYPE_FIELDS (record) = f_gpr;
1843 TREE_CHAIN (f_gpr) = f_fpr;
1844 TREE_CHAIN (f_fpr) = f_sav;
1845 TREE_CHAIN (f_sav) = f_mem;
1847 TYPE_FIELDS (record) = f_sav;
1848 TREE_CHAIN (f_sav) = f_mem;
1849 TREE_CHAIN (f_mem) = f_gpr;
1850 TREE_CHAIN (f_gpr) = f_fpr;
1853 layout_type (record);
1857 /* Initialize the va_list structure. */
1860 i860_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
1863 tree f_gpr, f_fpr, f_mem, f_sav;
1864 tree gpr, fpr, mem, sav;
1866 saveregs = make_tree (ptr_type_node, expand_builtin_saveregs ());
1868 #ifdef I860_SVR4_VA_LIST
1869 f_gpr = TYPE_FIELDS (va_list_type_node);
1870 f_fpr = TREE_CHAIN (f_gpr);
1871 f_sav = TREE_CHAIN (f_fpr);
1872 f_mem = TREE_CHAIN (f_sav);
1874 f_sav = TYPE_FIELDS (va_list_type_node);
1875 f_mem = TREE_CHAIN (f_sav);
1876 f_gpr = TREE_CHAIN (f_mem);
1877 f_fpr = TREE_CHAIN (f_gpr);
1880 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
1881 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
1882 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
1883 mem = build (COMPONENT_REF, TREE_TYPE (f_mem), valist, f_mem);
1885 /* Initialize the `mem_ptr' field to the address of the first anonymous
1887 t = make_tree (TREE_TYPE (mem), virtual_incoming_args_rtx);
1888 off = INTVAL (current_function_arg_offset_rtx);
1889 off = off < 0 ? 0 : off;
1890 t = build (PLUS_EXPR, TREE_TYPE (mem), t, build_int_2 (off, 0));
1891 t = build (MODIFY_EXPR, TREE_TYPE (mem), mem, t);
1892 TREE_SIDE_EFFECTS (t) = 1;
1893 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1895 /* Initialize the `ireg_used' field. */
1896 t = build_int_2 (current_function_args_info.ints / UNITS_PER_WORD, 0);
1897 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
1898 TREE_SIDE_EFFECTS (t) = 1;
1899 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1901 /* Initialize the `freg_used' field. */
1902 t = build_int_2 (current_function_args_info.floats / UNITS_PER_WORD, 0);
1903 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t);
1904 TREE_SIDE_EFFECTS (t) = 1;
1905 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1907 /* Initialize the `reg_base' field. */
1908 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, saveregs);
1909 TREE_SIDE_EFFECTS (t) = 1;
1910 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1913 #define NUM_PARM_FREGS 8
1914 #define NUM_PARM_IREGS 12
1915 #ifdef I860_SVR4_VA_LIST
1916 #define FREG_OFFSET 0
1917 #define IREG_OFFSET (NUM_PARM_FREGS * UNITS_PER_WORD)
1919 #define FREG_OFFSET (NUM_PARM_IREGS * UNITS_PER_WORD)
1920 #define IREG_OFFSET 0
1923 /* Update the VALIST structure as necessary for an
1924 argument of the given TYPE, and return the argument. */
1927 i860_va_arg (tree valist, tree type)
1929 tree f_gpr, f_fpr, f_mem, f_sav;
1930 tree gpr, fpr, mem, sav, reg, t, u;
1931 int size, n_reg, sav_ofs, sav_scale, max_reg;
1932 rtx lab_false, lab_over, addr_rtx, r;
1934 #ifdef I860_SVR4_VA_LIST
1935 f_gpr = TYPE_FIELDS (va_list_type_node);
1936 f_fpr = TREE_CHAIN (f_gpr);
1937 f_sav = TREE_CHAIN (f_fpr);
1938 f_mem = TREE_CHAIN (f_sav);
1940 f_sav = TYPE_FIELDS (va_list_type_node);
1941 f_mem = TREE_CHAIN (f_sav);
1942 f_gpr = TREE_CHAIN (f_mem);
1943 f_fpr = TREE_CHAIN (f_gpr);
1946 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
1947 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
1948 mem = build (COMPONENT_REF, TREE_TYPE (f_mem), valist, f_mem);
1949 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
1951 size = int_size_in_bytes (type);
1953 if (AGGREGATE_TYPE_P (type))
1955 /* Aggregates are passed on the stack. */
1956 HOST_WIDE_INT align;
1958 align = TYPE_ALIGN (type);
1959 if (align < BITS_PER_WORD)
1960 align = BITS_PER_WORD;
1961 align /= BITS_PER_UNIT;
1963 addr_rtx = gen_reg_rtx (Pmode);
1964 t = build (PLUS_EXPR, ptr_type_node, mem, build_int_2 (align - 1, 0));
1965 t = build (BIT_AND_EXPR, ptr_type_node, t, build_int_2 (-align, -1));
1966 r = expand_expr (t, addr_rtx, VOIDmode /* Pmode */, EXPAND_NORMAL);
1968 emit_move_insn (addr_rtx, r);
1970 t = fold (build (PLUS_EXPR, ptr_type_node,
1971 make_tree (ptr_type_node, addr_rtx),
1972 build_int_2 (size, 0)));
1973 t = build (MODIFY_EXPR, ptr_type_node, mem, t);
1974 TREE_SIDE_EFFECTS (t) = 1;
1975 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1979 else if (FLOAT_TYPE_P (type) || (INTEGRAL_TYPE_P (type) && size == 8))
1981 /* Floats and long longs are passed in the floating-point registers. */
1983 n_reg = size / UNITS_PER_WORD;
1984 sav_ofs = FREG_OFFSET;
1985 sav_scale = UNITS_PER_WORD;
1986 max_reg = NUM_PARM_FREGS;
1990 /* Everything else is passed in general registers. */
1992 n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1993 sav_ofs = IREG_OFFSET;
1994 sav_scale = UNITS_PER_WORD;
1995 max_reg = NUM_PARM_IREGS;
2000 /* The value was passed in a register, so read it from the register
2001 save area initialized by __builtin_saveregs. */
2003 lab_false = gen_label_rtx ();
2004 lab_over = gen_label_rtx ();
2005 addr_rtx = gen_reg_rtx (Pmode);
2007 emit_cmp_and_jump_insns (expand_expr (reg, NULL_RTX, Pmode, EXPAND_NORMAL),
2008 GEN_INT (max_reg - n_reg),
2009 GT, const1_rtx, Pmode, 0, lab_false);
2012 t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
2016 u = build (MULT_EXPR, long_integer_type_node,
2017 reg, build_int_2 (sav_scale, 0));
2018 TREE_SIDE_EFFECTS (u) = 1;
2020 t = build (PLUS_EXPR, ptr_type_node, t, u);
2021 TREE_SIDE_EFFECTS (t) = 1;
2023 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
2025 emit_move_insn (addr_rtx, r);
2027 emit_jump_insn (gen_jump (lab_over));
2029 emit_label (lab_false);
2031 /* The value was passed in memory, so read it from the overflow area. */
2033 t = save_expr (mem);
2034 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
2036 emit_move_insn (addr_rtx, r);
2038 t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
2039 t = build (MODIFY_EXPR, TREE_TYPE (mem), mem, t);
2040 TREE_SIDE_EFFECTS (t) = 1;
2041 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2043 emit_label (lab_over);
2045 /* Increment either the ireg_used or freg_used field. */
2047 u = build (PREINCREMENT_EXPR, TREE_TYPE (reg), reg, build_int_2 (n_reg, 0));
2048 TREE_SIDE_EFFECTS (u) = 1;
2049 expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
2054 /* Compute a (partial) cost for rtx X. Return true if the complete
2055 cost has been computed, and false if subexpressions should be
2056 scanned. In either case, *TOTAL contains the cost result. */
2059 i860_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total)
2064 if (INTVAL (x) == 0)
2066 else if (INTVAL (x) < 0x2000 && INTVAL (x) >= -0x2000)
2083 i860_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
2085 fprintf (stream, ".%s%ld:\n", prefix, labelno);
2089 i860_file_start (void)
2091 output_file_directive (asm_out_file, main_input_filename);
2092 fprintf (asm_out_file, "\t.version\t\"01.01\"\n");
2096 i860_init_libfuncs (void)
2098 set_optab_libfunc (sdiv_optab, SImode, "*.div");
2099 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
2100 set_optab_libfunc (smod_optab, SImode, "*.rem");
2101 set_optab_libfunc (umod_optab, SImode, "*.urem");
2105 i860_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
2106 int incoming ATTRIBUTE_UNUSED)
2108 return gen_rtx_REG (Pmode, I860_STRUCT_VALUE_REGNUM);
2111 /* Initialize the GCC target structure. */
2112 #undef TARGET_RTX_COSTS
2113 #define TARGET_RTX_COSTS i860_rtx_costs
2115 #undef TARGET_ASM_INTERNAL_LABEL
2116 #define TARGET_ASM_INTERNAL_LABEL i860_internal_label
2118 #undef TARGET_ASM_FUNCTION_PROLOGUE
2119 #define TARGET_ASM_FUNCTION_PROLOGUE i860_output_function_prologue
2121 #undef TARGET_ASM_FUNCTION_EPILOGUE
2122 #define TARGET_ASM_FUNCTION_EPILOGUE i860_output_function_epilogue
2124 #undef TARGET_INIT_LIBFUNCS
2125 #define TARGET_INIT_LIBFUNCS i860_init_libfuncs
2127 #undef TARGET_BUILD_BUILTIN_VA_LIST
2128 #define TARGET_BUILD_BUILTIN_VA_LIST i860_build_builtin_va_list
2130 #undef TARGET_STRUCT_VALUE_RTX
2131 #define TARGET_STRUCT_VALUE_RTX i860_struct_value_rtx
2133 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
2134 #define TARGET_EXPAND_BUILTIN_SAVEREGS i860_saveregs
2136 struct gcc_target targetm = TARGET_INITIALIZER;