1 ;; GCC machine description for SSE instructions
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;; 16 byte integral modes handled by SSE, minus TImode, which gets
24 ;; special-cased for TARGET_64BIT.
25 (define_mode_macro SSEMODEI [V16QI V8HI V4SI V2DI])
27 ;; All 16-byte vector modes handled by SSE
28 (define_mode_macro SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF])
31 (define_mode_macro SSEMODE12 [V16QI V8HI])
32 (define_mode_macro SSEMODE24 [V8HI V4SI])
33 (define_mode_macro SSEMODE124 [V16QI V8HI V4SI])
34 (define_mode_macro SSEMODE248 [V8HI V4SI V2DI])
36 ;; Mapping from integer vector mode to mnemonic suffix
37 (define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")])
39 ;; Patterns whose name begins with "sse{,2,3}_" are invoked by intrinsics.
41 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
45 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
47 ;; All of these patterns are enabled for SSE1 as well as SSE2.
48 ;; This is essential for maintaining stable calling conventions.
50 (define_expand "mov<mode>"
51 [(set (match_operand:SSEMODEI 0 "nonimmediate_operand" "")
52 (match_operand:SSEMODEI 1 "nonimmediate_operand" ""))]
55 ix86_expand_vector_move (<MODE>mode, operands);
59 (define_insn "*mov<mode>_internal"
60 [(set (match_operand:SSEMODEI 0 "nonimmediate_operand" "=x,x ,m")
61 (match_operand:SSEMODEI 1 "vector_move_operand" "C ,xm,x"))]
62 "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
64 switch (which_alternative)
67 if (get_attr_mode (insn) == MODE_V4SF)
68 return "xorps\t%0, %0";
70 return "pxor\t%0, %0";
73 if (get_attr_mode (insn) == MODE_V4SF)
74 return "movaps\t{%1, %0|%0, %1}";
76 return "movdqa\t{%1, %0|%0, %1}";
81 [(set_attr "type" "sselog1,ssemov,ssemov")
83 (cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0))
86 (eq_attr "alternative" "0,1")
88 (ne (symbol_ref "optimize_size")
92 (eq_attr "alternative" "2")
94 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
96 (ne (symbol_ref "optimize_size")
100 (const_string "TI")))])
102 (define_expand "movv4sf"
103 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
104 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
107 ix86_expand_vector_move (V4SFmode, operands);
111 (define_insn "*movv4sf_internal"
112 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
113 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
117 movaps\t{%1, %0|%0, %1}
118 movaps\t{%1, %0|%0, %1}"
119 [(set_attr "type" "sselog1,ssemov,ssemov")
120 (set_attr "mode" "V4SF")])
123 [(set (match_operand:V4SF 0 "register_operand" "")
124 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
125 "TARGET_SSE && reload_completed"
128 rtx x = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
129 emit_insn (gen_sse_loadss (operands[0], x));
133 (define_expand "movv2df"
134 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
135 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
138 ix86_expand_vector_move (V2DFmode, operands);
142 (define_insn "*movv2df_internal"
143 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
144 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
145 "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
147 switch (which_alternative)
150 if (get_attr_mode (insn) == MODE_V4SF)
151 return "xorps\t%0, %0";
153 return "xorpd\t%0, %0";
156 if (get_attr_mode (insn) == MODE_V4SF)
157 return "movaps\t{%1, %0|%0, %1}";
159 return "movapd\t{%1, %0|%0, %1}";
164 [(set_attr "type" "sselog1,ssemov,ssemov")
166 (cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0))
167 (const_string "V4SF")
168 (eq_attr "alternative" "0,1")
170 (ne (symbol_ref "optimize_size")
172 (const_string "V4SF")
173 (const_string "V2DF"))
174 (eq_attr "alternative" "2")
176 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
178 (ne (symbol_ref "optimize_size")
180 (const_string "V4SF")
181 (const_string "V2DF"))]
182 (const_string "V2DF")))])
185 [(set (match_operand:V2DF 0 "register_operand" "")
186 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
187 "TARGET_SSE2 && reload_completed"
190 rtx x = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
191 emit_insn (gen_sse2_loadsd (operands[0], x));
195 (define_expand "movmisalign<mode>"
196 [(set (match_operand:SSEMODE 0 "nonimmediate_operand" "")
197 (match_operand:SSEMODE 1 "nonimmediate_operand" ""))]
200 ix86_expand_vector_move_misalign (<MODE>mode, operands);
204 (define_insn "sse_movups"
205 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
206 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
208 "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
209 "movups\t{%1, %0|%0, %1}"
210 [(set_attr "type" "ssemov")
211 (set_attr "mode" "V2DF")])
213 (define_insn "sse2_movupd"
214 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
215 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
217 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
218 "movupd\t{%1, %0|%0, %1}"
219 [(set_attr "type" "ssemov")
220 (set_attr "mode" "V2DF")])
222 (define_insn "sse2_movdqu"
223 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
224 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
226 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
227 "movdqu\t{%1, %0|%0, %1}"
228 [(set_attr "type" "ssemov")
229 (set_attr "mode" "TI")])
231 (define_insn "sse_movntv4sf"
232 [(set (match_operand:V4SF 0 "memory_operand" "=m")
233 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
236 "movntps\t{%1, %0|%0, %1}"
237 [(set_attr "type" "ssemov")
238 (set_attr "mode" "V4SF")])
240 (define_insn "sse2_movntv2df"
241 [(set (match_operand:V2DF 0 "memory_operand" "=m")
242 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
245 "movntpd\t{%1, %0|%0, %1}"
246 [(set_attr "type" "ssecvt")
247 (set_attr "mode" "V2DF")])
249 (define_insn "sse2_movntv2di"
250 [(set (match_operand:V2DI 0 "memory_operand" "=m")
251 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
254 "movntdq\t{%1, %0|%0, %1}"
255 [(set_attr "type" "ssecvt")
256 (set_attr "mode" "TI")])
258 (define_insn "sse2_movntsi"
259 [(set (match_operand:SI 0 "memory_operand" "=m")
260 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
263 "movnti\t{%1, %0|%0, %1}"
264 [(set_attr "type" "ssecvt")
265 (set_attr "mode" "V2DF")])
267 (define_insn "sse3_lddqu"
268 [(set (match_operand:V16QI 0 "register_operand" "=x")
269 (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
272 "lddqu\t{%1, %0|%0, %1}"
273 [(set_attr "type" "ssecvt")
274 (set_attr "mode" "TI")])
276 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
278 ;; Parallel single-precision floating point arithmetic
280 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
282 (define_expand "negv4sf2"
283 [(set (match_operand:V4SF 0 "register_operand" "")
284 (neg:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
286 "ix86_expand_fp_absneg_operator (NEG, V4SFmode, operands); DONE;")
288 (define_expand "absv4sf2"
289 [(set (match_operand:V4SF 0 "register_operand" "")
290 (abs:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
292 "ix86_expand_fp_absneg_operator (ABS, V4SFmode, operands); DONE;")
294 (define_expand "addv4sf3"
295 [(set (match_operand:V4SF 0 "register_operand" "")
296 (plus:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
297 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
299 "ix86_fixup_binary_operands_no_copy (PLUS, V4SFmode, operands);")
301 (define_insn "*addv4sf3"
302 [(set (match_operand:V4SF 0 "register_operand" "=x")
303 (plus:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
304 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
305 "TARGET_SSE && ix86_binary_operator_ok (PLUS, V4SFmode, operands)"
306 "addps\t{%2, %0|%0, %2}"
307 [(set_attr "type" "sseadd")
308 (set_attr "mode" "V4SF")])
310 (define_insn "sse_vmaddv4sf3"
311 [(set (match_operand:V4SF 0 "register_operand" "=x")
313 (plus:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
314 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
317 "TARGET_SSE && ix86_binary_operator_ok (PLUS, V4SFmode, operands)"
318 "addss\t{%2, %0|%0, %2}"
319 [(set_attr "type" "sseadd")
320 (set_attr "mode" "SF")])
322 (define_expand "subv4sf3"
323 [(set (match_operand:V4SF 0 "register_operand" "")
324 (minus:V4SF (match_operand:V4SF 1 "register_operand" "")
325 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
327 "ix86_fixup_binary_operands_no_copy (MINUS, V4SFmode, operands);")
329 (define_insn "*subv4sf3"
330 [(set (match_operand:V4SF 0 "register_operand" "=x")
331 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
332 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
334 "subps\t{%2, %0|%0, %2}"
335 [(set_attr "type" "sseadd")
336 (set_attr "mode" "V4SF")])
338 (define_insn "sse_vmsubv4sf3"
339 [(set (match_operand:V4SF 0 "register_operand" "=x")
341 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
342 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
346 "subss\t{%2, %0|%0, %2}"
347 [(set_attr "type" "sseadd")
348 (set_attr "mode" "SF")])
350 (define_expand "mulv4sf3"
351 [(set (match_operand:V4SF 0 "register_operand" "")
352 (mult:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
353 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
355 "ix86_fixup_binary_operands_no_copy (MULT, V4SFmode, operands);")
357 (define_insn "*mulv4sf3"
358 [(set (match_operand:V4SF 0 "register_operand" "=x")
359 (mult:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
360 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
361 "TARGET_SSE && ix86_binary_operator_ok (MULT, V4SFmode, operands)"
362 "mulps\t{%2, %0|%0, %2}"
363 [(set_attr "type" "ssemul")
364 (set_attr "mode" "V4SF")])
366 (define_insn "sse_vmmulv4sf3"
367 [(set (match_operand:V4SF 0 "register_operand" "=x")
369 (mult:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
370 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
373 "TARGET_SSE && ix86_binary_operator_ok (MULT, V4SFmode, operands)"
374 "mulss\t{%2, %0|%0, %2}"
375 [(set_attr "type" "ssemul")
376 (set_attr "mode" "SF")])
378 (define_expand "divv4sf3"
379 [(set (match_operand:V4SF 0 "register_operand" "")
380 (div:V4SF (match_operand:V4SF 1 "register_operand" "")
381 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
383 "ix86_fixup_binary_operands_no_copy (DIV, V4SFmode, operands);")
385 (define_insn "*divv4sf3"
386 [(set (match_operand:V4SF 0 "register_operand" "=x")
387 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
388 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
390 "divps\t{%2, %0|%0, %2}"
391 [(set_attr "type" "ssediv")
392 (set_attr "mode" "V4SF")])
394 (define_insn "sse_vmdivv4sf3"
395 [(set (match_operand:V4SF 0 "register_operand" "=x")
397 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
398 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
402 "divss\t{%2, %0|%0, %2}"
403 [(set_attr "type" "ssediv")
404 (set_attr "mode" "SF")])
406 (define_insn "sse_rcpv4sf2"
407 [(set (match_operand:V4SF 0 "register_operand" "=x")
409 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
411 "rcpps\t{%1, %0|%0, %1}"
412 [(set_attr "type" "sse")
413 (set_attr "mode" "V4SF")])
415 (define_insn "sse_vmrcpv4sf2"
416 [(set (match_operand:V4SF 0 "register_operand" "=x")
418 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
420 (match_operand:V4SF 2 "register_operand" "0")
423 "rcpss\t{%1, %0|%0, %1}"
424 [(set_attr "type" "sse")
425 (set_attr "mode" "SF")])
427 (define_insn "sse_rsqrtv4sf2"
428 [(set (match_operand:V4SF 0 "register_operand" "=x")
430 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
432 "rsqrtps\t{%1, %0|%0, %1}"
433 [(set_attr "type" "sse")
434 (set_attr "mode" "V4SF")])
436 (define_insn "sse_vmrsqrtv4sf2"
437 [(set (match_operand:V4SF 0 "register_operand" "=x")
439 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
441 (match_operand:V4SF 2 "register_operand" "0")
444 "rsqrtss\t{%1, %0|%0, %1}"
445 [(set_attr "type" "sse")
446 (set_attr "mode" "SF")])
448 (define_insn "sqrtv4sf2"
449 [(set (match_operand:V4SF 0 "register_operand" "=x")
450 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
452 "sqrtps\t{%1, %0|%0, %1}"
453 [(set_attr "type" "sse")
454 (set_attr "mode" "V4SF")])
456 (define_insn "sse_vmsqrtv4sf2"
457 [(set (match_operand:V4SF 0 "register_operand" "=x")
459 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
460 (match_operand:V4SF 2 "register_operand" "0")
463 "sqrtss\t{%1, %0|%0, %1}"
464 [(set_attr "type" "sse")
465 (set_attr "mode" "SF")])
467 (define_expand "smaxv4sf3"
468 [(set (match_operand:V4SF 0 "register_operand" "")
469 (smax:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
470 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
472 "ix86_fixup_binary_operands_no_copy (SMAX, V4SFmode, operands);")
474 (define_insn "*smaxv4sf3"
475 [(set (match_operand:V4SF 0 "register_operand" "=x")
476 (smax:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
477 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
478 "TARGET_SSE && ix86_binary_operator_ok (SMAX, V4SFmode, operands)"
479 "maxps\t{%2, %0|%0, %2}"
480 [(set_attr "type" "sse")
481 (set_attr "mode" "V4SF")])
483 (define_insn "sse_vmsmaxv4sf3"
484 [(set (match_operand:V4SF 0 "register_operand" "=x")
486 (smax:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
487 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
490 "TARGET_SSE && ix86_binary_operator_ok (SMAX, V4SFmode, operands)"
491 "maxss\t{%2, %0|%0, %2}"
492 [(set_attr "type" "sse")
493 (set_attr "mode" "SF")])
495 (define_expand "sminv4sf3"
496 [(set (match_operand:V4SF 0 "register_operand" "")
497 (smin:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
498 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
500 "ix86_fixup_binary_operands_no_copy (SMIN, V4SFmode, operands);")
502 (define_insn "*sminv4sf3"
503 [(set (match_operand:V4SF 0 "register_operand" "=x")
504 (smin:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
505 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
506 "TARGET_SSE && ix86_binary_operator_ok (SMIN, V4SFmode, operands)"
507 "minps\t{%2, %0|%0, %2}"
508 [(set_attr "type" "sse")
509 (set_attr "mode" "V4SF")])
511 (define_insn "sse_vmsminv4sf3"
512 [(set (match_operand:V4SF 0 "register_operand" "=x")
514 (smin:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
515 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
518 "TARGET_SSE && ix86_binary_operator_ok (SMIN, V4SFmode, operands)"
519 "minss\t{%2, %0|%0, %2}"
520 [(set_attr "type" "sse")
521 (set_attr "mode" "SF")])
523 (define_insn "sse3_addsubv4sf3"
524 [(set (match_operand:V4SF 0 "register_operand" "=x")
527 (match_operand:V4SF 1 "register_operand" "0")
528 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
529 (minus:V4SF (match_dup 1) (match_dup 2))
532 "addsubps\t{%2, %0|%0, %2}"
533 [(set_attr "type" "sseadd")
534 (set_attr "mode" "V4SF")])
536 (define_insn "sse3_haddv4sf3"
537 [(set (match_operand:V4SF 0 "register_operand" "=x")
542 (match_operand:V4SF 1 "register_operand" "0")
543 (parallel [(const_int 0)]))
544 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
546 (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
547 (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
551 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
552 (parallel [(const_int 0)]))
553 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
555 (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
556 (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
558 "haddps\t{%2, %0|%0, %2}"
559 [(set_attr "type" "sseadd")
560 (set_attr "mode" "V4SF")])
562 (define_insn "sse3_hsubv4sf3"
563 [(set (match_operand:V4SF 0 "register_operand" "=x")
568 (match_operand:V4SF 1 "register_operand" "0")
569 (parallel [(const_int 0)]))
570 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
572 (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
573 (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
577 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
578 (parallel [(const_int 0)]))
579 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
581 (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
582 (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
584 "hsubps\t{%2, %0|%0, %2}"
585 [(set_attr "type" "sseadd")
586 (set_attr "mode" "V4SF")])
588 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
590 ;; Parallel single-precision floating point comparisons
592 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
594 (define_insn "sse_maskcmpv4sf3"
595 [(set (match_operand:V4SF 0 "register_operand" "=x")
596 (match_operator:V4SF 3 "sse_comparison_operator"
597 [(match_operand:V4SF 1 "register_operand" "0")
598 (match_operand:V4SF 2 "nonimmediate_operand" "xm")]))]
600 "cmp%D3ps\t{%2, %0|%0, %2}"
601 [(set_attr "type" "ssecmp")
602 (set_attr "mode" "V4SF")])
604 (define_insn "sse_vmmaskcmpv4sf3"
605 [(set (match_operand:V4SF 0 "register_operand" "=x")
607 (match_operator:V4SF 3 "sse_comparison_operator"
608 [(match_operand:V4SF 1 "register_operand" "0")
609 (match_operand:V4SF 2 "register_operand" "x")])
613 "cmp%D3ss\t{%2, %0|%0, %2}"
614 [(set_attr "type" "ssecmp")
615 (set_attr "mode" "SF")])
617 (define_insn "sse_comi"
618 [(set (reg:CCFP FLAGS_REG)
621 (match_operand:V4SF 0 "register_operand" "x")
622 (parallel [(const_int 0)]))
624 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
625 (parallel [(const_int 0)]))))]
627 "comiss\t{%1, %0|%0, %1}"
628 [(set_attr "type" "ssecomi")
629 (set_attr "mode" "SF")])
631 (define_insn "sse_ucomi"
632 [(set (reg:CCFPU FLAGS_REG)
635 (match_operand:V4SF 0 "register_operand" "x")
636 (parallel [(const_int 0)]))
638 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
639 (parallel [(const_int 0)]))))]
641 "ucomiss\t{%1, %0|%0, %1}"
642 [(set_attr "type" "ssecomi")
643 (set_attr "mode" "SF")])
645 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
647 ;; Parallel single-precision floating point logical operations
649 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
651 (define_expand "andv4sf3"
652 [(set (match_operand:V4SF 0 "register_operand" "")
653 (and:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
654 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
656 "ix86_fixup_binary_operands_no_copy (AND, V4SFmode, operands);")
658 (define_insn "*andv4sf3"
659 [(set (match_operand:V4SF 0 "register_operand" "=x")
660 (and:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
661 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
662 "TARGET_SSE && ix86_binary_operator_ok (AND, V4SFmode, operands)"
663 "andps\t{%2, %0|%0, %2}"
664 [(set_attr "type" "sselog")
665 (set_attr "mode" "V4SF")])
667 (define_insn "sse_nandv4sf3"
668 [(set (match_operand:V4SF 0 "register_operand" "=x")
669 (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" "0"))
670 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
672 "andnps\t{%2, %0|%0, %2}"
673 [(set_attr "type" "sselog")
674 (set_attr "mode" "V4SF")])
676 (define_expand "iorv4sf3"
677 [(set (match_operand:V4SF 0 "register_operand" "")
678 (ior:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
679 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
681 "ix86_fixup_binary_operands_no_copy (IOR, V4SFmode, operands);")
683 (define_insn "*iorv4sf3"
684 [(set (match_operand:V4SF 0 "register_operand" "=x")
685 (ior:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
686 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
687 "TARGET_SSE && ix86_binary_operator_ok (IOR, V4SFmode, operands)"
688 "orps\t{%2, %0|%0, %2}"
689 [(set_attr "type" "sselog")
690 (set_attr "mode" "V4SF")])
692 (define_expand "xorv4sf3"
693 [(set (match_operand:V4SF 0 "register_operand" "")
694 (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")
695 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
697 "ix86_fixup_binary_operands_no_copy (XOR, V4SFmode, operands);")
699 (define_insn "*xorv4sf3"
700 [(set (match_operand:V4SF 0 "register_operand" "=x")
701 (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0")
702 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
703 "TARGET_SSE && ix86_binary_operator_ok (XOR, V4SFmode, operands)"
704 "xorps\t{%2, %0|%0, %2}"
705 [(set_attr "type" "sselog")
706 (set_attr "mode" "V4SF")])
708 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
710 ;; Parallel single-precision floating point conversion operations
712 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
714 (define_insn "sse_cvtpi2ps"
715 [(set (match_operand:V4SF 0 "register_operand" "=x")
718 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
719 (match_operand:V4SF 1 "register_operand" "0")
722 "cvtpi2ps\t{%2, %0|%0, %2}"
723 [(set_attr "type" "ssecvt")
724 (set_attr "mode" "V4SF")])
726 (define_insn "sse_cvtps2pi"
727 [(set (match_operand:V2SI 0 "register_operand" "=y")
729 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
731 (parallel [(const_int 0) (const_int 1)])))]
733 "cvtps2pi\t{%1, %0|%0, %1}"
734 [(set_attr "type" "ssecvt")
735 (set_attr "mode" "DI")])
737 (define_insn "sse_cvttps2pi"
738 [(set (match_operand:V2SI 0 "register_operand" "=y")
740 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
741 (parallel [(const_int 0) (const_int 1)])))]
743 "cvttps2pi\t{%1, %0|%0, %1}"
744 [(set_attr "type" "ssecvt")
745 (set_attr "mode" "SF")])
747 (define_insn "sse_cvtsi2ss"
748 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
751 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
752 (match_operand:V4SF 1 "register_operand" "0,0")
755 "cvtsi2ss\t{%2, %0|%0, %2}"
756 [(set_attr "type" "sseicvt")
757 (set_attr "athlon_decode" "vector,double")
758 (set_attr "mode" "SF")])
760 (define_insn "sse_cvtsi2ssq"
761 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
764 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
765 (match_operand:V4SF 1 "register_operand" "0,0")
767 "TARGET_SSE && TARGET_64BIT"
768 "cvtsi2ssq\t{%2, %0|%0, %2}"
769 [(set_attr "type" "sseicvt")
770 (set_attr "athlon_decode" "vector,double")
771 (set_attr "mode" "SF")])
773 (define_insn "sse_cvtss2si"
774 [(set (match_operand:SI 0 "register_operand" "=r,r")
777 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
778 (parallel [(const_int 0)]))]
779 UNSPEC_FIX_NOTRUNC))]
781 "cvtss2si\t{%1, %0|%0, %1}"
782 [(set_attr "type" "sseicvt")
783 (set_attr "athlon_decode" "double,vector")
784 (set_attr "mode" "SI")])
786 (define_insn "sse_cvtss2siq"
787 [(set (match_operand:DI 0 "register_operand" "=r,r")
790 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
791 (parallel [(const_int 0)]))]
792 UNSPEC_FIX_NOTRUNC))]
793 "TARGET_SSE && TARGET_64BIT"
794 "cvtss2siq\t{%1, %0|%0, %1}"
795 [(set_attr "type" "sseicvt")
796 (set_attr "athlon_decode" "double,vector")
797 (set_attr "mode" "DI")])
799 (define_insn "sse_cvttss2si"
800 [(set (match_operand:SI 0 "register_operand" "=r,r")
803 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
804 (parallel [(const_int 0)]))))]
806 "cvttss2si\t{%1, %0|%0, %1}"
807 [(set_attr "type" "sseicvt")
808 (set_attr "athlon_decode" "double,vector")
809 (set_attr "mode" "SI")])
811 (define_insn "sse_cvttss2siq"
812 [(set (match_operand:DI 0 "register_operand" "=r,r")
815 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
816 (parallel [(const_int 0)]))))]
817 "TARGET_SSE && TARGET_64BIT"
818 "cvttss2siq\t{%1, %0|%0, %1}"
819 [(set_attr "type" "sseicvt")
820 (set_attr "athlon_decode" "double,vector")
821 (set_attr "mode" "DI")])
823 (define_insn "sse2_cvtdq2ps"
824 [(set (match_operand:V4SF 0 "register_operand" "=x")
825 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
827 "cvtdq2ps\t{%1, %0|%0, %1}"
828 [(set_attr "type" "ssecvt")
829 (set_attr "mode" "V2DF")])
831 (define_insn "sse2_cvtps2dq"
832 [(set (match_operand:V4SI 0 "register_operand" "=x")
833 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
834 UNSPEC_FIX_NOTRUNC))]
836 "cvtps2dq\t{%1, %0|%0, %1}"
837 [(set_attr "type" "ssecvt")
838 (set_attr "mode" "TI")])
840 (define_insn "sse2_cvttps2dq"
841 [(set (match_operand:V4SI 0 "register_operand" "=x")
842 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
844 "cvttps2dq\t{%1, %0|%0, %1}"
845 [(set_attr "type" "ssecvt")
846 (set_attr "mode" "TI")])
848 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
850 ;; Parallel single-precision floating point element swizzling
852 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
854 (define_insn "sse_movhlps"
855 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
858 (match_operand:V4SF 1 "nonimmediate_operand" " 0,o,x")
859 (match_operand:V4SF 2 "nonimmediate_operand" " x,0,0"))
860 (parallel [(const_int 4)
864 "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
866 movhlps\t{%2, %0|%0, %2}
867 movlps\t{%H1, %0|%0, %H1}
868 movhps\t{%1, %0|%0, %1}"
869 [(set_attr "type" "ssemov")
870 (set_attr "mode" "V4SF,V2SF,V2SF")])
872 (define_insn "sse_movlhps"
873 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
876 (match_operand:V4SF 1 "nonimmediate_operand" " 0,0,0")
877 (match_operand:V4SF 2 "nonimmediate_operand" " x,m,x"))
878 (parallel [(const_int 0)
882 "TARGET_SSE && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
884 movlhps\t{%2, %0|%0, %2}
885 movhps\t{%2, %0|%0, %2}
886 movlps\t{%2, %H0|%H0, %2}"
887 [(set_attr "type" "ssemov")
888 (set_attr "mode" "V4SF,V2SF,V2SF")])
890 (define_insn "sse_unpckhps"
891 [(set (match_operand:V4SF 0 "register_operand" "=x")
894 (match_operand:V4SF 1 "register_operand" "0")
895 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
896 (parallel [(const_int 2) (const_int 6)
897 (const_int 3) (const_int 7)])))]
899 "unpckhps\t{%2, %0|%0, %2}"
900 [(set_attr "type" "sselog")
901 (set_attr "mode" "V4SF")])
903 (define_insn "sse_unpcklps"
904 [(set (match_operand:V4SF 0 "register_operand" "=x")
907 (match_operand:V4SF 1 "register_operand" "0")
908 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
909 (parallel [(const_int 0) (const_int 4)
910 (const_int 1) (const_int 5)])))]
912 "unpcklps\t{%2, %0|%0, %2}"
913 [(set_attr "type" "sselog")
914 (set_attr "mode" "V4SF")])
916 ;; These are modeled with the same vec_concat as the others so that we
917 ;; capture users of shufps that can use the new instructions
918 (define_insn "sse3_movshdup"
919 [(set (match_operand:V4SF 0 "register_operand" "=x")
922 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
924 (parallel [(const_int 1)
929 "movshdup\t{%1, %0|%0, %1}"
930 [(set_attr "type" "sse")
931 (set_attr "mode" "V4SF")])
933 (define_insn "sse3_movsldup"
934 [(set (match_operand:V4SF 0 "register_operand" "=x")
937 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
939 (parallel [(const_int 0)
944 "movsldup\t{%1, %0|%0, %1}"
945 [(set_attr "type" "sse")
946 (set_attr "mode" "V4SF")])
948 (define_expand "sse_shufps"
949 [(match_operand:V4SF 0 "register_operand" "")
950 (match_operand:V4SF 1 "register_operand" "")
951 (match_operand:V4SF 2 "nonimmediate_operand" "")
952 (match_operand:SI 3 "const_int_operand" "")]
955 int mask = INTVAL (operands[3]);
956 emit_insn (gen_sse_shufps_1 (operands[0], operands[1], operands[2],
957 GEN_INT ((mask >> 0) & 3),
958 GEN_INT ((mask >> 2) & 3),
959 GEN_INT (((mask >> 4) & 3) + 4),
960 GEN_INT (((mask >> 6) & 3) + 4)));
964 (define_insn "sse_shufps_1"
965 [(set (match_operand:V4SF 0 "register_operand" "=x")
968 (match_operand:V4SF 1 "register_operand" "0")
969 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
970 (parallel [(match_operand 3 "const_0_to_3_operand" "")
971 (match_operand 4 "const_0_to_3_operand" "")
972 (match_operand 5 "const_4_to_7_operand" "")
973 (match_operand 6 "const_4_to_7_operand" "")])))]
977 mask |= INTVAL (operands[3]) << 0;
978 mask |= INTVAL (operands[4]) << 2;
979 mask |= (INTVAL (operands[5]) - 4) << 4;
980 mask |= (INTVAL (operands[6]) - 4) << 6;
981 operands[3] = GEN_INT (mask);
983 return "shufps\t{%3, %2, %0|%0, %2, %3}";
985 [(set_attr "type" "sselog")
986 (set_attr "mode" "V4SF")])
988 (define_insn "sse_storehps"
989 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
991 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,o")
992 (parallel [(const_int 2) (const_int 3)])))]
995 movhps\t{%1, %0|%0, %1}
996 movhlps\t{%1, %0|%0, %1}
997 movlps\t{%H1, %0|%0, %H1}"
998 [(set_attr "type" "ssemov")
999 (set_attr "mode" "V2SF,V4SF,V2SF")])
1001 (define_insn "sse_loadhps"
1002 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
1005 (match_operand:V4SF 1 "nonimmediate_operand" "0,0,0")
1006 (parallel [(const_int 0) (const_int 1)]))
1007 (match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
1010 movhps\t{%2, %0|%0, %2}
1011 movlhps\t{%2, %0|%0, %2}
1012 movlps\t{%2, %H0|%H0, %2}"
1013 [(set_attr "type" "ssemov")
1014 (set_attr "mode" "V2SF,V4SF,V2SF")])
1016 (define_insn "sse_storelps"
1017 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
1019 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,m")
1020 (parallel [(const_int 0) (const_int 1)])))]
1023 movlps\t{%1, %0|%0, %1}
1024 movaps\t{%1, %0|%0, %1}
1025 movlps\t{%1, %0|%0, %1}"
1026 [(set_attr "type" "ssemov")
1027 (set_attr "mode" "V2SF,V4SF,V2SF")])
1029 (define_insn "sse_loadlps"
1030 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
1032 (match_operand:V2SF 2 "nonimmediate_operand" "0,m,x")
1034 (match_operand:V4SF 1 "nonimmediate_operand" "x,0,0")
1035 (parallel [(const_int 2) (const_int 3)]))))]
1038 shufps\t{$0xe4, %1, %0|%0, %1, 0xe4}
1039 movlps\t{%2, %0|%0, %2}
1040 movlps\t{%2, %0|%0, %2}"
1041 [(set_attr "type" "sselog,ssemov,ssemov")
1042 (set_attr "mode" "V4SF,V2SF,V2SF")])
1044 (define_expand "sse_loadss"
1045 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
1047 (vec_duplicate:V4SF (match_operand:SF 1 "nonimmediate_operand" ""))
1051 "operands[2] = CONST0_RTX (V4SFmode);")
1053 (define_insn "sse_loadlss"
1054 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,Y ,m")
1057 (match_operand:SF 2 "general_operand" " x,m,*r,x*rfF"))
1058 (match_operand:V4SF 1 "vector_move_operand" " 0,C,C ,0")
1062 movss\t{%2, %0|%0, %2}
1063 movss\t{%2, %0|%0, %2}
1064 movd\t{%2, %0|%0, %2}
1066 [(set_attr "type" "ssemov")
1067 (set_attr "mode" "SF")])
1070 [(set (match_operand:V4SF 0 "memory_operand" "")
1073 (match_operand:SF 1 "nonmemory_operand" ""))
1076 "TARGET_SSE && reload_completed"
1079 emit_move_insn (adjust_address (operands[0], SFmode, 0), operands[1]);
1083 (define_insn "sse_movss"
1084 [(set (match_operand:V4SF 0 "register_operand" "=x")
1086 (match_operand:V4SF 2 "register_operand" "x")
1087 (match_operand:V4SF 1 "register_operand" "0")
1090 "movss\t{%2, %0|%0, %2}"
1091 [(set_attr "type" "ssemov")
1092 (set_attr "mode" "SF")])
1094 (define_insn_and_split "sse_storess"
1095 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,m,fr")
1097 (match_operand:V4SF 1 "nonimmediate_operand" "xm,x,m")
1098 (parallel [(const_int 0)])))]
1099 "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1101 "&& reload_completed"
1104 emit_move_insn (operands[0], gen_lowpart (SFmode, operands[1]));
1108 (define_expand "vec_setv4sf"
1109 [(match_operand:V4SF 0 "register_operand" "")
1110 (match_operand:SF 1 "register_operand" "")
1111 (match_operand 2 "const_int_operand" "")]
1114 rtx tmp, op0 = operands[0], op1 = operands[1];
1116 switch (INTVAL (operands[2]))
1119 emit_insn (gen_sse_loadlss (op0, op0, op1));
1123 /* tmp = op0 = A B C D */
1124 tmp = copy_to_reg (op0);
1127 emit_insn (gen_sse_unpcklps (op0, op0, op0));
1130 emit_insn (gen_sse_loadlss (op0, op0, op1));
1133 emit_insn (gen_sse_shufps_1 (op0, op0, tmp, GEN_INT (1), GEN_INT (0),
1134 GEN_INT (2), GEN_INT (3)));
1138 tmp = copy_to_reg (op0);
1139 emit_insn (gen_sse_loadlss (op0, op0, op1));
1140 emit_insn (gen_sse_shufps_1 (op0, op0, tmp, GEN_INT (0), GEN_INT (1),
1141 GEN_INT (0), GEN_INT (3)));
1145 tmp = copy_to_reg (op0);
1146 emit_insn (gen_sse_loadlss (op0, op0, op1));
1147 emit_insn (gen_sse_shufps_1 (op0, op0, tmp, GEN_INT (0), GEN_INT (1),
1148 GEN_INT (2), GEN_INT (0)));
1157 (define_expand "vec_extractv4sf"
1158 [(match_operand:SF 0 "register_operand" "")
1159 (match_operand:V4SF 1 "register_operand" "")
1160 (match_operand 2 "const_int_operand" "")]
1163 rtx tmp, op0 = operands[0], op1 = operands[1];
1165 switch (INTVAL (operands[2]))
1172 tmp = copy_to_reg (op1);
1173 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp, GEN_INT (1), GEN_INT (1),
1174 GEN_INT (2), GEN_INT (3)));
1178 tmp = copy_to_reg (op1);
1179 emit_insn (gen_sse_unpckhps (tmp, tmp, tmp));
1183 tmp = copy_to_reg (op1);
1184 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp, GEN_INT (3), GEN_INT (1),
1185 GEN_INT (2), GEN_INT (3)));
1192 emit_insn (gen_sse_storess (op0, op1));
1196 (define_expand "vec_initv4sf"
1197 [(match_operand:V4SF 0 "register_operand" "")
1198 (match_operand 1 "" "")]
1201 ix86_expand_vector_init (operands[0], operands[1]);
1206 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1208 ;; Parallel double-precision floating point arithmetic
1210 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1212 (define_expand "negv2df2"
1213 [(set (match_operand:V2DF 0 "register_operand" "")
1214 (neg:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")))]
1216 "ix86_expand_fp_absneg_operator (NEG, V2DFmode, operands); DONE;")
1218 (define_expand "absv2df2"
1219 [(set (match_operand:V2DF 0 "register_operand" "")
1220 (abs:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")))]
1222 "ix86_expand_fp_absneg_operator (ABS, V2DFmode, operands); DONE;")
1224 (define_expand "addv2df3"
1225 [(set (match_operand:V2DF 0 "register_operand" "")
1226 (plus:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
1227 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
1229 "ix86_fixup_binary_operands_no_copy (PLUS, V2DFmode, operands);")
1231 (define_insn "*addv2df3"
1232 [(set (match_operand:V2DF 0 "register_operand" "=x")
1233 (plus:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
1234 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
1235 "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V2DFmode, operands)"
1236 "addpd\t{%2, %0|%0, %2}"
1237 [(set_attr "type" "sseadd")
1238 (set_attr "mode" "V2DF")])
1240 (define_insn "sse2_vmaddv2df3"
1241 [(set (match_operand:V2DF 0 "register_operand" "=x")
1243 (plus:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
1244 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1247 "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V4SFmode, operands)"
1248 "addsd\t{%2, %0|%0, %2}"
1249 [(set_attr "type" "sseadd")
1250 (set_attr "mode" "DF")])
1252 (define_expand "subv2df3"
1253 [(set (match_operand:V2DF 0 "register_operand" "")
1254 (minus:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
1255 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
1257 "ix86_fixup_binary_operands_no_copy (MINUS, V2DFmode, operands);")
1259 (define_insn "*subv2df3"
1260 [(set (match_operand:V2DF 0 "register_operand" "=x")
1261 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
1262 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
1264 "subpd\t{%2, %0|%0, %2}"
1265 [(set_attr "type" "sseadd")
1266 (set_attr "mode" "V2DF")])
1268 (define_insn "sse2_vmsubv2df3"
1269 [(set (match_operand:V2DF 0 "register_operand" "=x")
1271 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
1272 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1276 "subsd\t{%2, %0|%0, %2}"
1277 [(set_attr "type" "sseadd")
1278 (set_attr "mode" "DF")])
1280 (define_expand "mulv2df3"
1281 [(set (match_operand:V2DF 0 "register_operand" "")
1282 (mult:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
1283 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
1285 "ix86_fixup_binary_operands_no_copy (MULT, V2DFmode, operands);")
1287 (define_insn "*mulv2df3"
1288 [(set (match_operand:V2DF 0 "register_operand" "=x")
1289 (mult:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
1290 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
1291 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2DFmode, operands)"
1292 "mulpd\t{%2, %0|%0, %2}"
1293 [(set_attr "type" "ssemul")
1294 (set_attr "mode" "V2DF")])
1296 (define_insn "sse2_vmmulv2df3"
1297 [(set (match_operand:V2DF 0 "register_operand" "=x")
1299 (mult:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
1300 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1303 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2DFmode, operands)"
1304 "mulsd\t{%2, %0|%0, %2}"
1305 [(set_attr "type" "ssemul")
1306 (set_attr "mode" "DF")])
1308 (define_expand "divv2df3"
1309 [(set (match_operand:V2DF 0 "register_operand" "")
1310 (div:V2DF (match_operand:V2DF 1 "register_operand" "")
1311 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
1313 "ix86_fixup_binary_operands_no_copy (DIV, V2DFmode, operands);")
1315 (define_insn "*divv2df3"
1316 [(set (match_operand:V2DF 0 "register_operand" "=x")
1317 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
1318 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
1320 "divpd\t{%2, %0|%0, %2}"
1321 [(set_attr "type" "ssediv")
1322 (set_attr "mode" "V2DF")])
1324 (define_insn "sse2_vmdivv2df3"
1325 [(set (match_operand:V2DF 0 "register_operand" "=x")
1327 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
1328 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1332 "divsd\t{%2, %0|%0, %2}"
1333 [(set_attr "type" "ssediv")
1334 (set_attr "mode" "DF")])
1336 (define_insn "sqrtv2df2"
1337 [(set (match_operand:V2DF 0 "register_operand" "=x")
1338 (sqrt:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
1340 "sqrtpd\t{%1, %0|%0, %1}"
1341 [(set_attr "type" "sse")
1342 (set_attr "mode" "V2DF")])
1344 (define_insn "sse2_vmsqrtv2df2"
1345 [(set (match_operand:V2DF 0 "register_operand" "=x")
1347 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
1348 (match_operand:V2DF 2 "register_operand" "0")
1351 "sqrtsd\t{%1, %0|%0, %1}"
1352 [(set_attr "type" "sse")
1353 (set_attr "mode" "SF")])
1355 (define_expand "smaxv2df3"
1356 [(set (match_operand:V2DF 0 "register_operand" "")
1357 (smax:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
1358 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
1360 "ix86_fixup_binary_operands_no_copy (SMAX, V2DFmode, operands);")
1362 (define_insn "*smaxv2df3"
1363 [(set (match_operand:V2DF 0 "register_operand" "=x")
1364 (smax:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
1365 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
1366 "TARGET_SSE2 && ix86_binary_operator_ok (SMAX, V2DFmode, operands)"
1367 "maxpd\t{%2, %0|%0, %2}"
1368 [(set_attr "type" "sseadd")
1369 (set_attr "mode" "V2DF")])
1371 (define_insn "sse2_vmsmaxv2df3"
1372 [(set (match_operand:V2DF 0 "register_operand" "=x")
1374 (smax:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
1375 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1378 "TARGET_SSE2 && ix86_binary_operator_ok (SMAX, V2DFmode, operands)"
1379 "maxsd\t{%2, %0|%0, %2}"
1380 [(set_attr "type" "sseadd")
1381 (set_attr "mode" "DF")])
1383 (define_expand "sminv2df3"
1384 [(set (match_operand:V2DF 0 "register_operand" "")
1385 (smin:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
1386 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
1388 "ix86_fixup_binary_operands_no_copy (SMIN, V2DFmode, operands);")
1390 (define_insn "*sminv2df3"
1391 [(set (match_operand:V2DF 0 "register_operand" "=x")
1392 (smin:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
1393 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
1394 "TARGET_SSE2 && ix86_binary_operator_ok (SMIN, V2DFmode, operands)"
1395 "minpd\t{%2, %0|%0, %2}"
1396 [(set_attr "type" "sseadd")
1397 (set_attr "mode" "V2DF")])
1399 (define_insn "sse2_vmsminv2df3"
1400 [(set (match_operand:V2DF 0 "register_operand" "=x")
1402 (smin:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
1403 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1406 "TARGET_SSE2 && ix86_binary_operator_ok (SMIN, V2DFmode, operands)"
1407 "minsd\t{%2, %0|%0, %2}"
1408 [(set_attr "type" "sseadd")
1409 (set_attr "mode" "DF")])
1411 (define_insn "sse3_addsubv2df3"
1412 [(set (match_operand:V2DF 0 "register_operand" "=x")
1415 (match_operand:V2DF 1 "register_operand" "0")
1416 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1417 (minus:V2DF (match_dup 1) (match_dup 2))
1420 "addsubpd\t{%2, %0|%0, %2}"
1421 [(set_attr "type" "sseadd")
1422 (set_attr "mode" "V2DF")])
1424 (define_insn "sse3_haddv2df3"
1425 [(set (match_operand:V2DF 0 "register_operand" "=x")
1429 (match_operand:V2DF 1 "register_operand" "0")
1430 (parallel [(const_int 0)]))
1431 (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
1434 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
1435 (parallel [(const_int 0)]))
1436 (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
1438 "haddpd\t{%2, %0|%0, %2}"
1439 [(set_attr "type" "sseadd")
1440 (set_attr "mode" "V2DF")])
1442 (define_insn "sse3_hsubv2df3"
1443 [(set (match_operand:V2DF 0 "register_operand" "=x")
1447 (match_operand:V2DF 1 "register_operand" "0")
1448 (parallel [(const_int 0)]))
1449 (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
1452 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
1453 (parallel [(const_int 0)]))
1454 (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
1456 "hsubpd\t{%2, %0|%0, %2}"
1457 [(set_attr "type" "sseadd")
1458 (set_attr "mode" "V2DF")])
1460 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1462 ;; Parallel double-precision floating point comparisons
1464 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1466 (define_insn "sse2_maskcmpv2df3"
1467 [(set (match_operand:V2DF 0 "register_operand" "=x")
1468 (match_operator:V2DF 3 "sse_comparison_operator"
1469 [(match_operand:V2DF 1 "register_operand" "0")
1470 (match_operand:V2DF 2 "nonimmediate_operand" "xm")]))]
1472 "cmp%D3pd\t{%2, %0|%0, %2}"
1473 [(set_attr "type" "ssecmp")
1474 (set_attr "mode" "V2DF")])
1476 (define_insn "sse2_vmmaskcmpv2df3"
1477 [(set (match_operand:V2DF 0 "register_operand" "=x")
1479 (match_operator:V2DF 3 "sse_comparison_operator"
1480 [(match_operand:V2DF 1 "register_operand" "0")
1481 (match_operand:V2DF 2 "nonimmediate_operand" "xm")])
1485 "cmp%D3sd\t{%2, %0|%0, %2}"
1486 [(set_attr "type" "ssecmp")
1487 (set_attr "mode" "DF")])
1489 (define_insn "sse2_comi"
1490 [(set (reg:CCFP FLAGS_REG)
1493 (match_operand:V2DF 0 "register_operand" "x")
1494 (parallel [(const_int 0)]))
1496 (match_operand:V2DF 1 "nonimmediate_operand" "xm")
1497 (parallel [(const_int 0)]))))]
1499 "comisd\t{%1, %0|%0, %1}"
1500 [(set_attr "type" "ssecomi")
1501 (set_attr "mode" "DF")])
1503 (define_insn "sse2_ucomi"
1504 [(set (reg:CCFPU FLAGS_REG)
1507 (match_operand:V2DF 0 "register_operand" "x")
1508 (parallel [(const_int 0)]))
1510 (match_operand:V2DF 1 "nonimmediate_operand" "xm")
1511 (parallel [(const_int 0)]))))]
1513 "ucomisd\t{%1, %0|%0, %1}"
1514 [(set_attr "type" "ssecomi")
1515 (set_attr "mode" "DF")])
1517 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1519 ;; Parallel double-precision floating point logical operations
1521 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1523 (define_expand "andv2df3"
1524 [(set (match_operand:V2DF 0 "register_operand" "")
1525 (and:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
1526 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
1528 "ix86_fixup_binary_operands_no_copy (AND, V2DFmode, operands);")
1530 (define_insn "*andv2df3"
1531 [(set (match_operand:V2DF 0 "register_operand" "=x")
1532 (and:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
1533 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
1534 "TARGET_SSE2 && ix86_binary_operator_ok (AND, V4SFmode, operands)"
1535 "andpd\t{%2, %0|%0, %2}"
1536 [(set_attr "type" "sselog")
1537 (set_attr "mode" "V2DF")])
1539 (define_insn "sse2_nandv2df3"
1540 [(set (match_operand:V2DF 0 "register_operand" "=x")
1541 (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" "0"))
1542 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
1544 "andnpd\t{%2, %0|%0, %2}"
1545 [(set_attr "type" "sselog")
1546 (set_attr "mode" "V2DF")])
1548 (define_expand "iorv2df3"
1549 [(set (match_operand:V2DF 0 "register_operand" "")
1550 (ior:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
1551 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
1553 "ix86_fixup_binary_operands_no_copy (IOR, V2DFmode, operands);")
1555 (define_insn "*iorv2df3"
1556 [(set (match_operand:V2DF 0 "register_operand" "=x")
1557 (ior:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
1558 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
1559 "TARGET_SSE2 && ix86_binary_operator_ok (IOR, V2DFmode, operands)"
1560 "orpd\t{%2, %0|%0, %2}"
1561 [(set_attr "type" "sselog")
1562 (set_attr "mode" "V2DF")])
1564 (define_expand "xorv2df3"
1565 [(set (match_operand:V2DF 0 "register_operand" "")
1566 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "")
1567 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
1569 "ix86_fixup_binary_operands_no_copy (XOR, V2DFmode, operands);")
1571 (define_insn "*xorv2df3"
1572 [(set (match_operand:V2DF 0 "register_operand" "=x")
1573 (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0")
1574 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
1575 "TARGET_SSE2 && ix86_binary_operator_ok (XOR, V2DFmode, operands)"
1576 "xorpd\t{%2, %0|%0, %2}"
1577 [(set_attr "type" "sselog")
1578 (set_attr "mode" "V2DF")])
1580 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1582 ;; Parallel double-precision floating point conversion operations
1584 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1586 (define_insn "sse2_cvtpi2pd"
1587 [(set (match_operand:V2DF 0 "register_operand" "=x")
1588 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
1590 "cvtpi2pd\t{%1, %0|%0, %1}"
1591 [(set_attr "type" "ssecvt")
1592 (set_attr "mode" "V2DF")])
1594 (define_insn "sse2_cvtpd2pi"
1595 [(set (match_operand:V2SI 0 "register_operand" "=y")
1596 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
1597 UNSPEC_FIX_NOTRUNC))]
1599 "cvtpd2pi\t{%1, %0|%0, %1}"
1600 [(set_attr "type" "ssecvt")
1601 (set_attr "mode" "DI")])
1603 (define_insn "sse2_cvttpd2pi"
1604 [(set (match_operand:V2SI 0 "register_operand" "=y")
1605 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
1607 "cvttpd2pi\t{%1, %0|%0, %1}"
1608 [(set_attr "type" "ssecvt")
1609 (set_attr "mode" "TI")])
1611 (define_insn "sse2_cvtsi2sd"
1612 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
1615 (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
1616 (match_operand:V2DF 1 "register_operand" "0,0")
1619 "cvtsi2sd\t{%2, %0|%0, %2}"
1620 [(set_attr "type" "sseicvt")
1621 (set_attr "mode" "DF")
1622 (set_attr "athlon_decode" "double,direct")])
1624 (define_insn "sse2_cvtsi2sdq"
1625 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
1628 (float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m")))
1629 (match_operand:V2DF 1 "register_operand" "0,0")
1631 "TARGET_SSE2 && TARGET_64BIT"
1632 "cvtsi2sdq\t{%2, %0|%0, %2}"
1633 [(set_attr "type" "sseicvt")
1634 (set_attr "mode" "DF")
1635 (set_attr "athlon_decode" "double,direct")])
1637 (define_insn "sse2_cvtsd2si"
1638 [(set (match_operand:SI 0 "register_operand" "=r,r")
1641 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1642 (parallel [(const_int 0)]))]
1643 UNSPEC_FIX_NOTRUNC))]
1645 "cvtsd2si\t{%1, %0|%0, %1}"
1646 [(set_attr "type" "sseicvt")
1647 (set_attr "athlon_decode" "double,vector")
1648 (set_attr "mode" "SI")])
1650 (define_insn "sse2_cvtsd2siq"
1651 [(set (match_operand:DI 0 "register_operand" "=r,r")
1654 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1655 (parallel [(const_int 0)]))]
1656 UNSPEC_FIX_NOTRUNC))]
1657 "TARGET_SSE2 && TARGET_64BIT"
1658 "cvtsd2siq\t{%1, %0|%0, %1}"
1659 [(set_attr "type" "sseicvt")
1660 (set_attr "athlon_decode" "double,vector")
1661 (set_attr "mode" "DI")])
1663 (define_insn "sse2_cvttsd2si"
1664 [(set (match_operand:SI 0 "register_operand" "=r,r")
1667 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1668 (parallel [(const_int 0)]))))]
1670 "cvttsd2si\t{%1, %0|%0, %1}"
1671 [(set_attr "type" "sseicvt")
1672 (set_attr "mode" "SI")
1673 (set_attr "athlon_decode" "double,vector")])
1675 (define_insn "sse2_cvttsd2siq"
1676 [(set (match_operand:DI 0 "register_operand" "=r,r")
1679 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
1680 (parallel [(const_int 0)]))))]
1681 "TARGET_SSE2 && TARGET_64BIT"
1682 "cvttsd2siq\t{%1, %0|%0, %1}"
1683 [(set_attr "type" "sseicvt")
1684 (set_attr "mode" "DI")
1685 (set_attr "athlon_decode" "double,vector")])
1687 (define_insn "sse2_cvtdq2pd"
1688 [(set (match_operand:V2DF 0 "register_operand" "=x")
1691 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
1692 (parallel [(const_int 0) (const_int 1)]))))]
1694 "cvtdq2pd\t{%1, %0|%0, %1}"
1695 [(set_attr "type" "ssecvt")
1696 (set_attr "mode" "V2DF")])
1698 (define_expand "sse2_cvtpd2dq"
1699 [(set (match_operand:V4SI 0 "register_operand" "")
1701 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "")]
1705 "operands[2] = CONST0_RTX (V2SImode);")
1707 (define_insn "*sse2_cvtpd2dq"
1708 [(set (match_operand:V4SI 0 "register_operand" "=x")
1710 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
1712 (match_operand:V2SI 2 "const0_operand" "")))]
1714 "cvtpd2dq\t{%1, %0|%0, %1}"
1715 [(set_attr "type" "ssecvt")
1716 (set_attr "mode" "TI")])
1718 (define_expand "sse2_cvttpd2dq"
1719 [(set (match_operand:V4SI 0 "register_operand" "")
1721 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" ""))
1724 "operands[2] = CONST0_RTX (V2SImode);")
1726 (define_insn "*sse2_cvttpd2dq"
1727 [(set (match_operand:V4SI 0 "register_operand" "=x")
1729 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
1730 (match_operand:V2SI 2 "const0_operand" "")))]
1732 "cvttpd2dq\t{%1, %0|%0, %1}"
1733 [(set_attr "type" "ssecvt")
1734 (set_attr "mode" "TI")])
1736 (define_insn "sse2_cvtsd2ss"
1737 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
1740 (float_truncate:V2SF
1741 (match_operand:V2DF 2 "nonimmediate_operand" "x,m")))
1742 (match_operand:V4SF 1 "register_operand" "0,0")
1745 "cvtsd2ss\t{%2, %0|%0, %2}"
1746 [(set_attr "type" "ssecvt")
1747 (set_attr "athlon_decode" "vector,double")
1748 (set_attr "mode" "SF")])
1750 (define_insn "sse2_cvtss2sd"
1751 [(set (match_operand:V2DF 0 "register_operand" "=x")
1755 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
1756 (parallel [(const_int 0) (const_int 1)])))
1757 (match_operand:V2DF 1 "register_operand" "0")
1760 "cvtss2sd\t{%2, %0|%0, %2}"
1761 [(set_attr "type" "ssecvt")
1762 (set_attr "mode" "DF")])
1764 (define_expand "sse2_cvtpd2ps"
1765 [(set (match_operand:V4SF 0 "register_operand" "")
1767 (float_truncate:V2SF
1768 (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
1771 "operands[2] = CONST0_RTX (V2SFmode);")
1773 (define_insn "*sse2_cvtpd2ps"
1774 [(set (match_operand:V4SF 0 "register_operand" "=x")
1776 (float_truncate:V2SF
1777 (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
1778 (match_operand:V2SF 2 "const0_operand" "")))]
1780 "cvtpd2ps\t{%1, %0|%0, %1}"
1781 [(set_attr "type" "ssecvt")
1782 (set_attr "mode" "V4SF")])
1784 (define_insn "sse2_cvtps2pd"
1785 [(set (match_operand:V2DF 0 "register_operand" "=x")
1788 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
1789 (parallel [(const_int 0) (const_int 1)]))))]
1791 "cvtps2pd\t{%1, %0|%0, %1}"
1792 [(set_attr "type" "ssecvt")
1793 (set_attr "mode" "V2DF")])
1795 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1797 ;; Parallel double-precision floating point element swizzling
1799 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1801 (define_insn "sse2_unpckhpd"
1802 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
1805 (match_operand:V2DF 1 "nonimmediate_operand" " 0,o,x")
1806 (match_operand:V2DF 2 "nonimmediate_operand" " x,0,0"))
1807 (parallel [(const_int 1)
1809 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
1811 unpckhpd\t{%2, %0|%0, %2}
1812 movlpd\t{%H1, %0|%0, %H1}
1813 movhpd\t{%1, %0|%0, %1}"
1814 [(set_attr "type" "sselog,ssemov,ssemov")
1815 (set_attr "mode" "V2DF,V1DF,V1DF")])
1817 (define_insn "sse3_movddup"
1818 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,o")
1821 (match_operand:V2DF 1 "nonimmediate_operand" "xm,x")
1823 (parallel [(const_int 0)
1825 "TARGET_SSE3 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
1827 movddup\t{%1, %0|%0, %1}
1829 [(set_attr "type" "sselog,ssemov")
1830 (set_attr "mode" "V2DF")])
1833 [(set (match_operand:V2DF 0 "memory_operand" "")
1836 (match_operand:V2DF 1 "register_operand" "")
1838 (parallel [(const_int 0)
1840 "TARGET_SSE3 && reload_completed"
1843 rtx low = gen_lowpart (DFmode, operands[1]);
1844 emit_move_insn (adjust_address (operands[0], DFmode, 0), low);
1845 emit_move_insn (adjust_address (operands[0], DFmode, 8), low);
1849 (define_insn "sse2_unpcklpd"
1850 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o")
1853 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0")
1854 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x"))
1855 (parallel [(const_int 0)
1857 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
1859 unpcklpd\t{%2, %0|%0, %2}
1860 movhpd\t{%2, %0|%0, %2}
1861 movlpd\t{%2, %H0|%H0, %2}"
1862 [(set_attr "type" "sselog,ssemov,ssemov")
1863 (set_attr "mode" "V2DF,V1DF,V1DF")])
1865 (define_expand "sse2_shufpd"
1866 [(match_operand:V2DF 0 "register_operand" "")
1867 (match_operand:V2DF 1 "register_operand" "")
1868 (match_operand:V2DF 2 "nonimmediate_operand" "")
1869 (match_operand:SI 3 "const_int_operand" "")]
1872 int mask = INTVAL (operands[3]);
1873 emit_insn (gen_sse2_shufpd_1 (operands[0], operands[1], operands[2],
1875 GEN_INT (mask & 2 ? 3 : 2)));
1879 (define_insn "sse2_shufpd_1"
1880 [(set (match_operand:V2DF 0 "register_operand" "=x")
1883 (match_operand:V2DF 1 "register_operand" "0")
1884 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1885 (parallel [(match_operand 3 "const_0_to_1_operand" "")
1886 (match_operand 4 "const_2_to_3_operand" "")])))]
1890 mask = INTVAL (operands[3]);
1891 mask |= (INTVAL (operands[4]) - 2) << 1;
1892 operands[3] = GEN_INT (mask);
1894 return "shufpd\t{%3, %2, %0|%0, %2, %3}";
1896 [(set_attr "type" "sselog")
1897 (set_attr "mode" "V2DF")])
1899 (define_insn "sse2_storehpd"
1900 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x*fr")
1902 (match_operand:V2DF 1 "nonimmediate_operand" " x,0,o")
1903 (parallel [(const_int 1)])))]
1904 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1906 movhpd\t{%1, %0|%0, %1}
1909 [(set_attr "type" "ssemov,sselog1,ssemov")
1910 (set_attr "mode" "V1DF,V2DF,DF")])
1913 [(set (match_operand:DF 0 "register_operand" "")
1915 (match_operand:V2DF 1 "memory_operand" "")
1916 (parallel [(const_int 1)])))]
1917 "TARGET_SSE2 && reload_completed"
1918 [(set (match_dup 0) (match_dup 1))]
1920 operands[1] = adjust_address (operands[1], DFmode, 8);
1923 (define_insn "sse2_storelpd"
1924 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x*fr")
1926 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,m")
1927 (parallel [(const_int 0)])))]
1928 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1930 movlpd\t{%1, %0|%0, %1}
1933 [(set_attr "type" "ssemov")
1934 (set_attr "mode" "V1DF,DF,DF")])
1937 [(set (match_operand:DF 0 "register_operand" "")
1939 (match_operand:V2DF 1 "nonimmediate_operand" "")
1940 (parallel [(const_int 0)])))]
1941 "TARGET_SSE2 && reload_completed"
1942 [(set (match_dup 0) (match_dup 1))]
1944 operands[0] = gen_lowpart (DFmode, operands[0]);
1945 operands[1] = gen_lowpart (DFmode, operands[1]);
1948 (define_insn "sse2_loadhpd"
1949 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,o")
1952 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,x,0")
1953 (parallel [(const_int 0)]))
1954 (match_operand:DF 2 "nonimmediate_operand" " m,x,0,x*fr")))]
1955 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
1957 movhpd\t{%2, %0|%0, %2}
1958 unpcklpd\t{%2, %0|%0, %2}
1959 shufpd\t{$1, %1, %0|%0, %1, 1}
1961 [(set_attr "type" "ssemov,sselog,sselog,other")
1962 (set_attr "mode" "V1DF,V2DF,V2DF,DF")])
1965 [(set (match_operand:V2DF 0 "memory_operand" "")
1967 (vec_select:DF (match_dup 0) (parallel [(const_int 0)]))
1968 (match_operand:DF 1 "register_operand" "")))]
1969 "TARGET_SSE2 && reload_completed"
1970 [(set (match_dup 0) (match_dup 1))]
1972 operands[0] = adjust_address (operands[0], DFmode, 8);
1975 (define_insn "sse2_loadlpd"
1976 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,x,m")
1978 (match_operand:DF 2 "nonimmediate_operand" " m,m,x,0,0,x*fr")
1980 (match_operand:V2DF 1 "vector_move_operand" " C,0,0,x,o,0")
1981 (parallel [(const_int 1)]))))]
1982 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
1984 movsd\t{%2, %0|%0, %2}
1985 movlpd\t{%2, %0|%0, %2}
1986 movsd\t{%2, %0|%0, %2}
1987 shufpd\t{$2, %2, %0|%0, %2, 2}
1988 movhpd\t{%H1, %0|%0, %H1}
1990 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,other")
1991 (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,DF")])
1994 [(set (match_operand:V2DF 0 "memory_operand" "")
1996 (match_operand:DF 1 "register_operand" "")
1997 (vec_select:DF (match_dup 0) (parallel [(const_int 1)]))))]
1998 "TARGET_SSE2 && reload_completed"
1999 [(set (match_dup 0) (match_dup 1))]
2001 operands[0] = adjust_address (operands[0], DFmode, 8);
2004 (define_expand "sse2_loadsd"
2005 [(set (match_operand:V2DF 0 "register_operand" "")
2007 (match_operand:DF 1 "nonimmediate_operand" "")
2008 (vec_select:DF (match_dup 2) (parallel [(const_int 1)]))))]
2010 "operands[2] = CONST0_RTX (V2DFmode);")
2012 (define_insn "sse2_movsd"
2013 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m,x,x,o")
2015 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x,0,0,0")
2016 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0,x,o,x")
2020 movsd\t{%2, %0|%0, %2}
2021 movlpd\t{%2, %0|%0, %2}
2022 movlpd\t{%2, %0|%0, %2}
2023 shufpd\t{$2, %2, %0|%0, %2, 2}
2024 movhps\t{%H1, %0|%0, %H1
2025 movhps\t{%1, %H0|%H0, %1"
2026 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
2027 (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,V1DF")])
2029 (define_insn "sse3_loadddup"
2030 [(set (match_operand:V2DF 0 "register_operand" "=x")
2032 (match_operand:DF 1 "nonimmediate_operand" "xm")))]
2034 "movddup\t{%1, %0|%0, %1}"
2035 [(set_attr "type" "ssecvt")
2036 (set_attr "mode" "DF")])
2038 (define_expand "vec_setv2df"
2039 [(match_operand:V2DF 0 "register_operand" "")
2040 (match_operand:DF 1 "register_operand" "")
2041 (match_operand 2 "const_int_operand" "")]
2044 switch (INTVAL (operands[2]))
2047 emit_insn (gen_sse2_loadlpd (operands[0], operands[0], operands[1]));
2050 emit_insn (gen_sse2_loadhpd (operands[0], operands[0], operands[1]));
2058 (define_expand "vec_extractv2df"
2059 [(match_operand:DF 0 "register_operand" "")
2060 (match_operand:V2DF 1 "register_operand" "")
2061 (match_operand 2 "const_int_operand" "")]
2064 switch (INTVAL (operands[2]))
2067 emit_insn (gen_sse2_storelpd (operands[0], operands[1]));
2070 emit_insn (gen_sse2_storehpd (operands[0], operands[1]));
2078 (define_expand "vec_initv2df"
2079 [(match_operand:V2DF 0 "register_operand" "")
2080 (match_operand 1 "" "")]
2083 ix86_expand_vector_init (operands[0], operands[1]);
2087 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2089 ;; Parallel integral arithmetic
2091 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2093 (define_expand "neg<mode>2"
2094 [(set (match_operand:SSEMODEI 0 "register_operand" "")
2097 (match_operand:SSEMODEI 1 "nonimmediate_operand" "")))]
2099 "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
2101 (define_expand "add<mode>3"
2102 [(set (match_operand:SSEMODEI 0 "register_operand" "")
2103 (plus:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
2104 (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
2106 "ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);")
2108 (define_insn "*add<mode>3"
2109 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
2111 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
2112 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
2113 "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
2114 "padd<ssevecsize>\t{%2, %0|%0, %2}"
2115 [(set_attr "type" "sseiadd")
2116 (set_attr "mode" "TI")])
2118 (define_insn "sse2_ssadd<mode>3"
2119 [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
2121 (match_operand:SSEMODE12 1 "nonimmediate_operand" "%0")
2122 (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
2123 "TARGET_SSE2 && ix86_binary_operator_ok (SS_PLUS, <MODE>mode, operands)"
2124 "padds<ssevecsize>\t{%2, %0|%0, %2}"
2125 [(set_attr "type" "sseiadd")
2126 (set_attr "mode" "TI")])
2128 (define_insn "sse2_usadd<mode>3"
2129 [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
2131 (match_operand:SSEMODE12 1 "nonimmediate_operand" "%0")
2132 (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
2133 "TARGET_SSE2 && ix86_binary_operator_ok (US_PLUS, <MODE>mode, operands)"
2134 "paddus<ssevecsize>\t{%2, %0|%0, %2}"
2135 [(set_attr "type" "sseiadd")
2136 (set_attr "mode" "TI")])
2138 (define_expand "sub<mode>3"
2139 [(set (match_operand:SSEMODEI 0 "register_operand" "")
2140 (minus:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "")
2141 (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
2143 "ix86_fixup_binary_operands_no_copy (MINUS, <MODE>mode, operands);")
2145 (define_insn "*sub<mode>3"
2146 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
2148 (match_operand:SSEMODEI 1 "register_operand" "0")
2149 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
2151 "psub<ssevecsize>\t{%2, %0|%0, %2}"
2152 [(set_attr "type" "sseiadd")
2153 (set_attr "mode" "TI")])
2155 (define_insn "sse2_sssub<mode>3"
2156 [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
2158 (match_operand:SSEMODE12 1 "register_operand" "0")
2159 (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
2161 "psubs<ssevecsize>\t{%2, %0|%0, %2}"
2162 [(set_attr "type" "sseiadd")
2163 (set_attr "mode" "TI")])
2165 (define_insn "sse2_ussub<mode>3"
2166 [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
2168 (match_operand:SSEMODE12 1 "register_operand" "0")
2169 (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
2171 "psubus<ssevecsize>\t{%2, %0|%0, %2}"
2172 [(set_attr "type" "sseiadd")
2173 (set_attr "mode" "TI")])
2175 (define_expand "mulv8hi3"
2176 [(set (match_operand:V8HI 0 "register_operand" "")
2177 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "")
2178 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
2180 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
2182 (define_insn "*mulv8hi3"
2183 [(set (match_operand:V8HI 0 "register_operand" "=x")
2184 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0")
2185 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
2186 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
2187 "pmullw\t{%2, %0|%0, %2}"
2188 [(set_attr "type" "sseimul")
2189 (set_attr "mode" "TI")])
2191 (define_insn "sse2_smulv8hi3_highpart"
2192 [(set (match_operand:V8HI 0 "register_operand" "=x")
2197 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
2199 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
2201 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
2202 "pmulhw\t{%2, %0|%0, %2}"
2203 [(set_attr "type" "sseimul")
2204 (set_attr "mode" "TI")])
2206 (define_insn "sse2_umulv8hi3_highpart"
2207 [(set (match_operand:V8HI 0 "register_operand" "=x")
2212 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
2214 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
2216 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
2217 "pmulhuw\t{%2, %0|%0, %2}"
2218 [(set_attr "type" "sseimul")
2219 (set_attr "mode" "TI")])
2221 (define_insn "sse2_umulv2siv2di3"
2222 [(set (match_operand:V2DI 0 "register_operand" "=x")
2226 (match_operand:V4SI 1 "nonimmediate_operand" "%0")
2227 (parallel [(const_int 0) (const_int 2)])))
2230 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
2231 (parallel [(const_int 0) (const_int 2)])))))]
2232 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
2233 "pmuludq\t{%2, %0|%0, %2}"
2234 [(set_attr "type" "sseimul")
2235 (set_attr "mode" "TI")])
2237 (define_insn "sse2_pmaddwd"
2238 [(set (match_operand:V4SI 0 "register_operand" "=x")
2243 (match_operand:V8HI 1 "nonimmediate_operand" "%0")
2244 (parallel [(const_int 0)
2250 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
2251 (parallel [(const_int 0)
2257 (vec_select:V4HI (match_dup 1)
2258 (parallel [(const_int 1)
2263 (vec_select:V4HI (match_dup 2)
2264 (parallel [(const_int 1)
2267 (const_int 7)]))))))]
2269 "pmaddwd\t{%2, %0|%0, %2}"
2270 [(set_attr "type" "sseiadd")
2271 (set_attr "mode" "TI")])
2273 (define_insn "ashr<mode>3"
2274 [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
2276 (match_operand:SSEMODE24 1 "register_operand" "0")
2277 (match_operand:SI 2 "nonmemory_operand" "xi")))]
2279 "psra<ssevecsize>\t{%2, %0|%0, %2}"
2280 [(set_attr "type" "sseishft")
2281 (set_attr "mode" "TI")])
2283 (define_insn "lshr<mode>3"
2284 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
2285 (lshiftrt:SSEMODE248
2286 (match_operand:SSEMODE248 1 "register_operand" "0")
2287 (match_operand:SI 2 "nonmemory_operand" "xi")))]
2289 "psrl<ssevecsize>\t{%2, %0|%0, %2}"
2290 [(set_attr "type" "sseishft")
2291 (set_attr "mode" "TI")])
2293 (define_insn "ashl<mode>3"
2294 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
2296 (match_operand:SSEMODE248 1 "register_operand" "0")
2297 (match_operand:SI 2 "nonmemory_operand" "xi")))]
2299 "psll<ssevecsize>\t{%2, %0|%0, %2}"
2300 [(set_attr "type" "sseishft")
2301 (set_attr "mode" "TI")])
2303 (define_insn "sse2_ashlti3"
2304 [(set (match_operand:TI 0 "register_operand" "=x")
2305 (ashift:TI (match_operand:TI 1 "register_operand" "0")
2306 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
2309 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
2310 return "pslldq\t{%2, %0|%0, %2}";
2312 [(set_attr "type" "sseishft")
2313 (set_attr "mode" "TI")])
2315 (define_insn "sse2_lshrti3"
2316 [(set (match_operand:TI 0 "register_operand" "=x")
2317 (lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
2318 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
2321 operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
2322 return "psrldq\t{%2, %0|%0, %2}";
2324 [(set_attr "type" "sseishft")
2325 (set_attr "mode" "TI")])
2327 (define_expand "umaxv16qi3"
2328 [(set (match_operand:V16QI 0 "register_operand" "")
2329 (umax:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "")
2330 (match_operand:V16QI 2 "nonimmediate_operand" "")))]
2332 "ix86_fixup_binary_operands_no_copy (UMAX, V16QImode, operands);")
2334 (define_insn "*umaxv16qi3"
2335 [(set (match_operand:V16QI 0 "register_operand" "=x")
2336 (umax:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "%0")
2337 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
2338 "TARGET_SSE2 && ix86_binary_operator_ok (UMAX, V16QImode, operands)"
2339 "pmaxub\t{%2, %0|%0, %2}"
2340 [(set_attr "type" "sseiadd")
2341 (set_attr "mode" "TI")])
2343 (define_expand "smaxv8hi3"
2344 [(set (match_operand:V8HI 0 "register_operand" "")
2345 (smax:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "")
2346 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
2348 "ix86_fixup_binary_operands_no_copy (SMAX, V8HImode, operands);")
2350 (define_insn "*smaxv8hi3"
2351 [(set (match_operand:V8HI 0 "register_operand" "=x")
2352 (smax:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0")
2353 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
2354 "TARGET_SSE2 && ix86_binary_operator_ok (SMAX, V8HImode, operands)"
2355 "pmaxsw\t{%2, %0|%0, %2}"
2356 [(set_attr "type" "sseiadd")
2357 (set_attr "mode" "TI")])
2359 (define_expand "uminv16qi3"
2360 [(set (match_operand:V16QI 0 "register_operand" "")
2361 (umin:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "")
2362 (match_operand:V16QI 2 "nonimmediate_operand" "")))]
2364 "ix86_fixup_binary_operands_no_copy (UMAX, V16QImode, operands);")
2366 (define_insn "*uminv16qi3"
2367 [(set (match_operand:V16QI 0 "register_operand" "=x")
2368 (umin:V16QI (match_operand:V16QI 1 "nonimmediate_operand" "%0")
2369 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
2370 "TARGET_SSE2 && ix86_binary_operator_ok (UMIN, V16QImode, operands)"
2371 "pminub\t{%2, %0|%0, %2}"
2372 [(set_attr "type" "sseiadd")
2373 (set_attr "mode" "TI")])
2375 (define_expand "sminv8hi3"
2376 [(set (match_operand:V8HI 0 "register_operand" "")
2377 (smin:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "")
2378 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
2380 "ix86_fixup_binary_operands_no_copy (SMIN, V8HImode, operands);")
2382 (define_insn "*sminv8hi3"
2383 [(set (match_operand:V8HI 0 "register_operand" "=x")
2384 (smin:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0")
2385 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
2386 "TARGET_SSE2 && ix86_binary_operator_ok (SMIN, V8HImode, operands)"
2387 "pminsw\t{%2, %0|%0, %2}"
2388 [(set_attr "type" "sseiadd")
2389 (set_attr "mode" "TI")])
2391 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2393 ;; Parallel integral comparisons
2395 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2397 (define_insn "sse2_eq<mode>3"
2398 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
2400 (match_operand:SSEMODE124 1 "nonimmediate_operand" "%0")
2401 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
2402 "TARGET_SSE2 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
2403 "pcmpeq<ssevecsize>\t{%2, %0|%0, %2}"
2404 [(set_attr "type" "ssecmp")
2405 (set_attr "mode" "TI")])
2407 (define_insn "sse2_gt<mode>3"
2408 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
2410 (match_operand:SSEMODE124 1 "register_operand" "0")
2411 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
2413 "pcmpgt<ssevecsize>\t{%2, %0|%0, %2}"
2414 [(set_attr "type" "ssecmp")
2415 (set_attr "mode" "TI")])
2417 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2419 ;; Parallel integral logical operations
2421 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2423 (define_expand "one_cmpl<mode>2"
2424 [(set (match_operand:SSEMODEI 0 "register_operand" "")
2425 (xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
2429 int i, n = GET_MODE_NUNITS (<MODE>mode);
2430 rtvec v = rtvec_alloc (n);
2432 for (i = 0; i < n; ++i)
2433 RTVEC_ELT (v, i) = constm1_rtx;
2435 operands[2] = force_reg (<MODE>mode, gen_rtx_CONST_VECTOR (<MODE>mode, v));
2438 (define_expand "and<mode>3"
2439 [(set (match_operand:SSEMODEI 0 "register_operand" "")
2440 (and:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
2441 (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
2443 "ix86_fixup_binary_operands_no_copy (AND, <MODE>mode, operands);")
2445 (define_insn "*and<mode>3"
2446 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
2448 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
2449 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
2450 "TARGET_SSE2 && ix86_binary_operator_ok (AND, <MODE>mode, operands)"
2451 "pand\t{%2, %0|%0, %2}"
2452 [(set_attr "type" "sselog")
2453 (set_attr "mode" "TI")])
2455 (define_insn "sse2_nand<mode>3"
2456 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
2458 (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
2459 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
2461 "pandn\t{%2, %0|%0, %2}"
2462 [(set_attr "type" "sselog")
2463 (set_attr "mode" "TI")])
2465 (define_expand "ior<mode>3"
2466 [(set (match_operand:SSEMODEI 0 "register_operand" "")
2467 (ior:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
2468 (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
2470 "ix86_fixup_binary_operands_no_copy (IOR, <MODE>mode, operands);")
2472 (define_insn "*ior<mode>3"
2473 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
2475 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
2476 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
2477 "TARGET_SSE2 && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
2478 "por\t{%2, %0|%0, %2}"
2479 [(set_attr "type" "sselog")
2480 (set_attr "mode" "TI")])
2482 (define_expand "xor<mode>3"
2483 [(set (match_operand:SSEMODEI 0 "register_operand" "")
2484 (xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
2485 (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
2487 "ix86_fixup_binary_operands_no_copy (XOR, <MODE>mode, operands);")
2489 (define_insn "*xor<mode>3"
2490 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
2492 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
2493 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
2494 "TARGET_SSE2 && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
2495 "pxor\t{%2, %0|%0, %2}"
2496 [(set_attr "type" "sselog")
2497 (set_attr "mode" "TI")])
2499 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2501 ;; Parallel integral element swizzling
2503 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2505 (define_insn "sse2_packsswb"
2506 [(set (match_operand:V16QI 0 "register_operand" "=x")
2509 (match_operand:V8HI 1 "register_operand" "0"))
2511 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
2513 "packsswb\t{%2, %0|%0, %2}"
2514 [(set_attr "type" "sselog")
2515 (set_attr "mode" "TI")])
2517 (define_insn "sse2_packssdw"
2518 [(set (match_operand:V8HI 0 "register_operand" "=x")
2521 (match_operand:V4SI 1 "register_operand" "0"))
2523 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
2525 "packssdw\t{%2, %0|%0, %2}"
2526 [(set_attr "type" "sselog")
2527 (set_attr "mode" "TI")])
2529 (define_insn "sse2_packuswb"
2530 [(set (match_operand:V16QI 0 "register_operand" "=x")
2533 (match_operand:V8HI 1 "register_operand" "0"))
2535 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
2537 "packuswb\t{%2, %0|%0, %2}"
2538 [(set_attr "type" "sselog")
2539 (set_attr "mode" "TI")])
2541 (define_insn "sse2_punpckhbw"
2542 [(set (match_operand:V16QI 0 "register_operand" "=x")
2545 (match_operand:V16QI 1 "register_operand" "0")
2546 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
2547 (parallel [(const_int 8) (const_int 24)
2548 (const_int 9) (const_int 25)
2549 (const_int 10) (const_int 26)
2550 (const_int 11) (const_int 27)
2551 (const_int 12) (const_int 28)
2552 (const_int 13) (const_int 29)
2553 (const_int 14) (const_int 30)
2554 (const_int 15) (const_int 31)])))]
2556 "punpckhbw\t{%2, %0|%0, %2}"
2557 [(set_attr "type" "sselog")
2558 (set_attr "mode" "TI")])
2560 (define_insn "sse2_punpcklbw"
2561 [(set (match_operand:V16QI 0 "register_operand" "=x")
2564 (match_operand:V16QI 1 "register_operand" "0")
2565 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
2566 (parallel [(const_int 0) (const_int 16)
2567 (const_int 1) (const_int 17)
2568 (const_int 2) (const_int 18)
2569 (const_int 3) (const_int 19)
2570 (const_int 4) (const_int 20)
2571 (const_int 5) (const_int 21)
2572 (const_int 6) (const_int 22)
2573 (const_int 7) (const_int 23)])))]
2575 "punpcklbw\t{%2, %0|%0, %2}"
2576 [(set_attr "type" "sselog")
2577 (set_attr "mode" "TI")])
2579 (define_insn "sse2_punpckhwd"
2580 [(set (match_operand:V8HI 0 "register_operand" "=x")
2583 (match_operand:V8HI 1 "register_operand" "0")
2584 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
2585 (parallel [(const_int 4) (const_int 12)
2586 (const_int 5) (const_int 13)
2587 (const_int 6) (const_int 14)
2588 (const_int 7) (const_int 15)])))]
2590 "punpckhwd\t{%2, %0|%0, %2}"
2591 [(set_attr "type" "sselog")
2592 (set_attr "mode" "TI")])
2594 (define_insn "sse2_punpcklwd"
2595 [(set (match_operand:V8HI 0 "register_operand" "=x")
2598 (match_operand:V8HI 1 "register_operand" "0")
2599 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
2600 (parallel [(const_int 0) (const_int 8)
2601 (const_int 1) (const_int 9)
2602 (const_int 2) (const_int 10)
2603 (const_int 3) (const_int 11)])))]
2605 "punpcklwd\t{%2, %0|%0, %2}"
2606 [(set_attr "type" "sselog")
2607 (set_attr "mode" "TI")])
2609 (define_insn "sse2_punpckhdq"
2610 [(set (match_operand:V4SI 0 "register_operand" "=x")
2613 (match_operand:V4SI 1 "register_operand" "0")
2614 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
2615 (parallel [(const_int 2) (const_int 6)
2616 (const_int 3) (const_int 7)])))]
2618 "punpckhdq\t{%2, %0|%0, %2}"
2619 [(set_attr "type" "sselog")
2620 (set_attr "mode" "TI")])
2622 (define_insn "sse2_punpckldq"
2623 [(set (match_operand:V4SI 0 "register_operand" "=x")
2626 (match_operand:V4SI 1 "register_operand" "0")
2627 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
2628 (parallel [(const_int 0) (const_int 4)
2629 (const_int 1) (const_int 5)])))]
2631 "punpckldq\t{%2, %0|%0, %2}"
2632 [(set_attr "type" "sselog")
2633 (set_attr "mode" "TI")])
2635 (define_insn "sse2_punpckhqdq"
2636 [(set (match_operand:V2DI 0 "register_operand" "=x")
2639 (match_operand:V2DI 1 "register_operand" "0")
2640 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
2641 (parallel [(const_int 1)
2644 "punpckhqdq\t{%2, %0|%0, %2}"
2645 [(set_attr "type" "sselog")
2646 (set_attr "mode" "TI")])
2648 (define_insn "sse2_punpcklqdq"
2649 [(set (match_operand:V2DI 0 "register_operand" "=x")
2652 (match_operand:V2DI 1 "register_operand" "0")
2653 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
2654 (parallel [(const_int 0)
2657 "punpcklqdq\t{%2, %0|%0, %2}"
2658 [(set_attr "type" "sselog")
2659 (set_attr "mode" "TI")])
2661 (define_expand "sse2_pinsrw"
2662 [(set (match_operand:V8HI 0 "register_operand" "")
2664 (match_operand:V8HI 1 "register_operand" "")
2666 (match_operand:SI 2 "nonimmediate_operand" ""))
2667 (match_operand:SI 3 "const_0_to_7_operand" "")))]
2670 operands[2] = gen_lowpart (HImode, operands[2]);
2671 operands[3] = GEN_INT ((1 << INTVAL (operands[3])));
2674 (define_insn "*sse2_pinsrw"
2675 [(set (match_operand:V8HI 0 "register_operand" "=x")
2677 (match_operand:V8HI 1 "register_operand" "0")
2679 (match_operand:HI 2 "nonimmediate_operand" "rm"))
2680 (match_operand:SI 3 "const_pow2_1_to_128_operand" "n")))]
2683 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
2684 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
2686 [(set_attr "type" "sselog")
2687 (set_attr "mode" "TI")])
2689 (define_insn "sse2_pextrw"
2690 [(set (match_operand:SI 0 "register_operand" "=r")
2693 (match_operand:V8HI 1 "register_operand" "x")
2694 (parallel [(match_operand:SI 2 "const_0_to_7_operand" "0")]))))]
2696 "pextrw\t{%2, %1, %0|%0, %1, %2}"
2697 [(set_attr "type" "sselog")
2698 (set_attr "mode" "TI")])
2700 (define_expand "sse2_pshufd"
2701 [(match_operand:V4SI 0 "register_operand" "")
2702 (match_operand:V4SI 1 "nonimmediate_operand" "")
2703 (match_operand:SI 2 "const_int_operand" "")]
2706 int mask = INTVAL (operands[2]);
2707 emit_insn (gen_sse2_pshufd_1 (operands[0], operands[1],
2708 GEN_INT ((mask >> 0) & 3),
2709 GEN_INT ((mask >> 2) & 3),
2710 GEN_INT ((mask >> 4) & 3),
2711 GEN_INT ((mask >> 6) & 3)));
2715 (define_insn "sse2_pshufd_1"
2716 [(set (match_operand:V4SI 0 "register_operand" "=x")
2718 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
2719 (parallel [(match_operand 2 "const_0_to_3_operand" "")
2720 (match_operand 3 "const_0_to_3_operand" "")
2721 (match_operand 4 "const_0_to_3_operand" "")
2722 (match_operand 5 "const_0_to_3_operand" "")])))]
2726 mask |= INTVAL (operands[2]) << 0;
2727 mask |= INTVAL (operands[3]) << 2;
2728 mask |= INTVAL (operands[4]) << 4;
2729 mask |= INTVAL (operands[5]) << 6;
2730 operands[2] = GEN_INT (mask);
2732 return "pshufd\t{%2, %1, %0|%0, %1, %2}";
2734 [(set_attr "type" "sselog1")
2735 (set_attr "mode" "TI")])
2737 (define_expand "sse2_pshuflw"
2738 [(match_operand:V8HI 0 "register_operand" "")
2739 (match_operand:V8HI 1 "nonimmediate_operand" "")
2740 (match_operand:SI 2 "const_int_operand" "")]
2743 int mask = INTVAL (operands[2]);
2744 emit_insn (gen_sse2_pshuflw_1 (operands[0], operands[1],
2745 GEN_INT ((mask >> 0) & 3),
2746 GEN_INT ((mask >> 2) & 3),
2747 GEN_INT ((mask >> 4) & 3),
2748 GEN_INT ((mask >> 6) & 3)));
2752 (define_insn "sse2_pshuflw_1"
2753 [(set (match_operand:V8HI 0 "register_operand" "=x")
2755 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
2756 (parallel [(match_operand 2 "const_0_to_3_operand" "")
2757 (match_operand 3 "const_0_to_3_operand" "")
2758 (match_operand 4 "const_0_to_3_operand" "")
2759 (match_operand 5 "const_0_to_3_operand" "")
2767 mask |= INTVAL (operands[2]) << 0;
2768 mask |= INTVAL (operands[3]) << 2;
2769 mask |= INTVAL (operands[4]) << 4;
2770 mask |= INTVAL (operands[5]) << 6;
2771 operands[2] = GEN_INT (mask);
2773 return "pshuflw\t{%2, %1, %0|%0, %1, %2}";
2775 [(set_attr "type" "sselog")
2776 (set_attr "mode" "TI")])
2778 (define_expand "sse2_pshufhw"
2779 [(match_operand:V8HI 0 "register_operand" "")
2780 (match_operand:V8HI 1 "nonimmediate_operand" "")
2781 (match_operand:SI 2 "const_int_operand" "")]
2784 int mask = INTVAL (operands[2]);
2785 emit_insn (gen_sse2_pshufhw_1 (operands[0], operands[1],
2786 GEN_INT (((mask >> 0) & 3) + 4),
2787 GEN_INT (((mask >> 2) & 3) + 4),
2788 GEN_INT (((mask >> 4) & 3) + 4),
2789 GEN_INT (((mask >> 6) & 3) + 4)));
2793 (define_insn "sse2_pshufhw_1"
2794 [(set (match_operand:V8HI 0 "register_operand" "=x")
2796 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
2797 (parallel [(const_int 0)
2801 (match_operand 2 "const_4_to_7_operand" "")
2802 (match_operand 3 "const_4_to_7_operand" "")
2803 (match_operand 4 "const_4_to_7_operand" "")
2804 (match_operand 5 "const_4_to_7_operand" "")])))]
2808 mask |= (INTVAL (operands[2]) - 4) << 0;
2809 mask |= (INTVAL (operands[3]) - 4) << 2;
2810 mask |= (INTVAL (operands[4]) - 4) << 4;
2811 mask |= (INTVAL (operands[5]) - 4) << 6;
2812 operands[2] = GEN_INT (mask);
2814 return "pshufhw\t{%2, %1, %0|%0, %1, %2}";
2816 [(set_attr "type" "sselog")
2817 (set_attr "mode" "TI")])
2819 (define_expand "sse2_loadd"
2820 [(set (match_operand:V4SI 0 "register_operand" "")
2823 (match_operand:SI 1 "nonimmediate_operand" ""))
2827 "operands[2] = CONST0_RTX (V4SImode);")
2829 (define_insn "sse2_loadld"
2830 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
2833 (match_operand:SI 2 "nonimmediate_operand" "mr,x"))
2834 (match_operand:V4SI 1 "vector_move_operand" "C,0")
2838 movd\t{%2, %0|%0, %2}
2839 movss\t{%2, %0|%0, %2}"
2840 [(set_attr "type" "ssemov")
2841 (set_attr "mode" "TI")])
2843 (define_insn_and_split "sse2_stored"
2844 [(set (match_operand:SI 0 "nonimmediate_operand" "=mrx")
2846 (match_operand:V4SI 1 "register_operand" "x")
2847 (parallel [(const_int 0)])))]
2850 "&& reload_completed"
2851 [(set (match_dup 0) (match_dup 1))]
2853 operands[1] = gen_lowpart (SImode, operands[1]);
2856 (define_expand "sse2_storeq"
2857 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2859 (match_operand:V2DI 1 "register_operand" "")
2860 (parallel [(const_int 0)])))]
2864 (define_insn "*sse2_storeq"
2865 [(set (match_operand:DI 0 "nonimmediate_operand" "=myx")
2867 (match_operand:V2DI 1 "register_operand" "x")
2868 (parallel [(const_int 0)])))]
2869 "TARGET_SSE2 && !TARGET_64BIT"
2872 (define_insn "*sse2_storeq_rex64"
2873 [(set (match_operand:DI 0 "nonimmediate_operand" "=myxr")
2875 (match_operand:V2DI 1 "register_operand" "x")
2876 (parallel [(const_int 0)])))]
2877 "TARGET_SSE2 && TARGET_64BIT"
2881 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2883 (match_operand:V2DI 1 "register_operand" "")
2884 (parallel [(const_int 0)])))]
2885 "TARGET_SSE2 && reload_completed"
2886 [(set (match_dup 0) (match_dup 1))]
2888 operands[1] = gen_lowpart (DImode, operands[1]);
2891 (define_expand "sse2_loadq"
2892 [(set (match_operand:V2DI 0 "register_operand" "")
2895 (match_operand:DI 1 "nonimmediate_operand" ""))
2899 "operands[2] = CONST0_RTX (V2DImode);")
2901 (define_insn "*sse2_loadq"
2902 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,x")
2905 (match_operand:DI 1 "nonimmediate_operand" " m, y,x"))
2906 (match_operand:V2DI 2 "vector_move_operand" " C, C,0")
2908 "TARGET_SSE2 && !TARGET_64BIT"
2910 movq\t{%1, %0|%0, %1}
2911 movq2dq\t{%1, %0|%0, %1}
2912 movq\t{%1, %0|%0, %1}"
2913 [(set_attr "type" "ssemov")
2914 (set_attr "mode" "TI")])
2916 (define_insn "*sse2_loadq_rex64"
2917 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x,x")
2920 (match_operand:DI 1 "nonimmediate_operand" " m, y, r,x"))
2921 (match_operand:V2DI 2 "vector_move_operand" " C, C, C,0")
2923 "TARGET_SSE2 && TARGET_64BIT"
2925 movq\t{%1, %0|%0, %1}
2926 movq2dq\t{%1, %0|%0, %1}
2927 movd\t{%1, %0|%0, %1}
2928 movq\t{%1, %0|%0, %1}"
2929 [(set_attr "type" "ssemov")
2930 (set_attr "mode" "TI")])
2932 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2936 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2938 (define_insn "sse2_uavgv16qi3"
2939 [(set (match_operand:V16QI 0 "register_operand" "=x")
2945 (match_operand:V16QI 1 "nonimmediate_operand" "%0"))
2947 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))
2948 (const_vector:V16QI [(const_int 1) (const_int 1)
2949 (const_int 1) (const_int 1)
2950 (const_int 1) (const_int 1)
2951 (const_int 1) (const_int 1)
2952 (const_int 1) (const_int 1)
2953 (const_int 1) (const_int 1)
2954 (const_int 1) (const_int 1)
2955 (const_int 1) (const_int 1)]))
2957 "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V16QImode, operands)"
2958 "pavgb\t{%2, %0|%0, %2}"
2959 [(set_attr "type" "sseiadd")
2960 (set_attr "mode" "TI")])
2962 (define_insn "sse2_uavgv8hi3"
2963 [(set (match_operand:V8HI 0 "register_operand" "=x")
2969 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
2971 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
2972 (const_vector:V8HI [(const_int 1) (const_int 1)
2973 (const_int 1) (const_int 1)
2974 (const_int 1) (const_int 1)
2975 (const_int 1) (const_int 1)]))
2977 "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V8HImode, operands)"
2978 "pavgw\t{%2, %0|%0, %2}"
2979 [(set_attr "type" "sseiadd")
2980 (set_attr "mode" "TI")])
2982 ;; The correct representation for this is absolutely enormous, and
2983 ;; surely not generally useful.
2984 (define_insn "sse2_psadbw"
2985 [(set (match_operand:V2DI 0 "register_operand" "=x")
2986 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
2987 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
2990 "psadbw\t{%2, %0|%0, %2}"
2991 [(set_attr "type" "sseiadd")
2992 (set_attr "mode" "TI")])
2994 (define_insn "sse_movmskps"
2995 [(set (match_operand:SI 0 "register_operand" "=r")
2996 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
2999 "movmskps\t{%1, %0|%0, %1}"
3000 [(set_attr "type" "ssecvt")
3001 (set_attr "mode" "V4SF")])
3003 (define_insn "sse2_movmskpd"
3004 [(set (match_operand:SI 0 "register_operand" "=r")
3005 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
3008 "movmskpd\t{%1, %0|%0, %1}"
3009 [(set_attr "type" "ssecvt")
3010 (set_attr "mode" "V2DF")])
3012 (define_insn "sse2_pmovmskb"
3013 [(set (match_operand:SI 0 "register_operand" "=r")
3014 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
3017 "pmovmskb\t{%1, %0|%0, %1}"
3018 [(set_attr "type" "ssecvt")
3019 (set_attr "mode" "V2DF")])
3021 (define_expand "sse2_maskmovdqu"
3022 [(set (match_operand:V16QI 0 "memory_operand" "")
3023 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
3024 (match_operand:V16QI 2 "register_operand" "x")
3030 (define_insn "*sse2_maskmovdqu"
3031 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
3032 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
3033 (match_operand:V16QI 2 "register_operand" "x")
3034 (mem:V16QI (match_dup 0))]
3036 "TARGET_SSE2 && !TARGET_64BIT"
3037 ;; @@@ check ordering of operands in intel/nonintel syntax
3038 "maskmovdqu\t{%2, %1|%1, %2}"
3039 [(set_attr "type" "ssecvt")
3040 (set_attr "mode" "TI")])
3042 (define_insn "*sse2_maskmovdqu_rex64"
3043 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
3044 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
3045 (match_operand:V16QI 2 "register_operand" "x")
3046 (mem:V16QI (match_dup 0))]
3048 "TARGET_SSE2 && TARGET_64BIT"
3049 ;; @@@ check ordering of operands in intel/nonintel syntax
3050 "maskmovdqu\t{%2, %1|%1, %2}"
3051 [(set_attr "type" "ssecvt")
3052 (set_attr "mode" "TI")])
3054 (define_insn "sse_ldmxcsr"
3055 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
3059 [(set_attr "type" "sse")
3060 (set_attr "memory" "load")])
3062 (define_insn "sse_stmxcsr"
3063 [(set (match_operand:SI 0 "memory_operand" "=m")
3064 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
3067 [(set_attr "type" "sse")
3068 (set_attr "memory" "store")])
3070 (define_expand "sse_sfence"
3072 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
3073 "TARGET_SSE || TARGET_3DNOW_A"
3075 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
3076 MEM_VOLATILE_P (operands[0]) = 1;
3079 (define_insn "*sse_sfence"
3080 [(set (match_operand:BLK 0 "" "")
3081 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
3082 "TARGET_SSE || TARGET_3DNOW_A"
3084 [(set_attr "type" "sse")
3085 (set_attr "memory" "unknown")])
3087 (define_insn "sse2_clflush"
3088 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
3092 [(set_attr "type" "sse")
3093 (set_attr "memory" "unknown")])
3095 (define_expand "sse2_mfence"
3097 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
3100 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
3101 MEM_VOLATILE_P (operands[0]) = 1;
3104 (define_insn "*sse2_mfence"
3105 [(set (match_operand:BLK 0 "" "")
3106 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
3109 [(set_attr "type" "sse")
3110 (set_attr "memory" "unknown")])
3112 (define_expand "sse2_lfence"
3114 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
3117 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
3118 MEM_VOLATILE_P (operands[0]) = 1;
3121 (define_insn "*sse2_lfence"
3122 [(set (match_operand:BLK 0 "" "")
3123 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
3126 [(set_attr "type" "sse")
3127 (set_attr "memory" "unknown")])
3129 (define_insn "sse3_mwait"
3130 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
3131 (match_operand:SI 1 "register_operand" "c")]
3135 [(set_attr "length" "3")])
3137 (define_insn "sse3_monitor"
3138 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
3139 (match_operand:SI 1 "register_operand" "c")
3140 (match_operand:SI 2 "register_operand" "d")]
3143 "monitor\t%0, %1, %2"
3144 [(set_attr "length" "3")])