1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Return true if OP is either a i387 or SSE fp register.
22 (define_predicate "any_fp_register_operand"
23 (and (match_code "reg")
24 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
26 ;; Return true if OP is an i387 fp register.
27 (define_predicate "fp_register_operand"
28 (and (match_code "reg")
29 (match_test "FP_REGNO_P (REGNO (op))")))
31 ;; Return true if OP is a non-fp register_operand.
32 (define_predicate "register_and_not_any_fp_reg_operand"
33 (and (match_code "reg")
34 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
36 ;; Return true if OP is a register operand other than an i387 fp register.
37 (define_predicate "register_and_not_fp_reg_operand"
38 (and (match_code "reg")
39 (not (match_test "FP_REGNO_P (REGNO (op))"))))
41 ;; True if the operand is an MMX register.
42 (define_predicate "mmx_reg_operand"
43 (and (match_code "reg")
44 (match_test "MMX_REGNO_P (REGNO (op))")))
46 ;; True if the operand is an SSE register.
47 (define_predicate "sse_reg_operand"
48 (and (match_code "reg")
49 (match_test "SSE_REGNO_P (REGNO (op))")))
51 ;; True if the operand is a Q_REGS class register.
52 (define_predicate "q_regs_operand"
53 (match_operand 0 "register_operand")
55 if (GET_CODE (op) == SUBREG)
57 return ANY_QI_REG_P (op);
60 ;; Match an SI or HImode register for a zero_extract.
61 (define_special_predicate "ext_register_operand"
62 (match_operand 0 "register_operand")
64 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
65 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
67 if (GET_CODE (op) == SUBREG)
70 /* Be careful to accept only registers having upper parts. */
72 && (REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) <= BX_REG));
75 ;; Return true if op is the AX register.
76 (define_predicate "ax_reg_operand"
77 (and (match_code "reg")
78 (match_test "REGNO (op) == AX_REG")))
80 ;; Return true if op is the flags register.
81 (define_predicate "flags_reg_operand"
82 (and (match_code "reg")
83 (match_test "REGNO (op) == FLAGS_REG")))
85 ;; Return true if op is one of QImode registers: %[abcd][hl].
86 (define_predicate "QIreg_operand"
87 (match_test "QI_REG_P (op)"))
89 ;; Return true if op is a QImode register operand other than
91 (define_predicate "ext_QIreg_operand"
92 (and (match_code "reg")
93 (match_test "TARGET_64BIT")
94 (match_test "REGNO (op) > BX_REG")))
96 ;; Return true if op is not xmm0 register.
97 (define_predicate "reg_not_xmm0_operand"
98 (match_operand 0 "register_operand")
100 if (GET_CODE (op) == SUBREG)
101 op = SUBREG_REG (op);
103 return !REG_P (op) || REGNO (op) != FIRST_SSE_REG;
106 ;; As above, but also allow memory operands.
107 (define_predicate "nonimm_not_xmm0_operand"
108 (ior (match_operand 0 "memory_operand")
109 (match_operand 0 "reg_not_xmm0_operand")))
111 ;; Return true if op is not xmm0 register, but only for non-AVX targets.
112 (define_predicate "reg_not_xmm0_operand_maybe_avx"
113 (if_then_else (match_test "TARGET_AVX")
114 (match_operand 0 "register_operand")
115 (match_operand 0 "reg_not_xmm0_operand")))
117 ;; As above, but also allow memory operands.
118 (define_predicate "nonimm_not_xmm0_operand_maybe_avx"
119 (if_then_else (match_test "TARGET_AVX")
120 (match_operand 0 "nonimmediate_operand")
121 (match_operand 0 "nonimm_not_xmm0_operand")))
123 ;; Return true if VALUE can be stored in a sign extended immediate field.
124 (define_predicate "x86_64_immediate_operand"
125 (match_code "const_int,symbol_ref,label_ref,const")
128 return immediate_operand (op, mode);
130 switch (GET_CODE (op))
133 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
134 to be at least 32 and this all acceptable constants are
135 represented as CONST_INT. */
136 if (HOST_BITS_PER_WIDE_INT == 32)
140 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
141 return trunc_int_for_mode (val, SImode) == val;
146 /* For certain code models, the symbolic references are known to fit.
147 in CM_SMALL_PIC model we know it fits if it is local to the shared
148 library. Don't count TLS SYMBOL_REFs here, since they should fit
149 only if inside of UNSPEC handled below. */
150 /* TLS symbols are not constant. */
151 if (SYMBOL_REF_TLS_MODEL (op))
153 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
154 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
157 /* For certain code models, the code is near as well. */
158 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
159 || ix86_cmodel == CM_KERNEL);
162 /* We also may accept the offsetted memory references in certain
164 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
165 switch (XINT (XEXP (op, 0), 1))
167 case UNSPEC_GOTPCREL:
169 case UNSPEC_GOTNTPOFF:
176 if (GET_CODE (XEXP (op, 0)) == PLUS)
178 rtx op1 = XEXP (XEXP (op, 0), 0);
179 rtx op2 = XEXP (XEXP (op, 0), 1);
180 HOST_WIDE_INT offset;
182 if (ix86_cmodel == CM_LARGE)
184 if (!CONST_INT_P (op2))
186 offset = trunc_int_for_mode (INTVAL (op2), DImode);
187 switch (GET_CODE (op1))
190 /* TLS symbols are not constant. */
191 if (SYMBOL_REF_TLS_MODEL (op1))
193 /* For CM_SMALL assume that latest object is 16MB before
194 end of 31bits boundary. We may also accept pretty
195 large negative constants knowing that all objects are
196 in the positive half of address space. */
197 if ((ix86_cmodel == CM_SMALL
198 || (ix86_cmodel == CM_MEDIUM
199 && !SYMBOL_REF_FAR_ADDR_P (op1)))
200 && offset < 16*1024*1024
201 && trunc_int_for_mode (offset, SImode) == offset)
203 /* For CM_KERNEL we know that all object resist in the
204 negative half of 32bits address space. We may not
205 accept negative offsets, since they may be just off
206 and we may accept pretty large positive ones. */
207 if (ix86_cmodel == CM_KERNEL
209 && trunc_int_for_mode (offset, SImode) == offset)
214 /* These conditions are similar to SYMBOL_REF ones, just the
215 constraints for code models differ. */
216 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
217 && offset < 16*1024*1024
218 && trunc_int_for_mode (offset, SImode) == offset)
220 if (ix86_cmodel == CM_KERNEL
222 && trunc_int_for_mode (offset, SImode) == offset)
227 switch (XINT (op1, 1))
232 && trunc_int_for_mode (offset, SImode) == offset)
250 ;; Return true if VALUE can be stored in the zero extended immediate field.
251 (define_predicate "x86_64_zext_immediate_operand"
252 (match_code "const_double,const_int,symbol_ref,label_ref,const")
254 switch (GET_CODE (op))
257 if (HOST_BITS_PER_WIDE_INT == 32)
258 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
263 if (HOST_BITS_PER_WIDE_INT == 32)
264 return INTVAL (op) >= 0;
266 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
269 /* For certain code models, the symbolic references are known to fit. */
270 /* TLS symbols are not constant. */
271 if (SYMBOL_REF_TLS_MODEL (op))
273 return (ix86_cmodel == CM_SMALL
274 || (ix86_cmodel == CM_MEDIUM
275 && !SYMBOL_REF_FAR_ADDR_P (op)));
278 /* For certain code models, the code is near as well. */
279 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
282 /* We also may accept the offsetted memory references in certain
284 if (GET_CODE (XEXP (op, 0)) == PLUS)
286 rtx op1 = XEXP (XEXP (op, 0), 0);
287 rtx op2 = XEXP (XEXP (op, 0), 1);
289 if (ix86_cmodel == CM_LARGE)
291 switch (GET_CODE (op1))
294 /* TLS symbols are not constant. */
295 if (SYMBOL_REF_TLS_MODEL (op1))
297 /* For small code model we may accept pretty large positive
298 offsets, since one bit is available for free. Negative
299 offsets are limited by the size of NULL pointer area
300 specified by the ABI. */
301 if ((ix86_cmodel == CM_SMALL
302 || (ix86_cmodel == CM_MEDIUM
303 && !SYMBOL_REF_FAR_ADDR_P (op1)))
305 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
306 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
308 /* ??? For the kernel, we may accept adjustment of
309 -0x10000000, since we know that it will just convert
310 negative address space to positive, but perhaps this
311 is not worthwhile. */
315 /* These conditions are similar to SYMBOL_REF ones, just the
316 constraints for code models differ. */
317 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
319 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
320 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
336 ;; Return true if OP is general operand representable on x86_64.
337 (define_predicate "x86_64_general_operand"
338 (if_then_else (match_test "TARGET_64BIT")
339 (ior (match_operand 0 "nonimmediate_operand")
340 (match_operand 0 "x86_64_immediate_operand"))
341 (match_operand 0 "general_operand")))
343 ;; Return true if OP is general operand representable on x86_64
344 ;; as either sign extended or zero extended constant.
345 (define_predicate "x86_64_szext_general_operand"
346 (if_then_else (match_test "TARGET_64BIT")
347 (ior (match_operand 0 "nonimmediate_operand")
348 (match_operand 0 "x86_64_immediate_operand")
349 (match_operand 0 "x86_64_zext_immediate_operand"))
350 (match_operand 0 "general_operand")))
352 ;; Return true if OP is nonmemory operand representable on x86_64.
353 (define_predicate "x86_64_nonmemory_operand"
354 (if_then_else (match_test "TARGET_64BIT")
355 (ior (match_operand 0 "register_operand")
356 (match_operand 0 "x86_64_immediate_operand"))
357 (match_operand 0 "nonmemory_operand")))
359 ;; Return true if OP is nonmemory operand representable on x86_64.
360 (define_predicate "x86_64_szext_nonmemory_operand"
361 (if_then_else (match_test "TARGET_64BIT")
362 (ior (match_operand 0 "register_operand")
363 (match_operand 0 "x86_64_immediate_operand")
364 (match_operand 0 "x86_64_zext_immediate_operand"))
365 (match_operand 0 "nonmemory_operand")))
367 ;; Return true when operand is PIC expression that can be computed by lea
369 (define_predicate "pic_32bit_operand"
370 (match_code "const,symbol_ref,label_ref")
375 /* Rule out relocations that translate into 64bit constants. */
376 if (TARGET_64BIT && GET_CODE (op) == CONST)
379 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
381 if (GET_CODE (op) == UNSPEC
382 && (XINT (op, 1) == UNSPEC_GOTOFF
383 || XINT (op, 1) == UNSPEC_GOT))
387 return symbolic_operand (op, mode);
390 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
391 (define_predicate "x86_64_movabs_operand"
392 (and (match_operand 0 "nonmemory_operand")
393 (not (match_operand 0 "pic_32bit_operand"))))
395 ;; Return true if OP is either a symbol reference or a sum of a symbol
396 ;; reference and a constant.
397 (define_predicate "symbolic_operand"
398 (match_code "symbol_ref,label_ref,const")
400 switch (GET_CODE (op))
408 if (GET_CODE (op) == SYMBOL_REF
409 || GET_CODE (op) == LABEL_REF
410 || (GET_CODE (op) == UNSPEC
411 && (XINT (op, 1) == UNSPEC_GOT
412 || XINT (op, 1) == UNSPEC_GOTOFF
413 || XINT (op, 1) == UNSPEC_GOTPCREL)))
415 if (GET_CODE (op) != PLUS
416 || !CONST_INT_P (XEXP (op, 1)))
420 if (GET_CODE (op) == SYMBOL_REF
421 || GET_CODE (op) == LABEL_REF)
423 /* Only @GOTOFF gets offsets. */
424 if (GET_CODE (op) != UNSPEC
425 || XINT (op, 1) != UNSPEC_GOTOFF)
428 op = XVECEXP (op, 0, 0);
429 if (GET_CODE (op) == SYMBOL_REF
430 || GET_CODE (op) == LABEL_REF)
439 ;; Return true if OP is a symbolic operand that resolves locally.
440 (define_predicate "local_symbolic_operand"
441 (match_code "const,label_ref,symbol_ref")
443 if (GET_CODE (op) == CONST
444 && GET_CODE (XEXP (op, 0)) == PLUS
445 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
446 op = XEXP (XEXP (op, 0), 0);
448 if (GET_CODE (op) == LABEL_REF)
451 if (GET_CODE (op) != SYMBOL_REF)
454 if (SYMBOL_REF_TLS_MODEL (op))
457 if (SYMBOL_REF_LOCAL_P (op))
460 /* There is, however, a not insubstantial body of code in the rest of
461 the compiler that assumes it can just stick the results of
462 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
463 /* ??? This is a hack. Should update the body of the compiler to
464 always create a DECL an invoke targetm.encode_section_info. */
465 if (strncmp (XSTR (op, 0), internal_label_prefix,
466 internal_label_prefix_len) == 0)
472 ;; Test for a legitimate @GOTOFF operand.
474 ;; VxWorks does not impose a fixed gap between segments; the run-time
475 ;; gap can be different from the object-file gap. We therefore can't
476 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
477 ;; same segment as the GOT. Unfortunately, the flexibility of linker
478 ;; scripts means that we can't be sure of that in general, so assume
479 ;; that @GOTOFF is never valid on VxWorks.
480 (define_predicate "gotoff_operand"
481 (and (not (match_test "TARGET_VXWORKS_RTP"))
482 (match_operand 0 "local_symbolic_operand")))
484 ;; Test for various thread-local symbols.
485 (define_predicate "tls_symbolic_operand"
486 (and (match_code "symbol_ref")
487 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
489 (define_predicate "tls_modbase_operand"
490 (and (match_code "symbol_ref")
491 (match_test "op == ix86_tls_module_base ()")))
493 ;; Test for a pc-relative call operand
494 (define_predicate "constant_call_address_operand"
495 (match_code "symbol_ref")
497 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
499 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
504 ;; P6 processors will jump to the address after the decrement when %esp
505 ;; is used as a call operand, so they will execute return address as a code.
506 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
508 (define_predicate "call_register_no_elim_operand"
509 (match_operand 0 "register_operand")
511 if (GET_CODE (op) == SUBREG)
512 op = SUBREG_REG (op);
514 if (!TARGET_64BIT && op == stack_pointer_rtx)
517 return register_no_elim_operand (op, mode);
520 ;; True for any non-virtual or eliminable register. Used in places where
521 ;; instantiation of such a register may cause the pattern to not be recognized.
522 (define_predicate "register_no_elim_operand"
523 (match_operand 0 "register_operand")
525 if (GET_CODE (op) == SUBREG)
526 op = SUBREG_REG (op);
527 return !(op == arg_pointer_rtx
528 || op == frame_pointer_rtx
529 || IN_RANGE (REGNO (op),
530 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
533 ;; Similarly, but include the stack pointer. This is used to prevent esp
534 ;; from being used as an index reg.
535 (define_predicate "index_register_operand"
536 (match_operand 0 "register_operand")
538 if (GET_CODE (op) == SUBREG)
539 op = SUBREG_REG (op);
540 if (reload_in_progress || reload_completed)
541 return REG_OK_FOR_INDEX_STRICT_P (op);
543 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
546 ;; Return false if this is any eliminable register. Otherwise general_operand.
547 (define_predicate "general_no_elim_operand"
548 (if_then_else (match_code "reg,subreg")
549 (match_operand 0 "register_no_elim_operand")
550 (match_operand 0 "general_operand")))
552 ;; Return false if this is any eliminable register. Otherwise
553 ;; register_operand or a constant.
554 (define_predicate "nonmemory_no_elim_operand"
555 (ior (match_operand 0 "register_no_elim_operand")
556 (match_operand 0 "immediate_operand")))
558 ;; Test for a valid operand for indirect branch.
559 (define_predicate "indirect_branch_operand"
560 (if_then_else (match_test "TARGET_X32")
561 (match_operand 0 "register_operand")
562 (match_operand 0 "nonimmediate_operand")))
564 ;; Test for a valid operand for a call instruction.
565 (define_predicate "call_insn_operand"
566 (ior (match_operand 0 "constant_call_address_operand")
567 (match_operand 0 "call_register_no_elim_operand")
568 (and (match_test "!TARGET_X32")
569 (match_operand 0 "memory_operand"))))
571 ;; Similarly, but for tail calls, in which we cannot allow memory references.
572 (define_predicate "sibcall_insn_operand"
573 (ior (match_operand 0 "constant_call_address_operand")
574 (match_operand 0 "register_no_elim_operand")))
576 ;; Match exactly zero.
577 (define_predicate "const0_operand"
578 (match_code "const_int,const_double,const_vector")
580 if (mode == VOIDmode)
581 mode = GET_MODE (op);
582 return op == CONST0_RTX (mode);
585 ;; Match exactly one.
586 (define_predicate "const1_operand"
587 (and (match_code "const_int")
588 (match_test "op == const1_rtx")))
590 ;; Match exactly eight.
591 (define_predicate "const8_operand"
592 (and (match_code "const_int")
593 (match_test "INTVAL (op) == 8")))
595 ;; Match exactly 128.
596 (define_predicate "const128_operand"
597 (and (match_code "const_int")
598 (match_test "INTVAL (op) == 128")))
600 ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
601 (define_predicate "const_32bit_mask"
602 (and (match_code "const_int")
603 (match_test "trunc_int_for_mode (INTVAL (op), DImode)
604 == (HOST_WIDE_INT) 0xffffffff")))
606 ;; Match 2, 4, or 8. Used for leal multiplicands.
607 (define_predicate "const248_operand"
608 (match_code "const_int")
610 HOST_WIDE_INT i = INTVAL (op);
611 return i == 2 || i == 4 || i == 8;
614 ;; Match 1, 2, 4, or 8
615 (define_predicate "const1248_operand"
616 (match_code "const_int")
618 HOST_WIDE_INT i = INTVAL (op);
619 return i == 1 || i == 2 || i == 4 || i == 8;
622 ;; Match 3, 5, or 9. Used for leal multiplicands.
623 (define_predicate "const359_operand"
624 (match_code "const_int")
626 HOST_WIDE_INT i = INTVAL (op);
627 return i == 3 || i == 5 || i == 9;
631 (define_predicate "const_0_to_1_operand"
632 (and (match_code "const_int")
633 (ior (match_test "op == const0_rtx")
634 (match_test "op == const1_rtx"))))
637 (define_predicate "const_0_to_3_operand"
638 (and (match_code "const_int")
639 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
642 (define_predicate "const_0_to_7_operand"
643 (and (match_code "const_int")
644 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
647 (define_predicate "const_0_to_15_operand"
648 (and (match_code "const_int")
649 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
652 (define_predicate "const_0_to_31_operand"
653 (and (match_code "const_int")
654 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
657 (define_predicate "const_0_to_63_operand"
658 (and (match_code "const_int")
659 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
662 (define_predicate "const_0_to_255_operand"
663 (and (match_code "const_int")
664 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
666 ;; Match (0 to 255) * 8
667 (define_predicate "const_0_to_255_mul_8_operand"
668 (match_code "const_int")
670 unsigned HOST_WIDE_INT val = INTVAL (op);
671 return val <= 255*8 && val % 8 == 0;
674 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
675 ;; for shift & compare patterns, as shifting by 0 does not change flags).
676 (define_predicate "const_1_to_31_operand"
677 (and (match_code "const_int")
678 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
680 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
681 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
682 (define_predicate "const_1_to_63_operand"
683 (and (match_code "const_int")
684 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
687 (define_predicate "const_2_to_3_operand"
688 (and (match_code "const_int")
689 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
692 (define_predicate "const_4_to_5_operand"
693 (and (match_code "const_int")
694 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
697 (define_predicate "const_4_to_7_operand"
698 (and (match_code "const_int")
699 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
702 (define_predicate "const_6_to_7_operand"
703 (and (match_code "const_int")
704 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
707 (define_predicate "const_8_to_11_operand"
708 (and (match_code "const_int")
709 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
712 (define_predicate "const_12_to_15_operand"
713 (and (match_code "const_int")
714 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
716 ;; True if this is a constant appropriate for an increment or decrement.
717 (define_predicate "incdec_operand"
718 (match_code "const_int")
720 /* On Pentium4, the inc and dec operations causes extra dependency on flag
721 registers, since carry flag is not set. */
722 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
724 return op == const1_rtx || op == constm1_rtx;
727 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
728 (define_predicate "reg_or_pm1_operand"
729 (ior (match_operand 0 "register_operand")
730 (and (match_code "const_int")
731 (ior (match_test "op == const1_rtx")
732 (match_test "op == constm1_rtx")))))
734 ;; True if OP is acceptable as operand of DImode shift expander.
735 (define_predicate "shiftdi_operand"
736 (if_then_else (match_test "TARGET_64BIT")
737 (match_operand 0 "nonimmediate_operand")
738 (match_operand 0 "register_operand")))
740 (define_predicate "ashldi_input_operand"
741 (if_then_else (match_test "TARGET_64BIT")
742 (match_operand 0 "nonimmediate_operand")
743 (match_operand 0 "reg_or_pm1_operand")))
745 ;; Return true if OP is a vector load from the constant pool with just
746 ;; the first element nonzero.
747 (define_predicate "zero_extended_scalar_load_operand"
751 op = maybe_get_pool_constant (op);
753 if (!(op && GET_CODE (op) == CONST_VECTOR))
756 n_elts = CONST_VECTOR_NUNITS (op);
758 for (n_elts--; n_elts > 0; n_elts--)
760 rtx elt = CONST_VECTOR_ELT (op, n_elts);
761 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
767 /* Return true if operand is a vector constant that is all ones. */
768 (define_predicate "vector_all_ones_operand"
769 (match_code "const_vector")
771 int nunits = GET_MODE_NUNITS (mode);
773 if (GET_CODE (op) == CONST_VECTOR
774 && CONST_VECTOR_NUNITS (op) == nunits)
777 for (i = 0; i < nunits; ++i)
779 rtx x = CONST_VECTOR_ELT (op, i);
780 if (x != constm1_rtx)
789 ; Return true when OP is operand acceptable for standard SSE move.
790 (define_predicate "vector_move_operand"
791 (ior (match_operand 0 "nonimmediate_operand")
792 (match_operand 0 "const0_operand")))
794 ;; Return true when OP is nonimmediate or standard SSE constant.
795 (define_predicate "nonimmediate_or_sse_const_operand"
796 (match_operand 0 "general_operand")
798 if (nonimmediate_operand (op, mode))
800 if (standard_sse_constant_p (op) > 0)
805 ;; Return true if OP is a register or a zero.
806 (define_predicate "reg_or_0_operand"
807 (ior (match_operand 0 "register_operand")
808 (match_operand 0 "const0_operand")))
810 ;; Return true if op if a valid address for LEA, and does not contain
811 ;; a segment override.
812 (define_predicate "lea_address_operand"
813 (match_operand 0 "address_operand")
815 struct ix86_address parts;
818 /* LEA handles zero-extend by itself. */
819 if (GET_CODE (op) == ZERO_EXTEND
820 || GET_CODE (op) == AND)
823 ok = ix86_decompose_address (op, &parts);
825 return parts.seg == SEG_DEFAULT;
828 ;; Return true if the rtx is known to be at least 32 bits aligned.
829 (define_predicate "aligned_operand"
830 (match_operand 0 "general_operand")
832 struct ix86_address parts;
835 /* Registers and immediate operands are always "aligned". */
839 /* All patterns using aligned_operand on memory operands ends up
840 in promoting memory operand to 64bit and thus causing memory mismatch. */
841 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
844 /* Don't even try to do any aligned optimizations with volatiles. */
845 if (MEM_VOLATILE_P (op))
848 if (MEM_ALIGN (op) >= 32)
853 /* Pushes and pops are only valid on the stack pointer. */
854 if (GET_CODE (op) == PRE_DEC
855 || GET_CODE (op) == POST_INC)
858 /* Decode the address. */
859 ok = ix86_decompose_address (op, &parts);
862 if (parts.base && GET_CODE (parts.base) == SUBREG)
863 parts.base = SUBREG_REG (parts.base);
864 if (parts.index && GET_CODE (parts.index) == SUBREG)
865 parts.index = SUBREG_REG (parts.index);
867 /* Look for some component that isn't known to be aligned. */
870 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
875 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
880 if (!CONST_INT_P (parts.disp)
881 || (INTVAL (parts.disp) & 3))
885 /* Didn't find one -- this must be an aligned address. */
889 ;; Return true if OP is memory operand with a displacement.
890 (define_predicate "memory_displacement_operand"
891 (match_operand 0 "memory_operand")
893 struct ix86_address parts;
896 ok = ix86_decompose_address (XEXP (op, 0), &parts);
898 return parts.disp != NULL_RTX;
901 ;; Return true if OP is memory operand with a displacement only.
902 (define_predicate "memory_displacement_only_operand"
903 (match_operand 0 "memory_operand")
905 struct ix86_address parts;
911 ok = ix86_decompose_address (XEXP (op, 0), &parts);
914 if (parts.base || parts.index)
917 return parts.disp != NULL_RTX;
920 ;; Return true if OP is memory operand which will need zero or
921 ;; one register at most, not counting stack pointer or frame pointer.
922 (define_predicate "cmpxchg8b_pic_memory_operand"
923 (match_operand 0 "memory_operand")
925 struct ix86_address parts;
928 ok = ix86_decompose_address (XEXP (op, 0), &parts);
931 if (parts.base && GET_CODE (parts.base) == SUBREG)
932 parts.base = SUBREG_REG (parts.base);
933 if (parts.index && GET_CODE (parts.index) == SUBREG)
934 parts.index = SUBREG_REG (parts.index);
936 if (parts.base == NULL_RTX
937 || parts.base == arg_pointer_rtx
938 || parts.base == frame_pointer_rtx
939 || parts.base == hard_frame_pointer_rtx
940 || parts.base == stack_pointer_rtx)
943 if (parts.index == NULL_RTX
944 || parts.index == arg_pointer_rtx
945 || parts.index == frame_pointer_rtx
946 || parts.index == hard_frame_pointer_rtx
947 || parts.index == stack_pointer_rtx)
954 ;; Return true if OP is memory operand that cannot be represented
955 ;; by the modRM array.
956 (define_predicate "long_memory_operand"
957 (and (match_operand 0 "memory_operand")
958 (match_test "memory_address_length (op)")))
960 ;; Return true if OP is a comparison operator that can be issued by fcmov.
961 (define_predicate "fcmov_comparison_operator"
962 (match_operand 0 "comparison_operator")
964 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
965 enum rtx_code code = GET_CODE (op);
967 if (inmode == CCFPmode || inmode == CCFPUmode)
969 if (!ix86_trivial_fp_comparison_operator (op, mode))
971 code = ix86_fp_compare_code_to_integer (code);
973 /* i387 supports just limited amount of conditional codes. */
976 case LTU: case GTU: case LEU: case GEU:
977 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
978 || inmode == CCCmode)
981 case ORDERED: case UNORDERED:
989 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
990 ;; The first set are supported directly; the second set can't be done with
991 ;; full IEEE support, i.e. NaNs.
993 (define_predicate "sse_comparison_operator"
994 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
995 (and (match_test "TARGET_AVX")
996 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
998 (define_predicate "ix86_comparison_int_operator"
999 (match_code "ne,eq,ge,gt,le,lt"))
1001 (define_predicate "ix86_comparison_uns_operator"
1002 (match_code "ne,eq,geu,gtu,leu,ltu"))
1004 (define_predicate "bt_comparison_operator"
1005 (match_code "ne,eq"))
1007 ;; Return true if OP is a valid comparison operator in valid mode.
1008 (define_predicate "ix86_comparison_operator"
1009 (match_operand 0 "comparison_operator")
1011 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1012 enum rtx_code code = GET_CODE (op);
1014 if (inmode == CCFPmode || inmode == CCFPUmode)
1015 return ix86_trivial_fp_comparison_operator (op, mode);
1022 if (inmode == CCmode || inmode == CCGCmode
1023 || inmode == CCGOCmode || inmode == CCNOmode)
1026 case LTU: case GTU: case LEU: case GEU:
1027 if (inmode == CCmode || inmode == CCCmode)
1030 case ORDERED: case UNORDERED:
1031 if (inmode == CCmode)
1035 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1043 ;; Return true if OP is a valid comparison operator
1044 ;; testing carry flag to be set.
1045 (define_predicate "ix86_carry_flag_operator"
1046 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1048 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1049 enum rtx_code code = GET_CODE (op);
1051 if (inmode == CCFPmode || inmode == CCFPUmode)
1053 if (!ix86_trivial_fp_comparison_operator (op, mode))
1055 code = ix86_fp_compare_code_to_integer (code);
1057 else if (inmode == CCCmode)
1058 return code == LTU || code == GTU;
1059 else if (inmode != CCmode)
1065 ;; Return true if this comparison only requires testing one flag bit.
1066 (define_predicate "ix86_trivial_fp_comparison_operator"
1067 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1069 ;; Return true if we know how to do this comparison. Others require
1070 ;; testing more than one flag bit, and we let the generic middle-end
1072 (define_predicate "ix86_fp_comparison_operator"
1073 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1074 == IX86_FPCMP_ARITH")
1075 (match_operand 0 "comparison_operator")
1076 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1078 ;; Same as above, but for swapped comparison used in fp_jcc_4_387.
1079 (define_predicate "ix86_swapped_fp_comparison_operator"
1080 (match_operand 0 "comparison_operator")
1082 enum rtx_code code = GET_CODE (op);
1085 PUT_CODE (op, swap_condition (code));
1086 ret = ix86_fp_comparison_operator (op, mode);
1087 PUT_CODE (op, code);
1091 ;; Nearly general operand, but accept any const_double, since we wish
1092 ;; to be able to drop them into memory rather than have them get pulled
1094 (define_predicate "cmp_fp_expander_operand"
1095 (ior (match_code "const_double")
1096 (match_operand 0 "general_operand")))
1098 ;; Return true if this is a valid binary floating-point operation.
1099 (define_predicate "binary_fp_operator"
1100 (match_code "plus,minus,mult,div"))
1102 ;; Return true if this is a multiply operation.
1103 (define_predicate "mult_operator"
1104 (match_code "mult"))
1106 ;; Return true if this is a division operation.
1107 (define_predicate "div_operator"
1110 ;; Return true if this is a plus, minus, and, ior or xor operation.
1111 (define_predicate "plusminuslogic_operator"
1112 (match_code "plus,minus,and,ior,xor"))
1114 ;; Return true if this is a float extend operation.
1115 (define_predicate "float_operator"
1116 (match_code "float"))
1118 ;; Return true for ARITHMETIC_P.
1119 (define_predicate "arith_or_logical_operator"
1120 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1121 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1123 ;; Return true for COMMUTATIVE_P.
1124 (define_predicate "commutative_operator"
1125 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1127 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1128 (define_predicate "promotable_binary_operator"
1129 (ior (match_code "plus,and,ior,xor,ashift")
1130 (and (match_code "mult")
1131 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1133 (define_predicate "compare_operator"
1134 (match_code "compare"))
1136 (define_predicate "absneg_operator"
1137 (match_code "abs,neg"))
1139 ;; Return true if OP is misaligned memory operand
1140 (define_predicate "misaligned_operand"
1141 (and (match_code "mem")
1142 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1144 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1145 (define_predicate "emms_operation"
1146 (match_code "parallel")
1150 if (XVECLEN (op, 0) != 17)
1153 for (i = 0; i < 8; i++)
1155 rtx elt = XVECEXP (op, 0, i+1);
1157 if (GET_CODE (elt) != CLOBBER
1158 || GET_CODE (SET_DEST (elt)) != REG
1159 || GET_MODE (SET_DEST (elt)) != XFmode
1160 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1163 elt = XVECEXP (op, 0, i+9);
1165 if (GET_CODE (elt) != CLOBBER
1166 || GET_CODE (SET_DEST (elt)) != REG
1167 || GET_MODE (SET_DEST (elt)) != DImode
1168 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1174 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1175 (define_predicate "vzeroall_operation"
1176 (match_code "parallel")
1178 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1180 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1183 for (i = 0; i < nregs; i++)
1185 rtx elt = XVECEXP (op, 0, i+1);
1187 if (GET_CODE (elt) != SET
1188 || GET_CODE (SET_DEST (elt)) != REG
1189 || GET_MODE (SET_DEST (elt)) != V8SImode
1190 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1191 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1197 ;; Return true if OP is a parallel for a vbroadcast permute.
1199 (define_predicate "avx_vbroadcast_operand"
1200 (and (match_code "parallel")
1201 (match_code "const_int" "a"))
1203 rtx elt = XVECEXP (op, 0, 0);
1204 int i, nelt = XVECLEN (op, 0);
1206 /* Don't bother checking there are the right number of operands,
1207 merely that they're all identical. */
1208 for (i = 1; i < nelt; ++i)
1209 if (XVECEXP (op, 0, i) != elt)