1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Return true if OP is either a i387 or SSE fp register.
22 (define_predicate "any_fp_register_operand"
23 (and (match_code "reg")
24 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
26 ;; Return true if OP is an i387 fp register.
27 (define_predicate "fp_register_operand"
28 (and (match_code "reg")
29 (match_test "FP_REGNO_P (REGNO (op))")))
31 ;; Return true if OP is a non-fp register_operand.
32 (define_predicate "register_and_not_any_fp_reg_operand"
33 (and (match_code "reg")
34 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
36 ;; Return true if OP is a register operand other than an i387 fp register.
37 (define_predicate "register_and_not_fp_reg_operand"
38 (and (match_code "reg")
39 (not (match_test "FP_REGNO_P (REGNO (op))"))))
41 ;; True if the operand is an MMX register.
42 (define_predicate "mmx_reg_operand"
43 (and (match_code "reg")
44 (match_test "MMX_REGNO_P (REGNO (op))")))
46 ;; True if the operand is an SSE register.
47 (define_predicate "sse_reg_operand"
48 (and (match_code "reg")
49 (match_test "SSE_REGNO_P (REGNO (op))")))
51 ;; True if the operand is a Q_REGS class register.
52 (define_predicate "q_regs_operand"
53 (match_operand 0 "register_operand")
55 if (GET_CODE (op) == SUBREG)
57 return ANY_QI_REG_P (op);
60 ;; Match an SI or HImode register for a zero_extract.
61 (define_special_predicate "ext_register_operand"
62 (match_operand 0 "register_operand")
64 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
65 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
67 if (GET_CODE (op) == SUBREG)
70 /* Be careful to accept only registers having upper parts. */
72 && (REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) <= BX_REG));
75 ;; Return true if op is the AX register.
76 (define_predicate "ax_reg_operand"
77 (and (match_code "reg")
78 (match_test "REGNO (op) == AX_REG")))
80 ;; Return true if op is the flags register.
81 (define_predicate "flags_reg_operand"
82 (and (match_code "reg")
83 (match_test "REGNO (op) == FLAGS_REG")))
85 ;; Return true if op is one of QImode registers: %[abcd][hl].
86 (define_predicate "QIreg_operand"
87 (match_test "QI_REG_P (op)"))
89 ;; Return true if op is a QImode register operand other than
91 (define_predicate "ext_QIreg_operand"
92 (and (match_code "reg")
93 (match_test "TARGET_64BIT")
94 (match_test "REGNO (op) > BX_REG")))
96 ;; Return true if op is not xmm0 register.
97 (define_predicate "reg_not_xmm0_operand"
98 (match_operand 0 "register_operand")
100 if (GET_CODE (op) == SUBREG)
101 op = SUBREG_REG (op);
103 return !REG_P (op) || REGNO (op) != FIRST_SSE_REG;
106 ;; As above, but also allow memory operands.
107 (define_predicate "nonimm_not_xmm0_operand"
108 (ior (match_operand 0 "memory_operand")
109 (match_operand 0 "reg_not_xmm0_operand")))
111 ;; Return true if op is not xmm0 register, but only for non-AVX targets.
112 (define_predicate "reg_not_xmm0_operand_maybe_avx"
113 (if_then_else (match_test "TARGET_AVX")
114 (match_operand 0 "register_operand")
115 (match_operand 0 "reg_not_xmm0_operand")))
117 ;; As above, but also allow memory operands.
118 (define_predicate "nonimm_not_xmm0_operand_maybe_avx"
119 (if_then_else (match_test "TARGET_AVX")
120 (match_operand 0 "nonimmediate_operand")
121 (match_operand 0 "nonimm_not_xmm0_operand")))
123 ;; Return true if VALUE can be stored in a sign extended immediate field.
124 (define_predicate "x86_64_immediate_operand"
125 (match_code "const_int,symbol_ref,label_ref,const")
128 return immediate_operand (op, mode);
130 switch (GET_CODE (op))
133 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
134 to be at least 32 and this all acceptable constants are
135 represented as CONST_INT. */
136 if (HOST_BITS_PER_WIDE_INT == 32)
140 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
141 return trunc_int_for_mode (val, SImode) == val;
146 /* For certain code models, the symbolic references are known to fit.
147 in CM_SMALL_PIC model we know it fits if it is local to the shared
148 library. Don't count TLS SYMBOL_REFs here, since they should fit
149 only if inside of UNSPEC handled below. */
150 /* TLS symbols are not constant. */
151 if (SYMBOL_REF_TLS_MODEL (op))
153 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
154 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
157 /* For certain code models, the code is near as well. */
158 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
159 || ix86_cmodel == CM_KERNEL);
162 /* We also may accept the offsetted memory references in certain
164 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
165 switch (XINT (XEXP (op, 0), 1))
167 case UNSPEC_GOTPCREL:
169 case UNSPEC_GOTNTPOFF:
176 if (GET_CODE (XEXP (op, 0)) == PLUS)
178 rtx op1 = XEXP (XEXP (op, 0), 0);
179 rtx op2 = XEXP (XEXP (op, 0), 1);
180 HOST_WIDE_INT offset;
182 if (ix86_cmodel == CM_LARGE)
184 if (!CONST_INT_P (op2))
186 offset = trunc_int_for_mode (INTVAL (op2), DImode);
187 switch (GET_CODE (op1))
190 /* TLS symbols are not constant. */
191 if (SYMBOL_REF_TLS_MODEL (op1))
193 /* For CM_SMALL assume that latest object is 16MB before
194 end of 31bits boundary. We may also accept pretty
195 large negative constants knowing that all objects are
196 in the positive half of address space. */
197 if ((ix86_cmodel == CM_SMALL
198 || (ix86_cmodel == CM_MEDIUM
199 && !SYMBOL_REF_FAR_ADDR_P (op1)))
200 && offset < 16*1024*1024
201 && trunc_int_for_mode (offset, SImode) == offset)
203 /* For CM_KERNEL we know that all object resist in the
204 negative half of 32bits address space. We may not
205 accept negative offsets, since they may be just off
206 and we may accept pretty large positive ones. */
207 if (ix86_cmodel == CM_KERNEL
209 && trunc_int_for_mode (offset, SImode) == offset)
214 /* These conditions are similar to SYMBOL_REF ones, just the
215 constraints for code models differ. */
216 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
217 && offset < 16*1024*1024
218 && trunc_int_for_mode (offset, SImode) == offset)
220 if (ix86_cmodel == CM_KERNEL
222 && trunc_int_for_mode (offset, SImode) == offset)
227 switch (XINT (op1, 1))
232 && trunc_int_for_mode (offset, SImode) == offset)
250 ;; Return true if VALUE can be stored in the zero extended immediate field.
251 (define_predicate "x86_64_zext_immediate_operand"
252 (match_code "const_double,const_int,symbol_ref,label_ref,const")
254 switch (GET_CODE (op))
257 if (HOST_BITS_PER_WIDE_INT == 32)
258 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
263 if (HOST_BITS_PER_WIDE_INT == 32)
264 return INTVAL (op) >= 0;
266 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
269 /* For certain code models, the symbolic references are known to fit. */
270 /* TLS symbols are not constant. */
271 if (SYMBOL_REF_TLS_MODEL (op))
273 return (ix86_cmodel == CM_SMALL
274 || (ix86_cmodel == CM_MEDIUM
275 && !SYMBOL_REF_FAR_ADDR_P (op)));
278 /* For certain code models, the code is near as well. */
279 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
282 /* We also may accept the offsetted memory references in certain
284 if (GET_CODE (XEXP (op, 0)) == PLUS)
286 rtx op1 = XEXP (XEXP (op, 0), 0);
287 rtx op2 = XEXP (XEXP (op, 0), 1);
289 if (ix86_cmodel == CM_LARGE)
291 switch (GET_CODE (op1))
294 /* TLS symbols are not constant. */
295 if (SYMBOL_REF_TLS_MODEL (op1))
297 /* For small code model we may accept pretty large positive
298 offsets, since one bit is available for free. Negative
299 offsets are limited by the size of NULL pointer area
300 specified by the ABI. */
301 if ((ix86_cmodel == CM_SMALL
302 || (ix86_cmodel == CM_MEDIUM
303 && !SYMBOL_REF_FAR_ADDR_P (op1)))
305 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
306 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
308 /* ??? For the kernel, we may accept adjustment of
309 -0x10000000, since we know that it will just convert
310 negative address space to positive, but perhaps this
311 is not worthwhile. */
315 /* These conditions are similar to SYMBOL_REF ones, just the
316 constraints for code models differ. */
317 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
319 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
320 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
336 ;; Return true if OP is general operand representable on x86_64.
337 (define_predicate "x86_64_general_operand"
338 (if_then_else (match_test "TARGET_64BIT")
339 (ior (match_operand 0 "nonimmediate_operand")
340 (match_operand 0 "x86_64_immediate_operand"))
341 (match_operand 0 "general_operand")))
343 ;; Return true if OP is general operand representable on x86_64
344 ;; as either sign extended or zero extended constant.
345 (define_predicate "x86_64_szext_general_operand"
346 (if_then_else (match_test "TARGET_64BIT")
347 (ior (match_operand 0 "nonimmediate_operand")
348 (match_operand 0 "x86_64_immediate_operand")
349 (match_operand 0 "x86_64_zext_immediate_operand"))
350 (match_operand 0 "general_operand")))
352 ;; Return true if OP is nonmemory operand representable on x86_64.
353 (define_predicate "x86_64_nonmemory_operand"
354 (if_then_else (match_test "TARGET_64BIT")
355 (ior (match_operand 0 "register_operand")
356 (match_operand 0 "x86_64_immediate_operand"))
357 (match_operand 0 "nonmemory_operand")))
359 ;; Return true if OP is nonmemory operand representable on x86_64.
360 (define_predicate "x86_64_szext_nonmemory_operand"
361 (if_then_else (match_test "TARGET_64BIT")
362 (ior (match_operand 0 "register_operand")
363 (match_operand 0 "x86_64_immediate_operand")
364 (match_operand 0 "x86_64_zext_immediate_operand"))
365 (match_operand 0 "nonmemory_operand")))
367 ;; Return true when operand is PIC expression that can be computed by lea
369 (define_predicate "pic_32bit_operand"
370 (match_code "const,symbol_ref,label_ref")
374 /* Rule out relocations that translate into 64bit constants. */
375 if (TARGET_64BIT && GET_CODE (op) == CONST)
378 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
380 if (GET_CODE (op) == UNSPEC
381 && (XINT (op, 1) == UNSPEC_GOTOFF
382 || XINT (op, 1) == UNSPEC_GOT))
385 return symbolic_operand (op, mode);
389 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
390 (define_predicate "x86_64_movabs_operand"
391 (if_then_else (not (and (match_test "TARGET_64BIT")
392 (match_test "flag_pic")))
393 (match_operand 0 "nonmemory_operand")
394 (ior (match_operand 0 "register_operand")
395 (and (match_operand 0 "const_double_operand")
396 (match_test "GET_MODE_SIZE (mode) <= 8")))))
398 ;; Return true if OP is either a symbol reference or a sum of a symbol
399 ;; reference and a constant.
400 (define_predicate "symbolic_operand"
401 (match_code "symbol_ref,label_ref,const")
403 switch (GET_CODE (op))
411 if (GET_CODE (op) == SYMBOL_REF
412 || GET_CODE (op) == LABEL_REF
413 || (GET_CODE (op) == UNSPEC
414 && (XINT (op, 1) == UNSPEC_GOT
415 || XINT (op, 1) == UNSPEC_GOTOFF
416 || XINT (op, 1) == UNSPEC_GOTPCREL)))
418 if (GET_CODE (op) != PLUS
419 || !CONST_INT_P (XEXP (op, 1)))
423 if (GET_CODE (op) == SYMBOL_REF
424 || GET_CODE (op) == LABEL_REF)
426 /* Only @GOTOFF gets offsets. */
427 if (GET_CODE (op) != UNSPEC
428 || XINT (op, 1) != UNSPEC_GOTOFF)
431 op = XVECEXP (op, 0, 0);
432 if (GET_CODE (op) == SYMBOL_REF
433 || GET_CODE (op) == LABEL_REF)
442 ;; Return true if OP is a symbolic operand that resolves locally.
443 (define_predicate "local_symbolic_operand"
444 (match_code "const,label_ref,symbol_ref")
446 if (GET_CODE (op) == CONST
447 && GET_CODE (XEXP (op, 0)) == PLUS
448 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
449 op = XEXP (XEXP (op, 0), 0);
451 if (GET_CODE (op) == LABEL_REF)
454 if (GET_CODE (op) != SYMBOL_REF)
457 if (SYMBOL_REF_TLS_MODEL (op))
460 if (SYMBOL_REF_LOCAL_P (op))
463 /* There is, however, a not insubstantial body of code in the rest of
464 the compiler that assumes it can just stick the results of
465 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
466 /* ??? This is a hack. Should update the body of the compiler to
467 always create a DECL an invoke targetm.encode_section_info. */
468 if (strncmp (XSTR (op, 0), internal_label_prefix,
469 internal_label_prefix_len) == 0)
475 ;; Test for a legitimate @GOTOFF operand.
477 ;; VxWorks does not impose a fixed gap between segments; the run-time
478 ;; gap can be different from the object-file gap. We therefore can't
479 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
480 ;; same segment as the GOT. Unfortunately, the flexibility of linker
481 ;; scripts means that we can't be sure of that in general, so assume
482 ;; that @GOTOFF is never valid on VxWorks.
483 (define_predicate "gotoff_operand"
484 (and (not (match_test "TARGET_VXWORKS_RTP"))
485 (match_operand 0 "local_symbolic_operand")))
487 ;; Test for various thread-local symbols.
488 (define_predicate "tls_symbolic_operand"
489 (and (match_code "symbol_ref")
490 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
492 (define_predicate "tls_modbase_operand"
493 (and (match_code "symbol_ref")
494 (match_test "op == ix86_tls_module_base ()")))
496 (define_predicate "tp_or_register_operand"
497 (ior (match_operand 0 "register_operand")
498 (and (match_code "unspec")
499 (match_test "XINT (op, 1) == UNSPEC_TP"))))
501 ;; Test for a pc-relative call operand
502 (define_predicate "constant_call_address_operand"
503 (match_code "symbol_ref")
505 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
507 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
512 ;; P6 processors will jump to the address after the decrement when %esp
513 ;; is used as a call operand, so they will execute return address as a code.
514 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
516 (define_predicate "call_register_no_elim_operand"
517 (match_operand 0 "register_operand")
519 if (GET_CODE (op) == SUBREG)
520 op = SUBREG_REG (op);
522 if (!TARGET_64BIT && op == stack_pointer_rtx)
525 return register_no_elim_operand (op, mode);
528 ;; True for any non-virtual or eliminable register. Used in places where
529 ;; instantiation of such a register may cause the pattern to not be recognized.
530 (define_predicate "register_no_elim_operand"
531 (match_operand 0 "register_operand")
533 if (GET_CODE (op) == SUBREG)
534 op = SUBREG_REG (op);
535 return !(op == arg_pointer_rtx
536 || op == frame_pointer_rtx
537 || IN_RANGE (REGNO (op),
538 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
541 ;; Similarly, but include the stack pointer. This is used to prevent esp
542 ;; from being used as an index reg.
543 (define_predicate "index_register_operand"
544 (match_operand 0 "register_operand")
546 if (GET_CODE (op) == SUBREG)
547 op = SUBREG_REG (op);
548 if (reload_in_progress || reload_completed)
549 return REG_OK_FOR_INDEX_STRICT_P (op);
551 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
554 ;; Return false if this is any eliminable register. Otherwise general_operand.
555 (define_predicate "general_no_elim_operand"
556 (if_then_else (match_code "reg,subreg")
557 (match_operand 0 "register_no_elim_operand")
558 (match_operand 0 "general_operand")))
560 ;; Return false if this is any eliminable register. Otherwise
561 ;; register_operand or a constant.
562 (define_predicate "nonmemory_no_elim_operand"
563 (ior (match_operand 0 "register_no_elim_operand")
564 (match_operand 0 "immediate_operand")))
566 ;; Test for a valid operand for a call instruction.
567 (define_predicate "call_insn_operand"
568 (ior (match_operand 0 "constant_call_address_operand")
569 (match_operand 0 "call_register_no_elim_operand")
570 (match_operand 0 "memory_operand")))
572 ;; Similarly, but for tail calls, in which we cannot allow memory references.
573 (define_predicate "sibcall_insn_operand"
574 (ior (match_operand 0 "constant_call_address_operand")
575 (match_operand 0 "register_no_elim_operand")))
577 ;; Match exactly zero.
578 (define_predicate "const0_operand"
579 (match_code "const_int,const_double,const_vector")
581 if (mode == VOIDmode)
582 mode = GET_MODE (op);
583 return op == CONST0_RTX (mode);
586 ;; Match exactly one.
587 (define_predicate "const1_operand"
588 (and (match_code "const_int")
589 (match_test "op == const1_rtx")))
591 ;; Match exactly eight.
592 (define_predicate "const8_operand"
593 (and (match_code "const_int")
594 (match_test "INTVAL (op) == 8")))
596 ;; Match exactly 128.
597 (define_predicate "const128_operand"
598 (and (match_code "const_int")
599 (match_test "INTVAL (op) == 128")))
601 ;; Match 2, 4, or 8. Used for leal multiplicands.
602 (define_predicate "const248_operand"
603 (match_code "const_int")
605 HOST_WIDE_INT i = INTVAL (op);
606 return i == 2 || i == 4 || i == 8;
609 ;; Match 3, 5, or 9. Used for leal multiplicands.
610 (define_predicate "const359_operand"
611 (match_code "const_int")
613 HOST_WIDE_INT i = INTVAL (op);
614 return i == 3 || i == 5 || i == 9;
618 (define_predicate "const_0_to_1_operand"
619 (and (match_code "const_int")
620 (ior (match_test "op == const0_rtx")
621 (match_test "op == const1_rtx"))))
624 (define_predicate "const_0_to_3_operand"
625 (and (match_code "const_int")
626 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
629 (define_predicate "const_0_to_7_operand"
630 (and (match_code "const_int")
631 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
634 (define_predicate "const_0_to_15_operand"
635 (and (match_code "const_int")
636 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
639 (define_predicate "const_0_to_31_operand"
640 (and (match_code "const_int")
641 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
644 (define_predicate "const_0_to_63_operand"
645 (and (match_code "const_int")
646 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
649 (define_predicate "const_0_to_255_operand"
650 (and (match_code "const_int")
651 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
653 ;; Match (0 to 255) * 8
654 (define_predicate "const_0_to_255_mul_8_operand"
655 (match_code "const_int")
657 unsigned HOST_WIDE_INT val = INTVAL (op);
658 return val <= 255*8 && val % 8 == 0;
661 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
662 ;; for shift & compare patterns, as shifting by 0 does not change flags).
663 (define_predicate "const_1_to_31_operand"
664 (and (match_code "const_int")
665 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
667 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
668 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
669 (define_predicate "const_1_to_63_operand"
670 (and (match_code "const_int")
671 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
674 (define_predicate "const_2_to_3_operand"
675 (and (match_code "const_int")
676 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
679 (define_predicate "const_4_to_5_operand"
680 (and (match_code "const_int")
681 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
684 (define_predicate "const_4_to_7_operand"
685 (and (match_code "const_int")
686 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
689 (define_predicate "const_6_to_7_operand"
690 (and (match_code "const_int")
691 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
694 (define_predicate "const_8_to_11_operand"
695 (and (match_code "const_int")
696 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
699 (define_predicate "const_12_to_15_operand"
700 (and (match_code "const_int")
701 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
703 ;; True if this is a constant appropriate for an increment or decrement.
704 (define_predicate "incdec_operand"
705 (match_code "const_int")
707 /* On Pentium4, the inc and dec operations causes extra dependency on flag
708 registers, since carry flag is not set. */
709 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
711 return op == const1_rtx || op == constm1_rtx;
714 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
715 (define_predicate "reg_or_pm1_operand"
716 (ior (match_operand 0 "register_operand")
717 (and (match_code "const_int")
718 (ior (match_test "op == const1_rtx")
719 (match_test "op == constm1_rtx")))))
721 ;; True if OP is acceptable as operand of DImode shift expander.
722 (define_predicate "shiftdi_operand"
723 (if_then_else (match_test "TARGET_64BIT")
724 (match_operand 0 "nonimmediate_operand")
725 (match_operand 0 "register_operand")))
727 (define_predicate "ashldi_input_operand"
728 (if_then_else (match_test "TARGET_64BIT")
729 (match_operand 0 "nonimmediate_operand")
730 (match_operand 0 "reg_or_pm1_operand")))
732 ;; Return true if OP is a vector load from the constant pool with just
733 ;; the first element nonzero.
734 (define_predicate "zero_extended_scalar_load_operand"
738 op = maybe_get_pool_constant (op);
740 if (!(op && GET_CODE (op) == CONST_VECTOR))
743 n_elts = CONST_VECTOR_NUNITS (op);
745 for (n_elts--; n_elts > 0; n_elts--)
747 rtx elt = CONST_VECTOR_ELT (op, n_elts);
748 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
754 /* Return true if operand is a vector constant that is all ones. */
755 (define_predicate "vector_all_ones_operand"
756 (match_code "const_vector")
758 int nunits = GET_MODE_NUNITS (mode);
760 if (GET_CODE (op) == CONST_VECTOR
761 && CONST_VECTOR_NUNITS (op) == nunits)
764 for (i = 0; i < nunits; ++i)
766 rtx x = CONST_VECTOR_ELT (op, i);
767 if (x != constm1_rtx)
776 ; Return true when OP is operand acceptable for standard SSE move.
777 (define_predicate "vector_move_operand"
778 (ior (match_operand 0 "nonimmediate_operand")
779 (match_operand 0 "const0_operand")))
781 ;; Return true when OP is nonimmediate or standard SSE constant.
782 (define_predicate "nonimmediate_or_sse_const_operand"
783 (match_operand 0 "general_operand")
785 if (nonimmediate_operand (op, mode))
787 if (standard_sse_constant_p (op) > 0)
792 ;; Return true if OP is a register or a zero.
793 (define_predicate "reg_or_0_operand"
794 (ior (match_operand 0 "register_operand")
795 (match_operand 0 "const0_operand")))
797 ;; Return true if op if a valid address, and does not contain
798 ;; a segment override.
799 (define_predicate "no_seg_address_operand"
800 (match_operand 0 "address_operand")
802 struct ix86_address parts;
805 ok = ix86_decompose_address (op, &parts);
807 return parts.seg == SEG_DEFAULT;
810 ;; Return true if the rtx is known to be at least 32 bits aligned.
811 (define_predicate "aligned_operand"
812 (match_operand 0 "general_operand")
814 struct ix86_address parts;
817 /* Registers and immediate operands are always "aligned". */
821 /* All patterns using aligned_operand on memory operands ends up
822 in promoting memory operand to 64bit and thus causing memory mismatch. */
823 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
826 /* Don't even try to do any aligned optimizations with volatiles. */
827 if (MEM_VOLATILE_P (op))
830 if (MEM_ALIGN (op) >= 32)
835 /* Pushes and pops are only valid on the stack pointer. */
836 if (GET_CODE (op) == PRE_DEC
837 || GET_CODE (op) == POST_INC)
840 /* Decode the address. */
841 ok = ix86_decompose_address (op, &parts);
844 /* Look for some component that isn't known to be aligned. */
847 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
852 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
857 if (!CONST_INT_P (parts.disp)
858 || (INTVAL (parts.disp) & 3))
862 /* Didn't find one -- this must be an aligned address. */
866 ;; Return true if OP is memory operand with a displacement.
867 (define_predicate "memory_displacement_operand"
868 (match_operand 0 "memory_operand")
870 struct ix86_address parts;
873 ok = ix86_decompose_address (XEXP (op, 0), &parts);
875 return parts.disp != NULL_RTX;
878 ;; Return true if OP is memory operand with a displacement only.
879 (define_predicate "memory_displacement_only_operand"
880 (match_operand 0 "memory_operand")
882 struct ix86_address parts;
888 ok = ix86_decompose_address (XEXP (op, 0), &parts);
891 if (parts.base || parts.index)
894 return parts.disp != NULL_RTX;
897 ;; Return true if OP is memory operand which will need zero or
898 ;; one register at most, not counting stack pointer or frame pointer.
899 (define_predicate "cmpxchg8b_pic_memory_operand"
900 (match_operand 0 "memory_operand")
902 struct ix86_address parts;
905 ok = ix86_decompose_address (XEXP (op, 0), &parts);
907 if (parts.base == NULL_RTX
908 || parts.base == arg_pointer_rtx
909 || parts.base == frame_pointer_rtx
910 || parts.base == hard_frame_pointer_rtx
911 || parts.base == stack_pointer_rtx)
914 if (parts.index == NULL_RTX
915 || parts.index == arg_pointer_rtx
916 || parts.index == frame_pointer_rtx
917 || parts.index == hard_frame_pointer_rtx
918 || parts.index == stack_pointer_rtx)
925 ;; Return true if OP is memory operand that cannot be represented
926 ;; by the modRM array.
927 (define_predicate "long_memory_operand"
928 (and (match_operand 0 "memory_operand")
929 (match_test "memory_address_length (op)")))
931 ;; Return true if OP is a comparison operator that can be issued by fcmov.
932 (define_predicate "fcmov_comparison_operator"
933 (match_operand 0 "comparison_operator")
935 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
936 enum rtx_code code = GET_CODE (op);
938 if (inmode == CCFPmode || inmode == CCFPUmode)
940 if (!ix86_trivial_fp_comparison_operator (op, mode))
942 code = ix86_fp_compare_code_to_integer (code);
944 /* i387 supports just limited amount of conditional codes. */
947 case LTU: case GTU: case LEU: case GEU:
948 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
949 || inmode == CCCmode)
952 case ORDERED: case UNORDERED:
960 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
961 ;; The first set are supported directly; the second set can't be done with
962 ;; full IEEE support, i.e. NaNs.
964 (define_predicate "sse_comparison_operator"
965 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
966 (and (match_test "TARGET_AVX")
967 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
969 (define_predicate "ix86_comparison_int_operator"
970 (match_code "ne,eq,ge,gt,le,lt"))
972 (define_predicate "ix86_comparison_uns_operator"
973 (match_code "ne,eq,geu,gtu,leu,ltu"))
975 (define_predicate "bt_comparison_operator"
976 (match_code "ne,eq"))
978 ;; Return true if OP is a valid comparison operator in valid mode.
979 (define_predicate "ix86_comparison_operator"
980 (match_operand 0 "comparison_operator")
982 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
983 enum rtx_code code = GET_CODE (op);
985 if (inmode == CCFPmode || inmode == CCFPUmode)
986 return ix86_trivial_fp_comparison_operator (op, mode);
993 if (inmode == CCmode || inmode == CCGCmode
994 || inmode == CCGOCmode || inmode == CCNOmode)
997 case LTU: case GTU: case LEU: case GEU:
998 if (inmode == CCmode || inmode == CCCmode)
1001 case ORDERED: case UNORDERED:
1002 if (inmode == CCmode)
1006 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1014 ;; Return true if OP is a valid comparison operator
1015 ;; testing carry flag to be set.
1016 (define_predicate "ix86_carry_flag_operator"
1017 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1019 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1020 enum rtx_code code = GET_CODE (op);
1022 if (inmode == CCFPmode || inmode == CCFPUmode)
1024 if (!ix86_trivial_fp_comparison_operator (op, mode))
1026 code = ix86_fp_compare_code_to_integer (code);
1028 else if (inmode == CCCmode)
1029 return code == LTU || code == GTU;
1030 else if (inmode != CCmode)
1036 ;; Return true if this comparison only requires testing one flag bit.
1037 (define_predicate "ix86_trivial_fp_comparison_operator"
1038 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1040 ;; Return true if we know how to do this comparison. Others require
1041 ;; testing more than one flag bit, and we let the generic middle-end
1043 (define_predicate "ix86_fp_comparison_operator"
1044 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1045 == IX86_FPCMP_ARITH")
1046 (match_operand 0 "comparison_operator")
1047 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1049 ;; Same as above, but for swapped comparison used in fp_jcc_4_387.
1050 (define_predicate "ix86_swapped_fp_comparison_operator"
1051 (match_operand 0 "comparison_operator")
1053 enum rtx_code code = GET_CODE (op);
1056 PUT_CODE (op, swap_condition (code));
1057 ret = ix86_fp_comparison_operator (op, mode);
1058 PUT_CODE (op, code);
1062 ;; Nearly general operand, but accept any const_double, since we wish
1063 ;; to be able to drop them into memory rather than have them get pulled
1065 (define_predicate "cmp_fp_expander_operand"
1066 (ior (match_code "const_double")
1067 (match_operand 0 "general_operand")))
1069 ;; Return true if this is a valid binary floating-point operation.
1070 (define_predicate "binary_fp_operator"
1071 (match_code "plus,minus,mult,div"))
1073 ;; Return true if this is a multiply operation.
1074 (define_predicate "mult_operator"
1075 (match_code "mult"))
1077 ;; Return true if this is a division operation.
1078 (define_predicate "div_operator"
1081 ;; Return true if this is a plus, minus, and, ior or xor operation.
1082 (define_predicate "plusminuslogic_operator"
1083 (match_code "plus,minus,and,ior,xor"))
1085 ;; Return true if this is a float extend operation.
1086 (define_predicate "float_operator"
1087 (match_code "float"))
1089 ;; Return true for ARITHMETIC_P.
1090 (define_predicate "arith_or_logical_operator"
1091 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1092 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1094 ;; Return true for COMMUTATIVE_P.
1095 (define_predicate "commutative_operator"
1096 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1098 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1099 (define_predicate "promotable_binary_operator"
1100 (ior (match_code "plus,and,ior,xor,ashift")
1101 (and (match_code "mult")
1102 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1104 (define_predicate "compare_operator"
1105 (match_code "compare"))
1107 (define_predicate "absneg_operator"
1108 (match_code "abs,neg"))
1110 ;; Return true if OP is misaligned memory operand
1111 (define_predicate "misaligned_operand"
1112 (and (match_code "mem")
1113 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1115 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1116 (define_predicate "emms_operation"
1117 (match_code "parallel")
1121 if (XVECLEN (op, 0) != 17)
1124 for (i = 0; i < 8; i++)
1126 rtx elt = XVECEXP (op, 0, i+1);
1128 if (GET_CODE (elt) != CLOBBER
1129 || GET_CODE (SET_DEST (elt)) != REG
1130 || GET_MODE (SET_DEST (elt)) != XFmode
1131 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1134 elt = XVECEXP (op, 0, i+9);
1136 if (GET_CODE (elt) != CLOBBER
1137 || GET_CODE (SET_DEST (elt)) != REG
1138 || GET_MODE (SET_DEST (elt)) != DImode
1139 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1145 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1146 (define_predicate "vzeroall_operation"
1147 (match_code "parallel")
1149 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1151 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1154 for (i = 0; i < nregs; i++)
1156 rtx elt = XVECEXP (op, 0, i+1);
1158 if (GET_CODE (elt) != SET
1159 || GET_CODE (SET_DEST (elt)) != REG
1160 || GET_MODE (SET_DEST (elt)) != V8SImode
1161 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1162 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1168 ;; Return true if OP is a parallel for a vbroadcast permute.
1170 (define_predicate "avx_vbroadcast_operand"
1171 (and (match_code "parallel")
1172 (match_code "const_int" "a"))
1174 rtx elt = XVECEXP (op, 0, 0);
1175 int i, nelt = XVECLEN (op, 0);
1177 /* Don't bother checking there are the right number of operands,
1178 merely that they're all identical. */
1179 for (i = 1; i < nelt; ++i)
1180 if (XVECEXP (op, 0, i) != elt)