1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009, 2010
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; Return true if OP is either a i387 or SSE fp register.
22 (define_predicate "any_fp_register_operand"
23 (and (match_code "reg")
24 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
26 ;; Return true if OP is an i387 fp register.
27 (define_predicate "fp_register_operand"
28 (and (match_code "reg")
29 (match_test "FP_REGNO_P (REGNO (op))")))
31 ;; Return true if OP is a non-fp register_operand.
32 (define_predicate "register_and_not_any_fp_reg_operand"
33 (and (match_code "reg")
34 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
36 ;; Return true if OP is a register operand other than an i387 fp register.
37 (define_predicate "register_and_not_fp_reg_operand"
38 (and (match_code "reg")
39 (not (match_test "FP_REGNO_P (REGNO (op))"))))
41 ;; True if the operand is an MMX register.
42 (define_predicate "mmx_reg_operand"
43 (and (match_code "reg")
44 (match_test "MMX_REGNO_P (REGNO (op))")))
46 ;; True if the operand is an SSE register.
47 (define_predicate "sse_reg_operand"
48 (and (match_code "reg")
49 (match_test "SSE_REGNO_P (REGNO (op))")))
51 ;; True if the operand is a Q_REGS class register.
52 (define_predicate "q_regs_operand"
53 (match_operand 0 "register_operand")
55 if (GET_CODE (op) == SUBREG)
57 return ANY_QI_REG_P (op);
60 ;; Match an SI or HImode register for a zero_extract.
61 (define_special_predicate "ext_register_operand"
62 (match_operand 0 "register_operand")
64 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
65 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
67 if (GET_CODE (op) == SUBREG)
70 /* Be careful to accept only registers having upper parts. */
72 && (REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) <= BX_REG));
75 ;; Return true if op is the AX register.
76 (define_predicate "ax_reg_operand"
77 (and (match_code "reg")
78 (match_test "REGNO (op) == AX_REG")))
80 ;; Return true if op is the flags register.
81 (define_predicate "flags_reg_operand"
82 (and (match_code "reg")
83 (match_test "REGNO (op) == FLAGS_REG")))
85 ;; Return true if op is a QImode register operand other than
87 (define_predicate "ext_QIreg_operand"
88 (and (match_code "reg")
89 (match_test "TARGET_64BIT")
90 (match_test "REGNO (op) > BX_REG")))
92 ;; Return true if op is not xmm0 register.
93 (define_predicate "reg_not_xmm0_operand"
94 (match_operand 0 "register_operand")
96 if (GET_CODE (op) == SUBREG)
99 return !REG_P (op) || REGNO (op) != FIRST_SSE_REG;
102 ;; As above, but also allow memory operands.
103 (define_predicate "nonimm_not_xmm0_operand"
104 (ior (match_operand 0 "memory_operand")
105 (match_operand 0 "reg_not_xmm0_operand")))
107 ;; Return true if op is not xmm0 register, but only for non-AVX targets.
108 (define_predicate "reg_not_xmm0_operand_maybe_avx"
109 (if_then_else (match_test "TARGET_AVX")
110 (match_operand 0 "register_operand")
111 (match_operand 0 "reg_not_xmm0_operand")))
113 ;; As above, but also allow memory operands.
114 (define_predicate "nonimm_not_xmm0_operand_maybe_avx"
115 (if_then_else (match_test "TARGET_AVX")
116 (match_operand 0 "nonimmediate_operand")
117 (match_operand 0 "nonimm_not_xmm0_operand")))
119 ;; Return true if VALUE can be stored in a sign extended immediate field.
120 (define_predicate "x86_64_immediate_operand"
121 (match_code "const_int,symbol_ref,label_ref,const")
124 return immediate_operand (op, mode);
126 switch (GET_CODE (op))
129 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
130 to be at least 32 and this all acceptable constants are
131 represented as CONST_INT. */
132 if (HOST_BITS_PER_WIDE_INT == 32)
136 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
137 return trunc_int_for_mode (val, SImode) == val;
142 /* For certain code models, the symbolic references are known to fit.
143 in CM_SMALL_PIC model we know it fits if it is local to the shared
144 library. Don't count TLS SYMBOL_REFs here, since they should fit
145 only if inside of UNSPEC handled below. */
146 /* TLS symbols are not constant. */
147 if (SYMBOL_REF_TLS_MODEL (op))
149 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
150 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
153 /* For certain code models, the code is near as well. */
154 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
155 || ix86_cmodel == CM_KERNEL);
158 /* We also may accept the offsetted memory references in certain
160 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
161 switch (XINT (XEXP (op, 0), 1))
163 case UNSPEC_GOTPCREL:
165 case UNSPEC_GOTNTPOFF:
172 if (GET_CODE (XEXP (op, 0)) == PLUS)
174 rtx op1 = XEXP (XEXP (op, 0), 0);
175 rtx op2 = XEXP (XEXP (op, 0), 1);
176 HOST_WIDE_INT offset;
178 if (ix86_cmodel == CM_LARGE)
180 if (!CONST_INT_P (op2))
182 offset = trunc_int_for_mode (INTVAL (op2), DImode);
183 switch (GET_CODE (op1))
186 /* TLS symbols are not constant. */
187 if (SYMBOL_REF_TLS_MODEL (op1))
189 /* For CM_SMALL assume that latest object is 16MB before
190 end of 31bits boundary. We may also accept pretty
191 large negative constants knowing that all objects are
192 in the positive half of address space. */
193 if ((ix86_cmodel == CM_SMALL
194 || (ix86_cmodel == CM_MEDIUM
195 && !SYMBOL_REF_FAR_ADDR_P (op1)))
196 && offset < 16*1024*1024
197 && trunc_int_for_mode (offset, SImode) == offset)
199 /* For CM_KERNEL we know that all object resist in the
200 negative half of 32bits address space. We may not
201 accept negative offsets, since they may be just off
202 and we may accept pretty large positive ones. */
203 if (ix86_cmodel == CM_KERNEL
205 && trunc_int_for_mode (offset, SImode) == offset)
210 /* These conditions are similar to SYMBOL_REF ones, just the
211 constraints for code models differ. */
212 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
213 && offset < 16*1024*1024
214 && trunc_int_for_mode (offset, SImode) == offset)
216 if (ix86_cmodel == CM_KERNEL
218 && trunc_int_for_mode (offset, SImode) == offset)
223 switch (XINT (op1, 1))
228 && trunc_int_for_mode (offset, SImode) == offset)
246 ;; Return true if VALUE can be stored in the zero extended immediate field.
247 (define_predicate "x86_64_zext_immediate_operand"
248 (match_code "const_double,const_int,symbol_ref,label_ref,const")
250 switch (GET_CODE (op))
253 if (HOST_BITS_PER_WIDE_INT == 32)
254 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
259 if (HOST_BITS_PER_WIDE_INT == 32)
260 return INTVAL (op) >= 0;
262 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
265 /* For certain code models, the symbolic references are known to fit. */
266 /* TLS symbols are not constant. */
267 if (SYMBOL_REF_TLS_MODEL (op))
269 return (ix86_cmodel == CM_SMALL
270 || (ix86_cmodel == CM_MEDIUM
271 && !SYMBOL_REF_FAR_ADDR_P (op)));
274 /* For certain code models, the code is near as well. */
275 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
278 /* We also may accept the offsetted memory references in certain
280 if (GET_CODE (XEXP (op, 0)) == PLUS)
282 rtx op1 = XEXP (XEXP (op, 0), 0);
283 rtx op2 = XEXP (XEXP (op, 0), 1);
285 if (ix86_cmodel == CM_LARGE)
287 switch (GET_CODE (op1))
290 /* TLS symbols are not constant. */
291 if (SYMBOL_REF_TLS_MODEL (op1))
293 /* For small code model we may accept pretty large positive
294 offsets, since one bit is available for free. Negative
295 offsets are limited by the size of NULL pointer area
296 specified by the ABI. */
297 if ((ix86_cmodel == CM_SMALL
298 || (ix86_cmodel == CM_MEDIUM
299 && !SYMBOL_REF_FAR_ADDR_P (op1)))
301 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
302 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
304 /* ??? For the kernel, we may accept adjustment of
305 -0x10000000, since we know that it will just convert
306 negative address space to positive, but perhaps this
307 is not worthwhile. */
311 /* These conditions are similar to SYMBOL_REF ones, just the
312 constraints for code models differ. */
313 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
315 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
316 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
332 ;; Return true if OP is general operand representable on x86_64.
333 (define_predicate "x86_64_general_operand"
334 (if_then_else (match_test "TARGET_64BIT")
335 (ior (match_operand 0 "nonimmediate_operand")
336 (match_operand 0 "x86_64_immediate_operand"))
337 (match_operand 0 "general_operand")))
339 ;; Return true if OP is general operand representable on x86_64
340 ;; as either sign extended or zero extended constant.
341 (define_predicate "x86_64_szext_general_operand"
342 (if_then_else (match_test "TARGET_64BIT")
343 (ior (match_operand 0 "nonimmediate_operand")
344 (match_operand 0 "x86_64_immediate_operand")
345 (match_operand 0 "x86_64_zext_immediate_operand"))
346 (match_operand 0 "general_operand")))
348 ;; Return true if OP is nonmemory operand representable on x86_64.
349 (define_predicate "x86_64_nonmemory_operand"
350 (if_then_else (match_test "TARGET_64BIT")
351 (ior (match_operand 0 "register_operand")
352 (match_operand 0 "x86_64_immediate_operand"))
353 (match_operand 0 "nonmemory_operand")))
355 ;; Return true if OP is nonmemory operand representable on x86_64.
356 (define_predicate "x86_64_szext_nonmemory_operand"
357 (if_then_else (match_test "TARGET_64BIT")
358 (ior (match_operand 0 "register_operand")
359 (match_operand 0 "x86_64_immediate_operand")
360 (match_operand 0 "x86_64_zext_immediate_operand"))
361 (match_operand 0 "nonmemory_operand")))
363 ;; Return true when operand is PIC expression that can be computed by lea
365 (define_predicate "pic_32bit_operand"
366 (match_code "const,symbol_ref,label_ref")
370 /* Rule out relocations that translate into 64bit constants. */
371 if (TARGET_64BIT && GET_CODE (op) == CONST)
374 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
376 if (GET_CODE (op) == UNSPEC
377 && (XINT (op, 1) == UNSPEC_GOTOFF
378 || XINT (op, 1) == UNSPEC_GOT))
381 return symbolic_operand (op, mode);
385 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
386 (define_predicate "x86_64_movabs_operand"
387 (if_then_else (not (and (match_test "TARGET_64BIT")
388 (match_test "flag_pic")))
389 (match_operand 0 "nonmemory_operand")
390 (ior (match_operand 0 "register_operand")
391 (and (match_operand 0 "const_double_operand")
392 (match_test "GET_MODE_SIZE (mode) <= 8")))))
394 ;; Return true if OP is either a symbol reference or a sum of a symbol
395 ;; reference and a constant.
396 (define_predicate "symbolic_operand"
397 (match_code "symbol_ref,label_ref,const")
399 switch (GET_CODE (op))
407 if (GET_CODE (op) == SYMBOL_REF
408 || GET_CODE (op) == LABEL_REF
409 || (GET_CODE (op) == UNSPEC
410 && (XINT (op, 1) == UNSPEC_GOT
411 || XINT (op, 1) == UNSPEC_GOTOFF
412 || XINT (op, 1) == UNSPEC_GOTPCREL)))
414 if (GET_CODE (op) != PLUS
415 || !CONST_INT_P (XEXP (op, 1)))
419 if (GET_CODE (op) == SYMBOL_REF
420 || GET_CODE (op) == LABEL_REF)
422 /* Only @GOTOFF gets offsets. */
423 if (GET_CODE (op) != UNSPEC
424 || XINT (op, 1) != UNSPEC_GOTOFF)
427 op = XVECEXP (op, 0, 0);
428 if (GET_CODE (op) == SYMBOL_REF
429 || GET_CODE (op) == LABEL_REF)
438 ;; Return true if OP is a symbolic operand that resolves locally.
439 (define_predicate "local_symbolic_operand"
440 (match_code "const,label_ref,symbol_ref")
442 if (GET_CODE (op) == CONST
443 && GET_CODE (XEXP (op, 0)) == PLUS
444 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
445 op = XEXP (XEXP (op, 0), 0);
447 if (GET_CODE (op) == LABEL_REF)
450 if (GET_CODE (op) != SYMBOL_REF)
453 if (SYMBOL_REF_TLS_MODEL (op))
456 if (SYMBOL_REF_LOCAL_P (op))
459 /* There is, however, a not insubstantial body of code in the rest of
460 the compiler that assumes it can just stick the results of
461 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
462 /* ??? This is a hack. Should update the body of the compiler to
463 always create a DECL an invoke targetm.encode_section_info. */
464 if (strncmp (XSTR (op, 0), internal_label_prefix,
465 internal_label_prefix_len) == 0)
471 ;; Test for a legitimate @GOTOFF operand.
473 ;; VxWorks does not impose a fixed gap between segments; the run-time
474 ;; gap can be different from the object-file gap. We therefore can't
475 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
476 ;; same segment as the GOT. Unfortunately, the flexibility of linker
477 ;; scripts means that we can't be sure of that in general, so assume
478 ;; that @GOTOFF is never valid on VxWorks.
479 (define_predicate "gotoff_operand"
480 (and (not (match_test "TARGET_VXWORKS_RTP"))
481 (match_operand 0 "local_symbolic_operand")))
483 ;; Test for various thread-local symbols.
484 (define_predicate "tls_symbolic_operand"
485 (and (match_code "symbol_ref")
486 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
488 (define_predicate "tls_modbase_operand"
489 (and (match_code "symbol_ref")
490 (match_test "op == ix86_tls_module_base ()")))
492 (define_predicate "tp_or_register_operand"
493 (ior (match_operand 0 "register_operand")
494 (and (match_code "unspec")
495 (match_test "XINT (op, 1) == UNSPEC_TP"))))
497 ;; Test for a pc-relative call operand
498 (define_predicate "constant_call_address_operand"
499 (match_code "symbol_ref")
501 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
503 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
508 ;; P6 processors will jump to the address after the decrement when %esp
509 ;; is used as a call operand, so they will execute return address as a code.
510 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
512 (define_predicate "call_register_no_elim_operand"
513 (match_operand 0 "register_operand")
515 if (GET_CODE (op) == SUBREG)
516 op = SUBREG_REG (op);
518 if (!TARGET_64BIT && op == stack_pointer_rtx)
521 return register_no_elim_operand (op, mode);
524 ;; True for any non-virtual or eliminable register. Used in places where
525 ;; instantiation of such a register may cause the pattern to not be recognized.
526 (define_predicate "register_no_elim_operand"
527 (match_operand 0 "register_operand")
529 if (GET_CODE (op) == SUBREG)
530 op = SUBREG_REG (op);
531 return !(op == arg_pointer_rtx
532 || op == frame_pointer_rtx
533 || IN_RANGE (REGNO (op),
534 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
537 ;; Similarly, but include the stack pointer. This is used to prevent esp
538 ;; from being used as an index reg.
539 (define_predicate "index_register_operand"
540 (match_operand 0 "register_operand")
542 if (GET_CODE (op) == SUBREG)
543 op = SUBREG_REG (op);
544 if (reload_in_progress || reload_completed)
545 return REG_OK_FOR_INDEX_STRICT_P (op);
547 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
550 ;; Return false if this is any eliminable register. Otherwise general_operand.
551 (define_predicate "general_no_elim_operand"
552 (if_then_else (match_code "reg,subreg")
553 (match_operand 0 "register_no_elim_operand")
554 (match_operand 0 "general_operand")))
556 ;; Return false if this is any eliminable register. Otherwise
557 ;; register_operand or a constant.
558 (define_predicate "nonmemory_no_elim_operand"
559 (ior (match_operand 0 "register_no_elim_operand")
560 (match_operand 0 "immediate_operand")))
562 ;; Test for a valid operand for a call instruction.
563 (define_predicate "call_insn_operand"
564 (ior (match_operand 0 "constant_call_address_operand")
565 (match_operand 0 "call_register_no_elim_operand")
566 (match_operand 0 "memory_operand")))
568 ;; Similarly, but for tail calls, in which we cannot allow memory references.
569 (define_predicate "sibcall_insn_operand"
570 (ior (match_operand 0 "constant_call_address_operand")
571 (match_operand 0 "register_no_elim_operand")))
573 ;; Match exactly zero.
574 (define_predicate "const0_operand"
575 (match_code "const_int,const_double,const_vector")
577 if (mode == VOIDmode)
578 mode = GET_MODE (op);
579 return op == CONST0_RTX (mode);
582 ;; Match exactly one.
583 (define_predicate "const1_operand"
584 (and (match_code "const_int")
585 (match_test "op == const1_rtx")))
587 ;; Match exactly eight.
588 (define_predicate "const8_operand"
589 (and (match_code "const_int")
590 (match_test "INTVAL (op) == 8")))
592 ;; Match exactly 128.
593 (define_predicate "const128_operand"
594 (and (match_code "const_int")
595 (match_test "INTVAL (op) == 128")))
597 ;; Match 2, 4, or 8. Used for leal multiplicands.
598 (define_predicate "const248_operand"
599 (match_code "const_int")
601 HOST_WIDE_INT i = INTVAL (op);
602 return i == 2 || i == 4 || i == 8;
606 (define_predicate "const_0_to_1_operand"
607 (and (match_code "const_int")
608 (ior (match_test "op == const0_rtx")
609 (match_test "op == const1_rtx"))))
612 (define_predicate "const_0_to_3_operand"
613 (and (match_code "const_int")
614 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
617 (define_predicate "const_0_to_7_operand"
618 (and (match_code "const_int")
619 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
622 (define_predicate "const_0_to_15_operand"
623 (and (match_code "const_int")
624 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
627 (define_predicate "const_0_to_31_operand"
628 (and (match_code "const_int")
629 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
632 (define_predicate "const_0_to_63_operand"
633 (and (match_code "const_int")
634 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
637 (define_predicate "const_0_to_255_operand"
638 (and (match_code "const_int")
639 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
641 ;; Match (0 to 255) * 8
642 (define_predicate "const_0_to_255_mul_8_operand"
643 (match_code "const_int")
645 unsigned HOST_WIDE_INT val = INTVAL (op);
646 return val <= 255*8 && val % 8 == 0;
649 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
650 ;; for shift & compare patterns, as shifting by 0 does not change flags).
651 (define_predicate "const_1_to_31_operand"
652 (and (match_code "const_int")
653 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
655 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
656 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
657 (define_predicate "const_1_to_63_operand"
658 (and (match_code "const_int")
659 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
662 (define_predicate "const_2_to_3_operand"
663 (and (match_code "const_int")
664 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
667 (define_predicate "const_4_to_5_operand"
668 (and (match_code "const_int")
669 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
672 (define_predicate "const_4_to_7_operand"
673 (and (match_code "const_int")
674 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
677 (define_predicate "const_6_to_7_operand"
678 (and (match_code "const_int")
679 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
682 (define_predicate "const_8_to_11_operand"
683 (and (match_code "const_int")
684 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
687 (define_predicate "const_12_to_15_operand"
688 (and (match_code "const_int")
689 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
691 ;; Match exactly one bit in 2-bit mask.
692 (define_predicate "const_pow2_1_to_2_operand"
693 (and (match_code "const_int")
694 (ior (match_test "op == const1_rtx")
695 (match_test "op == const2_rtx"))))
697 ;; Match exactly one bit in 4-bit mask.
698 (define_predicate "const_pow2_1_to_8_operand"
699 (match_code "const_int")
701 unsigned int log = exact_log2 (INTVAL (op));
705 ;; Match exactly one bit in 8-bit mask.
706 (define_predicate "const_pow2_1_to_128_operand"
707 (match_code "const_int")
709 unsigned int log = exact_log2 (INTVAL (op));
713 ;; Match exactly one bit in 16-bit mask.
714 (define_predicate "const_pow2_1_to_32768_operand"
715 (match_code "const_int")
717 unsigned int log = exact_log2 (INTVAL (op));
721 ;; True if this is a constant appropriate for an increment or decrement.
722 (define_predicate "incdec_operand"
723 (match_code "const_int")
725 /* On Pentium4, the inc and dec operations causes extra dependency on flag
726 registers, since carry flag is not set. */
727 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
729 return op == const1_rtx || op == constm1_rtx;
732 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
733 (define_predicate "reg_or_pm1_operand"
734 (ior (match_operand 0 "register_operand")
735 (and (match_code "const_int")
736 (ior (match_test "op == const1_rtx")
737 (match_test "op == constm1_rtx")))))
739 ;; True if OP is acceptable as operand of DImode shift expander.
740 (define_predicate "shiftdi_operand"
741 (if_then_else (match_test "TARGET_64BIT")
742 (match_operand 0 "nonimmediate_operand")
743 (match_operand 0 "register_operand")))
745 (define_predicate "ashldi_input_operand"
746 (if_then_else (match_test "TARGET_64BIT")
747 (match_operand 0 "nonimmediate_operand")
748 (match_operand 0 "reg_or_pm1_operand")))
750 ;; Return true if OP is a vector load from the constant pool with just
751 ;; the first element nonzero.
752 (define_predicate "zero_extended_scalar_load_operand"
756 op = maybe_get_pool_constant (op);
758 if (!(op && GET_CODE (op) == CONST_VECTOR))
761 n_elts = CONST_VECTOR_NUNITS (op);
763 for (n_elts--; n_elts > 0; n_elts--)
765 rtx elt = CONST_VECTOR_ELT (op, n_elts);
766 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
772 /* Return true if operand is a vector constant that is all ones. */
773 (define_predicate "vector_all_ones_operand"
774 (match_code "const_vector")
776 int nunits = GET_MODE_NUNITS (mode);
778 if (GET_CODE (op) == CONST_VECTOR
779 && CONST_VECTOR_NUNITS (op) == nunits)
782 for (i = 0; i < nunits; ++i)
784 rtx x = CONST_VECTOR_ELT (op, i);
785 if (x != constm1_rtx)
794 ; Return true when OP is operand acceptable for standard SSE move.
795 (define_predicate "vector_move_operand"
796 (ior (match_operand 0 "nonimmediate_operand")
797 (match_operand 0 "const0_operand")))
799 ;; Return true when OP is nonimmediate or standard SSE constant.
800 (define_predicate "nonimmediate_or_sse_const_operand"
801 (match_operand 0 "general_operand")
803 if (nonimmediate_operand (op, mode))
805 if (standard_sse_constant_p (op) > 0)
810 ;; Return true if OP is a register or a zero.
811 (define_predicate "reg_or_0_operand"
812 (ior (match_operand 0 "register_operand")
813 (match_operand 0 "const0_operand")))
815 ;; Return true if op if a valid address, and does not contain
816 ;; a segment override.
817 (define_special_predicate "no_seg_address_operand"
818 (match_operand 0 "address_operand")
820 struct ix86_address parts;
823 ok = ix86_decompose_address (op, &parts);
825 return parts.seg == SEG_DEFAULT;
828 ;; Return true if the rtx is known to be at least 32 bits aligned.
829 (define_predicate "aligned_operand"
830 (match_operand 0 "general_operand")
832 struct ix86_address parts;
835 /* Registers and immediate operands are always "aligned". */
839 /* All patterns using aligned_operand on memory operands ends up
840 in promoting memory operand to 64bit and thus causing memory mismatch. */
841 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
844 /* Don't even try to do any aligned optimizations with volatiles. */
845 if (MEM_VOLATILE_P (op))
848 if (MEM_ALIGN (op) >= 32)
853 /* Pushes and pops are only valid on the stack pointer. */
854 if (GET_CODE (op) == PRE_DEC
855 || GET_CODE (op) == POST_INC)
858 /* Decode the address. */
859 ok = ix86_decompose_address (op, &parts);
862 /* Look for some component that isn't known to be aligned. */
865 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
870 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
875 if (!CONST_INT_P (parts.disp)
876 || (INTVAL (parts.disp) & 3))
880 /* Didn't find one -- this must be an aligned address. */
884 ;; Return true if OP is memory operand with a displacement.
885 (define_predicate "memory_displacement_operand"
886 (match_operand 0 "memory_operand")
888 struct ix86_address parts;
891 ok = ix86_decompose_address (XEXP (op, 0), &parts);
893 return parts.disp != NULL_RTX;
896 ;; Return true if OP is memory operand with a displacement only.
897 (define_predicate "memory_displacement_only_operand"
898 (match_operand 0 "memory_operand")
900 struct ix86_address parts;
906 ok = ix86_decompose_address (XEXP (op, 0), &parts);
909 if (parts.base || parts.index)
912 return parts.disp != NULL_RTX;
915 ;; Return true if OP is memory operand which will need zero or
916 ;; one register at most, not counting stack pointer or frame pointer.
917 (define_predicate "cmpxchg8b_pic_memory_operand"
918 (match_operand 0 "memory_operand")
920 struct ix86_address parts;
923 ok = ix86_decompose_address (XEXP (op, 0), &parts);
925 if (parts.base == NULL_RTX
926 || parts.base == arg_pointer_rtx
927 || parts.base == frame_pointer_rtx
928 || parts.base == hard_frame_pointer_rtx
929 || parts.base == stack_pointer_rtx)
932 if (parts.index == NULL_RTX
933 || parts.index == arg_pointer_rtx
934 || parts.index == frame_pointer_rtx
935 || parts.index == hard_frame_pointer_rtx
936 || parts.index == stack_pointer_rtx)
943 ;; Return true if OP is memory operand that cannot be represented
944 ;; by the modRM array.
945 (define_predicate "long_memory_operand"
946 (and (match_operand 0 "memory_operand")
947 (match_test "memory_address_length (op)")))
949 ;; Return true if OP is a comparison operator that can be issued by fcmov.
950 (define_predicate "fcmov_comparison_operator"
951 (match_operand 0 "comparison_operator")
953 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
954 enum rtx_code code = GET_CODE (op);
956 if (inmode == CCFPmode || inmode == CCFPUmode)
958 if (!ix86_trivial_fp_comparison_operator (op, mode))
960 code = ix86_fp_compare_code_to_integer (code);
962 /* i387 supports just limited amount of conditional codes. */
965 case LTU: case GTU: case LEU: case GEU:
966 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
967 || inmode == CCCmode)
970 case ORDERED: case UNORDERED:
978 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
979 ;; The first set are supported directly; the second set can't be done with
980 ;; full IEEE support, i.e. NaNs.
982 (define_predicate "sse_comparison_operator"
983 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
984 (and (match_test "TARGET_AVX")
985 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
987 (define_predicate "ix86_comparison_int_operator"
988 (match_code "ne,eq,ge,gt,le,lt"))
990 (define_predicate "ix86_comparison_uns_operator"
991 (match_code "ne,eq,geu,gtu,leu,ltu"))
993 (define_predicate "bt_comparison_operator"
994 (match_code "ne,eq"))
996 ;; Return true if OP is a valid comparison operator in valid mode.
997 (define_predicate "ix86_comparison_operator"
998 (match_operand 0 "comparison_operator")
1000 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1001 enum rtx_code code = GET_CODE (op);
1003 if (inmode == CCFPmode || inmode == CCFPUmode)
1004 return ix86_trivial_fp_comparison_operator (op, mode);
1011 if (inmode == CCmode || inmode == CCGCmode
1012 || inmode == CCGOCmode || inmode == CCNOmode)
1015 case LTU: case GTU: case LEU: case GEU:
1016 if (inmode == CCmode || inmode == CCCmode)
1019 case ORDERED: case UNORDERED:
1020 if (inmode == CCmode)
1024 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1032 ;; Return true if OP is a valid comparison operator
1033 ;; testing carry flag to be set.
1034 (define_predicate "ix86_carry_flag_operator"
1035 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1037 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1038 enum rtx_code code = GET_CODE (op);
1040 if (inmode == CCFPmode || inmode == CCFPUmode)
1042 if (!ix86_trivial_fp_comparison_operator (op, mode))
1044 code = ix86_fp_compare_code_to_integer (code);
1046 else if (inmode == CCCmode)
1047 return code == LTU || code == GTU;
1048 else if (inmode != CCmode)
1054 ;; Return true if this comparison only requires testing one flag bit.
1055 (define_predicate "ix86_trivial_fp_comparison_operator"
1056 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1058 ;; Return true if we know how to do this comparison. Others require
1059 ;; testing more than one flag bit, and we let the generic middle-end
1061 (define_predicate "ix86_fp_comparison_operator"
1062 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1063 == IX86_FPCMP_ARITH")
1064 (match_operand 0 "comparison_operator")
1065 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1067 ;; Same as above, but for swapped comparison used in fp_jcc_4_387.
1068 (define_predicate "ix86_swapped_fp_comparison_operator"
1069 (match_operand 0 "comparison_operator")
1071 enum rtx_code code = GET_CODE (op);
1074 PUT_CODE (op, swap_condition (code));
1075 ret = ix86_fp_comparison_operator (op, mode);
1076 PUT_CODE (op, code);
1080 ;; Nearly general operand, but accept any const_double, since we wish
1081 ;; to be able to drop them into memory rather than have them get pulled
1083 (define_predicate "cmp_fp_expander_operand"
1084 (ior (match_code "const_double")
1085 (match_operand 0 "general_operand")))
1087 ;; Return true if this is a valid binary floating-point operation.
1088 (define_predicate "binary_fp_operator"
1089 (match_code "plus,minus,mult,div"))
1091 ;; Return true if this is a multiply operation.
1092 (define_predicate "mult_operator"
1093 (match_code "mult"))
1095 ;; Return true if this is a division operation.
1096 (define_predicate "div_operator"
1099 ;; Return true if this is a float extend operation.
1100 (define_predicate "float_operator"
1101 (match_code "float"))
1103 ;; Return true for ARITHMETIC_P.
1104 (define_predicate "arith_or_logical_operator"
1105 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1106 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1108 ;; Return true for COMMUTATIVE_P.
1109 (define_predicate "commutative_operator"
1110 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1112 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1113 (define_predicate "promotable_binary_operator"
1114 (ior (match_code "plus,and,ior,xor,ashift")
1115 (and (match_code "mult")
1116 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1118 (define_predicate "compare_operator"
1119 (match_code "compare"))
1121 (define_predicate "absneg_operator"
1122 (match_code "abs,neg"))
1124 ;; Return true if OP is misaligned memory operand
1125 (define_predicate "misaligned_operand"
1126 (and (match_code "mem")
1127 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1129 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1130 (define_predicate "emms_operation"
1131 (match_code "parallel")
1135 if (XVECLEN (op, 0) != 17)
1138 for (i = 0; i < 8; i++)
1140 rtx elt = XVECEXP (op, 0, i+1);
1142 if (GET_CODE (elt) != CLOBBER
1143 || GET_CODE (SET_DEST (elt)) != REG
1144 || GET_MODE (SET_DEST (elt)) != XFmode
1145 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1148 elt = XVECEXP (op, 0, i+9);
1150 if (GET_CODE (elt) != CLOBBER
1151 || GET_CODE (SET_DEST (elt)) != REG
1152 || GET_MODE (SET_DEST (elt)) != DImode
1153 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1159 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1160 (define_predicate "vzeroall_operation"
1161 (match_code "parallel")
1163 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1165 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1168 for (i = 0; i < nregs; i++)
1170 rtx elt = XVECEXP (op, 0, i+1);
1172 if (GET_CODE (elt) != SET
1173 || GET_CODE (SET_DEST (elt)) != REG
1174 || GET_MODE (SET_DEST (elt)) != V8SImode
1175 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1176 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1182 ;; Return true if OP is a parallel for a vpermilp[ds] permute.
1183 ;; ??? It would be much easier if the PARALLEL for a VEC_SELECT
1184 ;; had a mode, but it doesn't. So we have 4 copies and install
1185 ;; the mode by hand.
1187 (define_predicate "avx_vpermilp_v8sf_operand"
1188 (and (match_code "parallel")
1189 (match_test "avx_vpermilp_parallel (op, V8SFmode)")))
1191 (define_predicate "avx_vpermilp_v4df_operand"
1192 (and (match_code "parallel")
1193 (match_test "avx_vpermilp_parallel (op, V4DFmode)")))
1195 (define_predicate "avx_vpermilp_v4sf_operand"
1196 (and (match_code "parallel")
1197 (match_test "avx_vpermilp_parallel (op, V4SFmode)")))
1199 (define_predicate "avx_vpermilp_v2df_operand"
1200 (and (match_code "parallel")
1201 (match_test "avx_vpermilp_parallel (op, V2DFmode)")))
1203 ;; Return true if OP is a parallel for a vperm2f128 permute.
1205 (define_predicate "avx_vperm2f128_v8sf_operand"
1206 (and (match_code "parallel")
1207 (match_test "avx_vperm2f128_parallel (op, V8SFmode)")))
1209 (define_predicate "avx_vperm2f128_v8si_operand"
1210 (and (match_code "parallel")
1211 (match_test "avx_vperm2f128_parallel (op, V8SImode)")))
1213 (define_predicate "avx_vperm2f128_v4df_operand"
1214 (and (match_code "parallel")
1215 (match_test "avx_vperm2f128_parallel (op, V4DFmode)")))
1217 ;; Return true if OP is a parallel for a vbroadcast permute.
1219 (define_predicate "avx_vbroadcast_operand"
1220 (and (match_code "parallel")
1221 (match_code "const_int" "a"))
1223 rtx elt = XVECEXP (op, 0, 0);
1224 int i, nelt = XVECLEN (op, 0);
1226 /* Don't bother checking there are the right number of operands,
1227 merely that they're all identical. */
1228 for (i = 1; i < nelt; ++i)
1229 if (XVECEXP (op, 0, i) != elt)