1 ;; GCC machine description for MMX and 3dNOW! instructions
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;; The MMX and 3dNOW! patterns are in the same file because they use
23 ;; the same register file, and 3dNOW! adds a number of extensions to
24 ;; the base integer MMX isa.
26 ;; Note! Except for the basic move instructions, *all* of these
27 ;; patterns are outside the normal optabs namespace. This is because
28 ;; use of these registers requires the insertion of emms or femms
29 ;; instructions to return to normal fpu mode. The compiler doesn't
30 ;; know how to do that itself, which means it's up to the user. Which
31 ;; means that we should never use any of these patterns except at the
32 ;; direction of the user via a builtin.
34 ;; 8 byte integral modes handled by MMX (and by extension, SSE)
35 (define_mode_macro MMXMODEI [V8QI V4HI V2SI])
37 ;; All 8-byte vector modes handled by MMX
38 (define_mode_macro MMXMODE [V8QI V4HI V2SI V2SF])
41 (define_mode_macro MMXMODE12 [V8QI V4HI])
42 (define_mode_macro MMXMODE24 [V4HI V2SI])
44 ;; Mapping from integer vector mode to mnemonic suffix
45 (define_mode_attr mmxvecsize [(V8QI "b") (V4HI "w") (V2SI "d") (DI "q")])
47 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
51 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
53 ;; All of these patterns are enabled for MMX as well as 3dNOW.
54 ;; This is essential for maintaining stable calling conventions.
56 (define_expand "mov<mode>"
57 [(set (match_operand:MMXMODEI 0 "nonimmediate_operand" "")
58 (match_operand:MMXMODEI 1 "nonimmediate_operand" ""))]
61 ix86_expand_vector_move (<MODE>mode, operands);
65 (define_insn "*mov<mode>_internal_rex64"
66 [(set (match_operand:MMXMODEI 0 "nonimmediate_operand"
67 "=rm,r,*y,*y ,m ,*y,Y ,x,x ,m,r,x")
68 (match_operand:MMXMODEI 1 "vector_move_operand"
69 "Cr ,m,C ,*ym,*y,Y ,*y,C,xm,x,x,r"))]
70 "TARGET_64BIT && TARGET_MMX
71 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
78 movdq2q\t{%1, %0|%0, %1}
79 movq2dq\t{%1, %0|%0, %1}
84 movd\t{%1, %0|%0, %1}"
85 [(set_attr "type" "imov,imov,mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov,ssemov,ssemov")
86 (set_attr "mode" "DI")])
88 (define_insn "*mov<mode>_internal"
89 [(set (match_operand:MMXMODEI 0 "nonimmediate_operand"
90 "=*y,*y ,m ,*y,*Y,*Y,*Y ,m ,*x,*x,*x,m ,?r ,?m")
91 (match_operand:MMXMODEI 1 "vector_move_operand"
92 "C ,*ym,*y,*Y,*y,C ,*Ym,*Y,C ,*x,m ,*x,irm,r"))]
94 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
99 movdq2q\t{%1, %0|%0, %1}
100 movq2dq\t{%1, %0|%0, %1}
102 movq\t{%1, %0|%0, %1}
103 movq\t{%1, %0|%0, %1}
105 movaps\t{%1, %0|%0, %1}
106 movlps\t{%1, %0|%0, %1}
107 movlps\t{%1, %0|%0, %1}
110 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov,ssemov,ssemov,ssemov,ssemov,*,*")
111 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
113 (define_expand "movv2sf"
114 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
115 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
118 ix86_expand_vector_move (V2SFmode, operands);
122 (define_insn "*movv2sf_internal_rex64"
123 [(set (match_operand:V2SF 0 "nonimmediate_operand"
124 "=rm,r,*y ,*y ,m ,*y,Y ,x,x,x,m,r,x")
125 (match_operand:V2SF 1 "vector_move_operand"
126 "Cr ,m ,C ,*ym,*y,Y ,*y,C,x,m,x,x,r"))]
127 "TARGET_64BIT && TARGET_MMX
128 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
130 movq\t{%1, %0|%0, %1}
131 movq\t{%1, %0|%0, %1}
133 movq\t{%1, %0|%0, %1}
134 movq\t{%1, %0|%0, %1}
135 movdq2q\t{%1, %0|%0, %1}
136 movq2dq\t{%1, %0|%0, %1}
138 movaps\t{%1, %0|%0, %1}
139 movlps\t{%1, %0|%0, %1}
140 movlps\t{%1, %0|%0, %1}
141 movd\t{%1, %0|%0, %1}
142 movd\t{%1, %0|%0, %1}"
143 [(set_attr "type" "imov,imov,mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov,ssemov,ssemov,ssemov")
144 (set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
146 (define_insn "*movv2sf_internal"
147 [(set (match_operand:V2SF 0 "nonimmediate_operand"
148 "=*y,*y ,m,*y,*Y,*x,*x,*x,m ,?r ,?m")
149 (match_operand:V2SF 1 "vector_move_operand"
150 "C ,*ym,*y,*Y,*y,C ,*x,m ,*x,irm,r"))]
152 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
155 movq\t{%1, %0|%0, %1}
156 movq\t{%1, %0|%0, %1}
157 movdq2q\t{%1, %0|%0, %1}
158 movq2dq\t{%1, %0|%0, %1}
160 movaps\t{%1, %0|%0, %1}
161 movlps\t{%1, %0|%0, %1}
162 movlps\t{%1, %0|%0, %1}
165 [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov,ssemov,*,*")
166 (set_attr "mode" "DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
168 ;; %%% This multiword shite has got to go.
170 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
171 (match_operand:MMXMODE 1 "general_operand" ""))]
172 "!TARGET_64BIT && reload_completed
173 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
174 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
176 "ix86_split_long_move (operands); DONE;")
178 (define_expand "push<mode>1"
179 [(match_operand:MMXMODE 0 "register_operand" "")]
182 ix86_expand_push (<MODE>mode, operands[0]);
186 (define_expand "movmisalign<mode>"
187 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
188 (match_operand:MMXMODE 1 "nonimmediate_operand" ""))]
191 ix86_expand_vector_move (<MODE>mode, operands);
195 (define_insn "sse_movntdi"
196 [(set (match_operand:DI 0 "memory_operand" "=m")
197 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
199 "TARGET_SSE || TARGET_3DNOW_A"
200 "movntq\t{%1, %0|%0, %1}"
201 [(set_attr "type" "mmxmov")
202 (set_attr "mode" "DI")])
204 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
206 ;; Parallel single-precision floating point arithmetic
208 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
210 (define_insn "mmx_addv2sf3"
211 [(set (match_operand:V2SF 0 "register_operand" "=y")
212 (plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
213 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
214 "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
215 "pfadd\\t{%2, %0|%0, %2}"
216 [(set_attr "type" "mmxadd")
217 (set_attr "mode" "V2SF")])
219 (define_insn "mmx_subv2sf3"
220 [(set (match_operand:V2SF 0 "register_operand" "=y,y")
221 (minus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "0,ym")
222 (match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))]
223 "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
225 pfsub\\t{%2, %0|%0, %2}
226 pfsubr\\t{%2, %0|%0, %2}"
227 [(set_attr "type" "mmxadd")
228 (set_attr "mode" "V2SF")])
230 (define_expand "mmx_subrv2sf3"
231 [(set (match_operand:V2SF 0 "register_operand" "")
232 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "")
233 (match_operand:V2SF 1 "nonimmediate_operand" "")))]
234 "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
237 (define_insn "mmx_mulv2sf3"
238 [(set (match_operand:V2SF 0 "register_operand" "=y")
239 (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
240 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
241 "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
242 "pfmul\\t{%2, %0|%0, %2}"
243 [(set_attr "type" "mmxmul")
244 (set_attr "mode" "V2SF")])
246 (define_insn "mmx_smaxv2sf3"
247 [(set (match_operand:V2SF 0 "register_operand" "=y")
248 (smax:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
249 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
250 "TARGET_3DNOW && ix86_binary_operator_ok (SMAX, V2SFmode, operands)"
251 "pfmax\\t{%2, %0|%0, %2}"
252 [(set_attr "type" "mmxadd")
253 (set_attr "mode" "V2SF")])
255 (define_insn "mmx_sminv2sf3"
256 [(set (match_operand:V2SF 0 "register_operand" "=y")
257 (smin:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
258 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
259 "TARGET_3DNOW && ix86_binary_operator_ok (SMIN, V2SFmode, operands)"
260 "pfmin\\t{%2, %0|%0, %2}"
261 [(set_attr "type" "mmxadd")
262 (set_attr "mode" "V2SF")])
264 (define_insn "mmx_rcpv2sf2"
265 [(set (match_operand:V2SF 0 "register_operand" "=y")
266 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
269 "pfrcp\\t{%1, %0|%0, %1}"
270 [(set_attr "type" "mmx")
271 (set_attr "mode" "V2SF")])
273 (define_insn "mmx_rcpit1v2sf3"
274 [(set (match_operand:V2SF 0 "register_operand" "=y")
275 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
276 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
279 "pfrcpit1\\t{%2, %0|%0, %2}"
280 [(set_attr "type" "mmx")
281 (set_attr "mode" "V2SF")])
283 (define_insn "mmx_rcpit2v2sf3"
284 [(set (match_operand:V2SF 0 "register_operand" "=y")
285 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
286 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
289 "pfrcpit2\\t{%2, %0|%0, %2}"
290 [(set_attr "type" "mmx")
291 (set_attr "mode" "V2SF")])
293 (define_insn "mmx_rsqrtv2sf2"
294 [(set (match_operand:V2SF 0 "register_operand" "=y")
295 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
298 "pfrsqrt\\t{%1, %0|%0, %1}"
299 [(set_attr "type" "mmx")
300 (set_attr "mode" "V2SF")])
302 (define_insn "mmx_rsqit1v2sf3"
303 [(set (match_operand:V2SF 0 "register_operand" "=y")
304 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
305 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
308 "pfrsqit1\\t{%2, %0|%0, %2}"
309 [(set_attr "type" "mmx")
310 (set_attr "mode" "V2SF")])
312 (define_insn "mmx_haddv2sf3"
313 [(set (match_operand:V2SF 0 "register_operand" "=y")
317 (match_operand:V2SF 1 "register_operand" "0")
318 (parallel [(const_int 0)]))
319 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
322 (match_operand:V2SF 2 "nonimmediate_operand" "ym")
323 (parallel [(const_int 0)]))
324 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
326 "pfacc\\t{%2, %0|%0, %2}"
327 [(set_attr "type" "mmxadd")
328 (set_attr "mode" "V2SF")])
330 (define_insn "mmx_hsubv2sf3"
331 [(set (match_operand:V2SF 0 "register_operand" "=y")
335 (match_operand:V2SF 1 "register_operand" "0")
336 (parallel [(const_int 0)]))
337 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
340 (match_operand:V2SF 2 "nonimmediate_operand" "ym")
341 (parallel [(const_int 0)]))
342 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
344 "pfnacc\\t{%2, %0|%0, %2}"
345 [(set_attr "type" "mmxadd")
346 (set_attr "mode" "V2SF")])
348 (define_insn "mmx_addsubv2sf3"
349 [(set (match_operand:V2SF 0 "register_operand" "=y")
352 (match_operand:V2SF 1 "register_operand" "0")
353 (match_operand:V2SF 2 "nonimmediate_operand" "ym"))
354 (minus:V2SF (match_dup 1) (match_dup 2))
357 "pfpnacc\\t{%2, %0|%0, %2}"
358 [(set_attr "type" "mmxadd")
359 (set_attr "mode" "V2SF")])
361 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
363 ;; Parallel single-precision floating point comparisons
365 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
367 (define_insn "mmx_gtv2sf3"
368 [(set (match_operand:V2SI 0 "register_operand" "=y")
369 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
370 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
372 "pfcmpgt\\t{%2, %0|%0, %2}"
373 [(set_attr "type" "mmxcmp")
374 (set_attr "mode" "V2SF")])
376 (define_insn "mmx_gev2sf3"
377 [(set (match_operand:V2SI 0 "register_operand" "=y")
378 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
379 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
381 "pfcmpge\\t{%2, %0|%0, %2}"
382 [(set_attr "type" "mmxcmp")
383 (set_attr "mode" "V2SF")])
385 (define_insn "mmx_eqv2sf3"
386 [(set (match_operand:V2SI 0 "register_operand" "=y")
387 (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
388 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
389 "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
390 "pfcmpeq\\t{%2, %0|%0, %2}"
391 [(set_attr "type" "mmxcmp")
392 (set_attr "mode" "V2SF")])
394 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
396 ;; Parallel single-precision floating point conversion operations
398 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
400 (define_insn "mmx_pf2id"
401 [(set (match_operand:V2SI 0 "register_operand" "=y")
402 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
404 "pf2id\\t{%1, %0|%0, %1}"
405 [(set_attr "type" "mmxcvt")
406 (set_attr "mode" "V2SF")])
408 (define_insn "mmx_pf2iw"
409 [(set (match_operand:V2SI 0 "register_operand" "=y")
413 (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
415 "pf2iw\\t{%1, %0|%0, %1}"
416 [(set_attr "type" "mmxcvt")
417 (set_attr "mode" "V2SF")])
419 (define_insn "mmx_pi2fw"
420 [(set (match_operand:V2SF 0 "register_operand" "=y")
424 (match_operand:V2SI 1 "nonimmediate_operand" "ym")))))]
426 "pi2fw\\t{%1, %0|%0, %1}"
427 [(set_attr "type" "mmxcvt")
428 (set_attr "mode" "V2SF")])
430 (define_insn "mmx_floatv2si2"
431 [(set (match_operand:V2SF 0 "register_operand" "=y")
432 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
434 "pi2fd\\t{%1, %0|%0, %1}"
435 [(set_attr "type" "mmxcvt")
436 (set_attr "mode" "V2SF")])
438 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
440 ;; Parallel single-precision floating point element swizzling
442 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
444 (define_insn "mmx_pswapdv2sf2"
445 [(set (match_operand:V2SF 0 "register_operand" "=y")
446 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
447 (parallel [(const_int 1) (const_int 0)])))]
449 "pswapd\\t{%1, %0|%0, %1}"
450 [(set_attr "type" "mmxcvt")
451 (set_attr "mode" "V2SF")])
453 (define_insn "*vec_dupv2sf"
454 [(set (match_operand:V2SF 0 "register_operand" "=y")
456 (match_operand:SF 1 "register_operand" "0")))]
459 [(set_attr "type" "mmxcvt")
460 (set_attr "mode" "DI")])
462 (define_insn "*mmx_concatv2sf"
463 [(set (match_operand:V2SF 0 "register_operand" "=y,y")
465 (match_operand:SF 1 "nonimmediate_operand" " 0,rm")
466 (match_operand:SF 2 "vector_move_operand" "ym,C")))]
467 "TARGET_MMX && !TARGET_SSE"
469 punpckldq\t{%2, %0|%0, %2}
470 movd\t{%1, %0|%0, %1}"
471 [(set_attr "type" "mmxcvt,mmxmov")
472 (set_attr "mode" "DI")])
474 (define_expand "vec_setv2sf"
475 [(match_operand:V2SF 0 "register_operand" "")
476 (match_operand:SF 1 "register_operand" "")
477 (match_operand 2 "const_int_operand" "")]
480 ix86_expand_vector_set (false, operands[0], operands[1],
481 INTVAL (operands[2]));
485 (define_insn_and_split "*vec_extractv2sf_0"
486 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,y,m,m,frxy")
488 (match_operand:V2SF 1 "nonimmediate_operand" " x,y,x,y,m")
489 (parallel [(const_int 0)])))]
490 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
492 "&& reload_completed"
495 rtx op1 = operands[1];
497 op1 = gen_rtx_REG (SFmode, REGNO (op1));
499 op1 = gen_lowpart (SFmode, op1);
500 emit_move_insn (operands[0], op1);
504 (define_insn "*vec_extractv2sf_1"
505 [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x,frxy")
507 (match_operand:V2SF 1 "nonimmediate_operand" " 0,0,o")
508 (parallel [(const_int 1)])))]
509 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
514 [(set_attr "type" "mmxcvt,sselog1,*")
515 (set_attr "mode" "DI,V4SF,SI")])
518 [(set (match_operand:SF 0 "register_operand" "")
520 (match_operand:V2SF 1 "memory_operand" "")
521 (parallel [(const_int 1)])))]
522 "TARGET_MMX && reload_completed"
525 operands[1] = adjust_address (operands[1], SFmode, 4);
526 emit_move_insn (operands[0], operands[1]);
530 (define_expand "vec_extractv2sf"
531 [(match_operand:SF 0 "register_operand" "")
532 (match_operand:V2SF 1 "register_operand" "")
533 (match_operand 2 "const_int_operand" "")]
536 ix86_expand_vector_extract (false, operands[0], operands[1],
537 INTVAL (operands[2]));
541 (define_expand "vec_initv2sf"
542 [(match_operand:V2SF 0 "register_operand" "")
543 (match_operand 1 "" "")]
546 ix86_expand_vector_init (false, operands[0], operands[1]);
550 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
552 ;; Parallel integral arithmetic
554 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
556 (define_insn "mmx_add<mode>3"
557 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
559 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
560 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
561 "TARGET_MMX && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
562 "padd<mmxvecsize>\t{%2, %0|%0, %2}"
563 [(set_attr "type" "mmxadd")
564 (set_attr "mode" "DI")])
566 (define_insn "mmx_adddi3"
567 [(set (match_operand:DI 0 "register_operand" "=y")
569 [(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
570 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
572 "TARGET_MMX && ix86_binary_operator_ok (PLUS, DImode, operands)"
573 "paddq\t{%2, %0|%0, %2}"
574 [(set_attr "type" "mmxadd")
575 (set_attr "mode" "DI")])
577 (define_insn "mmx_ssadd<mode>3"
578 [(set (match_operand:MMXMODE12 0 "register_operand" "=y")
580 (match_operand:MMXMODE12 1 "nonimmediate_operand" "%0")
581 (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
583 "padds<mmxvecsize>\t{%2, %0|%0, %2}"
584 [(set_attr "type" "mmxadd")
585 (set_attr "mode" "DI")])
587 (define_insn "mmx_usadd<mode>3"
588 [(set (match_operand:MMXMODE12 0 "register_operand" "=y")
590 (match_operand:MMXMODE12 1 "nonimmediate_operand" "%0")
591 (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
593 "paddus<mmxvecsize>\t{%2, %0|%0, %2}"
594 [(set_attr "type" "mmxadd")
595 (set_attr "mode" "DI")])
597 (define_insn "mmx_sub<mode>3"
598 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
600 (match_operand:MMXMODEI 1 "register_operand" "0")
601 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
603 "psub<mmxvecsize>\t{%2, %0|%0, %2}"
604 [(set_attr "type" "mmxadd")
605 (set_attr "mode" "DI")])
607 (define_insn "mmx_subdi3"
608 [(set (match_operand:DI 0 "register_operand" "=y")
610 [(minus:DI (match_operand:DI 1 "register_operand" "0")
611 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
614 "psubq\t{%2, %0|%0, %2}"
615 [(set_attr "type" "mmxadd")
616 (set_attr "mode" "DI")])
618 (define_insn "mmx_sssub<mode>3"
619 [(set (match_operand:MMXMODE12 0 "register_operand" "=y")
621 (match_operand:MMXMODE12 1 "register_operand" "0")
622 (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
624 "psubs<mmxvecsize>\t{%2, %0|%0, %2}"
625 [(set_attr "type" "mmxadd")
626 (set_attr "mode" "DI")])
628 (define_insn "mmx_ussub<mode>3"
629 [(set (match_operand:MMXMODE12 0 "register_operand" "=y")
631 (match_operand:MMXMODE12 1 "register_operand" "0")
632 (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
634 "psubus<mmxvecsize>\t{%2, %0|%0, %2}"
635 [(set_attr "type" "mmxadd")
636 (set_attr "mode" "DI")])
638 (define_insn "mmx_mulv4hi3"
639 [(set (match_operand:V4HI 0 "register_operand" "=y")
640 (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0")
641 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
642 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
643 "pmullw\t{%2, %0|%0, %2}"
644 [(set_attr "type" "mmxmul")
645 (set_attr "mode" "DI")])
647 (define_insn "mmx_smulv4hi3_highpart"
648 [(set (match_operand:V4HI 0 "register_operand" "=y")
651 (mult:V4SI (sign_extend:V4SI
652 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
654 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
656 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
657 "pmulhw\t{%2, %0|%0, %2}"
658 [(set_attr "type" "mmxmul")
659 (set_attr "mode" "DI")])
661 (define_insn "mmx_umulv4hi3_highpart"
662 [(set (match_operand:V4HI 0 "register_operand" "=y")
665 (mult:V4SI (zero_extend:V4SI
666 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
668 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
670 "(TARGET_SSE || TARGET_3DNOW_A)
671 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
672 "pmulhuw\t{%2, %0|%0, %2}"
673 [(set_attr "type" "mmxmul")
674 (set_attr "mode" "DI")])
676 (define_insn "mmx_pmaddwd"
677 [(set (match_operand:V2SI 0 "register_operand" "=y")
682 (match_operand:V4HI 1 "nonimmediate_operand" "%0")
683 (parallel [(const_int 0) (const_int 2)])))
686 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
687 (parallel [(const_int 0) (const_int 2)]))))
690 (vec_select:V2HI (match_dup 1)
691 (parallel [(const_int 1) (const_int 3)])))
693 (vec_select:V2HI (match_dup 2)
694 (parallel [(const_int 1) (const_int 3)]))))))]
695 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
696 "pmaddwd\t{%2, %0|%0, %2}"
697 [(set_attr "type" "mmxmul")
698 (set_attr "mode" "DI")])
700 (define_insn "mmx_pmulhrwv4hi3"
701 [(set (match_operand:V4HI 0 "register_operand" "=y")
707 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
709 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
710 (const_vector:V4SI [(const_int 32768) (const_int 32768)
711 (const_int 32768) (const_int 32768)]))
713 "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
714 "pmulhrw\\t{%2, %0|%0, %2}"
715 [(set_attr "type" "mmxmul")
716 (set_attr "mode" "DI")])
718 (define_insn "sse2_umulsidi3"
719 [(set (match_operand:DI 0 "register_operand" "=y")
723 (match_operand:V2SI 1 "nonimmediate_operand" "%0")
724 (parallel [(const_int 0)])))
727 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
728 (parallel [(const_int 0)])))))]
729 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)"
730 "pmuludq\t{%2, %0|%0, %2}"
731 [(set_attr "type" "mmxmul")
732 (set_attr "mode" "DI")])
734 (define_insn "mmx_umaxv8qi3"
735 [(set (match_operand:V8QI 0 "register_operand" "=y")
736 (umax:V8QI (match_operand:V8QI 1 "nonimmediate_operand" "%0")
737 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
738 "(TARGET_SSE || TARGET_3DNOW_A)
739 && ix86_binary_operator_ok (UMAX, V8QImode, operands)"
740 "pmaxub\t{%2, %0|%0, %2}"
741 [(set_attr "type" "mmxadd")
742 (set_attr "mode" "DI")])
744 (define_insn "mmx_smaxv4hi3"
745 [(set (match_operand:V4HI 0 "register_operand" "=y")
746 (smax:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0")
747 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
748 "(TARGET_SSE || TARGET_3DNOW_A)
749 && ix86_binary_operator_ok (SMAX, V4HImode, operands)"
750 "pmaxsw\t{%2, %0|%0, %2}"
751 [(set_attr "type" "mmxadd")
752 (set_attr "mode" "DI")])
754 (define_insn "mmx_uminv8qi3"
755 [(set (match_operand:V8QI 0 "register_operand" "=y")
756 (umin:V8QI (match_operand:V8QI 1 "nonimmediate_operand" "%0")
757 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
758 "(TARGET_SSE || TARGET_3DNOW_A)
759 && ix86_binary_operator_ok (UMIN, V8QImode, operands)"
760 "pminub\t{%2, %0|%0, %2}"
761 [(set_attr "type" "mmxadd")
762 (set_attr "mode" "DI")])
764 (define_insn "mmx_sminv4hi3"
765 [(set (match_operand:V4HI 0 "register_operand" "=y")
766 (smin:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0")
767 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
768 "(TARGET_SSE || TARGET_3DNOW_A)
769 && ix86_binary_operator_ok (SMIN, V4HImode, operands)"
770 "pminsw\t{%2, %0|%0, %2}"
771 [(set_attr "type" "mmxadd")
772 (set_attr "mode" "DI")])
774 (define_insn "mmx_ashr<mode>3"
775 [(set (match_operand:MMXMODE24 0 "register_operand" "=y")
777 (match_operand:MMXMODE24 1 "register_operand" "0")
778 (match_operand:DI 2 "nonmemory_operand" "yi")))]
780 "psra<mmxvecsize>\t{%2, %0|%0, %2}"
781 [(set_attr "type" "mmxshft")
782 (set_attr "mode" "DI")])
784 (define_insn "mmx_lshr<mode>3"
785 [(set (match_operand:MMXMODE24 0 "register_operand" "=y")
787 (match_operand:MMXMODE24 1 "register_operand" "0")
788 (match_operand:DI 2 "nonmemory_operand" "yi")))]
790 "psrl<mmxvecsize>\t{%2, %0|%0, %2}"
791 [(set_attr "type" "mmxshft")
792 (set_attr "mode" "DI")])
794 (define_insn "mmx_lshrdi3"
795 [(set (match_operand:DI 0 "register_operand" "=y")
797 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
798 (match_operand:DI 2 "nonmemory_operand" "yi"))]
801 "psrlq\t{%2, %0|%0, %2}"
802 [(set_attr "type" "mmxshft")
803 (set_attr "mode" "DI")])
805 (define_insn "mmx_ashl<mode>3"
806 [(set (match_operand:MMXMODE24 0 "register_operand" "=y")
808 (match_operand:MMXMODE24 1 "register_operand" "0")
809 (match_operand:DI 2 "nonmemory_operand" "yi")))]
811 "psll<mmxvecsize>\t{%2, %0|%0, %2}"
812 [(set_attr "type" "mmxshft")
813 (set_attr "mode" "DI")])
815 (define_insn "mmx_ashldi3"
816 [(set (match_operand:DI 0 "register_operand" "=y")
818 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
819 (match_operand:DI 2 "nonmemory_operand" "yi"))]
822 "psllq\t{%2, %0|%0, %2}"
823 [(set_attr "type" "mmxshft")
824 (set_attr "mode" "DI")])
826 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
828 ;; Parallel integral comparisons
830 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
832 (define_insn "mmx_eq<mode>3"
833 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
835 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
836 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
837 "TARGET_MMX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
838 "pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}"
839 [(set_attr "type" "mmxcmp")
840 (set_attr "mode" "DI")])
842 (define_insn "mmx_gt<mode>3"
843 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
845 (match_operand:MMXMODEI 1 "register_operand" "0")
846 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
848 "pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}"
849 [(set_attr "type" "mmxcmp")
850 (set_attr "mode" "DI")])
852 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
854 ;; Parallel integral logical operations
856 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
858 (define_insn "mmx_and<mode>3"
859 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
861 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
862 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
863 "TARGET_MMX && ix86_binary_operator_ok (AND, <MODE>mode, operands)"
864 "pand\t{%2, %0|%0, %2}"
865 [(set_attr "type" "mmxadd")
866 (set_attr "mode" "DI")])
868 (define_insn "mmx_nand<mode>3"
869 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
871 (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0"))
872 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
874 "pandn\t{%2, %0|%0, %2}"
875 [(set_attr "type" "mmxadd")
876 (set_attr "mode" "DI")])
878 (define_insn "mmx_ior<mode>3"
879 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
881 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
882 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
883 "TARGET_MMX && ix86_binary_operator_ok (IOR, <MODE>mode, operands)"
884 "por\t{%2, %0|%0, %2}"
885 [(set_attr "type" "mmxadd")
886 (set_attr "mode" "DI")])
888 (define_insn "mmx_xor<mode>3"
889 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
891 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
892 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
893 "TARGET_MMX && ix86_binary_operator_ok (XOR, <MODE>mode, operands)"
894 "pxor\t{%2, %0|%0, %2}"
895 [(set_attr "type" "mmxadd")
896 (set_attr "mode" "DI")
897 (set_attr "memory" "none")])
899 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
901 ;; Parallel integral element swizzling
903 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
905 (define_insn "mmx_packsswb"
906 [(set (match_operand:V8QI 0 "register_operand" "=y")
909 (match_operand:V4HI 1 "register_operand" "0"))
911 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))]
913 "packsswb\t{%2, %0|%0, %2}"
914 [(set_attr "type" "mmxshft")
915 (set_attr "mode" "DI")])
917 (define_insn "mmx_packssdw"
918 [(set (match_operand:V4HI 0 "register_operand" "=y")
921 (match_operand:V2SI 1 "register_operand" "0"))
923 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))))]
925 "packssdw\t{%2, %0|%0, %2}"
926 [(set_attr "type" "mmxshft")
927 (set_attr "mode" "DI")])
929 (define_insn "mmx_packuswb"
930 [(set (match_operand:V8QI 0 "register_operand" "=y")
933 (match_operand:V4HI 1 "register_operand" "0"))
935 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))]
937 "packuswb\t{%2, %0|%0, %2}"
938 [(set_attr "type" "mmxshft")
939 (set_attr "mode" "DI")])
941 (define_insn "mmx_punpckhbw"
942 [(set (match_operand:V8QI 0 "register_operand" "=y")
945 (match_operand:V8QI 1 "register_operand" "0")
946 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
947 (parallel [(const_int 4) (const_int 12)
948 (const_int 5) (const_int 13)
949 (const_int 6) (const_int 14)
950 (const_int 7) (const_int 15)])))]
952 "punpckhbw\t{%2, %0|%0, %2}"
953 [(set_attr "type" "mmxcvt")
954 (set_attr "mode" "DI")])
956 (define_insn "mmx_punpcklbw"
957 [(set (match_operand:V8QI 0 "register_operand" "=y")
960 (match_operand:V8QI 1 "register_operand" "0")
961 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
962 (parallel [(const_int 0) (const_int 8)
963 (const_int 1) (const_int 9)
964 (const_int 2) (const_int 10)
965 (const_int 3) (const_int 11)])))]
967 "punpcklbw\t{%2, %0|%0, %2}"
968 [(set_attr "type" "mmxcvt")
969 (set_attr "mode" "DI")])
971 (define_insn "mmx_punpckhwd"
972 [(set (match_operand:V4HI 0 "register_operand" "=y")
975 (match_operand:V4HI 1 "register_operand" "0")
976 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
977 (parallel [(const_int 2) (const_int 6)
978 (const_int 3) (const_int 7)])))]
980 "punpckhwd\t{%2, %0|%0, %2}"
981 [(set_attr "type" "mmxcvt")
982 (set_attr "mode" "DI")])
984 (define_insn "mmx_punpcklwd"
985 [(set (match_operand:V4HI 0 "register_operand" "=y")
988 (match_operand:V4HI 1 "register_operand" "0")
989 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
990 (parallel [(const_int 0) (const_int 4)
991 (const_int 1) (const_int 5)])))]
993 "punpcklwd\t{%2, %0|%0, %2}"
994 [(set_attr "type" "mmxcvt")
995 (set_attr "mode" "DI")])
997 (define_insn "mmx_punpckhdq"
998 [(set (match_operand:V2SI 0 "register_operand" "=y")
1001 (match_operand:V2SI 1 "register_operand" "0")
1002 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))
1003 (parallel [(const_int 1)
1006 "punpckhdq\t{%2, %0|%0, %2}"
1007 [(set_attr "type" "mmxcvt")
1008 (set_attr "mode" "DI")])
1010 (define_insn "mmx_punpckldq"
1011 [(set (match_operand:V2SI 0 "register_operand" "=y")
1014 (match_operand:V2SI 1 "register_operand" "0")
1015 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))
1016 (parallel [(const_int 0)
1019 "punpckldq\t{%2, %0|%0, %2}"
1020 [(set_attr "type" "mmxcvt")
1021 (set_attr "mode" "DI")])
1023 (define_expand "mmx_pinsrw"
1024 [(set (match_operand:V4HI 0 "register_operand" "")
1027 (match_operand:SI 2 "nonimmediate_operand" ""))
1028 (match_operand:V4HI 1 "register_operand" "")
1029 (match_operand:SI 3 "const_0_to_3_operand" "")))]
1030 "TARGET_SSE || TARGET_3DNOW_A"
1032 operands[2] = gen_lowpart (HImode, operands[2]);
1033 operands[3] = GEN_INT (1 << INTVAL (operands[3]));
1036 (define_insn "*mmx_pinsrw"
1037 [(set (match_operand:V4HI 0 "register_operand" "=y")
1040 (match_operand:HI 2 "nonimmediate_operand" "rm"))
1041 (match_operand:V4HI 1 "register_operand" "0")
1042 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
1043 "TARGET_SSE || TARGET_3DNOW_A"
1045 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
1046 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
1048 [(set_attr "type" "mmxcvt")
1049 (set_attr "mode" "DI")])
1051 (define_insn "mmx_pextrw"
1052 [(set (match_operand:SI 0 "register_operand" "=r")
1055 (match_operand:V4HI 1 "register_operand" "y")
1056 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
1057 "TARGET_SSE || TARGET_3DNOW_A"
1058 "pextrw\t{%2, %1, %0|%0, %1, %2}"
1059 [(set_attr "type" "mmxcvt")
1060 (set_attr "mode" "DI")])
1062 (define_expand "mmx_pshufw"
1063 [(match_operand:V4HI 0 "register_operand" "")
1064 (match_operand:V4HI 1 "nonimmediate_operand" "")
1065 (match_operand:SI 2 "const_int_operand" "")]
1066 "TARGET_SSE || TARGET_3DNOW_A"
1068 int mask = INTVAL (operands[2]);
1069 emit_insn (gen_mmx_pshufw_1 (operands[0], operands[1],
1070 GEN_INT ((mask >> 0) & 3),
1071 GEN_INT ((mask >> 2) & 3),
1072 GEN_INT ((mask >> 4) & 3),
1073 GEN_INT ((mask >> 6) & 3)));
1077 (define_insn "mmx_pshufw_1"
1078 [(set (match_operand:V4HI 0 "register_operand" "=y")
1080 (match_operand:V4HI 1 "nonimmediate_operand" "ym")
1081 (parallel [(match_operand 2 "const_0_to_3_operand" "")
1082 (match_operand 3 "const_0_to_3_operand" "")
1083 (match_operand 4 "const_0_to_3_operand" "")
1084 (match_operand 5 "const_0_to_3_operand" "")])))]
1085 "TARGET_SSE || TARGET_3DNOW_A"
1088 mask |= INTVAL (operands[2]) << 0;
1089 mask |= INTVAL (operands[3]) << 2;
1090 mask |= INTVAL (operands[4]) << 4;
1091 mask |= INTVAL (operands[5]) << 6;
1092 operands[2] = GEN_INT (mask);
1094 return "pshufw\t{%2, %1, %0|%0, %1, %2}";
1096 [(set_attr "type" "mmxcvt")
1097 (set_attr "mode" "DI")])
1099 (define_insn "mmx_pswapdv2si2"
1100 [(set (match_operand:V2SI 0 "register_operand" "=y")
1102 (match_operand:V2SI 1 "nonimmediate_operand" "ym")
1103 (parallel [(const_int 1) (const_int 0)])))]
1105 "pswapd\\t{%1, %0|%0, %1}"
1106 [(set_attr "type" "mmxcvt")
1107 (set_attr "mode" "DI")])
1109 (define_insn "*vec_dupv4hi"
1110 [(set (match_operand:V4HI 0 "register_operand" "=y")
1113 (match_operand:SI 1 "register_operand" "0"))))]
1115 "pshufw\t{$0, %0, %0|%0, %0, 0}"
1116 [(set_attr "type" "mmxcvt")
1117 (set_attr "mode" "DI")])
1119 (define_insn "*vec_dupv2si"
1120 [(set (match_operand:V2SI 0 "register_operand" "=y")
1122 (match_operand:SI 1 "register_operand" "0")))]
1125 [(set_attr "type" "mmxcvt")
1126 (set_attr "mode" "DI")])
1128 (define_insn "*mmx_concatv2si"
1129 [(set (match_operand:V2SI 0 "register_operand" "=y,y")
1131 (match_operand:SI 1 "nonimmediate_operand" " 0,rm")
1132 (match_operand:SI 2 "vector_move_operand" "ym,C")))]
1133 "TARGET_MMX && !TARGET_SSE"
1135 punpckldq\t{%2, %0|%0, %2}
1136 movd\t{%1, %0|%0, %1}"
1137 [(set_attr "type" "mmxcvt,mmxmov")
1138 (set_attr "mode" "DI")])
1140 (define_expand "vec_setv2si"
1141 [(match_operand:V2SI 0 "register_operand" "")
1142 (match_operand:SI 1 "register_operand" "")
1143 (match_operand 2 "const_int_operand" "")]
1146 ix86_expand_vector_set (false, operands[0], operands[1],
1147 INTVAL (operands[2]));
1151 (define_insn_and_split "*vec_extractv2si_0"
1152 [(set (match_operand:SI 0 "nonimmediate_operand" "=x,y,m,m,frxy")
1154 (match_operand:V2SI 1 "nonimmediate_operand" " x,y,x,y,m")
1155 (parallel [(const_int 0)])))]
1156 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1158 "&& reload_completed"
1161 rtx op1 = operands[1];
1163 op1 = gen_rtx_REG (SImode, REGNO (op1));
1165 op1 = gen_lowpart (SImode, op1);
1166 emit_move_insn (operands[0], op1);
1170 (define_insn "*vec_extractv2si_1"
1171 [(set (match_operand:SI 0 "nonimmediate_operand" "=y,Y,Y,x,frxy")
1173 (match_operand:V2SI 1 "nonimmediate_operand" " 0,0,Y,0,o")
1174 (parallel [(const_int 1)])))]
1175 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1179 pshufd\t{$85, %1, %0|%0, %1, 85}
1182 [(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,*")
1183 (set_attr "mode" "DI,TI,TI,V4SF,SI")])
1186 [(set (match_operand:SI 0 "register_operand" "")
1188 (match_operand:V2SI 1 "memory_operand" "")
1189 (parallel [(const_int 1)])))]
1190 "TARGET_MMX && reload_completed"
1193 operands[1] = adjust_address (operands[1], SImode, 4);
1194 emit_move_insn (operands[0], operands[1]);
1198 (define_expand "vec_extractv2si"
1199 [(match_operand:SI 0 "register_operand" "")
1200 (match_operand:V2SI 1 "register_operand" "")
1201 (match_operand 2 "const_int_operand" "")]
1204 ix86_expand_vector_extract (false, operands[0], operands[1],
1205 INTVAL (operands[2]));
1209 (define_expand "vec_initv2si"
1210 [(match_operand:V2SI 0 "register_operand" "")
1211 (match_operand 1 "" "")]
1214 ix86_expand_vector_init (false, operands[0], operands[1]);
1218 (define_expand "vec_setv4hi"
1219 [(match_operand:V4HI 0 "register_operand" "")
1220 (match_operand:HI 1 "register_operand" "")
1221 (match_operand 2 "const_int_operand" "")]
1224 ix86_expand_vector_set (false, operands[0], operands[1],
1225 INTVAL (operands[2]));
1229 (define_expand "vec_extractv4hi"
1230 [(match_operand:HI 0 "register_operand" "")
1231 (match_operand:V4HI 1 "register_operand" "")
1232 (match_operand 2 "const_int_operand" "")]
1235 ix86_expand_vector_extract (false, operands[0], operands[1],
1236 INTVAL (operands[2]));
1240 (define_expand "vec_initv4hi"
1241 [(match_operand:V4HI 0 "register_operand" "")
1242 (match_operand 1 "" "")]
1245 ix86_expand_vector_init (false, operands[0], operands[1]);
1249 (define_expand "vec_setv8qi"
1250 [(match_operand:V8QI 0 "register_operand" "")
1251 (match_operand:QI 1 "register_operand" "")
1252 (match_operand 2 "const_int_operand" "")]
1255 ix86_expand_vector_set (false, operands[0], operands[1],
1256 INTVAL (operands[2]));
1260 (define_expand "vec_extractv8qi"
1261 [(match_operand:QI 0 "register_operand" "")
1262 (match_operand:V8QI 1 "register_operand" "")
1263 (match_operand 2 "const_int_operand" "")]
1266 ix86_expand_vector_extract (false, operands[0], operands[1],
1267 INTVAL (operands[2]));
1271 (define_expand "vec_initv8qi"
1272 [(match_operand:V8QI 0 "register_operand" "")
1273 (match_operand 1 "" "")]
1276 ix86_expand_vector_init (false, operands[0], operands[1]);
1280 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1284 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1286 (define_insn "mmx_uavgv8qi3"
1287 [(set (match_operand:V8QI 0 "register_operand" "=y")
1293 (match_operand:V8QI 1 "nonimmediate_operand" "%0"))
1295 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))
1296 (const_vector:V8HI [(const_int 1) (const_int 1)
1297 (const_int 1) (const_int 1)
1298 (const_int 1) (const_int 1)
1299 (const_int 1) (const_int 1)]))
1301 "(TARGET_SSE || TARGET_3DNOW)
1302 && ix86_binary_operator_ok (PLUS, V8QImode, operands)"
1304 /* These two instructions have the same operation, but their encoding
1305 is different. Prefer the one that is de facto standard. */
1306 if (TARGET_SSE || TARGET_3DNOW_A)
1307 return "pavgb\t{%2, %0|%0, %2}";
1309 return "pavgusb\\t{%2, %0|%0, %2}";
1311 [(set_attr "type" "mmxshft")
1312 (set_attr "mode" "DI")])
1314 (define_insn "mmx_uavgv4hi3"
1315 [(set (match_operand:V4HI 0 "register_operand" "=y")
1321 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
1323 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
1324 (const_vector:V4SI [(const_int 1) (const_int 1)
1325 (const_int 1) (const_int 1)]))
1327 "(TARGET_SSE || TARGET_3DNOW_A)
1328 && ix86_binary_operator_ok (PLUS, V4HImode, operands)"
1329 "pavgw\t{%2, %0|%0, %2}"
1330 [(set_attr "type" "mmxshft")
1331 (set_attr "mode" "DI")])
1333 (define_insn "mmx_psadbw"
1334 [(set (match_operand:DI 0 "register_operand" "=y")
1335 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
1336 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
1338 "TARGET_SSE || TARGET_3DNOW_A"
1339 "psadbw\t{%2, %0|%0, %2}"
1340 [(set_attr "type" "mmxshft")
1341 (set_attr "mode" "DI")])
1343 (define_insn "mmx_pmovmskb"
1344 [(set (match_operand:SI 0 "register_operand" "=r")
1345 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
1347 "TARGET_SSE || TARGET_3DNOW_A"
1348 "pmovmskb\t{%1, %0|%0, %1}"
1349 [(set_attr "type" "ssecvt")
1350 (set_attr "mode" "V4SF")])
1352 (define_expand "mmx_maskmovq"
1353 [(set (match_operand:V8QI 0 "memory_operand" "")
1354 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1355 (match_operand:V8QI 2 "register_operand" "y")
1358 "TARGET_SSE || TARGET_3DNOW_A"
1361 (define_insn "*mmx_maskmovq"
1362 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
1363 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1364 (match_operand:V8QI 2 "register_operand" "y")
1365 (mem:V8QI (match_dup 0))]
1367 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
1368 ;; @@@ check ordering of operands in intel/nonintel syntax
1369 "maskmovq\t{%2, %1|%1, %2}"
1370 [(set_attr "type" "mmxcvt")
1371 (set_attr "mode" "DI")])
1373 (define_insn "*mmx_maskmovq_rex"
1374 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
1375 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1376 (match_operand:V8QI 2 "register_operand" "y")
1377 (mem:V8QI (match_dup 0))]
1379 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
1380 ;; @@@ check ordering of operands in intel/nonintel syntax
1381 "maskmovq\t{%2, %1|%1, %2}"
1382 [(set_attr "type" "mmxcvt")
1383 (set_attr "mode" "DI")])
1385 (define_insn "mmx_emms"
1386 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
1387 (clobber (reg:XF 8))
1388 (clobber (reg:XF 9))
1389 (clobber (reg:XF 10))
1390 (clobber (reg:XF 11))
1391 (clobber (reg:XF 12))
1392 (clobber (reg:XF 13))
1393 (clobber (reg:XF 14))
1394 (clobber (reg:XF 15))
1395 (clobber (reg:DI 29))
1396 (clobber (reg:DI 30))
1397 (clobber (reg:DI 31))
1398 (clobber (reg:DI 32))
1399 (clobber (reg:DI 33))
1400 (clobber (reg:DI 34))
1401 (clobber (reg:DI 35))
1402 (clobber (reg:DI 36))]
1405 [(set_attr "type" "mmx")
1406 (set_attr "memory" "unknown")])
1408 (define_insn "mmx_femms"
1409 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
1410 (clobber (reg:XF 8))
1411 (clobber (reg:XF 9))
1412 (clobber (reg:XF 10))
1413 (clobber (reg:XF 11))
1414 (clobber (reg:XF 12))
1415 (clobber (reg:XF 13))
1416 (clobber (reg:XF 14))
1417 (clobber (reg:XF 15))
1418 (clobber (reg:DI 29))
1419 (clobber (reg:DI 30))
1420 (clobber (reg:DI 31))
1421 (clobber (reg:DI 32))
1422 (clobber (reg:DI 33))
1423 (clobber (reg:DI 34))
1424 (clobber (reg:DI 35))
1425 (clobber (reg:DI 36))]
1428 [(set_attr "type" "mmx")
1429 (set_attr "memory" "none")])