1 ;; GCC machine description for MMX and 3dNOW! instructions
2 ;; Copyright (C) 2005, 2007, 2008, 2009
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; The MMX and 3dNOW! patterns are in the same file because they use
22 ;; the same register file, and 3dNOW! adds a number of extensions to
23 ;; the base integer MMX isa.
25 ;; Note! Except for the basic move instructions, *all* of these
26 ;; patterns are outside the normal optabs namespace. This is because
27 ;; use of these registers requires the insertion of emms or femms
28 ;; instructions to return to normal fpu mode. The compiler doesn't
29 ;; know how to do that itself, which means it's up to the user. Which
30 ;; means that we should never use any of these patterns except at the
31 ;; direction of the user via a builtin.
33 ;; 8 byte integral modes handled by MMX (and by extension, SSE)
34 (define_mode_iterator MMXMODEI [V8QI V4HI V2SI])
35 (define_mode_iterator MMXMODEI8 [V8QI V4HI V2SI V1DI])
37 ;; All 8-byte vector modes handled by MMX
38 (define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF])
41 (define_mode_iterator MMXMODE12 [V8QI V4HI])
42 (define_mode_iterator MMXMODE24 [V4HI V2SI])
43 (define_mode_iterator MMXMODE248 [V4HI V2SI V1DI])
45 ;; Mapping from integer vector mode to mnemonic suffix
46 (define_mode_attr mmxvecsize [(V8QI "b") (V4HI "w") (V2SI "d") (V1DI "q")])
48 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
52 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
54 ;; All of these patterns are enabled for MMX as well as 3dNOW.
55 ;; This is essential for maintaining stable calling conventions.
57 (define_expand "mov<mode>"
58 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand" "")
59 (match_operand:MMXMODEI8 1 "nonimmediate_operand" ""))]
62 ix86_expand_vector_move (<MODE>mode, operands);
66 (define_insn "*mov<mode>_internal_rex64"
67 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
68 "=rm,r,!?y,!?y ,m ,!y,*Y2,x,x ,m,r,Yi")
69 (match_operand:MMXMODEI8 1 "vector_move_operand"
70 "Cr ,m,C ,!?ym,!?y,*Y2,!y,C,xm,x,Yi,r"))]
71 "TARGET_64BIT && TARGET_MMX
72 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
74 mov{q}\t{%1, %0|%0, %1}
75 mov{q}\t{%1, %0|%0, %1}
79 movdq2q\t{%1, %0|%0, %1}
80 movq2dq\t{%1, %0|%0, %1}
82 %vmovq\t{%1, %0|%0, %1}
83 %vmovq\t{%1, %0|%0, %1}
84 %vmovq\t{%1, %0|%0, %1}
85 %vmovq\t{%1, %0|%0, %1}"
86 [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,ssemov")
87 (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*")
88 (set_attr "prefix_rep" "*,*,*,*,*,1,1,*,1,*,*,*")
89 (set_attr "prefix_data16" "*,*,*,*,*,*,*,*,*,1,1,1")
90 (set (attr "prefix_rex")
91 (if_then_else (eq_attr "alternative" "8,9")
92 (symbol_ref "x86_extended_reg_mentioned_p (insn)")
95 (if_then_else (eq_attr "alternative" "7,8,9,10,11")
96 (const_string "maybe_vex")
97 (const_string "orig")))
98 (set_attr "mode" "DI")])
100 (define_insn "*mov<mode>_internal_avx"
101 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
102 "=!?y,!?y,m ,!y ,*Y2,*Y2,*Y2 ,m ,r ,m")
103 (match_operand:MMXMODEI8 1 "vector_move_operand"
104 "C ,!ym,!?y,*Y2,!y ,C ,*Y2m,*Y2,irm,r"))]
106 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
109 movq\t{%1, %0|%0, %1}
110 movq\t{%1, %0|%0, %1}
111 movdq2q\t{%1, %0|%0, %1}
112 movq2dq\t{%1, %0|%0, %1}
114 vmovq\t{%1, %0|%0, %1}
115 vmovq\t{%1, %0|%0, %1}
118 [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,*,*")
119 (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*")
120 (set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*")
122 (if_then_else (eq_attr "alternative" "5,6,7")
124 (const_string "orig")))
125 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,DI,DI,DI")])
127 (define_insn "*mov<mode>_internal"
128 [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
129 "=!?y,!?y,m ,!y ,*Y2,*Y2,*Y2 ,m ,*x,*x,*x,m ,r ,m")
130 (match_operand:MMXMODEI8 1 "vector_move_operand"
131 "C ,!ym,!?y,*Y2,!y ,C ,*Y2m,*Y2,C ,*x,m ,*x,irm,r"))]
133 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
136 movq\t{%1, %0|%0, %1}
137 movq\t{%1, %0|%0, %1}
138 movdq2q\t{%1, %0|%0, %1}
139 movq2dq\t{%1, %0|%0, %1}
141 movq\t{%1, %0|%0, %1}
142 movq\t{%1, %0|%0, %1}
144 movaps\t{%1, %0|%0, %1}
145 movlps\t{%1, %0|%0, %1}
146 movlps\t{%1, %0|%0, %1}
149 [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov,*,*")
150 (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*,*,*,*")
151 (set_attr "prefix_rep" "*,*,*,1,1,*,1,*,*,*,*,*,*,*")
152 (set_attr "prefix_data16" "*,*,*,*,*,*,*,1,*,*,*,*,*,*")
153 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
155 (define_expand "movv2sf"
156 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
157 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
160 ix86_expand_vector_move (V2SFmode, operands);
164 (define_insn "*movv2sf_internal_rex64_avx"
165 [(set (match_operand:V2SF 0 "nonimmediate_operand"
166 "=rm,r ,!?y,!?y ,m ,!y,Y2,x,x,x,m,r,x")
167 (match_operand:V2SF 1 "vector_move_operand"
168 "Cr ,m ,C ,!?ym,!y,Y2,!y,C,x,m,x,x,r"))]
169 "TARGET_64BIT && TARGET_AVX
170 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
172 mov{q}\t{%1, %0|%0, %1}
173 mov{q}\t{%1, %0|%0, %1}
175 movq\t{%1, %0|%0, %1}
176 movq\t{%1, %0|%0, %1}
177 movdq2q\t{%1, %0|%0, %1}
178 movq2dq\t{%1, %0|%0, %1}
180 vmovaps\t{%1, %0|%0, %1}
181 vmovlps\t{%1, %0, %0|%0, %0, %1}
182 vmovlps\t{%1, %0|%0, %1}
183 vmovq\t{%1, %0|%0, %1}
184 vmovq\t{%1, %0|%0, %1}"
185 [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov")
186 (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*,*")
187 (set_attr "prefix_rep" "*,*,*,*,*,1,1,*,*,*,*,*,*")
188 (set_attr "length_vex" "*,*,*,*,*,*,*,*,*,*,*,4,4")
190 (if_then_else (eq_attr "alternative" "7,8,9,10,11,12")
192 (const_string "orig")))
193 (set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
195 (define_insn "*movv2sf_internal_rex64"
196 [(set (match_operand:V2SF 0 "nonimmediate_operand"
197 "=rm,r ,!?y,!?y ,m ,!y,*Y2,x,x,x,m,r,Yi")
198 (match_operand:V2SF 1 "vector_move_operand"
199 "Cr ,m ,C ,!?ym,!y,*Y2,!y,C,x,m,x,Yi,r"))]
200 "TARGET_64BIT && TARGET_MMX
201 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
203 mov{q}\t{%1, %0|%0, %1}
204 mov{q}\t{%1, %0|%0, %1}
206 movq\t{%1, %0|%0, %1}
207 movq\t{%1, %0|%0, %1}
208 movdq2q\t{%1, %0|%0, %1}
209 movq2dq\t{%1, %0|%0, %1}
211 movaps\t{%1, %0|%0, %1}
212 movlps\t{%1, %0|%0, %1}
213 movlps\t{%1, %0|%0, %1}
214 movd\t{%1, %0|%0, %1}
215 movd\t{%1, %0|%0, %1}"
216 [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov")
217 (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*,*")
218 (set_attr "prefix_rep" "*,*,*,*,*,1,1,*,*,*,*,*,*")
219 (set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
221 (define_insn "*movv2sf_internal_avx"
222 [(set (match_operand:V2SF 0 "nonimmediate_operand"
223 "=!?y,!?y ,m ,!y ,*Y2,*x,*x,*x,m ,r ,m")
224 (match_operand:V2SF 1 "vector_move_operand"
225 "C ,!?ym,!?y,*Y2,!y ,C ,*x,m ,*x,irm,r"))]
227 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
230 movq\t{%1, %0|%0, %1}
231 movq\t{%1, %0|%0, %1}
232 movdq2q\t{%1, %0|%0, %1}
233 movq2dq\t{%1, %0|%0, %1}
235 vmovaps\t{%1, %0|%0, %1}
236 vmovlps\t{%1, %0, %0|%0, %0, %1}
237 vmovlps\t{%1, %0|%0, %1}
240 [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*")
241 (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*")
242 (set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*,*")
244 (if_then_else (eq_attr "alternative" "5,6,7,8")
246 (const_string "orig")))
247 (set_attr "mode" "DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
249 (define_insn "*movv2sf_internal"
250 [(set (match_operand:V2SF 0 "nonimmediate_operand"
251 "=!?y,!?y ,m ,!y ,*Y2,*x,*x,*x,m ,r ,m")
252 (match_operand:V2SF 1 "vector_move_operand"
253 "C ,!?ym,!?y,*Y2,!y ,C ,*x,m ,*x,irm,r"))]
255 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
258 movq\t{%1, %0|%0, %1}
259 movq\t{%1, %0|%0, %1}
260 movdq2q\t{%1, %0|%0, %1}
261 movq2dq\t{%1, %0|%0, %1}
263 movaps\t{%1, %0|%0, %1}
264 movlps\t{%1, %0|%0, %1}
265 movlps\t{%1, %0|%0, %1}
268 [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*")
269 (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*")
270 (set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*,*")
271 (set_attr "mode" "DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
273 ;; %%% This multiword shite has got to go.
275 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
276 (match_operand:MMXMODE 1 "general_operand" ""))]
277 "!TARGET_64BIT && reload_completed
278 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
279 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
281 "ix86_split_long_move (operands); DONE;")
283 (define_expand "push<mode>1"
284 [(match_operand:MMXMODE 0 "register_operand" "")]
287 ix86_expand_push (<MODE>mode, operands[0]);
291 (define_expand "movmisalign<mode>"
292 [(set (match_operand:MMXMODE 0 "nonimmediate_operand" "")
293 (match_operand:MMXMODE 1 "nonimmediate_operand" ""))]
296 ix86_expand_vector_move (<MODE>mode, operands);
300 (define_insn "sse_movntdi"
301 [(set (match_operand:DI 0 "memory_operand" "=m")
302 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
304 "TARGET_SSE || TARGET_3DNOW_A"
305 "movntq\t{%1, %0|%0, %1}"
306 [(set_attr "type" "mmxmov")
307 (set_attr "mode" "DI")])
309 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
311 ;; Parallel single-precision floating point arithmetic
313 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
315 (define_expand "mmx_addv2sf3"
316 [(set (match_operand:V2SF 0 "register_operand" "")
318 (match_operand:V2SF 1 "nonimmediate_operand" "")
319 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
321 "ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
323 (define_insn "*mmx_addv2sf3"
324 [(set (match_operand:V2SF 0 "register_operand" "=y")
325 (plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
326 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
327 "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
328 "pfadd\t{%2, %0|%0, %2}"
329 [(set_attr "type" "mmxadd")
330 (set_attr "prefix_extra" "1")
331 (set_attr "mode" "V2SF")])
333 (define_expand "mmx_subv2sf3"
334 [(set (match_operand:V2SF 0 "register_operand" "")
335 (minus:V2SF (match_operand:V2SF 1 "register_operand" "")
336 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
340 (define_expand "mmx_subrv2sf3"
341 [(set (match_operand:V2SF 0 "register_operand" "")
342 (minus:V2SF (match_operand:V2SF 2 "register_operand" "")
343 (match_operand:V2SF 1 "nonimmediate_operand" "")))]
347 (define_insn "*mmx_subv2sf3"
348 [(set (match_operand:V2SF 0 "register_operand" "=y,y")
349 (minus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "0,ym")
350 (match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))]
351 "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
353 pfsub\t{%2, %0|%0, %2}
354 pfsubr\t{%1, %0|%0, %1}"
355 [(set_attr "type" "mmxadd")
356 (set_attr "prefix_extra" "1")
357 (set_attr "mode" "V2SF")])
359 (define_expand "mmx_mulv2sf3"
360 [(set (match_operand:V2SF 0 "register_operand" "")
361 (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "")
362 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
364 "ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
366 (define_insn "*mmx_mulv2sf3"
367 [(set (match_operand:V2SF 0 "register_operand" "=y")
368 (mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
369 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
370 "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
371 "pfmul\t{%2, %0|%0, %2}"
372 [(set_attr "type" "mmxmul")
373 (set_attr "prefix_extra" "1")
374 (set_attr "mode" "V2SF")])
376 ;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
377 ;; isn't really correct, as those rtl operators aren't defined when
378 ;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
380 (define_expand "mmx_<code>v2sf3"
381 [(set (match_operand:V2SF 0 "register_operand" "")
383 (match_operand:V2SF 1 "nonimmediate_operand" "")
384 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
387 if (!flag_finite_math_only)
388 operands[1] = force_reg (V2SFmode, operands[1]);
389 ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);
392 (define_insn "*mmx_<code>v2sf3_finite"
393 [(set (match_operand:V2SF 0 "register_operand" "=y")
395 (match_operand:V2SF 1 "nonimmediate_operand" "%0")
396 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
397 "TARGET_3DNOW && flag_finite_math_only
398 && ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
399 "pf<maxminfprefix>\t{%2, %0|%0, %2}"
400 [(set_attr "type" "mmxadd")
401 (set_attr "prefix_extra" "1")
402 (set_attr "mode" "V2SF")])
404 (define_insn "*mmx_<code>v2sf3"
405 [(set (match_operand:V2SF 0 "register_operand" "=y")
407 (match_operand:V2SF 1 "register_operand" "0")
408 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
410 "pf<maxminfprefix>\t{%2, %0|%0, %2}"
411 [(set_attr "type" "mmxadd")
412 (set_attr "prefix_extra" "1")
413 (set_attr "mode" "V2SF")])
415 (define_insn "mmx_rcpv2sf2"
416 [(set (match_operand:V2SF 0 "register_operand" "=y")
417 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
420 "pfrcp\t{%1, %0|%0, %1}"
421 [(set_attr "type" "mmx")
422 (set_attr "prefix_extra" "1")
423 (set_attr "mode" "V2SF")])
425 (define_insn "mmx_rcpit1v2sf3"
426 [(set (match_operand:V2SF 0 "register_operand" "=y")
427 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
428 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
431 "pfrcpit1\t{%2, %0|%0, %2}"
432 [(set_attr "type" "mmx")
433 (set_attr "prefix_extra" "1")
434 (set_attr "mode" "V2SF")])
436 (define_insn "mmx_rcpit2v2sf3"
437 [(set (match_operand:V2SF 0 "register_operand" "=y")
438 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
439 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
442 "pfrcpit2\t{%2, %0|%0, %2}"
443 [(set_attr "type" "mmx")
444 (set_attr "prefix_extra" "1")
445 (set_attr "mode" "V2SF")])
447 (define_insn "mmx_rsqrtv2sf2"
448 [(set (match_operand:V2SF 0 "register_operand" "=y")
449 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
452 "pfrsqrt\t{%1, %0|%0, %1}"
453 [(set_attr "type" "mmx")
454 (set_attr "prefix_extra" "1")
455 (set_attr "mode" "V2SF")])
457 (define_insn "mmx_rsqit1v2sf3"
458 [(set (match_operand:V2SF 0 "register_operand" "=y")
459 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
460 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
463 "pfrsqit1\t{%2, %0|%0, %2}"
464 [(set_attr "type" "mmx")
465 (set_attr "prefix_extra" "1")
466 (set_attr "mode" "V2SF")])
468 (define_insn "mmx_haddv2sf3"
469 [(set (match_operand:V2SF 0 "register_operand" "=y")
473 (match_operand:V2SF 1 "register_operand" "0")
474 (parallel [(const_int 0)]))
475 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
478 (match_operand:V2SF 2 "nonimmediate_operand" "ym")
479 (parallel [(const_int 0)]))
480 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
482 "pfacc\t{%2, %0|%0, %2}"
483 [(set_attr "type" "mmxadd")
484 (set_attr "prefix_extra" "1")
485 (set_attr "mode" "V2SF")])
487 (define_insn "mmx_hsubv2sf3"
488 [(set (match_operand:V2SF 0 "register_operand" "=y")
492 (match_operand:V2SF 1 "register_operand" "0")
493 (parallel [(const_int 0)]))
494 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
497 (match_operand:V2SF 2 "nonimmediate_operand" "ym")
498 (parallel [(const_int 0)]))
499 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))))]
501 "pfnacc\t{%2, %0|%0, %2}"
502 [(set_attr "type" "mmxadd")
503 (set_attr "prefix_extra" "1")
504 (set_attr "mode" "V2SF")])
506 (define_insn "mmx_addsubv2sf3"
507 [(set (match_operand:V2SF 0 "register_operand" "=y")
510 (match_operand:V2SF 1 "register_operand" "0")
511 (match_operand:V2SF 2 "nonimmediate_operand" "ym"))
512 (minus:V2SF (match_dup 1) (match_dup 2))
515 "pfpnacc\t{%2, %0|%0, %2}"
516 [(set_attr "type" "mmxadd")
517 (set_attr "prefix_extra" "1")
518 (set_attr "mode" "V2SF")])
520 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
522 ;; Parallel single-precision floating point comparisons
524 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
526 (define_expand "mmx_eqv2sf3"
527 [(set (match_operand:V2SI 0 "register_operand" "")
528 (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "")
529 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
531 "ix86_fixup_binary_operands_no_copy (EQ, V2SFmode, operands);")
533 (define_insn "*mmx_eqv2sf3"
534 [(set (match_operand:V2SI 0 "register_operand" "=y")
535 (eq:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "%0")
536 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
537 "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
538 "pfcmpeq\t{%2, %0|%0, %2}"
539 [(set_attr "type" "mmxcmp")
540 (set_attr "prefix_extra" "1")
541 (set_attr "mode" "V2SF")])
543 (define_insn "mmx_gtv2sf3"
544 [(set (match_operand:V2SI 0 "register_operand" "=y")
545 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
546 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
548 "pfcmpgt\t{%2, %0|%0, %2}"
549 [(set_attr "type" "mmxcmp")
550 (set_attr "prefix_extra" "1")
551 (set_attr "mode" "V2SF")])
553 (define_insn "mmx_gev2sf3"
554 [(set (match_operand:V2SI 0 "register_operand" "=y")
555 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
556 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
558 "pfcmpge\t{%2, %0|%0, %2}"
559 [(set_attr "type" "mmxcmp")
560 (set_attr "prefix_extra" "1")
561 (set_attr "mode" "V2SF")])
563 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
565 ;; Parallel single-precision floating point conversion operations
567 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
569 (define_insn "mmx_pf2id"
570 [(set (match_operand:V2SI 0 "register_operand" "=y")
571 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
573 "pf2id\t{%1, %0|%0, %1}"
574 [(set_attr "type" "mmxcvt")
575 (set_attr "prefix_extra" "1")
576 (set_attr "mode" "V2SF")])
578 (define_insn "mmx_pf2iw"
579 [(set (match_operand:V2SI 0 "register_operand" "=y")
583 (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
585 "pf2iw\t{%1, %0|%0, %1}"
586 [(set_attr "type" "mmxcvt")
587 (set_attr "prefix_extra" "1")
588 (set_attr "mode" "V2SF")])
590 (define_insn "mmx_pi2fw"
591 [(set (match_operand:V2SF 0 "register_operand" "=y")
595 (match_operand:V2SI 1 "nonimmediate_operand" "ym")))))]
597 "pi2fw\t{%1, %0|%0, %1}"
598 [(set_attr "type" "mmxcvt")
599 (set_attr "prefix_extra" "1")
600 (set_attr "mode" "V2SF")])
602 (define_insn "mmx_floatv2si2"
603 [(set (match_operand:V2SF 0 "register_operand" "=y")
604 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
606 "pi2fd\t{%1, %0|%0, %1}"
607 [(set_attr "type" "mmxcvt")
608 (set_attr "prefix_extra" "1")
609 (set_attr "mode" "V2SF")])
611 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
613 ;; Parallel single-precision floating point element swizzling
615 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
617 (define_insn "mmx_pswapdv2sf2"
618 [(set (match_operand:V2SF 0 "register_operand" "=y")
619 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
620 (parallel [(const_int 1) (const_int 0)])))]
622 "pswapd\t{%1, %0|%0, %1}"
623 [(set_attr "type" "mmxcvt")
624 (set_attr "prefix_extra" "1")
625 (set_attr "mode" "V2SF")])
627 (define_insn "*vec_dupv2sf"
628 [(set (match_operand:V2SF 0 "register_operand" "=y")
630 (match_operand:SF 1 "register_operand" "0")))]
633 [(set_attr "type" "mmxcvt")
634 (set_attr "mode" "DI")])
636 (define_insn "*mmx_concatv2sf"
637 [(set (match_operand:V2SF 0 "register_operand" "=y,y")
639 (match_operand:SF 1 "nonimmediate_operand" " 0,rm")
640 (match_operand:SF 2 "vector_move_operand" "ym,C")))]
641 "TARGET_MMX && !TARGET_SSE"
643 punpckldq\t{%2, %0|%0, %2}
644 movd\t{%1, %0|%0, %1}"
645 [(set_attr "type" "mmxcvt,mmxmov")
646 (set_attr "mode" "DI")])
648 (define_expand "vec_setv2sf"
649 [(match_operand:V2SF 0 "register_operand" "")
650 (match_operand:SF 1 "register_operand" "")
651 (match_operand 2 "const_int_operand" "")]
654 ix86_expand_vector_set (false, operands[0], operands[1],
655 INTVAL (operands[2]));
659 ;; Avoid combining registers from different units in a single alternative,
660 ;; see comment above inline_secondary_memory_needed function in i386.c
661 (define_insn_and_split "*vec_extractv2sf_0"
662 [(set (match_operand:SF 0 "nonimmediate_operand" "=x, m,y ,m,f,r")
664 (match_operand:V2SF 1 "nonimmediate_operand" " xm,x,ym,y,m,m")
665 (parallel [(const_int 0)])))]
666 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
668 "&& reload_completed"
671 rtx op1 = operands[1];
673 op1 = gen_rtx_REG (SFmode, REGNO (op1));
675 op1 = gen_lowpart (SFmode, op1);
676 emit_move_insn (operands[0], op1);
680 ;; Avoid combining registers from different units in a single alternative,
681 ;; see comment above inline_secondary_memory_needed function in i386.c
682 (define_insn "*vec_extractv2sf_1"
683 [(set (match_operand:SF 0 "nonimmediate_operand" "=y,x,y,x,f,r")
685 (match_operand:V2SF 1 "nonimmediate_operand" " 0,0,o,o,o,o")
686 (parallel [(const_int 1)])))]
687 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
695 [(set_attr "type" "mmxcvt,sselog1,mmxmov,ssemov,fmov,imov")
696 (set_attr "mode" "DI,V4SF,SF,SF,SF,SF")])
699 [(set (match_operand:SF 0 "register_operand" "")
701 (match_operand:V2SF 1 "memory_operand" "")
702 (parallel [(const_int 1)])))]
703 "TARGET_MMX && reload_completed"
706 operands[1] = adjust_address (operands[1], SFmode, 4);
707 emit_move_insn (operands[0], operands[1]);
711 (define_expand "vec_extractv2sf"
712 [(match_operand:SF 0 "register_operand" "")
713 (match_operand:V2SF 1 "register_operand" "")
714 (match_operand 2 "const_int_operand" "")]
717 ix86_expand_vector_extract (false, operands[0], operands[1],
718 INTVAL (operands[2]));
722 (define_expand "vec_initv2sf"
723 [(match_operand:V2SF 0 "register_operand" "")
724 (match_operand 1 "" "")]
727 ix86_expand_vector_init (false, operands[0], operands[1]);
731 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
733 ;; Parallel integral arithmetic
735 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
737 (define_expand "mmx_<plusminus_insn><mode>3"
738 [(set (match_operand:MMXMODEI8 0 "register_operand" "")
740 (match_operand:MMXMODEI8 1 "nonimmediate_operand" "")
741 (match_operand:MMXMODEI8 2 "nonimmediate_operand" "")))]
742 "TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode)"
743 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
745 (define_insn "*mmx_<plusminus_insn><mode>3"
746 [(set (match_operand:MMXMODEI8 0 "register_operand" "=y")
748 (match_operand:MMXMODEI8 1 "nonimmediate_operand" "<comm>0")
749 (match_operand:MMXMODEI8 2 "nonimmediate_operand" "ym")))]
750 "(TARGET_MMX || (TARGET_SSE2 && <MODE>mode == V1DImode))
751 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
752 "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
753 [(set_attr "type" "mmxadd")
754 (set_attr "mode" "DI")])
756 (define_expand "mmx_<plusminus_insn><mode>3"
757 [(set (match_operand:MMXMODE12 0 "register_operand" "")
758 (sat_plusminus:MMXMODE12
759 (match_operand:MMXMODE12 1 "nonimmediate_operand" "")
760 (match_operand:MMXMODE12 2 "nonimmediate_operand" "")))]
762 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
764 (define_insn "*mmx_<plusminus_insn><mode>3"
765 [(set (match_operand:MMXMODE12 0 "register_operand" "=y")
766 (sat_plusminus:MMXMODE12
767 (match_operand:MMXMODE12 1 "nonimmediate_operand" "<comm>0")
768 (match_operand:MMXMODE12 2 "nonimmediate_operand" "ym")))]
769 "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
770 "p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}"
771 [(set_attr "type" "mmxadd")
772 (set_attr "mode" "DI")])
774 (define_expand "mmx_mulv4hi3"
775 [(set (match_operand:V4HI 0 "register_operand" "")
776 (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "")
777 (match_operand:V4HI 2 "nonimmediate_operand" "")))]
779 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
781 (define_insn "*mmx_mulv4hi3"
782 [(set (match_operand:V4HI 0 "register_operand" "=y")
783 (mult:V4HI (match_operand:V4HI 1 "nonimmediate_operand" "%0")
784 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
785 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
786 "pmullw\t{%2, %0|%0, %2}"
787 [(set_attr "type" "mmxmul")
788 (set_attr "mode" "DI")])
790 (define_expand "mmx_smulv4hi3_highpart"
791 [(set (match_operand:V4HI 0 "register_operand" "")
796 (match_operand:V4HI 1 "nonimmediate_operand" ""))
798 (match_operand:V4HI 2 "nonimmediate_operand" "")))
801 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
803 (define_insn "*mmx_smulv4hi3_highpart"
804 [(set (match_operand:V4HI 0 "register_operand" "=y")
809 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
811 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
813 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
814 "pmulhw\t{%2, %0|%0, %2}"
815 [(set_attr "type" "mmxmul")
816 (set_attr "mode" "DI")])
818 (define_expand "mmx_umulv4hi3_highpart"
819 [(set (match_operand:V4HI 0 "register_operand" "")
824 (match_operand:V4HI 1 "nonimmediate_operand" ""))
826 (match_operand:V4HI 2 "nonimmediate_operand" "")))
828 "TARGET_SSE || TARGET_3DNOW_A"
829 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
831 (define_insn "*mmx_umulv4hi3_highpart"
832 [(set (match_operand:V4HI 0 "register_operand" "=y")
837 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
839 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
841 "(TARGET_SSE || TARGET_3DNOW_A)
842 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
843 "pmulhuw\t{%2, %0|%0, %2}"
844 [(set_attr "type" "mmxmul")
845 (set_attr "mode" "DI")])
847 (define_expand "mmx_pmaddwd"
848 [(set (match_operand:V2SI 0 "register_operand" "")
853 (match_operand:V4HI 1 "nonimmediate_operand" "")
854 (parallel [(const_int 0) (const_int 2)])))
857 (match_operand:V4HI 2 "nonimmediate_operand" "")
858 (parallel [(const_int 0) (const_int 2)]))))
861 (vec_select:V2HI (match_dup 1)
862 (parallel [(const_int 1) (const_int 3)])))
864 (vec_select:V2HI (match_dup 2)
865 (parallel [(const_int 1) (const_int 3)]))))))]
867 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
869 (define_insn "*mmx_pmaddwd"
870 [(set (match_operand:V2SI 0 "register_operand" "=y")
875 (match_operand:V4HI 1 "nonimmediate_operand" "%0")
876 (parallel [(const_int 0) (const_int 2)])))
879 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
880 (parallel [(const_int 0) (const_int 2)]))))
883 (vec_select:V2HI (match_dup 1)
884 (parallel [(const_int 1) (const_int 3)])))
886 (vec_select:V2HI (match_dup 2)
887 (parallel [(const_int 1) (const_int 3)]))))))]
888 "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)"
889 "pmaddwd\t{%2, %0|%0, %2}"
890 [(set_attr "type" "mmxmul")
891 (set_attr "mode" "DI")])
893 (define_expand "mmx_pmulhrwv4hi3"
894 [(set (match_operand:V4HI 0 "register_operand" "")
900 (match_operand:V4HI 1 "nonimmediate_operand" ""))
902 (match_operand:V4HI 2 "nonimmediate_operand" "")))
903 (const_vector:V4SI [(const_int 32768) (const_int 32768)
904 (const_int 32768) (const_int 32768)]))
907 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
909 (define_insn "*mmx_pmulhrwv4hi3"
910 [(set (match_operand:V4HI 0 "register_operand" "=y")
916 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
918 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
919 (const_vector:V4SI [(const_int 32768) (const_int 32768)
920 (const_int 32768) (const_int 32768)]))
922 "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
923 "pmulhrw\t{%2, %0|%0, %2}"
924 [(set_attr "type" "mmxmul")
925 (set_attr "prefix_extra" "1")
926 (set_attr "mode" "DI")])
928 (define_expand "sse2_umulv1siv1di3"
929 [(set (match_operand:V1DI 0 "register_operand" "")
933 (match_operand:V2SI 1 "nonimmediate_operand" "")
934 (parallel [(const_int 0)])))
937 (match_operand:V2SI 2 "nonimmediate_operand" "")
938 (parallel [(const_int 0)])))))]
940 "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
942 (define_insn "*sse2_umulv1siv1di3"
943 [(set (match_operand:V1DI 0 "register_operand" "=y")
947 (match_operand:V2SI 1 "nonimmediate_operand" "%0")
948 (parallel [(const_int 0)])))
951 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
952 (parallel [(const_int 0)])))))]
953 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)"
954 "pmuludq\t{%2, %0|%0, %2}"
955 [(set_attr "type" "mmxmul")
956 (set_attr "mode" "DI")])
958 (define_expand "mmx_<code>v4hi3"
959 [(set (match_operand:V4HI 0 "register_operand" "")
961 (match_operand:V4HI 1 "nonimmediate_operand" "")
962 (match_operand:V4HI 2 "nonimmediate_operand" "")))]
963 "TARGET_SSE || TARGET_3DNOW_A"
964 "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
966 (define_insn "*mmx_<code>v4hi3"
967 [(set (match_operand:V4HI 0 "register_operand" "=y")
969 (match_operand:V4HI 1 "nonimmediate_operand" "%0")
970 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
971 "(TARGET_SSE || TARGET_3DNOW_A)
972 && ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
973 "p<maxminiprefix>w\t{%2, %0|%0, %2}"
974 [(set_attr "type" "mmxadd")
975 (set_attr "mode" "DI")])
977 (define_expand "mmx_<code>v8qi3"
978 [(set (match_operand:V8QI 0 "register_operand" "")
980 (match_operand:V8QI 1 "nonimmediate_operand" "")
981 (match_operand:V8QI 2 "nonimmediate_operand" "")))]
982 "TARGET_SSE || TARGET_3DNOW_A"
983 "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
985 (define_insn "*mmx_<code>v8qi3"
986 [(set (match_operand:V8QI 0 "register_operand" "=y")
988 (match_operand:V8QI 1 "nonimmediate_operand" "%0")
989 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
990 "(TARGET_SSE || TARGET_3DNOW_A)
991 && ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
992 "p<maxminiprefix>b\t{%2, %0|%0, %2}"
993 [(set_attr "type" "mmxadd")
994 (set_attr "mode" "DI")])
996 (define_insn "mmx_ashr<mode>3"
997 [(set (match_operand:MMXMODE24 0 "register_operand" "=y")
999 (match_operand:MMXMODE24 1 "register_operand" "0")
1000 (match_operand:SI 2 "nonmemory_operand" "yN")))]
1002 "psra<mmxvecsize>\t{%2, %0|%0, %2}"
1003 [(set_attr "type" "mmxshft")
1004 (set (attr "length_immediate")
1005 (if_then_else (match_operand 2 "const_int_operand" "")
1007 (const_string "0")))
1008 (set_attr "mode" "DI")])
1010 (define_insn "mmx_lshr<mode>3"
1011 [(set (match_operand:MMXMODE248 0 "register_operand" "=y")
1012 (lshiftrt:MMXMODE248
1013 (match_operand:MMXMODE248 1 "register_operand" "0")
1014 (match_operand:SI 2 "nonmemory_operand" "yN")))]
1016 "psrl<mmxvecsize>\t{%2, %0|%0, %2}"
1017 [(set_attr "type" "mmxshft")
1018 (set (attr "length_immediate")
1019 (if_then_else (match_operand 2 "const_int_operand" "")
1021 (const_string "0")))
1022 (set_attr "mode" "DI")])
1024 (define_insn "mmx_ashl<mode>3"
1025 [(set (match_operand:MMXMODE248 0 "register_operand" "=y")
1027 (match_operand:MMXMODE248 1 "register_operand" "0")
1028 (match_operand:SI 2 "nonmemory_operand" "yN")))]
1030 "psll<mmxvecsize>\t{%2, %0|%0, %2}"
1031 [(set_attr "type" "mmxshft")
1032 (set (attr "length_immediate")
1033 (if_then_else (match_operand 2 "const_int_operand" "")
1035 (const_string "0")))
1036 (set_attr "mode" "DI")])
1038 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1040 ;; Parallel integral comparisons
1042 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1044 (define_expand "mmx_eq<mode>3"
1045 [(set (match_operand:MMXMODEI 0 "register_operand" "")
1047 (match_operand:MMXMODEI 1 "nonimmediate_operand" "")
1048 (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))]
1050 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
1052 (define_insn "*mmx_eq<mode>3"
1053 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
1055 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
1056 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
1057 "TARGET_MMX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
1058 "pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}"
1059 [(set_attr "type" "mmxcmp")
1060 (set_attr "mode" "DI")])
1062 (define_insn "mmx_gt<mode>3"
1063 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
1065 (match_operand:MMXMODEI 1 "register_operand" "0")
1066 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
1068 "pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}"
1069 [(set_attr "type" "mmxcmp")
1070 (set_attr "mode" "DI")])
1072 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1074 ;; Parallel integral logical operations
1076 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1078 (define_insn "mmx_andnot<mode>3"
1079 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
1081 (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0"))
1082 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
1084 "pandn\t{%2, %0|%0, %2}"
1085 [(set_attr "type" "mmxadd")
1086 (set_attr "mode" "DI")])
1088 (define_expand "mmx_<code><mode>3"
1089 [(set (match_operand:MMXMODEI 0 "register_operand" "")
1091 (match_operand:MMXMODEI 1 "nonimmediate_operand" "")
1092 (match_operand:MMXMODEI 2 "nonimmediate_operand" "")))]
1094 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
1096 (define_insn "*mmx_<code><mode>3"
1097 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
1099 (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0")
1100 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))]
1101 "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1102 "p<logicprefix>\t{%2, %0|%0, %2}"
1103 [(set_attr "type" "mmxadd")
1104 (set_attr "mode" "DI")])
1106 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1108 ;; Parallel integral element swizzling
1110 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1112 (define_insn "mmx_packsswb"
1113 [(set (match_operand:V8QI 0 "register_operand" "=y")
1116 (match_operand:V4HI 1 "register_operand" "0"))
1118 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))]
1120 "packsswb\t{%2, %0|%0, %2}"
1121 [(set_attr "type" "mmxshft")
1122 (set_attr "mode" "DI")])
1124 (define_insn "mmx_packssdw"
1125 [(set (match_operand:V4HI 0 "register_operand" "=y")
1128 (match_operand:V2SI 1 "register_operand" "0"))
1130 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))))]
1132 "packssdw\t{%2, %0|%0, %2}"
1133 [(set_attr "type" "mmxshft")
1134 (set_attr "mode" "DI")])
1136 (define_insn "mmx_packuswb"
1137 [(set (match_operand:V8QI 0 "register_operand" "=y")
1140 (match_operand:V4HI 1 "register_operand" "0"))
1142 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))))]
1144 "packuswb\t{%2, %0|%0, %2}"
1145 [(set_attr "type" "mmxshft")
1146 (set_attr "mode" "DI")])
1148 (define_insn "mmx_punpckhbw"
1149 [(set (match_operand:V8QI 0 "register_operand" "=y")
1152 (match_operand:V8QI 1 "register_operand" "0")
1153 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
1154 (parallel [(const_int 4) (const_int 12)
1155 (const_int 5) (const_int 13)
1156 (const_int 6) (const_int 14)
1157 (const_int 7) (const_int 15)])))]
1159 "punpckhbw\t{%2, %0|%0, %2}"
1160 [(set_attr "type" "mmxcvt")
1161 (set_attr "mode" "DI")])
1163 (define_insn "mmx_punpcklbw"
1164 [(set (match_operand:V8QI 0 "register_operand" "=y")
1167 (match_operand:V8QI 1 "register_operand" "0")
1168 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
1169 (parallel [(const_int 0) (const_int 8)
1170 (const_int 1) (const_int 9)
1171 (const_int 2) (const_int 10)
1172 (const_int 3) (const_int 11)])))]
1174 "punpcklbw\t{%2, %0|%0, %2}"
1175 [(set_attr "type" "mmxcvt")
1176 (set_attr "mode" "DI")])
1178 (define_insn "mmx_punpckhwd"
1179 [(set (match_operand:V4HI 0 "register_operand" "=y")
1182 (match_operand:V4HI 1 "register_operand" "0")
1183 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
1184 (parallel [(const_int 2) (const_int 6)
1185 (const_int 3) (const_int 7)])))]
1187 "punpckhwd\t{%2, %0|%0, %2}"
1188 [(set_attr "type" "mmxcvt")
1189 (set_attr "mode" "DI")])
1191 (define_insn "mmx_punpcklwd"
1192 [(set (match_operand:V4HI 0 "register_operand" "=y")
1195 (match_operand:V4HI 1 "register_operand" "0")
1196 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
1197 (parallel [(const_int 0) (const_int 4)
1198 (const_int 1) (const_int 5)])))]
1200 "punpcklwd\t{%2, %0|%0, %2}"
1201 [(set_attr "type" "mmxcvt")
1202 (set_attr "mode" "DI")])
1204 (define_insn "mmx_punpckhdq"
1205 [(set (match_operand:V2SI 0 "register_operand" "=y")
1208 (match_operand:V2SI 1 "register_operand" "0")
1209 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))
1210 (parallel [(const_int 1)
1213 "punpckhdq\t{%2, %0|%0, %2}"
1214 [(set_attr "type" "mmxcvt")
1215 (set_attr "mode" "DI")])
1217 (define_insn "mmx_punpckldq"
1218 [(set (match_operand:V2SI 0 "register_operand" "=y")
1221 (match_operand:V2SI 1 "register_operand" "0")
1222 (match_operand:V2SI 2 "nonimmediate_operand" "ym"))
1223 (parallel [(const_int 0)
1226 "punpckldq\t{%2, %0|%0, %2}"
1227 [(set_attr "type" "mmxcvt")
1228 (set_attr "mode" "DI")])
1230 (define_expand "mmx_pinsrw"
1231 [(set (match_operand:V4HI 0 "register_operand" "")
1234 (match_operand:SI 2 "nonimmediate_operand" ""))
1235 (match_operand:V4HI 1 "register_operand" "")
1236 (match_operand:SI 3 "const_0_to_3_operand" "")))]
1237 "TARGET_SSE || TARGET_3DNOW_A"
1239 operands[2] = gen_lowpart (HImode, operands[2]);
1240 operands[3] = GEN_INT (1 << INTVAL (operands[3]));
1243 (define_insn "*mmx_pinsrw"
1244 [(set (match_operand:V4HI 0 "register_operand" "=y")
1247 (match_operand:HI 2 "nonimmediate_operand" "rm"))
1248 (match_operand:V4HI 1 "register_operand" "0")
1249 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
1250 "TARGET_SSE || TARGET_3DNOW_A"
1252 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
1253 if (MEM_P (operands[2]))
1254 return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
1256 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
1258 [(set_attr "type" "mmxcvt")
1259 (set_attr "length_immediate" "1")
1260 (set_attr "mode" "DI")])
1262 (define_insn "mmx_pextrw"
1263 [(set (match_operand:SI 0 "register_operand" "=r")
1266 (match_operand:V4HI 1 "register_operand" "y")
1267 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
1268 "TARGET_SSE || TARGET_3DNOW_A"
1269 "pextrw\t{%2, %1, %0|%0, %1, %2}"
1270 [(set_attr "type" "mmxcvt")
1271 (set_attr "length_immediate" "1")
1272 (set_attr "mode" "DI")])
1274 (define_expand "mmx_pshufw"
1275 [(match_operand:V4HI 0 "register_operand" "")
1276 (match_operand:V4HI 1 "nonimmediate_operand" "")
1277 (match_operand:SI 2 "const_int_operand" "")]
1278 "TARGET_SSE || TARGET_3DNOW_A"
1280 int mask = INTVAL (operands[2]);
1281 emit_insn (gen_mmx_pshufw_1 (operands[0], operands[1],
1282 GEN_INT ((mask >> 0) & 3),
1283 GEN_INT ((mask >> 2) & 3),
1284 GEN_INT ((mask >> 4) & 3),
1285 GEN_INT ((mask >> 6) & 3)));
1289 (define_insn "mmx_pshufw_1"
1290 [(set (match_operand:V4HI 0 "register_operand" "=y")
1292 (match_operand:V4HI 1 "nonimmediate_operand" "ym")
1293 (parallel [(match_operand 2 "const_0_to_3_operand" "")
1294 (match_operand 3 "const_0_to_3_operand" "")
1295 (match_operand 4 "const_0_to_3_operand" "")
1296 (match_operand 5 "const_0_to_3_operand" "")])))]
1297 "TARGET_SSE || TARGET_3DNOW_A"
1300 mask |= INTVAL (operands[2]) << 0;
1301 mask |= INTVAL (operands[3]) << 2;
1302 mask |= INTVAL (operands[4]) << 4;
1303 mask |= INTVAL (operands[5]) << 6;
1304 operands[2] = GEN_INT (mask);
1306 return "pshufw\t{%2, %1, %0|%0, %1, %2}";
1308 [(set_attr "type" "mmxcvt")
1309 (set_attr "length_immediate" "1")
1310 (set_attr "mode" "DI")])
1312 (define_insn "mmx_pswapdv2si2"
1313 [(set (match_operand:V2SI 0 "register_operand" "=y")
1315 (match_operand:V2SI 1 "nonimmediate_operand" "ym")
1316 (parallel [(const_int 1) (const_int 0)])))]
1318 "pswapd\t{%1, %0|%0, %1}"
1319 [(set_attr "type" "mmxcvt")
1320 (set_attr "prefix_extra" "1")
1321 (set_attr "mode" "DI")])
1323 (define_insn "*vec_dupv4hi"
1324 [(set (match_operand:V4HI 0 "register_operand" "=y")
1327 (match_operand:SI 1 "register_operand" "0"))))]
1328 "TARGET_SSE || TARGET_3DNOW_A"
1329 "pshufw\t{$0, %0, %0|%0, %0, 0}"
1330 [(set_attr "type" "mmxcvt")
1331 (set_attr "length_immediate" "1")
1332 (set_attr "mode" "DI")])
1334 (define_insn "*vec_dupv2si"
1335 [(set (match_operand:V2SI 0 "register_operand" "=y")
1337 (match_operand:SI 1 "register_operand" "0")))]
1340 [(set_attr "type" "mmxcvt")
1341 (set_attr "mode" "DI")])
1343 (define_insn "*mmx_concatv2si"
1344 [(set (match_operand:V2SI 0 "register_operand" "=y,y")
1346 (match_operand:SI 1 "nonimmediate_operand" " 0,rm")
1347 (match_operand:SI 2 "vector_move_operand" "ym,C")))]
1348 "TARGET_MMX && !TARGET_SSE"
1350 punpckldq\t{%2, %0|%0, %2}
1351 movd\t{%1, %0|%0, %1}"
1352 [(set_attr "type" "mmxcvt,mmxmov")
1353 (set_attr "mode" "DI")])
1355 (define_expand "vec_setv2si"
1356 [(match_operand:V2SI 0 "register_operand" "")
1357 (match_operand:SI 1 "register_operand" "")
1358 (match_operand 2 "const_int_operand" "")]
1361 ix86_expand_vector_set (false, operands[0], operands[1],
1362 INTVAL (operands[2]));
1366 ;; Avoid combining registers from different units in a single alternative,
1367 ;; see comment above inline_secondary_memory_needed function in i386.c
1368 (define_insn_and_split "*vec_extractv2si_0"
1369 [(set (match_operand:SI 0 "nonimmediate_operand" "=x,m,y, m,r")
1371 (match_operand:V2SI 1 "nonimmediate_operand" "xm,x,ym,y,m")
1372 (parallel [(const_int 0)])))]
1373 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1375 "&& reload_completed"
1378 rtx op1 = operands[1];
1380 op1 = gen_rtx_REG (SImode, REGNO (op1));
1382 op1 = gen_lowpart (SImode, op1);
1383 emit_move_insn (operands[0], op1);
1387 ;; Avoid combining registers from different units in a single alternative,
1388 ;; see comment above inline_secondary_memory_needed function in i386.c
1389 (define_insn "*vec_extractv2si_1"
1390 [(set (match_operand:SI 0 "nonimmediate_operand" "=y,Y2,Y2,x,y,x,r")
1392 (match_operand:V2SI 1 "nonimmediate_operand" " 0,0 ,Y2,0,o,o,o")
1393 (parallel [(const_int 1)])))]
1394 "TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1398 pshufd\t{$85, %1, %0|%0, %1, 85}
1403 [(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,mmxmov,ssemov,imov")
1404 (set_attr "length_immediate" "*,*,1,*,*,*,*")
1405 (set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")])
1408 [(set (match_operand:SI 0 "register_operand" "")
1410 (match_operand:V2SI 1 "memory_operand" "")
1411 (parallel [(const_int 1)])))]
1412 "TARGET_MMX && reload_completed"
1415 operands[1] = adjust_address (operands[1], SImode, 4);
1416 emit_move_insn (operands[0], operands[1]);
1420 (define_expand "vec_extractv2si"
1421 [(match_operand:SI 0 "register_operand" "")
1422 (match_operand:V2SI 1 "register_operand" "")
1423 (match_operand 2 "const_int_operand" "")]
1426 ix86_expand_vector_extract (false, operands[0], operands[1],
1427 INTVAL (operands[2]));
1431 (define_expand "vec_initv2si"
1432 [(match_operand:V2SI 0 "register_operand" "")
1433 (match_operand 1 "" "")]
1436 ix86_expand_vector_init (false, operands[0], operands[1]);
1440 (define_expand "vec_setv4hi"
1441 [(match_operand:V4HI 0 "register_operand" "")
1442 (match_operand:HI 1 "register_operand" "")
1443 (match_operand 2 "const_int_operand" "")]
1446 ix86_expand_vector_set (false, operands[0], operands[1],
1447 INTVAL (operands[2]));
1451 (define_expand "vec_extractv4hi"
1452 [(match_operand:HI 0 "register_operand" "")
1453 (match_operand:V4HI 1 "register_operand" "")
1454 (match_operand 2 "const_int_operand" "")]
1457 ix86_expand_vector_extract (false, operands[0], operands[1],
1458 INTVAL (operands[2]));
1462 (define_expand "vec_initv4hi"
1463 [(match_operand:V4HI 0 "register_operand" "")
1464 (match_operand 1 "" "")]
1467 ix86_expand_vector_init (false, operands[0], operands[1]);
1471 (define_expand "vec_setv8qi"
1472 [(match_operand:V8QI 0 "register_operand" "")
1473 (match_operand:QI 1 "register_operand" "")
1474 (match_operand 2 "const_int_operand" "")]
1477 ix86_expand_vector_set (false, operands[0], operands[1],
1478 INTVAL (operands[2]));
1482 (define_expand "vec_extractv8qi"
1483 [(match_operand:QI 0 "register_operand" "")
1484 (match_operand:V8QI 1 "register_operand" "")
1485 (match_operand 2 "const_int_operand" "")]
1488 ix86_expand_vector_extract (false, operands[0], operands[1],
1489 INTVAL (operands[2]));
1493 (define_expand "vec_initv8qi"
1494 [(match_operand:V8QI 0 "register_operand" "")
1495 (match_operand 1 "" "")]
1498 ix86_expand_vector_init (false, operands[0], operands[1]);
1502 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1506 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1508 (define_expand "mmx_uavgv8qi3"
1509 [(set (match_operand:V8QI 0 "register_operand" "")
1515 (match_operand:V8QI 1 "nonimmediate_operand" ""))
1517 (match_operand:V8QI 2 "nonimmediate_operand" "")))
1518 (const_vector:V8HI [(const_int 1) (const_int 1)
1519 (const_int 1) (const_int 1)
1520 (const_int 1) (const_int 1)
1521 (const_int 1) (const_int 1)]))
1523 "TARGET_SSE || TARGET_3DNOW"
1524 "ix86_fixup_binary_operands_no_copy (PLUS, V8QImode, operands);")
1526 (define_insn "*mmx_uavgv8qi3"
1527 [(set (match_operand:V8QI 0 "register_operand" "=y")
1533 (match_operand:V8QI 1 "nonimmediate_operand" "%0"))
1535 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))
1536 (const_vector:V8HI [(const_int 1) (const_int 1)
1537 (const_int 1) (const_int 1)
1538 (const_int 1) (const_int 1)
1539 (const_int 1) (const_int 1)]))
1541 "(TARGET_SSE || TARGET_3DNOW)
1542 && ix86_binary_operator_ok (PLUS, V8QImode, operands)"
1544 /* These two instructions have the same operation, but their encoding
1545 is different. Prefer the one that is de facto standard. */
1546 if (TARGET_SSE || TARGET_3DNOW_A)
1547 return "pavgb\t{%2, %0|%0, %2}";
1549 return "pavgusb\t{%2, %0|%0, %2}";
1551 [(set_attr "type" "mmxshft")
1552 (set (attr "prefix_extra")
1554 (eq (symbol_ref "(TARGET_SSE || TARGET_3DNOW_A)") (const_int 0))
1556 (const_string "*")))
1557 (set_attr "mode" "DI")])
1559 (define_expand "mmx_uavgv4hi3"
1560 [(set (match_operand:V4HI 0 "register_operand" "")
1566 (match_operand:V4HI 1 "nonimmediate_operand" ""))
1568 (match_operand:V4HI 2 "nonimmediate_operand" "")))
1569 (const_vector:V4SI [(const_int 1) (const_int 1)
1570 (const_int 1) (const_int 1)]))
1572 "TARGET_SSE || TARGET_3DNOW_A"
1573 "ix86_fixup_binary_operands_no_copy (PLUS, V4HImode, operands);")
1575 (define_insn "*mmx_uavgv4hi3"
1576 [(set (match_operand:V4HI 0 "register_operand" "=y")
1582 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
1584 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
1585 (const_vector:V4SI [(const_int 1) (const_int 1)
1586 (const_int 1) (const_int 1)]))
1588 "(TARGET_SSE || TARGET_3DNOW_A)
1589 && ix86_binary_operator_ok (PLUS, V4HImode, operands)"
1590 "pavgw\t{%2, %0|%0, %2}"
1591 [(set_attr "type" "mmxshft")
1592 (set_attr "mode" "DI")])
1594 (define_insn "mmx_psadbw"
1595 [(set (match_operand:V1DI 0 "register_operand" "=y")
1596 (unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0")
1597 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
1599 "TARGET_SSE || TARGET_3DNOW_A"
1600 "psadbw\t{%2, %0|%0, %2}"
1601 [(set_attr "type" "mmxshft")
1602 (set_attr "mode" "DI")])
1604 (define_insn "mmx_pmovmskb"
1605 [(set (match_operand:SI 0 "register_operand" "=r")
1606 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
1608 "TARGET_SSE || TARGET_3DNOW_A"
1609 "pmovmskb\t{%1, %0|%0, %1}"
1610 [(set_attr "type" "mmxcvt")
1611 (set_attr "mode" "DI")])
1613 (define_expand "mmx_maskmovq"
1614 [(set (match_operand:V8QI 0 "memory_operand" "")
1615 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "")
1616 (match_operand:V8QI 2 "register_operand" "")
1619 "TARGET_SSE || TARGET_3DNOW_A"
1622 (define_insn "*mmx_maskmovq"
1623 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
1624 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1625 (match_operand:V8QI 2 "register_operand" "y")
1626 (mem:V8QI (match_dup 0))]
1628 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
1629 ;; @@@ check ordering of operands in intel/nonintel syntax
1630 "maskmovq\t{%2, %1|%1, %2}"
1631 [(set_attr "type" "mmxcvt")
1632 (set_attr "mode" "DI")])
1634 (define_insn "*mmx_maskmovq_rex"
1635 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
1636 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
1637 (match_operand:V8QI 2 "register_operand" "y")
1638 (mem:V8QI (match_dup 0))]
1640 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
1641 ;; @@@ check ordering of operands in intel/nonintel syntax
1642 "maskmovq\t{%2, %1|%1, %2}"
1643 [(set_attr "type" "mmxcvt")
1644 (set_attr "mode" "DI")])
1646 (define_expand "mmx_emms"
1647 [(match_par_dup 0 [(const_int 0)])]
1652 operands[0] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (17));
1654 XVECEXP (operands[0], 0, 0)
1655 = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx),
1658 for (regno = 0; regno < 8; regno++)
1660 XVECEXP (operands[0], 0, regno + 1)
1661 = gen_rtx_CLOBBER (VOIDmode,
1662 gen_rtx_REG (XFmode, FIRST_STACK_REG + regno));
1664 XVECEXP (operands[0], 0, regno + 9)
1665 = gen_rtx_CLOBBER (VOIDmode,
1666 gen_rtx_REG (DImode, FIRST_MMX_REG + regno));
1670 (define_insn "*mmx_emms"
1671 [(match_parallel 0 "emms_operation"
1672 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)])]
1675 [(set_attr "type" "mmx")
1676 (set_attr "modrm" "0")
1677 (set_attr "memory" "none")])
1679 (define_expand "mmx_femms"
1680 [(match_par_dup 0 [(const_int 0)])]
1685 operands[0] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (17));
1687 XVECEXP (operands[0], 0, 0)
1688 = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx),
1691 for (regno = 0; regno < 8; regno++)
1693 XVECEXP (operands[0], 0, regno + 1)
1694 = gen_rtx_CLOBBER (VOIDmode,
1695 gen_rtx_REG (XFmode, FIRST_STACK_REG + regno));
1697 XVECEXP (operands[0], 0, regno + 9)
1698 = gen_rtx_CLOBBER (VOIDmode,
1699 gen_rtx_REG (DImode, FIRST_MMX_REG + regno));
1703 (define_insn "*mmx_femms"
1704 [(match_parallel 0 "emms_operation"
1705 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)])]
1708 [(set_attr "type" "mmx")
1709 (set_attr "modrm" "0")
1710 (set_attr "memory" "none")])