1 ; Options for the IA-32 and AMD64 ports of the compiler.
3 ; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
5 ; This file is part of GCC.
7 ; GCC is free software; you can redistribute it and/or modify it under
8 ; the terms of the GNU General Public License as published by the Free
9 ; Software Foundation; either version 3, or (at your option) any later
12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 ; You should have received a copy of the GNU General Public License
18 ; along with GCC; see the file COPYING3. If not see
19 ; <http://www.gnu.org/licenses/>.
21 ;; Definitions to add to the cl_target_option structure
36 unsigned char schedule
40 unsigned char branch_cost
42 ;; which flags were passed by the user
44 int ix86_isa_flags_explicit
46 ;; which flags were passed by the user
48 int target_flags_explicit
50 ;; whether -mtune was not specified
52 unsigned char tune_defaulted
54 ;; whether -march was specified
56 unsigned char arch_specified
60 Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
61 sizeof(long double) is 16
64 Target Report Mask(80387) Save
68 Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save
69 sizeof(long double) is 12
71 maccumulate-outgoing-args
72 Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save
73 Reserve space for outgoing arguments in the function prologue
76 Target Report Mask(ALIGN_DOUBLE) Save
77 Align some doubles on dword boundary
80 Target RejectNegative Joined Var(ix86_align_funcs_string)
81 Function starts are aligned to this power of 2
84 Target RejectNegative Joined Var(ix86_align_jumps_string)
85 Jump targets are aligned to this power of 2
88 Target RejectNegative Joined Var(ix86_align_loops_string)
89 Loop code aligned to this power of 2
92 Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save
93 Align destination of the string operations
96 Target RejectNegative Joined Var(ix86_arch_string)
97 Generate code for given CPU
100 Target RejectNegative Joined Var(ix86_asm_string)
101 Use given assembler dialect
104 Target RejectNegative Joined Var(ix86_branch_cost_string)
105 Branches are this expensive (1-5, arbitrary units)
107 mlarge-data-threshold=
108 Target RejectNegative Joined Var(ix86_section_threshold_string)
109 Data greater than given threshold will go into .ldata section in x86-64 medium model
112 Target RejectNegative Joined Var(ix86_cmodel_string)
113 Use given x86-64 code model
116 Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save
117 Generate sin, cos, sqrt for FPU
120 Target Report Var(ix86_force_drap)
121 Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack
124 Target Report Mask(FLOAT_RETURNS) Save
125 Return values of functions in FPU registers
128 Target RejectNegative Joined Var(ix86_fpmath_string)
129 Generate floating point mathematics using given instruction set
132 Target RejectNegative Mask(80387) MaskExists Save
136 Target Report Mask(IEEE_FP) Save
137 Use IEEE math for fp comparisons
139 minline-all-stringops
140 Target Report Mask(INLINE_ALL_STRINGOPS) Save
141 Inline all known string operations
143 minline-stringops-dynamically
144 Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save
145 Inline memset/memcpy string operations, but perform inline version only for small blocks
152 Target Report Mask(MS_BITFIELD_LAYOUT) Save
153 Use native (MS) bitfield layout
156 Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save
159 Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save
162 Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save
165 Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save
167 momit-leaf-frame-pointer
168 Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save
169 Omit the frame pointer in leaf functions
172 Target RejectNegative Report Joined Var(ix87_precision_string)
173 Set 80387 floating-point precision (-mpc32, -mpc64, -mpc80)
175 mpreferred-stack-boundary=
176 Target RejectNegative Joined Var(ix86_preferred_stack_boundary_string)
177 Attempt to keep stack aligned to this power of 2
179 mincoming-stack-boundary=
180 Target RejectNegative Joined Var(ix86_incoming_stack_boundary_string)
181 Assume incoming stack aligned to this power of 2
184 Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save
185 Use push instructions to save outgoing arguments
188 Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save
189 Use red-zone in the x86-64 code
192 Target RejectNegative Joined Var(ix86_regparm_string)
193 Number of registers used to pass integer arguments
196 Target Report Mask(RTD) Save
197 Alternate calling convention
200 Target InverseMask(80387) Save
201 Do not use hardware fp
204 Target RejectNegative Mask(SSEREGPARM) Save
205 Use SSE register passing conventions for SF and DF mode
208 Target Report Var(ix86_force_align_arg_pointer) Init(-1)
209 Realign stack in prologue
212 Target Report Mask(STACK_PROBE) Save
216 Target RejectNegative Joined Var(ix86_stringop_string)
217 Chose strategy to generate stringop using
220 Target RejectNegative Joined Var(ix86_tls_dialect_string)
221 Use given thread-local storage dialect
224 Target Report Mask(TLS_DIRECT_SEG_REFS)
225 Use direct references against %gs when accessing tls data
228 Target RejectNegative Joined Var(ix86_tune_string)
229 Schedule code for given CPU
232 Target RejectNegative Joined Var(ix86_abi_string)
233 Generate code that conforms to the given ABI
236 Target RejectNegative Joined Var(ix86_veclibabi_string)
237 Vector library ABI to use
240 Target Report Mask(RECIP) Save
241 Generate reciprocals instead of divss and sqrtss.
244 Target Report Mask(CLD) Save
245 Generate cld instruction in the function prologue.
248 Target RejectNegative Report Mask(NO_FUSED_MADD) Undocumented Save
251 Target Report InverseMask(NO_FUSED_MADD, FUSED_MADD) Save
252 Enable automatic generation of fused floating point multiply-add instructions
253 if the ISA supports such instructions. The -mfused-madd option is on by
259 Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save
260 Generate 32bit i386 code
263 Target RejectNegative Negative(m32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save
264 Generate 64bit x86-64 code
267 Target Report Mask(ISA_MMX) Var(ix86_isa_flags) VarExists Save
268 Support MMX built-in functions
271 Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) VarExists Save
272 Support 3DNow! built-in functions
275 Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) VarExists Save
276 Support Athlon 3Dnow! built-in functions
279 Target Report Mask(ISA_SSE) Var(ix86_isa_flags) VarExists Save
280 Support MMX and SSE built-in functions and code generation
283 Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) VarExists Save
284 Support MMX, SSE and SSE2 built-in functions and code generation
287 Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) VarExists Save
288 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
291 Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) VarExists Save
292 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
295 Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) VarExists Save
296 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
299 Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) VarExists Save
300 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
303 Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) VarExists Save
304 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation
307 Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) VarExists Save
308 Do not support SSE4.1 and SSE4.2 built-in functions and code generation
311 Target Report Mask(ISA_AVX) Var(ix86_isa_flags) VarExists
312 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation
315 Target Report Mask(ISA_FMA) Var(ix86_isa_flags) VarExists
316 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation
319 Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists Save
320 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
323 Target Report Mask(ISA_SSE5) Var(ix86_isa_flags) VarExists Save
324 Support SSE5 built-in functions and code generation
327 Target Report Mask(ISA_ABM) Var(ix86_isa_flags) VarExists Save
328 Support code generation of Advanced Bit Manipulation (ABM) instructions.
331 Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) VarExists Save
332 Support code generation of popcnt instruction.
335 Target Report Mask(ISA_CX16) Var(ix86_isa_flags) VarExists Save
336 Support code generation of cmpxchg16b instruction.
339 Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) VarExists Save
340 Support code generation of sahf instruction in 64bit x86-64 code.
343 Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) VarExists Save
344 Support code generation of movbe instruction.
347 Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) VarExists Save
348 Support code generation of crc32 instruction.
351 Target Report Mask(ISA_AES) Var(ix86_isa_flags) VarExists Save
352 Support AES built-in functions and code generation
355 Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) VarExists Save
356 Support PCLMUL built-in functions and code generation
359 Target Report Var(ix86_sse2avx)
360 Encode SSE instructions with VEX prefix