PR bootstrap/35216

[pf3gnuchains/gcc-fork.git] / gcc / config / i386 / i386.md

;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
;; Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; x86_64 support added by Jan Hubicka
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.  */
;;
;; The original PO technology requires these to be ordered by speed,
;; so that assigner will pick the fastest.
;;
;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
;;
;; The special asm out single letter directives following a '%' are:
;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
;;     operands[1].
;; 'L' Print the opcode suffix for a 32-bit integer opcode.
;; 'W' Print the opcode suffix for a 16-bit integer opcode.
;; 'B' Print the opcode suffix for an 8-bit integer opcode.
;; 'Q' Print the opcode suffix for a 64-bit float opcode.
;; 'S' Print the opcode suffix for a 32-bit float opcode.
;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
;; 'J' Print the appropriate jump operand.
;;
;; 'b' Print the QImode name of the register for the indicated operand.
;;     %b0 would print %al if operands[0] is reg 0.
;; 'w' Likewise, print the HImode name of the register.
;; 'k' Likewise, print the SImode name of the register.
;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
;; 'y' Print "st(0)" instead of "st" as a register.

;; UNSPEC usage:

(define_constants
  [; Relocation specifiers
   (UNSPEC_GOT                  0)
   (UNSPEC_GOTOFF               1)
   (UNSPEC_GOTPCREL             2)
   (UNSPEC_GOTTPOFF             3)
   (UNSPEC_TPOFF                4)
   (UNSPEC_NTPOFF               5)
   (UNSPEC_DTPOFF               6)
   (UNSPEC_GOTNTPOFF            7)
   (UNSPEC_INDNTPOFF            8)
   (UNSPEC_PLTOFF               9)

   ; Prologue support
   (UNSPEC_STACK_ALLOC          11)
   (UNSPEC_SET_GOT              12)
   (UNSPEC_SSE_PROLOGUE_SAVE    13)
   (UNSPEC_REG_SAVE             14)
   (UNSPEC_DEF_CFA              15)
   (UNSPEC_SET_RIP              16)
   (UNSPEC_SET_GOT_OFFSET       17)

   ; TLS support
   (UNSPEC_TP                   18)
   (UNSPEC_TLS_GD               19)
   (UNSPEC_TLS_LD_BASE          20)
   (UNSPEC_TLSDESC              21)

   ; Other random patterns
   (UNSPEC_SCAS                 30)
   (UNSPEC_FNSTSW               31)
   (UNSPEC_SAHF                 32)
   (UNSPEC_FSTCW                33)
   (UNSPEC_ADD_CARRY            34)
   (UNSPEC_FLDCW                35)
   (UNSPEC_REP                  36)
   (UNSPEC_EH_RETURN            37)
   (UNSPEC_LD_MPIC              38)     ; load_macho_picbase
   (UNSPEC_TRUNC_NOOP           39)

   ; For SSE/MMX support:
   (UNSPEC_FIX_NOTRUNC          40)
   (UNSPEC_MASKMOV              41)
   (UNSPEC_MOVMSK               42)
   (UNSPEC_MOVNT                43)
   (UNSPEC_MOVU                 44)
   (UNSPEC_RCP                  45)
   (UNSPEC_RSQRT                46)
   (UNSPEC_SFENCE               47)
   (UNSPEC_PFRCP                49)
   (UNSPEC_PFRCPIT1             40)
   (UNSPEC_PFRCPIT2             41)
   (UNSPEC_PFRSQRT              42)
   (UNSPEC_PFRSQIT1             43)
   (UNSPEC_MFENCE               44)
   (UNSPEC_LFENCE               45)
   (UNSPEC_PSADBW               46)
   (UNSPEC_LDDQU                47)

   ; Generic math support
   (UNSPEC_COPYSIGN             50)
   (UNSPEC_IEEE_MIN             51)     ; not commutative
   (UNSPEC_IEEE_MAX             52)     ; not commutative

   ; x87 Floating point
   (UNSPEC_SIN                  60)
   (UNSPEC_COS                  61)
   (UNSPEC_FPATAN               62)
   (UNSPEC_FYL2X                63)
   (UNSPEC_FYL2XP1              64)
   (UNSPEC_FRNDINT              65)
   (UNSPEC_FIST                 66)
   (UNSPEC_F2XM1                67)
   (UNSPEC_TAN                  68)
   (UNSPEC_FXAM                 69)

   ; x87 Rounding
   (UNSPEC_FRNDINT_FLOOR        70)
   (UNSPEC_FRNDINT_CEIL         71)
   (UNSPEC_FRNDINT_TRUNC        72)
   (UNSPEC_FRNDINT_MASK_PM      73)
   (UNSPEC_FIST_FLOOR           74)
   (UNSPEC_FIST_CEIL            75)

   ; x87 Double output FP
   (UNSPEC_SINCOS_COS           80)
   (UNSPEC_SINCOS_SIN           81)
   (UNSPEC_XTRACT_FRACT         84)
   (UNSPEC_XTRACT_EXP           85)
   (UNSPEC_FSCALE_FRACT         86)
   (UNSPEC_FSCALE_EXP           87)
   (UNSPEC_FPREM_F              88)
   (UNSPEC_FPREM_U              89)
   (UNSPEC_FPREM1_F             90)
   (UNSPEC_FPREM1_U             91)

   (UNSPEC_C2_FLAG              95)

   ; SSP patterns
   (UNSPEC_SP_SET               100)
   (UNSPEC_SP_TEST              101)
   (UNSPEC_SP_TLS_SET           102)
   (UNSPEC_SP_TLS_TEST          103)

   ; SSSE3
   (UNSPEC_PSHUFB               120)
   (UNSPEC_PSIGN                121)
   (UNSPEC_PALIGNR              122)

   ; For SSE4A support
   (UNSPEC_EXTRQI               130)
   (UNSPEC_EXTRQ                131)
   (UNSPEC_INSERTQI             132)
   (UNSPEC_INSERTQ              133)

   ; For SSE4.1 support
   (UNSPEC_BLENDV               134)
   (UNSPEC_INSERTPS             135)
   (UNSPEC_DP                   136)
   (UNSPEC_MOVNTDQA             137)
   (UNSPEC_MPSADBW              138)
   (UNSPEC_PHMINPOSUW           139)
   (UNSPEC_PTEST                140)
   (UNSPEC_ROUND                141)

   ; For SSE4.2 support
   (UNSPEC_CRC32                143)
   (UNSPEC_PCMPESTR             144)
   (UNSPEC_PCMPISTR             145)

   ;; For SSE5
   (UNSPEC_SSE5_INTRINSIC       150)
   (UNSPEC_SSE5_UNSIGNED_CMP    151)
   (UNSPEC_SSE5_TRUEFALSE       152)
   (UNSPEC_SSE5_PERMUTE         153)
   (UNSPEC_SSE5_ASHIFT          154)
   (UNSPEC_SSE5_LSHIFT          155)
   (UNSPEC_FRCZ                 156)
   (UNSPEC_CVTPH2PS             157)
   (UNSPEC_CVTPS2PH             158)
  ])

(define_constants
  [(UNSPECV_BLOCKAGE            0)
   (UNSPECV_STACK_PROBE         1)
   (UNSPECV_EMMS                2)
   (UNSPECV_LDMXCSR             3)
   (UNSPECV_STMXCSR             4)
   (UNSPECV_FEMMS               5)
   (UNSPECV_CLFLUSH             6)
   (UNSPECV_ALIGN               7)
   (UNSPECV_MONITOR             8)
   (UNSPECV_MWAIT               9)
   (UNSPECV_CMPXCHG_1           10)
   (UNSPECV_CMPXCHG_2           11)
   (UNSPECV_XCHG                12)
   (UNSPECV_LOCK                13)
   (UNSPECV_PROLOGUE_USE        14)
  ])

;; Constants to represent pcomtrue/pcomfalse variants
(define_constants
  [(PCOM_FALSE                  0)
   (PCOM_TRUE                   1)
   (COM_FALSE_S                 2)
   (COM_FALSE_P                 3)
   (COM_TRUE_S                  4)
   (COM_TRUE_P                  5)
  ])

;; Registers by name.
(define_constants
  [(AX_REG                       0)
   (DX_REG                       1)
   (CX_REG                       2)
   (SI_REG                       4)
   (DI_REG                       5)
   (BP_REG                       6)
   (SP_REG                       7)
   (FLAGS_REG                   17)
   (FPSR_REG                    18)
   (FPCR_REG                    19)
   (R10_REG                     39)
   (R11_REG                     40)
  ])

;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
;; from i386.c.

;; In C guard expressions, put expressions which may be compile-time
;; constants first.  This allows for better optimization.  For
;; example, write "TARGET_64BIT && reload_completed", not
;; "reload_completed && TARGET_64BIT".

\f
;; Processor type.  This attribute must exactly match the processor_type
;; enumeration in i386.h.
(define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,
                    nocona,core2,generic32,generic64,amdfam10"
  (const (symbol_ref "ix86_tune")))

;; A basic instruction type.  Refinements due to arguments to be
;; provided in other attributes.
(define_attr "type"
  "other,multi,
   alu,alu1,negnot,imov,imovx,lea,
   incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
   icmp,test,ibr,setcc,icmov,
   push,pop,call,callv,leave,
   str,bitmanip,
   fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint,
   sselog,sselog1,sseiadd,sseiadd1,sseishft,sseimul,
   sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,ssediv,sseins,
   ssemuladd,sse4arg,
   mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
  (const_string "other"))

;; Main data type used by the insn
(define_attr "mode"
  "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF,V1DF"
  (const_string "unknown"))

;; The CPU unit operations uses.
(define_attr "unit" "integer,i387,sse,mmx,unknown"
  (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint")
           (const_string "i387")
         (eq_attr "type" "sselog,sselog1,sseiadd,sseiadd1,sseishft,sseimul,
                          sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,
                          ssecvt1,sseicvt,ssediv,sseins,ssemuladd,sse4arg")
           (const_string "sse")
         (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
           (const_string "mmx")
         (eq_attr "type" "other")
           (const_string "unknown")]
         (const_string "integer")))

;; The (bounding maximum) length of an instruction immediate.
(define_attr "length_immediate" ""
  (cond [(eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave,
                          bitmanip")
           (const_int 0)
         (eq_attr "unit" "i387,sse,mmx")
           (const_int 0)
         (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
                          imul,icmp,push,pop")
           (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
         (eq_attr "type" "imov,test")
           (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
         (eq_attr "type" "call")
           (if_then_else (match_operand 0 "constant_call_address_operand" "")
             (const_int 4)
             (const_int 0))
         (eq_attr "type" "callv")
           (if_then_else (match_operand 1 "constant_call_address_operand" "")
             (const_int 4)
             (const_int 0))
         ;; We don't know the size before shorten_branches.  Expect
         ;; the instruction to fit for better scheduling.
         (eq_attr "type" "ibr")
           (const_int 1)
         ]
         (symbol_ref "/* Update immediate_length and other attributes! */
                      gcc_unreachable (),1")))

;; The (bounding maximum) length of an instruction address.
(define_attr "length_address" ""
  (cond [(eq_attr "type" "str,other,multi,fxch")
           (const_int 0)
         (and (eq_attr "type" "call")
              (match_operand 0 "constant_call_address_operand" ""))
             (const_int 0)
         (and (eq_attr "type" "callv")
              (match_operand 1 "constant_call_address_operand" ""))
             (const_int 0)
         ]
         (symbol_ref "ix86_attr_length_address_default (insn)")))

;; Set when length prefix is used.
(define_attr "prefix_data16" ""
  (if_then_else (ior (eq_attr "mode" "HI")
                     (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
    (const_int 1)
    (const_int 0)))

;; Set when string REP prefix is used.
(define_attr "prefix_rep" ""
  (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
    (const_int 1)
    (const_int 0)))

;; Set when 0f opcode prefix is used.
(define_attr "prefix_0f" ""
  (if_then_else
    (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip")
         (eq_attr "unit" "sse,mmx"))
    (const_int 1)
    (const_int 0)))

;; Set when REX opcode prefix is used.
(define_attr "prefix_rex" ""
  (cond [(and (eq_attr "mode" "DI")
              (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
           (const_int 1)
         (and (eq_attr "mode" "QI")
              (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
                  (const_int 0)))
           (const_int 1)
         (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
             (const_int 0))
           (const_int 1)
        ]
        (const_int 0)))

;; There are also additional prefixes in SSSE3.
(define_attr "prefix_extra" "" (const_int 0))

;; Set when modrm byte is used.
(define_attr "modrm" ""
  (cond [(eq_attr "type" "str,leave")
           (const_int 0)
         (eq_attr "unit" "i387")
           (const_int 0)
         (and (eq_attr "type" "incdec")
              (ior (match_operand:SI 1 "register_operand" "")
                   (match_operand:HI 1 "register_operand" "")))
           (const_int 0)
         (and (eq_attr "type" "push")
              (not (match_operand 1 "memory_operand" "")))
           (const_int 0)
         (and (eq_attr "type" "pop")
              (not (match_operand 0 "memory_operand" "")))
           (const_int 0)
         (and (eq_attr "type" "imov")
              (ior (and (match_operand 0 "register_operand" "")
                        (match_operand 1 "immediate_operand" ""))
                   (ior (and (match_operand 0 "ax_reg_operand" "")
                             (match_operand 1 "memory_displacement_only_operand" ""))
                        (and (match_operand 0 "memory_displacement_only_operand" "")
                             (match_operand 1 "ax_reg_operand" "")))))
           (const_int 0)
         (and (eq_attr "type" "call")
              (match_operand 0 "constant_call_address_operand" ""))
             (const_int 0)
         (and (eq_attr "type" "callv")
              (match_operand 1 "constant_call_address_operand" ""))
             (const_int 0)
         ]
         (const_int 1)))

;; The (bounding maximum) length of an instruction in bytes.
;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
;; Later we may want to split them and compute proper length as for
;; other insns.
(define_attr "length" ""
  (cond [(eq_attr "type" "other,multi,fistp,frndint")
           (const_int 16)
         (eq_attr "type" "fcmp")
           (const_int 4)
         (eq_attr "unit" "i387")
           (plus (const_int 2)
                 (plus (attr "prefix_data16")
                       (attr "length_address")))]
         (plus (plus (attr "modrm")
                     (plus (attr "prefix_0f")
                           (plus (attr "prefix_rex")
                                 (plus (attr "prefix_extra")
                                       (const_int 1)))))
               (plus (attr "prefix_rep")
                     (plus (attr "prefix_data16")
                           (plus (attr "length_immediate")
                                 (attr "length_address")))))))

;; The `memory' attribute is `none' if no memory is referenced, `load' or
;; `store' if there is a simple memory reference therein, or `unknown'
;; if the instruction is complex.

(define_attr "memory" "none,load,store,both,unknown"
  (cond [(eq_attr "type" "other,multi,str")
           (const_string "unknown")
         (eq_attr "type" "lea,fcmov,fpspc")
           (const_string "none")
         (eq_attr "type" "fistp,leave")
           (const_string "both")
         (eq_attr "type" "frndint")
           (const_string "load")
         (eq_attr "type" "push")
           (if_then_else (match_operand 1 "memory_operand" "")
             (const_string "both")
             (const_string "store"))
         (eq_attr "type" "pop")
           (if_then_else (match_operand 0 "memory_operand" "")
             (const_string "both")
             (const_string "load"))
         (eq_attr "type" "setcc")
           (if_then_else (match_operand 0 "memory_operand" "")
             (const_string "store")
             (const_string "none"))
         (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
           (if_then_else (ior (match_operand 0 "memory_operand" "")
                              (match_operand 1 "memory_operand" ""))
             (const_string "load")
             (const_string "none"))
         (eq_attr "type" "ibr")
           (if_then_else (match_operand 0 "memory_operand" "")
             (const_string "load")
             (const_string "none"))
         (eq_attr "type" "call")
           (if_then_else (match_operand 0 "constant_call_address_operand" "")
             (const_string "none")
             (const_string "load"))
         (eq_attr "type" "callv")
           (if_then_else (match_operand 1 "constant_call_address_operand" "")
             (const_string "none")
             (const_string "load"))
         (and (eq_attr "type" "alu1,negnot,ishift1,sselog1")
              (match_operand 1 "memory_operand" ""))
           (const_string "both")
         (and (match_operand 0 "memory_operand" "")
              (match_operand 1 "memory_operand" ""))
           (const_string "both")
         (match_operand 0 "memory_operand" "")
           (const_string "store")
         (match_operand 1 "memory_operand" "")
           (const_string "load")
         (and (eq_attr "type"
                 "!alu1,negnot,ishift1,
                   imov,imovx,icmp,test,bitmanip,
                   fmov,fcmp,fsgn,
                   sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,sselog1,
                   sseiadd1,mmx,mmxmov,mmxcmp,mmxcvt")
              (match_operand 2 "memory_operand" ""))
           (const_string "load")
         (and (eq_attr "type" "icmov,ssemuladd,sse4arg")
              (match_operand 3 "memory_operand" ""))
           (const_string "load")
        ]
        (const_string "none")))

;; Indicates if an instruction has both an immediate and a displacement.

(define_attr "imm_disp" "false,true,unknown"
  (cond [(eq_attr "type" "other,multi")
           (const_string "unknown")
         (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
              (and (match_operand 0 "memory_displacement_operand" "")
                   (match_operand 1 "immediate_operand" "")))
           (const_string "true")
         (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
              (and (match_operand 0 "memory_displacement_operand" "")
                   (match_operand 2 "immediate_operand" "")))
           (const_string "true")
        ]
        (const_string "false")))

;; Indicates if an FP operation has an integer source.

(define_attr "fp_int_src" "false,true"
  (const_string "false"))

;; Defines rounding mode of an FP operation.

(define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
  (const_string "any"))

;; Describe a user's asm statement.
(define_asm_attributes
  [(set_attr "length" "128")
   (set_attr "type" "multi")])

;; All integer comparison codes.
(define_code_iterator int_cond [ne eq ge gt le lt geu gtu leu ltu ])

;; All floating-point comparison codes.
(define_code_iterator fp_cond [unordered ordered
                               uneq unge ungt unle unlt ltgt ])

(define_code_iterator plusminus [plus minus])

;; Base name for define_insn and insn mnemonic.
(define_code_attr addsub [(plus "add") (minus "sub")])

;; Mark commutative operators as such in constraints.
(define_code_attr comm [(plus "%") (minus "")])

;; Mapping of signed max and min
(define_code_iterator smaxmin [smax smin])

;; Mapping of unsigned max and min
(define_code_iterator umaxmin [umax umin])

;; Base name for integer and FP insn mnemonic
(define_code_attr maxminiprefix [(smax "maxs") (smin "mins") (umax "maxu") (umin "minu")])
(define_code_attr maxminfprefix [(smax "max") (smin "min")])

;; Mapping of parallel logic operators
(define_code_iterator plogic [and ior xor])

;; Base name for insn mnemonic.
(define_code_attr plogicprefix [(and "and") (ior "or") (xor "xor")])

;; All single word integer modes.
(define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")])

;; Instruction suffix for integer modes.
(define_mode_attr imodesuffix [(QI "b") (HI "w") (SI "l") (DI "q")])

;; Register class for integer modes.
(define_mode_attr r [(QI "q") (HI "r") (SI "r") (DI "r")])

;; Immediate operand constraint for integer modes.
(define_mode_attr i [(QI "i") (HI "i") (SI "i") (DI "e")])

;; General operand predicate for integer modes.
(define_mode_attr general_operand
        [(QI "general_operand")
         (HI "general_operand")
         (SI "general_operand")
         (DI "x86_64_general_operand")])

;; SSE and x87 SFmode and DFmode floating point modes
(define_mode_iterator MODEF [SF DF])

;; All x87 floating point modes
(define_mode_iterator X87MODEF [SF DF XF])

;; All integer modes handled by x87 fisttp operator.
(define_mode_iterator X87MODEI [HI SI DI])

;; All integer modes handled by integer x87 operators.
(define_mode_iterator X87MODEI12 [HI SI])

;; All integer modes handled by SSE cvtts?2si* operators.
(define_mode_iterator SSEMODEI24 [SI DI])

;; SSE asm suffix for floating point modes
(define_mode_attr ssemodefsuffix [(SF "s") (DF "d")])

;; SSE vector mode corresponding to a scalar mode
(define_mode_attr ssevecmode
  [(QI "V16QI") (HI "V8HI") (SI "V4SI") (DI "V2DI") (SF "V4SF") (DF "V2DF")])

;; Instruction suffix for REX 64bit operators.
(define_mode_attr rex64suffix [(SI "") (DI "{q}")])
\f
;; Scheduling descriptions

(include "pentium.md")
(include "ppro.md")
(include "k6.md")
(include "athlon.md")
(include "geode.md")

\f
;; Operand and operator predicates and constraints

(include "predicates.md")
(include "constraints.md")

\f
;; Compare instructions.

;; All compare insns have expanders that save the operands away without
;; actually generating RTL.  The bCOND or sCOND (emitted immediately
;; after the cmp) will actually emit the cmpM.

(define_expand "cmpti"
  [(set (reg:CC FLAGS_REG)
        (compare:CC (match_operand:TI 0 "nonimmediate_operand" "")
                    (match_operand:TI 1 "x86_64_general_operand" "")))]
  "TARGET_64BIT"
{
  if (MEM_P (operands[0]) && MEM_P (operands[1]))
    operands[0] = force_reg (TImode, operands[0]);
  ix86_compare_op0 = operands[0];
  ix86_compare_op1 = operands[1];
  DONE;
})

(define_expand "cmpdi"
  [(set (reg:CC FLAGS_REG)
        (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
                    (match_operand:DI 1 "x86_64_general_operand" "")))]
  ""
{
  if (MEM_P (operands[0]) && MEM_P (operands[1]))
    operands[0] = force_reg (DImode, operands[0]);
  ix86_compare_op0 = operands[0];
  ix86_compare_op1 = operands[1];
  DONE;
})

(define_expand "cmpsi"
  [(set (reg:CC FLAGS_REG)
        (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
                    (match_operand:SI 1 "general_operand" "")))]
  ""
{
  if (MEM_P (operands[0]) && MEM_P (operands[1]))
    operands[0] = force_reg (SImode, operands[0]);
  ix86_compare_op0 = operands[0];
  ix86_compare_op1 = operands[1];
  DONE;
})

(define_expand "cmphi"
  [(set (reg:CC FLAGS_REG)
        (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
                    (match_operand:HI 1 "general_operand" "")))]
  ""
{
  if (MEM_P (operands[0]) && MEM_P (operands[1]))
    operands[0] = force_reg (HImode, operands[0]);
  ix86_compare_op0 = operands[0];
  ix86_compare_op1 = operands[1];
  DONE;
})

(define_expand "cmpqi"
  [(set (reg:CC FLAGS_REG)
        (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
                    (match_operand:QI 1 "general_operand" "")))]
  "TARGET_QIMODE_MATH"
{
  if (MEM_P (operands[0]) && MEM_P (operands[1]))
    operands[0] = force_reg (QImode, operands[0]);
  ix86_compare_op0 = operands[0];
  ix86_compare_op1 = operands[1];
  DONE;
})

(define_insn "cmpdi_ccno_1_rex64"
  [(set (reg FLAGS_REG)
        (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
                 (match_operand:DI 1 "const0_operand" "n,n")))]
  "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
  "@
   test{q}\t%0, %0
   cmp{q}\t{%1, %0|%0, %1}"
  [(set_attr "type" "test,icmp")
   (set_attr "length_immediate" "0,1")
   (set_attr "mode" "DI")])

(define_insn "*cmpdi_minus_1_rex64"
  [(set (reg FLAGS_REG)
        (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
                           (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
                 (const_int 0)))]
  "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
  "cmp{q}\t{%1, %0|%0, %1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "DI")])

(define_expand "cmpdi_1_rex64"
  [(set (reg:CC FLAGS_REG)
        (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
                    (match_operand:DI 1 "general_operand" "")))]
  "TARGET_64BIT"
  "")

(define_insn "cmpdi_1_insn_rex64"
  [(set (reg FLAGS_REG)
        (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
                 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
  "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
  "cmp{q}\t{%1, %0|%0, %1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "DI")])


(define_insn "*cmpsi_ccno_1"
  [(set (reg FLAGS_REG)
        (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
                 (match_operand:SI 1 "const0_operand" "n,n")))]
  "ix86_match_ccmode (insn, CCNOmode)"
  "@
   test{l}\t%0, %0
   cmp{l}\t{%1, %0|%0, %1}"
  [(set_attr "type" "test,icmp")
   (set_attr "length_immediate" "0,1")
   (set_attr "mode" "SI")])

(define_insn "*cmpsi_minus_1"
  [(set (reg FLAGS_REG)
        (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
                           (match_operand:SI 1 "general_operand" "ri,mr"))
                 (const_int 0)))]
  "ix86_match_ccmode (insn, CCGOCmode)"
  "cmp{l}\t{%1, %0|%0, %1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "SI")])

(define_expand "cmpsi_1"
  [(set (reg:CC FLAGS_REG)
        (compare:CC (match_operand:SI 0 "nonimmediate_operand" "")
                    (match_operand:SI 1 "general_operand" "")))]
  ""
  "")

(define_insn "*cmpsi_1_insn"
  [(set (reg FLAGS_REG)
        (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
                 (match_operand:SI 1 "general_operand" "ri,mr")))]
  "!(MEM_P (operands[0]) && MEM_P (operands[1]))
    && ix86_match_ccmode (insn, CCmode)"
  "cmp{l}\t{%1, %0|%0, %1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "SI")])

(define_insn "*cmphi_ccno_1"
  [(set (reg FLAGS_REG)
        (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
                 (match_operand:HI 1 "const0_operand" "n,n")))]
  "ix86_match_ccmode (insn, CCNOmode)"
  "@
   test{w}\t%0, %0
   cmp{w}\t{%1, %0|%0, %1}"
  [(set_attr "type" "test,icmp")
   (set_attr "length_immediate" "0,1")
   (set_attr "mode" "HI")])

(define_insn "*cmphi_minus_1"
  [(set (reg FLAGS_REG)
        (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
                           (match_operand:HI 1 "general_operand" "ri,mr"))
                 (const_int 0)))]
  "ix86_match_ccmode (insn, CCGOCmode)"
  "cmp{w}\t{%1, %0|%0, %1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "HI")])

(define_insn "*cmphi_1"
  [(set (reg FLAGS_REG)
        (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
                 (match_operand:HI 1 "general_operand" "ri,mr")))]
  "!(MEM_P (operands[0]) && MEM_P (operands[1]))
   && ix86_match_ccmode (insn, CCmode)"
  "cmp{w}\t{%1, %0|%0, %1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "HI")])

(define_insn "*cmpqi_ccno_1"
  [(set (reg FLAGS_REG)
        (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
                 (match_operand:QI 1 "const0_operand" "n,n")))]
  "ix86_match_ccmode (insn, CCNOmode)"
  "@
   test{b}\t%0, %0
   cmp{b}\t{$0, %0|%0, 0}"
  [(set_attr "type" "test,icmp")
   (set_attr "length_immediate" "0,1")
   (set_attr "mode" "QI")])

(define_insn "*cmpqi_1"
  [(set (reg FLAGS_REG)
        (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
                 (match_operand:QI 1 "general_operand" "qi,mq")))]
  "!(MEM_P (operands[0]) && MEM_P (operands[1]))
    && ix86_match_ccmode (insn, CCmode)"
  "cmp{b}\t{%1, %0|%0, %1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "QI")])

(define_insn "*cmpqi_minus_1"
  [(set (reg FLAGS_REG)
        (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
                           (match_operand:QI 1 "general_operand" "qi,mq"))
                 (const_int 0)))]
  "ix86_match_ccmode (insn, CCGOCmode)"
  "cmp{b}\t{%1, %0|%0, %1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "QI")])

(define_insn "*cmpqi_ext_1"
  [(set (reg FLAGS_REG)
        (compare
          (match_operand:QI 0 "general_operand" "Qm")
          (subreg:QI
            (zero_extract:SI
              (match_operand 1 "ext_register_operand" "Q")
              (const_int 8)
              (const_int 8)) 0)))]
  "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
  "cmp{b}\t{%h1, %0|%0, %h1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "QI")])

(define_insn "*cmpqi_ext_1_rex64"
  [(set (reg FLAGS_REG)
        (compare
          (match_operand:QI 0 "register_operand" "Q")
          (subreg:QI
            (zero_extract:SI
              (match_operand 1 "ext_register_operand" "Q")
              (const_int 8)
              (const_int 8)) 0)))]
  "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
  "cmp{b}\t{%h1, %0|%0, %h1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "QI")])

(define_insn "*cmpqi_ext_2"
  [(set (reg FLAGS_REG)
        (compare
          (subreg:QI
            (zero_extract:SI
              (match_operand 0 "ext_register_operand" "Q")
              (const_int 8)
              (const_int 8)) 0)
          (match_operand:QI 1 "const0_operand" "n")))]
  "ix86_match_ccmode (insn, CCNOmode)"
  "test{b}\t%h0, %h0"
  [(set_attr "type" "test")
   (set_attr "length_immediate" "0")
   (set_attr "mode" "QI")])

(define_expand "cmpqi_ext_3"
  [(set (reg:CC FLAGS_REG)
        (compare:CC
          (subreg:QI
            (zero_extract:SI
              (match_operand 0 "ext_register_operand" "")
              (const_int 8)
              (const_int 8)) 0)
          (match_operand:QI 1 "general_operand" "")))]
  ""
  "")

(define_insn "cmpqi_ext_3_insn"
  [(set (reg FLAGS_REG)
        (compare
          (subreg:QI
            (zero_extract:SI
              (match_operand 0 "ext_register_operand" "Q")
              (const_int 8)
              (const_int 8)) 0)
          (match_operand:QI 1 "general_operand" "Qmn")))]
  "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
  "cmp{b}\t{%1, %h0|%h0, %1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "QI")])

(define_insn "cmpqi_ext_3_insn_rex64"
  [(set (reg FLAGS_REG)
        (compare
          (subreg:QI
            (zero_extract:SI
              (match_operand 0 "ext_register_operand" "Q")
              (const_int 8)
              (const_int 8)) 0)
          (match_operand:QI 1 "nonmemory_operand" "Qn")))]
  "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
  "cmp{b}\t{%1, %h0|%h0, %1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "QI")])

(define_insn "*cmpqi_ext_4"
  [(set (reg FLAGS_REG)
        (compare
          (subreg:QI
            (zero_extract:SI
              (match_operand 0 "ext_register_operand" "Q")
              (const_int 8)
              (const_int 8)) 0)
          (subreg:QI
            (zero_extract:SI
              (match_operand 1 "ext_register_operand" "Q")
              (const_int 8)
              (const_int 8)) 0)))]
  "ix86_match_ccmode (insn, CCmode)"
  "cmp{b}\t{%h1, %h0|%h0, %h1}"
  [(set_attr "type" "icmp")
   (set_attr "mode" "QI")])

;; These implement float point compares.
;; %%% See if we can get away with VOIDmode operands on the actual insns,
;; which would allow mix and match FP modes on the compares.  Which is what
;; the old patterns did, but with many more of them.

(define_expand "cmpxf"
  [(set (reg:CC FLAGS_REG)
        (compare:CC (match_operand:XF 0 "nonmemory_operand" "")
                    (match_operand:XF 1 "nonmemory_operand" "")))]
  "TARGET_80387"
{
  ix86_compare_op0 = operands[0];
  ix86_compare_op1 = operands[1];
  DONE;
})

(define_expand "cmp<mode>"
  [(set (reg:CC FLAGS_REG)
        (compare:CC (match_operand:MODEF 0 "cmp_fp_expander_operand" "")
                    (match_operand:MODEF 1 "cmp_fp_expander_operand" "")))]
  "TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
  ix86_compare_op0 = operands[0];
  ix86_compare_op1 = operands[1];
  DONE;
})

;; FP compares, step 1:
;; Set the FP condition codes.
;;
;; CCFPmode     compare with exceptions
;; CCFPUmode    compare with no exceptions

;; We may not use "#" to split and emit these, since the REG_DEAD notes
;; used to manage the reg stack popping would not be preserved.

(define_insn "*cmpfp_0"
  [(set (match_operand:HI 0 "register_operand" "=a")
        (unspec:HI
          [(compare:CCFP
             (match_operand 1 "register_operand" "f")
             (match_operand 2 "const0_operand" "X"))]
        UNSPEC_FNSTSW))]
  "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
   && GET_MODE (operands[1]) == GET_MODE (operands[2])"
  "* return output_fp_compare (insn, operands, 0, 0);"
  [(set_attr "type" "multi")
   (set_attr "unit" "i387")
   (set (attr "mode")
     (cond [(match_operand:SF 1 "" "")
              (const_string "SF")
            (match_operand:DF 1 "" "")
              (const_string "DF")
           ]
           (const_string "XF")))])

(define_insn_and_split "*cmpfp_0_cc"
  [(set (reg:CCFP FLAGS_REG)
        (compare:CCFP
          (match_operand 1 "register_operand" "f")
          (match_operand 2 "const0_operand" "X")))
   (clobber (match_operand:HI 0 "register_operand" "=a"))]
  "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
   && TARGET_SAHF && !TARGET_CMOVE
   && GET_MODE (operands[1]) == GET_MODE (operands[2])"
  "#"
  "&& reload_completed"
  [(set (match_dup 0)
        (unspec:HI
          [(compare:CCFP (match_dup 1)(match_dup 2))]
        UNSPEC_FNSTSW))
   (set (reg:CC FLAGS_REG)
        (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
  ""
  [(set_attr "type" "multi")
   (set_attr "unit" "i387")
   (set (attr "mode")
     (cond [(match_operand:SF 1 "" "")
              (const_string "SF")
            (match_operand:DF 1 "" "")
              (const_string "DF")
           ]
           (const_string "XF")))])

(define_insn "*cmpfp_xf"
  [(set (match_operand:HI 0 "register_operand" "=a")
        (unspec:HI
          [(compare:CCFP
             (match_operand:XF 1 "register_operand" "f")
             (match_operand:XF 2 "register_operand" "f"))]
          UNSPEC_FNSTSW))]
  "TARGET_80387"
  "* return output_fp_compare (insn, operands, 0, 0);"
  [(set_attr "type" "multi")
   (set_attr "unit" "i387")
   (set_attr "mode" "XF")])

(define_insn_and_split "*cmpfp_xf_cc"
  [(set (reg:CCFP FLAGS_REG)
        (compare:CCFP
          (match_operand:XF 1 "register_operand" "f")
          (match_operand:XF 2 "register_operand" "f")))
   (clobber (match_operand:HI 0 "register_operand" "=a"))]
  "TARGET_80387
   && TARGET_SAHF && !TARGET_CMOVE"
  "#"
  "&& reload_completed"
  [(set (match_dup 0)
        (unspec:HI
          [(compare:CCFP (match_dup 1)(match_dup 2))]
        UNSPEC_FNSTSW))
   (set (reg:CC FLAGS_REG)
        (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
  ""
  [(set_attr "type" "multi")
   (set_attr "unit" "i387")
   (set_attr "mode" "XF")])

(define_insn "*cmpfp_<mode>"
  [(set (match_operand:HI 0 "register_operand" "=a")
        (unspec:HI
          [(compare:CCFP
             (match_operand:MODEF 1 "register_operand" "f")
             (match_operand:MODEF 2 "nonimmediate_operand" "fm"))]
          UNSPEC_FNSTSW))]
  "TARGET_80387"
  "* return output_fp_compare (insn, operands, 0, 0);"
  [(set_attr "type" "multi")
   (set_attr "unit" "i387")
   (set_attr "mode" "<MODE>")])

(define_insn_and_split "*cmpfp_<mode>_cc"
  [(set (reg:CCFP FLAGS_REG)
        (compare:CCFP
          (match_operand:MODEF 1 "register_operand" "f")
          (match_operand:MODEF 2 "nonimmediate_operand" "fm")))
   (clobber (match_operand:HI 0 "register_operand" "=a"))]
  "TARGET_80387
   && TARGET_SAHF && !TARGET_CMOVE"
  "#"
  "&& reload_completed"
  [(set (match_dup 0)
        (unspec:HI
          [(compare:CCFP (match_dup 1)(match_dup 2))]
        UNSPEC_FNSTSW))
   (set (reg:CC FLAGS_REG)
        (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
  ""
  [(set_attr "type" "multi")
   (set_attr "unit" "i387")
   (set_attr "mode" "<MODE>")])

(define_insn "*cmpfp_u"
  [(set (match_operand:HI 0 "register_operand" "=a")
        (unspec:HI
          [(compare:CCFPU
             (match_operand 1 "register_operand" "f")
             (match_operand 2 "register_operand" "f"))]
          UNSPEC_FNSTSW))]
  "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
   && GET_MODE (operands[1]) == GET_MODE (operands[2])"
  "* return output_fp_compare (insn, operands, 0, 1);"
  [(set_attr "type" "multi")
   (set_attr "unit" "i387")
   (set (attr "mode")
     (cond [(match_operand:SF 1 "" "")
              (const_string "SF")
            (match_operand:DF 1 "" "")
              (const_string "DF")
           ]
           (const_string "XF")))])

(define_insn_and_split "*cmpfp_u_cc"
  [(set (reg:CCFPU FLAGS_REG)
        (compare:CCFPU
          (match_operand 1 "register_operand" "f")
          (match_operand 2 "register_operand" "f")))
   (clobber (match_operand:HI 0 "register_operand" "=a"))]
  "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
   && TARGET_SAHF && !TARGET_CMOVE
   && GET_MODE (operands[1]) == GET_MODE (operands[2])"
  "#"
  "&& reload_completed"
  [(set (match_dup 0)
        (unspec:HI
          [(compare:CCFPU (match_dup 1)(match_dup 2))]
        UNSPEC_FNSTSW))
   (set (reg:CC FLAGS_REG)
        (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
  ""
  [(set_attr "type" "multi")
   (set_attr "unit" "i387")
   (set (attr "mode")
     (cond [(match_operand:SF 1 "" "")
              (const_string "SF")
            (match_operand:DF 1 "" "")
              (const_string "DF")
           ]
           (const_string "XF")))])

(define_insn "*cmpfp_<mode>"
  [(set (match_operand:HI 0 "register_operand" "=a")
        (unspec:HI
          [(compare:CCFP
             (match_operand 1 "register_operand" "f")
             (match_operator 3 "float_operator"
               [(match_operand:X87MODEI12 2 "memory_operand" "m")]))]
          UNSPEC_FNSTSW))]
  "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
   && TARGET_USE_<MODE>MODE_FIOP
   && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
  "* return output_fp_compare (insn, operands, 0, 0);"
  [(set_attr "type" "multi")
   (set_attr "unit" "i387")
   (set_attr "fp_int_src" "true")
   (set_attr "mode" "<MODE>")])

(define_insn_and_split "*cmpfp_<mode>_cc"
  [(set (reg:CCFP FLAGS_REG)
        (compare:CCFP
          (match_operand 1 "register_operand" "f")
          (match_operator 3 "float_operator"
            [(match_operand:X87MODEI12 2 "memory_operand" "m")])))
   (clobber (match_operand:HI 0 "register_operand" "=a"))]
  "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
   && TARGET_SAHF && !TARGET_CMOVE
   && TARGET_USE_<MODE>MODE_FIOP
   && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
  "#"
  "&& reload_completed"
  [(set (match_dup 0)
        (unspec:HI
          [(compare:CCFP
             (match_dup 1)
             (match_op_dup 3 [(match_dup 2)]))]
        UNSPEC_FNSTSW))
   (set (reg:CC FLAGS_REG)
        (unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
  ""
  [(set_attr "type" "multi")
   (set_attr "unit" "i387")
   (set_attr "fp_int_src" "true")
   (set_attr "mode" "<MODE>")])

;; FP compares, step 2
;; Move the fpsw to ax.

(define_insn "x86_fnstsw_1"
  [(set (match_operand:HI 0 "register_operand" "=a")
        (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
  "TARGET_80387"
  "fnstsw\t%0"
  [(set_attr "length" "2")
   (set_attr "mode" "SI")
   (set_attr "unit" "i387")])

;; FP compares, step 3
;; Get ax into flags, general case.

(define_insn "x86_sahf_1"
  [(set (reg:CC FLAGS_REG)
        (unspec:CC [(match_operand:HI 0 "register_operand" "a")]
                   UNSPEC_SAHF))]
  "TARGET_SAHF"
{
#ifdef HAVE_AS_IX86_SAHF
  return "sahf";
#else
  return ".byte\t0x9e";
#endif
}
  [(set_attr "length" "1")
   (set_attr "athlon_decode" "vector")
   (set_attr "amdfam10_decode" "direct")
   (set_attr "mode" "SI")])

;; Pentium Pro can do steps 1 through 3 in one go.
;; comi*, ucomi*, fcomi*, ficomi*,fucomi* (i387 instructions set condition codes)
(define_insn "*cmpfp_i_mixed"
  [(set (reg:CCFP FLAGS_REG)
        (compare:CCFP (match_operand 0 "register_operand" "f,x")
                      (match_operand 1 "nonimmediate_operand" "f,xm")))]
  "TARGET_MIX_SSE_I387
   && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
   && GET_MODE (operands[0]) == GET_MODE (operands[1])"
  "* return output_fp_compare (insn, operands, 1, 0);"
  [(set_attr "type" "fcmp,ssecomi")
   (set (attr "mode")
     (if_then_else (match_operand:SF 1 "" "")
        (const_string "SF")
        (const_string "DF")))
   (set_attr "athlon_decode" "vector")
   (set_attr "amdfam10_decode" "direct")])

(define_insn "*cmpfp_i_sse"
  [(set (reg:CCFP FLAGS_REG)
        (compare:CCFP (match_operand 0 "register_operand" "x")
                      (match_operand 1 "nonimmediate_operand" "xm")))]
  "TARGET_SSE_MATH
   && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
   && GET_MODE (operands[0]) == GET_MODE (operands[1])"
  "* return output_fp_compare (insn, operands, 1, 0);"
  [(set_attr "type" "ssecomi")
   (set (attr "mode")
     (if_then_else (match_operand:SF 1 "" "")
        (const_string "SF")
        (const_string "DF")))
   (set_attr "athlon_decode" "vector")
   (set_attr "amdfam10_decode" "direct")])

(define_insn "*cmpfp_i_i387"
  [(set (reg:CCFP FLAGS_REG)
        (compare:CCFP (match_operand 0 "register_operand" "f")
                      (match_operand 1 "register_operand" "f")))]
  "X87_FLOAT_MODE_P (GET_MODE (operands[0]))
   && TARGET_CMOVE
   && !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
   && GET_MODE (operands[0]) == GET_MODE (operands[1])"
  "* return output_fp_compare (insn, operands, 1, 0);"
  [(set_attr "type" "fcmp")
   (set (attr "mode")
     (cond [(match_operand:SF 1 "" "")
              (const_string "SF")
            (match_operand:DF 1 "" "")
              (const_string "DF")
           ]
           (const_string "XF")))
   (set_attr "athlon_decode" "vector")
   (set_attr "amdfam10_decode" "direct")])

(define_insn "*cmpfp_iu_mixed"
  [(set (reg:CCFPU FLAGS_REG)
        (compare:CCFPU (match_operand 0 "register_operand" "f,x")
                       (match_operand 1 "nonimmediate_operand" "f,xm")))]
  "TARGET_MIX_SSE_I387
   && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
   && GET_MODE (operands[0]) == GET_MODE (operands[1])"
  "* return output_fp_compare (insn, operands, 1, 1);"
  [(set_attr "type" "fcmp,ssecomi")
   (set (attr "mode")
     (if_then_else (match_operand:SF 1 "" "")
        (const_string "SF")
        (const_string "DF")))
   (set_attr "athlon_decode" "vector")
   (set_attr "amdfam10_decode" "direct")])

(define_insn "*cmpfp_iu_sse"
  [(set (reg:CCFPU FLAGS_REG)
        (compare:CCFPU (match_operand 0 "register_operand" "x")
                       (match_operand 1 "nonimmediate_operand" "xm")))]
  "TARGET_SSE_MATH
   && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
   && GET_MODE (operands[0]) == GET_MODE (operands[1])"
  "* return output_fp_compare (insn, operands, 1, 1);"
  [(set_attr "type" "ssecomi")
   (set (attr "mode")
     (if_then_else (match_operand:SF 1 "" "")
        (const_string "SF")
        (const_string "DF")))
   (set_attr "athlon_decode" "vector")
   (set_attr "amdfam10_decode" "direct")])

(define_insn "*cmpfp_iu_387"
  [(set (reg:CCFPU FLAGS_REG)
        (compare:CCFPU (match_operand 0 "register_operand" "f")
                       (match_operand 1 "register_operand" "f")))]
  "X87_FLOAT_MODE_P (GET_MODE (operands[0]))
   && TARGET_CMOVE
   && !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
   && GET_MODE (operands[0]) == GET_MODE (operands[1])"
  "* return output_fp_compare (insn, operands, 1, 1);"
  [(set_attr "type" "fcmp")
   (set (attr "mode")
     (cond [(match_operand:SF 1 "" "")
              (const_string "SF")
            (match_operand:DF 1 "" "")
              (const_string "DF")
           ]
           (const_string "XF")))
   (set_attr "athlon_decode" "vector")
   (set_attr "amdfam10_decode" "direct")])
\f
;; Move instructions.

;; General case of fullword move.

(define_expand "movsi"
  [(set (match_operand:SI 0 "nonimmediate_operand" "")
        (match_operand:SI 1 "general_operand" ""))]
  ""
  "ix86_expand_move (SImode, operands); DONE;")

;; Push/pop instructions.  They are separate since autoinc/dec is not a
;; general_operand.
;;
;; %%% We don't use a post-inc memory reference because x86 is not a
;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
;; targets without our curiosities, and it is just as easy to represent
;; this differently.

(define_insn "*pushsi2"
  [(set (match_operand:SI 0 "push_operand" "=<")
        (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
  "!TARGET_64BIT"
  "push{l}\t%1"
  [(set_attr "type" "push")
   (set_attr "mode" "SI")])

;; For 64BIT abi we always round up to 8 bytes.
(define_insn "*pushsi2_rex64"
  [(set (match_operand:SI 0 "push_operand" "=X")
        (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
  "TARGET_64BIT"
  "push{q}\t%q1"
  [(set_attr "type" "push")
   (set_attr "mode" "SI")])

(define_insn "*pushsi2_prologue"
  [(set (match_operand:SI 0 "push_operand" "=<")
        (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
   (clobber (mem:BLK (scratch)))]
  "!TARGET_64BIT"
  "push{l}\t%1"
  [(set_attr "type" "push")
   (set_attr "mode" "SI")])

(define_insn "*popsi1_epilogue"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
        (mem:SI (reg:SI SP_REG)))
   (set (reg:SI SP_REG)
        (plus:SI (reg:SI SP_REG) (const_int 4)))
   (clobber (mem:BLK (scratch)))]
  "!TARGET_64BIT"
  "pop{l}\t%0"
  [(set_attr "type" "pop")
   (set_attr "mode" "SI")])

(define_insn "popsi1"
  [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
        (mem:SI (reg:SI SP_REG)))
   (set (reg:SI SP_REG)
        (plus:SI (reg:SI SP_REG) (const_int 4)))]
  "!TARGET_64BIT"
  "pop{l}\t%0"
  [(set_attr "type" "pop")
   (set_attr "mode" "SI")])

(define_insn "*movsi_xor"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (match_operand:SI 1 "const0_operand" "i"))
   (clobber (reg:CC FLAGS_REG))]
  "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
  "xor{l}\t%0, %0"
  [(set_attr "type" "alu1")
   (set_attr "mode" "SI")
   (set_attr "length_immediate" "0")])

(define_insn "*movsi_or"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (match_operand:SI 1 "immediate_operand" "i"))
   (clobber (reg:CC FLAGS_REG))]
  "reload_completed
   && operands[1] == constm1_rtx
   && (TARGET_MOVE_M1_VIA_OR || optimize_size)"
{
  operands[1] = constm1_rtx;
  return "or{l}\t{%1, %0|%0, %1}";
}
  [(set_attr "type" "alu1")
   (set_attr "mode" "SI")
   (set_attr "length_immediate" "1")])

(define_insn "*movsi_1"
  [(set (match_operand:SI 0 "nonimmediate_operand"
                        "=r  ,m  ,*y,*y,?rm,?*y,*x,*x,?r ,m ,?*Yi,*x")
        (match_operand:SI 1 "general_operand"
                        "rinm,rin,C ,*y,*y ,rm ,C ,*x,*Yi,*x,r   ,m "))]
  "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
  switch (get_attr_type (insn))
    {
    case TYPE_SSELOG1:
      if (get_attr_mode (insn) == MODE_TI)
        return "pxor\t%0, %0";
      return "xorps\t%0, %0";

    case TYPE_SSEMOV:
      switch (get_attr_mode (insn))
        {
        case MODE_TI:
          return "movdqa\t{%1, %0|%0, %1}";
        case MODE_V4SF:
          return "movaps\t{%1, %0|%0, %1}";
        case MODE_SI:
          return "movd\t{%1, %0|%0, %1}";
        case MODE_SF:
          return "movss\t{%1, %0|%0, %1}";
        default:
          gcc_unreachable ();
        }

    case TYPE_MMXADD:
      return "pxor\t%0, %0";

    case TYPE_MMXMOV:
      if (get_attr_mode (insn) == MODE_DI)
        return "movq\t{%1, %0|%0, %1}";
      return "movd\t{%1, %0|%0, %1}";

    case TYPE_LEA:
      return "lea{l}\t{%1, %0|%0, %1}";

    default:
      gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
      return "mov{l}\t{%1, %0|%0, %1}";
    }
}
  [(set (attr "type")
     (cond [(eq_attr "alternative" "2")
              (const_string "mmxadd")
            (eq_attr "alternative" "3,4,5")
              (const_string "mmxmov")
            (eq_attr "alternative" "6")
              (const_string "sselog1")
            (eq_attr "alternative" "7,8,9,10,11")
              (const_string "ssemov")
            (match_operand:DI 1 "pic_32bit_operand" "")
              (const_string "lea")
           ]
           (const_string "imov")))
   (set (attr "mode")
     (cond [(eq_attr "alternative" "2,3")
              (const_string "DI")
            (eq_attr "alternative" "6,7")
              (if_then_else
                (eq (symbol_ref "TARGET_SSE2") (const_int 0))
                (const_string "V4SF")
                (const_string "TI"))
            (and (eq_attr "alternative" "8,9,10,11")
                 (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
              (const_string "SF")
           ]
           (const_string "SI")))])

;; Stores and loads of ax to arbitrary constant address.
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabssi_1_rex64"
  [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
        (match_operand:SI 1 "nonmemory_operand" "a,er"))]
  "TARGET_64BIT && ix86_check_movabs (insn, 0)"
  "@
   movabs{l}\t{%1, %P0|%P0, %1}
   mov{l}\t{%1, %a0|%a0, %1}"
  [(set_attr "type" "imov")
   (set_attr "modrm" "0,*")
   (set_attr "length_address" "8,0")
   (set_attr "length_immediate" "0,*")
   (set_attr "memory" "store")
   (set_attr "mode" "SI")])

(define_insn "*movabssi_2_rex64"
  [(set (match_operand:SI 0 "register_operand" "=a,r")
        (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
  "TARGET_64BIT && ix86_check_movabs (insn, 1)"
  "@
   movabs{l}\t{%P1, %0|%0, %P1}
   mov{l}\t{%a1, %0|%0, %a1}"
  [(set_attr "type" "imov")
   (set_attr "modrm" "0,*")
   (set_attr "length_address" "8,0")
   (set_attr "length_immediate" "0")
   (set_attr "memory" "load")
   (set_attr "mode" "SI")])

(define_insn "*swapsi"
  [(set (match_operand:SI 0 "register_operand" "+r")
        (match_operand:SI 1 "register_operand" "+r"))
   (set (match_dup 1)
        (match_dup 0))]
  ""
  "xchg{l}\t%1, %0"
  [(set_attr "type" "imov")
   (set_attr "mode" "SI")
   (set_attr "pent_pair" "np")
   (set_attr "athlon_decode" "vector")
   (set_attr "amdfam10_decode" "double")])

(define_expand "movhi"
  [(set (match_operand:HI 0 "nonimmediate_operand" "")
        (match_operand:HI 1 "general_operand" ""))]
  ""
  "ix86_expand_move (HImode, operands); DONE;")

(define_insn "*pushhi2"
  [(set (match_operand:HI 0 "push_operand" "=X")
        (match_operand:HI 1 "nonmemory_no_elim_operand" "rn"))]
  "!TARGET_64BIT"
  "push{l}\t%k1"
  [(set_attr "type" "push")
   (set_attr "mode" "SI")])

;; For 64BIT abi we always round up to 8 bytes.
(define_insn "*pushhi2_rex64"
  [(set (match_operand:HI 0 "push_operand" "=X")
        (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
  "TARGET_64BIT"
  "push{q}\t%q1"
  [(set_attr "type" "push")
   (set_attr "mode" "DI")])

(define_insn "*movhi_1"
  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
        (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
  "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
  switch (get_attr_type (insn))
    {
    case TYPE_IMOVX:
      /* movzwl is faster than movw on p2 due to partial word stalls,
         though not as fast as an aligned movl.  */
      return "movz{wl|x}\t{%1, %k0|%k0, %1}";
    default:
      if (get_attr_mode (insn) == MODE_SI)
        return "mov{l}\t{%k1, %k0|%k0, %k1}";
      else
        return "mov{w}\t{%1, %0|%0, %1}";
    }
}
  [(set (attr "type")
     (cond [(ne (symbol_ref "optimize_size") (const_int 0))
              (const_string "imov")
            (and (eq_attr "alternative" "0")
                 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
                          (const_int 0))
                      (eq (symbol_ref "TARGET_HIMODE_MATH")
                          (const_int 0))))
              (const_string "imov")
            (and (eq_attr "alternative" "1,2")
                 (match_operand:HI 1 "aligned_operand" ""))
              (const_string "imov")
            (and (ne (symbol_ref "TARGET_MOVX")
                     (const_int 0))
                 (eq_attr "alternative" "0,2"))
              (const_string "imovx")
           ]
           (const_string "imov")))
    (set (attr "mode")
      (cond [(eq_attr "type" "imovx")
               (const_string "SI")
             (and (eq_attr "alternative" "1,2")
                  (match_operand:HI 1 "aligned_operand" ""))
               (const_string "SI")
             (and (eq_attr "alternative" "0")
                  (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
                           (const_int 0))
                       (eq (symbol_ref "TARGET_HIMODE_MATH")
                           (const_int 0))))
               (const_string "SI")
            ]
            (const_string "HI")))])

;; Stores and loads of ax to arbitrary constant address.
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabshi_1_rex64"
  [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
        (match_operand:HI 1 "nonmemory_operand" "a,er"))]
  "TARGET_64BIT && ix86_check_movabs (insn, 0)"
  "@
   movabs{w}\t{%1, %P0|%P0, %1}
   mov{w}\t{%1, %a0|%a0, %1}"
  [(set_attr "type" "imov")
   (set_attr "modrm" "0,*")
   (set_attr "length_address" "8,0")
   (set_attr "length_immediate" "0,*")
   (set_attr "memory" "store")
   (set_attr "mode" "HI")])

(define_insn "*movabshi_2_rex64"
  [(set (match_operand:HI 0 "register_operand" "=a,r")
        (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
  "TARGET_64BIT && ix86_check_movabs (insn, 1)"
  "@
   movabs{w}\t{%P1, %0|%0, %P1}
   mov{w}\t{%a1, %0|%0, %a1}"
  [(set_attr "type" "imov")
   (set_attr "modrm" "0,*")
   (set_attr "length_address" "8,0")
   (set_attr "length_immediate" "0")
   (set_attr "memory" "load")
   (set_attr "mode" "HI")])

(define_insn "*swaphi_1"
  [(set (match_operand:HI 0 "register_operand" "+r")
        (match_operand:HI 1 "register_operand" "+r"))
   (set (match_dup 1)
        (match_dup 0))]
  "!TARGET_PARTIAL_REG_STALL || optimize_size"
  "xchg{l}\t%k1, %k0"
  [(set_attr "type" "imov")
   (set_attr "mode" "SI")
   (set_attr "pent_pair" "np")
   (set_attr "athlon_decode" "vector")
   (set_attr "amdfam10_decode" "double")])

;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
(define_insn "*swaphi_2"
  [(set (match_operand:HI 0 "register_operand" "+r")
        (match_operand:HI 1 "register_operand" "+r"))
   (set (match_dup 1)
        (match_dup 0))]
  "TARGET_PARTIAL_REG_STALL"
  "xchg{w}\t%1, %0"
  [(set_attr "type" "imov")
   (set_attr "mode" "HI")
   (set_attr "pent_pair" "np")
   (set_attr "athlon_decode" "vector")])

(define_expand "movstricthi"
  [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
        (match_operand:HI 1 "general_operand" ""))]
  "! TARGET_PARTIAL_REG_STALL || optimize_size"
{
  /* Don't generate memory->memory moves, go through a register */
  if (MEM_P (operands[0]) && MEM_P (operands[1]))
    operands[1] = force_reg (HImode, operands[1]);
})

(define_insn "*movstricthi_1"
  [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
        (match_operand:HI 1 "general_operand" "rn,m"))]
  "(! TARGET_PARTIAL_REG_STALL || optimize_size)
   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  "mov{w}\t{%1, %0|%0, %1}"
  [(set_attr "type" "imov")
   (set_attr "mode" "HI")])

(define_insn "*movstricthi_xor"
  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
        (match_operand:HI 1 "const0_operand" "i"))
   (clobber (reg:CC FLAGS_REG))]
  "reload_completed
   && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
  "xor{w}\t%0, %0"
  [(set_attr "type" "alu1")
   (set_attr "mode" "HI")
   (set_attr "length_immediate" "0")])

(define_expand "movqi"
  [(set (match_operand:QI 0 "nonimmediate_operand" "")
        (match_operand:QI 1 "general_operand" ""))]
  ""
  "ix86_expand_move (QImode, operands); DONE;")

;; emit_push_insn when it calls move_by_pieces requires an insn to
;; "push a byte".  But actually we use pushl, which has the effect
;; of rounding the amount pushed up to a word.

(define_insn "*pushqi2"
  [(set (match_operand:QI 0 "push_operand" "=X")
        (match_operand:QI 1 "nonmemory_no_elim_operand" "rn"))]
  "!TARGET_64BIT"
  "push{l}\t%k1"
  [(set_attr "type" "push")
   (set_attr "mode" "SI")])

;; For 64BIT abi we always round up to 8 bytes.
(define_insn "*pushqi2_rex64"
  [(set (match_operand:QI 0 "push_operand" "=X")
        (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
  "TARGET_64BIT"
  "push{q}\t%q1"
  [(set_attr "type" "push")
   (set_attr "mode" "DI")])

;; Situation is quite tricky about when to choose full sized (SImode) move
;; over QImode moves.  For Q_REG -> Q_REG move we use full size only for
;; partial register dependency machines (such as AMD Athlon), where QImode
;; moves issue extra dependency and for partial register stalls machines
;; that don't use QImode patterns (and QImode move cause stall on the next
;; instruction).
;;
;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
;; register stall machines with, where we use QImode instructions, since
;; partial register stall can be caused there.  Then we use movzx.
(define_insn "*movqi_1"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
        (match_operand:QI 1 "general_operand"      " q,qn,qm,q,rn,qm,qn"))]
  "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
  switch (get_attr_type (insn))
    {
    case TYPE_IMOVX:
      gcc_assert (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]));
      return "movz{bl|x}\t{%1, %k0|%k0, %1}";
    default:
      if (get_attr_mode (insn) == MODE_SI)
        return "mov{l}\t{%k1, %k0|%k0, %k1}";
      else
        return "mov{b}\t{%1, %0|%0, %1}";
    }
}
  [(set (attr "type")
     (cond [(and (eq_attr "alternative" "5")
                 (not (match_operand:QI 1 "aligned_operand" "")))
              (const_string "imovx")
            (ne (symbol_ref "optimize_size") (const_int 0))
              (const_string "imov")
            (and (eq_attr "alternative" "3")
                 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
                          (const_int 0))
                      (eq (symbol_ref "TARGET_QIMODE_MATH")
                          (const_int 0))))
              (const_string "imov")
            (eq_attr "alternative" "3,5")
              (const_string "imovx")
            (and (ne (symbol_ref "TARGET_MOVX")
                     (const_int 0))
                 (eq_attr "alternative" "2"))
              (const_string "imovx")
           ]
           (const_string "imov")))
   (set (attr "mode")
      (cond [(eq_attr "alternative" "3,4,5")
               (const_string "SI")
             (eq_attr "alternative" "6")
               (const_string "QI")
             (eq_attr "type" "imovx")
               (const_string "SI")
             (and (eq_attr "type" "imov")
                  (and (eq_attr "alternative" "0,1")
                       (and (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
                                (const_int 0))
                            (and (eq (symbol_ref "optimize_size")
                                     (const_int 0))
                                 (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
                                     (const_int 0))))))
               (const_string "SI")
             ;; Avoid partial register stalls when not using QImode arithmetic
             (and (eq_attr "type" "imov")
                  (and (eq_attr "alternative" "0,1")
                       (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
                                (const_int 0))
                            (eq (symbol_ref "TARGET_QIMODE_MATH")
                                (const_int 0)))))
               (const_string "SI")
           ]
           (const_string "QI")))])

(define_expand "reload_outqi"
  [(parallel [(match_operand:QI 0 "" "=m")
              (match_operand:QI 1 "register_operand" "r")
              (match_operand:QI 2 "register_operand" "=&q")])]
  ""
{
  rtx op0, op1, op2;
  op0 = operands[0]; op1 = operands[1]; op2 = operands[2];

  gcc_assert (!reg_overlap_mentioned_p (op2, op0));
  if (! q_regs_operand (op1, QImode))
    {
      emit_insn (gen_movqi (op2, op1));
      op1 = op2;
    }
  emit_insn (gen_movqi (op0, op1));
  DONE;
})

(define_insn "*swapqi_1"
  [(set (match_operand:QI 0 "register_operand" "+r")
        (match_operand:QI 1 "register_operand" "+r"))
   (set (match_dup 1)
        (match_dup 0))]
  "!TARGET_PARTIAL_REG_STALL || optimize_size"
  "xchg{l}\t%k1, %k0"
  [(set_attr "type" "imov")
   (set_attr "mode" "SI")
   (set_attr "pent_pair" "np")
   (set_attr "athlon_decode" "vector")
   (set_attr "amdfam10_decode" "vector")])

;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
(define_insn "*swapqi_2"
  [(set (match_operand:QI 0 "register_operand" "+q")
        (match_operand:QI 1 "register_operand" "+q"))
   (set (match_dup 1)
        (match_dup 0))]
  "TARGET_PARTIAL_REG_STALL"
  "xchg{b}\t%1, %0"
  [(set_attr "type" "imov")
   (set_attr "mode" "QI")
   (set_attr "pent_pair" "np")
   (set_attr "athlon_decode" "vector")])

(define_expand "movstrictqi"
  [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
        (match_operand:QI 1 "general_operand" ""))]
  "! TARGET_PARTIAL_REG_STALL || optimize_size"
{
  /* Don't generate memory->memory moves, go through a register.  */
  if (MEM_P (operands[0]) && MEM_P (operands[1]))
    operands[1] = force_reg (QImode, operands[1]);
})

(define_insn "*movstrictqi_1"
  [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
        (match_operand:QI 1 "general_operand" "*qn,m"))]
  "(! TARGET_PARTIAL_REG_STALL || optimize_size)
   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  "mov{b}\t{%1, %0|%0, %1}"
  [(set_attr "type" "imov")
   (set_attr "mode" "QI")])

(define_insn "*movstrictqi_xor"
  [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
        (match_operand:QI 1 "const0_operand" "i"))
   (clobber (reg:CC FLAGS_REG))]
  "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
  "xor{b}\t%0, %0"
  [(set_attr "type" "alu1")
   (set_attr "mode" "QI")
   (set_attr "length_immediate" "0")])

(define_insn "*movsi_extv_1"
  [(set (match_operand:SI 0 "register_operand" "=R")
        (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
                         (const_int 8)
                         (const_int 8)))]
  ""
  "movs{bl|x}\t{%h1, %0|%0, %h1}"
  [(set_attr "type" "imovx")
   (set_attr "mode" "SI")])

(define_insn "*movhi_extv_1"
  [(set (match_operand:HI 0 "register_operand" "=R")
        (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
                         (const_int 8)
                         (const_int 8)))]
  ""
  "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
  [(set_attr "type" "imovx")
   (set_attr "mode" "SI")])

(define_insn "*movqi_extv_1"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
        (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
                         (const_int 8)
                         (const_int 8)))]
  "!TARGET_64BIT"
{
  switch (get_attr_type (insn))
    {
    case TYPE_IMOVX:
      return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
    default:
      return "mov{b}\t{%h1, %0|%0, %h1}";
    }
}
  [(set (attr "type")
     (if_then_else (and (match_operand:QI 0 "register_operand" "")
                        (ior (not (match_operand:QI 0 "q_regs_operand" ""))
                             (ne (symbol_ref "TARGET_MOVX")
                                 (const_int 0))))
        (const_string "imovx")
        (const_string "imov")))
   (set (attr "mode")
     (if_then_else (eq_attr "type" "imovx")
        (const_string "SI")
        (const_string "QI")))])

(define_insn "*movqi_extv_1_rex64"
  [(set (match_operand:QI 0 "register_operand" "=Q,?R")
        (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
                         (const_int 8)
                         (const_int 8)))]
  "TARGET_64BIT"
{
  switch (get_attr_type (insn))
    {
    case TYPE_IMOVX:
      return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
    default:
      return "mov{b}\t{%h1, %0|%0, %h1}";
    }
}
  [(set (attr "type")
     (if_then_else (and (match_operand:QI 0 "register_operand" "")
                        (ior (not (match_operand:QI 0 "q_regs_operand" ""))
                             (ne (symbol_ref "TARGET_MOVX")
                                 (const_int 0))))
        (const_string "imovx")
        (const_string "imov")))
   (set (attr "mode")
     (if_then_else (eq_attr "type" "imovx")
        (const_string "SI")
        (const_string "QI")))])

;; Stores and loads of ax to arbitrary constant address.
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabsqi_1_rex64"
  [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
        (match_operand:QI 1 "nonmemory_operand" "a,er"))]
  "TARGET_64BIT && ix86_check_movabs (insn, 0)"
  "@
   movabs{b}\t{%1, %P0|%P0, %1}
   mov{b}\t{%1, %a0|%a0, %1}"
  [(set_attr "type" "imov")
   (set_attr "modrm" "0,*")
   (set_attr "length_address" "8,0")
   (set_attr "length_immediate" "0,*")
   (set_attr "memory" "store")
   (set_attr "mode" "QI")])

(define_insn "*movabsqi_2_rex64"
  [(set (match_operand:QI 0 "register_operand" "=a,r")
        (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
  "TARGET_64BIT && ix86_check_movabs (insn, 1)"
  "@
   movabs{b}\t{%P1, %0|%0, %P1}
   mov{b}\t{%a1, %0|%0, %a1}"
  [(set_attr "type" "imov")
   (set_attr "modrm" "0,*")
   (set_attr "length_address" "8,0")
   (set_attr "length_immediate" "0")
   (set_attr "memory" "load")
   (set_attr "mode" "QI")])

(define_insn "*movdi_extzv_1"
  [(set (match_operand:DI 0 "register_operand" "=R")
        (zero_extract:DI (match_operand 1 "ext_register_operand" "Q")
                         (const_int 8)
                         (const_int 8)))]
  "TARGET_64BIT"
  "movz{bl|x}\t{%h1, %k0|%k0, %h1}"
  [(set_attr "type" "imovx")
   (set_attr "mode" "DI")])

(define_insn "*movsi_extzv_1"
  [(set (match_operand:SI 0 "register_operand" "=R")
        (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
                         (const_int 8)
                         (const_int 8)))]
  ""
  "movz{bl|x}\t{%h1, %0|%0, %h1}"
  [(set_attr "type" "imovx")
   (set_attr "mode" "SI")])

(define_insn "*movqi_extzv_2"
  [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
        (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
                                    (const_int 8)
                                    (const_int 8)) 0))]
  "!TARGET_64BIT"
{
  switch (get_attr_type (insn))
    {
    case TYPE_IMOVX:
      return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
    default:
      return "mov{b}\t{%h1, %0|%0, %h1}";
    }
}
  [(set (attr "type")
     (if_then_else (and (match_operand:QI 0 "register_operand" "")
                        (ior (not (match_operand:QI 0 "q_regs_operand" ""))
                             (ne (symbol_ref "TARGET_MOVX")
                                 (const_int 0))))
        (const_string "imovx")
        (const_string "imov")))
   (set (attr "mode")
     (if_then_else (eq_attr "type" "imovx")
        (const_string "SI")
        (const_string "QI")))])

(define_insn "*movqi_extzv_2_rex64"
  [(set (match_operand:QI 0 "register_operand" "=Q,?R")
        (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
                                    (const_int 8)
                                    (const_int 8)) 0))]
  "TARGET_64BIT"
{
  switch (get_attr_type (insn))
    {
    case TYPE_IMOVX:
      return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
    default:
      return "mov{b}\t{%h1, %0|%0, %h1}";
    }
}
  [(set (attr "type")
     (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
                        (ne (symbol_ref "TARGET_MOVX")
                            (const_int 0)))
        (const_string "imovx")
        (const_string "imov")))
   (set (attr "mode")
     (if_then_else (eq_attr "type" "imovx")
        (const_string "SI")
        (const_string "QI")))])

(define_insn "movsi_insv_1"
  [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
                         (const_int 8)
                         (const_int 8))
        (match_operand:SI 1 "general_operand" "Qmn"))]
  "!TARGET_64BIT"
  "mov{b}\t{%b1, %h0|%h0, %b1}"
  [(set_attr "type" "imov")
   (set_attr "mode" "QI")])

(define_insn "*movsi_insv_1_rex64"
  [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
                         (const_int 8)
                         (const_int 8))
        (match_operand:SI 1 "nonmemory_operand" "Qn"))]
  "TARGET_64BIT"
  "mov{b}\t{%b1, %h0|%h0, %b1}"
  [(set_attr "type" "imov")
   (set_attr "mode" "QI")])

(define_insn "movdi_insv_1_rex64"
  [(set (zero_extract:DI (match_operand 0 "ext_register_operand" "+Q")
                         (const_int 8)
                         (const_int 8))
        (match_operand:DI 1 "nonmemory_operand" "Qn"))]
  "TARGET_64BIT"
  "mov{b}\t{%b1, %h0|%h0, %b1}"
  [(set_attr "type" "imov")
   (set_attr "mode" "QI")])

(define_insn "*movqi_insv_2"
  [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
                         (const_int 8)
                         (const_int 8))
        (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
                     (const_int 8)))]
  ""
  "mov{b}\t{%h1, %h0|%h0, %h1}"
  [(set_attr "type" "imov")
   (set_attr "mode" "QI")])

(define_expand "movdi"
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
        (match_operand:DI 1 "general_operand" ""))]
  ""
  "ix86_expand_move (DImode, operands); DONE;")

(define_insn "*pushdi"
  [(set (match_operand:DI 0 "push_operand" "=<")
        (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
  "!TARGET_64BIT"
  "#")

(define_insn "*pushdi2_rex64"
  [(set (match_operand:DI 0 "push_operand" "=<,!<")
        (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
  "TARGET_64BIT"
  "@
   push{q}\t%1
   #"
  [(set_attr "type" "push,multi")
   (set_attr "mode" "DI")])

;; Convert impossible pushes of immediate to existing instructions.
;; First try to get scratch register and go through it.  In case this
;; fails, push sign extended lower part first and then overwrite
;; upper part by 32bit move.
(define_peephole2
  [(match_scratch:DI 2 "r")
   (set (match_operand:DI 0 "push_operand" "")
        (match_operand:DI 1 "immediate_operand" ""))]
  "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
   && !x86_64_immediate_operand (operands[1], DImode)"
  [(set (match_dup 2) (match_dup 1))
   (set (match_dup 0) (match_dup 2))]
  "")

;; We need to define this as both peepholer and splitter for case
;; peephole2 pass is not run.
;; "&& 1" is needed to keep it from matching the previous pattern.
(define_peephole2
  [(set (match_operand:DI 0 "push_operand" "")
        (match_operand:DI 1 "immediate_operand" ""))]
  "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
   && !x86_64_immediate_operand (operands[1], DImode) && 1"
  [(set (match_dup 0) (match_dup 1))
   (set (match_dup 2) (match_dup 3))]
  "split_di (operands + 1, 1, operands + 2, operands + 3);
   operands[1] = gen_lowpart (DImode, operands[2]);
   operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
                                                    GEN_INT (4)));
  ")

(define_split
  [(set (match_operand:DI 0 "push_operand" "")
        (match_operand:DI 1 "immediate_operand" ""))]
  "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
                    ? epilogue_completed : reload_completed)
   && !symbolic_operand (operands[1], DImode)
   && !x86_64_immediate_operand (operands[1], DImode)"
  [(set (match_dup 0) (match_dup 1))
   (set (match_dup 2) (match_dup 3))]
  "split_di (operands + 1, 1, operands + 2, operands + 3);
   operands[1] = gen_lowpart (DImode, operands[2]);
   operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
                                                    GEN_INT (4)));
  ")

(define_insn "*pushdi2_prologue_rex64"
  [(set (match_operand:DI 0 "push_operand" "=<")
        (match_operand:DI 1 "general_no_elim_operand" "re*m"))
   (clobber (mem:BLK (scratch)))]
  "TARGET_64BIT"
  "push{q}\t%1"
  [(set_attr "type" "push")
   (set_attr "mode" "DI")])

(define_insn "*popdi1_epilogue_rex64"
  [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
        (mem:DI (reg:DI SP_REG)))
   (set (reg:DI SP_REG)
        (plus:DI (reg:DI SP_REG) (const_int 8)))
   (clobber (mem:BLK (scratch)))]
  "TARGET_64BIT"
  "pop{q}\t%0"
  [(set_attr "type" "pop")
   (set_attr "mode" "DI")])

(define_insn "popdi1"
  [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
        (mem:DI (reg:DI SP_REG)))
   (set (reg:DI SP_REG)
        (plus:DI (reg:DI SP_REG) (const_int 8)))]
  "TARGET_64BIT"
  "pop{q}\t%0"
  [(set_attr "type" "pop")
   (set_attr "mode" "DI")])

(define_insn "*movdi_xor_rex64"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (match_operand:DI 1 "const0_operand" "i"))
   (clobber (reg:CC FLAGS_REG))]
  "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
   && reload_completed"
  "xor{l}\t%k0, %k0";
  [(set_attr "type" "alu1")
   (set_attr "mode" "SI")
   (set_attr "length_immediate" "0")])

(define_insn "*movdi_or_rex64"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (match_operand:DI 1 "const_int_operand" "i"))
   (clobber (reg:CC FLAGS_REG))]
  "TARGET_64BIT && (TARGET_MOVE_M1_VIA_OR || optimize_size)
   && reload_completed
   && operands[1] == constm1_rtx"
{
  operands[1] = constm1_rtx;
  return "or{q}\t{%1, %0|%0, %1}";
}
  [(set_attr "type" "alu1")
   (set_attr "mode" "DI")
   (set_attr "length_immediate" "1")])

(define_insn "*movdi_2"
  [(set (match_operand:DI 0 "nonimmediate_operand"
                        "=r  ,o  ,*y,m*y,*y,*Y2,m  ,*Y2,*Y2,*x,m ,*x,*x")
        (match_operand:DI 1 "general_operand"
                        "riFo,riF,C ,*y ,m ,C  ,*Y2,*Y2,m  ,C ,*x,*x,m "))]
  "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  "@
   #
   #
   pxor\t%0, %0
   movq\t{%1, %0|%0, %1}
   movq\t{%1, %0|%0, %1}
   pxor\t%0, %0
   movq\t{%1, %0|%0, %1}
   movdqa\t{%1, %0|%0, %1}
   movq\t{%1, %0|%0, %1}
   xorps\t%0, %0
   movlps\t{%1, %0|%0, %1}
   movaps\t{%1, %0|%0, %1}
   movlps\t{%1, %0|%0, %1}"
  [(set_attr "type" "*,*,mmx,mmxmov,mmxmov,sselog1,ssemov,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov")
   (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF")])

(define_split
  [(set (match_operand:DI 0 "push_operand" "")
        (match_operand:DI 1 "general_operand" ""))]
  "!TARGET_64BIT && reload_completed
   && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
  [(const_int 0)]
  "ix86_split_long_move (operands); DONE;")

;; %%% This multiword shite has got to go.
(define_split
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
        (match_operand:DI 1 "general_operand" ""))]
  "!TARGET_64BIT && reload_completed
   && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
   && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
  [(const_int 0)]
  "ix86_split_long_move (operands); DONE;")

(define_insn "*movdi_1_rex64"
  [(set (match_operand:DI 0 "nonimmediate_operand"
          "=r,r  ,r,m ,!m,*y,*y,?r ,m ,?*Ym,?*y,*x,*x,?r ,m,?*Yi,*x,?*x,?*Ym")
        (match_operand:DI 1 "general_operand"
          "Z ,rem,i,re,n ,C ,*y,*Ym,*y,r   ,m  ,C ,*x,*Yi,*x,r  ,m ,*Ym,*x"))]
  "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
  switch (get_attr_type (insn))
    {
    case TYPE_SSECVT:
      if (SSE_REG_P (operands[0]))
        return "movq2dq\t{%1, %0|%0, %1}";
      else
        return "movdq2q\t{%1, %0|%0, %1}";

    case TYPE_SSEMOV:
      if (get_attr_mode (insn) == MODE_TI)
        return "movdqa\t{%1, %0|%0, %1}";
      /* FALLTHRU */

    case TYPE_MMXMOV:
      /* Moves from and into integer register is done using movd
         opcode with REX prefix.  */
      if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
        return "movd\t{%1, %0|%0, %1}";
      return "movq\t{%1, %0|%0, %1}";

    case TYPE_SSELOG1:
    case TYPE_MMXADD:
      return "pxor\t%0, %0";

    case TYPE_MULTI:
      return "#";

    case TYPE_LEA:
      return "lea{q}\t{%a1, %0|%0, %a1}";

    default:
      gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
      if (get_attr_mode (insn) == MODE_SI)
        return "mov{l}\t{%k1, %k0|%k0, %k1}";
      else if (which_alternative == 2)
        return "movabs{q}\t{%1, %0|%0, %1}";
      else
        return "mov{q}\t{%1, %0|%0, %1}";
    }
}
  [(set (attr "type")
     (cond [(eq_attr "alternative" "5")
              (const_string "mmxadd")
            (eq_attr "alternative" "6,7,8,9,10")
              (const_string "mmxmov")
            (eq_attr "alternative" "11")
              (const_string "sselog1")
            (eq_attr "alternative" "12,13,14,15,16")
              (const_string "ssemov")
            (eq_attr "alternative" "17,18")
              (const_string "ssecvt")
            (eq_attr "alternative" "4")
              (const_string "multi")
            (match_operand:DI 1 "pic_32bit_operand" "")
              (const_string "lea")
           ]
           (const_string "imov")))
   (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")
   (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")
   (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,DI,DI,DI,TI,TI,DI,DI,DI,DI,DI,DI")])

;; Stores and loads of ax to arbitrary constant address.
;; We fake an second form of instruction to force reload to load address
;; into register when rax is not available
(define_insn "*movabsdi_1_rex64"
  [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
        (match_operand:DI 1 "nonmemory_operand" "a,er"))]
  "TARGET_64BIT && ix86_check_movabs (insn, 0)"
  "@
   movabs{q}\t{%1, %P0|%P0, %1}
   mov{q}\t{%1, %a0|%a0, %1}"
  [(set_attr "type" "imov")
   (set_attr "modrm" "0,*")
   (set_attr "length_address" "8,0")
   (set_attr "length_immediate" "0,*")
   (set_attr "memory" "store")
   (set_attr "mode" "DI")])

(define_insn "*movabsdi_2_rex64"
  [(set (match_operand:DI 0 "register_operand" "=a,r")
        (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
  "TARGET_64BIT && ix86_check_movabs (insn, 1)"
  "@
   movabs{q}\t{%P1, %0|%0, %P1}
   mov{q}\t{%a1, %0|%0, %a1}"
  [(set_attr "type" "imov")
   (set_attr "modrm" "0,*")
   (set_attr "length_address" "8,0")
   (set_attr "length_immediate" "0")
   (set_attr "memory" "load")
   (set_attr "mode" "DI")])

;; Convert impossible stores of immediate to existing instructions.
;; First try to get scratch register and go through it.  In case this
;; fails, move by 32bit parts.
(define_peephole2
  [(match_scratch:DI 2 "r")
   (set (match_operand:DI 0 "memory_operand" "")
        (match_operand:DI 1 "immediate_operand" ""))]
  "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
   && !x86_64_immediate_operand (operands[1], DImode)"
  [(set (match_dup 2) (match_dup 1))
   (set (match_dup 0) (match_dup 2))]
  "")

;; We need to define this as both peepholer and splitter for case
;; peephole2 pass is not run.
;; "&& 1" is needed to keep it from matching the previous pattern.
(define_peephole2
  [(set (match_operand:DI 0 "memory_operand" "")
        (match_operand:DI 1 "immediate_operand" ""))]
  "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
   && !x86_64_immediate_operand (operands[1], DImode) && 1"
  [(set (match_dup 2) (match_dup 3))
   (set (match_dup 4) (match_dup 5))]
  "split_di (operands, 2, operands + 2, operands + 4);")

(define_split
  [(set (match_operand:DI 0 "memory_operand" "")
        (match_operand:DI 1 "immediate_operand" ""))]
  "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
                    ? epilogue_completed : reload_completed)
   && !symbolic_operand (operands[1], DImode)
   && !x86_64_immediate_operand (operands[1], DImode)"
  [(set (match_dup 2) (match_dup 3))
   (set (match_dup 4) (match_dup 5))]
  "split_di (operands, 2, operands + 2, operands + 4);")

(define_insn "*swapdi_rex64"
  [(set (match_operand:DI 0 "register_operand" "+r")
        (match_operand:DI 1 "register_operand" "+r"))
   (set (match_dup 1)
        (match_dup 0))]
  "TARGET_64BIT"
  "xchg{q}\t%1, %0"
  [(set_attr "type" "imov")
   (set_attr "mode" "DI")
   (set_attr "pent_pair" "np")
   (set_attr "athlon_decode" "vector")
   (set_attr "amdfam10_decode" "double")])

(define_expand "movti"
  [(set (match_operand:TI 0 "nonimmediate_operand" "")
        (match_operand:TI 1 "nonimmediate_operand" ""))]
  "TARGET_SSE || TARGET_64BIT"
{
  if (TARGET_64BIT)
    ix86_expand_move (TImode, operands);
  else if (push_operand (operands[0], TImode))
    ix86_expand_push (TImode, operands[1]);
  else
    ix86_expand_vector_move (TImode, operands);
  DONE;
})

(define_insn "*movti_internal"
  [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
        (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
  "TARGET_SSE && !TARGET_64BIT
   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
  switch (which_alternative)
    {
    case 0:
      if (get_attr_mode (insn) == MODE_V4SF)
        return "xorps\t%0, %0";
      else
        return "pxor\t%0, %0";
    case 1:
    case 2:
      /* TDmode values are passed as TImode on the stack.  Moving them
         to stack may result in unaligned memory access.  */
      if (misaligned_operand (operands[0], TImode)
          || misaligned_operand (operands[1], TImode))
        { 
          if (get_attr_mode (insn) == MODE_V4SF)
            return "movups\t{%1, %0|%0, %1}";
         else
           return "movdqu\t{%1, %0|%0, %1}";
        }
      else
        { 
          if (get_attr_mode (insn) == MODE_V4SF)
            return "movaps\t{%1, %0|%0, %1}";
         else
           return "movdqa\t{%1, %0|%0, %1}";
        }
    default:
      gcc_unreachable ();
    }
}
  [(set_attr "type" "sselog1,ssemov,ssemov")
   (set (attr "mode")
        (cond [(ior (eq (symbol_ref "TARGET_SSE2") (const_int 0))
                    (ne (symbol_ref "optimize_size") (const_int 0)))
                 (const_string "V4SF")
               (and (eq_attr "alternative" "2")
                    (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
                        (const_int 0)))
                 (const_string "V4SF")]
              (const_string "TI")))])

(define_insn "*movti_rex64"
  [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
        (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
  "TARGET_64BIT
   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
  switch (which_alternative)
    {
    case 0:
    case 1:
      return "#";
    case 2:
      if (get_attr_mode (insn) == MODE_V4SF)
        return "xorps\t%0, %0";
      else
        return "pxor\t%0, %0";
    case 3:
    case 4:
      /* TDmode values are passed as TImode on the stack.  Moving them
         to stack may result in unaligned memory access.  */
      if (misaligned_operand (operands[0], TImode)
          || misaligned_operand (operands[1], TImode))
        { 
          if (get_attr_mode (insn) == MODE_V4SF)
            return "movups\t{%1, %0|%0, %1}";
         else
           return "movdqu\t{%1, %0|%0, %1}";
        }
      else
        { 
          if (get_attr_mode (insn) == MODE_V4SF)
            return "movaps\t{%1, %0|%0, %1}";
         else
           return "movdqa\t{%1, %0|%0, %1}";
        }
    default:
      gcc_unreachable ();
    }
}
  [(set_attr "type" "*,*,sselog1,ssemov,ssemov")
   (set (attr "mode")
        (cond [(eq_attr "alternative" "2,3")
                 (if_then_else
                   (ne (symbol_ref "optimize_size")
                       (const_int 0))
                   (const_string "V4SF")
                   (const_string "TI"))
               (eq_attr "alternative" "4")
                 (if_then_else
                   (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
                            (const_int 0))
                        (ne (symbol_ref "optimize_size")
                            (const_int 0)))
                   (const_string "V4SF")
                   (const_string "TI"))]
               (const_string "DI")))])

(define_split
  [(set (match_operand:TI 0 "nonimmediate_operand" "")
        (match_operand:TI 1 "general_operand" ""))]
  "reload_completed && !SSE_REG_P (operands[0])
   && !SSE_REG_P (operands[1])"
  [(const_int 0)]
  "ix86_split_long_move (operands); DONE;")

;; This expands to what emit_move_complex would generate if we didn't
;; have a movti pattern.  Having this avoids problems with reload on
;; 32-bit targets when SSE is present, but doesn't seem to be harmful
;; to have around all the time.
(define_expand "movcdi"
  [(set (match_operand:CDI 0 "nonimmediate_operand" "")
        (match_operand:CDI 1 "general_operand" ""))]
  ""
{
  if (push_operand (operands[0], CDImode))
    emit_move_complex_push (CDImode, operands[0], operands[1]);
  else
    emit_move_complex_parts (operands[0], operands[1]);
  DONE;
})

(define_expand "movsf"
  [(set (match_operand:SF 0 "nonimmediate_operand" "")
        (match_operand:SF 1 "general_operand" ""))]
  ""
  "ix86_expand_move (SFmode, operands); DONE;")

(define_insn "*pushsf"
  [(set (match_operand:SF 0 "push_operand" "=<,<,<")
        (match_operand:SF 1 "general_no_elim_operand" "f,rFm,x"))]
  "!TARGET_64BIT"
{
  /* Anything else should be already split before reg-stack.  */
  gcc_assert (which_alternative == 1);
  return "push{l}\t%1";
}
  [(set_attr "type" "multi,push,multi")
   (set_attr "unit" "i387,*,*")
   (set_attr "mode" "SF,SI,SF")])

(define_insn "*pushsf_rex64"
  [(set (match_operand:SF 0 "push_operand" "=X,X,X")
        (match_operand:SF 1 "nonmemory_no_elim_operand" "f,rF,x"))]
  "TARGET_64BIT"
{
  /* Anything else should be already split before reg-stack.  */
  gcc_assert (which_alternative == 1);
  return "push{q}\t%q1";
}
  [(set_attr "type" "multi,push,multi")
   (set_attr "unit" "i387,*,*")
   (set_attr "mode" "SF,DI,SF")])

(define_split
  [(set (match_operand:SF 0 "push_operand" "")
        (match_operand:SF 1 "memory_operand" ""))]
  "reload_completed
   && MEM_P (operands[1])
   && (operands[2] = find_constant_src (insn))"
  [(set (match_dup 0)
        (match_dup 2))])


;; %%% Kill this when call knows how to work this out.
(define_split
  [(set (match_operand:SF 0 "push_operand" "")
        (match_operand:SF 1 "any_fp_register_operand" ""))]
  "!TARGET_64BIT"
  [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
   (set (mem:SF (reg:SI SP_REG)) (match_dup 1))])

(define_split
  [(set (match_operand:SF 0 "push_operand" "")
        (match_operand:SF 1 "any_fp_register_operand" ""))]
  "TARGET_64BIT"
  [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
   (set (mem:SF (reg:DI SP_REG)) (match_dup 1))])

(define_insn "*movsf_1"
  [(set (match_operand:SF 0 "nonimmediate_operand"
          "=f,m,f,r  ,m ,x,x,x ,m,!*y,!m,!*y,?Yi,?r,!*Ym,!r")
        (match_operand:SF 1 "general_operand"
          "fm,f,G,rmF,Fr,C,x,xm,x,m  ,*y,*y ,r  ,Yi,r   ,*Ym"))]
  "!(MEM_P (operands[0]) && MEM_P (operands[1]))
   && (reload_in_progress || reload_completed
       || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
       || (!TARGET_SSE_MATH && optimize_size
           && standard_80387_constant_p (operands[1]))
       || GET_CODE (operands[1]) != CONST_DOUBLE
       || memory_operand (operands[0], SFmode))"
{
  switch (which_alternative)
    {
    case 0:
    case 1:
      return output_387_reg_move (insn, operands);

    case 2:
      return standard_80387_constant_opcode (operands[1]);

    case 3:
    case 4:
      return "mov{l}\t{%1, %0|%0, %1}";
    case 5:
      if (get_attr_mode (insn) == MODE_TI)
        return "pxor\t%0, %0";
      else
        return "xorps\t%0, %0";
    case 6:
      if (get_attr_mode (insn) == MODE_V4SF)
        return "movaps\t{%1, %0|%0, %1}";
      else
        return "movss\t{%1, %0|%0, %1}";
    case 7: case 8:
      return "movss\t{%1, %0|%0, %1}";

    case 9: case 10:
    case 12: case 13: case 14: case 15:
      return "movd\t{%1, %0|%0, %1}";

    case 11:
      return "movq\t{%1, %0|%0, %1}";

    default:
      gcc_unreachable ();
    }
}
  [(set_attr "type" "fmov,fmov,fmov,imov,imov,sselog1,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov,ssemov,ssemov,mmxmov,mmxmov")
   (set (attr "mode")
        (cond [(eq_attr "alternative" "3,4,9,10")
                 (const_string "SI")
               (eq_attr "alternative" "5")
                 (if_then_else
                   (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
                                 (const_int 0))
                             (ne (symbol_ref "TARGET_SSE2")
                                 (const_int 0)))
                        (eq (symbol_ref "optimize_size")
                            (const_int 0)))
                   (const_string "TI")
                   (const_string "V4SF"))
               /* For architectures resolving dependencies on
                  whole SSE registers use APS move to break dependency
                  chains, otherwise use short move to avoid extra work.

                  Do the same for architectures resolving dependencies on
                  the parts.  While in DF mode it is better to always handle
                  just register parts, the SF mode is different due to lack
                  of instructions to load just part of the register.  It is
                  better to maintain the whole registers in single format
                  to avoid problems on using packed logical operations.  */
               (eq_attr "alternative" "6")
                 (if_then_else
                   (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
                            (const_int 0))
                        (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
                            (const_int 0)))
                   (const_string "V4SF")
                   (const_string "SF"))
               (eq_attr "alternative" "11")
                 (const_string "DI")]
               (const_string "SF")))])

(define_insn "*swapsf"
  [(set (match_operand:SF 0 "fp_register_operand" "+f")
        (match_operand:SF 1 "fp_register_operand" "+f"))
   (set (match_dup 1)
        (match_dup 0))]
  "reload_completed || TARGET_80387"
{
  if (STACK_TOP_P (operands[0]))
    return "fxch\t%1";
  else
    return "fxch\t%0";
}
  [(set_attr "type" "fxch")
   (set_attr "mode" "SF")])

(define_expand "movdf"
  [(set (match_operand:DF 0 "nonimmediate_operand" "")
        (match_operand:DF 1 "general_operand" ""))]
  ""
  "ix86_expand_move (DFmode, operands); DONE;")

;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
;; Size of pushdf using integer instructions is 2+2*memory operand size
;; On the average, pushdf using integers can be still shorter.  Allow this
;; pattern for optimize_size too.

(define_insn "*pushdf_nointeger"
  [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
        (match_operand:DF 1 "general_no_elim_operand" "f,Fo,*r,Y2"))]
  "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
{
  /* This insn should be already split before reg-stack.  */
  gcc_unreachable ();
}
  [(set_attr "type" "multi")
   (set_attr "unit" "i387,*,*,*")
   (set_attr "mode" "DF,SI,SI,DF")])

(define_insn "*pushdf_integer"
  [(set (match_operand:DF 0 "push_operand" "=<,<,<")
        (match_operand:DF 1 "general_no_elim_operand" "f,rFo,Y2"))]
  "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
{
  /* This insn should be already split before reg-stack.  */
  gcc_unreachable ();
}
  [(set_attr "type" "multi")
   (set_attr "unit" "i387,*,*")
   (set_attr "mode" "DF,SI,DF")])

;; %%% Kill this when call knows how to work this out.
(define_split
  [(set (match_operand:DF 0 "push_operand" "")
        (match_operand:DF 1 "any_fp_register_operand" ""))]
  "!TARGET_64BIT && reload_completed"
  [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
   (set (mem:DF (reg:SI SP_REG)) (match_dup 1))]
  "")

(define_split
  [(set (match_operand:DF 0 "push_operand" "")
        (match_operand:DF 1 "any_fp_register_operand" ""))]
  "TARGET_64BIT && reload_completed"
  [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
   (set (mem:DF (reg:DI SP_REG)) (match_dup 1))]
  "")

(define_split
  [(set (match_operand:DF 0 "push_operand" "")
        (match_operand:DF 1 "general_operand" ""))]
  "reload_completed"
  [(const_int 0)]
  "ix86_split_long_move (operands); DONE;")

;; Moving is usually shorter when only FP registers are used. This separate
;; movdf pattern avoids the use of integer registers for FP operations
;; when optimizing for size.

(define_insn "*movdf_nointeger"
  [(set (match_operand:DF 0 "nonimmediate_operand"
                        "=f,m,f,*r  ,o  ,Y2*x,Y2*x,Y2*x ,m  ")
        (match_operand:DF 1 "general_operand"
                        "fm,f,G,*roF,*Fr,C   ,Y2*x,mY2*x,Y2*x"))]
  "!(MEM_P (operands[0]) && MEM_P (operands[1]))
   && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
   && (reload_in_progress || reload_completed
       || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
       || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
           && !memory_operand (operands[0], DFmode)
           && standard_80387_constant_p (operands[1]))
       || GET_CODE (operands[1]) != CONST_DOUBLE
       || ((optimize_size
            || !TARGET_MEMORY_MISMATCH_STALL
            || reload_in_progress || reload_completed)
           && memory_operand (operands[0], DFmode)))"
{
  switch (which_alternative)
    {
    case 0:
    case 1:
      return output_387_reg_move (insn, operands);

    case 2:
      return standard_80387_constant_opcode (operands[1]);

    case 3:
    case 4:
      return "#";
    case 5:
      switch (get_attr_mode (insn))
        {
        case MODE_V4SF:
          return "xorps\t%0, %0";
        case MODE_V2DF:
          return "xorpd\t%0, %0";
        case MODE_TI:
          return "pxor\t%0, %0";
        default:
          gcc_unreachable ();
        }
    case 6:
    case 7:
    case 8:
      switch (get_attr_mode (insn))
        {
        case MODE_V4SF:
          return "movaps\t{%1, %0|%0, %1}";
        case MODE_V2DF:
          return "movapd\t{%1, %0|%0, %1}";
        case MODE_TI:
          return "movdqa\t{%1, %0|%0, %1}";
        case MODE_DI:
          return "movq\t{%1, %0|%0, %1}";
        case MODE_DF:
          return "movsd\t{%1, %0|%0, %1}";
        case MODE_V1DF:
          return "movlpd\t{%1, %0|%0, %1}";
        case MODE_V2SF:
          return "movlps\t{%1, %0|%0, %1}";
        default:
          gcc_unreachable ();
        }

    default:
      gcc_unreachable ();
    }
}
  [(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
   (set (attr "mode")
        (cond [(eq_attr "alternative" "0,1,2")
                 (const_string "DF")
               (eq_attr "alternative" "3,4")
                 (const_string "SI")

               /* For SSE1, we have many fewer alternatives.  */
               (eq (symbol_ref "TARGET_SSE2") (const_int 0))
                 (cond [(eq_attr "alternative" "5,6")
                          (const_string "V4SF")
                       ]
                   (const_string "V2SF"))

               /* xorps is one byte shorter.  */
               (eq_attr "alternative" "5")
                 (cond [(ne (symbol_ref "optimize_size")
                            (const_int 0))
                          (const_string "V4SF")
                        (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
                            (const_int 0))
                          (const_string "TI")
                       ]
                       (const_string "V2DF"))

               /* For architectures resolving dependencies on
                  whole SSE registers use APD move to break dependency
                  chains, otherwise use short move to avoid extra work.

                  movaps encodes one byte shorter.  */
               (eq_attr "alternative" "6")
                 (cond
                   [(ne (symbol_ref "optimize_size")
                        (const_int 0))
                      (const_string "V4SF")
                    (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
                        (const_int 0))
                      (const_string "V2DF")
                   ]
                   (const_string "DF"))
               /* For architectures resolving dependencies on register
                  parts we may avoid extra work to zero out upper part
                  of register.  */
               (eq_attr "alternative" "7")
                 (if_then_else
                   (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
                       (const_int 0))
                   (const_string "V1DF")
                   (const_string "DF"))
              ]
              (const_string "DF")))])

(define_insn "*movdf_integer_rex64"
  [(set (match_operand:DF 0 "nonimmediate_operand"
                "=f,m,f,r  ,m ,Y2*x,Y2*x,Y2*x,m   ,Yi,r ")
        (match_operand:DF 1 "general_operand"
                "fm,f,G,rmF,Fr,C   ,Y2*x,m   ,Y2*x,r ,Yi"))]
  "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
   && (reload_in_progress || reload_completed
       || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
       || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
           && standard_80387_constant_p (operands[1]))
       || GET_CODE (operands[1]) != CONST_DOUBLE
       || memory_operand (operands[0], DFmode))"
{
  switch (which_alternative)
    {
    case 0:
    case 1:
      return output_387_reg_move (insn, operands);

    case 2:
      return standard_80387_constant_opcode (operands[1]);

    case 3:
    case 4:
      return "#";

    case 5:
      switch (get_attr_mode (insn))
        {
        case MODE_V4SF:
          return "xorps\t%0, %0";
        case MODE_V2DF:
          return "xorpd\t%0, %0";
        case MODE_TI:
          return "pxor\t%0, %0";
        default:
          gcc_unreachable ();
        }
    case 6:
    case 7:
    case 8:
      switch (get_attr_mode (insn))
        {
        case MODE_V4SF:
          return "movaps\t{%1, %0|%0, %1}";
        case MODE_V2DF:
          return "movapd\t{%1, %0|%0, %1}";
        case MODE_TI:
          return "movdqa\t{%1, %0|%0, %1}";
        case MODE_DI:
          return "movq\t{%1, %0|%0, %1}";
        case MODE_DF:
          return "movsd\t{%1, %0|%0, %1}";
        case MODE_V1DF:
          return "movlpd\t{%1, %0|%0, %1}";
        case MODE_V2SF:
          return "movlps\t{%1, %0|%0, %1}";
        default:
          gcc_unreachable ();
        }

    case 9:
    case 10:
      return "movd\t{%1, %0|%0, %1}";

    default:
      gcc_unreachable();
    }
}
  [(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov,ssemov,ssemov")
   (set (attr "mode")
        (cond [(eq_attr "alternative" "0,1,2")
                 (const_string "DF")
               (eq_attr "alternative" "3,4,9,10")
                 (const_string "DI")

               /* For SSE1, we have many fewer alternatives.  */
               (eq (symbol_ref "TARGET_SSE2") (const_int 0))
                 (cond [(eq_attr "alternative" "5,6")
                          (const_string "V4SF")
                       ]
                   (const_string "V2SF"))

               /* xorps is one byte shorter.  */
               (eq_attr "alternative" "5")
                 (cond [(ne (symbol_ref "optimize_size")
                            (const_int 0))
                          (const_string "V4SF")
                        (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
                            (const_int 0))
                          (const_string "TI")
                       ]
                       (const_string "V2DF"))

               /* For architectures resolving dependencies on
                  whole SSE registers use APD move to break dependency
                  chains, otherwise use short move to avoid extra work.

                  movaps encodes one byte shorter.  */
               (eq_attr "alternative" "6")
                 (cond
                   [(ne (symbol_ref "optimize_size")
                        (const_int 0))
                      (const_string "V4SF")
                    (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
                        (const_int 0))
                      (const_string "V2DF")
                   ]
                   (const_string "DF"))
               /* For architectures resolving dependencies on register
                  parts we may avoid extra work to zero out upper part
                  of register.  */
               (eq_attr "alternative" "7")
                 (if_then_else
                   (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
                       (const_int 0))
                   (const_string "V1DF")
                   (const_string "DF"))
              ]
              (const_string "DF")))])

(define_insn "*movdf_integer"
  [(set (match_operand:DF 0 "nonimmediate_operand"
                "=f,m,f,r  ,o ,Y2*x,Y2*x,Y2*x,m   ")
        (match_operand:DF 1 "general_operand"
                "fm,f,G,roF,Fr,C   ,Y2*x,m   ,Y2*x"))]
  "!(MEM_P (operands[0]) && MEM_P (operands[1]))
   && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
   && (reload_in_progress || reload_completed
       || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
       || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
           && standard_80387_constant_p (operands[1]))
       || GET_CODE (operands[1]) != CONST_DOUBLE
       || memory_operand (operands[0], DFmode))"
{
  switch (which_alternative)
    {
    case 0:
    case 1:
      return output_387_reg_move (insn, operands);

    case 2:
      return standard_80387_constant_opcode (operands[1]);

    case 3:
    case 4:
      return "#";

    case 5:
      switch (get_attr_mode (insn))
        {
        case MODE_V4SF:
          return "xorps\t%0, %0";
        case MODE_V2DF:
          return "xorpd\t%0, %0";
        case MODE_TI:
          return "pxor\t%0, %0";
        default:
          gcc_unreachable ();
        }
    case 6:
    case 7:
    case 8:
      switch (get_attr_mode (insn))
        {
        case MODE_V4SF:
          return "movaps\t{%1, %0|%0, %1}";
        case MODE_V2DF:
          return "movapd\t{%1, %0|%0, %1}";
        case MODE_TI:
          return "movdqa\t{%1, %0|%0, %1}";
        case MODE_DI:
          return "movq\t{%1, %0|%0, %1}";
        case MODE_DF:
          return "movsd\t{%1, %0|%0, %1}";
        case MODE_V1DF:
          return "movlpd\t{%1, %0|%0, %1}";
        case MODE_V2SF:
          return "movlps\t{%1, %0|%0, %1}";
        default:
          gcc_unreachable ();
        }

    default:
      gcc_unreachable();
    }
}
  [(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
   (set (attr "mode")
        (cond [(eq_attr "alternative" "0,1,2")
                 (const_string "DF")
               (eq_attr "alternative" "3,4")
                 (const_string "SI")

               /* For SSE1, we have many fewer alternatives.  */
               (eq (symbol_ref "TARGET_SSE2") (const_int 0))
                 (cond [(eq_attr "alternative" "5,6")
                          (const_string "V4SF")
                       ]
                   (const_string "V2SF"))

               /* xorps is one byte shorter.  */
               (eq_attr "alternative" "5")
                 (cond [(ne (symbol_ref "optimize_size")
                            (const_int 0))
                          (const_string "V4SF")
                        (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
                            (const_int 0))
                          (const_string "TI")
                       ]
                       (const_string "V2DF"))

               /* For architectures resolving dependencies on
                  whole SSE registers use APD move to break dependency
                  chains, otherwise use short move to avoid extra work.

                  movaps encodes one byte shorter.  */
               (eq_attr "alternative" "6")
                 (cond
                   [(ne (symbol_ref "optimize_size")
                        (const_int 0))
                      (const_string "V4SF")
                    (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
                        (const_int 0))
                      (const_string "V2DF")
                   ]
                   (const_string "DF"))
               /* For architectures resolving dependencies on register
                  parts we may avoid extra work to zero out upper part
                  of register.  */
               (eq_attr "alternative" "7")
                 (if_then_else
                   (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
                       (const_int 0))
                   (const_string "V1DF")
                   (const_string "DF"))
              ]
              (const_string "DF")))])

(define_split
  [(set (match_operand:DF 0 "nonimmediate_operand" "")
        (match_operand:DF 1 "general_operand" ""))]
  "reload_completed
   && !(MEM_P (operands[0]) && MEM_P (operands[1]))
   && ! (ANY_FP_REG_P (operands[0]) ||
         (GET_CODE (operands[0]) == SUBREG
          && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
   && ! (ANY_FP_REG_P (operands[1]) ||
         (GET_CODE (operands[1]) == SUBREG
          && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
  [(const_int 0)]
  "ix86_split_long_move (operands); DONE;")

(define_insn "*swapdf"
  [(set (match_operand:DF 0 "fp_register_operand" "+f")
        (match_operand:DF 1 "fp_register_operand" "+f"))
   (set (match_dup 1)
        (match_dup 0))]
  "reload_completed || TARGET_80387"
{
  if (STACK_TOP_P (operands[0]))
    return "fxch\t%1";
  else
    return "fxch\t%0";
}
  [(set_attr "type" "fxch")
   (set_attr "mode" "DF")])

(define_expand "movxf"
  [(set (match_operand:XF 0 "nonimmediate_operand" "")
        (match_operand:XF 1 "general_operand" ""))]
  ""
  "ix86_expand_move (XFmode, operands); DONE;")

;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
;; Size of pushdf using integer instructions is 3+3*memory operand size
;; Pushing using integer instructions is longer except for constants
;; and direct memory references.
;; (assuming that any given constant is pushed only once, but this ought to be
;;  handled elsewhere).

(define_insn "*pushxf_nointeger"
  [(set (match_operand:XF 0 "push_operand" "=X,X,X")
        (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
  "optimize_size"
{
  /* This insn should be already split before reg-stack.  */
  gcc_unreachable ();
}
  [(set_attr "type" "multi")
   (set_attr "unit" "i387,*,*")
   (set_attr "mode" "XF,SI,SI")])

(define_insn "*pushxf_integer"
  [(set (match_operand:XF 0 "push_operand" "=<,<")
        (match_operand:XF 1 "general_no_elim_operand" "f,ro"))]
  "!optimize_size"
{
  /* This insn should be already split before reg-stack.  */
  gcc_unreachable ();
}
  [(set_attr "type" "multi")
   (set_attr "unit" "i387,*")
   (set_attr "mode" "XF,SI")])

(define_split
  [(set (match_operand 0 "push_operand" "")
        (match_operand 1 "general_operand" ""))]
  "reload_completed
   && (GET_MODE (operands[0]) == XFmode
       || GET_MODE (operands[0]) == DFmode)
   && !ANY_FP_REG_P (operands[1])"
  [(const_int 0)]
  "ix86_split_long_move (operands); DONE;")

(define_split
  [(set (match_operand:XF 0 "push_operand" "")
        (match_operand:XF 1 "any_fp_register_operand" ""))]
  "!TARGET_64BIT"
  [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
   (set (mem:XF (reg:SI SP_REG)) (match_dup 1))]
  "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")

(define_split
  [(set (match_operand:XF 0 "push_operand" "")
        (match_operand:XF 1 "any_fp_register_operand" ""))]
  "TARGET_64BIT"
  [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
   (set (mem:XF (reg:DI SP_REG)) (match_dup 1))]
  "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")

;; Do not use integer registers when optimizing for size
(define_insn "*movxf_nointeger"
  [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
        (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
  "optimize_size
   && !(MEM_P (operands[0]) && MEM_P (operands[1]))
   && (reload_in_progress || reload_completed
       || (optimize_size && standard_80387_constant_p (operands[1]))
       || GET_CODE (operands[1]) != CONST_DOUBLE
       || memory_operand (operands[0], XFmode))"
{
  switch (which_alternative)
    {
    case 0:
    case 1:
      return output_387_reg_move (insn, operands);

    case 2:
      return standard_80387_constant_opcode (operands[1]);

    case 3: case 4:
      return "#";
    default:
      gcc_unreachable ();
    }
}
  [(set_attr "type" "fmov,fmov,fmov,multi,multi")
   (set_attr "mode" "XF,XF,XF,SI,SI")])

(define_insn "*movxf_integer"
  [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,r,o")
        (match_operand:XF 1 "general_operand" "fm,f,G,roF,Fr"))]
  "!optimize_size
   && !(MEM_P (operands[0]) && MEM_P (operands[1]))
   && (reload_in_progress || reload_completed
       || (optimize_size && standard_80387_constant_p (operands[1]))
       || GET_CODE (operands[1]) != CONST_DOUBLE
       || memory_operand (operands[0], XFmode))"
{
  switch (which_alternative)
    {
    case 0:
    case 1:
      return output_387_reg_move (insn, operands);

    case 2:
      return standard_80387_constant_opcode (operands[1]);

    case 3: case 4:
      return "#";

    default:
      gcc_unreachable ();
    }
}
  [(set_attr "type" "fmov,fmov,fmov,multi,multi")
   (set_attr "mode" "XF,XF,XF,SI,SI")])

(define_expand "movtf"
  [(set (match_operand:TF 0 "nonimmediate_operand" "")
        (match_operand:TF 1 "nonimmediate_operand" ""))]
  "TARGET_64BIT"
{
  ix86_expand_move (TFmode, operands);
  DONE;
})

(define_insn "*movtf_internal"
  [(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x,?r,?o")
        (match_operand:TF 1 "general_operand" "xm,x,C,roF,Fr"))]
  "TARGET_64BIT
   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
  switch (which_alternative)
    {
    case 0:
    case 1:
      if (get_attr_mode (insn) == MODE_V4SF)
        return "movaps\t{%1, %0|%0, %1}";
      else
        return "movdqa\t{%1, %0|%0, %1}";
    case 2:
      if (get_attr_mode (insn) == MODE_V4SF)
        return "xorps\t%0, %0";
      else
        return "pxor\t%0, %0";
    case 3:
    case 4:
        return "#";
    default:
      gcc_unreachable ();
    }
}
  [(set_attr "type" "ssemov,ssemov,sselog1,*,*")
   (set (attr "mode")
        (cond [(eq_attr "alternative" "0,2")
                 (if_then_else
                   (ne (symbol_ref "optimize_size")
                       (const_int 0))
                   (const_string "V4SF")
                   (const_string "TI"))
               (eq_attr "alternative" "1")
                 (if_then_else
                   (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
                            (const_int 0))
                        (ne (symbol_ref "optimize_size")
                            (const_int 0)))
                   (const_string "V4SF")
                   (const_string "TI"))]
               (const_string "DI")))])

(define_split
  [(set (match_operand 0 "nonimmediate_operand" "")
        (match_operand 1 "general_operand" ""))]
  "reload_completed
   && !(MEM_P (operands[0]) && MEM_P (operands[1]))
   && GET_MODE (operands[0]) == XFmode
   && ! (ANY_FP_REG_P (operands[0]) ||
         (GET_CODE (operands[0]) == SUBREG
          && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
   && ! (ANY_FP_REG_P (operands[1]) ||
         (GET_CODE (operands[1]) == SUBREG
          && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
  [(const_int 0)]
  "ix86_split_long_move (operands); DONE;")

(define_split
  [(set (match_operand 0 "register_operand" "")
        (match_operand 1 "memory_operand" ""))]
  "reload_completed
   && MEM_P (operands[1])
   && (GET_MODE (operands[0]) == TFmode
       || GET_MODE (operands[0]) == XFmode
       || GET_MODE (operands[0]) == SFmode
       || GET_MODE (operands[0]) == DFmode)
   && (operands[2] = find_constant_src (insn))"
  [(set (match_dup 0) (match_dup 2))]
{
  rtx c = operands[2];
  rtx r = operands[0];

  if (GET_CODE (r) == SUBREG)
    r = SUBREG_REG (r);

  if (SSE_REG_P (r))
    {
      if (!standard_sse_constant_p (c))
        FAIL;
    }
  else if (FP_REG_P (r))
    {
      if (!standard_80387_constant_p (c))
        FAIL;
    }
  else if (MMX_REG_P (r))
    FAIL;
})