1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 ;; 2001, 2002, 2003, 2004, 2005
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 ;; Boston, MA 02110-1301, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
31 ;; constraint letters.
33 ;; The special asm out single letter directives following a '%' are:
34 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
36 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
37 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
38 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
39 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
40 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
41 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
42 ;; 'J' Print the appropriate jump operand.
44 ;; 'b' Print the QImode name of the register for the indicated operand.
45 ;; %b0 would print %al if operands[0] is reg 0.
46 ;; 'w' Likewise, print the HImode name of the register.
47 ;; 'k' Likewise, print the SImode name of the register.
48 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
49 ;; 'y' Print "st(0)" instead of "st" as a register.
54 [; Relocation specifiers
66 (UNSPEC_STACK_ALLOC 11)
68 (UNSPEC_SSE_PROLOGUE_SAVE 13)
75 (UNSPEC_TLS_LD_BASE 18)
77 ; Other random patterns
87 ; For SSE/MMX support:
88 (UNSPEC_FIX_NOTRUNC 30)
96 (UNSPEC_NOP 38) ; prevents combiner cleverness
107 ; Generic math support
109 (UNSPEC_IEEE_MIN 51) ; not commutative
110 (UNSPEC_IEEE_MAX 52) ; not commutative
123 (UNSPEC_FRNDINT_FLOOR 70)
124 (UNSPEC_FRNDINT_CEIL 71)
125 (UNSPEC_FRNDINT_TRUNC 72)
126 (UNSPEC_FRNDINT_MASK_PM 73)
127 (UNSPEC_FIST_FLOOR 74)
128 (UNSPEC_FIST_CEIL 75)
130 ; x87 Double output FP
131 (UNSPEC_SINCOS_COS 80)
132 (UNSPEC_SINCOS_SIN 81)
135 (UNSPEC_XTRACT_FRACT 84)
136 (UNSPEC_XTRACT_EXP 85)
137 (UNSPEC_FSCALE_FRACT 86)
138 (UNSPEC_FSCALE_EXP 87)
147 (UNSPEC_SP_TLS_SET 102)
148 (UNSPEC_SP_TLS_TEST 103)
152 [(UNSPECV_BLOCKAGE 0)
153 (UNSPECV_STACK_PROBE 1)
162 (UNSPECV_CMPXCHG_1 10)
163 (UNSPECV_CMPXCHG_2 11)
168 ;; Registers by name.
177 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
180 ;; In C guard expressions, put expressions which may be compile-time
181 ;; constants first. This allows for better optimization. For
182 ;; example, write "TARGET_64BIT && reload_completed", not
183 ;; "reload_completed && TARGET_64BIT".
186 ;; Processor type. This attribute must exactly match the processor_type
187 ;; enumeration in i386.h.
188 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8,nocona"
189 (const (symbol_ref "ix86_tune")))
191 ;; A basic instruction type. Refinements due to arguments to be
192 ;; provided in other attributes.
195 alu,alu1,negnot,imov,imovx,lea,
196 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
197 icmp,test,ibr,setcc,icmov,
198 push,pop,call,callv,leave,
200 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint,
201 sselog,sselog1,sseiadd,sseishft,sseimul,
202 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
203 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
204 (const_string "other"))
206 ;; Main data type used by the insn
208 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF,V1DF"
209 (const_string "unknown"))
211 ;; The CPU unit operations uses.
212 (define_attr "unit" "integer,i387,sse,mmx,unknown"
213 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint")
214 (const_string "i387")
215 (eq_attr "type" "sselog,sselog1,sseiadd,sseishft,sseimul,
216 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
218 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
220 (eq_attr "type" "other")
221 (const_string "unknown")]
222 (const_string "integer")))
224 ;; The (bounding maximum) length of an instruction immediate.
225 (define_attr "length_immediate" ""
226 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
228 (eq_attr "unit" "i387,sse,mmx")
230 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
232 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
233 (eq_attr "type" "imov,test")
234 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
235 (eq_attr "type" "call")
236 (if_then_else (match_operand 0 "constant_call_address_operand" "")
239 (eq_attr "type" "callv")
240 (if_then_else (match_operand 1 "constant_call_address_operand" "")
243 ;; We don't know the size before shorten_branches. Expect
244 ;; the instruction to fit for better scheduling.
245 (eq_attr "type" "ibr")
248 (symbol_ref "/* Update immediate_length and other attributes! */
249 gcc_unreachable (),1")))
251 ;; The (bounding maximum) length of an instruction address.
252 (define_attr "length_address" ""
253 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
255 (and (eq_attr "type" "call")
256 (match_operand 0 "constant_call_address_operand" ""))
258 (and (eq_attr "type" "callv")
259 (match_operand 1 "constant_call_address_operand" ""))
262 (symbol_ref "ix86_attr_length_address_default (insn)")))
264 ;; Set when length prefix is used.
265 (define_attr "prefix_data16" ""
266 (if_then_else (ior (eq_attr "mode" "HI")
267 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
271 ;; Set when string REP prefix is used.
272 (define_attr "prefix_rep" ""
273 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
277 ;; Set when 0f opcode prefix is used.
278 (define_attr "prefix_0f" ""
280 (ior (eq_attr "type" "imovx,setcc,icmov")
281 (eq_attr "unit" "sse,mmx"))
285 ;; Set when REX opcode prefix is used.
286 (define_attr "prefix_rex" ""
287 (cond [(and (eq_attr "mode" "DI")
288 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
290 (and (eq_attr "mode" "QI")
291 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
294 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
300 ;; Set when modrm byte is used.
301 (define_attr "modrm" ""
302 (cond [(eq_attr "type" "str,cld,leave")
304 (eq_attr "unit" "i387")
306 (and (eq_attr "type" "incdec")
307 (ior (match_operand:SI 1 "register_operand" "")
308 (match_operand:HI 1 "register_operand" "")))
310 (and (eq_attr "type" "push")
311 (not (match_operand 1 "memory_operand" "")))
313 (and (eq_attr "type" "pop")
314 (not (match_operand 0 "memory_operand" "")))
316 (and (eq_attr "type" "imov")
317 (ior (and (match_operand 0 "register_operand" "")
318 (match_operand 1 "immediate_operand" ""))
319 (ior (and (match_operand 0 "ax_reg_operand" "")
320 (match_operand 1 "memory_displacement_only_operand" ""))
321 (and (match_operand 0 "memory_displacement_only_operand" "")
322 (match_operand 1 "ax_reg_operand" "")))))
324 (and (eq_attr "type" "call")
325 (match_operand 0 "constant_call_address_operand" ""))
327 (and (eq_attr "type" "callv")
328 (match_operand 1 "constant_call_address_operand" ""))
333 ;; The (bounding maximum) length of an instruction in bytes.
334 ;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
335 ;; Later we may want to split them and compute proper length as for
337 (define_attr "length" ""
338 (cond [(eq_attr "type" "other,multi,fistp,frndint")
340 (eq_attr "type" "fcmp")
342 (eq_attr "unit" "i387")
344 (plus (attr "prefix_data16")
345 (attr "length_address")))]
346 (plus (plus (attr "modrm")
347 (plus (attr "prefix_0f")
348 (plus (attr "prefix_rex")
350 (plus (attr "prefix_rep")
351 (plus (attr "prefix_data16")
352 (plus (attr "length_immediate")
353 (attr "length_address")))))))
355 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
356 ;; `store' if there is a simple memory reference therein, or `unknown'
357 ;; if the instruction is complex.
359 (define_attr "memory" "none,load,store,both,unknown"
360 (cond [(eq_attr "type" "other,multi,str")
361 (const_string "unknown")
362 (eq_attr "type" "lea,fcmov,fpspc,cld")
363 (const_string "none")
364 (eq_attr "type" "fistp,leave")
365 (const_string "both")
366 (eq_attr "type" "frndint")
367 (const_string "load")
368 (eq_attr "type" "push")
369 (if_then_else (match_operand 1 "memory_operand" "")
370 (const_string "both")
371 (const_string "store"))
372 (eq_attr "type" "pop")
373 (if_then_else (match_operand 0 "memory_operand" "")
374 (const_string "both")
375 (const_string "load"))
376 (eq_attr "type" "setcc")
377 (if_then_else (match_operand 0 "memory_operand" "")
378 (const_string "store")
379 (const_string "none"))
380 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
381 (if_then_else (ior (match_operand 0 "memory_operand" "")
382 (match_operand 1 "memory_operand" ""))
383 (const_string "load")
384 (const_string "none"))
385 (eq_attr "type" "ibr")
386 (if_then_else (match_operand 0 "memory_operand" "")
387 (const_string "load")
388 (const_string "none"))
389 (eq_attr "type" "call")
390 (if_then_else (match_operand 0 "constant_call_address_operand" "")
391 (const_string "none")
392 (const_string "load"))
393 (eq_attr "type" "callv")
394 (if_then_else (match_operand 1 "constant_call_address_operand" "")
395 (const_string "none")
396 (const_string "load"))
397 (and (eq_attr "type" "alu1,negnot,ishift1,sselog1")
398 (match_operand 1 "memory_operand" ""))
399 (const_string "both")
400 (and (match_operand 0 "memory_operand" "")
401 (match_operand 1 "memory_operand" ""))
402 (const_string "both")
403 (match_operand 0 "memory_operand" "")
404 (const_string "store")
405 (match_operand 1 "memory_operand" "")
406 (const_string "load")
408 "!alu1,negnot,ishift1,
409 imov,imovx,icmp,test,
411 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,sselog1,
412 mmx,mmxmov,mmxcmp,mmxcvt")
413 (match_operand 2 "memory_operand" ""))
414 (const_string "load")
415 (and (eq_attr "type" "icmov")
416 (match_operand 3 "memory_operand" ""))
417 (const_string "load")
419 (const_string "none")))
421 ;; Indicates if an instruction has both an immediate and a displacement.
423 (define_attr "imm_disp" "false,true,unknown"
424 (cond [(eq_attr "type" "other,multi")
425 (const_string "unknown")
426 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
427 (and (match_operand 0 "memory_displacement_operand" "")
428 (match_operand 1 "immediate_operand" "")))
429 (const_string "true")
430 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
431 (and (match_operand 0 "memory_displacement_operand" "")
432 (match_operand 2 "immediate_operand" "")))
433 (const_string "true")
435 (const_string "false")))
437 ;; Indicates if an FP operation has an integer source.
439 (define_attr "fp_int_src" "false,true"
440 (const_string "false"))
442 ;; Defines rounding mode of an FP operation.
444 (define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
445 (const_string "any"))
447 ;; Describe a user's asm statement.
448 (define_asm_attributes
449 [(set_attr "length" "128")
450 (set_attr "type" "multi")])
452 ;; All x87 floating point modes
453 (define_mode_macro X87MODEF [SF DF XF])
455 ;; All integer modes handled by x87 fisttp operator.
456 (define_mode_macro X87MODEI [HI SI DI])
458 ;; All integer modes handled by integer x87 operators.
459 (define_mode_macro X87MODEI12 [HI SI])
461 ;; All SSE floating point modes
462 (define_mode_macro SSEMODEF [SF DF])
464 ;; All integer modes handled by SSE cvtts?2si* operators.
465 (define_mode_macro SSEMODEI24 [SI DI])
468 ;; Scheduling descriptions
470 (include "pentium.md")
473 (include "athlon.md")
476 ;; Operand and operator predicates
478 (include "predicates.md")
481 ;; Compare instructions.
483 ;; All compare insns have expanders that save the operands away without
484 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
485 ;; after the cmp) will actually emit the cmpM.
487 (define_expand "cmpti"
488 [(set (reg:CC FLAGS_REG)
489 (compare:CC (match_operand:TI 0 "nonimmediate_operand" "")
490 (match_operand:TI 1 "x86_64_general_operand" "")))]
493 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
494 operands[0] = force_reg (TImode, operands[0]);
495 ix86_compare_op0 = operands[0];
496 ix86_compare_op1 = operands[1];
500 (define_expand "cmpdi"
501 [(set (reg:CC FLAGS_REG)
502 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
503 (match_operand:DI 1 "x86_64_general_operand" "")))]
506 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
507 operands[0] = force_reg (DImode, operands[0]);
508 ix86_compare_op0 = operands[0];
509 ix86_compare_op1 = operands[1];
513 (define_expand "cmpsi"
514 [(set (reg:CC FLAGS_REG)
515 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
516 (match_operand:SI 1 "general_operand" "")))]
519 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
520 operands[0] = force_reg (SImode, operands[0]);
521 ix86_compare_op0 = operands[0];
522 ix86_compare_op1 = operands[1];
526 (define_expand "cmphi"
527 [(set (reg:CC FLAGS_REG)
528 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
529 (match_operand:HI 1 "general_operand" "")))]
532 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
533 operands[0] = force_reg (HImode, operands[0]);
534 ix86_compare_op0 = operands[0];
535 ix86_compare_op1 = operands[1];
539 (define_expand "cmpqi"
540 [(set (reg:CC FLAGS_REG)
541 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
542 (match_operand:QI 1 "general_operand" "")))]
545 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
546 operands[0] = force_reg (QImode, operands[0]);
547 ix86_compare_op0 = operands[0];
548 ix86_compare_op1 = operands[1];
552 (define_insn "cmpdi_ccno_1_rex64"
553 [(set (reg FLAGS_REG)
554 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
555 (match_operand:DI 1 "const0_operand" "n,n")))]
556 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
558 test{q}\t{%0, %0|%0, %0}
559 cmp{q}\t{%1, %0|%0, %1}"
560 [(set_attr "type" "test,icmp")
561 (set_attr "length_immediate" "0,1")
562 (set_attr "mode" "DI")])
564 (define_insn "*cmpdi_minus_1_rex64"
565 [(set (reg FLAGS_REG)
566 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
567 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
569 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
570 "cmp{q}\t{%1, %0|%0, %1}"
571 [(set_attr "type" "icmp")
572 (set_attr "mode" "DI")])
574 (define_expand "cmpdi_1_rex64"
575 [(set (reg:CC FLAGS_REG)
576 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
577 (match_operand:DI 1 "general_operand" "")))]
581 (define_insn "cmpdi_1_insn_rex64"
582 [(set (reg FLAGS_REG)
583 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
584 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
585 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
586 "cmp{q}\t{%1, %0|%0, %1}"
587 [(set_attr "type" "icmp")
588 (set_attr "mode" "DI")])
591 (define_insn "*cmpsi_ccno_1"
592 [(set (reg FLAGS_REG)
593 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
594 (match_operand:SI 1 "const0_operand" "n,n")))]
595 "ix86_match_ccmode (insn, CCNOmode)"
597 test{l}\t{%0, %0|%0, %0}
598 cmp{l}\t{%1, %0|%0, %1}"
599 [(set_attr "type" "test,icmp")
600 (set_attr "length_immediate" "0,1")
601 (set_attr "mode" "SI")])
603 (define_insn "*cmpsi_minus_1"
604 [(set (reg FLAGS_REG)
605 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
606 (match_operand:SI 1 "general_operand" "ri,mr"))
608 "ix86_match_ccmode (insn, CCGOCmode)"
609 "cmp{l}\t{%1, %0|%0, %1}"
610 [(set_attr "type" "icmp")
611 (set_attr "mode" "SI")])
613 (define_expand "cmpsi_1"
614 [(set (reg:CC FLAGS_REG)
615 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
616 (match_operand:SI 1 "general_operand" "ri,mr")))]
620 (define_insn "*cmpsi_1_insn"
621 [(set (reg FLAGS_REG)
622 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
623 (match_operand:SI 1 "general_operand" "ri,mr")))]
624 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
625 && ix86_match_ccmode (insn, CCmode)"
626 "cmp{l}\t{%1, %0|%0, %1}"
627 [(set_attr "type" "icmp")
628 (set_attr "mode" "SI")])
630 (define_insn "*cmphi_ccno_1"
631 [(set (reg FLAGS_REG)
632 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
633 (match_operand:HI 1 "const0_operand" "n,n")))]
634 "ix86_match_ccmode (insn, CCNOmode)"
636 test{w}\t{%0, %0|%0, %0}
637 cmp{w}\t{%1, %0|%0, %1}"
638 [(set_attr "type" "test,icmp")
639 (set_attr "length_immediate" "0,1")
640 (set_attr "mode" "HI")])
642 (define_insn "*cmphi_minus_1"
643 [(set (reg FLAGS_REG)
644 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
645 (match_operand:HI 1 "general_operand" "ri,mr"))
647 "ix86_match_ccmode (insn, CCGOCmode)"
648 "cmp{w}\t{%1, %0|%0, %1}"
649 [(set_attr "type" "icmp")
650 (set_attr "mode" "HI")])
652 (define_insn "*cmphi_1"
653 [(set (reg FLAGS_REG)
654 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
655 (match_operand:HI 1 "general_operand" "ri,mr")))]
656 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
657 && ix86_match_ccmode (insn, CCmode)"
658 "cmp{w}\t{%1, %0|%0, %1}"
659 [(set_attr "type" "icmp")
660 (set_attr "mode" "HI")])
662 (define_insn "*cmpqi_ccno_1"
663 [(set (reg FLAGS_REG)
664 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
665 (match_operand:QI 1 "const0_operand" "n,n")))]
666 "ix86_match_ccmode (insn, CCNOmode)"
668 test{b}\t{%0, %0|%0, %0}
669 cmp{b}\t{$0, %0|%0, 0}"
670 [(set_attr "type" "test,icmp")
671 (set_attr "length_immediate" "0,1")
672 (set_attr "mode" "QI")])
674 (define_insn "*cmpqi_1"
675 [(set (reg FLAGS_REG)
676 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
677 (match_operand:QI 1 "general_operand" "qi,mq")))]
678 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
679 && ix86_match_ccmode (insn, CCmode)"
680 "cmp{b}\t{%1, %0|%0, %1}"
681 [(set_attr "type" "icmp")
682 (set_attr "mode" "QI")])
684 (define_insn "*cmpqi_minus_1"
685 [(set (reg FLAGS_REG)
686 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
687 (match_operand:QI 1 "general_operand" "qi,mq"))
689 "ix86_match_ccmode (insn, CCGOCmode)"
690 "cmp{b}\t{%1, %0|%0, %1}"
691 [(set_attr "type" "icmp")
692 (set_attr "mode" "QI")])
694 (define_insn "*cmpqi_ext_1"
695 [(set (reg FLAGS_REG)
697 (match_operand:QI 0 "general_operand" "Qm")
700 (match_operand 1 "ext_register_operand" "Q")
703 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
704 "cmp{b}\t{%h1, %0|%0, %h1}"
705 [(set_attr "type" "icmp")
706 (set_attr "mode" "QI")])
708 (define_insn "*cmpqi_ext_1_rex64"
709 [(set (reg FLAGS_REG)
711 (match_operand:QI 0 "register_operand" "Q")
714 (match_operand 1 "ext_register_operand" "Q")
717 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
718 "cmp{b}\t{%h1, %0|%0, %h1}"
719 [(set_attr "type" "icmp")
720 (set_attr "mode" "QI")])
722 (define_insn "*cmpqi_ext_2"
723 [(set (reg FLAGS_REG)
727 (match_operand 0 "ext_register_operand" "Q")
730 (match_operand:QI 1 "const0_operand" "n")))]
731 "ix86_match_ccmode (insn, CCNOmode)"
733 [(set_attr "type" "test")
734 (set_attr "length_immediate" "0")
735 (set_attr "mode" "QI")])
737 (define_expand "cmpqi_ext_3"
738 [(set (reg:CC FLAGS_REG)
742 (match_operand 0 "ext_register_operand" "")
745 (match_operand:QI 1 "general_operand" "")))]
749 (define_insn "cmpqi_ext_3_insn"
750 [(set (reg FLAGS_REG)
754 (match_operand 0 "ext_register_operand" "Q")
757 (match_operand:QI 1 "general_operand" "Qmn")))]
758 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
759 "cmp{b}\t{%1, %h0|%h0, %1}"
760 [(set_attr "type" "icmp")
761 (set_attr "mode" "QI")])
763 (define_insn "cmpqi_ext_3_insn_rex64"
764 [(set (reg FLAGS_REG)
768 (match_operand 0 "ext_register_operand" "Q")
771 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
772 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
773 "cmp{b}\t{%1, %h0|%h0, %1}"
774 [(set_attr "type" "icmp")
775 (set_attr "mode" "QI")])
777 (define_insn "*cmpqi_ext_4"
778 [(set (reg FLAGS_REG)
782 (match_operand 0 "ext_register_operand" "Q")
787 (match_operand 1 "ext_register_operand" "Q")
790 "ix86_match_ccmode (insn, CCmode)"
791 "cmp{b}\t{%h1, %h0|%h0, %h1}"
792 [(set_attr "type" "icmp")
793 (set_attr "mode" "QI")])
795 ;; These implement float point compares.
796 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
797 ;; which would allow mix and match FP modes on the compares. Which is what
798 ;; the old patterns did, but with many more of them.
800 (define_expand "cmpxf"
801 [(set (reg:CC FLAGS_REG)
802 (compare:CC (match_operand:XF 0 "nonmemory_operand" "")
803 (match_operand:XF 1 "nonmemory_operand" "")))]
806 ix86_compare_op0 = operands[0];
807 ix86_compare_op1 = operands[1];
811 (define_expand "cmpdf"
812 [(set (reg:CC FLAGS_REG)
813 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
814 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
815 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
817 ix86_compare_op0 = operands[0];
818 ix86_compare_op1 = operands[1];
822 (define_expand "cmpsf"
823 [(set (reg:CC FLAGS_REG)
824 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
825 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
826 "TARGET_80387 || TARGET_SSE_MATH"
828 ix86_compare_op0 = operands[0];
829 ix86_compare_op1 = operands[1];
833 ;; FP compares, step 1:
834 ;; Set the FP condition codes.
836 ;; CCFPmode compare with exceptions
837 ;; CCFPUmode compare with no exceptions
839 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
840 ;; used to manage the reg stack popping would not be preserved.
842 (define_insn "*cmpfp_0"
843 [(set (match_operand:HI 0 "register_operand" "=a")
846 (match_operand 1 "register_operand" "f")
847 (match_operand 2 "const0_operand" "X"))]
850 && FLOAT_MODE_P (GET_MODE (operands[1]))
851 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
852 "* return output_fp_compare (insn, operands, 0, 0);"
853 [(set_attr "type" "multi")
854 (set_attr "unit" "i387")
856 (cond [(match_operand:SF 1 "" "")
858 (match_operand:DF 1 "" "")
861 (const_string "XF")))])
863 (define_insn "*cmpfp_sf"
864 [(set (match_operand:HI 0 "register_operand" "=a")
867 (match_operand:SF 1 "register_operand" "f")
868 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
871 "* return output_fp_compare (insn, operands, 0, 0);"
872 [(set_attr "type" "multi")
873 (set_attr "unit" "i387")
874 (set_attr "mode" "SF")])
876 (define_insn "*cmpfp_df"
877 [(set (match_operand:HI 0 "register_operand" "=a")
880 (match_operand:DF 1 "register_operand" "f")
881 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
884 "* return output_fp_compare (insn, operands, 0, 0);"
885 [(set_attr "type" "multi")
886 (set_attr "unit" "i387")
887 (set_attr "mode" "DF")])
889 (define_insn "*cmpfp_xf"
890 [(set (match_operand:HI 0 "register_operand" "=a")
893 (match_operand:XF 1 "register_operand" "f")
894 (match_operand:XF 2 "register_operand" "f"))]
897 "* return output_fp_compare (insn, operands, 0, 0);"
898 [(set_attr "type" "multi")
899 (set_attr "unit" "i387")
900 (set_attr "mode" "XF")])
902 (define_insn "*cmpfp_u"
903 [(set (match_operand:HI 0 "register_operand" "=a")
906 (match_operand 1 "register_operand" "f")
907 (match_operand 2 "register_operand" "f"))]
910 && FLOAT_MODE_P (GET_MODE (operands[1]))
911 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
912 "* return output_fp_compare (insn, operands, 0, 1);"
913 [(set_attr "type" "multi")
914 (set_attr "unit" "i387")
916 (cond [(match_operand:SF 1 "" "")
918 (match_operand:DF 1 "" "")
921 (const_string "XF")))])
923 (define_insn "*cmpfp_<mode>"
924 [(set (match_operand:HI 0 "register_operand" "=a")
927 (match_operand 1 "register_operand" "f")
928 (match_operator 3 "float_operator"
929 [(match_operand:X87MODEI12 2 "memory_operand" "m")]))]
931 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
932 && FLOAT_MODE_P (GET_MODE (operands[1]))
933 && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
934 "* return output_fp_compare (insn, operands, 0, 0);"
935 [(set_attr "type" "multi")
936 (set_attr "unit" "i387")
937 (set_attr "fp_int_src" "true")
938 (set_attr "mode" "<MODE>")])
940 ;; FP compares, step 2
941 ;; Move the fpsw to ax.
943 (define_insn "x86_fnstsw_1"
944 [(set (match_operand:HI 0 "register_operand" "=a")
945 (unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
948 [(set_attr "length" "2")
949 (set_attr "mode" "SI")
950 (set_attr "unit" "i387")])
952 ;; FP compares, step 3
953 ;; Get ax into flags, general case.
955 (define_insn "x86_sahf_1"
956 [(set (reg:CC FLAGS_REG)
957 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
960 [(set_attr "length" "1")
961 (set_attr "athlon_decode" "vector")
962 (set_attr "mode" "SI")])
964 ;; Pentium Pro can do steps 1 through 3 in one go.
966 (define_insn "*cmpfp_i_mixed"
967 [(set (reg:CCFP FLAGS_REG)
968 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
969 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
971 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
972 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
973 "* return output_fp_compare (insn, operands, 1, 0);"
974 [(set_attr "type" "fcmp,ssecomi")
976 (if_then_else (match_operand:SF 1 "" "")
978 (const_string "DF")))
979 (set_attr "athlon_decode" "vector")])
981 (define_insn "*cmpfp_i_sse"
982 [(set (reg:CCFP FLAGS_REG)
983 (compare:CCFP (match_operand 0 "register_operand" "x")
984 (match_operand 1 "nonimmediate_operand" "xm")))]
986 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
987 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
988 "* return output_fp_compare (insn, operands, 1, 0);"
989 [(set_attr "type" "ssecomi")
991 (if_then_else (match_operand:SF 1 "" "")
993 (const_string "DF")))
994 (set_attr "athlon_decode" "vector")])
996 (define_insn "*cmpfp_i_i387"
997 [(set (reg:CCFP FLAGS_REG)
998 (compare:CCFP (match_operand 0 "register_operand" "f")
999 (match_operand 1 "register_operand" "f")))]
1000 "TARGET_80387 && TARGET_CMOVE
1001 && (!TARGET_SSE_MATH || !SSE_FLOAT_MODE_P (GET_MODE (operands[0])))
1002 && FLOAT_MODE_P (GET_MODE (operands[0]))
1003 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1004 "* return output_fp_compare (insn, operands, 1, 0);"
1005 [(set_attr "type" "fcmp")
1007 (cond [(match_operand:SF 1 "" "")
1009 (match_operand:DF 1 "" "")
1012 (const_string "XF")))
1013 (set_attr "athlon_decode" "vector")])
1015 (define_insn "*cmpfp_iu_mixed"
1016 [(set (reg:CCFPU FLAGS_REG)
1017 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1018 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1019 "TARGET_MIX_SSE_I387
1020 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1021 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1022 "* return output_fp_compare (insn, operands, 1, 1);"
1023 [(set_attr "type" "fcmp,ssecomi")
1025 (if_then_else (match_operand:SF 1 "" "")
1027 (const_string "DF")))
1028 (set_attr "athlon_decode" "vector")])
1030 (define_insn "*cmpfp_iu_sse"
1031 [(set (reg:CCFPU FLAGS_REG)
1032 (compare:CCFPU (match_operand 0 "register_operand" "x")
1033 (match_operand 1 "nonimmediate_operand" "xm")))]
1035 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1036 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1037 "* return output_fp_compare (insn, operands, 1, 1);"
1038 [(set_attr "type" "ssecomi")
1040 (if_then_else (match_operand:SF 1 "" "")
1042 (const_string "DF")))
1043 (set_attr "athlon_decode" "vector")])
1045 (define_insn "*cmpfp_iu_387"
1046 [(set (reg:CCFPU FLAGS_REG)
1047 (compare:CCFPU (match_operand 0 "register_operand" "f")
1048 (match_operand 1 "register_operand" "f")))]
1049 "TARGET_80387 && TARGET_CMOVE
1050 && (!TARGET_SSE_MATH || !SSE_FLOAT_MODE_P (GET_MODE (operands[0])))
1051 && FLOAT_MODE_P (GET_MODE (operands[0]))
1052 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1053 "* return output_fp_compare (insn, operands, 1, 1);"
1054 [(set_attr "type" "fcmp")
1056 (cond [(match_operand:SF 1 "" "")
1058 (match_operand:DF 1 "" "")
1061 (const_string "XF")))
1062 (set_attr "athlon_decode" "vector")])
1064 ;; Move instructions.
1066 ;; General case of fullword move.
1068 (define_expand "movsi"
1069 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1070 (match_operand:SI 1 "general_operand" ""))]
1072 "ix86_expand_move (SImode, operands); DONE;")
1074 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1077 ;; %%% We don't use a post-inc memory reference because x86 is not a
1078 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1079 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1080 ;; targets without our curiosities, and it is just as easy to represent
1081 ;; this differently.
1083 (define_insn "*pushsi2"
1084 [(set (match_operand:SI 0 "push_operand" "=<")
1085 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1088 [(set_attr "type" "push")
1089 (set_attr "mode" "SI")])
1091 ;; For 64BIT abi we always round up to 8 bytes.
1092 (define_insn "*pushsi2_rex64"
1093 [(set (match_operand:SI 0 "push_operand" "=X")
1094 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1097 [(set_attr "type" "push")
1098 (set_attr "mode" "SI")])
1100 (define_insn "*pushsi2_prologue"
1101 [(set (match_operand:SI 0 "push_operand" "=<")
1102 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1103 (clobber (mem:BLK (scratch)))]
1106 [(set_attr "type" "push")
1107 (set_attr "mode" "SI")])
1109 (define_insn "*popsi1_epilogue"
1110 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1111 (mem:SI (reg:SI SP_REG)))
1112 (set (reg:SI SP_REG)
1113 (plus:SI (reg:SI SP_REG) (const_int 4)))
1114 (clobber (mem:BLK (scratch)))]
1117 [(set_attr "type" "pop")
1118 (set_attr "mode" "SI")])
1120 (define_insn "popsi1"
1121 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1122 (mem:SI (reg:SI SP_REG)))
1123 (set (reg:SI SP_REG)
1124 (plus:SI (reg:SI SP_REG) (const_int 4)))]
1127 [(set_attr "type" "pop")
1128 (set_attr "mode" "SI")])
1130 (define_insn "*movsi_xor"
1131 [(set (match_operand:SI 0 "register_operand" "=r")
1132 (match_operand:SI 1 "const0_operand" "i"))
1133 (clobber (reg:CC FLAGS_REG))]
1134 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1135 "xor{l}\t{%0, %0|%0, %0}"
1136 [(set_attr "type" "alu1")
1137 (set_attr "mode" "SI")
1138 (set_attr "length_immediate" "0")])
1140 (define_insn "*movsi_or"
1141 [(set (match_operand:SI 0 "register_operand" "=r")
1142 (match_operand:SI 1 "immediate_operand" "i"))
1143 (clobber (reg:CC FLAGS_REG))]
1145 && operands[1] == constm1_rtx
1146 && (TARGET_PENTIUM || optimize_size)"
1148 operands[1] = constm1_rtx;
1149 return "or{l}\t{%1, %0|%0, %1}";
1151 [(set_attr "type" "alu1")
1152 (set_attr "mode" "SI")
1153 (set_attr "length_immediate" "1")])
1155 (define_insn "*movsi_1"
1156 [(set (match_operand:SI 0 "nonimmediate_operand"
1157 "=r ,m ,*y,*y,?rm,?*y,*x,*x,?r,m ,?*Y,*x")
1158 (match_operand:SI 1 "general_operand"
1159 "rinm,rin,C ,*y,*y ,rm ,C ,*x,*Y,*x,r ,m "))]
1160 "!(MEM_P (operands[0]) && MEM_P (operands[1]))"
1162 switch (get_attr_type (insn))
1165 if (get_attr_mode (insn) == MODE_TI)
1166 return "pxor\t%0, %0";
1167 return "xorps\t%0, %0";
1170 switch (get_attr_mode (insn))
1173 return "movdqa\t{%1, %0|%0, %1}";
1175 return "movaps\t{%1, %0|%0, %1}";
1177 return "movd\t{%1, %0|%0, %1}";
1179 return "movss\t{%1, %0|%0, %1}";
1185 return "pxor\t%0, %0";
1188 if (get_attr_mode (insn) == MODE_DI)
1189 return "movq\t{%1, %0|%0, %1}";
1190 return "movd\t{%1, %0|%0, %1}";
1193 return "lea{l}\t{%1, %0|%0, %1}";
1196 gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
1197 return "mov{l}\t{%1, %0|%0, %1}";
1201 (cond [(eq_attr "alternative" "2")
1202 (const_string "mmxadd")
1203 (eq_attr "alternative" "3,4,5")
1204 (const_string "mmxmov")
1205 (eq_attr "alternative" "6")
1206 (const_string "sselog1")
1207 (eq_attr "alternative" "7,8,9,10,11")
1208 (const_string "ssemov")
1209 (match_operand:DI 1 "pic_32bit_operand" "")
1210 (const_string "lea")
1212 (const_string "imov")))
1214 (cond [(eq_attr "alternative" "2,3")
1216 (eq_attr "alternative" "6,7")
1218 (eq (symbol_ref "TARGET_SSE2") (const_int 0))
1219 (const_string "V4SF")
1220 (const_string "TI"))
1221 (and (eq_attr "alternative" "8,9,10,11")
1222 (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
1225 (const_string "SI")))])
1227 ;; Stores and loads of ax to arbitrary constant address.
1228 ;; We fake an second form of instruction to force reload to load address
1229 ;; into register when rax is not available
1230 (define_insn "*movabssi_1_rex64"
1231 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1232 (match_operand:SI 1 "nonmemory_operand" "a,er"))]
1233 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1235 movabs{l}\t{%1, %P0|%P0, %1}
1236 mov{l}\t{%1, %a0|%a0, %1}"
1237 [(set_attr "type" "imov")
1238 (set_attr "modrm" "0,*")
1239 (set_attr "length_address" "8,0")
1240 (set_attr "length_immediate" "0,*")
1241 (set_attr "memory" "store")
1242 (set_attr "mode" "SI")])
1244 (define_insn "*movabssi_2_rex64"
1245 [(set (match_operand:SI 0 "register_operand" "=a,r")
1246 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1247 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1249 movabs{l}\t{%P1, %0|%0, %P1}
1250 mov{l}\t{%a1, %0|%0, %a1}"
1251 [(set_attr "type" "imov")
1252 (set_attr "modrm" "0,*")
1253 (set_attr "length_address" "8,0")
1254 (set_attr "length_immediate" "0")
1255 (set_attr "memory" "load")
1256 (set_attr "mode" "SI")])
1258 (define_insn "*swapsi"
1259 [(set (match_operand:SI 0 "register_operand" "+r")
1260 (match_operand:SI 1 "register_operand" "+r"))
1265 [(set_attr "type" "imov")
1266 (set_attr "mode" "SI")
1267 (set_attr "pent_pair" "np")
1268 (set_attr "athlon_decode" "vector")])
1270 (define_expand "movhi"
1271 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1272 (match_operand:HI 1 "general_operand" ""))]
1274 "ix86_expand_move (HImode, operands); DONE;")
1276 (define_insn "*pushhi2"
1277 [(set (match_operand:HI 0 "push_operand" "=<,<")
1278 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1281 push{w}\t{|WORD PTR }%1
1283 [(set_attr "type" "push")
1284 (set_attr "mode" "HI")])
1286 ;; For 64BIT abi we always round up to 8 bytes.
1287 (define_insn "*pushhi2_rex64"
1288 [(set (match_operand:HI 0 "push_operand" "=X")
1289 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1292 [(set_attr "type" "push")
1293 (set_attr "mode" "QI")])
1295 (define_insn "*movhi_1"
1296 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1297 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1298 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1300 switch (get_attr_type (insn))
1303 /* movzwl is faster than movw on p2 due to partial word stalls,
1304 though not as fast as an aligned movl. */
1305 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1307 if (get_attr_mode (insn) == MODE_SI)
1308 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1310 return "mov{w}\t{%1, %0|%0, %1}";
1314 (cond [(ne (symbol_ref "optimize_size") (const_int 0))
1315 (const_string "imov")
1316 (and (eq_attr "alternative" "0")
1317 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1319 (eq (symbol_ref "TARGET_HIMODE_MATH")
1321 (const_string "imov")
1322 (and (eq_attr "alternative" "1,2")
1323 (match_operand:HI 1 "aligned_operand" ""))
1324 (const_string "imov")
1325 (and (ne (symbol_ref "TARGET_MOVX")
1327 (eq_attr "alternative" "0,2"))
1328 (const_string "imovx")
1330 (const_string "imov")))
1332 (cond [(eq_attr "type" "imovx")
1334 (and (eq_attr "alternative" "1,2")
1335 (match_operand:HI 1 "aligned_operand" ""))
1337 (and (eq_attr "alternative" "0")
1338 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1340 (eq (symbol_ref "TARGET_HIMODE_MATH")
1344 (const_string "HI")))])
1346 ;; Stores and loads of ax to arbitrary constant address.
1347 ;; We fake an second form of instruction to force reload to load address
1348 ;; into register when rax is not available
1349 (define_insn "*movabshi_1_rex64"
1350 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1351 (match_operand:HI 1 "nonmemory_operand" "a,er"))]
1352 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1354 movabs{w}\t{%1, %P0|%P0, %1}
1355 mov{w}\t{%1, %a0|%a0, %1}"
1356 [(set_attr "type" "imov")
1357 (set_attr "modrm" "0,*")
1358 (set_attr "length_address" "8,0")
1359 (set_attr "length_immediate" "0,*")
1360 (set_attr "memory" "store")
1361 (set_attr "mode" "HI")])
1363 (define_insn "*movabshi_2_rex64"
1364 [(set (match_operand:HI 0 "register_operand" "=a,r")
1365 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1366 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1368 movabs{w}\t{%P1, %0|%0, %P1}
1369 mov{w}\t{%a1, %0|%0, %a1}"
1370 [(set_attr "type" "imov")
1371 (set_attr "modrm" "0,*")
1372 (set_attr "length_address" "8,0")
1373 (set_attr "length_immediate" "0")
1374 (set_attr "memory" "load")
1375 (set_attr "mode" "HI")])
1377 (define_insn "*swaphi_1"
1378 [(set (match_operand:HI 0 "register_operand" "+r")
1379 (match_operand:HI 1 "register_operand" "+r"))
1382 "!TARGET_PARTIAL_REG_STALL || optimize_size"
1384 [(set_attr "type" "imov")
1385 (set_attr "mode" "SI")
1386 (set_attr "pent_pair" "np")
1387 (set_attr "athlon_decode" "vector")])
1389 (define_insn "*swaphi_2"
1390 [(set (match_operand:HI 0 "register_operand" "+r")
1391 (match_operand:HI 1 "register_operand" "+r"))
1394 "TARGET_PARTIAL_REG_STALL"
1396 [(set_attr "type" "imov")
1397 (set_attr "mode" "HI")
1398 (set_attr "pent_pair" "np")
1399 (set_attr "athlon_decode" "vector")])
1401 (define_expand "movstricthi"
1402 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1403 (match_operand:HI 1 "general_operand" ""))]
1404 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1406 /* Don't generate memory->memory moves, go through a register */
1407 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1408 operands[1] = force_reg (HImode, operands[1]);
1411 (define_insn "*movstricthi_1"
1412 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1413 (match_operand:HI 1 "general_operand" "rn,m"))]
1414 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1415 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1416 "mov{w}\t{%1, %0|%0, %1}"
1417 [(set_attr "type" "imov")
1418 (set_attr "mode" "HI")])
1420 (define_insn "*movstricthi_xor"
1421 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1422 (match_operand:HI 1 "const0_operand" "i"))
1423 (clobber (reg:CC FLAGS_REG))]
1425 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1426 "xor{w}\t{%0, %0|%0, %0}"
1427 [(set_attr "type" "alu1")
1428 (set_attr "mode" "HI")
1429 (set_attr "length_immediate" "0")])
1431 (define_expand "movqi"
1432 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1433 (match_operand:QI 1 "general_operand" ""))]
1435 "ix86_expand_move (QImode, operands); DONE;")
1437 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1438 ;; "push a byte". But actually we use pushw, which has the effect
1439 ;; of rounding the amount pushed up to a halfword.
1441 (define_insn "*pushqi2"
1442 [(set (match_operand:QI 0 "push_operand" "=X,X")
1443 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1446 push{w}\t{|word ptr }%1
1448 [(set_attr "type" "push")
1449 (set_attr "mode" "HI")])
1451 ;; For 64BIT abi we always round up to 8 bytes.
1452 (define_insn "*pushqi2_rex64"
1453 [(set (match_operand:QI 0 "push_operand" "=X")
1454 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1457 [(set_attr "type" "push")
1458 (set_attr "mode" "QI")])
1460 ;; Situation is quite tricky about when to choose full sized (SImode) move
1461 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1462 ;; partial register dependency machines (such as AMD Athlon), where QImode
1463 ;; moves issue extra dependency and for partial register stalls machines
1464 ;; that don't use QImode patterns (and QImode move cause stall on the next
1467 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1468 ;; register stall machines with, where we use QImode instructions, since
1469 ;; partial register stall can be caused there. Then we use movzx.
1470 (define_insn "*movqi_1"
1471 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1472 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1473 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1475 switch (get_attr_type (insn))
1478 gcc_assert (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM);
1479 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1481 if (get_attr_mode (insn) == MODE_SI)
1482 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1484 return "mov{b}\t{%1, %0|%0, %1}";
1488 (cond [(and (eq_attr "alternative" "5")
1489 (not (match_operand:QI 1 "aligned_operand" "")))
1490 (const_string "imovx")
1491 (ne (symbol_ref "optimize_size") (const_int 0))
1492 (const_string "imov")
1493 (and (eq_attr "alternative" "3")
1494 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1496 (eq (symbol_ref "TARGET_QIMODE_MATH")
1498 (const_string "imov")
1499 (eq_attr "alternative" "3,5")
1500 (const_string "imovx")
1501 (and (ne (symbol_ref "TARGET_MOVX")
1503 (eq_attr "alternative" "2"))
1504 (const_string "imovx")
1506 (const_string "imov")))
1508 (cond [(eq_attr "alternative" "3,4,5")
1510 (eq_attr "alternative" "6")
1512 (eq_attr "type" "imovx")
1514 (and (eq_attr "type" "imov")
1515 (and (eq_attr "alternative" "0,1")
1516 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1519 ;; Avoid partial register stalls when not using QImode arithmetic
1520 (and (eq_attr "type" "imov")
1521 (and (eq_attr "alternative" "0,1")
1522 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1524 (eq (symbol_ref "TARGET_QIMODE_MATH")
1528 (const_string "QI")))])
1530 (define_expand "reload_outqi"
1531 [(parallel [(match_operand:QI 0 "" "=m")
1532 (match_operand:QI 1 "register_operand" "r")
1533 (match_operand:QI 2 "register_operand" "=&q")])]
1537 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1539 gcc_assert (!reg_overlap_mentioned_p (op2, op0));
1540 if (! q_regs_operand (op1, QImode))
1542 emit_insn (gen_movqi (op2, op1));
1545 emit_insn (gen_movqi (op0, op1));
1549 (define_insn "*swapqi_1"
1550 [(set (match_operand:QI 0 "register_operand" "+r")
1551 (match_operand:QI 1 "register_operand" "+r"))
1554 "!TARGET_PARTIAL_REG_STALL || optimize_size"
1556 [(set_attr "type" "imov")
1557 (set_attr "mode" "SI")
1558 (set_attr "pent_pair" "np")
1559 (set_attr "athlon_decode" "vector")])
1561 (define_insn "*swapqi_2"
1562 [(set (match_operand:QI 0 "register_operand" "+q")
1563 (match_operand:QI 1 "register_operand" "+q"))
1566 "TARGET_PARTIAL_REG_STALL"
1568 [(set_attr "type" "imov")
1569 (set_attr "mode" "QI")
1570 (set_attr "pent_pair" "np")
1571 (set_attr "athlon_decode" "vector")])
1573 (define_expand "movstrictqi"
1574 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1575 (match_operand:QI 1 "general_operand" ""))]
1576 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1578 /* Don't generate memory->memory moves, go through a register. */
1579 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1580 operands[1] = force_reg (QImode, operands[1]);
1583 (define_insn "*movstrictqi_1"
1584 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1585 (match_operand:QI 1 "general_operand" "*qn,m"))]
1586 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1587 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1588 "mov{b}\t{%1, %0|%0, %1}"
1589 [(set_attr "type" "imov")
1590 (set_attr "mode" "QI")])
1592 (define_insn "*movstrictqi_xor"
1593 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1594 (match_operand:QI 1 "const0_operand" "i"))
1595 (clobber (reg:CC FLAGS_REG))]
1596 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1597 "xor{b}\t{%0, %0|%0, %0}"
1598 [(set_attr "type" "alu1")
1599 (set_attr "mode" "QI")
1600 (set_attr "length_immediate" "0")])
1602 (define_insn "*movsi_extv_1"
1603 [(set (match_operand:SI 0 "register_operand" "=R")
1604 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1608 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1609 [(set_attr "type" "imovx")
1610 (set_attr "mode" "SI")])
1612 (define_insn "*movhi_extv_1"
1613 [(set (match_operand:HI 0 "register_operand" "=R")
1614 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1618 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1619 [(set_attr "type" "imovx")
1620 (set_attr "mode" "SI")])
1622 (define_insn "*movqi_extv_1"
1623 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1624 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1629 switch (get_attr_type (insn))
1632 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1634 return "mov{b}\t{%h1, %0|%0, %h1}";
1638 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1639 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1640 (ne (symbol_ref "TARGET_MOVX")
1642 (const_string "imovx")
1643 (const_string "imov")))
1645 (if_then_else (eq_attr "type" "imovx")
1647 (const_string "QI")))])
1649 (define_insn "*movqi_extv_1_rex64"
1650 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1651 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1656 switch (get_attr_type (insn))
1659 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1661 return "mov{b}\t{%h1, %0|%0, %h1}";
1665 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1666 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1667 (ne (symbol_ref "TARGET_MOVX")
1669 (const_string "imovx")
1670 (const_string "imov")))
1672 (if_then_else (eq_attr "type" "imovx")
1674 (const_string "QI")))])
1676 ;; Stores and loads of ax to arbitrary constant address.
1677 ;; We fake an second form of instruction to force reload to load address
1678 ;; into register when rax is not available
1679 (define_insn "*movabsqi_1_rex64"
1680 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
1681 (match_operand:QI 1 "nonmemory_operand" "a,er"))]
1682 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
1684 movabs{b}\t{%1, %P0|%P0, %1}
1685 mov{b}\t{%1, %a0|%a0, %1}"
1686 [(set_attr "type" "imov")
1687 (set_attr "modrm" "0,*")
1688 (set_attr "length_address" "8,0")
1689 (set_attr "length_immediate" "0,*")
1690 (set_attr "memory" "store")
1691 (set_attr "mode" "QI")])
1693 (define_insn "*movabsqi_2_rex64"
1694 [(set (match_operand:QI 0 "register_operand" "=a,r")
1695 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1696 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
1698 movabs{b}\t{%P1, %0|%0, %P1}
1699 mov{b}\t{%a1, %0|%0, %a1}"
1700 [(set_attr "type" "imov")
1701 (set_attr "modrm" "0,*")
1702 (set_attr "length_address" "8,0")
1703 (set_attr "length_immediate" "0")
1704 (set_attr "memory" "load")
1705 (set_attr "mode" "QI")])
1707 (define_insn "*movdi_extzv_1"
1708 [(set (match_operand:DI 0 "register_operand" "=R")
1709 (zero_extract:DI (match_operand 1 "ext_register_operand" "Q")
1713 "movz{bl|x}\t{%h1, %k0|%k0, %h1}"
1714 [(set_attr "type" "imovx")
1715 (set_attr "mode" "DI")])
1717 (define_insn "*movsi_extzv_1"
1718 [(set (match_operand:SI 0 "register_operand" "=R")
1719 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1723 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1724 [(set_attr "type" "imovx")
1725 (set_attr "mode" "SI")])
1727 (define_insn "*movqi_extzv_2"
1728 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1729 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1734 switch (get_attr_type (insn))
1737 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1739 return "mov{b}\t{%h1, %0|%0, %h1}";
1743 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1744 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1745 (ne (symbol_ref "TARGET_MOVX")
1747 (const_string "imovx")
1748 (const_string "imov")))
1750 (if_then_else (eq_attr "type" "imovx")
1752 (const_string "QI")))])
1754 (define_insn "*movqi_extzv_2_rex64"
1755 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1756 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1761 switch (get_attr_type (insn))
1764 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1766 return "mov{b}\t{%h1, %0|%0, %h1}";
1770 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1771 (ne (symbol_ref "TARGET_MOVX")
1773 (const_string "imovx")
1774 (const_string "imov")))
1776 (if_then_else (eq_attr "type" "imovx")
1778 (const_string "QI")))])
1780 (define_insn "movsi_insv_1"
1781 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1784 (match_operand:SI 1 "general_operand" "Qmn"))]
1786 "mov{b}\t{%b1, %h0|%h0, %b1}"
1787 [(set_attr "type" "imov")
1788 (set_attr "mode" "QI")])
1790 (define_insn "movdi_insv_1_rex64"
1791 [(set (zero_extract:DI (match_operand 0 "ext_register_operand" "+Q")
1794 (match_operand:DI 1 "nonmemory_operand" "Qn"))]
1796 "mov{b}\t{%b1, %h0|%h0, %b1}"
1797 [(set_attr "type" "imov")
1798 (set_attr "mode" "QI")])
1800 (define_insn "*movqi_insv_2"
1801 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1804 (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1807 "mov{b}\t{%h1, %h0|%h0, %h1}"
1808 [(set_attr "type" "imov")
1809 (set_attr "mode" "QI")])
1811 (define_expand "movdi"
1812 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1813 (match_operand:DI 1 "general_operand" ""))]
1815 "ix86_expand_move (DImode, operands); DONE;")
1817 (define_insn "*pushdi"
1818 [(set (match_operand:DI 0 "push_operand" "=<")
1819 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1823 (define_insn "*pushdi2_rex64"
1824 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1825 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1830 [(set_attr "type" "push,multi")
1831 (set_attr "mode" "DI")])
1833 ;; Convert impossible pushes of immediate to existing instructions.
1834 ;; First try to get scratch register and go through it. In case this
1835 ;; fails, push sign extended lower part first and then overwrite
1836 ;; upper part by 32bit move.
1838 [(match_scratch:DI 2 "r")
1839 (set (match_operand:DI 0 "push_operand" "")
1840 (match_operand:DI 1 "immediate_operand" ""))]
1841 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1842 && !x86_64_immediate_operand (operands[1], DImode)"
1843 [(set (match_dup 2) (match_dup 1))
1844 (set (match_dup 0) (match_dup 2))]
1847 ;; We need to define this as both peepholer and splitter for case
1848 ;; peephole2 pass is not run.
1849 ;; "&& 1" is needed to keep it from matching the previous pattern.
1851 [(set (match_operand:DI 0 "push_operand" "")
1852 (match_operand:DI 1 "immediate_operand" ""))]
1853 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1854 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1855 [(set (match_dup 0) (match_dup 1))
1856 (set (match_dup 2) (match_dup 3))]
1857 "split_di (operands + 1, 1, operands + 2, operands + 3);
1858 operands[1] = gen_lowpart (DImode, operands[2]);
1859 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1864 [(set (match_operand:DI 0 "push_operand" "")
1865 (match_operand:DI 1 "immediate_operand" ""))]
1866 "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
1867 ? flow2_completed : reload_completed)
1868 && !symbolic_operand (operands[1], DImode)
1869 && !x86_64_immediate_operand (operands[1], DImode)"
1870 [(set (match_dup 0) (match_dup 1))
1871 (set (match_dup 2) (match_dup 3))]
1872 "split_di (operands + 1, 1, operands + 2, operands + 3);
1873 operands[1] = gen_lowpart (DImode, operands[2]);
1874 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1878 (define_insn "*pushdi2_prologue_rex64"
1879 [(set (match_operand:DI 0 "push_operand" "=<")
1880 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1881 (clobber (mem:BLK (scratch)))]
1884 [(set_attr "type" "push")
1885 (set_attr "mode" "DI")])
1887 (define_insn "*popdi1_epilogue_rex64"
1888 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1889 (mem:DI (reg:DI SP_REG)))
1890 (set (reg:DI SP_REG)
1891 (plus:DI (reg:DI SP_REG) (const_int 8)))
1892 (clobber (mem:BLK (scratch)))]
1895 [(set_attr "type" "pop")
1896 (set_attr "mode" "DI")])
1898 (define_insn "popdi1"
1899 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1900 (mem:DI (reg:DI SP_REG)))
1901 (set (reg:DI SP_REG)
1902 (plus:DI (reg:DI SP_REG) (const_int 8)))]
1905 [(set_attr "type" "pop")
1906 (set_attr "mode" "DI")])
1908 (define_insn "*movdi_xor_rex64"
1909 [(set (match_operand:DI 0 "register_operand" "=r")
1910 (match_operand:DI 1 "const0_operand" "i"))
1911 (clobber (reg:CC FLAGS_REG))]
1912 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1913 && reload_completed"
1914 "xor{l}\t{%k0, %k0|%k0, %k0}"
1915 [(set_attr "type" "alu1")
1916 (set_attr "mode" "SI")
1917 (set_attr "length_immediate" "0")])
1919 (define_insn "*movdi_or_rex64"
1920 [(set (match_operand:DI 0 "register_operand" "=r")
1921 (match_operand:DI 1 "const_int_operand" "i"))
1922 (clobber (reg:CC FLAGS_REG))]
1923 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1925 && operands[1] == constm1_rtx"
1927 operands[1] = constm1_rtx;
1928 return "or{q}\t{%1, %0|%0, %1}";
1930 [(set_attr "type" "alu1")
1931 (set_attr "mode" "DI")
1932 (set_attr "length_immediate" "1")])
1934 (define_insn "*movdi_2"
1935 [(set (match_operand:DI 0 "nonimmediate_operand"
1936 "=r ,o ,*y,m*y,*y,*Y,m ,*Y,*Y,*x,m ,*x,*x")
1937 (match_operand:DI 1 "general_operand"
1938 "riFo,riF,C ,*y ,m ,C ,*Y,*Y,m ,C ,*x,*x,m "))]
1939 "!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1944 movq\t{%1, %0|%0, %1}
1945 movq\t{%1, %0|%0, %1}
1947 movq\t{%1, %0|%0, %1}
1948 movdqa\t{%1, %0|%0, %1}
1949 movq\t{%1, %0|%0, %1}
1951 movlps\t{%1, %0|%0, %1}
1952 movaps\t{%1, %0|%0, %1}
1953 movlps\t{%1, %0|%0, %1}"
1954 [(set_attr "type" "*,*,mmx,mmxmov,mmxmov,sselog1,ssemov,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov")
1955 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,TI,DI,V4SF,V2SF,V4SF,V2SF")])
1958 [(set (match_operand:DI 0 "push_operand" "")
1959 (match_operand:DI 1 "general_operand" ""))]
1960 "!TARGET_64BIT && reload_completed
1961 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1963 "ix86_split_long_move (operands); DONE;")
1965 ;; %%% This multiword shite has got to go.
1967 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1968 (match_operand:DI 1 "general_operand" ""))]
1969 "!TARGET_64BIT && reload_completed
1970 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1971 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1973 "ix86_split_long_move (operands); DONE;")
1975 (define_insn "*movdi_1_rex64"
1976 [(set (match_operand:DI 0 "nonimmediate_operand"
1977 "=r,r ,r,m ,!m,*y,*y,?rm,?*y,*x,*x,?rm,?*x,?*x,?*y")
1978 (match_operand:DI 1 "general_operand"
1979 "Z ,rem,i,re,n ,C ,*y,*y ,rm ,C ,*x,*x ,rm ,*y ,*x"))]
1980 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
1982 switch (get_attr_type (insn))
1985 if (which_alternative == 13)
1986 return "movq2dq\t{%1, %0|%0, %1}";
1988 return "movdq2q\t{%1, %0|%0, %1}";
1990 if (get_attr_mode (insn) == MODE_TI)
1991 return "movdqa\t{%1, %0|%0, %1}";
1994 /* Moves from and into integer register is done using movd opcode with
1996 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1997 return "movd\t{%1, %0|%0, %1}";
1998 return "movq\t{%1, %0|%0, %1}";
2001 return "pxor\t%0, %0";
2005 return "lea{q}\t{%a1, %0|%0, %a1}";
2007 gcc_assert (!flag_pic || LEGITIMATE_PIC_OPERAND_P (operands[1]));
2008 if (get_attr_mode (insn) == MODE_SI)
2009 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2010 else if (which_alternative == 2)
2011 return "movabs{q}\t{%1, %0|%0, %1}";
2013 return "mov{q}\t{%1, %0|%0, %1}";
2017 (cond [(eq_attr "alternative" "5")
2018 (const_string "mmxadd")
2019 (eq_attr "alternative" "6,7,8")
2020 (const_string "mmxmov")
2021 (eq_attr "alternative" "9")
2022 (const_string "sselog1")
2023 (eq_attr "alternative" "10,11,12")
2024 (const_string "ssemov")
2025 (eq_attr "alternative" "13,14")
2026 (const_string "ssecvt")
2027 (eq_attr "alternative" "4")
2028 (const_string "multi")
2029 (match_operand:DI 1 "pic_32bit_operand" "")
2030 (const_string "lea")
2032 (const_string "imov")))
2033 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*,*,*,*,*")
2034 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*,*,*,*,*")
2035 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,DI,TI,TI,DI,DI,DI,DI")])
2037 ;; Stores and loads of ax to arbitrary constant address.
2038 ;; We fake an second form of instruction to force reload to load address
2039 ;; into register when rax is not available
2040 (define_insn "*movabsdi_1_rex64"
2041 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
2042 (match_operand:DI 1 "nonmemory_operand" "a,er"))]
2043 "TARGET_64BIT && ix86_check_movabs (insn, 0)"
2045 movabs{q}\t{%1, %P0|%P0, %1}
2046 mov{q}\t{%1, %a0|%a0, %1}"
2047 [(set_attr "type" "imov")
2048 (set_attr "modrm" "0,*")
2049 (set_attr "length_address" "8,0")
2050 (set_attr "length_immediate" "0,*")
2051 (set_attr "memory" "store")
2052 (set_attr "mode" "DI")])
2054 (define_insn "*movabsdi_2_rex64"
2055 [(set (match_operand:DI 0 "register_operand" "=a,r")
2056 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2057 "TARGET_64BIT && ix86_check_movabs (insn, 1)"
2059 movabs{q}\t{%P1, %0|%0, %P1}
2060 mov{q}\t{%a1, %0|%0, %a1}"
2061 [(set_attr "type" "imov")
2062 (set_attr "modrm" "0,*")
2063 (set_attr "length_address" "8,0")
2064 (set_attr "length_immediate" "0")
2065 (set_attr "memory" "load")
2066 (set_attr "mode" "DI")])
2068 ;; Convert impossible stores of immediate to existing instructions.
2069 ;; First try to get scratch register and go through it. In case this
2070 ;; fails, move by 32bit parts.
2072 [(match_scratch:DI 2 "r")
2073 (set (match_operand:DI 0 "memory_operand" "")
2074 (match_operand:DI 1 "immediate_operand" ""))]
2075 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2076 && !x86_64_immediate_operand (operands[1], DImode)"
2077 [(set (match_dup 2) (match_dup 1))
2078 (set (match_dup 0) (match_dup 2))]
2081 ;; We need to define this as both peepholer and splitter for case
2082 ;; peephole2 pass is not run.
2083 ;; "&& 1" is needed to keep it from matching the previous pattern.
2085 [(set (match_operand:DI 0 "memory_operand" "")
2086 (match_operand:DI 1 "immediate_operand" ""))]
2087 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2088 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2089 [(set (match_dup 2) (match_dup 3))
2090 (set (match_dup 4) (match_dup 5))]
2091 "split_di (operands, 2, operands + 2, operands + 4);")
2094 [(set (match_operand:DI 0 "memory_operand" "")
2095 (match_operand:DI 1 "immediate_operand" ""))]
2096 "TARGET_64BIT && ((optimize > 0 && flag_peephole2)
2097 ? flow2_completed : reload_completed)
2098 && !symbolic_operand (operands[1], DImode)
2099 && !x86_64_immediate_operand (operands[1], DImode)"
2100 [(set (match_dup 2) (match_dup 3))
2101 (set (match_dup 4) (match_dup 5))]
2102 "split_di (operands, 2, operands + 2, operands + 4);")
2104 (define_insn "*swapdi_rex64"
2105 [(set (match_operand:DI 0 "register_operand" "+r")
2106 (match_operand:DI 1 "register_operand" "+r"))
2111 [(set_attr "type" "imov")
2112 (set_attr "mode" "DI")
2113 (set_attr "pent_pair" "np")
2114 (set_attr "athlon_decode" "vector")])
2116 (define_expand "movti"
2117 [(set (match_operand:TI 0 "nonimmediate_operand" "")
2118 (match_operand:TI 1 "nonimmediate_operand" ""))]
2119 "TARGET_SSE || TARGET_64BIT"
2122 ix86_expand_move (TImode, operands);
2124 ix86_expand_vector_move (TImode, operands);
2128 (define_insn "*movti_internal"
2129 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
2130 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
2131 "TARGET_SSE && !TARGET_64BIT
2132 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2134 switch (which_alternative)
2137 if (get_attr_mode (insn) == MODE_V4SF)
2138 return "xorps\t%0, %0";
2140 return "pxor\t%0, %0";
2143 if (get_attr_mode (insn) == MODE_V4SF)
2144 return "movaps\t{%1, %0|%0, %1}";
2146 return "movdqa\t{%1, %0|%0, %1}";
2151 [(set_attr "type" "ssemov,ssemov,ssemov")
2153 (cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0))
2154 (const_string "V4SF")
2156 (eq_attr "alternative" "0,1")
2158 (ne (symbol_ref "optimize_size")
2160 (const_string "V4SF")
2161 (const_string "TI"))
2162 (eq_attr "alternative" "2")
2164 (ne (symbol_ref "optimize_size")
2166 (const_string "V4SF")
2167 (const_string "TI"))]
2168 (const_string "TI")))])
2170 (define_insn "*movti_rex64"
2171 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
2172 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
2174 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2176 switch (which_alternative)
2182 if (get_attr_mode (insn) == MODE_V4SF)
2183 return "xorps\t%0, %0";
2185 return "pxor\t%0, %0";
2188 if (get_attr_mode (insn) == MODE_V4SF)
2189 return "movaps\t{%1, %0|%0, %1}";
2191 return "movdqa\t{%1, %0|%0, %1}";
2196 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
2198 (cond [(eq_attr "alternative" "2,3")
2200 (ne (symbol_ref "optimize_size")
2202 (const_string "V4SF")
2203 (const_string "TI"))
2204 (eq_attr "alternative" "4")
2206 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
2208 (ne (symbol_ref "optimize_size")
2210 (const_string "V4SF")
2211 (const_string "TI"))]
2212 (const_string "DI")))])
2215 [(set (match_operand:TI 0 "nonimmediate_operand" "")
2216 (match_operand:TI 1 "general_operand" ""))]
2217 "reload_completed && !SSE_REG_P (operands[0])
2218 && !SSE_REG_P (operands[1])"
2220 "ix86_split_long_move (operands); DONE;")
2222 (define_expand "movsf"
2223 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2224 (match_operand:SF 1 "general_operand" ""))]
2226 "ix86_expand_move (SFmode, operands); DONE;")
2228 (define_insn "*pushsf"
2229 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2230 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2233 /* Anything else should be already split before reg-stack. */
2234 gcc_assert (which_alternative == 1);
2235 return "push{l}\t%1";
2237 [(set_attr "type" "multi,push,multi")
2238 (set_attr "unit" "i387,*,*")
2239 (set_attr "mode" "SF,SI,SF")])
2241 (define_insn "*pushsf_rex64"
2242 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2243 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2246 /* Anything else should be already split before reg-stack. */
2247 gcc_assert (which_alternative == 1);
2248 return "push{q}\t%q1";
2250 [(set_attr "type" "multi,push,multi")
2251 (set_attr "unit" "i387,*,*")
2252 (set_attr "mode" "SF,DI,SF")])
2255 [(set (match_operand:SF 0 "push_operand" "")
2256 (match_operand:SF 1 "memory_operand" ""))]
2258 && GET_CODE (operands[1]) == MEM
2259 && constant_pool_reference_p (operands[1])"
2262 "operands[1] = avoid_constant_pool_reference (operands[1]);")
2265 ;; %%% Kill this when call knows how to work this out.
2267 [(set (match_operand:SF 0 "push_operand" "")
2268 (match_operand:SF 1 "any_fp_register_operand" ""))]
2270 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
2271 (set (mem:SF (reg:SI SP_REG)) (match_dup 1))])
2274 [(set (match_operand:SF 0 "push_operand" "")
2275 (match_operand:SF 1 "any_fp_register_operand" ""))]
2277 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2278 (set (mem:SF (reg:DI SP_REG)) (match_dup 1))])
2280 (define_insn "*movsf_1"
2281 [(set (match_operand:SF 0 "nonimmediate_operand"
2282 "=f#xr,m ,f#xr,r#xf ,m ,x#rf,x#rf,x#rf ,m ,!*y,!rm,!*y")
2283 (match_operand:SF 1 "general_operand"
2284 "fm#rx,f#rx,G ,rmF#fx,Fr#fx,C ,x ,xm#rf,x#rf,rm ,*y ,*y"))]
2285 "!(MEM_P (operands[0]) && MEM_P (operands[1]))
2286 && (reload_in_progress || reload_completed
2287 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2288 || GET_CODE (operands[1]) != CONST_DOUBLE
2289 || memory_operand (operands[0], SFmode))"
2291 switch (which_alternative)
2294 return output_387_reg_move (insn, operands);
2297 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2298 return "fstp%z0\t%y0";
2300 return "fst%z0\t%y0";
2303 return standard_80387_constant_opcode (operands[1]);
2307 return "mov{l}\t{%1, %0|%0, %1}";
2309 if (get_attr_mode (insn) == MODE_TI)
2310 return "pxor\t%0, %0";
2312 return "xorps\t%0, %0";
2314 if (get_attr_mode (insn) == MODE_V4SF)
2315 return "movaps\t{%1, %0|%0, %1}";
2317 return "movss\t{%1, %0|%0, %1}";
2320 return "movss\t{%1, %0|%0, %1}";
2324 return "movd\t{%1, %0|%0, %1}";
2327 return "movq\t{%1, %0|%0, %1}";
2333 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2335 (cond [(eq_attr "alternative" "3,4,9,10")
2337 (eq_attr "alternative" "5")
2339 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2341 (ne (symbol_ref "TARGET_SSE2")
2343 (eq (symbol_ref "optimize_size")
2346 (const_string "V4SF"))
2347 /* For architectures resolving dependencies on
2348 whole SSE registers use APS move to break dependency
2349 chains, otherwise use short move to avoid extra work.
2351 Do the same for architectures resolving dependencies on
2352 the parts. While in DF mode it is better to always handle
2353 just register parts, the SF mode is different due to lack
2354 of instructions to load just part of the register. It is
2355 better to maintain the whole registers in single format
2356 to avoid problems on using packed logical operations. */
2357 (eq_attr "alternative" "6")
2359 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2361 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2363 (const_string "V4SF")
2364 (const_string "SF"))
2365 (eq_attr "alternative" "11")
2366 (const_string "DI")]
2367 (const_string "SF")))])
2369 (define_insn "*swapsf"
2370 [(set (match_operand:SF 0 "fp_register_operand" "+f")
2371 (match_operand:SF 1 "fp_register_operand" "+f"))
2374 "reload_completed || TARGET_80387"
2376 if (STACK_TOP_P (operands[0]))
2381 [(set_attr "type" "fxch")
2382 (set_attr "mode" "SF")])
2384 (define_expand "movdf"
2385 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2386 (match_operand:DF 1 "general_operand" ""))]
2388 "ix86_expand_move (DFmode, operands); DONE;")
2390 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2391 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2392 ;; On the average, pushdf using integers can be still shorter. Allow this
2393 ;; pattern for optimize_size too.
2395 (define_insn "*pushdf_nointeger"
2396 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2397 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2398 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2400 /* This insn should be already split before reg-stack. */
2403 [(set_attr "type" "multi")
2404 (set_attr "unit" "i387,*,*,*")
2405 (set_attr "mode" "DF,SI,SI,DF")])
2407 (define_insn "*pushdf_integer"
2408 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2409 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2410 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2412 /* This insn should be already split before reg-stack. */
2415 [(set_attr "type" "multi")
2416 (set_attr "unit" "i387,*,*")
2417 (set_attr "mode" "DF,SI,DF")])
2419 ;; %%% Kill this when call knows how to work this out.
2421 [(set (match_operand:DF 0 "push_operand" "")
2422 (match_operand:DF 1 "any_fp_register_operand" ""))]
2423 "!TARGET_64BIT && reload_completed"
2424 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
2425 (set (mem:DF (reg:SI SP_REG)) (match_dup 1))]
2429 [(set (match_operand:DF 0 "push_operand" "")
2430 (match_operand:DF 1 "any_fp_register_operand" ""))]
2431 "TARGET_64BIT && reload_completed"
2432 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
2433 (set (mem:DF (reg:DI SP_REG)) (match_dup 1))]
2437 [(set (match_operand:DF 0 "push_operand" "")
2438 (match_operand:DF 1 "general_operand" ""))]
2441 "ix86_split_long_move (operands); DONE;")
2443 ;; Moving is usually shorter when only FP registers are used. This separate
2444 ;; movdf pattern avoids the use of integer registers for FP operations
2445 ;; when optimizing for size.
2447 (define_insn "*movdf_nointeger"
2448 [(set (match_operand:DF 0 "nonimmediate_operand"
2449 "=f#Y,m ,f#Y,*r ,o ,Y*x#f,Y*x#f,Y*x#f ,m ")
2450 (match_operand:DF 1 "general_operand"
2451 "fm#Y,f#Y,G ,*roF,F*r,C ,Y*x#f,HmY*x#f,Y*x#f"))]
2452 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2453 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2454 && (reload_in_progress || reload_completed
2455 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2456 || GET_CODE (operands[1]) != CONST_DOUBLE
2457 || memory_operand (operands[0], DFmode))"
2459 switch (which_alternative)
2462 return output_387_reg_move (insn, operands);
2465 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2466 return "fstp%z0\t%y0";
2468 return "fst%z0\t%y0";
2471 return standard_80387_constant_opcode (operands[1]);
2477 switch (get_attr_mode (insn))
2480 return "xorps\t%0, %0";
2482 return "xorpd\t%0, %0";
2484 return "pxor\t%0, %0";
2491 switch (get_attr_mode (insn))
2494 return "movaps\t{%1, %0|%0, %1}";
2496 return "movapd\t{%1, %0|%0, %1}";
2498 return "movdqa\t{%1, %0|%0, %1}";
2500 return "movq\t{%1, %0|%0, %1}";
2502 return "movsd\t{%1, %0|%0, %1}";
2504 return "movlpd\t{%1, %0|%0, %1}";
2506 return "movlps\t{%1, %0|%0, %1}";
2515 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2517 (cond [(eq_attr "alternative" "0,1,2")
2519 (eq_attr "alternative" "3,4")
2522 /* For SSE1, we have many fewer alternatives. */
2523 (eq (symbol_ref "TARGET_SSE2") (const_int 0))
2524 (cond [(eq_attr "alternative" "5,6")
2525 (const_string "V4SF")
2527 (const_string "V2SF"))
2529 /* xorps is one byte shorter. */
2530 (eq_attr "alternative" "5")
2531 (cond [(ne (symbol_ref "optimize_size")
2533 (const_string "V4SF")
2534 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2538 (const_string "V2DF"))
2540 /* For architectures resolving dependencies on
2541 whole SSE registers use APD move to break dependency
2542 chains, otherwise use short move to avoid extra work.
2544 movaps encodes one byte shorter. */
2545 (eq_attr "alternative" "6")
2547 [(ne (symbol_ref "optimize_size")
2549 (const_string "V4SF")
2550 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2552 (const_string "V2DF")
2554 (const_string "DF"))
2555 /* For architectures resolving dependencies on register
2556 parts we may avoid extra work to zero out upper part
2558 (eq_attr "alternative" "7")
2560 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2562 (const_string "V1DF")
2563 (const_string "DF"))
2565 (const_string "DF")))])
2567 (define_insn "*movdf_integer"
2568 [(set (match_operand:DF 0 "nonimmediate_operand"
2569 "=f#Yr,m ,f#Yr,r#Yf ,o ,Y*x#rf,Y*x#rf,Y*x#rf,m")
2570 (match_operand:DF 1 "general_operand"
2571 "fm#Yr,f#Yr,G ,roF#Yf,Fr#Yf,C ,Y*x#rf,m ,Y*x#rf"))]
2572 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2573 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2574 && (reload_in_progress || reload_completed
2575 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2576 || GET_CODE (operands[1]) != CONST_DOUBLE
2577 || memory_operand (operands[0], DFmode))"
2579 switch (which_alternative)
2582 return output_387_reg_move (insn, operands);
2585 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2586 return "fstp%z0\t%y0";
2588 return "fst%z0\t%y0";
2591 return standard_80387_constant_opcode (operands[1]);
2598 switch (get_attr_mode (insn))
2601 return "xorps\t%0, %0";
2603 return "xorpd\t%0, %0";
2605 return "pxor\t%0, %0";
2612 switch (get_attr_mode (insn))
2615 return "movaps\t{%1, %0|%0, %1}";
2617 return "movapd\t{%1, %0|%0, %1}";
2619 return "movdqa\t{%1, %0|%0, %1}";
2621 return "movq\t{%1, %0|%0, %1}";
2623 return "movsd\t{%1, %0|%0, %1}";
2625 return "movlpd\t{%1, %0|%0, %1}";
2627 return "movlps\t{%1, %0|%0, %1}";
2636 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2638 (cond [(eq_attr "alternative" "0,1,2")
2640 (eq_attr "alternative" "3,4")
2643 /* For SSE1, we have many fewer alternatives. */
2644 (eq (symbol_ref "TARGET_SSE2") (const_int 0))
2645 (cond [(eq_attr "alternative" "5,6")
2646 (const_string "V4SF")
2648 (const_string "V2SF"))
2650 /* xorps is one byte shorter. */
2651 (eq_attr "alternative" "5")
2652 (cond [(ne (symbol_ref "optimize_size")
2654 (const_string "V4SF")
2655 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2659 (const_string "V2DF"))
2661 /* For architectures resolving dependencies on
2662 whole SSE registers use APD move to break dependency
2663 chains, otherwise use short move to avoid extra work.
2665 movaps encodes one byte shorter. */
2666 (eq_attr "alternative" "6")
2668 [(ne (symbol_ref "optimize_size")
2670 (const_string "V4SF")
2671 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2673 (const_string "V2DF")
2675 (const_string "DF"))
2676 /* For architectures resolving dependencies on register
2677 parts we may avoid extra work to zero out upper part
2679 (eq_attr "alternative" "7")
2681 (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
2683 (const_string "V1DF")
2684 (const_string "DF"))
2686 (const_string "DF")))])
2689 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2690 (match_operand:DF 1 "general_operand" ""))]
2692 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2693 && ! (ANY_FP_REG_P (operands[0]) ||
2694 (GET_CODE (operands[0]) == SUBREG
2695 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2696 && ! (ANY_FP_REG_P (operands[1]) ||
2697 (GET_CODE (operands[1]) == SUBREG
2698 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2700 "ix86_split_long_move (operands); DONE;")
2702 (define_insn "*swapdf"
2703 [(set (match_operand:DF 0 "fp_register_operand" "+f")
2704 (match_operand:DF 1 "fp_register_operand" "+f"))
2707 "reload_completed || TARGET_80387"
2709 if (STACK_TOP_P (operands[0]))
2714 [(set_attr "type" "fxch")
2715 (set_attr "mode" "DF")])
2717 (define_expand "movxf"
2718 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2719 (match_operand:XF 1 "general_operand" ""))]
2721 "ix86_expand_move (XFmode, operands); DONE;")
2723 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2724 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2725 ;; Pushing using integer instructions is longer except for constants
2726 ;; and direct memory references.
2727 ;; (assuming that any given constant is pushed only once, but this ought to be
2728 ;; handled elsewhere).
2730 (define_insn "*pushxf_nointeger"
2731 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2732 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2735 /* This insn should be already split before reg-stack. */
2738 [(set_attr "type" "multi")
2739 (set_attr "unit" "i387,*,*")
2740 (set_attr "mode" "XF,SI,SI")])
2742 (define_insn "*pushxf_integer"
2743 [(set (match_operand:XF 0 "push_operand" "=<,<")
2744 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2747 /* This insn should be already split before reg-stack. */
2750 [(set_attr "type" "multi")
2751 (set_attr "unit" "i387,*")
2752 (set_attr "mode" "XF,SI")])
2755 [(set (match_operand 0 "push_operand" "")
2756 (match_operand 1 "general_operand" ""))]
2758 && (GET_MODE (operands[0]) == XFmode
2759 || GET_MODE (operands[0]) == DFmode)
2760 && !ANY_FP_REG_P (operands[1])"
2762 "ix86_split_long_move (operands); DONE;")
2765 [(set (match_operand:XF 0 "push_operand" "")
2766 (match_operand:XF 1 "any_fp_register_operand" ""))]
2768 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
2769 (set (mem:XF (reg:SI SP_REG)) (match_dup 1))]
2770 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2773 [(set (match_operand:XF 0 "push_operand" "")
2774 (match_operand:XF 1 "any_fp_register_operand" ""))]
2776 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
2777 (set (mem:XF (reg:DI SP_REG)) (match_dup 1))]
2778 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
2780 ;; Do not use integer registers when optimizing for size
2781 (define_insn "*movxf_nointeger"
2782 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2783 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2785 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2786 && (reload_in_progress || reload_completed
2787 || GET_CODE (operands[1]) != CONST_DOUBLE
2788 || memory_operand (operands[0], XFmode))"
2790 switch (which_alternative)
2793 return output_387_reg_move (insn, operands);
2796 /* There is no non-popping store to memory for XFmode. So if
2797 we need one, follow the store with a load. */
2798 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2799 return "fstp%z0\t%y0\;fld%z0\t%y0";
2801 return "fstp%z0\t%y0";
2804 return standard_80387_constant_opcode (operands[1]);
2812 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2813 (set_attr "mode" "XF,XF,XF,SI,SI")])
2815 (define_insn "*movxf_integer"
2816 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2817 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2819 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2820 && (reload_in_progress || reload_completed
2821 || GET_CODE (operands[1]) != CONST_DOUBLE
2822 || memory_operand (operands[0], XFmode))"
2824 switch (which_alternative)
2827 return output_387_reg_move (insn, operands);
2830 /* There is no non-popping store to memory for XFmode. So if
2831 we need one, follow the store with a load. */
2832 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2833 return "fstp%z0\t%y0\;fld%z0\t%y0";
2835 return "fstp%z0\t%y0";
2838 return standard_80387_constant_opcode (operands[1]);
2847 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2848 (set_attr "mode" "XF,XF,XF,SI,SI")])
2851 [(set (match_operand 0 "nonimmediate_operand" "")
2852 (match_operand 1 "general_operand" ""))]
2854 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2855 && GET_MODE (operands[0]) == XFmode
2856 && ! (ANY_FP_REG_P (operands[0]) ||
2857 (GET_CODE (operands[0]) == SUBREG
2858 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2859 && ! (ANY_FP_REG_P (operands[1]) ||
2860 (GET_CODE (operands[1]) == SUBREG
2861 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2863 "ix86_split_long_move (operands); DONE;")
2866 [(set (match_operand 0 "register_operand" "")
2867 (match_operand 1 "memory_operand" ""))]
2869 && GET_CODE (operands[1]) == MEM
2870 && (GET_MODE (operands[0]) == XFmode
2871 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2872 && constant_pool_reference_p (operands[1])"
2873 [(set (match_dup 0) (match_dup 1))]
2875 rtx c = avoid_constant_pool_reference (operands[1]);
2876 rtx r = operands[0];
2878 if (GET_CODE (r) == SUBREG)
2883 if (!standard_sse_constant_p (c))
2886 else if (FP_REG_P (r))
2888 if (!standard_80387_constant_p (c))
2891 else if (MMX_REG_P (r))
2897 (define_insn "swapxf"
2898 [(set (match_operand:XF 0 "register_operand" "+f")
2899 (match_operand:XF 1 "register_operand" "+f"))
2904 if (STACK_TOP_P (operands[0]))
2909 [(set_attr "type" "fxch")
2910 (set_attr "mode" "XF")])
2912 (define_expand "movtf"
2913 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2914 (match_operand:TF 1 "nonimmediate_operand" ""))]
2917 ix86_expand_move (TFmode, operands);
2921 (define_insn "*movtf_internal"
2922 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm")
2923 (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
2925 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2927 switch (which_alternative)
2933 if (get_attr_mode (insn) == MODE_V4SF)
2934 return "xorps\t%0, %0";
2936 return "pxor\t%0, %0";
2939 if (get_attr_mode (insn) == MODE_V4SF)
2940 return "movaps\t{%1, %0|%0, %1}";
2942 return "movdqa\t{%1, %0|%0, %1}";
2947 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
2949 (cond [(eq_attr "alternative" "2,3")
2951 (ne (symbol_ref "optimize_size")
2953 (const_string "V4SF")
2954 (const_string "TI"))
2955 (eq_attr "alternative" "4")
2957 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
2959 (ne (symbol_ref "optimize_size")
2961 (const_string "V4SF")
2962 (const_string "TI"))]
2963 (const_string "DI")))])
2966 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2967 (match_operand:TF 1 "general_operand" ""))]
2968 "reload_completed && !SSE_REG_P (operands[0])
2969 && !SSE_REG_P (operands[1])"
2971 "ix86_split_long_move (operands); DONE;")
2973 ;; Zero extension instructions
2975 (define_expand "zero_extendhisi2"
2976 [(set (match_operand:SI 0 "register_operand" "")
2977 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2980 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2982 operands[1] = force_reg (HImode, operands[1]);
2983 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2988 (define_insn "zero_extendhisi2_and"
2989 [(set (match_operand:SI 0 "register_operand" "=r")
2990 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2991 (clobber (reg:CC FLAGS_REG))]
2992 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2994 [(set_attr "type" "alu1")
2995 (set_attr "mode" "SI")])
2998 [(set (match_operand:SI 0 "register_operand" "")
2999 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3000 (clobber (reg:CC FLAGS_REG))]
3001 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3002 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3003 (clobber (reg:CC FLAGS_REG))])]
3006 (define_insn "*zero_extendhisi2_movzwl"
3007 [(set (match_operand:SI 0 "register_operand" "=r")
3008 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3009 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3010 "movz{wl|x}\t{%1, %0|%0, %1}"
3011 [(set_attr "type" "imovx")
3012 (set_attr "mode" "SI")])
3014 (define_expand "zero_extendqihi2"
3016 [(set (match_operand:HI 0 "register_operand" "")
3017 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3018 (clobber (reg:CC FLAGS_REG))])]
3022 (define_insn "*zero_extendqihi2_and"
3023 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3024 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3025 (clobber (reg:CC FLAGS_REG))]
3026 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3028 [(set_attr "type" "alu1")
3029 (set_attr "mode" "HI")])
3031 (define_insn "*zero_extendqihi2_movzbw_and"
3032 [(set (match_operand:HI 0 "register_operand" "=r,r")
3033 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3034 (clobber (reg:CC FLAGS_REG))]
3035 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3037 [(set_attr "type" "imovx,alu1")
3038 (set_attr "mode" "HI")])
3040 ; zero extend to SImode here to avoid partial register stalls
3041 (define_insn "*zero_extendqihi2_movzbl"
3042 [(set (match_operand:HI 0 "register_operand" "=r")
3043 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3044 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3045 "movz{bl|x}\t{%1, %k0|%k0, %k1}"
3046 [(set_attr "type" "imovx")
3047 (set_attr "mode" "SI")])
3049 ;; For the movzbw case strip only the clobber
3051 [(set (match_operand:HI 0 "register_operand" "")
3052 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3053 (clobber (reg:CC FLAGS_REG))]
3055 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3056 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3057 [(set (match_operand:HI 0 "register_operand" "")
3058 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3060 ;; When source and destination does not overlap, clear destination
3061 ;; first and then do the movb
3063 [(set (match_operand:HI 0 "register_operand" "")
3064 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3065 (clobber (reg:CC FLAGS_REG))]
3067 && ANY_QI_REG_P (operands[0])
3068 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3069 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3070 [(set (match_dup 0) (const_int 0))
3071 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3072 "operands[2] = gen_lowpart (QImode, operands[0]);")
3074 ;; Rest is handled by single and.
3076 [(set (match_operand:HI 0 "register_operand" "")
3077 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3078 (clobber (reg:CC FLAGS_REG))]
3080 && true_regnum (operands[0]) == true_regnum (operands[1])"
3081 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3082 (clobber (reg:CC FLAGS_REG))])]
3085 (define_expand "zero_extendqisi2"
3087 [(set (match_operand:SI 0 "register_operand" "")
3088 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3089 (clobber (reg:CC FLAGS_REG))])]
3093 (define_insn "*zero_extendqisi2_and"
3094 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3095 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3096 (clobber (reg:CC FLAGS_REG))]
3097 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3099 [(set_attr "type" "alu1")
3100 (set_attr "mode" "SI")])
3102 (define_insn "*zero_extendqisi2_movzbw_and"
3103 [(set (match_operand:SI 0 "register_operand" "=r,r")
3104 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3105 (clobber (reg:CC FLAGS_REG))]
3106 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3108 [(set_attr "type" "imovx,alu1")
3109 (set_attr "mode" "SI")])
3111 (define_insn "*zero_extendqisi2_movzbw"
3112 [(set (match_operand:SI 0 "register_operand" "=r")
3113 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3114 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3115 "movz{bl|x}\t{%1, %0|%0, %1}"
3116 [(set_attr "type" "imovx")
3117 (set_attr "mode" "SI")])
3119 ;; For the movzbl case strip only the clobber
3121 [(set (match_operand:SI 0 "register_operand" "")
3122 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3123 (clobber (reg:CC FLAGS_REG))]
3125 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3126 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3128 (zero_extend:SI (match_dup 1)))])
3130 ;; When source and destination does not overlap, clear destination
3131 ;; first and then do the movb
3133 [(set (match_operand:SI 0 "register_operand" "")
3134 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3135 (clobber (reg:CC FLAGS_REG))]
3137 && ANY_QI_REG_P (operands[0])
3138 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3139 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3140 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3141 [(set (match_dup 0) (const_int 0))
3142 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3143 "operands[2] = gen_lowpart (QImode, operands[0]);")
3145 ;; Rest is handled by single and.
3147 [(set (match_operand:SI 0 "register_operand" "")
3148 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3149 (clobber (reg:CC FLAGS_REG))]
3151 && true_regnum (operands[0]) == true_regnum (operands[1])"
3152 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3153 (clobber (reg:CC FLAGS_REG))])]
3156 ;; %%% Kill me once multi-word ops are sane.
3157 (define_expand "zero_extendsidi2"
3158 [(set (match_operand:DI 0 "register_operand" "=r")
3159 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3163 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3168 (define_insn "zero_extendsidi2_32"
3169 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,?*y,?*Y")
3170 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
3171 (clobber (reg:CC FLAGS_REG))]
3177 movd\t{%1, %0|%0, %1}
3178 movd\t{%1, %0|%0, %1}"
3179 [(set_attr "mode" "SI,SI,SI,DI,TI")
3180 (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
3182 (define_insn "zero_extendsidi2_rex64"
3183 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*y,?*Y")
3184 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))]
3187 mov\t{%k1, %k0|%k0, %k1}
3189 movd\t{%1, %0|%0, %1}
3190 movd\t{%1, %0|%0, %1}"
3191 [(set_attr "type" "imovx,imov,mmxmov,ssemov")
3192 (set_attr "mode" "SI,DI,SI,SI")])
3195 [(set (match_operand:DI 0 "memory_operand" "")
3196 (zero_extend:DI (match_dup 0)))]
3198 [(set (match_dup 4) (const_int 0))]
3199 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3202 [(set (match_operand:DI 0 "register_operand" "")
3203 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3204 (clobber (reg:CC FLAGS_REG))]
3205 "!TARGET_64BIT && reload_completed
3206 && true_regnum (operands[0]) == true_regnum (operands[1])"
3207 [(set (match_dup 4) (const_int 0))]
3208 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3211 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3212 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3213 (clobber (reg:CC FLAGS_REG))]
3214 "!TARGET_64BIT && reload_completed
3215 && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
3216 [(set (match_dup 3) (match_dup 1))
3217 (set (match_dup 4) (const_int 0))]
3218 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3220 (define_insn "zero_extendhidi2"
3221 [(set (match_operand:DI 0 "register_operand" "=r")
3222 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3224 "movz{wl|x}\t{%1, %k0|%k0, %1}"
3225 [(set_attr "type" "imovx")
3226 (set_attr "mode" "DI")])
3228 (define_insn "zero_extendqidi2"
3229 [(set (match_operand:DI 0 "register_operand" "=r")
3230 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
3232 "movz{bl|x}\t{%1, %k0|%k0, %1}"
3233 [(set_attr "type" "imovx")
3234 (set_attr "mode" "DI")])
3236 ;; Sign extension instructions
3238 (define_expand "extendsidi2"
3239 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3240 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3241 (clobber (reg:CC FLAGS_REG))
3242 (clobber (match_scratch:SI 2 ""))])]
3247 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3252 (define_insn "*extendsidi2_1"
3253 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3254 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3255 (clobber (reg:CC FLAGS_REG))
3256 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3260 (define_insn "extendsidi2_rex64"
3261 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3262 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3266 movs{lq|x}\t{%1,%0|%0, %1}"
3267 [(set_attr "type" "imovx")
3268 (set_attr "mode" "DI")
3269 (set_attr "prefix_0f" "0")
3270 (set_attr "modrm" "0,1")])
3272 (define_insn "extendhidi2"
3273 [(set (match_operand:DI 0 "register_operand" "=r")
3274 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3276 "movs{wq|x}\t{%1,%0|%0, %1}"
3277 [(set_attr "type" "imovx")
3278 (set_attr "mode" "DI")])
3280 (define_insn "extendqidi2"
3281 [(set (match_operand:DI 0 "register_operand" "=r")
3282 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3284 "movs{bq|x}\t{%1,%0|%0, %1}"
3285 [(set_attr "type" "imovx")
3286 (set_attr "mode" "DI")])
3288 ;; Extend to memory case when source register does die.
3290 [(set (match_operand:DI 0 "memory_operand" "")
3291 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3292 (clobber (reg:CC FLAGS_REG))
3293 (clobber (match_operand:SI 2 "register_operand" ""))]
3295 && dead_or_set_p (insn, operands[1])
3296 && !reg_mentioned_p (operands[1], operands[0]))"
3297 [(set (match_dup 3) (match_dup 1))
3298 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3299 (clobber (reg:CC FLAGS_REG))])
3300 (set (match_dup 4) (match_dup 1))]
3301 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3303 ;; Extend to memory case when source register does not die.
3305 [(set (match_operand:DI 0 "memory_operand" "")
3306 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3307 (clobber (reg:CC FLAGS_REG))
3308 (clobber (match_operand:SI 2 "register_operand" ""))]
3312 split_di (&operands[0], 1, &operands[3], &operands[4]);
3314 emit_move_insn (operands[3], operands[1]);
3316 /* Generate a cltd if possible and doing so it profitable. */
3317 if (true_regnum (operands[1]) == 0
3318 && true_regnum (operands[2]) == 1
3319 && (optimize_size || TARGET_USE_CLTD))
3321 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3325 emit_move_insn (operands[2], operands[1]);
3326 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3328 emit_move_insn (operands[4], operands[2]);
3332 ;; Extend to register case. Optimize case where source and destination
3333 ;; registers match and cases where we can use cltd.
3335 [(set (match_operand:DI 0 "register_operand" "")
3336 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3337 (clobber (reg:CC FLAGS_REG))
3338 (clobber (match_scratch:SI 2 ""))]
3342 split_di (&operands[0], 1, &operands[3], &operands[4]);
3344 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3345 emit_move_insn (operands[3], operands[1]);
3347 /* Generate a cltd if possible and doing so it profitable. */
3348 if (true_regnum (operands[3]) == 0
3349 && (optimize_size || TARGET_USE_CLTD))
3351 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3355 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3356 emit_move_insn (operands[4], operands[1]);
3358 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3362 (define_insn "extendhisi2"
3363 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3364 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3367 switch (get_attr_prefix_0f (insn))
3370 return "{cwtl|cwde}";
3372 return "movs{wl|x}\t{%1,%0|%0, %1}";
3375 [(set_attr "type" "imovx")
3376 (set_attr "mode" "SI")
3377 (set (attr "prefix_0f")
3378 ;; movsx is short decodable while cwtl is vector decoded.
3379 (if_then_else (and (eq_attr "cpu" "!k6")
3380 (eq_attr "alternative" "0"))
3382 (const_string "1")))
3384 (if_then_else (eq_attr "prefix_0f" "0")
3386 (const_string "1")))])
3388 (define_insn "*extendhisi2_zext"
3389 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3391 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3394 switch (get_attr_prefix_0f (insn))
3397 return "{cwtl|cwde}";
3399 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3402 [(set_attr "type" "imovx")
3403 (set_attr "mode" "SI")
3404 (set (attr "prefix_0f")
3405 ;; movsx is short decodable while cwtl is vector decoded.
3406 (if_then_else (and (eq_attr "cpu" "!k6")
3407 (eq_attr "alternative" "0"))
3409 (const_string "1")))
3411 (if_then_else (eq_attr "prefix_0f" "0")
3413 (const_string "1")))])
3415 (define_insn "extendqihi2"
3416 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3417 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3420 switch (get_attr_prefix_0f (insn))
3423 return "{cbtw|cbw}";
3425 return "movs{bw|x}\t{%1,%0|%0, %1}";
3428 [(set_attr "type" "imovx")
3429 (set_attr "mode" "HI")
3430 (set (attr "prefix_0f")
3431 ;; movsx is short decodable while cwtl is vector decoded.
3432 (if_then_else (and (eq_attr "cpu" "!k6")
3433 (eq_attr "alternative" "0"))
3435 (const_string "1")))
3437 (if_then_else (eq_attr "prefix_0f" "0")
3439 (const_string "1")))])
3441 (define_insn "extendqisi2"
3442 [(set (match_operand:SI 0 "register_operand" "=r")
3443 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3445 "movs{bl|x}\t{%1,%0|%0, %1}"
3446 [(set_attr "type" "imovx")
3447 (set_attr "mode" "SI")])
3449 (define_insn "*extendqisi2_zext"
3450 [(set (match_operand:DI 0 "register_operand" "=r")
3452 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3454 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3455 [(set_attr "type" "imovx")
3456 (set_attr "mode" "SI")])
3458 ;; Conversions between float and double.
3460 ;; These are all no-ops in the model used for the 80387. So just
3463 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3464 (define_insn "*dummy_extendsfdf2"
3465 [(set (match_operand:DF 0 "push_operand" "=<")
3466 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3471 [(set (match_operand:DF 0 "push_operand" "")
3472 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3474 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
3475 (set (mem:DF (reg:SI SP_REG)) (float_extend:DF (match_dup 1)))])
3478 [(set (match_operand:DF 0 "push_operand" "")
3479 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3481 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
3482 (set (mem:DF (reg:DI SP_REG)) (float_extend:DF (match_dup 1)))])
3484 (define_insn "*dummy_extendsfxf2"
3485 [(set (match_operand:XF 0 "push_operand" "=<")
3486 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3491 [(set (match_operand:XF 0 "push_operand" "")
3492 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3494 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3495 (set (mem:XF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3496 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3499 [(set (match_operand:XF 0 "push_operand" "")
3500 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3502 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3503 (set (mem:DF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3504 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3507 [(set (match_operand:XF 0 "push_operand" "")
3508 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3510 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 2)))
3511 (set (mem:DF (reg:SI SP_REG)) (float_extend:XF (match_dup 1)))]
3512 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3515 [(set (match_operand:XF 0 "push_operand" "")
3516 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3518 [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (match_dup 2)))
3519 (set (mem:XF (reg:DI SP_REG)) (float_extend:XF (match_dup 1)))]
3520 "operands[2] = GEN_INT (TARGET_128BIT_LONG_DOUBLE ? -16 : -12);")
3522 (define_expand "extendsfdf2"
3523 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3524 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3525 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
3527 /* ??? Needed for compress_float_constant since all fp constants
3528 are LEGITIMATE_CONSTANT_P. */
3529 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3530 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3531 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3532 operands[1] = force_reg (SFmode, operands[1]);
3535 (define_insn "*extendsfdf2_mixed"
3536 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m#fY,Y#f")
3537 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3538 "TARGET_SSE2 && TARGET_MIX_SSE_I387
3539 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3541 switch (which_alternative)
3544 return output_387_reg_move (insn, operands);
3547 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3548 return "fstp%z0\t%y0";
3550 return "fst%z0\t%y0";
3553 return "cvtss2sd\t{%1, %0|%0, %1}";
3559 [(set_attr "type" "fmov,fmov,ssecvt")
3560 (set_attr "mode" "SF,XF,DF")])
3562 (define_insn "*extendsfdf2_sse"
3563 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y")
3564 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3565 "TARGET_SSE2 && TARGET_SSE_MATH
3566 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3567 "cvtss2sd\t{%1, %0|%0, %1}"
3568 [(set_attr "type" "ssecvt")
3569 (set_attr "mode" "DF")])
3571 (define_insn "*extendsfdf2_i387"
3572 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,m")
3573 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3575 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3577 switch (which_alternative)
3580 return output_387_reg_move (insn, operands);
3583 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3584 return "fstp%z0\t%y0";
3586 return "fst%z0\t%y0";
3592 [(set_attr "type" "fmov")
3593 (set_attr "mode" "SF,XF")])
3595 (define_expand "extendsfxf2"
3596 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3597 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3600 /* ??? Needed for compress_float_constant since all fp constants
3601 are LEGITIMATE_CONSTANT_P. */
3602 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3603 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3604 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3605 operands[1] = force_reg (SFmode, operands[1]);
3608 (define_insn "*extendsfxf2_i387"
3609 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3610 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3612 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3614 switch (which_alternative)
3617 return output_387_reg_move (insn, operands);
3620 /* There is no non-popping store to memory for XFmode. So if
3621 we need one, follow the store with a load. */
3622 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3623 return "fstp%z0\t%y0";
3625 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3631 [(set_attr "type" "fmov")
3632 (set_attr "mode" "SF,XF")])
3634 (define_expand "extenddfxf2"
3635 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3636 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3639 /* ??? Needed for compress_float_constant since all fp constants
3640 are LEGITIMATE_CONSTANT_P. */
3641 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3642 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3643 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3644 operands[1] = force_reg (DFmode, operands[1]);
3647 (define_insn "*extenddfxf2_i387"
3648 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3649 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3651 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3653 switch (which_alternative)
3656 return output_387_reg_move (insn, operands);
3659 /* There is no non-popping store to memory for XFmode. So if
3660 we need one, follow the store with a load. */
3661 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3662 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3664 return "fstp%z0\t%y0";
3670 [(set_attr "type" "fmov")
3671 (set_attr "mode" "DF,XF")])
3673 ;; %%% This seems bad bad news.
3674 ;; This cannot output into an f-reg because there is no way to be sure
3675 ;; of truncating in that case. Otherwise this is just like a simple move
3676 ;; insn. So we pretend we can output to a reg in order to get better
3677 ;; register preferencing, but we really use a stack slot.
3679 ;; Conversion from DFmode to SFmode.
3681 (define_expand "truncdfsf2"
3682 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3684 (match_operand:DF 1 "nonimmediate_operand" "")))]
3685 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
3687 if (MEM_P (operands[0]) && MEM_P (operands[1]))
3688 operands[1] = force_reg (DFmode, operands[1]);
3690 if (TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387)
3692 else if (flag_unsafe_math_optimizations)
3696 rtx temp = assign_386_stack_local (SFmode, SLOT_TEMP);
3697 emit_insn (gen_truncdfsf2_with_temp (operands[0], operands[1], temp));
3702 (define_expand "truncdfsf2_with_temp"
3703 [(parallel [(set (match_operand:SF 0 "" "")
3704 (float_truncate:SF (match_operand:DF 1 "" "")))
3705 (clobber (match_operand:SF 2 "" ""))])]
3708 (define_insn "*truncdfsf_fast_mixed"
3709 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,f,Y")
3711 (match_operand:DF 1 "nonimmediate_operand" "f ,f,Ym")))]
3712 "TARGET_SSE2 && TARGET_MIX_SSE_I387 && flag_unsafe_math_optimizations"
3714 switch (which_alternative)
3717 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3718 return "fstp%z0\t%y0";
3720 return "fst%z0\t%y0";
3722 return output_387_reg_move (insn, operands);
3724 return "cvtsd2ss\t{%1, %0|%0, %1}";
3729 [(set_attr "type" "fmov,fmov,ssecvt")
3730 (set_attr "mode" "SF")])
3732 ;; Yes, this one doesn't depend on flag_unsafe_math_optimizations,
3733 ;; because nothing we do here is unsafe.
3734 (define_insn "*truncdfsf_fast_sse"
3735 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y")
3737 (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
3738 "TARGET_SSE2 && TARGET_SSE_MATH"
3739 "cvtsd2ss\t{%1, %0|%0, %1}"
3740 [(set_attr "type" "ssecvt")
3741 (set_attr "mode" "SF")])
3743 (define_insn "*truncdfsf_fast_i387"
3744 [(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
3746 (match_operand:DF 1 "nonimmediate_operand" "f")))]
3747 "TARGET_80387 && flag_unsafe_math_optimizations"
3748 "* return output_387_reg_move (insn, operands);"
3749 [(set_attr "type" "fmov")
3750 (set_attr "mode" "SF")])
3752 (define_insn "*truncdfsf_mixed"
3753 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r,Y")
3755 (match_operand:DF 1 "nonimmediate_operand" "f ,f ,Ym")))
3756 (clobber (match_operand:SF 2 "memory_operand" "=X,m ,X"))]
3757 "TARGET_MIX_SSE_I387"
3759 switch (which_alternative)
3762 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3763 return "fstp%z0\t%y0";
3765 return "fst%z0\t%y0";
3769 return "cvtsd2ss\t{%1, %0|%0, %1}";
3774 [(set_attr "type" "fmov,multi,ssecvt")
3775 (set_attr "unit" "*,i387,*")
3776 (set_attr "mode" "SF")])
3778 (define_insn "*truncdfsf_i387"
3779 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?fx*r")
3781 (match_operand:DF 1 "nonimmediate_operand" "f,f")))
3782 (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
3785 switch (which_alternative)
3788 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3789 return "fstp%z0\t%y0";
3791 return "fst%z0\t%y0";
3798 [(set_attr "type" "fmov,multi")
3799 (set_attr "unit" "*,i387")
3800 (set_attr "mode" "SF")])
3802 (define_insn "*truncdfsf2_i387_1"
3803 [(set (match_operand:SF 0 "memory_operand" "=m")
3805 (match_operand:DF 1 "register_operand" "f")))]
3807 && !(TARGET_SSE2 && TARGET_SSE_MATH)
3808 && !TARGET_MIX_SSE_I387"
3810 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3811 return "fstp%z0\t%y0";
3813 return "fst%z0\t%y0";
3815 [(set_attr "type" "fmov")
3816 (set_attr "mode" "SF")])
3819 [(set (match_operand:SF 0 "register_operand" "")
3821 (match_operand:DF 1 "fp_register_operand" "")))
3822 (clobber (match_operand 2 "" ""))]
3824 [(set (match_dup 2) (match_dup 1))
3825 (set (match_dup 0) (match_dup 2))]
3827 operands[1] = gen_rtx_REG (SFmode, true_regnum (operands[1]));
3830 ;; Conversion from XFmode to SFmode.
3832 (define_expand "truncxfsf2"
3833 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3835 (match_operand:XF 1 "register_operand" "")))
3836 (clobber (match_dup 2))])]
3839 if (flag_unsafe_math_optimizations)
3841 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SFmode);
3842 emit_insn (gen_truncxfsf2_i387_noop (reg, operands[1]));
3843 if (reg != operands[0])
3844 emit_move_insn (operands[0], reg);
3848 operands[2] = assign_386_stack_local (SFmode, SLOT_TEMP);
3851 (define_insn "*truncxfsf2_mixed"
3852 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3854 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3855 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3856 "TARGET_MIX_SSE_I387"
3858 gcc_assert (!which_alternative);
3859 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3860 return "fstp%z0\t%y0";
3862 return "fst%z0\t%y0";
3864 [(set_attr "type" "fmov,multi,multi,multi")
3865 (set_attr "unit" "*,i387,i387,i387")
3866 (set_attr "mode" "SF")])
3868 (define_insn "truncxfsf2_i387_noop"
3869 [(set (match_operand:SF 0 "register_operand" "=f")
3870 (float_truncate:SF (match_operand:XF 1 "register_operand" "f")))]
3871 "TARGET_80387 && flag_unsafe_math_optimizations"
3873 return output_387_reg_move (insn, operands);
3875 [(set_attr "type" "fmov")
3876 (set_attr "mode" "SF")])
3878 (define_insn "*truncxfsf2_i387"
3879 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#r,?r#f")
3881 (match_operand:XF 1 "register_operand" "f,f,f")))
3882 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m"))]
3885 gcc_assert (!which_alternative);
3886 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3887 return "fstp%z0\t%y0";
3889 return "fst%z0\t%y0";
3891 [(set_attr "type" "fmov,multi,multi")
3892 (set_attr "unit" "*,i387,i387")
3893 (set_attr "mode" "SF")])
3895 (define_insn "*truncxfsf2_i387_1"
3896 [(set (match_operand:SF 0 "memory_operand" "=m")
3898 (match_operand:XF 1 "register_operand" "f")))]
3901 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3902 return "fstp%z0\t%y0";
3904 return "fst%z0\t%y0";
3906 [(set_attr "type" "fmov")
3907 (set_attr "mode" "SF")])
3910 [(set (match_operand:SF 0 "register_operand" "")
3912 (match_operand:XF 1 "register_operand" "")))
3913 (clobber (match_operand:SF 2 "memory_operand" ""))]
3914 "TARGET_80387 && reload_completed"
3915 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3916 (set (match_dup 0) (match_dup 2))]
3920 [(set (match_operand:SF 0 "memory_operand" "")
3922 (match_operand:XF 1 "register_operand" "")))
3923 (clobber (match_operand:SF 2 "memory_operand" ""))]
3925 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3928 ;; Conversion from XFmode to DFmode.
3930 (define_expand "truncxfdf2"
3931 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3933 (match_operand:XF 1 "register_operand" "")))
3934 (clobber (match_dup 2))])]
3937 if (flag_unsafe_math_optimizations)
3939 rtx reg = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DFmode);
3940 emit_insn (gen_truncxfdf2_i387_noop (reg, operands[1]));
3941 if (reg != operands[0])
3942 emit_move_insn (operands[0], reg);
3946 operands[2] = assign_386_stack_local (DFmode, SLOT_TEMP);
3949 (define_insn "*truncxfdf2_mixed"
3950 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
3952 (match_operand:XF 1 "register_operand" "f,f,f,f")))
3953 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
3954 "TARGET_SSE2 && TARGET_MIX_SSE_I387"
3956 gcc_assert (!which_alternative);
3957 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3958 return "fstp%z0\t%y0";
3960 return "fst%z0\t%y0";
3962 [(set_attr "type" "fmov,multi,multi,multi")
3963 (set_attr "unit" "*,i387,i387,i387")
3964 (set_attr "mode" "DF")])
3966 (define_insn "truncxfdf2_i387_noop"
3967 [(set (match_operand:DF 0 "register_operand" "=f")
3968 (float_truncate:DF (match_operand:XF 1 "register_operand" "f")))]
3969 "TARGET_80387 && flag_unsafe_math_optimizations"
3971 return output_387_reg_move (insn, operands);
3973 [(set_attr "type" "fmov")
3974 (set_attr "mode" "DF")])
3976 (define_insn "*truncxfdf2_i387"
3977 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#r,?r#f")
3979 (match_operand:XF 1 "register_operand" "f,f,f")))
3980 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m"))]
3983 gcc_assert (!which_alternative);
3984 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3985 return "fstp%z0\t%y0";
3987 return "fst%z0\t%y0";
3989 [(set_attr "type" "fmov,multi,multi")
3990 (set_attr "unit" "*,i387,i387")
3991 (set_attr "mode" "DF")])
3993 (define_insn "*truncxfdf2_i387_1"
3994 [(set (match_operand:DF 0 "memory_operand" "=m")
3996 (match_operand:XF 1 "register_operand" "f")))]
3999 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4000 return "fstp%z0\t%y0";
4002 return "fst%z0\t%y0";
4004 [(set_attr "type" "fmov")
4005 (set_attr "mode" "DF")])
4008 [(set (match_operand:DF 0 "register_operand" "")
4010 (match_operand:XF 1 "register_operand" "")))
4011 (clobber (match_operand:DF 2 "memory_operand" ""))]
4012 "TARGET_80387 && reload_completed"
4013 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4014 (set (match_dup 0) (match_dup 2))]
4018 [(set (match_operand:DF 0 "memory_operand" "")
4020 (match_operand:XF 1 "register_operand" "")))
4021 (clobber (match_operand:DF 2 "memory_operand" ""))]
4023 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4026 ;; Signed conversion to DImode.
4028 (define_expand "fix_truncxfdi2"
4029 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4030 (fix:DI (match_operand:XF 1 "register_operand" "")))
4031 (clobber (reg:CC FLAGS_REG))])]
4036 emit_insn (gen_fix_truncdi_fisttp_i387_1 (operands[0], operands[1]));
4041 (define_expand "fix_trunc<mode>di2"
4042 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4043 (fix:DI (match_operand:SSEMODEF 1 "register_operand" "")))
4044 (clobber (reg:CC FLAGS_REG))])]
4045 "TARGET_80387 || (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))"
4048 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
4050 emit_insn (gen_fix_truncdi_fisttp_i387_1 (operands[0], operands[1]));
4053 if (TARGET_64BIT && SSE_FLOAT_MODE_P (<MODE>mode))
4055 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4056 emit_insn (gen_fix_trunc<mode>di_sse (out, operands[1]));
4057 if (out != operands[0])
4058 emit_move_insn (operands[0], out);
4063 ;; Signed conversion to SImode.
4065 (define_expand "fix_truncxfsi2"
4066 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4067 (fix:SI (match_operand:XF 1 "register_operand" "")))
4068 (clobber (reg:CC FLAGS_REG))])]
4073 emit_insn (gen_fix_truncsi_fisttp_i387_1 (operands[0], operands[1]));
4078 (define_expand "fix_trunc<mode>si2"
4079 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4080 (fix:SI (match_operand:SSEMODEF 1 "register_operand" "")))
4081 (clobber (reg:CC FLAGS_REG))])]
4082 "TARGET_80387 || SSE_FLOAT_MODE_P (<MODE>mode)"
4085 && !(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH))
4087 emit_insn (gen_fix_truncsi_fisttp_i387_1 (operands[0], operands[1]));
4090 if (SSE_FLOAT_MODE_P (<MODE>mode))
4092 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4093 emit_insn (gen_fix_trunc<mode>si_sse (out, operands[1]));
4094 if (out != operands[0])
4095 emit_move_insn (operands[0], out);
4100 ;; Signed conversion to HImode.
4102 (define_expand "fix_trunc<mode>hi2"
4103 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4104 (fix:HI (match_operand:X87MODEF 1 "register_operand" "")))
4105 (clobber (reg:CC FLAGS_REG))])]
4107 && !(SSE_FLOAT_MODE_P (<MODE>mode) && (!TARGET_FISTTP || TARGET_SSE_MATH))"
4111 emit_insn (gen_fix_trunchi_fisttp_i387_1 (operands[0], operands[1]));
4116 ;; When SSE is available, it is always faster to use it!
4117 (define_insn "fix_truncsfdi_sse"
4118 [(set (match_operand:DI 0 "register_operand" "=r,r")
4119 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4120 "TARGET_64BIT && TARGET_SSE && (!TARGET_FISTTP || TARGET_SSE_MATH)"
4121 "cvttss2si{q}\t{%1, %0|%0, %1}"
4122 [(set_attr "type" "sseicvt")
4123 (set_attr "mode" "SF")
4124 (set_attr "athlon_decode" "double,vector")])
4126 (define_insn "fix_truncdfdi_sse"
4127 [(set (match_operand:DI 0 "register_operand" "=r,r")
4128 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4129 "TARGET_64BIT && TARGET_SSE2 && (!TARGET_FISTTP || TARGET_SSE_MATH)"
4130 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4131 [(set_attr "type" "sseicvt")
4132 (set_attr "mode" "DF")
4133 (set_attr "athlon_decode" "double,vector")])
4135 (define_insn "fix_truncsfsi_sse"
4136 [(set (match_operand:SI 0 "register_operand" "=r,r")
4137 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4138 "TARGET_SSE && (!TARGET_FISTTP || TARGET_SSE_MATH)"
4139 "cvttss2si\t{%1, %0|%0, %1}"
4140 [(set_attr "type" "sseicvt")
4141 (set_attr "mode" "DF")
4142 (set_attr "athlon_decode" "double,vector")])
4144 (define_insn "fix_truncdfsi_sse"
4145 [(set (match_operand:SI 0 "register_operand" "=r,r")
4146 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4147 "TARGET_SSE2 && (!TARGET_FISTTP || TARGET_SSE_MATH)"
4148 "cvttsd2si\t{%1, %0|%0, %1}"
4149 [(set_attr "type" "sseicvt")
4150 (set_attr "mode" "DF")
4151 (set_attr "athlon_decode" "double,vector")])
4153 ;; Avoid vector decoded forms of the instruction.
4155 [(match_scratch:DF 2 "Y")
4156 (set (match_operand:SSEMODEI24 0 "register_operand" "")
4157 (fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
4158 "TARGET_K8 && !optimize_size"
4159 [(set (match_dup 2) (match_dup 1))
4160 (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
4164 [(match_scratch:SF 2 "x")
4165 (set (match_operand:SSEMODEI24 0 "register_operand" "")
4166 (fix:SSEMODEI24 (match_operand:SF 1 "memory_operand" "")))]
4167 "TARGET_K8 && !optimize_size"
4168 [(set (match_dup 2) (match_dup 1))
4169 (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
4172 (define_insn_and_split "fix_trunc<mode>_fisttp_i387_1"
4173 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
4174 (fix:X87MODEI (match_operand 1 "register_operand" "f,f")))]
4176 && FLOAT_MODE_P (GET_MODE (operands[1]))
4177 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4178 && (TARGET_64BIT || <MODE>mode != DImode))
4180 && !(reload_completed || reload_in_progress)"
4185 if (memory_operand (operands[0], VOIDmode))
4186 emit_insn (gen_fix_trunc<mode>_i387_fisttp (operands[0], operands[1]));
4189 operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
4190 emit_insn (gen_fix_trunc<mode>_i387_fisttp_with_temp (operands[0],
4196 [(set_attr "type" "fisttp")
4197 (set_attr "mode" "<MODE>")])
4199 (define_insn "fix_trunc<mode>_i387_fisttp"
4200 [(set (match_operand:X87MODEI 0 "memory_operand" "=m")
4201 (fix:X87MODEI (match_operand 1 "register_operand" "f")))
4202 (clobber (match_scratch:XF 2 "=&1f"))]
4204 && FLOAT_MODE_P (GET_MODE (operands[1]))
4205 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4206 && (TARGET_64BIT || <MODE>mode != DImode))
4207 && TARGET_SSE_MATH)"
4208 "* return output_fix_trunc (insn, operands, 1);"
4209 [(set_attr "type" "fisttp")
4210 (set_attr "mode" "<MODE>")])
4212 (define_insn "fix_trunc<mode>_i387_fisttp_with_temp"
4213 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
4214 (fix:X87MODEI (match_operand 1 "register_operand" "f,f")))
4215 (clobber (match_operand:X87MODEI 2 "memory_operand" "=m,m"))
4216 (clobber (match_scratch:XF 3 "=&1f,&1f"))]
4218 && FLOAT_MODE_P (GET_MODE (operands[1]))
4219 && !((SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4220 && (TARGET_64BIT || <MODE>mode != DImode))
4221 && TARGET_SSE_MATH)"
4223 [(set_attr "type" "fisttp")
4224 (set_attr "mode" "<MODE>")])
4227 [(set (match_operand:X87MODEI 0 "register_operand" "")
4228 (fix:X87MODEI (match_operand 1 "register_operand" "")))
4229 (clobber (match_operand:X87MODEI 2 "memory_operand" ""))
4230 (clobber (match_scratch 3 ""))]
4232 [(parallel [(set (match_dup 2) (fix:X87MODEI (match_dup 1)))
4233 (clobber (match_dup 3))])
4234 (set (match_dup 0) (match_dup 2))]
4238 [(set (match_operand:X87MODEI 0 "memory_operand" "")
4239 (fix:X87MODEI (match_operand 1 "register_operand" "")))
4240 (clobber (match_operand:X87MODEI 2 "memory_operand" ""))
4241 (clobber (match_scratch 3 ""))]
4243 [(parallel [(set (match_dup 0) (fix:X87MODEI (match_dup 1)))
4244 (clobber (match_dup 3))])]
4247 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4248 ;; of the machinery. Please note the clobber of FLAGS_REG. In i387 control
4249 ;; word calculation (inserted by LCM in mode switching pass) a FLAGS_REG
4250 ;; clobbering insns can be used. Look at emit_i387_cw_initialization ()
4251 ;; function in i386.c.
4252 (define_insn_and_split "*fix_trunc<mode>_i387_1"
4253 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
4254 (fix:X87MODEI (match_operand 1 "register_operand" "f,f")))
4255 (clobber (reg:CC FLAGS_REG))]
4256 "TARGET_80387 && !TARGET_FISTTP
4257 && FLOAT_MODE_P (GET_MODE (operands[1]))
4258 && !(SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
4259 && (TARGET_64BIT || <MODE>mode != DImode))
4260 && !(reload_completed || reload_in_progress)"
4265 ix86_optimize_mode_switching[I387_TRUNC] = 1;
4267 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
4268 operands[3] = assign_386_stack_local (HImode, SLOT_CW_TRUNC);
4269 if (memory_operand (operands[0], VOIDmode))
4270 emit_insn (gen_fix_trunc<mode>_i387 (operands[0], operands[1],
4271 operands[2], operands[3]));
4274 operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
4275 emit_insn (gen_fix_trunc<mode>_i387_with_temp (operands[0], operands[1],
4276 operands[2], operands[3],
4281 [(set_attr "type" "fistp")
4282 (set_attr "i387_cw" "trunc")
4283 (set_attr "mode" "<MODE>")])
4285 (define_insn "fix_truncdi_i387"
4286 [(set (match_operand:DI 0 "memory_operand" "=m")
4287 (fix:DI (match_operand 1 "register_operand" "f")))
4288 (use (match_operand:HI 2 "memory_operand" "m"))
4289 (use (match_operand:HI 3 "memory_operand" "m"))
4290 (clobber (match_scratch:XF 4 "=&1f"))]
4291 "TARGET_80387 && !TARGET_FISTTP
4292 && FLOAT_MODE_P (GET_MODE (operands[1]))
4293 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4294 "* return output_fix_trunc (insn, operands, 0);"
4295 [(set_attr "type" "fistp")
4296 (set_attr "i387_cw" "trunc")
4297 (set_attr "mode" "DI")])
4299 (define_insn "fix_truncdi_i387_with_temp"
4300 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4301 (fix:DI (match_operand 1 "register_operand" "f,f")))
4302 (use (match_operand:HI 2 "memory_operand" "m,m"))
4303 (use (match_operand:HI 3 "memory_operand" "m,m"))
4304 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4305 (clobber (match_scratch:XF 5 "=&1f,&1f"))]
4306 "TARGET_80387 && !TARGET_FISTTP
4307 && FLOAT_MODE_P (GET_MODE (operands[1]))
4308 && !(TARGET_64BIT && SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4310 [(set_attr "type" "fistp")
4311 (set_attr "i387_cw" "trunc")
4312 (set_attr "mode" "DI")])
4315 [(set (match_operand:DI 0 "register_operand" "")
4316 (fix:DI (match_operand 1 "register_operand" "")))
4317 (use (match_operand:HI 2 "memory_operand" ""))
4318 (use (match_operand:HI 3 "memory_operand" ""))
4319 (clobber (match_operand:DI 4 "memory_operand" ""))
4320 (clobber (match_scratch 5 ""))]
4322 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4325 (clobber (match_dup 5))])
4326 (set (match_dup 0) (match_dup 4))]
4330 [(set (match_operand:DI 0 "memory_operand" "")
4331 (fix:DI (match_operand 1 "register_operand" "")))
4332 (use (match_operand:HI 2 "memory_operand" ""))
4333 (use (match_operand:HI 3 "memory_operand" ""))
4334 (clobber (match_operand:DI 4 "memory_operand" ""))
4335 (clobber (match_scratch 5 ""))]
4337 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4340 (clobber (match_dup 5))])]
4343 (define_insn "fix_trunc<mode>_i387"
4344 [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
4345 (fix:X87MODEI12 (match_operand 1 "register_operand" "f")))
4346 (use (match_operand:HI 2 "memory_operand" "m"))
4347 (use (match_operand:HI 3 "memory_operand" "m"))]
4348 "TARGET_80387 && !TARGET_FISTTP
4349 && FLOAT_MODE_P (GET_MODE (operands[1]))
4350 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4351 "* return output_fix_trunc (insn, operands, 0);"
4352 [(set_attr "type" "fistp")
4353 (set_attr "i387_cw" "trunc")
4354 (set_attr "mode" "<MODE>")])
4356 (define_insn "fix_trunc<mode>_i387_with_temp"
4357 [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
4358 (fix:X87MODEI12 (match_operand 1 "register_operand" "f,f")))
4359 (use (match_operand:HI 2 "memory_operand" "m,m"))
4360 (use (match_operand:HI 3 "memory_operand" "m,m"))
4361 (clobber (match_operand:X87MODEI12 4 "memory_operand" "=m,m"))]
4362 "TARGET_80387 && !TARGET_FISTTP
4363 && FLOAT_MODE_P (GET_MODE (operands[1]))
4364 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4366 [(set_attr "type" "fistp")
4367 (set_attr "i387_cw" "trunc")
4368 (set_attr "mode" "<MODE>")])
4371 [(set (match_operand:X87MODEI12 0 "register_operand" "")
4372 (fix:X87MODEI12 (match_operand 1 "register_operand" "")))
4373 (use (match_operand:HI 2 "memory_operand" ""))
4374 (use (match_operand:HI 3 "memory_operand" ""))
4375 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
4377 [(parallel [(set (match_dup 4) (fix:X87MODEI12 (match_dup 1)))
4379 (use (match_dup 3))])
4380 (set (match_dup 0) (match_dup 4))]
4384 [(set (match_operand:X87MODEI12 0 "memory_operand" "")
4385 (fix:X87MODEI12 (match_operand 1 "register_operand" "")))
4386 (use (match_operand:HI 2 "memory_operand" ""))
4387 (use (match_operand:HI 3 "memory_operand" ""))
4388 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
4390 [(parallel [(set (match_dup 0) (fix:X87MODEI12 (match_dup 1)))
4392 (use (match_dup 3))])]
4395 (define_insn "x86_fnstcw_1"
4396 [(set (match_operand:HI 0 "memory_operand" "=m")
4397 (unspec:HI [(reg:HI FPSR_REG)] UNSPEC_FSTCW))]
4400 [(set_attr "length" "2")
4401 (set_attr "mode" "HI")
4402 (set_attr "unit" "i387")])
4404 (define_insn "x86_fldcw_1"
4405 [(set (reg:HI FPSR_REG)
4406 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4409 [(set_attr "length" "2")
4410 (set_attr "mode" "HI")
4411 (set_attr "unit" "i387")
4412 (set_attr "athlon_decode" "vector")])
4414 ;; Conversion between fixed point and floating point.
4416 ;; Even though we only accept memory inputs, the backend _really_
4417 ;; wants to be able to do this between registers.
4419 (define_expand "floathisf2"
4420 [(set (match_operand:SF 0 "register_operand" "")
4421 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4422 "TARGET_80387 || TARGET_SSE_MATH"
4424 if (TARGET_SSE_MATH)
4426 emit_insn (gen_floatsisf2 (operands[0],
4427 convert_to_mode (SImode, operands[1], 0)));
4432 (define_insn "*floathisf2_i387"
4433 [(set (match_operand:SF 0 "register_operand" "=f,f")
4434 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
4435 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
4439 [(set_attr "type" "fmov,multi")
4440 (set_attr "mode" "SF")
4441 (set_attr "unit" "*,i387")
4442 (set_attr "fp_int_src" "true")])
4444 (define_expand "floatsisf2"
4445 [(set (match_operand:SF 0 "register_operand" "")
4446 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4447 "TARGET_80387 || TARGET_SSE_MATH"
4450 (define_insn "*floatsisf2_mixed"
4451 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4452 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4453 "TARGET_MIX_SSE_I387"
4457 cvtsi2ss\t{%1, %0|%0, %1}
4458 cvtsi2ss\t{%1, %0|%0, %1}"
4459 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4460 (set_attr "mode" "SF")
4461 (set_attr "unit" "*,i387,*,*")
4462 (set_attr "athlon_decode" "*,*,vector,double")
4463 (set_attr "fp_int_src" "true")])
4465 (define_insn "*floatsisf2_sse"
4466 [(set (match_operand:SF 0 "register_operand" "=x,x")
4467 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4469 "cvtsi2ss\t{%1, %0|%0, %1}"
4470 [(set_attr "type" "sseicvt")
4471 (set_attr "mode" "SF")
4472 (set_attr "athlon_decode" "vector,double")
4473 (set_attr "fp_int_src" "true")])
4475 (define_insn "*floatsisf2_i387"
4476 [(set (match_operand:SF 0 "register_operand" "=f,f")
4477 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
4482 [(set_attr "type" "fmov,multi")
4483 (set_attr "mode" "SF")
4484 (set_attr "unit" "*,i387")
4485 (set_attr "fp_int_src" "true")])
4487 (define_expand "floatdisf2"
4488 [(set (match_operand:SF 0 "register_operand" "")
4489 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4490 "TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)"
4493 (define_insn "*floatdisf2_mixed"
4494 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4495 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4496 "TARGET_64BIT && TARGET_MIX_SSE_I387"
4500 cvtsi2ss{q}\t{%1, %0|%0, %1}
4501 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4502 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4503 (set_attr "mode" "SF")
4504 (set_attr "unit" "*,i387,*,*")
4505 (set_attr "athlon_decode" "*,*,vector,double")
4506 (set_attr "fp_int_src" "true")])
4508 (define_insn "*floatdisf2_sse"
4509 [(set (match_operand:SF 0 "register_operand" "=x,x")
4510 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4511 "TARGET_64BIT && TARGET_SSE_MATH"
4512 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4513 [(set_attr "type" "sseicvt")
4514 (set_attr "mode" "SF")
4515 (set_attr "athlon_decode" "vector,double")
4516 (set_attr "fp_int_src" "true")])
4518 (define_insn "*floatdisf2_i387"
4519 [(set (match_operand:SF 0 "register_operand" "=f,f")
4520 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
4525 [(set_attr "type" "fmov,multi")
4526 (set_attr "mode" "SF")
4527 (set_attr "unit" "*,i387")
4528 (set_attr "fp_int_src" "true")])
4530 (define_expand "floathidf2"
4531 [(set (match_operand:DF 0 "register_operand" "")
4532 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4533 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
4535 if (TARGET_SSE2 && TARGET_SSE_MATH)
4537 emit_insn (gen_floatsidf2 (operands[0],
4538 convert_to_mode (SImode, operands[1], 0)));
4543 (define_insn "*floathidf2_i387"
4544 [(set (match_operand:DF 0 "register_operand" "=f,f")
4545 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
4546 "TARGET_80387 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)"
4550 [(set_attr "type" "fmov,multi")
4551 (set_attr "mode" "DF")
4552 (set_attr "unit" "*,i387")
4553 (set_attr "fp_int_src" "true")])
4555 (define_expand "floatsidf2"
4556 [(set (match_operand:DF 0 "register_operand" "")
4557 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4558 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
4561 (define_insn "*floatsidf2_mixed"
4562 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4563 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4564 "TARGET_SSE2 && TARGET_MIX_SSE_I387"
4568 cvtsi2sd\t{%1, %0|%0, %1}
4569 cvtsi2sd\t{%1, %0|%0, %1}"
4570 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4571 (set_attr "mode" "DF")
4572 (set_attr "unit" "*,i387,*,*")
4573 (set_attr "athlon_decode" "*,*,double,direct")
4574 (set_attr "fp_int_src" "true")])
4576 (define_insn "*floatsidf2_sse"
4577 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4578 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4579 "TARGET_SSE2 && TARGET_SSE_MATH"
4580 "cvtsi2sd\t{%1, %0|%0, %1}"
4581 [(set_attr "type" "sseicvt")
4582 (set_attr "mode" "DF")
4583 (set_attr "athlon_decode" "double,direct")
4584 (set_attr "fp_int_src" "true")])
4586 (define_insn "*floatsidf2_i387"
4587 [(set (match_operand:DF 0 "register_operand" "=f,f")
4588 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
4593 [(set_attr "type" "fmov,multi")
4594 (set_attr "mode" "DF")
4595 (set_attr "unit" "*,i387")
4596 (set_attr "fp_int_src" "true")])
4598 (define_expand "floatdidf2"
4599 [(set (match_operand:DF 0 "register_operand" "")
4600 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
4601 "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)"
4604 (define_insn "*floatdidf2_mixed"
4605 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
4606 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4607 "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387"
4611 cvtsi2sd{q}\t{%1, %0|%0, %1}
4612 cvtsi2sd{q}\t{%1, %0|%0, %1}"
4613 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4614 (set_attr "mode" "DF")
4615 (set_attr "unit" "*,i387,*,*")
4616 (set_attr "athlon_decode" "*,*,double,direct")
4617 (set_attr "fp_int_src" "true")])
4619 (define_insn "*floatdidf2_sse"
4620 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
4621 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4622 "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
4623 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
4624 [(set_attr "type" "sseicvt")
4625 (set_attr "mode" "DF")
4626 (set_attr "athlon_decode" "double,direct")
4627 (set_attr "fp_int_src" "true")])
4629 (define_insn "*floatdidf2_i387"
4630 [(set (match_operand:DF 0 "register_operand" "=f,f")
4631 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
4636 [(set_attr "type" "fmov,multi")
4637 (set_attr "mode" "DF")
4638 (set_attr "unit" "*,i387")
4639 (set_attr "fp_int_src" "true")])
4641 (define_insn "floathixf2"
4642 [(set (match_operand:XF 0 "register_operand" "=f,f")
4643 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
4648 [(set_attr "type" "fmov,multi")
4649 (set_attr "mode" "XF")
4650 (set_attr "unit" "*,i387")
4651 (set_attr "fp_int_src" "true")])
4653 (define_insn "floatsixf2"
4654 [(set (match_operand:XF 0 "register_operand" "=f,f")
4655 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
4660 [(set_attr "type" "fmov,multi")
4661 (set_attr "mode" "XF")
4662 (set_attr "unit" "*,i387")
4663 (set_attr "fp_int_src" "true")])
4665 (define_insn "floatdixf2"
4666 [(set (match_operand:XF 0 "register_operand" "=f,f")
4667 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
4672 [(set_attr "type" "fmov,multi")
4673 (set_attr "mode" "XF")
4674 (set_attr "unit" "*,i387")
4675 (set_attr "fp_int_src" "true")])
4677 ;; %%% Kill these when reload knows how to do it.
4679 [(set (match_operand 0 "fp_register_operand" "")
4680 (float (match_operand 1 "register_operand" "")))]
4683 && FLOAT_MODE_P (GET_MODE (operands[0]))"
4686 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4687 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4688 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4689 ix86_free_from_memory (GET_MODE (operands[1]));
4693 (define_expand "floatunssisf2"
4694 [(use (match_operand:SF 0 "register_operand" ""))
4695 (use (match_operand:SI 1 "register_operand" ""))]
4696 "!TARGET_64BIT && TARGET_SSE_MATH"
4697 "x86_emit_floatuns (operands); DONE;")
4699 (define_expand "floatunsdisf2"
4700 [(use (match_operand:SF 0 "register_operand" ""))
4701 (use (match_operand:DI 1 "register_operand" ""))]
4702 "TARGET_64BIT && TARGET_SSE_MATH"
4703 "x86_emit_floatuns (operands); DONE;")
4705 (define_expand "floatunsdidf2"
4706 [(use (match_operand:DF 0 "register_operand" ""))
4707 (use (match_operand:DI 1 "register_operand" ""))]
4708 "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
4709 "x86_emit_floatuns (operands); DONE;")
4711 ;; SSE extract/set expanders
4716 ;; %%% splits for addditi3
4718 (define_expand "addti3"
4719 [(set (match_operand:TI 0 "nonimmediate_operand" "")
4720 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
4721 (match_operand:TI 2 "x86_64_general_operand" "")))
4722 (clobber (reg:CC FLAGS_REG))]
4724 "ix86_expand_binary_operator (PLUS, TImode, operands); DONE;")
4726 (define_insn "*addti3_1"
4727 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
4728 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0,0")
4729 (match_operand:TI 2 "general_operand" "roiF,riF")))
4730 (clobber (reg:CC FLAGS_REG))]
4731 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, TImode, operands)"
4735 [(set (match_operand:TI 0 "nonimmediate_operand" "")
4736 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
4737 (match_operand:TI 2 "general_operand" "")))
4738 (clobber (reg:CC FLAGS_REG))]
4739 "TARGET_64BIT && reload_completed"
4740 [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
4742 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))])
4743 (parallel [(set (match_dup 3)
4744 (plus:DI (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
4747 (clobber (reg:CC FLAGS_REG))])]
4748 "split_ti (operands+0, 1, operands+0, operands+3);
4749 split_ti (operands+1, 1, operands+1, operands+4);
4750 split_ti (operands+2, 1, operands+2, operands+5);")
4752 ;; %%% splits for addsidi3
4753 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4754 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4755 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4757 (define_expand "adddi3"
4758 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4759 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4760 (match_operand:DI 2 "x86_64_general_operand" "")))
4761 (clobber (reg:CC FLAGS_REG))]
4763 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
4765 (define_insn "*adddi3_1"
4766 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4767 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4768 (match_operand:DI 2 "general_operand" "roiF,riF")))
4769 (clobber (reg:CC FLAGS_REG))]
4770 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4774 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4775 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4776 (match_operand:DI 2 "general_operand" "")))
4777 (clobber (reg:CC FLAGS_REG))]
4778 "!TARGET_64BIT && reload_completed"
4779 [(parallel [(set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 1) (match_dup 2)]
4781 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4782 (parallel [(set (match_dup 3)
4783 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
4786 (clobber (reg:CC FLAGS_REG))])]
4787 "split_di (operands+0, 1, operands+0, operands+3);
4788 split_di (operands+1, 1, operands+1, operands+4);
4789 split_di (operands+2, 1, operands+2, operands+5);")
4791 (define_insn "adddi3_carry_rex64"
4792 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4793 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
4794 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
4795 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
4796 (clobber (reg:CC FLAGS_REG))]
4797 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4798 "adc{q}\t{%2, %0|%0, %2}"
4799 [(set_attr "type" "alu")
4800 (set_attr "pent_pair" "pu")
4801 (set_attr "mode" "DI")])
4803 (define_insn "*adddi3_cc_rex64"
4804 [(set (reg:CC FLAGS_REG)
4805 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
4806 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
4808 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
4809 (plus:DI (match_dup 1) (match_dup 2)))]
4810 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
4811 "add{q}\t{%2, %0|%0, %2}"
4812 [(set_attr "type" "alu")
4813 (set_attr "mode" "DI")])
4815 (define_insn "addqi3_carry"
4816 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4817 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
4818 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
4819 (match_operand:QI 2 "general_operand" "qi,qm")))
4820 (clobber (reg:CC FLAGS_REG))]
4821 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4822 "adc{b}\t{%2, %0|%0, %2}"
4823 [(set_attr "type" "alu")
4824 (set_attr "pent_pair" "pu")
4825 (set_attr "mode" "QI")])
4827 (define_insn "addhi3_carry"
4828 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
4829 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
4830 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
4831 (match_operand:HI 2 "general_operand" "ri,rm")))
4832 (clobber (reg:CC FLAGS_REG))]
4833 "ix86_binary_operator_ok (PLUS, HImode, operands)"
4834 "adc{w}\t{%2, %0|%0, %2}"
4835 [(set_attr "type" "alu")
4836 (set_attr "pent_pair" "pu")
4837 (set_attr "mode" "HI")])
4839 (define_insn "addsi3_carry"
4840 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4841 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
4842 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
4843 (match_operand:SI 2 "general_operand" "ri,rm")))
4844 (clobber (reg:CC FLAGS_REG))]
4845 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4846 "adc{l}\t{%2, %0|%0, %2}"
4847 [(set_attr "type" "alu")
4848 (set_attr "pent_pair" "pu")
4849 (set_attr "mode" "SI")])
4851 (define_insn "*addsi3_carry_zext"
4852 [(set (match_operand:DI 0 "register_operand" "=r")
4854 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
4855 (match_operand:SI 1 "nonimmediate_operand" "%0"))
4856 (match_operand:SI 2 "general_operand" "rim"))))
4857 (clobber (reg:CC FLAGS_REG))]
4858 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
4859 "adc{l}\t{%2, %k0|%k0, %2}"
4860 [(set_attr "type" "alu")
4861 (set_attr "pent_pair" "pu")
4862 (set_attr "mode" "SI")])
4864 (define_insn "*addsi3_cc"
4865 [(set (reg:CC FLAGS_REG)
4866 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
4867 (match_operand:SI 2 "general_operand" "ri,rm")]
4869 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4870 (plus:SI (match_dup 1) (match_dup 2)))]
4871 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4872 "add{l}\t{%2, %0|%0, %2}"
4873 [(set_attr "type" "alu")
4874 (set_attr "mode" "SI")])
4876 (define_insn "addqi3_cc"
4877 [(set (reg:CC FLAGS_REG)
4878 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
4879 (match_operand:QI 2 "general_operand" "qi,qm")]
4881 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4882 (plus:QI (match_dup 1) (match_dup 2)))]
4883 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4884 "add{b}\t{%2, %0|%0, %2}"
4885 [(set_attr "type" "alu")
4886 (set_attr "mode" "QI")])
4888 (define_expand "addsi3"
4889 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4890 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4891 (match_operand:SI 2 "general_operand" "")))
4892 (clobber (reg:CC FLAGS_REG))])]
4894 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
4896 (define_insn "*lea_1"
4897 [(set (match_operand:SI 0 "register_operand" "=r")
4898 (match_operand:SI 1 "no_seg_address_operand" "p"))]
4900 "lea{l}\t{%a1, %0|%0, %a1}"
4901 [(set_attr "type" "lea")
4902 (set_attr "mode" "SI")])
4904 (define_insn "*lea_1_rex64"
4905 [(set (match_operand:SI 0 "register_operand" "=r")
4906 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
4908 "lea{l}\t{%a1, %0|%0, %a1}"
4909 [(set_attr "type" "lea")
4910 (set_attr "mode" "SI")])
4912 (define_insn "*lea_1_zext"
4913 [(set (match_operand:DI 0 "register_operand" "=r")
4915 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
4917 "lea{l}\t{%a1, %k0|%k0, %a1}"
4918 [(set_attr "type" "lea")
4919 (set_attr "mode" "SI")])
4921 (define_insn "*lea_2_rex64"
4922 [(set (match_operand:DI 0 "register_operand" "=r")
4923 (match_operand:DI 1 "no_seg_address_operand" "p"))]
4925 "lea{q}\t{%a1, %0|%0, %a1}"
4926 [(set_attr "type" "lea")
4927 (set_attr "mode" "DI")])
4929 ;; The lea patterns for non-Pmodes needs to be matched by several
4930 ;; insns converted to real lea by splitters.
4932 (define_insn_and_split "*lea_general_1"
4933 [(set (match_operand 0 "register_operand" "=r")
4934 (plus (plus (match_operand 1 "index_register_operand" "l")
4935 (match_operand 2 "register_operand" "r"))
4936 (match_operand 3 "immediate_operand" "i")))]
4937 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4938 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4939 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4940 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4941 && GET_MODE (operands[0]) == GET_MODE (operands[2])
4942 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
4943 || GET_MODE (operands[3]) == VOIDmode)"
4945 "&& reload_completed"
4949 operands[0] = gen_lowpart (SImode, operands[0]);
4950 operands[1] = gen_lowpart (Pmode, operands[1]);
4951 operands[2] = gen_lowpart (Pmode, operands[2]);
4952 operands[3] = gen_lowpart (Pmode, operands[3]);
4953 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
4955 if (Pmode != SImode)
4956 pat = gen_rtx_SUBREG (SImode, pat, 0);
4957 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4960 [(set_attr "type" "lea")
4961 (set_attr "mode" "SI")])
4963 (define_insn_and_split "*lea_general_1_zext"
4964 [(set (match_operand:DI 0 "register_operand" "=r")
4966 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "l")
4967 (match_operand:SI 2 "register_operand" "r"))
4968 (match_operand:SI 3 "immediate_operand" "i"))))]
4971 "&& reload_completed"
4973 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
4975 (match_dup 3)) 0)))]
4977 operands[1] = gen_lowpart (Pmode, operands[1]);
4978 operands[2] = gen_lowpart (Pmode, operands[2]);
4979 operands[3] = gen_lowpart (Pmode, operands[3]);
4981 [(set_attr "type" "lea")
4982 (set_attr "mode" "SI")])
4984 (define_insn_and_split "*lea_general_2"
4985 [(set (match_operand 0 "register_operand" "=r")
4986 (plus (mult (match_operand 1 "index_register_operand" "l")
4987 (match_operand 2 "const248_operand" "i"))
4988 (match_operand 3 "nonmemory_operand" "ri")))]
4989 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
4990 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
4991 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4992 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4993 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
4994 || GET_MODE (operands[3]) == VOIDmode)"
4996 "&& reload_completed"
5000 operands[0] = gen_lowpart (SImode, operands[0]);
5001 operands[1] = gen_lowpart (Pmode, operands[1]);
5002 operands[3] = gen_lowpart (Pmode, operands[3]);
5003 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5005 if (Pmode != SImode)
5006 pat = gen_rtx_SUBREG (SImode, pat, 0);
5007 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5010 [(set_attr "type" "lea")
5011 (set_attr "mode" "SI")])
5013 (define_insn_and_split "*lea_general_2_zext"
5014 [(set (match_operand:DI 0 "register_operand" "=r")
5016 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "l")
5017 (match_operand:SI 2 "const248_operand" "n"))
5018 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5021 "&& reload_completed"
5023 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5025 (match_dup 3)) 0)))]
5027 operands[1] = gen_lowpart (Pmode, operands[1]);
5028 operands[3] = gen_lowpart (Pmode, operands[3]);
5030 [(set_attr "type" "lea")
5031 (set_attr "mode" "SI")])
5033 (define_insn_and_split "*lea_general_3"
5034 [(set (match_operand 0 "register_operand" "=r")
5035 (plus (plus (mult (match_operand 1 "index_register_operand" "l")
5036 (match_operand 2 "const248_operand" "i"))
5037 (match_operand 3 "register_operand" "r"))
5038 (match_operand 4 "immediate_operand" "i")))]
5039 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5040 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5041 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5042 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5043 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5045 "&& reload_completed"
5049 operands[0] = gen_lowpart (SImode, operands[0]);
5050 operands[1] = gen_lowpart (Pmode, operands[1]);
5051 operands[3] = gen_lowpart (Pmode, operands[3]);
5052 operands[4] = gen_lowpart (Pmode, operands[4]);
5053 pat = gen_rtx_PLUS (Pmode,
5054 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5058 if (Pmode != SImode)
5059 pat = gen_rtx_SUBREG (SImode, pat, 0);
5060 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5063 [(set_attr "type" "lea")
5064 (set_attr "mode" "SI")])
5066 (define_insn_and_split "*lea_general_3_zext"
5067 [(set (match_operand:DI 0 "register_operand" "=r")
5069 (plus:SI (plus:SI (mult:SI
5070 (match_operand:SI 1 "index_register_operand" "l")
5071 (match_operand:SI 2 "const248_operand" "n"))
5072 (match_operand:SI 3 "register_operand" "r"))
5073 (match_operand:SI 4 "immediate_operand" "i"))))]
5076 "&& reload_completed"
5078 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5081 (match_dup 4)) 0)))]
5083 operands[1] = gen_lowpart (Pmode, operands[1]);
5084 operands[3] = gen_lowpart (Pmode, operands[3]);
5085 operands[4] = gen_lowpart (Pmode, operands[4]);
5087 [(set_attr "type" "lea")
5088 (set_attr "mode" "SI")])
5090 (define_insn "*adddi_1_rex64"
5091 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5092 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5093 (match_operand:DI 2 "x86_64_general_operand" "rme,re,le")))
5094 (clobber (reg:CC FLAGS_REG))]
5095 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5097 switch (get_attr_type (insn))
5100 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5101 return "lea{q}\t{%a2, %0|%0, %a2}";
5104 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5105 if (operands[2] == const1_rtx)
5106 return "inc{q}\t%0";
5109 gcc_assert (operands[2] == constm1_rtx);
5110 return "dec{q}\t%0";
5114 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5116 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5117 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5118 if (GET_CODE (operands[2]) == CONST_INT
5119 /* Avoid overflows. */
5120 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5121 && (INTVAL (operands[2]) == 128
5122 || (INTVAL (operands[2]) < 0
5123 && INTVAL (operands[2]) != -128)))
5125 operands[2] = GEN_INT (-INTVAL (operands[2]));
5126 return "sub{q}\t{%2, %0|%0, %2}";
5128 return "add{q}\t{%2, %0|%0, %2}";
5132 (cond [(eq_attr "alternative" "2")
5133 (const_string "lea")
5134 ; Current assemblers are broken and do not allow @GOTOFF in
5135 ; ought but a memory context.
5136 (match_operand:DI 2 "pic_symbolic_operand" "")
5137 (const_string "lea")
5138 (match_operand:DI 2 "incdec_operand" "")
5139 (const_string "incdec")
5141 (const_string "alu")))
5142 (set_attr "mode" "DI")])
5144 ;; Convert lea to the lea pattern to avoid flags dependency.
5146 [(set (match_operand:DI 0 "register_operand" "")
5147 (plus:DI (match_operand:DI 1 "register_operand" "")
5148 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5149 (clobber (reg:CC FLAGS_REG))]
5150 "TARGET_64BIT && reload_completed
5151 && true_regnum (operands[0]) != true_regnum (operands[1])"
5153 (plus:DI (match_dup 1)
5157 (define_insn "*adddi_2_rex64"
5158 [(set (reg FLAGS_REG)
5160 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5161 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5163 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5164 (plus:DI (match_dup 1) (match_dup 2)))]
5165 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5166 && ix86_binary_operator_ok (PLUS, DImode, operands)
5167 /* Current assemblers are broken and do not allow @GOTOFF in
5168 ought but a memory context. */
5169 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5171 switch (get_attr_type (insn))
5174 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5175 if (operands[2] == const1_rtx)
5176 return "inc{q}\t%0";
5179 gcc_assert (operands[2] == constm1_rtx);
5180 return "dec{q}\t%0";
5184 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5185 /* ???? We ought to handle there the 32bit case too
5186 - do we need new constraint? */
5187 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5188 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5189 if (GET_CODE (operands[2]) == CONST_INT
5190 /* Avoid overflows. */
5191 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5192 && (INTVAL (operands[2]) == 128
5193 || (INTVAL (operands[2]) < 0
5194 && INTVAL (operands[2]) != -128)))
5196 operands[2] = GEN_INT (-INTVAL (operands[2]));
5197 return "sub{q}\t{%2, %0|%0, %2}";
5199 return "add{q}\t{%2, %0|%0, %2}";
5203 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5204 (const_string "incdec")
5205 (const_string "alu")))
5206 (set_attr "mode" "DI")])
5208 (define_insn "*adddi_3_rex64"
5209 [(set (reg FLAGS_REG)
5210 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5211 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5212 (clobber (match_scratch:DI 0 "=r"))]
5214 && ix86_match_ccmode (insn, CCZmode)
5215 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5216 /* Current assemblers are broken and do not allow @GOTOFF in
5217 ought but a memory context. */
5218 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5220 switch (get_attr_type (insn))
5223 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5224 if (operands[2] == const1_rtx)
5225 return "inc{q}\t%0";
5228 gcc_assert (operands[2] == constm1_rtx);
5229 return "dec{q}\t%0";
5233 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5234 /* ???? We ought to handle there the 32bit case too
5235 - do we need new constraint? */
5236 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5237 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5238 if (GET_CODE (operands[2]) == CONST_INT
5239 /* Avoid overflows. */
5240 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5241 && (INTVAL (operands[2]) == 128
5242 || (INTVAL (operands[2]) < 0
5243 && INTVAL (operands[2]) != -128)))
5245 operands[2] = GEN_INT (-INTVAL (operands[2]));
5246 return "sub{q}\t{%2, %0|%0, %2}";
5248 return "add{q}\t{%2, %0|%0, %2}";
5252 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5253 (const_string "incdec")
5254 (const_string "alu")))
5255 (set_attr "mode" "DI")])
5257 ; For comparisons against 1, -1 and 128, we may generate better code
5258 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5259 ; is matched then. We can't accept general immediate, because for
5260 ; case of overflows, the result is messed up.
5261 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5263 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5264 ; only for comparisons not depending on it.
5265 (define_insn "*adddi_4_rex64"
5266 [(set (reg FLAGS_REG)
5267 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5268 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5269 (clobber (match_scratch:DI 0 "=rm"))]
5271 && ix86_match_ccmode (insn, CCGCmode)"
5273 switch (get_attr_type (insn))
5276 if (operands[2] == constm1_rtx)
5277 return "inc{q}\t%0";
5280 gcc_assert (operands[2] == const1_rtx);
5281 return "dec{q}\t%0";
5285 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5286 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5287 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5288 if ((INTVAL (operands[2]) == -128
5289 || (INTVAL (operands[2]) > 0
5290 && INTVAL (operands[2]) != 128))
5291 /* Avoid overflows. */
5292 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5293 return "sub{q}\t{%2, %0|%0, %2}";
5294 operands[2] = GEN_INT (-INTVAL (operands[2]));
5295 return "add{q}\t{%2, %0|%0, %2}";
5299 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5300 (const_string "incdec")
5301 (const_string "alu")))
5302 (set_attr "mode" "DI")])
5304 (define_insn "*adddi_5_rex64"
5305 [(set (reg FLAGS_REG)
5307 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5308 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5310 (clobber (match_scratch:DI 0 "=r"))]
5312 && ix86_match_ccmode (insn, CCGOCmode)
5313 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5314 /* Current assemblers are broken and do not allow @GOTOFF in
5315 ought but a memory context. */
5316 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5318 switch (get_attr_type (insn))
5321 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5322 if (operands[2] == const1_rtx)
5323 return "inc{q}\t%0";
5326 gcc_assert (operands[2] == constm1_rtx);
5327 return "dec{q}\t%0";
5331 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5332 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5333 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5334 if (GET_CODE (operands[2]) == CONST_INT
5335 /* Avoid overflows. */
5336 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5337 && (INTVAL (operands[2]) == 128
5338 || (INTVAL (operands[2]) < 0
5339 && INTVAL (operands[2]) != -128)))
5341 operands[2] = GEN_INT (-INTVAL (operands[2]));
5342 return "sub{q}\t{%2, %0|%0, %2}";
5344 return "add{q}\t{%2, %0|%0, %2}";
5348 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5349 (const_string "incdec")
5350 (const_string "alu")))
5351 (set_attr "mode" "DI")])
5354 (define_insn "*addsi_1"
5355 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5356 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5357 (match_operand:SI 2 "general_operand" "rmni,rni,lni")))
5358 (clobber (reg:CC FLAGS_REG))]
5359 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5361 switch (get_attr_type (insn))
5364 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5365 return "lea{l}\t{%a2, %0|%0, %a2}";
5368 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5369 if (operands[2] == const1_rtx)
5370 return "inc{l}\t%0";
5373 gcc_assert (operands[2] == constm1_rtx);
5374 return "dec{l}\t%0";
5378 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5380 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5381 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5382 if (GET_CODE (operands[2]) == CONST_INT
5383 && (INTVAL (operands[2]) == 128
5384 || (INTVAL (operands[2]) < 0
5385 && INTVAL (operands[2]) != -128)))
5387 operands[2] = GEN_INT (-INTVAL (operands[2]));
5388 return "sub{l}\t{%2, %0|%0, %2}";
5390 return "add{l}\t{%2, %0|%0, %2}";
5394 (cond [(eq_attr "alternative" "2")
5395 (const_string "lea")
5396 ; Current assemblers are broken and do not allow @GOTOFF in
5397 ; ought but a memory context.
5398 (match_operand:SI 2 "pic_symbolic_operand" "")
5399 (const_string "lea")
5400 (match_operand:SI 2 "incdec_operand" "")
5401 (const_string "incdec")
5403 (const_string "alu")))
5404 (set_attr "mode" "SI")])
5406 ;; Convert lea to the lea pattern to avoid flags dependency.
5408 [(set (match_operand 0 "register_operand" "")
5409 (plus (match_operand 1 "register_operand" "")
5410 (match_operand 2 "nonmemory_operand" "")))
5411 (clobber (reg:CC FLAGS_REG))]
5413 && true_regnum (operands[0]) != true_regnum (operands[1])"
5417 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5418 may confuse gen_lowpart. */
5419 if (GET_MODE (operands[0]) != Pmode)
5421 operands[1] = gen_lowpart (Pmode, operands[1]);
5422 operands[2] = gen_lowpart (Pmode, operands[2]);
5424 operands[0] = gen_lowpart (SImode, operands[0]);
5425 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5426 if (Pmode != SImode)
5427 pat = gen_rtx_SUBREG (SImode, pat, 0);
5428 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5432 ;; It may seem that nonimmediate operand is proper one for operand 1.
5433 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5434 ;; we take care in ix86_binary_operator_ok to not allow two memory
5435 ;; operands so proper swapping will be done in reload. This allow
5436 ;; patterns constructed from addsi_1 to match.
5437 (define_insn "addsi_1_zext"
5438 [(set (match_operand:DI 0 "register_operand" "=r,r")
5440 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5441 (match_operand:SI 2 "general_operand" "rmni,lni"))))
5442 (clobber (reg:CC FLAGS_REG))]
5443 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5445 switch (get_attr_type (insn))
5448 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5449 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5452 if (operands[2] == const1_rtx)
5453 return "inc{l}\t%k0";
5456 gcc_assert (operands[2] == constm1_rtx);
5457 return "dec{l}\t%k0";
5461 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5462 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5463 if (GET_CODE (operands[2]) == CONST_INT
5464 && (INTVAL (operands[2]) == 128
5465 || (INTVAL (operands[2]) < 0
5466 && INTVAL (operands[2]) != -128)))
5468 operands[2] = GEN_INT (-INTVAL (operands[2]));
5469 return "sub{l}\t{%2, %k0|%k0, %2}";
5471 return "add{l}\t{%2, %k0|%k0, %2}";
5475 (cond [(eq_attr "alternative" "1")
5476 (const_string "lea")
5477 ; Current assemblers are broken and do not allow @GOTOFF in
5478 ; ought but a memory context.
5479 (match_operand:SI 2 "pic_symbolic_operand" "")
5480 (const_string "lea")
5481 (match_operand:SI 2 "incdec_operand" "")
5482 (const_string "incdec")
5484 (const_string "alu")))
5485 (set_attr "mode" "SI")])
5487 ;; Convert lea to the lea pattern to avoid flags dependency.
5489 [(set (match_operand:DI 0 "register_operand" "")
5491 (plus:SI (match_operand:SI 1 "register_operand" "")
5492 (match_operand:SI 2 "nonmemory_operand" ""))))
5493 (clobber (reg:CC FLAGS_REG))]
5494 "TARGET_64BIT && reload_completed
5495 && true_regnum (operands[0]) != true_regnum (operands[1])"
5497 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5499 operands[1] = gen_lowpart (Pmode, operands[1]);
5500 operands[2] = gen_lowpart (Pmode, operands[2]);
5503 (define_insn "*addsi_2"
5504 [(set (reg FLAGS_REG)
5506 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5507 (match_operand:SI 2 "general_operand" "rmni,rni"))
5509 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5510 (plus:SI (match_dup 1) (match_dup 2)))]
5511 "ix86_match_ccmode (insn, CCGOCmode)
5512 && ix86_binary_operator_ok (PLUS, SImode, operands)
5513 /* Current assemblers are broken and do not allow @GOTOFF in
5514 ought but a memory context. */
5515 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5517 switch (get_attr_type (insn))
5520 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5521 if (operands[2] == const1_rtx)
5522 return "inc{l}\t%0";
5525 gcc_assert (operands[2] == constm1_rtx);
5526 return "dec{l}\t%0";
5530 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5531 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5532 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5533 if (GET_CODE (operands[2]) == CONST_INT
5534 && (INTVAL (operands[2]) == 128
5535 || (INTVAL (operands[2]) < 0
5536 && INTVAL (operands[2]) != -128)))
5538 operands[2] = GEN_INT (-INTVAL (operands[2]));
5539 return "sub{l}\t{%2, %0|%0, %2}";
5541 return "add{l}\t{%2, %0|%0, %2}";
5545 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5546 (const_string "incdec")
5547 (const_string "alu")))
5548 (set_attr "mode" "SI")])
5550 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5551 (define_insn "*addsi_2_zext"
5552 [(set (reg FLAGS_REG)
5554 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5555 (match_operand:SI 2 "general_operand" "rmni"))
5557 (set (match_operand:DI 0 "register_operand" "=r")
5558 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5559 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5560 && ix86_binary_operator_ok (PLUS, SImode, operands)
5561 /* Current assemblers are broken and do not allow @GOTOFF in
5562 ought but a memory context. */
5563 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5565 switch (get_attr_type (insn))
5568 if (operands[2] == const1_rtx)
5569 return "inc{l}\t%k0";
5572 gcc_assert (operands[2] == constm1_rtx);
5573 return "dec{l}\t%k0";
5577 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5578 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5579 if (GET_CODE (operands[2]) == CONST_INT
5580 && (INTVAL (operands[2]) == 128
5581 || (INTVAL (operands[2]) < 0
5582 && INTVAL (operands[2]) != -128)))
5584 operands[2] = GEN_INT (-INTVAL (operands[2]));
5585 return "sub{l}\t{%2, %k0|%k0, %2}";
5587 return "add{l}\t{%2, %k0|%k0, %2}";
5591 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5592 (const_string "incdec")
5593 (const_string "alu")))
5594 (set_attr "mode" "SI")])
5596 (define_insn "*addsi_3"
5597 [(set (reg FLAGS_REG)
5598 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5599 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5600 (clobber (match_scratch:SI 0 "=r"))]
5601 "ix86_match_ccmode (insn, CCZmode)
5602 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5603 /* Current assemblers are broken and do not allow @GOTOFF in
5604 ought but a memory context. */
5605 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5607 switch (get_attr_type (insn))
5610 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5611 if (operands[2] == const1_rtx)
5612 return "inc{l}\t%0";
5615 gcc_assert (operands[2] == constm1_rtx);
5616 return "dec{l}\t%0";
5620 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5621 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5622 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5623 if (GET_CODE (operands[2]) == CONST_INT
5624 && (INTVAL (operands[2]) == 128
5625 || (INTVAL (operands[2]) < 0
5626 && INTVAL (operands[2]) != -128)))
5628 operands[2] = GEN_INT (-INTVAL (operands[2]));
5629 return "sub{l}\t{%2, %0|%0, %2}";
5631 return "add{l}\t{%2, %0|%0, %2}";
5635 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5636 (const_string "incdec")
5637 (const_string "alu")))
5638 (set_attr "mode" "SI")])
5640 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5641 (define_insn "*addsi_3_zext"
5642 [(set (reg FLAGS_REG)
5643 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
5644 (match_operand:SI 1 "nonimmediate_operand" "%0")))
5645 (set (match_operand:DI 0 "register_operand" "=r")
5646 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5647 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
5648 && ix86_binary_operator_ok (PLUS, SImode, operands)
5649 /* Current assemblers are broken and do not allow @GOTOFF in
5650 ought but a memory context. */
5651 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5653 switch (get_attr_type (insn))
5656 if (operands[2] == const1_rtx)
5657 return "inc{l}\t%k0";
5660 gcc_assert (operands[2] == constm1_rtx);
5661 return "dec{l}\t%k0";
5665 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5666 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5667 if (GET_CODE (operands[2]) == CONST_INT
5668 && (INTVAL (operands[2]) == 128
5669 || (INTVAL (operands[2]) < 0
5670 && INTVAL (operands[2]) != -128)))
5672 operands[2] = GEN_INT (-INTVAL (operands[2]));
5673 return "sub{l}\t{%2, %k0|%k0, %2}";
5675 return "add{l}\t{%2, %k0|%k0, %2}";
5679 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5680 (const_string "incdec")
5681 (const_string "alu")))
5682 (set_attr "mode" "SI")])
5684 ; For comparisons against 1, -1 and 128, we may generate better code
5685 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5686 ; is matched then. We can't accept general immediate, because for
5687 ; case of overflows, the result is messed up.
5688 ; This pattern also don't hold of 0x80000000, since the value overflows
5690 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5691 ; only for comparisons not depending on it.
5692 (define_insn "*addsi_4"
5693 [(set (reg FLAGS_REG)
5694 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
5695 (match_operand:SI 2 "const_int_operand" "n")))
5696 (clobber (match_scratch:SI 0 "=rm"))]
5697 "ix86_match_ccmode (insn, CCGCmode)
5698 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
5700 switch (get_attr_type (insn))
5703 if (operands[2] == constm1_rtx)
5704 return "inc{l}\t%0";
5707 gcc_assert (operands[2] == const1_rtx);
5708 return "dec{l}\t%0";
5712 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5713 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5714 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5715 if ((INTVAL (operands[2]) == -128
5716 || (INTVAL (operands[2]) > 0
5717 && INTVAL (operands[2]) != 128)))
5718 return "sub{l}\t{%2, %0|%0, %2}";
5719 operands[2] = GEN_INT (-INTVAL (operands[2]));
5720 return "add{l}\t{%2, %0|%0, %2}";
5724 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5725 (const_string "incdec")
5726 (const_string "alu")))
5727 (set_attr "mode" "SI")])
5729 (define_insn "*addsi_5"
5730 [(set (reg FLAGS_REG)
5732 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5733 (match_operand:SI 2 "general_operand" "rmni"))
5735 (clobber (match_scratch:SI 0 "=r"))]
5736 "ix86_match_ccmode (insn, CCGOCmode)
5737 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5738 /* Current assemblers are broken and do not allow @GOTOFF in
5739 ought but a memory context. */
5740 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5742 switch (get_attr_type (insn))
5745 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5746 if (operands[2] == const1_rtx)
5747 return "inc{l}\t%0";
5750 gcc_assert (operands[2] == constm1_rtx);
5751 return "dec{l}\t%0";
5755 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5756 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5757 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5758 if (GET_CODE (operands[2]) == CONST_INT
5759 && (INTVAL (operands[2]) == 128
5760 || (INTVAL (operands[2]) < 0
5761 && INTVAL (operands[2]) != -128)))
5763 operands[2] = GEN_INT (-INTVAL (operands[2]));
5764 return "sub{l}\t{%2, %0|%0, %2}";
5766 return "add{l}\t{%2, %0|%0, %2}";
5770 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5771 (const_string "incdec")
5772 (const_string "alu")))
5773 (set_attr "mode" "SI")])
5775 (define_expand "addhi3"
5776 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5777 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5778 (match_operand:HI 2 "general_operand" "")))
5779 (clobber (reg:CC FLAGS_REG))])]
5780 "TARGET_HIMODE_MATH"
5781 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
5783 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
5784 ;; type optimizations enabled by define-splits. This is not important
5785 ;; for PII, and in fact harmful because of partial register stalls.
5787 (define_insn "*addhi_1_lea"
5788 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
5789 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
5790 (match_operand:HI 2 "general_operand" "ri,rm,lni")))
5791 (clobber (reg:CC FLAGS_REG))]
5792 "!TARGET_PARTIAL_REG_STALL
5793 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5795 switch (get_attr_type (insn))
5800 if (operands[2] == const1_rtx)
5801 return "inc{w}\t%0";
5804 gcc_assert (operands[2] == constm1_rtx);
5805 return "dec{w}\t%0";
5809 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5810 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5811 if (GET_CODE (operands[2]) == CONST_INT
5812 && (INTVAL (operands[2]) == 128
5813 || (INTVAL (operands[2]) < 0
5814 && INTVAL (operands[2]) != -128)))
5816 operands[2] = GEN_INT (-INTVAL (operands[2]));
5817 return "sub{w}\t{%2, %0|%0, %2}";
5819 return "add{w}\t{%2, %0|%0, %2}";
5823 (if_then_else (eq_attr "alternative" "2")
5824 (const_string "lea")
5825 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5826 (const_string "incdec")
5827 (const_string "alu"))))
5828 (set_attr "mode" "HI,HI,SI")])
5830 (define_insn "*addhi_1"
5831 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5832 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5833 (match_operand:HI 2 "general_operand" "ri,rm")))
5834 (clobber (reg:CC FLAGS_REG))]
5835 "TARGET_PARTIAL_REG_STALL
5836 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5838 switch (get_attr_type (insn))
5841 if (operands[2] == const1_rtx)
5842 return "inc{w}\t%0";
5845 gcc_assert (operands[2] == constm1_rtx);
5846 return "dec{w}\t%0";
5850 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5851 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5852 if (GET_CODE (operands[2]) == CONST_INT
5853 && (INTVAL (operands[2]) == 128
5854 || (INTVAL (operands[2]) < 0
5855 && INTVAL (operands[2]) != -128)))
5857 operands[2] = GEN_INT (-INTVAL (operands[2]));
5858 return "sub{w}\t{%2, %0|%0, %2}";
5860 return "add{w}\t{%2, %0|%0, %2}";
5864 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5865 (const_string "incdec")
5866 (const_string "alu")))
5867 (set_attr "mode" "HI")])
5869 (define_insn "*addhi_2"
5870 [(set (reg FLAGS_REG)
5872 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5873 (match_operand:HI 2 "general_operand" "rmni,rni"))
5875 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
5876 (plus:HI (match_dup 1) (match_dup 2)))]
5877 "ix86_match_ccmode (insn, CCGOCmode)
5878 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5880 switch (get_attr_type (insn))
5883 if (operands[2] == const1_rtx)
5884 return "inc{w}\t%0";
5887 gcc_assert (operands[2] == constm1_rtx);
5888 return "dec{w}\t%0";
5892 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5893 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5894 if (GET_CODE (operands[2]) == CONST_INT
5895 && (INTVAL (operands[2]) == 128
5896 || (INTVAL (operands[2]) < 0
5897 && INTVAL (operands[2]) != -128)))
5899 operands[2] = GEN_INT (-INTVAL (operands[2]));
5900 return "sub{w}\t{%2, %0|%0, %2}";
5902 return "add{w}\t{%2, %0|%0, %2}";
5906 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5907 (const_string "incdec")
5908 (const_string "alu")))
5909 (set_attr "mode" "HI")])
5911 (define_insn "*addhi_3"
5912 [(set (reg FLAGS_REG)
5913 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
5914 (match_operand:HI 1 "nonimmediate_operand" "%0")))
5915 (clobber (match_scratch:HI 0 "=r"))]
5916 "ix86_match_ccmode (insn, CCZmode)
5917 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5919 switch (get_attr_type (insn))
5922 if (operands[2] == const1_rtx)
5923 return "inc{w}\t%0";
5926 gcc_assert (operands[2] == constm1_rtx);
5927 return "dec{w}\t%0";
5931 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5932 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5933 if (GET_CODE (operands[2]) == CONST_INT
5934 && (INTVAL (operands[2]) == 128
5935 || (INTVAL (operands[2]) < 0
5936 && INTVAL (operands[2]) != -128)))
5938 operands[2] = GEN_INT (-INTVAL (operands[2]));
5939 return "sub{w}\t{%2, %0|%0, %2}";
5941 return "add{w}\t{%2, %0|%0, %2}";
5945 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5946 (const_string "incdec")
5947 (const_string "alu")))
5948 (set_attr "mode" "HI")])
5950 ; See comments above addsi_4 for details.
5951 (define_insn "*addhi_4"
5952 [(set (reg FLAGS_REG)
5953 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
5954 (match_operand:HI 2 "const_int_operand" "n")))
5955 (clobber (match_scratch:HI 0 "=rm"))]
5956 "ix86_match_ccmode (insn, CCGCmode)
5957 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
5959 switch (get_attr_type (insn))
5962 if (operands[2] == constm1_rtx)
5963 return "inc{w}\t%0";
5966 gcc_assert (operands[2] == const1_rtx);
5967 return "dec{w}\t%0";
5971 gcc_assert (rtx_equal_p (operands[0], operands[1]));
5972 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5973 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5974 if ((INTVAL (operands[2]) == -128
5975 || (INTVAL (operands[2]) > 0
5976 && INTVAL (operands[2]) != 128)))
5977 return "sub{w}\t{%2, %0|%0, %2}";
5978 operands[2] = GEN_INT (-INTVAL (operands[2]));
5979 return "add{w}\t{%2, %0|%0, %2}";
5983 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5984 (const_string "incdec")
5985 (const_string "alu")))
5986 (set_attr "mode" "SI")])
5989 (define_insn "*addhi_5"
5990 [(set (reg FLAGS_REG)
5992 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
5993 (match_operand:HI 2 "general_operand" "rmni"))
5995 (clobber (match_scratch:HI 0 "=r"))]
5996 "ix86_match_ccmode (insn, CCGOCmode)
5997 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5999 switch (get_attr_type (insn))
6002 if (operands[2] == const1_rtx)
6003 return "inc{w}\t%0";
6006 gcc_assert (operands[2] == constm1_rtx);
6007 return "dec{w}\t%0";
6011 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6012 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6013 if (GET_CODE (operands[2]) == CONST_INT
6014 && (INTVAL (operands[2]) == 128
6015 || (INTVAL (operands[2]) < 0
6016 && INTVAL (operands[2]) != -128)))
6018 operands[2] = GEN_INT (-INTVAL (operands[2]));
6019 return "sub{w}\t{%2, %0|%0, %2}";
6021 return "add{w}\t{%2, %0|%0, %2}";
6025 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6026 (const_string "incdec")
6027 (const_string "alu")))
6028 (set_attr "mode" "HI")])
6030 (define_expand "addqi3"
6031 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6032 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6033 (match_operand:QI 2 "general_operand" "")))
6034 (clobber (reg:CC FLAGS_REG))])]
6035 "TARGET_QIMODE_MATH"
6036 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6038 ;; %%% Potential partial reg stall on alternative 2. What to do?
6039 (define_insn "*addqi_1_lea"
6040 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6041 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6042 (match_operand:QI 2 "general_operand" "qn,qmn,rn,ln")))
6043 (clobber (reg:CC FLAGS_REG))]
6044 "!TARGET_PARTIAL_REG_STALL
6045 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6047 int widen = (which_alternative == 2);
6048 switch (get_attr_type (insn))
6053 if (operands[2] == const1_rtx)
6054 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6057 gcc_assert (operands[2] == constm1_rtx);
6058 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6062 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6063 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6064 if (GET_CODE (operands[2]) == CONST_INT
6065 && (INTVAL (operands[2]) == 128
6066 || (INTVAL (operands[2]) < 0
6067 && INTVAL (operands[2]) != -128)))
6069 operands[2] = GEN_INT (-INTVAL (operands[2]));
6071 return "sub{l}\t{%2, %k0|%k0, %2}";
6073 return "sub{b}\t{%2, %0|%0, %2}";
6076 return "add{l}\t{%k2, %k0|%k0, %k2}";
6078 return "add{b}\t{%2, %0|%0, %2}";
6082 (if_then_else (eq_attr "alternative" "3")
6083 (const_string "lea")
6084 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6085 (const_string "incdec")
6086 (const_string "alu"))))
6087 (set_attr "mode" "QI,QI,SI,SI")])
6089 (define_insn "*addqi_1"
6090 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6091 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6092 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6093 (clobber (reg:CC FLAGS_REG))]
6094 "TARGET_PARTIAL_REG_STALL
6095 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6097 int widen = (which_alternative == 2);
6098 switch (get_attr_type (insn))
6101 if (operands[2] == const1_rtx)
6102 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6105 gcc_assert (operands[2] == constm1_rtx);
6106 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6110 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6111 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6112 if (GET_CODE (operands[2]) == CONST_INT
6113 && (INTVAL (operands[2]) == 128
6114 || (INTVAL (operands[2]) < 0
6115 && INTVAL (operands[2]) != -128)))
6117 operands[2] = GEN_INT (-INTVAL (operands[2]));
6119 return "sub{l}\t{%2, %k0|%k0, %2}";
6121 return "sub{b}\t{%2, %0|%0, %2}";
6124 return "add{l}\t{%k2, %k0|%k0, %k2}";
6126 return "add{b}\t{%2, %0|%0, %2}";
6130 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6131 (const_string "incdec")
6132 (const_string "alu")))
6133 (set_attr "mode" "QI,QI,SI")])
6135 (define_insn "*addqi_1_slp"
6136 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6137 (plus:QI (match_dup 0)
6138 (match_operand:QI 1 "general_operand" "qn,qnm")))
6139 (clobber (reg:CC FLAGS_REG))]
6140 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6141 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6143 switch (get_attr_type (insn))
6146 if (operands[1] == const1_rtx)
6147 return "inc{b}\t%0";
6150 gcc_assert (operands[1] == constm1_rtx);
6151 return "dec{b}\t%0";
6155 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6156 if (GET_CODE (operands[1]) == CONST_INT
6157 && INTVAL (operands[1]) < 0)
6159 operands[1] = GEN_INT (-INTVAL (operands[1]));
6160 return "sub{b}\t{%1, %0|%0, %1}";
6162 return "add{b}\t{%1, %0|%0, %1}";
6166 (if_then_else (match_operand:QI 1 "incdec_operand" "")
6167 (const_string "incdec")
6168 (const_string "alu1")))
6169 (set (attr "memory")
6170 (if_then_else (match_operand 1 "memory_operand" "")
6171 (const_string "load")
6172 (const_string "none")))
6173 (set_attr "mode" "QI")])
6175 (define_insn "*addqi_2"
6176 [(set (reg FLAGS_REG)
6178 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6179 (match_operand:QI 2 "general_operand" "qmni,qni"))
6181 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6182 (plus:QI (match_dup 1) (match_dup 2)))]
6183 "ix86_match_ccmode (insn, CCGOCmode)
6184 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6186 switch (get_attr_type (insn))
6189 if (operands[2] == const1_rtx)
6190 return "inc{b}\t%0";
6193 gcc_assert (operands[2] == constm1_rtx
6194 || (GET_CODE (operands[2]) == CONST_INT
6195 && INTVAL (operands[2]) == 255));
6196 return "dec{b}\t%0";
6200 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6201 if (GET_CODE (operands[2]) == CONST_INT
6202 && INTVAL (operands[2]) < 0)
6204 operands[2] = GEN_INT (-INTVAL (operands[2]));
6205 return "sub{b}\t{%2, %0|%0, %2}";
6207 return "add{b}\t{%2, %0|%0, %2}";
6211 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6212 (const_string "incdec")
6213 (const_string "alu")))
6214 (set_attr "mode" "QI")])
6216 (define_insn "*addqi_3"
6217 [(set (reg FLAGS_REG)
6218 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6219 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6220 (clobber (match_scratch:QI 0 "=q"))]
6221 "ix86_match_ccmode (insn, CCZmode)
6222 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6224 switch (get_attr_type (insn))
6227 if (operands[2] == const1_rtx)
6228 return "inc{b}\t%0";
6231 gcc_assert (operands[2] == constm1_rtx
6232 || (GET_CODE (operands[2]) == CONST_INT
6233 && INTVAL (operands[2]) == 255));
6234 return "dec{b}\t%0";
6238 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6239 if (GET_CODE (operands[2]) == CONST_INT
6240 && INTVAL (operands[2]) < 0)
6242 operands[2] = GEN_INT (-INTVAL (operands[2]));
6243 return "sub{b}\t{%2, %0|%0, %2}";
6245 return "add{b}\t{%2, %0|%0, %2}";
6249 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6250 (const_string "incdec")
6251 (const_string "alu")))
6252 (set_attr "mode" "QI")])
6254 ; See comments above addsi_4 for details.
6255 (define_insn "*addqi_4"
6256 [(set (reg FLAGS_REG)
6257 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6258 (match_operand:QI 2 "const_int_operand" "n")))
6259 (clobber (match_scratch:QI 0 "=qm"))]
6260 "ix86_match_ccmode (insn, CCGCmode)
6261 && (INTVAL (operands[2]) & 0xff) != 0x80"
6263 switch (get_attr_type (insn))
6266 if (operands[2] == constm1_rtx
6267 || (GET_CODE (operands[2]) == CONST_INT
6268 && INTVAL (operands[2]) == 255))
6269 return "inc{b}\t%0";
6272 gcc_assert (operands[2] == const1_rtx);
6273 return "dec{b}\t%0";
6277 gcc_assert (rtx_equal_p (operands[0], operands[1]));
6278 if (INTVAL (operands[2]) < 0)
6280 operands[2] = GEN_INT (-INTVAL (operands[2]));
6281 return "add{b}\t{%2, %0|%0, %2}";
6283 return "sub{b}\t{%2, %0|%0, %2}";
6287 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6288 (const_string "incdec")
6289 (const_string "alu")))
6290 (set_attr "mode" "QI")])
6293 (define_insn "*addqi_5"
6294 [(set (reg FLAGS_REG)
6296 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6297 (match_operand:QI 2 "general_operand" "qmni"))
6299 (clobber (match_scratch:QI 0 "=q"))]
6300 "ix86_match_ccmode (insn, CCGOCmode)
6301 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6303 switch (get_attr_type (insn))
6306 if (operands[2] == const1_rtx)
6307 return "inc{b}\t%0";
6310 gcc_assert (operands[2] == constm1_rtx
6311 || (GET_CODE (operands[2]) == CONST_INT
6312 && INTVAL (operands[2]) == 255));
6313 return "dec{b}\t%0";
6317 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6318 if (GET_CODE (operands[2]) == CONST_INT
6319 && INTVAL (operands[2]) < 0)
6321 operands[2] = GEN_INT (-INTVAL (operands[2]));
6322 return "sub{b}\t{%2, %0|%0, %2}";
6324 return "add{b}\t{%2, %0|%0, %2}";
6328 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6329 (const_string "incdec")
6330 (const_string "alu")))
6331 (set_attr "mode" "QI")])
6334 (define_insn "addqi_ext_1"
6335 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6340 (match_operand 1 "ext_register_operand" "0")
6343 (match_operand:QI 2 "general_operand" "Qmn")))
6344 (clobber (reg:CC FLAGS_REG))]
6347 switch (get_attr_type (insn))
6350 if (operands[2] == const1_rtx)
6351 return "inc{b}\t%h0";
6354 gcc_assert (operands[2] == constm1_rtx
6355 || (GET_CODE (operands[2]) == CONST_INT
6356 && INTVAL (operands[2]) == 255));
6357 return "dec{b}\t%h0";
6361 return "add{b}\t{%2, %h0|%h0, %2}";
6365 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6366 (const_string "incdec")
6367 (const_string "alu")))
6368 (set_attr "mode" "QI")])
6370 (define_insn "*addqi_ext_1_rex64"
6371 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6376 (match_operand 1 "ext_register_operand" "0")
6379 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6380 (clobber (reg:CC FLAGS_REG))]
6383 switch (get_attr_type (insn))
6386 if (operands[2] == const1_rtx)
6387 return "inc{b}\t%h0";
6390 gcc_assert (operands[2] == constm1_rtx
6391 || (GET_CODE (operands[2]) == CONST_INT
6392 && INTVAL (operands[2]) == 255));
6393 return "dec{b}\t%h0";
6397 return "add{b}\t{%2, %h0|%h0, %2}";
6401 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6402 (const_string "incdec")
6403 (const_string "alu")))
6404 (set_attr "mode" "QI")])
6406 (define_insn "*addqi_ext_2"
6407 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6412 (match_operand 1 "ext_register_operand" "%0")
6416 (match_operand 2 "ext_register_operand" "Q")
6419 (clobber (reg:CC FLAGS_REG))]
6421 "add{b}\t{%h2, %h0|%h0, %h2}"
6422 [(set_attr "type" "alu")
6423 (set_attr "mode" "QI")])
6425 ;; The patterns that match these are at the end of this file.
6427 (define_expand "addxf3"
6428 [(set (match_operand:XF 0 "register_operand" "")
6429 (plus:XF (match_operand:XF 1 "register_operand" "")
6430 (match_operand:XF 2 "register_operand" "")))]
6434 (define_expand "adddf3"
6435 [(set (match_operand:DF 0 "register_operand" "")
6436 (plus:DF (match_operand:DF 1 "register_operand" "")
6437 (match_operand:DF 2 "nonimmediate_operand" "")))]
6438 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6441 (define_expand "addsf3"
6442 [(set (match_operand:SF 0 "register_operand" "")
6443 (plus:SF (match_operand:SF 1 "register_operand" "")
6444 (match_operand:SF 2 "nonimmediate_operand" "")))]
6445 "TARGET_80387 || TARGET_SSE_MATH"
6448 ;; Subtract instructions
6450 ;; %%% splits for subditi3
6452 (define_expand "subti3"
6453 [(parallel [(set (match_operand:TI 0 "nonimmediate_operand" "")
6454 (minus:TI (match_operand:TI 1 "nonimmediate_operand" "")
6455 (match_operand:TI 2 "x86_64_general_operand" "")))
6456 (clobber (reg:CC FLAGS_REG))])]
6458 "ix86_expand_binary_operator (MINUS, TImode, operands); DONE;")
6460 (define_insn "*subti3_1"
6461 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o")
6462 (minus:TI (match_operand:TI 1 "nonimmediate_operand" "0,0")
6463 (match_operand:TI 2 "general_operand" "roiF,riF")))
6464 (clobber (reg:CC FLAGS_REG))]
6465 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, TImode, operands)"
6469 [(set (match_operand:TI 0 "nonimmediate_operand" "")
6470 (minus:TI (match_operand:TI 1 "nonimmediate_operand" "")
6471 (match_operand:TI 2 "general_operand" "")))
6472 (clobber (reg:CC FLAGS_REG))]
6473 "TARGET_64BIT && reload_completed"
6474 [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
6475 (set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))])
6476 (parallel [(set (match_dup 3)
6477 (minus:DI (match_dup 4)
6478 (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
6480 (clobber (reg:CC FLAGS_REG))])]
6481 "split_ti (operands+0, 1, operands+0, operands+3);
6482 split_ti (operands+1, 1, operands+1, operands+4);
6483 split_ti (operands+2, 1, operands+2, operands+5);")
6485 ;; %%% splits for subsidi3
6487 (define_expand "subdi3"
6488 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6489 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6490 (match_operand:DI 2 "x86_64_general_operand" "")))
6491 (clobber (reg:CC FLAGS_REG))])]
6493 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6495 (define_insn "*subdi3_1"
6496 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6497 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6498 (match_operand:DI 2 "general_operand" "roiF,riF")))
6499 (clobber (reg:CC FLAGS_REG))]
6500 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6504 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6505 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6506 (match_operand:DI 2 "general_operand" "")))
6507 (clobber (reg:CC FLAGS_REG))]
6508 "!TARGET_64BIT && reload_completed"
6509 [(parallel [(set (reg:CC FLAGS_REG) (compare:CC (match_dup 1) (match_dup 2)))
6510 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6511 (parallel [(set (match_dup 3)
6512 (minus:SI (match_dup 4)
6513 (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
6515 (clobber (reg:CC FLAGS_REG))])]
6516 "split_di (operands+0, 1, operands+0, operands+3);
6517 split_di (operands+1, 1, operands+1, operands+4);
6518 split_di (operands+2, 1, operands+2, operands+5);")
6520 (define_insn "subdi3_carry_rex64"
6521 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6522 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6523 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6524 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6525 (clobber (reg:CC FLAGS_REG))]
6526 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6527 "sbb{q}\t{%2, %0|%0, %2}"
6528 [(set_attr "type" "alu")
6529 (set_attr "pent_pair" "pu")
6530 (set_attr "mode" "DI")])
6532 (define_insn "*subdi_1_rex64"
6533 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6534 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6535 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6536 (clobber (reg:CC FLAGS_REG))]
6537 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6538 "sub{q}\t{%2, %0|%0, %2}"
6539 [(set_attr "type" "alu")
6540 (set_attr "mode" "DI")])
6542 (define_insn "*subdi_2_rex64"
6543 [(set (reg FLAGS_REG)
6545 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6546 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6548 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6549 (minus:DI (match_dup 1) (match_dup 2)))]
6550 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6551 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6552 "sub{q}\t{%2, %0|%0, %2}"
6553 [(set_attr "type" "alu")
6554 (set_attr "mode" "DI")])
6556 (define_insn "*subdi_3_rex63"
6557 [(set (reg FLAGS_REG)
6558 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6559 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6560 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6561 (minus:DI (match_dup 1) (match_dup 2)))]
6562 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6563 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6564 "sub{q}\t{%2, %0|%0, %2}"
6565 [(set_attr "type" "alu")
6566 (set_attr "mode" "DI")])
6568 (define_insn "subqi3_carry"
6569 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6570 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6571 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6572 (match_operand:QI 2 "general_operand" "qi,qm"))))
6573 (clobber (reg:CC FLAGS_REG))]
6574 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6575 "sbb{b}\t{%2, %0|%0, %2}"
6576 [(set_attr "type" "alu")
6577 (set_attr "pent_pair" "pu")
6578 (set_attr "mode" "QI")])
6580 (define_insn "subhi3_carry"
6581 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6582 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6583 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6584 (match_operand:HI 2 "general_operand" "ri,rm"))))
6585 (clobber (reg:CC FLAGS_REG))]
6586 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6587 "sbb{w}\t{%2, %0|%0, %2}"
6588 [(set_attr "type" "alu")
6589 (set_attr "pent_pair" "pu")
6590 (set_attr "mode" "HI")])
6592 (define_insn "subsi3_carry"
6593 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6594 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6595 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6596 (match_operand:SI 2 "general_operand" "ri,rm"))))
6597 (clobber (reg:CC FLAGS_REG))]
6598 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6599 "sbb{l}\t{%2, %0|%0, %2}"
6600 [(set_attr "type" "alu")
6601 (set_attr "pent_pair" "pu")
6602 (set_attr "mode" "SI")])
6604 (define_insn "subsi3_carry_zext"
6605 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6607 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6608 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6609 (match_operand:SI 2 "general_operand" "ri,rm")))))
6610 (clobber (reg:CC FLAGS_REG))]
6611 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6612 "sbb{l}\t{%2, %k0|%k0, %2}"
6613 [(set_attr "type" "alu")
6614 (set_attr "pent_pair" "pu")
6615 (set_attr "mode" "SI")])
6617 (define_expand "subsi3"
6618 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6619 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6620 (match_operand:SI 2 "general_operand" "")))
6621 (clobber (reg:CC FLAGS_REG))])]
6623 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6625 (define_insn "*subsi_1"
6626 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6627 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6628 (match_operand:SI 2 "general_operand" "ri,rm")))
6629 (clobber (reg:CC FLAGS_REG))]
6630 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6631 "sub{l}\t{%2, %0|%0, %2}"
6632 [(set_attr "type" "alu")
6633 (set_attr "mode" "SI")])
6635 (define_insn "*subsi_1_zext"
6636 [(set (match_operand:DI 0 "register_operand" "=r")
6638 (minus:SI (match_operand:SI 1 "register_operand" "0")
6639 (match_operand:SI 2 "general_operand" "rim"))))
6640 (clobber (reg:CC FLAGS_REG))]
6641 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6642 "sub{l}\t{%2, %k0|%k0, %2}"
6643 [(set_attr "type" "alu")
6644 (set_attr "mode" "SI")])
6646 (define_insn "*subsi_2"
6647 [(set (reg FLAGS_REG)
6649 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6650 (match_operand:SI 2 "general_operand" "ri,rm"))
6652 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6653 (minus:SI (match_dup 1) (match_dup 2)))]
6654 "ix86_match_ccmode (insn, CCGOCmode)
6655 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6656 "sub{l}\t{%2, %0|%0, %2}"
6657 [(set_attr "type" "alu")
6658 (set_attr "mode" "SI")])
6660 (define_insn "*subsi_2_zext"
6661 [(set (reg FLAGS_REG)
6663 (minus:SI (match_operand:SI 1 "register_operand" "0")
6664 (match_operand:SI 2 "general_operand" "rim"))
6666 (set (match_operand:DI 0 "register_operand" "=r")
6668 (minus:SI (match_dup 1)
6670 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6671 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6672 "sub{l}\t{%2, %k0|%k0, %2}"
6673 [(set_attr "type" "alu")
6674 (set_attr "mode" "SI")])
6676 (define_insn "*subsi_3"
6677 [(set (reg FLAGS_REG)
6678 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
6679 (match_operand:SI 2 "general_operand" "ri,rm")))
6680 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6681 (minus:SI (match_dup 1) (match_dup 2)))]
6682 "ix86_match_ccmode (insn, CCmode)
6683 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6684 "sub{l}\t{%2, %0|%0, %2}"
6685 [(set_attr "type" "alu")
6686 (set_attr "mode" "SI")])
6688 (define_insn "*subsi_3_zext"
6689 [(set (reg FLAGS_REG)
6690 (compare (match_operand:SI 1 "register_operand" "0")
6691 (match_operand:SI 2 "general_operand" "rim")))
6692 (set (match_operand:DI 0 "register_operand" "=r")
6694 (minus:SI (match_dup 1)
6696 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6697 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6698 "sub{q}\t{%2, %0|%0, %2}"
6699 [(set_attr "type" "alu")
6700 (set_attr "mode" "DI")])
6702 (define_expand "subhi3"
6703 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6704 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6705 (match_operand:HI 2 "general_operand" "")))
6706 (clobber (reg:CC FLAGS_REG))])]
6707 "TARGET_HIMODE_MATH"
6708 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
6710 (define_insn "*subhi_1"
6711 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6712 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6713 (match_operand:HI 2 "general_operand" "ri,rm")))
6714 (clobber (reg:CC FLAGS_REG))]
6715 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6716 "sub{w}\t{%2, %0|%0, %2}"
6717 [(set_attr "type" "alu")
6718 (set_attr "mode" "HI")])
6720 (define_insn "*subhi_2"
6721 [(set (reg FLAGS_REG)
6723 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6724 (match_operand:HI 2 "general_operand" "ri,rm"))
6726 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6727 (minus:HI (match_dup 1) (match_dup 2)))]
6728 "ix86_match_ccmode (insn, CCGOCmode)
6729 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6730 "sub{w}\t{%2, %0|%0, %2}"
6731 [(set_attr "type" "alu")
6732 (set_attr "mode" "HI")])
6734 (define_insn "*subhi_3"
6735 [(set (reg FLAGS_REG)
6736 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
6737 (match_operand:HI 2 "general_operand" "ri,rm")))
6738 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6739 (minus:HI (match_dup 1) (match_dup 2)))]
6740 "ix86_match_ccmode (insn, CCmode)
6741 && ix86_binary_operator_ok (MINUS, HImode, operands)"
6742 "sub{w}\t{%2, %0|%0, %2}"
6743 [(set_attr "type" "alu")
6744 (set_attr "mode" "HI")])
6746 (define_expand "subqi3"
6747 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6748 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6749 (match_operand:QI 2 "general_operand" "")))
6750 (clobber (reg:CC FLAGS_REG))])]
6751 "TARGET_QIMODE_MATH"
6752 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
6754 (define_insn "*subqi_1"
6755 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
6756 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6757 (match_operand:QI 2 "general_operand" "qn,qmn")))
6758 (clobber (reg:CC FLAGS_REG))]
6759 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6760 "sub{b}\t{%2, %0|%0, %2}"
6761 [(set_attr "type" "alu")
6762 (set_attr "mode" "QI")])
6764 (define_insn "*subqi_1_slp"
6765 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6766 (minus:QI (match_dup 0)
6767 (match_operand:QI 1 "general_operand" "qn,qmn")))
6768 (clobber (reg:CC FLAGS_REG))]
6769 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6770 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6771 "sub{b}\t{%1, %0|%0, %1}"
6772 [(set_attr "type" "alu1")
6773 (set_attr "mode" "QI")])
6775 (define_insn "*subqi_2"
6776 [(set (reg FLAGS_REG)
6778 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6779 (match_operand:QI 2 "general_operand" "qi,qm"))
6781 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6782 (minus:HI (match_dup 1) (match_dup 2)))]
6783 "ix86_match_ccmode (insn, CCGOCmode)
6784 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6785 "sub{b}\t{%2, %0|%0, %2}"
6786 [(set_attr "type" "alu")
6787 (set_attr "mode" "QI")])
6789 (define_insn "*subqi_3"
6790 [(set (reg FLAGS_REG)
6791 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
6792 (match_operand:QI 2 "general_operand" "qi,qm")))
6793 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
6794 (minus:HI (match_dup 1) (match_dup 2)))]
6795 "ix86_match_ccmode (insn, CCmode)
6796 && ix86_binary_operator_ok (MINUS, QImode, operands)"
6797 "sub{b}\t{%2, %0|%0, %2}"
6798 [(set_attr "type" "alu")
6799 (set_attr "mode" "QI")])
6801 ;; The patterns that match these are at the end of this file.
6803 (define_expand "subxf3"
6804 [(set (match_operand:XF 0 "register_operand" "")
6805 (minus:XF (match_operand:XF 1 "register_operand" "")
6806 (match_operand:XF 2 "register_operand" "")))]
6810 (define_expand "subdf3"
6811 [(set (match_operand:DF 0 "register_operand" "")
6812 (minus:DF (match_operand:DF 1 "register_operand" "")
6813 (match_operand:DF 2 "nonimmediate_operand" "")))]
6814 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6817 (define_expand "subsf3"
6818 [(set (match_operand:SF 0 "register_operand" "")
6819 (minus:SF (match_operand:SF 1 "register_operand" "")
6820 (match_operand:SF 2 "nonimmediate_operand" "")))]
6821 "TARGET_80387 || TARGET_SSE_MATH"
6824 ;; Multiply instructions
6826 (define_expand "muldi3"
6827 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6828 (mult:DI (match_operand:DI 1 "register_operand" "")
6829 (match_operand:DI 2 "x86_64_general_operand" "")))
6830 (clobber (reg:CC FLAGS_REG))])]
6834 (define_insn "*muldi3_1_rex64"
6835 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6836 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
6837 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
6838 (clobber (reg:CC FLAGS_REG))]
6840 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6842 imul{q}\t{%2, %1, %0|%0, %1, %2}
6843 imul{q}\t{%2, %1, %0|%0, %1, %2}
6844 imul{q}\t{%2, %0|%0, %2}"
6845 [(set_attr "type" "imul")
6846 (set_attr "prefix_0f" "0,0,1")
6847 (set (attr "athlon_decode")
6848 (cond [(eq_attr "cpu" "athlon")
6849 (const_string "vector")
6850 (eq_attr "alternative" "1")
6851 (const_string "vector")
6852 (and (eq_attr "alternative" "2")
6853 (match_operand 1 "memory_operand" ""))
6854 (const_string "vector")]
6855 (const_string "direct")))
6856 (set_attr "mode" "DI")])
6858 (define_expand "mulsi3"
6859 [(parallel [(set (match_operand:SI 0 "register_operand" "")
6860 (mult:SI (match_operand:SI 1 "register_operand" "")
6861 (match_operand:SI 2 "general_operand" "")))
6862 (clobber (reg:CC FLAGS_REG))])]
6866 (define_insn "*mulsi3_1"
6867 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
6868 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
6869 (match_operand:SI 2 "general_operand" "K,i,mr")))
6870 (clobber (reg:CC FLAGS_REG))]
6871 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6873 imul{l}\t{%2, %1, %0|%0, %1, %2}
6874 imul{l}\t{%2, %1, %0|%0, %1, %2}
6875 imul{l}\t{%2, %0|%0, %2}"
6876 [(set_attr "type" "imul")
6877 (set_attr "prefix_0f" "0,0,1")
6878 (set (attr "athlon_decode")
6879 (cond [(eq_attr "cpu" "athlon")
6880 (const_string "vector")
6881 (eq_attr "alternative" "1")
6882 (const_string "vector")
6883 (and (eq_attr "alternative" "2")
6884 (match_operand 1 "memory_operand" ""))
6885 (const_string "vector")]
6886 (const_string "direct")))
6887 (set_attr "mode" "SI")])
6889 (define_insn "*mulsi3_1_zext"
6890 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
6892 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
6893 (match_operand:SI 2 "general_operand" "K,i,mr"))))
6894 (clobber (reg:CC FLAGS_REG))]
6896 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6898 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6899 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
6900 imul{l}\t{%2, %k0|%k0, %2}"
6901 [(set_attr "type" "imul")
6902 (set_attr "prefix_0f" "0,0,1")
6903 (set (attr "athlon_decode")
6904 (cond [(eq_attr "cpu" "athlon")
6905 (const_string "vector")
6906 (eq_attr "alternative" "1")
6907 (const_string "vector")
6908 (and (eq_attr "alternative" "2")
6909 (match_operand 1 "memory_operand" ""))
6910 (const_string "vector")]
6911 (const_string "direct")))
6912 (set_attr "mode" "SI")])
6914 (define_expand "mulhi3"
6915 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6916 (mult:HI (match_operand:HI 1 "register_operand" "")
6917 (match_operand:HI 2 "general_operand" "")))
6918 (clobber (reg:CC FLAGS_REG))])]
6919 "TARGET_HIMODE_MATH"
6922 (define_insn "*mulhi3_1"
6923 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
6924 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
6925 (match_operand:HI 2 "general_operand" "K,i,mr")))
6926 (clobber (reg:CC FLAGS_REG))]
6927 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
6929 imul{w}\t{%2, %1, %0|%0, %1, %2}
6930 imul{w}\t{%2, %1, %0|%0, %1, %2}
6931 imul{w}\t{%2, %0|%0, %2}"
6932 [(set_attr "type" "imul")
6933 (set_attr "prefix_0f" "0,0,1")
6934 (set (attr "athlon_decode")
6935 (cond [(eq_attr "cpu" "athlon")
6936 (const_string "vector")
6937 (eq_attr "alternative" "1,2")
6938 (const_string "vector")]
6939 (const_string "direct")))
6940 (set_attr "mode" "HI")])
6942 (define_expand "mulqi3"
6943 [(parallel [(set (match_operand:QI 0 "register_operand" "")
6944 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
6945 (match_operand:QI 2 "register_operand" "")))
6946 (clobber (reg:CC FLAGS_REG))])]
6947 "TARGET_QIMODE_MATH"
6950 (define_insn "*mulqi3_1"
6951 [(set (match_operand:QI 0 "register_operand" "=a")
6952 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6953 (match_operand:QI 2 "nonimmediate_operand" "qm")))
6954 (clobber (reg:CC FLAGS_REG))]
6956 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6958 [(set_attr "type" "imul")
6959 (set_attr "length_immediate" "0")
6960 (set (attr "athlon_decode")
6961 (if_then_else (eq_attr "cpu" "athlon")
6962 (const_string "vector")
6963 (const_string "direct")))
6964 (set_attr "mode" "QI")])
6966 (define_expand "umulqihi3"
6967 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6968 (mult:HI (zero_extend:HI
6969 (match_operand:QI 1 "nonimmediate_operand" ""))
6971 (match_operand:QI 2 "register_operand" ""))))
6972 (clobber (reg:CC FLAGS_REG))])]
6973 "TARGET_QIMODE_MATH"
6976 (define_insn "*umulqihi3_1"
6977 [(set (match_operand:HI 0 "register_operand" "=a")
6978 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
6979 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
6980 (clobber (reg:CC FLAGS_REG))]
6982 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6984 [(set_attr "type" "imul")
6985 (set_attr "length_immediate" "0")
6986 (set (attr "athlon_decode")
6987 (if_then_else (eq_attr "cpu" "athlon")
6988 (const_string "vector")
6989 (const_string "direct")))
6990 (set_attr "mode" "QI")])
6992 (define_expand "mulqihi3"
6993 [(parallel [(set (match_operand:HI 0 "register_operand" "")
6994 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
6995 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
6996 (clobber (reg:CC FLAGS_REG))])]
6997 "TARGET_QIMODE_MATH"
7000 (define_insn "*mulqihi3_insn"
7001 [(set (match_operand:HI 0 "register_operand" "=a")
7002 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7003 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7004 (clobber (reg:CC FLAGS_REG))]
7006 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7008 [(set_attr "type" "imul")
7009 (set_attr "length_immediate" "0")
7010 (set (attr "athlon_decode")
7011 (if_then_else (eq_attr "cpu" "athlon")
7012 (const_string "vector")
7013 (const_string "direct")))
7014 (set_attr "mode" "QI")])
7016 (define_expand "umulditi3"
7017 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7018 (mult:TI (zero_extend:TI
7019 (match_operand:DI 1 "nonimmediate_operand" ""))
7021 (match_operand:DI 2 "register_operand" ""))))
7022 (clobber (reg:CC FLAGS_REG))])]
7026 (define_insn "*umulditi3_insn"
7027 [(set (match_operand:TI 0 "register_operand" "=A")
7028 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7029 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7030 (clobber (reg:CC FLAGS_REG))]
7032 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7034 [(set_attr "type" "imul")
7035 (set_attr "length_immediate" "0")
7036 (set (attr "athlon_decode")
7037 (if_then_else (eq_attr "cpu" "athlon")
7038 (const_string "vector")
7039 (const_string "double")))
7040 (set_attr "mode" "DI")])
7042 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7043 (define_expand "umulsidi3"
7044 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7045 (mult:DI (zero_extend:DI
7046 (match_operand:SI 1 "nonimmediate_operand" ""))
7048 (match_operand:SI 2 "register_operand" ""))))
7049 (clobber (reg:CC FLAGS_REG))])]
7053 (define_insn "*umulsidi3_insn"
7054 [(set (match_operand:DI 0 "register_operand" "=A")
7055 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7056 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7057 (clobber (reg:CC FLAGS_REG))]
7059 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7061 [(set_attr "type" "imul")
7062 (set_attr "length_immediate" "0")
7063 (set (attr "athlon_decode")
7064 (if_then_else (eq_attr "cpu" "athlon")
7065 (const_string "vector")
7066 (const_string "double")))
7067 (set_attr "mode" "SI")])
7069 (define_expand "mulditi3"
7070 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7071 (mult:TI (sign_extend:TI
7072 (match_operand:DI 1 "nonimmediate_operand" ""))
7074 (match_operand:DI 2 "register_operand" ""))))
7075 (clobber (reg:CC FLAGS_REG))])]
7079 (define_insn "*mulditi3_insn"
7080 [(set (match_operand:TI 0 "register_operand" "=A")
7081 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7082 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7083 (clobber (reg:CC FLAGS_REG))]
7085 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7087 [(set_attr "type" "imul")
7088 (set_attr "length_immediate" "0")
7089 (set (attr "athlon_decode")
7090 (if_then_else (eq_attr "cpu" "athlon")
7091 (const_string "vector")
7092 (const_string "double")))
7093 (set_attr "mode" "DI")])
7095 (define_expand "mulsidi3"
7096 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7097 (mult:DI (sign_extend:DI
7098 (match_operand:SI 1 "nonimmediate_operand" ""))
7100 (match_operand:SI 2 "register_operand" ""))))
7101 (clobber (reg:CC FLAGS_REG))])]
7105 (define_insn "*mulsidi3_insn"
7106 [(set (match_operand:DI 0 "register_operand" "=A")
7107 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7108 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7109 (clobber (reg:CC FLAGS_REG))]
7111 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7113 [(set_attr "type" "imul")
7114 (set_attr "length_immediate" "0")
7115 (set (attr "athlon_decode")
7116 (if_then_else (eq_attr "cpu" "athlon")
7117 (const_string "vector")
7118 (const_string "double")))
7119 (set_attr "mode" "SI")])
7121 (define_expand "umuldi3_highpart"
7122 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7125 (mult:TI (zero_extend:TI
7126 (match_operand:DI 1 "nonimmediate_operand" ""))
7128 (match_operand:DI 2 "register_operand" "")))
7130 (clobber (match_scratch:DI 3 ""))
7131 (clobber (reg:CC FLAGS_REG))])]
7135 (define_insn "*umuldi3_highpart_rex64"
7136 [(set (match_operand:DI 0 "register_operand" "=d")
7139 (mult:TI (zero_extend:TI
7140 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7142 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7144 (clobber (match_scratch:DI 3 "=1"))
7145 (clobber (reg:CC FLAGS_REG))]
7147 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7149 [(set_attr "type" "imul")
7150 (set_attr "length_immediate" "0")
7151 (set (attr "athlon_decode")
7152 (if_then_else (eq_attr "cpu" "athlon")
7153 (const_string "vector")
7154 (const_string "double")))
7155 (set_attr "mode" "DI")])
7157 (define_expand "umulsi3_highpart"
7158 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7161 (mult:DI (zero_extend:DI
7162 (match_operand:SI 1 "nonimmediate_operand" ""))
7164 (match_operand:SI 2 "register_operand" "")))
7166 (clobber (match_scratch:SI 3 ""))
7167 (clobber (reg:CC FLAGS_REG))])]
7171 (define_insn "*umulsi3_highpart_insn"
7172 [(set (match_operand:SI 0 "register_operand" "=d")
7175 (mult:DI (zero_extend:DI
7176 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7178 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7180 (clobber (match_scratch:SI 3 "=1"))
7181 (clobber (reg:CC FLAGS_REG))]
7182 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7184 [(set_attr "type" "imul")
7185 (set_attr "length_immediate" "0")
7186 (set (attr "athlon_decode")
7187 (if_then_else (eq_attr "cpu" "athlon")
7188 (const_string "vector")
7189 (const_string "double")))
7190 (set_attr "mode" "SI")])
7192 (define_insn "*umulsi3_highpart_zext"
7193 [(set (match_operand:DI 0 "register_operand" "=d")
7194 (zero_extend:DI (truncate:SI
7196 (mult:DI (zero_extend:DI
7197 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7199 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7201 (clobber (match_scratch:SI 3 "=1"))
7202 (clobber (reg:CC FLAGS_REG))]
7204 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7206 [(set_attr "type" "imul")
7207 (set_attr "length_immediate" "0")
7208 (set (attr "athlon_decode")
7209 (if_then_else (eq_attr "cpu" "athlon")
7210 (const_string "vector")
7211 (const_string "double")))
7212 (set_attr "mode" "SI")])
7214 (define_expand "smuldi3_highpart"
7215 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7218 (mult:TI (sign_extend:TI
7219 (match_operand:DI 1 "nonimmediate_operand" ""))
7221 (match_operand:DI 2 "register_operand" "")))
7223 (clobber (match_scratch:DI 3 ""))
7224 (clobber (reg:CC FLAGS_REG))])]
7228 (define_insn "*smuldi3_highpart_rex64"
7229 [(set (match_operand:DI 0 "register_operand" "=d")
7232 (mult:TI (sign_extend:TI
7233 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7235 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7237 (clobber (match_scratch:DI 3 "=1"))
7238 (clobber (reg:CC FLAGS_REG))]
7240 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7242 [(set_attr "type" "imul")
7243 (set (attr "athlon_decode")
7244 (if_then_else (eq_attr "cpu" "athlon")
7245 (const_string "vector")
7246 (const_string "double")))
7247 (set_attr "mode" "DI")])
7249 (define_expand "smulsi3_highpart"
7250 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7253 (mult:DI (sign_extend:DI
7254 (match_operand:SI 1 "nonimmediate_operand" ""))
7256 (match_operand:SI 2 "register_operand" "")))
7258 (clobber (match_scratch:SI 3 ""))
7259 (clobber (reg:CC FLAGS_REG))])]
7263 (define_insn "*smulsi3_highpart_insn"
7264 [(set (match_operand:SI 0 "register_operand" "=d")
7267 (mult:DI (sign_extend:DI
7268 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7270 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7272 (clobber (match_scratch:SI 3 "=1"))
7273 (clobber (reg:CC FLAGS_REG))]
7274 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7276 [(set_attr "type" "imul")
7277 (set (attr "athlon_decode")
7278 (if_then_else (eq_attr "cpu" "athlon")
7279 (const_string "vector")
7280 (const_string "double")))
7281 (set_attr "mode" "SI")])
7283 (define_insn "*smulsi3_highpart_zext"
7284 [(set (match_operand:DI 0 "register_operand" "=d")
7285 (zero_extend:DI (truncate:SI
7287 (mult:DI (sign_extend:DI
7288 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7290 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7292 (clobber (match_scratch:SI 3 "=1"))
7293 (clobber (reg:CC FLAGS_REG))]
7295 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7297 [(set_attr "type" "imul")
7298 (set (attr "athlon_decode")
7299 (if_then_else (eq_attr "cpu" "athlon")
7300 (const_string "vector")
7301 (const_string "double")))
7302 (set_attr "mode" "SI")])
7304 ;; The patterns that match these are at the end of this file.
7306 (define_expand "mulxf3"
7307 [(set (match_operand:XF 0 "register_operand" "")
7308 (mult:XF (match_operand:XF 1 "register_operand" "")
7309 (match_operand:XF 2 "register_operand" "")))]
7313 (define_expand "muldf3"
7314 [(set (match_operand:DF 0 "register_operand" "")
7315 (mult:DF (match_operand:DF 1 "register_operand" "")
7316 (match_operand:DF 2 "nonimmediate_operand" "")))]
7317 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7320 (define_expand "mulsf3"
7321 [(set (match_operand:SF 0 "register_operand" "")
7322 (mult:SF (match_operand:SF 1 "register_operand" "")
7323 (match_operand:SF 2 "nonimmediate_operand" "")))]
7324 "TARGET_80387 || TARGET_SSE_MATH"
7327 ;; Divide instructions
7329 (define_insn "divqi3"
7330 [(set (match_operand:QI 0 "register_operand" "=a")
7331 (div:QI (match_operand:HI 1 "register_operand" "0")
7332 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7333 (clobber (reg:CC FLAGS_REG))]
7334 "TARGET_QIMODE_MATH"
7336 [(set_attr "type" "idiv")
7337 (set_attr "mode" "QI")])
7339 (define_insn "udivqi3"
7340 [(set (match_operand:QI 0 "register_operand" "=a")
7341 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7342 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7343 (clobber (reg:CC FLAGS_REG))]
7344 "TARGET_QIMODE_MATH"
7346 [(set_attr "type" "idiv")
7347 (set_attr "mode" "QI")])
7349 ;; The patterns that match these are at the end of this file.
7351 (define_expand "divxf3"
7352 [(set (match_operand:XF 0 "register_operand" "")
7353 (div:XF (match_operand:XF 1 "register_operand" "")
7354 (match_operand:XF 2 "register_operand" "")))]
7358 (define_expand "divdf3"
7359 [(set (match_operand:DF 0 "register_operand" "")
7360 (div:DF (match_operand:DF 1 "register_operand" "")
7361 (match_operand:DF 2 "nonimmediate_operand" "")))]
7362 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7365 (define_expand "divsf3"
7366 [(set (match_operand:SF 0 "register_operand" "")
7367 (div:SF (match_operand:SF 1 "register_operand" "")
7368 (match_operand:SF 2 "nonimmediate_operand" "")))]
7369 "TARGET_80387 || TARGET_SSE_MATH"
7372 ;; Remainder instructions.
7374 (define_expand "divmoddi4"
7375 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7376 (div:DI (match_operand:DI 1 "register_operand" "")
7377 (match_operand:DI 2 "nonimmediate_operand" "")))
7378 (set (match_operand:DI 3 "register_operand" "")
7379 (mod:DI (match_dup 1) (match_dup 2)))
7380 (clobber (reg:CC FLAGS_REG))])]
7384 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7385 ;; Penalize eax case slightly because it results in worse scheduling
7387 (define_insn "*divmoddi4_nocltd_rex64"
7388 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7389 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7390 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7391 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7392 (mod:DI (match_dup 2) (match_dup 3)))
7393 (clobber (reg:CC FLAGS_REG))]
7394 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7396 [(set_attr "type" "multi")])
7398 (define_insn "*divmoddi4_cltd_rex64"
7399 [(set (match_operand:DI 0 "register_operand" "=a")
7400 (div:DI (match_operand:DI 2 "register_operand" "a")
7401 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7402 (set (match_operand:DI 1 "register_operand" "=&d")
7403 (mod:DI (match_dup 2) (match_dup 3)))
7404 (clobber (reg:CC FLAGS_REG))]
7405 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7407 [(set_attr "type" "multi")])
7409 (define_insn "*divmoddi_noext_rex64"
7410 [(set (match_operand:DI 0 "register_operand" "=a")
7411 (div:DI (match_operand:DI 1 "register_operand" "0")
7412 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7413 (set (match_operand:DI 3 "register_operand" "=d")
7414 (mod:DI (match_dup 1) (match_dup 2)))
7415 (use (match_operand:DI 4 "register_operand" "3"))
7416 (clobber (reg:CC FLAGS_REG))]
7419 [(set_attr "type" "idiv")
7420 (set_attr "mode" "DI")])
7423 [(set (match_operand:DI 0 "register_operand" "")
7424 (div:DI (match_operand:DI 1 "register_operand" "")
7425 (match_operand:DI 2 "nonimmediate_operand" "")))
7426 (set (match_operand:DI 3 "register_operand" "")
7427 (mod:DI (match_dup 1) (match_dup 2)))
7428 (clobber (reg:CC FLAGS_REG))]
7429 "TARGET_64BIT && reload_completed"
7430 [(parallel [(set (match_dup 3)
7431 (ashiftrt:DI (match_dup 4) (const_int 63)))
7432 (clobber (reg:CC FLAGS_REG))])
7433 (parallel [(set (match_dup 0)
7434 (div:DI (reg:DI 0) (match_dup 2)))
7436 (mod:DI (reg:DI 0) (match_dup 2)))
7438 (clobber (reg:CC FLAGS_REG))])]
7440 /* Avoid use of cltd in favor of a mov+shift. */
7441 if (!TARGET_USE_CLTD && !optimize_size)
7443 if (true_regnum (operands[1]))
7444 emit_move_insn (operands[0], operands[1]);
7446 emit_move_insn (operands[3], operands[1]);
7447 operands[4] = operands[3];
7451 gcc_assert (!true_regnum (operands[1]));
7452 operands[4] = operands[1];
7457 (define_expand "divmodsi4"
7458 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7459 (div:SI (match_operand:SI 1 "register_operand" "")
7460 (match_operand:SI 2 "nonimmediate_operand" "")))
7461 (set (match_operand:SI 3 "register_operand" "")
7462 (mod:SI (match_dup 1) (match_dup 2)))
7463 (clobber (reg:CC FLAGS_REG))])]
7467 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7468 ;; Penalize eax case slightly because it results in worse scheduling
7470 (define_insn "*divmodsi4_nocltd"
7471 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7472 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7473 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7474 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7475 (mod:SI (match_dup 2) (match_dup 3)))
7476 (clobber (reg:CC FLAGS_REG))]
7477 "!optimize_size && !TARGET_USE_CLTD"
7479 [(set_attr "type" "multi")])
7481 (define_insn "*divmodsi4_cltd"
7482 [(set (match_operand:SI 0 "register_operand" "=a")
7483 (div:SI (match_operand:SI 2 "register_operand" "a")
7484 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7485 (set (match_operand:SI 1 "register_operand" "=&d")
7486 (mod:SI (match_dup 2) (match_dup 3)))
7487 (clobber (reg:CC FLAGS_REG))]
7488 "optimize_size || TARGET_USE_CLTD"
7490 [(set_attr "type" "multi")])
7492 (define_insn "*divmodsi_noext"
7493 [(set (match_operand:SI 0 "register_operand" "=a")
7494 (div:SI (match_operand:SI 1 "register_operand" "0")
7495 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7496 (set (match_operand:SI 3 "register_operand" "=d")
7497 (mod:SI (match_dup 1) (match_dup 2)))
7498 (use (match_operand:SI 4 "register_operand" "3"))
7499 (clobber (reg:CC FLAGS_REG))]
7502 [(set_attr "type" "idiv")
7503 (set_attr "mode" "SI")])
7506 [(set (match_operand:SI 0 "register_operand" "")
7507 (div:SI (match_operand:SI 1 "register_operand" "")
7508 (match_operand:SI 2 "nonimmediate_operand" "")))
7509 (set (match_operand:SI 3 "register_operand" "")
7510 (mod:SI (match_dup 1) (match_dup 2)))
7511 (clobber (reg:CC FLAGS_REG))]
7513 [(parallel [(set (match_dup 3)
7514 (ashiftrt:SI (match_dup 4) (const_int 31)))
7515 (clobber (reg:CC FLAGS_REG))])
7516 (parallel [(set (match_dup 0)
7517 (div:SI (reg:SI 0) (match_dup 2)))
7519 (mod:SI (reg:SI 0) (match_dup 2)))
7521 (clobber (reg:CC FLAGS_REG))])]
7523 /* Avoid use of cltd in favor of a mov+shift. */
7524 if (!TARGET_USE_CLTD && !optimize_size)
7526 if (true_regnum (operands[1]))
7527 emit_move_insn (operands[0], operands[1]);
7529 emit_move_insn (operands[3], operands[1]);
7530 operands[4] = operands[3];
7534 gcc_assert (!true_regnum (operands[1]));
7535 operands[4] = operands[1];
7539 (define_insn "divmodhi4"
7540 [(set (match_operand:HI 0 "register_operand" "=a")
7541 (div:HI (match_operand:HI 1 "register_operand" "0")
7542 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7543 (set (match_operand:HI 3 "register_operand" "=&d")
7544 (mod:HI (match_dup 1) (match_dup 2)))
7545 (clobber (reg:CC FLAGS_REG))]
7546 "TARGET_HIMODE_MATH"
7548 [(set_attr "type" "multi")
7549 (set_attr "length_immediate" "0")
7550 (set_attr "mode" "SI")])
7552 (define_insn "udivmoddi4"
7553 [(set (match_operand:DI 0 "register_operand" "=a")
7554 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7555 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7556 (set (match_operand:DI 3 "register_operand" "=&d")
7557 (umod:DI (match_dup 1) (match_dup 2)))
7558 (clobber (reg:CC FLAGS_REG))]
7560 "xor{q}\t%3, %3\;div{q}\t%2"
7561 [(set_attr "type" "multi")
7562 (set_attr "length_immediate" "0")
7563 (set_attr "mode" "DI")])
7565 (define_insn "*udivmoddi4_noext"
7566 [(set (match_operand:DI 0 "register_operand" "=a")
7567 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7568 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7569 (set (match_operand:DI 3 "register_operand" "=d")
7570 (umod:DI (match_dup 1) (match_dup 2)))
7572 (clobber (reg:CC FLAGS_REG))]
7575 [(set_attr "type" "idiv")
7576 (set_attr "mode" "DI")])
7579 [(set (match_operand:DI 0 "register_operand" "")
7580 (udiv:DI (match_operand:DI 1 "register_operand" "")
7581 (match_operand:DI 2 "nonimmediate_operand" "")))
7582 (set (match_operand:DI 3 "register_operand" "")
7583 (umod:DI (match_dup 1) (match_dup 2)))
7584 (clobber (reg:CC FLAGS_REG))]
7585 "TARGET_64BIT && reload_completed"
7586 [(set (match_dup 3) (const_int 0))
7587 (parallel [(set (match_dup 0)
7588 (udiv:DI (match_dup 1) (match_dup 2)))
7590 (umod:DI (match_dup 1) (match_dup 2)))
7592 (clobber (reg:CC FLAGS_REG))])]
7595 (define_insn "udivmodsi4"
7596 [(set (match_operand:SI 0 "register_operand" "=a")
7597 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7598 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7599 (set (match_operand:SI 3 "register_operand" "=&d")
7600 (umod:SI (match_dup 1) (match_dup 2)))
7601 (clobber (reg:CC FLAGS_REG))]
7603 "xor{l}\t%3, %3\;div{l}\t%2"
7604 [(set_attr "type" "multi")
7605 (set_attr "length_immediate" "0")
7606 (set_attr "mode" "SI")])
7608 (define_insn "*udivmodsi4_noext"
7609 [(set (match_operand:SI 0 "register_operand" "=a")
7610 (udiv:SI (match_operand:SI 1 "register_operand" "0")
7611 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7612 (set (match_operand:SI 3 "register_operand" "=d")
7613 (umod:SI (match_dup 1) (match_dup 2)))
7615 (clobber (reg:CC FLAGS_REG))]
7618 [(set_attr "type" "idiv")
7619 (set_attr "mode" "SI")])
7622 [(set (match_operand:SI 0 "register_operand" "")
7623 (udiv:SI (match_operand:SI 1 "register_operand" "")
7624 (match_operand:SI 2 "nonimmediate_operand" "")))
7625 (set (match_operand:SI 3 "register_operand" "")
7626 (umod:SI (match_dup 1) (match_dup 2)))
7627 (clobber (reg:CC FLAGS_REG))]
7629 [(set (match_dup 3) (const_int 0))
7630 (parallel [(set (match_dup 0)
7631 (udiv:SI (match_dup 1) (match_dup 2)))
7633 (umod:SI (match_dup 1) (match_dup 2)))
7635 (clobber (reg:CC FLAGS_REG))])]
7638 (define_expand "udivmodhi4"
7639 [(set (match_dup 4) (const_int 0))
7640 (parallel [(set (match_operand:HI 0 "register_operand" "")
7641 (udiv:HI (match_operand:HI 1 "register_operand" "")
7642 (match_operand:HI 2 "nonimmediate_operand" "")))
7643 (set (match_operand:HI 3 "register_operand" "")
7644 (umod:HI (match_dup 1) (match_dup 2)))
7646 (clobber (reg:CC FLAGS_REG))])]
7647 "TARGET_HIMODE_MATH"
7648 "operands[4] = gen_reg_rtx (HImode);")
7650 (define_insn "*udivmodhi_noext"
7651 [(set (match_operand:HI 0 "register_operand" "=a")
7652 (udiv:HI (match_operand:HI 1 "register_operand" "0")
7653 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7654 (set (match_operand:HI 3 "register_operand" "=d")
7655 (umod:HI (match_dup 1) (match_dup 2)))
7656 (use (match_operand:HI 4 "register_operand" "3"))
7657 (clobber (reg:CC FLAGS_REG))]
7660 [(set_attr "type" "idiv")
7661 (set_attr "mode" "HI")])
7663 ;; We cannot use div/idiv for double division, because it causes
7664 ;; "division by zero" on the overflow and that's not what we expect
7665 ;; from truncate. Because true (non truncating) double division is
7666 ;; never generated, we can't create this insn anyway.
7669 ; [(set (match_operand:SI 0 "register_operand" "=a")
7671 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
7673 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
7674 ; (set (match_operand:SI 3 "register_operand" "=d")
7676 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
7677 ; (clobber (reg:CC FLAGS_REG))]
7679 ; "div{l}\t{%2, %0|%0, %2}"
7680 ; [(set_attr "type" "idiv")])
7682 ;;- Logical AND instructions
7684 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
7685 ;; Note that this excludes ah.
7687 (define_insn "*testdi_1_rex64"
7688 [(set (reg FLAGS_REG)
7690 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
7691 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
7693 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7694 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7696 test{l}\t{%k1, %k0|%k0, %k1}
7697 test{l}\t{%k1, %k0|%k0, %k1}
7698 test{q}\t{%1, %0|%0, %1}
7699 test{q}\t{%1, %0|%0, %1}
7700 test{q}\t{%1, %0|%0, %1}"
7701 [(set_attr "type" "test")
7702 (set_attr "modrm" "0,1,0,1,1")
7703 (set_attr "mode" "SI,SI,DI,DI,DI")
7704 (set_attr "pent_pair" "uv,np,uv,np,uv")])
7706 (define_insn "testsi_1"
7707 [(set (reg FLAGS_REG)
7709 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
7710 (match_operand:SI 1 "general_operand" "in,in,rin"))
7712 "ix86_match_ccmode (insn, CCNOmode)
7713 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7714 "test{l}\t{%1, %0|%0, %1}"
7715 [(set_attr "type" "test")
7716 (set_attr "modrm" "0,1,1")
7717 (set_attr "mode" "SI")
7718 (set_attr "pent_pair" "uv,np,uv")])
7720 (define_expand "testsi_ccno_1"
7721 [(set (reg:CCNO FLAGS_REG)
7723 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
7724 (match_operand:SI 1 "nonmemory_operand" ""))
7729 (define_insn "*testhi_1"
7730 [(set (reg FLAGS_REG)
7731 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
7732 (match_operand:HI 1 "general_operand" "n,n,rn"))
7734 "ix86_match_ccmode (insn, CCNOmode)
7735 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7736 "test{w}\t{%1, %0|%0, %1}"
7737 [(set_attr "type" "test")
7738 (set_attr "modrm" "0,1,1")
7739 (set_attr "mode" "HI")
7740 (set_attr "pent_pair" "uv,np,uv")])
7742 (define_expand "testqi_ccz_1"
7743 [(set (reg:CCZ FLAGS_REG)
7744 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
7745 (match_operand:QI 1 "nonmemory_operand" ""))
7750 (define_insn "*testqi_1_maybe_si"
7751 [(set (reg FLAGS_REG)
7754 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
7755 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
7757 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
7758 && ix86_match_ccmode (insn,
7759 GET_CODE (operands[1]) == CONST_INT
7760 && INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)"
7762 if (which_alternative == 3)
7764 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0)
7765 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
7766 return "test{l}\t{%1, %k0|%k0, %1}";
7768 return "test{b}\t{%1, %0|%0, %1}";
7770 [(set_attr "type" "test")
7771 (set_attr "modrm" "0,1,1,1")
7772 (set_attr "mode" "QI,QI,QI,SI")
7773 (set_attr "pent_pair" "uv,np,uv,np")])
7775 (define_insn "*testqi_1"
7776 [(set (reg FLAGS_REG)
7779 (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm")
7780 (match_operand:QI 1 "general_operand" "n,n,qn"))
7782 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
7783 && ix86_match_ccmode (insn, CCNOmode)"
7784 "test{b}\t{%1, %0|%0, %1}"
7785 [(set_attr "type" "test")
7786 (set_attr "modrm" "0,1,1")
7787 (set_attr "mode" "QI")
7788 (set_attr "pent_pair" "uv,np,uv")])
7790 (define_expand "testqi_ext_ccno_0"
7791 [(set (reg:CCNO FLAGS_REG)
7795 (match_operand 0 "ext_register_operand" "")
7798 (match_operand 1 "const_int_operand" ""))
7803 (define_insn "*testqi_ext_0"
7804 [(set (reg FLAGS_REG)
7808 (match_operand 0 "ext_register_operand" "Q")
7811 (match_operand 1 "const_int_operand" "n"))
7813 "ix86_match_ccmode (insn, CCNOmode)"
7814 "test{b}\t{%1, %h0|%h0, %1}"
7815 [(set_attr "type" "test")
7816 (set_attr "mode" "QI")
7817 (set_attr "length_immediate" "1")
7818 (set_attr "pent_pair" "np")])
7820 (define_insn "*testqi_ext_1"
7821 [(set (reg FLAGS_REG)
7825 (match_operand 0 "ext_register_operand" "Q")
7829 (match_operand:QI 1 "general_operand" "Qm")))
7831 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
7832 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7833 "test{b}\t{%1, %h0|%h0, %1}"
7834 [(set_attr "type" "test")
7835 (set_attr "mode" "QI")])
7837 (define_insn "*testqi_ext_1_rex64"
7838 [(set (reg FLAGS_REG)
7842 (match_operand 0 "ext_register_operand" "Q")
7846 (match_operand:QI 1 "register_operand" "Q")))
7848 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
7849 "test{b}\t{%1, %h0|%h0, %1}"
7850 [(set_attr "type" "test")
7851 (set_attr "mode" "QI")])
7853 (define_insn "*testqi_ext_2"
7854 [(set (reg FLAGS_REG)
7858 (match_operand 0 "ext_register_operand" "Q")
7862 (match_operand 1 "ext_register_operand" "Q")
7866 "ix86_match_ccmode (insn, CCNOmode)"
7867 "test{b}\t{%h1, %h0|%h0, %h1}"
7868 [(set_attr "type" "test")
7869 (set_attr "mode" "QI")])
7871 ;; Combine likes to form bit extractions for some tests. Humor it.
7872 (define_insn "*testqi_ext_3"
7873 [(set (reg FLAGS_REG)
7874 (compare (zero_extract:SI
7875 (match_operand 0 "nonimmediate_operand" "rm")
7876 (match_operand:SI 1 "const_int_operand" "")
7877 (match_operand:SI 2 "const_int_operand" ""))
7879 "ix86_match_ccmode (insn, CCNOmode)
7880 && (GET_MODE (operands[0]) == SImode
7881 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
7882 || GET_MODE (operands[0]) == HImode
7883 || GET_MODE (operands[0]) == QImode)"
7886 (define_insn "*testqi_ext_3_rex64"
7887 [(set (reg FLAGS_REG)
7888 (compare (zero_extract:DI
7889 (match_operand 0 "nonimmediate_operand" "rm")
7890 (match_operand:DI 1 "const_int_operand" "")
7891 (match_operand:DI 2 "const_int_operand" ""))
7894 && ix86_match_ccmode (insn, CCNOmode)
7895 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
7896 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
7897 /* Ensure that resulting mask is zero or sign extended operand. */
7898 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
7899 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
7900 && INTVAL (operands[1]) > 32))
7901 && (GET_MODE (operands[0]) == SImode
7902 || GET_MODE (operands[0]) == DImode
7903 || GET_MODE (operands[0]) == HImode
7904 || GET_MODE (operands[0]) == QImode)"
7908 [(set (match_operand 0 "flags_reg_operand" "")
7909 (match_operator 1 "compare_operator"
7911 (match_operand 2 "nonimmediate_operand" "")
7912 (match_operand 3 "const_int_operand" "")
7913 (match_operand 4 "const_int_operand" ""))
7915 "ix86_match_ccmode (insn, CCNOmode)"
7916 [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
7918 rtx val = operands[2];
7919 HOST_WIDE_INT len = INTVAL (operands[3]);
7920 HOST_WIDE_INT pos = INTVAL (operands[4]);
7922 enum machine_mode mode, submode;
7924 mode = GET_MODE (val);
7925 if (GET_CODE (val) == MEM)
7927 /* ??? Combine likes to put non-volatile mem extractions in QImode
7928 no matter the size of the test. So find a mode that works. */
7929 if (! MEM_VOLATILE_P (val))
7931 mode = smallest_mode_for_size (pos + len, MODE_INT);
7932 val = adjust_address (val, mode, 0);
7935 else if (GET_CODE (val) == SUBREG
7936 && (submode = GET_MODE (SUBREG_REG (val)),
7937 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
7938 && pos + len <= GET_MODE_BITSIZE (submode))
7940 /* Narrow a paradoxical subreg to prevent partial register stalls. */
7942 val = SUBREG_REG (val);
7944 else if (mode == HImode && pos + len <= 8)
7946 /* Small HImode tests can be converted to QImode. */
7948 val = gen_lowpart (QImode, val);
7951 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
7952 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
7954 operands[2] = gen_rtx_AND (mode, val, gen_int_mode (mask, mode));
7957 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
7958 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
7959 ;; this is relatively important trick.
7960 ;; Do the conversion only post-reload to avoid limiting of the register class
7963 [(set (match_operand 0 "flags_reg_operand" "")
7964 (match_operator 1 "compare_operator"
7965 [(and (match_operand 2 "register_operand" "")
7966 (match_operand 3 "const_int_operand" ""))
7969 && QI_REG_P (operands[2])
7970 && GET_MODE (operands[2]) != QImode
7971 && ((ix86_match_ccmode (insn, CCZmode)
7972 && !(INTVAL (operands[3]) & ~(255 << 8)))
7973 || (ix86_match_ccmode (insn, CCNOmode)
7974 && !(INTVAL (operands[3]) & ~(127 << 8))))"
7977 [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8))
7980 "operands[2] = gen_lowpart (SImode, operands[2]);
7981 operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);")
7984 [(set (match_operand 0 "flags_reg_operand" "")
7985 (match_operator 1 "compare_operator"
7986 [(and (match_operand 2 "nonimmediate_operand" "")
7987 (match_operand 3 "const_int_operand" ""))
7990 && GET_MODE (operands[2]) != QImode
7991 && (!REG_P (operands[2]) || ANY_QI_REG_P (operands[2]))
7992 && ((ix86_match_ccmode (insn, CCZmode)
7993 && !(INTVAL (operands[3]) & ~255))
7994 || (ix86_match_ccmode (insn, CCNOmode)
7995 && !(INTVAL (operands[3]) & ~127)))"
7997 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
7999 "operands[2] = gen_lowpart (QImode, operands[2]);
8000 operands[3] = gen_lowpart (QImode, operands[3]);")
8003 ;; %%% This used to optimize known byte-wide and operations to memory,
8004 ;; and sometimes to QImode registers. If this is considered useful,
8005 ;; it should be done with splitters.
8007 (define_expand "anddi3"
8008 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8009 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8010 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8011 (clobber (reg:CC FLAGS_REG))]
8013 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8015 (define_insn "*anddi_1_rex64"
8016 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8017 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8018 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8019 (clobber (reg:CC FLAGS_REG))]
8020 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8022 switch (get_attr_type (insn))
8026 enum machine_mode mode;
8028 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
8029 if (INTVAL (operands[2]) == 0xff)
8033 gcc_assert (INTVAL (operands[2]) == 0xffff);
8037 operands[1] = gen_lowpart (mode, operands[1]);
8039 return "movz{bq|x}\t{%1,%0|%0, %1}";
8041 return "movz{wq|x}\t{%1,%0|%0, %1}";
8045 gcc_assert (rtx_equal_p (operands[0], operands[1]));
8046 if (get_attr_mode (insn) == MODE_SI)
8047 return "and{l}\t{%k2, %k0|%k0, %k2}";
8049 return "and{q}\t{%2, %0|%0, %2}";
8052 [(set_attr "type" "alu,alu,alu,imovx")
8053 (set_attr "length_immediate" "*,*,*,0")
8054 (set_attr "mode" "SI,DI,DI,DI")])
8056 (define_insn "*anddi_2"
8057 [(set (reg FLAGS_REG)
8058 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8059 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8061 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8062 (and:DI (match_dup 1) (match_dup 2)))]
8063 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8064 && ix86_binary_operator_ok (AND, DImode, operands)"
8066 and{l}\t{%k2, %k0|%k0, %k2}
8067 and{q}\t{%2, %0|%0, %2}
8068 and{q}\t{%2, %0|%0, %2}"
8069 [(set_attr "type" "alu")
8070 (set_attr "mode" "SI,DI,DI")])
8072 (define_expand "andsi3"
8073 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8074 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8075 (match_operand:SI 2 "general_operand" "")))
8076 (clobber (reg:CC FLAGS_REG))]
8078 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8080 (define_insn "*andsi_1"
8081 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8082 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8083 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8084 (clobber (reg:CC FLAGS_REG))]
8085 "ix86_binary_operator_ok (AND, SImode, operands)"
8087 switch (get_attr_type (insn))
8091 enum machine_mode mode;
8093 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
8094 if (INTVAL (operands[2]) == 0xff)
8098 gcc_assert (INTVAL (operands[2]) == 0xffff);
8102 operands[1] = gen_lowpart (mode, operands[1]);
8104 return "movz{bl|x}\t{%1,%0|%0, %1}";
8106 return "movz{wl|x}\t{%1,%0|%0, %1}";
8110 gcc_assert (rtx_equal_p (operands[0], operands[1]));
8111 return "and{l}\t{%2, %0|%0, %2}";
8114 [(set_attr "type" "alu,alu,imovx")
8115 (set_attr "length_immediate" "*,*,0")
8116 (set_attr "mode" "SI")])
8119 [(set (match_operand 0 "register_operand" "")
8121 (const_int -65536)))
8122 (clobber (reg:CC FLAGS_REG))]
8123 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8124 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8125 "operands[1] = gen_lowpart (HImode, operands[0]);")
8128 [(set (match_operand 0 "ext_register_operand" "")
8131 (clobber (reg:CC FLAGS_REG))]
8132 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8133 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8134 "operands[1] = gen_lowpart (QImode, operands[0]);")
8137 [(set (match_operand 0 "ext_register_operand" "")
8139 (const_int -65281)))
8140 (clobber (reg:CC FLAGS_REG))]
8141 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8142 [(parallel [(set (zero_extract:SI (match_dup 0)
8146 (zero_extract:SI (match_dup 0)
8149 (zero_extract:SI (match_dup 0)
8152 (clobber (reg:CC FLAGS_REG))])]
8153 "operands[0] = gen_lowpart (SImode, operands[0]);")
8155 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8156 (define_insn "*andsi_1_zext"
8157 [(set (match_operand:DI 0 "register_operand" "=r")
8159 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8160 (match_operand:SI 2 "general_operand" "rim"))))
8161 (clobber (reg:CC FLAGS_REG))]
8162 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8163 "and{l}\t{%2, %k0|%k0, %2}"
8164 [(set_attr "type" "alu")
8165 (set_attr "mode" "SI")])
8167 (define_insn "*andsi_2"
8168 [(set (reg FLAGS_REG)
8169 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8170 (match_operand:SI 2 "general_operand" "rim,ri"))
8172 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8173 (and:SI (match_dup 1) (match_dup 2)))]
8174 "ix86_match_ccmode (insn, CCNOmode)
8175 && ix86_binary_operator_ok (AND, SImode, operands)"
8176 "and{l}\t{%2, %0|%0, %2}"
8177 [(set_attr "type" "alu")
8178 (set_attr "mode" "SI")])
8180 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8181 (define_insn "*andsi_2_zext"
8182 [(set (reg FLAGS_REG)
8183 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8184 (match_operand:SI 2 "general_operand" "rim"))
8186 (set (match_operand:DI 0 "register_operand" "=r")
8187 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8188 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8189 && ix86_binary_operator_ok (AND, SImode, operands)"
8190 "and{l}\t{%2, %k0|%k0, %2}"
8191 [(set_attr "type" "alu")
8192 (set_attr "mode" "SI")])
8194 (define_expand "andhi3"
8195 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8196 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8197 (match_operand:HI 2 "general_operand" "")))
8198 (clobber (reg:CC FLAGS_REG))]
8199 "TARGET_HIMODE_MATH"
8200 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8202 (define_insn "*andhi_1"
8203 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8204 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8205 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8206 (clobber (reg:CC FLAGS_REG))]
8207 "ix86_binary_operator_ok (AND, HImode, operands)"
8209 switch (get_attr_type (insn))
8212 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
8213 gcc_assert (INTVAL (operands[2]) == 0xff);
8214 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8217 gcc_assert (rtx_equal_p (operands[0], operands[1]));
8219 return "and{w}\t{%2, %0|%0, %2}";
8222 [(set_attr "type" "alu,alu,imovx")
8223 (set_attr "length_immediate" "*,*,0")
8224 (set_attr "mode" "HI,HI,SI")])
8226 (define_insn "*andhi_2"
8227 [(set (reg FLAGS_REG)
8228 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8229 (match_operand:HI 2 "general_operand" "rim,ri"))
8231 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8232 (and:HI (match_dup 1) (match_dup 2)))]
8233 "ix86_match_ccmode (insn, CCNOmode)
8234 && ix86_binary_operator_ok (AND, HImode, operands)"
8235 "and{w}\t{%2, %0|%0, %2}"
8236 [(set_attr "type" "alu")
8237 (set_attr "mode" "HI")])
8239 (define_expand "andqi3"
8240 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8241 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8242 (match_operand:QI 2 "general_operand" "")))
8243 (clobber (reg:CC FLAGS_REG))]
8244 "TARGET_QIMODE_MATH"
8245 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8247 ;; %%% Potential partial reg stall on alternative 2. What to do?
8248 (define_insn "*andqi_1"
8249 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8250 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8251 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8252 (clobber (reg:CC FLAGS_REG))]
8253 "ix86_binary_operator_ok (AND, QImode, operands)"
8255 and{b}\t{%2, %0|%0, %2}
8256 and{b}\t{%2, %0|%0, %2}
8257 and{l}\t{%k2, %k0|%k0, %k2}"
8258 [(set_attr "type" "alu")
8259 (set_attr "mode" "QI,QI,SI")])
8261 (define_insn "*andqi_1_slp"
8262 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8263 (and:QI (match_dup 0)
8264 (match_operand:QI 1 "general_operand" "qi,qmi")))
8265 (clobber (reg:CC FLAGS_REG))]
8266 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8267 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8268 "and{b}\t{%1, %0|%0, %1}"
8269 [(set_attr "type" "alu1")
8270 (set_attr "mode" "QI")])
8272 (define_insn "*andqi_2_maybe_si"
8273 [(set (reg FLAGS_REG)
8275 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8276 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8278 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8279 (and:QI (match_dup 1) (match_dup 2)))]
8280 "ix86_binary_operator_ok (AND, QImode, operands)
8281 && ix86_match_ccmode (insn,
8282 GET_CODE (operands[2]) == CONST_INT
8283 && INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)"
8285 if (which_alternative == 2)
8287 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
8288 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8289 return "and{l}\t{%2, %k0|%k0, %2}";
8291 return "and{b}\t{%2, %0|%0, %2}";
8293 [(set_attr "type" "alu")
8294 (set_attr "mode" "QI,QI,SI")])
8296 (define_insn "*andqi_2"
8297 [(set (reg FLAGS_REG)
8299 (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8300 (match_operand:QI 2 "general_operand" "qim,qi"))
8302 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8303 (and:QI (match_dup 1) (match_dup 2)))]
8304 "ix86_match_ccmode (insn, CCNOmode)
8305 && ix86_binary_operator_ok (AND, QImode, operands)"
8306 "and{b}\t{%2, %0|%0, %2}"
8307 [(set_attr "type" "alu")
8308 (set_attr "mode" "QI")])
8310 (define_insn "*andqi_2_slp"
8311 [(set (reg FLAGS_REG)
8313 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8314 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8316 (set (strict_low_part (match_dup 0))
8317 (and:QI (match_dup 0) (match_dup 1)))]
8318 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8319 && ix86_match_ccmode (insn, CCNOmode)
8320 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8321 "and{b}\t{%1, %0|%0, %1}"
8322 [(set_attr "type" "alu1")
8323 (set_attr "mode" "QI")])
8325 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8326 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8327 ;; for a QImode operand, which of course failed.
8329 (define_insn "andqi_ext_0"
8330 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8335 (match_operand 1 "ext_register_operand" "0")
8338 (match_operand 2 "const_int_operand" "n")))
8339 (clobber (reg:CC FLAGS_REG))]
8341 "and{b}\t{%2, %h0|%h0, %2}"
8342 [(set_attr "type" "alu")
8343 (set_attr "length_immediate" "1")
8344 (set_attr "mode" "QI")])
8346 ;; Generated by peephole translating test to and. This shows up
8347 ;; often in fp comparisons.
8349 (define_insn "*andqi_ext_0_cc"
8350 [(set (reg FLAGS_REG)
8354 (match_operand 1 "ext_register_operand" "0")
8357 (match_operand 2 "const_int_operand" "n"))
8359 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8368 "ix86_match_ccmode (insn, CCNOmode)"
8369 "and{b}\t{%2, %h0|%h0, %2}"
8370 [(set_attr "type" "alu")
8371 (set_attr "length_immediate" "1")
8372 (set_attr "mode" "QI")])
8374 (define_insn "*andqi_ext_1"
8375 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8380 (match_operand 1 "ext_register_operand" "0")
8384 (match_operand:QI 2 "general_operand" "Qm"))))
8385 (clobber (reg:CC FLAGS_REG))]
8387 "and{b}\t{%2, %h0|%h0, %2}"
8388 [(set_attr "type" "alu")
8389 (set_attr "length_immediate" "0")
8390 (set_attr "mode" "QI")])
8392 (define_insn "*andqi_ext_1_rex64"
8393 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8398 (match_operand 1 "ext_register_operand" "0")
8402 (match_operand 2 "ext_register_operand" "Q"))))
8403 (clobber (reg:CC FLAGS_REG))]
8405 "and{b}\t{%2, %h0|%h0, %2}"
8406 [(set_attr "type" "alu")
8407 (set_attr "length_immediate" "0")
8408 (set_attr "mode" "QI")])
8410 (define_insn "*andqi_ext_2"
8411 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8416 (match_operand 1 "ext_register_operand" "%0")
8420 (match_operand 2 "ext_register_operand" "Q")
8423 (clobber (reg:CC FLAGS_REG))]
8425 "and{b}\t{%h2, %h0|%h0, %h2}"
8426 [(set_attr "type" "alu")
8427 (set_attr "length_immediate" "0")
8428 (set_attr "mode" "QI")])
8430 ;; Convert wide AND instructions with immediate operand to shorter QImode
8431 ;; equivalents when possible.
8432 ;; Don't do the splitting with memory operands, since it introduces risk
8433 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8434 ;; for size, but that can (should?) be handled by generic code instead.
8436 [(set (match_operand 0 "register_operand" "")
8437 (and (match_operand 1 "register_operand" "")
8438 (match_operand 2 "const_int_operand" "")))
8439 (clobber (reg:CC FLAGS_REG))]
8441 && QI_REG_P (operands[0])
8442 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8443 && !(~INTVAL (operands[2]) & ~(255 << 8))
8444 && GET_MODE (operands[0]) != QImode"
8445 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8446 (and:SI (zero_extract:SI (match_dup 1)
8447 (const_int 8) (const_int 8))
8449 (clobber (reg:CC FLAGS_REG))])]
8450 "operands[0] = gen_lowpart (SImode, operands[0]);
8451 operands[1] = gen_lowpart (SImode, operands[1]);
8452 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8454 ;; Since AND can be encoded with sign extended immediate, this is only
8455 ;; profitable when 7th bit is not set.
8457 [(set (match_operand 0 "register_operand" "")
8458 (and (match_operand 1 "general_operand" "")
8459 (match_operand 2 "const_int_operand" "")))
8460 (clobber (reg:CC FLAGS_REG))]
8462 && ANY_QI_REG_P (operands[0])
8463 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8464 && !(~INTVAL (operands[2]) & ~255)
8465 && !(INTVAL (operands[2]) & 128)
8466 && GET_MODE (operands[0]) != QImode"
8467 [(parallel [(set (strict_low_part (match_dup 0))
8468 (and:QI (match_dup 1)
8470 (clobber (reg:CC FLAGS_REG))])]
8471 "operands[0] = gen_lowpart (QImode, operands[0]);
8472 operands[1] = gen_lowpart (QImode, operands[1]);
8473 operands[2] = gen_lowpart (QImode, operands[2]);")
8475 ;; Logical inclusive OR instructions
8477 ;; %%% This used to optimize known byte-wide and operations to memory.
8478 ;; If this is considered useful, it should be done with splitters.
8480 (define_expand "iordi3"
8481 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8482 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8483 (match_operand:DI 2 "x86_64_general_operand" "")))
8484 (clobber (reg:CC FLAGS_REG))]
8486 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8488 (define_insn "*iordi_1_rex64"
8489 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8490 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8491 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8492 (clobber (reg:CC FLAGS_REG))]
8494 && ix86_binary_operator_ok (IOR, DImode, operands)"
8495 "or{q}\t{%2, %0|%0, %2}"
8496 [(set_attr "type" "alu")
8497 (set_attr "mode" "DI")])
8499 (define_insn "*iordi_2_rex64"
8500 [(set (reg FLAGS_REG)
8501 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8502 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8504 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8505 (ior:DI (match_dup 1) (match_dup 2)))]
8507 && ix86_match_ccmode (insn, CCNOmode)
8508 && ix86_binary_operator_ok (IOR, DImode, operands)"
8509 "or{q}\t{%2, %0|%0, %2}"
8510 [(set_attr "type" "alu")
8511 (set_attr "mode" "DI")])
8513 (define_insn "*iordi_3_rex64"
8514 [(set (reg FLAGS_REG)
8515 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8516 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8518 (clobber (match_scratch:DI 0 "=r"))]
8520 && ix86_match_ccmode (insn, CCNOmode)
8521 && ix86_binary_operator_ok (IOR, DImode, operands)"
8522 "or{q}\t{%2, %0|%0, %2}"
8523 [(set_attr "type" "alu")
8524 (set_attr "mode" "DI")])
8527 (define_expand "iorsi3"
8528 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8529 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8530 (match_operand:SI 2 "general_operand" "")))
8531 (clobber (reg:CC FLAGS_REG))]
8533 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8535 (define_insn "*iorsi_1"
8536 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8537 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8538 (match_operand:SI 2 "general_operand" "ri,rmi")))
8539 (clobber (reg:CC FLAGS_REG))]
8540 "ix86_binary_operator_ok (IOR, SImode, operands)"
8541 "or{l}\t{%2, %0|%0, %2}"
8542 [(set_attr "type" "alu")
8543 (set_attr "mode" "SI")])
8545 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8546 (define_insn "*iorsi_1_zext"
8547 [(set (match_operand:DI 0 "register_operand" "=rm")
8549 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8550 (match_operand:SI 2 "general_operand" "rim"))))
8551 (clobber (reg:CC FLAGS_REG))]
8552 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8553 "or{l}\t{%2, %k0|%k0, %2}"
8554 [(set_attr "type" "alu")
8555 (set_attr "mode" "SI")])
8557 (define_insn "*iorsi_1_zext_imm"
8558 [(set (match_operand:DI 0 "register_operand" "=rm")
8559 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8560 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8561 (clobber (reg:CC FLAGS_REG))]
8563 "or{l}\t{%2, %k0|%k0, %2}"
8564 [(set_attr "type" "alu")
8565 (set_attr "mode" "SI")])
8567 (define_insn "*iorsi_2"
8568 [(set (reg FLAGS_REG)
8569 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8570 (match_operand:SI 2 "general_operand" "rim,ri"))
8572 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8573 (ior:SI (match_dup 1) (match_dup 2)))]
8574 "ix86_match_ccmode (insn, CCNOmode)
8575 && ix86_binary_operator_ok (IOR, SImode, operands)"
8576 "or{l}\t{%2, %0|%0, %2}"
8577 [(set_attr "type" "alu")
8578 (set_attr "mode" "SI")])
8580 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8581 ;; ??? Special case for immediate operand is missing - it is tricky.
8582 (define_insn "*iorsi_2_zext"
8583 [(set (reg FLAGS_REG)
8584 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8585 (match_operand:SI 2 "general_operand" "rim"))
8587 (set (match_operand:DI 0 "register_operand" "=r")
8588 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8589 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8590 && ix86_binary_operator_ok (IOR, SImode, operands)"
8591 "or{l}\t{%2, %k0|%k0, %2}"
8592 [(set_attr "type" "alu")
8593 (set_attr "mode" "SI")])
8595 (define_insn "*iorsi_2_zext_imm"
8596 [(set (reg FLAGS_REG)
8597 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8598 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8600 (set (match_operand:DI 0 "register_operand" "=r")
8601 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8602 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8603 && ix86_binary_operator_ok (IOR, SImode, operands)"
8604 "or{l}\t{%2, %k0|%k0, %2}"
8605 [(set_attr "type" "alu")
8606 (set_attr "mode" "SI")])
8608 (define_insn "*iorsi_3"
8609 [(set (reg FLAGS_REG)
8610 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8611 (match_operand:SI 2 "general_operand" "rim"))
8613 (clobber (match_scratch:SI 0 "=r"))]
8614 "ix86_match_ccmode (insn, CCNOmode)
8615 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8616 "or{l}\t{%2, %0|%0, %2}"
8617 [(set_attr "type" "alu")
8618 (set_attr "mode" "SI")])
8620 (define_expand "iorhi3"
8621 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8622 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
8623 (match_operand:HI 2 "general_operand" "")))
8624 (clobber (reg:CC FLAGS_REG))]
8625 "TARGET_HIMODE_MATH"
8626 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
8628 (define_insn "*iorhi_1"
8629 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
8630 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8631 (match_operand:HI 2 "general_operand" "rmi,ri")))
8632 (clobber (reg:CC FLAGS_REG))]
8633 "ix86_binary_operator_ok (IOR, HImode, operands)"
8634 "or{w}\t{%2, %0|%0, %2}"
8635 [(set_attr "type" "alu")
8636 (set_attr "mode" "HI")])
8638 (define_insn "*iorhi_2"
8639 [(set (reg FLAGS_REG)
8640 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8641 (match_operand:HI 2 "general_operand" "rim,ri"))
8643 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8644 (ior:HI (match_dup 1) (match_dup 2)))]
8645 "ix86_match_ccmode (insn, CCNOmode)
8646 && ix86_binary_operator_ok (IOR, HImode, operands)"
8647 "or{w}\t{%2, %0|%0, %2}"
8648 [(set_attr "type" "alu")
8649 (set_attr "mode" "HI")])
8651 (define_insn "*iorhi_3"
8652 [(set (reg FLAGS_REG)
8653 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
8654 (match_operand:HI 2 "general_operand" "rim"))
8656 (clobber (match_scratch:HI 0 "=r"))]
8657 "ix86_match_ccmode (insn, CCNOmode)
8658 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8659 "or{w}\t{%2, %0|%0, %2}"
8660 [(set_attr "type" "alu")
8661 (set_attr "mode" "HI")])
8663 (define_expand "iorqi3"
8664 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8665 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
8666 (match_operand:QI 2 "general_operand" "")))
8667 (clobber (reg:CC FLAGS_REG))]
8668 "TARGET_QIMODE_MATH"
8669 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
8671 ;; %%% Potential partial reg stall on alternative 2. What to do?
8672 (define_insn "*iorqi_1"
8673 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
8674 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8675 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
8676 (clobber (reg:CC FLAGS_REG))]
8677 "ix86_binary_operator_ok (IOR, QImode, operands)"
8679 or{b}\t{%2, %0|%0, %2}
8680 or{b}\t{%2, %0|%0, %2}
8681 or{l}\t{%k2, %k0|%k0, %k2}"
8682 [(set_attr "type" "alu")
8683 (set_attr "mode" "QI,QI,SI")])
8685 (define_insn "*iorqi_1_slp"
8686 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
8687 (ior:QI (match_dup 0)
8688 (match_operand:QI 1 "general_operand" "qmi,qi")))
8689 (clobber (reg:CC FLAGS_REG))]
8690 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8691 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8692 "or{b}\t{%1, %0|%0, %1}"
8693 [(set_attr "type" "alu1")
8694 (set_attr "mode" "QI")])
8696 (define_insn "*iorqi_2"
8697 [(set (reg FLAGS_REG)
8698 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
8699 (match_operand:QI 2 "general_operand" "qim,qi"))
8701 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
8702 (ior:QI (match_dup 1) (match_dup 2)))]
8703 "ix86_match_ccmode (insn, CCNOmode)
8704 && ix86_binary_operator_ok (IOR, QImode, operands)"
8705 "or{b}\t{%2, %0|%0, %2}"
8706 [(set_attr "type" "alu")
8707 (set_attr "mode" "QI")])
8709 (define_insn "*iorqi_2_slp"
8710 [(set (reg FLAGS_REG)
8711 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8712 (match_operand:QI 1 "general_operand" "qim,qi"))
8714 (set (strict_low_part (match_dup 0))
8715 (ior:QI (match_dup 0) (match_dup 1)))]
8716 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8717 && ix86_match_ccmode (insn, CCNOmode)
8718 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8719 "or{b}\t{%1, %0|%0, %1}"
8720 [(set_attr "type" "alu1")
8721 (set_attr "mode" "QI")])
8723 (define_insn "*iorqi_3"
8724 [(set (reg FLAGS_REG)
8725 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
8726 (match_operand:QI 2 "general_operand" "qim"))
8728 (clobber (match_scratch:QI 0 "=q"))]
8729 "ix86_match_ccmode (insn, CCNOmode)
8730 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8731 "or{b}\t{%2, %0|%0, %2}"
8732 [(set_attr "type" "alu")
8733 (set_attr "mode" "QI")])
8735 (define_insn "iorqi_ext_0"
8736 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8741 (match_operand 1 "ext_register_operand" "0")
8744 (match_operand 2 "const_int_operand" "n")))
8745 (clobber (reg:CC FLAGS_REG))]
8746 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8747 "or{b}\t{%2, %h0|%h0, %2}"
8748 [(set_attr "type" "alu")
8749 (set_attr "length_immediate" "1")
8750 (set_attr "mode" "QI")])
8752 (define_insn "*iorqi_ext_1"
8753 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8758 (match_operand 1 "ext_register_operand" "0")
8762 (match_operand:QI 2 "general_operand" "Qm"))))
8763 (clobber (reg:CC FLAGS_REG))]
8765 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8766 "or{b}\t{%2, %h0|%h0, %2}"
8767 [(set_attr "type" "alu")
8768 (set_attr "length_immediate" "0")
8769 (set_attr "mode" "QI")])
8771 (define_insn "*iorqi_ext_1_rex64"
8772 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8777 (match_operand 1 "ext_register_operand" "0")
8781 (match_operand 2 "ext_register_operand" "Q"))))
8782 (clobber (reg:CC FLAGS_REG))]
8784 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
8785 "or{b}\t{%2, %h0|%h0, %2}"
8786 [(set_attr "type" "alu")
8787 (set_attr "length_immediate" "0")
8788 (set_attr "mode" "QI")])
8790 (define_insn "*iorqi_ext_2"
8791 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8795 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
8798 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
8801 (clobber (reg:CC FLAGS_REG))]
8802 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
8803 "ior{b}\t{%h2, %h0|%h0, %h2}"
8804 [(set_attr "type" "alu")
8805 (set_attr "length_immediate" "0")
8806 (set_attr "mode" "QI")])
8809 [(set (match_operand 0 "register_operand" "")
8810 (ior (match_operand 1 "register_operand" "")
8811 (match_operand 2 "const_int_operand" "")))
8812 (clobber (reg:CC FLAGS_REG))]
8814 && QI_REG_P (operands[0])
8815 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8816 && !(INTVAL (operands[2]) & ~(255 << 8))
8817 && GET_MODE (operands[0]) != QImode"
8818 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8819 (ior:SI (zero_extract:SI (match_dup 1)
8820 (const_int 8) (const_int 8))
8822 (clobber (reg:CC FLAGS_REG))])]
8823 "operands[0] = gen_lowpart (SImode, operands[0]);
8824 operands[1] = gen_lowpart (SImode, operands[1]);
8825 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8827 ;; Since OR can be encoded with sign extended immediate, this is only
8828 ;; profitable when 7th bit is set.
8830 [(set (match_operand 0 "register_operand" "")
8831 (ior (match_operand 1 "general_operand" "")
8832 (match_operand 2 "const_int_operand" "")))
8833 (clobber (reg:CC FLAGS_REG))]
8835 && ANY_QI_REG_P (operands[0])
8836 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8837 && !(INTVAL (operands[2]) & ~255)
8838 && (INTVAL (operands[2]) & 128)
8839 && GET_MODE (operands[0]) != QImode"
8840 [(parallel [(set (strict_low_part (match_dup 0))
8841 (ior:QI (match_dup 1)
8843 (clobber (reg:CC FLAGS_REG))])]
8844 "operands[0] = gen_lowpart (QImode, operands[0]);
8845 operands[1] = gen_lowpart (QImode, operands[1]);
8846 operands[2] = gen_lowpart (QImode, operands[2]);")
8848 ;; Logical XOR instructions
8850 ;; %%% This used to optimize known byte-wide and operations to memory.
8851 ;; If this is considered useful, it should be done with splitters.
8853 (define_expand "xordi3"
8854 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8855 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
8856 (match_operand:DI 2 "x86_64_general_operand" "")))
8857 (clobber (reg:CC FLAGS_REG))]
8859 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
8861 (define_insn "*xordi_1_rex64"
8862 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8863 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8864 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
8865 (clobber (reg:CC FLAGS_REG))]
8867 && ix86_binary_operator_ok (XOR, DImode, operands)"
8869 xor{q}\t{%2, %0|%0, %2}
8870 xor{q}\t{%2, %0|%0, %2}"
8871 [(set_attr "type" "alu")
8872 (set_attr "mode" "DI,DI")])
8874 (define_insn "*xordi_2_rex64"
8875 [(set (reg FLAGS_REG)
8876 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8877 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8879 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8880 (xor:DI (match_dup 1) (match_dup 2)))]
8882 && ix86_match_ccmode (insn, CCNOmode)
8883 && ix86_binary_operator_ok (XOR, DImode, operands)"
8885 xor{q}\t{%2, %0|%0, %2}
8886 xor{q}\t{%2, %0|%0, %2}"
8887 [(set_attr "type" "alu")
8888 (set_attr "mode" "DI,DI")])
8890 (define_insn "*xordi_3_rex64"
8891 [(set (reg FLAGS_REG)
8892 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8893 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8895 (clobber (match_scratch:DI 0 "=r"))]
8897 && ix86_match_ccmode (insn, CCNOmode)
8898 && ix86_binary_operator_ok (XOR, DImode, operands)"
8899 "xor{q}\t{%2, %0|%0, %2}"
8900 [(set_attr "type" "alu")
8901 (set_attr "mode" "DI")])
8903 (define_expand "xorsi3"
8904 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8905 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
8906 (match_operand:SI 2 "general_operand" "")))
8907 (clobber (reg:CC FLAGS_REG))]
8909 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
8911 (define_insn "*xorsi_1"
8912 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8913 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8914 (match_operand:SI 2 "general_operand" "ri,rm")))
8915 (clobber (reg:CC FLAGS_REG))]
8916 "ix86_binary_operator_ok (XOR, SImode, operands)"
8917 "xor{l}\t{%2, %0|%0, %2}"
8918 [(set_attr "type" "alu")
8919 (set_attr "mode" "SI")])
8921 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8922 ;; Add speccase for immediates
8923 (define_insn "*xorsi_1_zext"
8924 [(set (match_operand:DI 0 "register_operand" "=r")
8926 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8927 (match_operand:SI 2 "general_operand" "rim"))))
8928 (clobber (reg:CC FLAGS_REG))]
8929 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8930 "xor{l}\t{%2, %k0|%k0, %2}"
8931 [(set_attr "type" "alu")
8932 (set_attr "mode" "SI")])
8934 (define_insn "*xorsi_1_zext_imm"
8935 [(set (match_operand:DI 0 "register_operand" "=r")
8936 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8937 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8938 (clobber (reg:CC FLAGS_REG))]
8939 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
8940 "xor{l}\t{%2, %k0|%k0, %2}"
8941 [(set_attr "type" "alu")
8942 (set_attr "mode" "SI")])
8944 (define_insn "*xorsi_2"
8945 [(set (reg FLAGS_REG)
8946 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8947 (match_operand:SI 2 "general_operand" "rim,ri"))
8949 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8950 (xor:SI (match_dup 1) (match_dup 2)))]
8951 "ix86_match_ccmode (insn, CCNOmode)
8952 && ix86_binary_operator_ok (XOR, SImode, operands)"
8953 "xor{l}\t{%2, %0|%0, %2}"
8954 [(set_attr "type" "alu")
8955 (set_attr "mode" "SI")])
8957 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8958 ;; ??? Special case for immediate operand is missing - it is tricky.
8959 (define_insn "*xorsi_2_zext"
8960 [(set (reg FLAGS_REG)
8961 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8962 (match_operand:SI 2 "general_operand" "rim"))
8964 (set (match_operand:DI 0 "register_operand" "=r")
8965 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
8966 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8967 && ix86_binary_operator_ok (XOR, SImode, operands)"
8968 "xor{l}\t{%2, %k0|%k0, %2}"
8969 [(set_attr "type" "alu")
8970 (set_attr "mode" "SI")])
8972 (define_insn "*xorsi_2_zext_imm"
8973 [(set (reg FLAGS_REG)
8974 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8975 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8977 (set (match_operand:DI 0 "register_operand" "=r")
8978 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8979 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8980 && ix86_binary_operator_ok (XOR, SImode, operands)"
8981 "xor{l}\t{%2, %k0|%k0, %2}"
8982 [(set_attr "type" "alu")
8983 (set_attr "mode" "SI")])
8985 (define_insn "*xorsi_3"
8986 [(set (reg FLAGS_REG)
8987 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8988 (match_operand:SI 2 "general_operand" "rim"))
8990 (clobber (match_scratch:SI 0 "=r"))]
8991 "ix86_match_ccmode (insn, CCNOmode)
8992 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8993 "xor{l}\t{%2, %0|%0, %2}"
8994 [(set_attr "type" "alu")
8995 (set_attr "mode" "SI")])
8997 (define_expand "xorhi3"
8998 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8999 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9000 (match_operand:HI 2 "general_operand" "")))
9001 (clobber (reg:CC FLAGS_REG))]
9002 "TARGET_HIMODE_MATH"
9003 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9005 (define_insn "*xorhi_1"
9006 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9007 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9008 (match_operand:HI 2 "general_operand" "rmi,ri")))
9009 (clobber (reg:CC FLAGS_REG))]
9010 "ix86_binary_operator_ok (XOR, HImode, operands)"
9011 "xor{w}\t{%2, %0|%0, %2}"
9012 [(set_attr "type" "alu")
9013 (set_attr "mode" "HI")])
9015 (define_insn "*xorhi_2"
9016 [(set (reg FLAGS_REG)
9017 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9018 (match_operand:HI 2 "general_operand" "rim,ri"))
9020 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9021 (xor:HI (match_dup 1) (match_dup 2)))]
9022 "ix86_match_ccmode (insn, CCNOmode)
9023 && ix86_binary_operator_ok (XOR, HImode, operands)"
9024 "xor{w}\t{%2, %0|%0, %2}"
9025 [(set_attr "type" "alu")
9026 (set_attr "mode" "HI")])
9028 (define_insn "*xorhi_3"
9029 [(set (reg FLAGS_REG)
9030 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9031 (match_operand:HI 2 "general_operand" "rim"))
9033 (clobber (match_scratch:HI 0 "=r"))]
9034 "ix86_match_ccmode (insn, CCNOmode)
9035 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9036 "xor{w}\t{%2, %0|%0, %2}"
9037 [(set_attr "type" "alu")
9038 (set_attr "mode" "HI")])
9040 (define_expand "xorqi3"
9041 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9042 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9043 (match_operand:QI 2 "general_operand" "")))
9044 (clobber (reg:CC FLAGS_REG))]
9045 "TARGET_QIMODE_MATH"
9046 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9048 ;; %%% Potential partial reg stall on alternative 2. What to do?
9049 (define_insn "*xorqi_1"
9050 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9051 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9052 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9053 (clobber (reg:CC FLAGS_REG))]
9054 "ix86_binary_operator_ok (XOR, QImode, operands)"
9056 xor{b}\t{%2, %0|%0, %2}
9057 xor{b}\t{%2, %0|%0, %2}
9058 xor{l}\t{%k2, %k0|%k0, %k2}"
9059 [(set_attr "type" "alu")
9060 (set_attr "mode" "QI,QI,SI")])
9062 (define_insn "*xorqi_1_slp"
9063 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9064 (xor:QI (match_dup 0)
9065 (match_operand:QI 1 "general_operand" "qi,qmi")))
9066 (clobber (reg:CC FLAGS_REG))]
9067 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9068 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9069 "xor{b}\t{%1, %0|%0, %1}"
9070 [(set_attr "type" "alu1")
9071 (set_attr "mode" "QI")])
9073 (define_insn "xorqi_ext_0"
9074 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9079 (match_operand 1 "ext_register_operand" "0")
9082 (match_operand 2 "const_int_operand" "n")))
9083 (clobber (reg:CC FLAGS_REG))]
9084 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9085 "xor{b}\t{%2, %h0|%h0, %2}"
9086 [(set_attr "type" "alu")
9087 (set_attr "length_immediate" "1")
9088 (set_attr "mode" "QI")])
9090 (define_insn "*xorqi_ext_1"
9091 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9096 (match_operand 1 "ext_register_operand" "0")
9100 (match_operand:QI 2 "general_operand" "Qm"))))
9101 (clobber (reg:CC FLAGS_REG))]
9103 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9104 "xor{b}\t{%2, %h0|%h0, %2}"
9105 [(set_attr "type" "alu")
9106 (set_attr "length_immediate" "0")
9107 (set_attr "mode" "QI")])
9109 (define_insn "*xorqi_ext_1_rex64"
9110 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9115 (match_operand 1 "ext_register_operand" "0")
9119 (match_operand 2 "ext_register_operand" "Q"))))
9120 (clobber (reg:CC FLAGS_REG))]
9122 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9123 "xor{b}\t{%2, %h0|%h0, %2}"
9124 [(set_attr "type" "alu")
9125 (set_attr "length_immediate" "0")
9126 (set_attr "mode" "QI")])
9128 (define_insn "*xorqi_ext_2"
9129 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9133 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9136 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9139 (clobber (reg:CC FLAGS_REG))]
9140 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9141 "xor{b}\t{%h2, %h0|%h0, %h2}"
9142 [(set_attr "type" "alu")
9143 (set_attr "length_immediate" "0")
9144 (set_attr "mode" "QI")])
9146 (define_insn "*xorqi_cc_1"
9147 [(set (reg FLAGS_REG)
9149 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9150 (match_operand:QI 2 "general_operand" "qim,qi"))
9152 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9153 (xor:QI (match_dup 1) (match_dup 2)))]
9154 "ix86_match_ccmode (insn, CCNOmode)
9155 && ix86_binary_operator_ok (XOR, QImode, operands)"
9156 "xor{b}\t{%2, %0|%0, %2}"
9157 [(set_attr "type" "alu")
9158 (set_attr "mode" "QI")])
9160 (define_insn "*xorqi_2_slp"
9161 [(set (reg FLAGS_REG)
9162 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9163 (match_operand:QI 1 "general_operand" "qim,qi"))
9165 (set (strict_low_part (match_dup 0))
9166 (xor:QI (match_dup 0) (match_dup 1)))]
9167 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9168 && ix86_match_ccmode (insn, CCNOmode)
9169 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9170 "xor{b}\t{%1, %0|%0, %1}"
9171 [(set_attr "type" "alu1")
9172 (set_attr "mode" "QI")])
9174 (define_insn "*xorqi_cc_2"
9175 [(set (reg FLAGS_REG)
9177 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9178 (match_operand:QI 2 "general_operand" "qim"))
9180 (clobber (match_scratch:QI 0 "=q"))]
9181 "ix86_match_ccmode (insn, CCNOmode)
9182 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9183 "xor{b}\t{%2, %0|%0, %2}"
9184 [(set_attr "type" "alu")
9185 (set_attr "mode" "QI")])
9187 (define_insn "*xorqi_cc_ext_1"
9188 [(set (reg FLAGS_REG)
9192 (match_operand 1 "ext_register_operand" "0")
9195 (match_operand:QI 2 "general_operand" "qmn"))
9197 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9201 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9203 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9204 "xor{b}\t{%2, %h0|%h0, %2}"
9205 [(set_attr "type" "alu")
9206 (set_attr "mode" "QI")])
9208 (define_insn "*xorqi_cc_ext_1_rex64"
9209 [(set (reg FLAGS_REG)
9213 (match_operand 1 "ext_register_operand" "0")
9216 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9218 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9222 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9224 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9225 "xor{b}\t{%2, %h0|%h0, %2}"
9226 [(set_attr "type" "alu")
9227 (set_attr "mode" "QI")])
9229 (define_expand "xorqi_cc_ext_1"
9231 (set (reg:CCNO FLAGS_REG)
9235 (match_operand 1 "ext_register_operand" "")
9238 (match_operand:QI 2 "general_operand" ""))
9240 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9244 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9250 [(set (match_operand 0 "register_operand" "")
9251 (xor (match_operand 1 "register_operand" "")
9252 (match_operand 2 "const_int_operand" "")))
9253 (clobber (reg:CC FLAGS_REG))]
9255 && QI_REG_P (operands[0])
9256 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9257 && !(INTVAL (operands[2]) & ~(255 << 8))
9258 && GET_MODE (operands[0]) != QImode"
9259 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9260 (xor:SI (zero_extract:SI (match_dup 1)
9261 (const_int 8) (const_int 8))
9263 (clobber (reg:CC FLAGS_REG))])]
9264 "operands[0] = gen_lowpart (SImode, operands[0]);
9265 operands[1] = gen_lowpart (SImode, operands[1]);
9266 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9268 ;; Since XOR can be encoded with sign extended immediate, this is only
9269 ;; profitable when 7th bit is set.
9271 [(set (match_operand 0 "register_operand" "")
9272 (xor (match_operand 1 "general_operand" "")
9273 (match_operand 2 "const_int_operand" "")))
9274 (clobber (reg:CC FLAGS_REG))]
9276 && ANY_QI_REG_P (operands[0])
9277 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9278 && !(INTVAL (operands[2]) & ~255)
9279 && (INTVAL (operands[2]) & 128)
9280 && GET_MODE (operands[0]) != QImode"
9281 [(parallel [(set (strict_low_part (match_dup 0))
9282 (xor:QI (match_dup 1)
9284 (clobber (reg:CC FLAGS_REG))])]
9285 "operands[0] = gen_lowpart (QImode, operands[0]);
9286 operands[1] = gen_lowpart (QImode, operands[1]);
9287 operands[2] = gen_lowpart (QImode, operands[2]);")
9289 ;; Negation instructions
9291 (define_expand "negti2"
9292 [(parallel [(set (match_operand:TI 0 "nonimmediate_operand" "")
9293 (neg:TI (match_operand:TI 1 "nonimmediate_operand" "")))
9294 (clobber (reg:CC FLAGS_REG))])]
9296 "ix86_expand_unary_operator (NEG, TImode, operands); DONE;")
9298 (define_insn "*negti2_1"
9299 [(set (match_operand:TI 0 "nonimmediate_operand" "=ro")
9300 (neg:TI (match_operand:TI 1 "general_operand" "0")))
9301 (clobber (reg:CC FLAGS_REG))]
9303 && ix86_unary_operator_ok (NEG, TImode, operands)"
9307 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9308 (neg:TI (match_operand:TI 1 "general_operand" "")))
9309 (clobber (reg:CC FLAGS_REG))]
9310 "TARGET_64BIT && reload_completed"
9312 [(set (reg:CCZ FLAGS_REG)
9313 (compare:CCZ (neg:DI (match_dup 2)) (const_int 0)))
9314 (set (match_dup 0) (neg:DI (match_dup 2)))])
9317 (plus:DI (plus:DI (ltu:DI (reg:CC FLAGS_REG) (const_int 0))
9320 (clobber (reg:CC FLAGS_REG))])
9323 (neg:DI (match_dup 1)))
9324 (clobber (reg:CC FLAGS_REG))])]
9325 "split_ti (operands+1, 1, operands+2, operands+3);
9326 split_ti (operands+0, 1, operands+0, operands+1);")
9328 (define_expand "negdi2"
9329 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9330 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9331 (clobber (reg:CC FLAGS_REG))])]
9333 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9335 (define_insn "*negdi2_1"
9336 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9337 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9338 (clobber (reg:CC FLAGS_REG))]
9340 && ix86_unary_operator_ok (NEG, DImode, operands)"
9344 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9345 (neg:DI (match_operand:DI 1 "general_operand" "")))
9346 (clobber (reg:CC FLAGS_REG))]
9347 "!TARGET_64BIT && reload_completed"
9349 [(set (reg:CCZ FLAGS_REG)
9350 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9351 (set (match_dup 0) (neg:SI (match_dup 2)))])
9354 (plus:SI (plus:SI (ltu:SI (reg:CC FLAGS_REG) (const_int 0))
9357 (clobber (reg:CC FLAGS_REG))])
9360 (neg:SI (match_dup 1)))
9361 (clobber (reg:CC FLAGS_REG))])]
9362 "split_di (operands+1, 1, operands+2, operands+3);
9363 split_di (operands+0, 1, operands+0, operands+1);")
9365 (define_insn "*negdi2_1_rex64"
9366 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9367 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9368 (clobber (reg:CC FLAGS_REG))]
9369 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9371 [(set_attr "type" "negnot")
9372 (set_attr "mode" "DI")])
9374 ;; The problem with neg is that it does not perform (compare x 0),
9375 ;; it really performs (compare 0 x), which leaves us with the zero
9376 ;; flag being the only useful item.
9378 (define_insn "*negdi2_cmpz_rex64"
9379 [(set (reg:CCZ FLAGS_REG)
9380 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9382 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9383 (neg:DI (match_dup 1)))]
9384 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9386 [(set_attr "type" "negnot")
9387 (set_attr "mode" "DI")])
9390 (define_expand "negsi2"
9391 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9392 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9393 (clobber (reg:CC FLAGS_REG))])]
9395 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9397 (define_insn "*negsi2_1"
9398 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9399 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9400 (clobber (reg:CC FLAGS_REG))]
9401 "ix86_unary_operator_ok (NEG, SImode, operands)"
9403 [(set_attr "type" "negnot")
9404 (set_attr "mode" "SI")])
9406 ;; Combine is quite creative about this pattern.
9407 (define_insn "*negsi2_1_zext"
9408 [(set (match_operand:DI 0 "register_operand" "=r")
9409 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9412 (clobber (reg:CC FLAGS_REG))]
9413 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9415 [(set_attr "type" "negnot")
9416 (set_attr "mode" "SI")])
9418 ;; The problem with neg is that it does not perform (compare x 0),
9419 ;; it really performs (compare 0 x), which leaves us with the zero
9420 ;; flag being the only useful item.
9422 (define_insn "*negsi2_cmpz"
9423 [(set (reg:CCZ FLAGS_REG)
9424 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9426 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9427 (neg:SI (match_dup 1)))]
9428 "ix86_unary_operator_ok (NEG, SImode, operands)"
9430 [(set_attr "type" "negnot")
9431 (set_attr "mode" "SI")])
9433 (define_insn "*negsi2_cmpz_zext"
9434 [(set (reg:CCZ FLAGS_REG)
9435 (compare:CCZ (lshiftrt:DI
9437 (match_operand:DI 1 "register_operand" "0")
9441 (set (match_operand:DI 0 "register_operand" "=r")
9442 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9445 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9447 [(set_attr "type" "negnot")
9448 (set_attr "mode" "SI")])
9450 (define_expand "neghi2"
9451 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9452 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9453 (clobber (reg:CC FLAGS_REG))])]
9454 "TARGET_HIMODE_MATH"
9455 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9457 (define_insn "*neghi2_1"
9458 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9459 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9460 (clobber (reg:CC FLAGS_REG))]
9461 "ix86_unary_operator_ok (NEG, HImode, operands)"
9463 [(set_attr "type" "negnot")
9464 (set_attr "mode" "HI")])
9466 (define_insn "*neghi2_cmpz"
9467 [(set (reg:CCZ FLAGS_REG)
9468 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9470 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9471 (neg:HI (match_dup 1)))]
9472 "ix86_unary_operator_ok (NEG, HImode, operands)"
9474 [(set_attr "type" "negnot")
9475 (set_attr "mode" "HI")])
9477 (define_expand "negqi2"
9478 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9479 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9480 (clobber (reg:CC FLAGS_REG))])]
9481 "TARGET_QIMODE_MATH"
9482 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9484 (define_insn "*negqi2_1"
9485 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9486 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9487 (clobber (reg:CC FLAGS_REG))]
9488 "ix86_unary_operator_ok (NEG, QImode, operands)"
9490 [(set_attr "type" "negnot")
9491 (set_attr "mode" "QI")])
9493 (define_insn "*negqi2_cmpz"
9494 [(set (reg:CCZ FLAGS_REG)
9495 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9497 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9498 (neg:QI (match_dup 1)))]
9499 "ix86_unary_operator_ok (NEG, QImode, operands)"
9501 [(set_attr "type" "negnot")
9502 (set_attr "mode" "QI")])
9504 ;; Changing of sign for FP values is doable using integer unit too.
9506 (define_expand "negsf2"
9507 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9508 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
9509 "TARGET_80387 || TARGET_SSE_MATH"
9510 "ix86_expand_fp_absneg_operator (NEG, SFmode, operands); DONE;")
9512 (define_expand "abssf2"
9513 [(set (match_operand:SF 0 "nonimmediate_operand" "")
9514 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
9515 "TARGET_80387 || TARGET_SSE_MATH"
9516 "ix86_expand_fp_absneg_operator (ABS, SFmode, operands); DONE;")
9518 (define_insn "*absnegsf2_mixed"
9519 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#f,x#f,f#x,rm")
9520 (match_operator:SF 3 "absneg_operator"
9521 [(match_operand:SF 1 "nonimmediate_operand" "0 ,x#f,0 ,0")]))
9522 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm ,0 ,X ,X"))
9523 (clobber (reg:CC FLAGS_REG))]
9524 "TARGET_SSE_MATH && TARGET_MIX_SSE_I387
9525 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9528 (define_insn "*absnegsf2_sse"
9529 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,rm")
9530 (match_operator:SF 3 "absneg_operator"
9531 [(match_operand:SF 1 "nonimmediate_operand" "0 ,x,0")]))
9532 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,X"))
9533 (clobber (reg:CC FLAGS_REG))]
9535 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9538 (define_insn "*absnegsf2_i387"
9539 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,rm")
9540 (match_operator:SF 3 "absneg_operator"
9541 [(match_operand:SF 1 "nonimmediate_operand" "0,0")]))
9542 (use (match_operand 2 "" ""))
9543 (clobber (reg:CC FLAGS_REG))]
9544 "TARGET_80387 && !TARGET_SSE_MATH
9545 && ix86_unary_operator_ok (GET_CODE (operands[3]), SFmode, operands)"
9548 (define_expand "copysignsf3"
9549 [(match_operand:SF 0 "register_operand" "")
9550 (match_operand:SF 1 "nonmemory_operand" "")
9551 (match_operand:SF 2 "register_operand" "")]
9554 ix86_expand_copysign (operands);
9558 (define_insn_and_split "copysignsf3_const"
9559 [(set (match_operand:SF 0 "register_operand" "=x")
9561 [(match_operand:V4SF 1 "vector_move_operand" "xmC")
9562 (match_operand:SF 2 "register_operand" "0")
9563 (match_operand:V4SF 3 "nonimmediate_operand" "xm")]
9567 "&& reload_completed"
9570 ix86_split_copysign_const (operands);
9574 (define_insn "copysignsf3_var"
9575 [(set (match_operand:SF 0 "register_operand" "=x, x, x, x,x")
9577 [(match_operand:SF 2 "register_operand" " x, 0, 0, x,x")
9578 (match_operand:SF 3 "register_operand" " 1, 1, x, 1,x")
9579 (match_operand:V4SF 4 "nonimmediate_operand" " X,xm,xm, 0,0")
9580 (match_operand:V4SF 5 "nonimmediate_operand" " 0,xm, 1,xm,1")]
9582 (clobber (match_scratch:V4SF 1 "=x, x, x, x,x"))]
9587 [(set (match_operand:SF 0 "register_operand" "")
9589 [(match_operand:SF 2 "register_operand" "")
9590 (match_operand:SF 3 "register_operand" "")
9591 (match_operand:V4SF 4 "" "")
9592 (match_operand:V4SF 5 "" "")]
9594 (clobber (match_scratch:V4SF 1 ""))]
9595 "TARGET_SSE_MATH && reload_completed"
9598 ix86_split_copysign_var (operands);
9602 (define_expand "negdf2"
9603 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9604 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
9605 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
9606 "ix86_expand_fp_absneg_operator (NEG, DFmode, operands); DONE;")
9608 (define_expand "absdf2"
9609 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9610 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
9611 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
9612 "ix86_expand_fp_absneg_operator (ABS, DFmode, operands); DONE;")
9614 (define_insn "*absnegdf2_mixed"
9615 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,f#Y,rm")
9616 (match_operator:DF 3 "absneg_operator"
9617 [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y#f,0 ,0")]))
9618 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym ,0 ,X ,X"))
9619 (clobber (reg:CC FLAGS_REG))]
9620 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
9621 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9624 (define_insn "*absnegdf2_sse"
9625 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,Y,rm")
9626 (match_operator:DF 3 "absneg_operator"
9627 [(match_operand:DF 1 "nonimmediate_operand" "0 ,Y,0")]))
9628 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,X"))
9629 (clobber (reg:CC FLAGS_REG))]
9630 "TARGET_SSE2 && TARGET_SSE_MATH
9631 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9634 (define_insn "*absnegdf2_i387"
9635 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,rm")
9636 (match_operator:DF 3 "absneg_operator"
9637 [(match_operand:DF 1 "nonimmediate_operand" "0,0")]))
9638 (use (match_operand 2 "" ""))
9639 (clobber (reg:CC FLAGS_REG))]
9640 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
9641 && ix86_unary_operator_ok (GET_CODE (operands[3]), DFmode, operands)"
9644 (define_expand "copysigndf3"
9645 [(match_operand:DF 0 "register_operand" "")
9646 (match_operand:DF 1 "nonmemory_operand" "")
9647 (match_operand:DF 2 "register_operand" "")]
9648 "TARGET_SSE2 && TARGET_SSE_MATH"
9650 ix86_expand_copysign (operands);
9654 (define_insn_and_split "copysigndf3_const"
9655 [(set (match_operand:DF 0 "register_operand" "=x")
9657 [(match_operand:V2DF 1 "vector_move_operand" "xmC")
9658 (match_operand:DF 2 "register_operand" "0")
9659 (match_operand:V2DF 3 "nonimmediate_operand" "xm")]
9661 "TARGET_SSE2 && TARGET_SSE_MATH"
9663 "&& reload_completed"
9666 ix86_split_copysign_const (operands);
9670 (define_insn "copysigndf3_var"
9671 [(set (match_operand:DF 0 "register_operand" "=x, x, x, x,x")
9673 [(match_operand:DF 2 "register_operand" " x, 0, 0, x,x")
9674 (match_operand:DF 3 "register_operand" " 1, 1, x, 1,x")
9675 (match_operand:V2DF 4 "nonimmediate_operand" " X,xm,xm, 0,0")
9676 (match_operand:V2DF 5 "nonimmediate_operand" " 0,xm, 1,xm,1")]
9678 (clobber (match_scratch:V2DF 1 "=x, x, x, x,x"))]
9679 "TARGET_SSE2 && TARGET_SSE_MATH"
9683 [(set (match_operand:DF 0 "register_operand" "")
9685 [(match_operand:DF 2 "register_operand" "")
9686 (match_operand:DF 3 "register_operand" "")
9687 (match_operand:V2DF 4 "" "")
9688 (match_operand:V2DF 5 "" "")]
9690 (clobber (match_scratch:V2DF 1 ""))]
9691 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
9694 ix86_split_copysign_var (operands);
9698 (define_expand "negxf2"
9699 [(set (match_operand:XF 0 "nonimmediate_operand" "")
9700 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
9702 "ix86_expand_fp_absneg_operator (NEG, XFmode, operands); DONE;")
9704 (define_expand "absxf2"
9705 [(set (match_operand:XF 0 "nonimmediate_operand" "")
9706 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
9708 "ix86_expand_fp_absneg_operator (ABS, XFmode, operands); DONE;")
9710 (define_insn "*absnegxf2_i387"
9711 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,?rm")
9712 (match_operator:XF 3 "absneg_operator"
9713 [(match_operand:XF 1 "nonimmediate_operand" "0,0")]))
9714 (use (match_operand 2 "" ""))
9715 (clobber (reg:CC FLAGS_REG))]
9717 && ix86_unary_operator_ok (GET_CODE (operands[3]), XFmode, operands)"
9720 ;; Splitters for fp abs and neg.
9723 [(set (match_operand 0 "fp_register_operand" "")
9724 (match_operator 1 "absneg_operator" [(match_dup 0)]))
9725 (use (match_operand 2 "" ""))
9726 (clobber (reg:CC FLAGS_REG))]
9728 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0)]))])
9731 [(set (match_operand 0 "register_operand" "")
9732 (match_operator 3 "absneg_operator"
9733 [(match_operand 1 "register_operand" "")]))
9734 (use (match_operand 2 "nonimmediate_operand" ""))
9735 (clobber (reg:CC FLAGS_REG))]
9736 "reload_completed && SSE_REG_P (operands[0])"
9737 [(set (match_dup 0) (match_dup 3))]
9739 enum machine_mode mode = GET_MODE (operands[0]);
9740 enum machine_mode vmode = GET_MODE (operands[2]);
9743 operands[0] = simplify_gen_subreg (vmode, operands[0], mode, 0);
9744 operands[1] = simplify_gen_subreg (vmode, operands[1], mode, 0);
9745 if (operands_match_p (operands[0], operands[2]))
9748 operands[1] = operands[2];
9751 if (GET_CODE (operands[3]) == ABS)
9752 tmp = gen_rtx_AND (vmode, operands[1], operands[2]);
9754 tmp = gen_rtx_XOR (vmode, operands[1], operands[2]);
9759 [(set (match_operand:SF 0 "register_operand" "")
9760 (match_operator:SF 1 "absneg_operator" [(match_dup 0)]))
9761 (use (match_operand:V4SF 2 "" ""))
9762 (clobber (reg:CC FLAGS_REG))]
9764 [(parallel [(set (match_dup 0) (match_dup 1))
9765 (clobber (reg:CC FLAGS_REG))])]
9768 operands[0] = gen_lowpart (SImode, operands[0]);
9769 if (GET_CODE (operands[1]) == ABS)
9771 tmp = gen_int_mode (0x7fffffff, SImode);
9772 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9776 tmp = gen_int_mode (0x80000000, SImode);
9777 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9783 [(set (match_operand:DF 0 "register_operand" "")
9784 (match_operator:DF 1 "absneg_operator" [(match_dup 0)]))
9785 (use (match_operand 2 "" ""))
9786 (clobber (reg:CC FLAGS_REG))]
9788 [(parallel [(set (match_dup 0) (match_dup 1))
9789 (clobber (reg:CC FLAGS_REG))])]
9794 tmp = gen_lowpart (DImode, operands[0]);
9795 tmp = gen_rtx_ZERO_EXTRACT (DImode, tmp, const1_rtx, GEN_INT (63));
9798 if (GET_CODE (operands[1]) == ABS)
9801 tmp = gen_rtx_NOT (DImode, tmp);
9805 operands[0] = gen_highpart (SImode, operands[0]);
9806 if (GET_CODE (operands[1]) == ABS)
9808 tmp = gen_int_mode (0x7fffffff, SImode);
9809 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9813 tmp = gen_int_mode (0x80000000, SImode);
9814 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9821 [(set (match_operand:XF 0 "register_operand" "")
9822 (match_operator:XF 1 "absneg_operator" [(match_dup 0)]))
9823 (use (match_operand 2 "" ""))
9824 (clobber (reg:CC FLAGS_REG))]
9826 [(parallel [(set (match_dup 0) (match_dup 1))
9827 (clobber (reg:CC FLAGS_REG))])]
9830 operands[0] = gen_rtx_REG (SImode,
9831 true_regnum (operands[0])
9832 + (TARGET_64BIT ? 1 : 2));
9833 if (GET_CODE (operands[1]) == ABS)
9835 tmp = GEN_INT (0x7fff);
9836 tmp = gen_rtx_AND (SImode, operands[0], tmp);
9840 tmp = GEN_INT (0x8000);
9841 tmp = gen_rtx_XOR (SImode, operands[0], tmp);
9847 [(set (match_operand 0 "memory_operand" "")
9848 (match_operator 1 "absneg_operator" [(match_dup 0)]))
9849 (use (match_operand 2 "" ""))
9850 (clobber (reg:CC FLAGS_REG))]
9852 [(parallel [(set (match_dup 0) (match_dup 1))
9853 (clobber (reg:CC FLAGS_REG))])]
9855 enum machine_mode mode = GET_MODE (operands[0]);
9856 int size = mode == XFmode ? 10 : GET_MODE_SIZE (mode);
9859 operands[0] = adjust_address (operands[0], QImode, size - 1);
9860 if (GET_CODE (operands[1]) == ABS)
9862 tmp = gen_int_mode (0x7f, QImode);
9863 tmp = gen_rtx_AND (QImode, operands[0], tmp);
9867 tmp = gen_int_mode (0x80, QImode);
9868 tmp = gen_rtx_XOR (QImode, operands[0], tmp);
9873 ;; Conditionalize these after reload. If they match before reload, we
9874 ;; lose the clobber and ability to use integer instructions.
9876 (define_insn "*negsf2_1"
9877 [(set (match_operand:SF 0 "register_operand" "=f")
9878 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
9879 "TARGET_80387 && reload_completed"
9881 [(set_attr "type" "fsgn")
9882 (set_attr "mode" "SF")])
9884 (define_insn "*negdf2_1"
9885 [(set (match_operand:DF 0 "register_operand" "=f")
9886 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
9887 "TARGET_80387 && reload_completed"
9889 [(set_attr "type" "fsgn")
9890 (set_attr "mode" "DF")])
9892 (define_insn "*negxf2_1"
9893 [(set (match_operand:XF 0 "register_operand" "=f")
9894 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
9895 "TARGET_80387 && reload_completed"
9897 [(set_attr "type" "fsgn")
9898 (set_attr "mode" "XF")])
9900 (define_insn "*abssf2_1"
9901 [(set (match_operand:SF 0 "register_operand" "=f")
9902 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
9903 "TARGET_80387 && reload_completed"
9905 [(set_attr "type" "fsgn")
9906 (set_attr "mode" "SF")])
9908 (define_insn "*absdf2_1"
9909 [(set (match_operand:DF 0 "register_operand" "=f")
9910 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
9911 "TARGET_80387 && reload_completed"
9913 [(set_attr "type" "fsgn")
9914 (set_attr "mode" "DF")])
9916 (define_insn "*absxf2_1"
9917 [(set (match_operand:XF 0 "register_operand" "=f")
9918 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
9919 "TARGET_80387 && reload_completed"
9921 [(set_attr "type" "fsgn")
9922 (set_attr "mode" "DF")])
9924 (define_insn "*negextendsfdf2"
9925 [(set (match_operand:DF 0 "register_operand" "=f")
9926 (neg:DF (float_extend:DF
9927 (match_operand:SF 1 "register_operand" "0"))))]
9928 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
9930 [(set_attr "type" "fsgn")
9931 (set_attr "mode" "DF")])
9933 (define_insn "*negextenddfxf2"
9934 [(set (match_operand:XF 0 "register_operand" "=f")
9935 (neg:XF (float_extend:XF
9936 (match_operand:DF 1 "register_operand" "0"))))]
9939 [(set_attr "type" "fsgn")
9940 (set_attr "mode" "XF")])
9942 (define_insn "*negextendsfxf2"
9943 [(set (match_operand:XF 0 "register_operand" "=f")
9944 (neg:XF (float_extend:XF
9945 (match_operand:SF 1 "register_operand" "0"))))]
9948 [(set_attr "type" "fsgn")
9949 (set_attr "mode" "XF")])
9951 (define_insn "*absextendsfdf2"
9952 [(set (match_operand:DF 0 "register_operand" "=f")
9953 (abs:DF (float_extend:DF
9954 (match_operand:SF 1 "register_operand" "0"))))]
9955 "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)"
9957 [(set_attr "type" "fsgn")
9958 (set_attr "mode" "DF")])
9960 (define_insn "*absextenddfxf2"
9961 [(set (match_operand:XF 0 "register_operand" "=f")
9962 (abs:XF (float_extend:XF
9963 (match_operand:DF 1 "register_operand" "0"))))]
9966 [(set_attr "type" "fsgn")
9967 (set_attr "mode" "XF")])
9969 (define_insn "*absextendsfxf2"
9970 [(set (match_operand:XF 0 "register_operand" "=f")
9971 (abs:XF (float_extend:XF
9972 (match_operand:SF 1 "register_operand" "0"))))]
9975 [(set_attr "type" "fsgn")
9976 (set_attr "mode" "XF")])
9978 ;; One complement instructions
9980 (define_expand "one_cmpldi2"
9981 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9982 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
9984 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
9986 (define_insn "*one_cmpldi2_1_rex64"
9987 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9988 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
9989 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
9991 [(set_attr "type" "negnot")
9992 (set_attr "mode" "DI")])
9994 (define_insn "*one_cmpldi2_2_rex64"
9995 [(set (reg FLAGS_REG)
9996 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9998 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9999 (not:DI (match_dup 1)))]
10000 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10001 && ix86_unary_operator_ok (NOT, DImode, operands)"
10003 [(set_attr "type" "alu1")
10004 (set_attr "mode" "DI")])
10007 [(set (match_operand 0 "flags_reg_operand" "")
10008 (match_operator 2 "compare_operator"
10009 [(not:DI (match_operand:DI 3 "nonimmediate_operand" ""))
10011 (set (match_operand:DI 1 "nonimmediate_operand" "")
10012 (not:DI (match_dup 3)))]
10013 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10014 [(parallel [(set (match_dup 0)
10016 [(xor:DI (match_dup 3) (const_int -1))
10019 (xor:DI (match_dup 3) (const_int -1)))])]
10022 (define_expand "one_cmplsi2"
10023 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10024 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10026 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10028 (define_insn "*one_cmplsi2_1"
10029 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10030 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10031 "ix86_unary_operator_ok (NOT, SImode, operands)"
10033 [(set_attr "type" "negnot")
10034 (set_attr "mode" "SI")])
10036 ;; ??? Currently never generated - xor is used instead.
10037 (define_insn "*one_cmplsi2_1_zext"
10038 [(set (match_operand:DI 0 "register_operand" "=r")
10039 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10040 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10042 [(set_attr "type" "negnot")
10043 (set_attr "mode" "SI")])
10045 (define_insn "*one_cmplsi2_2"
10046 [(set (reg FLAGS_REG)
10047 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10049 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10050 (not:SI (match_dup 1)))]
10051 "ix86_match_ccmode (insn, CCNOmode)
10052 && ix86_unary_operator_ok (NOT, SImode, operands)"
10054 [(set_attr "type" "alu1")
10055 (set_attr "mode" "SI")])
10058 [(set (match_operand 0 "flags_reg_operand" "")
10059 (match_operator 2 "compare_operator"
10060 [(not:SI (match_operand:SI 3 "nonimmediate_operand" ""))
10062 (set (match_operand:SI 1 "nonimmediate_operand" "")
10063 (not:SI (match_dup 3)))]
10064 "ix86_match_ccmode (insn, CCNOmode)"
10065 [(parallel [(set (match_dup 0)
10066 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10069 (xor:SI (match_dup 3) (const_int -1)))])]
10072 ;; ??? Currently never generated - xor is used instead.
10073 (define_insn "*one_cmplsi2_2_zext"
10074 [(set (reg FLAGS_REG)
10075 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10077 (set (match_operand:DI 0 "register_operand" "=r")
10078 (zero_extend:DI (not:SI (match_dup 1))))]
10079 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10080 && ix86_unary_operator_ok (NOT, SImode, operands)"
10082 [(set_attr "type" "alu1")
10083 (set_attr "mode" "SI")])
10086 [(set (match_operand 0 "flags_reg_operand" "")
10087 (match_operator 2 "compare_operator"
10088 [(not:SI (match_operand:SI 3 "register_operand" ""))
10090 (set (match_operand:DI 1 "register_operand" "")
10091 (zero_extend:DI (not:SI (match_dup 3))))]
10092 "ix86_match_ccmode (insn, CCNOmode)"
10093 [(parallel [(set (match_dup 0)
10094 (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
10097 (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])]
10100 (define_expand "one_cmplhi2"
10101 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10102 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10103 "TARGET_HIMODE_MATH"
10104 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10106 (define_insn "*one_cmplhi2_1"
10107 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10108 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10109 "ix86_unary_operator_ok (NOT, HImode, operands)"
10111 [(set_attr "type" "negnot")
10112 (set_attr "mode" "HI")])
10114 (define_insn "*one_cmplhi2_2"
10115 [(set (reg FLAGS_REG)
10116 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10118 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10119 (not:HI (match_dup 1)))]
10120 "ix86_match_ccmode (insn, CCNOmode)
10121 && ix86_unary_operator_ok (NEG, HImode, operands)"
10123 [(set_attr "type" "alu1")
10124 (set_attr "mode" "HI")])
10127 [(set (match_operand 0 "flags_reg_operand" "")
10128 (match_operator 2 "compare_operator"
10129 [(not:HI (match_operand:HI 3 "nonimmediate_operand" ""))
10131 (set (match_operand:HI 1 "nonimmediate_operand" "")
10132 (not:HI (match_dup 3)))]
10133 "ix86_match_ccmode (insn, CCNOmode)"
10134 [(parallel [(set (match_dup 0)
10135 (match_op_dup 2 [(xor:HI (match_dup 3) (const_int -1))
10138 (xor:HI (match_dup 3) (const_int -1)))])]
10141 ;; %%% Potential partial reg stall on alternative 1. What to do?
10142 (define_expand "one_cmplqi2"
10143 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10144 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10145 "TARGET_QIMODE_MATH"
10146 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10148 (define_insn "*one_cmplqi2_1"
10149 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10150 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10151 "ix86_unary_operator_ok (NOT, QImode, operands)"
10155 [(set_attr "type" "negnot")
10156 (set_attr "mode" "QI,SI")])
10158 (define_insn "*one_cmplqi2_2"
10159 [(set (reg FLAGS_REG)
10160 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10162 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10163 (not:QI (match_dup 1)))]
10164 "ix86_match_ccmode (insn, CCNOmode)
10165 && ix86_unary_operator_ok (NOT, QImode, operands)"
10167 [(set_attr "type" "alu1")
10168 (set_attr "mode" "QI")])
10171 [(set (match_operand 0 "flags_reg_operand" "")
10172 (match_operator 2 "compare_operator"
10173 [(not:QI (match_operand:QI 3 "nonimmediate_operand" ""))
10175 (set (match_operand:QI 1 "nonimmediate_operand" "")
10176 (not:QI (match_dup 3)))]
10177 "ix86_match_ccmode (insn, CCNOmode)"
10178 [(parallel [(set (match_dup 0)
10179 (match_op_dup 2 [(xor:QI (match_dup 3) (const_int -1))
10182 (xor:QI (match_dup 3) (const_int -1)))])]
10185 ;; Arithmetic shift instructions
10187 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10188 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10189 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10190 ;; from the assembler input.
10192 ;; This instruction shifts the target reg/mem as usual, but instead of
10193 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10194 ;; is a left shift double, bits are taken from the high order bits of
10195 ;; reg, else if the insn is a shift right double, bits are taken from the
10196 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10197 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10199 ;; Since sh[lr]d does not change the `reg' operand, that is done
10200 ;; separately, making all shifts emit pairs of shift double and normal
10201 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10202 ;; support a 63 bit shift, each shift where the count is in a reg expands
10203 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10205 ;; If the shift count is a constant, we need never emit more than one
10206 ;; shift pair, instead using moves and sign extension for counts greater
10209 (define_expand "ashlti3"
10210 [(parallel [(set (match_operand:TI 0 "register_operand" "")
10211 (ashift:TI (match_operand:TI 1 "register_operand" "")
10212 (match_operand:QI 2 "nonmemory_operand" "")))
10213 (clobber (reg:CC FLAGS_REG))])]
10216 if (! immediate_operand (operands[2], QImode))
10218 emit_insn (gen_ashlti3_1 (operands[0], operands[1], operands[2]));
10221 ix86_expand_binary_operator (ASHIFT, TImode, operands);
10225 (define_insn "ashlti3_1"
10226 [(set (match_operand:TI 0 "register_operand" "=r")
10227 (ashift:TI (match_operand:TI 1 "register_operand" "0")
10228 (match_operand:QI 2 "register_operand" "c")))
10229 (clobber (match_scratch:DI 3 "=&r"))
10230 (clobber (reg:CC FLAGS_REG))]
10233 [(set_attr "type" "multi")])
10235 (define_insn "*ashlti3_2"
10236 [(set (match_operand:TI 0 "register_operand" "=r")
10237 (ashift:TI (match_operand:TI 1 "register_operand" "0")
10238 (match_operand:QI 2 "immediate_operand" "O")))
10239 (clobber (reg:CC FLAGS_REG))]
10242 [(set_attr "type" "multi")])
10245 [(set (match_operand:TI 0 "register_operand" "")
10246 (ashift:TI (match_operand:TI 1 "nonmemory_operand" "")
10247 (match_operand:QI 2 "register_operand" "")))
10248 (clobber (match_scratch:DI 3 ""))
10249 (clobber (reg:CC FLAGS_REG))]
10250 "TARGET_64BIT && reload_completed"
10252 "ix86_split_ashl (operands, operands[3], TImode); DONE;")
10255 [(set (match_operand:TI 0 "register_operand" "")
10256 (ashift:TI (match_operand:TI 1 "register_operand" "")
10257 (match_operand:QI 2 "immediate_operand" "")))
10258 (clobber (reg:CC FLAGS_REG))]
10259 "TARGET_64BIT && reload_completed"
10261 "ix86_split_ashl (operands, NULL_RTX, TImode); DONE;")
10263 (define_insn "x86_64_shld"
10264 [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m,r*m")
10265 (ior:DI (ashift:DI (match_dup 0)
10266 (match_operand:QI 2 "nonmemory_operand" "J,c"))
10267 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
10268 (minus:QI (const_int 64) (match_dup 2)))))
10269 (clobber (reg:CC FLAGS_REG))]
10272 shld{q}\t{%2, %1, %0|%0, %1, %2}
10273 shld{q}\t{%s2%1, %0|%0, %1, %2}"
10274 [(set_attr "type" "ishift")
10275 (set_attr "prefix_0f" "1")
10276 (set_attr "mode" "DI")
10277 (set_attr "athlon_decode" "vector")])
10279 (define_expand "x86_64_shift_adj"
10280 [(set (reg:CCZ FLAGS_REG)
10281 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10284 (set (match_operand:DI 0 "register_operand" "")
10285 (if_then_else:DI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10286 (match_operand:DI 1 "register_operand" "")
10289 (if_then_else:DI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10290 (match_operand:DI 3 "register_operand" "r")
10295 (define_expand "ashldi3"
10296 [(set (match_operand:DI 0 "shiftdi_operand" "")
10297 (ashift:DI (match_operand:DI 1 "ashldi_input_operand" "")
10298 (match_operand:QI 2 "nonmemory_operand" "")))]
10300 "ix86_expand_binary_operator (ASHIFT, DImode, operands); DONE;")
10302 (define_insn "*ashldi3_1_rex64"
10303 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
10304 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,l")
10305 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
10306 (clobber (reg:CC FLAGS_REG))]
10307 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10309 switch (get_attr_type (insn))
10312 gcc_assert (operands[2] == const1_rtx);
10313 gcc_assert (rtx_equal_p (operands[0], operands[1]));
10314 return "add{q}\t{%0, %0|%0, %0}";
10317 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10318 gcc_assert ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) <= 3);
10319 operands[1] = gen_rtx_MULT (DImode, operands[1],
10320 GEN_INT (1 << INTVAL (operands[2])));
10321 return "lea{q}\t{%a1, %0|%0, %a1}";
10324 if (REG_P (operands[2]))
10325 return "sal{q}\t{%b2, %0|%0, %b2}";
10326 else if (operands[2] == const1_rtx
10327 && (TARGET_SHIFT1 || optimize_size))
10328 return "sal{q}\t%0";
10330 return "sal{q}\t{%2, %0|%0, %2}";
10333 [(set (attr "type")
10334 (cond [(eq_attr "alternative" "1")
10335 (const_string "lea")
10336 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10338 (match_operand 0 "register_operand" ""))
10339 (match_operand 2 "const1_operand" ""))
10340 (const_string "alu")
10342 (const_string "ishift")))
10343 (set_attr "mode" "DI")])
10345 ;; Convert lea to the lea pattern to avoid flags dependency.
10347 [(set (match_operand:DI 0 "register_operand" "")
10348 (ashift:DI (match_operand:DI 1 "index_register_operand" "")
10349 (match_operand:QI 2 "immediate_operand" "")))
10350 (clobber (reg:CC FLAGS_REG))]
10351 "TARGET_64BIT && reload_completed
10352 && true_regnum (operands[0]) != true_regnum (operands[1])"
10353 [(set (match_dup 0)
10354 (mult:DI (match_dup 1)
10356 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
10358 ;; This pattern can't accept a variable shift count, since shifts by
10359 ;; zero don't affect the flags. We assume that shifts by constant
10360 ;; zero are optimized away.
10361 (define_insn "*ashldi3_cmp_rex64"
10362 [(set (reg FLAGS_REG)
10364 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
10365 (match_operand:QI 2 "immediate_operand" "e"))
10367 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10368 (ashift:DI (match_dup 1) (match_dup 2)))]
10369 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10370 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
10372 switch (get_attr_type (insn))
10375 gcc_assert (operands[2] == const1_rtx);
10376 return "add{q}\t{%0, %0|%0, %0}";
10379 if (REG_P (operands[2]))
10380 return "sal{q}\t{%b2, %0|%0, %b2}";
10381 else if (operands[2] == const1_rtx
10382 && (TARGET_SHIFT1 || optimize_size))
10383 return "sal{q}\t%0";
10385 return "sal{q}\t{%2, %0|%0, %2}";
10388 [(set (attr "type")
10389 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10391 (match_operand 0 "register_operand" ""))
10392 (match_operand 2 "const1_operand" ""))
10393 (const_string "alu")
10395 (const_string "ishift")))
10396 (set_attr "mode" "DI")])
10398 (define_insn "*ashldi3_1"
10399 [(set (match_operand:DI 0 "register_operand" "=&r,r")
10400 (ashift:DI (match_operand:DI 1 "reg_or_pm1_operand" "n,0")
10401 (match_operand:QI 2 "nonmemory_operand" "Jc,Jc")))
10402 (clobber (reg:CC FLAGS_REG))]
10405 [(set_attr "type" "multi")])
10407 ;; By default we don't ask for a scratch register, because when DImode
10408 ;; values are manipulated, registers are already at a premium. But if
10409 ;; we have one handy, we won't turn it away.
10411 [(match_scratch:SI 3 "r")
10412 (parallel [(set (match_operand:DI 0 "register_operand" "")
10413 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
10414 (match_operand:QI 2 "nonmemory_operand" "")))
10415 (clobber (reg:CC FLAGS_REG))])
10417 "!TARGET_64BIT && TARGET_CMOVE"
10419 "ix86_split_ashl (operands, operands[3], DImode); DONE;")
10422 [(set (match_operand:DI 0 "register_operand" "")
10423 (ashift:DI (match_operand:DI 1 "nonmemory_operand" "")
10424 (match_operand:QI 2 "nonmemory_operand" "")))
10425 (clobber (reg:CC FLAGS_REG))]
10426 "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
10427 ? flow2_completed : reload_completed)"
10429 "ix86_split_ashl (operands, NULL_RTX, DImode); DONE;")
10431 (define_insn "x86_shld_1"
10432 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
10433 (ior:SI (ashift:SI (match_dup 0)
10434 (match_operand:QI 2 "nonmemory_operand" "I,c"))
10435 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
10436 (minus:QI (const_int 32) (match_dup 2)))))
10437 (clobber (reg:CC FLAGS_REG))]
10440 shld{l}\t{%2, %1, %0|%0, %1, %2}
10441 shld{l}\t{%s2%1, %0|%0, %1, %2}"
10442 [(set_attr "type" "ishift")
10443 (set_attr "prefix_0f" "1")
10444 (set_attr "mode" "SI")
10445 (set_attr "pent_pair" "np")
10446 (set_attr "athlon_decode" "vector")])
10448 (define_expand "x86_shift_adj_1"
10449 [(set (reg:CCZ FLAGS_REG)
10450 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
10453 (set (match_operand:SI 0 "register_operand" "")
10454 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10455 (match_operand:SI 1 "register_operand" "")
10458 (if_then_else:SI (ne (reg:CCZ FLAGS_REG) (const_int 0))
10459 (match_operand:SI 3 "register_operand" "r")
10464 (define_expand "x86_shift_adj_2"
10465 [(use (match_operand:SI 0 "register_operand" ""))
10466 (use (match_operand:SI 1 "register_operand" ""))
10467 (use (match_operand:QI 2 "register_operand" ""))]
10470 rtx label = gen_label_rtx ();
10473 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
10475 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
10476 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
10477 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
10478 gen_rtx_LABEL_REF (VOIDmode, label),
10480 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
10481 JUMP_LABEL (tmp) = label;
10483 emit_move_insn (operands[0], operands[1]);
10484 ix86_expand_clear (operands[1]);
10486 emit_label (label);
10487 LABEL_NUSES (label) = 1;
10492 (define_expand "ashlsi3"
10493 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10494 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
10495 (match_operand:QI 2 "nonmemory_operand" "")))
10496 (clobber (reg:CC FLAGS_REG))]
10498 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
10500 (define_insn "*ashlsi3_1"
10501 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
10502 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,l")
10503 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10504 (clobber (reg:CC FLAGS_REG))]
10505 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10507 switch (get_attr_type (insn))
10510 gcc_assert (operands[2] == const1_rtx);
10511 gcc_assert (rtx_equal_p (operands[0], operands[1]));
10512 return "add{l}\t{%0, %0|%0, %0}";
10518 if (REG_P (operands[2]))
10519 return "sal{l}\t{%b2, %0|%0, %b2}";
10520 else if (operands[2] == const1_rtx
10521 && (TARGET_SHIFT1 || optimize_size))
10522 return "sal{l}\t%0";
10524 return "sal{l}\t{%2, %0|%0, %2}";
10527 [(set (attr "type")
10528 (cond [(eq_attr "alternative" "1")
10529 (const_string "lea")
10530 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10532 (match_operand 0 "register_operand" ""))
10533 (match_operand 2 "const1_operand" ""))
10534 (const_string "alu")
10536 (const_string "ishift")))
10537 (set_attr "mode" "SI")])
10539 ;; Convert lea to the lea pattern to avoid flags dependency.
10541 [(set (match_operand 0 "register_operand" "")
10542 (ashift (match_operand 1 "index_register_operand" "")
10543 (match_operand:QI 2 "const_int_operand" "")))
10544 (clobber (reg:CC FLAGS_REG))]
10546 && true_regnum (operands[0]) != true_regnum (operands[1])
10547 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 4"
10551 enum machine_mode mode = GET_MODE (operands[0]);
10553 if (GET_MODE_SIZE (mode) < 4)
10554 operands[0] = gen_lowpart (SImode, operands[0]);
10556 operands[1] = gen_lowpart (Pmode, operands[1]);
10557 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10559 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
10560 if (Pmode != SImode)
10561 pat = gen_rtx_SUBREG (SImode, pat, 0);
10562 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
10566 ;; Rare case of shifting RSP is handled by generating move and shift
10568 [(set (match_operand 0 "register_operand" "")
10569 (ashift (match_operand 1 "register_operand" "")
10570 (match_operand:QI 2 "const_int_operand" "")))
10571 (clobber (reg:CC FLAGS_REG))]
10573 && true_regnum (operands[0]) != true_regnum (operands[1])"
10577 emit_move_insn (operands[1], operands[0]);
10578 pat = gen_rtx_SET (VOIDmode, operands[0],
10579 gen_rtx_ASHIFT (GET_MODE (operands[0]),
10580 operands[0], operands[2]));
10581 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10582 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
10586 (define_insn "*ashlsi3_1_zext"
10587 [(set (match_operand:DI 0 "register_operand" "=r,r")
10588 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,l")
10589 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
10590 (clobber (reg:CC FLAGS_REG))]
10591 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10593 switch (get_attr_type (insn))
10596 gcc_assert (operands[2] == const1_rtx);
10597 return "add{l}\t{%k0, %k0|%k0, %k0}";
10603 if (REG_P (operands[2]))
10604 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10605 else if (operands[2] == const1_rtx
10606 && (TARGET_SHIFT1 || optimize_size))
10607 return "sal{l}\t%k0";
10609 return "sal{l}\t{%2, %k0|%k0, %2}";
10612 [(set (attr "type")
10613 (cond [(eq_attr "alternative" "1")
10614 (const_string "lea")
10615 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10617 (match_operand 2 "const1_operand" ""))
10618 (const_string "alu")
10620 (const_string "ishift")))
10621 (set_attr "mode" "SI")])
10623 ;; Convert lea to the lea pattern to avoid flags dependency.
10625 [(set (match_operand:DI 0 "register_operand" "")
10626 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
10627 (match_operand:QI 2 "const_int_operand" ""))))
10628 (clobber (reg:CC FLAGS_REG))]
10629 "TARGET_64BIT && reload_completed
10630 && true_regnum (operands[0]) != true_regnum (operands[1])"
10631 [(set (match_dup 0) (zero_extend:DI
10632 (subreg:SI (mult:SI (match_dup 1)
10633 (match_dup 2)) 0)))]
10635 operands[1] = gen_lowpart (Pmode, operands[1]);
10636 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
10639 ;; This pattern can't accept a variable shift count, since shifts by
10640 ;; zero don't affect the flags. We assume that shifts by constant
10641 ;; zero are optimized away.
10642 (define_insn "*ashlsi3_cmp"
10643 [(set (reg FLAGS_REG)
10645 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
10646 (match_operand:QI 2 "const_1_to_31_operand" "I"))
10648 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10649 (ashift:SI (match_dup 1) (match_dup 2)))]
10650 "ix86_match_ccmode (insn, CCGOCmode)
10651 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10653 switch (get_attr_type (insn))
10656 gcc_assert (operands[2] == const1_rtx);
10657 return "add{l}\t{%0, %0|%0, %0}";
10660 if (REG_P (operands[2]))
10661 return "sal{l}\t{%b2, %0|%0, %b2}";
10662 else if (operands[2] == const1_rtx
10663 && (TARGET_SHIFT1 || optimize_size))
10664 return "sal{l}\t%0";
10666 return "sal{l}\t{%2, %0|%0, %2}";
10669 [(set (attr "type")
10670 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10672 (match_operand 0 "register_operand" ""))
10673 (match_operand 2 "const1_operand" ""))
10674 (const_string "alu")
10676 (const_string "ishift")))
10677 (set_attr "mode" "SI")])
10679 (define_insn "*ashlsi3_cmp_zext"
10680 [(set (reg FLAGS_REG)
10682 (ashift:SI (match_operand:SI 1 "register_operand" "0")
10683 (match_operand:QI 2 "const_1_to_31_operand" "I"))
10685 (set (match_operand:DI 0 "register_operand" "=r")
10686 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
10687 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
10688 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
10690 switch (get_attr_type (insn))
10693 gcc_assert (operands[2] == const1_rtx);
10694 return "add{l}\t{%k0, %k0|%k0, %k0}";
10697 if (REG_P (operands[2]))
10698 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10699 else if (operands[2] == const1_rtx
10700 && (TARGET_SHIFT1 || optimize_size))
10701 return "sal{l}\t%k0";
10703 return "sal{l}\t{%2, %k0|%k0, %2}";
10706 [(set (attr "type")
10707 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10709 (match_operand 2 "const1_operand" ""))
10710 (const_string "alu")
10712 (const_string "ishift")))
10713 (set_attr "mode" "SI")])
10715 (define_expand "ashlhi3"
10716 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10717 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
10718 (match_operand:QI 2 "nonmemory_operand" "")))
10719 (clobber (reg:CC FLAGS_REG))]
10720 "TARGET_HIMODE_MATH"
10721 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
10723 (define_insn "*ashlhi3_1_lea"
10724 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
10725 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,l")
10726 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
10727 (clobber (reg:CC FLAGS_REG))]
10728 "!TARGET_PARTIAL_REG_STALL
10729 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10731 switch (get_attr_type (insn))
10736 gcc_assert (operands[2] == const1_rtx);
10737 return "add{w}\t{%0, %0|%0, %0}";
10740 if (REG_P (operands[2]))
10741 return "sal{w}\t{%b2, %0|%0, %b2}";
10742 else if (operands[2] == const1_rtx
10743 && (TARGET_SHIFT1 || optimize_size))
10744 return "sal{w}\t%0";
10746 return "sal{w}\t{%2, %0|%0, %2}";
10749 [(set (attr "type")
10750 (cond [(eq_attr "alternative" "1")
10751 (const_string "lea")
10752 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10754 (match_operand 0 "register_operand" ""))
10755 (match_operand 2 "const1_operand" ""))
10756 (const_string "alu")
10758 (const_string "ishift")))
10759 (set_attr "mode" "HI,SI")])
10761 (define_insn "*ashlhi3_1"
10762 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10763 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10764 (match_operand:QI 2 "nonmemory_operand" "cI")))
10765 (clobber (reg:CC FLAGS_REG))]
10766 "TARGET_PARTIAL_REG_STALL
10767 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10769 switch (get_attr_type (insn))
10772 gcc_assert (operands[2] == const1_rtx);
10773 return "add{w}\t{%0, %0|%0, %0}";
10776 if (REG_P (operands[2]))
10777 return "sal{w}\t{%b2, %0|%0, %b2}";
10778 else if (operands[2] == const1_rtx
10779 && (TARGET_SHIFT1 || optimize_size))
10780 return "sal{w}\t%0";
10782 return "sal{w}\t{%2, %0|%0, %2}";
10785 [(set (attr "type")
10786 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10788 (match_operand 0 "register_operand" ""))
10789 (match_operand 2 "const1_operand" ""))
10790 (const_string "alu")
10792 (const_string "ishift")))
10793 (set_attr "mode" "HI")])
10795 ;; This pattern can't accept a variable shift count, since shifts by
10796 ;; zero don't affect the flags. We assume that shifts by constant
10797 ;; zero are optimized away.
10798 (define_insn "*ashlhi3_cmp"
10799 [(set (reg FLAGS_REG)
10801 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
10802 (match_operand:QI 2 "const_1_to_31_operand" "I"))
10804 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10805 (ashift:HI (match_dup 1) (match_dup 2)))]
10806 "ix86_match_ccmode (insn, CCGOCmode)
10807 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
10809 switch (get_attr_type (insn))
10812 gcc_assert (operands[2] == const1_rtx);
10813 return "add{w}\t{%0, %0|%0, %0}";
10816 if (REG_P (operands[2]))
10817 return "sal{w}\t{%b2, %0|%0, %b2}";
10818 else if (operands[2] == const1_rtx
10819 && (TARGET_SHIFT1 || optimize_size))
10820 return "sal{w}\t%0";
10822 return "sal{w}\t{%2, %0|%0, %2}";
10825 [(set (attr "type")
10826 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10828 (match_operand 0 "register_operand" ""))
10829 (match_operand 2 "const1_operand" ""))
10830 (const_string "alu")
10832 (const_string "ishift")))
10833 (set_attr "mode" "HI")])
10835 (define_expand "ashlqi3"
10836 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10837 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
10838 (match_operand:QI 2 "nonmemory_operand" "")))
10839 (clobber (reg:CC FLAGS_REG))]
10840 "TARGET_QIMODE_MATH"
10841 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
10843 ;; %%% Potential partial reg stall on alternative 2. What to do?
10845 (define_insn "*ashlqi3_1_lea"
10846 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
10847 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,l")
10848 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
10849 (clobber (reg:CC FLAGS_REG))]
10850 "!TARGET_PARTIAL_REG_STALL
10851 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10853 switch (get_attr_type (insn))
10858 gcc_assert (operands[2] == const1_rtx);
10859 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10860 return "add{l}\t{%k0, %k0|%k0, %k0}";
10862 return "add{b}\t{%0, %0|%0, %0}";
10865 if (REG_P (operands[2]))
10867 if (get_attr_mode (insn) == MODE_SI)
10868 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10870 return "sal{b}\t{%b2, %0|%0, %b2}";
10872 else if (operands[2] == const1_rtx
10873 && (TARGET_SHIFT1 || optimize_size))
10875 if (get_attr_mode (insn) == MODE_SI)
10876 return "sal{l}\t%0";
10878 return "sal{b}\t%0";
10882 if (get_attr_mode (insn) == MODE_SI)
10883 return "sal{l}\t{%2, %k0|%k0, %2}";
10885 return "sal{b}\t{%2, %0|%0, %2}";
10889 [(set (attr "type")
10890 (cond [(eq_attr "alternative" "2")
10891 (const_string "lea")
10892 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10894 (match_operand 0 "register_operand" ""))
10895 (match_operand 2 "const1_operand" ""))
10896 (const_string "alu")
10898 (const_string "ishift")))
10899 (set_attr "mode" "QI,SI,SI")])
10901 (define_insn "*ashlqi3_1"
10902 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10903 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
10904 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
10905 (clobber (reg:CC FLAGS_REG))]
10906 "TARGET_PARTIAL_REG_STALL
10907 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10909 switch (get_attr_type (insn))
10912 gcc_assert (operands[2] == const1_rtx);
10913 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
10914 return "add{l}\t{%k0, %k0|%k0, %k0}";
10916 return "add{b}\t{%0, %0|%0, %0}";
10919 if (REG_P (operands[2]))
10921 if (get_attr_mode (insn) == MODE_SI)
10922 return "sal{l}\t{%b2, %k0|%k0, %b2}";
10924 return "sal{b}\t{%b2, %0|%0, %b2}";
10926 else if (operands[2] == const1_rtx
10927 && (TARGET_SHIFT1 || optimize_size))
10929 if (get_attr_mode (insn) == MODE_SI)
10930 return "sal{l}\t%0";
10932 return "sal{b}\t%0";
10936 if (get_attr_mode (insn) == MODE_SI)
10937 return "sal{l}\t{%2, %k0|%k0, %2}";
10939 return "sal{b}\t{%2, %0|%0, %2}";
10943 [(set (attr "type")
10944 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10946 (match_operand 0 "register_operand" ""))
10947 (match_operand 2 "const1_operand" ""))
10948 (const_string "alu")
10950 (const_string "ishift")))
10951 (set_attr "mode" "QI,SI")])
10953 ;; This pattern can't accept a variable shift count, since shifts by
10954 ;; zero don't affect the flags. We assume that shifts by constant
10955 ;; zero are optimized away.
10956 (define_insn "*ashlqi3_cmp"
10957 [(set (reg FLAGS_REG)
10959 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
10960 (match_operand:QI 2 "const_1_to_31_operand" "I"))
10962 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10963 (ashift:QI (match_dup 1) (match_dup 2)))]
10964 "ix86_match_ccmode (insn, CCGOCmode)
10965 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
10967 switch (get_attr_type (insn))
10970 gcc_assert (operands[2] == const1_rtx);
10971 return "add{b}\t{%0, %0|%0, %0}";
10974 if (REG_P (operands[2]))
10975 return "sal{b}\t{%b2, %0|%0, %b2}";
10976 else if (operands[2] == const1_rtx
10977 && (TARGET_SHIFT1 || optimize_size))
10978 return "sal{b}\t%0";
10980 return "sal{b}\t{%2, %0|%0, %2}";
10983 [(set (attr "type")
10984 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
10986 (match_operand 0 "register_operand" ""))
10987 (match_operand 2 "const1_operand" ""))
10988 (const_string "alu")
10990 (const_string "ishift")))
10991 (set_attr "mode" "QI")])
10993 ;; See comment above `ashldi3' about how this works.
10995 (define_expand "ashrti3"
10996 [(parallel [(set (match_operand:TI 0 "register_operand" "")
10997 (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
10998 (match_operand:QI 2 "nonmemory_operand" "")))
10999 (clobber (reg:CC FLAGS_REG))])]
11002 if (! immediate_operand (operands[2], QImode))
11004 emit_insn (gen_ashrti3_1 (operands[0], operands[1], operands[2]));
11007 ix86_expand_binary_operator (ASHIFTRT, TImode, operands);
11011 (define_insn "ashrti3_1"
11012 [(set (match_operand:TI 0 "register_operand" "=r")
11013 (ashiftrt:TI (match_operand:TI 1 "register_operand" "0")
11014 (match_operand:QI 2 "register_operand" "c")))
11015 (clobber (match_scratch:DI 3 "=&r"))
11016 (clobber (reg:CC FLAGS_REG))]
11019 [(set_attr "type" "multi")])
11021 (define_insn "*ashrti3_2"
11022 [(set (match_operand:TI 0 "register_operand" "=r")
11023 (ashiftrt:TI (match_operand:TI 1 "register_operand" "0")
11024 (match_operand:QI 2 "immediate_operand" "O")))
11025 (clobber (reg:CC FLAGS_REG))]
11028 [(set_attr "type" "multi")])
11031 [(set (match_operand:TI 0 "register_operand" "")
11032 (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
11033 (match_operand:QI 2 "register_operand" "")))
11034 (clobber (match_scratch:DI 3 ""))
11035 (clobber (reg:CC FLAGS_REG))]
11036 "TARGET_64BIT && reload_completed"
11038 "ix86_split_ashr (operands, operands[3], TImode); DONE;")
11041 [(set (match_operand:TI 0 "register_operand" "")
11042 (ashiftrt:TI (match_operand:TI 1 "register_operand" "")
11043 (match_operand:QI 2 "immediate_operand" "")))
11044 (clobber (reg:CC FLAGS_REG))]
11045 "TARGET_64BIT && reload_completed"
11047 "ix86_split_ashr (operands, NULL_RTX, TImode); DONE;")
11049 (define_insn "x86_64_shrd"
11050 [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m,r*m")
11051 (ior:DI (ashiftrt:DI (match_dup 0)
11052 (match_operand:QI 2 "nonmemory_operand" "J,c"))
11053 (ashift:DI (match_operand:DI 1 "register_operand" "r,r")
11054 (minus:QI (const_int 64) (match_dup 2)))))
11055 (clobber (reg:CC FLAGS_REG))]
11058 shrd{q}\t{%2, %1, %0|%0, %1, %2}
11059 shrd{q}\t{%s2%1, %0|%0, %1, %2}"
11060 [(set_attr "type" "ishift")
11061 (set_attr "prefix_0f" "1")
11062 (set_attr "mode" "DI")
11063 (set_attr "athlon_decode" "vector")])
11065 (define_expand "ashrdi3"
11066 [(set (match_operand:DI 0 "shiftdi_operand" "")
11067 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11068 (match_operand:QI 2 "nonmemory_operand" "")))]
11070 "ix86_expand_binary_operator (ASHIFTRT, DImode, operands); DONE;")
11072 (define_insn "*ashrdi3_63_rex64"
11073 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11074 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11075 (match_operand:DI 2 "const_int_operand" "i,i")))
11076 (clobber (reg:CC FLAGS_REG))]
11077 "TARGET_64BIT && INTVAL (operands[2]) == 63
11078 && (TARGET_USE_CLTD || optimize_size)
11079 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11082 sar{q}\t{%2, %0|%0, %2}"
11083 [(set_attr "type" "imovx,ishift")
11084 (set_attr "prefix_0f" "0,*")
11085 (set_attr "length_immediate" "0,*")
11086 (set_attr "modrm" "0,1")
11087 (set_attr "mode" "DI")])
11089 (define_insn "*ashrdi3_1_one_bit_rex64"
11090 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11091 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11092 (match_operand:QI 2 "const1_operand" "")))
11093 (clobber (reg:CC FLAGS_REG))]
11094 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11095 && (TARGET_SHIFT1 || optimize_size)"
11097 [(set_attr "type" "ishift")
11098 (set (attr "length")
11099 (if_then_else (match_operand:DI 0 "register_operand" "")
11101 (const_string "*")))])
11103 (define_insn "*ashrdi3_1_rex64"
11104 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11105 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11106 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11107 (clobber (reg:CC FLAGS_REG))]
11108 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11110 sar{q}\t{%2, %0|%0, %2}
11111 sar{q}\t{%b2, %0|%0, %b2}"
11112 [(set_attr "type" "ishift")
11113 (set_attr "mode" "DI")])
11115 ;; This pattern can't accept a variable shift count, since shifts by
11116 ;; zero don't affect the flags. We assume that shifts by constant
11117 ;; zero are optimized away.
11118 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11119 [(set (reg FLAGS_REG)
11121 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11122 (match_operand:QI 2 "const1_operand" ""))
11124 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11125 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11126 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11127 && (TARGET_SHIFT1 || optimize_size)
11128 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11130 [(set_attr "type" "ishift")
11131 (set (attr "length")
11132 (if_then_else (match_operand:DI 0 "register_operand" "")
11134 (const_string "*")))])
11136 ;; This pattern can't accept a variable shift count, since shifts by
11137 ;; zero don't affect the flags. We assume that shifts by constant
11138 ;; zero are optimized away.
11139 (define_insn "*ashrdi3_cmp_rex64"
11140 [(set (reg FLAGS_REG)
11142 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11143 (match_operand:QI 2 "const_int_operand" "n"))
11145 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11146 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11147 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11148 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11149 "sar{q}\t{%2, %0|%0, %2}"
11150 [(set_attr "type" "ishift")
11151 (set_attr "mode" "DI")])
11153 (define_insn "*ashrdi3_1"
11154 [(set (match_operand:DI 0 "register_operand" "=r")
11155 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11156 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11157 (clobber (reg:CC FLAGS_REG))]
11160 [(set_attr "type" "multi")])
11162 ;; By default we don't ask for a scratch register, because when DImode
11163 ;; values are manipulated, registers are already at a premium. But if
11164 ;; we have one handy, we won't turn it away.
11166 [(match_scratch:SI 3 "r")
11167 (parallel [(set (match_operand:DI 0 "register_operand" "")
11168 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11169 (match_operand:QI 2 "nonmemory_operand" "")))
11170 (clobber (reg:CC FLAGS_REG))])
11172 "!TARGET_64BIT && TARGET_CMOVE"
11174 "ix86_split_ashr (operands, operands[3], DImode); DONE;")
11177 [(set (match_operand:DI 0 "register_operand" "")
11178 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11179 (match_operand:QI 2 "nonmemory_operand" "")))
11180 (clobber (reg:CC FLAGS_REG))]
11181 "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
11182 ? flow2_completed : reload_completed)"
11184 "ix86_split_ashr (operands, NULL_RTX, DImode); DONE;")
11186 (define_insn "x86_shrd_1"
11187 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11188 (ior:SI (ashiftrt:SI (match_dup 0)
11189 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11190 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11191 (minus:QI (const_int 32) (match_dup 2)))))
11192 (clobber (reg:CC FLAGS_REG))]
11195 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11196 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11197 [(set_attr "type" "ishift")
11198 (set_attr "prefix_0f" "1")
11199 (set_attr "pent_pair" "np")
11200 (set_attr "mode" "SI")])
11202 (define_expand "x86_shift_adj_3"
11203 [(use (match_operand:SI 0 "register_operand" ""))
11204 (use (match_operand:SI 1 "register_operand" ""))
11205 (use (match_operand:QI 2 "register_operand" ""))]
11208 rtx label = gen_label_rtx ();
11211 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11213 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11214 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11215 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11216 gen_rtx_LABEL_REF (VOIDmode, label),
11218 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11219 JUMP_LABEL (tmp) = label;
11221 emit_move_insn (operands[0], operands[1]);
11222 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11224 emit_label (label);
11225 LABEL_NUSES (label) = 1;
11230 (define_insn "ashrsi3_31"
11231 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11232 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11233 (match_operand:SI 2 "const_int_operand" "i,i")))
11234 (clobber (reg:CC FLAGS_REG))]
11235 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11236 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11239 sar{l}\t{%2, %0|%0, %2}"
11240 [(set_attr "type" "imovx,ishift")
11241 (set_attr "prefix_0f" "0,*")
11242 (set_attr "length_immediate" "0,*")
11243 (set_attr "modrm" "0,1")
11244 (set_attr "mode" "SI")])
11246 (define_insn "*ashrsi3_31_zext"
11247 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11248 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11249 (match_operand:SI 2 "const_int_operand" "i,i"))))
11250 (clobber (reg:CC FLAGS_REG))]
11251 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11252 && INTVAL (operands[2]) == 31
11253 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11256 sar{l}\t{%2, %k0|%k0, %2}"
11257 [(set_attr "type" "imovx,ishift")
11258 (set_attr "prefix_0f" "0,*")
11259 (set_attr "length_immediate" "0,*")
11260 (set_attr "modrm" "0,1")
11261 (set_attr "mode" "SI")])
11263 (define_expand "ashrsi3"
11264 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11265 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11266 (match_operand:QI 2 "nonmemory_operand" "")))
11267 (clobber (reg:CC FLAGS_REG))]
11269 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11271 (define_insn "*ashrsi3_1_one_bit"
11272 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11273 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11274 (match_operand:QI 2 "const1_operand" "")))
11275 (clobber (reg:CC FLAGS_REG))]
11276 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11277 && (TARGET_SHIFT1 || optimize_size)"
11279 [(set_attr "type" "ishift")
11280 (set (attr "length")
11281 (if_then_else (match_operand:SI 0 "register_operand" "")
11283 (const_string "*")))])
11285 (define_insn "*ashrsi3_1_one_bit_zext"
11286 [(set (match_operand:DI 0 "register_operand" "=r")
11287 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11288 (match_operand:QI 2 "const1_operand" ""))))
11289 (clobber (reg:CC FLAGS_REG))]
11290 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11291 && (TARGET_SHIFT1 || optimize_size)"
11293 [(set_attr "type" "ishift")
11294 (set_attr "length" "2")])
11296 (define_insn "*ashrsi3_1"
11297 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11298 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11299 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11300 (clobber (reg:CC FLAGS_REG))]
11301 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11303 sar{l}\t{%2, %0|%0, %2}
11304 sar{l}\t{%b2, %0|%0, %b2}"
11305 [(set_attr "type" "ishift")
11306 (set_attr "mode" "SI")])
11308 (define_insn "*ashrsi3_1_zext"
11309 [(set (match_operand:DI 0 "register_operand" "=r,r")
11310 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11311 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11312 (clobber (reg:CC FLAGS_REG))]
11313 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11315 sar{l}\t{%2, %k0|%k0, %2}
11316 sar{l}\t{%b2, %k0|%k0, %b2}"
11317 [(set_attr "type" "ishift")
11318 (set_attr "mode" "SI")])
11320 ;; This pattern can't accept a variable shift count, since shifts by
11321 ;; zero don't affect the flags. We assume that shifts by constant
11322 ;; zero are optimized away.
11323 (define_insn "*ashrsi3_one_bit_cmp"
11324 [(set (reg FLAGS_REG)
11326 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11327 (match_operand:QI 2 "const1_operand" ""))
11329 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11330 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11331 "ix86_match_ccmode (insn, CCGOCmode)
11332 && (TARGET_SHIFT1 || optimize_size)
11333 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11335 [(set_attr "type" "ishift")
11336 (set (attr "length")
11337 (if_then_else (match_operand:SI 0 "register_operand" "")
11339 (const_string "*")))])
11341 (define_insn "*ashrsi3_one_bit_cmp_zext"
11342 [(set (reg FLAGS_REG)
11344 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11345 (match_operand:QI 2 "const1_operand" ""))
11347 (set (match_operand:DI 0 "register_operand" "=r")
11348 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11349 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
11350 && (TARGET_SHIFT1 || optimize_size)
11351 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11353 [(set_attr "type" "ishift")
11354 (set_attr "length" "2")])
11356 ;; This pattern can't accept a variable shift count, since shifts by
11357 ;; zero don't affect the flags. We assume that shifts by constant
11358 ;; zero are optimized away.
11359 (define_insn "*ashrsi3_cmp"
11360 [(set (reg FLAGS_REG)
11362 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11363 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11365 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11366 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
11367 "ix86_match_ccmode (insn, CCGOCmode)
11368 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11369 "sar{l}\t{%2, %0|%0, %2}"
11370 [(set_attr "type" "ishift")
11371 (set_attr "mode" "SI")])
11373 (define_insn "*ashrsi3_cmp_zext"
11374 [(set (reg FLAGS_REG)
11376 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11377 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11379 (set (match_operand:DI 0 "register_operand" "=r")
11380 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
11381 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11382 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11383 "sar{l}\t{%2, %k0|%k0, %2}"
11384 [(set_attr "type" "ishift")
11385 (set_attr "mode" "SI")])
11387 (define_expand "ashrhi3"
11388 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11389 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11390 (match_operand:QI 2 "nonmemory_operand" "")))
11391 (clobber (reg:CC FLAGS_REG))]
11392 "TARGET_HIMODE_MATH"
11393 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
11395 (define_insn "*ashrhi3_1_one_bit"
11396 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11397 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11398 (match_operand:QI 2 "const1_operand" "")))
11399 (clobber (reg:CC FLAGS_REG))]
11400 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
11401 && (TARGET_SHIFT1 || optimize_size)"
11403 [(set_attr "type" "ishift")
11404 (set (attr "length")
11405 (if_then_else (match_operand 0 "register_operand" "")
11407 (const_string "*")))])
11409 (define_insn "*ashrhi3_1"
11410 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11411 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11412 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11413 (clobber (reg:CC FLAGS_REG))]
11414 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11416 sar{w}\t{%2, %0|%0, %2}
11417 sar{w}\t{%b2, %0|%0, %b2}"
11418 [(set_attr "type" "ishift")
11419 (set_attr "mode" "HI")])
11421 ;; This pattern can't accept a variable shift count, since shifts by
11422 ;; zero don't affect the flags. We assume that shifts by constant
11423 ;; zero are optimized away.
11424 (define_insn "*ashrhi3_one_bit_cmp"
11425 [(set (reg FLAGS_REG)
11427 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11428 (match_operand:QI 2 "const1_operand" ""))
11430 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11431 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11432 "ix86_match_ccmode (insn, CCGOCmode)
11433 && (TARGET_SHIFT1 || optimize_size)
11434 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11436 [(set_attr "type" "ishift")
11437 (set (attr "length")
11438 (if_then_else (match_operand 0 "register_operand" "")
11440 (const_string "*")))])
11442 ;; This pattern can't accept a variable shift count, since shifts by
11443 ;; zero don't affect the flags. We assume that shifts by constant
11444 ;; zero are optimized away.
11445 (define_insn "*ashrhi3_cmp"
11446 [(set (reg FLAGS_REG)
11448 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11449 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11451 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11452 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
11453 "ix86_match_ccmode (insn, CCGOCmode)
11454 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
11455 "sar{w}\t{%2, %0|%0, %2}"
11456 [(set_attr "type" "ishift")
11457 (set_attr "mode" "HI")])
11459 (define_expand "ashrqi3"
11460 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11461 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11462 (match_operand:QI 2 "nonmemory_operand" "")))
11463 (clobber (reg:CC FLAGS_REG))]
11464 "TARGET_QIMODE_MATH"
11465 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
11467 (define_insn "*ashrqi3_1_one_bit"
11468 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11469 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11470 (match_operand:QI 2 "const1_operand" "")))
11471 (clobber (reg:CC FLAGS_REG))]
11472 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11473 && (TARGET_SHIFT1 || optimize_size)"
11475 [(set_attr "type" "ishift")
11476 (set (attr "length")
11477 (if_then_else (match_operand 0 "register_operand" "")
11479 (const_string "*")))])
11481 (define_insn "*ashrqi3_1_one_bit_slp"
11482 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11483 (ashiftrt:QI (match_dup 0)
11484 (match_operand:QI 1 "const1_operand" "")))
11485 (clobber (reg:CC FLAGS_REG))]
11486 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
11487 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
11488 && (TARGET_SHIFT1 || optimize_size)"
11490 [(set_attr "type" "ishift1")
11491 (set (attr "length")
11492 (if_then_else (match_operand 0 "register_operand" "")
11494 (const_string "*")))])
11496 (define_insn "*ashrqi3_1"
11497 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11498 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11499 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11500 (clobber (reg:CC FLAGS_REG))]
11501 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11503 sar{b}\t{%2, %0|%0, %2}
11504 sar{b}\t{%b2, %0|%0, %b2}"
11505 [(set_attr "type" "ishift")
11506 (set_attr "mode" "QI")])
11508 (define_insn "*ashrqi3_1_slp"
11509 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11510 (ashiftrt:QI (match_dup 0)
11511 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11512 (clobber (reg:CC FLAGS_REG))]
11513 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11514 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11516 sar{b}\t{%1, %0|%0, %1}
11517 sar{b}\t{%b1, %0|%0, %b1}"
11518 [(set_attr "type" "ishift1")
11519 (set_attr "mode" "QI")])
11521 ;; This pattern can't accept a variable shift count, since shifts by
11522 ;; zero don't affect the flags. We assume that shifts by constant
11523 ;; zero are optimized away.
11524 (define_insn "*ashrqi3_one_bit_cmp"
11525 [(set (reg FLAGS_REG)
11527 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11528 (match_operand:QI 2 "const1_operand" "I"))
11530 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11531 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11532 "ix86_match_ccmode (insn, CCGOCmode)
11533 && (TARGET_SHIFT1 || optimize_size)
11534 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11536 [(set_attr "type" "ishift")
11537 (set (attr "length")
11538 (if_then_else (match_operand 0 "register_operand" "")
11540 (const_string "*")))])
11542 ;; This pattern can't accept a variable shift count, since shifts by
11543 ;; zero don't affect the flags. We assume that shifts by constant
11544 ;; zero are optimized away.
11545 (define_insn "*ashrqi3_cmp"
11546 [(set (reg FLAGS_REG)
11548 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11549 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11551 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11552 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
11553 "ix86_match_ccmode (insn, CCGOCmode)
11554 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
11555 "sar{b}\t{%2, %0|%0, %2}"
11556 [(set_attr "type" "ishift")
11557 (set_attr "mode" "QI")])
11559 ;; Logical shift instructions
11561 ;; See comment above `ashldi3' about how this works.
11563 (define_expand "lshrti3"
11564 [(parallel [(set (match_operand:TI 0 "register_operand" "")
11565 (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
11566 (match_operand:QI 2 "nonmemory_operand" "")))
11567 (clobber (reg:CC FLAGS_REG))])]
11570 if (! immediate_operand (operands[2], QImode))
11572 emit_insn (gen_lshrti3_1 (operands[0], operands[1], operands[2]));
11575 ix86_expand_binary_operator (LSHIFTRT, TImode, operands);
11579 (define_insn "lshrti3_1"
11580 [(set (match_operand:TI 0 "register_operand" "=r")
11581 (lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
11582 (match_operand:QI 2 "register_operand" "c")))
11583 (clobber (match_scratch:DI 3 "=&r"))
11584 (clobber (reg:CC FLAGS_REG))]
11587 [(set_attr "type" "multi")])
11589 (define_insn "*lshrti3_2"
11590 [(set (match_operand:TI 0 "register_operand" "=r")
11591 (lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
11592 (match_operand:QI 2 "immediate_operand" "O")))
11593 (clobber (reg:CC FLAGS_REG))]
11596 [(set_attr "type" "multi")])
11599 [(set (match_operand:TI 0 "register_operand" "")
11600 (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
11601 (match_operand:QI 2 "register_operand" "")))
11602 (clobber (match_scratch:DI 3 ""))
11603 (clobber (reg:CC FLAGS_REG))]
11604 "TARGET_64BIT && reload_completed"
11606 "ix86_split_lshr (operands, operands[3], TImode); DONE;")
11609 [(set (match_operand:TI 0 "register_operand" "")
11610 (lshiftrt:TI (match_operand:TI 1 "register_operand" "")
11611 (match_operand:QI 2 "immediate_operand" "")))
11612 (clobber (reg:CC FLAGS_REG))]
11613 "TARGET_64BIT && reload_completed"
11615 "ix86_split_lshr (operands, NULL_RTX, TImode); DONE;")
11617 (define_expand "lshrdi3"
11618 [(set (match_operand:DI 0 "shiftdi_operand" "")
11619 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11620 (match_operand:QI 2 "nonmemory_operand" "")))]
11622 "ix86_expand_binary_operator (LSHIFTRT, DImode, operands); DONE;")
11624 (define_insn "*lshrdi3_1_one_bit_rex64"
11625 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11626 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11627 (match_operand:QI 2 "const1_operand" "")))
11628 (clobber (reg:CC FLAGS_REG))]
11629 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11630 && (TARGET_SHIFT1 || optimize_size)"
11632 [(set_attr "type" "ishift")
11633 (set (attr "length")
11634 (if_then_else (match_operand:DI 0 "register_operand" "")
11636 (const_string "*")))])
11638 (define_insn "*lshrdi3_1_rex64"
11639 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11640 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11641 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11642 (clobber (reg:CC FLAGS_REG))]
11643 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11645 shr{q}\t{%2, %0|%0, %2}
11646 shr{q}\t{%b2, %0|%0, %b2}"
11647 [(set_attr "type" "ishift")
11648 (set_attr "mode" "DI")])
11650 ;; This pattern can't accept a variable shift count, since shifts by
11651 ;; zero don't affect the flags. We assume that shifts by constant
11652 ;; zero are optimized away.
11653 (define_insn "*lshrdi3_cmp_one_bit_rex64"
11654 [(set (reg FLAGS_REG)
11656 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11657 (match_operand:QI 2 "const1_operand" ""))
11659 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11660 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11661 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11662 && (TARGET_SHIFT1 || optimize_size)
11663 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11665 [(set_attr "type" "ishift")
11666 (set (attr "length")
11667 (if_then_else (match_operand:DI 0 "register_operand" "")
11669 (const_string "*")))])
11671 ;; This pattern can't accept a variable shift count, since shifts by
11672 ;; zero don't affect the flags. We assume that shifts by constant
11673 ;; zero are optimized away.
11674 (define_insn "*lshrdi3_cmp_rex64"
11675 [(set (reg FLAGS_REG)
11677 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11678 (match_operand:QI 2 "const_int_operand" "e"))
11680 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11681 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
11682 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11683 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11684 "shr{q}\t{%2, %0|%0, %2}"
11685 [(set_attr "type" "ishift")
11686 (set_attr "mode" "DI")])
11688 (define_insn "*lshrdi3_1"
11689 [(set (match_operand:DI 0 "register_operand" "=r")
11690 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
11691 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11692 (clobber (reg:CC FLAGS_REG))]
11695 [(set_attr "type" "multi")])
11697 ;; By default we don't ask for a scratch register, because when DImode
11698 ;; values are manipulated, registers are already at a premium. But if
11699 ;; we have one handy, we won't turn it away.
11701 [(match_scratch:SI 3 "r")
11702 (parallel [(set (match_operand:DI 0 "register_operand" "")
11703 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11704 (match_operand:QI 2 "nonmemory_operand" "")))
11705 (clobber (reg:CC FLAGS_REG))])
11707 "!TARGET_64BIT && TARGET_CMOVE"
11709 "ix86_split_lshr (operands, operands[3], DImode); DONE;")
11712 [(set (match_operand:DI 0 "register_operand" "")
11713 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
11714 (match_operand:QI 2 "nonmemory_operand" "")))
11715 (clobber (reg:CC FLAGS_REG))]
11716 "!TARGET_64BIT && ((optimize > 0 && flag_peephole2)
11717 ? flow2_completed : reload_completed)"
11719 "ix86_split_lshr (operands, NULL_RTX, DImode); DONE;")
11721 (define_expand "lshrsi3"
11722 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11723 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11724 (match_operand:QI 2 "nonmemory_operand" "")))
11725 (clobber (reg:CC FLAGS_REG))]
11727 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
11729 (define_insn "*lshrsi3_1_one_bit"
11730 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11731 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11732 (match_operand:QI 2 "const1_operand" "")))
11733 (clobber (reg:CC FLAGS_REG))]
11734 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11735 && (TARGET_SHIFT1 || optimize_size)"
11737 [(set_attr "type" "ishift")
11738 (set (attr "length")
11739 (if_then_else (match_operand:SI 0 "register_operand" "")
11741 (const_string "*")))])
11743 (define_insn "*lshrsi3_1_one_bit_zext"
11744 [(set (match_operand:DI 0 "register_operand" "=r")
11745 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
11746 (match_operand:QI 2 "const1_operand" "")))
11747 (clobber (reg:CC FLAGS_REG))]
11748 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11749 && (TARGET_SHIFT1 || optimize_size)"
11751 [(set_attr "type" "ishift")
11752 (set_attr "length" "2")])
11754 (define_insn "*lshrsi3_1"
11755 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11756 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11757 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11758 (clobber (reg:CC FLAGS_REG))]
11759 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11761 shr{l}\t{%2, %0|%0, %2}
11762 shr{l}\t{%b2, %0|%0, %b2}"
11763 [(set_attr "type" "ishift")
11764 (set_attr "mode" "SI")])
11766 (define_insn "*lshrsi3_1_zext"
11767 [(set (match_operand:DI 0 "register_operand" "=r,r")
11769 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11770 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11771 (clobber (reg:CC FLAGS_REG))]
11772 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11774 shr{l}\t{%2, %k0|%k0, %2}
11775 shr{l}\t{%b2, %k0|%k0, %b2}"
11776 [(set_attr "type" "ishift")
11777 (set_attr "mode" "SI")])
11779 ;; This pattern can't accept a variable shift count, since shifts by
11780 ;; zero don't affect the flags. We assume that shifts by constant
11781 ;; zero are optimized away.
11782 (define_insn "*lshrsi3_one_bit_cmp"
11783 [(set (reg FLAGS_REG)
11785 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11786 (match_operand:QI 2 "const1_operand" ""))
11788 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11789 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11790 "ix86_match_ccmode (insn, CCGOCmode)
11791 && (TARGET_SHIFT1 || optimize_size)
11792 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11794 [(set_attr "type" "ishift")
11795 (set (attr "length")
11796 (if_then_else (match_operand:SI 0 "register_operand" "")
11798 (const_string "*")))])
11800 (define_insn "*lshrsi3_cmp_one_bit_zext"
11801 [(set (reg FLAGS_REG)
11803 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11804 (match_operand:QI 2 "const1_operand" ""))
11806 (set (match_operand:DI 0 "register_operand" "=r")
11807 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11808 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11809 && (TARGET_SHIFT1 || optimize_size)
11810 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11812 [(set_attr "type" "ishift")
11813 (set_attr "length" "2")])
11815 ;; This pattern can't accept a variable shift count, since shifts by
11816 ;; zero don't affect the flags. We assume that shifts by constant
11817 ;; zero are optimized away.
11818 (define_insn "*lshrsi3_cmp"
11819 [(set (reg FLAGS_REG)
11821 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11822 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11824 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11825 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
11826 "ix86_match_ccmode (insn, CCGOCmode)
11827 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11828 "shr{l}\t{%2, %0|%0, %2}"
11829 [(set_attr "type" "ishift")
11830 (set_attr "mode" "SI")])
11832 (define_insn "*lshrsi3_cmp_zext"
11833 [(set (reg FLAGS_REG)
11835 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
11836 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11838 (set (match_operand:DI 0 "register_operand" "=r")
11839 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
11840 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11841 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11842 "shr{l}\t{%2, %k0|%k0, %2}"
11843 [(set_attr "type" "ishift")
11844 (set_attr "mode" "SI")])
11846 (define_expand "lshrhi3"
11847 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11848 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
11849 (match_operand:QI 2 "nonmemory_operand" "")))
11850 (clobber (reg:CC FLAGS_REG))]
11851 "TARGET_HIMODE_MATH"
11852 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
11854 (define_insn "*lshrhi3_1_one_bit"
11855 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11856 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11857 (match_operand:QI 2 "const1_operand" "")))
11858 (clobber (reg:CC FLAGS_REG))]
11859 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
11860 && (TARGET_SHIFT1 || optimize_size)"
11862 [(set_attr "type" "ishift")
11863 (set (attr "length")
11864 (if_then_else (match_operand 0 "register_operand" "")
11866 (const_string "*")))])
11868 (define_insn "*lshrhi3_1"
11869 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
11870 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
11871 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11872 (clobber (reg:CC FLAGS_REG))]
11873 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11875 shr{w}\t{%2, %0|%0, %2}
11876 shr{w}\t{%b2, %0|%0, %b2}"
11877 [(set_attr "type" "ishift")
11878 (set_attr "mode" "HI")])
11880 ;; This pattern can't accept a variable shift count, since shifts by
11881 ;; zero don't affect the flags. We assume that shifts by constant
11882 ;; zero are optimized away.
11883 (define_insn "*lshrhi3_one_bit_cmp"
11884 [(set (reg FLAGS_REG)
11886 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11887 (match_operand:QI 2 "const1_operand" ""))
11889 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11890 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11891 "ix86_match_ccmode (insn, CCGOCmode)
11892 && (TARGET_SHIFT1 || optimize_size)
11893 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11895 [(set_attr "type" "ishift")
11896 (set (attr "length")
11897 (if_then_else (match_operand:SI 0 "register_operand" "")
11899 (const_string "*")))])
11901 ;; This pattern can't accept a variable shift count, since shifts by
11902 ;; zero don't affect the flags. We assume that shifts by constant
11903 ;; zero are optimized away.
11904 (define_insn "*lshrhi3_cmp"
11905 [(set (reg FLAGS_REG)
11907 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11908 (match_operand:QI 2 "const_1_to_31_operand" "I"))
11910 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11911 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
11912 "ix86_match_ccmode (insn, CCGOCmode)
11913 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
11914 "shr{w}\t{%2, %0|%0, %2}"
11915 [(set_attr "type" "ishift")
11916 (set_attr "mode" "HI")])
11918 (define_expand "lshrqi3"
11919 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11920 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
11921 (match_operand:QI 2 "nonmemory_operand" "")))
11922 (clobber (reg:CC FLAGS_REG))]
11923 "TARGET_QIMODE_MATH"
11924 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
11926 (define_insn "*lshrqi3_1_one_bit"
11927 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11928 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11929 (match_operand:QI 2 "const1_operand" "")))
11930 (clobber (reg:CC FLAGS_REG))]
11931 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
11932 && (TARGET_SHIFT1 || optimize_size)"
11934 [(set_attr "type" "ishift")
11935 (set (attr "length")
11936 (if_then_else (match_operand 0 "register_operand" "")
11938 (const_string "*")))])
11940 (define_insn "*lshrqi3_1_one_bit_slp"
11941 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
11942 (lshiftrt:QI (match_dup 0)
11943 (match_operand:QI 1 "const1_operand" "")))
11944 (clobber (reg:CC FLAGS_REG))]
11945 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11946 && (TARGET_SHIFT1 || optimize_size)"
11948 [(set_attr "type" "ishift1")
11949 (set (attr "length")
11950 (if_then_else (match_operand 0 "register_operand" "")
11952 (const_string "*")))])
11954 (define_insn "*lshrqi3_1"
11955 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
11956 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11957 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11958 (clobber (reg:CC FLAGS_REG))]
11959 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11961 shr{b}\t{%2, %0|%0, %2}
11962 shr{b}\t{%b2, %0|%0, %b2}"
11963 [(set_attr "type" "ishift")
11964 (set_attr "mode" "QI")])
11966 (define_insn "*lshrqi3_1_slp"
11967 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
11968 (lshiftrt:QI (match_dup 0)
11969 (match_operand:QI 1 "nonmemory_operand" "I,c")))
11970 (clobber (reg:CC FLAGS_REG))]
11971 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
11972 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
11974 shr{b}\t{%1, %0|%0, %1}
11975 shr{b}\t{%b1, %0|%0, %b1}"
11976 [(set_attr "type" "ishift1")
11977 (set_attr "mode" "QI")])
11979 ;; This pattern can't accept a variable shift count, since shifts by
11980 ;; zero don't affect the flags. We assume that shifts by constant
11981 ;; zero are optimized away.
11982 (define_insn "*lshrqi2_one_bit_cmp"
11983 [(set (reg FLAGS_REG)
11985 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11986 (match_operand:QI 2 "const1_operand" ""))
11988 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11989 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
11990 "ix86_match_ccmode (insn, CCGOCmode)
11991 && (TARGET_SHIFT1 || optimize_size)
11992 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
11994 [(set_attr "type" "ishift")
11995 (set (attr "length")
11996 (if_then_else (match_operand:SI 0 "register_operand" "")
11998 (const_string "*")))])
12000 ;; This pattern can't accept a variable shift count, since shifts by
12001 ;; zero don't affect the flags. We assume that shifts by constant
12002 ;; zero are optimized away.
12003 (define_insn "*lshrqi2_cmp"
12004 [(set (reg FLAGS_REG)
12006 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12007 (match_operand:QI 2 "const_1_to_31_operand" "I"))
12009 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12010 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12011 "ix86_match_ccmode (insn, CCGOCmode)
12012 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12013 "shr{b}\t{%2, %0|%0, %2}"
12014 [(set_attr "type" "ishift")
12015 (set_attr "mode" "QI")])
12017 ;; Rotate instructions
12019 (define_expand "rotldi3"
12020 [(set (match_operand:DI 0 "shiftdi_operand" "")
12021 (rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
12022 (match_operand:QI 2 "nonmemory_operand" "")))
12023 (clobber (reg:CC FLAGS_REG))]
12028 ix86_expand_binary_operator (ROTATE, DImode, operands);
12031 if (!const_1_to_31_operand (operands[2], VOIDmode))
12033 emit_insn (gen_ix86_rotldi3 (operands[0], operands[1], operands[2]));
12037 ;; Implement rotation using two double-precision shift instructions
12038 ;; and a scratch register.
12039 (define_insn_and_split "ix86_rotldi3"
12040 [(set (match_operand:DI 0 "register_operand" "=r")
12041 (rotate:DI (match_operand:DI 1 "register_operand" "0")
12042 (match_operand:QI 2 "const_1_to_31_operand" "I")))
12043 (clobber (reg:CC FLAGS_REG))
12044 (clobber (match_scratch:SI 3 "=&r"))]
12047 "&& reload_completed"
12048 [(set (match_dup 3) (match_dup 4))
12050 [(set (match_dup 4)
12051 (ior:SI (ashift:SI (match_dup 4) (match_dup 2))
12052 (lshiftrt:SI (match_dup 5)
12053 (minus:QI (const_int 32) (match_dup 2)))))
12054 (clobber (reg:CC FLAGS_REG))])
12056 [(set (match_dup 5)
12057 (ior:SI (ashift:SI (match_dup 5) (match_dup 2))
12058 (lshiftrt:SI (match_dup 3)
12059 (minus:QI (const_int 32) (match_dup 2)))))
12060 (clobber (reg:CC FLAGS_REG))])]
12061 "split_di (operands, 1, operands + 4, operands + 5);")
12063 (define_insn "*rotlsi3_1_one_bit_rex64"
12064 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12065 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12066 (match_operand:QI 2 "const1_operand" "")))
12067 (clobber (reg:CC FLAGS_REG))]
12068 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12069 && (TARGET_SHIFT1 || optimize_size)"
12071 [(set_attr "type" "rotate")
12072 (set (attr "length")
12073 (if_then_else (match_operand:DI 0 "register_operand" "")
12075 (const_string "*")))])
12077 (define_insn "*rotldi3_1_rex64"
12078 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12079 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12080 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12081 (clobber (reg:CC FLAGS_REG))]
12082 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12084 rol{q}\t{%2, %0|%0, %2}
12085 rol{q}\t{%b2, %0|%0, %b2}"
12086 [(set_attr "type" "rotate")
12087 (set_attr "mode" "DI")])
12089 (define_expand "rotlsi3"
12090 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12091 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12092 (match_operand:QI 2 "nonmemory_operand" "")))
12093 (clobber (reg:CC FLAGS_REG))]
12095 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12097 (define_insn "*rotlsi3_1_one_bit"
12098 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12099 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12100 (match_operand:QI 2 "const1_operand" "")))
12101 (clobber (reg:CC FLAGS_REG))]
12102 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12103 && (TARGET_SHIFT1 || optimize_size)"
12105 [(set_attr "type" "rotate")
12106 (set (attr "length")
12107 (if_then_else (match_operand:SI 0 "register_operand" "")
12109 (const_string "*")))])
12111 (define_insn "*rotlsi3_1_one_bit_zext"
12112 [(set (match_operand:DI 0 "register_operand" "=r")
12114 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12115 (match_operand:QI 2 "const1_operand" ""))))
12116 (clobber (reg:CC FLAGS_REG))]
12117 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12118 && (TARGET_SHIFT1 || optimize_size)"
12120 [(set_attr "type" "rotate")
12121 (set_attr "length" "2")])
12123 (define_insn "*rotlsi3_1"
12124 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12125 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12126 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12127 (clobber (reg:CC FLAGS_REG))]
12128 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12130 rol{l}\t{%2, %0|%0, %2}
12131 rol{l}\t{%b2, %0|%0, %b2}"
12132 [(set_attr "type" "rotate")
12133 (set_attr "mode" "SI")])
12135 (define_insn "*rotlsi3_1_zext"
12136 [(set (match_operand:DI 0 "register_operand" "=r,r")
12138 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12139 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12140 (clobber (reg:CC FLAGS_REG))]
12141 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12143 rol{l}\t{%2, %k0|%k0, %2}
12144 rol{l}\t{%b2, %k0|%k0, %b2}"
12145 [(set_attr "type" "rotate")
12146 (set_attr "mode" "SI")])
12148 (define_expand "rotlhi3"
12149 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12150 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12151 (match_operand:QI 2 "nonmemory_operand" "")))
12152 (clobber (reg:CC FLAGS_REG))]
12153 "TARGET_HIMODE_MATH"
12154 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12156 (define_insn "*rotlhi3_1_one_bit"
12157 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12158 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12159 (match_operand:QI 2 "const1_operand" "")))
12160 (clobber (reg:CC FLAGS_REG))]
12161 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12162 && (TARGET_SHIFT1 || optimize_size)"
12164 [(set_attr "type" "rotate")
12165 (set (attr "length")
12166 (if_then_else (match_operand 0 "register_operand" "")
12168 (const_string "*")))])
12170 (define_insn "*rotlhi3_1"
12171 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12172 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12173 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12174 (clobber (reg:CC FLAGS_REG))]
12175 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12177 rol{w}\t{%2, %0|%0, %2}
12178 rol{w}\t{%b2, %0|%0, %b2}"
12179 [(set_attr "type" "rotate")
12180 (set_attr "mode" "HI")])
12182 (define_expand "rotlqi3"
12183 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12184 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12185 (match_operand:QI 2 "nonmemory_operand" "")))
12186 (clobber (reg:CC FLAGS_REG))]
12187 "TARGET_QIMODE_MATH"
12188 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12190 (define_insn "*rotlqi3_1_one_bit_slp"
12191 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12192 (rotate:QI (match_dup 0)
12193 (match_operand:QI 1 "const1_operand" "")))
12194 (clobber (reg:CC FLAGS_REG))]
12195 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12196 && (TARGET_SHIFT1 || optimize_size)"
12198 [(set_attr "type" "rotate1")
12199 (set (attr "length")
12200 (if_then_else (match_operand 0 "register_operand" "")
12202 (const_string "*")))])
12204 (define_insn "*rotlqi3_1_one_bit"
12205 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12206 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12207 (match_operand:QI 2 "const1_operand" "")))
12208 (clobber (reg:CC FLAGS_REG))]
12209 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12210 && (TARGET_SHIFT1 || optimize_size)"
12212 [(set_attr "type" "rotate")
12213 (set (attr "length")
12214 (if_then_else (match_operand 0 "register_operand" "")
12216 (const_string "*")))])
12218 (define_insn "*rotlqi3_1_slp"
12219 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12220 (rotate:QI (match_dup 0)
12221 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12222 (clobber (reg:CC FLAGS_REG))]
12223 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12224 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12226 rol{b}\t{%1, %0|%0, %1}
12227 rol{b}\t{%b1, %0|%0, %b1}"
12228 [(set_attr "type" "rotate1")
12229 (set_attr "mode" "QI")])
12231 (define_insn "*rotlqi3_1"
12232 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12233 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12234 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12235 (clobber (reg:CC FLAGS_REG))]
12236 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12238 rol{b}\t{%2, %0|%0, %2}
12239 rol{b}\t{%b2, %0|%0, %b2}"
12240 [(set_attr "type" "rotate")
12241 (set_attr "mode" "QI")])
12243 (define_expand "rotrdi3"
12244 [(set (match_operand:DI 0 "shiftdi_operand" "")
12245 (rotate:DI (match_operand:DI 1 "shiftdi_operand" "")
12246 (match_operand:QI 2 "nonmemory_operand" "")))
12247 (clobber (reg:CC FLAGS_REG))]
12252 ix86_expand_binary_operator (ROTATERT, DImode, operands);
12255 if (!const_1_to_31_operand (operands[2], VOIDmode))
12257 emit_insn (gen_ix86_rotrdi3 (operands[0], operands[1], operands[2]));
12261 ;; Implement rotation using two double-precision shift instructions
12262 ;; and a scratch register.
12263 (define_insn_and_split "ix86_rotrdi3"
12264 [(set (match_operand:DI 0 "register_operand" "=r")
12265 (rotatert:DI (match_operand:DI 1 "register_operand" "0")
12266 (match_operand:QI 2 "const_1_to_31_operand" "I")))
12267 (clobber (reg:CC FLAGS_REG))
12268 (clobber (match_scratch:SI 3 "=&r"))]
12271 "&& reload_completed"
12272 [(set (match_dup 3) (match_dup 4))
12274 [(set (match_dup 4)
12275 (ior:SI (ashiftrt:SI (match_dup 4) (match_dup 2))
12276 (ashift:SI (match_dup 5)
12277 (minus:QI (const_int 32) (match_dup 2)))))
12278 (clobber (reg:CC FLAGS_REG))])
12280 [(set (match_dup 5)
12281 (ior:SI (ashiftrt:SI (match_dup 5) (match_dup 2))
12282 (ashift:SI (match_dup 3)
12283 (minus:QI (const_int 32) (match_dup 2)))))
12284 (clobber (reg:CC FLAGS_REG))])]
12285 "split_di (operands, 1, operands + 4, operands + 5);")
12287 (define_insn "*rotrdi3_1_one_bit_rex64"
12288 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12289 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12290 (match_operand:QI 2 "const1_operand" "")))
12291 (clobber (reg:CC FLAGS_REG))]
12292 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12293 && (TARGET_SHIFT1 || optimize_size)"
12295 [(set_attr "type" "rotate")
12296 (set (attr "length")
12297 (if_then_else (match_operand:DI 0 "register_operand" "")
12299 (const_string "*")))])
12301 (define_insn "*rotrdi3_1_rex64"
12302 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12303 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12304 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12305 (clobber (reg:CC FLAGS_REG))]
12306 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12308 ror{q}\t{%2, %0|%0, %2}
12309 ror{q}\t{%b2, %0|%0, %b2}"
12310 [(set_attr "type" "rotate")
12311 (set_attr "mode" "DI")])
12313 (define_expand "rotrsi3"
12314 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12315 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12316 (match_operand:QI 2 "nonmemory_operand" "")))
12317 (clobber (reg:CC FLAGS_REG))]
12319 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12321 (define_insn "*rotrsi3_1_one_bit"
12322 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12323 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12324 (match_operand:QI 2 "const1_operand" "")))
12325 (clobber (reg:CC FLAGS_REG))]
12326 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12327 && (TARGET_SHIFT1 || optimize_size)"
12329 [(set_attr "type" "rotate")
12330 (set (attr "length")
12331 (if_then_else (match_operand:SI 0 "register_operand" "")
12333 (const_string "*")))])
12335 (define_insn "*rotrsi3_1_one_bit_zext"
12336 [(set (match_operand:DI 0 "register_operand" "=r")
12338 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12339 (match_operand:QI 2 "const1_operand" ""))))
12340 (clobber (reg:CC FLAGS_REG))]
12341 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12342 && (TARGET_SHIFT1 || optimize_size)"
12344 [(set_attr "type" "rotate")
12345 (set (attr "length")
12346 (if_then_else (match_operand:SI 0 "register_operand" "")
12348 (const_string "*")))])
12350 (define_insn "*rotrsi3_1"
12351 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12352 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12353 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12354 (clobber (reg:CC FLAGS_REG))]
12355 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12357 ror{l}\t{%2, %0|%0, %2}
12358 ror{l}\t{%b2, %0|%0, %b2}"
12359 [(set_attr "type" "rotate")
12360 (set_attr "mode" "SI")])
12362 (define_insn "*rotrsi3_1_zext"
12363 [(set (match_operand:DI 0 "register_operand" "=r,r")
12365 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12366 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12367 (clobber (reg:CC FLAGS_REG))]
12368 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12370 ror{l}\t{%2, %k0|%k0, %2}
12371 ror{l}\t{%b2, %k0|%k0, %b2}"
12372 [(set_attr "type" "rotate")
12373 (set_attr "mode" "SI")])
12375 (define_expand "rotrhi3"
12376 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12377 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12378 (match_operand:QI 2 "nonmemory_operand" "")))
12379 (clobber (reg:CC FLAGS_REG))]
12380 "TARGET_HIMODE_MATH"
12381 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12383 (define_insn "*rotrhi3_one_bit"
12384 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12385 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12386 (match_operand:QI 2 "const1_operand" "")))
12387 (clobber (reg:CC FLAGS_REG))]
12388 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12389 && (TARGET_SHIFT1 || optimize_size)"
12391 [(set_attr "type" "rotate")
12392 (set (attr "length")
12393 (if_then_else (match_operand 0 "register_operand" "")
12395 (const_string "*")))])
12397 (define_insn "*rotrhi3"
12398 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12399 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12400 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12401 (clobber (reg:CC FLAGS_REG))]
12402 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12404 ror{w}\t{%2, %0|%0, %2}
12405 ror{w}\t{%b2, %0|%0, %b2}"
12406 [(set_attr "type" "rotate")
12407 (set_attr "mode" "HI")])
12409 (define_expand "rotrqi3"
12410 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12411 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12412 (match_operand:QI 2 "nonmemory_operand" "")))
12413 (clobber (reg:CC FLAGS_REG))]
12414 "TARGET_QIMODE_MATH"
12415 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12417 (define_insn "*rotrqi3_1_one_bit"
12418 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12419 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12420 (match_operand:QI 2 "const1_operand" "")))
12421 (clobber (reg:CC FLAGS_REG))]
12422 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12423 && (TARGET_SHIFT1 || optimize_size)"
12425 [(set_attr "type" "rotate")
12426 (set (attr "length")
12427 (if_then_else (match_operand 0 "register_operand" "")
12429 (const_string "*")))])
12431 (define_insn "*rotrqi3_1_one_bit_slp"
12432 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12433 (rotatert:QI (match_dup 0)
12434 (match_operand:QI 1 "const1_operand" "")))
12435 (clobber (reg:CC FLAGS_REG))]
12436 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12437 && (TARGET_SHIFT1 || optimize_size)"
12439 [(set_attr "type" "rotate1")
12440 (set (attr "length")
12441 (if_then_else (match_operand 0 "register_operand" "")
12443 (const_string "*")))])
12445 (define_insn "*rotrqi3_1"
12446 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12447 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12448 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12449 (clobber (reg:CC FLAGS_REG))]
12450 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
12452 ror{b}\t{%2, %0|%0, %2}
12453 ror{b}\t{%b2, %0|%0, %b2}"
12454 [(set_attr "type" "rotate")
12455 (set_attr "mode" "QI")])
12457 (define_insn "*rotrqi3_1_slp"
12458 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12459 (rotatert:QI (match_dup 0)
12460 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12461 (clobber (reg:CC FLAGS_REG))]
12462 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12463 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12465 ror{b}\t{%1, %0|%0, %1}
12466 ror{b}\t{%b1, %0|%0, %b1}"
12467 [(set_attr "type" "rotate1")
12468 (set_attr "mode" "QI")])
12470 ;; Bit set / bit test instructions
12472 (define_expand "extv"
12473 [(set (match_operand:SI 0 "register_operand" "")
12474 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12475 (match_operand:SI 2 "immediate_operand" "")
12476 (match_operand:SI 3 "immediate_operand" "")))]
12479 /* Handle extractions from %ah et al. */
12480 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12483 /* From mips.md: extract_bit_field doesn't verify that our source
12484 matches the predicate, so check it again here. */
12485 if (! ext_register_operand (operands[1], VOIDmode))
12489 (define_expand "extzv"
12490 [(set (match_operand:SI 0 "register_operand" "")
12491 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
12492 (match_operand:SI 2 "immediate_operand" "")
12493 (match_operand:SI 3 "immediate_operand" "")))]
12496 /* Handle extractions from %ah et al. */
12497 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
12500 /* From mips.md: extract_bit_field doesn't verify that our source
12501 matches the predicate, so check it again here. */
12502 if (! ext_register_operand (operands[1], VOIDmode))
12506 (define_expand "insv"
12507 [(set (zero_extract (match_operand 0 "ext_register_operand" "")
12508 (match_operand 1 "immediate_operand" "")
12509 (match_operand 2 "immediate_operand" ""))
12510 (match_operand 3 "register_operand" ""))]
12513 /* Handle extractions from %ah et al. */
12514 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
12517 /* From mips.md: insert_bit_field doesn't verify that our source
12518 matches the predicate, so check it again here. */
12519 if (! ext_register_operand (operands[0], VOIDmode))
12523 emit_insn (gen_movdi_insv_1_rex64 (operands[0], operands[3]));
12525 emit_insn (gen_movsi_insv_1 (operands[0], operands[3]));
12530 ;; %%% bts, btr, btc, bt.
12531 ;; In general these instructions are *slow* when applied to memory,
12532 ;; since they enforce atomic operation. When applied to registers,
12533 ;; it depends on the cpu implementation. They're never faster than
12534 ;; the corresponding and/ior/xor operations, so with 32-bit there's
12535 ;; no point. But in 64-bit, we can't hold the relevant immediates
12536 ;; within the instruction itself, so operating on bits in the high
12537 ;; 32-bits of a register becomes easier.
12539 ;; These are slow on Nocona, but fast on Athlon64. We do require the use
12540 ;; of btrq and btcq for corner cases of post-reload expansion of absdf and
12541 ;; negdf respectively, so they can never be disabled entirely.
12543 (define_insn "*btsq"
12544 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
12546 (match_operand:DI 1 "const_0_to_63_operand" ""))
12548 (clobber (reg:CC FLAGS_REG))]
12549 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12551 [(set_attr "type" "alu1")])
12553 (define_insn "*btrq"
12554 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
12556 (match_operand:DI 1 "const_0_to_63_operand" ""))
12558 (clobber (reg:CC FLAGS_REG))]
12559 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12561 [(set_attr "type" "alu1")])
12563 (define_insn "*btcq"
12564 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
12566 (match_operand:DI 1 "const_0_to_63_operand" ""))
12567 (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
12568 (clobber (reg:CC FLAGS_REG))]
12569 "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
12571 [(set_attr "type" "alu1")])
12573 ;; Allow Nocona to avoid these instructions if a register is available.
12576 [(match_scratch:DI 2 "r")
12577 (parallel [(set (zero_extract:DI
12578 (match_operand:DI 0 "register_operand" "")
12580 (match_operand:DI 1 "const_0_to_63_operand" ""))
12582 (clobber (reg:CC FLAGS_REG))])]
12583 "TARGET_64BIT && !TARGET_USE_BT"
12586 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12589 if (HOST_BITS_PER_WIDE_INT >= 64)
12590 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12591 else if (i < HOST_BITS_PER_WIDE_INT)
12592 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12594 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12596 op1 = immed_double_const (lo, hi, DImode);
12599 emit_move_insn (operands[2], op1);
12603 emit_insn (gen_iordi3 (operands[0], operands[0], op1));
12608 [(match_scratch:DI 2 "r")
12609 (parallel [(set (zero_extract:DI
12610 (match_operand:DI 0 "register_operand" "")
12612 (match_operand:DI 1 "const_0_to_63_operand" ""))
12614 (clobber (reg:CC FLAGS_REG))])]
12615 "TARGET_64BIT && !TARGET_USE_BT"
12618 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12621 if (HOST_BITS_PER_WIDE_INT >= 64)
12622 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12623 else if (i < HOST_BITS_PER_WIDE_INT)
12624 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12626 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12628 op1 = immed_double_const (~lo, ~hi, DImode);
12631 emit_move_insn (operands[2], op1);
12635 emit_insn (gen_anddi3 (operands[0], operands[0], op1));
12640 [(match_scratch:DI 2 "r")
12641 (parallel [(set (zero_extract:DI
12642 (match_operand:DI 0 "register_operand" "")
12644 (match_operand:DI 1 "const_0_to_63_operand" ""))
12645 (not:DI (zero_extract:DI
12646 (match_dup 0) (const_int 1) (match_dup 1))))
12647 (clobber (reg:CC FLAGS_REG))])]
12648 "TARGET_64BIT && !TARGET_USE_BT"
12651 HOST_WIDE_INT i = INTVAL (operands[1]), hi, lo;
12654 if (HOST_BITS_PER_WIDE_INT >= 64)
12655 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12656 else if (i < HOST_BITS_PER_WIDE_INT)
12657 lo = (HOST_WIDE_INT)1 << i, hi = 0;
12659 lo = 0, hi = (HOST_WIDE_INT)1 << (i - HOST_BITS_PER_WIDE_INT);
12661 op1 = immed_double_const (lo, hi, DImode);
12664 emit_move_insn (operands[2], op1);
12668 emit_insn (gen_xordi3 (operands[0], operands[0], op1));
12672 ;; Store-flag instructions.
12674 ;; For all sCOND expanders, also expand the compare or test insn that
12675 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
12677 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
12678 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
12679 ;; way, which can later delete the movzx if only QImode is needed.
12681 (define_expand "seq"
12682 [(set (match_operand:QI 0 "register_operand" "")
12683 (eq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12685 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
12687 (define_expand "sne"
12688 [(set (match_operand:QI 0 "register_operand" "")
12689 (ne:QI (reg:CC FLAGS_REG) (const_int 0)))]
12691 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
12693 (define_expand "sgt"
12694 [(set (match_operand:QI 0 "register_operand" "")
12695 (gt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12697 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
12699 (define_expand "sgtu"
12700 [(set (match_operand:QI 0 "register_operand" "")
12701 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12703 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
12705 (define_expand "slt"
12706 [(set (match_operand:QI 0 "register_operand" "")
12707 (lt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12709 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
12711 (define_expand "sltu"
12712 [(set (match_operand:QI 0 "register_operand" "")
12713 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12715 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
12717 (define_expand "sge"
12718 [(set (match_operand:QI 0 "register_operand" "")
12719 (ge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12721 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
12723 (define_expand "sgeu"
12724 [(set (match_operand:QI 0 "register_operand" "")
12725 (geu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12727 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
12729 (define_expand "sle"
12730 [(set (match_operand:QI 0 "register_operand" "")
12731 (le:QI (reg:CC FLAGS_REG) (const_int 0)))]
12733 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
12735 (define_expand "sleu"
12736 [(set (match_operand:QI 0 "register_operand" "")
12737 (leu:QI (reg:CC FLAGS_REG) (const_int 0)))]
12739 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
12741 (define_expand "sunordered"
12742 [(set (match_operand:QI 0 "register_operand" "")
12743 (unordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12744 "TARGET_80387 || TARGET_SSE"
12745 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
12747 (define_expand "sordered"
12748 [(set (match_operand:QI 0 "register_operand" "")
12749 (ordered:QI (reg:CC FLAGS_REG) (const_int 0)))]
12751 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
12753 (define_expand "suneq"
12754 [(set (match_operand:QI 0 "register_operand" "")
12755 (uneq:QI (reg:CC FLAGS_REG) (const_int 0)))]
12756 "TARGET_80387 || TARGET_SSE"
12757 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
12759 (define_expand "sunge"
12760 [(set (match_operand:QI 0 "register_operand" "")
12761 (unge:QI (reg:CC FLAGS_REG) (const_int 0)))]
12762 "TARGET_80387 || TARGET_SSE"
12763 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
12765 (define_expand "sungt"
12766 [(set (match_operand:QI 0 "register_operand" "")
12767 (ungt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12768 "TARGET_80387 || TARGET_SSE"
12769 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
12771 (define_expand "sunle"
12772 [(set (match_operand:QI 0 "register_operand" "")
12773 (unle:QI (reg:CC FLAGS_REG) (const_int 0)))]
12774 "TARGET_80387 || TARGET_SSE"
12775 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
12777 (define_expand "sunlt"
12778 [(set (match_operand:QI 0 "register_operand" "")
12779 (unlt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12780 "TARGET_80387 || TARGET_SSE"
12781 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
12783 (define_expand "sltgt"
12784 [(set (match_operand:QI 0 "register_operand" "")
12785 (ltgt:QI (reg:CC FLAGS_REG) (const_int 0)))]
12786 "TARGET_80387 || TARGET_SSE"
12787 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
12789 (define_insn "*setcc_1"
12790 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12791 (match_operator:QI 1 "ix86_comparison_operator"
12792 [(reg FLAGS_REG) (const_int 0)]))]
12795 [(set_attr "type" "setcc")
12796 (set_attr "mode" "QI")])
12798 (define_insn "*setcc_2"
12799 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12800 (match_operator:QI 1 "ix86_comparison_operator"
12801 [(reg FLAGS_REG) (const_int 0)]))]
12804 [(set_attr "type" "setcc")
12805 (set_attr "mode" "QI")])
12807 ;; In general it is not safe to assume too much about CCmode registers,
12808 ;; so simplify-rtx stops when it sees a second one. Under certain
12809 ;; conditions this is safe on x86, so help combine not create
12816 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12817 (ne:QI (match_operator 1 "ix86_comparison_operator"
12818 [(reg FLAGS_REG) (const_int 0)])
12821 [(set (match_dup 0) (match_dup 1))]
12823 PUT_MODE (operands[1], QImode);
12827 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12828 (ne:QI (match_operator 1 "ix86_comparison_operator"
12829 [(reg FLAGS_REG) (const_int 0)])
12832 [(set (match_dup 0) (match_dup 1))]
12834 PUT_MODE (operands[1], QImode);
12838 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12839 (eq:QI (match_operator 1 "ix86_comparison_operator"
12840 [(reg FLAGS_REG) (const_int 0)])
12843 [(set (match_dup 0) (match_dup 1))]
12845 rtx new_op1 = copy_rtx (operands[1]);
12846 operands[1] = new_op1;
12847 PUT_MODE (new_op1, QImode);
12848 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12849 GET_MODE (XEXP (new_op1, 0))));
12851 /* Make sure that (a) the CCmode we have for the flags is strong
12852 enough for the reversed compare or (b) we have a valid FP compare. */
12853 if (! ix86_comparison_operator (new_op1, VOIDmode))
12858 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
12859 (eq:QI (match_operator 1 "ix86_comparison_operator"
12860 [(reg FLAGS_REG) (const_int 0)])
12863 [(set (match_dup 0) (match_dup 1))]
12865 rtx new_op1 = copy_rtx (operands[1]);
12866 operands[1] = new_op1;
12867 PUT_MODE (new_op1, QImode);
12868 PUT_CODE (new_op1, ix86_reverse_condition (GET_CODE (new_op1),
12869 GET_MODE (XEXP (new_op1, 0))));
12871 /* Make sure that (a) the CCmode we have for the flags is strong
12872 enough for the reversed compare or (b) we have a valid FP compare. */
12873 if (! ix86_comparison_operator (new_op1, VOIDmode))
12877 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
12878 ;; subsequent logical operations are used to imitate conditional moves.
12879 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
12882 (define_insn "*sse_setccsf"
12883 [(set (match_operand:SF 0 "register_operand" "=x")
12884 (match_operator:SF 1 "sse_comparison_operator"
12885 [(match_operand:SF 2 "register_operand" "0")
12886 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
12888 "cmp%D1ss\t{%3, %0|%0, %3}"
12889 [(set_attr "type" "ssecmp")
12890 (set_attr "mode" "SF")])
12892 (define_insn "*sse_setccdf"
12893 [(set (match_operand:DF 0 "register_operand" "=Y")
12894 (match_operator:DF 1 "sse_comparison_operator"
12895 [(match_operand:DF 2 "register_operand" "0")
12896 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
12898 "cmp%D1sd\t{%3, %0|%0, %3}"
12899 [(set_attr "type" "ssecmp")
12900 (set_attr "mode" "DF")])
12902 ;; Basic conditional jump instructions.
12903 ;; We ignore the overflow flag for signed branch instructions.
12905 ;; For all bCOND expanders, also expand the compare or test insn that
12906 ;; generates reg FLAGS_REG. Generate an equality comparison if `beq' or `bne'.
12908 (define_expand "beq"
12910 (if_then_else (match_dup 1)
12911 (label_ref (match_operand 0 "" ""))
12914 "ix86_expand_branch (EQ, operands[0]); DONE;")
12916 (define_expand "bne"
12918 (if_then_else (match_dup 1)
12919 (label_ref (match_operand 0 "" ""))
12922 "ix86_expand_branch (NE, operands[0]); DONE;")
12924 (define_expand "bgt"
12926 (if_then_else (match_dup 1)
12927 (label_ref (match_operand 0 "" ""))
12930 "ix86_expand_branch (GT, operands[0]); DONE;")
12932 (define_expand "bgtu"
12934 (if_then_else (match_dup 1)
12935 (label_ref (match_operand 0 "" ""))
12938 "ix86_expand_branch (GTU, operands[0]); DONE;")
12940 (define_expand "blt"
12942 (if_then_else (match_dup 1)
12943 (label_ref (match_operand 0 "" ""))
12946 "ix86_expand_branch (LT, operands[0]); DONE;")
12948 (define_expand "bltu"
12950 (if_then_else (match_dup 1)
12951 (label_ref (match_operand 0 "" ""))
12954 "ix86_expand_branch (LTU, operands[0]); DONE;")
12956 (define_expand "bge"
12958 (if_then_else (match_dup 1)
12959 (label_ref (match_operand 0 "" ""))
12962 "ix86_expand_branch (GE, operands[0]); DONE;")
12964 (define_expand "bgeu"
12966 (if_then_else (match_dup 1)
12967 (label_ref (match_operand 0 "" ""))
12970 "ix86_expand_branch (GEU, operands[0]); DONE;")
12972 (define_expand "ble"
12974 (if_then_else (match_dup 1)
12975 (label_ref (match_operand 0 "" ""))
12978 "ix86_expand_branch (LE, operands[0]); DONE;")
12980 (define_expand "bleu"
12982 (if_then_else (match_dup 1)
12983 (label_ref (match_operand 0 "" ""))
12986 "ix86_expand_branch (LEU, operands[0]); DONE;")
12988 (define_expand "bunordered"
12990 (if_then_else (match_dup 1)
12991 (label_ref (match_operand 0 "" ""))
12993 "TARGET_80387 || TARGET_SSE_MATH"
12994 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
12996 (define_expand "bordered"
12998 (if_then_else (match_dup 1)
12999 (label_ref (match_operand 0 "" ""))
13001 "TARGET_80387 || TARGET_SSE_MATH"
13002 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
13004 (define_expand "buneq"
13006 (if_then_else (match_dup 1)
13007 (label_ref (match_operand 0 "" ""))
13009 "TARGET_80387 || TARGET_SSE_MATH"
13010 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
13012 (define_expand "bunge"
13014 (if_then_else (match_dup 1)
13015 (label_ref (match_operand 0 "" ""))
13017 "TARGET_80387 || TARGET_SSE_MATH"
13018 "ix86_expand_branch (UNGE, operands[0]); DONE;")
13020 (define_expand "bungt"
13022 (if_then_else (match_dup 1)
13023 (label_ref (match_operand 0 "" ""))
13025 "TARGET_80387 || TARGET_SSE_MATH"
13026 "ix86_expand_branch (UNGT, operands[0]); DONE;")
13028 (define_expand "bunle"
13030 (if_then_else (match_dup 1)
13031 (label_ref (match_operand 0 "" ""))
13033 "TARGET_80387 || TARGET_SSE_MATH"
13034 "ix86_expand_branch (UNLE, operands[0]); DONE;")
13036 (define_expand "bunlt"
13038 (if_then_else (match_dup 1)
13039 (label_ref (match_operand 0 "" ""))
13041 "TARGET_80387 || TARGET_SSE_MATH"
13042 "ix86_expand_branch (UNLT, operands[0]); DONE;")
13044 (define_expand "bltgt"
13046 (if_then_else (match_dup 1)
13047 (label_ref (match_operand 0 "" ""))
13049 "TARGET_80387 || TARGET_SSE_MATH"
13050 "ix86_expand_branch (LTGT, operands[0]); DONE;")
13052 (define_insn "*jcc_1"
13054 (if_then_else (match_operator 1 "ix86_comparison_operator"
13055 [(reg FLAGS_REG) (const_int 0)])
13056 (label_ref (match_operand 0 "" ""))
13060 [(set_attr "type" "ibr")
13061 (set_attr "modrm" "0")
13062 (set (attr "length")
13063 (if_then_else (and (ge (minus (match_dup 0) (pc))
13065 (lt (minus (match_dup 0) (pc))
13070 (define_insn "*jcc_2"
13072 (if_then_else (match_operator 1 "ix86_comparison_operator"
13073 [(reg FLAGS_REG) (const_int 0)])
13075 (label_ref (match_operand 0 "" ""))))]
13078 [(set_attr "type" "ibr")
13079 (set_attr "modrm" "0")
13080 (set (attr "length")
13081 (if_then_else (and (ge (minus (match_dup 0) (pc))
13083 (lt (minus (match_dup 0) (pc))
13088 ;; In general it is not safe to assume too much about CCmode registers,
13089 ;; so simplify-rtx stops when it sees a second one. Under certain
13090 ;; conditions this is safe on x86, so help combine not create
13098 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
13099 [(reg FLAGS_REG) (const_int 0)])
13101 (label_ref (match_operand 1 "" ""))
13105 (if_then_else (match_dup 0)
13106 (label_ref (match_dup 1))
13109 PUT_MODE (operands[0], VOIDmode);
13114 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
13115 [(reg FLAGS_REG) (const_int 0)])
13117 (label_ref (match_operand 1 "" ""))
13121 (if_then_else (match_dup 0)
13122 (label_ref (match_dup 1))
13125 rtx new_op0 = copy_rtx (operands[0]);
13126 operands[0] = new_op0;
13127 PUT_MODE (new_op0, VOIDmode);
13128 PUT_CODE (new_op0, ix86_reverse_condition (GET_CODE (new_op0),
13129 GET_MODE (XEXP (new_op0, 0))));
13131 /* Make sure that (a) the CCmode we have for the flags is strong
13132 enough for the reversed compare or (b) we have a valid FP compare. */
13133 if (! ix86_comparison_operator (new_op0, VOIDmode))
13137 ;; Define combination compare-and-branch fp compare instructions to use
13138 ;; during early optimization. Splitting the operation apart early makes
13139 ;; for bad code when we want to reverse the operation.
13141 (define_insn "*fp_jcc_1_mixed"
13143 (if_then_else (match_operator 0 "comparison_operator"
13144 [(match_operand 1 "register_operand" "f#x,x#f")
13145 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13146 (label_ref (match_operand 3 "" ""))
13148 (clobber (reg:CCFP FPSR_REG))
13149 (clobber (reg:CCFP FLAGS_REG))]
13150 "TARGET_MIX_SSE_I387
13151 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13152 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13153 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13156 (define_insn "*fp_jcc_1_sse"
13158 (if_then_else (match_operator 0 "comparison_operator"
13159 [(match_operand 1 "register_operand" "x")
13160 (match_operand 2 "nonimmediate_operand" "xm")])
13161 (label_ref (match_operand 3 "" ""))
13163 (clobber (reg:CCFP FPSR_REG))
13164 (clobber (reg:CCFP FLAGS_REG))]
13166 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13167 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13168 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13171 (define_insn "*fp_jcc_1_387"
13173 (if_then_else (match_operator 0 "comparison_operator"
13174 [(match_operand 1 "register_operand" "f")
13175 (match_operand 2 "register_operand" "f")])
13176 (label_ref (match_operand 3 "" ""))
13178 (clobber (reg:CCFP FPSR_REG))
13179 (clobber (reg:CCFP FLAGS_REG))]
13180 "TARGET_CMOVE && TARGET_80387
13181 && FLOAT_MODE_P (GET_MODE (operands[1]))
13182 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13183 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13186 (define_insn "*fp_jcc_2_mixed"
13188 (if_then_else (match_operator 0 "comparison_operator"
13189 [(match_operand 1 "register_operand" "f#x,x#f")
13190 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13192 (label_ref (match_operand 3 "" ""))))
13193 (clobber (reg:CCFP FPSR_REG))
13194 (clobber (reg:CCFP FLAGS_REG))]
13195 "TARGET_MIX_SSE_I387
13196 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13197 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13198 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13201 (define_insn "*fp_jcc_2_sse"
13203 (if_then_else (match_operator 0 "comparison_operator"
13204 [(match_operand 1 "register_operand" "x")
13205 (match_operand 2 "nonimmediate_operand" "xm")])
13207 (label_ref (match_operand 3 "" ""))))
13208 (clobber (reg:CCFP FPSR_REG))
13209 (clobber (reg:CCFP FLAGS_REG))]
13211 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13212 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13213 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13216 (define_insn "*fp_jcc_2_387"
13218 (if_then_else (match_operator 0 "comparison_operator"
13219 [(match_operand 1 "register_operand" "f")
13220 (match_operand 2 "register_operand" "f")])
13222 (label_ref (match_operand 3 "" ""))))
13223 (clobber (reg:CCFP FPSR_REG))
13224 (clobber (reg:CCFP FLAGS_REG))]
13225 "TARGET_CMOVE && TARGET_80387
13226 && FLOAT_MODE_P (GET_MODE (operands[1]))
13227 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13228 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13231 (define_insn "*fp_jcc_3_387"
13233 (if_then_else (match_operator 0 "comparison_operator"
13234 [(match_operand 1 "register_operand" "f")
13235 (match_operand 2 "nonimmediate_operand" "fm")])
13236 (label_ref (match_operand 3 "" ""))
13238 (clobber (reg:CCFP FPSR_REG))
13239 (clobber (reg:CCFP FLAGS_REG))
13240 (clobber (match_scratch:HI 4 "=a"))]
13242 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13243 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13244 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13245 && SELECT_CC_MODE (GET_CODE (operands[0]),
13246 operands[1], operands[2]) == CCFPmode
13247 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13250 (define_insn "*fp_jcc_4_387"
13252 (if_then_else (match_operator 0 "comparison_operator"
13253 [(match_operand 1 "register_operand" "f")
13254 (match_operand 2 "nonimmediate_operand" "fm")])
13256 (label_ref (match_operand 3 "" ""))))
13257 (clobber (reg:CCFP FPSR_REG))
13258 (clobber (reg:CCFP FLAGS_REG))
13259 (clobber (match_scratch:HI 4 "=a"))]
13261 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13262 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13263 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13264 && SELECT_CC_MODE (GET_CODE (operands[0]),
13265 operands[1], operands[2]) == CCFPmode
13266 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13269 (define_insn "*fp_jcc_5_387"
13271 (if_then_else (match_operator 0 "comparison_operator"
13272 [(match_operand 1 "register_operand" "f")
13273 (match_operand 2 "register_operand" "f")])
13274 (label_ref (match_operand 3 "" ""))
13276 (clobber (reg:CCFP FPSR_REG))
13277 (clobber (reg:CCFP FLAGS_REG))
13278 (clobber (match_scratch:HI 4 "=a"))]
13280 && FLOAT_MODE_P (GET_MODE (operands[1]))
13281 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13282 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13285 (define_insn "*fp_jcc_6_387"
13287 (if_then_else (match_operator 0 "comparison_operator"
13288 [(match_operand 1 "register_operand" "f")
13289 (match_operand 2 "register_operand" "f")])
13291 (label_ref (match_operand 3 "" ""))))
13292 (clobber (reg:CCFP FPSR_REG))
13293 (clobber (reg:CCFP FLAGS_REG))
13294 (clobber (match_scratch:HI 4 "=a"))]
13296 && FLOAT_MODE_P (GET_MODE (operands[1]))
13297 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13298 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13301 (define_insn "*fp_jcc_7_387"
13303 (if_then_else (match_operator 0 "comparison_operator"
13304 [(match_operand 1 "register_operand" "f")
13305 (match_operand 2 "const0_operand" "X")])
13306 (label_ref (match_operand 3 "" ""))
13308 (clobber (reg:CCFP FPSR_REG))
13309 (clobber (reg:CCFP FLAGS_REG))
13310 (clobber (match_scratch:HI 4 "=a"))]
13312 && FLOAT_MODE_P (GET_MODE (operands[1]))
13313 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13314 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13315 && SELECT_CC_MODE (GET_CODE (operands[0]),
13316 operands[1], operands[2]) == CCFPmode
13317 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13320 ;; The order of operands in *fp_jcc_8_387 is forced by combine in
13321 ;; simplify_comparison () function. Float operator is treated as RTX_OBJ
13322 ;; with a precedence over other operators and is always put in the first
13323 ;; place. Swap condition and operands to match ficom instruction.
13325 (define_insn "*fp_jcc_8<mode>_387"
13327 (if_then_else (match_operator 0 "comparison_operator"
13328 [(match_operator 1 "float_operator"
13329 [(match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r")])
13330 (match_operand 3 "register_operand" "f,f")])
13331 (label_ref (match_operand 4 "" ""))
13333 (clobber (reg:CCFP FPSR_REG))
13334 (clobber (reg:CCFP FLAGS_REG))
13335 (clobber (match_scratch:HI 5 "=a,a"))]
13336 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
13337 && FLOAT_MODE_P (GET_MODE (operands[3]))
13338 && GET_MODE (operands[1]) == GET_MODE (operands[3])
13339 && !ix86_use_fcomi_compare (swap_condition (GET_CODE (operands[0])))
13340 && ix86_fp_compare_mode (swap_condition (GET_CODE (operands[0]))) == CCFPmode
13341 && ix86_fp_jump_nontrivial_p (swap_condition (GET_CODE (operands[0])))"
13346 (if_then_else (match_operator 0 "comparison_operator"
13347 [(match_operand 1 "register_operand" "")
13348 (match_operand 2 "nonimmediate_operand" "")])
13349 (match_operand 3 "" "")
13350 (match_operand 4 "" "")))
13351 (clobber (reg:CCFP FPSR_REG))
13352 (clobber (reg:CCFP FLAGS_REG))]
13356 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13357 operands[3], operands[4], NULL_RTX, NULL_RTX);
13363 (if_then_else (match_operator 0 "comparison_operator"
13364 [(match_operand 1 "register_operand" "")
13365 (match_operand 2 "general_operand" "")])
13366 (match_operand 3 "" "")
13367 (match_operand 4 "" "")))
13368 (clobber (reg:CCFP FPSR_REG))
13369 (clobber (reg:CCFP FLAGS_REG))
13370 (clobber (match_scratch:HI 5 "=a"))]
13374 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13375 operands[3], operands[4], operands[5], NULL_RTX);
13381 (if_then_else (match_operator 0 "comparison_operator"
13382 [(match_operator 1 "float_operator"
13383 [(match_operand:X87MODEI12 2 "memory_operand" "")])
13384 (match_operand 3 "register_operand" "")])
13385 (match_operand 4 "" "")
13386 (match_operand 5 "" "")))
13387 (clobber (reg:CCFP FPSR_REG))
13388 (clobber (reg:CCFP FLAGS_REG))
13389 (clobber (match_scratch:HI 6 "=a"))]
13393 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[2]);
13394 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
13395 operands[3], operands[7],
13396 operands[4], operands[5], operands[6], NULL_RTX);
13400 ;; %%% Kill this when reload knows how to do it.
13403 (if_then_else (match_operator 0 "comparison_operator"
13404 [(match_operator 1 "float_operator"
13405 [(match_operand:X87MODEI12 2 "register_operand" "")])
13406 (match_operand 3 "register_operand" "")])
13407 (match_operand 4 "" "")
13408 (match_operand 5 "" "")))
13409 (clobber (reg:CCFP FPSR_REG))
13410 (clobber (reg:CCFP FLAGS_REG))
13411 (clobber (match_scratch:HI 6 "=a"))]
13415 operands[7] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
13416 operands[7] = gen_rtx_FLOAT (GET_MODE (operands[1]), operands[7]);
13417 ix86_split_fp_branch (swap_condition (GET_CODE (operands[0])),
13418 operands[3], operands[7],
13419 operands[4], operands[5], operands[6], operands[2]);
13423 ;; Unconditional and other jump instructions
13425 (define_insn "jump"
13427 (label_ref (match_operand 0 "" "")))]
13430 [(set_attr "type" "ibr")
13431 (set (attr "length")
13432 (if_then_else (and (ge (minus (match_dup 0) (pc))
13434 (lt (minus (match_dup 0) (pc))
13438 (set_attr "modrm" "0")])
13440 (define_expand "indirect_jump"
13441 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13445 (define_insn "*indirect_jump"
13446 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13449 [(set_attr "type" "ibr")
13450 (set_attr "length_immediate" "0")])
13452 (define_insn "*indirect_jump_rtx64"
13453 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13456 [(set_attr "type" "ibr")
13457 (set_attr "length_immediate" "0")])
13459 (define_expand "tablejump"
13460 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13461 (use (label_ref (match_operand 1 "" "")))])]
13464 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13465 relative. Convert the relative address to an absolute address. */
13469 enum rtx_code code;
13475 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13477 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13481 op1 = pic_offset_table_rtx;
13486 op0 = pic_offset_table_rtx;
13490 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13495 (define_insn "*tablejump_1"
13496 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13497 (use (label_ref (match_operand 1 "" "")))]
13500 [(set_attr "type" "ibr")
13501 (set_attr "length_immediate" "0")])
13503 (define_insn "*tablejump_1_rtx64"
13504 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13505 (use (label_ref (match_operand 1 "" "")))]
13508 [(set_attr "type" "ibr")
13509 (set_attr "length_immediate" "0")])
13511 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13514 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
13515 (set (match_operand:QI 1 "register_operand" "")
13516 (match_operator:QI 2 "ix86_comparison_operator"
13517 [(reg FLAGS_REG) (const_int 0)]))
13518 (set (match_operand 3 "q_regs_operand" "")
13519 (zero_extend (match_dup 1)))]
13520 "(peep2_reg_dead_p (3, operands[1])
13521 || operands_match_p (operands[1], operands[3]))
13522 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13523 [(set (match_dup 4) (match_dup 0))
13524 (set (strict_low_part (match_dup 5))
13527 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
13528 operands[5] = gen_lowpart (QImode, operands[3]);
13529 ix86_expand_clear (operands[3]);
13532 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13535 [(set (reg FLAGS_REG) (match_operand 0 "" ""))
13536 (set (match_operand:QI 1 "register_operand" "")
13537 (match_operator:QI 2 "ix86_comparison_operator"
13538 [(reg FLAGS_REG) (const_int 0)]))
13539 (parallel [(set (match_operand 3 "q_regs_operand" "")
13540 (zero_extend (match_dup 1)))
13541 (clobber (reg:CC FLAGS_REG))])]
13542 "(peep2_reg_dead_p (3, operands[1])
13543 || operands_match_p (operands[1], operands[3]))
13544 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13545 [(set (match_dup 4) (match_dup 0))
13546 (set (strict_low_part (match_dup 5))
13549 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), FLAGS_REG);
13550 operands[5] = gen_lowpart (QImode, operands[3]);
13551 ix86_expand_clear (operands[3]);
13554 ;; Call instructions.
13556 ;; The predicates normally associated with named expanders are not properly
13557 ;; checked for calls. This is a bug in the generic code, but it isn't that
13558 ;; easy to fix. Ignore it for now and be prepared to fix things up.
13560 ;; Call subroutine returning no value.
13562 (define_expand "call_pop"
13563 [(parallel [(call (match_operand:QI 0 "" "")
13564 (match_operand:SI 1 "" ""))
13565 (set (reg:SI SP_REG)
13566 (plus:SI (reg:SI SP_REG)
13567 (match_operand:SI 3 "" "")))])]
13570 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
13574 (define_insn "*call_pop_0"
13575 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
13576 (match_operand:SI 1 "" ""))
13577 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13578 (match_operand:SI 2 "immediate_operand" "")))]
13581 if (SIBLING_CALL_P (insn))
13584 return "call\t%P0";
13586 [(set_attr "type" "call")])
13588 (define_insn "*call_pop_1"
13589 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13590 (match_operand:SI 1 "" ""))
13591 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
13592 (match_operand:SI 2 "immediate_operand" "i")))]
13595 if (constant_call_address_operand (operands[0], Pmode))
13597 if (SIBLING_CALL_P (insn))
13600 return "call\t%P0";
13602 if (SIBLING_CALL_P (insn))
13605 return "call\t%A0";
13607 [(set_attr "type" "call")])
13609 (define_expand "call"
13610 [(call (match_operand:QI 0 "" "")
13611 (match_operand 1 "" ""))
13612 (use (match_operand 2 "" ""))]
13615 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
13619 (define_expand "sibcall"
13620 [(call (match_operand:QI 0 "" "")
13621 (match_operand 1 "" ""))
13622 (use (match_operand 2 "" ""))]
13625 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
13629 (define_insn "*call_0"
13630 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
13631 (match_operand 1 "" ""))]
13634 if (SIBLING_CALL_P (insn))
13637 return "call\t%P0";
13639 [(set_attr "type" "call")])
13641 (define_insn "*call_1"
13642 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
13643 (match_operand 1 "" ""))]
13644 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
13646 if (constant_call_address_operand (operands[0], Pmode))
13647 return "call\t%P0";
13648 return "call\t%A0";
13650 [(set_attr "type" "call")])
13652 (define_insn "*sibcall_1"
13653 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
13654 (match_operand 1 "" ""))]
13655 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
13657 if (constant_call_address_operand (operands[0], Pmode))
13661 [(set_attr "type" "call")])
13663 (define_insn "*call_1_rex64"
13664 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
13665 (match_operand 1 "" ""))]
13666 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
13668 if (constant_call_address_operand (operands[0], Pmode))
13669 return "call\t%P0";
13670 return "call\t%A0";
13672 [(set_attr "type" "call")])
13674 (define_insn "*sibcall_1_rex64"
13675 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
13676 (match_operand 1 "" ""))]
13677 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13679 [(set_attr "type" "call")])
13681 (define_insn "*sibcall_1_rex64_v"
13682 [(call (mem:QI (reg:DI 40))
13683 (match_operand 0 "" ""))]
13684 "SIBLING_CALL_P (insn) && TARGET_64BIT"
13686 [(set_attr "type" "call")])
13689 ;; Call subroutine, returning value in operand 0
13691 (define_expand "call_value_pop"
13692 [(parallel [(set (match_operand 0 "" "")
13693 (call (match_operand:QI 1 "" "")
13694 (match_operand:SI 2 "" "")))
13695 (set (reg:SI SP_REG)
13696 (plus:SI (reg:SI SP_REG)
13697 (match_operand:SI 4 "" "")))])]
13700 ix86_expand_call (operands[0], operands[1], operands[2],
13701 operands[3], operands[4], 0);
13705 (define_expand "call_value"
13706 [(set (match_operand 0 "" "")
13707 (call (match_operand:QI 1 "" "")
13708 (match_operand:SI 2 "" "")))
13709 (use (match_operand:SI 3 "" ""))]
13710 ;; Operand 2 not used on the i386.
13713 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
13717 (define_expand "sibcall_value"
13718 [(set (match_operand 0 "" "")
13719 (call (match_operand:QI 1 "" "")
13720 (match_operand:SI 2 "" "")))
13721 (use (match_operand:SI 3 "" ""))]
13722 ;; Operand 2 not used on the i386.
13725 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
13729 ;; Call subroutine returning any type.
13731 (define_expand "untyped_call"
13732 [(parallel [(call (match_operand 0 "" "")
13734 (match_operand 1 "" "")
13735 (match_operand 2 "" "")])]
13740 /* In order to give reg-stack an easier job in validating two
13741 coprocessor registers as containing a possible return value,
13742 simply pretend the untyped call returns a complex long double
13745 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
13746 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13747 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
13750 for (i = 0; i < XVECLEN (operands[2], 0); i++)
13752 rtx set = XVECEXP (operands[2], 0, i);
13753 emit_move_insn (SET_DEST (set), SET_SRC (set));
13756 /* The optimizer does not know that the call sets the function value
13757 registers we stored in the result block. We avoid problems by
13758 claiming that all hard registers are used and clobbered at this
13760 emit_insn (gen_blockage (const0_rtx));
13765 ;; Prologue and epilogue instructions
13767 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
13768 ;; all of memory. This blocks insns from being moved across this point.
13770 (define_insn "blockage"
13771 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
13774 [(set_attr "length" "0")])
13776 ;; Insn emitted into the body of a function to return from a function.
13777 ;; This is only done if the function's epilogue is known to be simple.
13778 ;; See comments for ix86_can_use_return_insn_p in i386.c.
13780 (define_expand "return"
13782 "ix86_can_use_return_insn_p ()"
13784 if (current_function_pops_args)
13786 rtx popc = GEN_INT (current_function_pops_args);
13787 emit_jump_insn (gen_return_pop_internal (popc));
13792 (define_insn "return_internal"
13796 [(set_attr "length" "1")
13797 (set_attr "length_immediate" "0")
13798 (set_attr "modrm" "0")])
13800 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
13801 ;; instruction Athlon and K8 have.
13803 (define_insn "return_internal_long"
13805 (unspec [(const_int 0)] UNSPEC_REP)]
13808 [(set_attr "length" "1")
13809 (set_attr "length_immediate" "0")
13810 (set_attr "prefix_rep" "1")
13811 (set_attr "modrm" "0")])
13813 (define_insn "return_pop_internal"
13815 (use (match_operand:SI 0 "const_int_operand" ""))]
13818 [(set_attr "length" "3")
13819 (set_attr "length_immediate" "2")
13820 (set_attr "modrm" "0")])
13822 (define_insn "return_indirect_internal"
13824 (use (match_operand:SI 0 "register_operand" "r"))]
13827 [(set_attr "type" "ibr")
13828 (set_attr "length_immediate" "0")])
13834 [(set_attr "length" "1")
13835 (set_attr "length_immediate" "0")
13836 (set_attr "modrm" "0")])
13838 ;; Align to 16-byte boundary, max skip in op0. Used to avoid
13839 ;; branch prediction penalty for the third jump in a 16-byte
13842 (define_insn "align"
13843 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
13846 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
13847 ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
13849 /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
13850 The align insn is used to avoid 3 jump instructions in the row to improve
13851 branch prediction and the benefits hardly outweight the cost of extra 8
13852 nops on the average inserted by full alignment pseudo operation. */
13856 [(set_attr "length" "16")])
13858 (define_expand "prologue"
13861 "ix86_expand_prologue (); DONE;")
13863 (define_insn "set_got"
13864 [(set (match_operand:SI 0 "register_operand" "=r")
13865 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
13866 (clobber (reg:CC FLAGS_REG))]
13868 { return output_set_got (operands[0]); }
13869 [(set_attr "type" "multi")
13870 (set_attr "length" "12")])
13872 (define_insn "set_got_rex64"
13873 [(set (match_operand:DI 0 "register_operand" "=r")
13874 (unspec:DI [(const_int 0)] UNSPEC_SET_GOT))]
13876 "lea{q}\t_GLOBAL_OFFSET_TABLE_(%%rip), %0"
13877 [(set_attr "type" "lea")
13878 (set_attr "length" "6")])
13880 (define_expand "epilogue"
13883 "ix86_expand_epilogue (1); DONE;")
13885 (define_expand "sibcall_epilogue"
13888 "ix86_expand_epilogue (0); DONE;")
13890 (define_expand "eh_return"
13891 [(use (match_operand 0 "register_operand" ""))]
13894 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
13896 /* Tricky bit: we write the address of the handler to which we will
13897 be returning into someone else's stack frame, one word below the
13898 stack address we wish to restore. */
13899 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
13900 tmp = plus_constant (tmp, -UNITS_PER_WORD);
13901 tmp = gen_rtx_MEM (Pmode, tmp);
13902 emit_move_insn (tmp, ra);
13904 if (Pmode == SImode)
13905 emit_jump_insn (gen_eh_return_si (sa));
13907 emit_jump_insn (gen_eh_return_di (sa));
13912 (define_insn_and_split "eh_return_si"
13914 (unspec [(match_operand:SI 0 "register_operand" "c")]
13915 UNSPEC_EH_RETURN))]
13920 "ix86_expand_epilogue (2); DONE;")
13922 (define_insn_and_split "eh_return_di"
13924 (unspec [(match_operand:DI 0 "register_operand" "c")]
13925 UNSPEC_EH_RETURN))]
13930 "ix86_expand_epilogue (2); DONE;")
13932 (define_insn "leave"
13933 [(set (reg:SI SP_REG) (plus:SI (reg:SI BP_REG) (const_int 4)))
13934 (set (reg:SI BP_REG) (mem:SI (reg:SI BP_REG)))
13935 (clobber (mem:BLK (scratch)))]
13938 [(set_attr "type" "leave")])
13940 (define_insn "leave_rex64"
13941 [(set (reg:DI SP_REG) (plus:DI (reg:DI BP_REG) (const_int 8)))
13942 (set (reg:DI BP_REG) (mem:DI (reg:DI BP_REG)))
13943 (clobber (mem:BLK (scratch)))]
13946 [(set_attr "type" "leave")])
13948 (define_expand "ffssi2"
13950 [(set (match_operand:SI 0 "register_operand" "")
13951 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
13952 (clobber (match_scratch:SI 2 ""))
13953 (clobber (reg:CC FLAGS_REG))])]
13957 (define_insn_and_split "*ffs_cmove"
13958 [(set (match_operand:SI 0 "register_operand" "=r")
13959 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13960 (clobber (match_scratch:SI 2 "=&r"))
13961 (clobber (reg:CC FLAGS_REG))]
13964 "&& reload_completed"
13965 [(set (match_dup 2) (const_int -1))
13966 (parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
13967 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13968 (set (match_dup 0) (if_then_else:SI
13969 (eq (reg:CCZ FLAGS_REG) (const_int 0))
13972 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
13973 (clobber (reg:CC FLAGS_REG))])]
13976 (define_insn_and_split "*ffs_no_cmove"
13977 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
13978 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
13979 (clobber (match_scratch:SI 2 "=&q"))
13980 (clobber (reg:CC FLAGS_REG))]
13984 [(parallel [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 1) (const_int 0)))
13985 (set (match_dup 0) (ctz:SI (match_dup 1)))])
13986 (set (strict_low_part (match_dup 3))
13987 (eq:QI (reg:CCZ FLAGS_REG) (const_int 0)))
13988 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
13989 (clobber (reg:CC FLAGS_REG))])
13990 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
13991 (clobber (reg:CC FLAGS_REG))])
13992 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
13993 (clobber (reg:CC FLAGS_REG))])]
13995 operands[3] = gen_lowpart (QImode, operands[2]);
13996 ix86_expand_clear (operands[2]);
13999 (define_insn "*ffssi_1"
14000 [(set (reg:CCZ FLAGS_REG)
14001 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
14003 (set (match_operand:SI 0 "register_operand" "=r")
14004 (ctz:SI (match_dup 1)))]
14006 "bsf{l}\t{%1, %0|%0, %1}"
14007 [(set_attr "prefix_0f" "1")])
14009 (define_expand "ffsdi2"
14011 [(set (match_operand:DI 0 "register_operand" "")
14012 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "")))
14013 (clobber (match_scratch:DI 2 ""))
14014 (clobber (reg:CC FLAGS_REG))])]
14015 "TARGET_64BIT && TARGET_CMOVE"
14018 (define_insn_and_split "*ffs_rex64"
14019 [(set (match_operand:DI 0 "register_operand" "=r")
14020 (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
14021 (clobber (match_scratch:DI 2 "=&r"))
14022 (clobber (reg:CC FLAGS_REG))]
14023 "TARGET_64BIT && TARGET_CMOVE"
14025 "&& reload_completed"
14026 [(set (match_dup 2) (const_int -1))
14027 (parallel [(set (reg:CCZ FLAGS_REG)
14028 (compare:CCZ (match_dup 1) (const_int 0)))
14029 (set (match_dup 0) (ctz:DI (match_dup 1)))])
14030 (set (match_dup 0) (if_then_else:DI
14031 (eq (reg:CCZ FLAGS_REG) (const_int 0))
14034 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
14035 (clobber (reg:CC FLAGS_REG))])]
14038 (define_insn "*ffsdi_1"
14039 [(set (reg:CCZ FLAGS_REG)
14040 (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
14042 (set (match_operand:DI 0 "register_operand" "=r")
14043 (ctz:DI (match_dup 1)))]
14045 "bsf{q}\t{%1, %0|%0, %1}"
14046 [(set_attr "prefix_0f" "1")])
14048 (define_insn "ctzsi2"
14049 [(set (match_operand:SI 0 "register_operand" "=r")
14050 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14051 (clobber (reg:CC FLAGS_REG))]
14053 "bsf{l}\t{%1, %0|%0, %1}"
14054 [(set_attr "prefix_0f" "1")])
14056 (define_insn "ctzdi2"
14057 [(set (match_operand:DI 0 "register_operand" "=r")
14058 (ctz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
14059 (clobber (reg:CC FLAGS_REG))]
14061 "bsf{q}\t{%1, %0|%0, %1}"
14062 [(set_attr "prefix_0f" "1")])
14064 (define_expand "clzsi2"
14066 [(set (match_operand:SI 0 "register_operand" "")
14067 (minus:SI (const_int 31)
14068 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
14069 (clobber (reg:CC FLAGS_REG))])
14071 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
14072 (clobber (reg:CC FLAGS_REG))])]
14076 (define_insn "*bsr"
14077 [(set (match_operand:SI 0 "register_operand" "=r")
14078 (minus:SI (const_int 31)
14079 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
14080 (clobber (reg:CC FLAGS_REG))]
14082 "bsr{l}\t{%1, %0|%0, %1}"
14083 [(set_attr "prefix_0f" "1")])
14085 (define_expand "clzdi2"
14087 [(set (match_operand:DI 0 "register_operand" "")
14088 (minus:DI (const_int 63)
14089 (clz:DI (match_operand:DI 1 "nonimmediate_operand" ""))))
14090 (clobber (reg:CC FLAGS_REG))])
14092 [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
14093 (clobber (reg:CC FLAGS_REG))])]
14097 (define_insn "*bsr_rex64"
14098 [(set (match_operand:DI 0 "register_operand" "=r")
14099 (minus:DI (const_int 63)
14100 (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))))
14101 (clobber (reg:CC FLAGS_REG))]
14103 "bsr{q}\t{%1, %0|%0, %1}"
14104 [(set_attr "prefix_0f" "1")])
14106 ;; Thread-local storage patterns for ELF.
14108 ;; Note that these code sequences must appear exactly as shown
14109 ;; in order to allow linker relaxation.
14111 (define_insn "*tls_global_dynamic_32_gnu"
14112 [(set (match_operand:SI 0 "register_operand" "=a")
14113 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14114 (match_operand:SI 2 "tls_symbolic_operand" "")
14115 (match_operand:SI 3 "call_insn_operand" "")]
14117 (clobber (match_scratch:SI 4 "=d"))
14118 (clobber (match_scratch:SI 5 "=c"))
14119 (clobber (reg:CC FLAGS_REG))]
14120 "!TARGET_64BIT && TARGET_GNU_TLS"
14121 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
14122 [(set_attr "type" "multi")
14123 (set_attr "length" "12")])
14125 (define_insn "*tls_global_dynamic_32_sun"
14126 [(set (match_operand:SI 0 "register_operand" "=a")
14127 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14128 (match_operand:SI 2 "tls_symbolic_operand" "")
14129 (match_operand:SI 3 "call_insn_operand" "")]
14131 (clobber (match_scratch:SI 4 "=d"))
14132 (clobber (match_scratch:SI 5 "=c"))
14133 (clobber (reg:CC FLAGS_REG))]
14134 "!TARGET_64BIT && TARGET_SUN_TLS"
14135 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
14136 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
14137 [(set_attr "type" "multi")
14138 (set_attr "length" "14")])
14140 (define_expand "tls_global_dynamic_32"
14141 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14144 (match_operand:SI 1 "tls_symbolic_operand" "")
14147 (clobber (match_scratch:SI 4 ""))
14148 (clobber (match_scratch:SI 5 ""))
14149 (clobber (reg:CC FLAGS_REG))])]
14153 operands[2] = pic_offset_table_rtx;
14156 operands[2] = gen_reg_rtx (Pmode);
14157 emit_insn (gen_set_got (operands[2]));
14159 operands[3] = ix86_tls_get_addr ();
14162 (define_insn "*tls_global_dynamic_64"
14163 [(set (match_operand:DI 0 "register_operand" "=a")
14164 (call:DI (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
14165 (match_operand:DI 3 "" "")))
14166 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14169 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
14170 [(set_attr "type" "multi")
14171 (set_attr "length" "16")])
14173 (define_expand "tls_global_dynamic_64"
14174 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14175 (call:DI (mem:QI (match_dup 2)) (const_int 0)))
14176 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14180 operands[2] = ix86_tls_get_addr ();
14183 (define_insn "*tls_local_dynamic_base_32_gnu"
14184 [(set (match_operand:SI 0 "register_operand" "=a")
14185 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14186 (match_operand:SI 2 "call_insn_operand" "")]
14187 UNSPEC_TLS_LD_BASE))
14188 (clobber (match_scratch:SI 3 "=d"))
14189 (clobber (match_scratch:SI 4 "=c"))
14190 (clobber (reg:CC FLAGS_REG))]
14191 "!TARGET_64BIT && TARGET_GNU_TLS"
14192 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
14193 [(set_attr "type" "multi")
14194 (set_attr "length" "11")])
14196 (define_insn "*tls_local_dynamic_base_32_sun"
14197 [(set (match_operand:SI 0 "register_operand" "=a")
14198 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14199 (match_operand:SI 2 "call_insn_operand" "")]
14200 UNSPEC_TLS_LD_BASE))
14201 (clobber (match_scratch:SI 3 "=d"))
14202 (clobber (match_scratch:SI 4 "=c"))
14203 (clobber (reg:CC FLAGS_REG))]
14204 "!TARGET_64BIT && TARGET_SUN_TLS"
14205 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
14206 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
14207 [(set_attr "type" "multi")
14208 (set_attr "length" "13")])
14210 (define_expand "tls_local_dynamic_base_32"
14211 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14212 (unspec:SI [(match_dup 1) (match_dup 2)]
14213 UNSPEC_TLS_LD_BASE))
14214 (clobber (match_scratch:SI 3 ""))
14215 (clobber (match_scratch:SI 4 ""))
14216 (clobber (reg:CC FLAGS_REG))])]
14220 operands[1] = pic_offset_table_rtx;
14223 operands[1] = gen_reg_rtx (Pmode);
14224 emit_insn (gen_set_got (operands[1]));
14226 operands[2] = ix86_tls_get_addr ();
14229 (define_insn "*tls_local_dynamic_base_64"
14230 [(set (match_operand:DI 0 "register_operand" "=a")
14231 (call:DI (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14232 (match_operand:DI 2 "" "")))
14233 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14235 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14236 [(set_attr "type" "multi")
14237 (set_attr "length" "12")])
14239 (define_expand "tls_local_dynamic_base_64"
14240 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14241 (call:DI (mem:QI (match_dup 1)) (const_int 0)))
14242 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14245 operands[1] = ix86_tls_get_addr ();
14248 ;; Local dynamic of a single variable is a lose. Show combine how
14249 ;; to convert that back to global dynamic.
14251 (define_insn_and_split "*tls_local_dynamic_32_once"
14252 [(set (match_operand:SI 0 "register_operand" "=a")
14253 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14254 (match_operand:SI 2 "call_insn_operand" "")]
14255 UNSPEC_TLS_LD_BASE)
14256 (const:SI (unspec:SI
14257 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14259 (clobber (match_scratch:SI 4 "=d"))
14260 (clobber (match_scratch:SI 5 "=c"))
14261 (clobber (reg:CC FLAGS_REG))]
14265 [(parallel [(set (match_dup 0)
14266 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14268 (clobber (match_dup 4))
14269 (clobber (match_dup 5))
14270 (clobber (reg:CC FLAGS_REG))])]
14273 ;; Load and add the thread base pointer from %gs:0.
14275 (define_insn "*load_tp_si"
14276 [(set (match_operand:SI 0 "register_operand" "=r")
14277 (unspec:SI [(const_int 0)] UNSPEC_TP))]
14279 "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14280 [(set_attr "type" "imov")
14281 (set_attr "modrm" "0")
14282 (set_attr "length" "7")
14283 (set_attr "memory" "load")
14284 (set_attr "imm_disp" "false")])
14286 (define_insn "*add_tp_si"
14287 [(set (match_operand:SI 0 "register_operand" "=r")
14288 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
14289 (match_operand:SI 1 "register_operand" "0")))
14290 (clobber (reg:CC FLAGS_REG))]
14292 "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14293 [(set_attr "type" "alu")
14294 (set_attr "modrm" "0")
14295 (set_attr "length" "7")
14296 (set_attr "memory" "load")
14297 (set_attr "imm_disp" "false")])
14299 (define_insn "*load_tp_di"
14300 [(set (match_operand:DI 0 "register_operand" "=r")
14301 (unspec:DI [(const_int 0)] UNSPEC_TP))]
14303 "mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14304 [(set_attr "type" "imov")
14305 (set_attr "modrm" "0")
14306 (set_attr "length" "7")
14307 (set_attr "memory" "load")
14308 (set_attr "imm_disp" "false")])
14310 (define_insn "*add_tp_di"
14311 [(set (match_operand:DI 0 "register_operand" "=r")
14312 (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
14313 (match_operand:DI 1 "register_operand" "0")))
14314 (clobber (reg:CC FLAGS_REG))]
14316 "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14317 [(set_attr "type" "alu")
14318 (set_attr "modrm" "0")
14319 (set_attr "length" "7")
14320 (set_attr "memory" "load")
14321 (set_attr "imm_disp" "false")])
14323 ;; These patterns match the binary 387 instructions for addM3, subM3,
14324 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14325 ;; SFmode. The first is the normal insn, the second the same insn but
14326 ;; with one operand a conversion, and the third the same insn but with
14327 ;; the other operand a conversion. The conversion may be SFmode or
14328 ;; SImode if the target mode DFmode, but only SImode if the target mode
14331 ;; Gcc is slightly more smart about handling normal two address instructions
14332 ;; so use special patterns for add and mull.
14334 (define_insn "*fop_sf_comm_mixed"
14335 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14336 (match_operator:SF 3 "binary_fp_operator"
14337 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14338 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14339 "TARGET_MIX_SSE_I387
14340 && COMMUTATIVE_ARITH_P (operands[3])
14341 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14342 "* return output_387_binary_op (insn, operands);"
14343 [(set (attr "type")
14344 (if_then_else (eq_attr "alternative" "1")
14345 (if_then_else (match_operand:SF 3 "mult_operator" "")
14346 (const_string "ssemul")
14347 (const_string "sseadd"))
14348 (if_then_else (match_operand:SF 3 "mult_operator" "")
14349 (const_string "fmul")
14350 (const_string "fop"))))
14351 (set_attr "mode" "SF")])
14353 (define_insn "*fop_sf_comm_sse"
14354 [(set (match_operand:SF 0 "register_operand" "=x")
14355 (match_operator:SF 3 "binary_fp_operator"
14356 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14357 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14359 && COMMUTATIVE_ARITH_P (operands[3])
14360 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14361 "* return output_387_binary_op (insn, operands);"
14362 [(set (attr "type")
14363 (if_then_else (match_operand:SF 3 "mult_operator" "")
14364 (const_string "ssemul")
14365 (const_string "sseadd")))
14366 (set_attr "mode" "SF")])
14368 (define_insn "*fop_sf_comm_i387"
14369 [(set (match_operand:SF 0 "register_operand" "=f")
14370 (match_operator:SF 3 "binary_fp_operator"
14371 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14372 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14374 && COMMUTATIVE_ARITH_P (operands[3])
14375 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14376 "* return output_387_binary_op (insn, operands);"
14377 [(set (attr "type")
14378 (if_then_else (match_operand:SF 3 "mult_operator" "")
14379 (const_string "fmul")
14380 (const_string "fop")))
14381 (set_attr "mode" "SF")])
14383 (define_insn "*fop_sf_1_mixed"
14384 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14385 (match_operator:SF 3 "binary_fp_operator"
14386 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14387 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14388 "TARGET_MIX_SSE_I387
14389 && !COMMUTATIVE_ARITH_P (operands[3])
14390 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14391 "* return output_387_binary_op (insn, operands);"
14392 [(set (attr "type")
14393 (cond [(and (eq_attr "alternative" "2")
14394 (match_operand:SF 3 "mult_operator" ""))
14395 (const_string "ssemul")
14396 (and (eq_attr "alternative" "2")
14397 (match_operand:SF 3 "div_operator" ""))
14398 (const_string "ssediv")
14399 (eq_attr "alternative" "2")
14400 (const_string "sseadd")
14401 (match_operand:SF 3 "mult_operator" "")
14402 (const_string "fmul")
14403 (match_operand:SF 3 "div_operator" "")
14404 (const_string "fdiv")
14406 (const_string "fop")))
14407 (set_attr "mode" "SF")])
14409 (define_insn "*fop_sf_1_sse"
14410 [(set (match_operand:SF 0 "register_operand" "=x")
14411 (match_operator:SF 3 "binary_fp_operator"
14412 [(match_operand:SF 1 "register_operand" "0")
14413 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14415 && !COMMUTATIVE_ARITH_P (operands[3])"
14416 "* return output_387_binary_op (insn, operands);"
14417 [(set (attr "type")
14418 (cond [(match_operand:SF 3 "mult_operator" "")
14419 (const_string "ssemul")
14420 (match_operand:SF 3 "div_operator" "")
14421 (const_string "ssediv")
14423 (const_string "sseadd")))
14424 (set_attr "mode" "SF")])
14426 ;; This pattern is not fully shadowed by the pattern above.
14427 (define_insn "*fop_sf_1_i387"
14428 [(set (match_operand:SF 0 "register_operand" "=f,f")
14429 (match_operator:SF 3 "binary_fp_operator"
14430 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14431 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14432 "TARGET_80387 && !TARGET_SSE_MATH
14433 && !COMMUTATIVE_ARITH_P (operands[3])
14434 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14435 "* return output_387_binary_op (insn, operands);"
14436 [(set (attr "type")
14437 (cond [(match_operand:SF 3 "mult_operator" "")
14438 (const_string "fmul")
14439 (match_operand:SF 3 "div_operator" "")
14440 (const_string "fdiv")
14442 (const_string "fop")))
14443 (set_attr "mode" "SF")])
14445 ;; ??? Add SSE splitters for these!
14446 (define_insn "*fop_sf_2<mode>_i387"
14447 [(set (match_operand:SF 0 "register_operand" "=f,f")
14448 (match_operator:SF 3 "binary_fp_operator"
14449 [(float:SF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
14450 (match_operand:SF 2 "register_operand" "0,0")]))]
14451 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
14452 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14453 [(set (attr "type")
14454 (cond [(match_operand:SF 3 "mult_operator" "")
14455 (const_string "fmul")
14456 (match_operand:SF 3 "div_operator" "")
14457 (const_string "fdiv")
14459 (const_string "fop")))
14460 (set_attr "fp_int_src" "true")
14461 (set_attr "mode" "<MODE>")])
14463 (define_insn "*fop_sf_3<mode>_i387"
14464 [(set (match_operand:SF 0 "register_operand" "=f,f")
14465 (match_operator:SF 3 "binary_fp_operator"
14466 [(match_operand:SF 1 "register_operand" "0,0")
14467 (float:SF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
14468 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
14469 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14470 [(set (attr "type")
14471 (cond [(match_operand:SF 3 "mult_operator" "")
14472 (const_string "fmul")
14473 (match_operand:SF 3 "div_operator" "")
14474 (const_string "fdiv")
14476 (const_string "fop")))
14477 (set_attr "fp_int_src" "true")
14478 (set_attr "mode" "<MODE>")])
14480 (define_insn "*fop_df_comm_mixed"
14481 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14482 (match_operator:DF 3 "binary_fp_operator"
14483 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14484 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14485 "TARGET_SSE2 && TARGET_MIX_SSE_I387
14486 && COMMUTATIVE_ARITH_P (operands[3])
14487 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14488 "* return output_387_binary_op (insn, operands);"
14489 [(set (attr "type")
14490 (if_then_else (eq_attr "alternative" "1")
14491 (if_then_else (match_operand:SF 3 "mult_operator" "")
14492 (const_string "ssemul")
14493 (const_string "sseadd"))
14494 (if_then_else (match_operand:SF 3 "mult_operator" "")
14495 (const_string "fmul")
14496 (const_string "fop"))))
14497 (set_attr "mode" "DF")])
14499 (define_insn "*fop_df_comm_sse"
14500 [(set (match_operand:DF 0 "register_operand" "=Y")
14501 (match_operator:DF 3 "binary_fp_operator"
14502 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14503 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14504 "TARGET_SSE2 && TARGET_SSE_MATH
14505 && COMMUTATIVE_ARITH_P (operands[3])
14506 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14507 "* return output_387_binary_op (insn, operands);"
14508 [(set (attr "type")
14509 (if_then_else (match_operand:SF 3 "mult_operator" "")
14510 (const_string "ssemul")
14511 (const_string "sseadd")))
14512 (set_attr "mode" "DF")])
14514 (define_insn "*fop_df_comm_i387"
14515 [(set (match_operand:DF 0 "register_operand" "=f")
14516 (match_operator:DF 3 "binary_fp_operator"
14517 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14518 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14520 && COMMUTATIVE_ARITH_P (operands[3])
14521 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14522 "* return output_387_binary_op (insn, operands);"
14523 [(set (attr "type")
14524 (if_then_else (match_operand:SF 3 "mult_operator" "")
14525 (const_string "fmul")
14526 (const_string "fop")))
14527 (set_attr "mode" "DF")])
14529 (define_insn "*fop_df_1_mixed"
14530 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14531 (match_operator:DF 3 "binary_fp_operator"
14532 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14533 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14534 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14535 && !COMMUTATIVE_ARITH_P (operands[3])
14536 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14537 "* return output_387_binary_op (insn, operands);"
14538 [(set (attr "type")
14539 (cond [(and (eq_attr "alternative" "2")
14540 (match_operand:SF 3 "mult_operator" ""))
14541 (const_string "ssemul")
14542 (and (eq_attr "alternative" "2")
14543 (match_operand:SF 3 "div_operator" ""))
14544 (const_string "ssediv")
14545 (eq_attr "alternative" "2")
14546 (const_string "sseadd")
14547 (match_operand:DF 3 "mult_operator" "")
14548 (const_string "fmul")
14549 (match_operand:DF 3 "div_operator" "")
14550 (const_string "fdiv")
14552 (const_string "fop")))
14553 (set_attr "mode" "DF")])
14555 (define_insn "*fop_df_1_sse"
14556 [(set (match_operand:DF 0 "register_operand" "=Y")
14557 (match_operator:DF 3 "binary_fp_operator"
14558 [(match_operand:DF 1 "register_operand" "0")
14559 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14560 "TARGET_SSE2 && TARGET_SSE_MATH
14561 && !COMMUTATIVE_ARITH_P (operands[3])"
14562 "* return output_387_binary_op (insn, operands);"
14563 [(set_attr "mode" "DF")
14565 (cond [(match_operand:SF 3 "mult_operator" "")
14566 (const_string "ssemul")
14567 (match_operand:SF 3 "div_operator" "")
14568 (const_string "ssediv")
14570 (const_string "sseadd")))])
14572 ;; This pattern is not fully shadowed by the pattern above.
14573 (define_insn "*fop_df_1_i387"
14574 [(set (match_operand:DF 0 "register_operand" "=f,f")
14575 (match_operator:DF 3 "binary_fp_operator"
14576 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14577 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14578 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
14579 && !COMMUTATIVE_ARITH_P (operands[3])
14580 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14581 "* return output_387_binary_op (insn, operands);"
14582 [(set (attr "type")
14583 (cond [(match_operand:DF 3 "mult_operator" "")
14584 (const_string "fmul")
14585 (match_operand:DF 3 "div_operator" "")
14586 (const_string "fdiv")
14588 (const_string "fop")))
14589 (set_attr "mode" "DF")])
14591 ;; ??? Add SSE splitters for these!
14592 (define_insn "*fop_df_2<mode>_i387"
14593 [(set (match_operand:DF 0 "register_operand" "=f,f")
14594 (match_operator:DF 3 "binary_fp_operator"
14595 [(float:DF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
14596 (match_operand:DF 2 "register_operand" "0,0")]))]
14597 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
14598 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14599 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14600 [(set (attr "type")
14601 (cond [(match_operand:DF 3 "mult_operator" "")
14602 (const_string "fmul")
14603 (match_operand:DF 3 "div_operator" "")
14604 (const_string "fdiv")
14606 (const_string "fop")))
14607 (set_attr "fp_int_src" "true")
14608 (set_attr "mode" "<MODE>")])
14610 (define_insn "*fop_df_3<mode>_i387"
14611 [(set (match_operand:DF 0 "register_operand" "=f,f")
14612 (match_operator:DF 3 "binary_fp_operator"
14613 [(match_operand:DF 1 "register_operand" "0,0")
14614 (float:DF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
14615 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
14616 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14617 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14618 [(set (attr "type")
14619 (cond [(match_operand:DF 3 "mult_operator" "")
14620 (const_string "fmul")
14621 (match_operand:DF 3 "div_operator" "")
14622 (const_string "fdiv")
14624 (const_string "fop")))
14625 (set_attr "fp_int_src" "true")
14626 (set_attr "mode" "<MODE>")])
14628 (define_insn "*fop_df_4_i387"
14629 [(set (match_operand:DF 0 "register_operand" "=f,f")
14630 (match_operator:DF 3 "binary_fp_operator"
14631 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
14632 (match_operand:DF 2 "register_operand" "0,f")]))]
14633 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
14634 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14635 "* return output_387_binary_op (insn, operands);"
14636 [(set (attr "type")
14637 (cond [(match_operand:DF 3 "mult_operator" "")
14638 (const_string "fmul")
14639 (match_operand:DF 3 "div_operator" "")
14640 (const_string "fdiv")
14642 (const_string "fop")))
14643 (set_attr "mode" "SF")])
14645 (define_insn "*fop_df_5_i387"
14646 [(set (match_operand:DF 0 "register_operand" "=f,f")
14647 (match_operator:DF 3 "binary_fp_operator"
14648 [(match_operand:DF 1 "register_operand" "0,f")
14650 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14651 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14652 "* return output_387_binary_op (insn, operands);"
14653 [(set (attr "type")
14654 (cond [(match_operand:DF 3 "mult_operator" "")
14655 (const_string "fmul")
14656 (match_operand:DF 3 "div_operator" "")
14657 (const_string "fdiv")
14659 (const_string "fop")))
14660 (set_attr "mode" "SF")])
14662 (define_insn "*fop_df_6_i387"
14663 [(set (match_operand:DF 0 "register_operand" "=f,f")
14664 (match_operator:DF 3 "binary_fp_operator"
14666 (match_operand:SF 1 "register_operand" "0,f"))
14668 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
14669 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14670 "* return output_387_binary_op (insn, operands);"
14671 [(set (attr "type")
14672 (cond [(match_operand:DF 3 "mult_operator" "")
14673 (const_string "fmul")
14674 (match_operand:DF 3 "div_operator" "")
14675 (const_string "fdiv")
14677 (const_string "fop")))
14678 (set_attr "mode" "SF")])
14680 (define_insn "*fop_xf_comm_i387"
14681 [(set (match_operand:XF 0 "register_operand" "=f")
14682 (match_operator:XF 3 "binary_fp_operator"
14683 [(match_operand:XF 1 "register_operand" "%0")
14684 (match_operand:XF 2 "register_operand" "f")]))]
14686 && COMMUTATIVE_ARITH_P (operands[3])"
14687 "* return output_387_binary_op (insn, operands);"
14688 [(set (attr "type")
14689 (if_then_else (match_operand:XF 3 "mult_operator" "")
14690 (const_string "fmul")
14691 (const_string "fop")))
14692 (set_attr "mode" "XF")])
14694 (define_insn "*fop_xf_1_i387"
14695 [(set (match_operand:XF 0 "register_operand" "=f,f")
14696 (match_operator:XF 3 "binary_fp_operator"
14697 [(match_operand:XF 1 "register_operand" "0,f")
14698 (match_operand:XF 2 "register_operand" "f,0")]))]
14700 && !COMMUTATIVE_ARITH_P (operands[3])"
14701 "* return output_387_binary_op (insn, operands);"
14702 [(set (attr "type")
14703 (cond [(match_operand:XF 3 "mult_operator" "")
14704 (const_string "fmul")
14705 (match_operand:XF 3 "div_operator" "")
14706 (const_string "fdiv")
14708 (const_string "fop")))
14709 (set_attr "mode" "XF")])
14711 (define_insn "*fop_xf_2<mode>_i387"
14712 [(set (match_operand:XF 0 "register_operand" "=f,f")
14713 (match_operator:XF 3 "binary_fp_operator"
14714 [(float:XF (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
14715 (match_operand:XF 2 "register_operand" "0,0")]))]
14716 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
14717 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14718 [(set (attr "type")
14719 (cond [(match_operand:XF 3 "mult_operator" "")
14720 (const_string "fmul")
14721 (match_operand:XF 3 "div_operator" "")
14722 (const_string "fdiv")
14724 (const_string "fop")))
14725 (set_attr "fp_int_src" "true")
14726 (set_attr "mode" "<MODE>")])
14728 (define_insn "*fop_xf_3<mode>_i387"
14729 [(set (match_operand:XF 0 "register_operand" "=f,f")
14730 (match_operator:XF 3 "binary_fp_operator"
14731 [(match_operand:XF 1 "register_operand" "0,0")
14732 (float:XF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
14733 "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
14734 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14735 [(set (attr "type")
14736 (cond [(match_operand:XF 3 "mult_operator" "")
14737 (const_string "fmul")
14738 (match_operand:XF 3 "div_operator" "")
14739 (const_string "fdiv")
14741 (const_string "fop")))
14742 (set_attr "fp_int_src" "true")
14743 (set_attr "mode" "<MODE>")])
14745 (define_insn "*fop_xf_4_i387"
14746 [(set (match_operand:XF 0 "register_operand" "=f,f")
14747 (match_operator:XF 3 "binary_fp_operator"
14748 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
14749 (match_operand:XF 2 "register_operand" "0,f")]))]
14751 "* return output_387_binary_op (insn, operands);"
14752 [(set (attr "type")
14753 (cond [(match_operand:XF 3 "mult_operator" "")
14754 (const_string "fmul")
14755 (match_operand:XF 3 "div_operator" "")
14756 (const_string "fdiv")
14758 (const_string "fop")))
14759 (set_attr "mode" "SF")])
14761 (define_insn "*fop_xf_5_i387"
14762 [(set (match_operand:XF 0 "register_operand" "=f,f")
14763 (match_operator:XF 3 "binary_fp_operator"
14764 [(match_operand:XF 1 "register_operand" "0,f")
14766 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14768 "* return output_387_binary_op (insn, operands);"
14769 [(set (attr "type")
14770 (cond [(match_operand:XF 3 "mult_operator" "")
14771 (const_string "fmul")
14772 (match_operand:XF 3 "div_operator" "")
14773 (const_string "fdiv")
14775 (const_string "fop")))
14776 (set_attr "mode" "SF")])
14778 (define_insn "*fop_xf_6_i387"
14779 [(set (match_operand:XF 0 "register_operand" "=f,f")
14780 (match_operator:XF 3 "binary_fp_operator"
14782 (match_operand 1 "register_operand" "0,f"))
14784 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
14786 "* return output_387_binary_op (insn, operands);"
14787 [(set (attr "type")
14788 (cond [(match_operand:XF 3 "mult_operator" "")
14789 (const_string "fmul")
14790 (match_operand:XF 3 "div_operator" "")
14791 (const_string "fdiv")
14793 (const_string "fop")))
14794 (set_attr "mode" "SF")])
14797 [(set (match_operand 0 "register_operand" "")
14798 (match_operator 3 "binary_fp_operator"
14799 [(float (match_operand:X87MODEI12 1 "register_operand" ""))
14800 (match_operand 2 "register_operand" "")]))]
14801 "TARGET_80387 && reload_completed
14802 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14805 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
14806 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14807 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14808 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14809 GET_MODE (operands[3]),
14812 ix86_free_from_memory (GET_MODE (operands[1]));
14817 [(set (match_operand 0 "register_operand" "")
14818 (match_operator 3 "binary_fp_operator"
14819 [(match_operand 1 "register_operand" "")
14820 (float (match_operand:X87MODEI12 2 "register_operand" ""))]))]
14821 "TARGET_80387 && reload_completed
14822 && FLOAT_MODE_P (GET_MODE (operands[0]))"
14825 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
14826 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
14827 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14828 gen_rtx_fmt_ee (GET_CODE (operands[3]),
14829 GET_MODE (operands[3]),
14832 ix86_free_from_memory (GET_MODE (operands[2]));
14836 ;; FPU special functions.
14838 (define_expand "sqrtsf2"
14839 [(set (match_operand:SF 0 "register_operand" "")
14840 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
14841 "TARGET_USE_FANCY_MATH_387 || TARGET_SSE_MATH"
14843 if (!TARGET_SSE_MATH)
14844 operands[1] = force_reg (SFmode, operands[1]);
14847 (define_insn "*sqrtsf2_mixed"
14848 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14849 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
14850 "TARGET_USE_FANCY_MATH_387 && TARGET_MIX_SSE_I387"
14853 sqrtss\t{%1, %0|%0, %1}"
14854 [(set_attr "type" "fpspc,sse")
14855 (set_attr "mode" "SF,SF")
14856 (set_attr "athlon_decode" "direct,*")])
14858 (define_insn "*sqrtsf2_sse"
14859 [(set (match_operand:SF 0 "register_operand" "=x")
14860 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
14862 "sqrtss\t{%1, %0|%0, %1}"
14863 [(set_attr "type" "sse")
14864 (set_attr "mode" "SF")
14865 (set_attr "athlon_decode" "*")])
14867 (define_insn "*sqrtsf2_i387"
14868 [(set (match_operand:SF 0 "register_operand" "=f")
14869 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
14870 "TARGET_USE_FANCY_MATH_387"
14872 [(set_attr "type" "fpspc")
14873 (set_attr "mode" "SF")
14874 (set_attr "athlon_decode" "direct")])
14876 (define_expand "sqrtdf2"
14877 [(set (match_operand:DF 0 "register_operand" "")
14878 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
14879 "TARGET_USE_FANCY_MATH_387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
14881 if (!(TARGET_SSE2 && TARGET_SSE_MATH))
14882 operands[1] = force_reg (DFmode, operands[1]);
14885 (define_insn "*sqrtdf2_mixed"
14886 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14887 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
14888 "TARGET_USE_FANCY_MATH_387 && TARGET_SSE2 && TARGET_MIX_SSE_I387"
14891 sqrtsd\t{%1, %0|%0, %1}"
14892 [(set_attr "type" "fpspc,sse")
14893 (set_attr "mode" "DF,DF")
14894 (set_attr "athlon_decode" "direct,*")])
14896 (define_insn "*sqrtdf2_sse"
14897 [(set (match_operand:DF 0 "register_operand" "=Y")
14898 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
14899 "TARGET_SSE2 && TARGET_SSE_MATH"
14900 "sqrtsd\t{%1, %0|%0, %1}"
14901 [(set_attr "type" "sse")
14902 (set_attr "mode" "DF")
14903 (set_attr "athlon_decode" "*")])
14905 (define_insn "*sqrtdf2_i387"
14906 [(set (match_operand:DF 0 "register_operand" "=f")
14907 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
14908 "TARGET_USE_FANCY_MATH_387"
14910 [(set_attr "type" "fpspc")
14911 (set_attr "mode" "DF")
14912 (set_attr "athlon_decode" "direct")])
14914 (define_insn "*sqrtextendsfdf2_i387"
14915 [(set (match_operand:DF 0 "register_operand" "=f")
14916 (sqrt:DF (float_extend:DF
14917 (match_operand:SF 1 "register_operand" "0"))))]
14918 "TARGET_USE_FANCY_MATH_387
14919 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)"
14921 [(set_attr "type" "fpspc")
14922 (set_attr "mode" "DF")
14923 (set_attr "athlon_decode" "direct")])
14925 (define_insn "sqrtxf2"
14926 [(set (match_operand:XF 0 "register_operand" "=f")
14927 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
14928 "TARGET_USE_FANCY_MATH_387
14929 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
14931 [(set_attr "type" "fpspc")
14932 (set_attr "mode" "XF")
14933 (set_attr "athlon_decode" "direct")])
14935 (define_insn "*sqrtextendsfxf2_i387"
14936 [(set (match_operand:XF 0 "register_operand" "=f")
14937 (sqrt:XF (float_extend:XF
14938 (match_operand:SF 1 "register_operand" "0"))))]
14939 "TARGET_USE_FANCY_MATH_387"
14941 [(set_attr "type" "fpspc")
14942 (set_attr "mode" "XF")
14943 (set_attr "athlon_decode" "direct")])
14945 (define_insn "*sqrtextenddfxf2_i387"
14946 [(set (match_operand:XF 0 "register_operand" "=f")
14947 (sqrt:XF (float_extend:XF
14948 (match_operand:DF 1 "register_operand" "0"))))]
14949 "TARGET_USE_FANCY_MATH_387"
14951 [(set_attr "type" "fpspc")
14952 (set_attr "mode" "XF")
14953 (set_attr "athlon_decode" "direct")])
14955 (define_insn "fpremxf4"
14956 [(set (match_operand:XF 0 "register_operand" "=f")
14957 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
14958 (match_operand:XF 3 "register_operand" "1")]
14960 (set (match_operand:XF 1 "register_operand" "=u")
14961 (unspec:XF [(match_dup 2) (match_dup 3)]
14963 (set (reg:CCFP FPSR_REG)
14964 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
14965 "TARGET_USE_FANCY_MATH_387
14966 && flag_unsafe_math_optimizations"
14968 [(set_attr "type" "fpspc")
14969 (set_attr "mode" "XF")])
14971 (define_expand "fmodsf3"
14972 [(use (match_operand:SF 0 "register_operand" ""))
14973 (use (match_operand:SF 1 "register_operand" ""))
14974 (use (match_operand:SF 2 "register_operand" ""))]
14975 "TARGET_USE_FANCY_MATH_387
14976 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
14977 && flag_unsafe_math_optimizations"
14979 rtx label = gen_label_rtx ();
14981 rtx op1 = gen_reg_rtx (XFmode);
14982 rtx op2 = gen_reg_rtx (XFmode);
14984 emit_insn(gen_extendsfxf2 (op1, operands[1]));
14985 emit_insn(gen_extendsfxf2 (op2, operands[2]));
14987 emit_label (label);
14989 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
14990 ix86_emit_fp_unordered_jump (label);
14992 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op1));
14996 (define_expand "fmoddf3"
14997 [(use (match_operand:DF 0 "register_operand" ""))
14998 (use (match_operand:DF 1 "register_operand" ""))
14999 (use (match_operand:DF 2 "register_operand" ""))]
15000 "TARGET_USE_FANCY_MATH_387
15001 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15002 && flag_unsafe_math_optimizations"
15004 rtx label = gen_label_rtx ();
15006 rtx op1 = gen_reg_rtx (XFmode);
15007 rtx op2 = gen_reg_rtx (XFmode);
15009 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15010 emit_insn (gen_extenddfxf2 (op2, operands[2]));
15012 emit_label (label);
15014 emit_insn (gen_fpremxf4 (op1, op2, op1, op2));
15015 ix86_emit_fp_unordered_jump (label);
15017 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op1));
15021 (define_expand "fmodxf3"
15022 [(use (match_operand:XF 0 "register_operand" ""))
15023 (use (match_operand:XF 1 "register_operand" ""))
15024 (use (match_operand:XF 2 "register_operand" ""))]
15025 "TARGET_USE_FANCY_MATH_387
15026 && flag_unsafe_math_optimizations"
15028 rtx label = gen_label_rtx ();
15030 emit_label (label);
15032 emit_insn (gen_fpremxf4 (operands[1], operands[2],
15033 operands[1], operands[2]));
15034 ix86_emit_fp_unordered_jump (label);
15036 emit_move_insn (operands[0], operands[1]);
15040 (define_insn "fprem1xf4"
15041 [(set (match_operand:XF 0 "register_operand" "=f")
15042 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15043 (match_operand:XF 3 "register_operand" "1")]
15045 (set (match_operand:XF 1 "register_operand" "=u")
15046 (unspec:XF [(match_dup 2) (match_dup 3)]
15048 (set (reg:CCFP FPSR_REG)
15049 (unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
15050 "TARGET_USE_FANCY_MATH_387
15051 && flag_unsafe_math_optimizations"
15053 [(set_attr "type" "fpspc")
15054 (set_attr "mode" "XF")])
15056 (define_expand "dremsf3"
15057 [(use (match_operand:SF 0 "register_operand" ""))
15058 (use (match_operand:SF 1 "register_operand" ""))
15059 (use (match_operand:SF 2 "register_operand" ""))]
15060 "TARGET_USE_FANCY_MATH_387
15061 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15062 && flag_unsafe_math_optimizations"
15064 rtx label = gen_label_rtx ();
15066 rtx op1 = gen_reg_rtx (XFmode);
15067 rtx op2 = gen_reg_rtx (XFmode);
15069 emit_insn(gen_extendsfxf2 (op1, operands[1]));
15070 emit_insn(gen_extendsfxf2 (op2, operands[2]));
15072 emit_label (label);
15074 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
15075 ix86_emit_fp_unordered_jump (label);
15077 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op1));
15081 (define_expand "dremdf3"
15082 [(use (match_operand:DF 0 "register_operand" ""))
15083 (use (match_operand:DF 1 "register_operand" ""))
15084 (use (match_operand:DF 2 "register_operand" ""))]
15085 "TARGET_USE_FANCY_MATH_387
15086 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15087 && flag_unsafe_math_optimizations"
15089 rtx label = gen_label_rtx ();
15091 rtx op1 = gen_reg_rtx (XFmode);
15092 rtx op2 = gen_reg_rtx (XFmode);
15094 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15095 emit_insn (gen_extenddfxf2 (op2, operands[2]));
15097 emit_label (label);
15099 emit_insn (gen_fprem1xf4 (op1, op2, op1, op2));
15100 ix86_emit_fp_unordered_jump (label);
15102 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op1));
15106 (define_expand "dremxf3"
15107 [(use (match_operand:XF 0 "register_operand" ""))
15108 (use (match_operand:XF 1 "register_operand" ""))
15109 (use (match_operand:XF 2 "register_operand" ""))]
15110 "TARGET_USE_FANCY_MATH_387
15111 && flag_unsafe_math_optimizations"
15113 rtx label = gen_label_rtx ();
15115 emit_label (label);
15117 emit_insn (gen_fprem1xf4 (operands[1], operands[2],
15118 operands[1], operands[2]));
15119 ix86_emit_fp_unordered_jump (label);
15121 emit_move_insn (operands[0], operands[1]);
15125 (define_insn "*sindf2"
15126 [(set (match_operand:DF 0 "register_operand" "=f")
15127 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
15128 "TARGET_USE_FANCY_MATH_387
15129 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15130 && flag_unsafe_math_optimizations"
15132 [(set_attr "type" "fpspc")
15133 (set_attr "mode" "DF")])
15135 (define_insn "*sinsf2"
15136 [(set (match_operand:SF 0 "register_operand" "=f")
15137 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
15138 "TARGET_USE_FANCY_MATH_387
15139 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15140 && flag_unsafe_math_optimizations"
15142 [(set_attr "type" "fpspc")
15143 (set_attr "mode" "SF")])
15145 (define_insn "*sinextendsfdf2"
15146 [(set (match_operand:DF 0 "register_operand" "=f")
15147 (unspec:DF [(float_extend:DF
15148 (match_operand:SF 1 "register_operand" "0"))]
15150 "TARGET_USE_FANCY_MATH_387
15151 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15152 && flag_unsafe_math_optimizations"
15154 [(set_attr "type" "fpspc")
15155 (set_attr "mode" "DF")])
15157 (define_insn "*sinxf2"
15158 [(set (match_operand:XF 0 "register_operand" "=f")
15159 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
15160 "TARGET_USE_FANCY_MATH_387
15161 && flag_unsafe_math_optimizations"
15163 [(set_attr "type" "fpspc")
15164 (set_attr "mode" "XF")])
15166 (define_insn "*cosdf2"
15167 [(set (match_operand:DF 0 "register_operand" "=f")
15168 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
15169 "TARGET_USE_FANCY_MATH_387
15170 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15171 && flag_unsafe_math_optimizations"
15173 [(set_attr "type" "fpspc")
15174 (set_attr "mode" "DF")])
15176 (define_insn "*cossf2"
15177 [(set (match_operand:SF 0 "register_operand" "=f")
15178 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
15179 "TARGET_USE_FANCY_MATH_387
15180 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15181 && flag_unsafe_math_optimizations"
15183 [(set_attr "type" "fpspc")
15184 (set_attr "mode" "SF")])
15186 (define_insn "*cosextendsfdf2"
15187 [(set (match_operand:DF 0 "register_operand" "=f")
15188 (unspec:DF [(float_extend:DF
15189 (match_operand:SF 1 "register_operand" "0"))]
15191 "TARGET_USE_FANCY_MATH_387
15192 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15193 && flag_unsafe_math_optimizations"
15195 [(set_attr "type" "fpspc")
15196 (set_attr "mode" "DF")])
15198 (define_insn "*cosxf2"
15199 [(set (match_operand:XF 0 "register_operand" "=f")
15200 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
15201 "TARGET_USE_FANCY_MATH_387
15202 && flag_unsafe_math_optimizations"
15204 [(set_attr "type" "fpspc")
15205 (set_attr "mode" "XF")])
15207 ;; With sincos pattern defined, sin and cos builtin function will be
15208 ;; expanded to sincos pattern with one of its outputs left unused.
15209 ;; Cse pass will detected, if two sincos patterns can be combined,
15210 ;; otherwise sincos pattern will be split back to sin or cos pattern,
15211 ;; depending on the unused output.
15213 (define_insn "sincosdf3"
15214 [(set (match_operand:DF 0 "register_operand" "=f")
15215 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
15216 UNSPEC_SINCOS_COS))
15217 (set (match_operand:DF 1 "register_operand" "=u")
15218 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15219 "TARGET_USE_FANCY_MATH_387
15220 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15221 && flag_unsafe_math_optimizations"
15223 [(set_attr "type" "fpspc")
15224 (set_attr "mode" "DF")])
15227 [(set (match_operand:DF 0 "register_operand" "")
15228 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15229 UNSPEC_SINCOS_COS))
15230 (set (match_operand:DF 1 "register_operand" "")
15231 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15232 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15233 && !reload_completed && !reload_in_progress"
15234 [(set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_SIN))]
15238 [(set (match_operand:DF 0 "register_operand" "")
15239 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15240 UNSPEC_SINCOS_COS))
15241 (set (match_operand:DF 1 "register_operand" "")
15242 (unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15243 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15244 && !reload_completed && !reload_in_progress"
15245 [(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_COS))]
15248 (define_insn "sincossf3"
15249 [(set (match_operand:SF 0 "register_operand" "=f")
15250 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15251 UNSPEC_SINCOS_COS))
15252 (set (match_operand:SF 1 "register_operand" "=u")
15253 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15254 "TARGET_USE_FANCY_MATH_387
15255 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15256 && flag_unsafe_math_optimizations"
15258 [(set_attr "type" "fpspc")
15259 (set_attr "mode" "SF")])
15262 [(set (match_operand:SF 0 "register_operand" "")
15263 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15264 UNSPEC_SINCOS_COS))
15265 (set (match_operand:SF 1 "register_operand" "")
15266 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15267 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15268 && !reload_completed && !reload_in_progress"
15269 [(set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_SIN))]
15273 [(set (match_operand:SF 0 "register_operand" "")
15274 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15275 UNSPEC_SINCOS_COS))
15276 (set (match_operand:SF 1 "register_operand" "")
15277 (unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15278 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15279 && !reload_completed && !reload_in_progress"
15280 [(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_COS))]
15283 (define_insn "*sincosextendsfdf3"
15284 [(set (match_operand:DF 0 "register_operand" "=f")
15285 (unspec:DF [(float_extend:DF
15286 (match_operand:SF 2 "register_operand" "0"))]
15287 UNSPEC_SINCOS_COS))
15288 (set (match_operand:DF 1 "register_operand" "=u")
15289 (unspec:DF [(float_extend:DF
15290 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15291 "TARGET_USE_FANCY_MATH_387
15292 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15293 && flag_unsafe_math_optimizations"
15295 [(set_attr "type" "fpspc")
15296 (set_attr "mode" "DF")])
15299 [(set (match_operand:DF 0 "register_operand" "")
15300 (unspec:DF [(float_extend:DF
15301 (match_operand:SF 2 "register_operand" ""))]
15302 UNSPEC_SINCOS_COS))
15303 (set (match_operand:DF 1 "register_operand" "")
15304 (unspec:DF [(float_extend:DF
15305 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15306 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15307 && !reload_completed && !reload_in_progress"
15308 [(set (match_dup 1) (unspec:DF [(float_extend:DF
15309 (match_dup 2))] UNSPEC_SIN))]
15313 [(set (match_operand:DF 0 "register_operand" "")
15314 (unspec:DF [(float_extend:DF
15315 (match_operand:SF 2 "register_operand" ""))]
15316 UNSPEC_SINCOS_COS))
15317 (set (match_operand:DF 1 "register_operand" "")
15318 (unspec:DF [(float_extend:DF
15319 (match_dup 2))] UNSPEC_SINCOS_SIN))]
15320 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15321 && !reload_completed && !reload_in_progress"
15322 [(set (match_dup 0) (unspec:DF [(float_extend:DF
15323 (match_dup 2))] UNSPEC_COS))]
15326 (define_insn "sincosxf3"
15327 [(set (match_operand:XF 0 "register_operand" "=f")
15328 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15329 UNSPEC_SINCOS_COS))
15330 (set (match_operand:XF 1 "register_operand" "=u")
15331 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15332 "TARGET_USE_FANCY_MATH_387
15333 && flag_unsafe_math_optimizations"
15335 [(set_attr "type" "fpspc")
15336 (set_attr "mode" "XF")])
15339 [(set (match_operand:XF 0 "register_operand" "")
15340 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15341 UNSPEC_SINCOS_COS))
15342 (set (match_operand:XF 1 "register_operand" "")
15343 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15344 "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
15345 && !reload_completed && !reload_in_progress"
15346 [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]
15350 [(set (match_operand:XF 0 "register_operand" "")
15351 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15352 UNSPEC_SINCOS_COS))
15353 (set (match_operand:XF 1 "register_operand" "")
15354 (unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
15355 "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
15356 && !reload_completed && !reload_in_progress"
15357 [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]
15360 (define_insn "*tandf3_1"
15361 [(set (match_operand:DF 0 "register_operand" "=f")
15362 (unspec:DF [(match_operand:DF 2 "register_operand" "0")]
15364 (set (match_operand:DF 1 "register_operand" "=u")
15365 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
15366 "TARGET_USE_FANCY_MATH_387
15367 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15368 && flag_unsafe_math_optimizations"
15370 [(set_attr "type" "fpspc")
15371 (set_attr "mode" "DF")])
15373 ;; optimize sequence: fptan
15376 ;; into fptan insn.
15379 [(parallel[(set (match_operand:DF 0 "register_operand" "")
15380 (unspec:DF [(match_operand:DF 2 "register_operand" "")]
15382 (set (match_operand:DF 1 "register_operand" "")
15383 (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])
15385 (match_operand:DF 3 "immediate_operand" ""))]
15386 "standard_80387_constant_p (operands[3]) == 2"
15387 [(parallel[(set (match_dup 0) (unspec:DF [(match_dup 2)] UNSPEC_TAN_ONE))
15388 (set (match_dup 1) (unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15391 (define_expand "tandf2"
15392 [(parallel [(set (match_dup 2)
15393 (unspec:DF [(match_operand:DF 1 "register_operand" "")]
15395 (set (match_operand:DF 0 "register_operand" "")
15396 (unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15397 "TARGET_USE_FANCY_MATH_387
15398 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15399 && flag_unsafe_math_optimizations"
15401 operands[2] = gen_reg_rtx (DFmode);
15404 (define_insn "*tansf3_1"
15405 [(set (match_operand:SF 0 "register_operand" "=f")
15406 (unspec:SF [(match_operand:SF 2 "register_operand" "0")]
15408 (set (match_operand:SF 1 "register_operand" "=u")
15409 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
15410 "TARGET_USE_FANCY_MATH_387
15411 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15412 && flag_unsafe_math_optimizations"
15414 [(set_attr "type" "fpspc")
15415 (set_attr "mode" "SF")])
15417 ;; optimize sequence: fptan
15420 ;; into fptan insn.
15423 [(parallel[(set (match_operand:SF 0 "register_operand" "")
15424 (unspec:SF [(match_operand:SF 2 "register_operand" "")]
15426 (set (match_operand:SF 1 "register_operand" "")
15427 (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])
15429 (match_operand:SF 3 "immediate_operand" ""))]
15430 "standard_80387_constant_p (operands[3]) == 2"
15431 [(parallel[(set (match_dup 0) (unspec:SF [(match_dup 2)] UNSPEC_TAN_ONE))
15432 (set (match_dup 1) (unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15435 (define_expand "tansf2"
15436 [(parallel [(set (match_dup 2)
15437 (unspec:SF [(match_operand:SF 1 "register_operand" "")]
15439 (set (match_operand:SF 0 "register_operand" "")
15440 (unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15441 "TARGET_USE_FANCY_MATH_387
15442 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15443 && flag_unsafe_math_optimizations"
15445 operands[2] = gen_reg_rtx (SFmode);
15448 (define_insn "*tanxf3_1"
15449 [(set (match_operand:XF 0 "register_operand" "=f")
15450 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15452 (set (match_operand:XF 1 "register_operand" "=u")
15453 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))]
15454 "TARGET_USE_FANCY_MATH_387
15455 && flag_unsafe_math_optimizations"
15457 [(set_attr "type" "fpspc")
15458 (set_attr "mode" "XF")])
15460 ;; optimize sequence: fptan
15463 ;; into fptan insn.
15466 [(parallel[(set (match_operand:XF 0 "register_operand" "")
15467 (unspec:XF [(match_operand:XF 2 "register_operand" "")]
15469 (set (match_operand:XF 1 "register_operand" "")
15470 (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])
15472 (match_operand:XF 3 "immediate_operand" ""))]
15473 "standard_80387_constant_p (operands[3]) == 2"
15474 [(parallel[(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_TAN_ONE))
15475 (set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))])]
15478 (define_expand "tanxf2"
15479 [(parallel [(set (match_dup 2)
15480 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
15482 (set (match_operand:XF 0 "register_operand" "")
15483 (unspec:XF [(match_dup 1)] UNSPEC_TAN_TAN))])]
15484 "TARGET_USE_FANCY_MATH_387
15485 && flag_unsafe_math_optimizations"
15487 operands[2] = gen_reg_rtx (XFmode);
15490 (define_insn "atan2df3_1"
15491 [(set (match_operand:DF 0 "register_operand" "=f")
15492 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15493 (match_operand:DF 1 "register_operand" "u")]
15495 (clobber (match_scratch:DF 3 "=1"))]
15496 "TARGET_USE_FANCY_MATH_387
15497 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15498 && flag_unsafe_math_optimizations"
15500 [(set_attr "type" "fpspc")
15501 (set_attr "mode" "DF")])
15503 (define_expand "atan2df3"
15504 [(use (match_operand:DF 0 "register_operand" ""))
15505 (use (match_operand:DF 2 "register_operand" ""))
15506 (use (match_operand:DF 1 "register_operand" ""))]
15507 "TARGET_USE_FANCY_MATH_387
15508 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15509 && flag_unsafe_math_optimizations"
15511 rtx copy = gen_reg_rtx (DFmode);
15512 emit_move_insn (copy, operands[1]);
15513 emit_insn (gen_atan2df3_1 (operands[0], copy, operands[2]));
15517 (define_expand "atandf2"
15518 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15519 (unspec:DF [(match_dup 2)
15520 (match_operand:DF 1 "register_operand" "")]
15522 (clobber (match_scratch:DF 3 ""))])]
15523 "TARGET_USE_FANCY_MATH_387
15524 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15525 && flag_unsafe_math_optimizations"
15527 operands[2] = gen_reg_rtx (DFmode);
15528 emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
15531 (define_insn "atan2sf3_1"
15532 [(set (match_operand:SF 0 "register_operand" "=f")
15533 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15534 (match_operand:SF 1 "register_operand" "u")]
15536 (clobber (match_scratch:SF 3 "=1"))]
15537 "TARGET_USE_FANCY_MATH_387
15538 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15539 && flag_unsafe_math_optimizations"
15541 [(set_attr "type" "fpspc")
15542 (set_attr "mode" "SF")])
15544 (define_expand "atan2sf3"
15545 [(use (match_operand:SF 0 "register_operand" ""))
15546 (use (match_operand:SF 2 "register_operand" ""))
15547 (use (match_operand:SF 1 "register_operand" ""))]
15548 "TARGET_USE_FANCY_MATH_387
15549 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15550 && flag_unsafe_math_optimizations"
15552 rtx copy = gen_reg_rtx (SFmode);
15553 emit_move_insn (copy, operands[1]);
15554 emit_insn (gen_atan2sf3_1 (operands[0], copy, operands[2]));
15558 (define_expand "atansf2"
15559 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15560 (unspec:SF [(match_dup 2)
15561 (match_operand:SF 1 "register_operand" "")]
15563 (clobber (match_scratch:SF 3 ""))])]
15564 "TARGET_USE_FANCY_MATH_387
15565 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15566 && flag_unsafe_math_optimizations"
15568 operands[2] = gen_reg_rtx (SFmode);
15569 emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
15572 (define_insn "atan2xf3_1"
15573 [(set (match_operand:XF 0 "register_operand" "=f")
15574 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15575 (match_operand:XF 1 "register_operand" "u")]
15577 (clobber (match_scratch:XF 3 "=1"))]
15578 "TARGET_USE_FANCY_MATH_387
15579 && flag_unsafe_math_optimizations"
15581 [(set_attr "type" "fpspc")
15582 (set_attr "mode" "XF")])
15584 (define_expand "atan2xf3"
15585 [(use (match_operand:XF 0 "register_operand" ""))
15586 (use (match_operand:XF 2 "register_operand" ""))
15587 (use (match_operand:XF 1 "register_operand" ""))]
15588 "TARGET_USE_FANCY_MATH_387
15589 && flag_unsafe_math_optimizations"
15591 rtx copy = gen_reg_rtx (XFmode);
15592 emit_move_insn (copy, operands[1]);
15593 emit_insn (gen_atan2xf3_1 (operands[0], copy, operands[2]));
15597 (define_expand "atanxf2"
15598 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15599 (unspec:XF [(match_dup 2)
15600 (match_operand:XF 1 "register_operand" "")]
15602 (clobber (match_scratch:XF 3 ""))])]
15603 "TARGET_USE_FANCY_MATH_387
15604 && flag_unsafe_math_optimizations"
15606 operands[2] = gen_reg_rtx (XFmode);
15607 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15610 (define_expand "asindf2"
15611 [(set (match_dup 2)
15612 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15613 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15614 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15615 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15616 (parallel [(set (match_dup 7)
15617 (unspec:XF [(match_dup 6) (match_dup 2)]
15619 (clobber (match_scratch:XF 8 ""))])
15620 (set (match_operand:DF 0 "register_operand" "")
15621 (float_truncate:DF (match_dup 7)))]
15622 "TARGET_USE_FANCY_MATH_387
15623 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15624 && flag_unsafe_math_optimizations"
15628 for (i=2; i<8; i++)
15629 operands[i] = gen_reg_rtx (XFmode);
15631 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15634 (define_expand "asinsf2"
15635 [(set (match_dup 2)
15636 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15637 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15638 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15639 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15640 (parallel [(set (match_dup 7)
15641 (unspec:XF [(match_dup 6) (match_dup 2)]
15643 (clobber (match_scratch:XF 8 ""))])
15644 (set (match_operand:SF 0 "register_operand" "")
15645 (float_truncate:SF (match_dup 7)))]
15646 "TARGET_USE_FANCY_MATH_387
15647 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15648 && flag_unsafe_math_optimizations"
15652 for (i=2; i<8; i++)
15653 operands[i] = gen_reg_rtx (XFmode);
15655 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15658 (define_expand "asinxf2"
15659 [(set (match_dup 2)
15660 (mult:XF (match_operand:XF 1 "register_operand" "")
15662 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15663 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15664 (parallel [(set (match_operand:XF 0 "register_operand" "")
15665 (unspec:XF [(match_dup 5) (match_dup 1)]
15667 (clobber (match_scratch:XF 6 ""))])]
15668 "TARGET_USE_FANCY_MATH_387
15669 && flag_unsafe_math_optimizations"
15673 for (i=2; i<6; i++)
15674 operands[i] = gen_reg_rtx (XFmode);
15676 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15679 (define_expand "acosdf2"
15680 [(set (match_dup 2)
15681 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15682 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15683 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15684 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15685 (parallel [(set (match_dup 7)
15686 (unspec:XF [(match_dup 2) (match_dup 6)]
15688 (clobber (match_scratch:XF 8 ""))])
15689 (set (match_operand:DF 0 "register_operand" "")
15690 (float_truncate:DF (match_dup 7)))]
15691 "TARGET_USE_FANCY_MATH_387
15692 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15693 && flag_unsafe_math_optimizations"
15697 for (i=2; i<8; i++)
15698 operands[i] = gen_reg_rtx (XFmode);
15700 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15703 (define_expand "acossf2"
15704 [(set (match_dup 2)
15705 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15706 (set (match_dup 3) (mult:XF (match_dup 2) (match_dup 2)))
15707 (set (match_dup 5) (minus:XF (match_dup 4) (match_dup 3)))
15708 (set (match_dup 6) (sqrt:XF (match_dup 5)))
15709 (parallel [(set (match_dup 7)
15710 (unspec:XF [(match_dup 2) (match_dup 6)]
15712 (clobber (match_scratch:XF 8 ""))])
15713 (set (match_operand:SF 0 "register_operand" "")
15714 (float_truncate:SF (match_dup 7)))]
15715 "TARGET_USE_FANCY_MATH_387
15716 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15717 && flag_unsafe_math_optimizations"
15721 for (i=2; i<8; i++)
15722 operands[i] = gen_reg_rtx (XFmode);
15724 emit_move_insn (operands[4], CONST1_RTX (XFmode)); /* fld1 */
15727 (define_expand "acosxf2"
15728 [(set (match_dup 2)
15729 (mult:XF (match_operand:XF 1 "register_operand" "")
15731 (set (match_dup 4) (minus:XF (match_dup 3) (match_dup 2)))
15732 (set (match_dup 5) (sqrt:XF (match_dup 4)))
15733 (parallel [(set (match_operand:XF 0 "register_operand" "")
15734 (unspec:XF [(match_dup 1) (match_dup 5)]
15736 (clobber (match_scratch:XF 6 ""))])]
15737 "TARGET_USE_FANCY_MATH_387
15738 && flag_unsafe_math_optimizations"
15742 for (i=2; i<6; i++)
15743 operands[i] = gen_reg_rtx (XFmode);
15745 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15748 (define_insn "fyl2x_xf3"
15749 [(set (match_operand:XF 0 "register_operand" "=f")
15750 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15751 (match_operand:XF 1 "register_operand" "u")]
15753 (clobber (match_scratch:XF 3 "=1"))]
15754 "TARGET_USE_FANCY_MATH_387
15755 && flag_unsafe_math_optimizations"
15757 [(set_attr "type" "fpspc")
15758 (set_attr "mode" "XF")])
15760 (define_expand "logsf2"
15761 [(set (match_dup 2)
15762 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15763 (parallel [(set (match_dup 4)
15764 (unspec:XF [(match_dup 2)
15765 (match_dup 3)] UNSPEC_FYL2X))
15766 (clobber (match_scratch:XF 5 ""))])
15767 (set (match_operand:SF 0 "register_operand" "")
15768 (float_truncate:SF (match_dup 4)))]
15769 "TARGET_USE_FANCY_MATH_387
15770 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15771 && flag_unsafe_math_optimizations"
15775 operands[2] = gen_reg_rtx (XFmode);
15776 operands[3] = gen_reg_rtx (XFmode);
15777 operands[4] = gen_reg_rtx (XFmode);
15779 temp = standard_80387_constant_rtx (4); /* fldln2 */
15780 emit_move_insn (operands[3], temp);
15783 (define_expand "logdf2"
15784 [(set (match_dup 2)
15785 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15786 (parallel [(set (match_dup 4)
15787 (unspec:XF [(match_dup 2)
15788 (match_dup 3)] UNSPEC_FYL2X))
15789 (clobber (match_scratch:XF 5 ""))])
15790 (set (match_operand:DF 0 "register_operand" "")
15791 (float_truncate:DF (match_dup 4)))]
15792 "TARGET_USE_FANCY_MATH_387
15793 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15794 && flag_unsafe_math_optimizations"
15798 operands[2] = gen_reg_rtx (XFmode);
15799 operands[3] = gen_reg_rtx (XFmode);
15800 operands[4] = gen_reg_rtx (XFmode);
15802 temp = standard_80387_constant_rtx (4); /* fldln2 */
15803 emit_move_insn (operands[3], temp);
15806 (define_expand "logxf2"
15807 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15808 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15809 (match_dup 2)] UNSPEC_FYL2X))
15810 (clobber (match_scratch:XF 3 ""))])]
15811 "TARGET_USE_FANCY_MATH_387
15812 && flag_unsafe_math_optimizations"
15816 operands[2] = gen_reg_rtx (XFmode);
15817 temp = standard_80387_constant_rtx (4); /* fldln2 */
15818 emit_move_insn (operands[2], temp);
15821 (define_expand "log10sf2"
15822 [(set (match_dup 2)
15823 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15824 (parallel [(set (match_dup 4)
15825 (unspec:XF [(match_dup 2)
15826 (match_dup 3)] UNSPEC_FYL2X))
15827 (clobber (match_scratch:XF 5 ""))])
15828 (set (match_operand:SF 0 "register_operand" "")
15829 (float_truncate:SF (match_dup 4)))]
15830 "TARGET_USE_FANCY_MATH_387
15831 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15832 && flag_unsafe_math_optimizations"
15836 operands[2] = gen_reg_rtx (XFmode);
15837 operands[3] = gen_reg_rtx (XFmode);
15838 operands[4] = gen_reg_rtx (XFmode);
15840 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15841 emit_move_insn (operands[3], temp);
15844 (define_expand "log10df2"
15845 [(set (match_dup 2)
15846 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15847 (parallel [(set (match_dup 4)
15848 (unspec:XF [(match_dup 2)
15849 (match_dup 3)] UNSPEC_FYL2X))
15850 (clobber (match_scratch:XF 5 ""))])
15851 (set (match_operand:DF 0 "register_operand" "")
15852 (float_truncate:DF (match_dup 4)))]
15853 "TARGET_USE_FANCY_MATH_387
15854 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15855 && flag_unsafe_math_optimizations"
15859 operands[2] = gen_reg_rtx (XFmode);
15860 operands[3] = gen_reg_rtx (XFmode);
15861 operands[4] = gen_reg_rtx (XFmode);
15863 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15864 emit_move_insn (operands[3], temp);
15867 (define_expand "log10xf2"
15868 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15869 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15870 (match_dup 2)] UNSPEC_FYL2X))
15871 (clobber (match_scratch:XF 3 ""))])]
15872 "TARGET_USE_FANCY_MATH_387
15873 && flag_unsafe_math_optimizations"
15877 operands[2] = gen_reg_rtx (XFmode);
15878 temp = standard_80387_constant_rtx (3); /* fldlg2 */
15879 emit_move_insn (operands[2], temp);
15882 (define_expand "log2sf2"
15883 [(set (match_dup 2)
15884 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15885 (parallel [(set (match_dup 4)
15886 (unspec:XF [(match_dup 2)
15887 (match_dup 3)] UNSPEC_FYL2X))
15888 (clobber (match_scratch:XF 5 ""))])
15889 (set (match_operand:SF 0 "register_operand" "")
15890 (float_truncate:SF (match_dup 4)))]
15891 "TARGET_USE_FANCY_MATH_387
15892 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15893 && flag_unsafe_math_optimizations"
15895 operands[2] = gen_reg_rtx (XFmode);
15896 operands[3] = gen_reg_rtx (XFmode);
15897 operands[4] = gen_reg_rtx (XFmode);
15899 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15902 (define_expand "log2df2"
15903 [(set (match_dup 2)
15904 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15905 (parallel [(set (match_dup 4)
15906 (unspec:XF [(match_dup 2)
15907 (match_dup 3)] UNSPEC_FYL2X))
15908 (clobber (match_scratch:XF 5 ""))])
15909 (set (match_operand:DF 0 "register_operand" "")
15910 (float_truncate:DF (match_dup 4)))]
15911 "TARGET_USE_FANCY_MATH_387
15912 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15913 && flag_unsafe_math_optimizations"
15915 operands[2] = gen_reg_rtx (XFmode);
15916 operands[3] = gen_reg_rtx (XFmode);
15917 operands[4] = gen_reg_rtx (XFmode);
15919 emit_move_insn (operands[3], CONST1_RTX (XFmode)); /* fld1 */
15922 (define_expand "log2xf2"
15923 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15924 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15925 (match_dup 2)] UNSPEC_FYL2X))
15926 (clobber (match_scratch:XF 3 ""))])]
15927 "TARGET_USE_FANCY_MATH_387
15928 && flag_unsafe_math_optimizations"
15930 operands[2] = gen_reg_rtx (XFmode);
15931 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15934 (define_insn "fyl2xp1_xf3"
15935 [(set (match_operand:XF 0 "register_operand" "=f")
15936 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15937 (match_operand:XF 1 "register_operand" "u")]
15939 (clobber (match_scratch:XF 3 "=1"))]
15940 "TARGET_USE_FANCY_MATH_387
15941 && flag_unsafe_math_optimizations"
15943 [(set_attr "type" "fpspc")
15944 (set_attr "mode" "XF")])
15946 (define_expand "log1psf2"
15947 [(use (match_operand:SF 0 "register_operand" ""))
15948 (use (match_operand:SF 1 "register_operand" ""))]
15949 "TARGET_USE_FANCY_MATH_387
15950 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
15951 && flag_unsafe_math_optimizations"
15953 rtx op0 = gen_reg_rtx (XFmode);
15954 rtx op1 = gen_reg_rtx (XFmode);
15956 emit_insn (gen_extendsfxf2 (op1, operands[1]));
15957 ix86_emit_i387_log1p (op0, op1);
15958 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
15962 (define_expand "log1pdf2"
15963 [(use (match_operand:DF 0 "register_operand" ""))
15964 (use (match_operand:DF 1 "register_operand" ""))]
15965 "TARGET_USE_FANCY_MATH_387
15966 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
15967 && flag_unsafe_math_optimizations"
15969 rtx op0 = gen_reg_rtx (XFmode);
15970 rtx op1 = gen_reg_rtx (XFmode);
15972 emit_insn (gen_extenddfxf2 (op1, operands[1]));
15973 ix86_emit_i387_log1p (op0, op1);
15974 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
15978 (define_expand "log1pxf2"
15979 [(use (match_operand:XF 0 "register_operand" ""))
15980 (use (match_operand:XF 1 "register_operand" ""))]
15981 "TARGET_USE_FANCY_MATH_387
15982 && flag_unsafe_math_optimizations"
15984 ix86_emit_i387_log1p (operands[0], operands[1]);
15988 (define_insn "*fxtractxf3"
15989 [(set (match_operand:XF 0 "register_operand" "=f")
15990 (unspec:XF [(match_operand:XF 2 "register_operand" "0")]
15991 UNSPEC_XTRACT_FRACT))
15992 (set (match_operand:XF 1 "register_operand" "=u")
15993 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
15994 "TARGET_USE_FANCY_MATH_387
15995 && flag_unsafe_math_optimizations"
15997 [(set_attr "type" "fpspc")
15998 (set_attr "mode" "XF")])
16000 (define_expand "logbsf2"
16001 [(set (match_dup 2)
16002 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16003 (parallel [(set (match_dup 3)
16004 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
16006 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
16007 (set (match_operand:SF 0 "register_operand" "")
16008 (float_truncate:SF (match_dup 4)))]
16009 "TARGET_USE_FANCY_MATH_387
16010 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
16011 && flag_unsafe_math_optimizations"
16013 operands[2] = gen_reg_rtx (XFmode);
16014 operands[3] = gen_reg_rtx (XFmode);
16015 operands[4] = gen_reg_rtx (XFmode);
16018 (define_expand "logbdf2"
16019 [(set (match_dup 2)
16020 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16021 (parallel [(set (match_dup 3)
16022 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_FRACT))
16024 (unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
16025 (set (match_operand:DF 0 "register_operand" "")
16026 (float_truncate:DF (match_dup 4)))]
16027 "TARGET_USE_FANCY_MATH_387
16028 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
16029 && flag_unsafe_math_optimizations"
16031 operands[2] = gen_reg_rtx (XFmode);
16032 operands[3] = gen_reg_rtx (XFmode);
16033 operands[4] = gen_reg_rtx (XFmode);
16036 (define_expand "logbxf2"
16037 [(parallel [(set (match_dup 2)
16038 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
16039 UNSPEC_XTRACT_FRACT))
16040 (set (match_operand:XF 0 "register_operand" "")
16041 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
16042 "TARGET_USE_FANCY_MATH_387
16043 && flag_unsafe_math_optimizations"
16045 operands[2] = gen_reg_rtx (XFmode);
16048 (define_expand "ilogbsi2"
16049 [(parallel [(set (match_dup 2)
16050 (unspec:XF [(match_operand:XF 1 "register_operand" "")]
16051 UNSPEC_XTRACT_FRACT))
16052 (set (match_operand:XF 3 "register_operand" "")
16053 (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])
16054 (parallel [(set (match_operand:SI 0 "register_operand" "")
16055 (fix:SI (match_dup 3)))
16056 (clobber (reg:CC FLAGS_REG))])]
16057 "TARGET_USE_FANCY_MATH_387
16058 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
16059 && flag_unsafe_math_optimizations"
16061 operands[2] = gen_reg_rtx (XFmode);
16062 operands[3] = gen_reg_rtx (XFmode);
16065 (define_insn "*f2xm1xf2"
16066 [(set (match_operand:XF 0 "register_operand" "=f")
16067 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16069 "TARGET_USE_FANCY_MATH_387
16070 && flag_unsafe_math_optimizations"
16072 [(set_attr "type" "fpspc")
16073 (set_attr "mode" "XF")])
16075 (define_insn "*fscalexf4"
16076 [(set (match_operand:XF 0 "register_operand" "=f")
16077 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
16078 (match_operand:XF 3 "register_operand" "1")]
16079 UNSPEC_FSCALE_FRACT))
16080 (set (match_operand:XF 1 "register_operand" "=u")
16081 (unspec:XF [(match_dup 2) (match_dup 3)]
16082 UNSPEC_FSCALE_EXP))]
16083 "TARGET_USE_FANCY_MATH_387
16084 && flag_unsafe_math_optimizations"
16086 [(set_attr "type" "fpspc")
16087 (set_attr "mode" "XF")])
16089 (define_expand "expsf2"
16090 [(set (match_dup 2)
16091 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16092 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16093 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16094 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16095 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16096 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16097 (parallel [(set (match_dup 10)
16098 (unspec:XF [(match_dup 9) (match_dup 5)]
16099 UNSPEC_FSCALE_FRACT))
16100 (set (match_dup 11)
16101 (unspec:XF [(match_dup 9) (match_dup 5)]
16102 UNSPEC_FSCALE_EXP))])
16103 (set (match_operand:SF 0 "register_operand" "")
16104 (float_truncate:SF (match_dup 10)))]
16105 "TARGET_USE_FANCY_MATH_387
16106 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
16107 && flag_unsafe_math_optimizations"
16112 for (i=2; i<12; i++)
16113 operands[i] = gen_reg_rtx (XFmode);
16114 temp = standard_80387_constant_rtx (5); /* fldl2e */
16115 emit_move_insn (operands[3], temp);
16116 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16119 (define_expand "expdf2"
16120 [(set (match_dup 2)
16121 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16122 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16123 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16124 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16125 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16126 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16127 (parallel [(set (match_dup 10)
16128 (unspec:XF [(match_dup 9) (match_dup 5)]
16129 UNSPEC_FSCALE_FRACT))
16130 (set (match_dup 11)
16131 (unspec:XF [(match_dup 9) (match_dup 5)]
16132 UNSPEC_FSCALE_EXP))])
16133 (set (match_operand:DF 0 "register_operand" "")
16134 (float_truncate:DF (match_dup 10)))]
16135 "TARGET_USE_FANCY_MATH_387
16136 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
16137 && flag_unsafe_math_optimizations"
16142 for (i=2; i<12; i++)
16143 operands[i] = gen_reg_rtx (XFmode);
16144 temp = standard_80387_constant_rtx (5); /* fldl2e */
16145 emit_move_insn (operands[3], temp);
16146 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16149 (define_expand "expxf2"
16150 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16152 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16153 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16154 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16155 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
16156 (parallel [(set (match_operand:XF 0 "register_operand" "")
16157 (unspec:XF [(match_dup 8) (match_dup 4)]
16158 UNSPEC_FSCALE_FRACT))
16160 (unspec:XF [(match_dup 8) (match_dup 4)]
16161 UNSPEC_FSCALE_EXP))])]
16162 "TARGET_USE_FANCY_MATH_387
16163 && flag_unsafe_math_optimizations"
16168 for (i=2; i<10; i++)
16169 operands[i] = gen_reg_rtx (XFmode);
16170 temp = standard_80387_constant_rtx (5); /* fldl2e */
16171 emit_move_insn (operands[2], temp);
16172 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
16175 (define_expand "exp10sf2"
16176 [(set (match_dup 2)
16177 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16178 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16179 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16180 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16181 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16182 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16183 (parallel [(set (match_dup 10)
16184 (unspec:XF [(match_dup 9) (match_dup 5)]
16185 UNSPEC_FSCALE_FRACT))
16186 (set (match_dup 11)
16187 (unspec:XF [(match_dup 9) (match_dup 5)]
16188 UNSPEC_FSCALE_EXP))])
16189 (set (match_operand:SF 0 "register_operand" "")
16190 (float_truncate:SF (match_dup 10)))]
16191 "TARGET_USE_FANCY_MATH_387
16192 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
16193 && flag_unsafe_math_optimizations"
16198 for (i=2; i<12; i++)
16199 operands[i] = gen_reg_rtx (XFmode);
16200 temp = standard_80387_constant_rtx (6); /* fldl2t */
16201 emit_move_insn (operands[3], temp);
16202 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16205 (define_expand "exp10df2"
16206 [(set (match_dup 2)
16207 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16208 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16209 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16210 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16211 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16212 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
16213 (parallel [(set (match_dup 10)
16214 (unspec:XF [(match_dup 9) (match_dup 5)]
16215 UNSPEC_FSCALE_FRACT))
16216 (set (match_dup 11)
16217 (unspec:XF [(match_dup 9) (match_dup 5)]
16218 UNSPEC_FSCALE_EXP))])
16219 (set (match_operand:DF 0 "register_operand" "")
16220 (float_truncate:DF (match_dup 10)))]
16221 "TARGET_USE_FANCY_MATH_387
16222 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
16223 && flag_unsafe_math_optimizations"
16228 for (i=2; i<12; i++)
16229 operands[i] = gen_reg_rtx (XFmode);
16230 temp = standard_80387_constant_rtx (6); /* fldl2t */
16231 emit_move_insn (operands[3], temp);
16232 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
16235 (define_expand "exp10xf2"
16236 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16238 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16239 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16240 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16241 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
16242 (parallel [(set (match_operand:XF 0 "register_operand" "")
16243 (unspec:XF [(match_dup 8) (match_dup 4)]
16244 UNSPEC_FSCALE_FRACT))
16246 (unspec:XF [(match_dup 8) (match_dup 4)]
16247 UNSPEC_FSCALE_EXP))])]
16248 "TARGET_USE_FANCY_MATH_387
16249 && flag_unsafe_math_optimizations"
16254 for (i=2; i<10; i++)
16255 operands[i] = gen_reg_rtx (XFmode);
16256 temp = standard_80387_constant_rtx (6); /* fldl2t */
16257 emit_move_insn (operands[2], temp);
16258 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
16261 (define_expand "exp2sf2"
16262 [(set (match_dup 2)
16263 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16264 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16265 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16266 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16267 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16268 (parallel [(set (match_dup 8)
16269 (unspec:XF [(match_dup 7) (match_dup 3)]
16270 UNSPEC_FSCALE_FRACT))
16272 (unspec:XF [(match_dup 7) (match_dup 3)]
16273 UNSPEC_FSCALE_EXP))])
16274 (set (match_operand:SF 0 "register_operand" "")
16275 (float_truncate:SF (match_dup 8)))]
16276 "TARGET_USE_FANCY_MATH_387
16277 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
16278 && flag_unsafe_math_optimizations"
16282 for (i=2; i<10; i++)
16283 operands[i] = gen_reg_rtx (XFmode);
16284 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16287 (define_expand "exp2df2"
16288 [(set (match_dup 2)
16289 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16290 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16291 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16292 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16293 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16294 (parallel [(set (match_dup 8)
16295 (unspec:XF [(match_dup 7) (match_dup 3)]
16296 UNSPEC_FSCALE_FRACT))
16298 (unspec:XF [(match_dup 7) (match_dup 3)]
16299 UNSPEC_FSCALE_EXP))])
16300 (set (match_operand:DF 0 "register_operand" "")
16301 (float_truncate:DF (match_dup 8)))]
16302 "TARGET_USE_FANCY_MATH_387
16303 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
16304 && flag_unsafe_math_optimizations"
16308 for (i=2; i<10; i++)
16309 operands[i] = gen_reg_rtx (XFmode);
16310 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16313 (define_expand "exp2xf2"
16314 [(set (match_dup 2) (match_operand:XF 1 "register_operand" ""))
16315 (set (match_dup 3) (unspec:XF [(match_dup 2)] UNSPEC_FRNDINT))
16316 (set (match_dup 4) (minus:XF (match_dup 2) (match_dup 3)))
16317 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_F2XM1))
16318 (set (match_dup 7) (plus:XF (match_dup 5) (match_dup 6)))
16319 (parallel [(set (match_operand:XF 0 "register_operand" "")
16320 (unspec:XF [(match_dup 7) (match_dup 3)]
16321 UNSPEC_FSCALE_FRACT))
16323 (unspec:XF [(match_dup 7) (match_dup 3)]
16324 UNSPEC_FSCALE_EXP))])]
16325 "TARGET_USE_FANCY_MATH_387
16326 && flag_unsafe_math_optimizations"
16330 for (i=2; i<9; i++)
16331 operands[i] = gen_reg_rtx (XFmode);
16332 emit_move_insn (operands[6], CONST1_RTX (XFmode)); /* fld1 */
16335 (define_expand "expm1df2"
16336 [(set (match_dup 2)
16337 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16338 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16339 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16340 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16341 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16342 (parallel [(set (match_dup 8)
16343 (unspec:XF [(match_dup 7) (match_dup 5)]
16344 UNSPEC_FSCALE_FRACT))
16346 (unspec:XF [(match_dup 7) (match_dup 5)]
16347 UNSPEC_FSCALE_EXP))])
16348 (parallel [(set (match_dup 11)
16349 (unspec:XF [(match_dup 10) (match_dup 9)]
16350 UNSPEC_FSCALE_FRACT))
16351 (set (match_dup 12)
16352 (unspec:XF [(match_dup 10) (match_dup 9)]
16353 UNSPEC_FSCALE_EXP))])
16354 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16355 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16356 (set (match_operand:DF 0 "register_operand" "")
16357 (float_truncate:DF (match_dup 14)))]
16358 "TARGET_USE_FANCY_MATH_387
16359 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
16360 && flag_unsafe_math_optimizations"
16365 for (i=2; i<15; i++)
16366 operands[i] = gen_reg_rtx (XFmode);
16367 temp = standard_80387_constant_rtx (5); /* fldl2e */
16368 emit_move_insn (operands[3], temp);
16369 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16372 (define_expand "expm1sf2"
16373 [(set (match_dup 2)
16374 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16375 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
16376 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
16377 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
16378 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
16379 (parallel [(set (match_dup 8)
16380 (unspec:XF [(match_dup 7) (match_dup 5)]
16381 UNSPEC_FSCALE_FRACT))
16383 (unspec:XF [(match_dup 7) (match_dup 5)]
16384 UNSPEC_FSCALE_EXP))])
16385 (parallel [(set (match_dup 11)
16386 (unspec:XF [(match_dup 10) (match_dup 9)]
16387 UNSPEC_FSCALE_FRACT))
16388 (set (match_dup 12)
16389 (unspec:XF [(match_dup 10) (match_dup 9)]
16390 UNSPEC_FSCALE_EXP))])
16391 (set (match_dup 13) (minus:XF (match_dup 11) (match_dup 10)))
16392 (set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
16393 (set (match_operand:SF 0 "register_operand" "")
16394 (float_truncate:SF (match_dup 14)))]
16395 "TARGET_USE_FANCY_MATH_387
16396 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
16397 && flag_unsafe_math_optimizations"
16402 for (i=2; i<15; i++)
16403 operands[i] = gen_reg_rtx (XFmode);
16404 temp = standard_80387_constant_rtx (5); /* fldl2e */
16405 emit_move_insn (operands[3], temp);
16406 emit_move_insn (operands[10], CONST1_RTX (XFmode)); /* fld1 */
16409 (define_expand "expm1xf2"
16410 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
16412 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
16413 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
16414 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
16415 (parallel [(set (match_dup 7)
16416 (unspec:XF [(match_dup 6) (match_dup 4)]
16417 UNSPEC_FSCALE_FRACT))
16419 (unspec:XF [(match_dup 6) (match_dup 4)]
16420 UNSPEC_FSCALE_EXP))])
16421 (parallel [(set (match_dup 10)
16422 (unspec:XF [(match_dup 9) (match_dup 8)]
16423 UNSPEC_FSCALE_FRACT))
16424 (set (match_dup 11)
16425 (unspec:XF [(match_dup 9) (match_dup 8)]
16426 UNSPEC_FSCALE_EXP))])
16427 (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
16428 (set (match_operand:XF 0 "register_operand" "")
16429 (plus:XF (match_dup 12) (match_dup 7)))]
16430 "TARGET_USE_FANCY_MATH_387
16431 && flag_unsafe_math_optimizations"
16436 for (i=2; i<13; i++)
16437 operands[i] = gen_reg_rtx (XFmode);
16438 temp = standard_80387_constant_rtx (5); /* fldl2e */
16439 emit_move_insn (operands[2], temp);
16440 emit_move_insn (operands[9], CONST1_RTX (XFmode)); /* fld1 */
16443 (define_expand "ldexpdf3"
16444 [(set (match_dup 3)
16445 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
16447 (float:XF (match_operand:SI 2 "register_operand" "")))
16448 (parallel [(set (match_dup 5)
16449 (unspec:XF [(match_dup 3) (match_dup 4)]
16450 UNSPEC_FSCALE_FRACT))
16452 (unspec:XF [(match_dup 3) (match_dup 4)]
16453 UNSPEC_FSCALE_EXP))])
16454 (set (match_operand:DF 0 "register_operand" "")
16455 (float_truncate:DF (match_dup 5)))]
16456 "TARGET_USE_FANCY_MATH_387
16457 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
16458 && flag_unsafe_math_optimizations"
16462 for (i=3; i<7; i++)
16463 operands[i] = gen_reg_rtx (XFmode);
16466 (define_expand "ldexpsf3"
16467 [(set (match_dup 3)
16468 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
16470 (float:XF (match_operand:SI 2 "register_operand" "")))
16471 (parallel [(set (match_dup 5)
16472 (unspec:XF [(match_dup 3) (match_dup 4)]
16473 UNSPEC_FSCALE_FRACT))
16475 (unspec:XF [(match_dup 3) (match_dup 4)]
16476 UNSPEC_FSCALE_EXP))])
16477 (set (match_operand:SF 0 "register_operand" "")
16478 (float_truncate:SF (match_dup 5)))]
16479 "TARGET_USE_FANCY_MATH_387
16480 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
16481 && flag_unsafe_math_optimizations"
16485 for (i=3; i<7; i++)
16486 operands[i] = gen_reg_rtx (XFmode);
16489 (define_expand "ldexpxf3"
16490 [(set (match_dup 3)
16491 (float:XF (match_operand:SI 2 "register_operand" "")))
16492 (parallel [(set (match_operand:XF 0 " register_operand" "")
16493 (unspec:XF [(match_operand:XF 1 "register_operand" "")
16495 UNSPEC_FSCALE_FRACT))
16497 (unspec:XF [(match_dup 1) (match_dup 3)]
16498 UNSPEC_FSCALE_EXP))])]
16499 "TARGET_USE_FANCY_MATH_387
16500 && flag_unsafe_math_optimizations"
16504 for (i=3; i<5; i++)
16505 operands[i] = gen_reg_rtx (XFmode);
16509 (define_insn "frndintxf2"
16510 [(set (match_operand:XF 0 "register_operand" "=f")
16511 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16513 "TARGET_USE_FANCY_MATH_387
16514 && flag_unsafe_math_optimizations"
16516 [(set_attr "type" "fpspc")
16517 (set_attr "mode" "XF")])
16519 (define_expand "rintdf2"
16520 [(use (match_operand:DF 0 "register_operand" ""))
16521 (use (match_operand:DF 1 "register_operand" ""))]
16522 "TARGET_USE_FANCY_MATH_387
16523 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
16524 && flag_unsafe_math_optimizations"
16526 rtx op0 = gen_reg_rtx (XFmode);
16527 rtx op1 = gen_reg_rtx (XFmode);
16529 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16530 emit_insn (gen_frndintxf2 (op0, op1));
16532 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16536 (define_expand "rintsf2"
16537 [(use (match_operand:SF 0 "register_operand" ""))
16538 (use (match_operand:SF 1 "register_operand" ""))]
16539 "TARGET_USE_FANCY_MATH_387
16540 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
16541 && flag_unsafe_math_optimizations"
16543 rtx op0 = gen_reg_rtx (XFmode);
16544 rtx op1 = gen_reg_rtx (XFmode);
16546 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16547 emit_insn (gen_frndintxf2 (op0, op1));
16549 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16553 (define_expand "rintxf2"
16554 [(use (match_operand:XF 0 "register_operand" ""))
16555 (use (match_operand:XF 1 "register_operand" ""))]
16556 "TARGET_USE_FANCY_MATH_387
16557 && flag_unsafe_math_optimizations"
16559 emit_insn (gen_frndintxf2 (operands[0], operands[1]));
16563 (define_insn_and_split "*fistdi2_1"
16564 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
16565 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
16567 "TARGET_USE_FANCY_MATH_387
16568 && flag_unsafe_math_optimizations
16569 && !(reload_completed || reload_in_progress)"
16574 if (memory_operand (operands[0], VOIDmode))
16575 emit_insn (gen_fistdi2 (operands[0], operands[1]));
16578 operands[2] = assign_386_stack_local (DImode, SLOT_TEMP);
16579 emit_insn (gen_fistdi2_with_temp (operands[0], operands[1],
16584 [(set_attr "type" "fpspc")
16585 (set_attr "mode" "DI")])
16587 (define_insn "fistdi2"
16588 [(set (match_operand:DI 0 "memory_operand" "=m")
16589 (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
16591 (clobber (match_scratch:XF 2 "=&1f"))]
16592 "TARGET_USE_FANCY_MATH_387
16593 && flag_unsafe_math_optimizations"
16594 "* return output_fix_trunc (insn, operands, 0);"
16595 [(set_attr "type" "fpspc")
16596 (set_attr "mode" "DI")])
16598 (define_insn "fistdi2_with_temp"
16599 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
16600 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
16602 (clobber (match_operand:DI 2 "memory_operand" "=m,m"))
16603 (clobber (match_scratch:XF 3 "=&1f,&1f"))]
16604 "TARGET_USE_FANCY_MATH_387
16605 && flag_unsafe_math_optimizations"
16607 [(set_attr "type" "fpspc")
16608 (set_attr "mode" "DI")])
16611 [(set (match_operand:DI 0 "register_operand" "")
16612 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
16614 (clobber (match_operand:DI 2 "memory_operand" ""))
16615 (clobber (match_scratch 3 ""))]
16617 [(parallel [(set (match_dup 2) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
16618 (clobber (match_dup 3))])
16619 (set (match_dup 0) (match_dup 2))]
16623 [(set (match_operand:DI 0 "memory_operand" "")
16624 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
16626 (clobber (match_operand:DI 2 "memory_operand" ""))
16627 (clobber (match_scratch 3 ""))]
16629 [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
16630 (clobber (match_dup 3))])]
16633 (define_insn_and_split "*fist<mode>2_1"
16634 [(set (match_operand:X87MODEI12 0 "register_operand" "=r")
16635 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
16637 "TARGET_USE_FANCY_MATH_387
16638 && flag_unsafe_math_optimizations
16639 && !(reload_completed || reload_in_progress)"
16644 operands[2] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
16645 emit_insn (gen_fist<mode>2_with_temp (operands[0], operands[1],
16649 [(set_attr "type" "fpspc")
16650 (set_attr "mode" "<MODE>")])
16652 (define_insn "fist<mode>2"
16653 [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
16654 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
16656 "TARGET_USE_FANCY_MATH_387
16657 && flag_unsafe_math_optimizations"
16658 "* return output_fix_trunc (insn, operands, 0);"
16659 [(set_attr "type" "fpspc")
16660 (set_attr "mode" "<MODE>")])
16662 (define_insn "fist<mode>2_with_temp"
16663 [(set (match_operand:X87MODEI12 0 "register_operand" "=r")
16664 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
16666 (clobber (match_operand:X87MODEI12 2 "memory_operand" "=m"))]
16667 "TARGET_USE_FANCY_MATH_387
16668 && flag_unsafe_math_optimizations"
16670 [(set_attr "type" "fpspc")
16671 (set_attr "mode" "<MODE>")])
16674 [(set (match_operand:X87MODEI12 0 "register_operand" "")
16675 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
16677 (clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
16679 [(set (match_dup 2) (unspec:X87MODEI12 [(match_dup 1)]
16681 (set (match_dup 0) (match_dup 2))]
16685 [(set (match_operand:X87MODEI12 0 "memory_operand" "")
16686 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
16688 (clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
16690 [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
16694 (define_expand "lrint<mode>2"
16695 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
16696 (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
16698 "TARGET_USE_FANCY_MATH_387
16699 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
16700 && flag_unsafe_math_optimizations"
16703 ;; Rounding mode control word calculation could clobber FLAGS_REG.
16704 (define_insn_and_split "frndintxf2_floor"
16705 [(set (match_operand:XF 0 "register_operand" "=f")
16706 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16707 UNSPEC_FRNDINT_FLOOR))
16708 (clobber (reg:CC FLAGS_REG))]
16709 "TARGET_USE_FANCY_MATH_387
16710 && flag_unsafe_math_optimizations
16711 && !(reload_completed || reload_in_progress)"
16716 ix86_optimize_mode_switching[I387_FLOOR] = 1;
16718 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
16719 operands[3] = assign_386_stack_local (HImode, SLOT_CW_FLOOR);
16721 emit_insn (gen_frndintxf2_floor_i387 (operands[0], operands[1],
16722 operands[2], operands[3]));
16725 [(set_attr "type" "frndint")
16726 (set_attr "i387_cw" "floor")
16727 (set_attr "mode" "XF")])
16729 (define_insn "frndintxf2_floor_i387"
16730 [(set (match_operand:XF 0 "register_operand" "=f")
16731 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16732 UNSPEC_FRNDINT_FLOOR))
16733 (use (match_operand:HI 2 "memory_operand" "m"))
16734 (use (match_operand:HI 3 "memory_operand" "m"))]
16735 "TARGET_USE_FANCY_MATH_387
16736 && flag_unsafe_math_optimizations"
16737 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16738 [(set_attr "type" "frndint")
16739 (set_attr "i387_cw" "floor")
16740 (set_attr "mode" "XF")])
16742 (define_expand "floorxf2"
16743 [(use (match_operand:XF 0 "register_operand" ""))
16744 (use (match_operand:XF 1 "register_operand" ""))]
16745 "TARGET_USE_FANCY_MATH_387
16746 && flag_unsafe_math_optimizations"
16748 emit_insn (gen_frndintxf2_floor (operands[0], operands[1]));
16752 (define_expand "floordf2"
16753 [(use (match_operand:DF 0 "register_operand" ""))
16754 (use (match_operand:DF 1 "register_operand" ""))]
16755 "TARGET_USE_FANCY_MATH_387
16756 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
16757 && flag_unsafe_math_optimizations"
16759 rtx op0 = gen_reg_rtx (XFmode);
16760 rtx op1 = gen_reg_rtx (XFmode);
16762 emit_insn (gen_extenddfxf2 (op1, operands[1]));
16763 emit_insn (gen_frndintxf2_floor (op0, op1));
16765 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
16769 (define_expand "floorsf2"
16770 [(use (match_operand:SF 0 "register_operand" ""))
16771 (use (match_operand:SF 1 "register_operand" ""))]
16772 "TARGET_USE_FANCY_MATH_387
16773 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
16774 && flag_unsafe_math_optimizations"
16776 rtx op0 = gen_reg_rtx (XFmode);
16777 rtx op1 = gen_reg_rtx (XFmode);
16779 emit_insn (gen_extendsfxf2 (op1, operands[1]));
16780 emit_insn (gen_frndintxf2_floor (op0, op1));
16782 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
16786 (define_insn_and_split "*fist<mode>2_floor_1"
16787 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
16788 (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "f,f")]
16789 UNSPEC_FIST_FLOOR))
16790 (clobber (reg:CC FLAGS_REG))]
16791 "TARGET_USE_FANCY_MATH_387
16792 && flag_unsafe_math_optimizations
16793 && !(reload_completed || reload_in_progress)"
16798 ix86_optimize_mode_switching[I387_FLOOR] = 1;
16800 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
16801 operands[3] = assign_386_stack_local (HImode, SLOT_CW_FLOOR);
16802 if (memory_operand (operands[0], VOIDmode))
16803 emit_insn (gen_fist<mode>2_floor (operands[0], operands[1],
16804 operands[2], operands[3]));
16807 operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
16808 emit_insn (gen_fist<mode>2_floor_with_temp (operands[0], operands[1],
16809 operands[2], operands[3],
16814 [(set_attr "type" "fistp")
16815 (set_attr "i387_cw" "floor")
16816 (set_attr "mode" "<MODE>")])
16818 (define_insn "fistdi2_floor"
16819 [(set (match_operand:DI 0 "memory_operand" "=m")
16820 (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
16821 UNSPEC_FIST_FLOOR))
16822 (use (match_operand:HI 2 "memory_operand" "m"))
16823 (use (match_operand:HI 3 "memory_operand" "m"))
16824 (clobber (match_scratch:XF 4 "=&1f"))]
16825 "TARGET_USE_FANCY_MATH_387
16826 && flag_unsafe_math_optimizations"
16827 "* return output_fix_trunc (insn, operands, 0);"
16828 [(set_attr "type" "fistp")
16829 (set_attr "i387_cw" "floor")
16830 (set_attr "mode" "DI")])
16832 (define_insn "fistdi2_floor_with_temp"
16833 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
16834 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
16835 UNSPEC_FIST_FLOOR))
16836 (use (match_operand:HI 2 "memory_operand" "m,m"))
16837 (use (match_operand:HI 3 "memory_operand" "m,m"))
16838 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
16839 (clobber (match_scratch:XF 5 "=&1f,&1f"))]
16840 "TARGET_USE_FANCY_MATH_387
16841 && flag_unsafe_math_optimizations"
16843 [(set_attr "type" "fistp")
16844 (set_attr "i387_cw" "floor")
16845 (set_attr "mode" "DI")])
16848 [(set (match_operand:DI 0 "register_operand" "")
16849 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
16850 UNSPEC_FIST_FLOOR))
16851 (use (match_operand:HI 2 "memory_operand" ""))
16852 (use (match_operand:HI 3 "memory_operand" ""))
16853 (clobber (match_operand:DI 4 "memory_operand" ""))
16854 (clobber (match_scratch 5 ""))]
16856 [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
16857 (use (match_dup 2))
16858 (use (match_dup 3))
16859 (clobber (match_dup 5))])
16860 (set (match_dup 0) (match_dup 4))]
16864 [(set (match_operand:DI 0 "memory_operand" "")
16865 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
16866 UNSPEC_FIST_FLOOR))
16867 (use (match_operand:HI 2 "memory_operand" ""))
16868 (use (match_operand:HI 3 "memory_operand" ""))
16869 (clobber (match_operand:DI 4 "memory_operand" ""))
16870 (clobber (match_scratch 5 ""))]
16872 [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
16873 (use (match_dup 2))
16874 (use (match_dup 3))
16875 (clobber (match_dup 5))])]
16878 (define_insn "fist<mode>2_floor"
16879 [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
16880 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
16881 UNSPEC_FIST_FLOOR))
16882 (use (match_operand:HI 2 "memory_operand" "m"))
16883 (use (match_operand:HI 3 "memory_operand" "m"))]
16884 "TARGET_USE_FANCY_MATH_387
16885 && flag_unsafe_math_optimizations"
16886 "* return output_fix_trunc (insn, operands, 0);"
16887 [(set_attr "type" "fistp")
16888 (set_attr "i387_cw" "floor")
16889 (set_attr "mode" "<MODE>")])
16891 (define_insn "fist<mode>2_floor_with_temp"
16892 [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
16893 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f,f")]
16894 UNSPEC_FIST_FLOOR))
16895 (use (match_operand:HI 2 "memory_operand" "m,m"))
16896 (use (match_operand:HI 3 "memory_operand" "m,m"))
16897 (clobber (match_operand:X87MODEI12 4 "memory_operand" "=m,m"))]
16898 "TARGET_USE_FANCY_MATH_387
16899 && flag_unsafe_math_optimizations"
16901 [(set_attr "type" "fistp")
16902 (set_attr "i387_cw" "floor")
16903 (set_attr "mode" "<MODE>")])
16906 [(set (match_operand:X87MODEI12 0 "register_operand" "")
16907 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
16908 UNSPEC_FIST_FLOOR))
16909 (use (match_operand:HI 2 "memory_operand" ""))
16910 (use (match_operand:HI 3 "memory_operand" ""))
16911 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
16913 [(parallel [(set (match_dup 4) (unspec:X87MODEI12 [(match_dup 1)]
16914 UNSPEC_FIST_FLOOR))
16915 (use (match_dup 2))
16916 (use (match_dup 3))])
16917 (set (match_dup 0) (match_dup 4))]
16921 [(set (match_operand:X87MODEI12 0 "memory_operand" "")
16922 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
16923 UNSPEC_FIST_FLOOR))
16924 (use (match_operand:HI 2 "memory_operand" ""))
16925 (use (match_operand:HI 3 "memory_operand" ""))
16926 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
16928 [(parallel [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
16929 UNSPEC_FIST_FLOOR))
16930 (use (match_dup 2))
16931 (use (match_dup 3))])]
16934 (define_expand "lfloor<mode>2"
16935 [(parallel [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
16936 (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
16937 UNSPEC_FIST_FLOOR))
16938 (clobber (reg:CC FLAGS_REG))])]
16939 "TARGET_USE_FANCY_MATH_387
16940 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
16941 && flag_unsafe_math_optimizations"
16944 ;; Rounding mode control word calculation could clobber FLAGS_REG.
16945 (define_insn_and_split "frndintxf2_ceil"
16946 [(set (match_operand:XF 0 "register_operand" "=f")
16947 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16948 UNSPEC_FRNDINT_CEIL))
16949 (clobber (reg:CC FLAGS_REG))]
16950 "TARGET_USE_FANCY_MATH_387
16951 && flag_unsafe_math_optimizations
16952 && !(reload_completed || reload_in_progress)"
16957 ix86_optimize_mode_switching[I387_CEIL] = 1;
16959 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
16960 operands[3] = assign_386_stack_local (HImode, SLOT_CW_CEIL);
16962 emit_insn (gen_frndintxf2_ceil_i387 (operands[0], operands[1],
16963 operands[2], operands[3]));
16966 [(set_attr "type" "frndint")
16967 (set_attr "i387_cw" "ceil")
16968 (set_attr "mode" "XF")])
16970 (define_insn "frndintxf2_ceil_i387"
16971 [(set (match_operand:XF 0 "register_operand" "=f")
16972 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
16973 UNSPEC_FRNDINT_CEIL))
16974 (use (match_operand:HI 2 "memory_operand" "m"))
16975 (use (match_operand:HI 3 "memory_operand" "m"))]
16976 "TARGET_USE_FANCY_MATH_387
16977 && flag_unsafe_math_optimizations"
16978 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
16979 [(set_attr "type" "frndint")
16980 (set_attr "i387_cw" "ceil")
16981 (set_attr "mode" "XF")])
16983 (define_expand "ceilxf2"
16984 [(use (match_operand:XF 0 "register_operand" ""))
16985 (use (match_operand:XF 1 "register_operand" ""))]
16986 "TARGET_USE_FANCY_MATH_387
16987 && flag_unsafe_math_optimizations"
16989 emit_insn (gen_frndintxf2_ceil (operands[0], operands[1]));
16993 (define_expand "ceildf2"
16994 [(use (match_operand:DF 0 "register_operand" ""))
16995 (use (match_operand:DF 1 "register_operand" ""))]
16996 "TARGET_USE_FANCY_MATH_387
16997 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
16998 && flag_unsafe_math_optimizations"
17000 rtx op0 = gen_reg_rtx (XFmode);
17001 rtx op1 = gen_reg_rtx (XFmode);
17003 emit_insn (gen_extenddfxf2 (op1, operands[1]));
17004 emit_insn (gen_frndintxf2_ceil (op0, op1));
17006 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
17010 (define_expand "ceilsf2"
17011 [(use (match_operand:SF 0 "register_operand" ""))
17012 (use (match_operand:SF 1 "register_operand" ""))]
17013 "TARGET_USE_FANCY_MATH_387
17014 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
17015 && flag_unsafe_math_optimizations"
17017 rtx op0 = gen_reg_rtx (XFmode);
17018 rtx op1 = gen_reg_rtx (XFmode);
17020 emit_insn (gen_extendsfxf2 (op1, operands[1]));
17021 emit_insn (gen_frndintxf2_ceil (op0, op1));
17023 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
17027 (define_insn_and_split "*fist<mode>2_ceil_1"
17028 [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "=m,?r")
17029 (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "f,f")]
17031 (clobber (reg:CC FLAGS_REG))]
17032 "TARGET_USE_FANCY_MATH_387
17033 && flag_unsafe_math_optimizations
17034 && !(reload_completed || reload_in_progress)"
17039 ix86_optimize_mode_switching[I387_CEIL] = 1;
17041 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
17042 operands[3] = assign_386_stack_local (HImode, SLOT_CW_CEIL);
17043 if (memory_operand (operands[0], VOIDmode))
17044 emit_insn (gen_fist<mode>2_ceil (operands[0], operands[1],
17045 operands[2], operands[3]));
17048 operands[4] = assign_386_stack_local (<MODE>mode, SLOT_TEMP);
17049 emit_insn (gen_fist<mode>2_ceil_with_temp (operands[0], operands[1],
17050 operands[2], operands[3],
17055 [(set_attr "type" "fistp")
17056 (set_attr "i387_cw" "ceil")
17057 (set_attr "mode" "<MODE>")])
17059 (define_insn "fistdi2_ceil"
17060 [(set (match_operand:DI 0 "memory_operand" "=m")
17061 (unspec:DI [(match_operand:XF 1 "register_operand" "f")]
17063 (use (match_operand:HI 2 "memory_operand" "m"))
17064 (use (match_operand:HI 3 "memory_operand" "m"))
17065 (clobber (match_scratch:XF 4 "=&1f"))]
17066 "TARGET_USE_FANCY_MATH_387
17067 && flag_unsafe_math_optimizations"
17068 "* return output_fix_trunc (insn, operands, 0);"
17069 [(set_attr "type" "fistp")
17070 (set_attr "i387_cw" "ceil")
17071 (set_attr "mode" "DI")])
17073 (define_insn "fistdi2_ceil_with_temp"
17074 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
17075 (unspec:DI [(match_operand:XF 1 "register_operand" "f,f")]
17077 (use (match_operand:HI 2 "memory_operand" "m,m"))
17078 (use (match_operand:HI 3 "memory_operand" "m,m"))
17079 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
17080 (clobber (match_scratch:XF 5 "=&1f,&1f"))]
17081 "TARGET_USE_FANCY_MATH_387
17082 && flag_unsafe_math_optimizations"
17084 [(set_attr "type" "fistp")
17085 (set_attr "i387_cw" "ceil")
17086 (set_attr "mode" "DI")])
17089 [(set (match_operand:DI 0 "register_operand" "")
17090 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
17092 (use (match_operand:HI 2 "memory_operand" ""))
17093 (use (match_operand:HI 3 "memory_operand" ""))
17094 (clobber (match_operand:DI 4 "memory_operand" ""))
17095 (clobber (match_scratch 5 ""))]
17097 [(parallel [(set (match_dup 4) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
17098 (use (match_dup 2))
17099 (use (match_dup 3))
17100 (clobber (match_dup 5))])
17101 (set (match_dup 0) (match_dup 4))]
17105 [(set (match_operand:DI 0 "memory_operand" "")
17106 (unspec:DI [(match_operand:XF 1 "register_operand" "")]
17108 (use (match_operand:HI 2 "memory_operand" ""))
17109 (use (match_operand:HI 3 "memory_operand" ""))
17110 (clobber (match_operand:DI 4 "memory_operand" ""))
17111 (clobber (match_scratch 5 ""))]
17113 [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
17114 (use (match_dup 2))
17115 (use (match_dup 3))
17116 (clobber (match_dup 5))])]
17119 (define_insn "fist<mode>2_ceil"
17120 [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
17121 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f")]
17123 (use (match_operand:HI 2 "memory_operand" "m"))
17124 (use (match_operand:HI 3 "memory_operand" "m"))]
17125 "TARGET_USE_FANCY_MATH_387
17126 && flag_unsafe_math_optimizations"
17127 "* return output_fix_trunc (insn, operands, 0);"
17128 [(set_attr "type" "fistp")
17129 (set_attr "i387_cw" "ceil")
17130 (set_attr "mode" "<MODE>")])
17132 (define_insn "fist<mode>2_ceil_with_temp"
17133 [(set (match_operand:X87MODEI12 0 "nonimmediate_operand" "=m,?r")
17134 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "f,f")]
17136 (use (match_operand:HI 2 "memory_operand" "m,m"))
17137 (use (match_operand:HI 3 "memory_operand" "m,m"))
17138 (clobber (match_operand:X87MODEI12 4 "memory_operand" "=m,m"))]
17139 "TARGET_USE_FANCY_MATH_387
17140 && flag_unsafe_math_optimizations"
17142 [(set_attr "type" "fistp")
17143 (set_attr "i387_cw" "ceil")
17144 (set_attr "mode" "<MODE>")])
17147 [(set (match_operand:X87MODEI12 0 "register_operand" "")
17148 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
17150 (use (match_operand:HI 2 "memory_operand" ""))
17151 (use (match_operand:HI 3 "memory_operand" ""))
17152 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
17154 [(parallel [(set (match_dup 4) (unspec:X87MODEI12 [(match_dup 1)]
17156 (use (match_dup 2))
17157 (use (match_dup 3))])
17158 (set (match_dup 0) (match_dup 4))]
17162 [(set (match_operand:X87MODEI12 0 "memory_operand" "")
17163 (unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
17165 (use (match_operand:HI 2 "memory_operand" ""))
17166 (use (match_operand:HI 3 "memory_operand" ""))
17167 (clobber (match_operand:X87MODEI12 4 "memory_operand" ""))]
17169 [(parallel [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
17171 (use (match_dup 2))
17172 (use (match_dup 3))])]
17175 (define_expand "lceil<mode>2"
17176 [(parallel [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
17177 (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
17179 (clobber (reg:CC FLAGS_REG))])]
17180 "TARGET_USE_FANCY_MATH_387
17181 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
17182 && flag_unsafe_math_optimizations"
17185 ;; Rounding mode control word calculation could clobber FLAGS_REG.
17186 (define_insn_and_split "frndintxf2_trunc"
17187 [(set (match_operand:XF 0 "register_operand" "=f")
17188 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
17189 UNSPEC_FRNDINT_TRUNC))
17190 (clobber (reg:CC FLAGS_REG))]
17191 "TARGET_USE_FANCY_MATH_387
17192 && flag_unsafe_math_optimizations
17193 && !(reload_completed || reload_in_progress)"
17198 ix86_optimize_mode_switching[I387_TRUNC] = 1;
17200 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
17201 operands[3] = assign_386_stack_local (HImode, SLOT_CW_TRUNC);
17203 emit_insn (gen_frndintxf2_trunc_i387 (operands[0], operands[1],
17204 operands[2], operands[3]));
17207 [(set_attr "type" "frndint")
17208 (set_attr "i387_cw" "trunc")
17209 (set_attr "mode" "XF")])
17211 (define_insn "frndintxf2_trunc_i387"
17212 [(set (match_operand:XF 0 "register_operand" "=f")
17213 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
17214 UNSPEC_FRNDINT_TRUNC))
17215 (use (match_operand:HI 2 "memory_operand" "m"))
17216 (use (match_operand:HI 3 "memory_operand" "m"))]
17217 "TARGET_USE_FANCY_MATH_387
17218 && flag_unsafe_math_optimizations"
17219 "fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
17220 [(set_attr "type" "frndint")
17221 (set_attr "i387_cw" "trunc")
17222 (set_attr "mode" "XF")])
17224 (define_expand "btruncxf2"
17225 [(use (match_operand:XF 0 "register_operand" ""))
17226 (use (match_operand:XF 1 "register_operand" ""))]
17227 "TARGET_USE_FANCY_MATH_387
17228 && flag_unsafe_math_optimizations"
17230 emit_insn (gen_frndintxf2_trunc (operands[0], operands[1]));
17234 (define_expand "btruncdf2"
17235 [(use (match_operand:DF 0 "register_operand" ""))
17236 (use (match_operand:DF 1 "register_operand" ""))]
17237 "TARGET_USE_FANCY_MATH_387
17238 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
17239 && flag_unsafe_math_optimizations"
17241 rtx op0 = gen_reg_rtx (XFmode);
17242 rtx op1 = gen_reg_rtx (XFmode);
17244 emit_insn (gen_extenddfxf2 (op1, operands[1]));
17245 emit_insn (gen_frndintxf2_trunc (op0, op1));
17247 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
17251 (define_expand "btruncsf2"
17252 [(use (match_operand:SF 0 "register_operand" ""))
17253 (use (match_operand:SF 1 "register_operand" ""))]
17254 "TARGET_USE_FANCY_MATH_387
17255 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
17256 && flag_unsafe_math_optimizations"
17258 rtx op0 = gen_reg_rtx (XFmode);
17259 rtx op1 = gen_reg_rtx (XFmode);
17261 emit_insn (gen_extendsfxf2 (op1, operands[1]));
17262 emit_insn (gen_frndintxf2_trunc (op0, op1));
17264 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
17268 ;; Rounding mode control word calculation could clobber FLAGS_REG.
17269 (define_insn_and_split "frndintxf2_mask_pm"
17270 [(set (match_operand:XF 0 "register_operand" "=f")
17271 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
17272 UNSPEC_FRNDINT_MASK_PM))
17273 (clobber (reg:CC FLAGS_REG))]
17274 "TARGET_USE_FANCY_MATH_387
17275 && flag_unsafe_math_optimizations
17276 && !(reload_completed || reload_in_progress)"
17281 ix86_optimize_mode_switching[I387_MASK_PM] = 1;
17283 operands[2] = assign_386_stack_local (HImode, SLOT_CW_STORED);
17284 operands[3] = assign_386_stack_local (HImode, SLOT_CW_MASK_PM);
17286 emit_insn (gen_frndintxf2_mask_pm_i387 (operands[0], operands[1],
17287 operands[2], operands[3]));
17290 [(set_attr "type" "frndint")
17291 (set_attr "i387_cw" "mask_pm")
17292 (set_attr "mode" "XF")])
17294 (define_insn "frndintxf2_mask_pm_i387"
17295 [(set (match_operand:XF 0 "register_operand" "=f")
17296 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
17297 UNSPEC_FRNDINT_MASK_PM))
17298 (use (match_operand:HI 2 "memory_operand" "m"))
17299 (use (match_operand:HI 3 "memory_operand" "m"))]
17300 "TARGET_USE_FANCY_MATH_387
17301 && flag_unsafe_math_optimizations"
17302 "fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
17303 [(set_attr "type" "frndint")
17304 (set_attr "i387_cw" "mask_pm")
17305 (set_attr "mode" "XF")])
17307 (define_expand "nearbyintxf2"
17308 [(use (match_operand:XF 0 "register_operand" ""))
17309 (use (match_operand:XF 1 "register_operand" ""))]
17310 "TARGET_USE_FANCY_MATH_387
17311 && flag_unsafe_math_optimizations"
17313 emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1]));
17318 (define_expand "nearbyintdf2"
17319 [(use (match_operand:DF 0 "register_operand" ""))
17320 (use (match_operand:DF 1 "register_operand" ""))]
17321 "TARGET_USE_FANCY_MATH_387
17322 && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
17323 && flag_unsafe_math_optimizations"
17325 rtx op0 = gen_reg_rtx (XFmode);
17326 rtx op1 = gen_reg_rtx (XFmode);
17328 emit_insn (gen_extenddfxf2 (op1, operands[1]));
17329 emit_insn (gen_frndintxf2_mask_pm (op0, op1));
17331 emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
17335 (define_expand "nearbyintsf2"
17336 [(use (match_operand:SF 0 "register_operand" ""))
17337 (use (match_operand:SF 1 "register_operand" ""))]
17338 "TARGET_USE_FANCY_MATH_387
17339 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
17340 && flag_unsafe_math_optimizations"
17342 rtx op0 = gen_reg_rtx (XFmode);
17343 rtx op1 = gen_reg_rtx (XFmode);
17345 emit_insn (gen_extendsfxf2 (op1, operands[1]));
17346 emit_insn (gen_frndintxf2_mask_pm (op0, op1));
17348 emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
17353 ;; Block operation instructions
17356 [(set (reg:SI DIRFLAG_REG) (const_int 0))]
17359 [(set_attr "type" "cld")])
17361 (define_expand "movmemsi"
17362 [(use (match_operand:BLK 0 "memory_operand" ""))
17363 (use (match_operand:BLK 1 "memory_operand" ""))
17364 (use (match_operand:SI 2 "nonmemory_operand" ""))
17365 (use (match_operand:SI 3 "const_int_operand" ""))]
17366 "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
17368 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
17374 (define_expand "movmemdi"
17375 [(use (match_operand:BLK 0 "memory_operand" ""))
17376 (use (match_operand:BLK 1 "memory_operand" ""))
17377 (use (match_operand:DI 2 "nonmemory_operand" ""))
17378 (use (match_operand:DI 3 "const_int_operand" ""))]
17381 if (ix86_expand_movmem (operands[0], operands[1], operands[2], operands[3]))
17387 ;; Most CPUs don't like single string operations
17388 ;; Handle this case here to simplify previous expander.
17390 (define_expand "strmov"
17391 [(set (match_dup 4) (match_operand 3 "memory_operand" ""))
17392 (set (match_operand 1 "memory_operand" "") (match_dup 4))
17393 (parallel [(set (match_operand 0 "register_operand" "") (match_dup 5))
17394 (clobber (reg:CC FLAGS_REG))])
17395 (parallel [(set (match_operand 2 "register_operand" "") (match_dup 6))
17396 (clobber (reg:CC FLAGS_REG))])]
17399 rtx adjust = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[1])));
17401 /* If .md ever supports :P for Pmode, these can be directly
17402 in the pattern above. */
17403 operands[5] = gen_rtx_PLUS (Pmode, operands[0], adjust);
17404 operands[6] = gen_rtx_PLUS (Pmode, operands[2], adjust);
17406 if (TARGET_SINGLE_STRINGOP || optimize_size)
17408 emit_insn (gen_strmov_singleop (operands[0], operands[1],
17409 operands[2], operands[3],
17410 operands[5], operands[6]));
17414 operands[4] = gen_reg_rtx (GET_MODE (operands[1]));
17417 (define_expand "strmov_singleop"
17418 [(parallel [(set (match_operand 1 "memory_operand" "")
17419 (match_operand 3 "memory_operand" ""))
17420 (set (match_operand 0 "register_operand" "")
17421 (match_operand 4 "" ""))
17422 (set (match_operand 2 "register_operand" "")
17423 (match_operand 5 "" ""))
17424 (use (reg:SI DIRFLAG_REG))])]
17425 "TARGET_SINGLE_STRINGOP || optimize_size"
17428 (define_insn "*strmovdi_rex_1"
17429 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
17430 (mem:DI (match_operand:DI 3 "register_operand" "1")))
17431 (set (match_operand:DI 0 "register_operand" "=D")
17432 (plus:DI (match_dup 2)
17434 (set (match_operand:DI 1 "register_operand" "=S")
17435 (plus:DI (match_dup 3)
17437 (use (reg:SI DIRFLAG_REG))]
17438 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17440 [(set_attr "type" "str")
17441 (set_attr "mode" "DI")
17442 (set_attr "memory" "both")])
17444 (define_insn "*strmovsi_1"
17445 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
17446 (mem:SI (match_operand:SI 3 "register_operand" "1")))
17447 (set (match_operand:SI 0 "register_operand" "=D")
17448 (plus:SI (match_dup 2)
17450 (set (match_operand:SI 1 "register_operand" "=S")
17451 (plus:SI (match_dup 3)
17453 (use (reg:SI DIRFLAG_REG))]
17454 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17456 [(set_attr "type" "str")
17457 (set_attr "mode" "SI")
17458 (set_attr "memory" "both")])
17460 (define_insn "*strmovsi_rex_1"
17461 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
17462 (mem:SI (match_operand:DI 3 "register_operand" "1")))
17463 (set (match_operand:DI 0 "register_operand" "=D")
17464 (plus:DI (match_dup 2)
17466 (set (match_operand:DI 1 "register_operand" "=S")
17467 (plus:DI (match_dup 3)
17469 (use (reg:SI DIRFLAG_REG))]
17470 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17472 [(set_attr "type" "str")
17473 (set_attr "mode" "SI")
17474 (set_attr "memory" "both")])
17476 (define_insn "*strmovhi_1"
17477 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
17478 (mem:HI (match_operand:SI 3 "register_operand" "1")))
17479 (set (match_operand:SI 0 "register_operand" "=D")
17480 (plus:SI (match_dup 2)
17482 (set (match_operand:SI 1 "register_operand" "=S")
17483 (plus:SI (match_dup 3)
17485 (use (reg:SI DIRFLAG_REG))]
17486 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17488 [(set_attr "type" "str")
17489 (set_attr "memory" "both")
17490 (set_attr "mode" "HI")])
17492 (define_insn "*strmovhi_rex_1"
17493 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
17494 (mem:HI (match_operand:DI 3 "register_operand" "1")))
17495 (set (match_operand:DI 0 "register_operand" "=D")
17496 (plus:DI (match_dup 2)
17498 (set (match_operand:DI 1 "register_operand" "=S")
17499 (plus:DI (match_dup 3)
17501 (use (reg:SI DIRFLAG_REG))]
17502 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17504 [(set_attr "type" "str")
17505 (set_attr "memory" "both")
17506 (set_attr "mode" "HI")])
17508 (define_insn "*strmovqi_1"
17509 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
17510 (mem:QI (match_operand:SI 3 "register_operand" "1")))
17511 (set (match_operand:SI 0 "register_operand" "=D")
17512 (plus:SI (match_dup 2)
17514 (set (match_operand:SI 1 "register_operand" "=S")
17515 (plus:SI (match_dup 3)
17517 (use (reg:SI DIRFLAG_REG))]
17518 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17520 [(set_attr "type" "str")
17521 (set_attr "memory" "both")
17522 (set_attr "mode" "QI")])
17524 (define_insn "*strmovqi_rex_1"
17525 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
17526 (mem:QI (match_operand:DI 3 "register_operand" "1")))
17527 (set (match_operand:DI 0 "register_operand" "=D")
17528 (plus:DI (match_dup 2)
17530 (set (match_operand:DI 1 "register_operand" "=S")
17531 (plus:DI (match_dup 3)
17533 (use (reg:SI DIRFLAG_REG))]
17534 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17536 [(set_attr "type" "str")
17537 (set_attr "memory" "both")
17538 (set_attr "mode" "QI")])
17540 (define_expand "rep_mov"
17541 [(parallel [(set (match_operand 4 "register_operand" "") (const_int 0))
17542 (set (match_operand 0 "register_operand" "")
17543 (match_operand 5 "" ""))
17544 (set (match_operand 2 "register_operand" "")
17545 (match_operand 6 "" ""))
17546 (set (match_operand 1 "memory_operand" "")
17547 (match_operand 3 "memory_operand" ""))
17548 (use (match_dup 4))
17549 (use (reg:SI DIRFLAG_REG))])]
17553 (define_insn "*rep_movdi_rex64"
17554 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
17555 (set (match_operand:DI 0 "register_operand" "=D")
17556 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
17558 (match_operand:DI 3 "register_operand" "0")))
17559 (set (match_operand:DI 1 "register_operand" "=S")
17560 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
17561 (match_operand:DI 4 "register_operand" "1")))
17562 (set (mem:BLK (match_dup 3))
17563 (mem:BLK (match_dup 4)))
17564 (use (match_dup 5))
17565 (use (reg:SI DIRFLAG_REG))]
17567 "{rep\;movsq|rep movsq}"
17568 [(set_attr "type" "str")
17569 (set_attr "prefix_rep" "1")
17570 (set_attr "memory" "both")
17571 (set_attr "mode" "DI")])
17573 (define_insn "*rep_movsi"
17574 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
17575 (set (match_operand:SI 0 "register_operand" "=D")
17576 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
17578 (match_operand:SI 3 "register_operand" "0")))
17579 (set (match_operand:SI 1 "register_operand" "=S")
17580 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
17581 (match_operand:SI 4 "register_operand" "1")))
17582 (set (mem:BLK (match_dup 3))
17583 (mem:BLK (match_dup 4)))
17584 (use (match_dup 5))
17585 (use (reg:SI DIRFLAG_REG))]
17587 "{rep\;movsl|rep movsd}"
17588 [(set_attr "type" "str")
17589 (set_attr "prefix_rep" "1")
17590 (set_attr "memory" "both")
17591 (set_attr "mode" "SI")])
17593 (define_insn "*rep_movsi_rex64"
17594 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
17595 (set (match_operand:DI 0 "register_operand" "=D")
17596 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
17598 (match_operand:DI 3 "register_operand" "0")))
17599 (set (match_operand:DI 1 "register_operand" "=S")
17600 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
17601 (match_operand:DI 4 "register_operand" "1")))
17602 (set (mem:BLK (match_dup 3))
17603 (mem:BLK (match_dup 4)))
17604 (use (match_dup 5))
17605 (use (reg:SI DIRFLAG_REG))]
17607 "{rep\;movsl|rep movsd}"
17608 [(set_attr "type" "str")
17609 (set_attr "prefix_rep" "1")
17610 (set_attr "memory" "both")
17611 (set_attr "mode" "SI")])
17613 (define_insn "*rep_movqi"
17614 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
17615 (set (match_operand:SI 0 "register_operand" "=D")
17616 (plus:SI (match_operand:SI 3 "register_operand" "0")
17617 (match_operand:SI 5 "register_operand" "2")))
17618 (set (match_operand:SI 1 "register_operand" "=S")
17619 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
17620 (set (mem:BLK (match_dup 3))
17621 (mem:BLK (match_dup 4)))
17622 (use (match_dup 5))
17623 (use (reg:SI DIRFLAG_REG))]
17625 "{rep\;movsb|rep movsb}"
17626 [(set_attr "type" "str")
17627 (set_attr "prefix_rep" "1")
17628 (set_attr "memory" "both")
17629 (set_attr "mode" "SI")])
17631 (define_insn "*rep_movqi_rex64"
17632 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
17633 (set (match_operand:DI 0 "register_operand" "=D")
17634 (plus:DI (match_operand:DI 3 "register_operand" "0")
17635 (match_operand:DI 5 "register_operand" "2")))
17636 (set (match_operand:DI 1 "register_operand" "=S")
17637 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
17638 (set (mem:BLK (match_dup 3))
17639 (mem:BLK (match_dup 4)))
17640 (use (match_dup 5))
17641 (use (reg:SI DIRFLAG_REG))]
17643 "{rep\;movsb|rep movsb}"
17644 [(set_attr "type" "str")
17645 (set_attr "prefix_rep" "1")
17646 (set_attr "memory" "both")
17647 (set_attr "mode" "SI")])
17649 (define_expand "setmemsi"
17650 [(use (match_operand:BLK 0 "memory_operand" ""))
17651 (use (match_operand:SI 1 "nonmemory_operand" ""))
17652 (use (match_operand 2 "const_int_operand" ""))
17653 (use (match_operand 3 "const_int_operand" ""))]
17656 /* If value to set is not zero, use the library routine. */
17657 if (operands[2] != const0_rtx)
17660 if (ix86_expand_clrmem (operands[0], operands[1], operands[3]))
17666 (define_expand "setmemdi"
17667 [(use (match_operand:BLK 0 "memory_operand" ""))
17668 (use (match_operand:DI 1 "nonmemory_operand" ""))
17669 (use (match_operand 2 "const_int_operand" ""))
17670 (use (match_operand 3 "const_int_operand" ""))]
17673 /* If value to set is not zero, use the library routine. */
17674 if (operands[2] != const0_rtx)
17677 if (ix86_expand_clrmem (operands[0], operands[1], operands[3]))
17683 ;; Most CPUs don't like single string operations
17684 ;; Handle this case here to simplify previous expander.
17686 (define_expand "strset"
17687 [(set (match_operand 1 "memory_operand" "")
17688 (match_operand 2 "register_operand" ""))
17689 (parallel [(set (match_operand 0 "register_operand" "")
17691 (clobber (reg:CC FLAGS_REG))])]
17694 if (GET_MODE (operands[1]) != GET_MODE (operands[2]))
17695 operands[1] = adjust_address_nv (operands[1], GET_MODE (operands[2]), 0);
17697 /* If .md ever supports :P for Pmode, this can be directly
17698 in the pattern above. */
17699 operands[3] = gen_rtx_PLUS (Pmode, operands[0],
17700 GEN_INT (GET_MODE_SIZE (GET_MODE
17702 if (TARGET_SINGLE_STRINGOP || optimize_size)
17704 emit_insn (gen_strset_singleop (operands[0], operands[1], operands[2],
17710 (define_expand "strset_singleop"
17711 [(parallel [(set (match_operand 1 "memory_operand" "")
17712 (match_operand 2 "register_operand" ""))
17713 (set (match_operand 0 "register_operand" "")
17714 (match_operand 3 "" ""))
17715 (use (reg:SI DIRFLAG_REG))])]
17716 "TARGET_SINGLE_STRINGOP || optimize_size"
17719 (define_insn "*strsetdi_rex_1"
17720 [(set (mem:DI (match_operand:DI 1 "register_operand" "0"))
17721 (match_operand:DI 2 "register_operand" "a"))
17722 (set (match_operand:DI 0 "register_operand" "=D")
17723 (plus:DI (match_dup 1)
17725 (use (reg:SI DIRFLAG_REG))]
17726 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17728 [(set_attr "type" "str")
17729 (set_attr "memory" "store")
17730 (set_attr "mode" "DI")])
17732 (define_insn "*strsetsi_1"
17733 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
17734 (match_operand:SI 2 "register_operand" "a"))
17735 (set (match_operand:SI 0 "register_operand" "=D")
17736 (plus:SI (match_dup 1)
17738 (use (reg:SI DIRFLAG_REG))]
17739 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17741 [(set_attr "type" "str")
17742 (set_attr "memory" "store")
17743 (set_attr "mode" "SI")])
17745 (define_insn "*strsetsi_rex_1"
17746 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
17747 (match_operand:SI 2 "register_operand" "a"))
17748 (set (match_operand:DI 0 "register_operand" "=D")
17749 (plus:DI (match_dup 1)
17751 (use (reg:SI DIRFLAG_REG))]
17752 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17754 [(set_attr "type" "str")
17755 (set_attr "memory" "store")
17756 (set_attr "mode" "SI")])
17758 (define_insn "*strsethi_1"
17759 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
17760 (match_operand:HI 2 "register_operand" "a"))
17761 (set (match_operand:SI 0 "register_operand" "=D")
17762 (plus:SI (match_dup 1)
17764 (use (reg:SI DIRFLAG_REG))]
17765 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17767 [(set_attr "type" "str")
17768 (set_attr "memory" "store")
17769 (set_attr "mode" "HI")])
17771 (define_insn "*strsethi_rex_1"
17772 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
17773 (match_operand:HI 2 "register_operand" "a"))
17774 (set (match_operand:DI 0 "register_operand" "=D")
17775 (plus:DI (match_dup 1)
17777 (use (reg:SI DIRFLAG_REG))]
17778 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17780 [(set_attr "type" "str")
17781 (set_attr "memory" "store")
17782 (set_attr "mode" "HI")])
17784 (define_insn "*strsetqi_1"
17785 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
17786 (match_operand:QI 2 "register_operand" "a"))
17787 (set (match_operand:SI 0 "register_operand" "=D")
17788 (plus:SI (match_dup 1)
17790 (use (reg:SI DIRFLAG_REG))]
17791 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17793 [(set_attr "type" "str")
17794 (set_attr "memory" "store")
17795 (set_attr "mode" "QI")])
17797 (define_insn "*strsetqi_rex_1"
17798 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
17799 (match_operand:QI 2 "register_operand" "a"))
17800 (set (match_operand:DI 0 "register_operand" "=D")
17801 (plus:DI (match_dup 1)
17803 (use (reg:SI DIRFLAG_REG))]
17804 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
17806 [(set_attr "type" "str")
17807 (set_attr "memory" "store")
17808 (set_attr "mode" "QI")])
17810 (define_expand "rep_stos"
17811 [(parallel [(set (match_operand 1 "register_operand" "") (const_int 0))
17812 (set (match_operand 0 "register_operand" "")
17813 (match_operand 4 "" ""))
17814 (set (match_operand 2 "memory_operand" "") (const_int 0))
17815 (use (match_operand 3 "register_operand" ""))
17816 (use (match_dup 1))
17817 (use (reg:SI DIRFLAG_REG))])]
17821 (define_insn "*rep_stosdi_rex64"
17822 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17823 (set (match_operand:DI 0 "register_operand" "=D")
17824 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
17826 (match_operand:DI 3 "register_operand" "0")))
17827 (set (mem:BLK (match_dup 3))
17829 (use (match_operand:DI 2 "register_operand" "a"))
17830 (use (match_dup 4))
17831 (use (reg:SI DIRFLAG_REG))]
17833 "{rep\;stosq|rep stosq}"
17834 [(set_attr "type" "str")
17835 (set_attr "prefix_rep" "1")
17836 (set_attr "memory" "store")
17837 (set_attr "mode" "DI")])
17839 (define_insn "*rep_stossi"
17840 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
17841 (set (match_operand:SI 0 "register_operand" "=D")
17842 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
17844 (match_operand:SI 3 "register_operand" "0")))
17845 (set (mem:BLK (match_dup 3))
17847 (use (match_operand:SI 2 "register_operand" "a"))
17848 (use (match_dup 4))
17849 (use (reg:SI DIRFLAG_REG))]
17851 "{rep\;stosl|rep stosd}"
17852 [(set_attr "type" "str")
17853 (set_attr "prefix_rep" "1")
17854 (set_attr "memory" "store")
17855 (set_attr "mode" "SI")])
17857 (define_insn "*rep_stossi_rex64"
17858 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17859 (set (match_operand:DI 0 "register_operand" "=D")
17860 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
17862 (match_operand:DI 3 "register_operand" "0")))
17863 (set (mem:BLK (match_dup 3))
17865 (use (match_operand:SI 2 "register_operand" "a"))
17866 (use (match_dup 4))
17867 (use (reg:SI DIRFLAG_REG))]
17869 "{rep\;stosl|rep stosd}"
17870 [(set_attr "type" "str")
17871 (set_attr "prefix_rep" "1")
17872 (set_attr "memory" "store")
17873 (set_attr "mode" "SI")])
17875 (define_insn "*rep_stosqi"
17876 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
17877 (set (match_operand:SI 0 "register_operand" "=D")
17878 (plus:SI (match_operand:SI 3 "register_operand" "0")
17879 (match_operand:SI 4 "register_operand" "1")))
17880 (set (mem:BLK (match_dup 3))
17882 (use (match_operand:QI 2 "register_operand" "a"))
17883 (use (match_dup 4))
17884 (use (reg:SI DIRFLAG_REG))]
17886 "{rep\;stosb|rep stosb}"
17887 [(set_attr "type" "str")
17888 (set_attr "prefix_rep" "1")
17889 (set_attr "memory" "store")
17890 (set_attr "mode" "QI")])
17892 (define_insn "*rep_stosqi_rex64"
17893 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
17894 (set (match_operand:DI 0 "register_operand" "=D")
17895 (plus:DI (match_operand:DI 3 "register_operand" "0")
17896 (match_operand:DI 4 "register_operand" "1")))
17897 (set (mem:BLK (match_dup 3))
17899 (use (match_operand:QI 2 "register_operand" "a"))
17900 (use (match_dup 4))
17901 (use (reg:SI DIRFLAG_REG))]
17903 "{rep\;stosb|rep stosb}"
17904 [(set_attr "type" "str")
17905 (set_attr "prefix_rep" "1")
17906 (set_attr "memory" "store")
17907 (set_attr "mode" "QI")])
17909 (define_expand "cmpstrnsi"
17910 [(set (match_operand:SI 0 "register_operand" "")
17911 (compare:SI (match_operand:BLK 1 "general_operand" "")
17912 (match_operand:BLK 2 "general_operand" "")))
17913 (use (match_operand 3 "general_operand" ""))
17914 (use (match_operand 4 "immediate_operand" ""))]
17915 "! optimize_size || TARGET_INLINE_ALL_STRINGOPS"
17917 rtx addr1, addr2, out, outlow, count, countreg, align;
17919 /* Can't use this if the user has appropriated esi or edi. */
17920 if (global_regs[4] || global_regs[5])
17924 if (GET_CODE (out) != REG)
17925 out = gen_reg_rtx (SImode);
17927 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
17928 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
17929 if (addr1 != XEXP (operands[1], 0))
17930 operands[1] = replace_equiv_address_nv (operands[1], addr1);
17931 if (addr2 != XEXP (operands[2], 0))
17932 operands[2] = replace_equiv_address_nv (operands[2], addr2);
17934 count = operands[3];
17935 countreg = ix86_zero_extend_to_Pmode (count);
17937 /* %%% Iff we are testing strict equality, we can use known alignment
17938 to good advantage. This may be possible with combine, particularly
17939 once cc0 is dead. */
17940 align = operands[4];
17942 emit_insn (gen_cld ());
17943 if (GET_CODE (count) == CONST_INT)
17945 if (INTVAL (count) == 0)
17947 emit_move_insn (operands[0], const0_rtx);
17950 emit_insn (gen_cmpstrnqi_nz_1 (addr1, addr2, countreg, align,
17951 operands[1], operands[2]));
17956 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
17958 emit_insn (gen_cmpsi_1 (countreg, countreg));
17959 emit_insn (gen_cmpstrnqi_1 (addr1, addr2, countreg, align,
17960 operands[1], operands[2]));
17963 outlow = gen_lowpart (QImode, out);
17964 emit_insn (gen_cmpintqi (outlow));
17965 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
17967 if (operands[0] != out)
17968 emit_move_insn (operands[0], out);
17973 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
17975 (define_expand "cmpintqi"
17976 [(set (match_dup 1)
17977 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
17979 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
17980 (parallel [(set (match_operand:QI 0 "register_operand" "")
17981 (minus:QI (match_dup 1)
17983 (clobber (reg:CC FLAGS_REG))])]
17985 "operands[1] = gen_reg_rtx (QImode);
17986 operands[2] = gen_reg_rtx (QImode);")
17988 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
17989 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
17991 (define_expand "cmpstrnqi_nz_1"
17992 [(parallel [(set (reg:CC FLAGS_REG)
17993 (compare:CC (match_operand 4 "memory_operand" "")
17994 (match_operand 5 "memory_operand" "")))
17995 (use (match_operand 2 "register_operand" ""))
17996 (use (match_operand:SI 3 "immediate_operand" ""))
17997 (use (reg:SI DIRFLAG_REG))
17998 (clobber (match_operand 0 "register_operand" ""))
17999 (clobber (match_operand 1 "register_operand" ""))
18000 (clobber (match_dup 2))])]
18004 (define_insn "*cmpstrnqi_nz_1"
18005 [(set (reg:CC FLAGS_REG)
18006 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
18007 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
18008 (use (match_operand:SI 6 "register_operand" "2"))
18009 (use (match_operand:SI 3 "immediate_operand" "i"))
18010 (use (reg:SI DIRFLAG_REG))
18011 (clobber (match_operand:SI 0 "register_operand" "=S"))
18012 (clobber (match_operand:SI 1 "register_operand" "=D"))
18013 (clobber (match_operand:SI 2 "register_operand" "=c"))]
18016 [(set_attr "type" "str")
18017 (set_attr "mode" "QI")
18018 (set_attr "prefix_rep" "1")])
18020 (define_insn "*cmpstrnqi_nz_rex_1"
18021 [(set (reg:CC FLAGS_REG)
18022 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
18023 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
18024 (use (match_operand:DI 6 "register_operand" "2"))
18025 (use (match_operand:SI 3 "immediate_operand" "i"))
18026 (use (reg:SI DIRFLAG_REG))
18027 (clobber (match_operand:DI 0 "register_operand" "=S"))
18028 (clobber (match_operand:DI 1 "register_operand" "=D"))
18029 (clobber (match_operand:DI 2 "register_operand" "=c"))]
18032 [(set_attr "type" "str")
18033 (set_attr "mode" "QI")
18034 (set_attr "prefix_rep" "1")])
18036 ;; The same, but the count is not known to not be zero.
18038 (define_expand "cmpstrnqi_1"
18039 [(parallel [(set (reg:CC FLAGS_REG)
18040 (if_then_else:CC (ne (match_operand 2 "register_operand" "")
18042 (compare:CC (match_operand 4 "memory_operand" "")
18043 (match_operand 5 "memory_operand" ""))
18045 (use (match_operand:SI 3 "immediate_operand" ""))
18046 (use (reg:CC FLAGS_REG))
18047 (use (reg:SI DIRFLAG_REG))
18048 (clobber (match_operand 0 "register_operand" ""))
18049 (clobber (match_operand 1 "register_operand" ""))
18050 (clobber (match_dup 2))])]
18054 (define_insn "*cmpstrnqi_1"
18055 [(set (reg:CC FLAGS_REG)
18056 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
18058 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
18059 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
18061 (use (match_operand:SI 3 "immediate_operand" "i"))
18062 (use (reg:CC FLAGS_REG))
18063 (use (reg:SI DIRFLAG_REG))
18064 (clobber (match_operand:SI 0 "register_operand" "=S"))
18065 (clobber (match_operand:SI 1 "register_operand" "=D"))
18066 (clobber (match_operand:SI 2 "register_operand" "=c"))]
18069 [(set_attr "type" "str")
18070 (set_attr "mode" "QI")
18071 (set_attr "prefix_rep" "1")])
18073 (define_insn "*cmpstrnqi_rex_1"
18074 [(set (reg:CC FLAGS_REG)
18075 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
18077 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
18078 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
18080 (use (match_operand:SI 3 "immediate_operand" "i"))
18081 (use (reg:CC FLAGS_REG))
18082 (use (reg:SI DIRFLAG_REG))
18083 (clobber (match_operand:DI 0 "register_operand" "=S"))
18084 (clobber (match_operand:DI 1 "register_operand" "=D"))
18085 (clobber (match_operand:DI 2 "register_operand" "=c"))]
18088 [(set_attr "type" "str")
18089 (set_attr "mode" "QI")
18090 (set_attr "prefix_rep" "1")])
18092 (define_expand "strlensi"
18093 [(set (match_operand:SI 0 "register_operand" "")
18094 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
18095 (match_operand:QI 2 "immediate_operand" "")
18096 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
18099 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
18105 (define_expand "strlendi"
18106 [(set (match_operand:DI 0 "register_operand" "")
18107 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
18108 (match_operand:QI 2 "immediate_operand" "")
18109 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
18112 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
18118 (define_expand "strlenqi_1"
18119 [(parallel [(set (match_operand 0 "register_operand" "") (match_operand 2 "" ""))
18120 (use (reg:SI DIRFLAG_REG))
18121 (clobber (match_operand 1 "register_operand" ""))
18122 (clobber (reg:CC FLAGS_REG))])]
18126 (define_insn "*strlenqi_1"
18127 [(set (match_operand:SI 0 "register_operand" "=&c")
18128 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
18129 (match_operand:QI 2 "register_operand" "a")
18130 (match_operand:SI 3 "immediate_operand" "i")
18131 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
18132 (use (reg:SI DIRFLAG_REG))
18133 (clobber (match_operand:SI 1 "register_operand" "=D"))
18134 (clobber (reg:CC FLAGS_REG))]
18137 [(set_attr "type" "str")
18138 (set_attr "mode" "QI")
18139 (set_attr "prefix_rep" "1")])
18141 (define_insn "*strlenqi_rex_1"
18142 [(set (match_operand:DI 0 "register_operand" "=&c")
18143 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
18144 (match_operand:QI 2 "register_operand" "a")
18145 (match_operand:DI 3 "immediate_operand" "i")
18146 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
18147 (use (reg:SI DIRFLAG_REG))
18148 (clobber (match_operand:DI 1 "register_operand" "=D"))
18149 (clobber (reg:CC FLAGS_REG))]
18152 [(set_attr "type" "str")
18153 (set_attr "mode" "QI")
18154 (set_attr "prefix_rep" "1")])
18156 ;; Peephole optimizations to clean up after cmpstrn*. This should be
18157 ;; handled in combine, but it is not currently up to the task.
18158 ;; When used for their truth value, the cmpstrn* expanders generate
18167 ;; The intermediate three instructions are unnecessary.
18169 ;; This one handles cmpstrn*_nz_1...
18172 (set (reg:CC FLAGS_REG)
18173 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
18174 (mem:BLK (match_operand 5 "register_operand" ""))))
18175 (use (match_operand 6 "register_operand" ""))
18176 (use (match_operand:SI 3 "immediate_operand" ""))
18177 (use (reg:SI DIRFLAG_REG))
18178 (clobber (match_operand 0 "register_operand" ""))
18179 (clobber (match_operand 1 "register_operand" ""))
18180 (clobber (match_operand 2 "register_operand" ""))])
18181 (set (match_operand:QI 7 "register_operand" "")
18182 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
18183 (set (match_operand:QI 8 "register_operand" "")
18184 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
18185 (set (reg FLAGS_REG)
18186 (compare (match_dup 7) (match_dup 8)))
18188 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
18190 (set (reg:CC FLAGS_REG)
18191 (compare:CC (mem:BLK (match_dup 4))
18192 (mem:BLK (match_dup 5))))
18193 (use (match_dup 6))
18194 (use (match_dup 3))
18195 (use (reg:SI DIRFLAG_REG))
18196 (clobber (match_dup 0))
18197 (clobber (match_dup 1))
18198 (clobber (match_dup 2))])]
18201 ;; ...and this one handles cmpstrn*_1.
18204 (set (reg:CC FLAGS_REG)
18205 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
18207 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
18208 (mem:BLK (match_operand 5 "register_operand" "")))
18210 (use (match_operand:SI 3 "immediate_operand" ""))
18211 (use (reg:CC FLAGS_REG))
18212 (use (reg:SI DIRFLAG_REG))
18213 (clobber (match_operand 0 "register_operand" ""))
18214 (clobber (match_operand 1 "register_operand" ""))
18215 (clobber (match_operand 2 "register_operand" ""))])
18216 (set (match_operand:QI 7 "register_operand" "")
18217 (gtu:QI (reg:CC FLAGS_REG) (const_int 0)))
18218 (set (match_operand:QI 8 "register_operand" "")
18219 (ltu:QI (reg:CC FLAGS_REG) (const_int 0)))
18220 (set (reg FLAGS_REG)
18221 (compare (match_dup 7) (match_dup 8)))
18223 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
18225 (set (reg:CC FLAGS_REG)
18226 (if_then_else:CC (ne (match_dup 6)
18228 (compare:CC (mem:BLK (match_dup 4))
18229 (mem:BLK (match_dup 5)))
18231 (use (match_dup 3))
18232 (use (reg:CC FLAGS_REG))
18233 (use (reg:SI DIRFLAG_REG))
18234 (clobber (match_dup 0))
18235 (clobber (match_dup 1))
18236 (clobber (match_dup 2))])]
18241 ;; Conditional move instructions.
18243 (define_expand "movdicc"
18244 [(set (match_operand:DI 0 "register_operand" "")
18245 (if_then_else:DI (match_operand 1 "comparison_operator" "")
18246 (match_operand:DI 2 "general_operand" "")
18247 (match_operand:DI 3 "general_operand" "")))]
18249 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
18251 (define_insn "x86_movdicc_0_m1_rex64"
18252 [(set (match_operand:DI 0 "register_operand" "=r")
18253 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
18256 (clobber (reg:CC FLAGS_REG))]
18259 ; Since we don't have the proper number of operands for an alu insn,
18260 ; fill in all the blanks.
18261 [(set_attr "type" "alu")
18262 (set_attr "pent_pair" "pu")
18263 (set_attr "memory" "none")
18264 (set_attr "imm_disp" "false")
18265 (set_attr "mode" "DI")
18266 (set_attr "length_immediate" "0")])
18268 (define_insn "*movdicc_c_rex64"
18269 [(set (match_operand:DI 0 "register_operand" "=r,r")
18270 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
18271 [(reg FLAGS_REG) (const_int 0)])
18272 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
18273 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
18274 "TARGET_64BIT && TARGET_CMOVE
18275 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18277 cmov%O2%C1\t{%2, %0|%0, %2}
18278 cmov%O2%c1\t{%3, %0|%0, %3}"
18279 [(set_attr "type" "icmov")
18280 (set_attr "mode" "DI")])
18282 (define_expand "movsicc"
18283 [(set (match_operand:SI 0 "register_operand" "")
18284 (if_then_else:SI (match_operand 1 "comparison_operator" "")
18285 (match_operand:SI 2 "general_operand" "")
18286 (match_operand:SI 3 "general_operand" "")))]
18288 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
18290 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
18291 ;; the register first winds up with `sbbl $0,reg', which is also weird.
18292 ;; So just document what we're doing explicitly.
18294 (define_insn "x86_movsicc_0_m1"
18295 [(set (match_operand:SI 0 "register_operand" "=r")
18296 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
18299 (clobber (reg:CC FLAGS_REG))]
18302 ; Since we don't have the proper number of operands for an alu insn,
18303 ; fill in all the blanks.
18304 [(set_attr "type" "alu")
18305 (set_attr "pent_pair" "pu")
18306 (set_attr "memory" "none")
18307 (set_attr "imm_disp" "false")
18308 (set_attr "mode" "SI")
18309 (set_attr "length_immediate" "0")])
18311 (define_insn "*movsicc_noc"
18312 [(set (match_operand:SI 0 "register_operand" "=r,r")
18313 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
18314 [(reg FLAGS_REG) (const_int 0)])
18315 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
18316 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
18318 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18320 cmov%O2%C1\t{%2, %0|%0, %2}
18321 cmov%O2%c1\t{%3, %0|%0, %3}"
18322 [(set_attr "type" "icmov")
18323 (set_attr "mode" "SI")])
18325 (define_expand "movhicc"
18326 [(set (match_operand:HI 0 "register_operand" "")
18327 (if_then_else:HI (match_operand 1 "comparison_operator" "")
18328 (match_operand:HI 2 "general_operand" "")
18329 (match_operand:HI 3 "general_operand" "")))]
18330 "TARGET_HIMODE_MATH"
18331 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
18333 (define_insn "*movhicc_noc"
18334 [(set (match_operand:HI 0 "register_operand" "=r,r")
18335 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
18336 [(reg FLAGS_REG) (const_int 0)])
18337 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
18338 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
18340 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18342 cmov%O2%C1\t{%2, %0|%0, %2}
18343 cmov%O2%c1\t{%3, %0|%0, %3}"
18344 [(set_attr "type" "icmov")
18345 (set_attr "mode" "HI")])
18347 (define_expand "movqicc"
18348 [(set (match_operand:QI 0 "register_operand" "")
18349 (if_then_else:QI (match_operand 1 "comparison_operator" "")
18350 (match_operand:QI 2 "general_operand" "")
18351 (match_operand:QI 3 "general_operand" "")))]
18352 "TARGET_QIMODE_MATH"
18353 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
18355 (define_insn_and_split "*movqicc_noc"
18356 [(set (match_operand:QI 0 "register_operand" "=r,r")
18357 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
18358 [(match_operand 4 "flags_reg_operand" "")
18360 (match_operand:QI 2 "register_operand" "r,0")
18361 (match_operand:QI 3 "register_operand" "0,r")))]
18362 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
18364 "&& reload_completed"
18365 [(set (match_dup 0)
18366 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
18369 "operands[0] = gen_lowpart (SImode, operands[0]);
18370 operands[2] = gen_lowpart (SImode, operands[2]);
18371 operands[3] = gen_lowpart (SImode, operands[3]);"
18372 [(set_attr "type" "icmov")
18373 (set_attr "mode" "SI")])
18375 (define_expand "movsfcc"
18376 [(set (match_operand:SF 0 "register_operand" "")
18377 (if_then_else:SF (match_operand 1 "comparison_operator" "")
18378 (match_operand:SF 2 "register_operand" "")
18379 (match_operand:SF 3 "register_operand" "")))]
18380 "(TARGET_80387 && TARGET_CMOVE) || TARGET_SSE_MATH"
18381 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
18383 (define_insn "*movsfcc_1_387"
18384 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
18385 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
18386 [(reg FLAGS_REG) (const_int 0)])
18387 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
18388 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
18389 "TARGET_80387 && TARGET_CMOVE
18390 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18392 fcmov%F1\t{%2, %0|%0, %2}
18393 fcmov%f1\t{%3, %0|%0, %3}
18394 cmov%O2%C1\t{%2, %0|%0, %2}
18395 cmov%O2%c1\t{%3, %0|%0, %3}"
18396 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
18397 (set_attr "mode" "SF,SF,SI,SI")])
18399 (define_expand "movdfcc"
18400 [(set (match_operand:DF 0 "register_operand" "")
18401 (if_then_else:DF (match_operand 1 "comparison_operator" "")
18402 (match_operand:DF 2 "register_operand" "")
18403 (match_operand:DF 3 "register_operand" "")))]
18404 "(TARGET_80387 && TARGET_CMOVE) || (TARGET_SSE2 && TARGET_SSE_MATH)"
18405 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
18407 (define_insn "*movdfcc_1"
18408 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
18409 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18410 [(reg FLAGS_REG) (const_int 0)])
18411 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
18412 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
18413 "!TARGET_64BIT && TARGET_80387 && TARGET_CMOVE
18414 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18416 fcmov%F1\t{%2, %0|%0, %2}
18417 fcmov%f1\t{%3, %0|%0, %3}
18420 [(set_attr "type" "fcmov,fcmov,multi,multi")
18421 (set_attr "mode" "DF")])
18423 (define_insn "*movdfcc_1_rex64"
18424 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
18425 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18426 [(reg FLAGS_REG) (const_int 0)])
18427 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
18428 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
18429 "TARGET_64BIT && TARGET_80387 && TARGET_CMOVE
18430 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
18432 fcmov%F1\t{%2, %0|%0, %2}
18433 fcmov%f1\t{%3, %0|%0, %3}
18434 cmov%O2%C1\t{%2, %0|%0, %2}
18435 cmov%O2%c1\t{%3, %0|%0, %3}"
18436 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
18437 (set_attr "mode" "DF")])
18440 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
18441 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
18442 [(match_operand 4 "flags_reg_operand" "")
18444 (match_operand:DF 2 "nonimmediate_operand" "")
18445 (match_operand:DF 3 "nonimmediate_operand" "")))]
18446 "!TARGET_64BIT && reload_completed"
18447 [(set (match_dup 2)
18448 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
18452 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
18455 "split_di (operands+2, 1, operands+5, operands+6);
18456 split_di (operands+3, 1, operands+7, operands+8);
18457 split_di (operands, 1, operands+2, operands+3);")
18459 (define_expand "movxfcc"
18460 [(set (match_operand:XF 0 "register_operand" "")
18461 (if_then_else:XF (match_operand 1 "comparison_operator" "")
18462 (match_operand:XF 2 "register_operand" "")
18463 (match_operand:XF 3 "register_operand" "")))]
18464 "TARGET_80387 && TARGET_CMOVE"
18465 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
18467 (define_insn "*movxfcc_1"
18468 [(set (match_operand:XF 0 "register_operand" "=f,f")
18469 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
18470 [(reg FLAGS_REG) (const_int 0)])
18471 (match_operand:XF 2 "register_operand" "f,0")
18472 (match_operand:XF 3 "register_operand" "0,f")))]
18473 "TARGET_80387 && TARGET_CMOVE"
18475 fcmov%F1\t{%2, %0|%0, %2}
18476 fcmov%f1\t{%3, %0|%0, %3}"
18477 [(set_attr "type" "fcmov")
18478 (set_attr "mode" "XF")])
18480 ;; These versions of the min/max patterns are intentionally ignorant of
18481 ;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
18482 ;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
18483 ;; are undefined in this condition, we're certain this is correct.
18485 (define_insn "sminsf3"
18486 [(set (match_operand:SF 0 "register_operand" "=x")
18487 (smin:SF (match_operand:SF 1 "nonimmediate_operand" "%0")
18488 (match_operand:SF 2 "nonimmediate_operand" "xm")))]
18490 "minss\t{%2, %0|%0, %2}"
18491 [(set_attr "type" "sseadd")
18492 (set_attr "mode" "SF")])
18494 (define_insn "smaxsf3"
18495 [(set (match_operand:SF 0 "register_operand" "=x")
18496 (smax:SF (match_operand:SF 1 "nonimmediate_operand" "%0")
18497 (match_operand:SF 2 "nonimmediate_operand" "xm")))]
18499 "maxss\t{%2, %0|%0, %2}"
18500 [(set_attr "type" "sseadd")
18501 (set_attr "mode" "SF")])
18503 (define_insn "smindf3"
18504 [(set (match_operand:DF 0 "register_operand" "=x")
18505 (smin:DF (match_operand:DF 1 "nonimmediate_operand" "%0")
18506 (match_operand:DF 2 "nonimmediate_operand" "xm")))]
18507 "TARGET_SSE2 && TARGET_SSE_MATH"
18508 "minsd\t{%2, %0|%0, %2}"
18509 [(set_attr "type" "sseadd")
18510 (set_attr "mode" "DF")])
18512 (define_insn "smaxdf3"
18513 [(set (match_operand:DF 0 "register_operand" "=x")
18514 (smax:DF (match_operand:DF 1 "nonimmediate_operand" "%0")
18515 (match_operand:DF 2 "nonimmediate_operand" "xm")))]
18516 "TARGET_SSE2 && TARGET_SSE_MATH"
18517 "maxsd\t{%2, %0|%0, %2}"
18518 [(set_attr "type" "sseadd")
18519 (set_attr "mode" "DF")])
18521 ;; These versions of the min/max patterns implement exactly the operations
18522 ;; min = (op1 < op2 ? op1 : op2)
18523 ;; max = (!(op1 < op2) ? op1 : op2)
18524 ;; Their operands are not commutative, and thus they may be used in the
18525 ;; presence of -0.0 and NaN.
18527 (define_insn "*ieee_sminsf3"
18528 [(set (match_operand:SF 0 "register_operand" "=x")
18529 (unspec:SF [(match_operand:SF 1 "register_operand" "0")
18530 (match_operand:SF 2 "nonimmediate_operand" "xm")]
18533 "minss\t{%2, %0|%0, %2}"
18534 [(set_attr "type" "sseadd")
18535 (set_attr "mode" "SF")])
18537 (define_insn "*ieee_smaxsf3"
18538 [(set (match_operand:SF 0 "register_operand" "=x")
18539 (unspec:SF [(match_operand:SF 1 "register_operand" "0")
18540 (match_operand:SF 2 "nonimmediate_operand" "xm")]
18543 "maxss\t{%2, %0|%0, %2}"
18544 [(set_attr "type" "sseadd")
18545 (set_attr "mode" "SF")])
18547 (define_insn "*ieee_smindf3"
18548 [(set (match_operand:DF 0 "register_operand" "=x")
18549 (unspec:DF [(match_operand:DF 1 "register_operand" "0")
18550 (match_operand:DF 2 "nonimmediate_operand" "xm")]
18552 "TARGET_SSE2 && TARGET_SSE_MATH"
18553 "minsd\t{%2, %0|%0, %2}"
18554 [(set_attr "type" "sseadd")
18555 (set_attr "mode" "DF")])
18557 (define_insn "*ieee_smaxdf3"
18558 [(set (match_operand:DF 0 "register_operand" "=x")
18559 (unspec:DF [(match_operand:DF 1 "register_operand" "0")
18560 (match_operand:DF 2 "nonimmediate_operand" "xm")]
18562 "TARGET_SSE2 && TARGET_SSE_MATH"
18563 "maxsd\t{%2, %0|%0, %2}"
18564 [(set_attr "type" "sseadd")
18565 (set_attr "mode" "DF")])
18567 ;; Conditional addition patterns
18568 (define_expand "addqicc"
18569 [(match_operand:QI 0 "register_operand" "")
18570 (match_operand 1 "comparison_operator" "")
18571 (match_operand:QI 2 "register_operand" "")
18572 (match_operand:QI 3 "const_int_operand" "")]
18574 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
18576 (define_expand "addhicc"
18577 [(match_operand:HI 0 "register_operand" "")
18578 (match_operand 1 "comparison_operator" "")
18579 (match_operand:HI 2 "register_operand" "")
18580 (match_operand:HI 3 "const_int_operand" "")]
18582 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
18584 (define_expand "addsicc"
18585 [(match_operand:SI 0 "register_operand" "")
18586 (match_operand 1 "comparison_operator" "")
18587 (match_operand:SI 2 "register_operand" "")
18588 (match_operand:SI 3 "const_int_operand" "")]
18590 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
18592 (define_expand "adddicc"
18593 [(match_operand:DI 0 "register_operand" "")
18594 (match_operand 1 "comparison_operator" "")
18595 (match_operand:DI 2 "register_operand" "")
18596 (match_operand:DI 3 "const_int_operand" "")]
18598 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
18601 ;; Misc patterns (?)
18603 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
18604 ;; Otherwise there will be nothing to keep
18606 ;; [(set (reg ebp) (reg esp))]
18607 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
18608 ;; (clobber (eflags)]
18609 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
18611 ;; in proper program order.
18612 (define_insn "pro_epilogue_adjust_stack_1"
18613 [(set (match_operand:SI 0 "register_operand" "=r,r")
18614 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
18615 (match_operand:SI 2 "immediate_operand" "i,i")))
18616 (clobber (reg:CC FLAGS_REG))
18617 (clobber (mem:BLK (scratch)))]
18620 switch (get_attr_type (insn))
18623 return "mov{l}\t{%1, %0|%0, %1}";
18626 if (GET_CODE (operands[2]) == CONST_INT
18627 && (INTVAL (operands[2]) == 128
18628 || (INTVAL (operands[2]) < 0
18629 && INTVAL (operands[2]) != -128)))
18631 operands[2] = GEN_INT (-INTVAL (operands[2]));
18632 return "sub{l}\t{%2, %0|%0, %2}";
18634 return "add{l}\t{%2, %0|%0, %2}";
18637 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18638 return "lea{l}\t{%a2, %0|%0, %a2}";
18641 gcc_unreachable ();
18644 [(set (attr "type")
18645 (cond [(eq_attr "alternative" "0")
18646 (const_string "alu")
18647 (match_operand:SI 2 "const0_operand" "")
18648 (const_string "imov")
18650 (const_string "lea")))
18651 (set_attr "mode" "SI")])
18653 (define_insn "pro_epilogue_adjust_stack_rex64"
18654 [(set (match_operand:DI 0 "register_operand" "=r,r")
18655 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18656 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
18657 (clobber (reg:CC FLAGS_REG))
18658 (clobber (mem:BLK (scratch)))]
18661 switch (get_attr_type (insn))
18664 return "mov{q}\t{%1, %0|%0, %1}";
18667 if (GET_CODE (operands[2]) == CONST_INT
18668 /* Avoid overflows. */
18669 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
18670 && (INTVAL (operands[2]) == 128
18671 || (INTVAL (operands[2]) < 0
18672 && INTVAL (operands[2]) != -128)))
18674 operands[2] = GEN_INT (-INTVAL (operands[2]));
18675 return "sub{q}\t{%2, %0|%0, %2}";
18677 return "add{q}\t{%2, %0|%0, %2}";
18680 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
18681 return "lea{q}\t{%a2, %0|%0, %a2}";
18684 gcc_unreachable ();
18687 [(set (attr "type")
18688 (cond [(eq_attr "alternative" "0")
18689 (const_string "alu")
18690 (match_operand:DI 2 "const0_operand" "")
18691 (const_string "imov")
18693 (const_string "lea")))
18694 (set_attr "mode" "DI")])
18696 (define_insn "pro_epilogue_adjust_stack_rex64_2"
18697 [(set (match_operand:DI 0 "register_operand" "=r,r")
18698 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
18699 (match_operand:DI 3 "immediate_operand" "i,i")))
18700 (use (match_operand:DI 2 "register_operand" "r,r"))
18701 (clobber (reg:CC FLAGS_REG))
18702 (clobber (mem:BLK (scratch)))]
18705 switch (get_attr_type (insn))
18708 return "add{q}\t{%2, %0|%0, %2}";
18711 operands[2] = gen_rtx_PLUS (DImode, operands[1], operands[2]);
18712 return "lea{q}\t{%a2, %0|%0, %a2}";
18715 gcc_unreachable ();
18718 [(set_attr "type" "alu,lea")
18719 (set_attr "mode" "DI")])
18721 (define_expand "allocate_stack_worker"
18722 [(match_operand:SI 0 "register_operand" "")]
18723 "TARGET_STACK_PROBE"
18725 if (reload_completed)
18728 emit_insn (gen_allocate_stack_worker_rex64_postreload (operands[0]));
18730 emit_insn (gen_allocate_stack_worker_postreload (operands[0]));
18735 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
18737 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
18742 (define_insn "allocate_stack_worker_1"
18743 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18744 UNSPECV_STACK_PROBE)
18745 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18746 (clobber (match_scratch:SI 1 "=0"))
18747 (clobber (reg:CC FLAGS_REG))]
18748 "!TARGET_64BIT && TARGET_STACK_PROBE"
18750 [(set_attr "type" "multi")
18751 (set_attr "length" "5")])
18753 (define_expand "allocate_stack_worker_postreload"
18754 [(parallel [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "a")]
18755 UNSPECV_STACK_PROBE)
18756 (set (reg:SI SP_REG) (minus:SI (reg:SI SP_REG) (match_dup 0)))
18757 (clobber (match_dup 0))
18758 (clobber (reg:CC FLAGS_REG))])]
18762 (define_insn "allocate_stack_worker_rex64"
18763 [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18764 UNSPECV_STACK_PROBE)
18765 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18766 (clobber (match_scratch:DI 1 "=0"))
18767 (clobber (reg:CC FLAGS_REG))]
18768 "TARGET_64BIT && TARGET_STACK_PROBE"
18770 [(set_attr "type" "multi")
18771 (set_attr "length" "5")])
18773 (define_expand "allocate_stack_worker_rex64_postreload"
18774 [(parallel [(unspec_volatile:DI [(match_operand:DI 0 "register_operand" "a")]
18775 UNSPECV_STACK_PROBE)
18776 (set (reg:DI SP_REG) (minus:DI (reg:DI SP_REG) (match_dup 0)))
18777 (clobber (match_dup 0))
18778 (clobber (reg:CC FLAGS_REG))])]
18782 (define_expand "allocate_stack"
18783 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
18784 (minus:SI (reg:SI SP_REG)
18785 (match_operand:SI 1 "general_operand" "")))
18786 (clobber (reg:CC FLAGS_REG))])
18787 (parallel [(set (reg:SI SP_REG)
18788 (minus:SI (reg:SI SP_REG) (match_dup 1)))
18789 (clobber (reg:CC FLAGS_REG))])]
18790 "TARGET_STACK_PROBE"
18792 #ifdef CHECK_STACK_LIMIT
18793 if (GET_CODE (operands[1]) == CONST_INT
18794 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
18795 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
18799 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
18802 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
18806 (define_expand "builtin_setjmp_receiver"
18807 [(label_ref (match_operand 0 "" ""))]
18808 "!TARGET_64BIT && flag_pic"
18810 emit_insn (gen_set_got (pic_offset_table_rtx));
18814 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
18817 [(set (match_operand 0 "register_operand" "")
18818 (match_operator 3 "promotable_binary_operator"
18819 [(match_operand 1 "register_operand" "")
18820 (match_operand 2 "aligned_operand" "")]))
18821 (clobber (reg:CC FLAGS_REG))]
18822 "! TARGET_PARTIAL_REG_STALL && reload_completed
18823 && ((GET_MODE (operands[0]) == HImode
18824 && ((!optimize_size && !TARGET_FAST_PREFIX)
18825 || GET_CODE (operands[2]) != CONST_INT
18826 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
18827 || (GET_MODE (operands[0]) == QImode
18828 && (TARGET_PROMOTE_QImode || optimize_size)))"
18829 [(parallel [(set (match_dup 0)
18830 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18831 (clobber (reg:CC FLAGS_REG))])]
18832 "operands[0] = gen_lowpart (SImode, operands[0]);
18833 operands[1] = gen_lowpart (SImode, operands[1]);
18834 if (GET_CODE (operands[3]) != ASHIFT)
18835 operands[2] = gen_lowpart (SImode, operands[2]);
18836 PUT_MODE (operands[3], SImode);")
18838 ; Promote the QImode tests, as i386 has encoding of the AND
18839 ; instruction with 32-bit sign-extended immediate and thus the
18840 ; instruction size is unchanged, except in the %eax case for
18841 ; which it is increased by one byte, hence the ! optimize_size.
18843 [(set (match_operand 0 "flags_reg_operand" "")
18844 (match_operator 2 "compare_operator"
18845 [(and (match_operand 3 "aligned_operand" "")
18846 (match_operand 4 "const_int_operand" ""))
18848 (set (match_operand 1 "register_operand" "")
18849 (and (match_dup 3) (match_dup 4)))]
18850 "! TARGET_PARTIAL_REG_STALL && reload_completed
18851 /* Ensure that the operand will remain sign-extended immediate. */
18852 && ix86_match_ccmode (insn, INTVAL (operands[4]) >= 0 ? CCNOmode : CCZmode)
18854 && ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX)
18855 || (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))"
18856 [(parallel [(set (match_dup 0)
18857 (match_op_dup 2 [(and:SI (match_dup 3) (match_dup 4))
18860 (and:SI (match_dup 3) (match_dup 4)))])]
18863 = gen_int_mode (INTVAL (operands[4])
18864 & GET_MODE_MASK (GET_MODE (operands[1])), SImode);
18865 operands[1] = gen_lowpart (SImode, operands[1]);
18866 operands[3] = gen_lowpart (SImode, operands[3]);
18869 ; Don't promote the QImode tests, as i386 doesn't have encoding of
18870 ; the TEST instruction with 32-bit sign-extended immediate and thus
18871 ; the instruction size would at least double, which is not what we
18872 ; want even with ! optimize_size.
18874 [(set (match_operand 0 "flags_reg_operand" "")
18875 (match_operator 1 "compare_operator"
18876 [(and (match_operand:HI 2 "aligned_operand" "")
18877 (match_operand:HI 3 "const_int_operand" ""))
18879 "! TARGET_PARTIAL_REG_STALL && reload_completed
18880 /* Ensure that the operand will remain sign-extended immediate. */
18881 && ix86_match_ccmode (insn, INTVAL (operands[3]) >= 0 ? CCNOmode : CCZmode)
18882 && ! TARGET_FAST_PREFIX
18883 && ! optimize_size"
18884 [(set (match_dup 0)
18885 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
18889 = gen_int_mode (INTVAL (operands[3])
18890 & GET_MODE_MASK (GET_MODE (operands[2])), SImode);
18891 operands[2] = gen_lowpart (SImode, operands[2]);
18895 [(set (match_operand 0 "register_operand" "")
18896 (neg (match_operand 1 "register_operand" "")))
18897 (clobber (reg:CC FLAGS_REG))]
18898 "! TARGET_PARTIAL_REG_STALL && reload_completed
18899 && (GET_MODE (operands[0]) == HImode
18900 || (GET_MODE (operands[0]) == QImode
18901 && (TARGET_PROMOTE_QImode || optimize_size)))"
18902 [(parallel [(set (match_dup 0)
18903 (neg:SI (match_dup 1)))
18904 (clobber (reg:CC FLAGS_REG))])]
18905 "operands[0] = gen_lowpart (SImode, operands[0]);
18906 operands[1] = gen_lowpart (SImode, operands[1]);")
18909 [(set (match_operand 0 "register_operand" "")
18910 (not (match_operand 1 "register_operand" "")))]
18911 "! TARGET_PARTIAL_REG_STALL && reload_completed
18912 && (GET_MODE (operands[0]) == HImode
18913 || (GET_MODE (operands[0]) == QImode
18914 && (TARGET_PROMOTE_QImode || optimize_size)))"
18915 [(set (match_dup 0)
18916 (not:SI (match_dup 1)))]
18917 "operands[0] = gen_lowpart (SImode, operands[0]);
18918 operands[1] = gen_lowpart (SImode, operands[1]);")
18921 [(set (match_operand 0 "register_operand" "")
18922 (if_then_else (match_operator 1 "comparison_operator"
18923 [(reg FLAGS_REG) (const_int 0)])
18924 (match_operand 2 "register_operand" "")
18925 (match_operand 3 "register_operand" "")))]
18926 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
18927 && (GET_MODE (operands[0]) == HImode
18928 || (GET_MODE (operands[0]) == QImode
18929 && (TARGET_PROMOTE_QImode || optimize_size)))"
18930 [(set (match_dup 0)
18931 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
18932 "operands[0] = gen_lowpart (SImode, operands[0]);
18933 operands[2] = gen_lowpart (SImode, operands[2]);
18934 operands[3] = gen_lowpart (SImode, operands[3]);")
18937 ;; RTL Peephole optimizations, run before sched2. These primarily look to
18938 ;; transform a complex memory operation into two memory to register operations.
18940 ;; Don't push memory operands
18942 [(set (match_operand:SI 0 "push_operand" "")
18943 (match_operand:SI 1 "memory_operand" ""))
18944 (match_scratch:SI 2 "r")]
18945 "!optimize_size && !TARGET_PUSH_MEMORY
18946 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
18947 [(set (match_dup 2) (match_dup 1))
18948 (set (match_dup 0) (match_dup 2))]
18952 [(set (match_operand:DI 0 "push_operand" "")
18953 (match_operand:DI 1 "memory_operand" ""))
18954 (match_scratch:DI 2 "r")]
18955 "!optimize_size && !TARGET_PUSH_MEMORY
18956 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
18957 [(set (match_dup 2) (match_dup 1))
18958 (set (match_dup 0) (match_dup 2))]
18961 ;; We need to handle SFmode only, because DFmode and XFmode is split to
18964 [(set (match_operand:SF 0 "push_operand" "")
18965 (match_operand:SF 1 "memory_operand" ""))
18966 (match_scratch:SF 2 "r")]
18967 "!optimize_size && !TARGET_PUSH_MEMORY
18968 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
18969 [(set (match_dup 2) (match_dup 1))
18970 (set (match_dup 0) (match_dup 2))]
18974 [(set (match_operand:HI 0 "push_operand" "")
18975 (match_operand:HI 1 "memory_operand" ""))
18976 (match_scratch:HI 2 "r")]
18977 "!optimize_size && !TARGET_PUSH_MEMORY
18978 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
18979 [(set (match_dup 2) (match_dup 1))
18980 (set (match_dup 0) (match_dup 2))]
18984 [(set (match_operand:QI 0 "push_operand" "")
18985 (match_operand:QI 1 "memory_operand" ""))
18986 (match_scratch:QI 2 "q")]
18987 "!optimize_size && !TARGET_PUSH_MEMORY
18988 && !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
18989 [(set (match_dup 2) (match_dup 1))
18990 (set (match_dup 0) (match_dup 2))]
18993 ;; Don't move an immediate directly to memory when the instruction
18996 [(match_scratch:SI 1 "r")
18997 (set (match_operand:SI 0 "memory_operand" "")
19000 && ! TARGET_USE_MOV0
19001 && TARGET_SPLIT_LONG_MOVES
19002 && get_attr_length (insn) >= ix86_cost->large_insn
19003 && peep2_regno_dead_p (0, FLAGS_REG)"
19004 [(parallel [(set (match_dup 1) (const_int 0))
19005 (clobber (reg:CC FLAGS_REG))])
19006 (set (match_dup 0) (match_dup 1))]
19010 [(match_scratch:HI 1 "r")
19011 (set (match_operand:HI 0 "memory_operand" "")
19014 && ! TARGET_USE_MOV0
19015 && TARGET_SPLIT_LONG_MOVES
19016 && get_attr_length (insn) >= ix86_cost->large_insn
19017 && peep2_regno_dead_p (0, FLAGS_REG)"
19018 [(parallel [(set (match_dup 2) (const_int 0))
19019 (clobber (reg:CC FLAGS_REG))])
19020 (set (match_dup 0) (match_dup 1))]
19021 "operands[2] = gen_lowpart (SImode, operands[1]);")
19024 [(match_scratch:QI 1 "q")
19025 (set (match_operand:QI 0 "memory_operand" "")
19028 && ! TARGET_USE_MOV0
19029 && TARGET_SPLIT_LONG_MOVES
19030 && get_attr_length (insn) >= ix86_cost->large_insn
19031 && peep2_regno_dead_p (0, FLAGS_REG)"
19032 [(parallel [(set (match_dup 2) (const_int 0))
19033 (clobber (reg:CC FLAGS_REG))])
19034 (set (match_dup 0) (match_dup 1))]
19035 "operands[2] = gen_lowpart (SImode, operands[1]);")
19038 [(match_scratch:SI 2 "r")
19039 (set (match_operand:SI 0 "memory_operand" "")
19040 (match_operand:SI 1 "immediate_operand" ""))]
19042 && get_attr_length (insn) >= ix86_cost->large_insn
19043 && TARGET_SPLIT_LONG_MOVES"
19044 [(set (match_dup 2) (match_dup 1))
19045 (set (match_dup 0) (match_dup 2))]
19049 [(match_scratch:HI 2 "r")
19050 (set (match_operand:HI 0 "memory_operand" "")
19051 (match_operand:HI 1 "immediate_operand" ""))]
19052 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
19053 && TARGET_SPLIT_LONG_MOVES"
19054 [(set (match_dup 2) (match_dup 1))
19055 (set (match_dup 0) (match_dup 2))]
19059 [(match_scratch:QI 2 "q")
19060 (set (match_operand:QI 0 "memory_operand" "")
19061 (match_operand:QI 1 "immediate_operand" ""))]
19062 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
19063 && TARGET_SPLIT_LONG_MOVES"
19064 [(set (match_dup 2) (match_dup 1))
19065 (set (match_dup 0) (match_dup 2))]
19068 ;; Don't compare memory with zero, load and use a test instead.
19070 [(set (match_operand 0 "flags_reg_operand" "")
19071 (match_operator 1 "compare_operator"
19072 [(match_operand:SI 2 "memory_operand" "")
19074 (match_scratch:SI 3 "r")]
19075 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
19076 [(set (match_dup 3) (match_dup 2))
19077 (set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))]
19080 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
19081 ;; Don't split NOTs with a displacement operand, because resulting XOR
19082 ;; will not be pairable anyway.
19084 ;; On AMD K6, NOT is vector decoded with memory operand that cannot be
19085 ;; represented using a modRM byte. The XOR replacement is long decoded,
19086 ;; so this split helps here as well.
19088 ;; Note: Can't do this as a regular split because we can't get proper
19089 ;; lifetime information then.
19092 [(set (match_operand:SI 0 "nonimmediate_operand" "")
19093 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
19095 && peep2_regno_dead_p (0, FLAGS_REG)
19096 && ((TARGET_PENTIUM
19097 && (GET_CODE (operands[0]) != MEM
19098 || !memory_displacement_operand (operands[0], SImode)))
19099 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
19100 [(parallel [(set (match_dup 0)
19101 (xor:SI (match_dup 1) (const_int -1)))
19102 (clobber (reg:CC FLAGS_REG))])]
19106 [(set (match_operand:HI 0 "nonimmediate_operand" "")
19107 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
19109 && peep2_regno_dead_p (0, FLAGS_REG)
19110 && ((TARGET_PENTIUM
19111 && (GET_CODE (operands[0]) != MEM
19112 || !memory_displacement_operand (operands[0], HImode)))
19113 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
19114 [(parallel [(set (match_dup 0)
19115 (xor:HI (match_dup 1) (const_int -1)))
19116 (clobber (reg:CC FLAGS_REG))])]
19120 [(set (match_operand:QI 0 "nonimmediate_operand" "")
19121 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
19123 && peep2_regno_dead_p (0, FLAGS_REG)
19124 && ((TARGET_PENTIUM
19125 && (GET_CODE (operands[0]) != MEM
19126 || !memory_displacement_operand (operands[0], QImode)))
19127 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
19128 [(parallel [(set (match_dup 0)
19129 (xor:QI (match_dup 1) (const_int -1)))
19130 (clobber (reg:CC FLAGS_REG))])]
19133 ;; Non pairable "test imm, reg" instructions can be translated to
19134 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
19135 ;; byte opcode instead of two, have a short form for byte operands),
19136 ;; so do it for other CPUs as well. Given that the value was dead,
19137 ;; this should not create any new dependencies. Pass on the sub-word
19138 ;; versions if we're concerned about partial register stalls.
19141 [(set (match_operand 0 "flags_reg_operand" "")
19142 (match_operator 1 "compare_operator"
19143 [(and:SI (match_operand:SI 2 "register_operand" "")
19144 (match_operand:SI 3 "immediate_operand" ""))
19146 "ix86_match_ccmode (insn, CCNOmode)
19147 && (true_regnum (operands[2]) != 0
19148 || (GET_CODE (operands[3]) == CONST_INT
19149 && CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'K')))
19150 && peep2_reg_dead_p (1, operands[2])"
19152 [(set (match_dup 0)
19153 (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
19156 (and:SI (match_dup 2) (match_dup 3)))])]
19159 ;; We don't need to handle HImode case, because it will be promoted to SImode
19160 ;; on ! TARGET_PARTIAL_REG_STALL
19163 [(set (match_operand 0 "flags_reg_operand" "")
19164 (match_operator 1 "compare_operator"
19165 [(and:QI (match_operand:QI 2 "register_operand" "")
19166 (match_operand:QI 3 "immediate_operand" ""))
19168 "! TARGET_PARTIAL_REG_STALL
19169 && ix86_match_ccmode (insn, CCNOmode)
19170 && true_regnum (operands[2]) != 0
19171 && peep2_reg_dead_p (1, operands[2])"
19173 [(set (match_dup 0)
19174 (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
19177 (and:QI (match_dup 2) (match_dup 3)))])]
19181 [(set (match_operand 0 "flags_reg_operand" "")
19182 (match_operator 1 "compare_operator"
19185 (match_operand 2 "ext_register_operand" "")
19188 (match_operand 3 "const_int_operand" ""))
19190 "! TARGET_PARTIAL_REG_STALL
19191 && ix86_match_ccmode (insn, CCNOmode)
19192 && true_regnum (operands[2]) != 0
19193 && peep2_reg_dead_p (1, operands[2])"
19194 [(parallel [(set (match_dup 0)
19203 (set (zero_extract:SI (match_dup 2)
19214 ;; Don't do logical operations with memory inputs.
19216 [(match_scratch:SI 2 "r")
19217 (parallel [(set (match_operand:SI 0 "register_operand" "")
19218 (match_operator:SI 3 "arith_or_logical_operator"
19220 (match_operand:SI 1 "memory_operand" "")]))
19221 (clobber (reg:CC FLAGS_REG))])]
19222 "! optimize_size && ! TARGET_READ_MODIFY"
19223 [(set (match_dup 2) (match_dup 1))
19224 (parallel [(set (match_dup 0)
19225 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
19226 (clobber (reg:CC FLAGS_REG))])]
19230 [(match_scratch:SI 2 "r")
19231 (parallel [(set (match_operand:SI 0 "register_operand" "")
19232 (match_operator:SI 3 "arith_or_logical_operator"
19233 [(match_operand:SI 1 "memory_operand" "")
19235 (clobber (reg:CC FLAGS_REG))])]
19236 "! optimize_size && ! TARGET_READ_MODIFY"
19237 [(set (match_dup 2) (match_dup 1))
19238 (parallel [(set (match_dup 0)
19239 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
19240 (clobber (reg:CC FLAGS_REG))])]
19243 ; Don't do logical operations with memory outputs
19245 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
19246 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
19247 ; the same decoder scheduling characteristics as the original.
19250 [(match_scratch:SI 2 "r")
19251 (parallel [(set (match_operand:SI 0 "memory_operand" "")
19252 (match_operator:SI 3 "arith_or_logical_operator"
19254 (match_operand:SI 1 "nonmemory_operand" "")]))
19255 (clobber (reg:CC FLAGS_REG))])]
19256 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
19257 [(set (match_dup 2) (match_dup 0))
19258 (parallel [(set (match_dup 2)
19259 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
19260 (clobber (reg:CC FLAGS_REG))])
19261 (set (match_dup 0) (match_dup 2))]
19265 [(match_scratch:SI 2 "r")
19266 (parallel [(set (match_operand:SI 0 "memory_operand" "")
19267 (match_operator:SI 3 "arith_or_logical_operator"
19268 [(match_operand:SI 1 "nonmemory_operand" "")
19270 (clobber (reg:CC FLAGS_REG))])]
19271 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
19272 [(set (match_dup 2) (match_dup 0))
19273 (parallel [(set (match_dup 2)
19274 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
19275 (clobber (reg:CC FLAGS_REG))])
19276 (set (match_dup 0) (match_dup 2))]
19279 ;; Attempt to always use XOR for zeroing registers.
19281 [(set (match_operand 0 "register_operand" "")
19282 (match_operand 1 "const0_operand" ""))]
19283 "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
19284 && (! TARGET_USE_MOV0 || optimize_size)
19285 && GENERAL_REG_P (operands[0])
19286 && peep2_regno_dead_p (0, FLAGS_REG)"
19287 [(parallel [(set (match_dup 0) (const_int 0))
19288 (clobber (reg:CC FLAGS_REG))])]
19290 operands[0] = gen_lowpart (word_mode, operands[0]);
19294 [(set (strict_low_part (match_operand 0 "register_operand" ""))
19296 "(GET_MODE (operands[0]) == QImode
19297 || GET_MODE (operands[0]) == HImode)
19298 && (! TARGET_USE_MOV0 || optimize_size)
19299 && peep2_regno_dead_p (0, FLAGS_REG)"
19300 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
19301 (clobber (reg:CC FLAGS_REG))])])
19303 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
19305 [(set (match_operand 0 "register_operand" "")
19307 "(GET_MODE (operands[0]) == HImode
19308 || GET_MODE (operands[0]) == SImode
19309 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
19310 && (optimize_size || TARGET_PENTIUM)
19311 && peep2_regno_dead_p (0, FLAGS_REG)"
19312 [(parallel [(set (match_dup 0) (const_int -1))
19313 (clobber (reg:CC FLAGS_REG))])]
19314 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
19317 ;; Attempt to convert simple leas to adds. These can be created by
19320 [(set (match_operand:SI 0 "register_operand" "")
19321 (plus:SI (match_dup 0)
19322 (match_operand:SI 1 "nonmemory_operand" "")))]
19323 "peep2_regno_dead_p (0, FLAGS_REG)"
19324 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
19325 (clobber (reg:CC FLAGS_REG))])]
19329 [(set (match_operand:SI 0 "register_operand" "")
19330 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
19331 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
19332 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
19333 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
19334 (clobber (reg:CC FLAGS_REG))])]
19335 "operands[2] = gen_lowpart (SImode, operands[2]);")
19338 [(set (match_operand:DI 0 "register_operand" "")
19339 (plus:DI (match_dup 0)
19340 (match_operand:DI 1 "x86_64_general_operand" "")))]
19341 "peep2_regno_dead_p (0, FLAGS_REG)"
19342 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
19343 (clobber (reg:CC FLAGS_REG))])]
19347 [(set (match_operand:SI 0 "register_operand" "")
19348 (mult:SI (match_dup 0)
19349 (match_operand:SI 1 "const_int_operand" "")))]
19350 "exact_log2 (INTVAL (operands[1])) >= 0
19351 && peep2_regno_dead_p (0, FLAGS_REG)"
19352 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19353 (clobber (reg:CC FLAGS_REG))])]
19354 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19357 [(set (match_operand:DI 0 "register_operand" "")
19358 (mult:DI (match_dup 0)
19359 (match_operand:DI 1 "const_int_operand" "")))]
19360 "exact_log2 (INTVAL (operands[1])) >= 0
19361 && peep2_regno_dead_p (0, FLAGS_REG)"
19362 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
19363 (clobber (reg:CC FLAGS_REG))])]
19364 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
19367 [(set (match_operand:SI 0 "register_operand" "")
19368 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
19369 (match_operand:DI 2 "const_int_operand" "")) 0))]
19370 "exact_log2 (INTVAL (operands[2])) >= 0
19371 && REGNO (operands[0]) == REGNO (operands[1])
19372 && peep2_regno_dead_p (0, FLAGS_REG)"
19373 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
19374 (clobber (reg:CC FLAGS_REG))])]
19375 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
19377 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
19378 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
19379 ;; many CPUs it is also faster, since special hardware to avoid esp
19380 ;; dependencies is present.
19382 ;; While some of these conversions may be done using splitters, we use peepholes
19383 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
19385 ;; Convert prologue esp subtractions to push.
19386 ;; We need register to push. In order to keep verify_flow_info happy we have
19388 ;; - use scratch and clobber it in order to avoid dependencies
19389 ;; - use already live register
19390 ;; We can't use the second way right now, since there is no reliable way how to
19391 ;; verify that given register is live. First choice will also most likely in
19392 ;; fewer dependencies. On the place of esp adjustments it is very likely that
19393 ;; call clobbered registers are dead. We may want to use base pointer as an
19394 ;; alternative when no register is available later.
19397 [(match_scratch:SI 0 "r")
19398 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19399 (clobber (reg:CC FLAGS_REG))
19400 (clobber (mem:BLK (scratch)))])]
19401 "optimize_size || !TARGET_SUB_ESP_4"
19402 [(clobber (match_dup 0))
19403 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19404 (clobber (mem:BLK (scratch)))])])
19407 [(match_scratch:SI 0 "r")
19408 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19409 (clobber (reg:CC FLAGS_REG))
19410 (clobber (mem:BLK (scratch)))])]
19411 "optimize_size || !TARGET_SUB_ESP_8"
19412 [(clobber (match_dup 0))
19413 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19414 (parallel [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19415 (clobber (mem:BLK (scratch)))])])
19417 ;; Convert esp subtractions to push.
19419 [(match_scratch:SI 0 "r")
19420 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
19421 (clobber (reg:CC FLAGS_REG))])]
19422 "optimize_size || !TARGET_SUB_ESP_4"
19423 [(clobber (match_dup 0))
19424 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19427 [(match_scratch:SI 0 "r")
19428 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -8)))
19429 (clobber (reg:CC FLAGS_REG))])]
19430 "optimize_size || !TARGET_SUB_ESP_8"
19431 [(clobber (match_dup 0))
19432 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))
19433 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 0))])
19435 ;; Convert epilogue deallocator to pop.
19437 [(match_scratch:SI 0 "r")
19438 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19439 (clobber (reg:CC FLAGS_REG))
19440 (clobber (mem:BLK (scratch)))])]
19441 "optimize_size || !TARGET_ADD_ESP_4"
19442 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19443 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19444 (clobber (mem:BLK (scratch)))])]
19447 ;; Two pops case is tricky, since pop causes dependency on destination register.
19448 ;; We use two registers if available.
19450 [(match_scratch:SI 0 "r")
19451 (match_scratch:SI 1 "r")
19452 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19453 (clobber (reg:CC FLAGS_REG))
19454 (clobber (mem:BLK (scratch)))])]
19455 "optimize_size || !TARGET_ADD_ESP_8"
19456 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19457 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19458 (clobber (mem:BLK (scratch)))])
19459 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19460 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19464 [(match_scratch:SI 0 "r")
19465 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19466 (clobber (reg:CC FLAGS_REG))
19467 (clobber (mem:BLK (scratch)))])]
19469 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19470 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19471 (clobber (mem:BLK (scratch)))])
19472 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19473 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19476 ;; Convert esp additions to pop.
19478 [(match_scratch:SI 0 "r")
19479 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
19480 (clobber (reg:CC FLAGS_REG))])]
19482 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19483 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19486 ;; Two pops case is tricky, since pop causes dependency on destination register.
19487 ;; We use two registers if available.
19489 [(match_scratch:SI 0 "r")
19490 (match_scratch:SI 1 "r")
19491 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19492 (clobber (reg:CC FLAGS_REG))])]
19494 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19495 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19496 (parallel [(set (match_dup 1) (mem:SI (reg:SI SP_REG)))
19497 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19501 [(match_scratch:SI 0 "r")
19502 (parallel [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
19503 (clobber (reg:CC FLAGS_REG))])]
19505 [(parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19506 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])
19507 (parallel [(set (match_dup 0) (mem:SI (reg:SI SP_REG)))
19508 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))])]
19511 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
19512 ;; required and register dies. Similarly for 128 to plus -128.
19514 [(set (match_operand 0 "flags_reg_operand" "")
19515 (match_operator 1 "compare_operator"
19516 [(match_operand 2 "register_operand" "")
19517 (match_operand 3 "const_int_operand" "")]))]
19518 "(INTVAL (operands[3]) == -1
19519 || INTVAL (operands[3]) == 1
19520 || INTVAL (operands[3]) == 128)
19521 && ix86_match_ccmode (insn, CCGCmode)
19522 && peep2_reg_dead_p (1, operands[2])"
19523 [(parallel [(set (match_dup 0)
19524 (match_op_dup 1 [(match_dup 2) (match_dup 3)]))
19525 (clobber (match_dup 2))])]
19529 [(match_scratch:DI 0 "r")
19530 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19531 (clobber (reg:CC FLAGS_REG))
19532 (clobber (mem:BLK (scratch)))])]
19533 "optimize_size || !TARGET_SUB_ESP_4"
19534 [(clobber (match_dup 0))
19535 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19536 (clobber (mem:BLK (scratch)))])])
19539 [(match_scratch:DI 0 "r")
19540 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19541 (clobber (reg:CC FLAGS_REG))
19542 (clobber (mem:BLK (scratch)))])]
19543 "optimize_size || !TARGET_SUB_ESP_8"
19544 [(clobber (match_dup 0))
19545 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19546 (parallel [(set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19547 (clobber (mem:BLK (scratch)))])])
19549 ;; Convert esp subtractions to push.
19551 [(match_scratch:DI 0 "r")
19552 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -8)))
19553 (clobber (reg:CC FLAGS_REG))])]
19554 "optimize_size || !TARGET_SUB_ESP_4"
19555 [(clobber (match_dup 0))
19556 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19559 [(match_scratch:DI 0 "r")
19560 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int -16)))
19561 (clobber (reg:CC FLAGS_REG))])]
19562 "optimize_size || !TARGET_SUB_ESP_8"
19563 [(clobber (match_dup 0))
19564 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))
19565 (set (mem:DI (pre_dec:DI (reg:DI SP_REG))) (match_dup 0))])
19567 ;; Convert epilogue deallocator to pop.
19569 [(match_scratch:DI 0 "r")
19570 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19571 (clobber (reg:CC FLAGS_REG))
19572 (clobber (mem:BLK (scratch)))])]
19573 "optimize_size || !TARGET_ADD_ESP_4"
19574 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19575 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19576 (clobber (mem:BLK (scratch)))])]
19579 ;; Two pops case is tricky, since pop causes dependency on destination register.
19580 ;; We use two registers if available.
19582 [(match_scratch:DI 0 "r")
19583 (match_scratch:DI 1 "r")
19584 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19585 (clobber (reg:CC FLAGS_REG))
19586 (clobber (mem:BLK (scratch)))])]
19587 "optimize_size || !TARGET_ADD_ESP_8"
19588 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19589 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19590 (clobber (mem:BLK (scratch)))])
19591 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19592 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19596 [(match_scratch:DI 0 "r")
19597 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19598 (clobber (reg:CC FLAGS_REG))
19599 (clobber (mem:BLK (scratch)))])]
19601 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19602 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19603 (clobber (mem:BLK (scratch)))])
19604 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19605 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19608 ;; Convert esp additions to pop.
19610 [(match_scratch:DI 0 "r")
19611 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))
19612 (clobber (reg:CC FLAGS_REG))])]
19614 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19615 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19618 ;; Two pops case is tricky, since pop causes dependency on destination register.
19619 ;; We use two registers if available.
19621 [(match_scratch:DI 0 "r")
19622 (match_scratch:DI 1 "r")
19623 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19624 (clobber (reg:CC FLAGS_REG))])]
19626 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19627 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19628 (parallel [(set (match_dup 1) (mem:DI (reg:DI SP_REG)))
19629 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19633 [(match_scratch:DI 0 "r")
19634 (parallel [(set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 16)))
19635 (clobber (reg:CC FLAGS_REG))])]
19637 [(parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19638 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])
19639 (parallel [(set (match_dup 0) (mem:DI (reg:DI SP_REG)))
19640 (set (reg:DI SP_REG) (plus:DI (reg:DI SP_REG) (const_int 8)))])]
19643 ;; Convert imul by three, five and nine into lea
19646 [(set (match_operand:SI 0 "register_operand" "")
19647 (mult:SI (match_operand:SI 1 "register_operand" "")
19648 (match_operand:SI 2 "const_int_operand" "")))
19649 (clobber (reg:CC FLAGS_REG))])]
19650 "INTVAL (operands[2]) == 3
19651 || INTVAL (operands[2]) == 5
19652 || INTVAL (operands[2]) == 9"
19653 [(set (match_dup 0)
19654 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
19656 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19660 [(set (match_operand:SI 0 "register_operand" "")
19661 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19662 (match_operand:SI 2 "const_int_operand" "")))
19663 (clobber (reg:CC FLAGS_REG))])]
19665 && (INTVAL (operands[2]) == 3
19666 || INTVAL (operands[2]) == 5
19667 || INTVAL (operands[2]) == 9)"
19668 [(set (match_dup 0) (match_dup 1))
19670 (plus:SI (mult:SI (match_dup 0) (match_dup 2))
19672 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19676 [(set (match_operand:DI 0 "register_operand" "")
19677 (mult:DI (match_operand:DI 1 "register_operand" "")
19678 (match_operand:DI 2 "const_int_operand" "")))
19679 (clobber (reg:CC FLAGS_REG))])]
19681 && (INTVAL (operands[2]) == 3
19682 || INTVAL (operands[2]) == 5
19683 || INTVAL (operands[2]) == 9)"
19684 [(set (match_dup 0)
19685 (plus:DI (mult:DI (match_dup 1) (match_dup 2))
19687 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19691 [(set (match_operand:DI 0 "register_operand" "")
19692 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19693 (match_operand:DI 2 "const_int_operand" "")))
19694 (clobber (reg:CC FLAGS_REG))])]
19697 && (INTVAL (operands[2]) == 3
19698 || INTVAL (operands[2]) == 5
19699 || INTVAL (operands[2]) == 9)"
19700 [(set (match_dup 0) (match_dup 1))
19702 (plus:DI (mult:DI (match_dup 0) (match_dup 2))
19704 { operands[2] = GEN_INT (INTVAL (operands[2]) - 1); })
19706 ;; Imul $32bit_imm, mem, reg is vector decoded, while
19707 ;; imul $32bit_imm, reg, reg is direct decoded.
19709 [(match_scratch:DI 3 "r")
19710 (parallel [(set (match_operand:DI 0 "register_operand" "")
19711 (mult:DI (match_operand:DI 1 "memory_operand" "")
19712 (match_operand:DI 2 "immediate_operand" "")))
19713 (clobber (reg:CC FLAGS_REG))])]
19714 "TARGET_K8 && !optimize_size
19715 && (GET_CODE (operands[2]) != CONST_INT
19716 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19717 [(set (match_dup 3) (match_dup 1))
19718 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
19719 (clobber (reg:CC FLAGS_REG))])]
19723 [(match_scratch:SI 3 "r")
19724 (parallel [(set (match_operand:SI 0 "register_operand" "")
19725 (mult:SI (match_operand:SI 1 "memory_operand" "")
19726 (match_operand:SI 2 "immediate_operand" "")))
19727 (clobber (reg:CC FLAGS_REG))])]
19728 "TARGET_K8 && !optimize_size
19729 && (GET_CODE (operands[2]) != CONST_INT
19730 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19731 [(set (match_dup 3) (match_dup 1))
19732 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
19733 (clobber (reg:CC FLAGS_REG))])]
19737 [(match_scratch:SI 3 "r")
19738 (parallel [(set (match_operand:DI 0 "register_operand" "")
19740 (mult:SI (match_operand:SI 1 "memory_operand" "")
19741 (match_operand:SI 2 "immediate_operand" ""))))
19742 (clobber (reg:CC FLAGS_REG))])]
19743 "TARGET_K8 && !optimize_size
19744 && (GET_CODE (operands[2]) != CONST_INT
19745 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
19746 [(set (match_dup 3) (match_dup 1))
19747 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
19748 (clobber (reg:CC FLAGS_REG))])]
19751 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
19752 ;; Convert it into imul reg, reg
19753 ;; It would be better to force assembler to encode instruction using long
19754 ;; immediate, but there is apparently no way to do so.
19756 [(parallel [(set (match_operand:DI 0 "register_operand" "")
19757 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
19758 (match_operand:DI 2 "const_int_operand" "")))
19759 (clobber (reg:CC FLAGS_REG))])
19760 (match_scratch:DI 3 "r")]
19761 "TARGET_K8 && !optimize_size
19762 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19763 [(set (match_dup 3) (match_dup 2))
19764 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
19765 (clobber (reg:CC FLAGS_REG))])]
19767 if (!rtx_equal_p (operands[0], operands[1]))
19768 emit_move_insn (operands[0], operands[1]);
19772 [(parallel [(set (match_operand:SI 0 "register_operand" "")
19773 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
19774 (match_operand:SI 2 "const_int_operand" "")))
19775 (clobber (reg:CC FLAGS_REG))])
19776 (match_scratch:SI 3 "r")]
19777 "TARGET_K8 && !optimize_size
19778 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
19779 [(set (match_dup 3) (match_dup 2))
19780 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
19781 (clobber (reg:CC FLAGS_REG))])]
19783 if (!rtx_equal_p (operands[0], operands[1]))
19784 emit_move_insn (operands[0], operands[1]);
19788 [(parallel [(set (match_operand:HI 0 "register_operand" "")
19789 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
19790 (match_operand:HI 2 "immediate_operand" "")))
19791 (clobber (reg:CC FLAGS_REG))])
19792 (match_scratch:HI 3 "r")]
19793 "TARGET_K8 && !optimize_size"
19794 [(set (match_dup 3) (match_dup 2))
19795 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
19796 (clobber (reg:CC FLAGS_REG))])]
19798 if (!rtx_equal_p (operands[0], operands[1]))
19799 emit_move_insn (operands[0], operands[1]);
19802 ;; After splitting up read-modify operations, array accesses with memory
19803 ;; operands might end up in form:
19805 ;; movl 4(%esp), %edx
19807 ;; instead of pre-splitting:
19809 ;; addl 4(%esp), %eax
19811 ;; movl 4(%esp), %edx
19812 ;; leal (%edx,%eax,4), %eax
19815 [(parallel [(set (match_operand 0 "register_operand" "")
19816 (ashift (match_operand 1 "register_operand" "")
19817 (match_operand 2 "const_int_operand" "")))
19818 (clobber (reg:CC FLAGS_REG))])
19819 (set (match_operand 3 "register_operand")
19820 (match_operand 4 "x86_64_general_operand" ""))
19821 (parallel [(set (match_operand 5 "register_operand" "")
19822 (plus (match_operand 6 "register_operand" "")
19823 (match_operand 7 "register_operand" "")))
19824 (clobber (reg:CC FLAGS_REG))])]
19825 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 3
19826 /* Validate MODE for lea. */
19827 && ((!TARGET_PARTIAL_REG_STALL
19828 && (GET_MODE (operands[0]) == QImode
19829 || GET_MODE (operands[0]) == HImode))
19830 || GET_MODE (operands[0]) == SImode
19831 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
19832 /* We reorder load and the shift. */
19833 && !rtx_equal_p (operands[1], operands[3])
19834 && !reg_overlap_mentioned_p (operands[0], operands[4])
19835 /* Last PLUS must consist of operand 0 and 3. */
19836 && !rtx_equal_p (operands[0], operands[3])
19837 && (rtx_equal_p (operands[3], operands[6])
19838 || rtx_equal_p (operands[3], operands[7]))
19839 && (rtx_equal_p (operands[0], operands[6])
19840 || rtx_equal_p (operands[0], operands[7]))
19841 /* The intermediate operand 0 must die or be same as output. */
19842 && (rtx_equal_p (operands[0], operands[5])
19843 || peep2_reg_dead_p (3, operands[0]))"
19844 [(set (match_dup 3) (match_dup 4))
19845 (set (match_dup 0) (match_dup 1))]
19847 enum machine_mode mode = GET_MODE (operands[5]) == DImode ? DImode : SImode;
19848 int scale = 1 << INTVAL (operands[2]);
19849 rtx index = gen_lowpart (Pmode, operands[1]);
19850 rtx base = gen_lowpart (Pmode, operands[3]);
19851 rtx dest = gen_lowpart (mode, operands[5]);
19853 operands[1] = gen_rtx_PLUS (Pmode, base,
19854 gen_rtx_MULT (Pmode, index, GEN_INT (scale)));
19856 operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
19857 operands[0] = dest;
19860 ;; Call-value patterns last so that the wildcard operand does not
19861 ;; disrupt insn-recog's switch tables.
19863 (define_insn "*call_value_pop_0"
19864 [(set (match_operand 0 "" "")
19865 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19866 (match_operand:SI 2 "" "")))
19867 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19868 (match_operand:SI 3 "immediate_operand" "")))]
19871 if (SIBLING_CALL_P (insn))
19874 return "call\t%P1";
19876 [(set_attr "type" "callv")])
19878 (define_insn "*call_value_pop_1"
19879 [(set (match_operand 0 "" "")
19880 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19881 (match_operand:SI 2 "" "")))
19882 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
19883 (match_operand:SI 3 "immediate_operand" "i")))]
19886 if (constant_call_address_operand (operands[1], Pmode))
19888 if (SIBLING_CALL_P (insn))
19891 return "call\t%P1";
19893 if (SIBLING_CALL_P (insn))
19896 return "call\t%A1";
19898 [(set_attr "type" "callv")])
19900 (define_insn "*call_value_0"
19901 [(set (match_operand 0 "" "")
19902 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19903 (match_operand:SI 2 "" "")))]
19906 if (SIBLING_CALL_P (insn))
19909 return "call\t%P1";
19911 [(set_attr "type" "callv")])
19913 (define_insn "*call_value_0_rex64"
19914 [(set (match_operand 0 "" "")
19915 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19916 (match_operand:DI 2 "const_int_operand" "")))]
19919 if (SIBLING_CALL_P (insn))
19922 return "call\t%P1";
19924 [(set_attr "type" "callv")])
19926 (define_insn "*call_value_1"
19927 [(set (match_operand 0 "" "")
19928 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19929 (match_operand:SI 2 "" "")))]
19930 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
19932 if (constant_call_address_operand (operands[1], Pmode))
19933 return "call\t%P1";
19934 return "call\t%A1";
19936 [(set_attr "type" "callv")])
19938 (define_insn "*sibcall_value_1"
19939 [(set (match_operand 0 "" "")
19940 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
19941 (match_operand:SI 2 "" "")))]
19942 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
19944 if (constant_call_address_operand (operands[1], Pmode))
19948 [(set_attr "type" "callv")])
19950 (define_insn "*call_value_1_rex64"
19951 [(set (match_operand 0 "" "")
19952 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
19953 (match_operand:DI 2 "" "")))]
19954 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
19956 if (constant_call_address_operand (operands[1], Pmode))
19957 return "call\t%P1";
19958 return "call\t%A1";
19960 [(set_attr "type" "callv")])
19962 (define_insn "*sibcall_value_1_rex64"
19963 [(set (match_operand 0 "" "")
19964 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19965 (match_operand:DI 2 "" "")))]
19966 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19968 [(set_attr "type" "callv")])
19970 (define_insn "*sibcall_value_1_rex64_v"
19971 [(set (match_operand 0 "" "")
19972 (call (mem:QI (reg:DI 40))
19973 (match_operand:DI 1 "" "")))]
19974 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19976 [(set_attr "type" "callv")])
19978 ;; We used to use "int $5", in honor of #BR which maps to interrupt vector 5.
19979 ;; That, however, is usually mapped by the OS to SIGSEGV, which is often
19980 ;; caught for use by garbage collectors and the like. Using an insn that
19981 ;; maps to SIGILL makes it more likely the program will rightfully die.
19982 ;; Keeping with tradition, "6" is in honor of #UD.
19983 (define_insn "trap"
19984 [(trap_if (const_int 1) (const_int 6))]
19987 [(set_attr "length" "2")])
19989 (define_expand "sse_prologue_save"
19990 [(parallel [(set (match_operand:BLK 0 "" "")
19991 (unspec:BLK [(reg:DI 21)
19998 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
19999 (use (match_operand:DI 1 "register_operand" ""))
20000 (use (match_operand:DI 2 "immediate_operand" ""))
20001 (use (label_ref:DI (match_operand 3 "" "")))])]
20005 (define_insn "*sse_prologue_save_insn"
20006 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
20007 (match_operand:DI 4 "const_int_operand" "n")))
20008 (unspec:BLK [(reg:DI 21)
20015 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
20016 (use (match_operand:DI 1 "register_operand" "r"))
20017 (use (match_operand:DI 2 "const_int_operand" "i"))
20018 (use (label_ref:DI (match_operand 3 "" "X")))]
20020 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
20021 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
20025 operands[0] = gen_rtx_MEM (Pmode,
20026 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
20027 output_asm_insn (\"jmp\\t%A1\", operands);
20028 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
20030 operands[4] = adjust_address (operands[0], DImode, i*16);
20031 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
20032 PUT_MODE (operands[4], TImode);
20033 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
20034 output_asm_insn (\"rex\", operands);
20035 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
20037 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
20038 CODE_LABEL_NUMBER (operands[3]));
20042 [(set_attr "type" "other")
20043 (set_attr "length_immediate" "0")
20044 (set_attr "length_address" "0")
20045 (set_attr "length" "135")
20046 (set_attr "memory" "store")
20047 (set_attr "modrm" "0")
20048 (set_attr "mode" "DI")])
20050 (define_expand "prefetch"
20051 [(prefetch (match_operand 0 "address_operand" "")
20052 (match_operand:SI 1 "const_int_operand" "")
20053 (match_operand:SI 2 "const_int_operand" ""))]
20054 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
20056 int rw = INTVAL (operands[1]);
20057 int locality = INTVAL (operands[2]);
20059 gcc_assert (rw == 0 || rw == 1);
20060 gcc_assert (locality >= 0 && locality <= 3);
20061 gcc_assert (GET_MODE (operands[0]) == Pmode
20062 || GET_MODE (operands[0]) == VOIDmode);
20064 /* Use 3dNOW prefetch in case we are asking for write prefetch not
20065 supported by SSE counterpart or the SSE prefetch is not available
20066 (K6 machines). Otherwise use SSE prefetch as it allows specifying
20068 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
20069 operands[2] = GEN_INT (3);
20071 operands[1] = const0_rtx;
20074 (define_insn "*prefetch_sse"
20075 [(prefetch (match_operand:SI 0 "address_operand" "p")
20077 (match_operand:SI 1 "const_int_operand" ""))]
20078 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
20080 static const char * const patterns[4] = {
20081 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
20084 int locality = INTVAL (operands[1]);
20085 gcc_assert (locality >= 0 && locality <= 3);
20087 return patterns[locality];
20089 [(set_attr "type" "sse")
20090 (set_attr "memory" "none")])
20092 (define_insn "*prefetch_sse_rex"
20093 [(prefetch (match_operand:DI 0 "address_operand" "p")
20095 (match_operand:SI 1 "const_int_operand" ""))]
20096 "TARGET_PREFETCH_SSE && TARGET_64BIT"
20098 static const char * const patterns[4] = {
20099 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
20102 int locality = INTVAL (operands[1]);
20103 gcc_assert (locality >= 0 && locality <= 3);
20105 return patterns[locality];
20107 [(set_attr "type" "sse")
20108 (set_attr "memory" "none")])
20110 (define_insn "*prefetch_3dnow"
20111 [(prefetch (match_operand:SI 0 "address_operand" "p")
20112 (match_operand:SI 1 "const_int_operand" "n")
20114 "TARGET_3DNOW && !TARGET_64BIT"
20116 if (INTVAL (operands[1]) == 0)
20117 return "prefetch\t%a0";
20119 return "prefetchw\t%a0";
20121 [(set_attr "type" "mmx")
20122 (set_attr "memory" "none")])
20124 (define_insn "*prefetch_3dnow_rex"
20125 [(prefetch (match_operand:DI 0 "address_operand" "p")
20126 (match_operand:SI 1 "const_int_operand" "n")
20128 "TARGET_3DNOW && TARGET_64BIT"
20130 if (INTVAL (operands[1]) == 0)
20131 return "prefetch\t%a0";
20133 return "prefetchw\t%a0";
20135 [(set_attr "type" "mmx")
20136 (set_attr "memory" "none")])
20138 (define_expand "stack_protect_set"
20139 [(match_operand 0 "memory_operand" "")
20140 (match_operand 1 "memory_operand" "")]
20143 #ifdef TARGET_THREAD_SSP_OFFSET
20145 emit_insn (gen_stack_tls_protect_set_di (operands[0],
20146 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
20148 emit_insn (gen_stack_tls_protect_set_si (operands[0],
20149 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
20152 emit_insn (gen_stack_protect_set_di (operands[0], operands[1]));
20154 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
20159 (define_insn "stack_protect_set_si"
20160 [(set (match_operand:SI 0 "memory_operand" "=m")
20161 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
20162 (set (match_scratch:SI 2 "=&r") (const_int 0))
20163 (clobber (reg:CC FLAGS_REG))]
20165 "mov{l}\t{%1, %2|%2, %1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
20166 [(set_attr "type" "multi")])
20168 (define_insn "stack_protect_set_di"
20169 [(set (match_operand:DI 0 "memory_operand" "=m")
20170 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
20171 (set (match_scratch:DI 2 "=&r") (const_int 0))
20172 (clobber (reg:CC FLAGS_REG))]
20174 "mov{q}\t{%1, %2|%2, %1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
20175 [(set_attr "type" "multi")])
20177 (define_insn "stack_tls_protect_set_si"
20178 [(set (match_operand:SI 0 "memory_operand" "=m")
20179 (unspec:SI [(match_operand:SI 1 "const_int_operand" "i")] UNSPEC_SP_TLS_SET))
20180 (set (match_scratch:SI 2 "=&r") (const_int 0))
20181 (clobber (reg:CC FLAGS_REG))]
20183 "mov{l}\t{%%gs:%P1, %2|%2, DWORD PTR %%gs:%P1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
20184 [(set_attr "type" "multi")])
20186 (define_insn "stack_tls_protect_set_di"
20187 [(set (match_operand:DI 0 "memory_operand" "=m")
20188 (unspec:DI [(match_operand:DI 1 "const_int_operand" "i")] UNSPEC_SP_TLS_SET))
20189 (set (match_scratch:DI 2 "=&r") (const_int 0))
20190 (clobber (reg:CC FLAGS_REG))]
20192 "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR %%fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
20193 [(set_attr "type" "multi")])
20195 (define_expand "stack_protect_test"
20196 [(match_operand 0 "memory_operand" "")
20197 (match_operand 1 "memory_operand" "")
20198 (match_operand 2 "" "")]
20201 rtx flags = gen_rtx_REG (CCZmode, FLAGS_REG);
20202 ix86_compare_op0 = operands[0];
20203 ix86_compare_op1 = operands[1];
20204 ix86_compare_emitted = flags;
20206 #ifdef TARGET_THREAD_SSP_OFFSET
20208 emit_insn (gen_stack_tls_protect_test_di (flags, operands[0],
20209 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
20211 emit_insn (gen_stack_tls_protect_test_si (flags, operands[0],
20212 GEN_INT (TARGET_THREAD_SSP_OFFSET)));
20215 emit_insn (gen_stack_protect_test_di (flags, operands[0], operands[1]));
20217 emit_insn (gen_stack_protect_test_si (flags, operands[0], operands[1]));
20219 emit_jump_insn (gen_beq (operands[2]));
20223 (define_insn "stack_protect_test_si"
20224 [(set (match_operand:CCZ 0 "flags_reg_operand" "")
20225 (unspec:CCZ [(match_operand:SI 1 "memory_operand" "m")
20226 (match_operand:SI 2 "memory_operand" "m")]
20228 (clobber (match_scratch:SI 3 "=&r"))]
20230 "mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%2, %3|%3, %2}"
20231 [(set_attr "type" "multi")])
20233 (define_insn "stack_protect_test_di"
20234 [(set (match_operand:CCZ 0 "flags_reg_operand" "")
20235 (unspec:CCZ [(match_operand:DI 1 "memory_operand" "m")
20236 (match_operand:DI 2 "memory_operand" "m")]
20238 (clobber (match_scratch:DI 3 "=&r"))]
20240 "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%2, %3|%3, %2}"
20241 [(set_attr "type" "multi")])
20243 (define_insn "stack_tls_protect_test_si"
20244 [(set (match_operand:CCZ 0 "flags_reg_operand" "")
20245 (unspec:CCZ [(match_operand:SI 1 "memory_operand" "m")
20246 (match_operand:SI 2 "const_int_operand" "i")]
20247 UNSPEC_SP_TLS_TEST))
20248 (clobber (match_scratch:SI 3 "=r"))]
20250 "mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%%gs:%P2, %3|%3, DWORD PTR %%gs:%P2}"
20251 [(set_attr "type" "multi")])
20253 (define_insn "stack_tls_protect_test_di"
20254 [(set (match_operand:CCZ 0 "flags_reg_operand" "")
20255 (unspec:CCZ [(match_operand:DI 1 "memory_operand" "m")
20256 (match_operand:DI 2 "const_int_operand" "i")]
20257 UNSPEC_SP_TLS_TEST))
20258 (clobber (match_scratch:DI 3 "=r"))]
20260 "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR %%fs:%P2}"
20261 [(set_attr "type" "multi")])
20265 (include "sync.md")