1 ;; GCC machine description for IA-32.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 ;; Free Software Foundation, Inc.
4 ;; Mostly by William Schelter.
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA. */
23 ;; The original PO technology requires these to be ordered by speed,
24 ;; so that assigner will pick the fastest.
26 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
29 ;; updates for most instructions.
31 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
32 ;; constraint letters.
34 ;; The special asm out single letter directives following a '%' are:
35 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
37 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
38 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
39 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
40 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
41 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
42 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
43 ;; 'J' Print the appropriate jump operand.
45 ;; 'b' Print the QImode name of the register for the indicated operand.
46 ;; %b0 would print %al if operands[0] is reg 0.
47 ;; 'w' Likewise, print the HImode name of the register.
48 ;; 'k' Likewise, print the SImode name of the register.
49 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
50 ;; 'y' Print "st(0)" instead of "st" as a register.
53 ;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode.
54 ;; operand 0 is the memory address to scan.
55 ;; operand 1 is a register containing the value to scan for. The mode
56 ;; of the scas opcode will be the same as the mode of this operand.
57 ;; operand 2 is the known alignment of operand 0.
58 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
59 ;; operand 0 is the argument for `sin'.
60 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
61 ;; operand 0 is the argument for `cos'.
62 ;; 3 This is part of a `stack probe' operation. The mode of the UNSPEC is
63 ;; always SImode. operand 0 is the size of the stack allocation.
64 ;; 4 This is the source of a fake SET of the frame pointer which is used to
65 ;; prevent insns referencing it being scheduled across the initial
66 ;; decrement of the stack pointer.
67 ;; 5 This is a `bsf' operation.
68 ;; 6 This is the @GOT offset of a PIC address.
69 ;; 7 This is the @GOTOFF offset of a PIC address.
70 ;; 8 This is a reference to a symbol's @PLT address.
71 ;; 9 This is an `fnstsw' operation.
72 ;; 10 This is a `sahf' operation.
73 ;; 11 This is a `fstcw' operation
74 ;; 12 This is behaviour of add when setting carry flag.
76 ;; For SSE/MMX support:
77 ;; 30 This is `fix', guaranteed to be truncating.
78 ;; 31 This is a `emms' operation.
79 ;; 32 This is a `maskmov' operation.
80 ;; 33 This is a `movmsk' operation.
81 ;; 34 This is a `non-temporal' move.
82 ;; 35 This is a `prefetch' operation.
83 ;; 36 This is used to distinguish COMISS from UCOMISS.
84 ;; 37 This is a `ldmxcsr' operation.
85 ;; 38 This is a forced `movaps' instruction (rather than whatever movti does)
86 ;; 39 This is a forced `movups' instruction (rather than whatever movti does)
87 ;; 40 This is a `stmxcsr' operation.
88 ;; 41 This is a `shuffle' operation.
89 ;; 42 This is a `rcp' operation.
90 ;; 43 This is a `rsqsrt' operation.
91 ;; 44 This is a `sfence' operation.
92 ;; 45 This is a noop to prevent excessive combiner cleverness.
94 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
98 ;; Processor type. This attribute must exactly match the processor_type
99 ;; enumeration in i386.h.
100 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4"
101 (const (symbol_ref "ix86_cpu")))
103 ;; A basic instruction type. Refinements due to arguments to be
104 ;; provided in other attributes.
106 "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx"
107 (const_string "other"))
109 ;; Main data type used by the insn
110 (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI"
111 (const_string "unknown"))
113 ;; Set for i387 operations.
114 (define_attr "i387" ""
115 (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch")
119 ;; The (bounding maximum) length of an instruction immediate.
120 (define_attr "length_immediate" ""
121 (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx")
125 (eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
126 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
127 (eq_attr "type" "imov,test")
128 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
129 (eq_attr "type" "call")
130 (if_then_else (match_operand 0 "constant_call_address_operand" "")
133 (eq_attr "type" "callv")
134 (if_then_else (match_operand 1 "constant_call_address_operand" "")
137 (eq_attr "type" "ibr")
138 (if_then_else (and (ge (minus (match_dup 0) (pc))
140 (lt (minus (match_dup 0) (pc))
145 (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1")))
147 ;; The (bounding maximum) length of an instruction address.
148 (define_attr "length_address" ""
149 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
151 (and (eq_attr "type" "call")
152 (match_operand 1 "constant_call_address_operand" ""))
154 (and (eq_attr "type" "callv")
155 (match_operand 1 "constant_call_address_operand" ""))
158 (symbol_ref "ix86_attr_length_address_default (insn)")))
160 ;; Set when length prefix is used.
161 (define_attr "prefix_data16" ""
162 (if_then_else (eq_attr "mode" "HI")
166 ;; Set when string REP prefix is used.
167 (define_attr "prefix_rep" "" (const_int 0))
169 ;; Set when 0f opcode prefix is used.
170 (define_attr "prefix_0f" ""
171 (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx")
175 ;; Set when modrm byte is used.
176 (define_attr "modrm" ""
177 (cond [(eq_attr "type" "str,cld")
181 (and (eq_attr "type" "incdec")
182 (ior (match_operand:SI 1 "register_operand" "")
183 (match_operand:HI 1 "register_operand" "")))
185 (and (eq_attr "type" "push")
186 (not (match_operand 1 "memory_operand" "")))
188 (and (eq_attr "type" "pop")
189 (not (match_operand 0 "memory_operand" "")))
191 (and (eq_attr "type" "imov")
192 (and (match_operand 0 "register_operand" "")
193 (match_operand 1 "immediate_operand" "")))
198 ;; The (bounding maximum) length of an instruction in bytes.
199 (define_attr "length" ""
200 (cond [(eq_attr "type" "other,multi")
203 (plus (plus (attr "modrm")
204 (plus (attr "prefix_0f")
207 (plus (attr "prefix_rep")
208 (plus (attr "prefix_data16")
209 (plus (attr "length_immediate")
210 (attr "length_address")))))))
212 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
213 ;; `store' if there is a simple memory reference therein, or `unknown'
214 ;; if the instruction is complex.
216 (define_attr "memory" "none,load,store,both,unknown"
217 (cond [(eq_attr "type" "other,multi,str")
218 (const_string "unknown")
219 (eq_attr "type" "lea,fcmov,fpspc,cld")
220 (const_string "none")
221 (eq_attr "type" "push")
222 (if_then_else (match_operand 1 "memory_operand" "")
223 (const_string "both")
224 (const_string "store"))
225 (eq_attr "type" "pop,setcc")
226 (if_then_else (match_operand 0 "memory_operand" "")
227 (const_string "both")
228 (const_string "load"))
229 (eq_attr "type" "icmp,test")
230 (if_then_else (ior (match_operand 0 "memory_operand" "")
231 (match_operand 1 "memory_operand" ""))
232 (const_string "load")
233 (const_string "none"))
234 (eq_attr "type" "ibr")
235 (if_then_else (match_operand 0 "memory_operand" "")
236 (const_string "load")
237 (const_string "none"))
238 (eq_attr "type" "call")
239 (if_then_else (match_operand 0 "constant_call_address_operand" "")
240 (const_string "none")
241 (const_string "load"))
242 (eq_attr "type" "callv")
243 (if_then_else (match_operand 1 "constant_call_address_operand" "")
244 (const_string "none")
245 (const_string "load"))
246 (and (eq_attr "type" "alu1,negnot")
247 (match_operand 1 "memory_operand" ""))
248 (const_string "both")
249 (and (match_operand 0 "memory_operand" "")
250 (match_operand 1 "memory_operand" ""))
251 (const_string "both")
252 (match_operand 0 "memory_operand" "")
253 (const_string "store")
254 (match_operand 1 "memory_operand" "")
255 (const_string "load")
256 (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx")
257 (match_operand 2 "memory_operand" ""))
258 (const_string "load")
259 (and (eq_attr "type" "icmov")
260 (match_operand 3 "memory_operand" ""))
261 (const_string "load")
263 (const_string "none")))
265 ;; Indicates if an instruction has both an immediate and a displacement.
267 (define_attr "imm_disp" "false,true,unknown"
268 (cond [(eq_attr "type" "other,multi")
269 (const_string "unknown")
270 (and (eq_attr "type" "icmp,test,imov")
271 (and (match_operand 0 "memory_displacement_operand" "")
272 (match_operand 1 "immediate_operand" "")))
273 (const_string "true")
274 (and (eq_attr "type" "alu,ishift,imul,idiv")
275 (and (match_operand 0 "memory_displacement_operand" "")
276 (match_operand 2 "immediate_operand" "")))
277 (const_string "true")
279 (const_string "false")))
281 ;; Indicates if an FP operation has an integer source.
283 (define_attr "fp_int_src" "false,true"
284 (const_string "false"))
286 ;; Describe a user's asm statement.
287 (define_asm_attributes
288 [(set_attr "length" "128")
289 (set_attr "type" "multi")])
291 ;; Pentium Scheduling
293 ;; The Pentium is an in-order core with two integer pipelines.
295 ;; True for insns that behave like prefixed insns on the Pentium.
296 (define_attr "pent_prefix" "false,true"
297 (if_then_else (ior (eq_attr "prefix_0f" "1")
298 (ior (eq_attr "prefix_data16" "1")
299 (eq_attr "prefix_rep" "1")))
300 (const_string "true")
301 (const_string "false")))
303 ;; Categorize how an instruction slots.
305 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
306 ;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium
307 ;; rules, because it results in noticeably better code on non-MMX Pentium
308 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
309 ;; common, so the scheduler usualy has a non-prefixed insn to pair).
311 (define_attr "pent_pair" "uv,pu,pv,np"
312 (cond [(eq_attr "imm_disp" "true")
314 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
315 (and (eq_attr "type" "pop,push")
316 (eq_attr "memory" "!both")))
317 (if_then_else (eq_attr "pent_prefix" "true")
320 (eq_attr "type" "ibr")
322 (and (eq_attr "type" "ishift")
323 (match_operand 2 "const_int_operand" ""))
325 (and (eq_attr "type" "call")
326 (match_operand 0 "constant_call_address_operand" ""))
328 (and (eq_attr "type" "callv")
329 (match_operand 1 "constant_call_address_operand" ""))
332 (const_string "np")))
334 ;; Rough readiness numbers. Fine tuning happens in i386.c.
336 ;; u describes pipe U
337 ;; v describes pipe V
338 ;; uv describes either pipe U or V for those that can issue to either
339 ;; np describes not paring
341 ;; fpm describes fp insns of different types are not pipelined.
343 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
345 (define_function_unit "pent_np" 1 0
346 (and (eq_attr "cpu" "pentium")
347 (eq_attr "type" "imul"))
350 (define_function_unit "pent_mul" 1 1
351 (and (eq_attr "cpu" "pentium")
352 (eq_attr "type" "imul"))
355 ;; Rep movs takes minimally 12 cycles.
356 (define_function_unit "pent_np" 1 0
357 (and (eq_attr "cpu" "pentium")
358 (eq_attr "type" "str"))
361 ; ??? IDIV for SI takes 46 cycles, for HI 30, for QI 22
362 (define_function_unit "pent_np" 1 0
363 (and (eq_attr "cpu" "pentium")
364 (eq_attr "type" "idiv"))
367 ; Fp reg-reg moves takes 1 cycle. Loads takes 1 cycle for SF/DF mode,
368 ; 3 cycles for XFmode. Stores takes 2 cycles for SF/DF and 3 for XF.
369 ; fldz and fld1 takes 2 cycles. Only reg-reg moves are pairable.
370 ; The integer <-> fp conversion is not modeled correctly. Fild behaves
371 ; like normal fp operation and fist takes 6 cycles.
373 (define_function_unit "fpu" 1 0
374 (and (eq_attr "cpu" "pentium")
375 (and (eq_attr "type" "fmov")
376 (and (eq_attr "memory" "load,store")
377 (eq_attr "mode" "XF"))))
380 (define_function_unit "pent_np" 1 0
381 (and (eq_attr "cpu" "pentium")
382 (and (eq_attr "type" "fmov")
383 (and (eq_attr "memory" "load,store")
384 (eq_attr "mode" "XF"))))
387 (define_function_unit "fpu" 1 0
388 (and (eq_attr "cpu" "pentium")
389 (and (eq_attr "type" "fmov")
390 (ior (match_operand 1 "immediate_operand" "")
391 (eq_attr "memory" "store"))))
394 (define_function_unit "pent_np" 1 0
395 (and (eq_attr "cpu" "pentium")
396 (and (eq_attr "type" "fmov")
397 (ior (match_operand 1 "immediate_operand" "")
398 (eq_attr "memory" "store"))))
401 (define_function_unit "pent_np" 1 0
402 (and (eq_attr "cpu" "pentium")
403 (eq_attr "type" "cld"))
406 (define_function_unit "fpu" 1 0
407 (and (eq_attr "cpu" "pentium")
408 (and (eq_attr "type" "fmov")
409 (eq_attr "memory" "none,load")))
412 ; Read/Modify/Write instructions usually take 3 cycles.
413 (define_function_unit "pent_u" 1 0
414 (and (eq_attr "cpu" "pentium")
415 (and (eq_attr "type" "alu,alu1,ishift")
416 (and (eq_attr "pent_pair" "pu")
417 (eq_attr "memory" "both"))))
420 (define_function_unit "pent_uv" 2 0
421 (and (eq_attr "cpu" "pentium")
422 (and (eq_attr "type" "alu,alu1,ishift")
423 (and (eq_attr "pent_pair" "!np")
424 (eq_attr "memory" "both"))))
427 (define_function_unit "pent_np" 1 0
428 (and (eq_attr "cpu" "pentium")
429 (and (eq_attr "type" "alu,alu1,negnot,ishift")
430 (and (eq_attr "pent_pair" "np")
431 (eq_attr "memory" "both"))))
434 ; Read/Modify or Modify/Write instructions usually take 2 cycles.
435 (define_function_unit "pent_u" 1 0
436 (and (eq_attr "cpu" "pentium")
437 (and (eq_attr "type" "alu,ishift")
438 (and (eq_attr "pent_pair" "pu")
439 (eq_attr "memory" "load,store"))))
442 (define_function_unit "pent_uv" 2 0
443 (and (eq_attr "cpu" "pentium")
444 (and (eq_attr "type" "alu,ishift")
445 (and (eq_attr "pent_pair" "!np")
446 (eq_attr "memory" "load,store"))))
449 (define_function_unit "pent_np" 1 0
450 (and (eq_attr "cpu" "pentium")
451 (and (eq_attr "type" "alu,ishift")
452 (and (eq_attr "pent_pair" "np")
453 (eq_attr "memory" "load,store"))))
456 ; Insns w/o memory operands and move instructions usually take one cycle.
457 (define_function_unit "pent_u" 1 0
458 (and (eq_attr "cpu" "pentium")
459 (eq_attr "pent_pair" "pu"))
462 (define_function_unit "pent_v" 1 0
463 (and (eq_attr "cpu" "pentium")
464 (eq_attr "pent_pair" "pv"))
467 (define_function_unit "pent_uv" 2 0
468 (and (eq_attr "cpu" "pentium")
469 (eq_attr "pent_pair" "!np"))
472 (define_function_unit "pent_np" 1 0
473 (and (eq_attr "cpu" "pentium")
474 (eq_attr "pent_pair" "np"))
477 ; Pairable insns only conflict with other non-pairable insns.
478 (define_function_unit "pent_np" 1 0
479 (and (eq_attr "cpu" "pentium")
480 (and (eq_attr "type" "alu,alu1,ishift")
481 (and (eq_attr "pent_pair" "!np")
482 (eq_attr "memory" "both"))))
484 [(eq_attr "pent_pair" "np")])
486 (define_function_unit "pent_np" 1 0
487 (and (eq_attr "cpu" "pentium")
488 (and (eq_attr "type" "alu,alu1,ishift")
489 (and (eq_attr "pent_pair" "!np")
490 (eq_attr "memory" "load,store"))))
492 [(eq_attr "pent_pair" "np")])
494 (define_function_unit "pent_np" 1 0
495 (and (eq_attr "cpu" "pentium")
496 (eq_attr "pent_pair" "!np"))
498 [(eq_attr "pent_pair" "np")])
500 ; Floating point instructions usually blocks cycle longer when combined with
501 ; integer instructions, because of the inpaired fxch instruction.
502 (define_function_unit "pent_np" 1 0
503 (and (eq_attr "cpu" "pentium")
504 (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp"))
506 [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp")])
508 (define_function_unit "fpu" 1 0
509 (and (eq_attr "cpu" "pentium")
510 (eq_attr "type" "fcmp,fxch,fsgn"))
513 ; Addition takes 3 cycles; assume other random cruft does as well.
514 ; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
515 (define_function_unit "fpu" 1 0
516 (and (eq_attr "cpu" "pentium")
517 (eq_attr "type" "fop,fop1"))
520 ; Multiplication takes 3 cycles and is only half pipelined.
521 (define_function_unit "fpu" 1 0
522 (and (eq_attr "cpu" "pentium")
523 (eq_attr "type" "fmul"))
526 (define_function_unit "pent_mul" 1 1
527 (and (eq_attr "cpu" "pentium")
528 (eq_attr "type" "fmul"))
531 ; ??? This is correct only for fdiv and sqrt -- sin/cos take 65-100 cycles.
532 ; They can overlap with integer insns. Only the last two cycles can overlap
533 ; with other fp insns. Only fsin/fcos can overlap with multiplies.
534 ; Only last two cycles of fsin/fcos can overlap with other instructions.
535 (define_function_unit "fpu" 1 0
536 (and (eq_attr "cpu" "pentium")
537 (eq_attr "type" "fdiv"))
540 (define_function_unit "pent_mul" 1 1
541 (and (eq_attr "cpu" "pentium")
542 (eq_attr "type" "fdiv"))
545 (define_function_unit "fpu" 1 0
546 (and (eq_attr "cpu" "pentium")
547 (eq_attr "type" "fpspc"))
550 (define_function_unit "pent_mul" 1 1
551 (and (eq_attr "cpu" "pentium")
552 (eq_attr "type" "fpspc"))
555 ;; Pentium Pro/PII Scheduling
557 ;; The PPro has an out-of-order core, but the instruction decoders are
558 ;; naturally in-order and asymmetric. We get best performance by scheduling
559 ;; for the decoders, for in doing so we give the oo execution unit the
562 ;; Categorize how many uops an ia32 instruction evaluates to:
563 ;; one -- an instruction with 1 uop can be decoded by any of the
565 ;; few -- an instruction with 1 to 4 uops can be decoded only by
567 ;; many -- a complex instruction may take an unspecified number of
568 ;; cycles to decode in decoder 0.
570 (define_attr "ppro_uops" "one,few,many"
571 (cond [(eq_attr "type" "other,multi,call,callv,fpspc,str")
572 (const_string "many")
573 (eq_attr "type" "icmov,fcmov,str,cld")
575 (eq_attr "type" "imov")
576 (if_then_else (eq_attr "memory" "store,both")
578 (const_string "one"))
579 (eq_attr "memory" "!none")
582 (const_string "one")))
584 ;; Rough readiness numbers. Fine tuning happens in i386.c.
586 ;; p0 describes port 0.
587 ;; p01 describes ports 0 and 1 as a pair; alu insns can issue to either.
588 ;; p2 describes port 2 for loads.
589 ;; p34 describes ports 3 and 4 for stores.
590 ;; fpu describes the fpu accessed via port 0.
591 ;; ??? It is less than clear if there are separate fadd and fmul units
592 ;; that could operate in parallel.
594 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
596 (define_function_unit "ppro_p0" 1 0
597 (and (eq_attr "cpu" "pentiumpro")
598 (eq_attr "type" "ishift,lea,ibr,cld"))
601 (define_function_unit "ppro_p0" 1 0
602 (and (eq_attr "cpu" "pentiumpro")
603 (eq_attr "type" "imul"))
606 ;; ??? Does the divider lock out the pipe while it works,
607 ;; or is there a disconnected unit?
608 (define_function_unit "ppro_p0" 1 0
609 (and (eq_attr "cpu" "pentiumpro")
610 (eq_attr "type" "idiv"))
613 (define_function_unit "ppro_p0" 1 0
614 (and (eq_attr "cpu" "pentiumpro")
615 (eq_attr "type" "fop,fop1,fsgn"))
618 (define_function_unit "ppro_p0" 1 0
619 (and (eq_attr "cpu" "pentiumpro")
620 (eq_attr "type" "fcmov"))
623 (define_function_unit "ppro_p0" 1 0
624 (and (eq_attr "cpu" "pentiumpro")
625 (eq_attr "type" "fcmp"))
628 (define_function_unit "ppro_p0" 1 0
629 (and (eq_attr "cpu" "pentiumpro")
630 (eq_attr "type" "fmov"))
633 (define_function_unit "ppro_p0" 1 0
634 (and (eq_attr "cpu" "pentiumpro")
635 (eq_attr "type" "fmul"))
638 (define_function_unit "ppro_p0" 1 0
639 (and (eq_attr "cpu" "pentiumpro")
640 (eq_attr "type" "fdiv,fpspc"))
643 (define_function_unit "ppro_p01" 2 0
644 (and (eq_attr "cpu" "pentiumpro")
645 (eq_attr "type" "!imov,fmov"))
648 (define_function_unit "ppro_p01" 2 0
649 (and (and (eq_attr "cpu" "pentiumpro")
650 (eq_attr "type" "imov,fmov"))
651 (eq_attr "memory" "none"))
654 (define_function_unit "ppro_p2" 1 0
655 (and (eq_attr "cpu" "pentiumpro")
656 (ior (eq_attr "type" "pop")
657 (eq_attr "memory" "load,both")))
660 (define_function_unit "ppro_p34" 1 0
661 (and (eq_attr "cpu" "pentiumpro")
662 (ior (eq_attr "type" "push")
663 (eq_attr "memory" "store,both")))
666 (define_function_unit "fpu" 1 0
667 (and (eq_attr "cpu" "pentiumpro")
668 (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov"))
671 (define_function_unit "fpu" 1 0
672 (and (eq_attr "cpu" "pentiumpro")
673 (eq_attr "type" "fmul"))
676 (define_function_unit "fpu" 1 0
677 (and (eq_attr "cpu" "pentiumpro")
678 (eq_attr "type" "fdiv,fpspc"))
681 ;; imul uses the fpu. ??? does it have the same throughput as fmul?
682 (define_function_unit "fpu" 1 0
683 (and (eq_attr "cpu" "pentiumpro")
684 (eq_attr "type" "imul"))
687 ;; AMD K6/K6-2 Scheduling
689 ;; The K6 has similar architecture to PPro. Important difference is, that
690 ;; there are only two decoders and they seems to be much slower than execution
691 ;; units. So we have to pay much more attention to proper decoding for
692 ;; schedulers. We share most of scheduler code for PPro in i386.c
694 ;; The fp unit is not pipelined and do one operation per two cycles including
697 ;; alu describes both ALU units (ALU-X and ALU-Y).
698 ;; alux describes X alu unit
699 ;; fpu describes FPU unit
700 ;; load describes load unit.
701 ;; branch describes branch unit.
702 ;; store decsribes store unit. This unit is not modelled completely and only
703 ;; used to model lea operation. Otherwise it lie outside of the critical
706 ;; ??? fxch isn't handled; not an issue until sched3 after reg-stack is real.
708 ;; The decoder specification is in the PPro section above!
710 ;; Shift instructions and certain arithmetic are issued only to X pipe.
711 (define_function_unit "k6_alux" 1 0
712 (and (eq_attr "cpu" "k6")
713 (eq_attr "type" "ishift,alu1,negnot,cld"))
716 ;; The QI mode arithmetic is issued to X pipe only.
717 (define_function_unit "k6_alux" 1 0
718 (and (eq_attr "cpu" "k6")
719 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
720 (match_operand:QI 0 "general_operand" "")))
723 (define_function_unit "k6_alu" 2 0
724 (and (eq_attr "cpu" "k6")
725 (eq_attr "type" "ishift,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
728 (define_function_unit "k6_alu" 2 0
729 (and (eq_attr "cpu" "k6")
730 (and (eq_attr "type" "imov")
731 (eq_attr "memory" "none")))
734 (define_function_unit "k6_branch" 1 0
735 (and (eq_attr "cpu" "k6")
736 (eq_attr "type" "call,callv,ibr"))
739 ;; Load unit have two cycle latency, but we take care for it in adjust_cost
740 (define_function_unit "k6_load" 1 0
741 (and (eq_attr "cpu" "k6")
742 (ior (eq_attr "type" "pop")
743 (eq_attr "memory" "load,both")))
746 (define_function_unit "k6_load" 1 0
747 (and (eq_attr "cpu" "k6")
748 (and (eq_attr "type" "str")
749 (eq_attr "memory" "load,both")))
752 ;; Lea have two instructions, so latency is probably 2
753 (define_function_unit "k6_store" 1 0
754 (and (eq_attr "cpu" "k6")
755 (eq_attr "type" "lea"))
758 (define_function_unit "k6_store" 1 0
759 (and (eq_attr "cpu" "k6")
760 (eq_attr "type" "str"))
763 (define_function_unit "k6_store" 1 0
764 (and (eq_attr "cpu" "k6")
765 (ior (eq_attr "type" "push")
766 (eq_attr "memory" "store,both")))
769 (define_function_unit "k6_fpu" 1 1
770 (and (eq_attr "cpu" "k6")
771 (eq_attr "type" "fop,fop1,fmov,fcmp"))
774 (define_function_unit "k6_fpu" 1 1
775 (and (eq_attr "cpu" "k6")
776 (eq_attr "type" "fmul"))
780 (define_function_unit "k6_fpu" 1 1
781 (and (eq_attr "cpu" "k6")
782 (eq_attr "type" "fdiv,fpspc"))
785 (define_function_unit "k6_alu" 2 0
786 (and (eq_attr "cpu" "k6")
787 (eq_attr "type" "imul"))
790 (define_function_unit "k6_alux" 1 0
791 (and (eq_attr "cpu" "k6")
792 (eq_attr "type" "imul"))
796 (define_function_unit "k6_alu" 2 0
797 (and (eq_attr "cpu" "k6")
798 (eq_attr "type" "idiv"))
801 (define_function_unit "k6_alux" 1 0
802 (and (eq_attr "cpu" "k6")
803 (eq_attr "type" "idiv"))
806 ;; AMD Athlon Scheduling
808 ;; The Athlon does contain three pipelined FP units, three integer units and
809 ;; three address generation units.
811 ;; The predecode logic is determining boundaries of instructions in the 64
812 ;; byte cache line. So the cache line straddling problem of K6 might be issue
813 ;; here as well, but it is not noted in the documentation.
815 ;; Three DirectPath instructions decoders and only one VectorPath decoder
816 ;; is available. They can decode three DirectPath instructions or one VectorPath
817 ;; instruction per cycle.
818 ;; Decoded macro instructions are then passed to 72 entry instruction control
820 ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
822 ;; The load/store queue unit is not attached to the schedulers but
823 ;; communicates with all the execution units seperately instead.
825 (define_attr "athlon_decode" "direct,vector"
826 (cond [(eq_attr "type" "call,imul,idiv,other,multi,fcmov,fpspc,str,pop,cld,fcmov")
827 (const_string "vector")
828 (and (eq_attr "type" "push")
829 (match_operand 1 "memory_operand" ""))
830 (const_string "vector")
831 (and (eq_attr "type" "fmov")
832 (and (eq_attr "memory" "load,store")
833 (eq_attr "mode" "XF")))
834 (const_string "vector")]
835 (const_string "direct")))
837 (define_function_unit "athlon_vectordec" 1 0
838 (and (eq_attr "cpu" "athlon")
839 (eq_attr "athlon_decode" "vector"))
842 (define_function_unit "athlon_directdec" 3 0
843 (and (eq_attr "cpu" "athlon")
844 (eq_attr "athlon_decode" "direct"))
847 (define_function_unit "athlon_vectordec" 1 0
848 (and (eq_attr "cpu" "athlon")
849 (eq_attr "athlon_decode" "direct"))
850 1 1 [(eq_attr "athlon_decode" "vector")])
852 (define_function_unit "athlon_ieu" 3 0
853 (and (eq_attr "cpu" "athlon")
854 (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
857 (define_function_unit "athlon_ieu" 3 0
858 (and (eq_attr "cpu" "athlon")
859 (eq_attr "type" "str"))
862 (define_function_unit "athlon_ieu" 3 0
863 (and (eq_attr "cpu" "athlon")
864 (eq_attr "type" "imul"))
867 (define_function_unit "athlon_ieu" 3 0
868 (and (eq_attr "cpu" "athlon")
869 (eq_attr "type" "idiv"))
872 (define_function_unit "athlon_muldiv" 1 0
873 (and (eq_attr "cpu" "athlon")
874 (eq_attr "type" "imul"))
877 (define_function_unit "athlon_muldiv" 1 0
878 (and (eq_attr "cpu" "athlon")
879 (eq_attr "type" "idiv"))
882 (define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
883 (cond [(eq_attr "type" "fop,fop1,fcmp")
885 (eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
887 (and (eq_attr "type" "fmov") (eq_attr "memory" "store,both"))
888 (const_string "store")
889 (and (eq_attr "type" "fmov") (eq_attr "memory" "load"))
891 (and (eq_attr "type" "fmov")
892 (ior (match_operand:SI 1 "register_operand" "")
893 (match_operand 1 "immediate_operand" "")))
894 (const_string "store")
895 (eq_attr "type" "fmov")
896 (const_string "muladd")]
897 (const_string "none")))
899 ;; We use latencies 1 for definitions. This is OK to model colisions
900 ;; in execution units. The real latencies are modeled in the "fp" pipeline.
902 ;; fsin, fcos: 96-192
904 ;; fsqrt: 19 for SFmode, 27 for DFmode, 35 for XFmode.
905 (define_function_unit "athlon_fp" 3 0
906 (and (eq_attr "cpu" "athlon")
907 (eq_attr "type" "fpspc"))
910 ;; 16 cycles for SFmode, 20 for DFmode and 24 for XFmode.
911 (define_function_unit "athlon_fp" 3 0
912 (and (eq_attr "cpu" "athlon")
913 (eq_attr "type" "fdiv"))
916 (define_function_unit "athlon_fp" 3 0
917 (and (eq_attr "cpu" "athlon")
918 (eq_attr "type" "fop,fop1,fmul"))
921 ;; XFmode loads are slow.
922 ;; XFmode store is slow too (8 cycles), but we don't need to model it, because
923 ;; there are no dependent instructions.
925 (define_function_unit "athlon_fp" 3 0
926 (and (eq_attr "cpu" "athlon")
927 (and (eq_attr "type" "fmov")
928 (and (eq_attr "memory" "load")
929 (eq_attr "mode" "XF"))))
932 (define_function_unit "athlon_fp" 3 0
933 (and (eq_attr "cpu" "athlon")
934 (eq_attr "type" "fmov,fsgn"))
937 ;; fcmp and ftst instructions
938 (define_function_unit "athlon_fp" 3 0
939 (and (eq_attr "cpu" "athlon")
940 (and (eq_attr "type" "fcmp")
941 (eq_attr "athlon_decode" "direct")))
944 ;; fcmpi instructions.
945 (define_function_unit "athlon_fp" 3 0
946 (and (eq_attr "cpu" "athlon")
947 (and (eq_attr "type" "fcmp")
948 (eq_attr "athlon_decode" "vector")))
951 (define_function_unit "athlon_fp" 3 0
952 (and (eq_attr "cpu" "athlon")
953 (eq_attr "type" "fcmov"))
956 (define_function_unit "athlon_fp_mul" 1 0
957 (and (eq_attr "cpu" "athlon")
958 (eq_attr "athlon_fpunits" "mul"))
961 (define_function_unit "athlon_fp_add" 1 0
962 (and (eq_attr "cpu" "athlon")
963 (eq_attr "athlon_fpunits" "add"))
966 (define_function_unit "athlon_fp_muladd" 2 0
967 (and (eq_attr "cpu" "athlon")
968 (eq_attr "athlon_fpunits" "muladd,mul,add"))
971 (define_function_unit "athlon_fp_store" 1 0
972 (and (eq_attr "cpu" "athlon")
973 (eq_attr "athlon_fpunits" "store"))
976 ;; We don't need to model the Adress Generation Unit, since we don't model
977 ;; the re-order buffer yet and thus we never schedule more than three operations
978 ;; at time. Later we may want to experiment with MD_SCHED macros modeling the
979 ;; decoders independently on the functional units.
981 ;(define_function_unit "athlon_agu" 3 0
982 ; (and (eq_attr "cpu" "athlon")
983 ; (and (eq_attr "memory" "!none")
984 ; (eq_attr "athlon_fpunits" "none")))
987 ;; Model load unit to avoid too long sequences of loads. We don't need to
988 ;; model store queue, since it is hardly going to be bottleneck.
990 (define_function_unit "athlon_load" 2 0
991 (and (eq_attr "cpu" "athlon")
992 (eq_attr "memory" "load,both"))
996 ;; Compare instructions.
998 ;; All compare insns have expanders that save the operands away without
999 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
1000 ;; after the cmp) will actually emit the cmpM.
1002 (define_expand "cmpdi"
1004 (compare:CC (match_operand:DI 0 "general_operand" "")
1005 (match_operand:DI 1 "general_operand" "")))]
1009 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1010 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1011 operands[0] = force_reg (DImode, operands[0]);
1012 ix86_compare_op0 = operands[0];
1013 ix86_compare_op1 = operands[1];
1017 (define_expand "cmpsi"
1019 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
1020 (match_operand:SI 1 "general_operand" "")))]
1024 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1025 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1026 operands[0] = force_reg (SImode, operands[0]);
1027 ix86_compare_op0 = operands[0];
1028 ix86_compare_op1 = operands[1];
1032 (define_expand "cmphi"
1034 (compare:CC (match_operand:HI 0 "general_operand" "")
1035 (match_operand:HI 1 "general_operand" "")))]
1039 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1040 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1041 operands[0] = force_reg (HImode, operands[0]);
1042 ix86_compare_op0 = operands[0];
1043 ix86_compare_op1 = operands[1];
1047 (define_expand "cmpqi"
1049 (compare:CC (match_operand:QI 0 "general_operand" "")
1050 (match_operand:QI 1 "general_operand" "")))]
1051 "TARGET_QIMODE_MATH"
1054 if ((GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1055 || (CONSTANT_P (operands[0]) && CONSTANT_P (operands[1])))
1056 operands[0] = force_reg (QImode, operands[0]);
1057 ix86_compare_op0 = operands[0];
1058 ix86_compare_op1 = operands[1];
1062 (define_insn "*cmpsi_ccno_1"
1064 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
1065 (match_operand:SI 1 "const0_operand" "n,n")))]
1066 "ix86_match_ccmode (insn, CCNOmode)"
1068 test{l}\\t{%0, %0|%0, %0}
1069 cmp{l}\\t{%1, %0|%0, %1}"
1070 [(set_attr "type" "test,icmp")
1071 (set_attr "length_immediate" "0,1")
1072 (set_attr "mode" "SI")])
1074 (define_insn "*cmpsi_minus_1"
1076 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1077 (match_operand:SI 1 "general_operand" "ri,mr"))
1079 "ix86_match_ccmode (insn, CCGOCmode)"
1080 "cmp{l}\\t{%1, %0|%0, %1}"
1081 [(set_attr "type" "icmp")
1082 (set_attr "mode" "SI")])
1084 (define_expand "cmpsi_1"
1086 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1087 (match_operand:SI 1 "general_operand" "ri,mr")))]
1091 (define_insn "*cmpsi_1_insn"
1093 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
1094 (match_operand:SI 1 "general_operand" "ri,mr")))]
1095 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1096 && ix86_match_ccmode (insn, CCmode)"
1097 "cmp{l}\\t{%1, %0|%0, %1}"
1098 [(set_attr "type" "icmp")
1099 (set_attr "mode" "SI")])
1101 (define_insn "*cmphi_ccno_1"
1103 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
1104 (match_operand:HI 1 "const0_operand" "n,n")))]
1105 "ix86_match_ccmode (insn, CCNOmode)"
1107 test{w}\\t{%0, %0|%0, %0}
1108 cmp{w}\\t{%1, %0|%0, %1}"
1109 [(set_attr "type" "test,icmp")
1110 (set_attr "length_immediate" "0,1")
1111 (set_attr "mode" "HI")])
1113 (define_insn "*cmphi_minus_1"
1115 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1116 (match_operand:HI 1 "general_operand" "ri,mr"))
1118 "ix86_match_ccmode (insn, CCGOCmode)"
1119 "cmp{w}\\t{%1, %0|%0, %1}"
1120 [(set_attr "type" "icmp")
1121 (set_attr "mode" "HI")])
1123 (define_insn "*cmphi_1"
1125 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
1126 (match_operand:HI 1 "general_operand" "ri,mr")))]
1127 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1128 && ix86_match_ccmode (insn, CCmode)"
1129 "cmp{w}\\t{%1, %0|%0, %1}"
1130 [(set_attr "type" "icmp")
1131 (set_attr "mode" "HI")])
1133 (define_insn "*cmpqi_ccno_1"
1135 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
1136 (match_operand:QI 1 "const0_operand" "n,n")))]
1137 "ix86_match_ccmode (insn, CCNOmode)"
1139 test{b}\\t{%0, %0|%0, %0}
1140 cmp{b}\\t{$0, %0|%0, 0}"
1141 [(set_attr "type" "test,icmp")
1142 (set_attr "length_immediate" "0,1")
1143 (set_attr "mode" "QI")])
1145 (define_insn "*cmpqi_1"
1147 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1148 (match_operand:QI 1 "general_operand" "qi,mq")))]
1149 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
1150 && ix86_match_ccmode (insn, CCmode)"
1151 "cmp{b}\\t{%1, %0|%0, %1}"
1152 [(set_attr "type" "icmp")
1153 (set_attr "mode" "QI")])
1155 (define_insn "*cmpqi_minus_1"
1157 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
1158 (match_operand:QI 1 "general_operand" "qi,mq"))
1160 "ix86_match_ccmode (insn, CCGOCmode)"
1161 "cmp{b}\\t{%1, %0|%0, %1}"
1162 [(set_attr "type" "icmp")
1163 (set_attr "mode" "QI")])
1165 (define_insn "*cmpqi_ext_1"
1168 (match_operand:QI 0 "general_operand" "qm")
1171 (match_operand 1 "ext_register_operand" "q")
1173 (const_int 8)) 0)))]
1174 "ix86_match_ccmode (insn, CCmode)"
1175 "cmp{b}\\t{%h1, %0|%0, %h1}"
1176 [(set_attr "type" "icmp")
1177 (set_attr "mode" "QI")])
1179 (define_insn "*cmpqi_ext_2"
1184 (match_operand 0 "ext_register_operand" "q")
1187 (match_operand:QI 1 "const0_operand" "n")))]
1188 "ix86_match_ccmode (insn, CCNOmode)"
1189 "test{b}\\t%h0, %h0"
1190 [(set_attr "type" "test")
1191 (set_attr "length_immediate" "0")
1192 (set_attr "mode" "QI")])
1194 (define_expand "cmpqi_ext_3"
1199 (match_operand 0 "ext_register_operand" "q")
1202 (match_operand:QI 1 "general_operand" "qmn")))]
1206 (define_insn "cmpqi_ext_3_insn"
1211 (match_operand 0 "ext_register_operand" "q")
1214 (match_operand:QI 1 "general_operand" "qmn")))]
1215 "ix86_match_ccmode (insn, CCmode)"
1216 "cmp{b}\\t{%1, %h0|%h0, %1}"
1217 [(set_attr "type" "icmp")
1218 (set_attr "mode" "QI")])
1220 (define_insn "*cmpqi_ext_4"
1225 (match_operand 0 "ext_register_operand" "q")
1230 (match_operand 1 "ext_register_operand" "q")
1232 (const_int 8)) 0)))]
1233 "ix86_match_ccmode (insn, CCmode)"
1234 "cmp{b}\\t{%h1, %h0|%h0, %h1}"
1235 [(set_attr "type" "icmp")
1236 (set_attr "mode" "QI")])
1238 ;; These implement float point compares.
1239 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
1240 ;; which would allow mix and match FP modes on the compares. Which is what
1241 ;; the old patterns did, but with many more of them.
1243 (define_expand "cmpxf"
1245 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
1246 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
1250 ix86_compare_op0 = operands[0];
1251 ix86_compare_op1 = operands[1];
1255 (define_expand "cmptf"
1257 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
1258 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
1262 ix86_compare_op0 = operands[0];
1263 ix86_compare_op1 = operands[1];
1267 (define_expand "cmpdf"
1269 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
1270 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
1271 "TARGET_80387 || TARGET_SSE2"
1274 ix86_compare_op0 = operands[0];
1275 ix86_compare_op1 = operands[1];
1279 (define_expand "cmpsf"
1281 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
1282 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
1283 "TARGET_80387 || TARGET_SSE"
1286 ix86_compare_op0 = operands[0];
1287 ix86_compare_op1 = operands[1];
1291 ;; FP compares, step 1:
1292 ;; Set the FP condition codes.
1294 ;; CCFPmode compare with exceptions
1295 ;; CCFPUmode compare with no exceptions
1297 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
1298 ;; and that fp moves clobber the condition codes, and that there is
1299 ;; currently no way to describe this fact to reg-stack. So there are
1300 ;; no splitters yet for this.
1302 ;; %%% YIKES! This scheme does not retain a strong connection between
1303 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
1304 ;; work! Only allow tos/mem with tos in op 0.
1306 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
1307 ;; things aren't as bad as they sound...
1309 (define_insn "*cmpfp_0"
1310 [(set (match_operand:HI 0 "register_operand" "=a")
1312 [(compare:CCFP (match_operand 1 "register_operand" "f")
1313 (match_operand 2 "const0_operand" "X"))] 9))]
1315 && FLOAT_MODE_P (GET_MODE (operands[1]))
1316 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1319 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
1320 return \"ftst\;fnstsw\\t%0\;fstp\\t%y0\";
1322 return \"ftst\;fnstsw\\t%0\";
1324 [(set_attr "type" "multi")
1325 (set_attr "mode" "unknownfp")])
1327 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
1328 ;; used to manage the reg stack popping would not be preserved.
1330 (define_insn "*cmpfp_2_sf"
1333 (match_operand:SF 0 "register_operand" "f")
1334 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
1336 "* return output_fp_compare (insn, operands, 0, 0);"
1337 [(set_attr "type" "fcmp")
1338 (set_attr "mode" "SF")])
1340 (define_insn "*cmpfp_2_sf_1"
1341 [(set (match_operand:HI 0 "register_operand" "=a")
1344 (match_operand:SF 1 "register_operand" "f")
1345 (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))]
1347 "* return output_fp_compare (insn, operands, 2, 0);"
1348 [(set_attr "type" "fcmp")
1349 (set_attr "mode" "SF")])
1351 (define_insn "*cmpfp_2_df"
1354 (match_operand:DF 0 "register_operand" "f")
1355 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
1357 "* return output_fp_compare (insn, operands, 0, 0);"
1358 [(set_attr "type" "fcmp")
1359 (set_attr "mode" "DF")])
1361 (define_insn "*cmpfp_2_df_1"
1362 [(set (match_operand:HI 0 "register_operand" "=a")
1365 (match_operand:DF 1 "register_operand" "f")
1366 (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))]
1368 "* return output_fp_compare (insn, operands, 2, 0);"
1369 [(set_attr "type" "multi")
1370 (set_attr "mode" "DF")])
1372 (define_insn "*cmpfp_2_xf"
1375 (match_operand:XF 0 "register_operand" "f")
1376 (match_operand:XF 1 "register_operand" "f")))]
1378 "* return output_fp_compare (insn, operands, 0, 0);"
1379 [(set_attr "type" "fcmp")
1380 (set_attr "mode" "XF")])
1382 (define_insn "*cmpfp_2_tf"
1385 (match_operand:TF 0 "register_operand" "f")
1386 (match_operand:TF 1 "register_operand" "f")))]
1388 "* return output_fp_compare (insn, operands, 0, 0);"
1389 [(set_attr "type" "fcmp")
1390 (set_attr "mode" "XF")])
1392 (define_insn "*cmpfp_2_xf_1"
1393 [(set (match_operand:HI 0 "register_operand" "=a")
1396 (match_operand:XF 1 "register_operand" "f")
1397 (match_operand:XF 2 "register_operand" "f"))] 9))]
1399 "* return output_fp_compare (insn, operands, 2, 0);"
1400 [(set_attr "type" "multi")
1401 (set_attr "mode" "XF")])
1403 (define_insn "*cmpfp_2_tf_1"
1404 [(set (match_operand:HI 0 "register_operand" "=a")
1407 (match_operand:TF 1 "register_operand" "f")
1408 (match_operand:TF 2 "register_operand" "f"))] 9))]
1410 "* return output_fp_compare (insn, operands, 2, 0);"
1411 [(set_attr "type" "multi")
1412 (set_attr "mode" "XF")])
1414 (define_insn "*cmpfp_2u"
1415 [(set (reg:CCFPU 18)
1417 (match_operand 0 "register_operand" "f")
1418 (match_operand 1 "register_operand" "f")))]
1420 && FLOAT_MODE_P (GET_MODE (operands[0]))
1421 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1422 "* return output_fp_compare (insn, operands, 0, 1);"
1423 [(set_attr "type" "fcmp")
1424 (set_attr "mode" "unknownfp")])
1426 (define_insn "*cmpfp_2u_1"
1427 [(set (match_operand:HI 0 "register_operand" "=a")
1430 (match_operand 1 "register_operand" "f")
1431 (match_operand 2 "register_operand" "f"))] 9))]
1433 && FLOAT_MODE_P (GET_MODE (operands[1]))
1434 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
1435 "* return output_fp_compare (insn, operands, 2, 1);"
1436 [(set_attr "type" "multi")
1437 (set_attr "mode" "unknownfp")])
1439 ;; Patterns to match the SImode-in-memory ficom instructions.
1441 ;; %%% Play games with accepting gp registers, as otherwise we have to
1442 ;; force them to memory during rtl generation, which is no good. We
1443 ;; can get rid of this once we teach reload to do memory input reloads
1446 (define_insn "*ficom_1"
1449 (match_operand 0 "register_operand" "f,f")
1450 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
1451 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
1452 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
1455 ;; Split the not-really-implemented gp register case into a
1456 ;; push-op-pop sequence.
1458 ;; %%% This is most efficient, but am I gonna get in trouble
1459 ;; for separating cc0_setter and cc0_user?
1464 (match_operand:SF 0 "register_operand" "")
1465 (float (match_operand:SI 1 "register_operand" ""))))]
1466 "0 && TARGET_80387 && reload_completed"
1467 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
1468 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
1469 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
1470 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
1471 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
1472 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
1474 ;; FP compares, step 2
1475 ;; Move the fpsw to ax.
1477 (define_insn "x86_fnstsw_1"
1478 [(set (match_operand:HI 0 "register_operand" "=a")
1479 (unspec:HI [(reg 18)] 9))]
1482 [(set_attr "length" "2")
1483 (set_attr "mode" "SI")
1484 (set_attr "i387" "1")
1485 (set_attr "ppro_uops" "few")])
1487 ;; FP compares, step 3
1488 ;; Get ax into flags, general case.
1490 (define_insn "x86_sahf_1"
1492 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] 10))]
1495 [(set_attr "length" "1")
1496 (set_attr "athlon_decode" "vector")
1497 (set_attr "mode" "SI")
1498 (set_attr "ppro_uops" "one")])
1500 ;; Pentium Pro can do steps 1 through 3 in one go.
1502 (define_insn "*cmpfp_i"
1504 (compare:CCFP (match_operand 0 "register_operand" "f")
1505 (match_operand 1 "register_operand" "f")))]
1506 "TARGET_80387 && TARGET_CMOVE
1507 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1508 && FLOAT_MODE_P (GET_MODE (operands[0]))
1509 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1510 "* return output_fp_compare (insn, operands, 1, 0);"
1511 [(set_attr "type" "fcmp")
1512 (set_attr "mode" "unknownfp")
1513 (set_attr "athlon_decode" "vector")])
1515 (define_insn "*cmpfp_i_sse"
1517 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1518 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1520 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1521 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1522 "* return output_fp_compare (insn, operands, 1, 0);"
1523 [(set_attr "type" "fcmp,sse")
1524 (set_attr "mode" "unknownfp")
1525 (set_attr "athlon_decode" "vector")])
1527 (define_insn "*cmpfp_i_sse_only"
1529 (compare:CCFP (match_operand 0 "register_operand" "x")
1530 (match_operand 1 "nonimmediate_operand" "xm")))]
1531 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1532 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1533 "* return output_fp_compare (insn, operands, 1, 0);"
1534 [(set_attr "type" "sse")
1535 (set_attr "mode" "unknownfp")
1536 (set_attr "athlon_decode" "vector")])
1538 (define_insn "*cmpfp_iu"
1539 [(set (reg:CCFPU 17)
1540 (compare:CCFPU (match_operand 0 "register_operand" "f")
1541 (match_operand 1 "register_operand" "f")))]
1542 "TARGET_80387 && TARGET_CMOVE
1543 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1544 && FLOAT_MODE_P (GET_MODE (operands[0]))
1545 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1546 "* return output_fp_compare (insn, operands, 1, 1);"
1547 [(set_attr "type" "fcmp")
1548 (set_attr "mode" "unknownfp")
1549 (set_attr "athlon_decode" "vector")])
1551 (define_insn "*cmpfp_iu_sse"
1552 [(set (reg:CCFPU 17)
1553 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1554 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1556 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1557 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1558 "* return output_fp_compare (insn, operands, 1, 1);"
1559 [(set_attr "type" "fcmp,sse")
1560 (set_attr "mode" "unknownfp")
1561 (set_attr "athlon_decode" "vector")])
1563 (define_insn "*cmpfp_iu_sse_only"
1564 [(set (reg:CCFPU 17)
1565 (compare:CCFPU (match_operand 0 "register_operand" "x")
1566 (match_operand 1 "nonimmediate_operand" "xm")))]
1567 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1568 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1569 "* return output_fp_compare (insn, operands, 1, 1);"
1570 [(set_attr "type" "sse")
1571 (set_attr "mode" "unknownfp")
1572 (set_attr "athlon_decode" "vector")])
1574 ;; Move instructions.
1576 ;; General case of fullword move.
1578 (define_expand "movsi"
1579 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1580 (match_operand:SI 1 "general_operand" ""))]
1582 "ix86_expand_move (SImode, operands); DONE;")
1584 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1587 ;; %%% We don't use a post-inc memory reference because x86 is not a
1588 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1589 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1590 ;; targets without our curiosities, and it is just as easy to represent
1591 ;; this differently.
1593 (define_insn "*pushsi2"
1594 [(set (match_operand:SI 0 "push_operand" "=<")
1595 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1598 [(set_attr "type" "push")
1599 (set_attr "mode" "SI")])
1601 (define_insn "*pushsi2_prologue"
1602 [(set (match_operand:SI 0 "push_operand" "=<")
1603 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1604 (set (reg:SI 6) (reg:SI 6))]
1607 [(set_attr "type" "push")
1608 (set_attr "mode" "SI")])
1610 (define_insn "*popsi1_epilogue"
1611 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1612 (mem:SI (reg:SI 7)))
1614 (plus:SI (reg:SI 7) (const_int 4)))
1615 (set (reg:SI 6) (reg:SI 6))]
1618 [(set_attr "type" "pop")
1619 (set_attr "mode" "SI")])
1621 (define_insn "popsi1"
1622 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1623 (mem:SI (reg:SI 7)))
1625 (plus:SI (reg:SI 7) (const_int 4)))]
1628 [(set_attr "type" "pop")
1629 (set_attr "mode" "SI")])
1631 (define_insn "*movsi_xor"
1632 [(set (match_operand:SI 0 "register_operand" "=r")
1633 (match_operand:SI 1 "const0_operand" "i"))
1634 (clobber (reg:CC 17))]
1635 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1636 "xor{l}\\t{%0, %0|%0, %0}"
1637 [(set_attr "type" "alu1")
1638 (set_attr "mode" "SI")
1639 (set_attr "length_immediate" "0")])
1641 (define_insn "*movsi_or"
1642 [(set (match_operand:SI 0 "register_operand" "=r")
1643 (match_operand:SI 1 "immediate_operand" "i"))
1644 (clobber (reg:CC 17))]
1645 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1646 && INTVAL (operands[1]) == -1
1647 && (TARGET_PENTIUM || optimize_size)"
1650 operands[1] = constm1_rtx;
1651 return \"or{l}\\t{%1, %0|%0, %1}\";
1653 [(set_attr "type" "alu1")
1654 (set_attr "mode" "SI")
1655 (set_attr "length_immediate" "1")])
1657 (define_insn "*movsi_1"
1658 [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m,!*y,!r")
1659 (match_operand:SI 1 "general_operand" "im,rinm,rinm,rin,r,*y"))]
1660 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1663 switch (get_attr_type (insn))
1666 return \"movd\\t{%1, %0|%0, %1}\";
1669 return \"lea{l}\\t{%1, %0|%0, %1}\";
1672 if (flag_pic && SYMBOLIC_CONST (operands[1]))
1674 return \"mov{l}\\t{%1, %0|%0, %1}\";
1678 (cond [(ior (match_operand:SI 0 "mmx_reg_operand" "")
1679 (match_operand:SI 1 "mmx_reg_operand" ""))
1680 (const_string "mmx")
1681 (and (ne (symbol_ref "flag_pic") (const_int 0))
1682 (match_operand:SI 1 "symbolic_operand" ""))
1683 (const_string "lea")
1685 (const_string "imov")))
1686 (set_attr "modrm" "0,*,0,*,*,*")
1687 (set_attr "mode" "SI")])
1689 (define_insn "*swapsi"
1690 [(set (match_operand:SI 0 "register_operand" "+r")
1691 (match_operand:SI 1 "register_operand" "+r"))
1696 [(set_attr "type" "imov")
1697 (set_attr "pent_pair" "np")
1698 (set_attr "athlon_decode" "vector")
1699 (set_attr "mode" "SI")
1700 (set_attr "modrm" "0")
1701 (set_attr "ppro_uops" "few")])
1703 (define_expand "movhi"
1704 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1705 (match_operand:HI 1 "general_operand" ""))]
1707 "ix86_expand_move (HImode, operands); DONE;")
1709 (define_insn "*pushhi2"
1710 [(set (match_operand:HI 0 "push_operand" "=<,<")
1711 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1714 push{w}\\t{|WORD PTR }%1
1716 [(set_attr "type" "push")
1717 (set_attr "mode" "HI")])
1719 (define_insn "*pophi1"
1720 [(set (match_operand:HI 0 "nonimmediate_operand" "=r*m")
1721 (mem:HI (reg:SI 7)))
1723 (plus:SI (reg:SI 7) (const_int 2)))]
1726 [(set_attr "type" "pop")
1727 (set_attr "mode" "HI")])
1729 (define_insn "*movhi_1"
1730 [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
1731 (match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
1732 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1735 switch (get_attr_type (insn))
1738 /* movzwl is faster than movw on p2 due to partial word stalls,
1739 though not as fast as an aligned movl. */
1740 return \"movz{wl|x}\\t{%1, %k0|%k0, %1}\";
1742 if (get_attr_mode (insn) == MODE_SI)
1743 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
1745 return \"mov{w}\\t{%1, %0|%0, %1}\";
1749 (cond [(and (eq_attr "alternative" "0,1")
1750 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1752 (eq (symbol_ref "TARGET_HIMODE_MATH")
1754 (const_string "imov")
1755 (and (eq_attr "alternative" "2,3,4")
1756 (match_operand:HI 1 "aligned_operand" ""))
1757 (const_string "imov")
1758 (and (ne (symbol_ref "TARGET_MOVX")
1760 (eq_attr "alternative" "0,1,3,4"))
1761 (const_string "imovx")
1763 (const_string "imov")))
1765 (cond [(eq_attr "type" "imovx")
1767 (and (eq_attr "alternative" "2,3,4")
1768 (match_operand:HI 1 "aligned_operand" ""))
1770 (and (eq_attr "alternative" "0,1")
1771 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1773 (eq (symbol_ref "TARGET_HIMODE_MATH")
1777 (const_string "HI")))
1778 (set_attr "modrm" "0,*,*,0,*,*")])
1780 (define_insn "*swaphi_1"
1781 [(set (match_operand:HI 0 "register_operand" "+r")
1782 (match_operand:HI 1 "register_operand" "+r"))
1785 "TARGET_PARTIAL_REG_STALL"
1787 [(set_attr "type" "imov")
1788 (set_attr "pent_pair" "np")
1789 (set_attr "mode" "HI")
1790 (set_attr "modrm" "0")
1791 (set_attr "ppro_uops" "few")])
1793 (define_insn "*swaphi_2"
1794 [(set (match_operand:HI 0 "register_operand" "+r")
1795 (match_operand:HI 1 "register_operand" "+r"))
1798 "! TARGET_PARTIAL_REG_STALL"
1799 "xchg{l}\\t%k1, %k0"
1800 [(set_attr "type" "imov")
1801 (set_attr "pent_pair" "np")
1802 (set_attr "mode" "SI")
1803 (set_attr "modrm" "0")
1804 (set_attr "ppro_uops" "few")])
1806 (define_expand "movstricthi"
1807 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1808 (match_operand:HI 1 "general_operand" ""))]
1809 "! TARGET_PARTIAL_REG_STALL"
1812 /* Don't generate memory->memory moves, go through a register */
1813 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1814 operands[1] = force_reg (HImode, operands[1]);
1817 (define_insn "*movstricthi_1"
1818 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1819 (match_operand:HI 1 "general_operand" "rn,m"))]
1820 "! TARGET_PARTIAL_REG_STALL
1821 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1822 "mov{w}\\t{%1, %0|%0, %1}"
1823 [(set_attr "type" "imov")
1824 (set_attr "mode" "HI")])
1826 (define_insn "*movstricthi_xor"
1827 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1828 (match_operand:HI 1 "const0_operand" "i"))
1829 (clobber (reg:CC 17))]
1830 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1831 "xor{w}\\t{%0, %0|%0, %0}"
1832 [(set_attr "type" "alu1")
1833 (set_attr "mode" "HI")
1834 (set_attr "length_immediate" "0")])
1836 (define_expand "movqi"
1837 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1838 (match_operand:QI 1 "general_operand" ""))]
1840 "ix86_expand_move (QImode, operands); DONE;")
1842 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1843 ;; "push a byte". But actually we use pushw, which has the effect
1844 ;; of rounding the amount pushed up to a halfword.
1846 (define_insn "*pushqi2"
1847 [(set (match_operand:QI 0 "push_operand" "=<,<")
1848 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1851 push{w}\\t{|word ptr }%1
1853 [(set_attr "type" "push")
1854 (set_attr "mode" "HI")])
1856 (define_insn "*popqi1"
1857 [(set (match_operand:QI 0 "nonimmediate_operand" "=r*m")
1858 (mem:QI (reg:SI 7)))
1860 (plus:SI (reg:SI 7) (const_int 2)))]
1863 [(set_attr "type" "pop")
1864 (set_attr "mode" "HI")])
1866 ;; Situation is quite tricky about when to choose full sized (SImode) move
1867 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1868 ;; partial register dependency machines (such as AMD Athlon), where QImode
1869 ;; moves issue extra dependency and for partial register stalls machines
1870 ;; that don't use QImode patterns (and QImode move cause stall on the next
1873 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1874 ;; register stall machines with, where we use QImode instructions, since
1875 ;; partial register stall can be caused there. Then we use movzx.
1876 (define_insn "*movqi_1"
1877 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1878 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1879 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1882 switch (get_attr_type (insn))
1885 if (!QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1887 return \"movz{bl|x}\\t{%1, %k0|%k0, %1}\";
1889 if (get_attr_mode (insn) == MODE_SI)
1890 return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
1892 return \"mov{b}\\t{%1, %0|%0, %1}\";
1896 (cond [(and (eq_attr "alternative" "3")
1897 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1899 (eq (symbol_ref "TARGET_QIMODE_MATH")
1901 (const_string "imov")
1902 (eq_attr "alternative" "3,5")
1903 (const_string "imovx")
1904 (and (ne (symbol_ref "TARGET_MOVX")
1906 (eq_attr "alternative" "2"))
1907 (const_string "imovx")
1909 (const_string "imov")))
1911 (cond [(eq_attr "alternative" "3,4,5")
1913 (eq_attr "alternative" "6")
1915 (eq_attr "type" "imovx")
1917 (and (eq_attr "type" "imov")
1918 (and (eq_attr "alternative" "0,1,2")
1919 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1922 ;; Avoid partial register stalls when not using QImode arithmetic
1923 (and (eq_attr "type" "imov")
1924 (and (eq_attr "alternative" "0,1,2")
1925 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1927 (eq (symbol_ref "TARGET_QIMODE_MATH")
1931 (const_string "QI")))])
1933 (define_expand "reload_outqi"
1934 [(parallel [(match_operand:QI 0 "" "=m")
1935 (match_operand:QI 1 "register_operand" "r")
1936 (match_operand:QI 2 "register_operand" "=&q")])]
1941 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1943 if (reg_overlap_mentioned_p (op2, op0))
1945 if (! q_regs_operand (op1, QImode))
1947 emit_insn (gen_movqi (op2, op1));
1950 emit_insn (gen_movqi (op0, op1));
1954 (define_insn "*swapqi"
1955 [(set (match_operand:QI 0 "register_operand" "+r")
1956 (match_operand:QI 1 "register_operand" "+r"))
1961 [(set_attr "type" "imov")
1962 (set_attr "pent_pair" "np")
1963 (set_attr "mode" "QI")
1964 (set_attr "modrm" "0")
1965 (set_attr "ppro_uops" "few")])
1967 (define_expand "movstrictqi"
1968 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1969 (match_operand:QI 1 "general_operand" ""))]
1970 "! TARGET_PARTIAL_REG_STALL"
1973 /* Don't generate memory->memory moves, go through a register */
1974 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1975 operands[1] = force_reg (QImode, operands[1]);
1978 (define_insn "*movstrictqi_1"
1979 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1980 (match_operand:QI 1 "general_operand" "*qn,m"))]
1981 "! TARGET_PARTIAL_REG_STALL
1982 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1983 "mov{b}\\t{%1, %0|%0, %1}"
1984 [(set_attr "type" "imov")
1985 (set_attr "mode" "QI")])
1987 (define_insn "*movstrictqi_xor"
1988 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1989 (match_operand:QI 1 "const0_operand" "i"))
1990 (clobber (reg:CC 17))]
1991 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1992 "xor{b}\\t{%0, %0|%0, %0}"
1993 [(set_attr "type" "alu1")
1994 (set_attr "mode" "QI")
1995 (set_attr "length_immediate" "0")])
1997 (define_insn "*movsi_extv_1"
1998 [(set (match_operand:SI 0 "register_operand" "=r")
1999 (sign_extract:SI (match_operand:SI 1 "register_operand" "q")
2003 "movs{bl|x}\\t{%h1, %0|%0, %h1}"
2004 [(set_attr "type" "imovx")
2005 (set_attr "mode" "SI")])
2007 (define_insn "*movhi_extv_1"
2008 [(set (match_operand:HI 0 "register_operand" "=r")
2009 (sign_extract:HI (match_operand:SI 1 "register_operand" "q")
2013 "movs{bl|x}\\t{%h1, %k0|%k0, %h1}"
2014 [(set_attr "type" "imovx")
2015 (set_attr "mode" "SI")])
2017 (define_insn "*movqi_extv_1"
2018 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?r")
2019 (sign_extract:QI (match_operand:SI 1 "register_operand" "q,q")
2025 switch (get_attr_type (insn))
2028 return \"movs{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2030 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2034 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2035 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2036 (ne (symbol_ref "TARGET_MOVX")
2038 (const_string "imovx")
2039 (const_string "imov")))
2041 (if_then_else (eq_attr "type" "imovx")
2043 (const_string "QI")))])
2045 (define_insn "*movsi_extzv_1"
2046 [(set (match_operand:SI 0 "register_operand" "=r")
2047 (zero_extract:SI (match_operand 1 "ext_register_operand" "q")
2051 "movz{bl|x}\\t{%h1, %0|%0, %h1}"
2052 [(set_attr "type" "imovx")
2053 (set_attr "mode" "SI")])
2055 (define_insn "*movqi_extzv_1"
2056 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?r")
2057 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "q,q")
2063 switch (get_attr_type (insn))
2066 return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
2068 return \"mov{b}\\t{%h1, %0|%0, %h1}\";
2072 (if_then_else (and (match_operand:QI 0 "register_operand" "")
2073 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
2074 (ne (symbol_ref "TARGET_MOVX")
2076 (const_string "imovx")
2077 (const_string "imov")))
2079 (if_then_else (eq_attr "type" "imovx")
2081 (const_string "QI")))])
2083 (define_insn "*movsi_insv_1"
2084 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+q")
2087 (match_operand:SI 1 "nonimmediate_operand" "qm"))]
2089 "mov{b}\\t{%b1, %h0|%h0, %b1}"
2090 [(set_attr "type" "imov")
2091 (set_attr "mode" "QI")])
2093 (define_insn "*movqi_insv_2"
2094 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+q")
2097 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "q")
2101 "mov{b}\\t{%h1, %h0|%h0, %h1}"
2102 [(set_attr "type" "imov")
2103 (set_attr "mode" "QI")])
2105 (define_expand "movdi"
2106 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2107 (match_operand:DI 1 "general_operand" ""))]
2109 "ix86_expand_move (DImode, operands); DONE;")
2111 (define_insn "*pushdi"
2112 [(set (match_operand:DI 0 "push_operand" "=<")
2113 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
2117 (define_insn "*movdi_2"
2118 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y")
2119 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m"))]
2120 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
2124 movq\\t{%1, %0|%0, %1}
2125 movq\\t{%1, %0|%0, %1}"
2126 [(set_attr "type" "*,*,mmx,mmx")])
2129 [(set (match_operand:DI 0 "push_operand" "")
2130 (match_operand:DI 1 "general_operand" ""))]
2131 "reload_completed && ! MMX_REG_P (operands[1])"
2133 "if (!ix86_split_long_move (operands)) abort (); DONE;")
2135 ;; %%% This multiword shite has got to go.
2137 [(set (match_operand:DI 0 "nonimmediate_operand" "")
2138 (match_operand:DI 1 "general_operand" ""))]
2139 "reload_completed && ! MMX_REG_P (operands[0]) && ! MMX_REG_P (operands[1])"
2140 [(set (match_dup 2) (match_dup 5))
2141 (set (match_dup 3) (match_dup 6))]
2142 "if (ix86_split_long_move (operands)) DONE;")
2144 (define_expand "movsf"
2145 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2146 (match_operand:SF 1 "general_operand" ""))]
2148 "ix86_expand_move (SFmode, operands); DONE;")
2150 (define_insn "*pushsf"
2151 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2152 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2156 switch (which_alternative)
2159 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2160 operands[0] = gen_rtx_MEM (SFmode, stack_pointer_rtx);
2161 operands[2] = stack_pointer_rtx;
2162 operands[3] = GEN_INT (4);
2163 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2164 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2166 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2169 return \"push{l}\\t%1\";
2177 [(set_attr "type" "multi,push,multi")
2178 (set_attr "mode" "SF,SI,SF")])
2181 [(set (match_operand:SF 0 "push_operand" "")
2182 (match_operand:SF 1 "memory_operand" ""))]
2184 && GET_CODE (operands[1]) == MEM
2185 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2186 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2189 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2192 ;; %%% Kill this when call knows how to work this out.
2194 [(set (match_operand:SF 0 "push_operand" "")
2195 (match_operand:SF 1 "register_operand" ""))]
2196 "ANY_FP_REGNO_P (REGNO (operands[1]))"
2197 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2198 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2200 (define_insn "*movsf_1"
2201 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m")
2202 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,H,x,xm#rf,x#rf"))]
2203 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2204 && (reload_in_progress || reload_completed
2205 || GET_CODE (operands[1]) != CONST_DOUBLE
2206 || memory_operand (operands[0], SFmode))"
2209 switch (which_alternative)
2212 if (REG_P (operands[1])
2213 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2214 return \"fstp\\t%y0\";
2215 else if (STACK_TOP_P (operands[0]))
2216 return \"fld%z1\\t%y1\";
2218 return \"fst\\t%y0\";
2221 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2222 return \"fstp%z0\\t%y0\";
2224 return \"fst%z0\\t%y0\";
2227 switch (standard_80387_constant_p (operands[1]))
2238 return \"mov{l}\\t{%1, %0|%0, %1}\";
2240 return \"pxor\\t%0, %0\";
2242 if (TARGET_PARTIAL_REG_DEPENDENCY)
2243 return \"movaps\\t{%1, %0|%0, %1}\";
2245 return \"movss\\t{%1, %0|%0, %1}\";
2248 return \"movss\\t{%1, %0|%0, %1}\";
2254 [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse")
2255 (set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF")])
2257 (define_insn "*swapsf"
2258 [(set (match_operand:SF 0 "register_operand" "+f")
2259 (match_operand:SF 1 "register_operand" "+f"))
2262 "reload_completed || !TARGET_SSE2"
2265 if (STACK_TOP_P (operands[0]))
2266 return \"fxch\\t%1\";
2268 return \"fxch\\t%0\";
2270 [(set_attr "type" "fxch")
2271 (set_attr "mode" "SF")])
2273 (define_expand "movdf"
2274 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2275 (match_operand:DF 1 "general_operand" ""))]
2277 "ix86_expand_move (DFmode, operands); DONE;")
2279 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2280 ;; Size of pushdf using integer insturctions is 2+2*memory operand size
2281 ;; On the average, pushdf using integers can be still shorter. Allow this
2282 ;; pattern for optimize_size too.
2284 (define_insn "*pushdf_nointeger"
2285 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2286 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2287 "!TARGET_INTEGER_DFMODE_MOVES"
2290 switch (which_alternative)
2293 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2294 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2295 operands[2] = stack_pointer_rtx;
2296 operands[3] = GEN_INT (8);
2297 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2298 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2300 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2311 [(set_attr "type" "multi")
2312 (set_attr "mode" "DF,SI,SI,DF")])
2314 (define_insn "*pushdf_integer"
2315 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2316 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2317 "TARGET_INTEGER_DFMODE_MOVES"
2320 switch (which_alternative)
2323 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2324 operands[0] = gen_rtx_MEM (DFmode, stack_pointer_rtx);
2325 operands[2] = stack_pointer_rtx;
2326 operands[3] = GEN_INT (8);
2327 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2328 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2330 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2340 [(set_attr "type" "multi")
2341 (set_attr "mode" "DF,SI,DF")])
2343 ;; %%% Kill this when call knows how to work this out.
2345 [(set (match_operand:DF 0 "push_operand" "")
2346 (match_operand:DF 1 "register_operand" ""))]
2347 "reload_completed && ANY_FP_REGNO_P (REGNO (operands[1]))"
2348 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2349 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2353 [(set (match_operand:DF 0 "push_operand" "")
2354 (match_operand:DF 1 "general_operand" ""))]
2357 "if (!ix86_split_long_move (operands)) abort (); DONE;")
2359 ;; Moving is usually shorter when only FP registers are used. This separate
2360 ;; movdf pattern avoids the use of integer registers for FP operations
2361 ;; when optimizing for size.
2363 (define_insn "*movdf_nointeger"
2364 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2365 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,H,Y#f,YHm#f,Y#f"))]
2366 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2367 && (optimize_size || !TARGET_INTEGER_DFMODE_MOVES)
2368 && (reload_in_progress || reload_completed
2369 || GET_CODE (operands[1]) != CONST_DOUBLE
2370 || memory_operand (operands[0], DFmode))"
2373 switch (which_alternative)
2376 if (REG_P (operands[1])
2377 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2378 return \"fstp\\t%y0\";
2379 else if (STACK_TOP_P (operands[0]))
2380 return \"fld%z1\\t%y1\";
2382 return \"fst\\t%y0\";
2385 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2386 return \"fstp%z0\\t%y0\";
2388 return \"fst%z0\\t%y0\";
2391 switch (standard_80387_constant_p (operands[1]))
2404 return \"pxor\\t%0, %0\";
2406 if (TARGET_PARTIAL_REG_DEPENDENCY)
2407 return \"movapd\\t{%1, %0|%0, %1}\";
2409 return \"movsd\\t{%1, %0|%0, %1}\";
2412 return \"movsd\\t{%1, %0|%0, %1}\";
2418 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2419 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2421 (define_insn "*movdf_integer"
2422 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2423 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,H,Y#rf,Ym#rf,Y#rf"))]
2424 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2425 && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
2426 && (reload_in_progress || reload_completed
2427 || GET_CODE (operands[1]) != CONST_DOUBLE
2428 || memory_operand (operands[0], DFmode))"
2431 switch (which_alternative)
2434 if (REG_P (operands[1])
2435 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2436 return \"fstp\\t%y0\";
2437 else if (STACK_TOP_P (operands[0]))
2438 return \"fld%z1\\t%y1\";
2440 return \"fst\\t%y0\";
2443 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2444 return \"fstp%z0\\t%y0\";
2446 return \"fst%z0\\t%y0\";
2449 switch (standard_80387_constant_p (operands[1]))
2463 return \"pxor\\t%0, %0\";
2465 if (TARGET_PARTIAL_REG_DEPENDENCY)
2466 return \"movapd\\t{%1, %0|%0, %1}\";
2468 return \"movsd\\t{%1, %0|%0, %1}\";
2471 return \"movsd\\t{%1, %0|%0, %1}\";
2477 [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
2478 (set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
2481 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2482 (match_operand:DF 1 "general_operand" ""))]
2484 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2485 && ! (ANY_FP_REG_P (operands[0]) ||
2486 (GET_CODE (operands[0]) == SUBREG
2487 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2488 && ! (ANY_FP_REG_P (operands[1]) ||
2489 (GET_CODE (operands[1]) == SUBREG
2490 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2491 [(set (match_dup 2) (match_dup 5))
2492 (set (match_dup 3) (match_dup 6))]
2493 "if (ix86_split_long_move (operands)) DONE;")
2495 (define_insn "*swapdf"
2496 [(set (match_operand:DF 0 "register_operand" "+f")
2497 (match_operand:DF 1 "register_operand" "+f"))
2500 "reload_completed || !TARGET_SSE2"
2503 if (STACK_TOP_P (operands[0]))
2504 return \"fxch\\t%1\";
2506 return \"fxch\\t%0\";
2508 [(set_attr "type" "fxch")
2509 (set_attr "mode" "DF")])
2511 (define_expand "movxf"
2512 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2513 (match_operand:XF 1 "general_operand" ""))]
2515 "ix86_expand_move (XFmode, operands); DONE;")
2517 (define_expand "movtf"
2518 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2519 (match_operand:TF 1 "general_operand" ""))]
2521 "ix86_expand_move (TFmode, operands); DONE;")
2523 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2524 ;; Size of pushdf using integer insturctions is 3+3*memory operand size
2525 ;; Pushing using integer instructions is longer except for constants
2526 ;; and direct memory references.
2527 ;; (assuming that any given constant is pushed only once, but this ought to be
2528 ;; handled elsewhere).
2530 (define_insn "*pushxf_nointeger"
2531 [(set (match_operand:XF 0 "push_operand" "=<,<,<")
2532 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2536 switch (which_alternative)
2539 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2540 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2541 operands[2] = stack_pointer_rtx;
2542 operands[3] = GEN_INT (12);
2543 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2544 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2546 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2556 [(set_attr "type" "multi")
2557 (set_attr "mode" "XF,SI,SI")])
2559 (define_insn "*pushtf_nointeger"
2560 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
2561 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
2565 switch (which_alternative)
2568 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2569 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2570 operands[2] = stack_pointer_rtx;
2571 operands[3] = GEN_INT (16);
2572 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2573 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2575 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2585 [(set_attr "type" "multi")
2586 (set_attr "mode" "XF,SI,SI")])
2588 (define_insn "*pushxf_integer"
2589 [(set (match_operand:XF 0 "push_operand" "=<,<")
2590 (match_operand:XF 1 "general_no_elim_operand" "f#r,rFo#f"))]
2594 switch (which_alternative)
2597 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2598 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2599 operands[2] = stack_pointer_rtx;
2600 operands[3] = GEN_INT (12);
2601 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2602 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2604 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2613 [(set_attr "type" "multi")
2614 (set_attr "mode" "XF,SI")])
2616 (define_insn "*pushtf_integer"
2617 [(set (match_operand:TF 0 "push_operand" "=<,<")
2618 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
2622 switch (which_alternative)
2625 /* %%% We loose REG_DEAD notes for controling pops if we split late. */
2626 operands[0] = gen_rtx_MEM (XFmode, stack_pointer_rtx);
2627 operands[2] = stack_pointer_rtx;
2628 operands[3] = GEN_INT (16);
2629 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2630 return \"sub{l}\\t{%3, %2|%2, %3}\;fstp%z0\\t%y0\";
2632 return \"sub{l}\\t{%3, %2|%2, %3}\;fst%z0\\t%y0\";
2641 [(set_attr "type" "multi")
2642 (set_attr "mode" "XF,SI")])
2645 [(set (match_operand 0 "push_operand" "")
2646 (match_operand 1 "general_operand" ""))]
2648 && (GET_MODE (operands[0]) == XFmode
2649 || GET_MODE (operands[0]) == TFmode
2650 || GET_MODE (operands[0]) == DFmode)
2651 && (!REG_P (operands[1]) || !ANY_FP_REGNO_P (REGNO (operands[1])))"
2653 "if (!ix86_split_long_move (operands)) abort (); DONE;")
2656 [(set (match_operand:XF 0 "push_operand" "")
2657 (match_operand:XF 1 "register_operand" ""))]
2658 "ANY_FP_REGNO_P (REGNO (operands[1]))"
2659 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
2660 (set (mem:XF (reg:SI 7)) (match_dup 1))])
2663 [(set (match_operand:TF 0 "push_operand" "")
2664 (match_operand:TF 1 "register_operand" ""))]
2665 "ANY_FP_REGNO_P (REGNO (operands[1]))"
2666 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
2667 (set (mem:TF (reg:SI 7)) (match_dup 1))])
2669 ;; Do not use integer registers when optimizing for size
2670 (define_insn "*movxf_nointeger"
2671 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2672 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2673 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2675 && (reload_in_progress || reload_completed
2676 || GET_CODE (operands[1]) != CONST_DOUBLE
2677 || memory_operand (operands[0], XFmode))"
2680 switch (which_alternative)
2683 if (REG_P (operands[1])
2684 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2685 return \"fstp\\t%y0\";
2686 else if (STACK_TOP_P (operands[0]))
2687 return \"fld%z1\\t%y1\";
2689 return \"fst\\t%y0\";
2692 /* There is no non-popping store to memory for XFmode. So if
2693 we need one, follow the store with a load. */
2694 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2695 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
2697 return \"fstp%z0\\t%y0\";
2700 switch (standard_80387_constant_p (operands[1]))
2714 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2715 (set_attr "mode" "XF,XF,XF,SI,SI")])
2717 (define_insn "*movtf_nointeger"
2718 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2719 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2720 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2722 && (reload_in_progress || reload_completed
2723 || GET_CODE (operands[1]) != CONST_DOUBLE
2724 || memory_operand (operands[0], TFmode))"
2727 switch (which_alternative)
2730 if (REG_P (operands[1])
2731 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2732 return \"fstp\\t%y0\";
2733 else if (STACK_TOP_P (operands[0]))
2734 return \"fld%z1\\t%y1\";
2736 return \"fst\\t%y0\";
2739 /* There is no non-popping store to memory for XFmode. So if
2740 we need one, follow the store with a load. */
2741 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2742 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
2744 return \"fstp%z0\\t%y0\";
2747 switch (standard_80387_constant_p (operands[1]))
2761 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2762 (set_attr "mode" "XF,XF,XF,SI,SI")])
2764 (define_insn "*movxf_integer"
2765 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2766 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2767 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2769 && (reload_in_progress || reload_completed
2770 || GET_CODE (operands[1]) != CONST_DOUBLE
2771 || memory_operand (operands[0], XFmode))"
2774 switch (which_alternative)
2777 if (REG_P (operands[1])
2778 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2779 return \"fstp\\t%y0\";
2780 else if (STACK_TOP_P (operands[0]))
2781 return \"fld%z1\\t%y1\";
2783 return \"fst\\t%y0\";
2786 /* There is no non-popping store to memory for XFmode. So if
2787 we need one, follow the store with a load. */
2788 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2789 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
2791 return \"fstp%z0\\t%y0\";
2794 switch (standard_80387_constant_p (operands[1]))
2808 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2809 (set_attr "mode" "XF,XF,XF,SI,SI")])
2811 (define_insn "*movtf_integer"
2812 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2813 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2814 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2816 && (reload_in_progress || reload_completed
2817 || GET_CODE (operands[1]) != CONST_DOUBLE
2818 || memory_operand (operands[0], TFmode))"
2821 switch (which_alternative)
2824 if (REG_P (operands[1])
2825 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2826 return \"fstp\\t%y0\";
2827 else if (STACK_TOP_P (operands[0]))
2828 return \"fld%z1\\t%y1\";
2830 return \"fst\\t%y0\";
2833 /* There is no non-popping store to memory for XFmode. So if
2834 we need one, follow the store with a load. */
2835 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2836 return \"fstp%z0\\t%y0\;fld%z0\\t%y0\";
2838 return \"fstp%z0\\t%y0\";
2841 switch (standard_80387_constant_p (operands[1]))
2855 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2856 (set_attr "mode" "XF,XF,XF,SI,SI")])
2859 [(set (match_operand 0 "nonimmediate_operand" "")
2860 (match_operand 1 "general_operand" ""))]
2862 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2863 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
2864 && ! (ANY_FP_REG_P (operands[0]) ||
2865 (GET_CODE (operands[0]) == SUBREG
2866 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2867 && ! (ANY_FP_REG_P (operands[1]) ||
2868 (GET_CODE (operands[1]) == SUBREG
2869 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2870 [(set (match_dup 2) (match_dup 5))
2871 (set (match_dup 3) (match_dup 6))
2872 (set (match_dup 4) (match_dup 7))]
2873 "if (ix86_split_long_move (operands)) DONE;")
2876 [(set (match_operand 0 "register_operand" "")
2877 (match_operand 1 "memory_operand" ""))]
2879 && GET_CODE (operands[1]) == MEM
2880 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
2881 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
2882 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2883 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
2884 && (!(SSE_REG_P (operands[0]) ||
2885 (GET_CODE (operands[0]) == SUBREG
2886 && SSE_REG_P (SUBREG_REG (operands[0]))))
2887 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
2888 && (!(FP_REG_P (operands[0]) ||
2889 (GET_CODE (operands[0]) == SUBREG
2890 && FP_REG_P (SUBREG_REG (operands[0]))))
2891 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
2894 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2896 (define_insn "swapxf"
2897 [(set (match_operand:XF 0 "register_operand" "+f")
2898 (match_operand:XF 1 "register_operand" "+f"))
2904 if (STACK_TOP_P (operands[0]))
2905 return \"fxch\\t%1\";
2907 return \"fxch\\t%0\";
2909 [(set_attr "type" "fxch")
2910 (set_attr "mode" "XF")])
2912 (define_insn "swaptf"
2913 [(set (match_operand:TF 0 "register_operand" "+f")
2914 (match_operand:TF 1 "register_operand" "+f"))
2920 if (STACK_TOP_P (operands[0]))
2921 return \"fxch\\t%1\";
2923 return \"fxch\\t%0\";
2925 [(set_attr "type" "fxch")
2926 (set_attr "mode" "XF")])
2928 ;; Zero extension instructions
2930 (define_expand "zero_extendhisi2"
2931 [(set (match_operand:SI 0 "register_operand" "")
2932 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2936 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
2938 operands[1] = force_reg (HImode, operands[1]);
2939 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
2944 (define_insn "zero_extendhisi2_and"
2945 [(set (match_operand:SI 0 "register_operand" "=r")
2946 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
2947 (clobber (reg:CC 17))]
2948 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2950 [(set_attr "type" "alu1")
2951 (set_attr "mode" "SI")])
2954 [(set (match_operand:SI 0 "register_operand" "")
2955 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
2956 (clobber (reg:CC 17))]
2957 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2958 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
2959 (clobber (reg:CC 17))])]
2962 (define_insn "*zero_extendhisi2_movzwl"
2963 [(set (match_operand:SI 0 "register_operand" "=r")
2964 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
2965 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2966 "movz{wl|x}\\t{%1, %0|%0, %1}"
2967 [(set_attr "type" "imovx")
2968 (set_attr "mode" "SI")])
2970 (define_expand "zero_extendqihi2"
2972 [(set (match_operand:HI 0 "register_operand" "")
2973 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
2974 (clobber (reg:CC 17))])]
2978 (define_insn "*zero_extendqihi2_and"
2979 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
2980 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
2981 (clobber (reg:CC 17))]
2982 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
2984 [(set_attr "type" "alu1")
2985 (set_attr "mode" "HI")])
2987 (define_insn "*zero_extendqihi2_movzbw_and"
2988 [(set (match_operand:HI 0 "register_operand" "=r,r")
2989 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
2990 (clobber (reg:CC 17))]
2991 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
2993 [(set_attr "type" "imovx,alu1")
2994 (set_attr "mode" "HI")])
2996 (define_insn "*zero_extendqihi2_movzbw"
2997 [(set (match_operand:HI 0 "register_operand" "=r")
2998 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
2999 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3000 "movz{bw|x}\\t{%1, %0|%0, %1}"
3001 [(set_attr "type" "imovx")
3002 (set_attr "mode" "HI")])
3004 ;; For the movzbw case strip only the clobber
3006 [(set (match_operand:HI 0 "register_operand" "")
3007 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3008 (clobber (reg:CC 17))]
3010 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3011 && (!REG_P (operands[1]) || QI_REG_P (operands[1]))"
3012 [(set (match_operand:HI 0 "register_operand" "")
3013 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3015 ;; When source and destination does not overlap, clear destination
3016 ;; first and then do the movb
3018 [(set (match_operand:HI 0 "register_operand" "")
3019 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3020 (clobber (reg:CC 17))]
3022 && QI_REG_P (operands[0])
3023 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3024 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3025 [(set (match_dup 0) (const_int 0))
3026 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3027 "operands[2] = gen_lowpart (QImode, operands[0]);")
3029 ;; Rest is handled by single and.
3031 [(set (match_operand:HI 0 "register_operand" "")
3032 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3033 (clobber (reg:CC 17))]
3035 && true_regnum (operands[0]) == true_regnum (operands[1])"
3036 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3037 (clobber (reg:CC 17))])]
3040 (define_expand "zero_extendqisi2"
3042 [(set (match_operand:SI 0 "register_operand" "")
3043 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3044 (clobber (reg:CC 17))])]
3048 (define_insn "*zero_extendqisi2_and"
3049 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3050 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3051 (clobber (reg:CC 17))]
3052 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3054 [(set_attr "type" "alu1")
3055 (set_attr "mode" "SI")])
3057 (define_insn "*zero_extendqisi2_movzbw_and"
3058 [(set (match_operand:SI 0 "register_operand" "=r,r")
3059 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3060 (clobber (reg:CC 17))]
3061 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3063 [(set_attr "type" "imovx,alu1")
3064 (set_attr "mode" "SI")])
3066 (define_insn "*zero_extendqisi2_movzbw"
3067 [(set (match_operand:SI 0 "register_operand" "=r")
3068 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3069 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3070 "movz{bl|x}\\t{%1, %0|%0, %1}"
3071 [(set_attr "type" "imovx")
3072 (set_attr "mode" "SI")])
3074 ;; For the movzbl case strip only the clobber
3076 [(set (match_operand:SI 0 "register_operand" "")
3077 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3078 (clobber (reg:CC 17))]
3080 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3081 && (!REG_P (operands[1]) || QI_REG_P (operands[1]))"
3083 (zero_extend:SI (match_dup 1)))])
3085 ;; When source and destination does not overlap, clear destination
3086 ;; first and then do the movb
3088 [(set (match_operand:SI 0 "register_operand" "")
3089 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3090 (clobber (reg:CC 17))]
3092 && QI_REG_P (operands[0])
3093 && (QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3094 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3095 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3096 [(set (match_dup 0) (const_int 0))
3097 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3098 "operands[2] = gen_lowpart (QImode, operands[0]);")
3100 ;; Rest is handled by single and.
3102 [(set (match_operand:SI 0 "register_operand" "")
3103 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3104 (clobber (reg:CC 17))]
3106 && true_regnum (operands[0]) == true_regnum (operands[1])"
3107 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3108 (clobber (reg:CC 17))])]
3111 ;; %%% Kill me once multi-word ops are sane.
3112 (define_insn "zero_extendsidi2"
3113 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3114 (zero_extend:DI (match_operand:SI 1 "general_operand" "0,rm,r")))
3115 (clobber (reg:CC 17))]
3118 [(set_attr "mode" "SI")])
3121 [(set (match_operand:DI 0 "register_operand" "")
3122 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3123 (clobber (reg:CC 17))]
3124 "reload_completed && true_regnum (operands[0]) == true_regnum (operands[1])"
3125 [(set (match_dup 4) (const_int 0))]
3126 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3129 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3130 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3131 (clobber (reg:CC 17))]
3133 [(set (match_dup 3) (match_dup 1))
3134 (set (match_dup 4) (const_int 0))]
3135 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3137 ;; Sign extension instructions
3139 (define_insn "extendsidi2"
3140 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3141 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3142 (clobber (reg:CC 17))
3143 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3147 ;; Extend to memory case when source register does die.
3149 [(set (match_operand:DI 0 "memory_operand" "")
3150 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3151 (clobber (reg:CC 17))
3152 (clobber (match_operand:SI 2 "register_operand" ""))]
3154 && dead_or_set_p (insn, operands[1])
3155 && !reg_mentioned_p (operands[1], operands[0]))"
3156 [(set (match_dup 3) (match_dup 1))
3157 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3158 (clobber (reg:CC 17))])
3159 (set (match_dup 4) (match_dup 1))]
3160 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3162 ;; Extend to memory case when source register does not die.
3164 [(set (match_operand:DI 0 "memory_operand" "")
3165 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3166 (clobber (reg:CC 17))
3167 (clobber (match_operand:SI 2 "register_operand" ""))]
3172 split_di (&operands[0], 1, &operands[3], &operands[4]);
3174 emit_move_insn (operands[3], operands[1]);
3176 /* Generate a cltd if possible and doing so it profitable. */
3177 if (true_regnum (operands[1]) == 0
3178 && true_regnum (operands[2]) == 1
3179 && (optimize_size || TARGET_USE_CLTD))
3181 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3185 emit_move_insn (operands[2], operands[1]);
3186 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3188 emit_move_insn (operands[4], operands[2]);
3192 ;; Extend to register case. Optimize case where source and destination
3193 ;; registers match and cases where we can use cltd.
3195 [(set (match_operand:DI 0 "register_operand" "")
3196 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3197 (clobber (reg:CC 17))
3198 (clobber (match_scratch:SI 2 ""))]
3203 split_di (&operands[0], 1, &operands[3], &operands[4]);
3205 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3206 emit_move_insn (operands[3], operands[1]);
3208 /* Generate a cltd if possible and doing so it profitable. */
3209 if (true_regnum (operands[3]) == 0
3210 && (optimize_size || TARGET_USE_CLTD))
3212 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3216 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3217 emit_move_insn (operands[4], operands[1]);
3219 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3223 (define_insn "extendhisi2"
3224 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3225 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3229 switch (get_attr_prefix_0f (insn))
3232 return \"{cwtl|cwde}\";
3234 return \"movs{wl|x}\\t{%1,%0|%0, %1}\";
3237 [(set_attr "type" "imovx")
3238 (set_attr "mode" "SI")
3239 (set (attr "prefix_0f")
3240 ;; movsx is short decodable while cwtl is vector decoded.
3241 (if_then_else (and (eq_attr "cpu" "!k6")
3242 (eq_attr "alternative" "0"))
3244 (const_string "1")))
3246 (if_then_else (eq_attr "prefix_0f" "0")
3248 (const_string "1")))])
3250 (define_insn "extendqihi2"
3251 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3252 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3256 switch (get_attr_prefix_0f (insn))
3259 return \"{cbtw|cbw}\";
3261 return \"movs{bw|x}\\t{%1,%0|%0, %1}\";
3264 [(set_attr "type" "imovx")
3265 (set_attr "mode" "HI")
3266 (set (attr "prefix_0f")
3267 ;; movsx is short decodable while cwtl is vector decoded.
3268 (if_then_else (and (eq_attr "cpu" "!k6")
3269 (eq_attr "alternative" "0"))
3271 (const_string "1")))
3273 (if_then_else (eq_attr "prefix_0f" "0")
3275 (const_string "1")))])
3277 (define_insn "extendqisi2"
3278 [(set (match_operand:SI 0 "register_operand" "=r")
3279 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3281 "movs{bl|x}\\t{%1,%0|%0, %1}"
3282 [(set_attr "type" "imovx")
3283 (set_attr "mode" "SI")])
3285 ;; Conversions between float and double.
3287 ;; These are all no-ops in the model used for the 80387. So just
3290 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3291 (define_insn "*dummy_extendsfdf2"
3292 [(set (match_operand:DF 0 "push_operand" "=<")
3293 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3298 [(set (match_operand:DF 0 "push_operand" "")
3299 (float_extend:DF (match_operand:SF 1 "register_operand" "")))]
3300 "FP_REGNO_P (REGNO (operands[1]))"
3301 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3302 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3304 (define_insn "*dummy_extendsfxf2"
3305 [(set (match_operand:XF 0 "push_operand" "=<")
3306 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3311 [(set (match_operand:XF 0 "push_operand" "")
3312 (float_extend:XF (match_operand:SF 1 "register_operand" "")))]
3313 "FP_REGNO_P (REGNO (operands[1]))"
3314 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3315 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3317 (define_insn "*dummy_extendsftf2"
3318 [(set (match_operand:TF 0 "push_operand" "=<")
3319 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3324 [(set (match_operand:TF 0 "push_operand" "")
3325 (float_extend:TF (match_operand:SF 1 "register_operand" "")))]
3326 "FP_REGNO_P (REGNO (operands[1]))"
3327 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3328 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3330 (define_insn "*dummy_extenddfxf2"
3331 [(set (match_operand:XF 0 "push_operand" "=<")
3332 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3337 [(set (match_operand:XF 0 "push_operand" "")
3338 (float_extend:XF (match_operand:DF 1 "register_operand" "")))]
3339 "FP_REGNO_P (REGNO (operands[1]))"
3340 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3341 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3343 (define_insn "*dummy_extenddftf2"
3344 [(set (match_operand:TF 0 "push_operand" "=<")
3345 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3350 [(set (match_operand:TF 0 "push_operand" "")
3351 (float_extend:TF (match_operand:DF 1 "register_operand" "")))]
3352 "FP_REGNO_P (REGNO (operands[1]))"
3353 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3354 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3356 (define_expand "extendsfdf2"
3357 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3358 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3359 "TARGET_80387 || TARGET_SSE2"
3362 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3363 operands[1] = force_reg (SFmode, operands[1]);
3366 (define_insn "*extendsfdf2_1"
3367 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3368 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3369 "(TARGET_80387 || TARGET_SSE2)
3370 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3373 switch (which_alternative)
3376 if (REG_P (operands[1])
3377 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3378 return \"fstp\\t%y0\";
3379 else if (STACK_TOP_P (operands[0]))
3380 return \"fld%z1\\t%y1\";
3382 return \"fst\\t%y0\";
3385 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3386 return \"fstp%z0\\t%y0\";
3389 return \"fst%z0\\t%y0\";
3391 return \"cvtss2sd\\t{%1, %0|%0, %1}\";
3397 [(set_attr "type" "fmov,fmov,sse")
3398 (set_attr "mode" "SF,XF,DF")])
3400 (define_insn "*extendsfdf2_1_sse_only"
3401 [(set (match_operand:DF 0 "register_operand" "=Y")
3402 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3403 "!TARGET_80387 && TARGET_SSE2
3404 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3405 "cvtss2sd\\t{%1, %0|%0, %1}"
3406 [(set_attr "type" "sse")
3407 (set_attr "mode" "DF")])
3409 (define_expand "extendsfxf2"
3410 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3411 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "")))]
3415 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3416 operands[1] = force_reg (SFmode, operands[1]);
3419 (define_insn "*extendsfxf2_1"
3420 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3421 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3423 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3426 switch (which_alternative)
3429 if (REG_P (operands[1])
3430 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3431 return \"fstp\\t%y0\";
3432 else if (STACK_TOP_P (operands[0]))
3433 return \"fld%z1\\t%y1\";
3435 return \"fst\\t%y0\";
3438 /* There is no non-popping store to memory for XFmode. So if
3439 we need one, follow the store with a load. */
3440 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3441 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
3443 return \"fstp%z0\\t%y0\";
3449 [(set_attr "type" "fmov")
3450 (set_attr "mode" "SF,XF")])
3452 (define_expand "extendsftf2"
3453 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3454 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))]
3458 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3459 operands[1] = force_reg (SFmode, operands[1]);
3462 (define_insn "*extendsftf2_1"
3463 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3464 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3466 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3469 switch (which_alternative)
3472 if (REG_P (operands[1])
3473 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3474 return \"fstp\\t%y0\";
3475 else if (STACK_TOP_P (operands[0]))
3476 return \"fld%z1\\t%y1\";
3478 return \"fst\\t%y0\";
3481 /* There is no non-popping store to memory for XFmode. So if
3482 we need one, follow the store with a load. */
3483 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3484 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
3486 return \"fstp%z0\\t%y0\";
3492 [(set_attr "type" "fmov")
3493 (set_attr "mode" "SF,XF")])
3495 (define_expand "extenddfxf2"
3496 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3497 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "")))]
3501 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3502 operands[1] = force_reg (DFmode, operands[1]);
3505 (define_insn "*extenddfxf2_1"
3506 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3507 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3509 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3512 switch (which_alternative)
3515 if (REG_P (operands[1])
3516 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3517 return \"fstp\\t%y0\";
3518 else if (STACK_TOP_P (operands[0]))
3519 return \"fld%z1\\t%y1\";
3521 return \"fst\\t%y0\";
3524 /* There is no non-popping store to memory for XFmode. So if
3525 we need one, follow the store with a load. */
3526 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3527 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
3529 return \"fstp%z0\\t%y0\";
3535 [(set_attr "type" "fmov")
3536 (set_attr "mode" "DF,XF")])
3538 (define_expand "extenddftf2"
3539 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3540 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))]
3544 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3545 operands[1] = force_reg (DFmode, operands[1]);
3548 (define_insn "*extenddftf2_1"
3549 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3550 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3552 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3555 switch (which_alternative)
3558 if (REG_P (operands[1])
3559 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3560 return \"fstp\\t%y0\";
3561 else if (STACK_TOP_P (operands[0]))
3562 return \"fld%z1\\t%y1\";
3564 return \"fst\\t%y0\";
3567 /* There is no non-popping store to memory for XFmode. So if
3568 we need one, follow the store with a load. */
3569 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3570 return \"fstp%z0\\t%y0\\n\\tfld%z0\\t%y0\";
3572 return \"fstp%z0\\t%y0\";
3578 [(set_attr "type" "fmov")
3579 (set_attr "mode" "DF,XF")])
3581 ;; %%% This seems bad bad news.
3582 ;; This cannot output into an f-reg because there is no way to be sure
3583 ;; of truncating in that case. Otherwise this is just like a simple move
3584 ;; insn. So we pretend we can output to a reg in order to get better
3585 ;; register preferencing, but we really use a stack slot.
3587 (define_expand "truncdfsf2"
3588 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3590 (match_operand:DF 1 "register_operand" "")))
3591 (clobber (match_dup 2))])]
3592 "TARGET_80387 || TARGET_SSE2"
3595 operands[2] = assign_386_stack_local (SFmode, 0);
3598 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3603 (define_insn "*truncdfsf2_1"
3604 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f")
3606 (match_operand:DF 1 "register_operand" "f,0")))
3607 (clobber (match_operand:SF 2 "memory_operand" "=X,m"))]
3608 "TARGET_80387 && !TARGET_SSE2"
3611 switch (which_alternative)
3614 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3615 return \"fstp%z0\\t%y0\";
3617 return \"fst%z0\\t%y0\";
3619 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
3623 [(set_attr "type" "fmov,multi")
3624 (set_attr "mode" "SF,SF")])
3626 (define_insn "*truncdfsf2_1_sse"
3627 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f,Y")
3629 (match_operand:DF 1 "nonimmediate_operand" "f,0,mY")))
3630 (clobber (match_operand:SF 2 "memory_operand" "=X,m,X"))]
3631 "TARGET_80387 && TARGET_SSE2"
3634 switch (which_alternative)
3637 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3638 return \"fstp%z0\\t%y0\";
3640 return \"fst%z0\\t%y0\";
3642 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
3645 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
3649 [(set_attr "type" "fmov,multi,sse")
3650 (set_attr "mode" "SF,SF,DF")])
3652 (define_insn "*truncdfsf2_2"
3653 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
3655 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
3656 "TARGET_80387 && TARGET_SSE2
3657 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3660 switch (which_alternative)
3663 return \"cvtsd2ss\\t{%1, %0|%0, %1}\";
3665 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3666 return \"fstp%z0\\t%y0\";
3668 return \"fst%z0\\t%y0\";
3671 [(set_attr "type" "sse,fmov")
3672 (set_attr "mode" "DF,SF")])
3674 (define_insn "truncdfsf2_3"
3675 [(set (match_operand:SF 0 "nonimmediate_operand" "=m")
3677 (match_operand:DF 1 "register_operand" "f")))]
3681 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3682 return \"fstp%z0\\t%y0\";
3684 return \"fst%z0\\t%y0\";
3686 [(set_attr "type" "fmov")
3687 (set_attr "mode" "SF")])
3689 (define_insn "truncdfsf2_sse_only"
3690 [(set (match_operand:SF 0 "register_operand" "=Y")
3692 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
3693 "!TARGET_80387 && TARGET_SSE2"
3694 "cvtsd2ss\\t{%1, %0|%0, %1}"
3695 [(set_attr "type" "sse")
3696 (set_attr "mode" "DF")])
3699 [(set (match_operand:SF 0 "memory_operand" "")
3701 (match_operand:DF 1 "register_operand" "")))
3702 (clobber (match_operand:SF 2 "memory_operand" ""))]
3704 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3708 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3710 (match_operand:DF 1 "nonimmediate_operand" "")))
3711 (clobber (match_operand 2 "" ""))]
3712 "TARGET_80387 && !FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
3713 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3717 [(set (match_operand:SF 0 "register_operand" "")
3719 (match_operand:DF 1 "register_operand" "")))
3720 (clobber (match_operand:SF 2 "memory_operand" ""))]
3721 "TARGET_80387 && reload_completed
3722 && FP_REG_P (operands[0])"
3723 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3724 (set (match_dup 0) (match_dup 2))]
3727 (define_expand "truncxfsf2"
3728 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3730 (match_operand:XF 1 "register_operand" "")))
3731 (clobber (match_dup 2))])]
3733 "operands[2] = assign_386_stack_local (SFmode, 0);")
3735 (define_insn "*truncxfsf2_1"
3736 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,f")
3738 (match_operand:XF 1 "register_operand" "f,0")))
3739 (clobber (match_operand:SF 2 "memory_operand" "=m,m"))]
3743 switch (which_alternative)
3746 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3747 return \"fstp%z0\\t%y0\";
3749 return \"fst%z0\\t%y0\";
3751 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
3755 [(set_attr "type" "fmov,multi")
3756 (set_attr "mode" "SF")])
3758 (define_insn "*truncxfsf2_2"
3759 [(set (match_operand:SF 0 "memory_operand" "=m")
3761 (match_operand:XF 1 "register_operand" "f")))]
3765 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3766 return \"fstp%z0\\t%y0\";
3768 return \"fst%z0\\t%y0\";
3770 [(set_attr "type" "fmov")
3771 (set_attr "mode" "SF")])
3774 [(set (match_operand:SF 0 "memory_operand" "")
3776 (match_operand:XF 1 "register_operand" "")))
3777 (clobber (match_operand:SF 2 "memory_operand" ""))]
3779 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3783 [(set (match_operand:SF 0 "register_operand" "")
3785 (match_operand:XF 1 "register_operand" "")))
3786 (clobber (match_operand:SF 2 "memory_operand" ""))]
3787 "TARGET_80387 && reload_completed"
3788 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3789 (set (match_dup 0) (match_dup 2))]
3792 (define_expand "trunctfsf2"
3793 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3795 (match_operand:TF 1 "register_operand" "")))
3796 (clobber (match_dup 2))])]
3798 "operands[2] = assign_386_stack_local (SFmode, 0);")
3800 (define_insn "*trunctfsf2_1"
3801 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,f")
3803 (match_operand:TF 1 "register_operand" "f,0")))
3804 (clobber (match_operand:SF 2 "memory_operand" "=m,m"))]
3808 switch (which_alternative)
3811 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3812 return \"fstp%z0\\t%y0\";
3814 return \"fst%z0\\t%y0\";
3816 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
3820 [(set_attr "type" "fmov,multi")
3821 (set_attr "mode" "SF")])
3823 (define_insn "*truncxfsf2_2"
3824 [(set (match_operand:SF 0 "nonimmediate_operand" "=m")
3826 (match_operand:TF 1 "register_operand" "f")))]
3830 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3831 return \"fstp%z0\\t%y0\";
3833 return \"fst%z0\\t%y0\";
3835 [(set_attr "type" "fmov")
3836 (set_attr "mode" "SF")])
3839 [(set (match_operand:SF 0 "memory_operand" "")
3841 (match_operand:TF 1 "register_operand" "")))
3842 (clobber (match_operand:SF 2 "memory_operand" ""))]
3844 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
3848 [(set (match_operand:SF 0 "register_operand" "")
3850 (match_operand:TF 1 "register_operand" "")))
3851 (clobber (match_operand:SF 2 "memory_operand" ""))]
3852 "TARGET_80387 && reload_completed"
3853 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
3854 (set (match_dup 0) (match_dup 2))]
3858 (define_expand "truncxfdf2"
3859 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3861 (match_operand:XF 1 "register_operand" "")))
3862 (clobber (match_dup 2))])]
3864 "operands[2] = assign_386_stack_local (DFmode, 0);")
3866 (define_insn "*truncxfdf2_1"
3867 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,f")
3869 (match_operand:XF 1 "register_operand" "f,0")))
3870 (clobber (match_operand:DF 2 "memory_operand" "=m,m"))]
3874 switch (which_alternative)
3877 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3878 return \"fstp%z0\\t%y0\";
3880 return \"fst%z0\\t%y0\";
3882 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
3886 [(set_attr "type" "fmov,multi")
3887 (set_attr "mode" "DF")])
3889 (define_insn "*truncxfdf2_2"
3890 [(set (match_operand:DF 0 "memory_operand" "=m")
3892 (match_operand:XF 1 "register_operand" "f")))]
3896 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3897 return \"fstp%z0\\t%y0\";
3899 return \"fst%z0\\t%y0\";
3901 [(set_attr "type" "fmov")
3902 (set_attr "mode" "DF")])
3905 [(set (match_operand:DF 0 "memory_operand" "")
3907 (match_operand:XF 1 "register_operand" "")))
3908 (clobber (match_operand:DF 2 "memory_operand" ""))]
3910 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
3914 [(set (match_operand:DF 0 "register_operand" "")
3916 (match_operand:XF 1 "register_operand" "")))
3917 (clobber (match_operand:DF 2 "memory_operand" ""))]
3918 "TARGET_80387 && reload_completed"
3919 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
3920 (set (match_dup 0) (match_dup 2))]
3923 (define_expand "trunctfdf2"
3924 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
3926 (match_operand:TF 1 "register_operand" "")))
3927 (clobber (match_dup 2))])]
3929 "operands[2] = assign_386_stack_local (DFmode, 0);")
3931 (define_insn "*trunctfdf2_1"
3932 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,f")
3934 (match_operand:TF 1 "register_operand" "f,0")))
3935 (clobber (match_operand:DF 2 "memory_operand" "=m,m"))]
3939 switch (which_alternative)
3942 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3943 return \"fstp%z0\\t%y0\";
3945 return \"fst%z0\\t%y0\";
3947 return \"fstp%z2\\t%y2\;fld%z2\\t%y2\";
3951 [(set_attr "type" "fmov,multi")
3952 (set_attr "mode" "DF")])
3954 (define_insn "*truncxfdf2_2"
3955 [(set (match_operand:DF 0 "memory_operand" "=m")
3957 (match_operand:TF 1 "register_operand" "f")))]
3961 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3962 return \"fstp%z0\\t%y0\";
3964 return \"fst%z0\\t%y0\";
3966 [(set_attr "type" "fmov")
3967 (set_attr "mode" "DF")])
3970 [(set (match_operand:DF 0 "memory_operand" "")
3972 (match_operand:TF 1 "register_operand" "")))
3973 (clobber (match_operand:DF 2 "memory_operand" ""))]
3975 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
3979 [(set (match_operand:DF 0 "register_operand" "")
3981 (match_operand:TF 1 "register_operand" "")))
3982 (clobber (match_operand:DF 2 "memory_operand" ""))]
3983 "TARGET_80387 && reload_completed"
3984 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
3985 (set (match_dup 0) (match_dup 2))]
3989 ;; %%% Break up all these bad boys.
3991 ;; Signed conversion to DImode.
3993 (define_expand "fix_truncxfdi2"
3994 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
3995 (fix:DI (match_operand:XF 1 "register_operand" "")))
3996 (clobber (match_dup 2))
3997 (clobber (match_dup 3))
3998 (clobber (match_scratch:SI 4 ""))
3999 (clobber (match_scratch:XF 5 ""))])]
4001 "operands[2] = assign_386_stack_local (SImode, 0);
4002 operands[3] = assign_386_stack_local (DImode, 1);")
4004 (define_expand "fix_trunctfdi2"
4005 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4006 (fix:DI (match_operand:TF 1 "register_operand" "")))
4007 (clobber (match_dup 2))
4008 (clobber (match_dup 3))
4009 (clobber (match_scratch:SI 4 ""))
4010 (clobber (match_scratch:TF 5 ""))])]
4012 "operands[2] = assign_386_stack_local (SImode, 0);
4013 operands[3] = assign_386_stack_local (DImode, 1);")
4015 (define_expand "fix_truncdfdi2"
4016 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4017 (fix:DI (match_operand:DF 1 "register_operand" "")))
4018 (clobber (match_dup 2))
4019 (clobber (match_dup 3))
4020 (clobber (match_scratch:SI 4 ""))
4021 (clobber (match_scratch:DF 5 ""))])]
4023 "operands[2] = assign_386_stack_local (SImode, 0);
4024 operands[3] = assign_386_stack_local (DImode, 1);")
4026 (define_expand "fix_truncsfdi2"
4027 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
4028 (fix:DI (match_operand:SF 1 "register_operand" "")))
4029 (clobber (match_dup 2))
4030 (clobber (match_dup 3))
4031 (clobber (match_scratch:SI 4 ""))
4032 (clobber (match_scratch:SF 5 ""))])]
4034 "operands[2] = assign_386_stack_local (SImode, 0);
4035 operands[3] = assign_386_stack_local (DImode, 1);")
4037 (define_insn "*fix_truncdi_1"
4038 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4039 (fix:DI (match_operand 1 "register_operand" "f,f")))
4040 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4041 (clobber (match_operand:DI 3 "memory_operand" "=m,m"))
4042 (clobber (match_scratch:SI 4 "=&r,&r"))
4043 (clobber (match_scratch 5 "=&f,&f"))]
4044 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))"
4045 "* return output_fix_trunc (insn, operands);"
4046 [(set_attr "type" "multi")])
4049 [(set (match_operand:DI 0 "register_operand" "")
4050 (fix:DI (match_operand 1 "register_operand" "")))
4051 (clobber (match_operand:SI 2 "memory_operand" ""))
4052 (clobber (match_operand:DI 3 "memory_operand" ""))
4053 (clobber (match_scratch:SI 4 ""))
4054 (clobber (match_scratch 5 ""))]
4055 "reload_completed && !reg_overlap_mentioned_p (operands[4], operands[3])"
4056 [(parallel [(set (match_dup 3) (fix:DI (match_dup 1)))
4057 (clobber (match_dup 2))
4058 (clobber (match_dup 3))
4059 (clobber (match_dup 4))
4060 (clobber (match_dup 5))])
4061 (set (match_dup 0) (match_dup 3))]
4064 ;; Signed conversion to SImode.
4066 (define_expand "fix_truncxfsi2"
4067 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4068 (fix:SI (match_operand:XF 1 "register_operand" "")))
4069 (clobber (match_dup 2))
4070 (clobber (match_dup 3))
4071 (clobber (match_scratch:SI 4 ""))])]
4073 "operands[2] = assign_386_stack_local (SImode, 0);
4074 operands[3] = assign_386_stack_local (SImode, 1);")
4076 (define_expand "fix_trunctfsi2"
4077 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4078 (fix:SI (match_operand:TF 1 "register_operand" "")))
4079 (clobber (match_dup 2))
4080 (clobber (match_dup 3))
4081 (clobber (match_scratch:SI 4 ""))])]
4083 "operands[2] = assign_386_stack_local (SImode, 0);
4084 operands[3] = assign_386_stack_local (SImode, 1);")
4086 (define_expand "fix_truncdfsi2"
4087 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4088 (fix:SI (match_operand:DF 1 "register_operand" "")))
4089 (clobber (match_dup 2))
4090 (clobber (match_dup 3))
4091 (clobber (match_scratch:SI 4 ""))])]
4092 "TARGET_80387 || TARGET_SSE2"
4097 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4098 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4099 if (out != operands[0])
4100 emit_move_insn (operands[0], out);
4105 operands[2] = assign_386_stack_local (SImode, 0);
4106 operands[3] = assign_386_stack_local (SImode, 1);
4110 (define_expand "fix_truncsfsi2"
4111 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4112 (fix:SI (match_operand:SF 1 "register_operand" "")))
4113 (clobber (match_dup 2))
4114 (clobber (match_dup 3))
4115 (clobber (match_scratch:SI 4 ""))])]
4116 "TARGET_80387 || TARGET_SSE"
4121 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4122 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4123 if (out != operands[0])
4124 emit_move_insn (operands[0], out);
4129 operands[2] = assign_386_stack_local (SImode, 0);
4130 operands[3] = assign_386_stack_local (SImode, 1);
4134 (define_insn "*fix_truncsi_1"
4135 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4136 (fix:SI (match_operand 1 "register_operand" "f,f")))
4137 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4138 (clobber (match_operand:SI 3 "memory_operand" "=m,m"))
4139 (clobber (match_scratch:SI 4 "=&r,r"))]
4140 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4141 && (!TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4142 "* return output_fix_trunc (insn, operands);"
4143 [(set_attr "type" "multi")])
4145 ;; When SSE available, it is always faster to use it!
4146 (define_insn "fix_truncsfsi_sse"
4147 [(set (match_operand:SI 0 "register_operand" "=r")
4148 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
4150 "cvttss2si\\t{%1, %0|%0, %1}"
4151 [(set_attr "type" "sse")])
4153 (define_insn "fix_truncdfsi_sse"
4154 [(set (match_operand:SI 0 "register_operand" "=r")
4155 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
4157 "cvttsd2si\\t{%1, %0|%0, %1}"
4158 [(set_attr "type" "sse")])
4161 [(set (match_operand:SI 0 "register_operand" "")
4162 (fix:SI (match_operand 1 "register_operand" "")))
4163 (clobber (match_operand:SI 2 "memory_operand" ""))
4164 (clobber (match_operand:SI 3 "memory_operand" ""))
4165 (clobber (match_scratch:SI 4 ""))]
4167 [(parallel [(set (match_dup 3) (fix:SI (match_dup 1)))
4168 (clobber (match_dup 2))
4169 (clobber (match_dup 3))
4170 (clobber (match_dup 4))])
4171 (set (match_dup 0) (match_dup 3))]
4174 ;; Signed conversion to HImode.
4176 (define_expand "fix_truncxfhi2"
4177 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4178 (fix:HI (match_operand:XF 1 "register_operand" "")))
4179 (clobber (match_dup 2))
4180 (clobber (match_dup 3))
4181 (clobber (match_scratch:SI 4 ""))])]
4183 "operands[2] = assign_386_stack_local (SImode, 0);
4184 operands[3] = assign_386_stack_local (HImode, 1);")
4186 (define_expand "fix_trunctfhi2"
4187 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4188 (fix:HI (match_operand:TF 1 "register_operand" "")))
4189 (clobber (match_dup 2))
4190 (clobber (match_dup 3))
4191 (clobber (match_scratch:SI 4 ""))])]
4193 "operands[2] = assign_386_stack_local (SImode, 0);
4194 operands[3] = assign_386_stack_local (HImode, 1);")
4196 (define_expand "fix_truncdfhi2"
4197 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4198 (fix:HI (match_operand:DF 1 "register_operand" "")))
4199 (clobber (match_dup 2))
4200 (clobber (match_dup 3))
4201 (clobber (match_scratch:SI 4 ""))])]
4202 "TARGET_80387 && !TARGET_SSE2"
4203 "operands[2] = assign_386_stack_local (SImode, 0);
4204 operands[3] = assign_386_stack_local (HImode, 1);")
4206 (define_expand "fix_truncsfhi2"
4207 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4208 (fix:HI (match_operand:SF 1 "register_operand" "")))
4209 (clobber (match_dup 2))
4210 (clobber (match_dup 3))
4211 (clobber (match_scratch:SI 4 ""))])]
4212 "TARGET_80387 && !TARGET_SSE"
4213 "operands[2] = assign_386_stack_local (SImode, 0);
4214 operands[3] = assign_386_stack_local (HImode, 1);")
4216 (define_insn "*fix_trunchi_1"
4217 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4218 (fix:HI (match_operand 1 "register_operand" "f,f")))
4219 (clobber (match_operand:SI 2 "memory_operand" "=o,o"))
4220 (clobber (match_operand:HI 3 "memory_operand" "=m,m"))
4221 (clobber (match_scratch:SI 4 "=&r,r"))]
4222 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4223 && (TARGET_SSE2 || !SSE_FLOAT_MODE_P (GET_MODE (operands[1])))"
4224 "* return output_fix_trunc (insn, operands);"
4225 [(set_attr "type" "multi")])
4228 [(set (match_operand:HI 0 "register_operand" "")
4229 (fix:HI (match_operand 1 "register_operand" "")))
4230 (clobber (match_operand:SI 2 "memory_operand" ""))
4231 (clobber (match_operand:HI 3 "memory_operand" ""))
4232 (clobber (match_scratch:SI 4 ""))]
4234 [(parallel [(set (match_dup 3) (fix:HI (match_dup 1)))
4235 (clobber (match_dup 2))
4236 (clobber (match_dup 3))
4237 (clobber (match_dup 4))])
4238 (set (match_dup 0) (match_dup 3))]
4241 ;; %%% Kill these when reload knows how to do it.
4243 [(set (match_operand 0 "register_operand" "")
4244 (fix (match_operand 1 "register_operand" "")))]
4245 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[1]))
4246 && FP_REG_P (operands[1])"
4250 operands[2] = ix86_force_to_memory (GET_MODE (operands[0]), operands[0]);
4251 operands[2] = gen_rtx_FIX (GET_MODE (operands[2]), operands[1]);
4252 emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1]));
4253 emit_move_insn (operands[0], operands[2]);
4254 ix86_free_from_memory (GET_MODE (operands[0]));
4259 (define_insn "x86_fnstcw_1"
4260 [(set (match_operand:HI 0 "memory_operand" "=m")
4261 (unspec:HI [(reg:HI 18)] 11))]
4264 [(set_attr "length" "2")
4265 (set_attr "mode" "HI")
4266 (set_attr "i387" "1")
4267 (set_attr "ppro_uops" "few")])
4269 (define_insn "x86_fldcw_1"
4271 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
4274 [(set_attr "length" "2")
4275 (set_attr "mode" "HI")
4276 (set_attr "i387" "1")
4277 (set_attr "athlon_decode" "vector")
4278 (set_attr "ppro_uops" "few")])
4280 ;; Conversion between fixed point and floating point.
4282 ;; Even though we only accept memory inputs, the backend _really_
4283 ;; wants to be able to do this between registers.
4285 (define_insn "floathisf2"
4286 [(set (match_operand:SF 0 "register_operand" "=f,f")
4287 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4288 "TARGET_80387 && !TARGET_SSE"
4292 [(set_attr "type" "fmov,multi")
4293 (set_attr "mode" "SF")
4294 (set_attr "fp_int_src" "true")])
4296 (define_expand "floatsisf2"
4297 [(set (match_operand:SF 0 "register_operand" "")
4298 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4299 "TARGET_SSE || TARGET_80387"
4302 (define_insn "*floatsisf2_i387"
4303 [(set (match_operand:SF 0 "register_operand" "=f,?f,x")
4304 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4305 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4309 cvtsi2ss\\t{%1, %0|%0, %1}"
4310 [(set_attr "type" "fmov,multi,sse")
4311 (set_attr "mode" "SF")
4312 (set_attr "fp_int_src" "true")])
4314 (define_insn "*floatsisf2_sse"
4315 [(set (match_operand:SF 0 "register_operand" "=x")
4316 (float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4317 "TARGET_80387 && TARGET_SSE"
4318 "cvtsi2ss\\t{%1, %0|%0, %1}"
4319 [(set_attr "type" "sse")
4320 (set_attr "mode" "SF")
4321 (set_attr "fp_int_src" "true")])
4323 (define_insn "floatdisf2"
4324 [(set (match_operand:SF 0 "register_operand" "=f,f")
4325 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4330 [(set_attr "type" "fmov,multi")
4331 (set_attr "mode" "SF")
4332 (set_attr "fp_int_src" "true")])
4334 (define_insn "floathidf2"
4335 [(set (match_operand:DF 0 "register_operand" "=f,f")
4336 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4337 "TARGET_80387 && !TARGET_SSE2"
4341 [(set_attr "type" "fmov,multi")
4342 (set_attr "mode" "DF")
4343 (set_attr "fp_int_src" "true")])
4345 (define_expand "floatsidf2"
4346 [(set (match_operand:DF 0 "register_operand" "")
4347 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4351 (define_insn "*floatsidf2_i387"
4352 [(set (match_operand:DF 0 "register_operand" "=f,?f,Y")
4353 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,mr")))]
4354 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
4358 cvtsi2sd\\t{%1, %0|%0, %1}"
4359 [(set_attr "type" "fmov,multi,sse")
4360 (set_attr "mode" "DF")
4361 (set_attr "fp_int_src" "true")])
4363 (define_insn "*floatsidf2_sse"
4364 [(set (match_operand:DF 0 "register_operand" "=Y")
4365 (float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
4367 "cvtsi2sd\\t{%1, %0|%0, %1}"
4368 [(set_attr "type" "sse")
4369 (set_attr "mode" "DF")
4370 (set_attr "fp_int_src" "true")])
4372 (define_insn "floatdidf2"
4373 [(set (match_operand:DF 0 "register_operand" "=f,f")
4374 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4375 "TARGET_80387 && TARGET_SSE2"
4379 [(set_attr "type" "fmov,multi")
4380 (set_attr "mode" "DF")
4381 (set_attr "fp_int_src" "true")])
4383 (define_insn "floathixf2"
4384 [(set (match_operand:XF 0 "register_operand" "=f,f")
4385 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4390 [(set_attr "type" "fmov,multi")
4391 (set_attr "mode" "XF")
4392 (set_attr "fp_int_src" "true")])
4394 (define_insn "floathitf2"
4395 [(set (match_operand:TF 0 "register_operand" "=f,f")
4396 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4401 [(set_attr "type" "fmov,multi")
4402 (set_attr "mode" "XF")
4403 (set_attr "fp_int_src" "true")])
4405 (define_insn "floatsixf2"
4406 [(set (match_operand:XF 0 "register_operand" "=f,f")
4407 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4412 [(set_attr "type" "fmov,multi")
4413 (set_attr "mode" "XF")
4414 (set_attr "fp_int_src" "true")])
4416 (define_insn "floatsitf2"
4417 [(set (match_operand:TF 0 "register_operand" "=f,f")
4418 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
4423 [(set_attr "type" "fmov,multi")
4424 (set_attr "mode" "XF")
4425 (set_attr "fp_int_src" "true")])
4427 (define_insn "floatdixf2"
4428 [(set (match_operand:XF 0 "register_operand" "=f,f")
4429 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4434 [(set_attr "type" "fmov,multi")
4435 (set_attr "mode" "XF")
4436 (set_attr "fp_int_src" "true")])
4438 (define_insn "floatditf2"
4439 [(set (match_operand:TF 0 "register_operand" "=f,f")
4440 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4445 [(set_attr "type" "fmov,multi")
4446 (set_attr "mode" "XF")
4447 (set_attr "fp_int_src" "true")])
4449 ;; %%% Kill these when reload knows how to do it.
4451 [(set (match_operand 0 "register_operand" "")
4452 (float (match_operand 1 "register_operand" "")))]
4453 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
4457 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
4458 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
4459 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
4460 ix86_free_from_memory (GET_MODE (operands[1]));
4466 ;; %%% define_expand from the very first?
4467 ;; %%% splits for addsidi3
4468 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
4469 ; (plus:DI (match_operand:DI 1 "general_operand" "")
4470 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
4472 (define_insn "adddi3"
4473 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
4474 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4475 (match_operand:DI 2 "general_operand" "roiF,riF")))
4476 (clobber (reg:CC 17))]
4481 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4482 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
4483 (match_operand:DI 2 "general_operand" "")))
4484 (clobber (reg:CC 17))]
4486 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)] 12))
4487 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
4488 (parallel [(set (match_dup 3)
4489 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4492 (clobber (reg:CC 17))])]
4493 "split_di (operands+0, 1, operands+0, operands+3);
4494 split_di (operands+1, 1, operands+1, operands+4);
4495 split_di (operands+2, 1, operands+2, operands+5);")
4497 (define_insn "*addsi3_carry"
4498 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4499 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
4500 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
4501 (match_operand:SI 2 "general_operand" "ri,rm")))
4502 (clobber (reg:CC 17))]
4503 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4504 "adc{l}\\t{%2, %0|%0, %2}"
4505 [(set_attr "type" "alu")
4506 (set_attr "pent_pair" "pu")
4507 (set_attr "mode" "SI")
4508 (set_attr "ppro_uops" "few")])
4510 (define_insn "*addsi3_cc"
4511 [(set (reg:CC 17) (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
4512 (match_operand:SI 2 "general_operand" "ri,rm")] 12))
4513 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
4514 (plus:SI (match_dup 1) (match_dup 2)))]
4515 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4516 "add{l}\\t{%2, %0|%0, %2}"
4517 [(set_attr "type" "alu")
4518 (set_attr "mode" "SI")])
4520 (define_insn "addqi3_cc"
4521 [(set (reg:CC 17) (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
4522 (match_operand:QI 2 "general_operand" "qi,qm")] 12))
4523 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
4524 (plus:QI (match_dup 1) (match_dup 2)))]
4525 "ix86_binary_operator_ok (PLUS, QImode, operands)"
4526 "add{b}\\t{%2, %0|%0, %2}"
4527 [(set_attr "type" "alu")
4528 (set_attr "mode" "QI")])
4530 (define_expand "addsi3"
4531 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
4532 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
4533 (match_operand:SI 2 "general_operand" "")))
4534 (clobber (reg:CC 17))])]
4536 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
4538 (define_insn "*lea_0"
4539 [(set (match_operand:SI 0 "register_operand" "=r")
4540 (match_operand:SI 1 "address_operand" "p"))]
4542 "lea{l}\\t{%a1, %0|%0, %a1}"
4543 [(set_attr "type" "lea")
4544 (set_attr "mode" "SI")])
4546 ;; The lea patterns for non-Pmodes needs to be matched by several
4547 ;; insns converted to real lea by splitters.
4549 (define_insn_and_split "*lea_general_1"
4550 [(set (match_operand 0 "register_operand" "=r")
4551 (plus (plus (match_operand 1 "register_operand" "r")
4552 (match_operand 2 "register_operand" "r"))
4553 (match_operand 3 "immediate_operand" "i")))]
4554 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
4555 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4556 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4557 && GET_MODE (operands[0]) == GET_MODE (operands[2])
4558 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
4559 || GET_MODE (operands[3]) == VOIDmode)"
4561 "&& reload_completed"
4566 operands[0] = gen_lowpart (SImode, operands[0]);
4567 operands[1] = gen_lowpart (Pmode, operands[1]);
4568 operands[2] = gen_lowpart (Pmode, operands[2]);
4569 operands[3] = gen_lowpart (Pmode, operands[3]);
4570 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
4572 if (Pmode != SImode)
4573 pat = gen_rtx_SUBREG (SImode, pat, 0);
4574 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4577 [(set_attr "type" "lea")
4578 (set_attr "mode" "SI")])
4580 (define_insn_and_split "*lea_general_2"
4581 [(set (match_operand 0 "register_operand" "=r")
4582 (plus (mult (match_operand 1 "register_operand" "r")
4583 (match_operand 2 "const248_operand" "i"))
4584 (match_operand 3 "nonmemory_operand" "ri")))]
4585 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
4586 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4587 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4588 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
4589 || GET_MODE (operands[3]) == VOIDmode)"
4591 "&& reload_completed"
4596 operands[0] = gen_lowpart (SImode, operands[0]);
4597 operands[1] = gen_lowpart (Pmode, operands[1]);
4598 operands[3] = gen_lowpart (Pmode, operands[3]);
4599 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
4601 if (Pmode != SImode)
4602 pat = gen_rtx_SUBREG (SImode, pat, 0);
4603 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4606 [(set_attr "type" "lea")
4607 (set_attr "mode" "SI")])
4609 (define_insn_and_split "*lea_general_3"
4610 [(set (match_operand 0 "register_operand" "=r")
4611 (plus (plus (mult (match_operand 1 "register_operand" "r")
4612 (match_operand 2 "const248_operand" "i"))
4613 (match_operand 3 "register_operand" "r"))
4614 (match_operand 4 "immediate_operand" "i")))]
4615 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode)
4616 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
4617 && GET_MODE (operands[0]) == GET_MODE (operands[1])
4618 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
4620 "&& reload_completed"
4625 operands[0] = gen_lowpart (SImode, operands[0]);
4626 operands[1] = gen_lowpart (Pmode, operands[1]);
4627 operands[3] = gen_lowpart (Pmode, operands[3]);
4628 operands[4] = gen_lowpart (Pmode, operands[4]);
4629 pat = gen_rtx_PLUS (Pmode,
4630 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
4634 if (Pmode != SImode)
4635 pat = gen_rtx_SUBREG (SImode, pat, 0);
4636 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4639 [(set_attr "type" "lea")
4640 (set_attr "mode" "SI")])
4642 (define_insn "*addsi_1"
4643 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
4644 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
4645 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
4646 (clobber (reg:CC 17))]
4647 "ix86_binary_operator_ok (PLUS, SImode, operands)"
4650 switch (get_attr_type (insn))
4653 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
4654 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
4657 if (! rtx_equal_p (operands[0], operands[1]))
4659 if (operands[2] == const1_rtx)
4660 return \"inc{l}\\t%0\";
4661 else if (operands[2] == constm1_rtx)
4662 return \"dec{l}\\t%0\";
4667 if (! rtx_equal_p (operands[0], operands[1]))
4670 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
4671 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
4672 if (GET_CODE (operands[2]) == CONST_INT
4673 && (INTVAL (operands[2]) == 128
4674 || (INTVAL (operands[2]) < 0
4675 && INTVAL (operands[2]) != -128)))
4677 operands[2] = GEN_INT (-INTVAL (operands[2]));
4678 return \"sub{l}\\t{%2, %0|%0, %2}\";
4680 return \"add{l}\\t{%2, %0|%0, %2}\";
4684 (cond [(eq_attr "alternative" "2")
4685 (const_string "lea")
4686 ; Current assemblers are broken and do not allow @GOTOFF in
4687 ; ought but a memory context.
4688 (match_operand:SI 2 "pic_symbolic_operand" "")
4689 (const_string "lea")
4690 (match_operand:SI 2 "incdec_operand" "")
4691 (const_string "incdec")
4693 (const_string "alu")))
4694 (set_attr "mode" "SI")])
4696 ;; Convert lea to the lea pattern to avoid flags dependency.
4698 [(set (match_operand 0 "register_operand" "")
4699 (plus (match_operand 1 "register_operand" "")
4700 (match_operand 2 "nonmemory_operand" "")))
4701 (clobber (reg:CC 17))]
4703 && true_regnum (operands[0]) != true_regnum (operands[1])"
4708 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
4709 may confuse gen_lowpart. */
4710 if (GET_MODE (operands[0]) != Pmode)
4712 operands[1] = gen_lowpart (Pmode, operands[1]);
4713 operands[2] = gen_lowpart (Pmode, operands[2]);
4715 operands[0] = gen_lowpart (SImode, operands[0]);
4716 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
4717 if (Pmode != SImode)
4718 pat = gen_rtx_SUBREG (SImode, pat, 0);
4719 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
4723 (define_insn "*addsi_2"
4726 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4727 (match_operand:SI 2 "general_operand" "rmni,rni"))
4729 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
4730 (plus:SI (match_dup 1) (match_dup 2)))]
4731 "ix86_match_ccmode (insn, CCGOCmode)
4732 && ix86_binary_operator_ok (PLUS, SImode, operands)
4733 /* Current assemblers are broken and do not allow @GOTOFF in
4734 ought but a memory context. */
4735 && ! pic_symbolic_operand (operands[2], VOIDmode)"
4738 switch (get_attr_type (insn))
4741 if (! rtx_equal_p (operands[0], operands[1]))
4743 if (operands[2] == const1_rtx)
4744 return \"inc{l}\\t%0\";
4745 else if (operands[2] == constm1_rtx)
4746 return \"dec{l}\\t%0\";
4751 if (! rtx_equal_p (operands[0], operands[1]))
4753 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
4754 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
4755 if (GET_CODE (operands[2]) == CONST_INT
4756 && (INTVAL (operands[2]) == 128
4757 || (INTVAL (operands[2]) < 0
4758 && INTVAL (operands[2]) != -128)))
4760 operands[2] = GEN_INT (-INTVAL (operands[2]));
4761 return \"sub{l}\\t{%2, %0|%0, %2}\";
4763 return \"add{l}\\t{%2, %0|%0, %2}\";
4767 (if_then_else (match_operand:SI 2 "incdec_operand" "")
4768 (const_string "incdec")
4769 (const_string "alu")))
4770 (set_attr "mode" "SI")])
4772 (define_insn "*addsi_3"
4774 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
4775 (match_operand:SI 1 "nonimmediate_operand" "%0")))
4776 (clobber (match_scratch:SI 0 "=r"))]
4777 "ix86_match_ccmode (insn, CCZmode)
4778 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
4779 /* Current assemblers are broken and do not allow @GOTOFF in
4780 ought but a memory context. */
4781 && ! pic_symbolic_operand (operands[2], VOIDmode)"
4784 switch (get_attr_type (insn))
4787 if (! rtx_equal_p (operands[0], operands[1]))
4789 if (operands[2] == const1_rtx)
4790 return \"inc{l}\\t%0\";
4791 else if (operands[2] == constm1_rtx)
4792 return \"dec{l}\\t%0\";
4797 if (! rtx_equal_p (operands[0], operands[1]))
4799 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
4800 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
4801 if (GET_CODE (operands[2]) == CONST_INT
4802 && (INTVAL (operands[2]) == 128
4803 || (INTVAL (operands[2]) < 0
4804 && INTVAL (operands[2]) != -128)))
4806 operands[2] = GEN_INT (-INTVAL (operands[2]));
4807 return \"sub{l}\\t{%2, %0|%0, %2}\";
4809 return \"add{l}\\t{%2, %0|%0, %2}\";
4813 (if_then_else (match_operand:SI 2 "incdec_operand" "")
4814 (const_string "incdec")
4815 (const_string "alu")))
4816 (set_attr "mode" "SI")])
4818 ; For comparisons agains 1, -1 and 128, we may generate better code
4819 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
4820 ; is matched then. We can't accept general immediate, because for
4821 ; case of overflows, the result is messed up.
4822 ; This pattern also don't hold of 0x80000000, since the value overflows
4824 ; Also carry flag is reversed compared to cmp, so this converison is valid
4825 ; only for comparisons not depending on it.
4826 (define_insn "*addsi_4"
4828 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
4829 (match_operand:SI 2 "const_int_operand" "n")))
4830 (clobber (match_scratch:SI 0 "=rm"))]
4831 "ix86_match_ccmode (insn, CCGCmode)
4832 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
4835 switch (get_attr_type (insn))
4838 if (operands[2] == constm1_rtx)
4839 return \"inc{l}\\t%0\";
4840 else if (operands[2] == const1_rtx)
4841 return \"dec{l}\\t%0\";
4846 if (! rtx_equal_p (operands[0], operands[1]))
4848 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
4849 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
4850 if ((INTVAL (operands[2]) == -128
4851 || (INTVAL (operands[2]) > 0
4852 && INTVAL (operands[2]) != 128)))
4853 return \"sub{l}\\t{%2, %0|%0, %2}\";
4854 operands[2] = GEN_INT (-INTVAL (operands[2]));
4855 return \"add{l}\\t{%2, %0|%0, %2}\";
4859 (if_then_else (match_operand:SI 2 "incdec_operand" "")
4860 (const_string "incdec")
4861 (const_string "alu")))
4862 (set_attr "mode" "SI")])
4864 (define_insn "*addsi_5"
4867 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
4868 (match_operand:SI 2 "general_operand" "rmni"))
4870 (clobber (match_scratch:SI 0 "=r"))]
4871 "ix86_match_ccmode (insn, CCGOCmode)
4872 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
4873 /* Current assemblers are broken and do not allow @GOTOFF in
4874 ought but a memory context. */
4875 && ! pic_symbolic_operand (operands[2], VOIDmode)"
4878 switch (get_attr_type (insn))
4881 if (! rtx_equal_p (operands[0], operands[1]))
4883 if (operands[2] == const1_rtx)
4884 return \"inc{l}\\t%0\";
4885 else if (operands[2] == constm1_rtx)
4886 return \"dec{l}\\t%0\";
4891 if (! rtx_equal_p (operands[0], operands[1]))
4893 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
4894 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
4895 if (GET_CODE (operands[2]) == CONST_INT
4896 && (INTVAL (operands[2]) == 128
4897 || (INTVAL (operands[2]) < 0
4898 && INTVAL (operands[2]) != -128)))
4900 operands[2] = GEN_INT (-INTVAL (operands[2]));
4901 return \"sub{l}\\t{%2, %0|%0, %2}\";
4903 return \"add{l}\\t{%2, %0|%0, %2}\";
4907 (if_then_else (match_operand:SI 2 "incdec_operand" "")
4908 (const_string "incdec")
4909 (const_string "alu")))
4910 (set_attr "mode" "SI")])
4912 (define_expand "addhi3"
4913 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
4914 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
4915 (match_operand:HI 2 "general_operand" "")))
4916 (clobber (reg:CC 17))])]
4917 "TARGET_HIMODE_MATH"
4918 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
4920 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
4921 ;; type optimizations enabled by define-splits. This is not important
4922 ;; for PII, and in fact harmful because of partial register stalls.
4924 (define_insn "*addhi_1_lea"
4925 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
4926 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
4927 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
4928 (clobber (reg:CC 17))]
4929 "!TARGET_PARTIAL_REG_STALL
4930 && ix86_binary_operator_ok (PLUS, HImode, operands)"
4933 switch (get_attr_type (insn))
4938 if (operands[2] == const1_rtx)
4939 return \"inc{w}\\t%0\";
4940 else if (operands[2] == constm1_rtx
4941 || (GET_CODE (operands[2]) == CONST_INT
4942 && INTVAL (operands[2]) == 65535))
4943 return \"dec{w}\\t%0\";
4947 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
4948 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
4949 if (GET_CODE (operands[2]) == CONST_INT
4950 && (INTVAL (operands[2]) == 128
4951 || (INTVAL (operands[2]) < 0
4952 && INTVAL (operands[2]) != -128)))
4954 operands[2] = GEN_INT (-INTVAL (operands[2]));
4955 return \"sub{w}\\t{%2, %0|%0, %2}\";
4957 return \"add{w}\\t{%2, %0|%0, %2}\";
4961 (if_then_else (eq_attr "alternative" "2")
4962 (const_string "lea")
4963 (if_then_else (match_operand:HI 2 "incdec_operand" "")
4964 (const_string "incdec")
4965 (const_string "alu"))))
4966 (set_attr "mode" "HI,HI,SI")])
4968 (define_insn "*addhi_1"
4969 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
4970 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
4971 (match_operand:HI 2 "general_operand" "ri,rm")))
4972 (clobber (reg:CC 17))]
4973 "TARGET_PARTIAL_REG_STALL
4974 && ix86_binary_operator_ok (PLUS, HImode, operands)"
4977 switch (get_attr_type (insn))
4980 if (operands[2] == const1_rtx)
4981 return \"inc{w}\\t%0\";
4982 else if (operands[2] == constm1_rtx
4983 || (GET_CODE (operands[2]) == CONST_INT
4984 && INTVAL (operands[2]) == 65535))
4985 return \"dec{w}\\t%0\";
4989 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
4990 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
4991 if (GET_CODE (operands[2]) == CONST_INT
4992 && (INTVAL (operands[2]) == 128
4993 || (INTVAL (operands[2]) < 0
4994 && INTVAL (operands[2]) != -128)))
4996 operands[2] = GEN_INT (-INTVAL (operands[2]));
4997 return \"sub{w}\\t{%2, %0|%0, %2}\";
4999 return \"add{w}\\t{%2, %0|%0, %2}\";
5003 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5004 (const_string "incdec")
5005 (const_string "alu")))
5006 (set_attr "mode" "HI")])
5008 (define_insn "*addhi_2"
5011 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
5012 (match_operand:HI 2 "general_operand" "rmni,rni"))
5014 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
5015 (plus:HI (match_dup 1) (match_dup 2)))]
5016 "ix86_match_ccmode (insn, CCGOCmode)
5017 && ix86_binary_operator_ok (PLUS, HImode, operands)"
5020 switch (get_attr_type (insn))
5023 if (operands[2] == const1_rtx)
5024 return \"inc{w}\\t%0\";
5025 else if (operands[2] == constm1_rtx
5026 || (GET_CODE (operands[2]) == CONST_INT
5027 && INTVAL (operands[2]) == 65535))
5028 return \"dec{w}\\t%0\";
5032 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5033 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5034 if (GET_CODE (operands[2]) == CONST_INT
5035 && (INTVAL (operands[2]) == 128
5036 || (INTVAL (operands[2]) < 0
5037 && INTVAL (operands[2]) != -128)))
5039 operands[2] = GEN_INT (-INTVAL (operands[2]));
5040 return \"sub{w}\\t{%2, %0|%0, %2}\";
5042 return \"add{w}\\t{%2, %0|%0, %2}\";
5046 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5047 (const_string "incdec")
5048 (const_string "alu")))
5049 (set_attr "mode" "HI")])
5051 (define_insn "*addhi_3"
5053 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
5054 (match_operand:HI 1 "nonimmediate_operand" "%0")))
5055 (clobber (match_scratch:HI 0 "=r"))]
5056 "ix86_match_ccmode (insn, CCZmode)
5057 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5060 switch (get_attr_type (insn))
5063 if (operands[2] == const1_rtx)
5064 return \"inc{w}\\t%0\";
5065 else if (operands[2] == constm1_rtx
5066 || (GET_CODE (operands[2]) == CONST_INT
5067 && INTVAL (operands[2]) == 65535))
5068 return \"dec{w}\\t%0\";
5072 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5073 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5074 if (GET_CODE (operands[2]) == CONST_INT
5075 && (INTVAL (operands[2]) == 128
5076 || (INTVAL (operands[2]) < 0
5077 && INTVAL (operands[2]) != -128)))
5079 operands[2] = GEN_INT (-INTVAL (operands[2]));
5080 return \"sub{w}\\t{%2, %0|%0, %2}\";
5082 return \"add{w}\\t{%2, %0|%0, %2}\";
5086 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5087 (const_string "incdec")
5088 (const_string "alu")))
5089 (set_attr "mode" "HI")])
5091 ; See comments above addsi_3_imm for details.
5092 (define_insn "*addhi_4"
5094 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
5095 (match_operand:HI 2 "const_int_operand" "n")))
5096 (clobber (match_scratch:HI 0 "=rm"))]
5097 "ix86_match_ccmode (insn, CCGCmode)
5098 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
5101 switch (get_attr_type (insn))
5104 if (operands[2] == constm1_rtx
5105 || (GET_CODE (operands[2]) == CONST_INT
5106 && INTVAL (operands[2]) == 65535))
5107 return \"inc{w}\\t%0\";
5108 else if (operands[2] == const1_rtx)
5109 return \"dec{w}\\t%0\";
5114 if (! rtx_equal_p (operands[0], operands[1]))
5116 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5117 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5118 if ((INTVAL (operands[2]) == -128
5119 || (INTVAL (operands[2]) > 0
5120 && INTVAL (operands[2]) != 128)))
5121 return \"sub{w}\\t{%2, %0|%0, %2}\";
5122 operands[2] = GEN_INT (-INTVAL (operands[2]));
5123 return \"add{w}\\t{%2, %0|%0, %2}\";
5127 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5128 (const_string "incdec")
5129 (const_string "alu")))
5130 (set_attr "mode" "SI")])
5133 (define_insn "*addhi_5"
5136 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
5137 (match_operand:HI 2 "general_operand" "rmni"))
5139 (clobber (match_scratch:HI 0 "=r"))]
5140 "ix86_match_ccmode (insn, CCGOCmode)
5141 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5144 switch (get_attr_type (insn))
5147 if (operands[2] == const1_rtx)
5148 return \"inc{w}\\t%0\";
5149 else if (operands[2] == constm1_rtx
5150 || (GET_CODE (operands[2]) == CONST_INT
5151 && INTVAL (operands[2]) == 65535))
5152 return \"dec{w}\\t%0\";
5156 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5157 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5158 if (GET_CODE (operands[2]) == CONST_INT
5159 && (INTVAL (operands[2]) == 128
5160 || (INTVAL (operands[2]) < 0
5161 && INTVAL (operands[2]) != -128)))
5163 operands[2] = GEN_INT (-INTVAL (operands[2]));
5164 return \"sub{w}\\t{%2, %0|%0, %2}\";
5166 return \"add{w}\\t{%2, %0|%0, %2}\";
5170 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5171 (const_string "incdec")
5172 (const_string "alu")))
5173 (set_attr "mode" "HI")])
5175 (define_expand "addqi3"
5176 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
5177 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
5178 (match_operand:QI 2 "general_operand" "")))
5179 (clobber (reg:CC 17))])]
5180 "TARGET_QIMODE_MATH"
5181 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
5183 ;; %%% Potential partial reg stall on alternative 2. What to do?
5184 (define_insn "*addqi_1_lea"
5185 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
5186 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
5187 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
5188 (clobber (reg:CC 17))]
5189 "!TARGET_PARTIAL_REG_STALL
5190 && ix86_binary_operator_ok (PLUS, QImode, operands)"
5193 int widen = (which_alternative == 2);
5194 switch (get_attr_type (insn))
5199 if (operands[2] == const1_rtx)
5200 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
5201 else if (operands[2] == constm1_rtx
5202 || (GET_CODE (operands[2]) == CONST_INT
5203 && INTVAL (operands[2]) == 255))
5204 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
5208 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5209 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5210 if (GET_CODE (operands[2]) == CONST_INT
5211 && (INTVAL (operands[2]) == 128
5212 || (INTVAL (operands[2]) < 0
5213 && INTVAL (operands[2]) != -128)))
5215 operands[2] = GEN_INT (-INTVAL (operands[2]));
5217 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
5219 return \"sub{b}\\t{%2, %0|%0, %2}\";
5222 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
5224 return \"add{b}\\t{%2, %0|%0, %2}\";
5228 (if_then_else (eq_attr "alternative" "3")
5229 (const_string "lea")
5230 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5231 (const_string "incdec")
5232 (const_string "alu"))))
5233 (set_attr "mode" "QI,QI,SI,SI")])
5235 (define_insn "*addqi_1"
5236 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
5237 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5238 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
5239 (clobber (reg:CC 17))]
5240 "TARGET_PARTIAL_REG_STALL
5241 && ix86_binary_operator_ok (PLUS, QImode, operands)"
5244 int widen = (which_alternative == 2);
5245 switch (get_attr_type (insn))
5248 if (operands[2] == const1_rtx)
5249 return widen ? \"inc{l}\\t%k0\" : \"inc{b}\\t%0\";
5250 else if (operands[2] == constm1_rtx
5251 || (GET_CODE (operands[2]) == CONST_INT
5252 && INTVAL (operands[2]) == 255))
5253 return widen ? \"dec{l}\\t%k0\" : \"dec{b}\\t%0\";
5257 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5258 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5259 if (GET_CODE (operands[2]) == CONST_INT
5260 && (INTVAL (operands[2]) == 128
5261 || (INTVAL (operands[2]) < 0
5262 && INTVAL (operands[2]) != -128)))
5264 operands[2] = GEN_INT (-INTVAL (operands[2]));
5266 return \"sub{l}\\t{%2, %k0|%k0, %2}\";
5268 return \"sub{b}\\t{%2, %0|%0, %2}\";
5271 return \"add{l}\\t{%k2, %k0|%k0, %k2}\";
5273 return \"add{b}\\t{%2, %0|%0, %2}\";
5277 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5278 (const_string "incdec")
5279 (const_string "alu")))
5280 (set_attr "mode" "QI,QI,SI")])
5282 (define_insn "*addqi_2"
5285 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
5286 (match_operand:QI 2 "general_operand" "qmni,qni"))
5288 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
5289 (plus:QI (match_dup 1) (match_dup 2)))]
5290 "ix86_match_ccmode (insn, CCGOCmode)
5291 && ix86_binary_operator_ok (PLUS, QImode, operands)"
5294 switch (get_attr_type (insn))
5297 if (operands[2] == const1_rtx)
5298 return \"inc{b}\\t%0\";
5299 else if (operands[2] == constm1_rtx
5300 || (GET_CODE (operands[2]) == CONST_INT
5301 && INTVAL (operands[2]) == 255))
5302 return \"dec{b}\\t%0\";
5306 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
5307 if (GET_CODE (operands[2]) == CONST_INT
5308 && INTVAL (operands[2]) < 0)
5310 operands[2] = GEN_INT (-INTVAL (operands[2]));
5311 return \"sub{b}\\t{%2, %0|%0, %2}\";
5313 return \"add{b}\\t{%2, %0|%0, %2}\";
5317 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5318 (const_string "incdec")
5319 (const_string "alu")))
5320 (set_attr "mode" "QI")])
5322 (define_insn "*addqi_3"
5324 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
5325 (match_operand:QI 1 "nonimmediate_operand" "%0")))
5326 (clobber (match_scratch:QI 0 "=q"))]
5327 "ix86_match_ccmode (insn, CCZmode)
5328 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5331 switch (get_attr_type (insn))
5334 if (operands[2] == const1_rtx)
5335 return \"inc{b}\\t%0\";
5336 else if (operands[2] == constm1_rtx
5337 || (GET_CODE (operands[2]) == CONST_INT
5338 && INTVAL (operands[2]) == 255))
5339 return \"dec{b}\\t%0\";
5343 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
5344 if (GET_CODE (operands[2]) == CONST_INT
5345 && INTVAL (operands[2]) < 0)
5347 operands[2] = GEN_INT (-INTVAL (operands[2]));
5348 return \"sub{b}\\t{%2, %0|%0, %2}\";
5350 return \"add{b}\\t{%2, %0|%0, %2}\";
5354 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5355 (const_string "incdec")
5356 (const_string "alu")))
5357 (set_attr "mode" "QI")])
5359 ; See comments above addsi_3_imm for details.
5360 (define_insn "*addqi_4"
5362 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
5363 (match_operand:QI 2 "const_int_operand" "n")))
5364 (clobber (match_scratch:QI 0 "=qm"))]
5365 "ix86_match_ccmode (insn, CCGCmode)
5366 && (INTVAL (operands[2]) & 0xff) != 0x80"
5369 switch (get_attr_type (insn))
5372 if (operands[2] == constm1_rtx
5373 || (GET_CODE (operands[2]) == CONST_INT
5374 && INTVAL (operands[2]) == 255))
5375 return \"inc{b}\\t%0\";
5376 else if (operands[2] == const1_rtx)
5377 return \"dec{b}\\t%0\";
5382 if (! rtx_equal_p (operands[0], operands[1]))
5384 if (INTVAL (operands[2]) < 0)
5386 operands[2] = GEN_INT (-INTVAL (operands[2]));
5387 return \"add{b}\\t{%2, %0|%0, %2}\";
5389 return \"sub{b}\\t{%2, %0|%0, %2}\";
5393 (if_then_else (match_operand:HI 2 "incdec_operand" "")
5394 (const_string "incdec")
5395 (const_string "alu")))
5396 (set_attr "mode" "QI")])
5399 (define_insn "*addqi_5"
5402 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
5403 (match_operand:QI 2 "general_operand" "qmni"))
5405 (clobber (match_scratch:QI 0 "=q"))]
5406 "ix86_match_ccmode (insn, CCGOCmode)
5407 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
5410 switch (get_attr_type (insn))
5413 if (operands[2] == const1_rtx)
5414 return \"inc{b}\\t%0\";
5415 else if (operands[2] == constm1_rtx
5416 || (GET_CODE (operands[2]) == CONST_INT
5417 && INTVAL (operands[2]) == 255))
5418 return \"dec{b}\\t%0\";
5422 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
5423 if (GET_CODE (operands[2]) == CONST_INT
5424 && INTVAL (operands[2]) < 0)
5426 operands[2] = GEN_INT (-INTVAL (operands[2]));
5427 return \"sub{b}\\t{%2, %0|%0, %2}\";
5429 return \"add{b}\\t{%2, %0|%0, %2}\";
5433 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5434 (const_string "incdec")
5435 (const_string "alu")))
5436 (set_attr "mode" "QI")])
5439 (define_insn "addqi_ext_1"
5440 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
5445 (match_operand 1 "ext_register_operand" "0")
5448 (match_operand:QI 2 "general_operand" "qmn")))
5449 (clobber (reg:CC 17))]
5453 switch (get_attr_type (insn))
5456 if (operands[2] == const1_rtx)
5457 return \"inc{b}\\t%h0\";
5458 else if (operands[2] == constm1_rtx
5459 || (GET_CODE (operands[2]) == CONST_INT
5460 && INTVAL (operands[2]) == 255))
5461 return \"dec{b}\\t%h0\";
5465 return \"add{b}\\t{%2, %h0|%h0, %2}\";
5469 (if_then_else (match_operand:QI 2 "incdec_operand" "")
5470 (const_string "incdec")
5471 (const_string "alu")))
5472 (set_attr "mode" "QI")])
5474 (define_insn "*addqi_ext_2"
5475 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
5480 (match_operand 1 "ext_register_operand" "%0")
5484 (match_operand 2 "ext_register_operand" "q")
5487 (clobber (reg:CC 17))]
5489 "add{b}\\t{%h2, %h0|%h0, %h2}"
5490 [(set_attr "type" "alu")
5491 (set_attr "mode" "QI")])
5493 ;; The patterns that match these are at the end of this file.
5495 (define_expand "addxf3"
5496 [(set (match_operand:XF 0 "register_operand" "")
5497 (plus:XF (match_operand:XF 1 "register_operand" "")
5498 (match_operand:XF 2 "register_operand" "")))]
5502 (define_expand "addtf3"
5503 [(set (match_operand:TF 0 "register_operand" "")
5504 (plus:TF (match_operand:TF 1 "register_operand" "")
5505 (match_operand:TF 2 "register_operand" "")))]
5509 (define_expand "adddf3"
5510 [(set (match_operand:DF 0 "register_operand" "")
5511 (plus:DF (match_operand:DF 1 "register_operand" "")
5512 (match_operand:DF 2 "nonimmediate_operand" "")))]
5513 "TARGET_80387 || TARGET_SSE2"
5516 (define_expand "addsf3"
5517 [(set (match_operand:SF 0 "register_operand" "")
5518 (plus:SF (match_operand:SF 1 "register_operand" "")
5519 (match_operand:SF 2 "nonimmediate_operand" "")))]
5520 "TARGET_80387 || TARGET_SSE"
5523 ;; Subtract instructions
5525 ;; %%% define_expand from the very first?
5526 ;; %%% splits for subsidi3
5528 (define_insn "subdi3"
5529 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5530 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
5531 (match_operand:DI 2 "general_operand" "roiF,riF")))
5532 (clobber (reg:CC 17))]
5537 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5538 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5539 (match_operand:DI 2 "general_operand" "")))
5540 (clobber (reg:CC 17))]
5542 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
5543 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
5544 (parallel [(set (match_dup 3)
5545 (minus:SI (match_dup 4)
5546 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5548 (clobber (reg:CC 17))])]
5549 "split_di (operands+0, 1, operands+0, operands+3);
5550 split_di (operands+1, 1, operands+1, operands+4);
5551 split_di (operands+2, 1, operands+2, operands+5);")
5553 (define_insn "subsi3_carry"
5554 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5555 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
5556 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5557 (match_operand:SI 2 "general_operand" "ri,rm"))))
5558 (clobber (reg:CC 17))]
5559 "ix86_binary_operator_ok (MINUS, SImode, operands)"
5560 "sbb{l}\\t{%2, %0|%0, %2}"
5561 [(set_attr "type" "alu")
5562 (set_attr "pent_pair" "pu")
5563 (set_attr "ppro_uops" "few")
5564 (set_attr "mode" "SI")])
5566 (define_expand "subsi3"
5567 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5568 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5569 (match_operand:SI 2 "general_operand" "")))
5570 (clobber (reg:CC 17))])]
5572 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
5574 (define_insn "*subsi_1"
5575 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5576 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
5577 (match_operand:SI 2 "general_operand" "ri,rm")))
5578 (clobber (reg:CC 17))]
5579 "ix86_binary_operator_ok (MINUS, SImode, operands)"
5580 "sub{l}\\t{%2, %0|%0, %2}"
5581 [(set_attr "type" "alu")
5582 (set_attr "mode" "SI")])
5584 (define_insn "*subsi_2"
5587 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
5588 (match_operand:SI 2 "general_operand" "ri,rm"))
5590 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5591 (minus:SI (match_dup 1) (match_dup 2)))]
5592 "ix86_match_ccmode (insn, CCGOCmode)
5593 && ix86_binary_operator_ok (MINUS, SImode, operands)"
5594 "sub{l}\\t{%2, %0|%0, %2}"
5595 [(set_attr "type" "alu")
5596 (set_attr "mode" "SI")])
5598 (define_insn "*subsi_3"
5600 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
5601 (match_operand:SI 2 "general_operand" "ri,rm")))
5602 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5603 (minus:SI (match_dup 1) (match_dup 2)))]
5604 "ix86_match_ccmode (insn, CCmode)
5605 && ix86_binary_operator_ok (MINUS, SImode, operands)"
5606 "sub{l}\\t{%2, %0|%0, %2}"
5607 [(set_attr "type" "alu")
5608 (set_attr "mode" "SI")])
5610 (define_expand "subhi3"
5611 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
5612 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
5613 (match_operand:HI 2 "general_operand" "")))
5614 (clobber (reg:CC 17))])]
5615 "TARGET_HIMODE_MATH"
5616 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
5618 (define_insn "*subhi_1"
5619 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5620 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
5621 (match_operand:HI 2 "general_operand" "ri,rm")))
5622 (clobber (reg:CC 17))]
5623 "ix86_binary_operator_ok (MINUS, HImode, operands)"
5624 "sub{w}\\t{%2, %0|%0, %2}"
5625 [(set_attr "type" "alu")
5626 (set_attr "mode" "HI")])
5628 (define_insn "*subhi_2"
5631 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
5632 (match_operand:HI 2 "general_operand" "ri,rm"))
5634 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5635 (minus:HI (match_dup 1) (match_dup 2)))]
5636 "ix86_match_ccmode (insn, CCGOCmode)
5637 && ix86_binary_operator_ok (MINUS, HImode, operands)"
5638 "sub{w}\\t{%2, %0|%0, %2}"
5639 [(set_attr "type" "alu")
5640 (set_attr "mode" "HI")])
5642 (define_insn "*subhi_3"
5644 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
5645 (match_operand:HI 2 "general_operand" "ri,rm")))
5646 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5647 (minus:HI (match_dup 1) (match_dup 2)))]
5648 "ix86_match_ccmode (insn, CCmode)
5649 && ix86_binary_operator_ok (MINUS, HImode, operands)"
5650 "sub{w}\\t{%2, %0|%0, %2}"
5651 [(set_attr "type" "alu")
5652 (set_attr "mode" "HI")])
5654 (define_expand "subqi3"
5655 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
5656 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
5657 (match_operand:QI 2 "general_operand" "")))
5658 (clobber (reg:CC 17))])]
5659 "TARGET_QIMODE_MATH"
5660 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
5662 (define_insn "*subqi_1"
5663 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5664 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
5665 (match_operand:QI 2 "general_operand" "qn,qmn")))
5666 (clobber (reg:CC 17))]
5667 "ix86_binary_operator_ok (MINUS, QImode, operands)"
5668 "sub{b}\\t{%2, %0|%0, %2}"
5669 [(set_attr "type" "alu")
5670 (set_attr "mode" "QI")])
5672 (define_insn "*subqi_2"
5675 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
5676 (match_operand:QI 2 "general_operand" "qi,qm"))
5678 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
5679 (minus:HI (match_dup 1) (match_dup 2)))]
5680 "ix86_match_ccmode (insn, CCGOCmode)
5681 && ix86_binary_operator_ok (MINUS, QImode, operands)"
5682 "sub{b}\\t{%2, %0|%0, %2}"
5683 [(set_attr "type" "alu")
5684 (set_attr "mode" "QI")])
5686 (define_insn "*subqi_3"
5688 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
5689 (match_operand:QI 2 "general_operand" "qi,qm")))
5690 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
5691 (minus:HI (match_dup 1) (match_dup 2)))]
5692 "ix86_match_ccmode (insn, CCmode)
5693 && ix86_binary_operator_ok (MINUS, QImode, operands)"
5694 "sub{b}\\t{%2, %0|%0, %2}"
5695 [(set_attr "type" "alu")
5696 (set_attr "mode" "QI")])
5698 ;; The patterns that match these are at the end of this file.
5700 (define_expand "subxf3"
5701 [(set (match_operand:XF 0 "register_operand" "")
5702 (minus:XF (match_operand:XF 1 "register_operand" "")
5703 (match_operand:XF 2 "register_operand" "")))]
5707 (define_expand "subtf3"
5708 [(set (match_operand:TF 0 "register_operand" "")
5709 (minus:TF (match_operand:TF 1 "register_operand" "")
5710 (match_operand:TF 2 "register_operand" "")))]
5714 (define_expand "subdf3"
5715 [(set (match_operand:DF 0 "register_operand" "")
5716 (minus:DF (match_operand:DF 1 "register_operand" "")
5717 (match_operand:DF 2 "nonimmediate_operand" "")))]
5718 "TARGET_80387 || TARGET_SSE2"
5721 (define_expand "subsf3"
5722 [(set (match_operand:SF 0 "register_operand" "")
5723 (minus:SF (match_operand:SF 1 "register_operand" "")
5724 (match_operand:SF 2 "nonimmediate_operand" "")))]
5725 "TARGET_80387 || TARGET_SSE"
5728 ;; Multiply instructions
5730 (define_expand "mulsi3"
5731 [(parallel [(set (match_operand:SI 0 "register_operand" "")
5732 (mult:SI (match_operand:SI 1 "register_operand" "")
5733 (match_operand:SI 2 "general_operand" "")))
5734 (clobber (reg:CC 17))])]
5738 (define_insn "*mulsi3_1"
5739 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
5740 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,0,0")
5741 (match_operand:SI 2 "general_operand" "K,i,mr")))
5742 (clobber (reg:CC 17))]
5743 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
5744 ; For the {r,0,i} alternative (i.e., register <- register * immediate),
5745 ; there are two ways of writing the exact same machine instruction
5746 ; in assembly language. One, for example, is:
5750 ; while the other is:
5752 ; imul $12, %eax, %eax
5754 ; The first is simply short-hand for the latter. But, some assemblers,
5755 ; like the SCO OSR5 COFF assembler, don't handle the first form.
5757 imul{l}\\t{%2, %1, %0|%0, %1, %2}
5758 imul{l}\\t{%2, %1, %0|%0, %1, %2}
5759 imul{l}\\t{%2, %0|%0, %2}"
5760 [(set_attr "type" "imul")
5761 (set_attr "prefix_0f" "0,0,1")
5762 (set_attr "mode" "SI")])
5764 (define_expand "mulhi3"
5765 [(parallel [(set (match_operand:HI 0 "register_operand" "")
5766 (mult:HI (match_operand:HI 1 "register_operand" "")
5767 (match_operand:HI 2 "general_operand" "")))
5768 (clobber (reg:CC 17))])]
5769 "TARGET_HIMODE_MATH"
5772 (define_insn "*mulhi3_1"
5773 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
5774 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
5775 (match_operand:HI 2 "general_operand" "K,i,mr")))
5776 (clobber (reg:CC 17))]
5777 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
5778 ; %%% There was a note about "Assembler has weird restrictions",
5779 ; concerning alternative 1 when op1 == op0. True?
5781 imul{w}\\t{%2, %1, %0|%0, %1, %2}
5782 imul{w}\\t{%2, %1, %0|%0, %1, %2}
5783 imul{w}\\t{%2, %0|%0, %2}"
5784 [(set_attr "type" "imul")
5785 (set_attr "prefix_0f" "0,0,1")
5786 (set_attr "mode" "HI")])
5788 (define_insn "mulqi3"
5789 [(set (match_operand:QI 0 "register_operand" "=a")
5790 (mult:QI (match_operand:QI 1 "register_operand" "%0")
5791 (match_operand:QI 2 "nonimmediate_operand" "qm")))
5792 (clobber (reg:CC 17))]
5793 "TARGET_QIMODE_MATH"
5795 [(set_attr "type" "imul")
5796 (set_attr "length_immediate" "0")
5797 (set_attr "mode" "QI")])
5799 (define_insn "umulqihi3"
5800 [(set (match_operand:HI 0 "register_operand" "=a")
5801 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
5802 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
5803 (clobber (reg:CC 17))]
5804 "TARGET_QIMODE_MATH"
5806 [(set_attr "type" "imul")
5807 (set_attr "length_immediate" "0")
5808 (set_attr "mode" "QI")])
5810 (define_insn "mulqihi3"
5811 [(set (match_operand:HI 0 "register_operand" "=a")
5812 (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
5813 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
5814 (clobber (reg:CC 17))]
5815 "TARGET_QIMODE_MATH"
5817 [(set_attr "type" "imul")
5818 (set_attr "length_immediate" "0")
5819 (set_attr "mode" "QI")])
5821 (define_insn "umulsidi3"
5822 [(set (match_operand:DI 0 "register_operand" "=A")
5823 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
5824 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
5825 (clobber (reg:CC 17))]
5828 [(set_attr "type" "imul")
5829 (set_attr "ppro_uops" "few")
5830 (set_attr "length_immediate" "0")
5831 (set_attr "mode" "SI")])
5833 (define_insn "mulsidi3"
5834 [(set (match_operand:DI 0 "register_operand" "=A")
5835 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
5836 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
5837 (clobber (reg:CC 17))]
5840 [(set_attr "type" "imul")
5841 (set_attr "length_immediate" "0")
5842 (set_attr "mode" "SI")])
5844 (define_insn "umulsi3_highpart"
5845 [(set (match_operand:SI 0 "register_operand" "=d")
5848 (mult:DI (zero_extend:DI
5849 (match_operand:SI 1 "register_operand" "%a"))
5851 (match_operand:SI 2 "nonimmediate_operand" "rm")))
5853 (clobber (match_scratch:SI 3 "=a"))
5854 (clobber (reg:CC 17))]
5857 [(set_attr "type" "imul")
5858 (set_attr "ppro_uops" "few")
5859 (set_attr "length_immediate" "0")
5860 (set_attr "mode" "SI")])
5862 (define_insn "smulsi3_highpart"
5863 [(set (match_operand:SI 0 "register_operand" "=d")
5866 (mult:DI (sign_extend:DI
5867 (match_operand:SI 1 "register_operand" "%a"))
5869 (match_operand:SI 2 "nonimmediate_operand" "rm")))
5871 (clobber (match_scratch:SI 3 "=a"))
5872 (clobber (reg:CC 17))]
5875 [(set_attr "type" "imul")
5876 (set_attr "ppro_uops" "few")
5877 (set_attr "mode" "SI")])
5879 ;; The patterns that match these are at the end of this file.
5881 (define_expand "mulxf3"
5882 [(set (match_operand:XF 0 "register_operand" "")
5883 (mult:XF (match_operand:XF 1 "register_operand" "")
5884 (match_operand:XF 2 "register_operand" "")))]
5888 (define_expand "multf3"
5889 [(set (match_operand:TF 0 "register_operand" "")
5890 (mult:TF (match_operand:TF 1 "register_operand" "")
5891 (match_operand:TF 2 "register_operand" "")))]
5895 (define_expand "muldf3"
5896 [(set (match_operand:DF 0 "register_operand" "")
5897 (mult:DF (match_operand:DF 1 "register_operand" "")
5898 (match_operand:DF 2 "nonimmediate_operand" "")))]
5899 "TARGET_80387 || TARGET_SSE2"
5902 (define_expand "mulsf3"
5903 [(set (match_operand:SF 0 "register_operand" "")
5904 (mult:SF (match_operand:SF 1 "register_operand" "")
5905 (match_operand:SF 2 "nonimmediate_operand" "")))]
5906 "TARGET_80387 || TARGET_SSE"
5909 ;; Divide instructions
5911 (define_insn "divqi3"
5912 [(set (match_operand:QI 0 "register_operand" "=a")
5913 (div:QI (match_operand:HI 1 "register_operand" "0")
5914 (match_operand:QI 2 "nonimmediate_operand" "qm")))
5915 (clobber (reg:CC 17))]
5916 "TARGET_QIMODE_MATH"
5918 [(set_attr "type" "idiv")
5919 (set_attr "mode" "QI")
5920 (set_attr "ppro_uops" "few")])
5922 (define_insn "udivqi3"
5923 [(set (match_operand:QI 0 "register_operand" "=a")
5924 (udiv:QI (match_operand:HI 1 "register_operand" "0")
5925 (match_operand:QI 2 "nonimmediate_operand" "qm")))
5926 (clobber (reg:CC 17))]
5927 "TARGET_QIMODE_MATH"
5929 [(set_attr "type" "idiv")
5930 (set_attr "mode" "QI")
5931 (set_attr "ppro_uops" "few")])
5933 ;; The patterns that match these are at the end of this file.
5935 (define_expand "divxf3"
5936 [(set (match_operand:XF 0 "register_operand" "")
5937 (div:XF (match_operand:XF 1 "register_operand" "")
5938 (match_operand:XF 2 "register_operand" "")))]
5942 (define_expand "divtf3"
5943 [(set (match_operand:TF 0 "register_operand" "")
5944 (div:TF (match_operand:TF 1 "register_operand" "")
5945 (match_operand:TF 2 "register_operand" "")))]
5949 (define_expand "divdf3"
5950 [(set (match_operand:DF 0 "register_operand" "")
5951 (div:DF (match_operand:DF 1 "register_operand" "")
5952 (match_operand:DF 2 "nonimmediate_operand" "")))]
5953 "TARGET_80387 || TARGET_SSE2"
5956 (define_expand "divsf3"
5957 [(set (match_operand:SF 0 "register_operand" "")
5958 (div:SF (match_operand:SF 1 "register_operand" "")
5959 (match_operand:SF 2 "nonimmediate_operand" "")))]
5960 "TARGET_80387 || TARGET_SSE"
5963 ;; Remainder instructions.
5964 (define_expand "divmodsi4"
5965 [(parallel [(set (match_operand:SI 0 "register_operand" "")
5966 (div:SI (match_operand:SI 1 "register_operand" "")
5967 (match_operand:SI 2 "nonimmediate_operand" "")))
5968 (set (match_operand:SI 3 "register_operand" "")
5969 (mod:SI (match_dup 1) (match_dup 2)))
5970 (clobber (reg:CC 17))])]
5974 ;; Allow to come the parameter in eax or edx to avoid extra moves.
5975 ;; Penalize eax case sligthly because it results in worse scheduling
5977 (define_insn "*divmodsi4_nocltd"
5978 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
5979 (div:SI (match_operand:SI 2 "register_operand" "1,0")
5980 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
5981 (set (match_operand:SI 1 "register_operand" "=&d,&d")
5982 (mod:SI (match_dup 2) (match_dup 3)))
5983 (clobber (reg:CC 17))]
5984 "!optimize_size && !TARGET_USE_CLTD"
5986 [(set_attr "type" "multi")])
5988 (define_insn "*divmodsi4_cltd"
5989 [(set (match_operand:SI 0 "register_operand" "=a")
5990 (div:SI (match_operand:SI 2 "register_operand" "a")
5991 (match_operand:SI 3 "nonimmediate_operand" "rm")))
5992 (set (match_operand:SI 1 "register_operand" "=&d")
5993 (mod:SI (match_dup 2) (match_dup 3)))
5994 (clobber (reg:CC 17))]
5995 "optimize_size || TARGET_USE_CLTD"
5997 [(set_attr "type" "multi")])
5999 (define_insn "*divmodsi_noext"
6000 [(set (match_operand:SI 0 "register_operand" "=a")
6001 (div:SI (match_operand:SI 1 "register_operand" "0")
6002 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6003 (set (match_operand:SI 3 "register_operand" "=d")
6004 (mod:SI (match_dup 1) (match_dup 2)))
6005 (use (match_operand:SI 4 "register_operand" "3"))
6006 (clobber (reg:CC 17))]
6009 [(set_attr "type" "idiv")
6010 (set_attr "mode" "SI")
6011 (set_attr "ppro_uops" "few")])
6014 [(set (match_operand:SI 0 "register_operand" "")
6015 (div:SI (match_operand:SI 1 "register_operand" "")
6016 (match_operand:SI 2 "nonimmediate_operand" "")))
6017 (set (match_operand:SI 3 "register_operand" "")
6018 (mod:SI (match_dup 1) (match_dup 2)))
6019 (clobber (reg:CC 17))]
6021 [(parallel [(set (match_dup 3)
6022 (ashiftrt:SI (match_dup 4) (const_int 31)))
6023 (clobber (reg:CC 17))])
6024 (parallel [(set (match_dup 0)
6025 (div:SI (reg:SI 0) (match_dup 2)))
6027 (mod:SI (reg:SI 0) (match_dup 2)))
6029 (clobber (reg:CC 17))])]
6032 /* Avoid use of cltd in favour of a mov+shift. */
6033 if (!TARGET_USE_CLTD && !optimize_size)
6035 if (true_regnum (operands[1]))
6036 emit_move_insn (operands[0], operands[1]);
6038 emit_move_insn (operands[3], operands[1]);
6039 operands[4] = operands[3];
6043 if (true_regnum (operands[1]))
6045 operands[4] = operands[1];
6049 (define_insn "divmodhi4"
6050 [(set (match_operand:HI 0 "register_operand" "=a")
6051 (div:HI (match_operand:HI 1 "register_operand" "0")
6052 (match_operand:HI 2 "nonimmediate_operand" "rm")))
6053 (set (match_operand:HI 3 "register_operand" "=&d")
6054 (mod:HI (match_dup 1) (match_dup 2)))
6055 (clobber (reg:CC 17))]
6056 "TARGET_HIMODE_MATH"
6057 "cwtd\;idiv{w}\\t%2"
6058 [(set_attr "type" "multi")
6059 (set_attr "length_immediate" "0")
6060 (set_attr "mode" "SI")])
6062 (define_insn "udivmodsi4"
6063 [(set (match_operand:SI 0 "register_operand" "=a")
6064 (udiv:SI (match_operand:SI 1 "register_operand" "0")
6065 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6066 (set (match_operand:SI 3 "register_operand" "=&d")
6067 (umod:SI (match_dup 1) (match_dup 2)))
6068 (clobber (reg:CC 17))]
6070 "xor{l}\\t%3, %3\;div{l}\\t%2"
6071 [(set_attr "type" "multi")
6072 (set_attr "length_immediate" "0")
6073 (set_attr "mode" "SI")])
6075 (define_insn "*udivmodsi4_noext"
6076 [(set (match_operand:SI 0 "register_operand" "=a")
6077 (udiv:SI (match_operand:SI 1 "register_operand" "0")
6078 (match_operand:SI 2 "nonimmediate_operand" "rm")))
6079 (set (match_operand:SI 3 "register_operand" "=d")
6080 (umod:SI (match_dup 1) (match_dup 2)))
6082 (clobber (reg:CC 17))]
6085 [(set_attr "type" "idiv")
6086 (set_attr "ppro_uops" "few")
6087 (set_attr "mode" "SI")])
6090 [(set (match_operand:SI 0 "register_operand" "")
6091 (udiv:SI (match_operand:SI 1 "register_operand" "")
6092 (match_operand:SI 2 "nonimmediate_operand" "")))
6093 (set (match_operand:SI 3 "register_operand" "")
6094 (umod:SI (match_dup 1) (match_dup 2)))
6095 (clobber (reg:CC 17))]
6097 [(set (match_dup 3) (const_int 0))
6098 (parallel [(set (match_dup 0)
6099 (udiv:SI (match_dup 1) (match_dup 2)))
6101 (umod:SI (match_dup 1) (match_dup 2)))
6103 (clobber (reg:CC 17))])]
6106 (define_expand "udivmodhi4"
6107 [(set (match_dup 4) (const_int 0))
6108 (parallel [(set (match_operand:HI 0 "register_operand" "")
6109 (udiv:HI (match_operand:HI 1 "register_operand" "")
6110 (match_operand:HI 2 "nonimmediate_operand" "")))
6111 (set (match_operand:HI 3 "register_operand" "")
6112 (umod:HI (match_dup 1) (match_dup 2)))
6114 (clobber (reg:CC 17))])]
6115 "TARGET_HIMODE_MATH"
6116 "operands[4] = gen_reg_rtx (HImode);")
6118 (define_insn "*udivmodhi_noext"
6119 [(set (match_operand:HI 0 "register_operand" "=a")
6120 (udiv:HI (match_operand:HI 1 "register_operand" "0")
6121 (match_operand:HI 2 "nonimmediate_operand" "rm")))
6122 (set (match_operand:HI 3 "register_operand" "=d")
6123 (umod:HI (match_dup 1) (match_dup 2)))
6124 (use (match_operand:HI 4 "register_operand" "3"))
6125 (clobber (reg:CC 17))]
6128 [(set_attr "type" "idiv")
6129 (set_attr "mode" "HI")
6130 (set_attr "ppro_uops" "few")])
6132 ;; We can not use div/idiv for double division, because it causes
6133 ;; "division by zero" on the overflow and that's not what we expect
6134 ;; from truncate. Because true (non truncating) double division is
6135 ;; never generated, we can't create this insn anyway.
6138 ; [(set (match_operand:SI 0 "register_operand" "=a")
6140 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
6142 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
6143 ; (set (match_operand:SI 3 "register_operand" "=d")
6145 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
6146 ; (clobber (reg:CC 17))]
6148 ; "div{l}\\t{%2, %0|%0, %2}"
6149 ; [(set_attr "type" "idiv")
6150 ; (set_attr "ppro_uops" "few")])
6152 ;;- Logical AND instructions
6154 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
6155 ;; Note that this excludes ah.
6158 (define_insn "testsi_1"
6161 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%*a,r,rm")
6162 (match_operand:SI 1 "nonmemory_operand" "in,in,rin"))
6164 "ix86_match_ccmode (insn, CCNOmode)"
6165 "test{l}\\t{%1, %0|%0, %1}"
6166 [(set_attr "type" "test")
6167 (set_attr "modrm" "0,1,1")
6168 (set_attr "mode" "SI")
6169 (set_attr "pent_pair" "uv,np,uv")])
6171 (define_expand "testsi_ccno_1"
6174 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
6175 (match_operand:SI 1 "nonmemory_operand" ""))
6180 (define_insn "*testhi_1"
6182 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%*a,r,rm")
6183 (match_operand:HI 1 "nonmemory_operand" "n,n,rn"))
6185 "ix86_match_ccmode (insn, CCNOmode)"
6186 "test{w}\\t{%1, %0|%0, %1}"
6187 [(set_attr "type" "test")
6188 (set_attr "modrm" "0,1,1")
6189 (set_attr "mode" "HI")
6190 (set_attr "pent_pair" "uv,np,uv")])
6192 (define_expand "testqi_ccz_1"
6194 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
6195 (match_operand:QI 1 "nonmemory_operand" ""))
6200 (define_insn "*testqi_1"
6202 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
6203 (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
6205 "ix86_match_ccmode (insn, CCNOmode)"
6208 if (which_alternative == 3)
6210 if (GET_CODE (operands[1]) == CONST_INT
6211 && (INTVAL (operands[1]) & 0xffffff00))
6212 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
6213 return \"test{l}\\t{%1, %k0|%k0, %1}\";
6215 return \"test{b}\\t{%1, %0|%0, %1}\";
6217 [(set_attr "type" "test")
6218 (set_attr "modrm" "0,1,1,1")
6219 (set_attr "mode" "QI,QI,QI,SI")
6220 (set_attr "pent_pair" "uv,np,uv,np")])
6222 (define_expand "testqi_ext_ccno_0"
6227 (match_operand 0 "ext_register_operand" "")
6230 (match_operand 1 "const_int_operand" ""))
6235 (define_insn "*testqi_ext_0"
6240 (match_operand 0 "ext_register_operand" "q")
6243 (match_operand 1 "const_int_operand" "n"))
6245 "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff
6246 && ix86_match_ccmode (insn, CCNOmode)"
6247 "test{b}\\t{%1, %h0|%h0, %1}"
6248 [(set_attr "type" "test")
6249 (set_attr "mode" "QI")
6250 (set_attr "length_immediate" "1")
6251 (set_attr "pent_pair" "np")])
6253 (define_insn "*testqi_ext_1"
6258 (match_operand 0 "ext_register_operand" "q")
6262 (match_operand:QI 1 "nonimmediate_operand" "qm")))
6264 "ix86_match_ccmode (insn, CCNOmode)"
6265 "test{b}\\t{%1, %h0|%h0, %1}"
6266 [(set_attr "type" "test")
6267 (set_attr "mode" "QI")])
6269 (define_insn "*testqi_ext_2"
6274 (match_operand 0 "ext_register_operand" "q")
6278 (match_operand 1 "ext_register_operand" "q")
6282 "ix86_match_ccmode (insn, CCNOmode)"
6283 "test{b}\\t{%h1, %h0|%h0, %h1}"
6284 [(set_attr "type" "test")
6285 (set_attr "mode" "QI")])
6287 ;; Combine likes to form bit extractions for some tests. Humor it.
6288 (define_insn "*testqi_ext_3"
6290 (compare (zero_extract:SI
6291 (match_operand 0 "nonimmediate_operand" "rm")
6292 (match_operand:SI 1 "const_int_operand" "")
6293 (match_operand:SI 2 "const_int_operand" ""))
6295 "ix86_match_ccmode (insn, CCNOmode)
6296 && (GET_MODE (operands[0]) == SImode
6297 || GET_MODE (operands[0]) == HImode
6298 || GET_MODE (operands[0]) == QImode)"
6303 (compare (zero_extract:SI
6304 (match_operand 0 "nonimmediate_operand" "rm")
6305 (match_operand:SI 1 "const_int_operand" "")
6306 (match_operand:SI 2 "const_int_operand" ""))
6308 "ix86_match_ccmode (insn, CCNOmode)"
6309 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
6312 HOST_WIDE_INT len = INTVAL (operands[1]);
6313 HOST_WIDE_INT pos = INTVAL (operands[2]);
6315 enum machine_mode mode;
6317 mode = GET_MODE (operands[0]);
6318 if (GET_CODE (operands[0]) == MEM)
6320 /* ??? Combine likes to put non-volatile mem extractions in QImode
6321 no matter the size of the test. So find a mode that works. */
6322 if (! MEM_VOLATILE_P (operands[0]))
6324 mode = smallest_mode_for_size (pos + len, MODE_INT);
6325 operands[0] = change_address (operands[0], mode, NULL_RTX);
6328 else if (mode == HImode && pos + len <= 8)
6330 /* Small HImode tests can be converted to QImode. */
6332 operands[0] = gen_lowpart (QImode, operands[0]);
6335 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
6336 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
6338 operands[3] = gen_rtx_AND (mode, operands[0], GEN_INT (mask));
6341 ;; %%% This used to optimize known byte-wide and operations to memory,
6342 ;; and sometimes to QImode registers. If this is considered useful,
6343 ;; it should be done with splitters.
6345 (define_expand "andsi3"
6346 [(set (match_operand:SI 0 "nonimmediate_operand" "")
6347 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
6348 (match_operand:SI 2 "general_operand" "")))
6349 (clobber (reg:CC 17))]
6351 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
6353 (define_insn "*andsi_1"
6354 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
6355 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
6356 (match_operand:SI 2 "general_operand" "ri,rm,L")))
6357 (clobber (reg:CC 17))]
6358 "ix86_binary_operator_ok (AND, SImode, operands)"
6361 switch (get_attr_type (insn))
6365 enum machine_mode mode;
6367 if (GET_CODE (operands[2]) != CONST_INT)
6369 if (INTVAL (operands[2]) == 0xff)
6371 else if (INTVAL (operands[2]) == 0xffff)
6376 operands[1] = gen_lowpart (mode, operands[1]);
6378 return \"movz{bl|x}\\t{%1,%0|%0, %1}\";
6380 return \"movz{wl|x}\\t{%1,%0|%0, %1}\";
6384 if (! rtx_equal_p (operands[0], operands[1]))
6386 return \"and{l}\\t{%2, %0|%0, %2}\";
6389 [(set_attr "type" "alu,alu,imovx")
6390 (set_attr "length_immediate" "*,*,0")
6391 (set_attr "mode" "SI")])
6394 [(set (match_operand:SI 0 "register_operand" "")
6395 (and:SI (match_dup 0)
6396 (const_int -65536)))
6397 (clobber (reg:CC 17))]
6399 [(set (strict_low_part (match_dup 1)) (const_int 0))]
6400 "operands[1] = gen_lowpart (HImode, operands[0]);")
6403 [(set (match_operand 0 "q_regs_operand" "")
6406 (clobber (reg:CC 17))]
6407 "(optimize_size || !TARGET_PARTIAL_REG_STALL)
6408 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode)"
6409 [(set (strict_low_part (match_dup 1)) (const_int 0))]
6410 "operands[1] = gen_lowpart (QImode, operands[0]);")
6413 [(set (match_operand 0 "q_regs_operand" "")
6415 (const_int -65281)))
6416 (clobber (reg:CC 17))]
6417 "(optimize_size || !TARGET_PARTIAL_REG_STALL)
6418 && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode)"
6419 [(parallel [(set (zero_extract:SI (match_dup 0)
6423 (zero_extract:SI (match_dup 0)
6426 (zero_extract:SI (match_dup 0)
6429 (clobber (reg:CC 17))])]
6430 "operands[0] = gen_lowpart (SImode, operands[0]);")
6432 (define_insn "*andsi_2"
6434 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
6435 (match_operand:SI 2 "general_operand" "rim,ri"))
6437 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
6438 (and:SI (match_dup 1) (match_dup 2)))]
6439 "ix86_match_ccmode (insn, CCNOmode)
6440 && ix86_binary_operator_ok (AND, SImode, operands)"
6441 "and{l}\\t{%2, %0|%0, %2}"
6442 [(set_attr "type" "alu")
6443 (set_attr "mode" "SI")])
6445 (define_expand "andhi3"
6446 [(set (match_operand:HI 0 "nonimmediate_operand" "")
6447 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
6448 (match_operand:HI 2 "general_operand" "")))
6449 (clobber (reg:CC 17))]
6450 "TARGET_HIMODE_MATH"
6451 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
6453 (define_insn "*andhi_1"
6454 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6455 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
6456 (match_operand:HI 2 "general_operand" "ri,rm,L")))
6457 (clobber (reg:CC 17))]
6458 "ix86_binary_operator_ok (AND, HImode, operands)"
6461 switch (get_attr_type (insn))
6464 if (GET_CODE (operands[2]) != CONST_INT)
6466 if (INTVAL (operands[2]) == 0xff)
6467 return \"movz{bl|x}\\t{%b1, %k0|%k0, %b1}\";
6471 if (! rtx_equal_p (operands[0], operands[1]))
6474 return \"and{w}\\t{%2, %0|%0, %2}\";
6477 [(set_attr "type" "alu,alu,imovx")
6478 (set_attr "length_immediate" "*,*,0")
6479 (set_attr "mode" "HI,HI,SI")])
6481 (define_insn "*andhi_2"
6483 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6484 (match_operand:HI 2 "general_operand" "rim,ri"))
6486 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6487 (and:HI (match_dup 1) (match_dup 2)))]
6488 "ix86_match_ccmode (insn, CCNOmode)
6489 && ix86_binary_operator_ok (AND, HImode, operands)"
6490 "and{w}\\t{%2, %0|%0, %2}"
6491 [(set_attr "type" "alu")
6492 (set_attr "mode" "HI")])
6494 (define_expand "andqi3"
6495 [(set (match_operand:QI 0 "nonimmediate_operand" "")
6496 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
6497 (match_operand:QI 2 "general_operand" "")))
6498 (clobber (reg:CC 17))]
6499 "TARGET_QIMODE_MATH"
6500 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
6502 ;; %%% Potential partial reg stall on alternative 2. What to do?
6503 (define_insn "*andqi_1"
6504 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6505 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6506 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
6507 (clobber (reg:CC 17))]
6508 "ix86_binary_operator_ok (AND, QImode, operands)"
6510 and{b}\\t{%2, %0|%0, %2}
6511 and{b}\\t{%2, %0|%0, %2}
6512 and{l}\\t{%k2, %k0|%k0, %k2}"
6513 [(set_attr "type" "alu")
6514 (set_attr "mode" "QI,QI,SI")])
6516 (define_insn "*andqi_1_slp"
6517 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6518 (and:QI (match_dup 0)
6519 (match_operand:QI 1 "general_operand" "qi,qmi")))
6520 (clobber (reg:CC 17))]
6522 "and{b}\\t{%1, %0|%0, %1}"
6523 [(set_attr "type" "alu1")
6524 (set_attr "mode" "QI")])
6526 (define_insn "*andqi_2"
6529 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6530 (match_operand:QI 2 "general_operand" "qim,qi,i"))
6532 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
6533 (and:QI (match_dup 1) (match_dup 2)))]
6534 "ix86_match_ccmode (insn, CCNOmode)
6535 && ix86_binary_operator_ok (AND, QImode, operands)"
6538 if (which_alternative == 2)
6540 if (GET_CODE (operands[2]) == CONST_INT
6541 && (INTVAL (operands[2]) & 0xffffff00))
6542 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
6543 return \"and{l}\\t{%2, %k0|%k0, %2}\";
6545 return \"and{b}\\t{%2, %0|%0, %2}\";
6547 [(set_attr "type" "alu")
6548 (set_attr "mode" "QI,QI,SI")])
6550 (define_insn "*andqi_2_slp"
6553 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
6554 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
6556 (set (strict_low_part (match_dup 0))
6557 (and:QI (match_dup 0) (match_dup 1)))]
6558 "ix86_match_ccmode (insn, CCNOmode)"
6559 "and{b}\\t{%1, %0|%0, %1}"
6560 [(set_attr "type" "alu1")
6561 (set_attr "mode" "QI")])
6563 ;; ??? A bug in recog prevents it from recognizing a const_int as an
6564 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
6565 ;; for a QImode operand, which of course failed.
6567 (define_insn "andqi_ext_0"
6568 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
6573 (match_operand 1 "ext_register_operand" "0")
6576 (match_operand 2 "const_int_operand" "n")))
6577 (clobber (reg:CC 17))]
6578 "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
6579 "and{b}\\t{%2, %h0|%h0, %2}"
6580 [(set_attr "type" "alu")
6581 (set_attr "length_immediate" "1")
6582 (set_attr "mode" "QI")])
6584 ;; Generated by peephole translating test to and. This shows up
6585 ;; often in fp comparisons.
6587 (define_insn "*andqi_ext_0_cc"
6592 (match_operand 1 "ext_register_operand" "0")
6595 (match_operand 2 "const_int_operand" "n"))
6597 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
6606 "ix86_match_ccmode (insn, CCNOmode)
6607 && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
6608 "and{b}\\t{%2, %h0|%h0, %2}"
6609 [(set_attr "type" "alu")
6610 (set_attr "length_immediate" "1")
6611 (set_attr "mode" "QI")])
6613 (define_insn "*andqi_ext_1"
6614 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
6619 (match_operand 1 "ext_register_operand" "0")
6623 (match_operand:QI 2 "general_operand" "qm"))))
6624 (clobber (reg:CC 17))]
6626 "and{b}\\t{%2, %h0|%h0, %2}"
6627 [(set_attr "type" "alu")
6628 (set_attr "length_immediate" "0")
6629 (set_attr "mode" "QI")])
6631 (define_insn "*andqi_ext_2"
6632 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
6637 (match_operand 1 "ext_register_operand" "%0")
6641 (match_operand 2 "ext_register_operand" "q")
6644 (clobber (reg:CC 17))]
6646 "and{b}\\t{%h2, %h0|%h0, %h2}"
6647 [(set_attr "type" "alu")
6648 (set_attr "length_immediate" "0")
6649 (set_attr "mode" "QI")])
6651 ;; Logical inclusive OR instructions
6653 ;; %%% This used to optimize known byte-wide and operations to memory.
6654 ;; If this is considered useful, it should be done with splitters.
6656 (define_expand "iorsi3"
6657 [(set (match_operand:SI 0 "nonimmediate_operand" "")
6658 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
6659 (match_operand:SI 2 "general_operand" "")))
6660 (clobber (reg:CC 17))]
6662 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
6664 (define_insn "*iorsi_1"
6665 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6666 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
6667 (match_operand:SI 2 "general_operand" "ri,rmi")))
6668 (clobber (reg:CC 17))]
6669 "ix86_binary_operator_ok (IOR, SImode, operands)"
6670 "or{l}\\t{%2, %0|%0, %2}"
6671 [(set_attr "type" "alu")
6672 (set_attr "mode" "SI")])
6674 (define_insn "*iorsi_2"
6676 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
6677 (match_operand:SI 2 "general_operand" "rim,ri"))
6679 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
6680 (ior:SI (match_dup 1) (match_dup 2)))]
6681 "ix86_match_ccmode (insn, CCNOmode)
6682 && ix86_binary_operator_ok (IOR, SImode, operands)"
6683 "or{l}\\t{%2, %0|%0, %2}"
6684 [(set_attr "type" "alu")
6685 (set_attr "mode" "SI")])
6687 (define_insn "*iorsi_3"
6689 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6690 (match_operand:SI 2 "general_operand" "rim"))
6692 (clobber (match_scratch:SI 0 "=r"))]
6693 "ix86_match_ccmode (insn, CCNOmode)
6694 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6695 "or{l}\\t{%2, %0|%0, %2}"
6696 [(set_attr "type" "alu")
6697 (set_attr "mode" "SI")])
6699 (define_expand "iorhi3"
6700 [(set (match_operand:HI 0 "nonimmediate_operand" "")
6701 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
6702 (match_operand:HI 2 "general_operand" "")))
6703 (clobber (reg:CC 17))]
6704 "TARGET_HIMODE_MATH"
6705 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
6707 (define_insn "*iorhi_1"
6708 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
6709 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6710 (match_operand:HI 2 "general_operand" "rmi,ri")))
6711 (clobber (reg:CC 17))]
6712 "ix86_binary_operator_ok (IOR, HImode, operands)"
6713 "or{w}\\t{%2, %0|%0, %2}"
6714 [(set_attr "type" "alu")
6715 (set_attr "mode" "HI")])
6717 (define_insn "*iorhi_2"
6719 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6720 (match_operand:HI 2 "general_operand" "rim,ri"))
6722 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6723 (ior:HI (match_dup 1) (match_dup 2)))]
6724 "ix86_match_ccmode (insn, CCNOmode)
6725 && ix86_binary_operator_ok (IOR, HImode, operands)"
6726 "or{w}\\t{%2, %0|%0, %2}"
6727 [(set_attr "type" "alu")
6728 (set_attr "mode" "HI")])
6730 (define_insn "*iorhi_3"
6732 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6733 (match_operand:HI 2 "general_operand" "rim"))
6735 (clobber (match_scratch:HI 0 "=r"))]
6736 "ix86_match_ccmode (insn, CCNOmode)
6737 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6738 "or{w}\\t{%2, %0|%0, %2}"
6739 [(set_attr "type" "alu")
6740 (set_attr "mode" "HI")])
6742 (define_expand "iorqi3"
6743 [(set (match_operand:QI 0 "nonimmediate_operand" "")
6744 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
6745 (match_operand:QI 2 "general_operand" "")))
6746 (clobber (reg:CC 17))]
6747 "TARGET_QIMODE_MATH"
6748 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
6750 ;; %%% Potential partial reg stall on alternative 2. What to do?
6751 (define_insn "*iorqi_1"
6752 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
6753 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6754 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
6755 (clobber (reg:CC 17))]
6756 "ix86_binary_operator_ok (IOR, QImode, operands)"
6758 or{b}\\t{%2, %0|%0, %2}
6759 or{b}\\t{%2, %0|%0, %2}
6760 or{l}\\t{%k2, %k0|%k0, %k2}"
6761 [(set_attr "type" "alu")
6762 (set_attr "mode" "QI,QI,SI")])
6764 (define_insn "*iorqi_1_slp"
6765 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
6766 (ior:QI (match_dup 0)
6767 (match_operand:QI 1 "general_operand" "qmi,qi")))
6768 (clobber (reg:CC 17))]
6770 "or{b}\\t{%1, %0|%0, %1}"
6771 [(set_attr "type" "alu1")
6772 (set_attr "mode" "QI")])
6774 (define_insn "*iorqi_2"
6776 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6777 (match_operand:QI 2 "general_operand" "qim,qi"))
6779 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6780 (ior:QI (match_dup 1) (match_dup 2)))]
6781 "ix86_match_ccmode (insn, CCNOmode)
6782 && ix86_binary_operator_ok (IOR, QImode, operands)"
6783 "or{b}\\t{%2, %0|%0, %2}"
6784 [(set_attr "type" "alu")
6785 (set_attr "mode" "QI")])
6787 (define_insn "*iorqi_2_slp"
6789 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
6790 (match_operand:QI 1 "general_operand" "qim,qi"))
6792 (set (strict_low_part (match_dup 0))
6793 (ior:QI (match_dup 0) (match_dup 1)))]
6794 "ix86_match_ccmode (insn, CCNOmode)"
6795 "or{b}\\t{%1, %0|%0, %1}"
6796 [(set_attr "type" "alu1")
6797 (set_attr "mode" "QI")])
6799 (define_insn "*iorqi_3"
6801 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6802 (match_operand:QI 2 "general_operand" "qim"))
6804 (clobber (match_scratch:QI 0 "=q"))]
6805 "ix86_match_ccmode (insn, CCNOmode)
6806 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6807 "or{b}\\t{%2, %0|%0, %2}"
6808 [(set_attr "type" "alu")
6809 (set_attr "mode" "QI")])
6812 ;; Logical XOR instructions
6814 ;; %%% This used to optimize known byte-wide and operations to memory.
6815 ;; If this is considered useful, it should be done with splitters.
6817 (define_expand "xorsi3"
6818 [(set (match_operand:SI 0 "nonimmediate_operand" "")
6819 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
6820 (match_operand:SI 2 "general_operand" "")))
6821 (clobber (reg:CC 17))]
6823 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
6825 (define_insn "*xorsi_1"
6826 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6827 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
6828 (match_operand:SI 2 "general_operand" "ri,rm")))
6829 (clobber (reg:CC 17))]
6830 "ix86_binary_operator_ok (XOR, SImode, operands)"
6831 "xor{l}\\t{%2, %0|%0, %2}"
6832 [(set_attr "type" "alu")
6833 (set_attr "mode" "SI")])
6835 (define_insn "*xorsi_2"
6837 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
6838 (match_operand:SI 2 "general_operand" "rim,ri"))
6840 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
6841 (xor:SI (match_dup 1) (match_dup 2)))]
6842 "ix86_match_ccmode (insn, CCNOmode)
6843 && ix86_binary_operator_ok (XOR, SImode, operands)"
6844 "xor{l}\\t{%2, %0|%0, %2}"
6845 [(set_attr "type" "alu")
6846 (set_attr "mode" "SI")])
6848 (define_insn "*xorsi_3"
6850 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6851 (match_operand:SI 2 "general_operand" "rim"))
6853 (clobber (match_scratch:SI 0 "=r"))]
6854 "ix86_match_ccmode (insn, CCNOmode)
6855 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6856 "xor{l}\\t{%2, %0|%0, %2}"
6857 [(set_attr "type" "alu")
6858 (set_attr "mode" "SI")])
6860 (define_expand "xorhi3"
6861 [(set (match_operand:HI 0 "nonimmediate_operand" "")
6862 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
6863 (match_operand:HI 2 "general_operand" "")))
6864 (clobber (reg:CC 17))]
6865 "TARGET_HIMODE_MATH"
6866 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
6868 (define_insn "*xorhi_1"
6869 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
6870 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6871 (match_operand:HI 2 "general_operand" "rmi,ri")))
6872 (clobber (reg:CC 17))]
6873 "ix86_binary_operator_ok (XOR, HImode, operands)"
6874 "xor{w}\\t{%2, %0|%0, %2}"
6875 [(set_attr "type" "alu")
6876 (set_attr "mode" "HI")])
6878 (define_insn "*xorhi_2"
6880 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6881 (match_operand:HI 2 "general_operand" "rim,ri"))
6883 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6884 (xor:HI (match_dup 1) (match_dup 2)))]
6885 "ix86_match_ccmode (insn, CCNOmode)
6886 && ix86_binary_operator_ok (XOR, HImode, operands)"
6887 "xor{w}\\t{%2, %0|%0, %2}"
6888 [(set_attr "type" "alu")
6889 (set_attr "mode" "HI")])
6891 (define_insn "*xorhi_3"
6893 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6894 (match_operand:HI 2 "general_operand" "rim"))
6896 (clobber (match_scratch:HI 0 "=r"))]
6897 "ix86_match_ccmode (insn, CCNOmode)
6898 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6899 "xor{w}\\t{%2, %0|%0, %2}"
6900 [(set_attr "type" "alu")
6901 (set_attr "mode" "HI")])
6903 (define_expand "xorqi3"
6904 [(set (match_operand:QI 0 "nonimmediate_operand" "")
6905 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
6906 (match_operand:QI 2 "general_operand" "")))
6907 (clobber (reg:CC 17))]
6908 "TARGET_QIMODE_MATH"
6909 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
6911 ;; %%% Potential partial reg stall on alternative 2. What to do?
6912 (define_insn "*xorqi_1"
6913 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
6914 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6915 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
6916 (clobber (reg:CC 17))]
6917 "ix86_binary_operator_ok (XOR, QImode, operands)"
6919 xor{b}\\t{%2, %0|%0, %2}
6920 xor{b}\\t{%2, %0|%0, %2}
6921 xor{l}\\t{%k2, %k0|%k0, %k2}"
6922 [(set_attr "type" "alu")
6923 (set_attr "mode" "QI,QI,SI")])
6925 (define_insn "*xorqi_ext_1"
6926 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
6930 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
6933 (zero_extract:SI (match_operand 2 "ext_register_operand" "q")
6936 (clobber (reg:CC 17))]
6938 "xor{b}\\t{%h2, %h0|%h0, %h2}"
6939 [(set_attr "type" "alu")
6940 (set_attr "length_immediate" "0")
6941 (set_attr "mode" "QI")])
6943 (define_insn "*xorqi_cc_1"
6946 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6947 (match_operand:QI 2 "general_operand" "qim,qi"))
6949 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6950 (xor:QI (match_dup 1) (match_dup 2)))]
6951 "ix86_match_ccmode (insn, CCNOmode)
6952 && ix86_binary_operator_ok (XOR, QImode, operands)"
6953 "xor{b}\\t{%2, %0|%0, %2}"
6954 [(set_attr "type" "alu")
6955 (set_attr "mode" "QI")])
6957 (define_insn "*xorqi_cc_2"
6960 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6961 (match_operand:QI 2 "general_operand" "qim"))
6963 (clobber (match_scratch:QI 0 "=q"))]
6964 "ix86_match_ccmode (insn, CCNOmode)
6965 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6966 "xor{b}\\t{%2, %0|%0, %2}"
6967 [(set_attr "type" "alu")
6968 (set_attr "mode" "QI")])
6970 (define_insn "*xorqi_cc_ext_1"
6975 (match_operand 1 "ext_register_operand" "0")
6978 (match_operand:QI 2 "general_operand" "qmn"))
6980 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
6984 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
6986 "ix86_match_ccmode (insn, CCNOmode)"
6987 "xor{b}\\t{%2, %h0|%h0, %2}"
6988 [(set_attr "type" "alu")
6989 (set_attr "mode" "QI")])
6991 (define_expand "xorqi_cc_ext_1"
6997 (match_operand 1 "ext_register_operand" "")
7000 (match_operand:QI 2 "general_operand" ""))
7002 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
7006 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
7011 ;; Negation instructions
7013 ;; %%% define_expand from the very first?
7015 (define_expand "negdi2"
7016 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
7017 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
7018 (clobber (reg:CC 17))])]
7020 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
7022 (define_insn "*negdi2_1"
7023 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
7024 (neg:DI (match_operand:DI 1 "general_operand" "0")))
7025 (clobber (reg:CC 17))]
7026 "ix86_unary_operator_ok (NEG, DImode, operands)"
7030 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7031 (neg:DI (match_operand:DI 1 "general_operand" "")))
7032 (clobber (reg:CC 17))]
7036 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
7037 (set (match_dup 0) (neg:SI (match_dup 2)))])
7040 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
7043 (clobber (reg:CC 17))])
7046 (neg:SI (match_dup 1)))
7047 (clobber (reg:CC 17))])]
7048 "split_di (operands+1, 1, operands+2, operands+3);
7049 split_di (operands+0, 1, operands+0, operands+1);")
7051 (define_expand "negsi2"
7052 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
7053 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
7054 (clobber (reg:CC 17))])]
7056 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
7058 (define_insn "*negsi2_1"
7059 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
7060 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
7061 (clobber (reg:CC 17))]
7062 "ix86_unary_operator_ok (NEG, SImode, operands)"
7064 [(set_attr "type" "negnot")
7065 (set_attr "mode" "SI")])
7067 ;; The problem with neg is that it does not perform (compare x 0),
7068 ;; it really performs (compare 0 x), which leaves us with the zero
7069 ;; flag being the only useful item.
7071 (define_insn "*negsi2_cmpz"
7073 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
7075 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
7076 (neg:SI (match_dup 1)))]
7077 "ix86_unary_operator_ok (NEG, SImode, operands)"
7079 [(set_attr "type" "negnot")
7080 (set_attr "mode" "SI")])
7082 (define_expand "neghi2"
7083 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7084 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
7085 (clobber (reg:CC 17))])]
7086 "TARGET_HIMODE_MATH"
7087 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
7089 (define_insn "*neghi2_1"
7090 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
7091 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
7092 (clobber (reg:CC 17))]
7093 "ix86_unary_operator_ok (NEG, HImode, operands)"
7095 [(set_attr "type" "negnot")
7096 (set_attr "mode" "HI")])
7098 (define_insn "*neghi2_cmpz"
7100 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
7102 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
7103 (neg:HI (match_dup 1)))]
7104 "ix86_unary_operator_ok (NEG, HImode, operands)"
7106 [(set_attr "type" "negnot")
7107 (set_attr "mode" "HI")])
7109 (define_expand "negqi2"
7110 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7111 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
7112 (clobber (reg:CC 17))])]
7113 "TARGET_QIMODE_MATH"
7114 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
7116 (define_insn "*negqi2_1"
7117 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
7118 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
7119 (clobber (reg:CC 17))]
7120 "ix86_unary_operator_ok (NEG, QImode, operands)"
7122 [(set_attr "type" "negnot")
7123 (set_attr "mode" "QI")])
7125 (define_insn "*negqi2_cmpz"
7127 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
7129 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
7130 (neg:QI (match_dup 1)))]
7131 "ix86_unary_operator_ok (NEG, QImode, operands)"
7133 [(set_attr "type" "negnot")
7134 (set_attr "mode" "QI")])
7136 ;; Changing of sign for FP values is doable using integer unit too.
7138 (define_expand "negsf2"
7139 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
7140 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
7141 (clobber (reg:CC 17))])]
7143 "ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
7145 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
7146 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
7148 (define_insn "*negsf2_if"
7149 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
7150 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
7151 (clobber (reg:CC 17))]
7152 "TARGET_80387 && ix86_unary_operator_ok (NEG, SFmode, operands)"
7156 [(set (match_operand:SF 0 "register_operand" "")
7157 (neg:SF (match_operand:SF 1 "register_operand" "")))
7158 (clobber (reg:CC 17))]
7159 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
7161 (neg:SF (match_dup 1)))]
7165 [(set (match_operand:SF 0 "register_operand" "")
7166 (neg:SF (match_operand:SF 1 "register_operand" "")))
7167 (clobber (reg:CC 17))]
7168 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
7169 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
7170 (clobber (reg:CC 17))])]
7171 "operands[1] = GEN_INT (0x80000000);
7172 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
7175 [(set (match_operand 0 "memory_operand" "")
7176 (neg (match_operand 1 "memory_operand" "")))
7177 (clobber (reg:CC 17))]
7178 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
7179 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
7180 (clobber (reg:CC 17))])]
7183 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
7185 /* XFmode's size is 12, but only 10 bytes are used. */
7188 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
7189 operands[0] = adj_offsettable_operand (operands[0], size - 1);
7190 operands[1] = GEN_INT (0x80);
7193 (define_expand "negdf2"
7194 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
7195 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
7196 (clobber (reg:CC 17))])]
7198 "ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
7200 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
7201 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
7203 (define_insn "*negdf2_if"
7204 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
7205 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
7206 (clobber (reg:CC 17))]
7207 "TARGET_80387 && ix86_unary_operator_ok (NEG, DFmode, operands)"
7211 [(set (match_operand:DF 0 "register_operand" "")
7212 (neg:DF (match_operand:DF 1 "register_operand" "")))
7213 (clobber (reg:CC 17))]
7214 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
7216 (neg:DF (match_dup 1)))]
7220 [(set (match_operand:DF 0 "register_operand" "")
7221 (neg:DF (match_operand:DF 1 "register_operand" "")))
7222 (clobber (reg:CC 17))]
7223 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
7224 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
7225 (clobber (reg:CC 17))])]
7226 "operands[4] = GEN_INT (0x80000000);
7227 split_di (operands+0, 1, operands+2, operands+3);")
7229 (define_expand "negxf2"
7230 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
7231 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
7232 (clobber (reg:CC 17))])]
7234 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
7236 (define_expand "negtf2"
7237 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7238 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
7239 (clobber (reg:CC 17))])]
7241 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
7243 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
7244 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
7246 (define_insn "*negxf2_if"
7247 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
7248 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
7249 (clobber (reg:CC 17))]
7250 "TARGET_80387 && ix86_unary_operator_ok (NEG, XFmode, operands)"
7254 [(set (match_operand:XF 0 "register_operand" "")
7255 (neg:XF (match_operand:XF 1 "register_operand" "")))
7256 (clobber (reg:CC 17))]
7257 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
7259 (neg:XF (match_dup 1)))]
7263 [(set (match_operand:XF 0 "register_operand" "")
7264 (neg:XF (match_operand:XF 1 "register_operand" "")))
7265 (clobber (reg:CC 17))]
7266 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
7267 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
7268 (clobber (reg:CC 17))])]
7269 "operands[1] = GEN_INT (0x8000);
7270 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
7272 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
7273 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
7275 (define_insn "*negtf2_if"
7276 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
7277 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
7278 (clobber (reg:CC 17))]
7279 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
7283 [(set (match_operand:TF 0 "register_operand" "")
7284 (neg:TF (match_operand:TF 1 "register_operand" "")))
7285 (clobber (reg:CC 17))]
7286 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
7288 (neg:TF (match_dup 1)))]
7292 [(set (match_operand:TF 0 "register_operand" "")
7293 (neg:TF (match_operand:TF 1 "register_operand" "")))
7294 (clobber (reg:CC 17))]
7295 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
7296 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
7297 (clobber (reg:CC 17))])]
7298 "operands[1] = GEN_INT (0x8000);
7299 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
7301 ;; Conditionize these after reload. If they matches before reload, we
7302 ;; lose the clobber and ability to use integer instructions.
7304 (define_insn "*negsf2_1"
7305 [(set (match_operand:SF 0 "register_operand" "=f")
7306 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
7307 "TARGET_80387 && reload_completed"
7309 [(set_attr "type" "fsgn")
7310 (set_attr "mode" "SF")
7311 (set_attr "ppro_uops" "few")])
7313 (define_insn "*negdf2_1"
7314 [(set (match_operand:DF 0 "register_operand" "=f")
7315 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
7316 "TARGET_80387 && reload_completed"
7318 [(set_attr "type" "fsgn")
7319 (set_attr "mode" "DF")
7320 (set_attr "ppro_uops" "few")])
7322 (define_insn "*negextendsfdf2"
7323 [(set (match_operand:DF 0 "register_operand" "=f")
7324 (neg:DF (float_extend:DF
7325 (match_operand:SF 1 "register_operand" "0"))))]
7328 [(set_attr "type" "fsgn")
7329 (set_attr "mode" "DF")
7330 (set_attr "ppro_uops" "few")])
7332 (define_insn "*negxf2_1"
7333 [(set (match_operand:XF 0 "register_operand" "=f")
7334 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
7335 "TARGET_80387 && reload_completed"
7337 [(set_attr "type" "fsgn")
7338 (set_attr "mode" "XF")
7339 (set_attr "ppro_uops" "few")])
7341 (define_insn "*negextenddfxf2"
7342 [(set (match_operand:XF 0 "register_operand" "=f")
7343 (neg:XF (float_extend:XF
7344 (match_operand:DF 1 "register_operand" "0"))))]
7347 [(set_attr "type" "fsgn")
7348 (set_attr "mode" "XF")
7349 (set_attr "ppro_uops" "few")])
7351 (define_insn "*negextendsfxf2"
7352 [(set (match_operand:XF 0 "register_operand" "=f")
7353 (neg:XF (float_extend:XF
7354 (match_operand:SF 1 "register_operand" "0"))))]
7357 [(set_attr "type" "fsgn")
7358 (set_attr "mode" "XF")
7359 (set_attr "ppro_uops" "few")])
7361 (define_insn "*negtf2_1"
7362 [(set (match_operand:TF 0 "register_operand" "=f")
7363 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
7364 "TARGET_80387 && reload_completed"
7366 [(set_attr "type" "fsgn")
7367 (set_attr "mode" "XF")
7368 (set_attr "ppro_uops" "few")])
7370 (define_insn "*negextenddftf2"
7371 [(set (match_operand:TF 0 "register_operand" "=f")
7372 (neg:TF (float_extend:TF
7373 (match_operand:DF 1 "register_operand" "0"))))]
7376 [(set_attr "type" "fsgn")
7377 (set_attr "mode" "XF")
7378 (set_attr "ppro_uops" "few")])
7380 (define_insn "*negextendsftf2"
7381 [(set (match_operand:TF 0 "register_operand" "=f")
7382 (neg:TF (float_extend:TF
7383 (match_operand:SF 1 "register_operand" "0"))))]
7386 [(set_attr "type" "fsgn")
7387 (set_attr "mode" "XF")
7388 (set_attr "ppro_uops" "few")])
7390 ;; Absolute value instructions
7392 (define_expand "abssf2"
7393 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
7394 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
7395 (clobber (reg:CC 17))])]
7397 "ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
7399 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
7400 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
7402 (define_insn "*abssf2_if"
7403 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
7404 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
7405 (clobber (reg:CC 17))]
7406 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands)"
7410 [(set (match_operand:SF 0 "register_operand" "")
7411 (abs:SF (match_operand:SF 1 "register_operand" "")))
7412 (clobber (reg:CC 17))]
7413 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0]))"
7415 (abs:SF (match_dup 1)))]
7419 [(set (match_operand:SF 0 "register_operand" "")
7420 (abs:SF (match_operand:SF 1 "register_operand" "")))
7421 (clobber (reg:CC 17))]
7422 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
7423 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
7424 (clobber (reg:CC 17))])]
7425 "operands[1] = GEN_INT (~0x80000000);
7426 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));")
7429 [(set (match_operand 0 "memory_operand" "")
7430 (abs (match_operand 1 "memory_operand" "")))
7431 (clobber (reg:CC 17))]
7432 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
7433 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
7434 (clobber (reg:CC 17))])]
7437 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
7439 /* XFmode's size is 12, but only 10 bytes are used. */
7442 operands[0] = gen_rtx_MEM (QImode, XEXP (operands[0], 0));
7443 operands[0] = adj_offsettable_operand (operands[0], size - 1);
7444 operands[1] = GEN_INT (~0x80);
7447 (define_expand "absdf2"
7448 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
7449 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
7450 (clobber (reg:CC 17))])]
7452 "ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
7454 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
7455 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
7457 (define_insn "*absdf2_if"
7458 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
7459 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
7460 (clobber (reg:CC 17))]
7461 "TARGET_80387 && ix86_unary_operator_ok (ABS, DFmode, operands)"
7465 [(set (match_operand:DF 0 "register_operand" "")
7466 (abs:DF (match_operand:DF 1 "register_operand" "")))
7467 (clobber (reg:CC 17))]
7468 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
7470 (abs:DF (match_dup 1)))]
7474 [(set (match_operand:DF 0 "register_operand" "")
7475 (abs:DF (match_operand:DF 1 "register_operand" "")))
7476 (clobber (reg:CC 17))]
7477 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
7478 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
7479 (clobber (reg:CC 17))])]
7480 "operands[4] = GEN_INT (~0x80000000);
7481 split_di (operands+0, 1, operands+2, operands+3);")
7483 (define_expand "absxf2"
7484 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
7485 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
7486 (clobber (reg:CC 17))])]
7488 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
7490 (define_expand "abstf2"
7491 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
7492 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
7493 (clobber (reg:CC 17))])]
7495 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
7497 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
7498 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
7500 (define_insn "*absxf2_if"
7501 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
7502 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
7503 (clobber (reg:CC 17))]
7504 "TARGET_80387 && ix86_unary_operator_ok (ABS, XFmode, operands)"
7508 [(set (match_operand:XF 0 "register_operand" "")
7509 (abs:XF (match_operand:XF 1 "register_operand" "")))
7510 (clobber (reg:CC 17))]
7511 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
7513 (abs:XF (match_dup 1)))]
7517 [(set (match_operand:XF 0 "register_operand" "")
7518 (abs:XF (match_operand:XF 1 "register_operand" "")))
7519 (clobber (reg:CC 17))]
7520 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
7521 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
7522 (clobber (reg:CC 17))])]
7523 "operands[1] = GEN_INT (~0x8000);
7524 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
7526 (define_insn "*abstf2_if"
7527 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
7528 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
7529 (clobber (reg:CC 17))]
7530 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
7534 [(set (match_operand:TF 0 "register_operand" "")
7535 (abs:TF (match_operand:TF 1 "register_operand" "")))
7536 (clobber (reg:CC 17))]
7537 "TARGET_80387 && FP_REGNO_P (REGNO (operands[0])) && reload_completed"
7539 (abs:TF (match_dup 1)))]
7543 [(set (match_operand:TF 0 "register_operand" "")
7544 (abs:TF (match_operand:TF 1 "register_operand" "")))
7545 (clobber (reg:CC 17))]
7546 "TARGET_80387 && reload_completed && !FP_REGNO_P (REGNO (operands[0]))"
7547 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
7548 (clobber (reg:CC 17))])]
7549 "operands[1] = GEN_INT (~0x8000);
7550 operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]) + 2);")
7552 (define_insn "*abssf2_1"
7553 [(set (match_operand:SF 0 "register_operand" "=f")
7554 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
7555 "TARGET_80387 && reload_completed"
7557 [(set_attr "type" "fsgn")
7558 (set_attr "mode" "SF")])
7560 (define_insn "*absdf2_1"
7561 [(set (match_operand:DF 0 "register_operand" "=f")
7562 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
7563 "TARGET_80387 && reload_completed"
7565 [(set_attr "type" "fsgn")
7566 (set_attr "mode" "DF")])
7568 (define_insn "*absextendsfdf2"
7569 [(set (match_operand:DF 0 "register_operand" "=f")
7570 (abs:DF (float_extend:DF
7571 (match_operand:SF 1 "register_operand" "0"))))]
7574 [(set_attr "type" "fsgn")
7575 (set_attr "mode" "DF")])
7577 (define_insn "*absxf2_1"
7578 [(set (match_operand:XF 0 "register_operand" "=f")
7579 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
7580 "TARGET_80387 && reload_completed"
7582 [(set_attr "type" "fsgn")
7583 (set_attr "mode" "DF")])
7585 (define_insn "*absextenddfxf2"
7586 [(set (match_operand:XF 0 "register_operand" "=f")
7587 (abs:XF (float_extend:XF
7588 (match_operand:DF 1 "register_operand" "0"))))]
7591 [(set_attr "type" "fsgn")
7592 (set_attr "mode" "XF")])
7594 (define_insn "*absextendsfxf2"
7595 [(set (match_operand:XF 0 "register_operand" "=f")
7596 (abs:XF (float_extend:XF
7597 (match_operand:SF 1 "register_operand" "0"))))]
7600 [(set_attr "type" "fsgn")
7601 (set_attr "mode" "XF")])
7603 (define_insn "*abstf2_1"
7604 [(set (match_operand:TF 0 "register_operand" "=f")
7605 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
7606 "TARGET_80387 && reload_completed"
7608 [(set_attr "type" "fsgn")
7609 (set_attr "mode" "DF")])
7611 (define_insn "*absextenddftf2"
7612 [(set (match_operand:TF 0 "register_operand" "=f")
7613 (abs:TF (float_extend:TF
7614 (match_operand:DF 1 "register_operand" "0"))))]
7617 [(set_attr "type" "fsgn")
7618 (set_attr "mode" "XF")])
7620 (define_insn "*absextendsftf2"
7621 [(set (match_operand:TF 0 "register_operand" "=f")
7622 (abs:TF (float_extend:TF
7623 (match_operand:SF 1 "register_operand" "0"))))]
7626 [(set_attr "type" "fsgn")
7627 (set_attr "mode" "XF")])
7629 ;; One complement instructions
7631 (define_expand "one_cmplsi2"
7632 [(set (match_operand:SI 0 "nonimmediate_operand" "")
7633 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
7635 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
7637 (define_insn "*one_cmplsi2_1"
7638 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
7639 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
7640 "ix86_unary_operator_ok (NOT, SImode, operands)"
7642 [(set_attr "type" "negnot")
7643 (set_attr "mode" "SI")])
7645 (define_insn "*one_cmplsi2_2"
7647 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
7649 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
7650 (not:SI (match_dup 1)))]
7651 "ix86_match_ccmode (insn, CCNOmode)
7652 && ix86_unary_operator_ok (NOT, SImode, operands)"
7654 [(set_attr "type" "alu1")
7655 (set_attr "mode" "SI")])
7659 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
7661 (set (match_operand:SI 0 "nonimmediate_operand" "")
7662 (not:SI (match_dup 1)))]
7663 "ix86_match_ccmode (insn, CCNOmode)"
7664 [(parallel [(set (reg:CCNO 17)
7665 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
7668 (xor:SI (match_dup 1) (const_int -1)))])]
7671 (define_expand "one_cmplhi2"
7672 [(set (match_operand:HI 0 "nonimmediate_operand" "")
7673 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
7674 "TARGET_HIMODE_MATH"
7675 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
7677 (define_insn "*one_cmplhi2_1"
7678 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
7679 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
7680 "ix86_unary_operator_ok (NOT, HImode, operands)"
7682 [(set_attr "type" "negnot")
7683 (set_attr "mode" "HI")])
7685 (define_insn "*one_cmplhi2_2"
7687 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
7689 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
7690 (not:HI (match_dup 1)))]
7691 "ix86_match_ccmode (insn, CCNOmode)
7692 && ix86_unary_operator_ok (NEG, HImode, operands)"
7694 [(set_attr "type" "alu1")
7695 (set_attr "mode" "HI")])
7699 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
7701 (set (match_operand:HI 0 "nonimmediate_operand" "")
7702 (not:HI (match_dup 1)))]
7703 "ix86_match_ccmode (insn, CCNOmode)"
7704 [(parallel [(set (reg:CCNO 17)
7705 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
7708 (xor:HI (match_dup 1) (const_int -1)))])]
7711 ;; %%% Potential partial reg stall on alternative 1. What to do?
7712 (define_expand "one_cmplqi2"
7713 [(set (match_operand:QI 0 "nonimmediate_operand" "")
7714 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
7715 "TARGET_QIMODE_MATH"
7716 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
7718 (define_insn "*one_cmplqi2_1"
7719 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
7720 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
7721 "ix86_unary_operator_ok (NOT, QImode, operands)"
7725 [(set_attr "type" "negnot")
7726 (set_attr "mode" "QI,SI")])
7728 (define_insn "*one_cmplqi2_2"
7730 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
7732 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
7733 (not:QI (match_dup 1)))]
7734 "ix86_match_ccmode (insn, CCNOmode)
7735 && ix86_unary_operator_ok (NOT, QImode, operands)"
7737 [(set_attr "type" "alu1")
7738 (set_attr "mode" "QI")])
7742 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
7744 (set (match_operand:QI 0 "nonimmediate_operand" "")
7745 (not:QI (match_dup 1)))]
7746 "ix86_match_ccmode (insn, CCNOmode)"
7747 [(parallel [(set (reg:CCNO 17)
7748 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
7751 (xor:QI (match_dup 1) (const_int -1)))])]
7754 ;; Arithmetic shift instructions
7756 ;; DImode shifts are implemented using the i386 "shift double" opcode,
7757 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
7758 ;; is variable, then the count is in %cl and the "imm" operand is dropped
7759 ;; from the assembler input.
7761 ;; This instruction shifts the target reg/mem as usual, but instead of
7762 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
7763 ;; is a left shift double, bits are taken from the high order bits of
7764 ;; reg, else if the insn is a shift right double, bits are taken from the
7765 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
7766 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
7768 ;; Since sh[lr]d does not change the `reg' operand, that is done
7769 ;; separately, making all shifts emit pairs of shift double and normal
7770 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
7771 ;; support a 63 bit shift, each shift where the count is in a reg expands
7772 ;; to a pair of shifts, a branch, a shift by 32 and a label.
7774 ;; If the shift count is a constant, we need never emit more than one
7775 ;; shift pair, instead using moves and sign extension for counts greater
7778 (define_expand "ashldi3"
7779 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
7780 (ashift:DI (match_operand:DI 1 "register_operand" "0")
7781 (match_operand:QI 2 "nonmemory_operand" "Jc")))
7782 (clobber (reg:CC 17))])]
7786 if (TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
7788 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
7793 (define_insn "ashldi3_1"
7794 [(set (match_operand:DI 0 "register_operand" "=r")
7795 (ashift:DI (match_operand:DI 1 "register_operand" "0")
7796 (match_operand:QI 2 "nonmemory_operand" "Jc")))
7797 (clobber (match_scratch:SI 3 "=&r"))
7798 (clobber (reg:CC 17))]
7801 [(set_attr "type" "multi")])
7803 (define_insn "*ashldi3_2"
7804 [(set (match_operand:DI 0 "register_operand" "=r")
7805 (ashift:DI (match_operand:DI 1 "register_operand" "0")
7806 (match_operand:QI 2 "nonmemory_operand" "Jc")))
7807 (clobber (reg:CC 17))]
7810 [(set_attr "type" "multi")])
7813 [(set (match_operand:DI 0 "register_operand" "")
7814 (ashift:DI (match_operand:DI 1 "register_operand" "")
7815 (match_operand:QI 2 "nonmemory_operand" "")))
7816 (clobber (match_scratch:SI 3 ""))
7817 (clobber (reg:CC 17))]
7818 "TARGET_CMOVE && reload_completed"
7820 "ix86_split_ashldi (operands, operands[3]); DONE;")
7823 [(set (match_operand:DI 0 "register_operand" "")
7824 (ashift:DI (match_operand:DI 1 "register_operand" "")
7825 (match_operand:QI 2 "nonmemory_operand" "")))
7826 (clobber (reg:CC 17))]
7829 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
7831 (define_insn "x86_shld_1"
7832 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
7833 (ior:SI (ashift:SI (match_dup 0)
7834 (match_operand:QI 2 "nonmemory_operand" "I,c"))
7835 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
7836 (minus:QI (const_int 32) (match_dup 2)))))
7837 (clobber (reg:CC 17))]
7840 shld{l}\\t{%2, %1, %0|%0, %1, %2}
7841 shld{l}\\t{%s2%1, %0|%0, %1, %2}"
7842 [(set_attr "type" "ishift")
7843 (set_attr "prefix_0f" "1")
7844 (set_attr "mode" "SI")
7845 (set_attr "pent_pair" "np")
7846 (set_attr "athlon_decode" "vector")
7847 (set_attr "ppro_uops" "few")])
7849 (define_expand "x86_shift_adj_1"
7851 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
7854 (set (match_operand:SI 0 "register_operand" "")
7855 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
7856 (match_operand:SI 1 "register_operand" "")
7859 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
7860 (match_operand:SI 3 "register_operand" "r")
7865 (define_expand "x86_shift_adj_2"
7866 [(use (match_operand:SI 0 "register_operand" ""))
7867 (use (match_operand:SI 1 "register_operand" ""))
7868 (use (match_operand:QI 2 "register_operand" ""))]
7872 rtx label = gen_label_rtx ();
7875 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
7877 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
7878 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
7879 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
7880 gen_rtx_LABEL_REF (VOIDmode, label),
7882 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
7883 JUMP_LABEL (tmp) = label;
7885 emit_move_insn (operands[0], operands[1]);
7886 emit_move_insn (operands[1], const0_rtx);
7889 LABEL_NUSES (label) = 1;
7894 (define_expand "ashlsi3"
7895 [(set (match_operand:SI 0 "nonimmediate_operand" "")
7896 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
7897 (match_operand:QI 2 "nonmemory_operand" "")))
7898 (clobber (reg:CC 17))]
7900 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
7902 (define_insn "*ashlsi3_1"
7903 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7904 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
7905 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
7906 (clobber (reg:CC 17))]
7907 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
7910 switch (get_attr_type (insn))
7913 if (operands[2] != const1_rtx)
7915 if (!rtx_equal_p (operands[0], operands[1]))
7917 return \"add{l}\\t{%0, %0|%0, %0}\";
7920 if (GET_CODE (operands[2]) != CONST_INT
7921 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
7923 operands[1] = gen_rtx_MULT (SImode, operands[1],
7924 GEN_INT (1 << INTVAL (operands[2])));
7925 return \"lea{l}\\t{%a1, %0|%0, %a1}\";
7928 if (REG_P (operands[2]))
7929 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
7930 else if (GET_CODE (operands[2]) == CONST_INT
7931 && INTVAL (operands[2]) == 1
7932 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
7933 return \"sal{l}\\t%0\";
7935 return \"sal{l}\\t{%2, %0|%0, %2}\";
7939 (cond [(eq_attr "alternative" "1")
7940 (const_string "lea")
7941 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
7943 (match_operand 0 "register_operand" ""))
7944 (match_operand 2 "const1_operand" ""))
7945 (const_string "alu")
7947 (const_string "ishift")))
7948 (set_attr "mode" "SI")])
7950 ;; Convert lea to the lea pattern to avoid flags dependency.
7952 [(set (match_operand 0 "register_operand" "")
7953 (ashift (match_operand 1 "register_operand" "")
7954 (match_operand:QI 2 "const_int_operand" "")))
7955 (clobber (reg:CC 17))]
7957 && true_regnum (operands[0]) != true_regnum (operands[1])"
7962 operands[0] = gen_lowpart (SImode, operands[0]);
7963 operands[1] = gen_lowpart (Pmode, operands[1]);
7964 operands[2] = GEN_INT (1 << INTVAL (operands[2]));
7965 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
7966 if (Pmode != SImode)
7967 pat = gen_rtx_SUBREG (SImode, pat, 0);
7968 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
7972 ;; This pattern can't accept a variable shift count, since shifts by
7973 ;; zero don't affect the flags. We assume that shifts by constant
7974 ;; zero are optimized away.
7975 (define_insn "*ashlsi3_cmp"
7978 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
7979 (match_operand:QI 2 "immediate_operand" "I"))
7981 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
7982 (ashift:SI (match_dup 1) (match_dup 2)))]
7983 "ix86_match_ccmode (insn, CCGOCmode)
7984 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
7987 switch (get_attr_type (insn))
7990 if (operands[2] != const1_rtx)
7992 return \"add{l}\\t{%0, %0|%0, %0}\";
7995 if (REG_P (operands[2]))
7996 return \"sal{l}\\t{%b2, %0|%0, %b2}\";
7997 else if (GET_CODE (operands[2]) == CONST_INT
7998 && INTVAL (operands[2]) == 1
7999 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8000 return \"sal{l}\\t%0\";
8002 return \"sal{l}\\t{%2, %0|%0, %2}\";
8006 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
8008 (match_operand 0 "register_operand" ""))
8009 (match_operand 2 "const1_operand" ""))
8010 (const_string "alu")
8012 (const_string "ishift")))
8013 (set_attr "mode" "SI")])
8015 (define_expand "ashlhi3"
8016 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8017 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
8018 (match_operand:QI 2 "nonmemory_operand" "")))
8019 (clobber (reg:CC 17))]
8020 "TARGET_HIMODE_MATH"
8021 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
8023 (define_insn "*ashlhi3_1_lea"
8024 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
8025 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
8026 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
8027 (clobber (reg:CC 17))]
8028 "!TARGET_PARTIAL_REG_STALL
8029 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
8032 switch (get_attr_type (insn))
8037 if (operands[2] != const1_rtx)
8039 return \"add{w}\\t{%0, %0|%0, %0}\";
8042 if (REG_P (operands[2]))
8043 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
8044 else if (GET_CODE (operands[2]) == CONST_INT
8045 && INTVAL (operands[2]) == 1
8046 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8047 return \"sal{w}\\t%0\";
8049 return \"sal{w}\\t{%2, %0|%0, %2}\";
8053 (cond [(eq_attr "alternative" "1")
8054 (const_string "lea")
8055 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
8057 (match_operand 0 "register_operand" ""))
8058 (match_operand 2 "const1_operand" ""))
8059 (const_string "alu")
8061 (const_string "ishift")))
8062 (set_attr "mode" "HI,SI")])
8064 (define_insn "*ashlhi3_1"
8065 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8066 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
8067 (match_operand:QI 2 "nonmemory_operand" "cI")))
8068 (clobber (reg:CC 17))]
8069 "TARGET_PARTIAL_REG_STALL
8070 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
8073 switch (get_attr_type (insn))
8076 if (operands[2] != const1_rtx)
8078 return \"add{w}\\t{%0, %0|%0, %0}\";
8081 if (REG_P (operands[2]))
8082 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
8083 else if (GET_CODE (operands[2]) == CONST_INT
8084 && INTVAL (operands[2]) == 1
8085 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8086 return \"sal{w}\\t%0\";
8088 return \"sal{w}\\t{%2, %0|%0, %2}\";
8092 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
8094 (match_operand 0 "register_operand" ""))
8095 (match_operand 2 "const1_operand" ""))
8096 (const_string "alu")
8098 (const_string "ishift")))
8099 (set_attr "mode" "HI")])
8101 ;; This pattern can't accept a variable shift count, since shifts by
8102 ;; zero don't affect the flags. We assume that shifts by constant
8103 ;; zero are optimized away.
8104 (define_insn "*ashlhi3_cmp"
8107 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
8108 (match_operand:QI 2 "immediate_operand" "I"))
8110 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8111 (ashift:HI (match_dup 1) (match_dup 2)))]
8112 "ix86_match_ccmode (insn, CCGOCmode)
8113 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
8116 switch (get_attr_type (insn))
8119 if (operands[2] != const1_rtx)
8121 return \"add{w}\\t{%0, %0|%0, %0}\";
8124 if (REG_P (operands[2]))
8125 return \"sal{w}\\t{%b2, %0|%0, %b2}\";
8126 else if (GET_CODE (operands[2]) == CONST_INT
8127 && INTVAL (operands[2]) == 1
8128 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8129 return \"sal{w}\\t%0\";
8131 return \"sal{w}\\t{%2, %0|%0, %2}\";
8135 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
8137 (match_operand 0 "register_operand" ""))
8138 (match_operand 2 "const1_operand" ""))
8139 (const_string "alu")
8141 (const_string "ishift")))
8142 (set_attr "mode" "HI")])
8144 (define_expand "ashlqi3"
8145 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8146 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
8147 (match_operand:QI 2 "nonmemory_operand" "")))
8148 (clobber (reg:CC 17))]
8149 "TARGET_QIMODE_MATH"
8150 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
8152 ;; %%% Potential partial reg stall on alternative 2. What to do?
8154 (define_insn "*ashlqi3_1_lea"
8155 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
8156 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
8157 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
8158 (clobber (reg:CC 17))]
8159 "!TARGET_PARTIAL_REG_STALL
8160 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
8163 switch (get_attr_type (insn))
8168 if (operands[2] != const1_rtx)
8170 if (NON_QI_REG_P (operands[1]))
8171 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
8173 return \"add{b}\\t{%0, %0|%0, %0}\";
8176 if (REG_P (operands[2]))
8178 if (get_attr_mode (insn) == MODE_SI)
8179 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
8181 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
8183 else if (GET_CODE (operands[2]) == CONST_INT
8184 && INTVAL (operands[2]) == 1
8185 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8187 if (get_attr_mode (insn) == MODE_SI)
8188 return \"sal{l}\\t%0\";
8190 return \"sal{b}\\t%0\";
8194 if (get_attr_mode (insn) == MODE_SI)
8195 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
8197 return \"sal{b}\\t{%2, %0|%0, %2}\";
8202 (cond [(eq_attr "alternative" "2")
8203 (const_string "lea")
8204 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
8206 (match_operand 0 "register_operand" ""))
8207 (match_operand 2 "const1_operand" ""))
8208 (const_string "alu")
8210 (const_string "ishift")))
8211 (set_attr "mode" "QI,SI,SI")])
8213 (define_insn "*ashlqi3_1"
8214 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
8215 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
8216 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
8217 (clobber (reg:CC 17))]
8218 "TARGET_PARTIAL_REG_STALL
8219 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
8222 switch (get_attr_type (insn))
8225 if (operands[2] != const1_rtx)
8227 if (NON_QI_REG_P (operands[1]))
8228 return \"add{l}\\t{%k0, %k0|%k0, %k0}\";
8230 return \"add{b}\\t{%0, %0|%0, %0}\";
8233 if (REG_P (operands[2]))
8235 if (NON_QI_REG_P (operands[1]))
8236 return \"sal{l}\\t{%b2, %k0|%k0, %b2}\";
8238 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
8240 else if (GET_CODE (operands[2]) == CONST_INT
8241 && INTVAL (operands[2]) == 1
8242 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8244 if (NON_QI_REG_P (operands[1]))
8245 return \"sal{l}\\t%0\";
8247 return \"sal{b}\\t%0\";
8251 if (NON_QI_REG_P (operands[1]))
8252 return \"sal{l}\\t{%2, %k0|%k0, %2}\";
8254 return \"sal{b}\\t{%2, %0|%0, %2}\";
8259 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
8261 (match_operand 0 "register_operand" ""))
8262 (match_operand 2 "const1_operand" ""))
8263 (const_string "alu")
8265 (const_string "ishift")))
8266 (set_attr "mode" "QI,SI")])
8268 ;; This pattern can't accept a variable shift count, since shifts by
8269 ;; zero don't affect the flags. We assume that shifts by constant
8270 ;; zero are optimized away.
8271 (define_insn "*ashlqi3_cmp"
8274 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
8275 (match_operand:QI 2 "immediate_operand" "I"))
8277 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
8278 (ashift:QI (match_dup 1) (match_dup 2)))]
8279 "ix86_match_ccmode (insn, CCGOCmode)
8280 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
8283 switch (get_attr_type (insn))
8286 if (operands[2] != const1_rtx)
8288 return \"add{b}\\t{%0, %0|%0, %0}\";
8291 if (REG_P (operands[2]))
8292 return \"sal{b}\\t{%b2, %0|%0, %b2}\";
8293 else if (GET_CODE (operands[2]) == CONST_INT
8294 && INTVAL (operands[2]) == 1
8295 && (TARGET_PENTIUM || TARGET_PENTIUMPRO))
8296 return \"sal{b}\\t%0\";
8298 return \"sal{b}\\t{%2, %0|%0, %2}\";
8302 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
8304 (match_operand 0 "register_operand" ""))
8305 (match_operand 2 "const1_operand" ""))
8306 (const_string "alu")
8308 (const_string "ishift")))
8309 (set_attr "mode" "QI")])
8311 ;; See comment above `ashldi3' about how this works.
8313 (define_expand "ashrdi3"
8314 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
8315 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8316 (match_operand:QI 2 "nonmemory_operand" "Jc")))
8317 (clobber (reg:CC 17))])]
8321 if (TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
8323 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
8328 (define_insn "ashrdi3_1"
8329 [(set (match_operand:DI 0 "register_operand" "=r")
8330 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8331 (match_operand:QI 2 "nonmemory_operand" "Jc")))
8332 (clobber (match_scratch:SI 3 "=&r"))
8333 (clobber (reg:CC 17))]
8336 [(set_attr "type" "multi")])
8338 (define_insn "*ashrdi3_2"
8339 [(set (match_operand:DI 0 "register_operand" "=r")
8340 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
8341 (match_operand:QI 2 "nonmemory_operand" "Jc")))
8342 (clobber (reg:CC 17))]
8345 [(set_attr "type" "multi")])
8348 [(set (match_operand:DI 0 "register_operand" "")
8349 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
8350 (match_operand:QI 2 "nonmemory_operand" "")))
8351 (clobber (match_scratch:SI 3 ""))
8352 (clobber (reg:CC 17))]
8353 "TARGET_CMOVE && reload_completed"
8355 "ix86_split_ashrdi (operands, operands[3]); DONE;")
8358 [(set (match_operand:DI 0 "register_operand" "")
8359 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
8360 (match_operand:QI 2 "nonmemory_operand" "")))
8361 (clobber (reg:CC 17))]
8364 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
8366 (define_insn "x86_shrd_1"
8367 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
8368 (ior:SI (ashiftrt:SI (match_dup 0)
8369 (match_operand:QI 2 "nonmemory_operand" "I,c"))
8370 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
8371 (minus:QI (const_int 32) (match_dup 2)))))
8372 (clobber (reg:CC 17))]
8375 shrd{l}\\t{%2, %1, %0|%0, %1, %2}
8376 shrd{l}\\t{%s2%1, %0|%0, %1, %2}"
8377 [(set_attr "type" "ishift")
8378 (set_attr "prefix_0f" "1")
8379 (set_attr "pent_pair" "np")
8380 (set_attr "ppro_uops" "few")
8381 (set_attr "mode" "SI")])
8383 (define_expand "x86_shift_adj_3"
8384 [(use (match_operand:SI 0 "register_operand" ""))
8385 (use (match_operand:SI 1 "register_operand" ""))
8386 (use (match_operand:QI 2 "register_operand" ""))]
8390 rtx label = gen_label_rtx ();
8393 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
8395 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
8396 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
8397 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
8398 gen_rtx_LABEL_REF (VOIDmode, label),
8400 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
8401 JUMP_LABEL (tmp) = label;
8403 emit_move_insn (operands[0], operands[1]);
8404 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
8407 LABEL_NUSES (label) = 1;
8412 (define_insn "ashrsi3_31"
8413 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
8414 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
8415 (match_operand:SI 2 "const_int_operand" "i,i")))
8416 (clobber (reg:CC 17))]
8417 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
8418 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
8421 sar{l}\\t{%2, %0|%0, %2}"
8422 [(set_attr "type" "imovx,ishift")
8423 (set_attr "prefix_0f" "0,*")
8424 (set_attr "length_immediate" "0,*")
8425 (set_attr "modrm" "0,1")
8426 (set_attr "mode" "SI")])
8428 (define_expand "ashrsi3"
8429 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8430 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
8431 (match_operand:QI 2 "nonmemory_operand" "")))
8432 (clobber (reg:CC 17))]
8434 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
8436 (define_insn "*ashrsi3_1_one_bit"
8437 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8438 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
8439 (match_operand:QI 2 "const_int_1_operand" "")))
8440 (clobber (reg:CC 17))]
8441 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
8442 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
8444 [(set_attr "type" "ishift")
8445 (set (attr "length")
8446 (if_then_else (match_operand:SI 0 "register_operand" "")
8448 (const_string "*")))])
8450 (define_insn "*ashrsi3_1"
8451 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
8452 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
8453 (match_operand:QI 2 "nonmemory_operand" "I,c")))
8454 (clobber (reg:CC 17))]
8455 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
8457 sar{l}\\t{%2, %0|%0, %2}
8458 sar{l}\\t{%b2, %0|%0, %b2}"
8459 [(set_attr "type" "ishift")
8460 (set_attr "mode" "SI")])
8462 ;; This pattern can't accept a variable shift count, since shifts by
8463 ;; zero don't affect the flags. We assume that shifts by constant
8464 ;; zero are optimized away.
8465 (define_insn "*ashrsi3_one_bit_cmp"
8468 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
8469 (match_operand:QI 2 "const_int_1_operand" ""))
8471 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8472 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
8473 "ix86_match_ccmode (insn, CCGOCmode)
8474 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
8475 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
8477 [(set_attr "type" "ishift")
8478 (set (attr "length")
8479 (if_then_else (match_operand:SI 0 "register_operand" "")
8481 (const_string "*")))])
8483 ;; This pattern can't accept a variable shift count, since shifts by
8484 ;; zero don't affect the flags. We assume that shifts by constant
8485 ;; zero are optimized away.
8486 (define_insn "*ashrsi3_cmp"
8489 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
8490 (match_operand:QI 2 "immediate_operand" "I"))
8492 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8493 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
8494 "ix86_match_ccmode (insn, CCGOCmode)
8495 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
8496 "sar{l}\\t{%2, %0|%0, %2}"
8497 [(set_attr "type" "ishift")
8498 (set_attr "mode" "SI")])
8500 (define_expand "ashrhi3"
8501 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8502 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
8503 (match_operand:QI 2 "nonmemory_operand" "")))
8504 (clobber (reg:CC 17))]
8505 "TARGET_HIMODE_MATH"
8506 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
8508 (define_insn "*ashrhi3_1_one_bit"
8509 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8510 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
8511 (match_operand:QI 2 "const_int_1_operand" "")))
8512 (clobber (reg:CC 17))]
8513 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
8514 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
8516 [(set_attr "type" "ishift")
8517 (set (attr "length")
8518 (if_then_else (match_operand:SI 0 "register_operand" "")
8520 (const_string "*")))])
8522 (define_insn "*ashrhi3_1"
8523 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
8524 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
8525 (match_operand:QI 2 "nonmemory_operand" "I,c")))
8526 (clobber (reg:CC 17))]
8527 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
8529 sar{w}\\t{%2, %0|%0, %2}
8530 sar{w}\\t{%b2, %0|%0, %b2}"
8531 [(set_attr "type" "ishift")
8532 (set_attr "mode" "HI")])
8534 ;; This pattern can't accept a variable shift count, since shifts by
8535 ;; zero don't affect the flags. We assume that shifts by constant
8536 ;; zero are optimized away.
8537 (define_insn "*ashrhi3_one_bit_cmp"
8540 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
8541 (match_operand:QI 2 "const_int_1_operand" ""))
8543 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8544 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
8545 "ix86_match_ccmode (insn, CCGOCmode)
8546 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
8547 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
8549 [(set_attr "type" "ishift")
8550 (set (attr "length")
8551 (if_then_else (match_operand:SI 0 "register_operand" "")
8553 (const_string "*")))])
8555 ;; This pattern can't accept a variable shift count, since shifts by
8556 ;; zero don't affect the flags. We assume that shifts by constant
8557 ;; zero are optimized away.
8558 (define_insn "*ashrhi3_cmp"
8561 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
8562 (match_operand:QI 2 "immediate_operand" "I"))
8564 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8565 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
8566 "ix86_match_ccmode (insn, CCGOCmode)
8567 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
8568 "sar{w}\\t{%2, %0|%0, %2}"
8569 [(set_attr "type" "ishift")
8570 (set_attr "mode" "HI")])
8572 (define_expand "ashrqi3"
8573 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8574 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
8575 (match_operand:QI 2 "nonmemory_operand" "")))
8576 (clobber (reg:CC 17))]
8577 "TARGET_QIMODE_MATH"
8578 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
8580 (define_insn "*ashrqi3_1_one_bit"
8581 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
8582 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
8583 (match_operand:QI 2 "const_int_1_operand" "")))
8584 (clobber (reg:CC 17))]
8585 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
8586 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
8588 [(set_attr "type" "ishift")
8589 (set (attr "length")
8590 (if_then_else (match_operand:SI 0 "register_operand" "")
8592 (const_string "*")))])
8594 (define_insn "*ashrqi3_1"
8595 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
8596 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
8597 (match_operand:QI 2 "nonmemory_operand" "I,c")))
8598 (clobber (reg:CC 17))]
8599 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
8601 sar{b}\\t{%2, %0|%0, %2}
8602 sar{b}\\t{%b2, %0|%0, %b2}"
8603 [(set_attr "type" "ishift")
8604 (set_attr "mode" "QI")])
8606 ;; This pattern can't accept a variable shift count, since shifts by
8607 ;; zero don't affect the flags. We assume that shifts by constant
8608 ;; zero are optimized away.
8609 (define_insn "*ashrqi3_one_bit_cmp"
8612 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
8613 (match_operand:QI 2 "const_int_1_operand" "I"))
8615 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
8616 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
8617 "ix86_match_ccmode (insn, CCGOCmode)
8618 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
8619 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
8621 [(set_attr "type" "ishift")
8622 (set (attr "length")
8623 (if_then_else (match_operand:SI 0 "register_operand" "")
8625 (const_string "*")))])
8627 ;; This pattern can't accept a variable shift count, since shifts by
8628 ;; zero don't affect the flags. We assume that shifts by constant
8629 ;; zero are optimized away.
8630 (define_insn "*ashrqi3_cmp"
8633 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
8634 (match_operand:QI 2 "immediate_operand" "I"))
8636 (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
8637 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
8638 "ix86_match_ccmode (insn, CCGOCmode)
8639 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
8640 "sar{b}\\t{%2, %0|%0, %2}"
8641 [(set_attr "type" "ishift")
8642 (set_attr "mode" "QI")])
8644 ;; Logical shift instructions
8646 ;; See comment above `ashldi3' about how this works.
8648 (define_expand "lshrdi3"
8649 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
8650 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
8651 (match_operand:QI 2 "nonmemory_operand" "Jc")))
8652 (clobber (reg:CC 17))])]
8656 if (TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
8658 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
8663 (define_insn "lshrdi3_1"
8664 [(set (match_operand:DI 0 "register_operand" "=r")
8665 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
8666 (match_operand:QI 2 "nonmemory_operand" "Jc")))
8667 (clobber (match_scratch:SI 3 "=&r"))
8668 (clobber (reg:CC 17))]
8671 [(set_attr "type" "multi")])
8673 (define_insn "*lshrdi3_2"
8674 [(set (match_operand:DI 0 "register_operand" "=r")
8675 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
8676 (match_operand:QI 2 "nonmemory_operand" "Jc")))
8677 (clobber (reg:CC 17))]
8680 [(set_attr "type" "multi")])
8683 [(set (match_operand:DI 0 "register_operand" "")
8684 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
8685 (match_operand:QI 2 "nonmemory_operand" "")))
8686 (clobber (match_scratch:SI 3 ""))
8687 (clobber (reg:CC 17))]
8688 "TARGET_CMOVE && reload_completed"
8690 "ix86_split_lshrdi (operands, operands[3]); DONE;")
8693 [(set (match_operand:DI 0 "register_operand" "")
8694 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
8695 (match_operand:QI 2 "nonmemory_operand" "")))
8696 (clobber (reg:CC 17))]
8699 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
8701 (define_expand "lshrsi3"
8702 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8703 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
8704 (match_operand:QI 2 "nonmemory_operand" "")))
8705 (clobber (reg:CC 17))]
8707 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
8709 (define_insn "*lshrsi3_1_one_bit"
8710 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8711 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
8712 (match_operand:QI 2 "const_int_1_operand" "")))
8713 (clobber (reg:CC 17))]
8714 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
8715 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
8717 [(set_attr "type" "ishift")
8718 (set (attr "length")
8719 (if_then_else (match_operand:SI 0 "register_operand" "")
8721 (const_string "*")))])
8723 (define_insn "*lshrsi3_1"
8724 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
8725 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
8726 (match_operand:QI 2 "nonmemory_operand" "I,c")))
8727 (clobber (reg:CC 17))]
8728 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
8730 shr{l}\\t{%2, %0|%0, %2}
8731 shr{l}\\t{%b2, %0|%0, %b2}"
8732 [(set_attr "type" "ishift")
8733 (set_attr "mode" "SI")])
8735 ;; This pattern can't accept a variable shift count, since shifts by
8736 ;; zero don't affect the flags. We assume that shifts by constant
8737 ;; zero are optimized away.
8738 (define_insn "*lshrsi3_one_bit_cmp"
8741 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
8742 (match_operand:QI 2 "const_int_1_operand" ""))
8744 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8745 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
8746 "ix86_match_ccmode (insn, CCGOCmode)
8747 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
8748 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
8750 [(set_attr "type" "ishift")
8751 (set (attr "length")
8752 (if_then_else (match_operand:SI 0 "register_operand" "")
8754 (const_string "*")))])
8756 ;; This pattern can't accept a variable shift count, since shifts by
8757 ;; zero don't affect the flags. We assume that shifts by constant
8758 ;; zero are optimized away.
8759 (define_insn "*lshrsi3_cmp"
8762 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
8763 (match_operand:QI 2 "immediate_operand" "I"))
8765 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8766 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
8767 "ix86_match_ccmode (insn, CCGOCmode)
8768 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
8769 "shr{l}\\t{%2, %0|%0, %2}"
8770 [(set_attr "type" "ishift")
8771 (set_attr "mode" "SI")])
8773 (define_expand "lshrhi3"
8774 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8775 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
8776 (match_operand:QI 2 "nonmemory_operand" "")))
8777 (clobber (reg:CC 17))]
8778 "TARGET_HIMODE_MATH"
8779 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
8781 (define_insn "*lshrhi3_1_one_bit"
8782 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8783 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
8784 (match_operand:QI 2 "const_int_1_operand" "")))
8785 (clobber (reg:CC 17))]
8786 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
8787 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
8789 [(set_attr "type" "ishift")
8790 (set (attr "length")
8791 (if_then_else (match_operand:SI 0 "register_operand" "")
8793 (const_string "*")))])
8795 (define_insn "*lshrhi3_1"
8796 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
8797 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
8798 (match_operand:QI 2 "nonmemory_operand" "I,c")))
8799 (clobber (reg:CC 17))]
8800 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
8802 shr{w}\\t{%2, %0|%0, %2}
8803 shr{w}\\t{%b2, %0|%0, %b2}"
8804 [(set_attr "type" "ishift")
8805 (set_attr "mode" "HI")])
8807 ;; This pattern can't accept a variable shift count, since shifts by
8808 ;; zero don't affect the flags. We assume that shifts by constant
8809 ;; zero are optimized away.
8810 (define_insn "*lshrhi3_one_bit_cmp"
8813 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
8814 (match_operand:QI 2 "const_int_1_operand" ""))
8816 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8817 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
8818 "ix86_match_ccmode (insn, CCGOCmode)
8819 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
8820 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
8822 [(set_attr "type" "ishift")
8823 (set (attr "length")
8824 (if_then_else (match_operand:SI 0 "register_operand" "")
8826 (const_string "*")))])
8828 ;; This pattern can't accept a variable shift count, since shifts by
8829 ;; zero don't affect the flags. We assume that shifts by constant
8830 ;; zero are optimized away.
8831 (define_insn "*lshrhi3_cmp"
8834 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
8835 (match_operand:QI 2 "immediate_operand" "I"))
8837 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8838 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
8839 "ix86_match_ccmode (insn, CCGOCmode)
8840 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
8841 "shr{w}\\t{%2, %0|%0, %2}"
8842 [(set_attr "type" "ishift")
8843 (set_attr "mode" "HI")])
8845 (define_expand "lshrqi3"
8846 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8847 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
8848 (match_operand:QI 2 "nonmemory_operand" "")))
8849 (clobber (reg:CC 17))]
8850 "TARGET_QIMODE_MATH"
8851 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
8853 (define_insn "*lshrqi3_1_one_bit"
8854 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
8855 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
8856 (match_operand:QI 2 "const_int_1_operand" "")))
8857 (clobber (reg:CC 17))]
8858 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
8859 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
8861 [(set_attr "type" "ishift")
8862 (set (attr "length")
8863 (if_then_else (match_operand:SI 0 "register_operand" "")
8865 (const_string "*")))])
8867 (define_insn "*lshrqi3_1"
8868 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
8869 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
8870 (match_operand:QI 2 "nonmemory_operand" "I,c")))
8871 (clobber (reg:CC 17))]
8872 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
8874 shr{b}\\t{%2, %0|%0, %2}
8875 shr{b}\\t{%b2, %0|%0, %b2}"
8876 [(set_attr "type" "ishift")
8877 (set_attr "mode" "QI")])
8879 ;; This pattern can't accept a variable shift count, since shifts by
8880 ;; zero don't affect the flags. We assume that shifts by constant
8881 ;; zero are optimized away.
8882 (define_insn "*lshrqi2_one_bit_cmp"
8885 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
8886 (match_operand:QI 2 "const_int_1_operand" ""))
8888 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
8889 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
8890 "ix86_match_ccmode (insn, CCGOCmode)
8891 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
8892 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
8894 [(set_attr "type" "ishift")
8895 (set (attr "length")
8896 (if_then_else (match_operand:SI 0 "register_operand" "")
8898 (const_string "*")))])
8900 ;; This pattern can't accept a variable shift count, since shifts by
8901 ;; zero don't affect the flags. We assume that shifts by constant
8902 ;; zero are optimized away.
8903 (define_insn "*lshrqi2_cmp"
8906 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
8907 (match_operand:QI 2 "immediate_operand" "I"))
8909 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
8910 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
8911 "ix86_match_ccmode (insn, CCGOCmode)
8912 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
8913 "shr{b}\\t{%2, %0|%0, %2}"
8914 [(set_attr "type" "ishift")
8915 (set_attr "mode" "QI")])
8917 ;; Rotate instructions
8919 (define_expand "rotlsi3"
8920 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8921 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
8922 (match_operand:QI 2 "nonmemory_operand" "")))
8923 (clobber (reg:CC 17))]
8925 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
8927 (define_insn "*rotlsi3_1_one_bit"
8928 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
8929 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
8930 (match_operand:QI 2 "const_int_1_operand" "")))
8931 (clobber (reg:CC 17))]
8932 "ix86_binary_operator_ok (ROTATE, SImode, operands)
8933 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
8935 [(set_attr "type" "ishift")
8936 (set (attr "length")
8937 (if_then_else (match_operand:SI 0 "register_operand" "")
8939 (const_string "*")))])
8941 (define_insn "*rotlsi3_1"
8942 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
8943 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
8944 (match_operand:QI 2 "nonmemory_operand" "I,c")))
8945 (clobber (reg:CC 17))]
8946 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
8948 rol{l}\\t{%2, %0|%0, %2}
8949 rol{l}\\t{%b2, %0|%0, %b2}"
8950 [(set_attr "type" "ishift")
8951 (set_attr "mode" "SI")])
8953 (define_expand "rotlhi3"
8954 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8955 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
8956 (match_operand:QI 2 "nonmemory_operand" "")))
8957 (clobber (reg:CC 17))]
8958 "TARGET_HIMODE_MATH"
8959 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
8961 (define_insn "*rotlhi3_1_one_bit"
8962 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
8963 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
8964 (match_operand:QI 2 "const_int_1_operand" "")))
8965 (clobber (reg:CC 17))]
8966 "ix86_binary_operator_ok (ROTATE, HImode, operands)
8967 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
8969 [(set_attr "type" "ishift")
8970 (set (attr "length")
8971 (if_then_else (match_operand:SI 0 "register_operand" "")
8973 (const_string "*")))])
8975 (define_insn "*rotlhi3_1"
8976 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
8977 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
8978 (match_operand:QI 2 "nonmemory_operand" "I,c")))
8979 (clobber (reg:CC 17))]
8980 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
8982 rol{w}\\t{%2, %0|%0, %2}
8983 rol{w}\\t{%b2, %0|%0, %b2}"
8984 [(set_attr "type" "ishift")
8985 (set_attr "mode" "HI")])
8987 (define_expand "rotlqi3"
8988 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8989 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
8990 (match_operand:QI 2 "nonmemory_operand" "")))
8991 (clobber (reg:CC 17))]
8992 "TARGET_QIMODE_MATH"
8993 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
8995 (define_insn "*rotlqi3_1_one_bit"
8996 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
8997 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
8998 (match_operand:QI 2 "const_int_1_operand" "")))
8999 (clobber (reg:CC 17))]
9000 "ix86_binary_operator_ok (ROTATE, QImode, operands)
9001 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9003 [(set_attr "type" "ishift")
9004 (set (attr "length")
9005 (if_then_else (match_operand:SI 0 "register_operand" "")
9007 (const_string "*")))])
9009 (define_insn "*rotlqi3_1"
9010 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
9011 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
9012 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9013 (clobber (reg:CC 17))]
9014 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
9016 rol{b}\\t{%2, %0|%0, %2}
9017 rol{b}\\t{%b2, %0|%0, %b2}"
9018 [(set_attr "type" "ishift")
9019 (set_attr "mode" "QI")])
9021 (define_expand "rotrsi3"
9022 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9023 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
9024 (match_operand:QI 2 "nonmemory_operand" "")))
9025 (clobber (reg:CC 17))]
9027 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
9029 (define_insn "*rotrsi3_1_one_bit"
9030 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9031 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
9032 (match_operand:QI 2 "const_int_1_operand" "")))
9033 (clobber (reg:CC 17))]
9034 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
9035 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9037 [(set_attr "type" "ishift")
9038 (set (attr "length")
9039 (if_then_else (match_operand:SI 0 "register_operand" "")
9041 (const_string "*")))])
9043 (define_insn "*rotrsi3_1"
9044 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
9045 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
9046 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9047 (clobber (reg:CC 17))]
9048 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
9050 ror{l}\\t{%2, %0|%0, %2}
9051 ror{l}\\t{%b2, %0|%0, %b2}"
9052 [(set_attr "type" "ishift")
9053 (set_attr "mode" "SI")])
9055 (define_expand "rotrhi3"
9056 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9057 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
9058 (match_operand:QI 2 "nonmemory_operand" "")))
9059 (clobber (reg:CC 17))]
9060 "TARGET_HIMODE_MATH"
9061 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
9063 (define_insn "*rotrhi3_one_bit"
9064 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9065 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
9066 (match_operand:QI 2 "const_int_1_operand" "")))
9067 (clobber (reg:CC 17))]
9068 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
9069 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9071 [(set_attr "type" "ishift")
9072 (set (attr "length")
9073 (if_then_else (match_operand:SI 0 "register_operand" "")
9075 (const_string "*")))])
9077 (define_insn "*rotrhi3"
9078 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
9079 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
9080 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9081 (clobber (reg:CC 17))]
9082 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
9084 ror{w}\\t{%2, %0|%0, %2}
9085 ror{w}\\t{%b2, %0|%0, %b2}"
9086 [(set_attr "type" "ishift")
9087 (set_attr "mode" "HI")])
9089 (define_expand "rotrqi3"
9090 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9091 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
9092 (match_operand:QI 2 "nonmemory_operand" "")))
9093 (clobber (reg:CC 17))]
9094 "TARGET_QIMODE_MATH"
9095 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
9097 (define_insn "*rotrqi3_1_one_bit"
9098 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9099 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
9100 (match_operand:QI 2 "const_int_1_operand" "")))
9101 (clobber (reg:CC 17))]
9102 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
9103 && (TARGET_PENTIUM || TARGET_PENTIUMPRO)"
9105 [(set_attr "type" "ishift")
9106 (set (attr "length")
9107 (if_then_else (match_operand:SI 0 "register_operand" "")
9109 (const_string "*")))])
9111 (define_insn "*rotrqi3_1"
9112 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
9113 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
9114 (match_operand:QI 2 "nonmemory_operand" "I,c")))
9115 (clobber (reg:CC 17))]
9116 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
9118 ror{b}\\t{%2, %0|%0, %2}
9119 ror{b}\\t{%b2, %0|%0, %b2}"
9120 [(set_attr "type" "ishift")
9121 (set_attr "mode" "QI")])
9123 ;; Bit set / bit test instructions
9125 (define_expand "extv"
9126 [(set (match_operand:SI 0 "register_operand" "")
9127 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
9128 (match_operand:SI 2 "immediate_operand" "")
9129 (match_operand:SI 3 "immediate_operand" "")))]
9133 /* Handle extractions from %ah et al. */
9134 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
9137 /* From mips.md: extract_bit_field doesn't verify that our source
9138 matches the predicate, so check it again here. */
9139 if (! register_operand (operands[1], VOIDmode))
9143 (define_expand "extzv"
9144 [(set (match_operand:SI 0 "register_operand" "")
9145 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
9146 (match_operand:SI 2 "immediate_operand" "")
9147 (match_operand:SI 3 "immediate_operand" "")))]
9151 /* Handle extractions from %ah et al. */
9152 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
9155 /* From mips.md: extract_bit_field doesn't verify that our source
9156 matches the predicate, so check it again here. */
9157 if (! register_operand (operands[1], VOIDmode))
9161 (define_expand "insv"
9162 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9163 (match_operand:SI 1 "immediate_operand" "")
9164 (match_operand:SI 2 "immediate_operand" ""))
9165 (match_operand:SI 3 "register_operand" ""))]
9169 /* Handle extractions from %ah et al. */
9170 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
9173 /* From mips.md: insert_bit_field doesn't verify that our source
9174 matches the predicate, so check it again here. */
9175 if (! register_operand (operands[0], VOIDmode))
9179 ;; %%% bts, btr, btc, bt.
9181 ;; Store-flag instructions.
9183 ;; For all sCOND expanders, also expand the compare or test insn that
9184 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
9186 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
9187 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
9188 ;; way, which can later delete the movzx if only QImode is needed.
9190 (define_expand "seq"
9191 [(set (match_operand:SI 0 "register_operand" "")
9192 (eq:SI (reg:CC 17) (const_int 0)))]
9194 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
9196 (define_expand "sne"
9197 [(set (match_operand:SI 0 "register_operand" "")
9198 (ne:SI (reg:CC 17) (const_int 0)))]
9200 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
9202 (define_expand "sgt"
9203 [(set (match_operand:SI 0 "register_operand" "")
9204 (gt:SI (reg:CC 17) (const_int 0)))]
9206 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
9208 (define_expand "sgtu"
9209 [(set (match_operand:SI 0 "register_operand" "")
9210 (gtu:SI (reg:CC 17) (const_int 0)))]
9212 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
9214 (define_expand "slt"
9215 [(set (match_operand:SI 0 "register_operand" "")
9216 (lt:SI (reg:CC 17) (const_int 0)))]
9218 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
9220 (define_expand "sltu"
9221 [(set (match_operand:SI 0 "register_operand" "")
9222 (ltu:SI (reg:CC 17) (const_int 0)))]
9224 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
9226 (define_expand "sge"
9227 [(set (match_operand:SI 0 "register_operand" "")
9228 (ge:SI (reg:CC 17) (const_int 0)))]
9230 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
9232 (define_expand "sgeu"
9233 [(set (match_operand:SI 0 "register_operand" "")
9234 (geu:SI (reg:CC 17) (const_int 0)))]
9236 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
9238 (define_expand "sle"
9239 [(set (match_operand:SI 0 "register_operand" "")
9240 (le:SI (reg:CC 17) (const_int 0)))]
9242 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
9244 (define_expand "sleu"
9245 [(set (match_operand:SI 0 "register_operand" "")
9246 (leu:SI (reg:CC 17) (const_int 0)))]
9248 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
9250 (define_expand "sunordered"
9251 [(set (match_operand:SI 0 "register_operand" "")
9252 (unordered:SI (reg:CC 17) (const_int 0)))]
9253 "TARGET_80387 || TARGET_SSE"
9254 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
9256 (define_expand "sordered"
9257 [(set (match_operand:SI 0 "register_operand" "")
9258 (ordered:SI (reg:CC 17) (const_int 0)))]
9260 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
9262 (define_expand "suneq"
9263 [(set (match_operand:SI 0 "register_operand" "")
9264 (uneq:SI (reg:CC 17) (const_int 0)))]
9265 "TARGET_80387 || TARGET_SSE"
9266 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
9268 (define_expand "sunge"
9269 [(set (match_operand:SI 0 "register_operand" "")
9270 (unge:SI (reg:CC 17) (const_int 0)))]
9271 "TARGET_80387 || TARGET_SSE"
9272 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
9274 (define_expand "sungt"
9275 [(set (match_operand:SI 0 "register_operand" "")
9276 (ungt:SI (reg:CC 17) (const_int 0)))]
9277 "TARGET_80387 || TARGET_SSE"
9278 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
9280 (define_expand "sunle"
9281 [(set (match_operand:SI 0 "register_operand" "")
9282 (unle:SI (reg:CC 17) (const_int 0)))]
9283 "TARGET_80387 || TARGET_SSE"
9284 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
9286 (define_expand "sunlt"
9287 [(set (match_operand:SI 0 "register_operand" "")
9288 (unlt:SI (reg:CC 17) (const_int 0)))]
9289 "TARGET_80387 || TARGET_SSE"
9290 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
9292 (define_expand "sltgt"
9293 [(set (match_operand:SI 0 "register_operand" "")
9294 (ltgt:SI (reg:CC 17) (const_int 0)))]
9295 "TARGET_80387 || TARGET_SSE"
9296 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
9298 (define_insn "*setcc_1"
9299 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9300 (match_operator:QI 1 "ix86_comparison_operator"
9301 [(reg 17) (const_int 0)]))]
9304 [(set_attr "type" "setcc")
9305 (set_attr "mode" "QI")])
9307 (define_insn "setcc_2"
9308 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
9309 (match_operator:QI 1 "ix86_comparison_operator"
9310 [(reg 17) (const_int 0)]))]
9313 [(set_attr "type" "setcc")
9314 (set_attr "mode" "QI")])
9316 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
9317 ;; subsequent logical operations are used to imitate conditional moves.
9318 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
9319 ;; it directly. Futher holding this value in pseudo register might bring
9320 ;; problem in implicit normalization in spill code.
9321 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
9322 ;; instructions after reload by splitting the conditional move patterns.
9324 (define_insn "*sse_setccsf"
9325 [(set (match_operand:SF 0 "register_operand" "=x")
9326 (match_operator:SF 1 "sse_comparison_operator"
9327 [(match_operand:SF 2 "register_operand" "0")
9328 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
9329 "TARGET_SSE && reload_completed"
9330 "cmp%D1ss\\t{%3, %0|%0, %3}"
9331 [(set_attr "type" "sse")
9332 (set_attr "mode" "SF")])
9334 (define_insn "*sse_setccdf"
9335 [(set (match_operand:DF 0 "register_operand" "=Y")
9336 (match_operator:DF 1 "sse_comparison_operator"
9337 [(match_operand:DF 2 "register_operand" "0")
9338 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
9339 "TARGET_SSE2 && reload_completed"
9340 "cmp%D1sd\\t{%3, %0|%0, %3}"
9341 [(set_attr "type" "sse")
9342 (set_attr "mode" "DF")])
9344 ;; Basic conditional jump instructions.
9345 ;; We ignore the overflow flag for signed branch instructions.
9347 ;; For all bCOND expanders, also expand the compare or test insn that
9348 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
9350 (define_expand "beq"
9352 (if_then_else (match_dup 1)
9353 (label_ref (match_operand 0 "" ""))
9356 "ix86_expand_branch (EQ, operands[0]); DONE;")
9358 (define_expand "bne"
9360 (if_then_else (match_dup 1)
9361 (label_ref (match_operand 0 "" ""))
9364 "ix86_expand_branch (NE, operands[0]); DONE;")
9366 (define_expand "bgt"
9368 (if_then_else (match_dup 1)
9369 (label_ref (match_operand 0 "" ""))
9372 "ix86_expand_branch (GT, operands[0]); DONE;")
9374 (define_expand "bgtu"
9376 (if_then_else (match_dup 1)
9377 (label_ref (match_operand 0 "" ""))
9380 "ix86_expand_branch (GTU, operands[0]); DONE;")
9382 (define_expand "blt"
9384 (if_then_else (match_dup 1)
9385 (label_ref (match_operand 0 "" ""))
9388 "ix86_expand_branch (LT, operands[0]); DONE;")
9390 (define_expand "bltu"
9392 (if_then_else (match_dup 1)
9393 (label_ref (match_operand 0 "" ""))
9396 "ix86_expand_branch (LTU, operands[0]); DONE;")
9398 (define_expand "bge"
9400 (if_then_else (match_dup 1)
9401 (label_ref (match_operand 0 "" ""))
9404 "ix86_expand_branch (GE, operands[0]); DONE;")
9406 (define_expand "bgeu"
9408 (if_then_else (match_dup 1)
9409 (label_ref (match_operand 0 "" ""))
9412 "ix86_expand_branch (GEU, operands[0]); DONE;")
9414 (define_expand "ble"
9416 (if_then_else (match_dup 1)
9417 (label_ref (match_operand 0 "" ""))
9420 "ix86_expand_branch (LE, operands[0]); DONE;")
9422 (define_expand "bleu"
9424 (if_then_else (match_dup 1)
9425 (label_ref (match_operand 0 "" ""))
9428 "ix86_expand_branch (LEU, operands[0]); DONE;")
9430 (define_expand "bunordered"
9432 (if_then_else (match_dup 1)
9433 (label_ref (match_operand 0 "" ""))
9435 "TARGET_80387 || TARGET_SSE"
9436 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
9438 (define_expand "bordered"
9440 (if_then_else (match_dup 1)
9441 (label_ref (match_operand 0 "" ""))
9443 "TARGET_80387 || TARGET_SSE"
9444 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
9446 (define_expand "buneq"
9448 (if_then_else (match_dup 1)
9449 (label_ref (match_operand 0 "" ""))
9451 "TARGET_80387 || TARGET_SSE"
9452 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
9454 (define_expand "bunge"
9456 (if_then_else (match_dup 1)
9457 (label_ref (match_operand 0 "" ""))
9459 "TARGET_80387 || TARGET_SSE"
9460 "ix86_expand_branch (UNGE, operands[0]); DONE;")
9462 (define_expand "bungt"
9464 (if_then_else (match_dup 1)
9465 (label_ref (match_operand 0 "" ""))
9467 "TARGET_80387 || TARGET_SSE"
9468 "ix86_expand_branch (UNGT, operands[0]); DONE;")
9470 (define_expand "bunle"
9472 (if_then_else (match_dup 1)
9473 (label_ref (match_operand 0 "" ""))
9475 "TARGET_80387 || TARGET_SSE"
9476 "ix86_expand_branch (UNLE, operands[0]); DONE;")
9478 (define_expand "bunlt"
9480 (if_then_else (match_dup 1)
9481 (label_ref (match_operand 0 "" ""))
9483 "TARGET_80387 || TARGET_SSE"
9484 "ix86_expand_branch (UNLT, operands[0]); DONE;")
9486 (define_expand "bltgt"
9488 (if_then_else (match_dup 1)
9489 (label_ref (match_operand 0 "" ""))
9491 "TARGET_80387 || TARGET_SSE"
9492 "ix86_expand_branch (LTGT, operands[0]); DONE;")
9494 (define_insn "*jcc_1"
9496 (if_then_else (match_operator 1 "ix86_comparison_operator"
9497 [(reg 17) (const_int 0)])
9498 (label_ref (match_operand 0 "" ""))
9502 [(set_attr "type" "ibr")
9503 (set (attr "prefix_0f")
9504 (if_then_else (and (ge (minus (match_dup 0) (pc))
9506 (lt (minus (match_dup 0) (pc))
9511 (define_insn "*jcc_2"
9513 (if_then_else (match_operator 1 "ix86_comparison_operator"
9514 [(reg 17) (const_int 0)])
9516 (label_ref (match_operand 0 "" ""))))]
9519 [(set_attr "type" "ibr")
9520 (set (attr "prefix_0f")
9521 (if_then_else (and (ge (minus (match_dup 0) (pc))
9523 (lt (minus (match_dup 0) (pc))
9528 ;; Define combination compare-and-branch fp compare instructions to use
9529 ;; during early optimization. Splitting the operation apart early makes
9530 ;; for bad code when we want to reverse the operation.
9532 (define_insn "*fp_jcc_1"
9534 (if_then_else (match_operator 0 "comparison_operator"
9535 [(match_operand 1 "register_operand" "f")
9536 (match_operand 2 "register_operand" "f")])
9537 (label_ref (match_operand 3 "" ""))
9539 (clobber (reg:CCFP 18))
9540 (clobber (reg:CCFP 17))]
9541 "TARGET_CMOVE && TARGET_80387
9542 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
9543 && FLOAT_MODE_P (GET_MODE (operands[1]))
9544 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
9547 (define_insn "*fp_jcc_1_sse"
9549 (if_then_else (match_operator 0 "comparison_operator"
9550 [(match_operand 1 "register_operand" "f#x,x#f")
9551 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
9552 (label_ref (match_operand 3 "" ""))
9554 (clobber (reg:CCFP 18))
9555 (clobber (reg:CCFP 17))]
9557 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
9558 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
9561 (define_insn "*fp_jcc_1_sse_only"
9563 (if_then_else (match_operator 0 "comparison_operator"
9564 [(match_operand 1 "register_operand" "x")
9565 (match_operand 2 "nonimmediate_operand" "xm")])
9566 (label_ref (match_operand 3 "" ""))
9568 (clobber (reg:CCFP 18))
9569 (clobber (reg:CCFP 17))]
9570 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
9571 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
9574 (define_insn "*fp_jcc_2"
9576 (if_then_else (match_operator 0 "comparison_operator"
9577 [(match_operand 1 "register_operand" "f")
9578 (match_operand 2 "register_operand" "f")])
9580 (label_ref (match_operand 3 "" ""))))
9581 (clobber (reg:CCFP 18))
9582 (clobber (reg:CCFP 17))]
9583 "TARGET_CMOVE && TARGET_80387
9584 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
9585 && FLOAT_MODE_P (GET_MODE (operands[1]))
9586 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
9589 (define_insn "*fp_jcc_2_sse"
9591 (if_then_else (match_operator 0 "comparison_operator"
9592 [(match_operand 1 "register_operand" "f#x,x#f")
9593 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
9595 (label_ref (match_operand 3 "" ""))))
9596 (clobber (reg:CCFP 18))
9597 (clobber (reg:CCFP 17))]
9599 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
9600 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
9603 (define_insn "*fp_jcc_2_sse_only"
9605 (if_then_else (match_operator 0 "comparison_operator"
9606 [(match_operand 1 "register_operand" "x")
9607 (match_operand 2 "nonimmediate_operand" "xm")])
9609 (label_ref (match_operand 3 "" ""))))
9610 (clobber (reg:CCFP 18))
9611 (clobber (reg:CCFP 17))]
9612 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
9613 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
9616 (define_insn "*fp_jcc_3"
9618 (if_then_else (match_operator 0 "comparison_operator"
9619 [(match_operand 1 "register_operand" "f")
9620 (match_operand 2 "nonimmediate_operand" "fm")])
9621 (label_ref (match_operand 3 "" ""))
9623 (clobber (reg:CCFP 18))
9624 (clobber (reg:CCFP 17))
9625 (clobber (match_scratch:HI 4 "=a"))]
9627 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
9628 && GET_MODE (operands[1]) == GET_MODE (operands[2])
9629 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
9630 && SELECT_CC_MODE (GET_CODE (operands[0]),
9631 operands[1], operands[2]) == CCFPmode"
9634 (define_insn "*fp_jcc_4"
9636 (if_then_else (match_operator 0 "comparison_operator"
9637 [(match_operand 1 "register_operand" "f")
9638 (match_operand 2 "nonimmediate_operand" "fm")])
9640 (label_ref (match_operand 3 "" ""))))
9641 (clobber (reg:CCFP 18))
9642 (clobber (reg:CCFP 17))
9643 (clobber (match_scratch:HI 4 "=a"))]
9645 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
9646 && GET_MODE (operands[1]) == GET_MODE (operands[2])
9647 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
9648 && SELECT_CC_MODE (GET_CODE (operands[0]),
9649 operands[1], operands[2]) == CCFPmode"
9652 (define_insn "*fp_jcc_5"
9654 (if_then_else (match_operator 0 "comparison_operator"
9655 [(match_operand 1 "register_operand" "f")
9656 (match_operand 2 "register_operand" "f")])
9657 (label_ref (match_operand 3 "" ""))
9659 (clobber (reg:CCFP 18))
9660 (clobber (reg:CCFP 17))
9661 (clobber (match_scratch:HI 4 "=a"))]
9663 && FLOAT_MODE_P (GET_MODE (operands[1]))
9664 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
9667 (define_insn "*fp_jcc_6"
9669 (if_then_else (match_operator 0 "comparison_operator"
9670 [(match_operand 1 "register_operand" "f")
9671 (match_operand 2 "register_operand" "f")])
9673 (label_ref (match_operand 3 "" ""))))
9674 (clobber (reg:CCFP 18))
9675 (clobber (reg:CCFP 17))
9676 (clobber (match_scratch:HI 4 "=a"))]
9678 && FLOAT_MODE_P (GET_MODE (operands[1]))
9679 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
9684 (if_then_else (match_operator 0 "comparison_operator"
9685 [(match_operand 1 "register_operand" "")
9686 (match_operand 2 "nonimmediate_operand" "")])
9687 (match_operand 3 "" "")
9688 (match_operand 4 "" "")))
9689 (clobber (reg:CCFP 18))
9690 (clobber (reg:CCFP 17))]
9695 ix86_split_fp_branch (operands[0], operands[1], operands[2],
9696 operands[3], operands[4], NULL_RTX);
9702 (if_then_else (match_operator 0 "comparison_operator"
9703 [(match_operand 1 "register_operand" "")
9704 (match_operand 2 "nonimmediate_operand" "")])
9705 (match_operand 3 "" "")
9706 (match_operand 4 "" "")))
9707 (clobber (reg:CCFP 18))
9708 (clobber (reg:CCFP 17))
9709 (clobber (match_scratch:HI 5 "=a"))]
9712 (if_then_else (match_dup 6)
9717 ix86_split_fp_branch (operands[0], operands[1], operands[2],
9718 operands[3], operands[4], operands[5]);
9722 ;; Unconditional and other jump instructions
9726 (label_ref (match_operand 0 "" "")))]
9729 [(set_attr "type" "ibr")])
9731 (define_insn "indirect_jump"
9732 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
9735 [(set_attr "type" "ibr")
9736 (set_attr "length_immediate" "0")])
9738 (define_insn "tablejump"
9739 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
9740 (use (label_ref (match_operand 1 "" "")))]
9743 [(set_attr "type" "ibr")
9744 (set_attr "length_immediate" "0")])
9746 ;; Implement switch statements when generating PIC code. Switches are
9747 ;; implemented by `tablejump' when not using -fpic.
9749 ;; Emit code here to do the range checking and make the index zero based.
9751 ;; Each entry in the "addr_diff_vec" looks like this as the result of the
9754 ;; .long _GLOBAL_OFFSET_TABLE_+[.-.L2]
9756 ;; 1. An expression involving an external reference may only use the
9757 ;; addition operator, and only with an assembly-time constant.
9758 ;; The example above satisfies this because ".-.L2" is a constant.
9760 ;; 2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is
9761 ;; given the value of "GOT - .", where GOT is the actual address of
9762 ;; the Global Offset Table. Therefore, the .long above actually
9763 ;; stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2". The
9764 ;; expression "GOT - .L2" by itself would generate an error from as(1).
9766 ;; The pattern below emits code that looks like this:
9769 ;; subl TABLE@GOTOFF(%ebx,index,4),reg
9772 ;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since
9773 ;; the addr_diff_vec is known to be part of this module.
9775 ;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which
9776 ;; evaluates to just ".L2".
9778 (define_expand "casesi"
9780 (match_operand:SI 0 "general_operand" ""))
9781 (parallel [(set (match_dup 6)
9782 (minus:SI (match_dup 5)
9783 (match_operand:SI 1 "general_operand" "")))
9784 (clobber (reg:CC 17))])
9786 (compare:CC (match_dup 6)
9787 (match_operand:SI 2 "general_operand" "")))
9789 (if_then_else (gtu (reg:CC 17)
9791 (label_ref (match_operand 4 "" ""))
9795 (minus:SI (match_dup 8)
9796 (mem:SI (plus:SI (plus:SI (mult:SI (match_dup 6) (const_int 4))
9798 (const (unspec [(label_ref (match_operand 3 "" ""))] 7))))))
9799 (clobber (reg:CC 17))])
9800 (parallel [(set (pc) (match_dup 7))
9801 (use (label_ref (match_dup 3)))])]
9805 operands[5] = gen_reg_rtx (SImode);
9806 operands[6] = gen_reg_rtx (SImode);
9807 operands[7] = gen_reg_rtx (SImode);
9808 operands[8] = pic_offset_table_rtx;
9809 current_function_uses_pic_offset_table = 1;
9812 (define_insn "*tablejump_pic"
9813 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
9814 (use (label_ref (match_operand 1 "" "")))]
9817 [(set_attr "type" "ibr")
9818 (set_attr "length_immediate" "0")])
9822 ;; This is all complicated by the fact that since this is a jump insn
9823 ;; we must handle our own reloads.
9825 (define_expand "doloop_end"
9826 [(use (match_operand 0 "" "")) ; loop pseudo
9827 (use (match_operand 1 "" "")) ; iterations; zero if unknown
9828 (use (match_operand 2 "" "")) ; max iterations
9829 (use (match_operand 3 "" "")) ; loop level
9830 (use (match_operand 4 "" ""))] ; label
9834 /* Only use cloop on innermost loops. */
9835 if (INTVAL (operands[3]) > 1)
9837 if (GET_MODE (operands[0]) != SImode)
9839 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
9844 (define_insn "doloop_end_internal"
9846 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
9848 (label_ref (match_operand 0 "" ""))
9850 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
9851 (plus:SI (match_dup 1)
9853 (clobber (match_scratch:SI 3 "=X,X,r"))
9854 (clobber (reg:CC 17))]
9858 if (which_alternative != 0)
9860 if (get_attr_length (insn) == 2)
9861 return \"loop\\t%l0\";
9863 return \"dec{l}\\t%1\;jne\\t%l0\";
9865 [(set_attr "ppro_uops" "many")
9867 (if_then_else (and (eq_attr "alternative" "0")
9868 (and (ge (minus (match_dup 0) (pc))
9870 (lt (minus (match_dup 0) (pc))
9872 (const_string "ibr")
9873 (const_string "multi")))])
9877 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
9879 (match_operand 0 "" "")
9882 (plus:SI (match_dup 1)
9884 (clobber (match_scratch:SI 2 ""))
9885 (clobber (reg:CC 17))]
9888 && REGNO (operands[1]) != 2"
9889 [(parallel [(set (reg:CCZ 17)
9890 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
9892 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
9893 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
9900 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
9902 (match_operand 0 "" "")
9904 (set (match_operand:SI 2 "nonimmediate_operand" "")
9905 (plus:SI (match_dup 1)
9907 (clobber (match_scratch:SI 3 ""))
9908 (clobber (reg:CC 17))]
9911 && (! REG_P (operands[2])
9912 || ! rtx_equal_p (operands[1], operands[2]))"
9913 [(set (match_dup 3) (match_dup 1))
9914 (parallel [(set (reg:CCZ 17)
9915 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
9917 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
9918 (set (match_dup 2) (match_dup 3))
9919 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
9924 ;; Call instructions.
9926 ;; The predicates normally associated with named expanders are not properly
9927 ;; checked for calls. This is a bug in the generic code, but it isn't that
9928 ;; easy to fix. Ignore it for now and be prepared to fix things up.
9930 ;; Call subroutine returning no value.
9932 (define_expand "call_pop"
9933 [(parallel [(call (match_operand:QI 0 "" "")
9934 (match_operand:SI 1 "" ""))
9937 (match_operand:SI 3 "" "")))])]
9941 if (operands[3] == const0_rtx)
9943 emit_insn (gen_call (operands[0], operands[1]));
9946 /* Static functions and indirect calls don't need
9947 current_function_uses_pic_offset_table. */
9949 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
9950 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
9951 current_function_uses_pic_offset_table = 1;
9952 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
9953 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
9956 (define_insn "*call_pop_0"
9957 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
9958 (match_operand:SI 1 "" ""))
9959 (set (reg:SI 7) (plus:SI (reg:SI 7)
9960 (match_operand:SI 2 "immediate_operand" "")))]
9964 if (SIBLING_CALL_P (insn))
9965 return \"jmp\\t%P0\";
9967 return \"call\\t%P0\";
9969 [(set_attr "type" "call")])
9971 (define_insn "*call_pop_1"
9972 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
9973 (match_operand:SI 1 "" ""))
9974 (set (reg:SI 7) (plus:SI (reg:SI 7)
9975 (match_operand:SI 2 "immediate_operand" "i")))]
9979 if (constant_call_address_operand (operands[0], Pmode))
9981 if (SIBLING_CALL_P (insn))
9982 return \"jmp\\t%P0\";
9984 return \"call\\t%P0\";
9986 if (SIBLING_CALL_P (insn))
9987 return \"jmp\\t%A0\";
9989 return \"call\\t%A0\";
9991 [(set_attr "type" "call")])
9993 (define_expand "call"
9994 [(call (match_operand:QI 0 "" "")
9995 (match_operand:SI 1 "" ""))]
9996 ;; Operand 1 not used on the i386.
10000 /* Static functions and indirect calls don't need
10001 current_function_uses_pic_offset_table. */
10003 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
10004 && ! SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
10005 current_function_uses_pic_offset_table = 1;
10006 if (! call_insn_operand (XEXP (operands[0], 0), Pmode))
10007 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
10010 (define_insn "*call_0"
10011 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
10012 (match_operand:SI 1 "" ""))]
10016 if (SIBLING_CALL_P (insn))
10017 return \"jmp\\t%P0\";
10019 return \"call\\t%P0\";
10021 [(set_attr "type" "call")])
10023 (define_insn "*call_1"
10024 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
10025 (match_operand:SI 1 "" ""))]
10029 if (constant_call_address_operand (operands[0], QImode))
10031 if (SIBLING_CALL_P (insn))
10032 return \"jmp\\t%P0\";
10034 return \"call\\t%P0\";
10036 if (SIBLING_CALL_P (insn))
10037 return \"jmp\\t%A0\";
10039 return \"call\\t%A0\";
10041 [(set_attr "type" "call")])
10043 ;; Call subroutine, returning value in operand 0
10044 ;; (which must be a hard register).
10046 (define_expand "call_value_pop"
10047 [(parallel [(set (match_operand 0 "" "")
10048 (call (match_operand:QI 1 "" "")
10049 (match_operand:SI 2 "" "")))
10051 (plus:SI (reg:SI 7)
10052 (match_operand:SI 4 "" "")))])]
10056 if (operands[4] == const0_rtx)
10058 emit_insn (gen_call_value (operands[0], operands[1], operands[2]));
10061 /* Static functions and indirect calls don't need
10062 current_function_uses_pic_offset_table. */
10064 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10065 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
10066 current_function_uses_pic_offset_table = 1;
10067 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
10068 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
10071 (define_expand "call_value"
10072 [(set (match_operand 0 "" "")
10073 (call (match_operand:QI 1 "" "")
10074 (match_operand:SI 2 "" "")))]
10075 ;; Operand 2 not used on the i386.
10079 /* Static functions and indirect calls don't need
10080 current_function_uses_pic_offset_table. */
10082 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10083 && ! SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
10084 current_function_uses_pic_offset_table = 1;
10085 if (! call_insn_operand (XEXP (operands[1], 0), Pmode))
10086 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
10089 ;; Call subroutine returning any type.
10091 (define_expand "untyped_call"
10092 [(parallel [(call (match_operand 0 "" "")
10094 (match_operand 1 "" "")
10095 (match_operand 2 "" "")])]
10101 /* In order to give reg-stack an easier job in validating two
10102 coprocessor registers as containing a possible return value,
10103 simply pretend the untyped call returns a complex long double
10106 emit_call_insn (TARGET_80387
10107 ? gen_call_value (gen_rtx_REG (XCmode, FIRST_FLOAT_REG),
10108 operands[0], const0_rtx)
10109 : gen_call (operands[0], const0_rtx));
10111 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10113 rtx set = XVECEXP (operands[2], 0, i);
10114 emit_move_insn (SET_DEST (set), SET_SRC (set));
10117 /* The optimizer does not know that the call sets the function value
10118 registers we stored in the result block. We avoid problems by
10119 claiming that all hard registers are used and clobbered at this
10121 emit_insn (gen_blockage ());
10126 ;; Prologue and epilogue instructions
10128 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10129 ;; all of memory. This blocks insns from being moved across this point.
10131 (define_insn "blockage"
10132 [(unspec_volatile [(const_int 0)] 0)]
10135 [(set_attr "length" "0")])
10137 ;; Insn emitted into the body of a function to return from a function.
10138 ;; This is only done if the function's epilogue is known to be simple.
10139 ;; See comments for ix86_can_use_return_insn_p in i386.c.
10141 (define_expand "return"
10143 "ix86_can_use_return_insn_p ()"
10146 if (current_function_pops_args)
10148 rtx popc = GEN_INT (current_function_pops_args);
10149 emit_jump_insn (gen_return_pop_internal (popc));
10154 (define_insn "return_internal"
10158 [(set_attr "length" "1")
10159 (set_attr "length_immediate" "0")
10160 (set_attr "modrm" "0")])
10162 (define_insn "return_pop_internal"
10164 (use (match_operand:SI 0 "const_int_operand" ""))]
10167 [(set_attr "length" "3")
10168 (set_attr "length_immediate" "2")
10169 (set_attr "modrm" "0")])
10171 (define_insn "return_indirect_internal"
10173 (use (match_operand:SI 0 "register_operand" "r"))]
10176 [(set_attr "type" "ibr")
10177 (set_attr "length_immediate" "0")])
10183 [(set_attr "length" "1")
10184 (set_attr "length_immediate" "0")
10185 (set_attr "modrm" "0")
10186 (set_attr "ppro_uops" "one")])
10188 (define_expand "prologue"
10191 "ix86_expand_prologue (); DONE;")
10193 (define_insn "prologue_set_got"
10194 [(set (match_operand:SI 0 "register_operand" "=r")
10195 (unspec_volatile:SI
10196 [(plus:SI (match_dup 0)
10197 (plus:SI (match_operand:SI 1 "symbolic_operand" "")
10198 (minus:SI (pc) (match_operand 2 "" ""))))] 1))
10199 (clobber (reg:CC 17))]
10203 if (GET_CODE (operands[2]) == LABEL_REF)
10204 operands[2] = XEXP (operands[2], 0);
10205 if (TARGET_DEEP_BRANCH_PREDICTION)
10206 return \"add{l}\\t{%1, %0|%0, %1}\";
10208 return \"add{l}\\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}\";
10210 [(set_attr "type" "alu")
10211 ; Since this insn may have two constant operands, we must set the
10213 (set_attr "length_immediate" "4")
10214 (set_attr "mode" "SI")])
10216 (define_insn "prologue_get_pc"
10217 [(set (match_operand:SI 0 "register_operand" "=r")
10218 (unspec_volatile:SI [(plus:SI (pc) (match_operand 1 "" ""))] 2))]
10222 if (GET_CODE (operands[1]) == LABEL_REF)
10223 operands[1] = XEXP (operands[1], 0);
10224 output_asm_insn (\"call\\t%X1\", operands);
10225 if (! TARGET_DEEP_BRANCH_PREDICTION)
10227 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
10228 CODE_LABEL_NUMBER (operands[1]));
10232 [(set_attr "type" "multi")])
10234 (define_expand "epilogue"
10237 "ix86_expand_epilogue (1); DONE;")
10239 (define_expand "sibcall_epilogue"
10242 "ix86_expand_epilogue (0); DONE;")
10244 (define_insn "leave"
10245 [(set (reg:SI 7) (reg:SI 6))
10246 (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7))))]
10249 [(set_attr "length_immediate" "0")
10250 (set_attr "length" "1")
10251 (set_attr "modrm" "0")
10252 (set_attr "modrm" "0")
10253 (set_attr "athlon_decode" "vector")
10254 (set_attr "ppro_uops" "few")])
10256 (define_expand "ffssi2"
10257 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10258 (ffs:SI (match_operand:SI 1 "general_operand" "")))]
10262 rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
10263 rtx in = operands[1];
10267 emit_move_insn (tmp, constm1_rtx);
10268 emit_insn (gen_ffssi_1 (out, in));
10269 emit_insn (gen_rtx_SET (VOIDmode, out,
10270 gen_rtx_IF_THEN_ELSE (SImode,
10271 gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
10275 emit_insn (gen_addsi3 (out, out, const1_rtx));
10276 emit_move_insn (operands[0], out);
10279 /* Pentium bsf instruction is extremly slow. The following code is
10280 recommended by the Intel Optimizing Manual as a reasonable replacement:
10284 MOV DWORD PTR [TEMP+4],ECX
10287 MOV DWORD PTR [TEMP],EAX
10288 FILD QWORD PTR [TEMP]
10289 FSTP QWORD PTR [TEMP]
10290 WAIT ; WAIT only needed for compatibility with
10291 ; earlier processors
10292 MOV ECX, DWORD PTR [TEMP+4]
10295 TEST EAX,EAX ; clear zero flag
10297 Following piece of code expand ffs to similar beast.
10300 else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
10302 rtx label = gen_label_rtx ();
10304 rtx mem = assign_386_stack_local (DImode, 0);
10305 rtx fptmp = gen_reg_rtx (DFmode);
10306 split_di (&mem, 1, &lo, &hi);
10308 emit_move_insn (out, const0_rtx);
10310 emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, 0, label);
10312 emit_move_insn (hi, out);
10313 emit_insn (gen_subsi3 (out, out, in));
10314 emit_insn (gen_andsi3 (out, out, in));
10315 emit_move_insn (lo, out);
10316 emit_insn (gen_floatdidf2 (fptmp,mem));
10317 emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
10318 emit_move_insn (out, hi);
10319 emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
10320 emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
10322 emit_label (label);
10323 LABEL_NUSES (label) = 1;
10325 emit_move_insn (operands[0], out);
10329 emit_move_insn (tmp, const0_rtx);
10330 emit_insn (gen_ffssi_1 (out, in));
10331 emit_insn (gen_rtx_SET (VOIDmode,
10332 gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
10333 gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
10335 emit_insn (gen_negsi2 (tmp, tmp));
10336 emit_insn (gen_iorsi3 (out, out, tmp));
10337 emit_insn (gen_addsi3 (out, out, const1_rtx));
10338 emit_move_insn (operands[0], out);
10343 (define_insn "ffssi_1"
10345 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
10347 (set (match_operand:SI 0 "register_operand" "=r")
10348 (unspec:SI [(match_dup 1)] 5))]
10350 "bsf{l}\\t{%1, %0|%0, %1}"
10351 [(set_attr "prefix_0f" "1")
10352 (set_attr "ppro_uops" "few")])
10354 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
10355 ;; and slower than the two-byte movzx insn needed to do the work in SImode.
10357 ;; These patterns match the binary 387 instructions for addM3, subM3,
10358 ;; mulM3 and divM3. There are three patterns for each of DFmode and
10359 ;; SFmode. The first is the normal insn, the second the same insn but
10360 ;; with one operand a conversion, and the third the same insn but with
10361 ;; the other operand a conversion. The conversion may be SFmode or
10362 ;; SImode if the target mode DFmode, but only SImode if the target mode
10365 ;; Gcc is slightly more smart about handling normal two address instructions
10366 ;; so use special patterns for add and mull.
10367 (define_insn "*fop_sf_comm"
10368 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
10369 (match_operator:SF 3 "binary_fp_operator"
10370 [(match_operand:SF 1 "register_operand" "%0,0")
10371 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
10372 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
10373 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
10374 "* return output_387_binary_op (insn, operands);"
10375 [(set (attr "type")
10376 (if_then_else (eq_attr "alternative" "1")
10377 (const_string "sse")
10378 (if_then_else (match_operand:SF 3 "mult_operator" "")
10379 (const_string "fmul")
10380 (const_string "fop"))))
10381 (set_attr "mode" "SF")])
10383 (define_insn "*fop_sf_comm_sse"
10384 [(set (match_operand:SF 0 "register_operand" "=x")
10385 (match_operator:SF 3 "binary_fp_operator"
10386 [(match_operand:SF 1 "register_operand" "%0")
10387 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
10388 "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
10389 "* return output_387_binary_op (insn, operands);"
10390 [(set_attr "type" "sse")
10391 (set_attr "mode" "SF")])
10393 (define_insn "*fop_df_comm"
10394 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
10395 (match_operator:DF 3 "binary_fp_operator"
10396 [(match_operand:DF 1 "register_operand" "%0,0")
10397 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
10398 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
10399 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
10400 "* return output_387_binary_op (insn, operands);"
10401 [(set (attr "type")
10402 (if_then_else (eq_attr "alternative" "1")
10403 (const_string "sse")
10404 (if_then_else (match_operand:SF 3 "mult_operator" "")
10405 (const_string "fmul")
10406 (const_string "fop"))))
10407 (set_attr "mode" "DF")])
10409 (define_insn "*fop_df_comm_sse"
10410 [(set (match_operand:DF 0 "register_operand" "=Y")
10411 (match_operator:DF 3 "binary_fp_operator"
10412 [(match_operand:DF 1 "register_operand" "%0")
10413 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
10415 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
10416 "* return output_387_binary_op (insn, operands);"
10417 [(set_attr "type" "sse")
10418 (set_attr "mode" "DF")])
10420 (define_insn "*fop_xf_comm"
10421 [(set (match_operand:XF 0 "register_operand" "=f")
10422 (match_operator:XF 3 "binary_fp_operator"
10423 [(match_operand:XF 1 "register_operand" "%0")
10424 (match_operand:XF 2 "register_operand" "f")]))]
10425 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
10426 "* return output_387_binary_op (insn, operands);"
10427 [(set (attr "type")
10428 (if_then_else (match_operand:XF 3 "mult_operator" "")
10429 (const_string "fmul")
10430 (const_string "fop")))
10431 (set_attr "mode" "XF")])
10433 (define_insn "*fop_tf_comm"
10434 [(set (match_operand:TF 0 "register_operand" "=f")
10435 (match_operator:TF 3 "binary_fp_operator"
10436 [(match_operand:TF 1 "register_operand" "%0")
10437 (match_operand:TF 2 "register_operand" "f")]))]
10438 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
10439 "* return output_387_binary_op (insn, operands);"
10440 [(set (attr "type")
10441 (if_then_else (match_operand:TF 3 "mult_operator" "")
10442 (const_string "fmul")
10443 (const_string "fop")))
10444 (set_attr "mode" "XF")])
10446 (define_insn "*fop_sf_1"
10447 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
10448 (match_operator:SF 3 "binary_fp_operator"
10449 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
10450 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
10451 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
10452 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
10453 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
10454 "* return output_387_binary_op (insn, operands);"
10455 [(set (attr "type")
10456 (cond [(eq_attr "alternative" "2")
10457 (const_string "sse")
10458 (match_operand:SF 3 "mult_operator" "")
10459 (const_string "fmul")
10460 (match_operand:SF 3 "div_operator" "")
10461 (const_string "fdiv")
10463 (const_string "fop")))
10464 (set_attr "mode" "SF")])
10466 (define_insn "*fop_sf_1_sse"
10467 [(set (match_operand:SF 0 "register_operand" "=x")
10468 (match_operator:SF 3 "binary_fp_operator"
10469 [(match_operand:SF 1 "register_operand" "0")
10470 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
10472 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
10473 "* return output_387_binary_op (insn, operands);"
10474 [(set_attr "type" "sse")
10475 (set_attr "mode" "SF")])
10477 ;; ??? Add SSE splitters for these!
10478 (define_insn "*fop_sf_2"
10479 [(set (match_operand:SF 0 "register_operand" "=f,f")
10480 (match_operator:SF 3 "binary_fp_operator"
10481 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
10482 (match_operand:SF 2 "register_operand" "0,0")]))]
10483 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
10484 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
10485 [(set (attr "type")
10486 (cond [(match_operand:SF 3 "mult_operator" "")
10487 (const_string "fmul")
10488 (match_operand:SF 3 "div_operator" "")
10489 (const_string "fdiv")
10491 (const_string "fop")))
10492 (set_attr "fp_int_src" "true")
10493 (set_attr "ppro_uops" "many")
10494 (set_attr "mode" "SI")])
10496 (define_insn "*fop_sf_3"
10497 [(set (match_operand:SF 0 "register_operand" "=f,f")
10498 (match_operator:SF 3 "binary_fp_operator"
10499 [(match_operand:SF 1 "register_operand" "0,0")
10500 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
10501 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
10502 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
10503 [(set (attr "type")
10504 (cond [(match_operand:SF 3 "mult_operator" "")
10505 (const_string "fmul")
10506 (match_operand:SF 3 "div_operator" "")
10507 (const_string "fdiv")
10509 (const_string "fop")))
10510 (set_attr "fp_int_src" "true")
10511 (set_attr "ppro_uops" "many")
10512 (set_attr "mode" "SI")])
10514 (define_insn "*fop_df_1"
10515 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
10516 (match_operator:DF 3 "binary_fp_operator"
10517 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
10518 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
10519 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
10520 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
10521 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
10522 "* return output_387_binary_op (insn, operands);"
10523 [(set (attr "type")
10524 (cond [(eq_attr "alternative" "2")
10525 (const_string "sse")
10526 (match_operand:DF 3 "mult_operator" "")
10527 (const_string "fmul")
10528 (match_operand:DF 3 "div_operator" "")
10529 (const_string "fdiv")
10531 (const_string "fop")))
10532 (set_attr "mode" "DF")])
10534 (define_insn "*fop_df_1_sse"
10535 [(set (match_operand:DF 0 "register_operand" "=Y")
10536 (match_operator:DF 3 "binary_fp_operator"
10537 [(match_operand:DF 1 "register_operand" "0")
10538 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
10540 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
10541 "* return output_387_binary_op (insn, operands);"
10542 [(set_attr "type" "sse")])
10544 ;; ??? Add SSE splitters for these!
10545 (define_insn "*fop_df_2"
10546 [(set (match_operand:DF 0 "register_operand" "=f,f")
10547 (match_operator:DF 3 "binary_fp_operator"
10548 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
10549 (match_operand:DF 2 "register_operand" "0,0")]))]
10550 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
10551 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
10552 [(set (attr "type")
10553 (cond [(match_operand:DF 3 "mult_operator" "")
10554 (const_string "fmul")
10555 (match_operand:DF 3 "div_operator" "")
10556 (const_string "fdiv")
10558 (const_string "fop")))
10559 (set_attr "fp_int_src" "true")
10560 (set_attr "ppro_uops" "many")
10561 (set_attr "mode" "SI")])
10563 (define_insn "*fop_df_3"
10564 [(set (match_operand:DF 0 "register_operand" "=f,f")
10565 (match_operator:DF 3 "binary_fp_operator"
10566 [(match_operand:DF 1 "register_operand" "0,0")
10567 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
10568 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
10569 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
10570 [(set (attr "type")
10571 (cond [(match_operand:DF 3 "mult_operator" "")
10572 (const_string "fmul")
10573 (match_operand:DF 3 "div_operator" "")
10574 (const_string "fdiv")
10576 (const_string "fop")))
10577 (set_attr "fp_int_src" "true")
10578 (set_attr "ppro_uops" "many")
10579 (set_attr "mode" "SI")])
10581 (define_insn "*fop_df_4"
10582 [(set (match_operand:DF 0 "register_operand" "=f,f")
10583 (match_operator:DF 3 "binary_fp_operator"
10584 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
10585 (match_operand:DF 2 "register_operand" "0,f")]))]
10587 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
10588 "* return output_387_binary_op (insn, operands);"
10589 [(set (attr "type")
10590 (cond [(match_operand:DF 3 "mult_operator" "")
10591 (const_string "fmul")
10592 (match_operand:DF 3 "div_operator" "")
10593 (const_string "fdiv")
10595 (const_string "fop")))
10596 (set_attr "mode" "SF")])
10598 (define_insn "*fop_df_5"
10599 [(set (match_operand:DF 0 "register_operand" "=f,f")
10600 (match_operator:DF 3 "binary_fp_operator"
10601 [(match_operand:DF 1 "register_operand" "0,f")
10603 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
10604 "TARGET_80387 && !TARGET_SSE2"
10605 "* return output_387_binary_op (insn, operands);"
10606 [(set (attr "type")
10607 (cond [(match_operand:DF 3 "mult_operator" "")
10608 (const_string "fmul")
10609 (match_operand:DF 3 "div_operator" "")
10610 (const_string "fdiv")
10612 (const_string "fop")))
10613 (set_attr "mode" "SF")])
10615 (define_insn "*fop_xf_1"
10616 [(set (match_operand:XF 0 "register_operand" "=f,f")
10617 (match_operator:XF 3 "binary_fp_operator"
10618 [(match_operand:XF 1 "register_operand" "0,f")
10619 (match_operand:XF 2 "register_operand" "f,0")]))]
10621 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
10622 "* return output_387_binary_op (insn, operands);"
10623 [(set (attr "type")
10624 (cond [(match_operand:XF 3 "mult_operator" "")
10625 (const_string "fmul")
10626 (match_operand:XF 3 "div_operator" "")
10627 (const_string "fdiv")
10629 (const_string "fop")))
10630 (set_attr "mode" "XF")])
10632 (define_insn "*fop_tf_1"
10633 [(set (match_operand:TF 0 "register_operand" "=f,f")
10634 (match_operator:TF 3 "binary_fp_operator"
10635 [(match_operand:TF 1 "register_operand" "0,f")
10636 (match_operand:TF 2 "register_operand" "f,0")]))]
10638 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
10639 "* return output_387_binary_op (insn, operands);"
10640 [(set (attr "type")
10641 (cond [(match_operand:TF 3 "mult_operator" "")
10642 (const_string "fmul")
10643 (match_operand:TF 3 "div_operator" "")
10644 (const_string "fdiv")
10646 (const_string "fop")))
10647 (set_attr "mode" "XF")])
10649 (define_insn "*fop_xf_2"
10650 [(set (match_operand:XF 0 "register_operand" "=f,f")
10651 (match_operator:XF 3 "binary_fp_operator"
10652 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
10653 (match_operand:XF 2 "register_operand" "0,0")]))]
10654 "TARGET_80387 && TARGET_USE_FIOP"
10655 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
10656 [(set (attr "type")
10657 (cond [(match_operand:XF 3 "mult_operator" "")
10658 (const_string "fmul")
10659 (match_operand:XF 3 "div_operator" "")
10660 (const_string "fdiv")
10662 (const_string "fop")))
10663 (set_attr "fp_int_src" "true")
10664 (set_attr "mode" "SI")
10665 (set_attr "ppro_uops" "many")])
10667 (define_insn "*fop_tf_2"
10668 [(set (match_operand:TF 0 "register_operand" "=f,f")
10669 (match_operator:TF 3 "binary_fp_operator"
10670 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
10671 (match_operand:TF 2 "register_operand" "0,0")]))]
10672 "TARGET_80387 && TARGET_USE_FIOP"
10673 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
10674 [(set (attr "type")
10675 (cond [(match_operand:TF 3 "mult_operator" "")
10676 (const_string "fmul")
10677 (match_operand:TF 3 "div_operator" "")
10678 (const_string "fdiv")
10680 (const_string "fop")))
10681 (set_attr "fp_int_src" "true")
10682 (set_attr "mode" "SI")
10683 (set_attr "ppro_uops" "many")])
10685 (define_insn "*fop_xf_3"
10686 [(set (match_operand:XF 0 "register_operand" "=f,f")
10687 (match_operator:XF 3 "binary_fp_operator"
10688 [(match_operand:XF 1 "register_operand" "0,0")
10689 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
10690 "TARGET_80387 && TARGET_USE_FIOP"
10691 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
10692 [(set (attr "type")
10693 (cond [(match_operand:XF 3 "mult_operator" "")
10694 (const_string "fmul")
10695 (match_operand:XF 3 "div_operator" "")
10696 (const_string "fdiv")
10698 (const_string "fop")))
10699 (set_attr "fp_int_src" "true")
10700 (set_attr "mode" "SI")
10701 (set_attr "ppro_uops" "many")])
10703 (define_insn "*fop_tf_3"
10704 [(set (match_operand:TF 0 "register_operand" "=f,f")
10705 (match_operator:TF 3 "binary_fp_operator"
10706 [(match_operand:TF 1 "register_operand" "0,0")
10707 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
10708 "TARGET_80387 && TARGET_USE_FIOP"
10709 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
10710 [(set (attr "type")
10711 (cond [(match_operand:TF 3 "mult_operator" "")
10712 (const_string "fmul")
10713 (match_operand:TF 3 "div_operator" "")
10714 (const_string "fdiv")
10716 (const_string "fop")))
10717 (set_attr "fp_int_src" "true")
10718 (set_attr "mode" "SI")
10719 (set_attr "ppro_uops" "many")])
10721 (define_insn "*fop_xf_4"
10722 [(set (match_operand:XF 0 "register_operand" "=f,f")
10723 (match_operator:XF 3 "binary_fp_operator"
10724 [(float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
10725 (match_operand:XF 2 "register_operand" "0,f")]))]
10727 "* return output_387_binary_op (insn, operands);"
10728 [(set (attr "type")
10729 (cond [(match_operand:XF 3 "mult_operator" "")
10730 (const_string "fmul")
10731 (match_operand:XF 3 "div_operator" "")
10732 (const_string "fdiv")
10734 (const_string "fop")))
10735 (set_attr "mode" "SF")])
10737 (define_insn "*fop_tf_4"
10738 [(set (match_operand:TF 0 "register_operand" "=f,f")
10739 (match_operator:TF 3 "binary_fp_operator"
10740 [(float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
10741 (match_operand:TF 2 "register_operand" "0,f")]))]
10743 "* return output_387_binary_op (insn, operands);"
10744 [(set (attr "type")
10745 (cond [(match_operand:TF 3 "mult_operator" "")
10746 (const_string "fmul")
10747 (match_operand:TF 3 "div_operator" "")
10748 (const_string "fdiv")
10750 (const_string "fop")))
10751 (set_attr "mode" "SF")])
10753 (define_insn "*fop_xf_5"
10754 [(set (match_operand:XF 0 "register_operand" "=f,f")
10755 (match_operator:XF 3 "binary_fp_operator"
10756 [(match_operand:XF 1 "register_operand" "0,f")
10758 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
10760 "* return output_387_binary_op (insn, operands);"
10761 [(set (attr "type")
10762 (cond [(match_operand:XF 3 "mult_operator" "")
10763 (const_string "fmul")
10764 (match_operand:XF 3 "div_operator" "")
10765 (const_string "fdiv")
10767 (const_string "fop")))
10768 (set_attr "mode" "SF")])
10770 (define_insn "*fop_tf_5"
10771 [(set (match_operand:TF 0 "register_operand" "=f,f")
10772 (match_operator:TF 3 "binary_fp_operator"
10773 [(match_operand:TF 1 "register_operand" "0,f")
10775 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
10777 "* return output_387_binary_op (insn, operands);"
10778 [(set (attr "type")
10779 (cond [(match_operand:TF 3 "mult_operator" "")
10780 (const_string "fmul")
10781 (match_operand:TF 3 "div_operator" "")
10782 (const_string "fdiv")
10784 (const_string "fop")))
10785 (set_attr "mode" "SF")])
10787 (define_insn "*fop_xf_6"
10788 [(set (match_operand:XF 0 "register_operand" "=f,f")
10789 (match_operator:XF 3 "binary_fp_operator"
10790 [(float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
10791 (match_operand:XF 2 "register_operand" "0,f")]))]
10793 "* return output_387_binary_op (insn, operands);"
10794 [(set (attr "type")
10795 (cond [(match_operand:XF 3 "mult_operator" "")
10796 (const_string "fmul")
10797 (match_operand:XF 3 "div_operator" "")
10798 (const_string "fdiv")
10800 (const_string "fop")))
10801 (set_attr "mode" "DF")])
10803 (define_insn "*fop_tf_6"
10804 [(set (match_operand:TF 0 "register_operand" "=f,f")
10805 (match_operator:TF 3 "binary_fp_operator"
10806 [(float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,0"))
10807 (match_operand:TF 2 "register_operand" "0,f")]))]
10809 "* return output_387_binary_op (insn, operands);"
10810 [(set (attr "type")
10811 (cond [(match_operand:TF 3 "mult_operator" "")
10812 (const_string "fmul")
10813 (match_operand:TF 3 "div_operator" "")
10814 (const_string "fdiv")
10816 (const_string "fop")))
10817 (set_attr "mode" "DF")])
10819 (define_insn "*fop_xf_7"
10820 [(set (match_operand:XF 0 "register_operand" "=f,f")
10821 (match_operator:XF 3 "binary_fp_operator"
10822 [(match_operand:XF 1 "register_operand" "0,f")
10824 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
10826 "* return output_387_binary_op (insn, operands);"
10827 [(set (attr "type")
10828 (cond [(match_operand:XF 3 "mult_operator" "")
10829 (const_string "fmul")
10830 (match_operand:XF 3 "div_operator" "")
10831 (const_string "fdiv")
10833 (const_string "fop")))
10834 (set_attr "mode" "DF")])
10836 (define_insn "*fop_tf_7"
10837 [(set (match_operand:TF 0 "register_operand" "=f,f")
10838 (match_operator:TF 3 "binary_fp_operator"
10839 [(match_operand:TF 1 "register_operand" "0,f")
10841 (match_operand:DF 2 "nonimmediate_operand" "fm,0"))]))]
10843 "* return output_387_binary_op (insn, operands);"
10844 [(set (attr "type")
10845 (cond [(match_operand:TF 3 "mult_operator" "")
10846 (const_string "fmul")
10847 (match_operand:TF 3 "div_operator" "")
10848 (const_string "fdiv")
10850 (const_string "fop")))
10851 (set_attr "mode" "DF")])
10854 [(set (match_operand 0 "register_operand" "")
10855 (match_operator 3 "binary_fp_operator"
10856 [(float (match_operand:SI 1 "register_operand" ""))
10857 (match_operand 2 "register_operand" "")]))]
10858 "TARGET_80387 && reload_completed
10859 && FLOAT_MODE_P (GET_MODE (operands[0]))"
10863 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
10864 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
10865 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10866 gen_rtx_fmt_ee (GET_CODE (operands[3]),
10867 GET_MODE (operands[3]),
10870 ix86_free_from_memory (GET_MODE (operands[1]));
10875 [(set (match_operand 0 "register_operand" "")
10876 (match_operator 3 "binary_fp_operator"
10877 [(match_operand 1 "register_operand" "")
10878 (float (match_operand:SI 2 "register_operand" ""))]))]
10879 "TARGET_80387 && reload_completed
10880 && FLOAT_MODE_P (GET_MODE (operands[0]))"
10884 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
10885 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
10886 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
10887 gen_rtx_fmt_ee (GET_CODE (operands[3]),
10888 GET_MODE (operands[3]),
10891 ix86_free_from_memory (GET_MODE (operands[2]));
10895 ;; FPU special functions.
10897 (define_expand "sqrtsf2"
10898 [(set (match_operand:SF 0 "register_operand" "")
10899 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
10900 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE"
10904 operands[1] = force_reg (SFmode, operands[1]);
10907 (define_insn "sqrtsf2_1"
10908 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
10909 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
10910 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
10911 && (TARGET_SSE && TARGET_MIX_SSE_I387)"
10914 sqrtss\\t{%1, %0|%0, %1}"
10915 [(set_attr "type" "fpspc,sse")
10916 (set_attr "mode" "SF,SF")
10917 (set_attr "athlon_decode" "direct,*")])
10919 (define_insn "sqrtsf2_1_sse_only"
10920 [(set (match_operand:SF 0 "register_operand" "=x")
10921 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
10922 "TARGET_SSE && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
10923 "sqrtss\\t{%1, %0|%0, %1}"
10924 [(set_attr "type" "sse")
10925 (set_attr "mode" "SF")
10926 (set_attr "athlon_decode" "*")])
10928 (define_insn "sqrtsf2_i387"
10929 [(set (match_operand:SF 0 "register_operand" "=f")
10930 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
10931 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
10932 && (!TARGET_SSE && !TARGET_MIX_SSE_I387)"
10934 [(set_attr "type" "fpspc")
10935 (set_attr "mode" "SF")
10936 (set_attr "athlon_decode" "direct")])
10938 (define_expand "sqrtdf2"
10939 [(set (match_operand:DF 0 "register_operand" "")
10940 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
10941 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
10945 operands[1] = force_reg (SFmode, operands[1]);
10948 (define_insn "sqrtdf2_1"
10949 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
10950 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
10951 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
10952 && (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
10955 sqrtsd\\t{%1, %0|%0, %1}"
10956 [(set_attr "type" "fpspc,sse")
10957 (set_attr "mode" "DF,DF")
10958 (set_attr "athlon_decode" "direct,*")])
10960 (define_insn "sqrtdf2_1_sse_only"
10961 [(set (match_operand:DF 0 "register_operand" "=Y")
10962 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
10963 "TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
10964 "sqrtsd\\t{%1, %0|%0, %1}"
10965 [(set_attr "type" "sse")
10966 (set_attr "mode" "DF")
10967 (set_attr "athlon_decode" "*")])
10969 (define_insn "sqrtdf2_i387"
10970 [(set (match_operand:DF 0 "register_operand" "=f")
10971 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
10972 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
10973 && (!TARGET_SSE2 && !TARGET_MIX_SSE_I387)"
10975 [(set_attr "type" "fpspc")
10976 (set_attr "mode" "DF")
10977 (set_attr "athlon_decode" "direct")])
10979 (define_insn "*sqrtextendsfdf2"
10980 [(set (match_operand:DF 0 "register_operand" "=f")
10981 (sqrt:DF (float_extend:DF
10982 (match_operand:SF 1 "register_operand" "0"))))]
10983 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_SSE2"
10985 [(set_attr "type" "fpspc")
10986 (set_attr "mode" "DF")
10987 (set_attr "athlon_decode" "direct")])
10989 (define_insn "sqrtxf2"
10990 [(set (match_operand:XF 0 "register_operand" "=f")
10991 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
10992 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
10993 && (TARGET_IEEE_FP || flag_fast_math) "
10995 [(set_attr "type" "fpspc")
10996 (set_attr "mode" "XF")
10997 (set_attr "athlon_decode" "direct")])
10999 (define_insn "sqrttf2"
11000 [(set (match_operand:TF 0 "register_operand" "=f")
11001 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
11002 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
11003 && (TARGET_IEEE_FP || flag_fast_math) "
11005 [(set_attr "type" "fpspc")
11006 (set_attr "mode" "XF")
11007 (set_attr "athlon_decode" "direct")])
11009 (define_insn "*sqrtextenddfxf2"
11010 [(set (match_operand:XF 0 "register_operand" "=f")
11011 (sqrt:XF (float_extend:XF
11012 (match_operand:DF 1 "register_operand" "0"))))]
11013 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
11015 [(set_attr "type" "fpspc")
11016 (set_attr "mode" "XF")
11017 (set_attr "athlon_decode" "direct")])
11019 (define_insn "*sqrtextenddftf2"
11020 [(set (match_operand:TF 0 "register_operand" "=f")
11021 (sqrt:TF (float_extend:TF
11022 (match_operand:DF 1 "register_operand" "0"))))]
11023 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
11025 [(set_attr "type" "fpspc")
11026 (set_attr "mode" "XF")
11027 (set_attr "athlon_decode" "direct")])
11029 (define_insn "*sqrtextendsfxf2"
11030 [(set (match_operand:XF 0 "register_operand" "=f")
11031 (sqrt:XF (float_extend:XF
11032 (match_operand:SF 1 "register_operand" "0"))))]
11033 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
11035 [(set_attr "type" "fpspc")
11036 (set_attr "mode" "XF")
11037 (set_attr "athlon_decode" "direct")])
11039 (define_insn "*sqrtextendsftf2"
11040 [(set (match_operand:TF 0 "register_operand" "=f")
11041 (sqrt:TF (float_extend:TF
11042 (match_operand:SF 1 "register_operand" "0"))))]
11043 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
11045 [(set_attr "type" "fpspc")
11046 (set_attr "mode" "XF")
11047 (set_attr "athlon_decode" "direct")])
11049 (define_insn "sindf2"
11050 [(set (match_operand:DF 0 "register_operand" "=f")
11051 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
11052 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
11054 [(set_attr "type" "fpspc")
11055 (set_attr "mode" "DF")])
11057 (define_insn "sinsf2"
11058 [(set (match_operand:SF 0 "register_operand" "=f")
11059 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
11060 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
11062 [(set_attr "type" "fpspc")
11063 (set_attr "mode" "SF")])
11065 (define_insn "*sinextendsfdf2"
11066 [(set (match_operand:DF 0 "register_operand" "=f")
11067 (unspec:DF [(float_extend:DF
11068 (match_operand:SF 1 "register_operand" "0"))] 1))]
11069 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
11071 [(set_attr "type" "fpspc")
11072 (set_attr "mode" "DF")])
11074 (define_insn "sinxf2"
11075 [(set (match_operand:XF 0 "register_operand" "=f")
11076 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
11077 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
11079 [(set_attr "type" "fpspc")
11080 (set_attr "mode" "XF")])
11082 (define_insn "sintf2"
11083 [(set (match_operand:TF 0 "register_operand" "=f")
11084 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 1))]
11085 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
11087 [(set_attr "type" "fpspc")
11088 (set_attr "mode" "XF")])
11090 (define_insn "cosdf2"
11091 [(set (match_operand:DF 0 "register_operand" "=f")
11092 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
11093 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
11095 [(set_attr "type" "fpspc")
11096 (set_attr "mode" "DF")])
11098 (define_insn "cossf2"
11099 [(set (match_operand:SF 0 "register_operand" "=f")
11100 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
11101 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
11103 [(set_attr "type" "fpspc")
11104 (set_attr "mode" "SF")])
11106 (define_insn "*cosextendsfdf2"
11107 [(set (match_operand:DF 0 "register_operand" "=f")
11108 (unspec:DF [(float_extend:DF
11109 (match_operand:SF 1 "register_operand" "0"))] 2))]
11110 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
11112 [(set_attr "type" "fpspc")
11113 (set_attr "mode" "DF")])
11115 (define_insn "cosxf2"
11116 [(set (match_operand:XF 0 "register_operand" "=f")
11117 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
11118 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
11120 [(set_attr "type" "fpspc")
11121 (set_attr "mode" "XF")])
11123 (define_insn "costf2"
11124 [(set (match_operand:TF 0 "register_operand" "=f")
11125 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] 2))]
11126 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
11128 [(set_attr "type" "fpspc")
11129 (set_attr "mode" "XF")])
11131 ;; Block operation instructions
11134 [(set (reg:SI 19) (const_int 0))]
11137 [(set_attr "type" "cld")])
11139 (define_expand "movstrsi"
11140 [(use (match_operand:BLK 0 "memory_operand" ""))
11141 (use (match_operand:BLK 1 "memory_operand" ""))
11142 (use (match_operand:SI 2 "nonmemory_operand" ""))
11143 (use (match_operand:SI 3 "const_int_operand" ""))]
11147 rtx srcreg, destreg, countreg;
11154 if (GET_CODE (operands[3]) == CONST_INT)
11155 align = INTVAL (operands[3]);
11157 /* This simple hack avoids all inlining code and simplifies code bellow. */
11158 if (!TARGET_ALIGN_STRINGOPS)
11161 if (GET_CODE (operands[2]) == CONST_INT)
11162 count = INTVAL (operands[2]);
11164 destreg = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
11165 srcreg = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
11167 emit_insn (gen_cld ());
11169 /* When optimizing for size emit simple rep ; movsb instruction for
11170 counts not divisible by 4. */
11172 if ((!optimize || optimize_size)
11173 && (count < 0 || (count & 0x03)))
11175 countreg = copy_to_mode_reg (SImode, operands[2]);
11176 emit_insn (gen_rep_movqi (destreg, srcreg, countreg,
11177 destreg, srcreg, countreg));
11180 /* For constant aligned (or small unaligned) copies use rep movsl
11181 followed by code copying the rest. For PentiumPro ensure 8 byte
11182 alignment to allow rep movsl acceleration. */
11184 else if (count >= 0
11186 || (!TARGET_PENTIUMPRO && align >= 4)
11187 || optimize_size || count < 64))
11191 countreg = copy_to_mode_reg (SImode,
11192 GEN_INT ((count >> 2)
11194 emit_insn (gen_rep_movsi (destreg, srcreg, countreg,
11195 destreg, srcreg, countreg));
11198 emit_insn (gen_strmovhi (destreg, srcreg));
11200 emit_insn (gen_strmovqi (destreg, srcreg));
11202 /* The generic code based on the glibc implementation:
11203 - align destination to 4 bytes (8 byte alignment is used for PentiumPro
11204 allowing accelerated copying there)
11205 - copy the data using rep movsl
11206 - copy the rest. */
11212 /* In case we don't know anything about the alignment, default to
11213 library version, since it is usually equally fast and result in
11215 if (!TARGET_INLINE_ALL_STRINGOPS && align < 4)
11221 if (TARGET_SINGLE_STRINGOP)
11222 emit_insn (gen_cld ());
11224 countreg2 = gen_reg_rtx (SImode);
11225 countreg = copy_to_mode_reg (SImode, operands[2]);
11227 /* We don't use loops to align destination and to copy parts smaller
11228 than 4 bytes, because gcc is able to optimize such code better (in
11229 the case the destination or the count really is aligned, gcc is often
11230 able to predict the branches) and also it is friendlier to the
11231 hardware branch prediction.
11233 Using loops is benefical for generic case, because we can
11234 handle small counts using the loops. Many CPUs (such as Athlon)
11235 have large REP prefix setup costs.
11237 This is quite costy. Maybe we can revisit this decision later or
11238 add some customizability to this code. */
11241 && align < (TARGET_PENTIUMPRO && (count < 0 || count >= 260) ? 8 : 4))
11243 label = gen_label_rtx ();
11244 emit_cmp_and_jump_insns (countreg, GEN_INT (3),
11245 LEU, 0, SImode, 1, 0, label);
11249 rtx label = gen_label_rtx ();
11250 rtx tmpcount = gen_reg_rtx (SImode);
11251 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (1)));
11252 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
11253 SImode, 1, 0, label);
11254 emit_insn (gen_strmovqi (destreg, srcreg));
11255 emit_insn (gen_addsi3 (countreg, countreg, constm1_rtx));
11256 emit_label (label);
11257 LABEL_NUSES (label) = 1;
11261 rtx label = gen_label_rtx ();
11262 rtx tmpcount = gen_reg_rtx (SImode);
11263 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (2)));
11264 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
11265 SImode, 1, 0, label);
11266 emit_insn (gen_strmovhi (destreg, srcreg));
11267 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-2)));
11268 emit_label (label);
11269 LABEL_NUSES (label) = 1;
11271 if (align <= 4 && TARGET_PENTIUMPRO && (count < 1 || count >= 260))
11273 rtx label = gen_label_rtx ();
11274 rtx tmpcount = gen_reg_rtx (SImode);
11275 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (4)));
11276 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
11277 SImode, 1, 0, label);
11278 emit_insn (gen_strmovsi (destreg, srcreg));
11279 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-4)));
11280 emit_label (label);
11281 LABEL_NUSES (label) = 1;
11284 if (!TARGET_SINGLE_STRINGOP)
11285 emit_insn (gen_cld());
11286 emit_insn (gen_lshrsi3 (countreg2, countreg, GEN_INT (2)));
11287 emit_insn (gen_rep_movsi (destreg, srcreg, countreg2,
11288 destreg, srcreg, countreg2));
11292 emit_label (label);
11293 LABEL_NUSES (label) = 1;
11295 if (align > 2 && count > 0 && (count & 2))
11296 emit_insn (gen_strmovhi (destreg, srcreg));
11297 if (align <= 2 || count < 0)
11299 rtx label = gen_label_rtx ();
11300 rtx tmpcount = gen_reg_rtx (SImode);
11301 emit_insn (gen_andsi3 (tmpcount, countreg, GEN_INT (2)));
11302 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
11303 SImode, 1, 0, label);
11304 emit_insn (gen_strmovhi (destreg, srcreg));
11305 emit_label (label);
11306 LABEL_NUSES (label) = 1;
11308 if (align > 1 && count > 0 && (count & 1))
11309 emit_insn (gen_strmovsi (destreg, srcreg));
11310 if (align <= 1 || count < 0)
11312 rtx label = gen_label_rtx ();
11313 rtx tmpcount = gen_reg_rtx (SImode);
11314 emit_insn (gen_andsi3 (tmpcount, countreg, GEN_INT (1)));
11315 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
11316 SImode, 1, 0, label);
11317 emit_insn (gen_strmovqi (destreg, srcreg));
11318 emit_label (label);
11319 LABEL_NUSES (label) = 1;
11323 insns = get_insns ();
11326 ix86_set_move_mem_attrs (insns, operands[0], operands[1], destreg, srcreg);
11327 emit_insns (insns);
11331 ;; Most CPUs don't like single string operations
11332 ;; Handle this case here to simplify previous expander.
11334 (define_expand "strmovsi"
11335 [(set (match_dup 2)
11336 (mem:SI (match_operand:SI 1 "register_operand" "")))
11337 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
11339 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
11340 (clobber (reg:CC 17))])
11341 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
11342 (clobber (reg:CC 17))])]
11346 if (TARGET_SINGLE_STRINGOP || optimize_size)
11348 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
11353 operands[2] = gen_reg_rtx (SImode);
11356 (define_expand "strmovhi"
11357 [(set (match_dup 2)
11358 (mem:HI (match_operand:SI 1 "register_operand" "")))
11359 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
11361 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
11362 (clobber (reg:CC 17))])
11363 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
11364 (clobber (reg:CC 17))])]
11368 if (TARGET_SINGLE_STRINGOP || optimize_size)
11370 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
11375 operands[2] = gen_reg_rtx (HImode);
11378 (define_expand "strmovqi"
11379 [(set (match_dup 2)
11380 (mem:QI (match_operand:SI 1 "register_operand" "")))
11381 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
11383 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
11384 (clobber (reg:CC 17))])
11385 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
11386 (clobber (reg:CC 17))])]
11390 if (TARGET_SINGLE_STRINGOP || optimize_size)
11392 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
11397 operands[2] = gen_reg_rtx (QImode);
11400 (define_insn "strmovsi_1"
11401 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
11402 (mem:SI (match_operand:SI 3 "register_operand" "1")))
11403 (set (match_operand:SI 0 "register_operand" "=D")
11404 (plus:SI (match_dup 2)
11406 (set (match_operand:SI 1 "register_operand" "=S")
11407 (plus:SI (match_dup 3)
11410 "TARGET_SINGLE_STRINGOP || optimize_size"
11412 [(set_attr "type" "str")
11413 (set_attr "mode" "SI")
11414 (set_attr "memory" "both")])
11416 (define_insn "strmovhi_1"
11417 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
11418 (mem:HI (match_operand:SI 3 "register_operand" "1")))
11419 (set (match_operand:SI 0 "register_operand" "=D")
11420 (plus:SI (match_dup 2)
11422 (set (match_operand:SI 1 "register_operand" "=S")
11423 (plus:SI (match_dup 3)
11426 "TARGET_SINGLE_STRINGOP || optimize_size"
11428 [(set_attr "type" "str")
11429 (set_attr "memory" "both")
11430 (set_attr "mode" "HI")])
11432 (define_insn "strmovqi_1"
11433 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
11434 (mem:QI (match_operand:SI 3 "register_operand" "1")))
11435 (set (match_operand:SI 0 "register_operand" "=D")
11436 (plus:SI (match_dup 2)
11438 (set (match_operand:SI 1 "register_operand" "=S")
11439 (plus:SI (match_dup 3)
11442 "TARGET_SINGLE_STRINGOP || optimize_size"
11444 [(set_attr "type" "str")
11445 (set_attr "memory" "both")
11446 (set_attr "mode" "QI")])
11448 (define_insn "rep_movsi"
11449 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
11450 (set (match_operand:SI 0 "register_operand" "=D")
11451 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
11453 (match_operand:SI 3 "register_operand" "0")))
11454 (set (match_operand:SI 1 "register_operand" "=S")
11455 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
11456 (match_operand:SI 4 "register_operand" "1")))
11457 (set (mem:BLK (match_dup 3))
11458 (mem:BLK (match_dup 4)))
11459 (use (match_dup 5))
11462 "rep\;movsl|rep movsd"
11463 [(set_attr "type" "str")
11464 (set_attr "prefix_rep" "1")
11465 (set_attr "memory" "both")
11466 (set_attr "mode" "SI")])
11468 (define_insn "rep_movqi"
11469 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
11470 (set (match_operand:SI 0 "register_operand" "=D")
11471 (plus:SI (match_operand:SI 3 "register_operand" "0")
11472 (match_operand:SI 5 "register_operand" "2")))
11473 (set (match_operand:SI 1 "register_operand" "=S")
11474 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
11475 (set (mem:BLK (match_dup 3))
11476 (mem:BLK (match_dup 4)))
11477 (use (match_dup 5))
11480 "rep\;movsb|rep movsb"
11481 [(set_attr "type" "str")
11482 (set_attr "prefix_rep" "1")
11483 (set_attr "memory" "both")
11484 (set_attr "mode" "SI")])
11486 (define_expand "clrstrsi"
11487 [(use (match_operand:BLK 0 "memory_operand" ""))
11488 (use (match_operand:SI 1 "nonmemory_operand" ""))
11489 (use (match_operand:SI 2 "const_int_operand" ""))]
11493 /* See comments in movstr expanders. The code is mostly identical. */
11495 rtx destreg, zeroreg, countreg;
11499 if (GET_CODE (operands[2]) == CONST_INT)
11500 align = INTVAL (operands[2]);
11502 /* This simple hack avoids all inlining code and simplifies code bellow. */
11503 if (!TARGET_ALIGN_STRINGOPS)
11506 if (GET_CODE (operands[1]) == CONST_INT)
11507 count = INTVAL (operands[1]);
11509 destreg = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
11511 emit_insn (gen_cld());
11513 /* When optimizing for size emit simple rep ; movsb instruction for
11514 counts not divisible by 4. */
11516 if ((!optimize || optimize_size)
11517 && (count < 0 || (count & 0x03)))
11519 countreg = copy_to_mode_reg (SImode, operands[1]);
11520 zeroreg = copy_to_mode_reg (QImode, const0_rtx);
11521 emit_insn (gen_rep_stosqi (destreg, countreg, zeroreg,
11522 destreg, countreg));
11524 else if (count >= 0
11526 || (!TARGET_PENTIUMPRO && align >= 4)
11527 || optimize_size || count < 64))
11529 zeroreg = copy_to_mode_reg (SImode, const0_rtx);
11530 if (INTVAL (operands[1]) & ~0x03)
11532 countreg = copy_to_mode_reg (SImode,
11533 GEN_INT ((INTVAL (operands[1]) >> 2)
11535 emit_insn (gen_rep_stossi (destreg, countreg, zeroreg,
11536 destreg, countreg));
11538 if (INTVAL (operands[1]) & 0x02)
11539 emit_insn (gen_strsethi (destreg,
11540 gen_rtx_SUBREG (HImode, zeroreg, 0)));
11541 if (INTVAL (operands[1]) & 0x01)
11542 emit_insn (gen_strsetqi (destreg,
11543 gen_rtx_SUBREG (QImode, zeroreg, 0)));
11550 /* In case we don't know anything about the alignment, default to
11551 library version, since it is usually equally fast and result in
11553 if (!TARGET_INLINE_ALL_STRINGOPS && align < 4)
11556 if (TARGET_SINGLE_STRINGOP)
11557 emit_insn (gen_cld());
11559 countreg2 = gen_reg_rtx (SImode);
11560 countreg = copy_to_mode_reg (SImode, operands[1]);
11561 zeroreg = copy_to_mode_reg (SImode, const0_rtx);
11564 && align < (TARGET_PENTIUMPRO && (count < 0 || count >= 260) ? 8 : 4))
11566 label = gen_label_rtx ();
11567 emit_cmp_and_jump_insns (countreg, GEN_INT (3),
11568 LEU, 0, SImode, 1, 0, label);
11572 rtx label = gen_label_rtx ();
11573 rtx tmpcount = gen_reg_rtx (SImode);
11574 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (1)));
11575 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
11576 SImode, 1, 0, label);
11577 emit_insn (gen_strsetqi (destreg,
11578 gen_rtx_SUBREG (QImode, zeroreg, 0)));
11579 emit_insn (gen_addsi3 (countreg, countreg, constm1_rtx));
11580 emit_label (label);
11581 LABEL_NUSES (label) = 1;
11585 rtx label = gen_label_rtx ();
11586 rtx tmpcount = gen_reg_rtx (SImode);
11587 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (2)));
11588 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
11589 SImode, 1, 0, label);
11590 emit_insn (gen_strsethi (destreg,
11591 gen_rtx_SUBREG (HImode, zeroreg, 0)));
11592 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-2)));
11593 emit_label (label);
11594 LABEL_NUSES (label) = 1;
11596 if (align <= 4 && TARGET_PENTIUMPRO && (count < 1 || count >= 260))
11598 rtx label = gen_label_rtx ();
11599 rtx tmpcount = gen_reg_rtx (SImode);
11600 emit_insn (gen_andsi3 (tmpcount, destreg, GEN_INT (4)));
11601 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
11602 SImode, 1, 0, label);
11603 emit_insn (gen_strsetsi (destreg, zeroreg));
11604 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-4)));
11605 emit_label (label);
11606 LABEL_NUSES (label) = 1;
11609 if (!TARGET_SINGLE_STRINGOP)
11610 emit_insn (gen_cld());
11611 emit_insn (gen_lshrsi3 (countreg2, countreg, GEN_INT (2)));
11612 emit_insn (gen_rep_stossi (destreg, countreg2, zeroreg,
11613 destreg, countreg2));
11617 emit_label (label);
11618 LABEL_NUSES (label) = 1;
11620 if (align > 2 && count > 0 && (count & 2))
11621 emit_insn (gen_strsethi (destreg,
11622 gen_rtx_SUBREG (HImode, zeroreg, 0)));
11623 if (align <= 2 || count < 0)
11625 rtx label = gen_label_rtx ();
11626 rtx tmpcount = gen_reg_rtx (SImode);
11627 emit_insn (gen_andsi3 (tmpcount, countreg, GEN_INT (2)));
11628 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
11629 SImode, 1, 0, label);
11630 emit_insn (gen_strsethi (destreg,
11631 gen_rtx_SUBREG (HImode, zeroreg, 0)));
11632 emit_label (label);
11633 LABEL_NUSES (label) = 1;
11635 if (align > 1 && count > 0 && (count & 1))
11636 emit_insn (gen_strsetqi (destreg,
11637 gen_rtx_SUBREG (QImode, zeroreg, 0)));
11638 if (align <= 1 || count < 0)
11640 rtx label = gen_label_rtx ();
11641 rtx tmpcount = gen_reg_rtx (SImode);
11642 emit_insn (gen_andsi3 (tmpcount, countreg, GEN_INT (1)));
11643 emit_cmp_and_jump_insns (tmpcount, GEN_INT (0), EQ, 0,
11644 SImode, 1, 0, label);
11645 emit_insn (gen_strsetqi (destreg,
11646 gen_rtx_SUBREG (QImode, zeroreg, 0)));
11647 emit_label (label);
11648 LABEL_NUSES (label) = 1;
11654 ;; Most CPUs don't like single string operations
11655 ;; Handle this case here to simplify previous expander.
11657 (define_expand "strsetsi"
11658 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
11659 (match_operand:SI 1 "register_operand" ""))
11660 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
11661 (clobber (reg:CC 17))])]
11665 if (TARGET_SINGLE_STRINGOP || optimize_size)
11667 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
11672 (define_expand "strsethi"
11673 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
11674 (match_operand:HI 1 "register_operand" ""))
11675 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
11676 (clobber (reg:CC 17))])]
11680 if (TARGET_SINGLE_STRINGOP || optimize_size)
11682 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
11687 (define_expand "strsetqi"
11688 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
11689 (match_operand:QI 1 "register_operand" ""))
11690 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
11691 (clobber (reg:CC 17))])]
11695 if (TARGET_SINGLE_STRINGOP || optimize_size)
11697 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
11702 (define_insn "strsetsi_1"
11703 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
11704 (match_operand:SI 2 "register_operand" "a"))
11705 (set (match_operand:SI 0 "register_operand" "=D")
11706 (plus:SI (match_dup 1)
11709 "TARGET_SINGLE_STRINGOP || optimize_size"
11711 [(set_attr "type" "str")
11712 (set_attr "memory" "store")
11713 (set_attr "mode" "SI")])
11715 (define_insn "strsethi_1"
11716 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
11717 (match_operand:HI 2 "register_operand" "a"))
11718 (set (match_operand:SI 0 "register_operand" "=D")
11719 (plus:SI (match_dup 1)
11722 "TARGET_SINGLE_STRINGOP || optimize_size"
11724 [(set_attr "type" "str")
11725 (set_attr "memory" "store")
11726 (set_attr "mode" "HI")])
11728 (define_insn "strsetqi_1"
11729 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
11730 (match_operand:QI 2 "register_operand" "a"))
11731 (set (match_operand:SI 0 "register_operand" "=D")
11732 (plus:SI (match_dup 1)
11735 "TARGET_SINGLE_STRINGOP || optimize_size"
11737 [(set_attr "type" "str")
11738 (set_attr "memory" "store")
11739 (set_attr "mode" "QI")])
11741 (define_insn "rep_stossi"
11742 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
11743 (set (match_operand:SI 0 "register_operand" "=D")
11744 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
11746 (match_operand:SI 3 "register_operand" "0")))
11747 (set (mem:BLK (match_dup 3))
11749 (use (match_operand:SI 2 "register_operand" "a"))
11750 (use (match_dup 4))
11753 "rep\;stosl|rep stosd"
11754 [(set_attr "type" "str")
11755 (set_attr "prefix_rep" "1")
11756 (set_attr "memory" "store")
11757 (set_attr "mode" "SI")])
11759 (define_insn "rep_stosqi"
11760 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
11761 (set (match_operand:SI 0 "register_operand" "=D")
11762 (plus:SI (match_operand:SI 3 "register_operand" "0")
11763 (match_operand:SI 4 "register_operand" "1")))
11764 (set (mem:BLK (match_dup 3))
11766 (use (match_operand:QI 2 "register_operand" "a"))
11767 (use (match_dup 4))
11770 "rep\;stosb|rep stosb"
11771 [(set_attr "type" "str")
11772 (set_attr "prefix_rep" "1")
11773 (set_attr "memory" "store")
11774 (set_attr "mode" "QI")])
11776 (define_expand "cmpstrsi"
11777 [(set (match_operand:SI 0 "register_operand" "")
11778 (compare:SI (match_operand:BLK 1 "general_operand" "")
11779 (match_operand:BLK 2 "general_operand" "")))
11780 (use (match_operand:SI 3 "general_operand" ""))
11781 (use (match_operand:SI 4 "immediate_operand" ""))]
11785 rtx addr1, addr2, out, outlow, count, countreg, align;
11788 if (GET_CODE (out) != REG)
11789 out = gen_reg_rtx (SImode);
11791 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
11792 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
11794 count = operands[3];
11795 countreg = copy_to_mode_reg (SImode, count);
11797 /* %%% Iff we are testing strict equality, we can use known alignment
11798 to good advantage. This may be possible with combine, particularly
11799 once cc0 is dead. */
11800 align = operands[4];
11802 emit_insn (gen_cld ());
11803 if (GET_CODE (count) == CONST_INT)
11805 if (INTVAL (count) == 0)
11807 emit_move_insn (operands[0], const0_rtx);
11810 emit_insn (gen_cmpstrsi_nz_1 (addr1, addr2, countreg, align,
11811 addr1, addr2, countreg));
11815 emit_insn (gen_cmpsi_1 (countreg, countreg));
11816 emit_insn (gen_cmpstrsi_1 (addr1, addr2, countreg, align,
11817 addr1, addr2, countreg));
11820 outlow = gen_lowpart (QImode, out);
11821 emit_insn (gen_cmpintqi (outlow));
11822 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
11824 if (operands[0] != out)
11825 emit_move_insn (operands[0], out);
11830 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
11832 (define_expand "cmpintqi"
11833 [(set (match_dup 1)
11834 (gtu:QI (reg:CC 17) (const_int 0)))
11836 (ltu:QI (reg:CC 17) (const_int 0)))
11837 (parallel [(set (match_operand:QI 0 "register_operand" "")
11838 (minus:QI (match_dup 1)
11840 (clobber (reg:CC 17))])]
11842 "operands[1] = gen_reg_rtx (QImode);
11843 operands[2] = gen_reg_rtx (QImode);")
11845 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
11846 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
11848 (define_insn "cmpstrsi_nz_1"
11850 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
11851 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
11852 (use (match_operand:SI 6 "register_operand" "2"))
11853 (use (match_operand:SI 3 "immediate_operand" "i"))
11855 (clobber (match_operand:SI 0 "register_operand" "=S"))
11856 (clobber (match_operand:SI 1 "register_operand" "=D"))
11857 (clobber (match_operand:SI 2 "register_operand" "=c"))]
11860 [(set_attr "type" "str")
11861 (set_attr "mode" "QI")
11862 (set_attr "prefix_rep" "1")])
11864 ;; The same, but the count is not known to not be zero.
11866 (define_insn "cmpstrsi_1"
11868 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
11870 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
11871 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
11873 (use (match_operand:SI 3 "immediate_operand" "i"))
11876 (clobber (match_operand:SI 0 "register_operand" "=S"))
11877 (clobber (match_operand:SI 1 "register_operand" "=D"))
11878 (clobber (match_operand:SI 2 "register_operand" "=c"))]
11881 [(set_attr "type" "str")
11882 (set_attr "mode" "QI")
11883 (set_attr "prefix_rep" "1")])
11885 (define_expand "strlensi"
11886 [(set (match_operand:SI 0 "register_operand" "")
11887 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
11888 (match_operand:QI 2 "immediate_operand" "")
11889 (match_operand:SI 3 "immediate_operand" "")] 0))]
11893 rtx out, addr, scratch1, scratch2, scratch3;
11894 rtx eoschar = operands[2];
11895 rtx align = operands[3];
11897 /* The generic case of strlen expander is long. Avoid it's
11898 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
11900 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
11901 && !TARGET_INLINE_ALL_STRINGOPS
11903 && (GET_CODE (align) != CONST_INT || INTVAL (align) < 4))
11907 addr = force_reg (Pmode, XEXP (operands[1], 0));
11908 scratch1 = gen_reg_rtx (SImode);
11910 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
11913 /* Well it seems that some optimizer does not combine a call like
11914 foo(strlen(bar), strlen(bar));
11915 when the move and the subtraction is done here. It does calculate
11916 the length just once when these instructions are done inside of
11917 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
11918 often used and I use one fewer register for the lifetime of
11919 output_strlen_unroll() this is better. */
11921 if (GET_CODE (align) != CONST_INT || INTVAL (align) < 4)
11922 emit_move_insn (scratch1, addr);
11924 emit_move_insn (out, addr);
11926 ix86_expand_strlensi_unroll_1 (out, align, scratch1);
11928 /* strlensi_unroll_1 returns the address of the zero at the end of
11929 the string, like memchr(), so compute the length by subtracting
11930 the start address. */
11931 emit_insn (gen_subsi3 (out, out, addr));
11935 scratch2 = gen_reg_rtx (SImode);
11936 scratch3 = gen_reg_rtx (SImode);
11938 emit_move_insn (scratch3, addr);
11940 emit_insn (gen_cld ());
11941 emit_insn (gen_strlensi_1 (scratch1, scratch3, eoschar,
11942 align, constm1_rtx, scratch3));
11943 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
11944 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
11949 (define_insn "strlensi_1"
11950 [(set (match_operand:SI 0 "register_operand" "=&c")
11951 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
11952 (match_operand:QI 2 "general_operand" "a")
11953 (match_operand:SI 3 "immediate_operand" "i")
11954 (match_operand:SI 4 "immediate_operand" "0")] 0))
11956 (clobber (match_operand:SI 1 "register_operand" "=D"))
11957 (clobber (reg:CC 17))]
11960 [(set_attr "type" "str")
11961 (set_attr "mode" "QI")
11962 (set_attr "prefix_rep" "1")])
11964 ;; Conditional move instructions.
11966 (define_expand "movsicc"
11967 [(set (match_operand:SI 0 "register_operand" "")
11968 (if_then_else:SI (match_operand 1 "comparison_operator" "")
11969 (match_operand:SI 2 "general_operand" "")
11970 (match_operand:SI 3 "general_operand" "")))]
11972 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
11974 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
11975 ;; the register first winds up with `sbbl $0,reg', which is also weird.
11976 ;; So just document what we're doing explicitly.
11978 (define_insn "x86_movsicc_0_m1"
11979 [(set (match_operand:SI 0 "register_operand" "=r")
11980 (if_then_else:SI (ltu (reg:CC 17) (const_int 0))
11983 (clobber (reg:CC 17))]
11986 ; Since we don't have the proper number of operands for an alu insn,
11987 ; fill in all the blanks.
11988 [(set_attr "type" "alu")
11989 (set_attr "memory" "none")
11990 (set_attr "imm_disp" "false")
11991 (set_attr "mode" "SI")
11992 (set_attr "length_immediate" "0")])
11994 (define_insn "*movsicc_noc"
11995 [(set (match_operand:SI 0 "register_operand" "=r,r")
11996 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
11997 [(reg 17) (const_int 0)])
11998 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
11999 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
12001 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
12003 cmov%C1\\t{%2, %0|%0, %2}
12004 cmov%c1\\t{%3, %0|%0, %3}"
12005 [(set_attr "type" "icmov")
12006 (set_attr "mode" "SI")])
12008 (define_expand "movhicc"
12009 [(set (match_operand:HI 0 "register_operand" "")
12010 (if_then_else:HI (match_operand 1 "comparison_operator" "")
12011 (match_operand:HI 2 "nonimmediate_operand" "")
12012 (match_operand:HI 3 "nonimmediate_operand" "")))]
12013 "TARGET_CMOVE && TARGET_HIMODE_MATH"
12014 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
12016 (define_insn "*movhicc_noc"
12017 [(set (match_operand:HI 0 "register_operand" "=r,r")
12018 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
12019 [(reg 17) (const_int 0)])
12020 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
12021 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
12023 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
12025 cmov%C1\\t{%2, %0|%0, %2}
12026 cmov%c1\\t{%3, %0|%0, %3}"
12027 [(set_attr "type" "icmov")
12028 (set_attr "mode" "HI")])
12030 (define_expand "movsfcc"
12031 [(set (match_operand:SF 0 "register_operand" "")
12032 (if_then_else:SF (match_operand 1 "comparison_operator" "")
12033 (match_operand:SF 2 "register_operand" "")
12034 (match_operand:SF 3 "register_operand" "")))]
12036 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
12038 (define_insn "*movsfcc_1"
12039 [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
12040 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
12041 [(reg 17) (const_int 0)])
12042 (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
12043 (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
12045 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
12047 fcmov%F1\\t{%2, %0|%0, %2}
12048 fcmov%f1\\t{%3, %0|%0, %3}
12049 cmov%C1\\t{%2, %0|%0, %2}
12050 cmov%c1\\t{%3, %0|%0, %3}"
12051 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
12052 (set_attr "mode" "SF,SF,SI,SI")])
12054 (define_expand "movdfcc"
12055 [(set (match_operand:DF 0 "register_operand" "")
12056 (if_then_else:DF (match_operand 1 "comparison_operator" "")
12057 (match_operand:DF 2 "register_operand" "")
12058 (match_operand:DF 3 "register_operand" "")))]
12060 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
12062 (define_insn "*movdfcc_1"
12063 [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
12064 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
12065 [(reg 17) (const_int 0)])
12066 (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
12067 (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
12069 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
12071 fcmov%F1\\t{%2, %0|%0, %2}
12072 fcmov%f1\\t{%3, %0|%0, %3}
12075 [(set_attr "type" "fcmov,fcmov,multi,multi")
12076 (set_attr "mode" "DF")])
12079 [(set (match_operand:DF 0 "register_operand" "")
12080 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
12081 [(match_operand 4 "" "") (const_int 0)])
12082 (match_operand:DF 2 "nonimmediate_operand" "")
12083 (match_operand:DF 3 "nonimmediate_operand" "")))]
12084 "!ANY_FP_REG_P (operands[0]) && reload_completed"
12085 [(set (match_dup 2)
12086 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
12090 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
12093 "split_di (operands+2, 1, operands+5, operands+6);
12094 split_di (operands+3, 1, operands+7, operands+8);
12095 split_di (operands, 1, operands+2, operands+3);")
12097 (define_expand "movxfcc"
12098 [(set (match_operand:XF 0 "register_operand" "")
12099 (if_then_else:XF (match_operand 1 "comparison_operator" "")
12100 (match_operand:XF 2 "register_operand" "")
12101 (match_operand:XF 3 "register_operand" "")))]
12103 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
12105 (define_expand "movtfcc"
12106 [(set (match_operand:TF 0 "register_operand" "")
12107 (if_then_else:TF (match_operand 1 "comparison_operator" "")
12108 (match_operand:TF 2 "register_operand" "")
12109 (match_operand:TF 3 "register_operand" "")))]
12111 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
12113 (define_insn "*movxfcc_1"
12114 [(set (match_operand:XF 0 "register_operand" "=f,f")
12115 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
12116 [(reg 17) (const_int 0)])
12117 (match_operand:XF 2 "register_operand" "f,0")
12118 (match_operand:XF 3 "register_operand" "0,f")))]
12121 fcmov%F1\\t{%2, %0|%0, %2}
12122 fcmov%f1\\t{%3, %0|%0, %3}"
12123 [(set_attr "type" "fcmov")
12124 (set_attr "mode" "XF")])
12126 (define_insn "*movtfcc_1"
12127 [(set (match_operand:TF 0 "register_operand" "=f,f")
12128 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
12129 [(reg 17) (const_int 0)])
12130 (match_operand:TF 2 "register_operand" "f,0")
12131 (match_operand:TF 3 "register_operand" "0,f")))]
12134 fcmov%F1\\t{%2, %0|%0, %2}
12135 fcmov%f1\\t{%3, %0|%0, %3}"
12136 [(set_attr "type" "fcmov")
12137 (set_attr "mode" "XF")])
12139 (define_expand "minsf3"
12141 (set (match_operand:SF 0 "register_operand" "")
12142 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
12143 (match_operand:SF 2 "nonimmediate_operand" ""))
12146 (clobber (reg:CC 17))])]
12150 (define_insn "*minsf"
12151 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
12152 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
12153 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
12156 (clobber (reg:CC 17))]
12157 "TARGET_SSE && TARGET_IEEE_FP"
12160 (define_insn "*minsf_nonieee"
12161 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
12162 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0")
12163 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
12166 (clobber (reg:CC 17))]
12167 "TARGET_SSE && !TARGET_IEEE_FP"
12171 [(set (match_operand:SF 0 "register_operand" "")
12172 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
12173 (match_operand:SF 2 "nonimmediate_operand" ""))
12176 (clobber (reg:CC 17))]
12177 "SSE_REG_P (operands[0]) && reload_completed"
12178 [(set (match_dup 0)
12179 (if_then_else:SF (lt (match_dup 1)
12184 ;; We can't represent the LT test directly. Do this by swapping the operands.
12186 [(set (match_operand:SF 0 "register_operand" "")
12187 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
12188 (match_operand:SF 2 "register_operand" ""))
12191 (clobber (reg:CC 17))]
12192 "FP_REG_P (operands[0]) && reload_completed"
12193 [(set (reg:CCFP 17)
12194 (compare:CCFP (match_dup 2)
12197 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
12201 (define_insn "*minsf_sse"
12202 [(set (match_operand:SF 0 "register_operand" "=x")
12203 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
12204 (match_operand:SF 2 "nonimmediate_operand" "xm"))
12207 "TARGET_SSE && reload_completed"
12208 "minss\\t{%2, %0|%0, %2}"
12209 [(set_attr "type" "sse")
12210 (set_attr "mode" "SF")])
12212 (define_expand "mindf3"
12214 (set (match_operand:DF 0 "register_operand" "")
12215 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
12216 (match_operand:DF 2 "nonimmediate_operand" ""))
12219 (clobber (reg:CC 17))])]
12223 (define_insn "*mindf"
12224 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
12225 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
12226 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
12229 (clobber (reg:CC 17))]
12230 "TARGET_SSE2 && TARGET_IEEE_FP"
12233 (define_insn "*mindf_nonieee"
12234 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
12235 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0")
12236 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
12239 (clobber (reg:CC 17))]
12240 "TARGET_SSE2 && !TARGET_IEEE_FP"
12244 [(set (match_operand:DF 0 "register_operand" "")
12245 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
12246 (match_operand:DF 2 "nonimmediate_operand" ""))
12249 (clobber (reg:CC 17))]
12250 "SSE_REG_P (operands[0]) && reload_completed"
12251 [(set (match_dup 0)
12252 (if_then_else:DF (lt (match_dup 1)
12257 ;; We can't represent the LT test directly. Do this by swapping the operands.
12259 [(set (match_operand:DF 0 "register_operand" "")
12260 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
12261 (match_operand:DF 2 "register_operand" ""))
12264 (clobber (reg:CC 17))]
12265 "FP_REG_P (operands[0]) && reload_completed"
12266 [(set (reg:CCFP 17)
12267 (compare:CCFP (match_dup 2)
12270 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
12274 (define_insn "*mindf_sse"
12275 [(set (match_operand:DF 0 "register_operand" "=Y")
12276 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
12277 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
12280 "TARGET_SSE2 && reload_completed"
12281 "minsd\\t{%2, %0|%0, %2}"
12282 [(set_attr "type" "sse")
12283 (set_attr "mode" "DF")])
12285 (define_expand "maxsf3"
12287 (set (match_operand:SF 0 "register_operand" "")
12288 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
12289 (match_operand:SF 2 "nonimmediate_operand" ""))
12292 (clobber (reg:CC 17))])]
12296 (define_insn "*maxsf"
12297 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
12298 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
12299 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x,0"))
12302 (clobber (reg:CC 17))]
12303 "TARGET_SSE && TARGET_IEEE_FP"
12306 (define_insn "*maxsf_nonieee"
12307 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
12308 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0")
12309 (match_operand:SF 2 "nonimmediate_operand" "xm#f,fm#x"))
12312 (clobber (reg:CC 17))]
12313 "TARGET_SSE && !TARGET_IEEE_FP"
12317 [(set (match_operand:SF 0 "register_operand" "")
12318 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
12319 (match_operand:SF 2 "nonimmediate_operand" ""))
12322 (clobber (reg:CC 17))]
12323 "SSE_REG_P (operands[0]) && reload_completed"
12324 [(set (match_dup 0)
12325 (if_then_else:SF (gt (match_dup 1)
12331 [(set (match_operand:SF 0 "register_operand" "")
12332 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
12333 (match_operand:SF 2 "register_operand" ""))
12336 (clobber (reg:CC 17))]
12337 "FP_REG_P (operands[0]) && reload_completed"
12338 [(set (reg:CCFP 17)
12339 (compare:CCFP (match_dup 1)
12342 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
12346 (define_insn "*maxsf_sse"
12347 [(set (match_operand:SF 0 "register_operand" "=x")
12348 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
12349 (match_operand:SF 2 "nonimmediate_operand" "xm"))
12352 "TARGET_SSE && reload_completed"
12353 "maxss\\t{%2, %0|%0, %2}"
12354 [(set_attr "type" "sse")
12355 (set_attr "mode" "SF")])
12357 (define_expand "maxdf3"
12359 (set (match_operand:DF 0 "register_operand" "")
12360 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
12361 (match_operand:DF 2 "nonimmediate_operand" ""))
12364 (clobber (reg:CC 17))])]
12368 (define_insn "*maxdf"
12369 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
12370 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
12371 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y,0"))
12374 (clobber (reg:CC 17))]
12375 "TARGET_SSE2 && TARGET_IEEE_FP"
12378 (define_insn "*maxdf_nonieee"
12379 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
12380 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0")
12381 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,fm#Y"))
12384 (clobber (reg:CC 17))]
12385 "TARGET_SSE2 && !TARGET_IEEE_FP"
12389 [(set (match_operand:DF 0 "register_operand" "")
12390 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
12391 (match_operand:DF 2 "nonimmediate_operand" ""))
12394 (clobber (reg:CC 17))]
12395 "SSE_REG_P (operands[0]) && reload_completed"
12396 [(set (match_dup 0)
12397 (if_then_else:DF (gt (match_dup 1)
12403 [(set (match_operand:DF 0 "register_operand" "")
12404 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
12405 (match_operand:DF 2 "register_operand" ""))
12408 (clobber (reg:CC 17))]
12409 "FP_REG_P (operands[0]) && reload_completed"
12410 [(set (reg:CCFP 17)
12411 (compare:CCFP (match_dup 1)
12414 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
12418 (define_insn "*maxdf_sse"
12419 [(set (match_operand:DF 0 "register_operand" "=Y")
12420 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
12421 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
12424 "TARGET_SSE2 && reload_completed"
12425 "maxsd\\t{%2, %0|%0, %2}"
12426 [(set_attr "type" "sse")
12427 (set_attr "mode" "DF")])
12429 ;; Misc patterns (?)
12431 ;; This pattern exists to put a dependancy on all ebp-based memory accesses.
12432 ;; Otherwise there will be nothing to keep
12434 ;; [(set (reg ebp) (reg esp))]
12435 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
12436 ;; (clobber (eflags)]
12437 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
12439 ;; in proper program order.
12441 (define_insn "pro_epilogue_adjust_stack"
12442 [(set (match_operand:SI 0 "register_operand" "=r,r")
12443 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
12444 (match_operand:SI 2 "immediate_operand" "i,i")))
12445 (set (match_operand:SI 3 "register_operand" "+r,r")
12447 (clobber (reg:CC 17))]
12451 switch (get_attr_type (insn))
12454 return \"mov{l}\\t{%1, %0|%0, %1}\";
12457 if (GET_CODE (operands[2]) == CONST_INT
12458 && (INTVAL (operands[2]) == 128
12459 || (INTVAL (operands[2]) < 0
12460 && INTVAL (operands[2]) != -128)))
12462 operands[2] = GEN_INT (-INTVAL (operands[2]));
12463 return \"sub{l}\\t{%2, %0|%0, %2}\";
12465 return \"add{l}\\t{%2, %0|%0, %2}\";
12468 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
12469 return \"lea{l}\\t{%a2, %0|%0, %a2}\";
12475 [(set (attr "type")
12476 (cond [(eq_attr "alternative" "0")
12477 (const_string "alu")
12478 (match_operand:SI 2 "const0_operand" "")
12479 (const_string "imov")
12481 (const_string "lea")))
12482 (set_attr "mode" "SI")])
12484 ;; Placeholder for the conditional moves. This one is split eighter to SSE
12485 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
12486 ;; fact is that compares supported by the cmp??ss instructions are exactly
12487 ;; swapped of those supported by cmove sequence.
12489 (define_insn "sse_movsfcc"
12490 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
12491 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
12492 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
12493 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
12494 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
12495 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
12496 (clobber (match_scratch:SF 6 "=2,&5,X,X,X,X,X,X,X,X"))
12497 (clobber (reg:CC 17))]
12499 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
12502 (define_insn "sse_movdfcc"
12503 [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
12504 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
12505 [(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
12506 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
12507 (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
12508 (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
12509 (clobber (match_scratch:DF 6 "=2,&5,X,X,X,X,X,X,X,X"))
12510 (clobber (reg:CC 17))]
12512 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
12515 ;; For non-sse moves just expand the usual cmove sequence.
12517 [(set (match_operand 0 "register_operand" "")
12518 (if_then_else (match_operator 1 "comparison_operator"
12519 [(match_operand 4 "nonimmediate_operand" "")
12520 (match_operand 5 "register_operand" "")])
12521 (match_operand 2 "nonimmediate_operand" "")
12522 (match_operand 3 "nonimmediate_operand" "")))
12523 (clobber (match_operand 6 "" ""))
12524 (clobber (reg:CC 17))]
12525 "!SSE_REG_P (operands[0]) && reload_completed
12526 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
12530 ix86_compare_op0 = operands[5];
12531 ix86_compare_op1 = operands[4];
12532 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
12533 VOIDmode, operands[5], operands[4]);
12534 ix86_expand_fp_movcc (operands);
12538 ;; Split SSE based conditional move into seqence:
12539 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
12540 ;; and op2, op0 - zero op2 if comparison was false
12541 ;; nand op0, op3 - load op3 to op0 if comparison was false
12542 ;; or op2, op0 - get the non-zero one into the result.
12544 [(set (match_operand 0 "register_operand" "")
12545 (if_then_else (match_operator 1 "sse_comparison_operator"
12546 [(match_operand 4 "register_operand" "")
12547 (match_operand 5 "nonimmediate_operand" "")])
12548 (match_operand 2 "register_operand" "")
12549 (match_operand 3 "register_operand" "")))
12550 (clobber (match_dup 2))
12551 (clobber (reg:CC 17))]
12552 "SSE_REG_P (operands[0]) && reload_completed"
12553 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
12554 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
12555 (subreg:TI (match_dup 0) 0)))
12556 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 0) 0))
12557 (subreg:TI (match_dup 3) 0)))
12558 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
12559 (subreg:TI (match_dup 7) 0)))]
12562 PUT_MODE (operands[1], GET_MODE (operands[0]));
12563 if (rtx_equal_p (operands[0], operands[4]))
12564 operands[6] = operands[4], operands[7] = operands[2];
12566 operands[6] = operands[2], operands[7] = operands[0];
12569 ;; Special case of conditional move we can handle effectivly.
12570 ;; Do not brother with the integer/floating point case, since these are
12571 ;; bot considerably slower, unlike in the generic case.
12572 (define_insn "*sse_movsfcc_const0_1"
12573 [(set (match_operand:SF 0 "register_operand" "=x")
12574 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
12575 [(match_operand:SF 4 "register_operand" "0")
12576 (match_operand:SF 5 "nonimmediate_operand" "xm")])
12577 (match_operand:SF 2 "register_operand" "x")
12578 (match_operand:SF 3 "const0_operand" "X")))]
12582 (define_insn "*sse_movsfcc_const0_2"
12583 [(set (match_operand:SF 0 "register_operand" "=x")
12584 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
12585 [(match_operand:SF 4 "register_operand" "0")
12586 (match_operand:SF 5 "nonimmediate_operand" "xm")])
12587 (match_operand:SF 2 "const0_operand" "x")
12588 (match_operand:SF 3 "register_operand" "X")))]
12592 (define_insn "*sse_movsfcc_const0_3"
12593 [(set (match_operand:SF 0 "register_operand" "=x")
12594 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
12595 [(match_operand:SF 4 "nonimmediate_operand" "xm")
12596 (match_operand:SF 5 "register_operand" "0")])
12597 (match_operand:SF 2 "register_operand" "x")
12598 (match_operand:SF 3 "const0_operand" "X")))]
12602 (define_insn "*sse_movsfcc_const0_4"
12603 [(set (match_operand:SF 0 "register_operand" "=x")
12604 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
12605 [(match_operand:SF 4 "nonimmediate_operand" "xm")
12606 (match_operand:SF 5 "register_operand" "0")])
12607 (match_operand:SF 2 "const0_operand" "x")
12608 (match_operand:SF 3 "register_operand" "X")))]
12612 (define_insn "*sse_movdfcc_const0_1"
12613 [(set (match_operand:SF 0 "register_operand" "=x")
12614 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
12615 [(match_operand:SF 4 "register_operand" "0")
12616 (match_operand:SF 5 "nonimmediate_operand" "xm")])
12617 (match_operand:SF 2 "register_operand" "x")
12618 (match_operand:SF 3 "const0_operand" "X")))]
12622 (define_insn "*sse_movdfcc_const0_2"
12623 [(set (match_operand:SF 0 "register_operand" "=x")
12624 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
12625 [(match_operand:SF 4 "register_operand" "0")
12626 (match_operand:SF 5 "nonimmediate_operand" "xm")])
12627 (match_operand:SF 2 "const0_operand" "x")
12628 (match_operand:SF 3 "register_operand" "X")))]
12632 (define_insn "*sse_movdfcc_const0_3"
12633 [(set (match_operand:SF 0 "register_operand" "=x")
12634 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
12635 [(match_operand:SF 4 "nonimmediate_operand" "xm")
12636 (match_operand:SF 5 "register_operand" "0")])
12637 (match_operand:SF 2 "register_operand" "x")
12638 (match_operand:SF 3 "const0_operand" "X")))]
12642 (define_insn "*sse_movdfcc_const0_4"
12643 [(set (match_operand:SF 0 "register_operand" "=x")
12644 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
12645 [(match_operand:SF 4 "nonimmediate_operand" "xm")
12646 (match_operand:SF 5 "register_operand" "0")])
12647 (match_operand:SF 2 "const0_operand" "x")
12648 (match_operand:SF 3 "register_operand" "X")))]
12653 [(set (match_operand 0 "register_operand" "")
12654 (if_then_else (match_operator 1 "comparison_operator"
12655 [(match_operand 4 "register_operand" "")
12656 (match_operand 5 "nonimmediate_operand" "")])
12657 (match_operand 2 "nonmemory_operand" "")
12658 (match_operand 3 "nonmemory_operand" "")))]
12659 "SSE_REG_P (operands[0]) && reload_completed
12660 && (const0_operand (operands[2], GET_MODE (operands[0]))
12661 || const0_operand (operands[3], GET_MODE (operands[0])))"
12662 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
12663 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
12664 (subreg:TI (match_dup 7) 0)))]
12667 PUT_MODE (operands[1], GET_MODE (operands[0]));
12668 if (!sse_comparison_operator (operands[1], VOIDmode))
12670 rtx tmp = operands[5];
12671 operands[5] = operands[4];
12673 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
12675 if (const0_operand (operands[2], GET_MODE (operands[0])))
12677 operands[7] = operands[3];
12678 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
12683 operands[7] = operands[2];
12684 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
12688 (define_insn "allocate_stack_worker"
12689 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
12690 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
12691 (clobber (match_dup 0))
12692 (clobber (reg:CC 17))]
12693 "TARGET_STACK_PROBE"
12695 [(set_attr "type" "multi")
12696 (set_attr "length" "5")])
12698 (define_expand "allocate_stack"
12699 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
12700 (minus:SI (reg:SI 7)
12701 (match_operand:SI 1 "general_operand" "")))
12702 (clobber (reg:CC 17))])
12703 (parallel [(set (reg:SI 7)
12704 (minus:SI (reg:SI 7) (match_dup 1)))
12705 (clobber (reg:CC 17))])]
12706 "TARGET_STACK_PROBE"
12709 #ifdef CHECK_STACK_LIMIT
12710 if (GET_CODE (operands[1]) == CONST_INT
12711 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
12712 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
12716 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
12719 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
12723 (define_expand "exception_receiver"
12728 load_pic_register ();
12732 (define_expand "builtin_setjmp_receiver"
12733 [(label_ref (match_operand 0 "" ""))]
12737 load_pic_register ();
12741 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
12744 [(set (match_operand 0 "register_operand" "")
12745 (match_operator 3 "promotable_binary_operator"
12746 [(match_operand 1 "register_operand" "")
12747 (match_operand 2 "aligned_operand" "")]))
12748 (clobber (reg:CC 17))]
12749 "! TARGET_PARTIAL_REG_STALL && reload_completed
12750 && ((GET_MODE (operands[0]) == HImode
12751 && (!optimize_size || GET_CODE (operands[2]) != CONST_INT
12752 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
12753 || (GET_MODE (operands[0]) == QImode
12754 && (TARGET_PROMOTE_QImode || optimize_size)))"
12755 [(parallel [(set (match_dup 0)
12756 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
12757 (clobber (reg:CC 17))])]
12758 "operands[0] = gen_lowpart (SImode, operands[0]);
12759 operands[1] = gen_lowpart (SImode, operands[1]);
12760 if (GET_CODE (operands[3]) != ASHIFT)
12761 operands[2] = gen_lowpart (SImode, operands[2]);
12762 PUT_MODE (operands[3], SImode);")
12766 (compare (and (match_operand 1 "aligned_operand" "")
12767 (match_operand 2 "const_int_operand" ""))
12769 (set (match_operand 0 "register_operand" "")
12770 (and (match_dup 1) (match_dup 2)))]
12771 "! TARGET_PARTIAL_REG_STALL && reload_completed
12772 && ix86_match_ccmode (insn, CCNOmode)
12773 && (GET_MODE (operands[0]) == HImode
12774 || (GET_MODE (operands[0]) == QImode
12775 && (TARGET_PROMOTE_QImode || optimize_size)))"
12776 [(parallel [(set (reg:CCNO 17)
12777 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
12780 (and:SI (match_dup 1) (match_dup 2)))])]
12782 = GEN_INT (INTVAL (operands[2]) & GET_MODE_MASK (GET_MODE (operands[0])));
12783 operands[0] = gen_lowpart (SImode, operands[0]);
12784 operands[1] = gen_lowpart (SImode, operands[1]);")
12788 (compare (and (match_operand 0 "aligned_operand" "")
12789 (match_operand 1 "const_int_operand" ""))
12791 "! TARGET_PARTIAL_REG_STALL && reload_completed
12792 && ix86_match_ccmode (insn, CCNOmode)
12793 && (GET_MODE (operands[0]) == HImode
12794 || (GET_MODE (operands[0]) == QImode
12795 && (TARGET_PROMOTE_QImode || optimize_size)))"
12796 [(set (reg:CCNO 17)
12797 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
12800 = GEN_INT (INTVAL (operands[1]) & GET_MODE_MASK (GET_MODE (operands[0])));
12801 operands[0] = gen_lowpart (SImode, operands[0]);")
12804 [(set (match_operand 0 "register_operand" "")
12805 (neg (match_operand 1 "register_operand" "")))
12806 (clobber (reg:CC 17))]
12807 "! TARGET_PARTIAL_REG_STALL && reload_completed
12808 && (GET_MODE (operands[0]) == HImode
12809 || (GET_MODE (operands[0]) == QImode
12810 && (TARGET_PROMOTE_QImode || optimize_size)))"
12811 [(parallel [(set (match_dup 0)
12812 (neg:SI (match_dup 1)))
12813 (clobber (reg:CC 17))])]
12814 "operands[0] = gen_lowpart (SImode, operands[0]);
12815 operands[1] = gen_lowpart (SImode, operands[1]);")
12818 [(set (match_operand 0 "register_operand" "")
12819 (not (match_operand 1 "register_operand" "")))]
12820 "! TARGET_PARTIAL_REG_STALL && reload_completed
12821 && (GET_MODE (operands[0]) == HImode
12822 || (GET_MODE (operands[0]) == QImode
12823 && (TARGET_PROMOTE_QImode || optimize_size)))"
12824 [(set (match_dup 0)
12825 (not:SI (match_dup 1)))]
12826 "operands[0] = gen_lowpart (SImode, operands[0]);
12827 operands[1] = gen_lowpart (SImode, operands[1]);")
12830 [(set (match_operand 0 "register_operand" "")
12831 (if_then_else (match_operator 1 "comparison_operator"
12832 [(reg 17) (const_int 0)])
12833 (match_operand 2 "register_operand" "")
12834 (match_operand 3 "register_operand" "")))]
12835 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
12836 && (GET_MODE (operands[0]) == HImode
12837 || (GET_MODE (operands[0]) == QImode
12838 && (TARGET_PROMOTE_QImode || optimize_size)))"
12839 [(set (match_dup 0)
12840 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
12841 "operands[0] = gen_lowpart (SImode, operands[0]);
12842 operands[2] = gen_lowpart (SImode, operands[2]);
12843 operands[3] = gen_lowpart (SImode, operands[3]);")
12846 ;; RTL Peephole optimizations, run before sched2. These primarily look to
12847 ;; transform a complex memory operation into two memory to register operations.
12849 ;; Don't push memory operands
12851 [(set (match_operand:SI 0 "push_operand" "")
12852 (match_operand:SI 1 "memory_operand" ""))
12853 (match_scratch:SI 2 "r")]
12854 "! optimize_size && ! TARGET_PUSH_MEMORY"
12855 [(set (match_dup 2) (match_dup 1))
12856 (set (match_dup 0) (match_dup 2))]
12859 ;; We need to handle SFmode only, because DFmode and XFmode is split to
12862 [(set (match_operand:SF 0 "push_operand" "")
12863 (match_operand:SF 1 "memory_operand" ""))
12864 (match_scratch:SF 2 "r")]
12865 "! optimize_size && ! TARGET_PUSH_MEMORY"
12866 [(set (match_dup 2) (match_dup 1))
12867 (set (match_dup 0) (match_dup 2))]
12871 [(set (match_operand:HI 0 "push_operand" "")
12872 (match_operand:HI 1 "memory_operand" ""))
12873 (match_scratch:HI 2 "r")]
12874 "! optimize_size && ! TARGET_PUSH_MEMORY"
12875 [(set (match_dup 2) (match_dup 1))
12876 (set (match_dup 0) (match_dup 2))]
12880 [(set (match_operand:QI 0 "push_operand" "")
12881 (match_operand:QI 1 "memory_operand" ""))
12882 (match_scratch:QI 2 "q")]
12883 "! optimize_size && ! TARGET_PUSH_MEMORY"
12884 [(set (match_dup 2) (match_dup 1))
12885 (set (match_dup 0) (match_dup 2))]
12888 ;; Don't move an immediate directly to memory when the instruction
12891 [(match_scratch:SI 1 "r")
12892 (set (match_operand:SI 0 "memory_operand" "")
12895 && ! TARGET_USE_MOV0
12896 && TARGET_SPLIT_LONG_MOVES
12897 && get_attr_length (insn) >= ix86_cost->large_insn
12898 && peep2_regno_dead_p (0, FLAGS_REG)"
12899 [(parallel [(set (match_dup 1) (const_int 0))
12900 (clobber (reg:CC 17))])
12901 (set (match_dup 0) (match_dup 1))]
12905 [(match_scratch:HI 1 "r")
12906 (set (match_operand:HI 0 "memory_operand" "")
12909 && ! TARGET_USE_MOV0
12910 && TARGET_SPLIT_LONG_MOVES
12911 && get_attr_length (insn) >= ix86_cost->large_insn
12912 && peep2_regno_dead_p (0, FLAGS_REG)"
12913 [(parallel [(set (match_dup 2) (const_int 0))
12914 (clobber (reg:CC 17))])
12915 (set (match_dup 0) (match_dup 1))]
12916 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
12919 [(match_scratch:QI 1 "q")
12920 (set (match_operand:QI 0 "memory_operand" "")
12923 && ! TARGET_USE_MOV0
12924 && TARGET_SPLIT_LONG_MOVES
12925 && get_attr_length (insn) >= ix86_cost->large_insn
12926 && peep2_regno_dead_p (0, FLAGS_REG)"
12927 [(parallel [(set (match_dup 2) (const_int 0))
12928 (clobber (reg:CC 17))])
12929 (set (match_dup 0) (match_dup 1))]
12930 "operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));")
12933 [(match_scratch:SI 2 "r")
12934 (set (match_operand:SI 0 "memory_operand" "")
12935 (match_operand:SI 1 "immediate_operand" ""))]
12937 && get_attr_length (insn) >= ix86_cost->large_insn
12938 && TARGET_SPLIT_LONG_MOVES"
12939 [(set (match_dup 2) (match_dup 1))
12940 (set (match_dup 0) (match_dup 2))]
12944 [(match_scratch:HI 2 "r")
12945 (set (match_operand:HI 0 "memory_operand" "")
12946 (match_operand:HI 1 "immediate_operand" ""))]
12947 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
12948 && TARGET_SPLIT_LONG_MOVES"
12949 [(set (match_dup 2) (match_dup 1))
12950 (set (match_dup 0) (match_dup 2))]
12954 [(match_scratch:QI 2 "q")
12955 (set (match_operand:QI 0 "memory_operand" "")
12956 (match_operand:QI 1 "immediate_operand" ""))]
12957 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
12958 && TARGET_SPLIT_LONG_MOVES"
12959 [(set (match_dup 2) (match_dup 1))
12960 (set (match_dup 0) (match_dup 2))]
12963 ;; Don't compare memory with zero, load and use a test instead.
12966 (compare (match_operand:SI 0 "memory_operand" "")
12968 (match_scratch:SI 3 "r")]
12969 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
12970 [(set (match_dup 3) (match_dup 0))
12971 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
12974 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
12975 ;; Don't split NOTs with a displacement operand, because resulting XOR
12976 ;; will not be pariable anyway.
12978 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
12979 ;; represented using a modRM byte. The XOR replacement is long decoded,
12980 ;; so this split helps here as well.
12982 ;; Note: Can't do this as a regular split because we can't get proper
12983 ;; lifetime information then.
12986 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12987 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
12989 && peep2_regno_dead_p (0, FLAGS_REG)
12990 && ((TARGET_PENTIUM
12991 && (GET_CODE (operands[0]) != MEM
12992 || !memory_displacement_operand (operands[0], SImode)))
12993 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
12994 [(parallel [(set (match_dup 0)
12995 (xor:SI (match_dup 1) (const_int -1)))
12996 (clobber (reg:CC 17))])]
13000 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
13001 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
13003 && peep2_regno_dead_p (0, FLAGS_REG)
13004 && ((TARGET_PENTIUM
13005 && (GET_CODE (operands[0]) != MEM
13006 || !memory_displacement_operand (operands[0], HImode)))
13007 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
13008 [(parallel [(set (match_dup 0)
13009 (xor:HI (match_dup 1) (const_int -1)))
13010 (clobber (reg:CC 17))])]
13014 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
13015 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
13017 && peep2_regno_dead_p (0, FLAGS_REG)
13018 && ((TARGET_PENTIUM
13019 && (GET_CODE (operands[0]) != MEM
13020 || !memory_displacement_operand (operands[0], QImode)))
13021 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
13022 [(parallel [(set (match_dup 0)
13023 (xor:QI (match_dup 1) (const_int -1)))
13024 (clobber (reg:CC 17))])]
13027 ;; Non pairable "test imm, reg" instructions can be translated to
13028 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
13029 ;; byte opcode instead of two, have a short form for byte operands),
13030 ;; so do it for other CPUs as well. Given that the value was dead,
13031 ;; this should not create any new dependancies. Pass on the sub-word
13032 ;; versions if we're concerned about partial register stalls.
13036 (compare (and:SI (match_operand:SI 0 "register_operand" "")
13037 (match_operand:SI 1 "immediate_operand" ""))
13039 "ix86_match_ccmode (insn, CCNOmode)
13040 && (true_regnum (operands[0]) != 0
13041 || CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))
13042 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
13044 [(set (reg:CCNO 17)
13045 (compare:CCNO (and:SI (match_dup 0)
13049 (and:SI (match_dup 0) (match_dup 1)))])]
13052 ;; We don't need to handle HImode case, because it will be promoted to SImode
13053 ;; on ! TARGET_PARTIAL_REG_STALL
13057 (compare (and:QI (match_operand:QI 0 "register_operand" "")
13058 (match_operand:QI 1 "immediate_operand" ""))
13060 "! TARGET_PARTIAL_REG_STALL
13061 && ix86_match_ccmode (insn, CCNOmode)
13062 && true_regnum (operands[0]) != 0
13063 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
13065 [(set (reg:CCNO 17)
13066 (compare:CCNO (and:QI (match_dup 0)
13070 (and:QI (match_dup 0) (match_dup 1)))])]
13078 (match_operand 0 "ext_register_operand" "q")
13081 (match_operand 1 "const_int_operand" "n"))
13083 "! TARGET_PARTIAL_REG_STALL
13084 && ix86_match_ccmode (insn, CCNOmode)
13085 && true_regnum (operands[0]) != 0
13086 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
13087 [(parallel [(set (reg:CCNO 17)
13096 (set (zero_extract:SI (match_dup 0)
13107 ;; Don't do logical operations with memory inputs.
13109 [(match_scratch:SI 2 "r")
13110 (parallel [(set (match_operand:SI 0 "register_operand" "")
13111 (match_operator:SI 3 "arith_or_logical_operator"
13113 (match_operand:SI 1 "memory_operand" "")]))
13114 (clobber (reg:CC 17))])]
13115 "! optimize_size && ! TARGET_READ_MODIFY"
13116 [(set (match_dup 2) (match_dup 1))
13117 (parallel [(set (match_dup 0)
13118 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
13119 (clobber (reg:CC 17))])]
13123 [(match_scratch:SI 2 "r")
13124 (parallel [(set (match_operand:SI 0 "register_operand" "")
13125 (match_operator:SI 3 "arith_or_logical_operator"
13126 [(match_operand:SI 1 "memory_operand" "")
13128 (clobber (reg:CC 17))])]
13129 "! optimize_size && ! TARGET_READ_MODIFY"
13130 [(set (match_dup 2) (match_dup 1))
13131 (parallel [(set (match_dup 0)
13132 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
13133 (clobber (reg:CC 17))])]
13136 ; Don't do logical operations with memory outputs
13138 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
13139 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
13140 ; the same decoder scheduling characteristics as the original.
13143 [(match_scratch:SI 2 "r")
13144 (parallel [(set (match_operand:SI 0 "memory_operand" "")
13145 (match_operator:SI 3 "arith_or_logical_operator"
13147 (match_operand:SI 1 "nonmemory_operand" "")]))
13148 (clobber (reg:CC 17))])]
13149 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
13150 [(set (match_dup 2) (match_dup 0))
13151 (parallel [(set (match_dup 2)
13152 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
13153 (clobber (reg:CC 17))])
13154 (set (match_dup 0) (match_dup 2))]
13158 [(match_scratch:SI 2 "r")
13159 (parallel [(set (match_operand:SI 0 "memory_operand" "")
13160 (match_operator:SI 3 "arith_or_logical_operator"
13161 [(match_operand:SI 1 "nonmemory_operand" "")
13163 (clobber (reg:CC 17))])]
13164 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
13165 [(set (match_dup 2) (match_dup 0))
13166 (parallel [(set (match_dup 2)
13167 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
13168 (clobber (reg:CC 17))])
13169 (set (match_dup 0) (match_dup 2))]
13172 ;; Attempt to always use XOR for zeroing registers.
13174 [(set (match_operand 0 "register_operand" "")
13176 "(GET_MODE (operands[0]) == QImode
13177 || GET_MODE (operands[0]) == HImode
13178 || GET_MODE (operands[0]) == SImode)
13179 && (! TARGET_USE_MOV0 || optimize_size)
13180 && peep2_regno_dead_p (0, FLAGS_REG)"
13181 [(parallel [(set (match_dup 0) (const_int 0))
13182 (clobber (reg:CC 17))])]
13183 "operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]));")
13186 [(set (strict_low_part (match_operand 0 "register_operand" ""))
13188 "(GET_MODE (operands[0]) == QImode
13189 || GET_MODE (operands[0]) == HImode)
13190 && (! TARGET_USE_MOV0 || optimize_size)
13191 && peep2_regno_dead_p (0, FLAGS_REG)"
13192 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
13193 (clobber (reg:CC 17))])])
13195 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
13197 [(set (match_operand 0 "register_operand" "")
13199 "(GET_MODE (operands[0]) == HImode
13200 || GET_MODE (operands[0]) == SImode)
13201 && (optimize_size || TARGET_PENTIUM)
13202 && peep2_regno_dead_p (0, FLAGS_REG)"
13203 [(parallel [(set (match_dup 0) (const_int -1))
13204 (clobber (reg:CC 17))])]
13205 "operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]));")
13207 ;; Attempt to convert simple leas to adds. These can be created by
13210 [(set (match_operand:SI 0 "register_operand" "")
13211 (plus:SI (match_dup 0)
13212 (match_operand:SI 1 "nonmemory_operand" "")))]
13213 "peep2_regno_dead_p (0, FLAGS_REG)"
13214 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
13215 (clobber (reg:CC 17))])]
13219 [(set (match_operand:SI 0 "register_operand" "")
13220 (mult:SI (match_dup 0)
13221 (match_operand:SI 1 "immediate_operand" "")))]
13222 "exact_log2 (INTVAL (operands[1])) >= 0
13223 && peep2_regno_dead_p (0, FLAGS_REG)"
13224 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
13225 (clobber (reg:CC 17))])]
13226 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
13228 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
13229 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
13230 ;; many CPUs it is also faster, since special hardware to avoid esp
13231 ;; dependancies is present.
13233 ;; While some of these converisons may be done using splitters, we use peepholes
13234 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
13236 ;; Convert prologue esp substractions to push.
13237 ;; We need register to push. In order to keep verify_flow_info happy we have
13239 ;; - use scratch and clobber it in order to avoid dependencies
13240 ;; - use already live register
13241 ;; We can't use the second way right now, since there is no reliable way how to
13242 ;; verify that given register is live. First choice will also most likely in
13243 ;; fewer dependencies. On the place of esp adjustments it is very likely that
13244 ;; call clobbered registers are dead. We may want to use base pointer as an
13245 ;; alternative when no register is available later.
13248 [(match_scratch:SI 0 "r")
13249 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
13250 (set (reg:SI 6) (reg:SI 6))
13251 (clobber (reg:CC 17))])]
13252 "optimize_size || !TARGET_SUB_ESP_4"
13253 [(clobber (match_dup 0))
13254 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
13255 (set (reg:SI 6) (reg:SI 6))])])
13258 [(match_scratch:SI 0 "r")
13259 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
13260 (set (reg:SI 6) (reg:SI 6))
13261 (clobber (reg:CC 17))])]
13262 "optimize_size || !TARGET_SUB_ESP_8"
13263 [(clobber (match_dup 0))
13264 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
13265 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
13266 (set (reg:SI 6) (reg:SI 6))])])
13268 ;; Convert esp substractions to push.
13270 [(match_scratch:SI 0 "r")
13271 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
13272 (clobber (reg:CC 17))])]
13273 "optimize_size || !TARGET_SUB_ESP_4"
13274 [(clobber (match_dup 0))
13275 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
13278 [(match_scratch:SI 0 "r")
13279 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
13280 (clobber (reg:CC 17))])]
13281 "optimize_size || !TARGET_SUB_ESP_8"
13282 [(clobber (match_dup 0))
13283 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
13284 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
13286 ;; Convert epilogue deallocator to pop.
13288 [(match_scratch:SI 0 "r")
13289 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
13290 (set (reg:SI 6) (reg:SI 6))
13291 (clobber (reg:CC 17))])]
13292 "optimize_size || !TARGET_ADD_ESP_4"
13293 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
13294 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
13295 (set (reg:SI 6) (reg:SI 6))])]
13298 ;; Two pops case is tricky, since pop causes dependency on destination register.
13299 ;; We use two registers if available.
13301 [(match_scratch:SI 0 "r")
13302 (match_scratch:SI 1 "r")
13303 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
13304 (set (reg:SI 6) (reg:SI 6))
13305 (clobber (reg:CC 17))])]
13306 "optimize_size || !TARGET_ADD_ESP_8"
13307 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
13308 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
13309 (set (reg:SI 6) (reg:SI 6))])
13310 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
13311 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
13315 [(match_scratch:SI 0 "r")
13316 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
13317 (set (reg:SI 6) (reg:SI 6))
13318 (clobber (reg:CC 17))])]
13320 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
13321 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
13322 (set (reg:SI 6) (reg:SI 6))])
13323 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
13324 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
13327 ;; Convert esp additions to pop.
13329 [(match_scratch:SI 0 "r")
13330 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
13331 (clobber (reg:CC 17))])]
13333 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
13334 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
13337 ;; Two pops case is tricky, since pop causes dependency on destination register.
13338 ;; We use two registers if available.
13340 [(match_scratch:SI 0 "r")
13341 (match_scratch:SI 1 "r")
13342 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
13343 (clobber (reg:CC 17))])]
13345 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
13346 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
13347 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
13348 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
13352 [(match_scratch:SI 0 "r")
13353 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
13354 (clobber (reg:CC 17))])]
13356 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
13357 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
13358 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
13359 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
13362 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
13363 ;; required and register dies.
13366 (compare (match_operand:SI 0 "register_operand" "")
13367 (match_operand:SI 1 "incdec_operand" "")))]
13368 "ix86_match_ccmode (insn, CCGCmode)
13369 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
13370 [(parallel [(set (reg:CCGC 17)
13371 (compare:CCGC (match_dup 0)
13373 (clobber (match_dup 0))])]
13378 (compare (match_operand:HI 0 "register_operand" "")
13379 (match_operand:HI 1 "incdec_operand" "")))]
13380 "ix86_match_ccmode (insn, CCGCmode)
13381 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
13382 [(parallel [(set (reg:CCGC 17)
13383 (compare:CCGC (match_dup 0)
13385 (clobber (match_dup 0))])]
13390 (compare (match_operand:QI 0 "register_operand" "")
13391 (match_operand:QI 1 "incdec_operand" "")))]
13392 "ix86_match_ccmode (insn, CCGCmode)
13393 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
13394 [(parallel [(set (reg:CCGC 17)
13395 (compare:CCGC (match_dup 0)
13397 (clobber (match_dup 0))])]
13400 ;; Convert compares with 128 to shorter add -128
13403 (compare (match_operand:SI 0 "register_operand" "")
13405 "ix86_match_ccmode (insn, CCGCmode)
13406 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
13407 [(parallel [(set (reg:CCGC 17)
13408 (compare:CCGC (match_dup 0)
13410 (clobber (match_dup 0))])]
13415 (compare (match_operand:HI 0 "register_operand" "")
13417 "ix86_match_ccmode (insn, CCGCmode)
13418 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
13419 [(parallel [(set (reg:CCGC 17)
13420 (compare:CCGC (match_dup 0)
13422 (clobber (match_dup 0))])]
13425 ;; Call-value patterns last so that the wildcard operand does not
13426 ;; disrupt insn-recog's switch tables.
13428 (define_insn "*call_value_pop_0"
13429 [(set (match_operand 0 "" "")
13430 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
13431 (match_operand:SI 2 "" "")))
13432 (set (reg:SI 7) (plus:SI (reg:SI 7)
13433 (match_operand:SI 3 "immediate_operand" "")))]
13437 if (SIBLING_CALL_P (insn))
13438 return \"jmp\\t%P1\";
13440 return \"call\\t%P1\";
13442 [(set_attr "type" "callv")])
13444 (define_insn "*call_value_pop_1"
13445 [(set (match_operand 0 "" "")
13446 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
13447 (match_operand:SI 2 "" "")))
13448 (set (reg:SI 7) (plus:SI (reg:SI 7)
13449 (match_operand:SI 3 "immediate_operand" "i")))]
13453 if (constant_call_address_operand (operands[1], QImode))
13455 if (SIBLING_CALL_P (insn))
13456 return \"jmp\\t%P1\";
13458 return \"call\\t%P1\";
13460 if (SIBLING_CALL_P (insn))
13461 return \"jmp\\t%A1\";
13463 return \"call\\t%A1\";
13465 [(set_attr "type" "callv")])
13467 (define_insn "*call_value_0"
13468 [(set (match_operand 0 "" "")
13469 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
13470 (match_operand:SI 2 "" "")))]
13474 if (SIBLING_CALL_P (insn))
13475 return \"jmp\\t%P1\";
13477 return \"call\\t%P1\";
13479 [(set_attr "type" "callv")])
13481 (define_insn "*call_value_1"
13482 [(set (match_operand 0 "" "")
13483 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
13484 (match_operand:SI 2 "" "")))]
13488 if (constant_call_address_operand (operands[1], QImode))
13490 if (SIBLING_CALL_P (insn))
13491 return \"jmp\\t%P1\";
13493 return \"call\\t%P1\";
13495 if (SIBLING_CALL_P (insn))
13496 return \"jmp\\t%A1\";
13498 return \"call\\t%A1\";
13500 [(set_attr "type" "callv")])
13502 (define_insn "trap"
13503 [(trap_if (const_int 1) (const_int 5))]
13507 ;;; ix86 doesn't have conditional trap instructions, but we fake them
13508 ;;; for the sake of bounds checking. By emitting bounds checks as
13509 ;;; conditional traps rather than as conditional jumps around
13510 ;;; unconditional traps we avoid introducing spurious basic-block
13511 ;;; boundaries and facilitate elimination of redundant checks. In
13512 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
13515 ;;; FIXME: Static branch prediction rules for ix86 are such that
13516 ;;; forward conditional branches predict as untaken. As implemented
13517 ;;; below, pseudo conditional traps violate that rule. We should use
13518 ;;; .pushsection/.popsection to place all of the `int 5's in a special
13519 ;;; section loaded at the end of the text segment and branch forward
13520 ;;; there on bounds-failure, and then jump back immediately (in case
13521 ;;; the system chooses to ignore bounds violations, or to report
13522 ;;; violations and continue execution).
13524 (define_expand "conditional_trap"
13525 [(trap_if (match_operator 0 "comparison_operator"
13526 [(match_dup 2) (const_int 0)])
13527 (match_operand 1 "const_int_operand" ""))]
13531 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
13532 ix86_expand_compare (GET_CODE (operands[0]),
13533 NULL_RTX, NULL_RTX),
13539 [(trap_if (match_operator 0 "comparison_operator"
13540 [(reg 17) (const_int 0)])
13541 (match_operand 1 "const_int_operand" ""))]
13545 operands[2] = gen_label_rtx ();
13546 output_asm_insn (\"j%c0\\t%l2\; int\\t%1\", operands);
13547 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
13548 CODE_LABEL_NUMBER (operands[2]));
13552 ;; Pentium III SIMD instructions.
13554 ;; Moves for SSE/MMX regs.
13556 (define_insn "movv4sf_internal"
13557 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
13558 (match_operand:V4SF 1 "general_operand" "xm,x"))]
13560 ;; @@@ let's try to use movaps here.
13561 "movaps\\t{%1, %0|%0, %1}"
13562 [(set_attr "type" "sse")])
13564 (define_insn "movv4si_internal"
13565 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
13566 (match_operand:V4SI 1 "general_operand" "xm,x"))]
13568 ;; @@@ let's try to use movaps here.
13569 "movaps\\t{%1, %0|%0, %1}"
13570 [(set_attr "type" "sse")])
13572 (define_insn "movv8qi_internal"
13573 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
13574 (match_operand:V8QI 1 "general_operand" "ym,y"))]
13576 "movq\\t{%1, %0|%0, %1}"
13577 [(set_attr "type" "mmx")])
13579 (define_insn "movv4hi_internal"
13580 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
13581 (match_operand:V4HI 1 "general_operand" "ym,y"))]
13583 "movq\\t{%1, %0|%0, %1}"
13584 [(set_attr "type" "mmx")])
13586 (define_insn "movv2si_internal"
13587 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
13588 (match_operand:V2SI 1 "general_operand" "ym,y"))]
13590 "movq\\t{%1, %0|%0, %1}"
13591 [(set_attr "type" "mmx")])
13593 (define_expand "movti"
13594 [(set (match_operand:TI 0 "general_operand" "")
13595 (match_operand:TI 1 "general_operand" ""))]
13599 /* For constants other than zero into memory. We do not know how the
13600 instructions used to build constants modify the upper 64 bits
13601 of the register, once we have that information we may be able
13602 to handle some of them more efficiently. */
13603 if ((reload_in_progress | reload_completed) == 0
13604 && register_operand (operands[0], TImode)
13605 && CONSTANT_P (operands[1]))
13607 rtx addr = gen_reg_rtx (Pmode);
13609 emit_move_insn (addr, XEXP (force_const_mem (TImode, operands[1]), 0));
13610 operands[1] = gen_rtx_MEM (TImode, addr);
13613 /* Make operand1 a register if it isn't already. */
13614 if ((reload_in_progress | reload_completed) == 0
13615 && !register_operand (operands[0], TImode)
13616 && !register_operand (operands[1], TImode)
13617 && operands[1] != CONST0_RTX (TImode))
13619 rtx temp = force_reg (TImode, operands[1]);
13620 emit_move_insn (operands[0], temp);
13625 (define_expand "movv4sf"
13626 [(set (match_operand:V4SF 0 "general_operand" "")
13627 (match_operand:V4SF 1 "general_operand" ""))]
13631 /* For constants other than zero into memory. We do not know how the
13632 instructions used to build constants modify the upper 64 bits
13633 of the register, once we have that information we may be able
13634 to handle some of them more efficiently. */
13635 if ((reload_in_progress | reload_completed) == 0
13636 && register_operand (operands[0], V4SFmode)
13637 && CONSTANT_P (operands[1]))
13639 rtx addr = gen_reg_rtx (Pmode);
13641 emit_move_insn (addr, XEXP (force_const_mem (V4SFmode, operands[1]), 0));
13642 operands[1] = gen_rtx_MEM (V4SFmode, addr);
13645 /* Make operand1 a register if it isn't already. */
13646 if ((reload_in_progress | reload_completed) == 0
13647 && !register_operand (operands[0], V4SFmode)
13648 && !register_operand (operands[1], V4SFmode)
13649 && operands[1] != CONST0_RTX (V4SFmode))
13651 rtx temp = force_reg (V4SFmode, operands[1]);
13652 emit_move_insn (operands[0], temp);
13657 (define_expand "movv4si"
13658 [(set (match_operand:V4SI 0 "general_operand" "")
13659 (match_operand:V4SI 1 "general_operand" ""))]
13663 /* For constants other than zero into memory. We do not know how the
13664 instructions used to build constants modify the upper 64 bits
13665 of the register, once we have that information we may be able
13666 to handle some of them more efficiently. */
13667 if ((reload_in_progress | reload_completed) == 0
13668 && register_operand (operands[0], V4SImode)
13669 && CONSTANT_P (operands[1]))
13671 rtx addr = gen_reg_rtx (Pmode);
13673 emit_move_insn (addr, XEXP (force_const_mem (V4SImode, operands[1]), 0));
13674 operands[1] = gen_rtx_MEM (V4SImode, addr);
13677 /* Make operand1 a register if it isn't already. */
13678 if ((reload_in_progress | reload_completed) == 0
13679 && !register_operand (operands[0], V4SImode)
13680 && !register_operand (operands[1], V4SImode)
13681 && operands[1] != CONST0_RTX (V4SImode))
13683 rtx temp = force_reg (V4SImode, operands[1]);
13684 emit_move_insn (operands[0], temp);
13689 (define_expand "movv2si"
13690 [(set (match_operand:V2SI 0 "general_operand" "")
13691 (match_operand:V2SI 1 "general_operand" ""))]
13695 /* For constants other than zero into memory. We do not know how the
13696 instructions used to build constants modify the upper 64 bits
13697 of the register, once we have that information we may be able
13698 to handle some of them more efficiently. */
13699 if ((reload_in_progress | reload_completed) == 0
13700 && register_operand (operands[0], V2SImode)
13701 && CONSTANT_P (operands[1]))
13703 rtx addr = gen_reg_rtx (Pmode);
13705 emit_move_insn (addr, XEXP (force_const_mem (V2SImode, operands[1]), 0));
13706 operands[1] = gen_rtx_MEM (V2SImode, addr);
13709 /* Make operand1 a register if it isn't already. */
13710 if ((reload_in_progress | reload_completed) == 0
13711 && !register_operand (operands[0], V2SImode)
13712 && !register_operand (operands[1], V2SImode)
13713 && operands[1] != CONST0_RTX (V2SImode))
13715 rtx temp = force_reg (V2SImode, operands[1]);
13716 emit_move_insn (operands[0], temp);
13721 (define_expand "movv4hi"
13722 [(set (match_operand:V4HI 0 "general_operand" "")
13723 (match_operand:V4HI 1 "general_operand" ""))]
13727 /* For constants other than zero into memory. We do not know how the
13728 instructions used to build constants modify the upper 64 bits
13729 of the register, once we have that information we may be able
13730 to handle some of them more efficiently. */
13731 if ((reload_in_progress | reload_completed) == 0
13732 && register_operand (operands[0], V4HImode)
13733 && CONSTANT_P (operands[1]))
13735 rtx addr = gen_reg_rtx (Pmode);
13737 emit_move_insn (addr, XEXP (force_const_mem (V4HImode, operands[1]), 0));
13738 operands[1] = gen_rtx_MEM (V4HImode, addr);
13741 /* Make operand1 a register if it isn't already. */
13742 if ((reload_in_progress | reload_completed) == 0
13743 && !register_operand (operands[0], V4HImode)
13744 && !register_operand (operands[1], V4HImode)
13745 && operands[1] != CONST0_RTX (V4HImode))
13747 rtx temp = force_reg (V4HImode, operands[1]);
13748 emit_move_insn (operands[0], temp);
13753 (define_expand "movv8qi"
13754 [(set (match_operand:V8QI 0 "general_operand" "")
13755 (match_operand:V8QI 1 "general_operand" ""))]
13759 /* For constants other than zero into memory. We do not know how the
13760 instructions used to build constants modify the upper 64 bits
13761 of the register, once we have that information we may be able
13762 to handle some of them more efficiently. */
13763 if ((reload_in_progress | reload_completed) == 0
13764 && register_operand (operands[0], V8QImode)
13765 && CONSTANT_P (operands[1]))
13767 rtx addr = gen_reg_rtx (Pmode);
13769 emit_move_insn (addr, XEXP (force_const_mem (V8QImode, operands[1]), 0));
13770 operands[1] = gen_rtx_MEM (V8QImode, addr);
13773 /* Make operand1 a register if it isn't already. */
13774 if ((reload_in_progress | reload_completed) == 0
13775 && !register_operand (operands[0], V8QImode)
13776 && !register_operand (operands[1], V8QImode)
13777 && operands[1] != CONST0_RTX (V8QImode))
13779 rtx temp = force_reg (V8QImode, operands[1]);
13780 emit_move_insn (operands[0], temp);
13785 (define_insn_and_split "*pushti"
13786 [(set (match_operand:TI 0 "push_operand" "=<")
13787 (match_operand:TI 1 "nonmemory_operand" "x"))]
13791 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
13792 (set (mem:TI (reg:SI 7)) (match_dup 1))]
13794 [(set_attr "type" "sse")])
13796 (define_insn_and_split "*pushv4sf"
13797 [(set (match_operand:V4SF 0 "push_operand" "=<")
13798 (match_operand:V4SF 1 "nonmemory_operand" "x"))]
13802 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
13803 (set (mem:V4SF (reg:SI 7)) (match_dup 1))]
13805 [(set_attr "type" "sse")])
13807 (define_insn_and_split "*pushv4si"
13808 [(set (match_operand:V4SI 0 "push_operand" "=<")
13809 (match_operand:V4SI 1 "nonmemory_operand" "x"))]
13813 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
13814 (set (mem:V4SI (reg:SI 7)) (match_dup 1))]
13816 [(set_attr "type" "sse")])
13818 (define_insn_and_split "*pushv2si"
13819 [(set (match_operand:V2SI 0 "push_operand" "=<")
13820 (match_operand:V2SI 1 "nonmemory_operand" "y"))]
13824 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
13825 (set (mem:V2SI (reg:SI 7)) (match_dup 1))]
13827 [(set_attr "type" "mmx")])
13829 (define_insn_and_split "*pushv4hi"
13830 [(set (match_operand:V4HI 0 "push_operand" "=<")
13831 (match_operand:V4HI 1 "nonmemory_operand" "y"))]
13835 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
13836 (set (mem:V4HI (reg:SI 7)) (match_dup 1))]
13838 [(set_attr "type" "mmx")])
13840 (define_insn_and_split "*pushv8qi"
13841 [(set (match_operand:V8QI 0 "push_operand" "=<")
13842 (match_operand:V8QI 1 "nonmemory_operand" "y"))]
13846 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
13847 (set (mem:V8QI (reg:SI 7)) (match_dup 1))]
13849 [(set_attr "type" "mmx")])
13851 (define_insn "movti_internal"
13852 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,m")
13853 (match_operand:TI 1 "general_operand" "xm,x"))]
13856 movaps\\t{%1, %0|%0, %1}
13857 movaps\\t{%1, %0|%0, %1}"
13858 [(set_attr "type" "sse")])
13860 ;; These two patterns are useful for specifying exactly whether to use
13861 ;; movaps or movups
13862 (define_insn "sse_movaps"
13863 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
13864 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 38))]
13867 movaps\\t{%1, %0|%0, %1}
13868 movaps\\t{%1, %0|%0, %1}"
13869 [(set_attr "type" "sse")])
13871 (define_insn "sse_movups"
13872 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
13873 (unspec:V4SF [(match_operand:V4SF 1 "general_operand" "xm,x")] 39))]
13876 movups\\t{%1, %0|%0, %1}
13877 movups\\t{%1, %0|%0, %1}"
13878 [(set_attr "type" "sse")])
13881 ;; SSE Strange Moves.
13883 (define_insn "sse_movmskps"
13884 [(set (match_operand:SI 0 "register_operand" "=r")
13885 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
13887 "movmskps\\t{%1, %0|%0, %1}"
13888 [(set_attr "type" "sse")])
13890 (define_insn "mmx_pmovmskb"
13891 [(set (match_operand:SI 0 "register_operand" "=r")
13892 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
13894 "pmovmskb\\t{%1, %0|%0, %1}"
13895 [(set_attr "type" "sse")])
13897 (define_insn "mmx_maskmovq"
13898 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
13899 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
13900 (match_operand:V8QI 2 "register_operand" "y")] 32))]
13902 ;; @@@ check ordering of operands in intel/nonintel syntax
13903 "maskmovq\\t{%2, %1|%1, %2}"
13904 [(set_attr "type" "sse")])
13906 (define_insn "sse_movntv4sf"
13907 [(set (match_operand:V4SF 0 "memory_operand" "=m")
13908 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
13910 "movntps\\t{%1, %0|%0, %1}"
13911 [(set_attr "type" "sse")])
13913 (define_insn "sse_movntdi"
13914 [(set (match_operand:DI 0 "memory_operand" "=m")
13915 (unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
13917 "movntq\\t{%1, %0|%0, %1}"
13918 [(set_attr "type" "sse")])
13920 (define_insn "sse_movhlps"
13921 [(set (match_operand:V4SF 0 "register_operand" "=x")
13923 (match_operand:V4SF 1 "register_operand" "0")
13924 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
13925 (parallel [(const_int 2)
13931 "movhlps\\t{%2, %0|%0, %2}"
13932 [(set_attr "type" "sse")])
13934 (define_insn "sse_movlhps"
13935 [(set (match_operand:V4SF 0 "register_operand" "=x")
13937 (match_operand:V4SF 1 "register_operand" "0")
13938 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
13939 (parallel [(const_int 2)
13945 "movlhps\\t{%2, %0|%0, %2}"
13946 [(set_attr "type" "sse")])
13948 (define_insn "sse_movhps"
13949 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
13951 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
13952 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
13954 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
13955 "movhps\\t{%2, %0|%0, %2}"
13956 [(set_attr "type" "sse")])
13958 (define_insn "sse_movlps"
13959 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
13961 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
13962 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
13964 "TARGET_SSE && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
13965 "movlps\\t{%2, %0|%0, %2}"
13966 [(set_attr "type" "sse")])
13968 (define_insn "sse_loadss"
13969 [(set (match_operand:V4SF 0 "register_operand" "=x")
13971 (match_operand:V4SF 1 "memory_operand" "m")
13972 (vec_duplicate:V4SF (float:SF (const_int 0)))
13975 "movss\\t{%1, %0|%0, %1}"
13976 [(set_attr "type" "sse")])
13978 (define_insn "sse_movss"
13979 [(set (match_operand:V4SF 0 "register_operand" "=x")
13981 (match_operand:V4SF 1 "register_operand" "0")
13982 (match_operand:V4SF 2 "register_operand" "x")
13985 "movss\\t{%2, %0|%0, %2}"
13986 [(set_attr "type" "sse")])
13988 (define_insn "sse_storess"
13989 [(set (match_operand:SF 0 "memory_operand" "=m")
13991 (match_operand:V4SF 1 "register_operand" "x")
13992 (parallel [(const_int 0)])))]
13994 "movss\\t{%1, %0|%0, %1}"
13995 [(set_attr "type" "sse")])
13997 (define_insn "sse_shufps"
13998 [(set (match_operand:V4SF 0 "register_operand" "=x")
13999 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
14000 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
14001 (match_operand:SI 3 "immediate_operand" "i")] 41))]
14003 ;; @@@ check operand order for intel/nonintel syntax
14004 "shufps\\t{%3, %2, %0|%0, %2, %3}"
14005 [(set_attr "type" "sse")])
14010 (define_insn "addv4sf3"
14011 [(set (match_operand:V4SF 0 "register_operand" "=x")
14012 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
14013 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
14015 "addps\\t{%2, %0|%0, %2}"
14016 [(set_attr "type" "sse")])
14018 (define_insn "vmaddv4sf3"
14019 [(set (match_operand:V4SF 0 "register_operand" "=x")
14020 (vec_merge:V4SF (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
14021 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
14025 "addss\\t{%2, %0|%0, %2}"
14026 [(set_attr "type" "sse")])
14028 (define_insn "subv4sf3"
14029 [(set (match_operand:V4SF 0 "register_operand" "=x")
14030 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
14031 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
14033 "subps\\t{%2, %0|%0, %2}"
14034 [(set_attr "type" "sse")])
14036 (define_insn "vmsubv4sf3"
14037 [(set (match_operand:V4SF 0 "register_operand" "=x")
14038 (vec_merge:V4SF (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
14039 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
14043 "subss\\t{%2, %0|%0, %2}"
14044 [(set_attr "type" "sse")])
14046 (define_insn "mulv4sf3"
14047 [(set (match_operand:V4SF 0 "register_operand" "=x")
14048 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
14049 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
14051 "mulps\\t{%2, %0|%0, %2}"
14052 [(set_attr "type" "sse")])
14054 (define_insn "vmmulv4sf3"
14055 [(set (match_operand:V4SF 0 "register_operand" "=x")
14056 (vec_merge:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
14057 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
14061 "mulss\\t{%2, %0|%0, %2}"
14062 [(set_attr "type" "sse")])
14064 (define_insn "divv4sf3"
14065 [(set (match_operand:V4SF 0 "register_operand" "=x")
14066 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
14067 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
14069 "divps\\t{%2, %0|%0, %2}"
14070 [(set_attr "type" "sse")])
14072 (define_insn "vmdivv4sf3"
14073 [(set (match_operand:V4SF 0 "register_operand" "=x")
14074 (vec_merge:V4SF (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
14075 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
14079 "divss\\t{%2, %0|%0, %2}"
14080 [(set_attr "type" "sse")])
14083 ;; SSE square root/reciprocal
14085 (define_insn "rcpv4sf2"
14086 [(set (match_operand:V4SF 0 "register_operand" "=x")
14087 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42))]
14089 "rcpps\\t{%1, %0|%0, %1}"
14090 [(set_attr "type" "sse")])
14092 (define_insn "vmrcpv4sf2"
14093 [(set (match_operand:V4SF 0 "register_operand" "=x")
14094 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 42)
14095 (match_operand:V4SF 2 "register_operand" "0")
14098 "rcpss\\t{%1, %0|%0, %1}"
14099 [(set_attr "type" "sse")])
14101 (define_insn "rsqrtv4sf2"
14102 [(set (match_operand:V4SF 0 "register_operand" "=x")
14103 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43))]
14105 "rsqrtps\\t{%1, %0|%0, %1}"
14106 [(set_attr "type" "sse")])
14108 (define_insn "vmrsqrtv4sf2"
14109 [(set (match_operand:V4SF 0 "register_operand" "=x")
14110 (vec_merge:V4SF (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "xm")] 43)
14111 (match_operand:V4SF 2 "register_operand" "0")
14114 "rsqrtss\\t{%1, %0|%0, %1}"
14115 [(set_attr "type" "sse")])
14117 (define_insn "sqrtv4sf2"
14118 [(set (match_operand:V4SF 0 "register_operand" "=x")
14119 (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm")))]
14121 "sqrtps\\t{%1, %0|%0, %1}"
14122 [(set_attr "type" "sse")])
14124 (define_insn "vmsqrtv4sf2"
14125 [(set (match_operand:V4SF 0 "register_operand" "=x")
14126 (vec_merge:V4SF (sqrt:V4SF (match_operand:V4SF 1 "register_operand" "xm"))
14127 (match_operand:V4SF 2 "register_operand" "0")
14130 "sqrtss\\t{%1, %0|%0, %1}"
14131 [(set_attr "type" "sse")])
14134 ;; SSE logical operations.
14136 ;; These are not called andti3 etc. because we really really don't want
14137 ;; the compiler to widen DImode ands to TImode ands and then try to move
14138 ;; into DImode subregs of SSE registers, and them together, and move out
14139 ;; of DImode subregs again!
14141 (define_insn "*sse_andti3_df_1"
14142 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
14143 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
14144 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
14146 "andpd\\t{%2, %0|%0, %2}"
14147 [(set_attr "type" "sse")])
14149 (define_insn "*sse_andti3_df_2"
14150 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
14151 (and:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
14152 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
14154 "andpd\\t{%2, %0|%0, %2}"
14155 [(set_attr "type" "sse")])
14157 (define_insn "*sse_andti3_sf_1"
14158 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
14159 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
14160 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
14162 "andps\\t{%2, %0|%0, %2}"
14163 [(set_attr "type" "sse")])
14165 (define_insn "*sse_andti3_sf_2"
14166 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
14167 (and:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
14168 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14170 "andps\\t{%2, %0|%0, %2}"
14171 [(set_attr "type" "sse")])
14173 (define_insn "sse_andti3"
14174 [(set (match_operand:TI 0 "register_operand" "=x")
14175 (and:TI (match_operand:TI 1 "register_operand" "%0")
14176 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14177 "TARGET_SSE && !TARGET_SSE2"
14178 "andps\\t{%2, %0|%0, %2}"
14179 [(set_attr "type" "sse")])
14181 (define_insn "*sse_andti3_sse2"
14182 [(set (match_operand:TI 0 "register_operand" "=x")
14183 (and:TI (match_operand:TI 1 "register_operand" "%0")
14184 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14186 "pand\\t{%2, %0|%0, %2}"
14187 [(set_attr "type" "sse")])
14189 (define_insn "*sse_nandti3_df"
14190 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
14191 (and:TI (not:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0))
14192 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
14194 "andnpd\\t{%2, %0|%0, %2}"
14195 [(set_attr "type" "sse")])
14197 (define_insn "*sse_nandti3_sf"
14198 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
14199 (and:TI (not:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0))
14200 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14202 "andnps\\t{%2, %0|%0, %2}"
14203 [(set_attr "type" "sse")])
14205 (define_insn "sse_nandti3"
14206 [(set (match_operand:TI 0 "register_operand" "=x")
14207 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
14208 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14209 "TARGET_SSE && !TARGET_SSE2"
14210 "andnps\\t{%2, %0|%0, %2}"
14211 [(set_attr "type" "sse")])
14213 (define_insn "*sse_nandti3_sse2"
14214 [(set (match_operand:TI 0 "register_operand" "=x")
14215 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
14216 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14218 "pnand\\t{%2, %0|%0, %2}"
14219 [(set_attr "type" "sse")])
14221 (define_insn "*sse_iorti3_df_1"
14222 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
14223 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
14224 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
14226 "orpd\\t{%2, %0|%0, %2}"
14227 [(set_attr "type" "sse")])
14229 (define_insn "*sse_iorti3_df_2"
14230 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
14231 (ior:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
14232 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
14234 "orpd\\t{%2, %0|%0, %2}"
14235 [(set_attr "type" "sse")])
14237 (define_insn "*sse_iorti3_sf_1"
14238 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
14239 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
14240 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
14242 "orps\\t{%2, %0|%0, %2}"
14243 [(set_attr "type" "sse")])
14245 (define_insn "*sse_iorti3_sf_2"
14246 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
14247 (ior:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
14248 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14250 "orps\\t{%2, %0|%0, %2}"
14251 [(set_attr "type" "sse")])
14253 (define_insn "sse_iorti3"
14254 [(set (match_operand:TI 0 "register_operand" "=x")
14255 (ior:TI (match_operand:TI 1 "register_operand" "%0")
14256 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14257 "TARGET_SSE && !TARGET_SSE2"
14258 "orps\\t{%2, %0|%0, %2}"
14259 [(set_attr "type" "sse")])
14261 (define_insn "*sse_iorti3_sse2"
14262 [(set (match_operand:TI 0 "register_operand" "=x")
14263 (ior:TI (match_operand:TI 1 "register_operand" "%0")
14264 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14266 "por\\t{%2, %0|%0, %2}"
14267 [(set_attr "type" "sse")])
14269 (define_insn "*sse_xorti3_df_1"
14270 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
14271 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "%0") 0)
14272 (subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
14274 "xorpd\\t{%2, %0|%0, %2}"
14275 [(set_attr "type" "sse")])
14277 (define_insn "*sse_xorti3_df_2"
14278 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
14279 (xor:TI (subreg:TI (match_operand:DF 1 "register_operand" "0") 0)
14280 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
14282 "xorpd\\t{%2, %0|%0, %2}"
14283 [(set_attr "type" "sse")])
14285 (define_insn "*sse_xorti3_sf_1"
14286 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
14287 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "%0") 0)
14288 (subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
14290 "xorps\\t{%2, %0|%0, %2}"
14291 [(set_attr "type" "sse")])
14293 (define_insn "*sse_xorti3_sf_2"
14294 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
14295 (xor:TI (subreg:TI (match_operand:SF 1 "register_operand" "0") 0)
14296 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14298 "xorps\\t{%2, %0|%0, %2}"
14299 [(set_attr "type" "sse")])
14301 (define_insn "sse_xorti3"
14302 [(set (match_operand:TI 0 "register_operand" "=x")
14303 (xor:TI (match_operand:TI 1 "register_operand" "%0")
14304 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14305 "TARGET_SSE && !TARGET_SSE2"
14306 "xorps\\t{%2, %0|%0, %2}"
14307 [(set_attr "type" "sse")])
14309 (define_insn "*sse_xorti3_sse2"
14310 [(set (match_operand:TI 0 "register_operand" "=x")
14311 (xor:TI (match_operand:TI 1 "register_operand" "%0")
14312 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
14314 "pxor\\t{%2, %0|%0, %2}"
14315 [(set_attr "type" "sse")])
14317 ;; Use xor, but don't show input operands so they aren't live before
14319 (define_insn "sse_clrti"
14320 [(set (match_operand:TI 0 "register_operand" "=x")
14321 (unspec:TI [(const_int 0)] 45))]
14323 "xorps\\t{%0, %0|%0, %0}"
14324 [(set_attr "type" "sse")])
14327 ;; SSE mask-generating compares
14329 (define_insn "maskcmpv4sf3"
14330 [(set (match_operand:V4SI 0 "register_operand" "=x")
14331 (match_operator:V4SI 3 "sse_comparison_operator"
14332 [(match_operand:V4SF 1 "register_operand" "0")
14333 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))]
14335 "cmp%D3ps\\t{%2, %0|%0, %2}"
14336 [(set_attr "type" "sse")])
14338 (define_insn "maskncmpv4sf3"
14339 [(set (match_operand:V4SI 0 "register_operand" "=x")
14341 (match_operator:V4SI 3 "sse_comparison_operator"
14342 [(match_operand:V4SF 1 "register_operand" "0")
14343 (match_operand:V4SF 2 "nonimmediate_operand" "x")])))]
14345 "cmpn%D3ps\\t{%2, %0|%0, %2}"
14346 [(set_attr "type" "sse")])
14348 (define_insn "vmmaskcmpv4sf3"
14349 [(set (match_operand:V4SI 0 "register_operand" "=x")
14351 (match_operator:V4SI 3 "sse_comparison_operator"
14352 [(match_operand:V4SF 1 "register_operand" "0")
14353 (match_operand:V4SF 2 "nonimmediate_operand" "x")])
14357 "cmp%D3ss\\t{%2, %0|%0, %2}"
14358 [(set_attr "type" "sse")])
14360 (define_insn "vmmaskncmpv4sf3"
14361 [(set (match_operand:V4SI 0 "register_operand" "=x")
14364 (match_operator:V4SI 3 "sse_comparison_operator"
14365 [(match_operand:V4SF 1 "register_operand" "0")
14366 (match_operand:V4SF 2 "nonimmediate_operand" "x")]))
14367 (subreg:V4SI (match_dup 1) 0)
14370 "cmp%D3ss\\t{%2, %0|%0, %2}"
14371 [(set_attr "type" "sse")])
14373 (define_insn "sse_comi"
14374 [(set (reg:CCFP 17)
14375 (match_operator:CCFP 2 "sse_comparison_operator"
14377 (match_operand:V4SF 0 "register_operand" "x")
14378 (parallel [(const_int 0)]))
14380 (match_operand:V4SF 1 "register_operand" "x")
14381 (parallel [(const_int 0)]))]))]
14383 "comiss\\t{%2, %0|%0, %2}"
14384 [(set_attr "type" "sse")])
14386 (define_insn "sse_ucomi"
14387 [(set (reg:CCFPU 17)
14388 (match_operator:CCFPU 2 "sse_comparison_operator"
14390 (match_operand:V4SF 0 "register_operand" "x")
14391 (parallel [(const_int 0)]))
14393 (match_operand:V4SF 1 "register_operand" "x")
14394 (parallel [(const_int 0)]))]))]
14396 "ucomiss\\t{%2, %0|%0, %2}"
14397 [(set_attr "type" "sse")])
14402 (define_insn "sse_unpckhps"
14403 [(set (match_operand:V4SF 0 "register_operand" "=x")
14405 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
14406 (parallel [(const_int 2)
14410 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
14411 (parallel [(const_int 0)
14417 "unpckhps\\t{%2, %0|%0, %2}"
14418 [(set_attr "type" "sse")])
14420 (define_insn "sse_unpcklps"
14421 [(set (match_operand:V4SF 0 "register_operand" "=x")
14423 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
14424 (parallel [(const_int 0)
14428 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "x")
14429 (parallel [(const_int 2)
14435 "unpcklps\\t{%2, %0|%0, %2}"
14436 [(set_attr "type" "sse")])
14441 (define_insn "smaxv4sf3"
14442 [(set (match_operand:V4SF 0 "register_operand" "=x")
14443 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
14444 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
14446 "maxps\\t{%2, %0|%0, %2}"
14447 [(set_attr "type" "sse")])
14449 (define_insn "vmsmaxv4sf3"
14450 [(set (match_operand:V4SF 0 "register_operand" "=x")
14451 (vec_merge:V4SF (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
14452 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
14456 "maxss\\t{%2, %0|%0, %2}"
14457 [(set_attr "type" "sse")])
14459 (define_insn "sminv4sf3"
14460 [(set (match_operand:V4SF 0 "register_operand" "=x")
14461 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
14462 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
14464 "minps\\t{%2, %0|%0, %2}"
14465 [(set_attr "type" "sse")])
14467 (define_insn "vmsminv4sf3"
14468 [(set (match_operand:V4SF 0 "register_operand" "=x")
14469 (vec_merge:V4SF (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
14470 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
14474 "minss\\t{%2, %0|%0, %2}"
14475 [(set_attr "type" "sse")])
14478 ;; SSE <-> integer/MMX conversions
14480 (define_insn "cvtpi2ps"
14481 [(set (match_operand:V4SF 0 "register_operand" "=x")
14482 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
14483 (vec_duplicate:V4SF
14484 (float:V2SF (match_operand:V2SI 2 "register_operand" "ym")))
14487 "cvtpi2ps\\t{%2, %0|%0, %2}"
14488 [(set_attr "type" "sse")])
14490 (define_insn "cvtps2pi"
14491 [(set (match_operand:V2SI 0 "register_operand" "=y")
14492 (vec_select:V2SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
14497 "cvtps2pi\\t{%1, %0|%0, %1}"
14498 [(set_attr "type" "sse")])
14500 (define_insn "cvttps2pi"
14501 [(set (match_operand:V2SI 0 "register_operand" "=y")
14502 (vec_select:V2SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
14507 "cvttps2pi\\t{%1, %0|%0, %1}"
14508 [(set_attr "type" "sse")])
14510 (define_insn "cvtsi2ss"
14511 [(set (match_operand:V4SF 0 "register_operand" "=x")
14512 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0")
14513 (vec_duplicate:V4SF
14514 (float:SF (match_operand:SI 2 "register_operand" "rm")))
14517 "cvtsi2ss\\t{%2, %0|%0, %2}"
14518 [(set_attr "type" "sse")])
14520 (define_insn "cvtss2si"
14521 [(set (match_operand:SI 0 "register_operand" "=y")
14522 (vec_select:SI (fix:V4SI (match_operand:V4SF 1 "register_operand" "xm"))
14523 (parallel [(const_int 0)])))]
14525 "cvtss2si\\t{%1, %0|%0, %1}"
14526 [(set_attr "type" "sse")])
14528 (define_insn "cvttss2si"
14529 [(set (match_operand:SI 0 "register_operand" "=y")
14530 (vec_select:SI (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "xm")] 30)
14531 (parallel [(const_int 0)])))]
14533 "cvttss2si\\t{%1, %0|%0, %1}"
14534 [(set_attr "type" "sse")])
14541 (define_insn "addv8qi3"
14542 [(set (match_operand:V8QI 0 "register_operand" "=y")
14543 (plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
14544 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
14546 "paddb\\t{%2, %0|%0, %2}"
14547 [(set_attr "type" "mmx")])
14549 (define_insn "addv4hi3"
14550 [(set (match_operand:V4HI 0 "register_operand" "=y")
14551 (plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
14552 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
14554 "paddw\\t{%2, %0|%0, %2}"
14555 [(set_attr "type" "mmx")])
14557 (define_insn "addv2si3"
14558 [(set (match_operand:V2SI 0 "register_operand" "=y")
14559 (plus:V2SI (match_operand:V2SI 1 "register_operand" "0")
14560 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
14562 "paddd\\t{%2, %0|%0, %2}"
14563 [(set_attr "type" "mmx")])
14565 (define_insn "ssaddv8qi3"
14566 [(set (match_operand:V8QI 0 "register_operand" "=y")
14567 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
14568 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
14570 "paddsb\\t{%2, %0|%0, %2}"
14571 [(set_attr "type" "mmx")])
14573 (define_insn "ssaddv4hi3"
14574 [(set (match_operand:V4HI 0 "register_operand" "=y")
14575 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
14576 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
14578 "paddsw\\t{%2, %0|%0, %2}"
14579 [(set_attr "type" "mmx")])
14581 (define_insn "usaddv8qi3"
14582 [(set (match_operand:V8QI 0 "register_operand" "=y")
14583 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "0")
14584 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
14586 "paddusb\\t{%2, %0|%0, %2}"
14587 [(set_attr "type" "mmx")])
14589 (define_insn "usaddv4hi3"
14590 [(set (match_operand:V4HI 0 "register_operand" "=y")
14591 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "0")
14592 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
14594 "paddusw\\t{%2, %0|%0, %2}"
14595 [(set_attr "type" "mmx")])
14597 (define_insn "subv8qi3"
14598 [(set (match_operand:V8QI 0 "register_operand" "=y")
14599 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
14600 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
14602 "psubb\\t{%2, %0|%0, %2}"
14603 [(set_attr "type" "mmx")])
14605 (define_insn "subv4hi3"
14606 [(set (match_operand:V4HI 0 "register_operand" "=y")
14607 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
14608 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
14610 "psubw\\t{%2, %0|%0, %2}"
14611 [(set_attr "type" "mmx")])
14613 (define_insn "subv2si3"
14614 [(set (match_operand:V2SI 0 "register_operand" "=y")
14615 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
14616 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
14618 "psubd\\t{%2, %0|%0, %2}"
14619 [(set_attr "type" "mmx")])
14621 (define_insn "sssubv8qi3"
14622 [(set (match_operand:V8QI 0 "register_operand" "=y")
14623 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
14624 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
14626 "psubsb\\t{%2, %0|%0, %2}"
14627 [(set_attr "type" "mmx")])
14629 (define_insn "sssubv4hi3"
14630 [(set (match_operand:V4HI 0 "register_operand" "=y")
14631 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
14632 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
14634 "psubsw\\t{%2, %0|%0, %2}"
14635 [(set_attr "type" "mmx")])
14637 (define_insn "ussubv8qi3"
14638 [(set (match_operand:V8QI 0 "register_operand" "=y")
14639 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
14640 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
14642 "psubusb\\t{%2, %0|%0, %2}"
14643 [(set_attr "type" "mmx")])
14645 (define_insn "ussubv4hi3"
14646 [(set (match_operand:V4HI 0 "register_operand" "=y")
14647 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
14648 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
14650 "psubusw\\t{%2, %0|%0, %2}"
14651 [(set_attr "type" "mmx")])
14653 (define_insn "mulv4hi3"
14654 [(set (match_operand:V4HI 0 "register_operand" "=y")
14655 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
14656 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
14658 "pmullw\\t{%2, %0|%0, %2}"
14659 [(set_attr "type" "mmx")])
14661 (define_insn "smulv4hi3_highpart"
14662 [(set (match_operand:V4HI 0 "register_operand" "=y")
14665 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
14666 (sign_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
14669 "pmulhw\\t{%2, %0|%0, %2}"
14670 [(set_attr "type" "mmx")])
14672 (define_insn "umulv4hi3_highpart"
14673 [(set (match_operand:V4HI 0 "register_operand" "=y")
14676 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "0"))
14677 (zero_extend:V4SI (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
14680 "pmulhuw\\t{%2, %0|%0, %2}"
14681 [(set_attr "type" "mmx")])
14683 (define_insn "mmx_pmaddwd"
14684 [(set (match_operand:V2SI 0 "register_operand" "=y")
14687 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
14688 (parallel [(const_int 0)
14690 (sign_extend:V2SI (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
14691 (parallel [(const_int 0)
14694 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
14695 (parallel [(const_int 1)
14697 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
14698 (parallel [(const_int 1)
14699 (const_int 3)]))))))]
14701 "pmaddwd\\t{%2, %0|%0, %2}"
14702 [(set_attr "type" "mmx")])
14705 ;; MMX logical operations
14706 ;; Note we don't want to declare these as regular iordi3 insns to prevent
14707 ;; normal code that also wants to use the FPU from getting broken.
14708 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
14709 (define_insn "mmx_iordi3"
14710 [(set (match_operand:DI 0 "register_operand" "=y")
14712 [(ior:DI (match_operand:DI 1 "register_operand" "0")
14713 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
14715 "por\\t{%2, %0|%0, %2}"
14716 [(set_attr "type" "mmx")])
14718 (define_insn "mmx_xordi3"
14719 [(set (match_operand:DI 0 "register_operand" "=y")
14721 [(xor:DI (match_operand:DI 1 "register_operand" "0")
14722 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
14724 "pxor\\t{%2, %0|%0, %2}"
14725 [(set_attr "type" "mmx")])
14727 ;; Same as pxor, but don't show input operands so that we don't think
14729 (define_insn "mmx_clrdi"
14730 [(set (match_operand:DI 0 "register_operand" "=y")
14731 (unspec:DI [(const_int 0)] 45))]
14733 "pxor\\t{%0, %0|%0, %0}"
14734 [(set_attr "type" "mmx")])
14736 (define_insn "mmx_anddi3"
14737 [(set (match_operand:DI 0 "register_operand" "=y")
14739 [(and:DI (match_operand:DI 1 "register_operand" "0")
14740 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
14742 "pand\\t{%2, %0|%0, %2}"
14743 [(set_attr "type" "mmx")])
14745 (define_insn "mmx_nanddi3"
14746 [(set (match_operand:DI 0 "register_operand" "=y")
14748 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
14749 (match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
14751 "pandn\\t{%2, %0|%0, %2}"
14752 [(set_attr "type" "mmx")])
14755 ;; MMX unsigned averages/sum of absolute differences
14757 (define_insn "mmx_uavgv8qi3"
14758 [(set (match_operand:V8QI 0 "register_operand" "=y")
14760 (plus:V8QI (plus:V8QI
14761 (match_operand:V8QI 1 "register_operand" "0")
14762 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
14763 (vec_const:V8QI (parallel [(const_int 1)
14773 "pavgb\\t{%2, %0|%0, %2}"
14774 [(set_attr "type" "sse")])
14776 (define_insn "mmx_uavgv4hi3"
14777 [(set (match_operand:V4HI 0 "register_operand" "=y")
14779 (plus:V4HI (plus:V4HI
14780 (match_operand:V4HI 1 "register_operand" "0")
14781 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
14782 (vec_const:V4HI (parallel [(const_int 1)
14788 "pavgw\\t{%2, %0|%0, %2}"
14789 [(set_attr "type" "sse")])
14791 (define_insn "mmx_psadbw"
14792 [(set (match_operand:V8QI 0 "register_operand" "=y")
14793 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
14794 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
14796 "psadbw\\t{%2, %0|%0, %2}"
14797 [(set_attr "type" "sse")])
14800 ;; MMX insert/extract/shuffle
14802 (define_insn "mmx_pinsrw"
14803 [(set (match_operand:V4HI 0 "register_operand" "=y")
14804 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
14805 (vec_duplicate:V4HI
14806 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
14807 (match_operand:SI 3 "immediate_operand" "i")))]
14809 "pinsrw\\t{%3, %2, %0|%0, %2, %3}"
14810 [(set_attr "type" "sse")])
14812 (define_insn "mmx_pextrw"
14813 [(set (match_operand:SI 0 "register_operand" "=r")
14814 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
14816 [(match_operand:SI 2 "immediate_operand" "i")]))))]
14818 "pextrw\\t{%2, %1, %0|%0, %1, %2}"
14819 [(set_attr "type" "sse")])
14821 (define_insn "mmx_pshufw"
14822 [(set (match_operand:V4HI 0 "register_operand" "=y")
14823 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
14824 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
14825 (match_operand:SI 3 "immediate_operand" "i")] 41))]
14827 "pshufw\\t{%3, %2, %0|%0, %2, %3}"
14828 [(set_attr "type" "sse")])
14831 ;; MMX mask-generating comparisons
14833 (define_insn "eqv8qi3"
14834 [(set (match_operand:V8QI 0 "register_operand" "=y")
14835 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
14836 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
14838 "pcmpeqb\\t{%2, %0|%0, %2}"
14839 [(set_attr "type" "mmx")])
14841 (define_insn "eqv4hi3"
14842 [(set (match_operand:V4HI 0 "register_operand" "=y")
14843 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
14844 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
14846 "pcmpeqw\\t{%2, %0|%0, %2}"
14847 [(set_attr "type" "mmx")])
14849 (define_insn "eqv2si3"
14850 [(set (match_operand:V2SI 0 "register_operand" "=y")
14851 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
14852 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
14854 "pcmpeqd\\t{%2, %0|%0, %2}"
14855 [(set_attr "type" "mmx")])
14857 (define_insn "gtv8qi3"
14858 [(set (match_operand:V8QI 0 "register_operand" "=y")
14859 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
14860 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
14862 "pcmpgtb\\t{%2, %0|%0, %2}"
14863 [(set_attr "type" "mmx")])
14865 (define_insn "gtv4hi3"
14866 [(set (match_operand:V4HI 0 "register_operand" "=y")
14867 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
14868 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
14870 "pcmpgtw\\t{%2, %0|%0, %2}"
14871 [(set_attr "type" "mmx")])
14873 (define_insn "gtv2si3"
14874 [(set (match_operand:V2SI 0 "register_operand" "=y")
14875 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
14876 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
14878 "pcmpgtd\\t{%2, %0|%0, %2}"
14879 [(set_attr "type" "mmx")])
14882 ;; MMX max/min insns
14884 (define_insn "umaxv8qi3"
14885 [(set (match_operand:V8QI 0 "register_operand" "=y")
14886 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
14887 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
14889 "pmaxub\\t{%2, %0|%0, %2}"
14890 [(set_attr "type" "sse")])
14892 (define_insn "smaxv4hi3"
14893 [(set (match_operand:V4HI 0 "register_operand" "=y")
14894 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
14895 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
14897 "pmaxsw\\t{%2, %0|%0, %2}"
14898 [(set_attr "type" "sse")])
14900 (define_insn "uminv8qi3"
14901 [(set (match_operand:V8QI 0 "register_operand" "=y")
14902 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
14903 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
14905 "pminub\\t{%2, %0|%0, %2}"
14906 [(set_attr "type" "sse")])
14908 (define_insn "sminv4hi3"
14909 [(set (match_operand:V4HI 0 "register_operand" "=y")
14910 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
14911 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
14913 "pminsw\\t{%2, %0|%0, %2}"
14914 [(set_attr "type" "sse")])
14919 (define_insn "ashrv4hi3"
14920 [(set (match_operand:V4HI 0 "register_operand" "=y")
14921 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
14922 (match_operand:DI 2 "nonmemory_operand" "yi")))]
14924 "psraw\\t{%2, %0|%0, %2}"
14925 [(set_attr "type" "mmx")])
14927 (define_insn "ashrv2si3"
14928 [(set (match_operand:V2SI 0 "register_operand" "=y")
14929 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
14930 (match_operand:DI 2 "nonmemory_operand" "yi")))]
14932 "psrad\\t{%2, %0|%0, %2}"
14933 [(set_attr "type" "mmx")])
14935 (define_insn "lshrv4hi3"
14936 [(set (match_operand:V4HI 0 "register_operand" "=y")
14937 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
14938 (match_operand:DI 2 "nonmemory_operand" "yi")))]
14940 "psrlw\\t{%2, %0|%0, %2}"
14941 [(set_attr "type" "mmx")])
14943 (define_insn "lshrv2si3"
14944 [(set (match_operand:V2SI 0 "register_operand" "=y")
14945 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
14946 (match_operand:DI 2 "nonmemory_operand" "yi")))]
14948 "psrld\\t{%2, %0|%0, %2}"
14949 [(set_attr "type" "mmx")])
14951 ;; See logical MMX insns.
14952 (define_insn "mmx_lshrdi3"
14953 [(set (match_operand:DI 0 "register_operand" "=y")
14955 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
14956 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
14958 "psrlq\\t{%2, %0|%0, %2}"
14959 [(set_attr "type" "mmx")])
14961 (define_insn "ashlv4hi3"
14962 [(set (match_operand:V4HI 0 "register_operand" "=y")
14963 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
14964 (match_operand:DI 2 "nonmemory_operand" "yi")))]
14966 "psllw\\t{%2, %0|%0, %2}"
14967 [(set_attr "type" "mmx")])
14969 (define_insn "ashlv2si3"
14970 [(set (match_operand:V2SI 0 "register_operand" "=y")
14971 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
14972 (match_operand:DI 2 "nonmemory_operand" "yi")))]
14974 "pslld\\t{%2, %0|%0, %2}"
14975 [(set_attr "type" "mmx")])
14977 ;; See logical MMX insns.
14978 (define_insn "mmx_ashldi3"
14979 [(set (match_operand:DI 0 "register_operand" "=y")
14981 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
14982 (match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
14984 "psllq\\t{%2, %0|%0, %2}"
14985 [(set_attr "type" "mmx")])
14988 ;; MMX pack/unpack insns.
14990 (define_insn "mmx_packsswb"
14991 [(set (match_operand:V8QI 0 "register_operand" "=y")
14993 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
14994 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
14996 "packsswb\\t{%2, %0|%0, %2}"
14997 [(set_attr "type" "mmx")])
14999 (define_insn "mmx_packssdw"
15000 [(set (match_operand:V4HI 0 "register_operand" "=y")
15002 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
15003 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
15005 "packssdw\\t{%2, %0|%0, %2}"
15006 [(set_attr "type" "mmx")])
15008 (define_insn "mmx_packuswb"
15009 [(set (match_operand:V8QI 0 "register_operand" "=y")
15011 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
15012 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
15014 "packuswb\\t{%2, %0|%0, %2}"
15015 [(set_attr "type" "mmx")])
15017 (define_insn "mmx_punpckhbw"
15018 [(set (match_operand:V8QI 0 "register_operand" "=y")
15020 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
15021 (parallel [(const_int 4)
15029 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
15030 (parallel [(const_int 0)
15040 "punpckhbw\\t{%2, %0|%0, %2}"
15041 [(set_attr "type" "mmx")])
15043 (define_insn "mmx_punpckhwd"
15044 [(set (match_operand:V4HI 0 "register_operand" "=y")
15046 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
15047 (parallel [(const_int 0)
15051 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
15052 (parallel [(const_int 2)
15058 "punpckhwd\\t{%2, %0|%0, %2}"
15059 [(set_attr "type" "mmx")])
15061 (define_insn "mmx_punpckhdq"
15062 [(set (match_operand:V2SI 0 "register_operand" "=y")
15064 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
15065 (parallel [(const_int 0)
15067 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
15068 (parallel [(const_int 1)
15072 "punpckhdq\\t{%2, %0|%0, %2}"
15073 [(set_attr "type" "mmx")])
15075 (define_insn "mmx_punpcklbw"
15076 [(set (match_operand:V8QI 0 "register_operand" "=y")
15078 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
15079 (parallel [(const_int 0)
15087 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
15088 (parallel [(const_int 4)
15098 "punpcklbw\\t{%2, %0|%0, %2}"
15099 [(set_attr "type" "mmx")])
15101 (define_insn "mmx_punpcklwd"
15102 [(set (match_operand:V4HI 0 "register_operand" "=y")
15104 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
15105 (parallel [(const_int 2)
15109 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
15110 (parallel [(const_int 0)
15116 "punpcklwd\\t{%2, %0|%0, %2}"
15117 [(set_attr "type" "mmx")])
15119 (define_insn "mmx_punpckldq"
15120 [(set (match_operand:V2SI 0 "register_operand" "=y")
15122 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
15123 (parallel [(const_int 1)
15125 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
15126 (parallel [(const_int 0)
15130 "punpckldq\\t{%2, %0|%0, %2}"
15131 [(set_attr "type" "mmx")])
15134 ;; Miscellaneous stuff
15136 (define_insn "emms"
15137 [(unspec_volatile [(const_int 0)] 31)
15138 (clobber (reg:XF 8))
15139 (clobber (reg:XF 9))
15140 (clobber (reg:XF 10))
15141 (clobber (reg:XF 11))
15142 (clobber (reg:XF 12))
15143 (clobber (reg:XF 13))
15144 (clobber (reg:XF 14))
15145 (clobber (reg:XF 15))
15146 (clobber (reg:DI 29))
15147 (clobber (reg:DI 30))
15148 (clobber (reg:DI 31))
15149 (clobber (reg:DI 32))
15150 (clobber (reg:DI 33))
15151 (clobber (reg:DI 34))
15152 (clobber (reg:DI 35))
15153 (clobber (reg:DI 36))]
15156 [(set_attr "type" "mmx")
15157 (set_attr "memory" "unknown")])
15159 (define_insn "ldmxcsr"
15160 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 37)]
15163 [(set_attr "type" "mmx")])
15165 (define_insn "stmxcsr"
15166 [(set (match_operand:SI 0 "memory_operand" "=m")
15167 (unspec_volatile:SI [(const_int 0)] 40))]
15170 [(set_attr "type" "mmx")])
15172 (define_expand "sfence"
15173 [(set (match_dup 0)
15174 (unspec:BLK [(match_dup 0)] 44))]
15178 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
15179 MEM_VOLATILE_P (operands[0]) = 1;
15182 (define_insn "*sfence_insn"
15183 [(set (match_operand:BLK 0 "" "")
15184 (unspec:BLK [(match_dup 0)] 44))]
15187 [(set_attr "type" "sse")
15188 (set_attr "memory" "unknown")])
15190 (define_insn "prefetch"
15191 [(unspec [(match_operand:SI 0 "address_operand" "p")
15192 (match_operand:SI 1 "immediate_operand" "n")] 35)]
15196 switch (INTVAL (operands[1]))
15199 return \"prefetchnta\\t%a0\";
15201 return \"prefetcht0\\t%a0\";
15203 return \"prefetcht1\\t%a0\";
15205 return \"prefetcht2\\t%a0\";
15210 [(set_attr "type" "sse")])