1 ;; GCC machine description for IA-32 and x86-64.
2 ;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
4 ;; Free Software Foundation, Inc.
5 ;; Mostly by William Schelter.
6 ;; x86_64 support added by Jan Hubicka
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA. */
25 ;; The original PO technology requires these to be ordered by speed,
26 ;; so that assigner will pick the fastest.
28 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
30 ;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code
31 ;; updates for most instructions.
33 ;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register
34 ;; constraint letters.
36 ;; The special asm out single letter directives following a '%' are:
37 ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
39 ;; 'L' Print the opcode suffix for a 32-bit integer opcode.
40 ;; 'W' Print the opcode suffix for a 16-bit integer opcode.
41 ;; 'B' Print the opcode suffix for an 8-bit integer opcode.
42 ;; 'Q' Print the opcode suffix for a 64-bit float opcode.
43 ;; 'S' Print the opcode suffix for a 32-bit float opcode.
44 ;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
45 ;; 'J' Print the appropriate jump operand.
47 ;; 'b' Print the QImode name of the register for the indicated operand.
48 ;; %b0 would print %al if operands[0] is reg 0.
49 ;; 'w' Likewise, print the HImode name of the register.
50 ;; 'k' Likewise, print the SImode name of the register.
51 ;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
52 ;; 'y' Print "st(0)" instead of "st" as a register.
57 [; Relocation specifiers
69 (UNSPEC_STACK_PROBE 10)
70 (UNSPEC_STACK_ALLOC 11)
72 (UNSPEC_SSE_PROLOGUE_SAVE 13)
77 (UNSPEC_TLS_LD_BASE 17)
79 ; Other random patterns
89 ; For SSE/MMX support:
100 (UNSPEC_NOP 45) ; prevents combiner cleverness
125 [(UNSPECV_BLOCKAGE 0)
126 (UNSPECV_EH_RETURN 13)
135 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
138 ;; In C guard expressions, put expressions which may be compile-time
139 ;; constants first. This allows for better optimization. For
140 ;; example, write "TARGET_64BIT && reload_completed", not
141 ;; "reload_completed && TARGET_64BIT".
144 ;; Processor type. This attribute must exactly match the processor_type
145 ;; enumeration in i386.h.
146 (define_attr "cpu" "i386,i486,pentium,pentiumpro,k6,athlon,pentium4,k8"
147 (const (symbol_ref "ix86_tune")))
149 ;; A basic instruction type. Refinements due to arguments to be
150 ;; provided in other attributes.
153 alu,alu1,negnot,imov,imovx,lea,
154 incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
155 icmp,test,ibr,setcc,icmov,
156 push,pop,call,callv,leave,
158 fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,
159 sselog,sseiadd,sseishft,sseimul,
160 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
161 mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
162 (const_string "other"))
164 ;; Main data type used by the insn
166 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF"
167 (const_string "unknown"))
169 ;; The CPU unit operations uses.
170 (define_attr "unit" "integer,i387,sse,mmx,unknown"
171 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
172 (const_string "i387")
173 (eq_attr "type" "sselog,sseiadd,sseishft,sseimul,
174 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
176 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
178 (eq_attr "type" "other")
179 (const_string "unknown")]
180 (const_string "integer")))
182 ;; The (bounding maximum) length of an instruction immediate.
183 (define_attr "length_immediate" ""
184 (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
186 (eq_attr "unit" "i387,sse,mmx")
188 (eq_attr "type" "alu,alu1,negnot,imovx,ishift,rotate,ishift1,rotate1,
190 (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
191 (eq_attr "type" "imov,test")
192 (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
193 (eq_attr "type" "call")
194 (if_then_else (match_operand 0 "constant_call_address_operand" "")
197 (eq_attr "type" "callv")
198 (if_then_else (match_operand 1 "constant_call_address_operand" "")
201 ;; We don't know the size before shorten_branches. Expect
202 ;; the instruction to fit for better scheduling.
203 (eq_attr "type" "ibr")
206 (symbol_ref "/* Update immediate_length and other attributes! */
209 ;; The (bounding maximum) length of an instruction address.
210 (define_attr "length_address" ""
211 (cond [(eq_attr "type" "str,cld,other,multi,fxch")
213 (and (eq_attr "type" "call")
214 (match_operand 0 "constant_call_address_operand" ""))
216 (and (eq_attr "type" "callv")
217 (match_operand 1 "constant_call_address_operand" ""))
220 (symbol_ref "ix86_attr_length_address_default (insn)")))
222 ;; Set when length prefix is used.
223 (define_attr "prefix_data16" ""
224 (if_then_else (ior (eq_attr "mode" "HI")
225 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
229 ;; Set when string REP prefix is used.
230 (define_attr "prefix_rep" ""
231 (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
235 ;; Set when 0f opcode prefix is used.
236 (define_attr "prefix_0f" ""
238 (ior (eq_attr "type" "imovx,setcc,icmov")
239 (eq_attr "unit" "sse,mmx"))
243 ;; Set when 0f opcode prefix is used.
244 (define_attr "prefix_rex" ""
245 (cond [(and (eq_attr "mode" "DI")
246 (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
248 (and (eq_attr "mode" "QI")
249 (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
252 (ne (symbol_ref "x86_extended_reg_mentioned_p (insn)")
258 ;; Set when modrm byte is used.
259 (define_attr "modrm" ""
260 (cond [(eq_attr "type" "str,cld,leave")
262 (eq_attr "unit" "i387")
264 (and (eq_attr "type" "incdec")
265 (ior (match_operand:SI 1 "register_operand" "")
266 (match_operand:HI 1 "register_operand" "")))
268 (and (eq_attr "type" "push")
269 (not (match_operand 1 "memory_operand" "")))
271 (and (eq_attr "type" "pop")
272 (not (match_operand 0 "memory_operand" "")))
274 (and (eq_attr "type" "imov")
275 (and (match_operand 0 "register_operand" "")
276 (match_operand 1 "immediate_operand" "")))
278 (and (eq_attr "type" "call")
279 (match_operand 0 "constant_call_address_operand" ""))
281 (and (eq_attr "type" "callv")
282 (match_operand 1 "constant_call_address_operand" ""))
287 ;; The (bounding maximum) length of an instruction in bytes.
288 ;; ??? fistp is in fact fldcw/fistp/fldcw sequence. Later we may want
289 ;; to split it and compute proper length as for other insns.
290 (define_attr "length" ""
291 (cond [(eq_attr "type" "other,multi,fistp")
293 (eq_attr "type" "fcmp")
295 (eq_attr "unit" "i387")
297 (plus (attr "prefix_data16")
298 (attr "length_address")))]
299 (plus (plus (attr "modrm")
300 (plus (attr "prefix_0f")
301 (plus (attr "prefix_rex")
303 (plus (attr "prefix_rep")
304 (plus (attr "prefix_data16")
305 (plus (attr "length_immediate")
306 (attr "length_address")))))))
308 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
309 ;; `store' if there is a simple memory reference therein, or `unknown'
310 ;; if the instruction is complex.
312 (define_attr "memory" "none,load,store,both,unknown"
313 (cond [(eq_attr "type" "other,multi,str")
314 (const_string "unknown")
315 (eq_attr "type" "lea,fcmov,fpspc,cld")
316 (const_string "none")
317 (eq_attr "type" "fistp,leave")
318 (const_string "both")
319 (eq_attr "type" "push")
320 (if_then_else (match_operand 1 "memory_operand" "")
321 (const_string "both")
322 (const_string "store"))
323 (eq_attr "type" "pop")
324 (if_then_else (match_operand 0 "memory_operand" "")
325 (const_string "both")
326 (const_string "load"))
327 (eq_attr "type" "setcc")
328 (if_then_else (match_operand 0 "memory_operand" "")
329 (const_string "store")
330 (const_string "none"))
331 (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp")
332 (if_then_else (ior (match_operand 0 "memory_operand" "")
333 (match_operand 1 "memory_operand" ""))
334 (const_string "load")
335 (const_string "none"))
336 (eq_attr "type" "ibr")
337 (if_then_else (match_operand 0 "memory_operand" "")
338 (const_string "load")
339 (const_string "none"))
340 (eq_attr "type" "call")
341 (if_then_else (match_operand 0 "constant_call_address_operand" "")
342 (const_string "none")
343 (const_string "load"))
344 (eq_attr "type" "callv")
345 (if_then_else (match_operand 1 "constant_call_address_operand" "")
346 (const_string "none")
347 (const_string "load"))
348 (and (eq_attr "type" "alu1,negnot")
349 (match_operand 1 "memory_operand" ""))
350 (const_string "both")
351 (and (match_operand 0 "memory_operand" "")
352 (match_operand 1 "memory_operand" ""))
353 (const_string "both")
354 (match_operand 0 "memory_operand" "")
355 (const_string "store")
356 (match_operand 1 "memory_operand" "")
357 (const_string "load")
360 imov,imovx,icmp,test,
362 sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
363 mmx,mmxmov,mmxcmp,mmxcvt")
364 (match_operand 2 "memory_operand" ""))
365 (const_string "load")
366 (and (eq_attr "type" "icmov")
367 (match_operand 3 "memory_operand" ""))
368 (const_string "load")
370 (const_string "none")))
372 ;; Indicates if an instruction has both an immediate and a displacement.
374 (define_attr "imm_disp" "false,true,unknown"
375 (cond [(eq_attr "type" "other,multi")
376 (const_string "unknown")
377 (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1")
378 (and (match_operand 0 "memory_displacement_operand" "")
379 (match_operand 1 "immediate_operand" "")))
380 (const_string "true")
381 (and (eq_attr "type" "alu,ishift,rotate,imul,idiv")
382 (and (match_operand 0 "memory_displacement_operand" "")
383 (match_operand 2 "immediate_operand" "")))
384 (const_string "true")
386 (const_string "false")))
388 ;; Indicates if an FP operation has an integer source.
390 (define_attr "fp_int_src" "false,true"
391 (const_string "false"))
393 ;; Describe a user's asm statement.
394 (define_asm_attributes
395 [(set_attr "length" "128")
396 (set_attr "type" "multi")])
398 (include "pentium.md")
401 (include "athlon.md")
403 ;; Compare instructions.
405 ;; All compare insns have expanders that save the operands away without
406 ;; actually generating RTL. The bCOND or sCOND (emitted immediately
407 ;; after the cmp) will actually emit the cmpM.
409 (define_expand "cmpdi"
411 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
412 (match_operand:DI 1 "x86_64_general_operand" "")))]
415 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
416 operands[0] = force_reg (DImode, operands[0]);
417 ix86_compare_op0 = operands[0];
418 ix86_compare_op1 = operands[1];
422 (define_expand "cmpsi"
424 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
425 (match_operand:SI 1 "general_operand" "")))]
428 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
429 operands[0] = force_reg (SImode, operands[0]);
430 ix86_compare_op0 = operands[0];
431 ix86_compare_op1 = operands[1];
435 (define_expand "cmphi"
437 (compare:CC (match_operand:HI 0 "nonimmediate_operand" "")
438 (match_operand:HI 1 "general_operand" "")))]
441 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
442 operands[0] = force_reg (HImode, operands[0]);
443 ix86_compare_op0 = operands[0];
444 ix86_compare_op1 = operands[1];
448 (define_expand "cmpqi"
450 (compare:CC (match_operand:QI 0 "nonimmediate_operand" "")
451 (match_operand:QI 1 "general_operand" "")))]
454 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
455 operands[0] = force_reg (QImode, operands[0]);
456 ix86_compare_op0 = operands[0];
457 ix86_compare_op1 = operands[1];
461 (define_insn "cmpdi_ccno_1_rex64"
463 (compare (match_operand:DI 0 "nonimmediate_operand" "r,?mr")
464 (match_operand:DI 1 "const0_operand" "n,n")))]
465 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
467 test{q}\t{%0, %0|%0, %0}
468 cmp{q}\t{%1, %0|%0, %1}"
469 [(set_attr "type" "test,icmp")
470 (set_attr "length_immediate" "0,1")
471 (set_attr "mode" "DI")])
473 (define_insn "*cmpdi_minus_1_rex64"
475 (compare (minus:DI (match_operand:DI 0 "nonimmediate_operand" "rm,r")
476 (match_operand:DI 1 "x86_64_general_operand" "re,mr"))
478 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)"
479 "cmp{q}\t{%1, %0|%0, %1}"
480 [(set_attr "type" "icmp")
481 (set_attr "mode" "DI")])
483 (define_expand "cmpdi_1_rex64"
485 (compare:CC (match_operand:DI 0 "nonimmediate_operand" "")
486 (match_operand:DI 1 "general_operand" "")))]
490 (define_insn "cmpdi_1_insn_rex64"
492 (compare (match_operand:DI 0 "nonimmediate_operand" "mr,r")
493 (match_operand:DI 1 "x86_64_general_operand" "re,mr")))]
494 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
495 "cmp{q}\t{%1, %0|%0, %1}"
496 [(set_attr "type" "icmp")
497 (set_attr "mode" "DI")])
500 (define_insn "*cmpsi_ccno_1"
502 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
503 (match_operand:SI 1 "const0_operand" "n,n")))]
504 "ix86_match_ccmode (insn, CCNOmode)"
506 test{l}\t{%0, %0|%0, %0}
507 cmp{l}\t{%1, %0|%0, %1}"
508 [(set_attr "type" "test,icmp")
509 (set_attr "length_immediate" "0,1")
510 (set_attr "mode" "SI")])
512 (define_insn "*cmpsi_minus_1"
514 (compare (minus:SI (match_operand:SI 0 "nonimmediate_operand" "rm,r")
515 (match_operand:SI 1 "general_operand" "ri,mr"))
517 "ix86_match_ccmode (insn, CCGOCmode)"
518 "cmp{l}\t{%1, %0|%0, %1}"
519 [(set_attr "type" "icmp")
520 (set_attr "mode" "SI")])
522 (define_expand "cmpsi_1"
524 (compare:CC (match_operand:SI 0 "nonimmediate_operand" "rm,r")
525 (match_operand:SI 1 "general_operand" "ri,mr")))]
529 (define_insn "*cmpsi_1_insn"
531 (compare (match_operand:SI 0 "nonimmediate_operand" "rm,r")
532 (match_operand:SI 1 "general_operand" "ri,mr")))]
533 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
534 && ix86_match_ccmode (insn, CCmode)"
535 "cmp{l}\t{%1, %0|%0, %1}"
536 [(set_attr "type" "icmp")
537 (set_attr "mode" "SI")])
539 (define_insn "*cmphi_ccno_1"
541 (compare (match_operand:HI 0 "nonimmediate_operand" "r,?mr")
542 (match_operand:HI 1 "const0_operand" "n,n")))]
543 "ix86_match_ccmode (insn, CCNOmode)"
545 test{w}\t{%0, %0|%0, %0}
546 cmp{w}\t{%1, %0|%0, %1}"
547 [(set_attr "type" "test,icmp")
548 (set_attr "length_immediate" "0,1")
549 (set_attr "mode" "HI")])
551 (define_insn "*cmphi_minus_1"
553 (compare (minus:HI (match_operand:HI 0 "nonimmediate_operand" "rm,r")
554 (match_operand:HI 1 "general_operand" "ri,mr"))
556 "ix86_match_ccmode (insn, CCGOCmode)"
557 "cmp{w}\t{%1, %0|%0, %1}"
558 [(set_attr "type" "icmp")
559 (set_attr "mode" "HI")])
561 (define_insn "*cmphi_1"
563 (compare (match_operand:HI 0 "nonimmediate_operand" "rm,r")
564 (match_operand:HI 1 "general_operand" "ri,mr")))]
565 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
566 && ix86_match_ccmode (insn, CCmode)"
567 "cmp{w}\t{%1, %0|%0, %1}"
568 [(set_attr "type" "icmp")
569 (set_attr "mode" "HI")])
571 (define_insn "*cmpqi_ccno_1"
573 (compare (match_operand:QI 0 "nonimmediate_operand" "q,?mq")
574 (match_operand:QI 1 "const0_operand" "n,n")))]
575 "ix86_match_ccmode (insn, CCNOmode)"
577 test{b}\t{%0, %0|%0, %0}
578 cmp{b}\t{$0, %0|%0, 0}"
579 [(set_attr "type" "test,icmp")
580 (set_attr "length_immediate" "0,1")
581 (set_attr "mode" "QI")])
583 (define_insn "*cmpqi_1"
585 (compare (match_operand:QI 0 "nonimmediate_operand" "qm,q")
586 (match_operand:QI 1 "general_operand" "qi,mq")))]
587 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
588 && ix86_match_ccmode (insn, CCmode)"
589 "cmp{b}\t{%1, %0|%0, %1}"
590 [(set_attr "type" "icmp")
591 (set_attr "mode" "QI")])
593 (define_insn "*cmpqi_minus_1"
595 (compare (minus:QI (match_operand:QI 0 "nonimmediate_operand" "qm,q")
596 (match_operand:QI 1 "general_operand" "qi,mq"))
598 "ix86_match_ccmode (insn, CCGOCmode)"
599 "cmp{b}\t{%1, %0|%0, %1}"
600 [(set_attr "type" "icmp")
601 (set_attr "mode" "QI")])
603 (define_insn "*cmpqi_ext_1"
606 (match_operand:QI 0 "general_operand" "Qm")
609 (match_operand 1 "ext_register_operand" "Q")
612 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
613 "cmp{b}\t{%h1, %0|%0, %h1}"
614 [(set_attr "type" "icmp")
615 (set_attr "mode" "QI")])
617 (define_insn "*cmpqi_ext_1_rex64"
620 (match_operand:QI 0 "register_operand" "Q")
623 (match_operand 1 "ext_register_operand" "Q")
626 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
627 "cmp{b}\t{%h1, %0|%0, %h1}"
628 [(set_attr "type" "icmp")
629 (set_attr "mode" "QI")])
631 (define_insn "*cmpqi_ext_2"
636 (match_operand 0 "ext_register_operand" "Q")
639 (match_operand:QI 1 "const0_operand" "n")))]
640 "ix86_match_ccmode (insn, CCNOmode)"
642 [(set_attr "type" "test")
643 (set_attr "length_immediate" "0")
644 (set_attr "mode" "QI")])
646 (define_expand "cmpqi_ext_3"
651 (match_operand 0 "ext_register_operand" "")
654 (match_operand:QI 1 "general_operand" "")))]
658 (define_insn "cmpqi_ext_3_insn"
663 (match_operand 0 "ext_register_operand" "Q")
666 (match_operand:QI 1 "general_operand" "Qmn")))]
667 "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
668 "cmp{b}\t{%1, %h0|%h0, %1}"
669 [(set_attr "type" "icmp")
670 (set_attr "mode" "QI")])
672 (define_insn "cmpqi_ext_3_insn_rex64"
677 (match_operand 0 "ext_register_operand" "Q")
680 (match_operand:QI 1 "nonmemory_operand" "Qn")))]
681 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
682 "cmp{b}\t{%1, %h0|%h0, %1}"
683 [(set_attr "type" "icmp")
684 (set_attr "mode" "QI")])
686 (define_insn "*cmpqi_ext_4"
691 (match_operand 0 "ext_register_operand" "Q")
696 (match_operand 1 "ext_register_operand" "Q")
699 "ix86_match_ccmode (insn, CCmode)"
700 "cmp{b}\t{%h1, %h0|%h0, %h1}"
701 [(set_attr "type" "icmp")
702 (set_attr "mode" "QI")])
704 ;; These implement float point compares.
705 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
706 ;; which would allow mix and match FP modes on the compares. Which is what
707 ;; the old patterns did, but with many more of them.
709 (define_expand "cmpxf"
711 (compare:CC (match_operand:XF 0 "cmp_fp_expander_operand" "")
712 (match_operand:XF 1 "cmp_fp_expander_operand" "")))]
713 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
715 ix86_compare_op0 = operands[0];
716 ix86_compare_op1 = operands[1];
720 (define_expand "cmptf"
722 (compare:CC (match_operand:TF 0 "cmp_fp_expander_operand" "")
723 (match_operand:TF 1 "cmp_fp_expander_operand" "")))]
726 ix86_compare_op0 = operands[0];
727 ix86_compare_op1 = operands[1];
731 (define_expand "cmpdf"
733 (compare:CC (match_operand:DF 0 "cmp_fp_expander_operand" "")
734 (match_operand:DF 1 "cmp_fp_expander_operand" "")))]
735 "TARGET_80387 || TARGET_SSE2"
737 ix86_compare_op0 = operands[0];
738 ix86_compare_op1 = operands[1];
742 (define_expand "cmpsf"
744 (compare:CC (match_operand:SF 0 "cmp_fp_expander_operand" "")
745 (match_operand:SF 1 "cmp_fp_expander_operand" "")))]
746 "TARGET_80387 || TARGET_SSE"
748 ix86_compare_op0 = operands[0];
749 ix86_compare_op1 = operands[1];
753 ;; FP compares, step 1:
754 ;; Set the FP condition codes.
756 ;; CCFPmode compare with exceptions
757 ;; CCFPUmode compare with no exceptions
759 ;; %%% It is an unfortunate fact that ftst has no non-popping variant,
760 ;; and that fp moves clobber the condition codes, and that there is
761 ;; currently no way to describe this fact to reg-stack. So there are
762 ;; no splitters yet for this.
764 ;; %%% YIKES! This scheme does not retain a strong connection between
765 ;; the real compare and the ultimate cc0 user, so CC_REVERSE does not
766 ;; work! Only allow tos/mem with tos in op 0.
768 ;; Hmm, of course, this is what the actual _hardware_ does. Perhaps
769 ;; things aren't as bad as they sound...
771 (define_insn "*cmpfp_0"
772 [(set (match_operand:HI 0 "register_operand" "=a")
774 [(compare:CCFP (match_operand 1 "register_operand" "f")
775 (match_operand 2 "const0_operand" "X"))]
778 && FLOAT_MODE_P (GET_MODE (operands[1]))
779 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
781 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
782 return "ftst\;fnstsw\t%0\;fstp\t%y0";
784 return "ftst\;fnstsw\t%0";
786 [(set_attr "type" "multi")
788 (cond [(match_operand:SF 1 "" "")
790 (match_operand:DF 1 "" "")
793 (const_string "XF")))])
795 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
796 ;; used to manage the reg stack popping would not be preserved.
798 (define_insn "*cmpfp_2_sf"
801 (match_operand:SF 0 "register_operand" "f")
802 (match_operand:SF 1 "nonimmediate_operand" "fm")))]
804 "* return output_fp_compare (insn, operands, 0, 0);"
805 [(set_attr "type" "fcmp")
806 (set_attr "mode" "SF")])
808 (define_insn "*cmpfp_2_sf_1"
809 [(set (match_operand:HI 0 "register_operand" "=a")
812 (match_operand:SF 1 "register_operand" "f")
813 (match_operand:SF 2 "nonimmediate_operand" "fm"))]
816 "* return output_fp_compare (insn, operands, 2, 0);"
817 [(set_attr "type" "fcmp")
818 (set_attr "mode" "SF")])
820 (define_insn "*cmpfp_2_df"
823 (match_operand:DF 0 "register_operand" "f")
824 (match_operand:DF 1 "nonimmediate_operand" "fm")))]
826 "* return output_fp_compare (insn, operands, 0, 0);"
827 [(set_attr "type" "fcmp")
828 (set_attr "mode" "DF")])
830 (define_insn "*cmpfp_2_df_1"
831 [(set (match_operand:HI 0 "register_operand" "=a")
834 (match_operand:DF 1 "register_operand" "f")
835 (match_operand:DF 2 "nonimmediate_operand" "fm"))]
838 "* return output_fp_compare (insn, operands, 2, 0);"
839 [(set_attr "type" "multi")
840 (set_attr "mode" "DF")])
842 (define_insn "*cmpfp_2_xf"
845 (match_operand:XF 0 "register_operand" "f")
846 (match_operand:XF 1 "register_operand" "f")))]
847 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
848 "* return output_fp_compare (insn, operands, 0, 0);"
849 [(set_attr "type" "fcmp")
850 (set_attr "mode" "XF")])
852 (define_insn "*cmpfp_2_tf"
855 (match_operand:TF 0 "register_operand" "f")
856 (match_operand:TF 1 "register_operand" "f")))]
858 "* return output_fp_compare (insn, operands, 0, 0);"
859 [(set_attr "type" "fcmp")
860 (set_attr "mode" "XF")])
862 (define_insn "*cmpfp_2_xf_1"
863 [(set (match_operand:HI 0 "register_operand" "=a")
866 (match_operand:XF 1 "register_operand" "f")
867 (match_operand:XF 2 "register_operand" "f"))]
869 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
870 "* return output_fp_compare (insn, operands, 2, 0);"
871 [(set_attr "type" "multi")
872 (set_attr "mode" "XF")])
874 (define_insn "*cmpfp_2_tf_1"
875 [(set (match_operand:HI 0 "register_operand" "=a")
878 (match_operand:TF 1 "register_operand" "f")
879 (match_operand:TF 2 "register_operand" "f"))]
882 "* return output_fp_compare (insn, operands, 2, 0);"
883 [(set_attr "type" "multi")
884 (set_attr "mode" "XF")])
886 (define_insn "*cmpfp_2u"
889 (match_operand 0 "register_operand" "f")
890 (match_operand 1 "register_operand" "f")))]
892 && FLOAT_MODE_P (GET_MODE (operands[0]))
893 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
894 "* return output_fp_compare (insn, operands, 0, 1);"
895 [(set_attr "type" "fcmp")
897 (cond [(match_operand:SF 1 "" "")
899 (match_operand:DF 1 "" "")
902 (const_string "XF")))])
904 (define_insn "*cmpfp_2u_1"
905 [(set (match_operand:HI 0 "register_operand" "=a")
908 (match_operand 1 "register_operand" "f")
909 (match_operand 2 "register_operand" "f"))]
912 && FLOAT_MODE_P (GET_MODE (operands[1]))
913 && GET_MODE (operands[1]) == GET_MODE (operands[2])"
914 "* return output_fp_compare (insn, operands, 2, 1);"
915 [(set_attr "type" "multi")
917 (cond [(match_operand:SF 1 "" "")
919 (match_operand:DF 1 "" "")
922 (const_string "XF")))])
924 ;; Patterns to match the SImode-in-memory ficom instructions.
926 ;; %%% Play games with accepting gp registers, as otherwise we have to
927 ;; force them to memory during rtl generation, which is no good. We
928 ;; can get rid of this once we teach reload to do memory input reloads
931 (define_insn "*ficom_1"
934 (match_operand 0 "register_operand" "f,f")
935 (float (match_operand:SI 1 "nonimmediate_operand" "m,?r"))))]
936 "0 && TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[0]))
937 && GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 1)) == GET_MODE (operands[0])"
940 ;; Split the not-really-implemented gp register case into a
941 ;; push-op-pop sequence.
943 ;; %%% This is most efficient, but am I gonna get in trouble
944 ;; for separating cc0_setter and cc0_user?
949 (match_operand:SF 0 "register_operand" "")
950 (float (match_operand:SI 1 "register_operand" ""))))]
951 "0 && TARGET_80387 && reload_completed"
952 [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 1))
953 (set (reg:CCFP 18) (compare:CCFP (match_dup 0) (match_dup 2)))
954 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
955 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
956 "operands[2] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
957 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);")
959 ;; FP compares, step 2
960 ;; Move the fpsw to ax.
962 (define_insn "*x86_fnstsw_1"
963 [(set (match_operand:HI 0 "register_operand" "=a")
964 (unspec:HI [(reg 18)] UNSPEC_FNSTSW))]
967 [(set_attr "length" "2")
968 (set_attr "mode" "SI")
969 (set_attr "unit" "i387")
970 (set_attr "ppro_uops" "few")])
972 ;; FP compares, step 3
973 ;; Get ax into flags, general case.
975 (define_insn "x86_sahf_1"
977 (unspec:CC [(match_operand:HI 0 "register_operand" "a")] UNSPEC_SAHF))]
980 [(set_attr "length" "1")
981 (set_attr "athlon_decode" "vector")
982 (set_attr "mode" "SI")
983 (set_attr "ppro_uops" "one")])
985 ;; Pentium Pro can do steps 1 through 3 in one go.
987 (define_insn "*cmpfp_i"
989 (compare:CCFP (match_operand 0 "register_operand" "f")
990 (match_operand 1 "register_operand" "f")))]
991 "TARGET_80387 && TARGET_CMOVE
992 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
993 && FLOAT_MODE_P (GET_MODE (operands[0]))
994 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
995 "* return output_fp_compare (insn, operands, 1, 0);"
996 [(set_attr "type" "fcmp")
998 (cond [(match_operand:SF 1 "" "")
1000 (match_operand:DF 1 "" "")
1003 (const_string "XF")))
1004 (set_attr "athlon_decode" "vector")])
1006 (define_insn "*cmpfp_i_sse"
1008 (compare:CCFP (match_operand 0 "register_operand" "f#x,x#f")
1009 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1011 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1012 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1013 "* return output_fp_compare (insn, operands, 1, 0);"
1014 [(set_attr "type" "fcmp,ssecomi")
1016 (if_then_else (match_operand:SF 1 "" "")
1018 (const_string "DF")))
1019 (set_attr "athlon_decode" "vector")])
1021 (define_insn "*cmpfp_i_sse_only"
1023 (compare:CCFP (match_operand 0 "register_operand" "x")
1024 (match_operand 1 "nonimmediate_operand" "xm")))]
1025 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1026 && GET_MODE (operands[0]) == GET_MODE (operands[0])"
1027 "* return output_fp_compare (insn, operands, 1, 0);"
1028 [(set_attr "type" "ssecomi")
1030 (if_then_else (match_operand:SF 1 "" "")
1032 (const_string "DF")))
1033 (set_attr "athlon_decode" "vector")])
1035 (define_insn "*cmpfp_iu"
1036 [(set (reg:CCFPU 17)
1037 (compare:CCFPU (match_operand 0 "register_operand" "f")
1038 (match_operand 1 "register_operand" "f")))]
1039 "TARGET_80387 && TARGET_CMOVE
1040 && !SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1041 && FLOAT_MODE_P (GET_MODE (operands[0]))
1042 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1043 "* return output_fp_compare (insn, operands, 1, 1);"
1044 [(set_attr "type" "fcmp")
1046 (cond [(match_operand:SF 1 "" "")
1048 (match_operand:DF 1 "" "")
1051 (const_string "XF")))
1052 (set_attr "athlon_decode" "vector")])
1054 (define_insn "*cmpfp_iu_sse"
1055 [(set (reg:CCFPU 17)
1056 (compare:CCFPU (match_operand 0 "register_operand" "f#x,x#f")
1057 (match_operand 1 "nonimmediate_operand" "f#x,xm#f")))]
1059 && SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1060 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1061 "* return output_fp_compare (insn, operands, 1, 1);"
1062 [(set_attr "type" "fcmp,ssecomi")
1064 (if_then_else (match_operand:SF 1 "" "")
1066 (const_string "DF")))
1067 (set_attr "athlon_decode" "vector")])
1069 (define_insn "*cmpfp_iu_sse_only"
1070 [(set (reg:CCFPU 17)
1071 (compare:CCFPU (match_operand 0 "register_operand" "x")
1072 (match_operand 1 "nonimmediate_operand" "xm")))]
1073 "SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
1074 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
1075 "* return output_fp_compare (insn, operands, 1, 1);"
1076 [(set_attr "type" "ssecomi")
1078 (if_then_else (match_operand:SF 1 "" "")
1080 (const_string "DF")))
1081 (set_attr "athlon_decode" "vector")])
1083 ;; Move instructions.
1085 ;; General case of fullword move.
1087 (define_expand "movsi"
1088 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1089 (match_operand:SI 1 "general_operand" ""))]
1091 "ix86_expand_move (SImode, operands); DONE;")
1093 ;; Push/pop instructions. They are separate since autoinc/dec is not a
1096 ;; %%% We don't use a post-inc memory reference because x86 is not a
1097 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
1098 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
1099 ;; targets without our curiosities, and it is just as easy to represent
1100 ;; this differently.
1102 (define_insn "*pushsi2"
1103 [(set (match_operand:SI 0 "push_operand" "=<")
1104 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
1107 [(set_attr "type" "push")
1108 (set_attr "mode" "SI")])
1110 ;; For 64BIT abi we always round up to 8 bytes.
1111 (define_insn "*pushsi2_rex64"
1112 [(set (match_operand:SI 0 "push_operand" "=X")
1113 (match_operand:SI 1 "nonmemory_no_elim_operand" "ri"))]
1116 [(set_attr "type" "push")
1117 (set_attr "mode" "SI")])
1119 (define_insn "*pushsi2_prologue"
1120 [(set (match_operand:SI 0 "push_operand" "=<")
1121 (match_operand:SI 1 "general_no_elim_operand" "ri*m"))
1122 (clobber (mem:BLK (scratch)))]
1125 [(set_attr "type" "push")
1126 (set_attr "mode" "SI")])
1128 (define_insn "*popsi1_epilogue"
1129 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1130 (mem:SI (reg:SI 7)))
1132 (plus:SI (reg:SI 7) (const_int 4)))
1133 (clobber (mem:BLK (scratch)))]
1136 [(set_attr "type" "pop")
1137 (set_attr "mode" "SI")])
1139 (define_insn "popsi1"
1140 [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
1141 (mem:SI (reg:SI 7)))
1143 (plus:SI (reg:SI 7) (const_int 4)))]
1146 [(set_attr "type" "pop")
1147 (set_attr "mode" "SI")])
1149 (define_insn "*movsi_xor"
1150 [(set (match_operand:SI 0 "register_operand" "=r")
1151 (match_operand:SI 1 "const0_operand" "i"))
1152 (clobber (reg:CC 17))]
1153 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1154 "xor{l}\t{%0, %0|%0, %0}"
1155 [(set_attr "type" "alu1")
1156 (set_attr "mode" "SI")
1157 (set_attr "length_immediate" "0")])
1159 (define_insn "*movsi_or"
1160 [(set (match_operand:SI 0 "register_operand" "=r")
1161 (match_operand:SI 1 "immediate_operand" "i"))
1162 (clobber (reg:CC 17))]
1163 "reload_completed && GET_CODE (operands[1]) == CONST_INT
1164 && INTVAL (operands[1]) == -1
1165 && (TARGET_PENTIUM || optimize_size)"
1167 operands[1] = constm1_rtx;
1168 return "or{l}\t{%1, %0|%0, %1}";
1170 [(set_attr "type" "alu1")
1171 (set_attr "mode" "SI")
1172 (set_attr "length_immediate" "1")])
1174 (define_insn "*movsi_1"
1175 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!rm,!*y,!*Y,!rm,!*Y")
1176 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,rm,*Y,*Y,rm"))]
1177 "(TARGET_INTER_UNIT_MOVES || optimize_size)
1178 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1180 switch (get_attr_type (insn))
1183 if (get_attr_mode (insn) == MODE_TI)
1184 return "movdqa\t{%1, %0|%0, %1}";
1185 return "movd\t{%1, %0|%0, %1}";
1188 if (get_attr_mode (insn) == MODE_DI)
1189 return "movq\t{%1, %0|%0, %1}";
1190 return "movd\t{%1, %0|%0, %1}";
1193 return "lea{l}\t{%1, %0|%0, %1}";
1196 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1198 return "mov{l}\t{%1, %0|%0, %1}";
1202 (cond [(eq_attr "alternative" "2,3,4")
1203 (const_string "mmxmov")
1204 (eq_attr "alternative" "5,6,7")
1205 (const_string "ssemov")
1206 (and (ne (symbol_ref "flag_pic") (const_int 0))
1207 (match_operand:SI 1 "symbolic_operand" ""))
1208 (const_string "lea")
1210 (const_string "imov")))
1211 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1213 (define_insn "*movsi_1_nointernunit"
1214 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m,!*y,!m,!*y,!*Y,!m,!*Y")
1215 (match_operand:SI 1 "general_operand" "rinm,rin,*y,*y,m,*Y,*Y,m"))]
1216 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
1217 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1219 switch (get_attr_type (insn))
1222 if (get_attr_mode (insn) == MODE_TI)
1223 return "movdqa\t{%1, %0|%0, %1}";
1224 return "movd\t{%1, %0|%0, %1}";
1227 if (get_attr_mode (insn) == MODE_DI)
1228 return "movq\t{%1, %0|%0, %1}";
1229 return "movd\t{%1, %0|%0, %1}";
1232 return "lea{l}\t{%1, %0|%0, %1}";
1235 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
1237 return "mov{l}\t{%1, %0|%0, %1}";
1241 (cond [(eq_attr "alternative" "2,3,4")
1242 (const_string "mmxmov")
1243 (eq_attr "alternative" "5,6,7")
1244 (const_string "ssemov")
1245 (and (ne (symbol_ref "flag_pic") (const_int 0))
1246 (match_operand:SI 1 "symbolic_operand" ""))
1247 (const_string "lea")
1249 (const_string "imov")))
1250 (set_attr "mode" "SI,SI,DI,SI,SI,TI,SI,SI")])
1252 ;; Stores and loads of ax to arbitrary constant address.
1253 ;; We fake an second form of instruction to force reload to load address
1254 ;; into register when rax is not available
1255 (define_insn "*movabssi_1_rex64"
1256 [(set (mem:SI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1257 (match_operand:SI 1 "nonmemory_operand" "a,er,i"))]
1260 movabs{l}\t{%1, %P0|%P0, %1}
1261 mov{l}\t{%1, %a0|%a0, %1}
1262 movabs{l}\t{%1, %a0|%a0, %1}"
1263 [(set_attr "type" "imov")
1264 (set_attr "modrm" "0,*,*")
1265 (set_attr "length_address" "8,0,0")
1266 (set_attr "length_immediate" "0,*,*")
1267 (set_attr "memory" "store")
1268 (set_attr "mode" "SI")])
1270 (define_insn "*movabssi_2_rex64"
1271 [(set (match_operand:SI 0 "register_operand" "=a,r")
1272 (mem:SI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1275 movabs{l}\t{%P1, %0|%0, %P1}
1276 mov{l}\t{%a1, %0|%0, %a1}"
1277 [(set_attr "type" "imov")
1278 (set_attr "modrm" "0,*")
1279 (set_attr "length_address" "8,0")
1280 (set_attr "length_immediate" "0")
1281 (set_attr "memory" "load")
1282 (set_attr "mode" "SI")])
1284 (define_insn "*swapsi"
1285 [(set (match_operand:SI 0 "register_operand" "+r")
1286 (match_operand:SI 1 "register_operand" "+r"))
1291 [(set_attr "type" "imov")
1292 (set_attr "pent_pair" "np")
1293 (set_attr "athlon_decode" "vector")
1294 (set_attr "mode" "SI")
1295 (set_attr "modrm" "0")
1296 (set_attr "ppro_uops" "few")])
1298 (define_expand "movhi"
1299 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1300 (match_operand:HI 1 "general_operand" ""))]
1302 "ix86_expand_move (HImode, operands); DONE;")
1304 (define_insn "*pushhi2"
1305 [(set (match_operand:HI 0 "push_operand" "=<,<")
1306 (match_operand:HI 1 "general_no_elim_operand" "n,r*m"))]
1309 push{w}\t{|WORD PTR }%1
1311 [(set_attr "type" "push")
1312 (set_attr "mode" "HI")])
1314 ;; For 64BIT abi we always round up to 8 bytes.
1315 (define_insn "*pushhi2_rex64"
1316 [(set (match_operand:HI 0 "push_operand" "=X")
1317 (match_operand:HI 1 "nonmemory_no_elim_operand" "ri"))]
1320 [(set_attr "type" "push")
1321 (set_attr "mode" "QI")])
1323 (define_insn "*movhi_1"
1324 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
1325 (match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
1326 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1328 switch (get_attr_type (insn))
1331 /* movzwl is faster than movw on p2 due to partial word stalls,
1332 though not as fast as an aligned movl. */
1333 return "movz{wl|x}\t{%1, %k0|%k0, %1}";
1335 if (get_attr_mode (insn) == MODE_SI)
1336 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1338 return "mov{w}\t{%1, %0|%0, %1}";
1342 (cond [(and (eq_attr "alternative" "0")
1343 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1345 (eq (symbol_ref "TARGET_HIMODE_MATH")
1347 (const_string "imov")
1348 (and (eq_attr "alternative" "1,2")
1349 (match_operand:HI 1 "aligned_operand" ""))
1350 (const_string "imov")
1351 (and (ne (symbol_ref "TARGET_MOVX")
1353 (eq_attr "alternative" "0,2"))
1354 (const_string "imovx")
1356 (const_string "imov")))
1358 (cond [(eq_attr "type" "imovx")
1360 (and (eq_attr "alternative" "1,2")
1361 (match_operand:HI 1 "aligned_operand" ""))
1363 (and (eq_attr "alternative" "0")
1364 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1366 (eq (symbol_ref "TARGET_HIMODE_MATH")
1370 (const_string "HI")))])
1372 ;; Stores and loads of ax to arbitrary constant address.
1373 ;; We fake an second form of instruction to force reload to load address
1374 ;; into register when rax is not available
1375 (define_insn "*movabshi_1_rex64"
1376 [(set (mem:HI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1377 (match_operand:HI 1 "nonmemory_operand" "a,er,i"))]
1380 movabs{w}\t{%1, %P0|%P0, %1}
1381 mov{w}\t{%1, %a0|%a0, %1}
1382 movabs{w}\t{%1, %a0|%a0, %1}"
1383 [(set_attr "type" "imov")
1384 (set_attr "modrm" "0,*,*")
1385 (set_attr "length_address" "8,0,0")
1386 (set_attr "length_immediate" "0,*,*")
1387 (set_attr "memory" "store")
1388 (set_attr "mode" "HI")])
1390 (define_insn "*movabshi_2_rex64"
1391 [(set (match_operand:HI 0 "register_operand" "=a,r")
1392 (mem:HI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1395 movabs{w}\t{%P1, %0|%0, %P1}
1396 mov{w}\t{%a1, %0|%0, %a1}"
1397 [(set_attr "type" "imov")
1398 (set_attr "modrm" "0,*")
1399 (set_attr "length_address" "8,0")
1400 (set_attr "length_immediate" "0")
1401 (set_attr "memory" "load")
1402 (set_attr "mode" "HI")])
1404 (define_insn "*swaphi_1"
1405 [(set (match_operand:HI 0 "register_operand" "+r")
1406 (match_operand:HI 1 "register_operand" "+r"))
1409 "TARGET_PARTIAL_REG_STALL"
1411 [(set_attr "type" "imov")
1412 (set_attr "pent_pair" "np")
1413 (set_attr "mode" "HI")
1414 (set_attr "modrm" "0")
1415 (set_attr "ppro_uops" "few")])
1417 (define_insn "*swaphi_2"
1418 [(set (match_operand:HI 0 "register_operand" "+r")
1419 (match_operand:HI 1 "register_operand" "+r"))
1422 "! TARGET_PARTIAL_REG_STALL"
1424 [(set_attr "type" "imov")
1425 (set_attr "pent_pair" "np")
1426 (set_attr "mode" "SI")
1427 (set_attr "modrm" "0")
1428 (set_attr "ppro_uops" "few")])
1430 (define_expand "movstricthi"
1431 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1432 (match_operand:HI 1 "general_operand" ""))]
1433 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1435 /* Don't generate memory->memory moves, go through a register */
1436 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1437 operands[1] = force_reg (HImode, operands[1]);
1440 (define_insn "*movstricthi_1"
1441 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
1442 (match_operand:HI 1 "general_operand" "rn,m"))]
1443 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1444 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1445 "mov{w}\t{%1, %0|%0, %1}"
1446 [(set_attr "type" "imov")
1447 (set_attr "mode" "HI")])
1449 (define_insn "*movstricthi_xor"
1450 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
1451 (match_operand:HI 1 "const0_operand" "i"))
1452 (clobber (reg:CC 17))]
1454 && ((!TARGET_USE_MOV0 && !TARGET_PARTIAL_REG_STALL) || optimize_size)"
1455 "xor{w}\t{%0, %0|%0, %0}"
1456 [(set_attr "type" "alu1")
1457 (set_attr "mode" "HI")
1458 (set_attr "length_immediate" "0")])
1460 (define_expand "movqi"
1461 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1462 (match_operand:QI 1 "general_operand" ""))]
1464 "ix86_expand_move (QImode, operands); DONE;")
1466 ;; emit_push_insn when it calls move_by_pieces requires an insn to
1467 ;; "push a byte". But actually we use pushw, which has the effect
1468 ;; of rounding the amount pushed up to a halfword.
1470 (define_insn "*pushqi2"
1471 [(set (match_operand:QI 0 "push_operand" "=X,X")
1472 (match_operand:QI 1 "nonmemory_no_elim_operand" "n,r"))]
1475 push{w}\t{|word ptr }%1
1477 [(set_attr "type" "push")
1478 (set_attr "mode" "HI")])
1480 ;; For 64BIT abi we always round up to 8 bytes.
1481 (define_insn "*pushqi2_rex64"
1482 [(set (match_operand:QI 0 "push_operand" "=X")
1483 (match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
1486 [(set_attr "type" "push")
1487 (set_attr "mode" "QI")])
1489 ;; Situation is quite tricky about when to choose full sized (SImode) move
1490 ;; over QImode moves. For Q_REG -> Q_REG move we use full size only for
1491 ;; partial register dependency machines (such as AMD Athlon), where QImode
1492 ;; moves issue extra dependency and for partial register stalls machines
1493 ;; that don't use QImode patterns (and QImode move cause stall on the next
1496 ;; For loads of Q_REG to NONQ_REG we use full sized moves except for partial
1497 ;; register stall machines with, where we use QImode instructions, since
1498 ;; partial register stall can be caused there. Then we use movzx.
1499 (define_insn "*movqi_1"
1500 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
1501 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn"))]
1502 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1504 switch (get_attr_type (insn))
1507 if (!ANY_QI_REG_P (operands[1]) && GET_CODE (operands[1]) != MEM)
1509 return "movz{bl|x}\t{%1, %k0|%k0, %1}";
1511 if (get_attr_mode (insn) == MODE_SI)
1512 return "mov{l}\t{%k1, %k0|%k0, %k1}";
1514 return "mov{b}\t{%1, %0|%0, %1}";
1518 (cond [(and (eq_attr "alternative" "3")
1519 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
1521 (eq (symbol_ref "TARGET_QIMODE_MATH")
1523 (const_string "imov")
1524 (eq_attr "alternative" "3,5")
1525 (const_string "imovx")
1526 (and (ne (symbol_ref "TARGET_MOVX")
1528 (eq_attr "alternative" "2"))
1529 (const_string "imovx")
1531 (const_string "imov")))
1533 (cond [(eq_attr "alternative" "3,4,5")
1535 (eq_attr "alternative" "6")
1537 (eq_attr "type" "imovx")
1539 (and (eq_attr "type" "imov")
1540 (and (eq_attr "alternative" "0,1,2")
1541 (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
1544 ;; Avoid partial register stalls when not using QImode arithmetic
1545 (and (eq_attr "type" "imov")
1546 (and (eq_attr "alternative" "0,1,2")
1547 (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
1549 (eq (symbol_ref "TARGET_QIMODE_MATH")
1553 (const_string "QI")))])
1555 (define_expand "reload_outqi"
1556 [(parallel [(match_operand:QI 0 "" "=m")
1557 (match_operand:QI 1 "register_operand" "r")
1558 (match_operand:QI 2 "register_operand" "=&q")])]
1562 op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
1564 if (reg_overlap_mentioned_p (op2, op0))
1566 if (! q_regs_operand (op1, QImode))
1568 emit_insn (gen_movqi (op2, op1));
1571 emit_insn (gen_movqi (op0, op1));
1575 (define_insn "*swapqi"
1576 [(set (match_operand:QI 0 "register_operand" "+r")
1577 (match_operand:QI 1 "register_operand" "+r"))
1582 [(set_attr "type" "imov")
1583 (set_attr "pent_pair" "np")
1584 (set_attr "mode" "QI")
1585 (set_attr "modrm" "0")
1586 (set_attr "ppro_uops" "few")])
1588 (define_expand "movstrictqi"
1589 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1590 (match_operand:QI 1 "general_operand" ""))]
1591 "! TARGET_PARTIAL_REG_STALL || optimize_size"
1593 /* Don't generate memory->memory moves, go through a register. */
1594 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
1595 operands[1] = force_reg (QImode, operands[1]);
1598 (define_insn "*movstrictqi_1"
1599 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
1600 (match_operand:QI 1 "general_operand" "*qn,m"))]
1601 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
1602 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1603 "mov{b}\t{%1, %0|%0, %1}"
1604 [(set_attr "type" "imov")
1605 (set_attr "mode" "QI")])
1607 (define_insn "*movstrictqi_xor"
1608 [(set (strict_low_part (match_operand:QI 0 "q_regs_operand" "+q"))
1609 (match_operand:QI 1 "const0_operand" "i"))
1610 (clobber (reg:CC 17))]
1611 "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
1612 "xor{b}\t{%0, %0|%0, %0}"
1613 [(set_attr "type" "alu1")
1614 (set_attr "mode" "QI")
1615 (set_attr "length_immediate" "0")])
1617 (define_insn "*movsi_extv_1"
1618 [(set (match_operand:SI 0 "register_operand" "=R")
1619 (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
1623 "movs{bl|x}\t{%h1, %0|%0, %h1}"
1624 [(set_attr "type" "imovx")
1625 (set_attr "mode" "SI")])
1627 (define_insn "*movhi_extv_1"
1628 [(set (match_operand:HI 0 "register_operand" "=R")
1629 (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
1633 "movs{bl|x}\t{%h1, %k0|%k0, %h1}"
1634 [(set_attr "type" "imovx")
1635 (set_attr "mode" "SI")])
1637 (define_insn "*movqi_extv_1"
1638 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
1639 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1644 switch (get_attr_type (insn))
1647 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1649 return "mov{b}\t{%h1, %0|%0, %h1}";
1653 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1654 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1655 (ne (symbol_ref "TARGET_MOVX")
1657 (const_string "imovx")
1658 (const_string "imov")))
1660 (if_then_else (eq_attr "type" "imovx")
1662 (const_string "QI")))])
1664 (define_insn "*movqi_extv_1_rex64"
1665 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1666 (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
1671 switch (get_attr_type (insn))
1674 return "movs{bl|x}\t{%h1, %k0|%k0, %h1}";
1676 return "mov{b}\t{%h1, %0|%0, %h1}";
1680 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1681 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1682 (ne (symbol_ref "TARGET_MOVX")
1684 (const_string "imovx")
1685 (const_string "imov")))
1687 (if_then_else (eq_attr "type" "imovx")
1689 (const_string "QI")))])
1691 ;; Stores and loads of ax to arbitrary constant address.
1692 ;; We fake an second form of instruction to force reload to load address
1693 ;; into register when rax is not available
1694 (define_insn "*movabsqi_1_rex64"
1695 [(set (mem:QI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
1696 (match_operand:QI 1 "nonmemory_operand" "a,er,i"))]
1699 movabs{b}\t{%1, %P0|%P0, %1}
1700 mov{b}\t{%1, %a0|%a0, %1}
1701 movabs{b}\t{%1, %a0|%a0, %1}"
1702 [(set_attr "type" "imov")
1703 (set_attr "modrm" "0,*,*")
1704 (set_attr "length_address" "8,0,0")
1705 (set_attr "length_immediate" "0,*,*")
1706 (set_attr "memory" "store")
1707 (set_attr "mode" "QI")])
1709 (define_insn "*movabsqi_2_rex64"
1710 [(set (match_operand:QI 0 "register_operand" "=a,r")
1711 (mem:QI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
1714 movabs{b}\t{%P1, %0|%0, %P1}
1715 mov{b}\t{%a1, %0|%0, %a1}"
1716 [(set_attr "type" "imov")
1717 (set_attr "modrm" "0,*")
1718 (set_attr "length_address" "8,0")
1719 (set_attr "length_immediate" "0")
1720 (set_attr "memory" "load")
1721 (set_attr "mode" "QI")])
1723 (define_insn "*movsi_extzv_1"
1724 [(set (match_operand:SI 0 "register_operand" "=R")
1725 (zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
1729 "movz{bl|x}\t{%h1, %0|%0, %h1}"
1730 [(set_attr "type" "imovx")
1731 (set_attr "mode" "SI")])
1733 (define_insn "*movqi_extzv_2"
1734 [(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
1735 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1740 switch (get_attr_type (insn))
1743 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1745 return "mov{b}\t{%h1, %0|%0, %h1}";
1749 (if_then_else (and (match_operand:QI 0 "register_operand" "")
1750 (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1751 (ne (symbol_ref "TARGET_MOVX")
1753 (const_string "imovx")
1754 (const_string "imov")))
1756 (if_then_else (eq_attr "type" "imovx")
1758 (const_string "QI")))])
1760 (define_insn "*movqi_extzv_2_rex64"
1761 [(set (match_operand:QI 0 "register_operand" "=Q,?R")
1762 (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
1767 switch (get_attr_type (insn))
1770 return "movz{bl|x}\t{%h1, %k0|%k0, %h1}";
1772 return "mov{b}\t{%h1, %0|%0, %h1}";
1776 (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
1777 (ne (symbol_ref "TARGET_MOVX")
1779 (const_string "imovx")
1780 (const_string "imov")))
1782 (if_then_else (eq_attr "type" "imovx")
1784 (const_string "QI")))])
1786 (define_insn "movsi_insv_1"
1787 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1790 (match_operand:SI 1 "general_operand" "Qmn"))]
1792 "mov{b}\t{%b1, %h0|%h0, %b1}"
1793 [(set_attr "type" "imov")
1794 (set_attr "mode" "QI")])
1796 (define_insn "*movsi_insv_1_rex64"
1797 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1800 (match_operand:SI 1 "nonmemory_operand" "Qn"))]
1802 "mov{b}\t{%b1, %h0|%h0, %b1}"
1803 [(set_attr "type" "imov")
1804 (set_attr "mode" "QI")])
1806 (define_insn "*movqi_insv_2"
1807 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
1810 (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
1814 "mov{b}\t{%h1, %h0|%h0, %h1}"
1815 [(set_attr "type" "imov")
1816 (set_attr "mode" "QI")])
1818 (define_expand "movdi"
1819 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1820 (match_operand:DI 1 "general_operand" ""))]
1822 "ix86_expand_move (DImode, operands); DONE;")
1824 (define_insn "*pushdi"
1825 [(set (match_operand:DI 0 "push_operand" "=<")
1826 (match_operand:DI 1 "general_no_elim_operand" "riF*m"))]
1830 (define_insn "pushdi2_rex64"
1831 [(set (match_operand:DI 0 "push_operand" "=<,!<")
1832 (match_operand:DI 1 "general_no_elim_operand" "re*m,n"))]
1837 [(set_attr "type" "push,multi")
1838 (set_attr "mode" "DI")])
1840 ;; Convert impossible pushes of immediate to existing instructions.
1841 ;; First try to get scratch register and go through it. In case this
1842 ;; fails, push sign extended lower part first and then overwrite
1843 ;; upper part by 32bit move.
1845 [(match_scratch:DI 2 "r")
1846 (set (match_operand:DI 0 "push_operand" "")
1847 (match_operand:DI 1 "immediate_operand" ""))]
1848 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1849 && !x86_64_immediate_operand (operands[1], DImode)"
1850 [(set (match_dup 2) (match_dup 1))
1851 (set (match_dup 0) (match_dup 2))]
1854 ;; We need to define this as both peepholer and splitter for case
1855 ;; peephole2 pass is not run.
1857 [(set (match_operand:DI 0 "push_operand" "")
1858 (match_operand:DI 1 "immediate_operand" ""))]
1859 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
1860 && !x86_64_immediate_operand (operands[1], DImode) && 1"
1861 [(set (match_dup 0) (match_dup 1))
1862 (set (match_dup 2) (match_dup 3))]
1863 "split_di (operands + 1, 1, operands + 2, operands + 3);
1864 operands[1] = gen_lowpart (DImode, operands[2]);
1865 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1870 [(set (match_operand:DI 0 "push_operand" "")
1871 (match_operand:DI 1 "immediate_operand" ""))]
1872 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
1873 && !symbolic_operand (operands[1], DImode)
1874 && !x86_64_immediate_operand (operands[1], DImode)"
1875 [(set (match_dup 0) (match_dup 1))
1876 (set (match_dup 2) (match_dup 3))]
1877 "split_di (operands + 1, 1, operands + 2, operands + 3);
1878 operands[1] = gen_lowpart (DImode, operands[2]);
1879 operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
1883 (define_insn "*pushdi2_prologue_rex64"
1884 [(set (match_operand:DI 0 "push_operand" "=<")
1885 (match_operand:DI 1 "general_no_elim_operand" "re*m"))
1886 (clobber (mem:BLK (scratch)))]
1889 [(set_attr "type" "push")
1890 (set_attr "mode" "DI")])
1892 (define_insn "*popdi1_epilogue_rex64"
1893 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1894 (mem:DI (reg:DI 7)))
1896 (plus:DI (reg:DI 7) (const_int 8)))
1897 (clobber (mem:BLK (scratch)))]
1900 [(set_attr "type" "pop")
1901 (set_attr "mode" "DI")])
1903 (define_insn "popdi1"
1904 [(set (match_operand:DI 0 "nonimmediate_operand" "=r*m")
1905 (mem:DI (reg:DI 7)))
1907 (plus:DI (reg:DI 7) (const_int 8)))]
1910 [(set_attr "type" "pop")
1911 (set_attr "mode" "DI")])
1913 (define_insn "*movdi_xor_rex64"
1914 [(set (match_operand:DI 0 "register_operand" "=r")
1915 (match_operand:DI 1 "const0_operand" "i"))
1916 (clobber (reg:CC 17))]
1917 "TARGET_64BIT && (!TARGET_USE_MOV0 || optimize_size)
1918 && reload_completed"
1919 "xor{l}\t{%k0, %k0|%k0, %k0}"
1920 [(set_attr "type" "alu1")
1921 (set_attr "mode" "SI")
1922 (set_attr "length_immediate" "0")])
1924 (define_insn "*movdi_or_rex64"
1925 [(set (match_operand:DI 0 "register_operand" "=r")
1926 (match_operand:DI 1 "const_int_operand" "i"))
1927 (clobber (reg:CC 17))]
1928 "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
1930 && GET_CODE (operands[1]) == CONST_INT
1931 && INTVAL (operands[1]) == -1"
1933 operands[1] = constm1_rtx;
1934 return "or{q}\t{%1, %0|%0, %1}";
1936 [(set_attr "type" "alu1")
1937 (set_attr "mode" "DI")
1938 (set_attr "length_immediate" "1")])
1940 (define_insn "*movdi_2"
1941 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*Y,!*Y")
1942 (match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*Y,*Y,m"))]
1944 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1948 movq\t{%1, %0|%0, %1}
1949 movq\t{%1, %0|%0, %1}
1950 movq\t{%1, %0|%0, %1}
1951 movdqa\t{%1, %0|%0, %1}
1952 movq\t{%1, %0|%0, %1}"
1953 [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
1954 (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
1957 [(set (match_operand:DI 0 "push_operand" "")
1958 (match_operand:DI 1 "general_operand" ""))]
1959 "!TARGET_64BIT && reload_completed
1960 && (! MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1962 "ix86_split_long_move (operands); DONE;")
1964 ;; %%% This multiword shite has got to go.
1966 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1967 (match_operand:DI 1 "general_operand" ""))]
1968 "!TARGET_64BIT && reload_completed
1969 && (!MMX_REG_P (operands[0]) && !SSE_REG_P (operands[0]))
1970 && (!MMX_REG_P (operands[1]) && !SSE_REG_P (operands[1]))"
1972 "ix86_split_long_move (operands); DONE;")
1974 (define_insn "*movdi_1_rex64"
1975 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!rm,!*y,!*Y,!rm,!*Y")
1976 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,rm,*Y,*Y,rm"))]
1978 && (TARGET_INTER_UNIT_MOVES || optimize_size)
1979 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
1981 switch (get_attr_type (insn))
1984 if (get_attr_mode (insn) == MODE_TI)
1985 return "movdqa\t{%1, %0|%0, %1}";
1988 /* Moves from and into integer register is done using movd opcode with
1990 if (GENERAL_REG_P (operands[0]) || GENERAL_REG_P (operands[1]))
1991 return "movd\t{%1, %0|%0, %1}";
1992 return "movq\t{%1, %0|%0, %1}";
1996 return "lea{q}\t{%a1, %0|%0, %a1}";
1998 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2000 if (get_attr_mode (insn) == MODE_SI)
2001 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2002 else if (which_alternative == 2)
2003 return "movabs{q}\t{%1, %0|%0, %1}";
2005 return "mov{q}\t{%1, %0|%0, %1}";
2009 (cond [(eq_attr "alternative" "5,6,7")
2010 (const_string "mmxmov")
2011 (eq_attr "alternative" "8,9,10")
2012 (const_string "ssemov")
2013 (eq_attr "alternative" "4")
2014 (const_string "multi")
2015 (and (ne (symbol_ref "flag_pic") (const_int 0))
2016 (match_operand:DI 1 "symbolic_operand" ""))
2017 (const_string "lea")
2019 (const_string "imov")))
2020 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2021 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2022 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2024 (define_insn "*movdi_1_rex64_nointerunit"
2025 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,mr,!mr,!*y,!m,!*y,!*Y,!m,!*Y")
2026 (match_operand:DI 1 "general_operand" "Z,rem,i,re,n,*y,*y,m,*Y,*Y,m"))]
2028 && (!TARGET_INTER_UNIT_MOVES && !optimize_size)
2029 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
2031 switch (get_attr_type (insn))
2034 if (get_attr_mode (insn) == MODE_TI)
2035 return "movdqa\t{%1, %0|%0, %1}";
2038 return "movq\t{%1, %0|%0, %1}";
2042 return "lea{q}\t{%a1, %0|%0, %a1}";
2044 if (flag_pic && !LEGITIMATE_PIC_OPERAND_P (operands[1]))
2046 if (get_attr_mode (insn) == MODE_SI)
2047 return "mov{l}\t{%k1, %k0|%k0, %k1}";
2048 else if (which_alternative == 2)
2049 return "movabs{q}\t{%1, %0|%0, %1}";
2051 return "mov{q}\t{%1, %0|%0, %1}";
2055 (cond [(eq_attr "alternative" "5,6,7")
2056 (const_string "mmxmov")
2057 (eq_attr "alternative" "8,9,10")
2058 (const_string "ssemov")
2059 (eq_attr "alternative" "4")
2060 (const_string "multi")
2061 (and (ne (symbol_ref "flag_pic") (const_int 0))
2062 (match_operand:DI 1 "symbolic_operand" ""))
2063 (const_string "lea")
2065 (const_string "imov")))
2066 (set_attr "modrm" "*,0,0,*,*,*,*,*,*,*,*")
2067 (set_attr "length_immediate" "*,4,8,*,*,*,*,*,*,*,*")
2068 (set_attr "mode" "SI,DI,DI,DI,SI,DI,DI,DI,TI,DI,DI")])
2070 ;; Stores and loads of ax to arbitrary constant address.
2071 ;; We fake an second form of instruction to force reload to load address
2072 ;; into register when rax is not available
2073 (define_insn "*movabsdi_1_rex64"
2074 [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
2075 (match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
2078 movabs{q}\t{%1, %P0|%P0, %1}
2079 mov{q}\t{%1, %a0|%a0, %1}
2080 movabs{q}\t{%1, %a0|%a0, %1}"
2081 [(set_attr "type" "imov")
2082 (set_attr "modrm" "0,*,*")
2083 (set_attr "length_address" "8,0,0")
2084 (set_attr "length_immediate" "0,*,*")
2085 (set_attr "memory" "store")
2086 (set_attr "mode" "DI")])
2088 (define_insn "*movabsdi_2_rex64"
2089 [(set (match_operand:DI 0 "register_operand" "=a,r")
2090 (mem:DI (match_operand:DI 1 "x86_64_movabs_operand" "i,r")))]
2093 movabs{q}\t{%P1, %0|%0, %P1}
2094 mov{q}\t{%a1, %0|%0, %a1}"
2095 [(set_attr "type" "imov")
2096 (set_attr "modrm" "0,*")
2097 (set_attr "length_address" "8,0")
2098 (set_attr "length_immediate" "0")
2099 (set_attr "memory" "load")
2100 (set_attr "mode" "DI")])
2102 ;; Convert impossible stores of immediate to existing instructions.
2103 ;; First try to get scratch register and go through it. In case this
2104 ;; fails, move by 32bit parts.
2106 [(match_scratch:DI 2 "r")
2107 (set (match_operand:DI 0 "memory_operand" "")
2108 (match_operand:DI 1 "immediate_operand" ""))]
2109 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2110 && !x86_64_immediate_operand (operands[1], DImode)"
2111 [(set (match_dup 2) (match_dup 1))
2112 (set (match_dup 0) (match_dup 2))]
2115 ;; We need to define this as both peepholer and splitter for case
2116 ;; peephole2 pass is not run.
2118 [(set (match_operand:DI 0 "memory_operand" "")
2119 (match_operand:DI 1 "immediate_operand" ""))]
2120 "TARGET_64BIT && !symbolic_operand (operands[1], DImode)
2121 && !x86_64_immediate_operand (operands[1], DImode) && 1"
2122 [(set (match_dup 2) (match_dup 3))
2123 (set (match_dup 4) (match_dup 5))]
2124 "split_di (operands, 2, operands + 2, operands + 4);")
2127 [(set (match_operand:DI 0 "memory_operand" "")
2128 (match_operand:DI 1 "immediate_operand" ""))]
2129 "TARGET_64BIT && (flow2_completed || (reload_completed && !flag_peephole2))
2130 && !symbolic_operand (operands[1], DImode)
2131 && !x86_64_immediate_operand (operands[1], DImode)"
2132 [(set (match_dup 2) (match_dup 3))
2133 (set (match_dup 4) (match_dup 5))]
2134 "split_di (operands, 2, operands + 2, operands + 4);")
2136 (define_insn "*swapdi_rex64"
2137 [(set (match_operand:DI 0 "register_operand" "+r")
2138 (match_operand:DI 1 "register_operand" "+r"))
2143 [(set_attr "type" "imov")
2144 (set_attr "pent_pair" "np")
2145 (set_attr "athlon_decode" "vector")
2146 (set_attr "mode" "DI")
2147 (set_attr "modrm" "0")
2148 (set_attr "ppro_uops" "few")])
2151 (define_expand "movsf"
2152 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2153 (match_operand:SF 1 "general_operand" ""))]
2155 "ix86_expand_move (SFmode, operands); DONE;")
2157 (define_insn "*pushsf"
2158 [(set (match_operand:SF 0 "push_operand" "=<,<,<")
2159 (match_operand:SF 1 "general_no_elim_operand" "f#rx,rFm#fx,x#rf"))]
2162 switch (which_alternative)
2165 return "push{l}\t%1";
2168 /* This insn should be already splitted before reg-stack. */
2172 [(set_attr "type" "multi,push,multi")
2173 (set_attr "mode" "SF,SI,SF")])
2175 (define_insn "*pushsf_rex64"
2176 [(set (match_operand:SF 0 "push_operand" "=X,X,X")
2177 (match_operand:SF 1 "nonmemory_no_elim_operand" "f#rx,rF#fx,x#rf"))]
2180 switch (which_alternative)
2183 return "push{q}\t%q1";
2186 /* This insn should be already splitted before reg-stack. */
2190 [(set_attr "type" "multi,push,multi")
2191 (set_attr "mode" "SF,DI,SF")])
2194 [(set (match_operand:SF 0 "push_operand" "")
2195 (match_operand:SF 1 "memory_operand" ""))]
2197 && GET_CODE (operands[1]) == MEM
2198 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2199 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))"
2202 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
2205 ;; %%% Kill this when call knows how to work this out.
2207 [(set (match_operand:SF 0 "push_operand" "")
2208 (match_operand:SF 1 "any_fp_register_operand" ""))]
2210 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
2211 (set (mem:SF (reg:SI 7)) (match_dup 1))])
2214 [(set (match_operand:SF 0 "push_operand" "")
2215 (match_operand:SF 1 "any_fp_register_operand" ""))]
2217 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2218 (set (mem:SF (reg:DI 7)) (match_dup 1))])
2220 (define_insn "*movsf_1"
2221 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!rm,!*y")
2222 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,rm,*y,*y"))]
2223 "(TARGET_INTER_UNIT_MOVES || optimize_size)
2224 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2225 && (reload_in_progress || reload_completed
2226 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2227 || GET_CODE (operands[1]) != CONST_DOUBLE
2228 || memory_operand (operands[0], SFmode))"
2230 switch (which_alternative)
2233 if (REG_P (operands[1])
2234 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2236 else if (STACK_TOP_P (operands[0]))
2237 return "fld%z1\t%y1";
2242 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2243 return "fstp%z0\t%y0";
2245 return "fst%z0\t%y0";
2248 return standard_80387_constant_opcode (operands[1]);
2252 return "mov{l}\t{%1, %0|%0, %1}";
2254 if (get_attr_mode (insn) == MODE_TI)
2255 return "pxor\t%0, %0";
2257 return "xorps\t%0, %0";
2259 if (get_attr_mode (insn) == MODE_V4SF)
2260 return "movaps\t{%1, %0|%0, %1}";
2262 return "movss\t{%1, %0|%0, %1}";
2265 return "movss\t{%1, %0|%0, %1}";
2269 return "movd\t{%1, %0|%0, %1}";
2272 return "movq\t{%1, %0|%0, %1}";
2278 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2280 (cond [(eq_attr "alternative" "3,4,9,10")
2282 (eq_attr "alternative" "5")
2284 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2286 (ne (symbol_ref "TARGET_SSE2")
2288 (eq (symbol_ref "optimize_size")
2291 (const_string "V4SF"))
2292 /* For architectures resolving dependencies on
2293 whole SSE registers use APS move to break dependency
2294 chains, otherwise use short move to avoid extra work.
2296 Do the same for architectures resolving dependencies on
2297 the parts. While in DF mode it is better to always handle
2298 just register parts, the SF mode is different due to lack
2299 of instructions to load just part of the register. It is
2300 better to maintain the whole registers in single format
2301 to avoid problems on using packed logical operations. */
2302 (eq_attr "alternative" "6")
2304 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2306 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2308 (const_string "V4SF")
2309 (const_string "SF"))
2310 (eq_attr "alternative" "11")
2311 (const_string "DI")]
2312 (const_string "SF")))])
2314 (define_insn "*movsf_1_nointerunit"
2315 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#xr,m,f#xr,r#xf,m,x#rf,x#rf,x#rf,m,!*y,!m,!*y")
2316 (match_operand:SF 1 "general_operand" "fm#rx,f#rx,G,rmF#fx,Fr#fx,C,x,xm#rf,x#rf,m,*y,*y"))]
2317 "(!TARGET_INTER_UNIT_MOVES && !optimize_size)
2318 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2319 && (reload_in_progress || reload_completed
2320 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2321 || GET_CODE (operands[1]) != CONST_DOUBLE
2322 || memory_operand (operands[0], SFmode))"
2324 switch (which_alternative)
2327 if (REG_P (operands[1])
2328 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2330 if (REGNO (operands[0]) == FIRST_STACK_REG
2331 && TARGET_USE_FFREEP)
2332 return "ffreep\t%y0";
2335 else if (STACK_TOP_P (operands[0]))
2336 return "fld%z1\t%y1";
2341 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2342 return "fstp%z0\t%y0";
2344 return "fst%z0\t%y0";
2347 return standard_80387_constant_opcode (operands[1]);
2351 return "mov{l}\t{%1, %0|%0, %1}";
2353 if (get_attr_mode (insn) == MODE_TI)
2354 return "pxor\t%0, %0";
2356 return "xorps\t%0, %0";
2358 if (get_attr_mode (insn) == MODE_V4SF)
2359 return "movaps\t{%1, %0|%0, %1}";
2361 return "movss\t{%1, %0|%0, %1}";
2364 return "movss\t{%1, %0|%0, %1}";
2368 return "movd\t{%1, %0|%0, %1}";
2371 return "movq\t{%1, %0|%0, %1}";
2377 [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov")
2379 (cond [(eq_attr "alternative" "3,4,9,10")
2381 (eq_attr "alternative" "5")
2383 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2385 (ne (symbol_ref "TARGET_SSE2")
2387 (eq (symbol_ref "optimize_size")
2390 (const_string "V4SF"))
2391 /* For architectures resolving dependencies on
2392 whole SSE registers use APS move to break dependency
2393 chains, otherwise use short move to avoid extra work.
2395 Do the same for architectures resolving dependencies on
2396 the parts. While in DF mode it is better to always handle
2397 just register parts, the SF mode is different due to lack
2398 of instructions to load just part of the register. It is
2399 better to maintain the whole registers in single format
2400 to avoid problems on using packed logical operations. */
2401 (eq_attr "alternative" "6")
2403 (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2405 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2407 (const_string "V4SF")
2408 (const_string "SF"))
2409 (eq_attr "alternative" "11")
2410 (const_string "DI")]
2411 (const_string "SF")))])
2413 (define_insn "*swapsf"
2414 [(set (match_operand:SF 0 "register_operand" "+f")
2415 (match_operand:SF 1 "register_operand" "+f"))
2418 "reload_completed || !TARGET_SSE"
2420 if (STACK_TOP_P (operands[0]))
2425 [(set_attr "type" "fxch")
2426 (set_attr "mode" "SF")])
2428 (define_expand "movdf"
2429 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2430 (match_operand:DF 1 "general_operand" ""))]
2432 "ix86_expand_move (DFmode, operands); DONE;")
2434 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2435 ;; Size of pushdf using integer instructions is 2+2*memory operand size
2436 ;; On the average, pushdf using integers can be still shorter. Allow this
2437 ;; pattern for optimize_size too.
2439 (define_insn "*pushdf_nointeger"
2440 [(set (match_operand:DF 0 "push_operand" "=<,<,<,<")
2441 (match_operand:DF 1 "general_no_elim_operand" "f#Y,Fo#fY,*r#fY,Y#f"))]
2442 "!TARGET_64BIT && !TARGET_INTEGER_DFMODE_MOVES"
2444 /* This insn should be already splitted before reg-stack. */
2447 [(set_attr "type" "multi")
2448 (set_attr "mode" "DF,SI,SI,DF")])
2450 (define_insn "*pushdf_integer"
2451 [(set (match_operand:DF 0 "push_operand" "=<,<,<")
2452 (match_operand:DF 1 "general_no_elim_operand" "f#rY,rFo#fY,Y#rf"))]
2453 "TARGET_64BIT || TARGET_INTEGER_DFMODE_MOVES"
2455 /* This insn should be already splitted before reg-stack. */
2458 [(set_attr "type" "multi")
2459 (set_attr "mode" "DF,SI,DF")])
2461 ;; %%% Kill this when call knows how to work this out.
2463 [(set (match_operand:DF 0 "push_operand" "")
2464 (match_operand:DF 1 "any_fp_register_operand" ""))]
2465 "!TARGET_64BIT && reload_completed"
2466 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
2467 (set (mem:DF (reg:SI 7)) (match_dup 1))]
2471 [(set (match_operand:DF 0 "push_operand" "")
2472 (match_operand:DF 1 "any_fp_register_operand" ""))]
2473 "TARGET_64BIT && reload_completed"
2474 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
2475 (set (mem:DF (reg:DI 7)) (match_dup 1))]
2479 [(set (match_operand:DF 0 "push_operand" "")
2480 (match_operand:DF 1 "general_operand" ""))]
2483 "ix86_split_long_move (operands); DONE;")
2485 ;; Moving is usually shorter when only FP registers are used. This separate
2486 ;; movdf pattern avoids the use of integer registers for FP operations
2487 ;; when optimizing for size.
2489 (define_insn "*movdf_nointeger"
2490 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,m,f#Y,*r,o,Y#f,Y#f,Y#f,m")
2491 (match_operand:DF 1 "general_operand" "fm#Y,f#Y,G,*roF,F*r,C,Y#f,YHm#f,Y#f"))]
2492 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2493 && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
2494 && (reload_in_progress || reload_completed
2495 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2496 || GET_CODE (operands[1]) != CONST_DOUBLE
2497 || memory_operand (operands[0], DFmode))"
2499 switch (which_alternative)
2502 if (REG_P (operands[1])
2503 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2505 if (REGNO (operands[0]) == FIRST_STACK_REG
2506 && TARGET_USE_FFREEP)
2507 return "ffreep\t%y0";
2510 else if (STACK_TOP_P (operands[0]))
2511 return "fld%z1\t%y1";
2516 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2517 return "fstp%z0\t%y0";
2519 return "fst%z0\t%y0";
2522 return standard_80387_constant_opcode (operands[1]);
2528 switch (get_attr_mode (insn))
2531 return "xorps\t%0, %0";
2533 return "xorpd\t%0, %0";
2535 return "pxor\t%0, %0";
2540 switch (get_attr_mode (insn))
2543 return "movaps\t{%1, %0|%0, %1}";
2545 return "movapd\t{%1, %0|%0, %1}";
2547 return "movsd\t{%1, %0|%0, %1}";
2552 if (get_attr_mode (insn) == MODE_V2DF)
2553 return "movlpd\t{%1, %0|%0, %1}";
2555 return "movsd\t{%1, %0|%0, %1}";
2557 return "movsd\t{%1, %0|%0, %1}";
2563 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2565 (cond [(eq_attr "alternative" "3,4")
2567 /* xorps is one byte shorter. */
2568 (eq_attr "alternative" "5")
2569 (cond [(ne (symbol_ref "optimize_size")
2571 (const_string "V4SF")
2572 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2574 (const_string "TI")]
2575 (const_string "V2DF"))
2576 /* For architectures resolving dependencies on
2577 whole SSE registers use APD move to break dependency
2578 chains, otherwise use short move to avoid extra work.
2580 movaps encodes one byte shorter. */
2581 (eq_attr "alternative" "6")
2583 [(ne (symbol_ref "optimize_size")
2585 (const_string "V4SF")
2586 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2588 (const_string "V2DF")]
2589 (const_string "DF"))
2590 /* For architectures resolving dependencies on register
2591 parts we may avoid extra work to zero out upper part
2593 (eq_attr "alternative" "7")
2595 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2597 (const_string "V2DF")
2598 (const_string "DF"))]
2599 (const_string "DF")))])
2601 (define_insn "*movdf_integer"
2602 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Yr,m,f#Yr,r#Yf,o,Y#rf,Y#rf,Y#rf,m")
2603 (match_operand:DF 1 "general_operand" "fm#Yr,f#Yr,G,roF#Yf,Fr#Yf,C,Y#rf,Ym#rf,Y#rf"))]
2604 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2605 && ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
2606 && (reload_in_progress || reload_completed
2607 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2608 || GET_CODE (operands[1]) != CONST_DOUBLE
2609 || memory_operand (operands[0], DFmode))"
2611 switch (which_alternative)
2614 if (REG_P (operands[1])
2615 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2617 if (REGNO (operands[0]) == FIRST_STACK_REG
2618 && TARGET_USE_FFREEP)
2619 return "ffreep\t%y0";
2622 else if (STACK_TOP_P (operands[0]))
2623 return "fld%z1\t%y1";
2628 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2629 return "fstp%z0\t%y0";
2631 return "fst%z0\t%y0";
2634 return standard_80387_constant_opcode (operands[1]);
2641 switch (get_attr_mode (insn))
2644 return "xorps\t%0, %0";
2646 return "xorpd\t%0, %0";
2648 return "pxor\t%0, %0";
2653 switch (get_attr_mode (insn))
2656 return "movaps\t{%1, %0|%0, %1}";
2658 return "movapd\t{%1, %0|%0, %1}";
2660 return "movsd\t{%1, %0|%0, %1}";
2665 if (get_attr_mode (insn) == MODE_V2DF)
2666 return "movlpd\t{%1, %0|%0, %1}";
2668 return "movsd\t{%1, %0|%0, %1}";
2670 return "movsd\t{%1, %0|%0, %1}";
2676 [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
2678 (cond [(eq_attr "alternative" "3,4")
2680 /* xorps is one byte shorter. */
2681 (eq_attr "alternative" "5")
2682 (cond [(ne (symbol_ref "optimize_size")
2684 (const_string "V4SF")
2685 (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
2687 (const_string "TI")]
2688 (const_string "V2DF"))
2689 /* For architectures resolving dependencies on
2690 whole SSE registers use APD move to break dependency
2691 chains, otherwise use short move to avoid extra work.
2693 movaps encodes one byte shorter. */
2694 (eq_attr "alternative" "6")
2696 [(ne (symbol_ref "optimize_size")
2698 (const_string "V4SF")
2699 (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
2701 (const_string "V2DF")]
2702 (const_string "DF"))
2703 /* For architectures resolving dependencies on register
2704 parts we may avoid extra work to zero out upper part
2706 (eq_attr "alternative" "7")
2708 (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
2710 (const_string "V2DF")
2711 (const_string "DF"))]
2712 (const_string "DF")))])
2715 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2716 (match_operand:DF 1 "general_operand" ""))]
2718 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2719 && ! (ANY_FP_REG_P (operands[0]) ||
2720 (GET_CODE (operands[0]) == SUBREG
2721 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
2722 && ! (ANY_FP_REG_P (operands[1]) ||
2723 (GET_CODE (operands[1]) == SUBREG
2724 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
2726 "ix86_split_long_move (operands); DONE;")
2728 (define_insn "*swapdf"
2729 [(set (match_operand:DF 0 "register_operand" "+f")
2730 (match_operand:DF 1 "register_operand" "+f"))
2733 "reload_completed || !TARGET_SSE2"
2735 if (STACK_TOP_P (operands[0]))
2740 [(set_attr "type" "fxch")
2741 (set_attr "mode" "DF")])
2743 (define_expand "movxf"
2744 [(set (match_operand:XF 0 "nonimmediate_operand" "")
2745 (match_operand:XF 1 "general_operand" ""))]
2746 "!TARGET_128BIT_LONG_DOUBLE"
2747 "ix86_expand_move (XFmode, operands); DONE;")
2749 (define_expand "movtf"
2750 [(set (match_operand:TF 0 "nonimmediate_operand" "")
2751 (match_operand:TF 1 "general_operand" ""))]
2753 "ix86_expand_move (TFmode, operands); DONE;")
2755 ;; Size of pushdf is 3 (for sub) + 2 (for fstp) + memory operand size.
2756 ;; Size of pushdf using integer instructions is 3+3*memory operand size
2757 ;; Pushing using integer instructions is longer except for constants
2758 ;; and direct memory references.
2759 ;; (assuming that any given constant is pushed only once, but this ought to be
2760 ;; handled elsewhere).
2762 (define_insn "*pushxf_nointeger"
2763 [(set (match_operand:XF 0 "push_operand" "=X,X,X")
2764 (match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
2765 "!TARGET_128BIT_LONG_DOUBLE && optimize_size"
2767 /* This insn should be already splitted before reg-stack. */
2770 [(set_attr "type" "multi")
2771 (set_attr "mode" "XF,SI,SI")])
2773 (define_insn "*pushtf_nointeger"
2774 [(set (match_operand:TF 0 "push_operand" "=<,<,<")
2775 (match_operand:TF 1 "general_no_elim_operand" "f,Fo,*r"))]
2778 /* This insn should be already splitted before reg-stack. */
2781 [(set_attr "type" "multi")
2782 (set_attr "mode" "XF,SI,SI")])
2784 (define_insn "*pushxf_integer"
2785 [(set (match_operand:XF 0 "push_operand" "=<,<")
2786 (match_operand:XF 1 "general_no_elim_operand" "f#r,ro#f"))]
2787 "!TARGET_128BIT_LONG_DOUBLE && !optimize_size"
2789 /* This insn should be already splitted before reg-stack. */
2792 [(set_attr "type" "multi")
2793 (set_attr "mode" "XF,SI")])
2795 (define_insn "*pushtf_integer"
2796 [(set (match_operand:TF 0 "push_operand" "=<,<")
2797 (match_operand:TF 1 "general_no_elim_operand" "f#r,rFo#f"))]
2800 /* This insn should be already splitted before reg-stack. */
2803 [(set_attr "type" "multi")
2804 (set_attr "mode" "XF,SI")])
2807 [(set (match_operand 0 "push_operand" "")
2808 (match_operand 1 "general_operand" ""))]
2810 && (GET_MODE (operands[0]) == XFmode
2811 || GET_MODE (operands[0]) == TFmode
2812 || GET_MODE (operands[0]) == DFmode)
2813 && !ANY_FP_REG_P (operands[1])"
2815 "ix86_split_long_move (operands); DONE;")
2818 [(set (match_operand:XF 0 "push_operand" "")
2819 (match_operand:XF 1 "any_fp_register_operand" ""))]
2820 "!TARGET_128BIT_LONG_DOUBLE"
2821 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
2822 (set (mem:XF (reg:SI 7)) (match_dup 1))])
2825 [(set (match_operand:TF 0 "push_operand" "")
2826 (match_operand:TF 1 "any_fp_register_operand" ""))]
2828 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
2829 (set (mem:TF (reg:SI 7)) (match_dup 1))])
2832 [(set (match_operand:TF 0 "push_operand" "")
2833 (match_operand:TF 1 "any_fp_register_operand" ""))]
2835 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
2836 (set (mem:TF (reg:DI 7)) (match_dup 1))])
2838 ;; Do not use integer registers when optimizing for size
2839 (define_insn "*movxf_nointeger"
2840 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2841 (match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2842 "!TARGET_128BIT_LONG_DOUBLE
2844 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2845 && (reload_in_progress || reload_completed
2846 || GET_CODE (operands[1]) != CONST_DOUBLE
2847 || memory_operand (operands[0], XFmode))"
2849 switch (which_alternative)
2852 if (REG_P (operands[1])
2853 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2855 if (REGNO (operands[0]) == FIRST_STACK_REG
2856 && TARGET_USE_FFREEP)
2857 return "ffreep\t%y0";
2860 else if (STACK_TOP_P (operands[0]))
2861 return "fld%z1\t%y1";
2866 /* There is no non-popping store to memory for XFmode. So if
2867 we need one, follow the store with a load. */
2868 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2869 return "fstp%z0\t%y0\;fld%z0\t%y0";
2871 return "fstp%z0\t%y0";
2874 return standard_80387_constant_opcode (operands[1]);
2881 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2882 (set_attr "mode" "XF,XF,XF,SI,SI")])
2884 (define_insn "*movtf_nointeger"
2885 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m,f,*r,o")
2886 (match_operand:TF 1 "general_operand" "fm,f,G,*roF,F*r"))]
2887 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2889 && (reload_in_progress || reload_completed
2890 || GET_CODE (operands[1]) != CONST_DOUBLE
2891 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2892 || memory_operand (operands[0], TFmode))"
2894 switch (which_alternative)
2897 if (REG_P (operands[1])
2898 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2900 if (REGNO (operands[0]) == FIRST_STACK_REG
2901 && TARGET_USE_FFREEP)
2902 return "ffreep\t%y0";
2905 else if (STACK_TOP_P (operands[0]))
2906 return "fld%z1\t%y1";
2911 /* There is no non-popping store to memory for XFmode. So if
2912 we need one, follow the store with a load. */
2913 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2914 return "fstp%z0\t%y0\;fld%z0\t%y0";
2916 return "fstp%z0\t%y0";
2919 return standard_80387_constant_opcode (operands[1]);
2926 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2927 (set_attr "mode" "XF,XF,XF,SI,SI")])
2929 (define_insn "*movxf_integer"
2930 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2931 (match_operand:XF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2932 "!TARGET_128BIT_LONG_DOUBLE
2934 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2935 && (reload_in_progress || reload_completed
2936 || GET_CODE (operands[1]) != CONST_DOUBLE
2937 || memory_operand (operands[0], XFmode))"
2939 switch (which_alternative)
2942 if (REG_P (operands[1])
2943 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2945 if (REGNO (operands[0]) == FIRST_STACK_REG
2946 && TARGET_USE_FFREEP)
2947 return "ffreep\t%y0";
2950 else if (STACK_TOP_P (operands[0]))
2951 return "fld%z1\t%y1";
2956 /* There is no non-popping store to memory for XFmode. So if
2957 we need one, follow the store with a load. */
2958 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2959 return "fstp%z0\t%y0\;fld%z0\t%y0";
2961 return "fstp%z0\t%y0";
2964 return standard_80387_constant_opcode (operands[1]);
2971 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
2972 (set_attr "mode" "XF,XF,XF,SI,SI")])
2974 (define_insn "*movtf_integer"
2975 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
2976 (match_operand:TF 1 "general_operand" "fm#r,f#r,G,roF#f,Fr#f"))]
2977 "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
2979 && (reload_in_progress || reload_completed
2980 || GET_CODE (operands[1]) != CONST_DOUBLE
2981 || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
2982 || memory_operand (operands[0], TFmode))"
2984 switch (which_alternative)
2987 if (REG_P (operands[1])
2988 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
2990 if (REGNO (operands[0]) == FIRST_STACK_REG
2991 && TARGET_USE_FFREEP)
2992 return "ffreep\t%y0";
2995 else if (STACK_TOP_P (operands[0]))
2996 return "fld%z1\t%y1";
3001 /* There is no non-popping store to memory for XFmode. So if
3002 we need one, follow the store with a load. */
3003 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3004 return "fstp%z0\t%y0\;fld%z0\t%y0";
3006 return "fstp%z0\t%y0";
3009 return standard_80387_constant_opcode (operands[1]);
3016 [(set_attr "type" "fmov,fmov,fmov,multi,multi")
3017 (set_attr "mode" "XF,XF,XF,SI,SI")])
3020 [(set (match_operand 0 "nonimmediate_operand" "")
3021 (match_operand 1 "general_operand" ""))]
3023 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
3024 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode)
3025 && ! (ANY_FP_REG_P (operands[0]) ||
3026 (GET_CODE (operands[0]) == SUBREG
3027 && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
3028 && ! (ANY_FP_REG_P (operands[1]) ||
3029 (GET_CODE (operands[1]) == SUBREG
3030 && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
3032 "ix86_split_long_move (operands); DONE;")
3035 [(set (match_operand 0 "register_operand" "")
3036 (match_operand 1 "memory_operand" ""))]
3038 && GET_CODE (operands[1]) == MEM
3039 && (GET_MODE (operands[0]) == XFmode || GET_MODE (operands[0]) == TFmode
3040 || GET_MODE (operands[0]) == SFmode || GET_MODE (operands[0]) == DFmode)
3041 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
3042 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))
3043 && (!(SSE_REG_P (operands[0]) ||
3044 (GET_CODE (operands[0]) == SUBREG
3045 && SSE_REG_P (SUBREG_REG (operands[0]))))
3046 || standard_sse_constant_p (get_pool_constant (XEXP (operands[1], 0))))
3047 && (!(FP_REG_P (operands[0]) ||
3048 (GET_CODE (operands[0]) == SUBREG
3049 && FP_REG_P (SUBREG_REG (operands[0]))))
3050 || standard_80387_constant_p (get_pool_constant (XEXP (operands[1], 0))))"
3053 "operands[1] = get_pool_constant (XEXP (operands[1], 0));")
3055 (define_insn "swapxf"
3056 [(set (match_operand:XF 0 "register_operand" "+f")
3057 (match_operand:XF 1 "register_operand" "+f"))
3062 if (STACK_TOP_P (operands[0]))
3067 [(set_attr "type" "fxch")
3068 (set_attr "mode" "XF")])
3070 (define_insn "swaptf"
3071 [(set (match_operand:TF 0 "register_operand" "+f")
3072 (match_operand:TF 1 "register_operand" "+f"))
3077 if (STACK_TOP_P (operands[0]))
3082 [(set_attr "type" "fxch")
3083 (set_attr "mode" "XF")])
3085 ;; Zero extension instructions
3087 (define_expand "zero_extendhisi2"
3088 [(set (match_operand:SI 0 "register_operand" "")
3089 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3092 if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3094 operands[1] = force_reg (HImode, operands[1]);
3095 emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
3100 (define_insn "zero_extendhisi2_and"
3101 [(set (match_operand:SI 0 "register_operand" "=r")
3102 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
3103 (clobber (reg:CC 17))]
3104 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3106 [(set_attr "type" "alu1")
3107 (set_attr "mode" "SI")])
3110 [(set (match_operand:SI 0 "register_operand" "")
3111 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
3112 (clobber (reg:CC 17))]
3113 "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3114 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
3115 (clobber (reg:CC 17))])]
3118 (define_insn "*zero_extendhisi2_movzwl"
3119 [(set (match_operand:SI 0 "register_operand" "=r")
3120 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3121 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3122 "movz{wl|x}\t{%1, %0|%0, %1}"
3123 [(set_attr "type" "imovx")
3124 (set_attr "mode" "SI")])
3126 (define_expand "zero_extendqihi2"
3128 [(set (match_operand:HI 0 "register_operand" "")
3129 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3130 (clobber (reg:CC 17))])]
3134 (define_insn "*zero_extendqihi2_and"
3135 [(set (match_operand:HI 0 "register_operand" "=r,?&q")
3136 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3137 (clobber (reg:CC 17))]
3138 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3140 [(set_attr "type" "alu1")
3141 (set_attr "mode" "HI")])
3143 (define_insn "*zero_extendqihi2_movzbw_and"
3144 [(set (match_operand:HI 0 "register_operand" "=r,r")
3145 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3146 (clobber (reg:CC 17))]
3147 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3149 [(set_attr "type" "imovx,alu1")
3150 (set_attr "mode" "HI")])
3152 (define_insn "*zero_extendqihi2_movzbw"
3153 [(set (match_operand:HI 0 "register_operand" "=r")
3154 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3155 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3156 "movz{bw|x}\t{%1, %0|%0, %1}"
3157 [(set_attr "type" "imovx")
3158 (set_attr "mode" "HI")])
3160 ;; For the movzbw case strip only the clobber
3162 [(set (match_operand:HI 0 "register_operand" "")
3163 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3164 (clobber (reg:CC 17))]
3166 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3167 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3168 [(set (match_operand:HI 0 "register_operand" "")
3169 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
3171 ;; When source and destination does not overlap, clear destination
3172 ;; first and then do the movb
3174 [(set (match_operand:HI 0 "register_operand" "")
3175 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
3176 (clobber (reg:CC 17))]
3178 && ANY_QI_REG_P (operands[0])
3179 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3180 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3181 [(set (match_dup 0) (const_int 0))
3182 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3183 "operands[2] = gen_lowpart (QImode, operands[0]);")
3185 ;; Rest is handled by single and.
3187 [(set (match_operand:HI 0 "register_operand" "")
3188 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))
3189 (clobber (reg:CC 17))]
3191 && true_regnum (operands[0]) == true_regnum (operands[1])"
3192 [(parallel [(set (match_dup 0) (and:HI (match_dup 0) (const_int 255)))
3193 (clobber (reg:CC 17))])]
3196 (define_expand "zero_extendqisi2"
3198 [(set (match_operand:SI 0 "register_operand" "")
3199 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3200 (clobber (reg:CC 17))])]
3204 (define_insn "*zero_extendqisi2_and"
3205 [(set (match_operand:SI 0 "register_operand" "=r,?&q")
3206 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
3207 (clobber (reg:CC 17))]
3208 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
3210 [(set_attr "type" "alu1")
3211 (set_attr "mode" "SI")])
3213 (define_insn "*zero_extendqisi2_movzbw_and"
3214 [(set (match_operand:SI 0 "register_operand" "=r,r")
3215 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
3216 (clobber (reg:CC 17))]
3217 "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
3219 [(set_attr "type" "imovx,alu1")
3220 (set_attr "mode" "SI")])
3222 (define_insn "*zero_extendqisi2_movzbw"
3223 [(set (match_operand:SI 0 "register_operand" "=r")
3224 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3225 "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
3226 "movz{bl|x}\t{%1, %0|%0, %1}"
3227 [(set_attr "type" "imovx")
3228 (set_attr "mode" "SI")])
3230 ;; For the movzbl case strip only the clobber
3232 [(set (match_operand:SI 0 "register_operand" "")
3233 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3234 (clobber (reg:CC 17))]
3236 && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
3237 && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
3239 (zero_extend:SI (match_dup 1)))])
3241 ;; When source and destination does not overlap, clear destination
3242 ;; first and then do the movb
3244 [(set (match_operand:SI 0 "register_operand" "")
3245 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
3246 (clobber (reg:CC 17))]
3248 && ANY_QI_REG_P (operands[0])
3249 && (ANY_QI_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM)
3250 && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
3251 && !reg_overlap_mentioned_p (operands[0], operands[1])"
3252 [(set (match_dup 0) (const_int 0))
3253 (set (strict_low_part (match_dup 2)) (match_dup 1))]
3254 "operands[2] = gen_lowpart (QImode, operands[0]);")
3256 ;; Rest is handled by single and.
3258 [(set (match_operand:SI 0 "register_operand" "")
3259 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
3260 (clobber (reg:CC 17))]
3262 && true_regnum (operands[0]) == true_regnum (operands[1])"
3263 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 255)))
3264 (clobber (reg:CC 17))])]
3267 ;; %%% Kill me once multi-word ops are sane.
3268 (define_expand "zero_extendsidi2"
3269 [(set (match_operand:DI 0 "register_operand" "=r")
3270 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
3274 emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
3279 (define_insn "zero_extendsidi2_32"
3280 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
3281 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
3282 (clobber (reg:CC 17))]
3285 [(set_attr "mode" "SI")])
3287 (define_insn "zero_extendsidi2_rex64"
3288 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
3289 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
3292 mov\t{%k1, %k0|%k0, %k1}
3294 [(set_attr "type" "imovx,imov")
3295 (set_attr "mode" "SI,DI")])
3298 [(set (match_operand:DI 0 "memory_operand" "")
3299 (zero_extend:DI (match_dup 0)))]
3301 [(set (match_dup 4) (const_int 0))]
3302 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3305 [(set (match_operand:DI 0 "register_operand" "")
3306 (zero_extend:DI (match_operand:SI 1 "register_operand" "")))
3307 (clobber (reg:CC 17))]
3308 "!TARGET_64BIT && reload_completed
3309 && true_regnum (operands[0]) == true_regnum (operands[1])"
3310 [(set (match_dup 4) (const_int 0))]
3311 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3314 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3315 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))
3316 (clobber (reg:CC 17))]
3317 "!TARGET_64BIT && reload_completed"
3318 [(set (match_dup 3) (match_dup 1))
3319 (set (match_dup 4) (const_int 0))]
3320 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3322 (define_insn "zero_extendhidi2"
3323 [(set (match_operand:DI 0 "register_operand" "=r,r")
3324 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
3327 movz{wl|x}\t{%1, %k0|%k0, %1}
3328 movz{wq|x}\t{%1, %0|%0, %1}"
3329 [(set_attr "type" "imovx")
3330 (set_attr "mode" "SI,DI")])
3332 (define_insn "zero_extendqidi2"
3333 [(set (match_operand:DI 0 "register_operand" "=r,r")
3334 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "Q,m")))]
3337 movz{bl|x}\t{%1, %k0|%k0, %1}
3338 movz{bq|x}\t{%1, %0|%0, %1}"
3339 [(set_attr "type" "imovx")
3340 (set_attr "mode" "SI,DI")])
3342 ;; Sign extension instructions
3344 (define_expand "extendsidi2"
3345 [(parallel [(set (match_operand:DI 0 "register_operand" "")
3346 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3347 (clobber (reg:CC 17))
3348 (clobber (match_scratch:SI 2 ""))])]
3353 emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
3358 (define_insn "*extendsidi2_1"
3359 [(set (match_operand:DI 0 "nonimmediate_operand" "=*A,r,?r,?*o")
3360 (sign_extend:DI (match_operand:SI 1 "register_operand" "0,0,r,r")))
3361 (clobber (reg:CC 17))
3362 (clobber (match_scratch:SI 2 "=X,X,X,&r"))]
3366 (define_insn "extendsidi2_rex64"
3367 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3368 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "*0,rm")))]
3372 movs{lq|x}\t{%1,%0|%0, %1}"
3373 [(set_attr "type" "imovx")
3374 (set_attr "mode" "DI")
3375 (set_attr "prefix_0f" "0")
3376 (set_attr "modrm" "0,1")])
3378 (define_insn "extendhidi2"
3379 [(set (match_operand:DI 0 "register_operand" "=r")
3380 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
3382 "movs{wq|x}\t{%1,%0|%0, %1}"
3383 [(set_attr "type" "imovx")
3384 (set_attr "mode" "DI")])
3386 (define_insn "extendqidi2"
3387 [(set (match_operand:DI 0 "register_operand" "=r")
3388 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3390 "movs{bq|x}\t{%1,%0|%0, %1}"
3391 [(set_attr "type" "imovx")
3392 (set_attr "mode" "DI")])
3394 ;; Extend to memory case when source register does die.
3396 [(set (match_operand:DI 0 "memory_operand" "")
3397 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3398 (clobber (reg:CC 17))
3399 (clobber (match_operand:SI 2 "register_operand" ""))]
3401 && dead_or_set_p (insn, operands[1])
3402 && !reg_mentioned_p (operands[1], operands[0]))"
3403 [(set (match_dup 3) (match_dup 1))
3404 (parallel [(set (match_dup 1) (ashiftrt:SI (match_dup 1) (const_int 31)))
3405 (clobber (reg:CC 17))])
3406 (set (match_dup 4) (match_dup 1))]
3407 "split_di (&operands[0], 1, &operands[3], &operands[4]);")
3409 ;; Extend to memory case when source register does not die.
3411 [(set (match_operand:DI 0 "memory_operand" "")
3412 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3413 (clobber (reg:CC 17))
3414 (clobber (match_operand:SI 2 "register_operand" ""))]
3418 split_di (&operands[0], 1, &operands[3], &operands[4]);
3420 emit_move_insn (operands[3], operands[1]);
3422 /* Generate a cltd if possible and doing so it profitable. */
3423 if (true_regnum (operands[1]) == 0
3424 && true_regnum (operands[2]) == 1
3425 && (optimize_size || TARGET_USE_CLTD))
3427 emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
3431 emit_move_insn (operands[2], operands[1]);
3432 emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
3434 emit_move_insn (operands[4], operands[2]);
3438 ;; Extend to register case. Optimize case where source and destination
3439 ;; registers match and cases where we can use cltd.
3441 [(set (match_operand:DI 0 "register_operand" "")
3442 (sign_extend:DI (match_operand:SI 1 "register_operand" "")))
3443 (clobber (reg:CC 17))
3444 (clobber (match_scratch:SI 2 ""))]
3448 split_di (&operands[0], 1, &operands[3], &operands[4]);
3450 if (true_regnum (operands[3]) != true_regnum (operands[1]))
3451 emit_move_insn (operands[3], operands[1]);
3453 /* Generate a cltd if possible and doing so it profitable. */
3454 if (true_regnum (operands[3]) == 0
3455 && (optimize_size || TARGET_USE_CLTD))
3457 emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
3461 if (true_regnum (operands[4]) != true_regnum (operands[1]))
3462 emit_move_insn (operands[4], operands[1]);
3464 emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
3468 (define_insn "extendhisi2"
3469 [(set (match_operand:SI 0 "register_operand" "=*a,r")
3470 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm")))]
3473 switch (get_attr_prefix_0f (insn))
3476 return "{cwtl|cwde}";
3478 return "movs{wl|x}\t{%1,%0|%0, %1}";
3481 [(set_attr "type" "imovx")
3482 (set_attr "mode" "SI")
3483 (set (attr "prefix_0f")
3484 ;; movsx is short decodable while cwtl is vector decoded.
3485 (if_then_else (and (eq_attr "cpu" "!k6")
3486 (eq_attr "alternative" "0"))
3488 (const_string "1")))
3490 (if_then_else (eq_attr "prefix_0f" "0")
3492 (const_string "1")))])
3494 (define_insn "*extendhisi2_zext"
3495 [(set (match_operand:DI 0 "register_operand" "=*a,r")
3497 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "*0,rm"))))]
3500 switch (get_attr_prefix_0f (insn))
3503 return "{cwtl|cwde}";
3505 return "movs{wl|x}\t{%1,%k0|%k0, %1}";
3508 [(set_attr "type" "imovx")
3509 (set_attr "mode" "SI")
3510 (set (attr "prefix_0f")
3511 ;; movsx is short decodable while cwtl is vector decoded.
3512 (if_then_else (and (eq_attr "cpu" "!k6")
3513 (eq_attr "alternative" "0"))
3515 (const_string "1")))
3517 (if_then_else (eq_attr "prefix_0f" "0")
3519 (const_string "1")))])
3521 (define_insn "extendqihi2"
3522 [(set (match_operand:HI 0 "register_operand" "=*a,r")
3523 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "*0,qm")))]
3526 switch (get_attr_prefix_0f (insn))
3529 return "{cbtw|cbw}";
3531 return "movs{bw|x}\t{%1,%0|%0, %1}";
3534 [(set_attr "type" "imovx")
3535 (set_attr "mode" "HI")
3536 (set (attr "prefix_0f")
3537 ;; movsx is short decodable while cwtl is vector decoded.
3538 (if_then_else (and (eq_attr "cpu" "!k6")
3539 (eq_attr "alternative" "0"))
3541 (const_string "1")))
3543 (if_then_else (eq_attr "prefix_0f" "0")
3545 (const_string "1")))])
3547 (define_insn "extendqisi2"
3548 [(set (match_operand:SI 0 "register_operand" "=r")
3549 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
3551 "movs{bl|x}\t{%1,%0|%0, %1}"
3552 [(set_attr "type" "imovx")
3553 (set_attr "mode" "SI")])
3555 (define_insn "*extendqisi2_zext"
3556 [(set (match_operand:DI 0 "register_operand" "=r")
3558 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
3560 "movs{bl|x}\t{%1,%k0|%k0, %1}"
3561 [(set_attr "type" "imovx")
3562 (set_attr "mode" "SI")])
3564 ;; Conversions between float and double.
3566 ;; These are all no-ops in the model used for the 80387. So just
3569 ;; %%% Kill these when call knows how to work out a DFmode push earlier.
3570 (define_insn "*dummy_extendsfdf2"
3571 [(set (match_operand:DF 0 "push_operand" "=<")
3572 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
3577 [(set (match_operand:DF 0 "push_operand" "")
3578 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3580 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
3581 (set (mem:DF (reg:SI 7)) (float_extend:DF (match_dup 1)))])
3584 [(set (match_operand:DF 0 "push_operand" "")
3585 (float_extend:DF (match_operand:SF 1 "fp_register_operand" "")))]
3587 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
3588 (set (mem:DF (reg:DI 7)) (float_extend:DF (match_dup 1)))])
3590 (define_insn "*dummy_extendsfxf2"
3591 [(set (match_operand:XF 0 "push_operand" "=<")
3592 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3597 [(set (match_operand:XF 0 "push_operand" "")
3598 (float_extend:XF (match_operand:SF 1 "fp_register_operand" "")))]
3599 "!TARGET_128BIT_LONG_DOUBLE"
3600 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3601 (set (mem:XF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3603 (define_insn "*dummy_extendsftf2"
3604 [(set (match_operand:TF 0 "push_operand" "=<")
3605 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f")))]
3610 [(set (match_operand:TF 0 "push_operand" "")
3611 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3613 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3614 (set (mem:TF (reg:SI 7)) (float_extend:TF (match_dup 1)))])
3617 [(set (match_operand:TF 0 "push_operand" "")
3618 (float_extend:TF (match_operand:SF 1 "fp_register_operand" "")))]
3620 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3621 (set (mem:DF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3623 (define_insn "*dummy_extenddfxf2"
3624 [(set (match_operand:XF 0 "push_operand" "=<")
3625 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3630 [(set (match_operand:XF 0 "push_operand" "")
3631 (float_extend:XF (match_operand:DF 1 "fp_register_operand" "")))]
3632 "!TARGET_128BIT_LONG_DOUBLE"
3633 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -12)))
3634 (set (mem:DF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3636 (define_insn "*dummy_extenddftf2"
3637 [(set (match_operand:TF 0 "push_operand" "=<")
3638 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f")))]
3643 [(set (match_operand:TF 0 "push_operand" "")
3644 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3646 [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
3647 (set (mem:TF (reg:SI 7)) (float_extend:XF (match_dup 1)))])
3650 [(set (match_operand:TF 0 "push_operand" "")
3651 (float_extend:TF (match_operand:DF 1 "fp_register_operand" "")))]
3653 [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
3654 (set (mem:TF (reg:DI 7)) (float_extend:TF (match_dup 1)))])
3656 (define_expand "extendsfdf2"
3657 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3658 (float_extend:DF (match_operand:SF 1 "general_operand" "")))]
3659 "TARGET_80387 || TARGET_SSE2"
3661 /* ??? Needed for compress_float_constant since all fp constants
3662 are LEGITIMATE_CONSTANT_P. */
3663 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3664 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3665 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3666 operands[1] = force_reg (SFmode, operands[1]);
3669 (define_insn "*extendsfdf2_1"
3670 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#Y,mf#Y,Y#f")
3671 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm#Y,f#Y,mY#f")))]
3672 "(TARGET_80387 || TARGET_SSE2)
3673 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3675 switch (which_alternative)
3678 if (REG_P (operands[1])
3679 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3681 else if (STACK_TOP_P (operands[0]))
3682 return "fld%z1\t%y1";
3687 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3688 return "fstp%z0\t%y0";
3691 return "fst%z0\t%y0";
3693 return "cvtss2sd\t{%1, %0|%0, %1}";
3699 [(set_attr "type" "fmov,fmov,ssecvt")
3700 (set_attr "mode" "SF,XF,DF")])
3702 (define_insn "*extendsfdf2_1_sse_only"
3703 [(set (match_operand:DF 0 "register_operand" "=Y")
3704 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "mY")))]
3705 "!TARGET_80387 && TARGET_SSE2
3706 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3707 "cvtss2sd\t{%1, %0|%0, %1}"
3708 [(set_attr "type" "ssecvt")
3709 (set_attr "mode" "DF")])
3711 (define_expand "extendsfxf2"
3712 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3713 (float_extend:XF (match_operand:SF 1 "general_operand" "")))]
3714 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
3716 /* ??? Needed for compress_float_constant since all fp constants
3717 are LEGITIMATE_CONSTANT_P. */
3718 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3719 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3720 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3721 operands[1] = force_reg (SFmode, operands[1]);
3724 (define_insn "*extendsfxf2_1"
3725 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3726 (float_extend:XF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3727 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
3728 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3730 switch (which_alternative)
3733 if (REG_P (operands[1])
3734 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3736 else if (STACK_TOP_P (operands[0]))
3737 return "fld%z1\t%y1";
3742 /* There is no non-popping store to memory for XFmode. So if
3743 we need one, follow the store with a load. */
3744 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3745 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3747 return "fstp%z0\t%y0";
3753 [(set_attr "type" "fmov")
3754 (set_attr "mode" "SF,XF")])
3756 (define_expand "extendsftf2"
3757 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3758 (float_extend:TF (match_operand:SF 1 "general_operand" "")))]
3761 /* ??? Needed for compress_float_constant since all fp constants
3762 are LEGITIMATE_CONSTANT_P. */
3763 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3764 operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
3765 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3766 operands[1] = force_reg (SFmode, operands[1]);
3769 (define_insn "*extendsftf2_1"
3770 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3771 (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "fm,f")))]
3773 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3775 switch (which_alternative)
3778 if (REG_P (operands[1])
3779 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3781 else if (STACK_TOP_P (operands[0]))
3782 return "fld%z1\t%y1";
3787 /* There is no non-popping store to memory for XFmode. So if
3788 we need one, follow the store with a load. */
3789 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3790 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3792 return "fstp%z0\t%y0";
3798 [(set_attr "type" "fmov")
3799 (set_attr "mode" "SF,XF")])
3801 (define_expand "extenddfxf2"
3802 [(set (match_operand:XF 0 "nonimmediate_operand" "")
3803 (float_extend:XF (match_operand:DF 1 "general_operand" "")))]
3804 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
3806 /* ??? Needed for compress_float_constant since all fp constants
3807 are LEGITIMATE_CONSTANT_P. */
3808 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3809 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3810 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3811 operands[1] = force_reg (DFmode, operands[1]);
3814 (define_insn "*extenddfxf2_1"
3815 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m")
3816 (float_extend:XF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3817 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
3818 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3820 switch (which_alternative)
3823 if (REG_P (operands[1])
3824 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3826 else if (STACK_TOP_P (operands[0]))
3827 return "fld%z1\t%y1";
3832 /* There is no non-popping store to memory for XFmode. So if
3833 we need one, follow the store with a load. */
3834 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3835 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3837 return "fstp%z0\t%y0";
3843 [(set_attr "type" "fmov")
3844 (set_attr "mode" "DF,XF")])
3846 (define_expand "extenddftf2"
3847 [(set (match_operand:TF 0 "nonimmediate_operand" "")
3848 (float_extend:TF (match_operand:DF 1 "general_operand" "")))]
3851 /* ??? Needed for compress_float_constant since all fp constants
3852 are LEGITIMATE_CONSTANT_P. */
3853 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3854 operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
3855 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
3856 operands[1] = force_reg (DFmode, operands[1]);
3859 (define_insn "*extenddftf2_1"
3860 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,m")
3861 (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "fm,f")))]
3863 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3865 switch (which_alternative)
3868 if (REG_P (operands[1])
3869 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3871 else if (STACK_TOP_P (operands[0]))
3872 return "fld%z1\t%y1";
3877 /* There is no non-popping store to memory for XFmode. So if
3878 we need one, follow the store with a load. */
3879 if (! find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3880 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
3882 return "fstp%z0\t%y0";
3888 [(set_attr "type" "fmov")
3889 (set_attr "mode" "DF,XF")])
3891 ;; %%% This seems bad bad news.
3892 ;; This cannot output into an f-reg because there is no way to be sure
3893 ;; of truncating in that case. Otherwise this is just like a simple move
3894 ;; insn. So we pretend we can output to a reg in order to get better
3895 ;; register preferencing, but we really use a stack slot.
3897 (define_expand "truncdfsf2"
3898 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
3900 (match_operand:DF 1 "register_operand" "")))
3901 (clobber (match_dup 2))])]
3902 "TARGET_80387 || TARGET_SSE2"
3905 operands[2] = assign_386_stack_local (SFmode, 0);
3908 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
3913 (define_insn "*truncdfsf2_1"
3914 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
3916 (match_operand:DF 1 "register_operand" "f,f,f,f")))
3917 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
3918 "TARGET_80387 && !TARGET_SSE2"
3920 switch (which_alternative)
3923 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3924 return "fstp%z0\t%y0";
3926 return "fst%z0\t%y0";
3931 [(set_attr "type" "fmov,multi,multi,multi")
3932 (set_attr "mode" "SF,SF,SF,SF")])
3934 (define_insn "*truncdfsf2_1_sse"
3935 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m#fxr,?f#xr,?r#fx,?x#fr,Y#fr")
3937 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3938 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3939 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3941 switch (which_alternative)
3944 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3945 return "fstp%z0\t%y0";
3947 return "fst%z0\t%y0";
3954 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3955 (set_attr "mode" "SF,SF,SF,SF,DF")])
3957 (define_insn "*truncdfsf2_1_sse_nooverlap"
3958 [(set (match_operand:SF 0 "nonimmediate_operand" "=*!m,?f#rx,?r#fx,?x#rf,&Y")
3960 (match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
3961 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
3962 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
3964 switch (which_alternative)
3967 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3968 return "fstp%z0\t%y0";
3970 return "fst%z0\t%y0";
3977 [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
3978 (set_attr "mode" "SF,SF,SF,SF,DF")])
3980 (define_insn "*truncdfsf2_2"
3981 [(set (match_operand:SF 0 "nonimmediate_operand" "=Y,Y,!m")
3983 (match_operand:DF 1 "nonimmediate_operand" "Y,mY,f#Y")))]
3984 "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
3985 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
3987 switch (which_alternative)
3991 return "cvtsd2ss\t{%1, %0|%0, %1}";
3993 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
3994 return "fstp%z0\t%y0";
3996 return "fst%z0\t%y0";
4001 [(set_attr "type" "ssecvt,ssecvt,fmov")
4002 (set_attr "athlon_decode" "vector,double,*")
4003 (set_attr "mode" "SF,SF,SF")])
4005 (define_insn "*truncdfsf2_2_nooverlap"
4006 [(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
4008 (match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
4009 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS
4010 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
4012 switch (which_alternative)
4017 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4018 return "fstp%z0\t%y0";
4020 return "fst%z0\t%y0";
4025 [(set_attr "type" "ssecvt,fmov")
4026 (set_attr "mode" "DF,SF")])
4028 (define_insn "*truncdfsf2_3"
4029 [(set (match_operand:SF 0 "memory_operand" "=m")
4031 (match_operand:DF 1 "register_operand" "f")))]
4034 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4035 return "fstp%z0\t%y0";
4037 return "fst%z0\t%y0";
4039 [(set_attr "type" "fmov")
4040 (set_attr "mode" "SF")])
4042 (define_insn "truncdfsf2_sse_only"
4043 [(set (match_operand:SF 0 "register_operand" "=Y,Y")
4045 (match_operand:DF 1 "nonimmediate_operand" "Y,mY")))]
4046 "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4047 "cvtsd2ss\t{%1, %0|%0, %1}"
4048 [(set_attr "type" "ssecvt")
4049 (set_attr "athlon_decode" "vector,double")
4050 (set_attr "mode" "SF")])
4052 (define_insn "*truncdfsf2_sse_only_nooverlap"
4053 [(set (match_operand:SF 0 "register_operand" "=&Y")
4055 (match_operand:DF 1 "nonimmediate_operand" "mY")))]
4056 "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4058 [(set_attr "type" "ssecvt")
4059 (set_attr "mode" "DF")])
4062 [(set (match_operand:SF 0 "memory_operand" "")
4064 (match_operand:DF 1 "register_operand" "")))
4065 (clobber (match_operand:SF 2 "memory_operand" ""))]
4067 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4070 ; Avoid possible reformatting penalty on the destination by first
4073 [(set (match_operand:SF 0 "register_operand" "")
4075 (match_operand:DF 1 "nonimmediate_operand" "")))
4076 (clobber (match_operand 2 "" ""))]
4077 "TARGET_80387 && reload_completed
4078 && SSE_REG_P (operands[0])
4079 && !STACK_REG_P (operands[1])"
4083 if (!TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS)
4084 emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
4087 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4088 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4089 /* simplify_gen_subreg refuses to widen memory references. */
4090 if (GET_CODE (src) == SUBREG)
4091 alter_subreg (&src);
4092 if (reg_overlap_mentioned_p (operands[0], operands[1]))
4094 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4095 emit_insn (gen_cvtsd2ss (dest, dest, src));
4101 [(set (match_operand:SF 0 "register_operand" "")
4103 (match_operand:DF 1 "nonimmediate_operand" "")))]
4104 "TARGET_80387 && reload_completed
4105 && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS"
4109 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4110 src = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0);
4111 /* simplify_gen_subreg refuses to widen memory references. */
4112 if (GET_CODE (src) == SUBREG)
4113 alter_subreg (&src);
4114 if (reg_overlap_mentioned_p (operands[0], operands[1]))
4116 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4117 emit_insn (gen_cvtsd2ss (dest, dest, src));
4122 [(set (match_operand:SF 0 "register_operand" "")
4124 (match_operand:DF 1 "fp_register_operand" "")))
4125 (clobber (match_operand:SF 2 "memory_operand" ""))]
4126 "TARGET_80387 && reload_completed"
4127 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4128 (set (match_dup 0) (match_dup 2))]
4131 (define_expand "truncxfsf2"
4132 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4134 (match_operand:XF 1 "register_operand" "")))
4135 (clobber (match_dup 2))])]
4136 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
4137 "operands[2] = assign_386_stack_local (SFmode, 0);")
4139 (define_insn "*truncxfsf2_1"
4140 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4142 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4143 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4144 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
4146 switch (which_alternative)
4149 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4150 return "fstp%z0\t%y0";
4152 return "fst%z0\t%y0";
4157 [(set_attr "type" "fmov,multi,multi,multi")
4158 (set_attr "mode" "SF")])
4160 (define_insn "*truncxfsf2_2"
4161 [(set (match_operand:SF 0 "memory_operand" "=m")
4163 (match_operand:XF 1 "register_operand" "f")))]
4164 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
4166 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4167 return "fstp%z0\t%y0";
4169 return "fst%z0\t%y0";
4171 [(set_attr "type" "fmov")
4172 (set_attr "mode" "SF")])
4175 [(set (match_operand:SF 0 "memory_operand" "")
4177 (match_operand:XF 1 "register_operand" "")))
4178 (clobber (match_operand:SF 2 "memory_operand" ""))]
4180 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4184 [(set (match_operand:SF 0 "register_operand" "")
4186 (match_operand:XF 1 "register_operand" "")))
4187 (clobber (match_operand:SF 2 "memory_operand" ""))]
4188 "TARGET_80387 && reload_completed"
4189 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4190 (set (match_dup 0) (match_dup 2))]
4193 (define_expand "trunctfsf2"
4194 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
4196 (match_operand:TF 1 "register_operand" "")))
4197 (clobber (match_dup 2))])]
4199 "operands[2] = assign_386_stack_local (SFmode, 0);")
4201 (define_insn "*trunctfsf2_1"
4202 [(set (match_operand:SF 0 "nonimmediate_operand" "=m,?f#rx,?r#fx,?x#rf")
4204 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4205 (clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m"))]
4208 switch (which_alternative)
4211 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4212 return "fstp%z0\t%y0";
4214 return "fst%z0\t%y0";
4219 [(set_attr "type" "fmov,multi,multi,multi")
4220 (set_attr "mode" "SF")])
4222 (define_insn "*trunctfsf2_2"
4223 [(set (match_operand:SF 0 "memory_operand" "=m")
4225 (match_operand:TF 1 "register_operand" "f")))]
4228 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4229 return "fstp%z0\t%y0";
4231 return "fst%z0\t%y0";
4233 [(set_attr "type" "fmov")
4234 (set_attr "mode" "SF")])
4237 [(set (match_operand:SF 0 "memory_operand" "")
4239 (match_operand:TF 1 "register_operand" "")))
4240 (clobber (match_operand:SF 2 "memory_operand" ""))]
4242 [(set (match_dup 0) (float_truncate:SF (match_dup 1)))]
4246 [(set (match_operand:SF 0 "register_operand" "")
4248 (match_operand:TF 1 "register_operand" "")))
4249 (clobber (match_operand:SF 2 "memory_operand" ""))]
4250 "TARGET_80387 && reload_completed"
4251 [(set (match_dup 2) (float_truncate:SF (match_dup 1)))
4252 (set (match_dup 0) (match_dup 2))]
4256 (define_expand "truncxfdf2"
4257 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4259 (match_operand:XF 1 "register_operand" "")))
4260 (clobber (match_dup 2))])]
4261 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
4262 "operands[2] = assign_386_stack_local (DFmode, 0);")
4264 (define_insn "*truncxfdf2_1"
4265 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4267 (match_operand:XF 1 "register_operand" "f,f,f,f")))
4268 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4269 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
4271 switch (which_alternative)
4274 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4275 return "fstp%z0\t%y0";
4277 return "fst%z0\t%y0";
4283 [(set_attr "type" "fmov,multi,multi,multi")
4284 (set_attr "mode" "DF")])
4286 (define_insn "*truncxfdf2_2"
4287 [(set (match_operand:DF 0 "memory_operand" "=m")
4289 (match_operand:XF 1 "register_operand" "f")))]
4290 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
4292 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4293 return "fstp%z0\t%y0";
4295 return "fst%z0\t%y0";
4297 [(set_attr "type" "fmov")
4298 (set_attr "mode" "DF")])
4301 [(set (match_operand:DF 0 "memory_operand" "")
4303 (match_operand:XF 1 "register_operand" "")))
4304 (clobber (match_operand:DF 2 "memory_operand" ""))]
4306 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4310 [(set (match_operand:DF 0 "register_operand" "")
4312 (match_operand:XF 1 "register_operand" "")))
4313 (clobber (match_operand:DF 2 "memory_operand" ""))]
4314 "TARGET_80387 && reload_completed"
4315 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4316 (set (match_dup 0) (match_dup 2))]
4319 (define_expand "trunctfdf2"
4320 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
4322 (match_operand:TF 1 "register_operand" "")))
4323 (clobber (match_dup 2))])]
4325 "operands[2] = assign_386_stack_local (DFmode, 0);")
4327 (define_insn "*trunctfdf2_1"
4328 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f#rY,?r#fY,?Y#rf")
4330 (match_operand:TF 1 "register_operand" "f,f,f,f")))
4331 (clobber (match_operand:DF 2 "memory_operand" "=X,m,m,m"))]
4334 switch (which_alternative)
4337 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4338 return "fstp%z0\t%y0";
4340 return "fst%z0\t%y0";
4346 [(set_attr "type" "fmov,multi,multi,multi")
4347 (set_attr "mode" "DF")])
4349 (define_insn "*trunctfdf2_2"
4350 [(set (match_operand:DF 0 "memory_operand" "=m")
4352 (match_operand:TF 1 "register_operand" "f")))]
4355 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
4356 return "fstp%z0\t%y0";
4358 return "fst%z0\t%y0";
4360 [(set_attr "type" "fmov")
4361 (set_attr "mode" "DF")])
4364 [(set (match_operand:DF 0 "memory_operand" "")
4366 (match_operand:TF 1 "register_operand" "")))
4367 (clobber (match_operand:DF 2 "memory_operand" ""))]
4369 [(set (match_dup 0) (float_truncate:DF (match_dup 1)))]
4373 [(set (match_operand:DF 0 "register_operand" "")
4375 (match_operand:TF 1 "register_operand" "")))
4376 (clobber (match_operand:DF 2 "memory_operand" ""))]
4377 "TARGET_80387 && reload_completed"
4378 [(set (match_dup 2) (float_truncate:DF (match_dup 1)))
4379 (set (match_dup 0) (match_dup 2))]
4383 ;; %%% Break up all these bad boys.
4385 ;; Signed conversion to DImode.
4387 (define_expand "fix_truncxfdi2"
4388 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4389 (fix:DI (match_operand:XF 1 "register_operand" "")))]
4390 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
4393 (define_expand "fix_trunctfdi2"
4394 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4395 (fix:DI (match_operand:TF 1 "register_operand" "")))]
4399 (define_expand "fix_truncdfdi2"
4400 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4401 (fix:DI (match_operand:DF 1 "register_operand" "")))]
4402 "TARGET_80387 || (TARGET_SSE2 && TARGET_64BIT)"
4404 if (TARGET_64BIT && TARGET_SSE2)
4406 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4407 emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
4408 if (out != operands[0])
4409 emit_move_insn (operands[0], out);
4414 (define_expand "fix_truncsfdi2"
4415 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4416 (fix:DI (match_operand:SF 1 "register_operand" "")))]
4417 "TARGET_80387 || (TARGET_SSE && TARGET_64BIT)"
4419 if (TARGET_SSE && TARGET_64BIT)
4421 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
4422 emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
4423 if (out != operands[0])
4424 emit_move_insn (operands[0], out);
4429 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4430 ;; of the machinery.
4431 (define_insn_and_split "*fix_truncdi_1"
4432 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4433 (fix:DI (match_operand 1 "register_operand" "f,f")))]
4434 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4435 && !reload_completed && !reload_in_progress
4436 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4441 ix86_optimize_mode_switching = 1;
4442 operands[2] = assign_386_stack_local (HImode, 1);
4443 operands[3] = assign_386_stack_local (HImode, 2);
4444 if (memory_operand (operands[0], VOIDmode))
4445 emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
4446 operands[2], operands[3]));
4449 operands[4] = assign_386_stack_local (DImode, 0);
4450 emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
4451 operands[2], operands[3],
4456 [(set_attr "type" "fistp")
4457 (set_attr "mode" "DI")])
4459 (define_insn "fix_truncdi_nomemory"
4460 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,?r")
4461 (fix:DI (match_operand 1 "register_operand" "f,f")))
4462 (use (match_operand:HI 2 "memory_operand" "m,m"))
4463 (use (match_operand:HI 3 "memory_operand" "m,m"))
4464 (clobber (match_operand:DI 4 "memory_operand" "=m,m"))
4465 (clobber (match_scratch:DF 5 "=&1f,&1f"))]
4466 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4467 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4469 [(set_attr "type" "fistp")
4470 (set_attr "mode" "DI")])
4472 (define_insn "fix_truncdi_memory"
4473 [(set (match_operand:DI 0 "memory_operand" "=m")
4474 (fix:DI (match_operand 1 "register_operand" "f")))
4475 (use (match_operand:HI 2 "memory_operand" "m"))
4476 (use (match_operand:HI 3 "memory_operand" "m"))
4477 (clobber (match_scratch:DF 4 "=&1f"))]
4478 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4479 && (!SSE_FLOAT_MODE_P (GET_MODE (operands[1])) || !TARGET_64BIT)"
4480 "* operands[5] = operands[4]; return output_fix_trunc (insn, operands);"
4481 [(set_attr "type" "fistp")
4482 (set_attr "mode" "DI")])
4485 [(set (match_operand:DI 0 "register_operand" "")
4486 (fix:DI (match_operand 1 "register_operand" "")))
4487 (use (match_operand:HI 2 "memory_operand" ""))
4488 (use (match_operand:HI 3 "memory_operand" ""))
4489 (clobber (match_operand:DI 4 "memory_operand" ""))
4490 (clobber (match_scratch 5 ""))]
4492 [(parallel [(set (match_dup 4) (fix:DI (match_dup 1)))
4495 (clobber (match_dup 5))])
4496 (set (match_dup 0) (match_dup 4))]
4500 [(set (match_operand:DI 0 "memory_operand" "")
4501 (fix:DI (match_operand 1 "register_operand" "")))
4502 (use (match_operand:HI 2 "memory_operand" ""))
4503 (use (match_operand:HI 3 "memory_operand" ""))
4504 (clobber (match_operand:DI 4 "memory_operand" ""))
4505 (clobber (match_scratch 5 ""))]
4507 [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
4510 (clobber (match_dup 5))])]
4513 ;; When SSE available, it is always faster to use it!
4514 (define_insn "fix_truncsfdi_sse"
4515 [(set (match_operand:DI 0 "register_operand" "=r,r")
4516 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4517 "TARGET_64BIT && TARGET_SSE"
4518 "cvttss2si{q}\t{%1, %0|%0, %1}"
4519 [(set_attr "type" "sseicvt")
4520 (set_attr "mode" "SF")
4521 (set_attr "athlon_decode" "double,vector")])
4523 ;; Avoid vector decoded form of the instruction.
4525 [(match_scratch:SF 2 "x")
4526 (set (match_operand:DI 0 "register_operand" "")
4527 (fix:DI (match_operand:SF 1 "memory_operand" "")))]
4528 "TARGET_K8 && !optimize_size"
4529 [(set (match_dup 2) (match_dup 1))
4530 (set (match_dup 0) (fix:DI (match_dup 2)))]
4533 (define_insn "fix_truncdfdi_sse"
4534 [(set (match_operand:DI 0 "register_operand" "=r,r")
4535 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4536 "TARGET_64BIT && TARGET_SSE2"
4537 "cvttsd2si{q}\t{%1, %0|%0, %1}"
4538 [(set_attr "type" "sseicvt,sseicvt")
4539 (set_attr "mode" "DF")
4540 (set_attr "athlon_decode" "double,vector")])
4542 ;; Avoid vector decoded form of the instruction.
4544 [(match_scratch:DF 2 "Y")
4545 (set (match_operand:DI 0 "register_operand" "")
4546 (fix:DI (match_operand:DF 1 "memory_operand" "")))]
4547 "TARGET_K8 && !optimize_size"
4548 [(set (match_dup 2) (match_dup 1))
4549 (set (match_dup 0) (fix:DI (match_dup 2)))]
4552 ;; Signed conversion to SImode.
4554 (define_expand "fix_truncxfsi2"
4555 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4556 (fix:SI (match_operand:XF 1 "register_operand" "")))]
4557 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
4560 (define_expand "fix_trunctfsi2"
4561 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4562 (fix:SI (match_operand:TF 1 "register_operand" "")))]
4566 (define_expand "fix_truncdfsi2"
4567 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4568 (fix:SI (match_operand:DF 1 "register_operand" "")))]
4569 "TARGET_80387 || TARGET_SSE2"
4573 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4574 emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
4575 if (out != operands[0])
4576 emit_move_insn (operands[0], out);
4581 (define_expand "fix_truncsfsi2"
4582 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4583 (fix:SI (match_operand:SF 1 "register_operand" "")))]
4584 "TARGET_80387 || TARGET_SSE"
4588 rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
4589 emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
4590 if (out != operands[0])
4591 emit_move_insn (operands[0], out);
4596 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4597 ;; of the machinery.
4598 (define_insn_and_split "*fix_truncsi_1"
4599 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4600 (fix:SI (match_operand 1 "register_operand" "f,f")))]
4601 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4602 && !reload_completed && !reload_in_progress
4603 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4608 ix86_optimize_mode_switching = 1;
4609 operands[2] = assign_386_stack_local (HImode, 1);
4610 operands[3] = assign_386_stack_local (HImode, 2);
4611 if (memory_operand (operands[0], VOIDmode))
4612 emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
4613 operands[2], operands[3]));
4616 operands[4] = assign_386_stack_local (SImode, 0);
4617 emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
4618 operands[2], operands[3],
4623 [(set_attr "type" "fistp")
4624 (set_attr "mode" "SI")])
4626 (define_insn "fix_truncsi_nomemory"
4627 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?r")
4628 (fix:SI (match_operand 1 "register_operand" "f,f")))
4629 (use (match_operand:HI 2 "memory_operand" "m,m"))
4630 (use (match_operand:HI 3 "memory_operand" "m,m"))
4631 (clobber (match_operand:SI 4 "memory_operand" "=m,m"))]
4632 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4633 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4635 [(set_attr "type" "fistp")
4636 (set_attr "mode" "SI")])
4638 (define_insn "fix_truncsi_memory"
4639 [(set (match_operand:SI 0 "memory_operand" "=m")
4640 (fix:SI (match_operand 1 "register_operand" "f")))
4641 (use (match_operand:HI 2 "memory_operand" "m"))
4642 (use (match_operand:HI 3 "memory_operand" "m"))]
4643 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4644 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4645 "* return output_fix_trunc (insn, operands);"
4646 [(set_attr "type" "fistp")
4647 (set_attr "mode" "SI")])
4649 ;; When SSE available, it is always faster to use it!
4650 (define_insn "fix_truncsfsi_sse"
4651 [(set (match_operand:SI 0 "register_operand" "=r,r")
4652 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "x,xm")))]
4654 "cvttss2si\t{%1, %0|%0, %1}"
4655 [(set_attr "type" "sseicvt")
4656 (set_attr "mode" "DF")
4657 (set_attr "athlon_decode" "double,vector")])
4659 ;; Avoid vector decoded form of the instruction.
4661 [(match_scratch:SF 2 "x")
4662 (set (match_operand:SI 0 "register_operand" "")
4663 (fix:SI (match_operand:SF 1 "memory_operand" "")))]
4664 "TARGET_K8 && !optimize_size"
4665 [(set (match_dup 2) (match_dup 1))
4666 (set (match_dup 0) (fix:SI (match_dup 2)))]
4669 (define_insn "fix_truncdfsi_sse"
4670 [(set (match_operand:SI 0 "register_operand" "=r,r")
4671 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "Y,Ym")))]
4673 "cvttsd2si\t{%1, %0|%0, %1}"
4674 [(set_attr "type" "sseicvt")
4675 (set_attr "mode" "DF")
4676 (set_attr "athlon_decode" "double,vector")])
4678 ;; Avoid vector decoded form of the instruction.
4680 [(match_scratch:DF 2 "Y")
4681 (set (match_operand:SI 0 "register_operand" "")
4682 (fix:SI (match_operand:DF 1 "memory_operand" "")))]
4683 "TARGET_K8 && !optimize_size"
4684 [(set (match_dup 2) (match_dup 1))
4685 (set (match_dup 0) (fix:SI (match_dup 2)))]
4689 [(set (match_operand:SI 0 "register_operand" "")
4690 (fix:SI (match_operand 1 "register_operand" "")))
4691 (use (match_operand:HI 2 "memory_operand" ""))
4692 (use (match_operand:HI 3 "memory_operand" ""))
4693 (clobber (match_operand:SI 4 "memory_operand" ""))]
4695 [(parallel [(set (match_dup 4) (fix:SI (match_dup 1)))
4697 (use (match_dup 3))])
4698 (set (match_dup 0) (match_dup 4))]
4702 [(set (match_operand:SI 0 "memory_operand" "")
4703 (fix:SI (match_operand 1 "register_operand" "")))
4704 (use (match_operand:HI 2 "memory_operand" ""))
4705 (use (match_operand:HI 3 "memory_operand" ""))
4706 (clobber (match_operand:SI 4 "memory_operand" ""))]
4708 [(parallel [(set (match_dup 0) (fix:SI (match_dup 1)))
4710 (use (match_dup 3))])]
4713 ;; Signed conversion to HImode.
4715 (define_expand "fix_truncxfhi2"
4716 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4717 (fix:HI (match_operand:XF 1 "register_operand" "")))]
4718 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
4721 (define_expand "fix_trunctfhi2"
4722 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4723 (fix:HI (match_operand:TF 1 "register_operand" "")))]
4727 (define_expand "fix_truncdfhi2"
4728 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4729 (fix:HI (match_operand:DF 1 "register_operand" "")))]
4730 "TARGET_80387 && !TARGET_SSE2"
4733 (define_expand "fix_truncsfhi2"
4734 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4735 (fix:HI (match_operand:SF 1 "register_operand" "")))]
4736 "TARGET_80387 && !TARGET_SSE"
4739 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
4740 ;; of the machinery.
4741 (define_insn_and_split "*fix_trunchi_1"
4742 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4743 (fix:HI (match_operand 1 "register_operand" "f,f")))]
4744 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4745 && !reload_completed && !reload_in_progress
4746 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4751 ix86_optimize_mode_switching = 1;
4752 operands[2] = assign_386_stack_local (HImode, 1);
4753 operands[3] = assign_386_stack_local (HImode, 2);
4754 if (memory_operand (operands[0], VOIDmode))
4755 emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
4756 operands[2], operands[3]));
4759 operands[4] = assign_386_stack_local (HImode, 0);
4760 emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
4761 operands[2], operands[3],
4766 [(set_attr "type" "fistp")
4767 (set_attr "mode" "HI")])
4769 (define_insn "fix_trunchi_nomemory"
4770 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,?r")
4771 (fix:HI (match_operand 1 "register_operand" "f,f")))
4772 (use (match_operand:HI 2 "memory_operand" "m,m"))
4773 (use (match_operand:HI 3 "memory_operand" "m,m"))
4774 (clobber (match_operand:HI 4 "memory_operand" "=m,m"))]
4775 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4776 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4778 [(set_attr "type" "fistp")
4779 (set_attr "mode" "HI")])
4781 (define_insn "fix_trunchi_memory"
4782 [(set (match_operand:HI 0 "memory_operand" "=m")
4783 (fix:HI (match_operand 1 "register_operand" "f")))
4784 (use (match_operand:HI 2 "memory_operand" "m"))
4785 (use (match_operand:HI 3 "memory_operand" "m"))]
4786 "TARGET_80387 && FLOAT_MODE_P (GET_MODE (operands[1]))
4787 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))"
4788 "* return output_fix_trunc (insn, operands);"
4789 [(set_attr "type" "fistp")
4790 (set_attr "mode" "HI")])
4793 [(set (match_operand:HI 0 "memory_operand" "")
4794 (fix:HI (match_operand 1 "register_operand" "")))
4795 (use (match_operand:HI 2 "memory_operand" ""))
4796 (use (match_operand:HI 3 "memory_operand" ""))
4797 (clobber (match_operand:HI 4 "memory_operand" ""))]
4799 [(parallel [(set (match_dup 0) (fix:HI (match_dup 1)))
4801 (use (match_dup 3))])]
4805 [(set (match_operand:HI 0 "register_operand" "")
4806 (fix:HI (match_operand 1 "register_operand" "")))
4807 (use (match_operand:HI 2 "memory_operand" ""))
4808 (use (match_operand:HI 3 "memory_operand" ""))
4809 (clobber (match_operand:HI 4 "memory_operand" ""))]
4811 [(parallel [(set (match_dup 4) (fix:HI (match_dup 1)))
4814 (clobber (match_dup 4))])
4815 (set (match_dup 0) (match_dup 4))]
4819 (define_insn "x86_fnstcw_1"
4820 [(set (match_operand:HI 0 "memory_operand" "=m")
4821 (unspec:HI [(reg:HI 18)] UNSPEC_FSTCW))]
4824 [(set_attr "length" "2")
4825 (set_attr "mode" "HI")
4826 (set_attr "unit" "i387")
4827 (set_attr "ppro_uops" "few")])
4829 (define_insn "x86_fldcw_1"
4831 (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
4834 [(set_attr "length" "2")
4835 (set_attr "mode" "HI")
4836 (set_attr "unit" "i387")
4837 (set_attr "athlon_decode" "vector")
4838 (set_attr "ppro_uops" "few")])
4840 ;; Conversion between fixed point and floating point.
4842 ;; Even though we only accept memory inputs, the backend _really_
4843 ;; wants to be able to do this between registers.
4845 (define_expand "floathisf2"
4846 [(set (match_operand:SF 0 "register_operand" "")
4847 (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
4848 "TARGET_SSE || TARGET_80387"
4850 if (TARGET_SSE && TARGET_SSE_MATH)
4852 emit_insn (gen_floatsisf2 (operands[0],
4853 convert_to_mode (SImode, operands[1], 0)));
4858 (define_insn "*floathisf2_1"
4859 [(set (match_operand:SF 0 "register_operand" "=f,f")
4860 (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4861 "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
4865 [(set_attr "type" "fmov,multi")
4866 (set_attr "mode" "SF")
4867 (set_attr "fp_int_src" "true")])
4869 (define_expand "floatsisf2"
4870 [(set (match_operand:SF 0 "register_operand" "")
4871 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4872 "TARGET_SSE || TARGET_80387"
4875 (define_insn "*floatsisf2_i387"
4876 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4877 (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
4878 "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4882 cvtsi2ss\t{%1, %0|%0, %1}
4883 cvtsi2ss\t{%1, %0|%0, %1}"
4884 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4885 (set_attr "mode" "SF")
4886 (set_attr "athlon_decode" "*,*,vector,double")
4887 (set_attr "fp_int_src" "true")])
4889 (define_insn "*floatsisf2_sse"
4890 [(set (match_operand:SF 0 "register_operand" "=x,x")
4891 (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
4893 "cvtsi2ss\t{%1, %0|%0, %1}"
4894 [(set_attr "type" "sseicvt")
4895 (set_attr "mode" "SF")
4896 (set_attr "athlon_decode" "vector,double")
4897 (set_attr "fp_int_src" "true")])
4899 ; Avoid possible reformatting penalty on the destination by first
4902 [(set (match_operand:SF 0 "register_operand" "")
4903 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
4904 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4905 && SSE_REG_P (operands[0])"
4909 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4910 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4911 emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
4915 (define_expand "floatdisf2"
4916 [(set (match_operand:SF 0 "register_operand" "")
4917 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4918 "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
4921 (define_insn "*floatdisf2_i387_only"
4922 [(set (match_operand:SF 0 "register_operand" "=f,?f")
4923 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
4924 "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
4928 [(set_attr "type" "fmov,multi")
4929 (set_attr "mode" "SF")
4930 (set_attr "fp_int_src" "true")])
4932 (define_insn "*floatdisf2_i387"
4933 [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
4934 (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
4935 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
4939 cvtsi2ss{q}\t{%1, %0|%0, %1}
4940 cvtsi2ss{q}\t{%1, %0|%0, %1}"
4941 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
4942 (set_attr "mode" "SF")
4943 (set_attr "athlon_decode" "*,*,vector,double")
4944 (set_attr "fp_int_src" "true")])
4946 (define_insn "*floatdisf2_sse"
4947 [(set (match_operand:SF 0 "register_operand" "=x,x")
4948 (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
4949 "TARGET_64BIT && TARGET_SSE"
4950 "cvtsi2ss{q}\t{%1, %0|%0, %1}"
4951 [(set_attr "type" "sseicvt")
4952 (set_attr "mode" "SF")
4953 (set_attr "athlon_decode" "vector,double")
4954 (set_attr "fp_int_src" "true")])
4956 ; Avoid possible reformatting penalty on the destination by first
4959 [(set (match_operand:SF 0 "register_operand" "")
4960 (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
4961 "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
4962 && SSE_REG_P (operands[0])"
4966 dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
4967 emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
4968 emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
4972 (define_expand "floathidf2"
4973 [(set (match_operand:DF 0 "register_operand" "")
4974 (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
4975 "TARGET_SSE2 || TARGET_80387"
4977 if (TARGET_SSE && TARGET_SSE_MATH)
4979 emit_insn (gen_floatsidf2 (operands[0],
4980 convert_to_mode (SImode, operands[1], 0)));
4985 (define_insn "*floathidf2_1"
4986 [(set (match_operand:DF 0 "register_operand" "=f,f")
4987 (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
4988 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
4992 [(set_attr "type" "fmov,multi")
4993 (set_attr "mode" "DF")
4994 (set_attr "fp_int_src" "true")])
4996 (define_expand "floatsidf2"
4997 [(set (match_operand:DF 0 "register_operand" "")
4998 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))]
4999 "TARGET_80387 || TARGET_SSE2"
5002 (define_insn "*floatsidf2_i387"
5003 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
5004 (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
5005 "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5009 cvtsi2sd\t{%1, %0|%0, %1}
5010 cvtsi2sd\t{%1, %0|%0, %1}"
5011 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
5012 (set_attr "mode" "DF")
5013 (set_attr "athlon_decode" "*,*,double,direct")
5014 (set_attr "fp_int_src" "true")])
5016 (define_insn "*floatsidf2_sse"
5017 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
5018 (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
5020 "cvtsi2sd\t{%1, %0|%0, %1}"
5021 [(set_attr "type" "sseicvt")
5022 (set_attr "mode" "DF")
5023 (set_attr "athlon_decode" "double,direct")
5024 (set_attr "fp_int_src" "true")])
5026 (define_expand "floatdidf2"
5027 [(set (match_operand:DF 0 "register_operand" "")
5028 (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
5029 "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
5032 (define_insn "*floatdidf2_i387_only"
5033 [(set (match_operand:DF 0 "register_operand" "=f,?f")
5034 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5035 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
5039 [(set_attr "type" "fmov,multi")
5040 (set_attr "mode" "DF")
5041 (set_attr "fp_int_src" "true")])
5043 (define_insn "*floatdidf2_i387"
5044 [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
5045 (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
5046 "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
5050 cvtsi2sd{q}\t{%1, %0|%0, %1}
5051 cvtsi2sd{q}\t{%1, %0|%0, %1}"
5052 [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
5053 (set_attr "mode" "DF")
5054 (set_attr "athlon_decode" "*,*,double,direct")
5055 (set_attr "fp_int_src" "true")])
5057 (define_insn "*floatdidf2_sse"
5058 [(set (match_operand:DF 0 "register_operand" "=Y,Y")
5059 (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
5061 "cvtsi2sd{q}\t{%1, %0|%0, %1}"
5062 [(set_attr "type" "sseicvt")
5063 (set_attr "mode" "DF")
5064 (set_attr "athlon_decode" "double,direct")
5065 (set_attr "fp_int_src" "true")])
5067 (define_insn "floathixf2"
5068 [(set (match_operand:XF 0 "register_operand" "=f,f")
5069 (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5070 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
5074 [(set_attr "type" "fmov,multi")
5075 (set_attr "mode" "XF")
5076 (set_attr "fp_int_src" "true")])
5078 (define_insn "floathitf2"
5079 [(set (match_operand:TF 0 "register_operand" "=f,f")
5080 (float:TF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
5085 [(set_attr "type" "fmov,multi")
5086 (set_attr "mode" "XF")
5087 (set_attr "fp_int_src" "true")])
5089 (define_insn "floatsixf2"
5090 [(set (match_operand:XF 0 "register_operand" "=f,f")
5091 (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5092 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
5096 [(set_attr "type" "fmov,multi")
5097 (set_attr "mode" "XF")
5098 (set_attr "fp_int_src" "true")])
5100 (define_insn "floatsitf2"
5101 [(set (match_operand:TF 0 "register_operand" "=f,f")
5102 (float:TF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
5107 [(set_attr "type" "fmov,multi")
5108 (set_attr "mode" "XF")
5109 (set_attr "fp_int_src" "true")])
5111 (define_insn "floatdixf2"
5112 [(set (match_operand:XF 0 "register_operand" "=f,f")
5113 (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5114 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
5118 [(set_attr "type" "fmov,multi")
5119 (set_attr "mode" "XF")
5120 (set_attr "fp_int_src" "true")])
5122 (define_insn "floatditf2"
5123 [(set (match_operand:TF 0 "register_operand" "=f,f")
5124 (float:TF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
5129 [(set_attr "type" "fmov,multi")
5130 (set_attr "mode" "XF")
5131 (set_attr "fp_int_src" "true")])
5133 ;; %%% Kill these when reload knows how to do it.
5135 [(set (match_operand 0 "fp_register_operand" "")
5136 (float (match_operand 1 "register_operand" "")))]
5137 "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
5140 operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
5141 operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
5142 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
5143 ix86_free_from_memory (GET_MODE (operands[1]));
5147 (define_expand "floatunssisf2"
5148 [(use (match_operand:SF 0 "register_operand" ""))
5149 (use (match_operand:SI 1 "register_operand" ""))]
5150 "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
5151 "x86_emit_floatuns (operands); DONE;")
5153 (define_expand "floatunsdisf2"
5154 [(use (match_operand:SF 0 "register_operand" ""))
5155 (use (match_operand:DI 1 "register_operand" ""))]
5156 "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
5157 "x86_emit_floatuns (operands); DONE;")
5159 (define_expand "floatunsdidf2"
5160 [(use (match_operand:DF 0 "register_operand" ""))
5161 (use (match_operand:DI 1 "register_operand" ""))]
5162 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
5163 "x86_emit_floatuns (operands); DONE;")
5167 ;; %%% splits for addsidi3
5168 ; [(set (match_operand:DI 0 "nonimmediate_operand" "")
5169 ; (plus:DI (match_operand:DI 1 "general_operand" "")
5170 ; (zero_extend:DI (match_operand:SI 2 "general_operand" ""))))]
5172 (define_expand "adddi3"
5173 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5174 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5175 (match_operand:DI 2 "x86_64_general_operand" "")))
5176 (clobber (reg:CC 17))]
5178 "ix86_expand_binary_operator (PLUS, DImode, operands); DONE;")
5180 (define_insn "*adddi3_1"
5181 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
5182 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5183 (match_operand:DI 2 "general_operand" "roiF,riF")))
5184 (clobber (reg:CC 17))]
5185 "!TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5189 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5190 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
5191 (match_operand:DI 2 "general_operand" "")))
5192 (clobber (reg:CC 17))]
5193 "!TARGET_64BIT && reload_completed"
5194 [(parallel [(set (reg:CC 17) (unspec:CC [(match_dup 1) (match_dup 2)]
5196 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
5197 (parallel [(set (match_dup 3)
5198 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
5201 (clobber (reg:CC 17))])]
5202 "split_di (operands+0, 1, operands+0, operands+3);
5203 split_di (operands+1, 1, operands+1, operands+4);
5204 split_di (operands+2, 1, operands+2, operands+5);")
5206 (define_insn "adddi3_carry_rex64"
5207 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5208 (plus:DI (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
5209 (match_operand:DI 1 "nonimmediate_operand" "%0,0"))
5210 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
5211 (clobber (reg:CC 17))]
5212 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5213 "adc{q}\t{%2, %0|%0, %2}"
5214 [(set_attr "type" "alu")
5215 (set_attr "pent_pair" "pu")
5216 (set_attr "mode" "DI")
5217 (set_attr "ppro_uops" "few")])
5219 (define_insn "*adddi3_cc_rex64"
5221 (unspec:CC [(match_operand:DI 1 "nonimmediate_operand" "%0,0")
5222 (match_operand:DI 2 "x86_64_general_operand" "re,rm")]
5224 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
5225 (plus:DI (match_dup 1) (match_dup 2)))]
5226 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5227 "add{q}\t{%2, %0|%0, %2}"
5228 [(set_attr "type" "alu")
5229 (set_attr "mode" "DI")])
5231 (define_insn "addqi3_carry"
5232 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm,r")
5233 (plus:QI (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
5234 (match_operand:QI 1 "nonimmediate_operand" "%0,0"))
5235 (match_operand:QI 2 "general_operand" "ri,rm")))
5236 (clobber (reg:CC 17))]
5237 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5238 "adc{b}\t{%2, %0|%0, %2}"
5239 [(set_attr "type" "alu")
5240 (set_attr "pent_pair" "pu")
5241 (set_attr "mode" "QI")
5242 (set_attr "ppro_uops" "few")])
5244 (define_insn "addhi3_carry"
5245 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
5246 (plus:HI (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
5247 (match_operand:HI 1 "nonimmediate_operand" "%0,0"))
5248 (match_operand:HI 2 "general_operand" "ri,rm")))
5249 (clobber (reg:CC 17))]
5250 "ix86_binary_operator_ok (PLUS, HImode, operands)"
5251 "adc{w}\t{%2, %0|%0, %2}"
5252 [(set_attr "type" "alu")
5253 (set_attr "pent_pair" "pu")
5254 (set_attr "mode" "HI")
5255 (set_attr "ppro_uops" "few")])
5257 (define_insn "addsi3_carry"
5258 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5259 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5260 (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
5261 (match_operand:SI 2 "general_operand" "ri,rm")))
5262 (clobber (reg:CC 17))]
5263 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5264 "adc{l}\t{%2, %0|%0, %2}"
5265 [(set_attr "type" "alu")
5266 (set_attr "pent_pair" "pu")
5267 (set_attr "mode" "SI")
5268 (set_attr "ppro_uops" "few")])
5270 (define_insn "*addsi3_carry_zext"
5271 [(set (match_operand:DI 0 "register_operand" "=r")
5273 (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
5274 (match_operand:SI 1 "nonimmediate_operand" "%0"))
5275 (match_operand:SI 2 "general_operand" "rim"))))
5276 (clobber (reg:CC 17))]
5277 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5278 "adc{l}\t{%2, %k0|%k0, %2}"
5279 [(set_attr "type" "alu")
5280 (set_attr "pent_pair" "pu")
5281 (set_attr "mode" "SI")
5282 (set_attr "ppro_uops" "few")])
5284 (define_insn "*addsi3_cc"
5286 (unspec:CC [(match_operand:SI 1 "nonimmediate_operand" "%0,0")
5287 (match_operand:SI 2 "general_operand" "ri,rm")]
5289 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
5290 (plus:SI (match_dup 1) (match_dup 2)))]
5291 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5292 "add{l}\t{%2, %0|%0, %2}"
5293 [(set_attr "type" "alu")
5294 (set_attr "mode" "SI")])
5296 (define_insn "addqi3_cc"
5298 (unspec:CC [(match_operand:QI 1 "nonimmediate_operand" "%0,0")
5299 (match_operand:QI 2 "general_operand" "qi,qm")]
5301 (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
5302 (plus:QI (match_dup 1) (match_dup 2)))]
5303 "ix86_binary_operator_ok (PLUS, QImode, operands)"
5304 "add{b}\t{%2, %0|%0, %2}"
5305 [(set_attr "type" "alu")
5306 (set_attr "mode" "QI")])
5308 (define_expand "addsi3"
5309 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
5310 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "")
5311 (match_operand:SI 2 "general_operand" "")))
5312 (clobber (reg:CC 17))])]
5314 "ix86_expand_binary_operator (PLUS, SImode, operands); DONE;")
5316 (define_insn "*lea_1"
5317 [(set (match_operand:SI 0 "register_operand" "=r")
5318 (match_operand:SI 1 "no_seg_address_operand" "p"))]
5320 "lea{l}\t{%a1, %0|%0, %a1}"
5321 [(set_attr "type" "lea")
5322 (set_attr "mode" "SI")])
5324 (define_insn "*lea_1_rex64"
5325 [(set (match_operand:SI 0 "register_operand" "=r")
5326 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0))]
5328 "lea{l}\t{%a1, %0|%0, %a1}"
5329 [(set_attr "type" "lea")
5330 (set_attr "mode" "SI")])
5332 (define_insn "*lea_1_zext"
5333 [(set (match_operand:DI 0 "register_operand" "=r")
5335 (subreg:SI (match_operand:DI 1 "no_seg_address_operand" "p") 0)))]
5337 "lea{l}\t{%a1, %k0|%k0, %a1}"
5338 [(set_attr "type" "lea")
5339 (set_attr "mode" "SI")])
5341 (define_insn "*lea_2_rex64"
5342 [(set (match_operand:DI 0 "register_operand" "=r")
5343 (match_operand:DI 1 "no_seg_address_operand" "p"))]
5345 "lea{q}\t{%a1, %0|%0, %a1}"
5346 [(set_attr "type" "lea")
5347 (set_attr "mode" "DI")])
5349 ;; The lea patterns for non-Pmodes needs to be matched by several
5350 ;; insns converted to real lea by splitters.
5352 (define_insn_and_split "*lea_general_1"
5353 [(set (match_operand 0 "register_operand" "=r")
5354 (plus (plus (match_operand 1 "index_register_operand" "r")
5355 (match_operand 2 "register_operand" "r"))
5356 (match_operand 3 "immediate_operand" "i")))]
5357 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5358 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5359 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5360 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5361 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5362 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5363 || GET_MODE (operands[3]) == VOIDmode)"
5365 "&& reload_completed"
5369 operands[0] = gen_lowpart (SImode, operands[0]);
5370 operands[1] = gen_lowpart (Pmode, operands[1]);
5371 operands[2] = gen_lowpart (Pmode, operands[2]);
5372 operands[3] = gen_lowpart (Pmode, operands[3]);
5373 pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
5375 if (Pmode != SImode)
5376 pat = gen_rtx_SUBREG (SImode, pat, 0);
5377 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5380 [(set_attr "type" "lea")
5381 (set_attr "mode" "SI")])
5383 (define_insn_and_split "*lea_general_1_zext"
5384 [(set (match_operand:DI 0 "register_operand" "=r")
5386 (plus:SI (plus:SI (match_operand:SI 1 "index_register_operand" "r")
5387 (match_operand:SI 2 "register_operand" "r"))
5388 (match_operand:SI 3 "immediate_operand" "i"))))]
5391 "&& reload_completed"
5393 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (match_dup 1)
5395 (match_dup 3)) 0)))]
5397 operands[1] = gen_lowpart (Pmode, operands[1]);
5398 operands[2] = gen_lowpart (Pmode, operands[2]);
5399 operands[3] = gen_lowpart (Pmode, operands[3]);
5401 [(set_attr "type" "lea")
5402 (set_attr "mode" "SI")])
5404 (define_insn_and_split "*lea_general_2"
5405 [(set (match_operand 0 "register_operand" "=r")
5406 (plus (mult (match_operand 1 "index_register_operand" "r")
5407 (match_operand 2 "const248_operand" "i"))
5408 (match_operand 3 "nonmemory_operand" "ri")))]
5409 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5410 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5411 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5412 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5413 && (GET_MODE (operands[0]) == GET_MODE (operands[3])
5414 || GET_MODE (operands[3]) == VOIDmode)"
5416 "&& reload_completed"
5420 operands[0] = gen_lowpart (SImode, operands[0]);
5421 operands[1] = gen_lowpart (Pmode, operands[1]);
5422 operands[3] = gen_lowpart (Pmode, operands[3]);
5423 pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
5425 if (Pmode != SImode)
5426 pat = gen_rtx_SUBREG (SImode, pat, 0);
5427 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5430 [(set_attr "type" "lea")
5431 (set_attr "mode" "SI")])
5433 (define_insn_and_split "*lea_general_2_zext"
5434 [(set (match_operand:DI 0 "register_operand" "=r")
5436 (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5437 (match_operand:SI 2 "const248_operand" "n"))
5438 (match_operand:SI 3 "nonmemory_operand" "ri"))))]
5441 "&& reload_completed"
5443 (zero_extend:DI (subreg:SI (plus:DI (mult:DI (match_dup 1)
5445 (match_dup 3)) 0)))]
5447 operands[1] = gen_lowpart (Pmode, operands[1]);
5448 operands[3] = gen_lowpart (Pmode, operands[3]);
5450 [(set_attr "type" "lea")
5451 (set_attr "mode" "SI")])
5453 (define_insn_and_split "*lea_general_3"
5454 [(set (match_operand 0 "register_operand" "=r")
5455 (plus (plus (mult (match_operand 1 "index_register_operand" "r")
5456 (match_operand 2 "const248_operand" "i"))
5457 (match_operand 3 "register_operand" "r"))
5458 (match_operand 4 "immediate_operand" "i")))]
5459 "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
5460 || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
5461 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
5462 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5463 && GET_MODE (operands[0]) == GET_MODE (operands[3])"
5465 "&& reload_completed"
5469 operands[0] = gen_lowpart (SImode, operands[0]);
5470 operands[1] = gen_lowpart (Pmode, operands[1]);
5471 operands[3] = gen_lowpart (Pmode, operands[3]);
5472 operands[4] = gen_lowpart (Pmode, operands[4]);
5473 pat = gen_rtx_PLUS (Pmode,
5474 gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
5478 if (Pmode != SImode)
5479 pat = gen_rtx_SUBREG (SImode, pat, 0);
5480 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5483 [(set_attr "type" "lea")
5484 (set_attr "mode" "SI")])
5486 (define_insn_and_split "*lea_general_3_zext"
5487 [(set (match_operand:DI 0 "register_operand" "=r")
5489 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "index_register_operand" "r")
5490 (match_operand:SI 2 "const248_operand" "n"))
5491 (match_operand:SI 3 "register_operand" "r"))
5492 (match_operand:SI 4 "immediate_operand" "i"))))]
5495 "&& reload_completed"
5497 (zero_extend:DI (subreg:SI (plus:DI (plus:DI (mult:DI (match_dup 1)
5500 (match_dup 4)) 0)))]
5502 operands[1] = gen_lowpart (Pmode, operands[1]);
5503 operands[3] = gen_lowpart (Pmode, operands[3]);
5504 operands[4] = gen_lowpart (Pmode, operands[4]);
5506 [(set_attr "type" "lea")
5507 (set_attr "mode" "SI")])
5509 (define_insn "*adddi_1_rex64"
5510 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
5511 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
5512 (match_operand:DI 2 "x86_64_general_operand" "rme,re,re")))
5513 (clobber (reg:CC 17))]
5514 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
5516 switch (get_attr_type (insn))
5519 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5520 return "lea{q}\t{%a2, %0|%0, %a2}";
5523 if (! rtx_equal_p (operands[0], operands[1]))
5525 if (operands[2] == const1_rtx)
5526 return "inc{q}\t%0";
5527 else if (operands[2] == constm1_rtx)
5528 return "dec{q}\t%0";
5533 if (! rtx_equal_p (operands[0], operands[1]))
5536 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5537 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5538 if (GET_CODE (operands[2]) == CONST_INT
5539 /* Avoid overflows. */
5540 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5541 && (INTVAL (operands[2]) == 128
5542 || (INTVAL (operands[2]) < 0
5543 && INTVAL (operands[2]) != -128)))
5545 operands[2] = GEN_INT (-INTVAL (operands[2]));
5546 return "sub{q}\t{%2, %0|%0, %2}";
5548 return "add{q}\t{%2, %0|%0, %2}";
5552 (cond [(eq_attr "alternative" "2")
5553 (const_string "lea")
5554 ; Current assemblers are broken and do not allow @GOTOFF in
5555 ; ought but a memory context.
5556 (match_operand:DI 2 "pic_symbolic_operand" "")
5557 (const_string "lea")
5558 (match_operand:DI 2 "incdec_operand" "")
5559 (const_string "incdec")
5561 (const_string "alu")))
5562 (set_attr "mode" "DI")])
5564 ;; Convert lea to the lea pattern to avoid flags dependency.
5566 [(set (match_operand:DI 0 "register_operand" "")
5567 (plus:DI (match_operand:DI 1 "register_operand" "")
5568 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
5569 (clobber (reg:CC 17))]
5570 "TARGET_64BIT && reload_completed
5571 && true_regnum (operands[0]) != true_regnum (operands[1])"
5573 (plus:DI (match_dup 1)
5577 (define_insn "*adddi_2_rex64"
5580 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5581 (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
5583 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
5584 (plus:DI (match_dup 1) (match_dup 2)))]
5585 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5586 && ix86_binary_operator_ok (PLUS, DImode, operands)
5587 /* Current assemblers are broken and do not allow @GOTOFF in
5588 ought but a memory context. */
5589 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5591 switch (get_attr_type (insn))
5594 if (! rtx_equal_p (operands[0], operands[1]))
5596 if (operands[2] == const1_rtx)
5597 return "inc{q}\t%0";
5598 else if (operands[2] == constm1_rtx)
5599 return "dec{q}\t%0";
5604 if (! rtx_equal_p (operands[0], operands[1]))
5606 /* ???? We ought to handle there the 32bit case too
5607 - do we need new constraint? */
5608 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5609 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5610 if (GET_CODE (operands[2]) == CONST_INT
5611 /* Avoid overflows. */
5612 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5613 && (INTVAL (operands[2]) == 128
5614 || (INTVAL (operands[2]) < 0
5615 && INTVAL (operands[2]) != -128)))
5617 operands[2] = GEN_INT (-INTVAL (operands[2]));
5618 return "sub{q}\t{%2, %0|%0, %2}";
5620 return "add{q}\t{%2, %0|%0, %2}";
5624 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5625 (const_string "incdec")
5626 (const_string "alu")))
5627 (set_attr "mode" "DI")])
5629 (define_insn "*adddi_3_rex64"
5631 (compare (neg:DI (match_operand:DI 2 "x86_64_general_operand" "rme"))
5632 (match_operand:DI 1 "x86_64_general_operand" "%0")))
5633 (clobber (match_scratch:DI 0 "=r"))]
5635 && ix86_match_ccmode (insn, CCZmode)
5636 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5637 /* Current assemblers are broken and do not allow @GOTOFF in
5638 ought but a memory context. */
5639 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5641 switch (get_attr_type (insn))
5644 if (! rtx_equal_p (operands[0], operands[1]))
5646 if (operands[2] == const1_rtx)
5647 return "inc{q}\t%0";
5648 else if (operands[2] == constm1_rtx)
5649 return "dec{q}\t%0";
5654 if (! rtx_equal_p (operands[0], operands[1]))
5656 /* ???? We ought to handle there the 32bit case too
5657 - do we need new constraint? */
5658 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5659 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5660 if (GET_CODE (operands[2]) == CONST_INT
5661 /* Avoid overflows. */
5662 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5663 && (INTVAL (operands[2]) == 128
5664 || (INTVAL (operands[2]) < 0
5665 && INTVAL (operands[2]) != -128)))
5667 operands[2] = GEN_INT (-INTVAL (operands[2]));
5668 return "sub{q}\t{%2, %0|%0, %2}";
5670 return "add{q}\t{%2, %0|%0, %2}";
5674 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5675 (const_string "incdec")
5676 (const_string "alu")))
5677 (set_attr "mode" "DI")])
5679 ; For comparisons against 1, -1 and 128, we may generate better code
5680 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
5681 ; is matched then. We can't accept general immediate, because for
5682 ; case of overflows, the result is messed up.
5683 ; This pattern also don't hold of 0x8000000000000000, since the value overflows
5685 ; Also carry flag is reversed compared to cmp, so this conversion is valid
5686 ; only for comparisons not depending on it.
5687 (define_insn "*adddi_4_rex64"
5689 (compare (match_operand:DI 1 "nonimmediate_operand" "0")
5690 (match_operand:DI 2 "x86_64_immediate_operand" "e")))
5691 (clobber (match_scratch:DI 0 "=rm"))]
5693 && ix86_match_ccmode (insn, CCGCmode)"
5695 switch (get_attr_type (insn))
5698 if (operands[2] == constm1_rtx)
5699 return "inc{q}\t%0";
5700 else if (operands[2] == const1_rtx)
5701 return "dec{q}\t%0";
5706 if (! rtx_equal_p (operands[0], operands[1]))
5708 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5709 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5710 if ((INTVAL (operands[2]) == -128
5711 || (INTVAL (operands[2]) > 0
5712 && INTVAL (operands[2]) != 128))
5713 /* Avoid overflows. */
5714 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1))))
5715 return "sub{q}\t{%2, %0|%0, %2}";
5716 operands[2] = GEN_INT (-INTVAL (operands[2]));
5717 return "add{q}\t{%2, %0|%0, %2}";
5721 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5722 (const_string "incdec")
5723 (const_string "alu")))
5724 (set_attr "mode" "DI")])
5726 (define_insn "*adddi_5_rex64"
5729 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
5730 (match_operand:DI 2 "x86_64_general_operand" "rme"))
5732 (clobber (match_scratch:DI 0 "=r"))]
5734 && ix86_match_ccmode (insn, CCGOCmode)
5735 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
5736 /* Current assemblers are broken and do not allow @GOTOFF in
5737 ought but a memory context. */
5738 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5740 switch (get_attr_type (insn))
5743 if (! rtx_equal_p (operands[0], operands[1]))
5745 if (operands[2] == const1_rtx)
5746 return "inc{q}\t%0";
5747 else if (operands[2] == constm1_rtx)
5748 return "dec{q}\t%0";
5753 if (! rtx_equal_p (operands[0], operands[1]))
5755 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5756 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5757 if (GET_CODE (operands[2]) == CONST_INT
5758 /* Avoid overflows. */
5759 && ((INTVAL (operands[2]) & ((((unsigned int) 1) << 31) - 1)))
5760 && (INTVAL (operands[2]) == 128
5761 || (INTVAL (operands[2]) < 0
5762 && INTVAL (operands[2]) != -128)))
5764 operands[2] = GEN_INT (-INTVAL (operands[2]));
5765 return "sub{q}\t{%2, %0|%0, %2}";
5767 return "add{q}\t{%2, %0|%0, %2}";
5771 (if_then_else (match_operand:DI 2 "incdec_operand" "")
5772 (const_string "incdec")
5773 (const_string "alu")))
5774 (set_attr "mode" "DI")])
5777 (define_insn "*addsi_1"
5778 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
5779 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
5780 (match_operand:SI 2 "general_operand" "rmni,rni,rni")))
5781 (clobber (reg:CC 17))]
5782 "ix86_binary_operator_ok (PLUS, SImode, operands)"
5784 switch (get_attr_type (insn))
5787 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5788 return "lea{l}\t{%a2, %0|%0, %a2}";
5791 if (! rtx_equal_p (operands[0], operands[1]))
5793 if (operands[2] == const1_rtx)
5794 return "inc{l}\t%0";
5795 else if (operands[2] == constm1_rtx)
5796 return "dec{l}\t%0";
5801 if (! rtx_equal_p (operands[0], operands[1]))
5804 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5805 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5806 if (GET_CODE (operands[2]) == CONST_INT
5807 && (INTVAL (operands[2]) == 128
5808 || (INTVAL (operands[2]) < 0
5809 && INTVAL (operands[2]) != -128)))
5811 operands[2] = GEN_INT (-INTVAL (operands[2]));
5812 return "sub{l}\t{%2, %0|%0, %2}";
5814 return "add{l}\t{%2, %0|%0, %2}";
5818 (cond [(eq_attr "alternative" "2")
5819 (const_string "lea")
5820 ; Current assemblers are broken and do not allow @GOTOFF in
5821 ; ought but a memory context.
5822 (match_operand:SI 2 "pic_symbolic_operand" "")
5823 (const_string "lea")
5824 (match_operand:SI 2 "incdec_operand" "")
5825 (const_string "incdec")
5827 (const_string "alu")))
5828 (set_attr "mode" "SI")])
5830 ;; Convert lea to the lea pattern to avoid flags dependency.
5832 [(set (match_operand 0 "register_operand" "")
5833 (plus (match_operand 1 "register_operand" "")
5834 (match_operand 2 "nonmemory_operand" "")))
5835 (clobber (reg:CC 17))]
5837 && true_regnum (operands[0]) != true_regnum (operands[1])"
5841 /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
5842 may confuse gen_lowpart. */
5843 if (GET_MODE (operands[0]) != Pmode)
5845 operands[1] = gen_lowpart (Pmode, operands[1]);
5846 operands[2] = gen_lowpart (Pmode, operands[2]);
5848 operands[0] = gen_lowpart (SImode, operands[0]);
5849 pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
5850 if (Pmode != SImode)
5851 pat = gen_rtx_SUBREG (SImode, pat, 0);
5852 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
5856 ;; It may seem that nonimmediate operand is proper one for operand 1.
5857 ;; The addsi_1 pattern allows nonimmediate operand at that place and
5858 ;; we take care in ix86_binary_operator_ok to not allow two memory
5859 ;; operands so proper swapping will be done in reload. This allow
5860 ;; patterns constructed from addsi_1 to match.
5861 (define_insn "addsi_1_zext"
5862 [(set (match_operand:DI 0 "register_operand" "=r,r")
5864 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
5865 (match_operand:SI 2 "general_operand" "rmni,rni"))))
5866 (clobber (reg:CC 17))]
5867 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
5869 switch (get_attr_type (insn))
5872 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
5873 return "lea{l}\t{%a2, %k0|%k0, %a2}";
5876 if (operands[2] == const1_rtx)
5877 return "inc{l}\t%k0";
5878 else if (operands[2] == constm1_rtx)
5879 return "dec{l}\t%k0";
5884 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5885 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5886 if (GET_CODE (operands[2]) == CONST_INT
5887 && (INTVAL (operands[2]) == 128
5888 || (INTVAL (operands[2]) < 0
5889 && INTVAL (operands[2]) != -128)))
5891 operands[2] = GEN_INT (-INTVAL (operands[2]));
5892 return "sub{l}\t{%2, %k0|%k0, %2}";
5894 return "add{l}\t{%2, %k0|%k0, %2}";
5898 (cond [(eq_attr "alternative" "1")
5899 (const_string "lea")
5900 ; Current assemblers are broken and do not allow @GOTOFF in
5901 ; ought but a memory context.
5902 (match_operand:SI 2 "pic_symbolic_operand" "")
5903 (const_string "lea")
5904 (match_operand:SI 2 "incdec_operand" "")
5905 (const_string "incdec")
5907 (const_string "alu")))
5908 (set_attr "mode" "SI")])
5910 ;; Convert lea to the lea pattern to avoid flags dependency.
5912 [(set (match_operand:DI 0 "register_operand" "")
5914 (plus:SI (match_operand:SI 1 "register_operand" "")
5915 (match_operand:SI 2 "nonmemory_operand" ""))))
5916 (clobber (reg:CC 17))]
5917 "TARGET_64BIT && reload_completed
5918 && true_regnum (operands[0]) != true_regnum (operands[1])"
5920 (zero_extend:DI (subreg:SI (plus:DI (match_dup 1) (match_dup 2)) 0)))]
5922 operands[1] = gen_lowpart (Pmode, operands[1]);
5923 operands[2] = gen_lowpart (Pmode, operands[2]);
5926 (define_insn "*addsi_2"
5929 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
5930 (match_operand:SI 2 "general_operand" "rmni,rni"))
5932 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
5933 (plus:SI (match_dup 1) (match_dup 2)))]
5934 "ix86_match_ccmode (insn, CCGOCmode)
5935 && ix86_binary_operator_ok (PLUS, SImode, operands)
5936 /* Current assemblers are broken and do not allow @GOTOFF in
5937 ought but a memory context. */
5938 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5940 switch (get_attr_type (insn))
5943 if (! rtx_equal_p (operands[0], operands[1]))
5945 if (operands[2] == const1_rtx)
5946 return "inc{l}\t%0";
5947 else if (operands[2] == constm1_rtx)
5948 return "dec{l}\t%0";
5953 if (! rtx_equal_p (operands[0], operands[1]))
5955 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
5956 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
5957 if (GET_CODE (operands[2]) == CONST_INT
5958 && (INTVAL (operands[2]) == 128
5959 || (INTVAL (operands[2]) < 0
5960 && INTVAL (operands[2]) != -128)))
5962 operands[2] = GEN_INT (-INTVAL (operands[2]));
5963 return "sub{l}\t{%2, %0|%0, %2}";
5965 return "add{l}\t{%2, %0|%0, %2}";
5969 (if_then_else (match_operand:SI 2 "incdec_operand" "")
5970 (const_string "incdec")
5971 (const_string "alu")))
5972 (set_attr "mode" "SI")])
5974 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
5975 (define_insn "*addsi_2_zext"
5978 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
5979 (match_operand:SI 2 "general_operand" "rmni"))
5981 (set (match_operand:DI 0 "register_operand" "=r")
5982 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
5983 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
5984 && ix86_binary_operator_ok (PLUS, SImode, operands)
5985 /* Current assemblers are broken and do not allow @GOTOFF in
5986 ought but a memory context. */
5987 && ! pic_symbolic_operand (operands[2], VOIDmode)"
5989 switch (get_attr_type (insn))
5992 if (operands[2] == const1_rtx)
5993 return "inc{l}\t%k0";
5994 else if (operands[2] == constm1_rtx)
5995 return "dec{l}\t%k0";
6000 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6001 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6002 if (GET_CODE (operands[2]) == CONST_INT
6003 && (INTVAL (operands[2]) == 128
6004 || (INTVAL (operands[2]) < 0
6005 && INTVAL (operands[2]) != -128)))
6007 operands[2] = GEN_INT (-INTVAL (operands[2]));
6008 return "sub{l}\t{%2, %k0|%k0, %2}";
6010 return "add{l}\t{%2, %k0|%k0, %2}";
6014 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6015 (const_string "incdec")
6016 (const_string "alu")))
6017 (set_attr "mode" "SI")])
6019 (define_insn "*addsi_3"
6021 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6022 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6023 (clobber (match_scratch:SI 0 "=r"))]
6024 "ix86_match_ccmode (insn, CCZmode)
6025 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6026 /* Current assemblers are broken and do not allow @GOTOFF in
6027 ought but a memory context. */
6028 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6030 switch (get_attr_type (insn))
6033 if (! rtx_equal_p (operands[0], operands[1]))
6035 if (operands[2] == const1_rtx)
6036 return "inc{l}\t%0";
6037 else if (operands[2] == constm1_rtx)
6038 return "dec{l}\t%0";
6043 if (! rtx_equal_p (operands[0], operands[1]))
6045 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6046 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6047 if (GET_CODE (operands[2]) == CONST_INT
6048 && (INTVAL (operands[2]) == 128
6049 || (INTVAL (operands[2]) < 0
6050 && INTVAL (operands[2]) != -128)))
6052 operands[2] = GEN_INT (-INTVAL (operands[2]));
6053 return "sub{l}\t{%2, %0|%0, %2}";
6055 return "add{l}\t{%2, %0|%0, %2}";
6059 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6060 (const_string "incdec")
6061 (const_string "alu")))
6062 (set_attr "mode" "SI")])
6064 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
6065 (define_insn "*addsi_3_zext"
6067 (compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
6068 (match_operand:SI 1 "nonimmediate_operand" "%0")))
6069 (set (match_operand:DI 0 "register_operand" "=r")
6070 (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
6071 "TARGET_64BIT && ix86_match_ccmode (insn, CCZmode)
6072 && ix86_binary_operator_ok (PLUS, SImode, operands)
6073 /* Current assemblers are broken and do not allow @GOTOFF in
6074 ought but a memory context. */
6075 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6077 switch (get_attr_type (insn))
6080 if (operands[2] == const1_rtx)
6081 return "inc{l}\t%k0";
6082 else if (operands[2] == constm1_rtx)
6083 return "dec{l}\t%k0";
6088 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6089 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6090 if (GET_CODE (operands[2]) == CONST_INT
6091 && (INTVAL (operands[2]) == 128
6092 || (INTVAL (operands[2]) < 0
6093 && INTVAL (operands[2]) != -128)))
6095 operands[2] = GEN_INT (-INTVAL (operands[2]));
6096 return "sub{l}\t{%2, %k0|%k0, %2}";
6098 return "add{l}\t{%2, %k0|%k0, %2}";
6102 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6103 (const_string "incdec")
6104 (const_string "alu")))
6105 (set_attr "mode" "SI")])
6107 ; For comparisons against 1, -1 and 128, we may generate better code
6108 ; by converting cmp to add, inc or dec as done by peephole2. This pattern
6109 ; is matched then. We can't accept general immediate, because for
6110 ; case of overflows, the result is messed up.
6111 ; This pattern also don't hold of 0x80000000, since the value overflows
6113 ; Also carry flag is reversed compared to cmp, so this conversion is valid
6114 ; only for comparisons not depending on it.
6115 (define_insn "*addsi_4"
6117 (compare (match_operand:SI 1 "nonimmediate_operand" "0")
6118 (match_operand:SI 2 "const_int_operand" "n")))
6119 (clobber (match_scratch:SI 0 "=rm"))]
6120 "ix86_match_ccmode (insn, CCGCmode)
6121 && (INTVAL (operands[2]) & 0xffffffff) != 0x80000000"
6123 switch (get_attr_type (insn))
6126 if (operands[2] == constm1_rtx)
6127 return "inc{l}\t%0";
6128 else if (operands[2] == const1_rtx)
6129 return "dec{l}\t%0";
6134 if (! rtx_equal_p (operands[0], operands[1]))
6136 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6137 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6138 if ((INTVAL (operands[2]) == -128
6139 || (INTVAL (operands[2]) > 0
6140 && INTVAL (operands[2]) != 128)))
6141 return "sub{l}\t{%2, %0|%0, %2}";
6142 operands[2] = GEN_INT (-INTVAL (operands[2]));
6143 return "add{l}\t{%2, %0|%0, %2}";
6147 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6148 (const_string "incdec")
6149 (const_string "alu")))
6150 (set_attr "mode" "SI")])
6152 (define_insn "*addsi_5"
6155 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
6156 (match_operand:SI 2 "general_operand" "rmni"))
6158 (clobber (match_scratch:SI 0 "=r"))]
6159 "ix86_match_ccmode (insn, CCGOCmode)
6160 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
6161 /* Current assemblers are broken and do not allow @GOTOFF in
6162 ought but a memory context. */
6163 && ! pic_symbolic_operand (operands[2], VOIDmode)"
6165 switch (get_attr_type (insn))
6168 if (! rtx_equal_p (operands[0], operands[1]))
6170 if (operands[2] == const1_rtx)
6171 return "inc{l}\t%0";
6172 else if (operands[2] == constm1_rtx)
6173 return "dec{l}\t%0";
6178 if (! rtx_equal_p (operands[0], operands[1]))
6180 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6181 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6182 if (GET_CODE (operands[2]) == CONST_INT
6183 && (INTVAL (operands[2]) == 128
6184 || (INTVAL (operands[2]) < 0
6185 && INTVAL (operands[2]) != -128)))
6187 operands[2] = GEN_INT (-INTVAL (operands[2]));
6188 return "sub{l}\t{%2, %0|%0, %2}";
6190 return "add{l}\t{%2, %0|%0, %2}";
6194 (if_then_else (match_operand:SI 2 "incdec_operand" "")
6195 (const_string "incdec")
6196 (const_string "alu")))
6197 (set_attr "mode" "SI")])
6199 (define_expand "addhi3"
6200 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
6201 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
6202 (match_operand:HI 2 "general_operand" "")))
6203 (clobber (reg:CC 17))])]
6204 "TARGET_HIMODE_MATH"
6205 "ix86_expand_binary_operator (PLUS, HImode, operands); DONE;")
6207 ;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
6208 ;; type optimizations enabled by define-splits. This is not important
6209 ;; for PII, and in fact harmful because of partial register stalls.
6211 (define_insn "*addhi_1_lea"
6212 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
6213 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r")
6214 (match_operand:HI 2 "general_operand" "ri,rm,rni")))
6215 (clobber (reg:CC 17))]
6216 "!TARGET_PARTIAL_REG_STALL
6217 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6219 switch (get_attr_type (insn))
6224 if (operands[2] == const1_rtx)
6225 return "inc{w}\t%0";
6226 else if (operands[2] == constm1_rtx)
6227 return "dec{w}\t%0";
6231 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6232 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6233 if (GET_CODE (operands[2]) == CONST_INT
6234 && (INTVAL (operands[2]) == 128
6235 || (INTVAL (operands[2]) < 0
6236 && INTVAL (operands[2]) != -128)))
6238 operands[2] = GEN_INT (-INTVAL (operands[2]));
6239 return "sub{w}\t{%2, %0|%0, %2}";
6241 return "add{w}\t{%2, %0|%0, %2}";
6245 (if_then_else (eq_attr "alternative" "2")
6246 (const_string "lea")
6247 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6248 (const_string "incdec")
6249 (const_string "alu"))))
6250 (set_attr "mode" "HI,HI,SI")])
6252 (define_insn "*addhi_1"
6253 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6254 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6255 (match_operand:HI 2 "general_operand" "ri,rm")))
6256 (clobber (reg:CC 17))]
6257 "TARGET_PARTIAL_REG_STALL
6258 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6260 switch (get_attr_type (insn))
6263 if (operands[2] == const1_rtx)
6264 return "inc{w}\t%0";
6265 else if (operands[2] == constm1_rtx)
6266 return "dec{w}\t%0";
6270 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6271 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6272 if (GET_CODE (operands[2]) == CONST_INT
6273 && (INTVAL (operands[2]) == 128
6274 || (INTVAL (operands[2]) < 0
6275 && INTVAL (operands[2]) != -128)))
6277 operands[2] = GEN_INT (-INTVAL (operands[2]));
6278 return "sub{w}\t{%2, %0|%0, %2}";
6280 return "add{w}\t{%2, %0|%0, %2}";
6284 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6285 (const_string "incdec")
6286 (const_string "alu")))
6287 (set_attr "mode" "HI")])
6289 (define_insn "*addhi_2"
6292 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
6293 (match_operand:HI 2 "general_operand" "rmni,rni"))
6295 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
6296 (plus:HI (match_dup 1) (match_dup 2)))]
6297 "ix86_match_ccmode (insn, CCGOCmode)
6298 && ix86_binary_operator_ok (PLUS, HImode, operands)"
6300 switch (get_attr_type (insn))
6303 if (operands[2] == const1_rtx)
6304 return "inc{w}\t%0";
6305 else if (operands[2] == constm1_rtx)
6306 return "dec{w}\t%0";
6310 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6311 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6312 if (GET_CODE (operands[2]) == CONST_INT
6313 && (INTVAL (operands[2]) == 128
6314 || (INTVAL (operands[2]) < 0
6315 && INTVAL (operands[2]) != -128)))
6317 operands[2] = GEN_INT (-INTVAL (operands[2]));
6318 return "sub{w}\t{%2, %0|%0, %2}";
6320 return "add{w}\t{%2, %0|%0, %2}";
6324 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6325 (const_string "incdec")
6326 (const_string "alu")))
6327 (set_attr "mode" "HI")])
6329 (define_insn "*addhi_3"
6331 (compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
6332 (match_operand:HI 1 "nonimmediate_operand" "%0")))
6333 (clobber (match_scratch:HI 0 "=r"))]
6334 "ix86_match_ccmode (insn, CCZmode)
6335 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6337 switch (get_attr_type (insn))
6340 if (operands[2] == const1_rtx)
6341 return "inc{w}\t%0";
6342 else if (operands[2] == constm1_rtx)
6343 return "dec{w}\t%0";
6347 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6348 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6349 if (GET_CODE (operands[2]) == CONST_INT
6350 && (INTVAL (operands[2]) == 128
6351 || (INTVAL (operands[2]) < 0
6352 && INTVAL (operands[2]) != -128)))
6354 operands[2] = GEN_INT (-INTVAL (operands[2]));
6355 return "sub{w}\t{%2, %0|%0, %2}";
6357 return "add{w}\t{%2, %0|%0, %2}";
6361 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6362 (const_string "incdec")
6363 (const_string "alu")))
6364 (set_attr "mode" "HI")])
6366 ; See comments above addsi_3_imm for details.
6367 (define_insn "*addhi_4"
6369 (compare (match_operand:HI 1 "nonimmediate_operand" "0")
6370 (match_operand:HI 2 "const_int_operand" "n")))
6371 (clobber (match_scratch:HI 0 "=rm"))]
6372 "ix86_match_ccmode (insn, CCGCmode)
6373 && (INTVAL (operands[2]) & 0xffff) != 0x8000"
6375 switch (get_attr_type (insn))
6378 if (operands[2] == constm1_rtx)
6379 return "inc{w}\t%0";
6380 else if (operands[2] == const1_rtx)
6381 return "dec{w}\t%0";
6386 if (! rtx_equal_p (operands[0], operands[1]))
6388 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6389 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6390 if ((INTVAL (operands[2]) == -128
6391 || (INTVAL (operands[2]) > 0
6392 && INTVAL (operands[2]) != 128)))
6393 return "sub{w}\t{%2, %0|%0, %2}";
6394 operands[2] = GEN_INT (-INTVAL (operands[2]));
6395 return "add{w}\t{%2, %0|%0, %2}";
6399 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6400 (const_string "incdec")
6401 (const_string "alu")))
6402 (set_attr "mode" "SI")])
6405 (define_insn "*addhi_5"
6408 (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
6409 (match_operand:HI 2 "general_operand" "rmni"))
6411 (clobber (match_scratch:HI 0 "=r"))]
6412 "ix86_match_ccmode (insn, CCGOCmode)
6413 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6415 switch (get_attr_type (insn))
6418 if (operands[2] == const1_rtx)
6419 return "inc{w}\t%0";
6420 else if (operands[2] == constm1_rtx)
6421 return "dec{w}\t%0";
6425 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6426 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6427 if (GET_CODE (operands[2]) == CONST_INT
6428 && (INTVAL (operands[2]) == 128
6429 || (INTVAL (operands[2]) < 0
6430 && INTVAL (operands[2]) != -128)))
6432 operands[2] = GEN_INT (-INTVAL (operands[2]));
6433 return "sub{w}\t{%2, %0|%0, %2}";
6435 return "add{w}\t{%2, %0|%0, %2}";
6439 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6440 (const_string "incdec")
6441 (const_string "alu")))
6442 (set_attr "mode" "HI")])
6444 (define_expand "addqi3"
6445 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
6446 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
6447 (match_operand:QI 2 "general_operand" "")))
6448 (clobber (reg:CC 17))])]
6449 "TARGET_QIMODE_MATH"
6450 "ix86_expand_binary_operator (PLUS, QImode, operands); DONE;")
6452 ;; %%% Potential partial reg stall on alternative 2. What to do?
6453 (define_insn "*addqi_1_lea"
6454 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r,r")
6455 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,r")
6456 (match_operand:QI 2 "general_operand" "qn,qmn,rn,rn")))
6457 (clobber (reg:CC 17))]
6458 "!TARGET_PARTIAL_REG_STALL
6459 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6461 int widen = (which_alternative == 2);
6462 switch (get_attr_type (insn))
6467 if (operands[2] == const1_rtx)
6468 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6469 else if (operands[2] == constm1_rtx)
6470 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6474 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6475 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6476 if (GET_CODE (operands[2]) == CONST_INT
6477 && (INTVAL (operands[2]) == 128
6478 || (INTVAL (operands[2]) < 0
6479 && INTVAL (operands[2]) != -128)))
6481 operands[2] = GEN_INT (-INTVAL (operands[2]));
6483 return "sub{l}\t{%2, %k0|%k0, %2}";
6485 return "sub{b}\t{%2, %0|%0, %2}";
6488 return "add{l}\t{%k2, %k0|%k0, %k2}";
6490 return "add{b}\t{%2, %0|%0, %2}";
6494 (if_then_else (eq_attr "alternative" "3")
6495 (const_string "lea")
6496 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6497 (const_string "incdec")
6498 (const_string "alu"))))
6499 (set_attr "mode" "QI,QI,SI,SI")])
6501 (define_insn "*addqi_1"
6502 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
6503 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
6504 (match_operand:QI 2 "general_operand" "qn,qmn,rn")))
6505 (clobber (reg:CC 17))]
6506 "TARGET_PARTIAL_REG_STALL
6507 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6509 int widen = (which_alternative == 2);
6510 switch (get_attr_type (insn))
6513 if (operands[2] == const1_rtx)
6514 return widen ? "inc{l}\t%k0" : "inc{b}\t%0";
6515 else if (operands[2] == constm1_rtx)
6516 return widen ? "dec{l}\t%k0" : "dec{b}\t%0";
6520 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
6521 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
6522 if (GET_CODE (operands[2]) == CONST_INT
6523 && (INTVAL (operands[2]) == 128
6524 || (INTVAL (operands[2]) < 0
6525 && INTVAL (operands[2]) != -128)))
6527 operands[2] = GEN_INT (-INTVAL (operands[2]));
6529 return "sub{l}\t{%2, %k0|%k0, %2}";
6531 return "sub{b}\t{%2, %0|%0, %2}";
6534 return "add{l}\t{%k2, %k0|%k0, %k2}";
6536 return "add{b}\t{%2, %0|%0, %2}";
6540 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6541 (const_string "incdec")
6542 (const_string "alu")))
6543 (set_attr "mode" "QI,QI,SI")])
6545 (define_insn "*addqi_1_slp"
6546 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
6547 (plus:QI (match_dup 0)
6548 (match_operand:QI 1 "general_operand" "qn,qnm")))
6549 (clobber (reg:CC 17))]
6550 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
6551 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
6553 switch (get_attr_type (insn))
6556 if (operands[1] == const1_rtx)
6557 return "inc{b}\t%0";
6558 else if (operands[1] == constm1_rtx)
6559 return "dec{b}\t%0";
6563 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. */
6564 if (GET_CODE (operands[1]) == CONST_INT
6565 && INTVAL (operands[1]) < 0)
6567 operands[2] = GEN_INT (-INTVAL (operands[2]));
6568 return "sub{b}\t{%1, %0|%0, %1}";
6570 return "add{b}\t{%1, %0|%0, %1}";
6574 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6575 (const_string "incdec")
6576 (const_string "alu1")))
6577 (set_attr "mode" "QI")])
6579 (define_insn "*addqi_2"
6582 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
6583 (match_operand:QI 2 "general_operand" "qmni,qni"))
6585 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
6586 (plus:QI (match_dup 1) (match_dup 2)))]
6587 "ix86_match_ccmode (insn, CCGOCmode)
6588 && ix86_binary_operator_ok (PLUS, QImode, operands)"
6590 switch (get_attr_type (insn))
6593 if (operands[2] == const1_rtx)
6594 return "inc{b}\t%0";
6595 else if (operands[2] == constm1_rtx
6596 || (GET_CODE (operands[2]) == CONST_INT
6597 && INTVAL (operands[2]) == 255))
6598 return "dec{b}\t%0";
6602 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6603 if (GET_CODE (operands[2]) == CONST_INT
6604 && INTVAL (operands[2]) < 0)
6606 operands[2] = GEN_INT (-INTVAL (operands[2]));
6607 return "sub{b}\t{%2, %0|%0, %2}";
6609 return "add{b}\t{%2, %0|%0, %2}";
6613 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6614 (const_string "incdec")
6615 (const_string "alu")))
6616 (set_attr "mode" "QI")])
6618 (define_insn "*addqi_3"
6620 (compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
6621 (match_operand:QI 1 "nonimmediate_operand" "%0")))
6622 (clobber (match_scratch:QI 0 "=q"))]
6623 "ix86_match_ccmode (insn, CCZmode)
6624 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6626 switch (get_attr_type (insn))
6629 if (operands[2] == const1_rtx)
6630 return "inc{b}\t%0";
6631 else if (operands[2] == constm1_rtx
6632 || (GET_CODE (operands[2]) == CONST_INT
6633 && INTVAL (operands[2]) == 255))
6634 return "dec{b}\t%0";
6638 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6639 if (GET_CODE (operands[2]) == CONST_INT
6640 && INTVAL (operands[2]) < 0)
6642 operands[2] = GEN_INT (-INTVAL (operands[2]));
6643 return "sub{b}\t{%2, %0|%0, %2}";
6645 return "add{b}\t{%2, %0|%0, %2}";
6649 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6650 (const_string "incdec")
6651 (const_string "alu")))
6652 (set_attr "mode" "QI")])
6654 ; See comments above addsi_3_imm for details.
6655 (define_insn "*addqi_4"
6657 (compare (match_operand:QI 1 "nonimmediate_operand" "0")
6658 (match_operand:QI 2 "const_int_operand" "n")))
6659 (clobber (match_scratch:QI 0 "=qm"))]
6660 "ix86_match_ccmode (insn, CCGCmode)
6661 && (INTVAL (operands[2]) & 0xff) != 0x80"
6663 switch (get_attr_type (insn))
6666 if (operands[2] == constm1_rtx
6667 || (GET_CODE (operands[2]) == CONST_INT
6668 && INTVAL (operands[2]) == 255))
6669 return "inc{b}\t%0";
6670 else if (operands[2] == const1_rtx)
6671 return "dec{b}\t%0";
6676 if (! rtx_equal_p (operands[0], operands[1]))
6678 if (INTVAL (operands[2]) < 0)
6680 operands[2] = GEN_INT (-INTVAL (operands[2]));
6681 return "add{b}\t{%2, %0|%0, %2}";
6683 return "sub{b}\t{%2, %0|%0, %2}";
6687 (if_then_else (match_operand:HI 2 "incdec_operand" "")
6688 (const_string "incdec")
6689 (const_string "alu")))
6690 (set_attr "mode" "QI")])
6693 (define_insn "*addqi_5"
6696 (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
6697 (match_operand:QI 2 "general_operand" "qmni"))
6699 (clobber (match_scratch:QI 0 "=q"))]
6700 "ix86_match_ccmode (insn, CCGOCmode)
6701 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
6703 switch (get_attr_type (insn))
6706 if (operands[2] == const1_rtx)
6707 return "inc{b}\t%0";
6708 else if (operands[2] == constm1_rtx
6709 || (GET_CODE (operands[2]) == CONST_INT
6710 && INTVAL (operands[2]) == 255))
6711 return "dec{b}\t%0";
6715 /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'. */
6716 if (GET_CODE (operands[2]) == CONST_INT
6717 && INTVAL (operands[2]) < 0)
6719 operands[2] = GEN_INT (-INTVAL (operands[2]));
6720 return "sub{b}\t{%2, %0|%0, %2}";
6722 return "add{b}\t{%2, %0|%0, %2}";
6726 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6727 (const_string "incdec")
6728 (const_string "alu")))
6729 (set_attr "mode" "QI")])
6732 (define_insn "addqi_ext_1"
6733 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6738 (match_operand 1 "ext_register_operand" "0")
6741 (match_operand:QI 2 "general_operand" "Qmn")))
6742 (clobber (reg:CC 17))]
6745 switch (get_attr_type (insn))
6748 if (operands[2] == const1_rtx)
6749 return "inc{b}\t%h0";
6750 else if (operands[2] == constm1_rtx
6751 || (GET_CODE (operands[2]) == CONST_INT
6752 && INTVAL (operands[2]) == 255))
6753 return "dec{b}\t%h0";
6757 return "add{b}\t{%2, %h0|%h0, %2}";
6761 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6762 (const_string "incdec")
6763 (const_string "alu")))
6764 (set_attr "mode" "QI")])
6766 (define_insn "*addqi_ext_1_rex64"
6767 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6772 (match_operand 1 "ext_register_operand" "0")
6775 (match_operand:QI 2 "nonmemory_operand" "Qn")))
6776 (clobber (reg:CC 17))]
6779 switch (get_attr_type (insn))
6782 if (operands[2] == const1_rtx)
6783 return "inc{b}\t%h0";
6784 else if (operands[2] == constm1_rtx
6785 || (GET_CODE (operands[2]) == CONST_INT
6786 && INTVAL (operands[2]) == 255))
6787 return "dec{b}\t%h0";
6791 return "add{b}\t{%2, %h0|%h0, %2}";
6795 (if_then_else (match_operand:QI 2 "incdec_operand" "")
6796 (const_string "incdec")
6797 (const_string "alu")))
6798 (set_attr "mode" "QI")])
6800 (define_insn "*addqi_ext_2"
6801 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
6806 (match_operand 1 "ext_register_operand" "%0")
6810 (match_operand 2 "ext_register_operand" "Q")
6813 (clobber (reg:CC 17))]
6815 "add{b}\t{%h2, %h0|%h0, %h2}"
6816 [(set_attr "type" "alu")
6817 (set_attr "mode" "QI")])
6819 ;; The patterns that match these are at the end of this file.
6821 (define_expand "addxf3"
6822 [(set (match_operand:XF 0 "register_operand" "")
6823 (plus:XF (match_operand:XF 1 "register_operand" "")
6824 (match_operand:XF 2 "register_operand" "")))]
6825 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
6828 (define_expand "addtf3"
6829 [(set (match_operand:TF 0 "register_operand" "")
6830 (plus:TF (match_operand:TF 1 "register_operand" "")
6831 (match_operand:TF 2 "register_operand" "")))]
6835 (define_expand "adddf3"
6836 [(set (match_operand:DF 0 "register_operand" "")
6837 (plus:DF (match_operand:DF 1 "register_operand" "")
6838 (match_operand:DF 2 "nonimmediate_operand" "")))]
6839 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
6842 (define_expand "addsf3"
6843 [(set (match_operand:SF 0 "register_operand" "")
6844 (plus:SF (match_operand:SF 1 "register_operand" "")
6845 (match_operand:SF 2 "nonimmediate_operand" "")))]
6846 "TARGET_80387 || TARGET_SSE_MATH"
6849 ;; Subtract instructions
6851 ;; %%% splits for subsidi3
6853 (define_expand "subdi3"
6854 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
6855 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6856 (match_operand:DI 2 "x86_64_general_operand" "")))
6857 (clobber (reg:CC 17))])]
6859 "ix86_expand_binary_operator (MINUS, DImode, operands); DONE;")
6861 (define_insn "*subdi3_1"
6862 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
6863 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6864 (match_operand:DI 2 "general_operand" "roiF,riF")))
6865 (clobber (reg:CC 17))]
6866 "!TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6870 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6871 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "")
6872 (match_operand:DI 2 "general_operand" "")))
6873 (clobber (reg:CC 17))]
6874 "!TARGET_64BIT && reload_completed"
6875 [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
6876 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
6877 (parallel [(set (match_dup 3)
6878 (minus:SI (match_dup 4)
6879 (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
6881 (clobber (reg:CC 17))])]
6882 "split_di (operands+0, 1, operands+0, operands+3);
6883 split_di (operands+1, 1, operands+1, operands+4);
6884 split_di (operands+2, 1, operands+2, operands+5);")
6886 (define_insn "subdi3_carry_rex64"
6887 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6888 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6889 (plus:DI (match_operand:DI 3 "ix86_carry_flag_operator" "")
6890 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))))
6891 (clobber (reg:CC 17))]
6892 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6893 "sbb{q}\t{%2, %0|%0, %2}"
6894 [(set_attr "type" "alu")
6895 (set_attr "pent_pair" "pu")
6896 (set_attr "ppro_uops" "few")
6897 (set_attr "mode" "DI")])
6899 (define_insn "*subdi_1_rex64"
6900 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6901 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6902 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6903 (clobber (reg:CC 17))]
6904 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
6905 "sub{q}\t{%2, %0|%0, %2}"
6906 [(set_attr "type" "alu")
6907 (set_attr "mode" "DI")])
6909 (define_insn "*subdi_2_rex64"
6912 (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
6913 (match_operand:DI 2 "x86_64_general_operand" "re,rm"))
6915 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6916 (minus:DI (match_dup 1) (match_dup 2)))]
6917 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
6918 && ix86_binary_operator_ok (MINUS, DImode, operands)"
6919 "sub{q}\t{%2, %0|%0, %2}"
6920 [(set_attr "type" "alu")
6921 (set_attr "mode" "DI")])
6923 (define_insn "*subdi_3_rex63"
6925 (compare (match_operand:DI 1 "nonimmediate_operand" "0,0")
6926 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
6927 (set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
6928 (minus:DI (match_dup 1) (match_dup 2)))]
6929 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
6930 && ix86_binary_operator_ok (MINUS, SImode, operands)"
6931 "sub{q}\t{%2, %0|%0, %2}"
6932 [(set_attr "type" "alu")
6933 (set_attr "mode" "DI")])
6935 (define_insn "subqi3_carry"
6936 [(set (match_operand:QI 0 "nonimmediate_operand" "=rm,r")
6937 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
6938 (plus:QI (match_operand:QI 3 "ix86_carry_flag_operator" "")
6939 (match_operand:QI 2 "general_operand" "ri,rm"))))
6940 (clobber (reg:CC 17))]
6941 "ix86_binary_operator_ok (MINUS, QImode, operands)"
6942 "sbb{b}\t{%2, %0|%0, %2}"
6943 [(set_attr "type" "alu")
6944 (set_attr "pent_pair" "pu")
6945 (set_attr "ppro_uops" "few")
6946 (set_attr "mode" "QI")])
6948 (define_insn "subhi3_carry"
6949 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
6950 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
6951 (plus:HI (match_operand:HI 3 "ix86_carry_flag_operator" "")
6952 (match_operand:HI 2 "general_operand" "ri,rm"))))
6953 (clobber (reg:CC 17))]
6954 "ix86_binary_operator_ok (MINUS, HImode, operands)"
6955 "sbb{w}\t{%2, %0|%0, %2}"
6956 [(set_attr "type" "alu")
6957 (set_attr "pent_pair" "pu")
6958 (set_attr "ppro_uops" "few")
6959 (set_attr "mode" "HI")])
6961 (define_insn "subsi3_carry"
6962 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6963 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6964 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6965 (match_operand:SI 2 "general_operand" "ri,rm"))))
6966 (clobber (reg:CC 17))]
6967 "ix86_binary_operator_ok (MINUS, SImode, operands)"
6968 "sbb{l}\t{%2, %0|%0, %2}"
6969 [(set_attr "type" "alu")
6970 (set_attr "pent_pair" "pu")
6971 (set_attr "ppro_uops" "few")
6972 (set_attr "mode" "SI")])
6974 (define_insn "subsi3_carry_zext"
6975 [(set (match_operand:DI 0 "register_operand" "=rm,r")
6977 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
6978 (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
6979 (match_operand:SI 2 "general_operand" "ri,rm")))))
6980 (clobber (reg:CC 17))]
6981 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
6982 "sbb{l}\t{%2, %k0|%k0, %2}"
6983 [(set_attr "type" "alu")
6984 (set_attr "pent_pair" "pu")
6985 (set_attr "ppro_uops" "few")
6986 (set_attr "mode" "SI")])
6988 (define_expand "subsi3"
6989 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
6990 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "")
6991 (match_operand:SI 2 "general_operand" "")))
6992 (clobber (reg:CC 17))])]
6994 "ix86_expand_binary_operator (MINUS, SImode, operands); DONE;")
6996 (define_insn "*subsi_1"
6997 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
6998 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
6999 (match_operand:SI 2 "general_operand" "ri,rm")))
7000 (clobber (reg:CC 17))]
7001 "ix86_binary_operator_ok (MINUS, SImode, operands)"
7002 "sub{l}\t{%2, %0|%0, %2}"
7003 [(set_attr "type" "alu")
7004 (set_attr "mode" "SI")])
7006 (define_insn "*subsi_1_zext"
7007 [(set (match_operand:DI 0 "register_operand" "=r")
7009 (minus:SI (match_operand:SI 1 "register_operand" "0")
7010 (match_operand:SI 2 "general_operand" "rim"))))
7011 (clobber (reg:CC 17))]
7012 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
7013 "sub{l}\t{%2, %k0|%k0, %2}"
7014 [(set_attr "type" "alu")
7015 (set_attr "mode" "SI")])
7017 (define_insn "*subsi_2"
7020 (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
7021 (match_operand:SI 2 "general_operand" "ri,rm"))
7023 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7024 (minus:SI (match_dup 1) (match_dup 2)))]
7025 "ix86_match_ccmode (insn, CCGOCmode)
7026 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7027 "sub{l}\t{%2, %0|%0, %2}"
7028 [(set_attr "type" "alu")
7029 (set_attr "mode" "SI")])
7031 (define_insn "*subsi_2_zext"
7034 (minus:SI (match_operand:SI 1 "register_operand" "0")
7035 (match_operand:SI 2 "general_operand" "rim"))
7037 (set (match_operand:DI 0 "register_operand" "=r")
7039 (minus:SI (match_dup 1)
7041 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
7042 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7043 "sub{l}\t{%2, %k0|%k0, %2}"
7044 [(set_attr "type" "alu")
7045 (set_attr "mode" "SI")])
7047 (define_insn "*subsi_3"
7049 (compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
7050 (match_operand:SI 2 "general_operand" "ri,rm")))
7051 (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
7052 (minus:SI (match_dup 1) (match_dup 2)))]
7053 "ix86_match_ccmode (insn, CCmode)
7054 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7055 "sub{l}\t{%2, %0|%0, %2}"
7056 [(set_attr "type" "alu")
7057 (set_attr "mode" "SI")])
7059 (define_insn "*subsi_3_zext"
7061 (compare (match_operand:SI 1 "register_operand" "0")
7062 (match_operand:SI 2 "general_operand" "rim")))
7063 (set (match_operand:DI 0 "register_operand" "=r")
7065 (minus:SI (match_dup 1)
7067 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
7068 && ix86_binary_operator_ok (MINUS, SImode, operands)"
7069 "sub{q}\t{%2, %0|%0, %2}"
7070 [(set_attr "type" "alu")
7071 (set_attr "mode" "DI")])
7073 (define_expand "subhi3"
7074 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
7075 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "")
7076 (match_operand:HI 2 "general_operand" "")))
7077 (clobber (reg:CC 17))])]
7078 "TARGET_HIMODE_MATH"
7079 "ix86_expand_binary_operator (MINUS, HImode, operands); DONE;")
7081 (define_insn "*subhi_1"
7082 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7083 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7084 (match_operand:HI 2 "general_operand" "ri,rm")))
7085 (clobber (reg:CC 17))]
7086 "ix86_binary_operator_ok (MINUS, HImode, operands)"
7087 "sub{w}\t{%2, %0|%0, %2}"
7088 [(set_attr "type" "alu")
7089 (set_attr "mode" "HI")])
7091 (define_insn "*subhi_2"
7094 (minus:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
7095 (match_operand:HI 2 "general_operand" "ri,rm"))
7097 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7098 (minus:HI (match_dup 1) (match_dup 2)))]
7099 "ix86_match_ccmode (insn, CCGOCmode)
7100 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7101 "sub{w}\t{%2, %0|%0, %2}"
7102 [(set_attr "type" "alu")
7103 (set_attr "mode" "HI")])
7105 (define_insn "*subhi_3"
7107 (compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
7108 (match_operand:HI 2 "general_operand" "ri,rm")))
7109 (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
7110 (minus:HI (match_dup 1) (match_dup 2)))]
7111 "ix86_match_ccmode (insn, CCmode)
7112 && ix86_binary_operator_ok (MINUS, HImode, operands)"
7113 "sub{w}\t{%2, %0|%0, %2}"
7114 [(set_attr "type" "alu")
7115 (set_attr "mode" "HI")])
7117 (define_expand "subqi3"
7118 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
7119 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "")
7120 (match_operand:QI 2 "general_operand" "")))
7121 (clobber (reg:CC 17))])]
7122 "TARGET_QIMODE_MATH"
7123 "ix86_expand_binary_operator (MINUS, QImode, operands); DONE;")
7125 (define_insn "*subqi_1"
7126 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
7127 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7128 (match_operand:QI 2 "general_operand" "qn,qmn")))
7129 (clobber (reg:CC 17))]
7130 "ix86_binary_operator_ok (MINUS, QImode, operands)"
7131 "sub{b}\t{%2, %0|%0, %2}"
7132 [(set_attr "type" "alu")
7133 (set_attr "mode" "QI")])
7135 (define_insn "*subqi_1_slp"
7136 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
7137 (minus:QI (match_dup 0)
7138 (match_operand:QI 1 "general_operand" "qn,qmn")))
7139 (clobber (reg:CC 17))]
7140 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
7141 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
7142 "sub{b}\t{%1, %0|%0, %1}"
7143 [(set_attr "type" "alu1")
7144 (set_attr "mode" "QI")])
7146 (define_insn "*subqi_2"
7149 (minus:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
7150 (match_operand:QI 2 "general_operand" "qi,qm"))
7152 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7153 (minus:HI (match_dup 1) (match_dup 2)))]
7154 "ix86_match_ccmode (insn, CCGOCmode)
7155 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7156 "sub{b}\t{%2, %0|%0, %2}"
7157 [(set_attr "type" "alu")
7158 (set_attr "mode" "QI")])
7160 (define_insn "*subqi_3"
7162 (compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
7163 (match_operand:QI 2 "general_operand" "qi,qm")))
7164 (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
7165 (minus:HI (match_dup 1) (match_dup 2)))]
7166 "ix86_match_ccmode (insn, CCmode)
7167 && ix86_binary_operator_ok (MINUS, QImode, operands)"
7168 "sub{b}\t{%2, %0|%0, %2}"
7169 [(set_attr "type" "alu")
7170 (set_attr "mode" "QI")])
7172 ;; The patterns that match these are at the end of this file.
7174 (define_expand "subxf3"
7175 [(set (match_operand:XF 0 "register_operand" "")
7176 (minus:XF (match_operand:XF 1 "register_operand" "")
7177 (match_operand:XF 2 "register_operand" "")))]
7178 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
7181 (define_expand "subtf3"
7182 [(set (match_operand:TF 0 "register_operand" "")
7183 (minus:TF (match_operand:TF 1 "register_operand" "")
7184 (match_operand:TF 2 "register_operand" "")))]
7188 (define_expand "subdf3"
7189 [(set (match_operand:DF 0 "register_operand" "")
7190 (minus:DF (match_operand:DF 1 "register_operand" "")
7191 (match_operand:DF 2 "nonimmediate_operand" "")))]
7192 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7195 (define_expand "subsf3"
7196 [(set (match_operand:SF 0 "register_operand" "")
7197 (minus:SF (match_operand:SF 1 "register_operand" "")
7198 (match_operand:SF 2 "nonimmediate_operand" "")))]
7199 "TARGET_80387 || TARGET_SSE_MATH"
7202 ;; Multiply instructions
7204 (define_expand "muldi3"
7205 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7206 (mult:DI (match_operand:DI 1 "register_operand" "")
7207 (match_operand:DI 2 "x86_64_general_operand" "")))
7208 (clobber (reg:CC 17))])]
7212 (define_insn "*muldi3_1_rex64"
7213 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7214 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
7215 (match_operand:DI 2 "x86_64_general_operand" "K,e,mr")))
7216 (clobber (reg:CC 17))]
7218 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7220 imul{q}\t{%2, %1, %0|%0, %1, %2}
7221 imul{q}\t{%2, %1, %0|%0, %1, %2}
7222 imul{q}\t{%2, %0|%0, %2}"
7223 [(set_attr "type" "imul")
7224 (set_attr "prefix_0f" "0,0,1")
7225 (set (attr "athlon_decode")
7226 (cond [(eq_attr "cpu" "athlon")
7227 (const_string "vector")
7228 (eq_attr "alternative" "1")
7229 (const_string "vector")
7230 (and (eq_attr "alternative" "2")
7231 (match_operand 1 "memory_operand" ""))
7232 (const_string "vector")]
7233 (const_string "direct")))
7234 (set_attr "mode" "DI")])
7236 (define_expand "mulsi3"
7237 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7238 (mult:SI (match_operand:SI 1 "register_operand" "")
7239 (match_operand:SI 2 "general_operand" "")))
7240 (clobber (reg:CC 17))])]
7244 (define_insn "*mulsi3_1"
7245 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7246 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7247 (match_operand:SI 2 "general_operand" "K,i,mr")))
7248 (clobber (reg:CC 17))]
7249 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7251 imul{l}\t{%2, %1, %0|%0, %1, %2}
7252 imul{l}\t{%2, %1, %0|%0, %1, %2}
7253 imul{l}\t{%2, %0|%0, %2}"
7254 [(set_attr "type" "imul")
7255 (set_attr "prefix_0f" "0,0,1")
7256 (set (attr "athlon_decode")
7257 (cond [(eq_attr "cpu" "athlon")
7258 (const_string "vector")
7259 (eq_attr "alternative" "1")
7260 (const_string "vector")
7261 (and (eq_attr "alternative" "2")
7262 (match_operand 1 "memory_operand" ""))
7263 (const_string "vector")]
7264 (const_string "direct")))
7265 (set_attr "mode" "SI")])
7267 (define_insn "*mulsi3_1_zext"
7268 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
7270 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
7271 (match_operand:SI 2 "general_operand" "K,i,mr"))))
7272 (clobber (reg:CC 17))]
7274 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7276 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7277 imul{l}\t{%2, %1, %k0|%k0, %1, %2}
7278 imul{l}\t{%2, %k0|%k0, %2}"
7279 [(set_attr "type" "imul")
7280 (set_attr "prefix_0f" "0,0,1")
7281 (set (attr "athlon_decode")
7282 (cond [(eq_attr "cpu" "athlon")
7283 (const_string "vector")
7284 (eq_attr "alternative" "1")
7285 (const_string "vector")
7286 (and (eq_attr "alternative" "2")
7287 (match_operand 1 "memory_operand" ""))
7288 (const_string "vector")]
7289 (const_string "direct")))
7290 (set_attr "mode" "SI")])
7292 (define_expand "mulhi3"
7293 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7294 (mult:HI (match_operand:HI 1 "register_operand" "")
7295 (match_operand:HI 2 "general_operand" "")))
7296 (clobber (reg:CC 17))])]
7297 "TARGET_HIMODE_MATH"
7300 (define_insn "*mulhi3_1"
7301 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
7302 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
7303 (match_operand:HI 2 "general_operand" "K,i,mr")))
7304 (clobber (reg:CC 17))]
7305 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7307 imul{w}\t{%2, %1, %0|%0, %1, %2}
7308 imul{w}\t{%2, %1, %0|%0, %1, %2}
7309 imul{w}\t{%2, %0|%0, %2}"
7310 [(set_attr "type" "imul")
7311 (set_attr "prefix_0f" "0,0,1")
7312 (set (attr "athlon_decode")
7313 (cond [(eq_attr "cpu" "athlon")
7314 (const_string "vector")
7315 (eq_attr "alternative" "1,2")
7316 (const_string "vector")]
7317 (const_string "direct")))
7318 (set_attr "mode" "HI")])
7320 (define_expand "mulqi3"
7321 [(parallel [(set (match_operand:QI 0 "register_operand" "")
7322 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "")
7323 (match_operand:QI 2 "register_operand" "")))
7324 (clobber (reg:CC 17))])]
7325 "TARGET_QIMODE_MATH"
7328 (define_insn "*mulqi3_1"
7329 [(set (match_operand:QI 0 "register_operand" "=a")
7330 (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
7331 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7332 (clobber (reg:CC 17))]
7334 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7336 [(set_attr "type" "imul")
7337 (set_attr "length_immediate" "0")
7338 (set (attr "athlon_decode")
7339 (if_then_else (eq_attr "cpu" "athlon")
7340 (const_string "vector")
7341 (const_string "direct")))
7342 (set_attr "mode" "QI")])
7344 (define_expand "umulqihi3"
7345 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7346 (mult:HI (zero_extend:HI
7347 (match_operand:QI 1 "nonimmediate_operand" ""))
7349 (match_operand:QI 2 "register_operand" ""))))
7350 (clobber (reg:CC 17))])]
7351 "TARGET_QIMODE_MATH"
7354 (define_insn "*umulqihi3_1"
7355 [(set (match_operand:HI 0 "register_operand" "=a")
7356 (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7357 (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7358 (clobber (reg:CC 17))]
7360 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7362 [(set_attr "type" "imul")
7363 (set_attr "length_immediate" "0")
7364 (set (attr "athlon_decode")
7365 (if_then_else (eq_attr "cpu" "athlon")
7366 (const_string "vector")
7367 (const_string "direct")))
7368 (set_attr "mode" "QI")])
7370 (define_expand "mulqihi3"
7371 [(parallel [(set (match_operand:HI 0 "register_operand" "")
7372 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" ""))
7373 (sign_extend:HI (match_operand:QI 2 "register_operand" ""))))
7374 (clobber (reg:CC 17))])]
7375 "TARGET_QIMODE_MATH"
7378 (define_insn "*mulqihi3_insn"
7379 [(set (match_operand:HI 0 "register_operand" "=a")
7380 (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0"))
7381 (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))
7382 (clobber (reg:CC 17))]
7384 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7386 [(set_attr "type" "imul")
7387 (set_attr "length_immediate" "0")
7388 (set (attr "athlon_decode")
7389 (if_then_else (eq_attr "cpu" "athlon")
7390 (const_string "vector")
7391 (const_string "direct")))
7392 (set_attr "mode" "QI")])
7394 (define_expand "umulditi3"
7395 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7396 (mult:TI (zero_extend:TI
7397 (match_operand:DI 1 "nonimmediate_operand" ""))
7399 (match_operand:DI 2 "register_operand" ""))))
7400 (clobber (reg:CC 17))])]
7404 (define_insn "*umulditi3_insn"
7405 [(set (match_operand:TI 0 "register_operand" "=A")
7406 (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7407 (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7408 (clobber (reg:CC 17))]
7410 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7412 [(set_attr "type" "imul")
7413 (set_attr "ppro_uops" "few")
7414 (set_attr "length_immediate" "0")
7415 (set (attr "athlon_decode")
7416 (if_then_else (eq_attr "cpu" "athlon")
7417 (const_string "vector")
7418 (const_string "double")))
7419 (set_attr "mode" "DI")])
7421 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
7422 (define_expand "umulsidi3"
7423 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7424 (mult:DI (zero_extend:DI
7425 (match_operand:SI 1 "nonimmediate_operand" ""))
7427 (match_operand:SI 2 "register_operand" ""))))
7428 (clobber (reg:CC 17))])]
7432 (define_insn "*umulsidi3_insn"
7433 [(set (match_operand:DI 0 "register_operand" "=A")
7434 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7435 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7436 (clobber (reg:CC 17))]
7438 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7440 [(set_attr "type" "imul")
7441 (set_attr "ppro_uops" "few")
7442 (set_attr "length_immediate" "0")
7443 (set (attr "athlon_decode")
7444 (if_then_else (eq_attr "cpu" "athlon")
7445 (const_string "vector")
7446 (const_string "double")))
7447 (set_attr "mode" "SI")])
7449 (define_expand "mulditi3"
7450 [(parallel [(set (match_operand:TI 0 "register_operand" "")
7451 (mult:TI (sign_extend:TI
7452 (match_operand:DI 1 "nonimmediate_operand" ""))
7454 (match_operand:DI 2 "register_operand" ""))))
7455 (clobber (reg:CC 17))])]
7459 (define_insn "*mulditi3_insn"
7460 [(set (match_operand:TI 0 "register_operand" "=A")
7461 (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0"))
7462 (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))))
7463 (clobber (reg:CC 17))]
7465 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7467 [(set_attr "type" "imul")
7468 (set_attr "length_immediate" "0")
7469 (set (attr "athlon_decode")
7470 (if_then_else (eq_attr "cpu" "athlon")
7471 (const_string "vector")
7472 (const_string "double")))
7473 (set_attr "mode" "DI")])
7475 (define_expand "mulsidi3"
7476 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7477 (mult:DI (sign_extend:DI
7478 (match_operand:SI 1 "nonimmediate_operand" ""))
7480 (match_operand:SI 2 "register_operand" ""))))
7481 (clobber (reg:CC 17))])]
7485 (define_insn "*mulsidi3_insn"
7486 [(set (match_operand:DI 0 "register_operand" "=A")
7487 (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0"))
7488 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))
7489 (clobber (reg:CC 17))]
7491 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7493 [(set_attr "type" "imul")
7494 (set_attr "length_immediate" "0")
7495 (set (attr "athlon_decode")
7496 (if_then_else (eq_attr "cpu" "athlon")
7497 (const_string "vector")
7498 (const_string "double")))
7499 (set_attr "mode" "SI")])
7501 (define_expand "umuldi3_highpart"
7502 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7505 (mult:TI (zero_extend:TI
7506 (match_operand:DI 1 "nonimmediate_operand" ""))
7508 (match_operand:DI 2 "register_operand" "")))
7510 (clobber (match_scratch:DI 3 ""))
7511 (clobber (reg:CC 17))])]
7515 (define_insn "*umuldi3_highpart_rex64"
7516 [(set (match_operand:DI 0 "register_operand" "=d")
7519 (mult:TI (zero_extend:TI
7520 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7522 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7524 (clobber (match_scratch:DI 3 "=1"))
7525 (clobber (reg:CC 17))]
7527 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7529 [(set_attr "type" "imul")
7530 (set_attr "ppro_uops" "few")
7531 (set_attr "length_immediate" "0")
7532 (set (attr "athlon_decode")
7533 (if_then_else (eq_attr "cpu" "athlon")
7534 (const_string "vector")
7535 (const_string "double")))
7536 (set_attr "mode" "DI")])
7538 (define_expand "umulsi3_highpart"
7539 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7542 (mult:DI (zero_extend:DI
7543 (match_operand:SI 1 "nonimmediate_operand" ""))
7545 (match_operand:SI 2 "register_operand" "")))
7547 (clobber (match_scratch:SI 3 ""))
7548 (clobber (reg:CC 17))])]
7552 (define_insn "*umulsi3_highpart_insn"
7553 [(set (match_operand:SI 0 "register_operand" "=d")
7556 (mult:DI (zero_extend:DI
7557 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7559 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7561 (clobber (match_scratch:SI 3 "=1"))
7562 (clobber (reg:CC 17))]
7563 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7565 [(set_attr "type" "imul")
7566 (set_attr "ppro_uops" "few")
7567 (set_attr "length_immediate" "0")
7568 (set (attr "athlon_decode")
7569 (if_then_else (eq_attr "cpu" "athlon")
7570 (const_string "vector")
7571 (const_string "double")))
7572 (set_attr "mode" "SI")])
7574 (define_insn "*umulsi3_highpart_zext"
7575 [(set (match_operand:DI 0 "register_operand" "=d")
7576 (zero_extend:DI (truncate:SI
7578 (mult:DI (zero_extend:DI
7579 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7581 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7583 (clobber (match_scratch:SI 3 "=1"))
7584 (clobber (reg:CC 17))]
7586 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7588 [(set_attr "type" "imul")
7589 (set_attr "ppro_uops" "few")
7590 (set_attr "length_immediate" "0")
7591 (set (attr "athlon_decode")
7592 (if_then_else (eq_attr "cpu" "athlon")
7593 (const_string "vector")
7594 (const_string "double")))
7595 (set_attr "mode" "SI")])
7597 (define_expand "smuldi3_highpart"
7598 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
7601 (mult:TI (sign_extend:TI
7602 (match_operand:DI 1 "nonimmediate_operand" ""))
7604 (match_operand:DI 2 "register_operand" "")))
7606 (clobber (match_scratch:DI 3 ""))
7607 (clobber (reg:CC 17))])]
7611 (define_insn "*smuldi3_highpart_rex64"
7612 [(set (match_operand:DI 0 "register_operand" "=d")
7615 (mult:TI (sign_extend:TI
7616 (match_operand:DI 1 "nonimmediate_operand" "%a"))
7618 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7620 (clobber (match_scratch:DI 3 "=1"))
7621 (clobber (reg:CC 17))]
7623 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7625 [(set_attr "type" "imul")
7626 (set_attr "ppro_uops" "few")
7627 (set (attr "athlon_decode")
7628 (if_then_else (eq_attr "cpu" "athlon")
7629 (const_string "vector")
7630 (const_string "double")))
7631 (set_attr "mode" "DI")])
7633 (define_expand "smulsi3_highpart"
7634 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7637 (mult:DI (sign_extend:DI
7638 (match_operand:SI 1 "nonimmediate_operand" ""))
7640 (match_operand:SI 2 "register_operand" "")))
7642 (clobber (match_scratch:SI 3 ""))
7643 (clobber (reg:CC 17))])]
7647 (define_insn "*smulsi3_highpart_insn"
7648 [(set (match_operand:SI 0 "register_operand" "=d")
7651 (mult:DI (sign_extend:DI
7652 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7654 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7656 (clobber (match_scratch:SI 3 "=1"))
7657 (clobber (reg:CC 17))]
7658 "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
7660 [(set_attr "type" "imul")
7661 (set_attr "ppro_uops" "few")
7662 (set (attr "athlon_decode")
7663 (if_then_else (eq_attr "cpu" "athlon")
7664 (const_string "vector")
7665 (const_string "double")))
7666 (set_attr "mode" "SI")])
7668 (define_insn "*smulsi3_highpart_zext"
7669 [(set (match_operand:DI 0 "register_operand" "=d")
7670 (zero_extend:DI (truncate:SI
7672 (mult:DI (sign_extend:DI
7673 (match_operand:SI 1 "nonimmediate_operand" "%a"))
7675 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7677 (clobber (match_scratch:SI 3 "=1"))
7678 (clobber (reg:CC 17))]
7680 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
7682 [(set_attr "type" "imul")
7683 (set_attr "ppro_uops" "few")
7684 (set (attr "athlon_decode")
7685 (if_then_else (eq_attr "cpu" "athlon")
7686 (const_string "vector")
7687 (const_string "double")))
7688 (set_attr "mode" "SI")])
7690 ;; The patterns that match these are at the end of this file.
7692 (define_expand "mulxf3"
7693 [(set (match_operand:XF 0 "register_operand" "")
7694 (mult:XF (match_operand:XF 1 "register_operand" "")
7695 (match_operand:XF 2 "register_operand" "")))]
7696 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
7699 (define_expand "multf3"
7700 [(set (match_operand:TF 0 "register_operand" "")
7701 (mult:TF (match_operand:TF 1 "register_operand" "")
7702 (match_operand:TF 2 "register_operand" "")))]
7706 (define_expand "muldf3"
7707 [(set (match_operand:DF 0 "register_operand" "")
7708 (mult:DF (match_operand:DF 1 "register_operand" "")
7709 (match_operand:DF 2 "nonimmediate_operand" "")))]
7710 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7713 (define_expand "mulsf3"
7714 [(set (match_operand:SF 0 "register_operand" "")
7715 (mult:SF (match_operand:SF 1 "register_operand" "")
7716 (match_operand:SF 2 "nonimmediate_operand" "")))]
7717 "TARGET_80387 || TARGET_SSE_MATH"
7720 ;; Divide instructions
7722 (define_insn "divqi3"
7723 [(set (match_operand:QI 0 "register_operand" "=a")
7724 (div:QI (match_operand:HI 1 "register_operand" "0")
7725 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7726 (clobber (reg:CC 17))]
7727 "TARGET_QIMODE_MATH"
7729 [(set_attr "type" "idiv")
7730 (set_attr "mode" "QI")
7731 (set_attr "ppro_uops" "few")])
7733 (define_insn "udivqi3"
7734 [(set (match_operand:QI 0 "register_operand" "=a")
7735 (udiv:QI (match_operand:HI 1 "register_operand" "0")
7736 (match_operand:QI 2 "nonimmediate_operand" "qm")))
7737 (clobber (reg:CC 17))]
7738 "TARGET_QIMODE_MATH"
7740 [(set_attr "type" "idiv")
7741 (set_attr "mode" "QI")
7742 (set_attr "ppro_uops" "few")])
7744 ;; The patterns that match these are at the end of this file.
7746 (define_expand "divxf3"
7747 [(set (match_operand:XF 0 "register_operand" "")
7748 (div:XF (match_operand:XF 1 "register_operand" "")
7749 (match_operand:XF 2 "register_operand" "")))]
7750 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
7753 (define_expand "divtf3"
7754 [(set (match_operand:TF 0 "register_operand" "")
7755 (div:TF (match_operand:TF 1 "register_operand" "")
7756 (match_operand:TF 2 "register_operand" "")))]
7760 (define_expand "divdf3"
7761 [(set (match_operand:DF 0 "register_operand" "")
7762 (div:DF (match_operand:DF 1 "register_operand" "")
7763 (match_operand:DF 2 "nonimmediate_operand" "")))]
7764 "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
7767 (define_expand "divsf3"
7768 [(set (match_operand:SF 0 "register_operand" "")
7769 (div:SF (match_operand:SF 1 "register_operand" "")
7770 (match_operand:SF 2 "nonimmediate_operand" "")))]
7771 "TARGET_80387 || TARGET_SSE_MATH"
7774 ;; Remainder instructions.
7776 (define_expand "divmoddi4"
7777 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7778 (div:DI (match_operand:DI 1 "register_operand" "")
7779 (match_operand:DI 2 "nonimmediate_operand" "")))
7780 (set (match_operand:DI 3 "register_operand" "")
7781 (mod:DI (match_dup 1) (match_dup 2)))
7782 (clobber (reg:CC 17))])]
7786 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7787 ;; Penalize eax case slightly because it results in worse scheduling
7789 (define_insn "*divmoddi4_nocltd_rex64"
7790 [(set (match_operand:DI 0 "register_operand" "=&a,?a")
7791 (div:DI (match_operand:DI 2 "register_operand" "1,0")
7792 (match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
7793 (set (match_operand:DI 1 "register_operand" "=&d,&d")
7794 (mod:DI (match_dup 2) (match_dup 3)))
7795 (clobber (reg:CC 17))]
7796 "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
7798 [(set_attr "type" "multi")])
7800 (define_insn "*divmoddi4_cltd_rex64"
7801 [(set (match_operand:DI 0 "register_operand" "=a")
7802 (div:DI (match_operand:DI 2 "register_operand" "a")
7803 (match_operand:DI 3 "nonimmediate_operand" "rm")))
7804 (set (match_operand:DI 1 "register_operand" "=&d")
7805 (mod:DI (match_dup 2) (match_dup 3)))
7806 (clobber (reg:CC 17))]
7807 "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
7809 [(set_attr "type" "multi")])
7811 (define_insn "*divmoddi_noext_rex64"
7812 [(set (match_operand:DI 0 "register_operand" "=a")
7813 (div:DI (match_operand:DI 1 "register_operand" "0")
7814 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7815 (set (match_operand:DI 3 "register_operand" "=d")
7816 (mod:DI (match_dup 1) (match_dup 2)))
7817 (use (match_operand:DI 4 "register_operand" "3"))
7818 (clobber (reg:CC 17))]
7821 [(set_attr "type" "idiv")
7822 (set_attr "mode" "DI")
7823 (set_attr "ppro_uops" "few")])
7826 [(set (match_operand:DI 0 "register_operand" "")
7827 (div:DI (match_operand:DI 1 "register_operand" "")
7828 (match_operand:DI 2 "nonimmediate_operand" "")))
7829 (set (match_operand:DI 3 "register_operand" "")
7830 (mod:DI (match_dup 1) (match_dup 2)))
7831 (clobber (reg:CC 17))]
7832 "TARGET_64BIT && reload_completed"
7833 [(parallel [(set (match_dup 3)
7834 (ashiftrt:DI (match_dup 4) (const_int 63)))
7835 (clobber (reg:CC 17))])
7836 (parallel [(set (match_dup 0)
7837 (div:DI (reg:DI 0) (match_dup 2)))
7839 (mod:DI (reg:DI 0) (match_dup 2)))
7841 (clobber (reg:CC 17))])]
7843 /* Avoid use of cltd in favor of a mov+shift. */
7844 if (!TARGET_USE_CLTD && !optimize_size)
7846 if (true_regnum (operands[1]))
7847 emit_move_insn (operands[0], operands[1]);
7849 emit_move_insn (operands[3], operands[1]);
7850 operands[4] = operands[3];
7854 if (true_regnum (operands[1]))
7856 operands[4] = operands[1];
7861 (define_expand "divmodsi4"
7862 [(parallel [(set (match_operand:SI 0 "register_operand" "")
7863 (div:SI (match_operand:SI 1 "register_operand" "")
7864 (match_operand:SI 2 "nonimmediate_operand" "")))
7865 (set (match_operand:SI 3 "register_operand" "")
7866 (mod:SI (match_dup 1) (match_dup 2)))
7867 (clobber (reg:CC 17))])]
7871 ;; Allow to come the parameter in eax or edx to avoid extra moves.
7872 ;; Penalize eax case slightly because it results in worse scheduling
7874 (define_insn "*divmodsi4_nocltd"
7875 [(set (match_operand:SI 0 "register_operand" "=&a,?a")
7876 (div:SI (match_operand:SI 2 "register_operand" "1,0")
7877 (match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
7878 (set (match_operand:SI 1 "register_operand" "=&d,&d")
7879 (mod:SI (match_dup 2) (match_dup 3)))
7880 (clobber (reg:CC 17))]
7881 "!optimize_size && !TARGET_USE_CLTD"
7883 [(set_attr "type" "multi")])
7885 (define_insn "*divmodsi4_cltd"
7886 [(set (match_operand:SI 0 "register_operand" "=a")
7887 (div:SI (match_operand:SI 2 "register_operand" "a")
7888 (match_operand:SI 3 "nonimmediate_operand" "rm")))
7889 (set (match_operand:SI 1 "register_operand" "=&d")
7890 (mod:SI (match_dup 2) (match_dup 3)))
7891 (clobber (reg:CC 17))]
7892 "optimize_size || TARGET_USE_CLTD"
7894 [(set_attr "type" "multi")])
7896 (define_insn "*divmodsi_noext"
7897 [(set (match_operand:SI 0 "register_operand" "=a")
7898 (div:SI (match_operand:SI 1 "register_operand" "0")
7899 (match_operand:SI 2 "nonimmediate_operand" "rm")))
7900 (set (match_operand:SI 3 "register_operand" "=d")
7901 (mod:SI (match_dup 1) (match_dup 2)))
7902 (use (match_operand:SI 4 "register_operand" "3"))
7903 (clobber (reg:CC 17))]
7906 [(set_attr "type" "idiv")
7907 (set_attr "mode" "SI")
7908 (set_attr "ppro_uops" "few")])
7911 [(set (match_operand:SI 0 "register_operand" "")
7912 (div:SI (match_operand:SI 1 "register_operand" "")
7913 (match_operand:SI 2 "nonimmediate_operand" "")))
7914 (set (match_operand:SI 3 "register_operand" "")
7915 (mod:SI (match_dup 1) (match_dup 2)))
7916 (clobber (reg:CC 17))]
7918 [(parallel [(set (match_dup 3)
7919 (ashiftrt:SI (match_dup 4) (const_int 31)))
7920 (clobber (reg:CC 17))])
7921 (parallel [(set (match_dup 0)
7922 (div:SI (reg:SI 0) (match_dup 2)))
7924 (mod:SI (reg:SI 0) (match_dup 2)))
7926 (clobber (reg:CC 17))])]
7928 /* Avoid use of cltd in favor of a mov+shift. */
7929 if (!TARGET_USE_CLTD && !optimize_size)
7931 if (true_regnum (operands[1]))
7932 emit_move_insn (operands[0], operands[1]);
7934 emit_move_insn (operands[3], operands[1]);
7935 operands[4] = operands[3];
7939 if (true_regnum (operands[1]))
7941 operands[4] = operands[1];
7945 (define_insn "divmodhi4"
7946 [(set (match_operand:HI 0 "register_operand" "=a")
7947 (div:HI (match_operand:HI 1 "register_operand" "0")
7948 (match_operand:HI 2 "nonimmediate_operand" "rm")))
7949 (set (match_operand:HI 3 "register_operand" "=&d")
7950 (mod:HI (match_dup 1) (match_dup 2)))
7951 (clobber (reg:CC 17))]
7952 "TARGET_HIMODE_MATH"
7954 [(set_attr "type" "multi")
7955 (set_attr "length_immediate" "0")
7956 (set_attr "mode" "SI")])
7958 (define_insn "udivmoddi4"
7959 [(set (match_operand:DI 0 "register_operand" "=a")
7960 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7961 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7962 (set (match_operand:DI 3 "register_operand" "=&d")
7963 (umod:DI (match_dup 1) (match_dup 2)))
7964 (clobber (reg:CC 17))]
7966 "xor{q}\t%3, %3\;div{q}\t%2"
7967 [(set_attr "type" "multi")
7968 (set_attr "length_immediate" "0")
7969 (set_attr "mode" "DI")])
7971 (define_insn "*udivmoddi4_noext"
7972 [(set (match_operand:DI 0 "register_operand" "=a")
7973 (udiv:DI (match_operand:DI 1 "register_operand" "0")
7974 (match_operand:DI 2 "nonimmediate_operand" "rm")))
7975 (set (match_operand:DI 3 "register_operand" "=d")
7976 (umod:DI (match_dup 1) (match_dup 2)))
7978 (clobber (reg:CC 17))]
7981 [(set_attr "type" "idiv")
7982 (set_attr "ppro_uops" "few")
7983 (set_attr "mode" "DI")])
7986 [(set (match_operand:DI 0 "register_operand" "")
7987 (udiv:DI (match_operand:DI 1 "register_operand" "")
7988 (match_operand:DI 2 "nonimmediate_operand" "")))
7989 (set (match_operand:DI 3 "register_operand" "")
7990 (umod:DI (match_dup 1) (match_dup 2)))
7991 (clobber (reg:CC 17))]
7992 "TARGET_64BIT && reload_completed"
7993 [(set (match_dup 3) (const_int 0))
7994 (parallel [(set (match_dup 0)
7995 (udiv:DI (match_dup 1) (match_dup 2)))
7997 (umod:DI (match_dup 1) (match_dup 2)))
7999 (clobber (reg:CC 17))])]
8002 (define_insn "udivmodsi4"
8003 [(set (match_operand:SI 0 "register_operand" "=a")
8004 (udiv:SI (match_operand:SI 1 "register_operand" "0")
8005 (match_operand:SI 2 "nonimmediate_operand" "rm")))
8006 (set (match_operand:SI 3 "register_operand" "=&d")
8007 (umod:SI (match_dup 1) (match_dup 2)))
8008 (clobber (reg:CC 17))]
8010 "xor{l}\t%3, %3\;div{l}\t%2"
8011 [(set_attr "type" "multi")
8012 (set_attr "length_immediate" "0")
8013 (set_attr "mode" "SI")])
8015 (define_insn "*udivmodsi4_noext"
8016 [(set (match_operand:SI 0 "register_operand" "=a")
8017 (udiv:SI (match_operand:SI 1 "register_operand" "0")
8018 (match_operand:SI 2 "nonimmediate_operand" "rm")))
8019 (set (match_operand:SI 3 "register_operand" "=d")
8020 (umod:SI (match_dup 1) (match_dup 2)))
8022 (clobber (reg:CC 17))]
8025 [(set_attr "type" "idiv")
8026 (set_attr "ppro_uops" "few")
8027 (set_attr "mode" "SI")])
8030 [(set (match_operand:SI 0 "register_operand" "")
8031 (udiv:SI (match_operand:SI 1 "register_operand" "")
8032 (match_operand:SI 2 "nonimmediate_operand" "")))
8033 (set (match_operand:SI 3 "register_operand" "")
8034 (umod:SI (match_dup 1) (match_dup 2)))
8035 (clobber (reg:CC 17))]
8037 [(set (match_dup 3) (const_int 0))
8038 (parallel [(set (match_dup 0)
8039 (udiv:SI (match_dup 1) (match_dup 2)))
8041 (umod:SI (match_dup 1) (match_dup 2)))
8043 (clobber (reg:CC 17))])]
8046 (define_expand "udivmodhi4"
8047 [(set (match_dup 4) (const_int 0))
8048 (parallel [(set (match_operand:HI 0 "register_operand" "")
8049 (udiv:HI (match_operand:HI 1 "register_operand" "")
8050 (match_operand:HI 2 "nonimmediate_operand" "")))
8051 (set (match_operand:HI 3 "register_operand" "")
8052 (umod:HI (match_dup 1) (match_dup 2)))
8054 (clobber (reg:CC 17))])]
8055 "TARGET_HIMODE_MATH"
8056 "operands[4] = gen_reg_rtx (HImode);")
8058 (define_insn "*udivmodhi_noext"
8059 [(set (match_operand:HI 0 "register_operand" "=a")
8060 (udiv:HI (match_operand:HI 1 "register_operand" "0")
8061 (match_operand:HI 2 "nonimmediate_operand" "rm")))
8062 (set (match_operand:HI 3 "register_operand" "=d")
8063 (umod:HI (match_dup 1) (match_dup 2)))
8064 (use (match_operand:HI 4 "register_operand" "3"))
8065 (clobber (reg:CC 17))]
8068 [(set_attr "type" "idiv")
8069 (set_attr "mode" "HI")
8070 (set_attr "ppro_uops" "few")])
8072 ;; We can not use div/idiv for double division, because it causes
8073 ;; "division by zero" on the overflow and that's not what we expect
8074 ;; from truncate. Because true (non truncating) double division is
8075 ;; never generated, we can't create this insn anyway.
8078 ; [(set (match_operand:SI 0 "register_operand" "=a")
8080 ; (udiv:DI (match_operand:DI 1 "register_operand" "A")
8082 ; (match_operand:SI 2 "nonimmediate_operand" "rm")))))
8083 ; (set (match_operand:SI 3 "register_operand" "=d")
8085 ; (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
8086 ; (clobber (reg:CC 17))]
8088 ; "div{l}\t{%2, %0|%0, %2}"
8089 ; [(set_attr "type" "idiv")
8090 ; (set_attr "ppro_uops" "few")])
8092 ;;- Logical AND instructions
8094 ;; On Pentium, "test imm, reg" is pairable only with eax, ax, and al.
8095 ;; Note that this excludes ah.
8097 (define_insn "*testdi_1_rex64"
8100 (and:DI (match_operand:DI 0 "nonimmediate_operand" "%!*a,r,!*a,r,rm")
8101 (match_operand:DI 1 "x86_64_szext_general_operand" "Z,Z,e,e,re"))
8103 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8104 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8106 test{l}\t{%k1, %k0|%k0, %k1}
8107 test{l}\t{%k1, %k0|%k0, %k1}
8108 test{q}\t{%1, %0|%0, %1}
8109 test{q}\t{%1, %0|%0, %1}
8110 test{q}\t{%1, %0|%0, %1}"
8111 [(set_attr "type" "test")
8112 (set_attr "modrm" "0,1,0,1,1")
8113 (set_attr "mode" "SI,SI,DI,DI,DI")
8114 (set_attr "pent_pair" "uv,np,uv,np,uv")])
8116 (define_insn "testsi_1"
8119 (and:SI (match_operand:SI 0 "nonimmediate_operand" "%!*a,r,rm")
8120 (match_operand:SI 1 "general_operand" "in,in,rin"))
8122 "ix86_match_ccmode (insn, CCNOmode)
8123 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8124 "test{l}\t{%1, %0|%0, %1}"
8125 [(set_attr "type" "test")
8126 (set_attr "modrm" "0,1,1")
8127 (set_attr "mode" "SI")
8128 (set_attr "pent_pair" "uv,np,uv")])
8130 (define_expand "testsi_ccno_1"
8133 (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
8134 (match_operand:SI 1 "nonmemory_operand" ""))
8139 (define_insn "*testhi_1"
8141 (compare (and:HI (match_operand:HI 0 "nonimmediate_operand" "%!*a,r,rm")
8142 (match_operand:HI 1 "general_operand" "n,n,rn"))
8144 "ix86_match_ccmode (insn, CCNOmode)
8145 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8146 "test{w}\t{%1, %0|%0, %1}"
8147 [(set_attr "type" "test")
8148 (set_attr "modrm" "0,1,1")
8149 (set_attr "mode" "HI")
8150 (set_attr "pent_pair" "uv,np,uv")])
8152 (define_expand "testqi_ccz_1"
8154 (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
8155 (match_operand:QI 1 "nonmemory_operand" ""))
8160 (define_insn "*testqi_1"
8162 (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r")
8163 (match_operand:QI 1 "general_operand" "n,n,qn,n"))
8165 "ix86_match_ccmode (insn, CCNOmode)
8166 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8168 if (which_alternative == 3)
8170 if (GET_CODE (operands[1]) == CONST_INT
8171 && (INTVAL (operands[1]) & 0xffffff00))
8172 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
8173 return "test{l}\t{%1, %k0|%k0, %1}";
8175 return "test{b}\t{%1, %0|%0, %1}";
8177 [(set_attr "type" "test")
8178 (set_attr "modrm" "0,1,1,1")
8179 (set_attr "mode" "QI,QI,QI,SI")
8180 (set_attr "pent_pair" "uv,np,uv,np")])
8182 (define_expand "testqi_ext_ccno_0"
8187 (match_operand 0 "ext_register_operand" "")
8190 (match_operand 1 "const_int_operand" ""))
8195 (define_insn "*testqi_ext_0"
8200 (match_operand 0 "ext_register_operand" "Q")
8203 (match_operand 1 "const_int_operand" "n"))
8205 "ix86_match_ccmode (insn, CCNOmode)"
8206 "test{b}\t{%1, %h0|%h0, %1}"
8207 [(set_attr "type" "test")
8208 (set_attr "mode" "QI")
8209 (set_attr "length_immediate" "1")
8210 (set_attr "pent_pair" "np")])
8212 (define_insn "*testqi_ext_1"
8217 (match_operand 0 "ext_register_operand" "Q")
8221 (match_operand:QI 1 "general_operand" "Qm")))
8223 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8224 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8225 "test{b}\t{%1, %h0|%h0, %1}"
8226 [(set_attr "type" "test")
8227 (set_attr "mode" "QI")])
8229 (define_insn "*testqi_ext_1_rex64"
8234 (match_operand 0 "ext_register_operand" "Q")
8238 (match_operand:QI 1 "register_operand" "Q")))
8240 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
8241 "test{b}\t{%1, %h0|%h0, %1}"
8242 [(set_attr "type" "test")
8243 (set_attr "mode" "QI")])
8245 (define_insn "*testqi_ext_2"
8250 (match_operand 0 "ext_register_operand" "Q")
8254 (match_operand 1 "ext_register_operand" "Q")
8258 "ix86_match_ccmode (insn, CCNOmode)"
8259 "test{b}\t{%h1, %h0|%h0, %h1}"
8260 [(set_attr "type" "test")
8261 (set_attr "mode" "QI")])
8263 ;; Combine likes to form bit extractions for some tests. Humor it.
8264 (define_insn "*testqi_ext_3"
8266 (compare (zero_extract:SI
8267 (match_operand 0 "nonimmediate_operand" "rm")
8268 (match_operand:SI 1 "const_int_operand" "")
8269 (match_operand:SI 2 "const_int_operand" ""))
8271 "ix86_match_ccmode (insn, CCNOmode)
8272 && (GET_MODE (operands[0]) == SImode
8273 || (TARGET_64BIT && GET_MODE (operands[0]) == DImode)
8274 || GET_MODE (operands[0]) == HImode
8275 || GET_MODE (operands[0]) == QImode)"
8278 (define_insn "*testqi_ext_3_rex64"
8280 (compare (zero_extract:DI
8281 (match_operand 0 "nonimmediate_operand" "rm")
8282 (match_operand:DI 1 "const_int_operand" "")
8283 (match_operand:DI 2 "const_int_operand" ""))
8286 && ix86_match_ccmode (insn, CCNOmode)
8287 /* The code below cannot deal with constants outside HOST_WIDE_INT. */
8288 && INTVAL (operands[1]) + INTVAL (operands[2]) < HOST_BITS_PER_WIDE_INT
8289 /* Ensure that resulting mask is zero or sign extended operand. */
8290 && (INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
8291 || (INTVAL (operands[1]) + INTVAL (operands[2]) == 64
8292 && INTVAL (operands[1]) > 32))
8293 && (GET_MODE (operands[0]) == SImode
8294 || GET_MODE (operands[0]) == DImode
8295 || GET_MODE (operands[0]) == HImode
8296 || GET_MODE (operands[0]) == QImode)"
8301 (compare (zero_extract
8302 (match_operand 0 "nonimmediate_operand" "")
8303 (match_operand 1 "const_int_operand" "")
8304 (match_operand 2 "const_int_operand" ""))
8306 "ix86_match_ccmode (insn, CCNOmode)"
8307 [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
8309 HOST_WIDE_INT len = INTVAL (operands[1]);
8310 HOST_WIDE_INT pos = INTVAL (operands[2]);
8312 enum machine_mode mode, submode;
8314 mode = GET_MODE (operands[0]);
8315 if (GET_CODE (operands[0]) == MEM)
8317 /* ??? Combine likes to put non-volatile mem extractions in QImode
8318 no matter the size of the test. So find a mode that works. */
8319 if (! MEM_VOLATILE_P (operands[0]))
8321 mode = smallest_mode_for_size (pos + len, MODE_INT);
8322 operands[0] = adjust_address (operands[0], mode, 0);
8325 else if (GET_CODE (operands[0]) == SUBREG
8326 && (submode = GET_MODE (SUBREG_REG (operands[0])),
8327 GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
8328 && pos + len <= GET_MODE_BITSIZE (submode))
8330 /* Narrow a paradoxical subreg to prevent partial register stalls. */
8332 operands[0] = SUBREG_REG (operands[0]);
8334 else if (mode == HImode && pos + len <= 8)
8336 /* Small HImode tests can be converted to QImode. */
8338 operands[0] = gen_lowpart (QImode, operands[0]);
8341 mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
8342 mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
8344 operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
8347 ;; Convert HImode/SImode test instructions with immediate to QImode ones.
8348 ;; i386 does not allow to encode test with 8bit sign extended immediate, so
8349 ;; this is relatively important trick.
8350 ;; Do the conversion only post-reload to avoid limiting of the register class
8355 (and (match_operand 0 "register_operand" "")
8356 (match_operand 1 "const_int_operand" ""))
8359 && QI_REG_P (operands[0])
8360 && ((ix86_match_ccmode (insn, CCZmode)
8361 && !(INTVAL (operands[1]) & ~(255 << 8)))
8362 || (ix86_match_ccmode (insn, CCNOmode)
8363 && !(INTVAL (operands[1]) & ~(127 << 8))))
8364 && GET_MODE (operands[0]) != QImode"
8367 (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8370 "operands[0] = gen_lowpart (SImode, operands[0]);
8371 operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);")
8376 (and (match_operand 0 "nonimmediate_operand" "")
8377 (match_operand 1 "const_int_operand" ""))
8380 && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0]))
8381 && ((ix86_match_ccmode (insn, CCZmode)
8382 && !(INTVAL (operands[1]) & ~255))
8383 || (ix86_match_ccmode (insn, CCNOmode)
8384 && !(INTVAL (operands[1]) & ~127)))
8385 && GET_MODE (operands[0]) != QImode"
8388 (and:QI (match_dup 0)
8391 "operands[0] = gen_lowpart (QImode, operands[0]);
8392 operands[1] = gen_lowpart (QImode, operands[1]);")
8395 ;; %%% This used to optimize known byte-wide and operations to memory,
8396 ;; and sometimes to QImode registers. If this is considered useful,
8397 ;; it should be done with splitters.
8399 (define_expand "anddi3"
8400 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8401 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
8402 (match_operand:DI 2 "x86_64_szext_general_operand" "")))
8403 (clobber (reg:CC 17))]
8405 "ix86_expand_binary_operator (AND, DImode, operands); DONE;")
8407 (define_insn "*anddi_1_rex64"
8408 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
8409 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,qm")
8410 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,re,rm,L")))
8411 (clobber (reg:CC 17))]
8412 "TARGET_64BIT && ix86_binary_operator_ok (AND, DImode, operands)"
8414 switch (get_attr_type (insn))
8418 enum machine_mode mode;
8420 if (GET_CODE (operands[2]) != CONST_INT)
8422 if (INTVAL (operands[2]) == 0xff)
8424 else if (INTVAL (operands[2]) == 0xffff)
8429 operands[1] = gen_lowpart (mode, operands[1]);
8431 return "movz{bq|x}\t{%1,%0|%0, %1}";
8433 return "movz{wq|x}\t{%1,%0|%0, %1}";
8437 if (! rtx_equal_p (operands[0], operands[1]))
8439 if (get_attr_mode (insn) == MODE_SI)
8440 return "and{l}\t{%k2, %k0|%k0, %k2}";
8442 return "and{q}\t{%2, %0|%0, %2}";
8445 [(set_attr "type" "alu,alu,alu,imovx")
8446 (set_attr "length_immediate" "*,*,*,0")
8447 (set_attr "mode" "SI,DI,DI,DI")])
8449 (define_insn "*anddi_2"
8451 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
8452 (match_operand:DI 2 "x86_64_szext_general_operand" "Z,rem,re"))
8454 (set (match_operand:DI 0 "nonimmediate_operand" "=r,r,rm")
8455 (and:DI (match_dup 1) (match_dup 2)))]
8456 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8457 && ix86_binary_operator_ok (AND, DImode, operands)"
8459 and{l}\t{%k2, %k0|%k0, %k2}
8460 and{q}\t{%2, %0|%0, %2}
8461 and{q}\t{%2, %0|%0, %2}"
8462 [(set_attr "type" "alu")
8463 (set_attr "mode" "SI,DI,DI")])
8465 (define_expand "andsi3"
8466 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8467 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
8468 (match_operand:SI 2 "general_operand" "")))
8469 (clobber (reg:CC 17))]
8471 "ix86_expand_binary_operator (AND, SImode, operands); DONE;")
8473 (define_insn "*andsi_1"
8474 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r,r")
8475 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,qm")
8476 (match_operand:SI 2 "general_operand" "ri,rm,L")))
8477 (clobber (reg:CC 17))]
8478 "ix86_binary_operator_ok (AND, SImode, operands)"
8480 switch (get_attr_type (insn))
8484 enum machine_mode mode;
8486 if (GET_CODE (operands[2]) != CONST_INT)
8488 if (INTVAL (operands[2]) == 0xff)
8490 else if (INTVAL (operands[2]) == 0xffff)
8495 operands[1] = gen_lowpart (mode, operands[1]);
8497 return "movz{bl|x}\t{%1,%0|%0, %1}";
8499 return "movz{wl|x}\t{%1,%0|%0, %1}";
8503 if (! rtx_equal_p (operands[0], operands[1]))
8505 return "and{l}\t{%2, %0|%0, %2}";
8508 [(set_attr "type" "alu,alu,imovx")
8509 (set_attr "length_immediate" "*,*,0")
8510 (set_attr "mode" "SI")])
8513 [(set (match_operand 0 "register_operand" "")
8515 (const_int -65536)))
8516 (clobber (reg:CC 17))]
8517 "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
8518 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8519 "operands[1] = gen_lowpart (HImode, operands[0]);")
8522 [(set (match_operand 0 "ext_register_operand" "")
8525 (clobber (reg:CC 17))]
8526 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8527 [(set (strict_low_part (match_dup 1)) (const_int 0))]
8528 "operands[1] = gen_lowpart (QImode, operands[0]);")
8531 [(set (match_operand 0 "ext_register_operand" "")
8533 (const_int -65281)))
8534 (clobber (reg:CC 17))]
8535 "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
8536 [(parallel [(set (zero_extract:SI (match_dup 0)
8540 (zero_extract:SI (match_dup 0)
8543 (zero_extract:SI (match_dup 0)
8546 (clobber (reg:CC 17))])]
8547 "operands[0] = gen_lowpart (SImode, operands[0]);")
8549 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8550 (define_insn "*andsi_1_zext"
8551 [(set (match_operand:DI 0 "register_operand" "=r")
8553 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8554 (match_operand:SI 2 "general_operand" "rim"))))
8555 (clobber (reg:CC 17))]
8556 "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
8557 "and{l}\t{%2, %k0|%k0, %2}"
8558 [(set_attr "type" "alu")
8559 (set_attr "mode" "SI")])
8561 (define_insn "*andsi_2"
8563 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8564 (match_operand:SI 2 "general_operand" "rim,ri"))
8566 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8567 (and:SI (match_dup 1) (match_dup 2)))]
8568 "ix86_match_ccmode (insn, CCNOmode)
8569 && ix86_binary_operator_ok (AND, SImode, operands)"
8570 "and{l}\t{%2, %0|%0, %2}"
8571 [(set_attr "type" "alu")
8572 (set_attr "mode" "SI")])
8574 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8575 (define_insn "*andsi_2_zext"
8577 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8578 (match_operand:SI 2 "general_operand" "rim"))
8580 (set (match_operand:DI 0 "register_operand" "=r")
8581 (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
8582 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8583 && ix86_binary_operator_ok (AND, SImode, operands)"
8584 "and{l}\t{%2, %k0|%k0, %2}"
8585 [(set_attr "type" "alu")
8586 (set_attr "mode" "SI")])
8588 (define_expand "andhi3"
8589 [(set (match_operand:HI 0 "nonimmediate_operand" "")
8590 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
8591 (match_operand:HI 2 "general_operand" "")))
8592 (clobber (reg:CC 17))]
8593 "TARGET_HIMODE_MATH"
8594 "ix86_expand_binary_operator (AND, HImode, operands); DONE;")
8596 (define_insn "*andhi_1"
8597 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r,r")
8598 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,qm")
8599 (match_operand:HI 2 "general_operand" "ri,rm,L")))
8600 (clobber (reg:CC 17))]
8601 "ix86_binary_operator_ok (AND, HImode, operands)"
8603 switch (get_attr_type (insn))
8606 if (GET_CODE (operands[2]) != CONST_INT)
8608 if (INTVAL (operands[2]) == 0xff)
8609 return "movz{bl|x}\t{%b1, %k0|%k0, %b1}";
8613 if (! rtx_equal_p (operands[0], operands[1]))
8616 return "and{w}\t{%2, %0|%0, %2}";
8619 [(set_attr "type" "alu,alu,imovx")
8620 (set_attr "length_immediate" "*,*,0")
8621 (set_attr "mode" "HI,HI,SI")])
8623 (define_insn "*andhi_2"
8625 (compare (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
8626 (match_operand:HI 2 "general_operand" "rim,ri"))
8628 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
8629 (and:HI (match_dup 1) (match_dup 2)))]
8630 "ix86_match_ccmode (insn, CCNOmode)
8631 && ix86_binary_operator_ok (AND, HImode, operands)"
8632 "and{w}\t{%2, %0|%0, %2}"
8633 [(set_attr "type" "alu")
8634 (set_attr "mode" "HI")])
8636 (define_expand "andqi3"
8637 [(set (match_operand:QI 0 "nonimmediate_operand" "")
8638 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
8639 (match_operand:QI 2 "general_operand" "")))
8640 (clobber (reg:CC 17))]
8641 "TARGET_QIMODE_MATH"
8642 "ix86_expand_binary_operator (AND, QImode, operands); DONE;")
8644 ;; %%% Potential partial reg stall on alternative 2. What to do?
8645 (define_insn "*andqi_1"
8646 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,q,r")
8647 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8648 (match_operand:QI 2 "general_operand" "qi,qmi,ri")))
8649 (clobber (reg:CC 17))]
8650 "ix86_binary_operator_ok (AND, QImode, operands)"
8652 and{b}\t{%2, %0|%0, %2}
8653 and{b}\t{%2, %0|%0, %2}
8654 and{l}\t{%k2, %k0|%k0, %k2}"
8655 [(set_attr "type" "alu")
8656 (set_attr "mode" "QI,QI,SI")])
8658 (define_insn "*andqi_1_slp"
8659 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
8660 (and:QI (match_dup 0)
8661 (match_operand:QI 1 "general_operand" "qi,qmi")))
8662 (clobber (reg:CC 17))]
8663 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8664 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8665 "and{b}\t{%1, %0|%0, %1}"
8666 [(set_attr "type" "alu1")
8667 (set_attr "mode" "QI")])
8669 (define_insn "*andqi_2"
8672 (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
8673 (match_operand:QI 2 "general_operand" "qim,qi,i"))
8675 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r")
8676 (and:QI (match_dup 1) (match_dup 2)))]
8677 "ix86_match_ccmode (insn, CCNOmode)
8678 && ix86_binary_operator_ok (AND, QImode, operands)"
8680 if (which_alternative == 2)
8682 if (GET_CODE (operands[2]) == CONST_INT
8683 && (INTVAL (operands[2]) & 0xffffff00))
8684 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
8685 return "and{l}\t{%2, %k0|%k0, %2}";
8687 return "and{b}\t{%2, %0|%0, %2}";
8689 [(set_attr "type" "alu")
8690 (set_attr "mode" "QI,QI,SI")])
8692 (define_insn "*andqi_2_slp"
8695 (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
8696 (match_operand:QI 1 "nonimmediate_operand" "qmi,qi"))
8698 (set (strict_low_part (match_dup 0))
8699 (and:QI (match_dup 0) (match_dup 1)))]
8700 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
8701 && ix86_match_ccmode (insn, CCNOmode)
8702 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
8703 "and{b}\t{%1, %0|%0, %1}"
8704 [(set_attr "type" "alu1")
8705 (set_attr "mode" "QI")])
8707 ;; ??? A bug in recog prevents it from recognizing a const_int as an
8708 ;; operand to zero_extend in andqi_ext_1. It was checking explicitly
8709 ;; for a QImode operand, which of course failed.
8711 (define_insn "andqi_ext_0"
8712 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8717 (match_operand 1 "ext_register_operand" "0")
8720 (match_operand 2 "const_int_operand" "n")))
8721 (clobber (reg:CC 17))]
8723 "and{b}\t{%2, %h0|%h0, %2}"
8724 [(set_attr "type" "alu")
8725 (set_attr "length_immediate" "1")
8726 (set_attr "mode" "QI")])
8728 ;; Generated by peephole translating test to and. This shows up
8729 ;; often in fp comparisons.
8731 (define_insn "*andqi_ext_0_cc"
8736 (match_operand 1 "ext_register_operand" "0")
8739 (match_operand 2 "const_int_operand" "n"))
8741 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8750 "ix86_match_ccmode (insn, CCNOmode)"
8751 "and{b}\t{%2, %h0|%h0, %2}"
8752 [(set_attr "type" "alu")
8753 (set_attr "length_immediate" "1")
8754 (set_attr "mode" "QI")])
8756 (define_insn "*andqi_ext_1"
8757 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8762 (match_operand 1 "ext_register_operand" "0")
8766 (match_operand:QI 2 "general_operand" "Qm"))))
8767 (clobber (reg:CC 17))]
8769 "and{b}\t{%2, %h0|%h0, %2}"
8770 [(set_attr "type" "alu")
8771 (set_attr "length_immediate" "0")
8772 (set_attr "mode" "QI")])
8774 (define_insn "*andqi_ext_1_rex64"
8775 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8780 (match_operand 1 "ext_register_operand" "0")
8784 (match_operand 2 "ext_register_operand" "Q"))))
8785 (clobber (reg:CC 17))]
8787 "and{b}\t{%2, %h0|%h0, %2}"
8788 [(set_attr "type" "alu")
8789 (set_attr "length_immediate" "0")
8790 (set_attr "mode" "QI")])
8792 (define_insn "*andqi_ext_2"
8793 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
8798 (match_operand 1 "ext_register_operand" "%0")
8802 (match_operand 2 "ext_register_operand" "Q")
8805 (clobber (reg:CC 17))]
8807 "and{b}\t{%h2, %h0|%h0, %h2}"
8808 [(set_attr "type" "alu")
8809 (set_attr "length_immediate" "0")
8810 (set_attr "mode" "QI")])
8812 ;; Convert wide AND instructions with immediate operand to shorter QImode
8813 ;; equivalents when possible.
8814 ;; Don't do the splitting with memory operands, since it introduces risk
8815 ;; of memory mismatch stalls. We may want to do the splitting for optimizing
8816 ;; for size, but that can (should?) be handled by generic code instead.
8818 [(set (match_operand 0 "register_operand" "")
8819 (and (match_operand 1 "register_operand" "")
8820 (match_operand 2 "const_int_operand" "")))
8821 (clobber (reg:CC 17))]
8823 && QI_REG_P (operands[0])
8824 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8825 && !(~INTVAL (operands[2]) & ~(255 << 8))
8826 && GET_MODE (operands[0]) != QImode"
8827 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
8828 (and:SI (zero_extract:SI (match_dup 1)
8829 (const_int 8) (const_int 8))
8831 (clobber (reg:CC 17))])]
8832 "operands[0] = gen_lowpart (SImode, operands[0]);
8833 operands[1] = gen_lowpart (SImode, operands[1]);
8834 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
8836 ;; Since AND can be encoded with sign extended immediate, this is only
8837 ;; profitable when 7th bit is not set.
8839 [(set (match_operand 0 "register_operand" "")
8840 (and (match_operand 1 "general_operand" "")
8841 (match_operand 2 "const_int_operand" "")))
8842 (clobber (reg:CC 17))]
8844 && ANY_QI_REG_P (operands[0])
8845 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
8846 && !(~INTVAL (operands[2]) & ~255)
8847 && !(INTVAL (operands[2]) & 128)
8848 && GET_MODE (operands[0]) != QImode"
8849 [(parallel [(set (strict_low_part (match_dup 0))
8850 (and:QI (match_dup 1)
8852 (clobber (reg:CC 17))])]
8853 "operands[0] = gen_lowpart (QImode, operands[0]);
8854 operands[1] = gen_lowpart (QImode, operands[1]);
8855 operands[2] = gen_lowpart (QImode, operands[2]);")
8857 ;; Logical inclusive OR instructions
8859 ;; %%% This used to optimize known byte-wide and operations to memory.
8860 ;; If this is considered useful, it should be done with splitters.
8862 (define_expand "iordi3"
8863 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8864 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
8865 (match_operand:DI 2 "x86_64_general_operand" "")))
8866 (clobber (reg:CC 17))]
8868 "ix86_expand_binary_operator (IOR, DImode, operands); DONE;")
8870 (define_insn "*iordi_1_rex64"
8871 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
8872 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8873 (match_operand:DI 2 "x86_64_general_operand" "re,rme")))
8874 (clobber (reg:CC 17))]
8876 && ix86_binary_operator_ok (IOR, DImode, operands)"
8877 "or{q}\t{%2, %0|%0, %2}"
8878 [(set_attr "type" "alu")
8879 (set_attr "mode" "DI")])
8881 (define_insn "*iordi_2_rex64"
8883 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
8884 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
8886 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
8887 (ior:DI (match_dup 1) (match_dup 2)))]
8889 && ix86_match_ccmode (insn, CCNOmode)
8890 && ix86_binary_operator_ok (IOR, DImode, operands)"
8891 "or{q}\t{%2, %0|%0, %2}"
8892 [(set_attr "type" "alu")
8893 (set_attr "mode" "DI")])
8895 (define_insn "*iordi_3_rex64"
8897 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
8898 (match_operand:DI 2 "x86_64_general_operand" "rem"))
8900 (clobber (match_scratch:DI 0 "=r"))]
8902 && ix86_match_ccmode (insn, CCNOmode)
8903 && ix86_binary_operator_ok (IOR, DImode, operands)"
8904 "or{q}\t{%2, %0|%0, %2}"
8905 [(set_attr "type" "alu")
8906 (set_attr "mode" "DI")])
8909 (define_expand "iorsi3"
8910 [(set (match_operand:SI 0 "nonimmediate_operand" "")
8911 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
8912 (match_operand:SI 2 "general_operand" "")))
8913 (clobber (reg:CC 17))]
8915 "ix86_expand_binary_operator (IOR, SImode, operands); DONE;")
8917 (define_insn "*iorsi_1"
8918 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
8919 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8920 (match_operand:SI 2 "general_operand" "ri,rmi")))
8921 (clobber (reg:CC 17))]
8922 "ix86_binary_operator_ok (IOR, SImode, operands)"
8923 "or{l}\t{%2, %0|%0, %2}"
8924 [(set_attr "type" "alu")
8925 (set_attr "mode" "SI")])
8927 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8928 (define_insn "*iorsi_1_zext"
8929 [(set (match_operand:DI 0 "register_operand" "=rm")
8931 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8932 (match_operand:SI 2 "general_operand" "rim"))))
8933 (clobber (reg:CC 17))]
8934 "TARGET_64BIT && ix86_binary_operator_ok (IOR, SImode, operands)"
8935 "or{l}\t{%2, %k0|%k0, %2}"
8936 [(set_attr "type" "alu")
8937 (set_attr "mode" "SI")])
8939 (define_insn "*iorsi_1_zext_imm"
8940 [(set (match_operand:DI 0 "register_operand" "=rm")
8941 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
8942 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
8943 (clobber (reg:CC 17))]
8945 "or{l}\t{%2, %k0|%k0, %2}"
8946 [(set_attr "type" "alu")
8947 (set_attr "mode" "SI")])
8949 (define_insn "*iorsi_2"
8951 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
8952 (match_operand:SI 2 "general_operand" "rim,ri"))
8954 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
8955 (ior:SI (match_dup 1) (match_dup 2)))]
8956 "ix86_match_ccmode (insn, CCNOmode)
8957 && ix86_binary_operator_ok (IOR, SImode, operands)"
8958 "or{l}\t{%2, %0|%0, %2}"
8959 [(set_attr "type" "alu")
8960 (set_attr "mode" "SI")])
8962 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
8963 ;; ??? Special case for immediate operand is missing - it is tricky.
8964 (define_insn "*iorsi_2_zext"
8966 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8967 (match_operand:SI 2 "general_operand" "rim"))
8969 (set (match_operand:DI 0 "register_operand" "=r")
8970 (zero_extend:DI (ior:SI (match_dup 1) (match_dup 2))))]
8971 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8972 && ix86_binary_operator_ok (IOR, SImode, operands)"
8973 "or{l}\t{%2, %k0|%k0, %2}"
8974 [(set_attr "type" "alu")
8975 (set_attr "mode" "SI")])
8977 (define_insn "*iorsi_2_zext_imm"
8979 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8980 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
8982 (set (match_operand:DI 0 "register_operand" "=r")
8983 (ior:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
8984 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
8985 && ix86_binary_operator_ok (IOR, SImode, operands)"
8986 "or{l}\t{%2, %k0|%k0, %2}"
8987 [(set_attr "type" "alu")
8988 (set_attr "mode" "SI")])
8990 (define_insn "*iorsi_3"
8992 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
8993 (match_operand:SI 2 "general_operand" "rim"))
8995 (clobber (match_scratch:SI 0 "=r"))]
8996 "ix86_match_ccmode (insn, CCNOmode)
8997 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
8998 "or{l}\t{%2, %0|%0, %2}"
8999 [(set_attr "type" "alu")
9000 (set_attr "mode" "SI")])
9002 (define_expand "iorhi3"
9003 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9004 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
9005 (match_operand:HI 2 "general_operand" "")))
9006 (clobber (reg:CC 17))]
9007 "TARGET_HIMODE_MATH"
9008 "ix86_expand_binary_operator (IOR, HImode, operands); DONE;")
9010 (define_insn "*iorhi_1"
9011 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9012 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9013 (match_operand:HI 2 "general_operand" "rmi,ri")))
9014 (clobber (reg:CC 17))]
9015 "ix86_binary_operator_ok (IOR, HImode, operands)"
9016 "or{w}\t{%2, %0|%0, %2}"
9017 [(set_attr "type" "alu")
9018 (set_attr "mode" "HI")])
9020 (define_insn "*iorhi_2"
9022 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9023 (match_operand:HI 2 "general_operand" "rim,ri"))
9025 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9026 (ior:HI (match_dup 1) (match_dup 2)))]
9027 "ix86_match_ccmode (insn, CCNOmode)
9028 && ix86_binary_operator_ok (IOR, HImode, operands)"
9029 "or{w}\t{%2, %0|%0, %2}"
9030 [(set_attr "type" "alu")
9031 (set_attr "mode" "HI")])
9033 (define_insn "*iorhi_3"
9035 (compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9036 (match_operand:HI 2 "general_operand" "rim"))
9038 (clobber (match_scratch:HI 0 "=r"))]
9039 "ix86_match_ccmode (insn, CCNOmode)
9040 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9041 "or{w}\t{%2, %0|%0, %2}"
9042 [(set_attr "type" "alu")
9043 (set_attr "mode" "HI")])
9045 (define_expand "iorqi3"
9046 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9047 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
9048 (match_operand:QI 2 "general_operand" "")))
9049 (clobber (reg:CC 17))]
9050 "TARGET_QIMODE_MATH"
9051 "ix86_expand_binary_operator (IOR, QImode, operands); DONE;")
9053 ;; %%% Potential partial reg stall on alternative 2. What to do?
9054 (define_insn "*iorqi_1"
9055 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9056 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9057 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9058 (clobber (reg:CC 17))]
9059 "ix86_binary_operator_ok (IOR, QImode, operands)"
9061 or{b}\t{%2, %0|%0, %2}
9062 or{b}\t{%2, %0|%0, %2}
9063 or{l}\t{%k2, %k0|%k0, %k2}"
9064 [(set_attr "type" "alu")
9065 (set_attr "mode" "QI,QI,SI")])
9067 (define_insn "*iorqi_1_slp"
9068 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+q,m"))
9069 (ior:QI (match_dup 0)
9070 (match_operand:QI 1 "general_operand" "qmi,qi")))
9071 (clobber (reg:CC 17))]
9072 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9073 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9074 "or{b}\t{%1, %0|%0, %1}"
9075 [(set_attr "type" "alu1")
9076 (set_attr "mode" "QI")])
9078 (define_insn "*iorqi_2"
9080 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9081 (match_operand:QI 2 "general_operand" "qim,qi"))
9083 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9084 (ior:QI (match_dup 1) (match_dup 2)))]
9085 "ix86_match_ccmode (insn, CCNOmode)
9086 && ix86_binary_operator_ok (IOR, QImode, operands)"
9087 "or{b}\t{%2, %0|%0, %2}"
9088 [(set_attr "type" "alu")
9089 (set_attr "mode" "QI")])
9091 (define_insn "*iorqi_2_slp"
9093 (compare (ior:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9094 (match_operand:QI 1 "general_operand" "qim,qi"))
9096 (set (strict_low_part (match_dup 0))
9097 (ior:QI (match_dup 0) (match_dup 1)))]
9098 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9099 && ix86_match_ccmode (insn, CCNOmode)
9100 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9101 "or{b}\t{%1, %0|%0, %1}"
9102 [(set_attr "type" "alu1")
9103 (set_attr "mode" "QI")])
9105 (define_insn "*iorqi_3"
9107 (compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9108 (match_operand:QI 2 "general_operand" "qim"))
9110 (clobber (match_scratch:QI 0 "=q"))]
9111 "ix86_match_ccmode (insn, CCNOmode)
9112 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9113 "or{b}\t{%2, %0|%0, %2}"
9114 [(set_attr "type" "alu")
9115 (set_attr "mode" "QI")])
9117 (define_insn "iorqi_ext_0"
9118 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9123 (match_operand 1 "ext_register_operand" "0")
9126 (match_operand 2 "const_int_operand" "n")))
9127 (clobber (reg:CC 17))]
9128 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9129 "or{b}\t{%2, %h0|%h0, %2}"
9130 [(set_attr "type" "alu")
9131 (set_attr "length_immediate" "1")
9132 (set_attr "mode" "QI")])
9134 (define_insn "*iorqi_ext_1"
9135 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9140 (match_operand 1 "ext_register_operand" "0")
9144 (match_operand:QI 2 "general_operand" "Qm"))))
9145 (clobber (reg:CC 17))]
9147 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9148 "or{b}\t{%2, %h0|%h0, %2}"
9149 [(set_attr "type" "alu")
9150 (set_attr "length_immediate" "0")
9151 (set_attr "mode" "QI")])
9153 (define_insn "*iorqi_ext_1_rex64"
9154 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9159 (match_operand 1 "ext_register_operand" "0")
9163 (match_operand 2 "ext_register_operand" "Q"))))
9164 (clobber (reg:CC 17))]
9166 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9167 "or{b}\t{%2, %h0|%h0, %2}"
9168 [(set_attr "type" "alu")
9169 (set_attr "length_immediate" "0")
9170 (set_attr "mode" "QI")])
9172 (define_insn "*iorqi_ext_2"
9173 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9177 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9180 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9183 (clobber (reg:CC 17))]
9184 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9185 "ior{b}\t{%h2, %h0|%h0, %h2}"
9186 [(set_attr "type" "alu")
9187 (set_attr "length_immediate" "0")
9188 (set_attr "mode" "QI")])
9191 [(set (match_operand 0 "register_operand" "")
9192 (ior (match_operand 1 "register_operand" "")
9193 (match_operand 2 "const_int_operand" "")))
9194 (clobber (reg:CC 17))]
9196 && QI_REG_P (operands[0])
9197 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9198 && !(INTVAL (operands[2]) & ~(255 << 8))
9199 && GET_MODE (operands[0]) != QImode"
9200 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9201 (ior:SI (zero_extract:SI (match_dup 1)
9202 (const_int 8) (const_int 8))
9204 (clobber (reg:CC 17))])]
9205 "operands[0] = gen_lowpart (SImode, operands[0]);
9206 operands[1] = gen_lowpart (SImode, operands[1]);
9207 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9209 ;; Since OR can be encoded with sign extended immediate, this is only
9210 ;; profitable when 7th bit is set.
9212 [(set (match_operand 0 "register_operand" "")
9213 (ior (match_operand 1 "general_operand" "")
9214 (match_operand 2 "const_int_operand" "")))
9215 (clobber (reg:CC 17))]
9217 && ANY_QI_REG_P (operands[0])
9218 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9219 && !(INTVAL (operands[2]) & ~255)
9220 && (INTVAL (operands[2]) & 128)
9221 && GET_MODE (operands[0]) != QImode"
9222 [(parallel [(set (strict_low_part (match_dup 0))
9223 (ior:QI (match_dup 1)
9225 (clobber (reg:CC 17))])]
9226 "operands[0] = gen_lowpart (QImode, operands[0]);
9227 operands[1] = gen_lowpart (QImode, operands[1]);
9228 operands[2] = gen_lowpart (QImode, operands[2]);")
9230 ;; Logical XOR instructions
9232 ;; %%% This used to optimize known byte-wide and operations to memory.
9233 ;; If this is considered useful, it should be done with splitters.
9235 (define_expand "xordi3"
9236 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9237 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
9238 (match_operand:DI 2 "x86_64_general_operand" "")))
9239 (clobber (reg:CC 17))]
9241 "ix86_expand_binary_operator (XOR, DImode, operands); DONE;")
9243 (define_insn "*xordi_1_rex64"
9244 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
9245 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9246 (match_operand:DI 2 "x86_64_general_operand" "re,rm")))
9247 (clobber (reg:CC 17))]
9249 && ix86_binary_operator_ok (XOR, DImode, operands)"
9251 xor{q}\t{%2, %0|%0, %2}
9252 xor{q}\t{%2, %0|%0, %2}"
9253 [(set_attr "type" "alu")
9254 (set_attr "mode" "DI,DI")])
9256 (define_insn "*xordi_2_rex64"
9258 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
9259 (match_operand:DI 2 "x86_64_general_operand" "rem,re"))
9261 (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
9262 (xor:DI (match_dup 1) (match_dup 2)))]
9264 && ix86_match_ccmode (insn, CCNOmode)
9265 && ix86_binary_operator_ok (XOR, DImode, operands)"
9267 xor{q}\t{%2, %0|%0, %2}
9268 xor{q}\t{%2, %0|%0, %2}"
9269 [(set_attr "type" "alu")
9270 (set_attr "mode" "DI,DI")])
9272 (define_insn "*xordi_3_rex64"
9274 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
9275 (match_operand:DI 2 "x86_64_general_operand" "rem"))
9277 (clobber (match_scratch:DI 0 "=r"))]
9279 && ix86_match_ccmode (insn, CCNOmode)
9280 && ix86_binary_operator_ok (XOR, DImode, operands)"
9281 "xor{q}\t{%2, %0|%0, %2}"
9282 [(set_attr "type" "alu")
9283 (set_attr "mode" "DI")])
9285 (define_expand "xorsi3"
9286 [(set (match_operand:SI 0 "nonimmediate_operand" "")
9287 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
9288 (match_operand:SI 2 "general_operand" "")))
9289 (clobber (reg:CC 17))]
9291 "ix86_expand_binary_operator (XOR, SImode, operands); DONE;")
9293 (define_insn "*xorsi_1"
9294 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
9295 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9296 (match_operand:SI 2 "general_operand" "ri,rm")))
9297 (clobber (reg:CC 17))]
9298 "ix86_binary_operator_ok (XOR, SImode, operands)"
9299 "xor{l}\t{%2, %0|%0, %2}"
9300 [(set_attr "type" "alu")
9301 (set_attr "mode" "SI")])
9303 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9304 ;; Add speccase for immediates
9305 (define_insn "*xorsi_1_zext"
9306 [(set (match_operand:DI 0 "register_operand" "=r")
9308 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9309 (match_operand:SI 2 "general_operand" "rim"))))
9310 (clobber (reg:CC 17))]
9311 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9312 "xor{l}\t{%2, %k0|%k0, %2}"
9313 [(set_attr "type" "alu")
9314 (set_attr "mode" "SI")])
9316 (define_insn "*xorsi_1_zext_imm"
9317 [(set (match_operand:DI 0 "register_operand" "=r")
9318 (xor:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
9319 (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z")))
9320 (clobber (reg:CC 17))]
9321 "TARGET_64BIT && ix86_binary_operator_ok (XOR, SImode, operands)"
9322 "xor{l}\t{%2, %k0|%k0, %2}"
9323 [(set_attr "type" "alu")
9324 (set_attr "mode" "SI")])
9326 (define_insn "*xorsi_2"
9328 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
9329 (match_operand:SI 2 "general_operand" "rim,ri"))
9331 (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
9332 (xor:SI (match_dup 1) (match_dup 2)))]
9333 "ix86_match_ccmode (insn, CCNOmode)
9334 && ix86_binary_operator_ok (XOR, SImode, operands)"
9335 "xor{l}\t{%2, %0|%0, %2}"
9336 [(set_attr "type" "alu")
9337 (set_attr "mode" "SI")])
9339 ;; See comment for addsi_1_zext why we do use nonimmediate_operand
9340 ;; ??? Special case for immediate operand is missing - it is tricky.
9341 (define_insn "*xorsi_2_zext"
9343 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9344 (match_operand:SI 2 "general_operand" "rim"))
9346 (set (match_operand:DI 0 "register_operand" "=r")
9347 (zero_extend:DI (xor:SI (match_dup 1) (match_dup 2))))]
9348 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9349 && ix86_binary_operator_ok (XOR, SImode, operands)"
9350 "xor{l}\t{%2, %k0|%k0, %2}"
9351 [(set_attr "type" "alu")
9352 (set_attr "mode" "SI")])
9354 (define_insn "*xorsi_2_zext_imm"
9356 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9357 (match_operand 2 "x86_64_zext_immediate_operand" "Z"))
9359 (set (match_operand:DI 0 "register_operand" "=r")
9360 (xor:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
9361 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
9362 && ix86_binary_operator_ok (XOR, SImode, operands)"
9363 "xor{l}\t{%2, %k0|%k0, %2}"
9364 [(set_attr "type" "alu")
9365 (set_attr "mode" "SI")])
9367 (define_insn "*xorsi_3"
9369 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
9370 (match_operand:SI 2 "general_operand" "rim"))
9372 (clobber (match_scratch:SI 0 "=r"))]
9373 "ix86_match_ccmode (insn, CCNOmode)
9374 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9375 "xor{l}\t{%2, %0|%0, %2}"
9376 [(set_attr "type" "alu")
9377 (set_attr "mode" "SI")])
9379 (define_expand "xorhi3"
9380 [(set (match_operand:HI 0 "nonimmediate_operand" "")
9381 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
9382 (match_operand:HI 2 "general_operand" "")))
9383 (clobber (reg:CC 17))]
9384 "TARGET_HIMODE_MATH"
9385 "ix86_expand_binary_operator (XOR, HImode, operands); DONE;")
9387 (define_insn "*xorhi_1"
9388 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,m")
9389 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9390 (match_operand:HI 2 "general_operand" "rmi,ri")))
9391 (clobber (reg:CC 17))]
9392 "ix86_binary_operator_ok (XOR, HImode, operands)"
9393 "xor{w}\t{%2, %0|%0, %2}"
9394 [(set_attr "type" "alu")
9395 (set_attr "mode" "HI")])
9397 (define_insn "*xorhi_2"
9399 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
9400 (match_operand:HI 2 "general_operand" "rim,ri"))
9402 (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
9403 (xor:HI (match_dup 1) (match_dup 2)))]
9404 "ix86_match_ccmode (insn, CCNOmode)
9405 && ix86_binary_operator_ok (XOR, HImode, operands)"
9406 "xor{w}\t{%2, %0|%0, %2}"
9407 [(set_attr "type" "alu")
9408 (set_attr "mode" "HI")])
9410 (define_insn "*xorhi_3"
9412 (compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
9413 (match_operand:HI 2 "general_operand" "rim"))
9415 (clobber (match_scratch:HI 0 "=r"))]
9416 "ix86_match_ccmode (insn, CCNOmode)
9417 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9418 "xor{w}\t{%2, %0|%0, %2}"
9419 [(set_attr "type" "alu")
9420 (set_attr "mode" "HI")])
9422 (define_expand "xorqi3"
9423 [(set (match_operand:QI 0 "nonimmediate_operand" "")
9424 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
9425 (match_operand:QI 2 "general_operand" "")))
9426 (clobber (reg:CC 17))]
9427 "TARGET_QIMODE_MATH"
9428 "ix86_expand_binary_operator (XOR, QImode, operands); DONE;")
9430 ;; %%% Potential partial reg stall on alternative 2. What to do?
9431 (define_insn "*xorqi_1"
9432 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,m,r")
9433 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
9434 (match_operand:QI 2 "general_operand" "qmi,qi,ri")))
9435 (clobber (reg:CC 17))]
9436 "ix86_binary_operator_ok (XOR, QImode, operands)"
9438 xor{b}\t{%2, %0|%0, %2}
9439 xor{b}\t{%2, %0|%0, %2}
9440 xor{l}\t{%k2, %k0|%k0, %k2}"
9441 [(set_attr "type" "alu")
9442 (set_attr "mode" "QI,QI,SI")])
9444 (define_insn "*xorqi_1_slp"
9445 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
9446 (xor:QI (match_dup 0)
9447 (match_operand:QI 1 "general_operand" "qi,qmi")))
9448 (clobber (reg:CC 17))]
9449 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9450 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9451 "xor{b}\t{%1, %0|%0, %1}"
9452 [(set_attr "type" "alu1")
9453 (set_attr "mode" "QI")])
9455 (define_insn "xorqi_ext_0"
9456 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9461 (match_operand 1 "ext_register_operand" "0")
9464 (match_operand 2 "const_int_operand" "n")))
9465 (clobber (reg:CC 17))]
9466 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9467 "xor{b}\t{%2, %h0|%h0, %2}"
9468 [(set_attr "type" "alu")
9469 (set_attr "length_immediate" "1")
9470 (set_attr "mode" "QI")])
9472 (define_insn "*xorqi_ext_1"
9473 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9478 (match_operand 1 "ext_register_operand" "0")
9482 (match_operand:QI 2 "general_operand" "Qm"))))
9483 (clobber (reg:CC 17))]
9485 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9486 "xor{b}\t{%2, %h0|%h0, %2}"
9487 [(set_attr "type" "alu")
9488 (set_attr "length_immediate" "0")
9489 (set_attr "mode" "QI")])
9491 (define_insn "*xorqi_ext_1_rex64"
9492 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9497 (match_operand 1 "ext_register_operand" "0")
9501 (match_operand 2 "ext_register_operand" "Q"))))
9502 (clobber (reg:CC 17))]
9504 && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
9505 "xor{b}\t{%2, %h0|%h0, %2}"
9506 [(set_attr "type" "alu")
9507 (set_attr "length_immediate" "0")
9508 (set_attr "mode" "QI")])
9510 (define_insn "*xorqi_ext_2"
9511 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9515 (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
9518 (zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
9521 (clobber (reg:CC 17))]
9522 "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
9523 "xor{b}\t{%h2, %h0|%h0, %h2}"
9524 [(set_attr "type" "alu")
9525 (set_attr "length_immediate" "0")
9526 (set_attr "mode" "QI")])
9528 (define_insn "*xorqi_cc_1"
9531 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
9532 (match_operand:QI 2 "general_operand" "qim,qi"))
9534 (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
9535 (xor:QI (match_dup 1) (match_dup 2)))]
9536 "ix86_match_ccmode (insn, CCNOmode)
9537 && ix86_binary_operator_ok (XOR, QImode, operands)"
9538 "xor{b}\t{%2, %0|%0, %2}"
9539 [(set_attr "type" "alu")
9540 (set_attr "mode" "QI")])
9542 (define_insn "*xorqi_2_slp"
9544 (compare (xor:QI (match_operand:QI 0 "nonimmediate_operand" "+q,qm")
9545 (match_operand:QI 1 "general_operand" "qim,qi"))
9547 (set (strict_low_part (match_dup 0))
9548 (xor:QI (match_dup 0) (match_dup 1)))]
9549 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
9550 && ix86_match_ccmode (insn, CCNOmode)
9551 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
9552 "xor{b}\t{%1, %0|%0, %1}"
9553 [(set_attr "type" "alu1")
9554 (set_attr "mode" "QI")])
9556 (define_insn "*xorqi_cc_2"
9559 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
9560 (match_operand:QI 2 "general_operand" "qim"))
9562 (clobber (match_scratch:QI 0 "=q"))]
9563 "ix86_match_ccmode (insn, CCNOmode)
9564 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
9565 "xor{b}\t{%2, %0|%0, %2}"
9566 [(set_attr "type" "alu")
9567 (set_attr "mode" "QI")])
9569 (define_insn "*xorqi_cc_ext_1"
9574 (match_operand 1 "ext_register_operand" "0")
9577 (match_operand:QI 2 "general_operand" "qmn"))
9579 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
9583 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9585 "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9586 "xor{b}\t{%2, %h0|%h0, %2}"
9587 [(set_attr "type" "alu")
9588 (set_attr "mode" "QI")])
9590 (define_insn "*xorqi_cc_ext_1_rex64"
9595 (match_operand 1 "ext_register_operand" "0")
9598 (match_operand:QI 2 "nonmemory_operand" "Qn"))
9600 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
9604 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9606 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
9607 "xor{b}\t{%2, %h0|%h0, %2}"
9608 [(set_attr "type" "alu")
9609 (set_attr "mode" "QI")])
9611 (define_expand "xorqi_cc_ext_1"
9617 (match_operand 1 "ext_register_operand" "")
9620 (match_operand:QI 2 "general_operand" ""))
9622 (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
9626 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
9632 [(set (match_operand 0 "register_operand" "")
9633 (xor (match_operand 1 "register_operand" "")
9634 (match_operand 2 "const_int_operand" "")))
9635 (clobber (reg:CC 17))]
9637 && QI_REG_P (operands[0])
9638 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9639 && !(INTVAL (operands[2]) & ~(255 << 8))
9640 && GET_MODE (operands[0]) != QImode"
9641 [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
9642 (xor:SI (zero_extract:SI (match_dup 1)
9643 (const_int 8) (const_int 8))
9645 (clobber (reg:CC 17))])]
9646 "operands[0] = gen_lowpart (SImode, operands[0]);
9647 operands[1] = gen_lowpart (SImode, operands[1]);
9648 operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);")
9650 ;; Since XOR can be encoded with sign extended immediate, this is only
9651 ;; profitable when 7th bit is set.
9653 [(set (match_operand 0 "register_operand" "")
9654 (xor (match_operand 1 "general_operand" "")
9655 (match_operand 2 "const_int_operand" "")))
9656 (clobber (reg:CC 17))]
9658 && ANY_QI_REG_P (operands[0])
9659 && (!TARGET_PARTIAL_REG_STALL || optimize_size)
9660 && !(INTVAL (operands[2]) & ~255)
9661 && (INTVAL (operands[2]) & 128)
9662 && GET_MODE (operands[0]) != QImode"
9663 [(parallel [(set (strict_low_part (match_dup 0))
9664 (xor:QI (match_dup 1)
9666 (clobber (reg:CC 17))])]
9667 "operands[0] = gen_lowpart (QImode, operands[0]);
9668 operands[1] = gen_lowpart (QImode, operands[1]);
9669 operands[2] = gen_lowpart (QImode, operands[2]);")
9671 ;; Negation instructions
9673 (define_expand "negdi2"
9674 [(parallel [(set (match_operand:DI 0 "nonimmediate_operand" "")
9675 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "")))
9676 (clobber (reg:CC 17))])]
9678 "ix86_expand_unary_operator (NEG, DImode, operands); DONE;")
9680 (define_insn "*negdi2_1"
9681 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
9682 (neg:DI (match_operand:DI 1 "general_operand" "0")))
9683 (clobber (reg:CC 17))]
9685 && ix86_unary_operator_ok (NEG, DImode, operands)"
9689 [(set (match_operand:DI 0 "nonimmediate_operand" "")
9690 (neg:DI (match_operand:DI 1 "general_operand" "")))
9691 (clobber (reg:CC 17))]
9692 "!TARGET_64BIT && reload_completed"
9695 (compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
9696 (set (match_dup 0) (neg:SI (match_dup 2)))])
9699 (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
9702 (clobber (reg:CC 17))])
9705 (neg:SI (match_dup 1)))
9706 (clobber (reg:CC 17))])]
9707 "split_di (operands+1, 1, operands+2, operands+3);
9708 split_di (operands+0, 1, operands+0, operands+1);")
9710 (define_insn "*negdi2_1_rex64"
9711 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9712 (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0")))
9713 (clobber (reg:CC 17))]
9714 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9716 [(set_attr "type" "negnot")
9717 (set_attr "mode" "DI")])
9719 ;; The problem with neg is that it does not perform (compare x 0),
9720 ;; it really performs (compare 0 x), which leaves us with the zero
9721 ;; flag being the only useful item.
9723 (define_insn "*negdi2_cmpz_rex64"
9725 (compare:CCZ (neg:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
9727 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
9728 (neg:DI (match_dup 1)))]
9729 "TARGET_64BIT && ix86_unary_operator_ok (NEG, DImode, operands)"
9731 [(set_attr "type" "negnot")
9732 (set_attr "mode" "DI")])
9735 (define_expand "negsi2"
9736 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
9737 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "")))
9738 (clobber (reg:CC 17))])]
9740 "ix86_expand_unary_operator (NEG, SImode, operands); DONE;")
9742 (define_insn "*negsi2_1"
9743 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9744 (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0")))
9745 (clobber (reg:CC 17))]
9746 "ix86_unary_operator_ok (NEG, SImode, operands)"
9748 [(set_attr "type" "negnot")
9749 (set_attr "mode" "SI")])
9751 ;; Combine is quite creative about this pattern.
9752 (define_insn "*negsi2_1_zext"
9753 [(set (match_operand:DI 0 "register_operand" "=r")
9754 (lshiftrt:DI (neg:DI (ashift:DI (match_operand:DI 1 "register_operand" "0")
9757 (clobber (reg:CC 17))]
9758 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9760 [(set_attr "type" "negnot")
9761 (set_attr "mode" "SI")])
9763 ;; The problem with neg is that it does not perform (compare x 0),
9764 ;; it really performs (compare 0 x), which leaves us with the zero
9765 ;; flag being the only useful item.
9767 (define_insn "*negsi2_cmpz"
9769 (compare:CCZ (neg:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
9771 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
9772 (neg:SI (match_dup 1)))]
9773 "ix86_unary_operator_ok (NEG, SImode, operands)"
9775 [(set_attr "type" "negnot")
9776 (set_attr "mode" "SI")])
9778 (define_insn "*negsi2_cmpz_zext"
9780 (compare:CCZ (lshiftrt:DI
9782 (match_operand:DI 1 "register_operand" "0")
9786 (set (match_operand:DI 0 "register_operand" "=r")
9787 (lshiftrt:DI (neg:DI (ashift:DI (match_dup 1)
9790 "TARGET_64BIT && ix86_unary_operator_ok (NEG, SImode, operands)"
9792 [(set_attr "type" "negnot")
9793 (set_attr "mode" "SI")])
9795 (define_expand "neghi2"
9796 [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
9797 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "")))
9798 (clobber (reg:CC 17))])]
9799 "TARGET_HIMODE_MATH"
9800 "ix86_expand_unary_operator (NEG, HImode, operands); DONE;")
9802 (define_insn "*neghi2_1"
9803 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9804 (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0")))
9805 (clobber (reg:CC 17))]
9806 "ix86_unary_operator_ok (NEG, HImode, operands)"
9808 [(set_attr "type" "negnot")
9809 (set_attr "mode" "HI")])
9811 (define_insn "*neghi2_cmpz"
9813 (compare:CCZ (neg:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
9815 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
9816 (neg:HI (match_dup 1)))]
9817 "ix86_unary_operator_ok (NEG, HImode, operands)"
9819 [(set_attr "type" "negnot")
9820 (set_attr "mode" "HI")])
9822 (define_expand "negqi2"
9823 [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
9824 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "")))
9825 (clobber (reg:CC 17))])]
9826 "TARGET_QIMODE_MATH"
9827 "ix86_expand_unary_operator (NEG, QImode, operands); DONE;")
9829 (define_insn "*negqi2_1"
9830 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9831 (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0")))
9832 (clobber (reg:CC 17))]
9833 "ix86_unary_operator_ok (NEG, QImode, operands)"
9835 [(set_attr "type" "negnot")
9836 (set_attr "mode" "QI")])
9838 (define_insn "*negqi2_cmpz"
9840 (compare:CCZ (neg:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
9842 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
9843 (neg:QI (match_dup 1)))]
9844 "ix86_unary_operator_ok (NEG, QImode, operands)"
9846 [(set_attr "type" "negnot")
9847 (set_attr "mode" "QI")])
9849 ;; Changing of sign for FP values is doable using integer unit too.
9851 (define_expand "negsf2"
9852 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
9853 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
9854 (clobber (reg:CC 17))])]
9858 /* In case operand is in memory, we will not use SSE. */
9859 if (memory_operand (operands[0], VOIDmode)
9860 && rtx_equal_p (operands[0], operands[1]))
9861 emit_insn (gen_negsf2_memory (operands[0], operands[1]));
9864 /* Using SSE is tricky, since we need bitwise negation of -0
9866 rtx reg = gen_reg_rtx (SFmode);
9867 rtx dest = operands[0];
9868 rtx imm = gen_lowpart (SFmode, gen_int_mode (0x80000000, SImode));
9870 operands[1] = force_reg (SFmode, operands[1]);
9871 operands[0] = force_reg (SFmode, operands[0]);
9872 reg = force_reg (V4SFmode,
9873 gen_rtx_CONST_VECTOR (V4SFmode,
9874 gen_rtvec (4, imm, CONST0_RTX (SFmode),
9875 CONST0_RTX (SFmode),
9876 CONST0_RTX (SFmode))));
9877 emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
9878 if (dest != operands[0])
9879 emit_move_insn (dest, operands[0]);
9883 ix86_expand_unary_operator (NEG, SFmode, operands); DONE;")
9885 (define_insn "negsf2_memory"
9886 [(set (match_operand:SF 0 "memory_operand" "=m")
9887 (neg:SF (match_operand:SF 1 "memory_operand" "0")))
9888 (clobber (reg:CC 17))]
9889 "ix86_unary_operator_ok (NEG, SFmode, operands)"
9892 (define_insn "negsf2_ifs"
9893 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
9894 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
9895 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
9896 (clobber (reg:CC 17))]
9898 && (reload_in_progress || reload_completed
9899 || (register_operand (operands[0], VOIDmode)
9900 && register_operand (operands[1], VOIDmode)))"
9904 [(set (match_operand:SF 0 "memory_operand" "")
9905 (neg:SF (match_operand:SF 1 "memory_operand" "")))
9906 (use (match_operand:SF 2 "" ""))
9907 (clobber (reg:CC 17))]
9909 [(parallel [(set (match_dup 0)
9910 (neg:SF (match_dup 1)))
9911 (clobber (reg:CC 17))])])
9914 [(set (match_operand:SF 0 "register_operand" "")
9915 (neg:SF (match_operand:SF 1 "register_operand" "")))
9916 (use (match_operand:V4SF 2 "" ""))
9917 (clobber (reg:CC 17))]
9918 "reload_completed && !SSE_REG_P (operands[0])"
9919 [(parallel [(set (match_dup 0)
9920 (neg:SF (match_dup 1)))
9921 (clobber (reg:CC 17))])])
9924 [(set (match_operand:SF 0 "register_operand" "")
9925 (neg:SF (match_operand:SF 1 "register_operand" "")))
9926 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
9927 (clobber (reg:CC 17))]
9928 "reload_completed && SSE_REG_P (operands[0])"
9929 [(set (subreg:TI (match_dup 0) 0)
9930 (xor:TI (match_dup 1)
9933 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
9934 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
9935 if (operands_match_p (operands[0], operands[2]))
9939 operands[1] = operands[2];
9945 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
9946 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
9948 (define_insn "*negsf2_if"
9949 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
9950 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
9951 (clobber (reg:CC 17))]
9952 "TARGET_80387 && !TARGET_SSE
9953 && ix86_unary_operator_ok (NEG, SFmode, operands)"
9957 [(set (match_operand:SF 0 "fp_register_operand" "")
9958 (neg:SF (match_operand:SF 1 "register_operand" "")))
9959 (clobber (reg:CC 17))]
9960 "TARGET_80387 && reload_completed"
9962 (neg:SF (match_dup 1)))]
9966 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
9967 (neg:SF (match_operand:SF 1 "register_operand" "")))
9968 (clobber (reg:CC 17))]
9969 "TARGET_80387 && reload_completed"
9970 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
9971 (clobber (reg:CC 17))])]
9972 "operands[1] = gen_int_mode (0x80000000, SImode);
9973 operands[0] = gen_lowpart (SImode, operands[0]);")
9976 [(set (match_operand 0 "memory_operand" "")
9977 (neg (match_operand 1 "memory_operand" "")))
9978 (clobber (reg:CC 17))]
9979 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
9980 [(parallel [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
9981 (clobber (reg:CC 17))])]
9983 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
9985 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
9988 operands[0] = adjust_address (operands[0], QImode, size - 1);
9989 operands[1] = gen_int_mode (0x80, QImode);
9992 (define_expand "negdf2"
9993 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
9994 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
9995 (clobber (reg:CC 17))])]
9999 /* In case operand is in memory, we will not use SSE. */
10000 if (memory_operand (operands[0], VOIDmode)
10001 && rtx_equal_p (operands[0], operands[1]))
10002 emit_insn (gen_negdf2_memory (operands[0], operands[1]));
10005 /* Using SSE is tricky, since we need bitwise negation of -0
10008 #if HOST_BITS_PER_WIDE_INT >= 64
10009 rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
10011 rtx imm = immed_double_const (0, 0x80000000, DImode);
10013 rtx dest = operands[0];
10015 operands[1] = force_reg (DFmode, operands[1]);
10016 operands[0] = force_reg (DFmode, operands[0]);
10017 imm = gen_lowpart (DFmode, imm);
10018 reg = force_reg (V2DFmode,
10019 gen_rtx_CONST_VECTOR (V2DFmode,
10020 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10021 emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
10022 if (dest != operands[0])
10023 emit_move_insn (dest, operands[0]);
10027 ix86_expand_unary_operator (NEG, DFmode, operands); DONE;")
10029 (define_insn "negdf2_memory"
10030 [(set (match_operand:DF 0 "memory_operand" "=m")
10031 (neg:DF (match_operand:DF 1 "memory_operand" "0")))
10032 (clobber (reg:CC 17))]
10033 "ix86_unary_operator_ok (NEG, DFmode, operands)"
10036 (define_insn "negdf2_ifs"
10037 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,f#Yr,rm#Yf")
10038 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10039 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10040 (clobber (reg:CC 17))]
10041 "!TARGET_64BIT && TARGET_SSE2
10042 && (reload_in_progress || reload_completed
10043 || (register_operand (operands[0], VOIDmode)
10044 && register_operand (operands[1], VOIDmode)))"
10047 (define_insn "*negdf2_ifs_rex64"
10048 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#f,Y#f,fm#Y")
10049 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10050 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10051 (clobber (reg:CC 17))]
10052 "TARGET_64BIT && TARGET_SSE2
10053 && (reload_in_progress || reload_completed
10054 || (register_operand (operands[0], VOIDmode)
10055 && register_operand (operands[1], VOIDmode)))"
10059 [(set (match_operand:DF 0 "memory_operand" "")
10060 (neg:DF (match_operand:DF 1 "memory_operand" "")))
10061 (use (match_operand:V2DF 2 "" ""))
10062 (clobber (reg:CC 17))]
10064 [(parallel [(set (match_dup 0)
10065 (neg:DF (match_dup 1)))
10066 (clobber (reg:CC 17))])])
10069 [(set (match_operand:DF 0 "register_operand" "")
10070 (neg:DF (match_operand:DF 1 "register_operand" "")))
10071 (use (match_operand:V2DF 2 "" ""))
10072 (clobber (reg:CC 17))]
10073 "reload_completed && !SSE_REG_P (operands[0])
10074 && (!TARGET_64BIT || FP_REG_P (operands[0]))"
10075 [(parallel [(set (match_dup 0)
10076 (neg:DF (match_dup 1)))
10077 (clobber (reg:CC 17))])])
10080 [(set (match_operand:DF 0 "register_operand" "")
10081 (neg:DF (match_operand:DF 1 "register_operand" "")))
10082 (use (match_operand:V2DF 2 "" ""))
10083 (clobber (reg:CC 17))]
10084 "TARGET_64BIT && reload_completed && GENERAL_REG_P (operands[0])"
10085 [(parallel [(set (match_dup 0)
10086 (xor:DI (match_dup 1) (match_dup 2)))
10087 (clobber (reg:CC 17))])]
10088 "operands[0] = gen_lowpart (DImode, operands[0]);
10089 operands[1] = gen_lowpart (DImode, operands[1]);
10090 operands[2] = gen_lowpart (DImode, operands[2]);")
10093 [(set (match_operand:DF 0 "register_operand" "")
10094 (neg:DF (match_operand:DF 1 "register_operand" "")))
10095 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10096 (clobber (reg:CC 17))]
10097 "reload_completed && SSE_REG_P (operands[0])"
10098 [(set (subreg:TI (match_dup 0) 0)
10099 (xor:TI (match_dup 1)
10102 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10103 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10104 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10105 /* Avoid possible reformatting on the operands. */
10106 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10107 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10108 if (operands_match_p (operands[0], operands[2]))
10112 operands[1] = operands[2];
10117 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10118 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10120 (define_insn "*negdf2_if"
10121 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10122 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10123 (clobber (reg:CC 17))]
10124 "!TARGET_64BIT && TARGET_80387
10125 && ix86_unary_operator_ok (NEG, DFmode, operands)"
10128 ;; FIXME: We should to allow integer registers here. Problem is that
10129 ;; we need another scratch register to get constant from.
10130 ;; Forcing constant to mem if no register available in peep2 should be
10131 ;; safe even for PIC mode, because of RIP relative addressing.
10132 (define_insn "*negdf2_if_rex64"
10133 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10134 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10135 (clobber (reg:CC 17))]
10136 "TARGET_64BIT && TARGET_80387
10137 && ix86_unary_operator_ok (NEG, DFmode, operands)"
10141 [(set (match_operand:DF 0 "fp_register_operand" "")
10142 (neg:DF (match_operand:DF 1 "register_operand" "")))
10143 (clobber (reg:CC 17))]
10144 "TARGET_80387 && reload_completed"
10145 [(set (match_dup 0)
10146 (neg:DF (match_dup 1)))]
10150 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10151 (neg:DF (match_operand:DF 1 "register_operand" "")))
10152 (clobber (reg:CC 17))]
10153 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10154 [(parallel [(set (match_dup 3) (xor:SI (match_dup 3) (match_dup 4)))
10155 (clobber (reg:CC 17))])]
10156 "operands[4] = gen_int_mode (0x80000000, SImode);
10157 split_di (operands+0, 1, operands+2, operands+3);")
10159 (define_expand "negxf2"
10160 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10161 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10162 (clobber (reg:CC 17))])]
10163 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
10164 "ix86_expand_unary_operator (NEG, XFmode, operands); DONE;")
10166 (define_expand "negtf2"
10167 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10168 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10169 (clobber (reg:CC 17))])]
10171 "ix86_expand_unary_operator (NEG, TFmode, operands); DONE;")
10173 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10174 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10176 (define_insn "*negxf2_if"
10177 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10178 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10179 (clobber (reg:CC 17))]
10180 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
10181 && ix86_unary_operator_ok (NEG, XFmode, operands)"
10185 [(set (match_operand:XF 0 "fp_register_operand" "")
10186 (neg:XF (match_operand:XF 1 "register_operand" "")))
10187 (clobber (reg:CC 17))]
10188 "TARGET_80387 && reload_completed"
10189 [(set (match_dup 0)
10190 (neg:XF (match_dup 1)))]
10194 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10195 (neg:XF (match_operand:XF 1 "register_operand" "")))
10196 (clobber (reg:CC 17))]
10197 "TARGET_80387 && reload_completed"
10198 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
10199 (clobber (reg:CC 17))])]
10200 "operands[1] = GEN_INT (0x8000);
10201 operands[0] = gen_rtx_REG (SImode,
10202 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10204 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10205 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10207 (define_insn "*negtf2_if"
10208 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10209 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10210 (clobber (reg:CC 17))]
10211 "TARGET_80387 && ix86_unary_operator_ok (NEG, TFmode, operands)"
10215 [(set (match_operand:TF 0 "fp_register_operand" "")
10216 (neg:TF (match_operand:TF 1 "register_operand" "")))
10217 (clobber (reg:CC 17))]
10218 "TARGET_80387 && reload_completed"
10219 [(set (match_dup 0)
10220 (neg:TF (match_dup 1)))]
10224 [(set (match_operand:TF 0 "register_and_not_fp_reg_operand" "")
10225 (neg:TF (match_operand:TF 1 "register_operand" "")))
10226 (clobber (reg:CC 17))]
10227 "TARGET_80387 && reload_completed"
10228 [(parallel [(set (match_dup 0) (xor:SI (match_dup 0) (match_dup 1)))
10229 (clobber (reg:CC 17))])]
10230 "operands[1] = GEN_INT (0x8000);
10231 operands[0] = gen_rtx_REG (SImode,
10232 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10234 ;; Conditionalize these after reload. If they matches before reload, we
10235 ;; lose the clobber and ability to use integer instructions.
10237 (define_insn "*negsf2_1"
10238 [(set (match_operand:SF 0 "register_operand" "=f")
10239 (neg:SF (match_operand:SF 1 "register_operand" "0")))]
10240 "TARGET_80387 && reload_completed"
10242 [(set_attr "type" "fsgn")
10243 (set_attr "mode" "SF")
10244 (set_attr "ppro_uops" "few")])
10246 (define_insn "*negdf2_1"
10247 [(set (match_operand:DF 0 "register_operand" "=f")
10248 (neg:DF (match_operand:DF 1 "register_operand" "0")))]
10249 "TARGET_80387 && reload_completed"
10251 [(set_attr "type" "fsgn")
10252 (set_attr "mode" "DF")
10253 (set_attr "ppro_uops" "few")])
10255 (define_insn "*negextendsfdf2"
10256 [(set (match_operand:DF 0 "register_operand" "=f")
10257 (neg:DF (float_extend:DF
10258 (match_operand:SF 1 "register_operand" "0"))))]
10261 [(set_attr "type" "fsgn")
10262 (set_attr "mode" "DF")
10263 (set_attr "ppro_uops" "few")])
10265 (define_insn "*negxf2_1"
10266 [(set (match_operand:XF 0 "register_operand" "=f")
10267 (neg:XF (match_operand:XF 1 "register_operand" "0")))]
10268 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && reload_completed"
10270 [(set_attr "type" "fsgn")
10271 (set_attr "mode" "XF")
10272 (set_attr "ppro_uops" "few")])
10274 (define_insn "*negextenddfxf2"
10275 [(set (match_operand:XF 0 "register_operand" "=f")
10276 (neg:XF (float_extend:XF
10277 (match_operand:DF 1 "register_operand" "0"))))]
10278 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
10280 [(set_attr "type" "fsgn")
10281 (set_attr "mode" "XF")
10282 (set_attr "ppro_uops" "few")])
10284 (define_insn "*negextendsfxf2"
10285 [(set (match_operand:XF 0 "register_operand" "=f")
10286 (neg:XF (float_extend:XF
10287 (match_operand:SF 1 "register_operand" "0"))))]
10288 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
10290 [(set_attr "type" "fsgn")
10291 (set_attr "mode" "XF")
10292 (set_attr "ppro_uops" "few")])
10294 (define_insn "*negtf2_1"
10295 [(set (match_operand:TF 0 "register_operand" "=f")
10296 (neg:TF (match_operand:TF 1 "register_operand" "0")))]
10297 "TARGET_80387 && reload_completed"
10299 [(set_attr "type" "fsgn")
10300 (set_attr "mode" "XF")
10301 (set_attr "ppro_uops" "few")])
10303 (define_insn "*negextenddftf2"
10304 [(set (match_operand:TF 0 "register_operand" "=f")
10305 (neg:TF (float_extend:TF
10306 (match_operand:DF 1 "register_operand" "0"))))]
10309 [(set_attr "type" "fsgn")
10310 (set_attr "mode" "XF")
10311 (set_attr "ppro_uops" "few")])
10313 (define_insn "*negextendsftf2"
10314 [(set (match_operand:TF 0 "register_operand" "=f")
10315 (neg:TF (float_extend:TF
10316 (match_operand:SF 1 "register_operand" "0"))))]
10319 [(set_attr "type" "fsgn")
10320 (set_attr "mode" "XF")
10321 (set_attr "ppro_uops" "few")])
10323 ;; Absolute value instructions
10325 (define_expand "abssf2"
10326 [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "")
10327 (neg:SF (match_operand:SF 1 "nonimmediate_operand" "")))
10328 (clobber (reg:CC 17))])]
10332 /* In case operand is in memory, we will not use SSE. */
10333 if (memory_operand (operands[0], VOIDmode)
10334 && rtx_equal_p (operands[0], operands[1]))
10335 emit_insn (gen_abssf2_memory (operands[0], operands[1]));
10338 /* Using SSE is tricky, since we need bitwise negation of -0
10340 rtx reg = gen_reg_rtx (V4SFmode);
10341 rtx dest = operands[0];
10344 operands[1] = force_reg (SFmode, operands[1]);
10345 operands[0] = force_reg (SFmode, operands[0]);
10346 imm = gen_lowpart (SFmode, gen_int_mode(~0x80000000, SImode));
10347 reg = force_reg (V4SFmode,
10348 gen_rtx_CONST_VECTOR (V4SFmode,
10349 gen_rtvec (4, imm, CONST0_RTX (SFmode),
10350 CONST0_RTX (SFmode),
10351 CONST0_RTX (SFmode))));
10352 emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
10353 if (dest != operands[0])
10354 emit_move_insn (dest, operands[0]);
10358 ix86_expand_unary_operator (ABS, SFmode, operands); DONE;")
10360 (define_insn "abssf2_memory"
10361 [(set (match_operand:SF 0 "memory_operand" "=m")
10362 (abs:SF (match_operand:SF 1 "memory_operand" "0")))
10363 (clobber (reg:CC 17))]
10364 "ix86_unary_operator_ok (ABS, SFmode, operands)"
10367 (define_insn "abssf2_ifs"
10368 [(set (match_operand:SF 0 "nonimmediate_operand" "=x#fr,x#fr,f#xr,rm#xf")
10369 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,x#fr,0,0")))
10370 (use (match_operand:V4SF 2 "nonimmediate_operand" "xm,0,xm*r,xm*r"))
10371 (clobber (reg:CC 17))]
10373 && (reload_in_progress || reload_completed
10374 || (register_operand (operands[0], VOIDmode)
10375 && register_operand (operands[1], VOIDmode)))"
10379 [(set (match_operand:SF 0 "memory_operand" "")
10380 (abs:SF (match_operand:SF 1 "memory_operand" "")))
10381 (use (match_operand:V4SF 2 "" ""))
10382 (clobber (reg:CC 17))]
10384 [(parallel [(set (match_dup 0)
10385 (abs:SF (match_dup 1)))
10386 (clobber (reg:CC 17))])])
10389 [(set (match_operand:SF 0 "register_operand" "")
10390 (abs:SF (match_operand:SF 1 "register_operand" "")))
10391 (use (match_operand:V4SF 2 "" ""))
10392 (clobber (reg:CC 17))]
10393 "reload_completed && !SSE_REG_P (operands[0])"
10394 [(parallel [(set (match_dup 0)
10395 (abs:SF (match_dup 1)))
10396 (clobber (reg:CC 17))])])
10399 [(set (match_operand:SF 0 "register_operand" "")
10400 (abs:SF (match_operand:SF 1 "register_operand" "")))
10401 (use (match_operand:V4SF 2 "nonimmediate_operand" ""))
10402 (clobber (reg:CC 17))]
10403 "reload_completed && SSE_REG_P (operands[0])"
10404 [(set (subreg:TI (match_dup 0) 0)
10405 (and:TI (match_dup 1)
10408 operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0);
10409 operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0);
10410 if (operands_match_p (operands[0], operands[2]))
10414 operands[1] = operands[2];
10419 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10420 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10422 (define_insn "*abssf2_if"
10423 [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f")
10424 (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")))
10425 (clobber (reg:CC 17))]
10426 "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE"
10430 [(set (match_operand:SF 0 "fp_register_operand" "")
10431 (abs:SF (match_operand:SF 1 "register_operand" "")))
10432 (clobber (reg:CC 17))]
10433 "TARGET_80387 && reload_completed"
10434 [(set (match_dup 0)
10435 (abs:SF (match_dup 1)))]
10439 [(set (match_operand:SF 0 "register_and_not_fp_reg_operand" "")
10440 (abs:SF (match_operand:SF 1 "register_operand" "")))
10441 (clobber (reg:CC 17))]
10442 "TARGET_80387 && reload_completed"
10443 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10444 (clobber (reg:CC 17))])]
10445 "operands[1] = gen_int_mode (~0x80000000, SImode);
10446 operands[0] = gen_lowpart (SImode, operands[0]);")
10449 [(set (match_operand 0 "memory_operand" "")
10450 (abs (match_operand 1 "memory_operand" "")))
10451 (clobber (reg:CC 17))]
10452 "TARGET_80387 && reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))"
10453 [(parallel [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
10454 (clobber (reg:CC 17))])]
10456 int size = GET_MODE_SIZE (GET_MODE (operands[1]));
10458 /* XFmode's size is 12, TFmode 16, but only 10 bytes are used. */
10461 operands[0] = adjust_address (operands[0], QImode, size - 1);
10462 operands[1] = gen_int_mode (~0x80, QImode);
10465 (define_expand "absdf2"
10466 [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "")
10467 (neg:DF (match_operand:DF 1 "nonimmediate_operand" "")))
10468 (clobber (reg:CC 17))])]
10472 /* In case operand is in memory, we will not use SSE. */
10473 if (memory_operand (operands[0], VOIDmode)
10474 && rtx_equal_p (operands[0], operands[1]))
10475 emit_insn (gen_absdf2_memory (operands[0], operands[1]));
10478 /* Using SSE is tricky, since we need bitwise negation of -0
10480 rtx reg = gen_reg_rtx (V2DFmode);
10481 #if HOST_BITS_PER_WIDE_INT >= 64
10482 rtx imm = gen_int_mode (~(((HOST_WIDE_INT)1) << 63), DImode);
10484 rtx imm = immed_double_const (~0, ~0x80000000, DImode);
10486 rtx dest = operands[0];
10488 operands[1] = force_reg (DFmode, operands[1]);
10489 operands[0] = force_reg (DFmode, operands[0]);
10491 /* Produce LONG_DOUBLE with the proper immediate argument. */
10492 imm = gen_lowpart (DFmode, imm);
10493 reg = force_reg (V2DFmode,
10494 gen_rtx_CONST_VECTOR (V2DFmode,
10495 gen_rtvec (2, imm, CONST0_RTX (DFmode))));
10496 emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
10497 if (dest != operands[0])
10498 emit_move_insn (dest, operands[0]);
10502 ix86_expand_unary_operator (ABS, DFmode, operands); DONE;")
10504 (define_insn "absdf2_memory"
10505 [(set (match_operand:DF 0 "memory_operand" "=m")
10506 (abs:DF (match_operand:DF 1 "memory_operand" "0")))
10507 (clobber (reg:CC 17))]
10508 "ix86_unary_operator_ok (ABS, DFmode, operands)"
10511 (define_insn "absdf2_ifs"
10512 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr,mr#Yf")
10513 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0,0")))
10514 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r,Ym*r"))
10515 (clobber (reg:CC 17))]
10516 "!TARGET_64BIT && TARGET_SSE2
10517 && (reload_in_progress || reload_completed
10518 || (register_operand (operands[0], VOIDmode)
10519 && register_operand (operands[1], VOIDmode)))"
10522 (define_insn "*absdf2_ifs_rex64"
10523 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y#fr,Y#fr,mf#Yr")
10524 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,Y#fr,0")))
10525 (use (match_operand:V2DF 2 "nonimmediate_operand" "Ym,0,Ym*r"))
10526 (clobber (reg:CC 17))]
10527 "TARGET_64BIT && TARGET_SSE2
10528 && (reload_in_progress || reload_completed
10529 || (register_operand (operands[0], VOIDmode)
10530 && register_operand (operands[1], VOIDmode)))"
10534 [(set (match_operand:DF 0 "memory_operand" "")
10535 (abs:DF (match_operand:DF 1 "memory_operand" "")))
10536 (use (match_operand:V2DF 2 "" ""))
10537 (clobber (reg:CC 17))]
10539 [(parallel [(set (match_dup 0)
10540 (abs:DF (match_dup 1)))
10541 (clobber (reg:CC 17))])])
10544 [(set (match_operand:DF 0 "register_operand" "")
10545 (abs:DF (match_operand:DF 1 "register_operand" "")))
10546 (use (match_operand:V2DF 2 "" ""))
10547 (clobber (reg:CC 17))]
10548 "reload_completed && !SSE_REG_P (operands[0])"
10549 [(parallel [(set (match_dup 0)
10550 (abs:DF (match_dup 1)))
10551 (clobber (reg:CC 17))])])
10554 [(set (match_operand:DF 0 "register_operand" "")
10555 (abs:DF (match_operand:DF 1 "register_operand" "")))
10556 (use (match_operand:V2DF 2 "nonimmediate_operand" ""))
10557 (clobber (reg:CC 17))]
10558 "reload_completed && SSE_REG_P (operands[0])"
10559 [(set (subreg:TI (match_dup 0) 0)
10560 (and:TI (match_dup 1)
10563 operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0);
10564 operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0);
10565 operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0);
10566 /* Avoid possible reformatting on the operands. */
10567 if (TARGET_SSE_PARTIAL_REGS && !optimize_size)
10568 emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0]));
10569 if (operands_match_p (operands[0], operands[2]))
10573 operands[1] = operands[2];
10579 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10580 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10582 (define_insn "*absdf2_if"
10583 [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,rm#f")
10584 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10585 (clobber (reg:CC 17))]
10586 "!TARGET_64BIT && TARGET_80387
10587 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10590 ;; FIXME: We should to allow integer registers here. Problem is that
10591 ;; we need another scratch register to get constant from.
10592 ;; Forcing constant to mem if no register available in peep2 should be
10593 ;; safe even for PIC mode, because of RIP relative addressing.
10594 (define_insn "*absdf2_if_rex64"
10595 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,mf")
10596 (abs:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")))
10597 (clobber (reg:CC 17))]
10598 "TARGET_64BIT && TARGET_80387
10599 && ix86_unary_operator_ok (ABS, DFmode, operands)"
10603 [(set (match_operand:DF 0 "fp_register_operand" "")
10604 (abs:DF (match_operand:DF 1 "register_operand" "")))
10605 (clobber (reg:CC 17))]
10606 "TARGET_80387 && reload_completed"
10607 [(set (match_dup 0)
10608 (abs:DF (match_dup 1)))]
10612 [(set (match_operand:DF 0 "register_and_not_fp_reg_operand" "")
10613 (abs:DF (match_operand:DF 1 "register_operand" "")))
10614 (clobber (reg:CC 17))]
10615 "!TARGET_64BIT && TARGET_80387 && reload_completed"
10616 [(parallel [(set (match_dup 3) (and:SI (match_dup 3) (match_dup 4)))
10617 (clobber (reg:CC 17))])]
10618 "operands[4] = gen_int_mode (~0x80000000, SImode);
10619 split_di (operands+0, 1, operands+2, operands+3);")
10621 (define_expand "absxf2"
10622 [(parallel [(set (match_operand:XF 0 "nonimmediate_operand" "")
10623 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))
10624 (clobber (reg:CC 17))])]
10625 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
10626 "ix86_expand_unary_operator (ABS, XFmode, operands); DONE;")
10628 (define_expand "abstf2"
10629 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
10630 (neg:TF (match_operand:TF 1 "nonimmediate_operand" "")))
10631 (clobber (reg:CC 17))])]
10633 "ix86_expand_unary_operator (ABS, TFmode, operands); DONE;")
10635 ;; Keep 'f' and 'r' in separate alternatives to avoid reload problems
10636 ;; because of secondary memory needed to reload from class FLOAT_INT_REGS
10638 (define_insn "*absxf2_if"
10639 [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,rm#f")
10640 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "0,0")))
10641 (clobber (reg:CC 17))]
10642 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
10643 && ix86_unary_operator_ok (ABS, XFmode, operands)"
10647 [(set (match_operand:XF 0 "fp_register_operand" "")
10648 (abs:XF (match_operand:XF 1 "register_operand" "")))
10649 (clobber (reg:CC 17))]
10650 "TARGET_80387 && reload_completed"
10651 [(set (match_dup 0)
10652 (abs:XF (match_dup 1)))]
10656 [(set (match_operand:XF 0 "register_and_not_fp_reg_operand" "")
10657 (abs:XF (match_operand:XF 1 "register_operand" "")))
10658 (clobber (reg:CC 17))]
10659 "TARGET_80387 && reload_completed"
10660 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10661 (clobber (reg:CC 17))])]
10662 "operands[1] = GEN_INT (~0x8000);
10663 operands[0] = gen_rtx_REG (SImode,
10664 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10666 (define_insn "*abstf2_if"
10667 [(set (match_operand:TF 0 "nonimmediate_operand" "=f#r,rm#f")
10668 (abs:TF (match_operand:TF 1 "nonimmediate_operand" "0,0")))
10669 (clobber (reg:CC 17))]
10670 "TARGET_80387 && ix86_unary_operator_ok (ABS, TFmode, operands)"
10674 [(set (match_operand:TF 0 "fp_register_operand" "")
10675 (abs:TF (match_operand:TF 1 "register_operand" "")))
10676 (clobber (reg:CC 17))]
10677 "TARGET_80387 && reload_completed"
10678 [(set (match_dup 0)
10679 (abs:TF (match_dup 1)))]
10683 [(set (match_operand:TF 0 "register_and_not_any_fp_reg_operand" "")
10684 (abs:TF (match_operand:TF 1 "register_operand" "")))
10685 (clobber (reg:CC 17))]
10686 "TARGET_80387 && reload_completed"
10687 [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (match_dup 1)))
10688 (clobber (reg:CC 17))])]
10689 "operands[1] = GEN_INT (~0x8000);
10690 operands[0] = gen_rtx_REG (SImode,
10691 true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));")
10693 (define_insn "*abssf2_1"
10694 [(set (match_operand:SF 0 "register_operand" "=f")
10695 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
10696 "TARGET_80387 && reload_completed"
10698 [(set_attr "type" "fsgn")
10699 (set_attr "mode" "SF")])
10701 (define_insn "*absdf2_1"
10702 [(set (match_operand:DF 0 "register_operand" "=f")
10703 (abs:DF (match_operand:DF 1 "register_operand" "0")))]
10704 "TARGET_80387 && reload_completed"
10706 [(set_attr "type" "fsgn")
10707 (set_attr "mode" "DF")])
10709 (define_insn "*absextendsfdf2"
10710 [(set (match_operand:DF 0 "register_operand" "=f")
10711 (abs:DF (float_extend:DF
10712 (match_operand:SF 1 "register_operand" "0"))))]
10715 [(set_attr "type" "fsgn")
10716 (set_attr "mode" "DF")])
10718 (define_insn "*absxf2_1"
10719 [(set (match_operand:XF 0 "register_operand" "=f")
10720 (abs:XF (match_operand:XF 1 "register_operand" "0")))]
10721 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && reload_completed"
10723 [(set_attr "type" "fsgn")
10724 (set_attr "mode" "DF")])
10726 (define_insn "*absextenddfxf2"
10727 [(set (match_operand:XF 0 "register_operand" "=f")
10728 (abs:XF (float_extend:XF
10729 (match_operand:DF 1 "register_operand" "0"))))]
10730 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
10732 [(set_attr "type" "fsgn")
10733 (set_attr "mode" "XF")])
10735 (define_insn "*absextendsfxf2"
10736 [(set (match_operand:XF 0 "register_operand" "=f")
10737 (abs:XF (float_extend:XF
10738 (match_operand:SF 1 "register_operand" "0"))))]
10739 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
10741 [(set_attr "type" "fsgn")
10742 (set_attr "mode" "XF")])
10744 (define_insn "*abstf2_1"
10745 [(set (match_operand:TF 0 "register_operand" "=f")
10746 (abs:TF (match_operand:TF 1 "register_operand" "0")))]
10747 "TARGET_80387 && reload_completed"
10749 [(set_attr "type" "fsgn")
10750 (set_attr "mode" "DF")])
10752 (define_insn "*absextenddftf2"
10753 [(set (match_operand:TF 0 "register_operand" "=f")
10754 (abs:TF (float_extend:TF
10755 (match_operand:DF 1 "register_operand" "0"))))]
10758 [(set_attr "type" "fsgn")
10759 (set_attr "mode" "XF")])
10761 (define_insn "*absextendsftf2"
10762 [(set (match_operand:TF 0 "register_operand" "=f")
10763 (abs:TF (float_extend:TF
10764 (match_operand:SF 1 "register_operand" "0"))))]
10767 [(set_attr "type" "fsgn")
10768 (set_attr "mode" "XF")])
10770 ;; One complement instructions
10772 (define_expand "one_cmpldi2"
10773 [(set (match_operand:DI 0 "nonimmediate_operand" "")
10774 (not:DI (match_operand:DI 1 "nonimmediate_operand" "")))]
10776 "ix86_expand_unary_operator (NOT, DImode, operands); DONE;")
10778 (define_insn "*one_cmpldi2_1_rex64"
10779 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10780 (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))]
10781 "TARGET_64BIT && ix86_unary_operator_ok (NOT, DImode, operands)"
10783 [(set_attr "type" "negnot")
10784 (set_attr "mode" "DI")])
10786 (define_insn "*one_cmpldi2_2_rex64"
10788 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "0"))
10790 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
10791 (not:DI (match_dup 1)))]
10792 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10793 && ix86_unary_operator_ok (NOT, DImode, operands)"
10795 [(set_attr "type" "alu1")
10796 (set_attr "mode" "DI")])
10800 (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" ""))
10802 (set (match_operand:DI 0 "nonimmediate_operand" "")
10803 (not:DI (match_dup 1)))]
10804 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
10805 [(parallel [(set (reg:CCNO 17)
10806 (compare:CCNO (xor:DI (match_dup 1) (const_int -1))
10809 (xor:DI (match_dup 1) (const_int -1)))])]
10812 (define_expand "one_cmplsi2"
10813 [(set (match_operand:SI 0 "nonimmediate_operand" "")
10814 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
10816 "ix86_expand_unary_operator (NOT, SImode, operands); DONE;")
10818 (define_insn "*one_cmplsi2_1"
10819 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10820 (not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
10821 "ix86_unary_operator_ok (NOT, SImode, operands)"
10823 [(set_attr "type" "negnot")
10824 (set_attr "mode" "SI")])
10826 ;; ??? Currently never generated - xor is used instead.
10827 (define_insn "*one_cmplsi2_1_zext"
10828 [(set (match_operand:DI 0 "register_operand" "=r")
10829 (zero_extend:DI (not:SI (match_operand:SI 1 "register_operand" "0"))))]
10830 "TARGET_64BIT && ix86_unary_operator_ok (NOT, SImode, operands)"
10832 [(set_attr "type" "negnot")
10833 (set_attr "mode" "SI")])
10835 (define_insn "*one_cmplsi2_2"
10837 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "0"))
10839 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
10840 (not:SI (match_dup 1)))]
10841 "ix86_match_ccmode (insn, CCNOmode)
10842 && ix86_unary_operator_ok (NOT, SImode, operands)"
10844 [(set_attr "type" "alu1")
10845 (set_attr "mode" "SI")])
10849 (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" ""))
10851 (set (match_operand:SI 0 "nonimmediate_operand" "")
10852 (not:SI (match_dup 1)))]
10853 "ix86_match_ccmode (insn, CCNOmode)"
10854 [(parallel [(set (reg:CCNO 17)
10855 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10858 (xor:SI (match_dup 1) (const_int -1)))])]
10861 ;; ??? Currently never generated - xor is used instead.
10862 (define_insn "*one_cmplsi2_2_zext"
10864 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
10866 (set (match_operand:DI 0 "register_operand" "=r")
10867 (zero_extend:DI (not:SI (match_dup 1))))]
10868 "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)
10869 && ix86_unary_operator_ok (NOT, SImode, operands)"
10871 [(set_attr "type" "alu1")
10872 (set_attr "mode" "SI")])
10876 (compare (not:SI (match_operand:SI 1 "register_operand" ""))
10878 (set (match_operand:DI 0 "register_operand" "")
10879 (zero_extend:DI (not:SI (match_dup 1))))]
10880 "ix86_match_ccmode (insn, CCNOmode)"
10881 [(parallel [(set (reg:CCNO 17)
10882 (compare:CCNO (xor:SI (match_dup 1) (const_int -1))
10885 (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])]
10888 (define_expand "one_cmplhi2"
10889 [(set (match_operand:HI 0 "nonimmediate_operand" "")
10890 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
10891 "TARGET_HIMODE_MATH"
10892 "ix86_expand_unary_operator (NOT, HImode, operands); DONE;")
10894 (define_insn "*one_cmplhi2_1"
10895 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10896 (not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
10897 "ix86_unary_operator_ok (NOT, HImode, operands)"
10899 [(set_attr "type" "negnot")
10900 (set_attr "mode" "HI")])
10902 (define_insn "*one_cmplhi2_2"
10904 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "0"))
10906 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
10907 (not:HI (match_dup 1)))]
10908 "ix86_match_ccmode (insn, CCNOmode)
10909 && ix86_unary_operator_ok (NEG, HImode, operands)"
10911 [(set_attr "type" "alu1")
10912 (set_attr "mode" "HI")])
10916 (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" ""))
10918 (set (match_operand:HI 0 "nonimmediate_operand" "")
10919 (not:HI (match_dup 1)))]
10920 "ix86_match_ccmode (insn, CCNOmode)"
10921 [(parallel [(set (reg:CCNO 17)
10922 (compare:CCNO (xor:HI (match_dup 1) (const_int -1))
10925 (xor:HI (match_dup 1) (const_int -1)))])]
10928 ;; %%% Potential partial reg stall on alternative 1. What to do?
10929 (define_expand "one_cmplqi2"
10930 [(set (match_operand:QI 0 "nonimmediate_operand" "")
10931 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
10932 "TARGET_QIMODE_MATH"
10933 "ix86_expand_unary_operator (NOT, QImode, operands); DONE;")
10935 (define_insn "*one_cmplqi2_1"
10936 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
10937 (not:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
10938 "ix86_unary_operator_ok (NOT, QImode, operands)"
10942 [(set_attr "type" "negnot")
10943 (set_attr "mode" "QI,SI")])
10945 (define_insn "*one_cmplqi2_2"
10947 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "0"))
10949 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
10950 (not:QI (match_dup 1)))]
10951 "ix86_match_ccmode (insn, CCNOmode)
10952 && ix86_unary_operator_ok (NOT, QImode, operands)"
10954 [(set_attr "type" "alu1")
10955 (set_attr "mode" "QI")])
10959 (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" ""))
10961 (set (match_operand:QI 0 "nonimmediate_operand" "")
10962 (not:QI (match_dup 1)))]
10963 "ix86_match_ccmode (insn, CCNOmode)"
10964 [(parallel [(set (reg:CCNO 17)
10965 (compare:CCNO (xor:QI (match_dup 1) (const_int -1))
10968 (xor:QI (match_dup 1) (const_int -1)))])]
10971 ;; Arithmetic shift instructions
10973 ;; DImode shifts are implemented using the i386 "shift double" opcode,
10974 ;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count
10975 ;; is variable, then the count is in %cl and the "imm" operand is dropped
10976 ;; from the assembler input.
10978 ;; This instruction shifts the target reg/mem as usual, but instead of
10979 ;; shifting in zeros, bits are shifted in from reg operand. If the insn
10980 ;; is a left shift double, bits are taken from the high order bits of
10981 ;; reg, else if the insn is a shift right double, bits are taken from the
10982 ;; low order bits of reg. So if %eax is "1234" and %edx is "5678",
10983 ;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345".
10985 ;; Since sh[lr]d does not change the `reg' operand, that is done
10986 ;; separately, making all shifts emit pairs of shift double and normal
10987 ;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to
10988 ;; support a 63 bit shift, each shift where the count is in a reg expands
10989 ;; to a pair of shifts, a branch, a shift by 32 and a label.
10991 ;; If the shift count is a constant, we need never emit more than one
10992 ;; shift pair, instead using moves and sign extension for counts greater
10995 (define_expand "ashldi3"
10996 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
10997 (ashift:DI (match_operand:DI 1 "shiftdi_operand" "")
10998 (match_operand:QI 2 "nonmemory_operand" "")))
10999 (clobber (reg:CC 17))])]
11002 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11004 emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
11007 ix86_expand_binary_operator (ASHIFT, DImode, operands);
11011 (define_insn "*ashldi3_1_rex64"
11012 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r")
11013 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0,r")
11014 (match_operand:QI 2 "nonmemory_operand" "cJ,M")))
11015 (clobber (reg:CC 17))]
11016 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
11018 switch (get_attr_type (insn))
11021 if (operands[2] != const1_rtx)
11023 if (!rtx_equal_p (operands[0], operands[1]))
11025 return "add{q}\t{%0, %0|%0, %0}";
11028 if (GET_CODE (operands[2]) != CONST_INT
11029 || (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 3)
11031 operands[1] = gen_rtx_MULT (DImode, operands[1],
11032 GEN_INT (1 << INTVAL (operands[2])));
11033 return "lea{q}\t{%a1, %0|%0, %a1}";
11036 if (REG_P (operands[2]))
11037 return "sal{q}\t{%b2, %0|%0, %b2}";
11038 else if (GET_CODE (operands[2]) == CONST_INT
11039 && INTVAL (operands[2]) == 1
11040 && (TARGET_SHIFT1 || optimize_size))
11041 return "sal{q}\t%0";
11043 return "sal{q}\t{%2, %0|%0, %2}";
11046 [(set (attr "type")
11047 (cond [(eq_attr "alternative" "1")
11048 (const_string "lea")
11049 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11051 (match_operand 0 "register_operand" ""))
11052 (match_operand 2 "const1_operand" ""))
11053 (const_string "alu")
11055 (const_string "ishift")))
11056 (set_attr "mode" "DI")])
11058 ;; Convert lea to the lea pattern to avoid flags dependency.
11060 [(set (match_operand:DI 0 "register_operand" "")
11061 (ashift:DI (match_operand:DI 1 "register_operand" "")
11062 (match_operand:QI 2 "immediate_operand" "")))
11063 (clobber (reg:CC 17))]
11064 "TARGET_64BIT && reload_completed
11065 && true_regnum (operands[0]) != true_regnum (operands[1])"
11066 [(set (match_dup 0)
11067 (mult:DI (match_dup 1)
11069 "operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);")
11071 ;; This pattern can't accept a variable shift count, since shifts by
11072 ;; zero don't affect the flags. We assume that shifts by constant
11073 ;; zero are optimized away.
11074 (define_insn "*ashldi3_cmp_rex64"
11077 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11078 (match_operand:QI 2 "immediate_operand" "e"))
11080 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11081 (ashift:DI (match_dup 1) (match_dup 2)))]
11082 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11083 && ix86_binary_operator_ok (ASHIFT, DImode, operands)"
11085 switch (get_attr_type (insn))
11088 if (operands[2] != const1_rtx)
11090 return "add{q}\t{%0, %0|%0, %0}";
11093 if (REG_P (operands[2]))
11094 return "sal{q}\t{%b2, %0|%0, %b2}";
11095 else if (GET_CODE (operands[2]) == CONST_INT
11096 && INTVAL (operands[2]) == 1
11097 && (TARGET_SHIFT1 || optimize_size))
11098 return "sal{q}\t%0";
11100 return "sal{q}\t{%2, %0|%0, %2}";
11103 [(set (attr "type")
11104 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11106 (match_operand 0 "register_operand" ""))
11107 (match_operand 2 "const1_operand" ""))
11108 (const_string "alu")
11110 (const_string "ishift")))
11111 (set_attr "mode" "DI")])
11113 (define_insn "ashldi3_1"
11114 [(set (match_operand:DI 0 "register_operand" "=r")
11115 (ashift:DI (match_operand:DI 1 "register_operand" "0")
11116 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11117 (clobber (match_scratch:SI 3 "=&r"))
11118 (clobber (reg:CC 17))]
11119 "!TARGET_64BIT && TARGET_CMOVE"
11121 [(set_attr "type" "multi")])
11123 (define_insn "*ashldi3_2"
11124 [(set (match_operand:DI 0 "register_operand" "=r")
11125 (ashift:DI (match_operand:DI 1 "register_operand" "0")
11126 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11127 (clobber (reg:CC 17))]
11130 [(set_attr "type" "multi")])
11133 [(set (match_operand:DI 0 "register_operand" "")
11134 (ashift:DI (match_operand:DI 1 "register_operand" "")
11135 (match_operand:QI 2 "nonmemory_operand" "")))
11136 (clobber (match_scratch:SI 3 ""))
11137 (clobber (reg:CC 17))]
11138 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11140 "ix86_split_ashldi (operands, operands[3]); DONE;")
11143 [(set (match_operand:DI 0 "register_operand" "")
11144 (ashift:DI (match_operand:DI 1 "register_operand" "")
11145 (match_operand:QI 2 "nonmemory_operand" "")))
11146 (clobber (reg:CC 17))]
11147 "!TARGET_64BIT && reload_completed"
11149 "ix86_split_ashldi (operands, NULL_RTX); DONE;")
11151 (define_insn "x86_shld_1"
11152 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11153 (ior:SI (ashift:SI (match_dup 0)
11154 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11155 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
11156 (minus:QI (const_int 32) (match_dup 2)))))
11157 (clobber (reg:CC 17))]
11160 shld{l}\t{%2, %1, %0|%0, %1, %2}
11161 shld{l}\t{%s2%1, %0|%0, %1, %2}"
11162 [(set_attr "type" "ishift")
11163 (set_attr "prefix_0f" "1")
11164 (set_attr "mode" "SI")
11165 (set_attr "pent_pair" "np")
11166 (set_attr "athlon_decode" "vector")
11167 (set_attr "ppro_uops" "few")])
11169 (define_expand "x86_shift_adj_1"
11171 (compare:CCZ (and:QI (match_operand:QI 2 "register_operand" "")
11174 (set (match_operand:SI 0 "register_operand" "")
11175 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
11176 (match_operand:SI 1 "register_operand" "")
11179 (if_then_else:SI (ne (reg:CCZ 17) (const_int 0))
11180 (match_operand:SI 3 "register_operand" "r")
11185 (define_expand "x86_shift_adj_2"
11186 [(use (match_operand:SI 0 "register_operand" ""))
11187 (use (match_operand:SI 1 "register_operand" ""))
11188 (use (match_operand:QI 2 "register_operand" ""))]
11191 rtx label = gen_label_rtx ();
11194 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11196 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11197 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11198 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11199 gen_rtx_LABEL_REF (VOIDmode, label),
11201 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11202 JUMP_LABEL (tmp) = label;
11204 emit_move_insn (operands[0], operands[1]);
11205 emit_move_insn (operands[1], const0_rtx);
11207 emit_label (label);
11208 LABEL_NUSES (label) = 1;
11213 (define_expand "ashlsi3"
11214 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11215 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "")
11216 (match_operand:QI 2 "nonmemory_operand" "")))
11217 (clobber (reg:CC 17))]
11219 "ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;")
11221 (define_insn "*ashlsi3_1"
11222 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
11223 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0,r")
11224 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11225 (clobber (reg:CC 17))]
11226 "ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11228 switch (get_attr_type (insn))
11231 if (operands[2] != const1_rtx)
11233 if (!rtx_equal_p (operands[0], operands[1]))
11235 return "add{l}\t{%0, %0|%0, %0}";
11241 if (REG_P (operands[2]))
11242 return "sal{l}\t{%b2, %0|%0, %b2}";
11243 else if (GET_CODE (operands[2]) == CONST_INT
11244 && INTVAL (operands[2]) == 1
11245 && (TARGET_SHIFT1 || optimize_size))
11246 return "sal{l}\t%0";
11248 return "sal{l}\t{%2, %0|%0, %2}";
11251 [(set (attr "type")
11252 (cond [(eq_attr "alternative" "1")
11253 (const_string "lea")
11254 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11256 (match_operand 0 "register_operand" ""))
11257 (match_operand 2 "const1_operand" ""))
11258 (const_string "alu")
11260 (const_string "ishift")))
11261 (set_attr "mode" "SI")])
11263 ;; Convert lea to the lea pattern to avoid flags dependency.
11265 [(set (match_operand 0 "register_operand" "")
11266 (ashift (match_operand 1 "index_register_operand" "")
11267 (match_operand:QI 2 "const_int_operand" "")))
11268 (clobber (reg:CC 17))]
11270 && true_regnum (operands[0]) != true_regnum (operands[1])"
11274 operands[0] = gen_lowpart (SImode, operands[0]);
11275 operands[1] = gen_lowpart (Pmode, operands[1]);
11276 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11277 pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
11278 if (Pmode != SImode)
11279 pat = gen_rtx_SUBREG (SImode, pat, 0);
11280 emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
11284 ;; Rare case of shifting RSP is handled by generating move and shift
11286 [(set (match_operand 0 "register_operand" "")
11287 (ashift (match_operand 1 "register_operand" "")
11288 (match_operand:QI 2 "const_int_operand" "")))
11289 (clobber (reg:CC 17))]
11291 && true_regnum (operands[0]) != true_regnum (operands[1])"
11295 emit_move_insn (operands[1], operands[0]);
11296 pat = gen_rtx_SET (VOIDmode, operands[0],
11297 gen_rtx_ASHIFT (GET_MODE (operands[0]),
11298 operands[0], operands[2]));
11299 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11300 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
11304 (define_insn "*ashlsi3_1_zext"
11305 [(set (match_operand:DI 0 "register_operand" "=r,r")
11306 (zero_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "0,r")
11307 (match_operand:QI 2 "nonmemory_operand" "cI,M"))))
11308 (clobber (reg:CC 17))]
11309 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11311 switch (get_attr_type (insn))
11314 if (operands[2] != const1_rtx)
11316 return "add{l}\t{%k0, %k0|%k0, %k0}";
11322 if (REG_P (operands[2]))
11323 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11324 else if (GET_CODE (operands[2]) == CONST_INT
11325 && INTVAL (operands[2]) == 1
11326 && (TARGET_SHIFT1 || optimize_size))
11327 return "sal{l}\t%k0";
11329 return "sal{l}\t{%2, %k0|%k0, %2}";
11332 [(set (attr "type")
11333 (cond [(eq_attr "alternative" "1")
11334 (const_string "lea")
11335 (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11337 (match_operand 2 "const1_operand" ""))
11338 (const_string "alu")
11340 (const_string "ishift")))
11341 (set_attr "mode" "SI")])
11343 ;; Convert lea to the lea pattern to avoid flags dependency.
11345 [(set (match_operand:DI 0 "register_operand" "")
11346 (zero_extend:DI (ashift (match_operand 1 "register_operand" "")
11347 (match_operand:QI 2 "const_int_operand" ""))))
11348 (clobber (reg:CC 17))]
11349 "TARGET_64BIT && reload_completed
11350 && true_regnum (operands[0]) != true_regnum (operands[1])"
11351 [(set (match_dup 0) (zero_extend:DI
11352 (subreg:SI (mult:SI (match_dup 1)
11353 (match_dup 2)) 0)))]
11355 operands[1] = gen_lowpart (Pmode, operands[1]);
11356 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
11359 ;; This pattern can't accept a variable shift count, since shifts by
11360 ;; zero don't affect the flags. We assume that shifts by constant
11361 ;; zero are optimized away.
11362 (define_insn "*ashlsi3_cmp"
11365 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11366 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11368 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11369 (ashift:SI (match_dup 1) (match_dup 2)))]
11370 "ix86_match_ccmode (insn, CCGOCmode)
11371 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11373 switch (get_attr_type (insn))
11376 if (operands[2] != const1_rtx)
11378 return "add{l}\t{%0, %0|%0, %0}";
11381 if (REG_P (operands[2]))
11382 return "sal{l}\t{%b2, %0|%0, %b2}";
11383 else if (GET_CODE (operands[2]) == CONST_INT
11384 && INTVAL (operands[2]) == 1
11385 && (TARGET_SHIFT1 || optimize_size))
11386 return "sal{l}\t%0";
11388 return "sal{l}\t{%2, %0|%0, %2}";
11391 [(set (attr "type")
11392 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11394 (match_operand 0 "register_operand" ""))
11395 (match_operand 2 "const1_operand" ""))
11396 (const_string "alu")
11398 (const_string "ishift")))
11399 (set_attr "mode" "SI")])
11401 (define_insn "*ashlsi3_cmp_zext"
11404 (ashift:SI (match_operand:SI 1 "register_operand" "0")
11405 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11407 (set (match_operand:DI 0 "register_operand" "=r")
11408 (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
11409 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11410 && ix86_binary_operator_ok (ASHIFT, SImode, operands)"
11412 switch (get_attr_type (insn))
11415 if (operands[2] != const1_rtx)
11417 return "add{l}\t{%k0, %k0|%k0, %k0}";
11420 if (REG_P (operands[2]))
11421 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11422 else if (GET_CODE (operands[2]) == CONST_INT
11423 && INTVAL (operands[2]) == 1
11424 && (TARGET_SHIFT1 || optimize_size))
11425 return "sal{l}\t%k0";
11427 return "sal{l}\t{%2, %k0|%k0, %2}";
11430 [(set (attr "type")
11431 (cond [(and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11433 (match_operand 2 "const1_operand" ""))
11434 (const_string "alu")
11436 (const_string "ishift")))
11437 (set_attr "mode" "SI")])
11439 (define_expand "ashlhi3"
11440 [(set (match_operand:HI 0 "nonimmediate_operand" "")
11441 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "")
11442 (match_operand:QI 2 "nonmemory_operand" "")))
11443 (clobber (reg:CC 17))]
11444 "TARGET_HIMODE_MATH"
11445 "ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;")
11447 (define_insn "*ashlhi3_1_lea"
11448 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
11449 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0,r")
11450 (match_operand:QI 2 "nonmemory_operand" "cI,M")))
11451 (clobber (reg:CC 17))]
11452 "!TARGET_PARTIAL_REG_STALL
11453 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11455 switch (get_attr_type (insn))
11460 if (operands[2] != const1_rtx)
11462 return "add{w}\t{%0, %0|%0, %0}";
11465 if (REG_P (operands[2]))
11466 return "sal{w}\t{%b2, %0|%0, %b2}";
11467 else if (GET_CODE (operands[2]) == CONST_INT
11468 && INTVAL (operands[2]) == 1
11469 && (TARGET_SHIFT1 || optimize_size))
11470 return "sal{w}\t%0";
11472 return "sal{w}\t{%2, %0|%0, %2}";
11475 [(set (attr "type")
11476 (cond [(eq_attr "alternative" "1")
11477 (const_string "lea")
11478 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11480 (match_operand 0 "register_operand" ""))
11481 (match_operand 2 "const1_operand" ""))
11482 (const_string "alu")
11484 (const_string "ishift")))
11485 (set_attr "mode" "HI,SI")])
11487 (define_insn "*ashlhi3_1"
11488 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11489 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11490 (match_operand:QI 2 "nonmemory_operand" "cI")))
11491 (clobber (reg:CC 17))]
11492 "TARGET_PARTIAL_REG_STALL
11493 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11495 switch (get_attr_type (insn))
11498 if (operands[2] != const1_rtx)
11500 return "add{w}\t{%0, %0|%0, %0}";
11503 if (REG_P (operands[2]))
11504 return "sal{w}\t{%b2, %0|%0, %b2}";
11505 else if (GET_CODE (operands[2]) == CONST_INT
11506 && INTVAL (operands[2]) == 1
11507 && (TARGET_SHIFT1 || optimize_size))
11508 return "sal{w}\t%0";
11510 return "sal{w}\t{%2, %0|%0, %2}";
11513 [(set (attr "type")
11514 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11516 (match_operand 0 "register_operand" ""))
11517 (match_operand 2 "const1_operand" ""))
11518 (const_string "alu")
11520 (const_string "ishift")))
11521 (set_attr "mode" "HI")])
11523 ;; This pattern can't accept a variable shift count, since shifts by
11524 ;; zero don't affect the flags. We assume that shifts by constant
11525 ;; zero are optimized away.
11526 (define_insn "*ashlhi3_cmp"
11529 (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
11530 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11532 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
11533 (ashift:HI (match_dup 1) (match_dup 2)))]
11534 "ix86_match_ccmode (insn, CCGOCmode)
11535 && ix86_binary_operator_ok (ASHIFT, HImode, operands)"
11537 switch (get_attr_type (insn))
11540 if (operands[2] != const1_rtx)
11542 return "add{w}\t{%0, %0|%0, %0}";
11545 if (REG_P (operands[2]))
11546 return "sal{w}\t{%b2, %0|%0, %b2}";
11547 else if (GET_CODE (operands[2]) == CONST_INT
11548 && INTVAL (operands[2]) == 1
11549 && (TARGET_SHIFT1 || optimize_size))
11550 return "sal{w}\t%0";
11552 return "sal{w}\t{%2, %0|%0, %2}";
11555 [(set (attr "type")
11556 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11558 (match_operand 0 "register_operand" ""))
11559 (match_operand 2 "const1_operand" ""))
11560 (const_string "alu")
11562 (const_string "ishift")))
11563 (set_attr "mode" "HI")])
11565 (define_expand "ashlqi3"
11566 [(set (match_operand:QI 0 "nonimmediate_operand" "")
11567 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "")
11568 (match_operand:QI 2 "nonmemory_operand" "")))
11569 (clobber (reg:CC 17))]
11570 "TARGET_QIMODE_MATH"
11571 "ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;")
11573 ;; %%% Potential partial reg stall on alternative 2. What to do?
11575 (define_insn "*ashlqi3_1_lea"
11576 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r,r")
11577 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0,r")
11578 (match_operand:QI 2 "nonmemory_operand" "cI,cI,M")))
11579 (clobber (reg:CC 17))]
11580 "!TARGET_PARTIAL_REG_STALL
11581 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11583 switch (get_attr_type (insn))
11588 if (operands[2] != const1_rtx)
11590 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11591 return "add{l}\t{%k0, %k0|%k0, %k0}";
11593 return "add{b}\t{%0, %0|%0, %0}";
11596 if (REG_P (operands[2]))
11598 if (get_attr_mode (insn) == MODE_SI)
11599 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11601 return "sal{b}\t{%b2, %0|%0, %b2}";
11603 else if (GET_CODE (operands[2]) == CONST_INT
11604 && INTVAL (operands[2]) == 1
11605 && (TARGET_SHIFT1 || optimize_size))
11607 if (get_attr_mode (insn) == MODE_SI)
11608 return "sal{l}\t%0";
11610 return "sal{b}\t%0";
11614 if (get_attr_mode (insn) == MODE_SI)
11615 return "sal{l}\t{%2, %k0|%k0, %2}";
11617 return "sal{b}\t{%2, %0|%0, %2}";
11621 [(set (attr "type")
11622 (cond [(eq_attr "alternative" "2")
11623 (const_string "lea")
11624 (and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11626 (match_operand 0 "register_operand" ""))
11627 (match_operand 2 "const1_operand" ""))
11628 (const_string "alu")
11630 (const_string "ishift")))
11631 (set_attr "mode" "QI,SI,SI")])
11633 (define_insn "*ashlqi3_1"
11634 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,r")
11635 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
11636 (match_operand:QI 2 "nonmemory_operand" "cI,cI")))
11637 (clobber (reg:CC 17))]
11638 "TARGET_PARTIAL_REG_STALL
11639 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11641 switch (get_attr_type (insn))
11644 if (operands[2] != const1_rtx)
11646 if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
11647 return "add{l}\t{%k0, %k0|%k0, %k0}";
11649 return "add{b}\t{%0, %0|%0, %0}";
11652 if (REG_P (operands[2]))
11654 if (get_attr_mode (insn) == MODE_SI)
11655 return "sal{l}\t{%b2, %k0|%k0, %b2}";
11657 return "sal{b}\t{%b2, %0|%0, %b2}";
11659 else if (GET_CODE (operands[2]) == CONST_INT
11660 && INTVAL (operands[2]) == 1
11661 && (TARGET_SHIFT1 || optimize_size))
11663 if (get_attr_mode (insn) == MODE_SI)
11664 return "sal{l}\t%0";
11666 return "sal{b}\t%0";
11670 if (get_attr_mode (insn) == MODE_SI)
11671 return "sal{l}\t{%2, %k0|%k0, %2}";
11673 return "sal{b}\t{%2, %0|%0, %2}";
11677 [(set (attr "type")
11678 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11680 (match_operand 0 "register_operand" ""))
11681 (match_operand 2 "const1_operand" ""))
11682 (const_string "alu")
11684 (const_string "ishift")))
11685 (set_attr "mode" "QI,SI")])
11687 ;; This pattern can't accept a variable shift count, since shifts by
11688 ;; zero don't affect the flags. We assume that shifts by constant
11689 ;; zero are optimized away.
11690 (define_insn "*ashlqi3_cmp"
11693 (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
11694 (match_operand:QI 2 "const_int_1_31_operand" "I"))
11696 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
11697 (ashift:QI (match_dup 1) (match_dup 2)))]
11698 "ix86_match_ccmode (insn, CCGOCmode)
11699 && ix86_binary_operator_ok (ASHIFT, QImode, operands)"
11701 switch (get_attr_type (insn))
11704 if (operands[2] != const1_rtx)
11706 return "add{b}\t{%0, %0|%0, %0}";
11709 if (REG_P (operands[2]))
11710 return "sal{b}\t{%b2, %0|%0, %b2}";
11711 else if (GET_CODE (operands[2]) == CONST_INT
11712 && INTVAL (operands[2]) == 1
11713 && (TARGET_SHIFT1 || optimize_size))
11714 return "sal{b}\t%0";
11716 return "sal{b}\t{%2, %0|%0, %2}";
11719 [(set (attr "type")
11720 (cond [(and (and (ne (symbol_ref "TARGET_DOUBLE_WITH_ADD")
11722 (match_operand 0 "register_operand" ""))
11723 (match_operand 2 "const1_operand" ""))
11724 (const_string "alu")
11726 (const_string "ishift")))
11727 (set_attr "mode" "QI")])
11729 ;; See comment above `ashldi3' about how this works.
11731 (define_expand "ashrdi3"
11732 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
11733 (ashiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
11734 (match_operand:QI 2 "nonmemory_operand" "")))
11735 (clobber (reg:CC 17))])]
11738 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
11740 emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
11743 ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
11747 (define_insn "ashrdi3_63_rex64"
11748 [(set (match_operand:DI 0 "nonimmediate_operand" "=*d,rm")
11749 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "*a,0")
11750 (match_operand:DI 2 "const_int_operand" "i,i")))
11751 (clobber (reg:CC 17))]
11752 "TARGET_64BIT && INTVAL (operands[2]) == 63 && (TARGET_USE_CLTD || optimize_size)
11753 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11756 sar{q}\t{%2, %0|%0, %2}"
11757 [(set_attr "type" "imovx,ishift")
11758 (set_attr "prefix_0f" "0,*")
11759 (set_attr "length_immediate" "0,*")
11760 (set_attr "modrm" "0,1")
11761 (set_attr "mode" "DI")])
11763 (define_insn "*ashrdi3_1_one_bit_rex64"
11764 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11765 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11766 (match_operand:QI 2 "const_int_1_operand" "")))
11767 (clobber (reg:CC 17))]
11768 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)
11769 && (TARGET_SHIFT1 || optimize_size)"
11771 [(set_attr "type" "ishift")
11772 (set (attr "length")
11773 (if_then_else (match_operand:DI 0 "register_operand" "")
11775 (const_string "*")))])
11777 (define_insn "*ashrdi3_1_rex64"
11778 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
11779 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
11780 (match_operand:QI 2 "nonmemory_operand" "J,c")))
11781 (clobber (reg:CC 17))]
11782 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11784 sar{q}\t{%2, %0|%0, %2}
11785 sar{q}\t{%b2, %0|%0, %b2}"
11786 [(set_attr "type" "ishift")
11787 (set_attr "mode" "DI")])
11789 ;; This pattern can't accept a variable shift count, since shifts by
11790 ;; zero don't affect the flags. We assume that shifts by constant
11791 ;; zero are optimized away.
11792 (define_insn "*ashrdi3_one_bit_cmp_rex64"
11795 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11796 (match_operand:QI 2 "const_int_1_operand" ""))
11798 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11799 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11800 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11801 && (TARGET_SHIFT1 || optimize_size)
11802 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11804 [(set_attr "type" "ishift")
11805 (set (attr "length")
11806 (if_then_else (match_operand:DI 0 "register_operand" "")
11808 (const_string "*")))])
11810 ;; This pattern can't accept a variable shift count, since shifts by
11811 ;; zero don't affect the flags. We assume that shifts by constant
11812 ;; zero are optimized away.
11813 (define_insn "*ashrdi3_cmp_rex64"
11816 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
11817 (match_operand:QI 2 "const_int_operand" "n"))
11819 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
11820 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
11821 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
11822 && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
11823 "sar{q}\t{%2, %0|%0, %2}"
11824 [(set_attr "type" "ishift")
11825 (set_attr "mode" "DI")])
11828 (define_insn "ashrdi3_1"
11829 [(set (match_operand:DI 0 "register_operand" "=r")
11830 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11831 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11832 (clobber (match_scratch:SI 3 "=&r"))
11833 (clobber (reg:CC 17))]
11834 "!TARGET_64BIT && TARGET_CMOVE"
11836 [(set_attr "type" "multi")])
11838 (define_insn "*ashrdi3_2"
11839 [(set (match_operand:DI 0 "register_operand" "=r")
11840 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
11841 (match_operand:QI 2 "nonmemory_operand" "Jc")))
11842 (clobber (reg:CC 17))]
11845 [(set_attr "type" "multi")])
11848 [(set (match_operand:DI 0 "register_operand" "")
11849 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11850 (match_operand:QI 2 "nonmemory_operand" "")))
11851 (clobber (match_scratch:SI 3 ""))
11852 (clobber (reg:CC 17))]
11853 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
11855 "ix86_split_ashrdi (operands, operands[3]); DONE;")
11858 [(set (match_operand:DI 0 "register_operand" "")
11859 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
11860 (match_operand:QI 2 "nonmemory_operand" "")))
11861 (clobber (reg:CC 17))]
11862 "!TARGET_64BIT && reload_completed"
11864 "ix86_split_ashrdi (operands, NULL_RTX); DONE;")
11866 (define_insn "x86_shrd_1"
11867 [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
11868 (ior:SI (ashiftrt:SI (match_dup 0)
11869 (match_operand:QI 2 "nonmemory_operand" "I,c"))
11870 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
11871 (minus:QI (const_int 32) (match_dup 2)))))
11872 (clobber (reg:CC 17))]
11875 shrd{l}\t{%2, %1, %0|%0, %1, %2}
11876 shrd{l}\t{%s2%1, %0|%0, %1, %2}"
11877 [(set_attr "type" "ishift")
11878 (set_attr "prefix_0f" "1")
11879 (set_attr "pent_pair" "np")
11880 (set_attr "ppro_uops" "few")
11881 (set_attr "mode" "SI")])
11883 (define_expand "x86_shift_adj_3"
11884 [(use (match_operand:SI 0 "register_operand" ""))
11885 (use (match_operand:SI 1 "register_operand" ""))
11886 (use (match_operand:QI 2 "register_operand" ""))]
11889 rtx label = gen_label_rtx ();
11892 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
11894 tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
11895 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
11896 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11897 gen_rtx_LABEL_REF (VOIDmode, label),
11899 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11900 JUMP_LABEL (tmp) = label;
11902 emit_move_insn (operands[0], operands[1]);
11903 emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
11905 emit_label (label);
11906 LABEL_NUSES (label) = 1;
11911 (define_insn "ashrsi3_31"
11912 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
11913 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
11914 (match_operand:SI 2 "const_int_operand" "i,i")))
11915 (clobber (reg:CC 17))]
11916 "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
11917 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11920 sar{l}\t{%2, %0|%0, %2}"
11921 [(set_attr "type" "imovx,ishift")
11922 (set_attr "prefix_0f" "0,*")
11923 (set_attr "length_immediate" "0,*")
11924 (set_attr "modrm" "0,1")
11925 (set_attr "mode" "SI")])
11927 (define_insn "*ashrsi3_31_zext"
11928 [(set (match_operand:DI 0 "register_operand" "=*d,r")
11929 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
11930 (match_operand:SI 2 "const_int_operand" "i,i"))))
11931 (clobber (reg:CC 17))]
11932 "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
11933 && INTVAL (operands[2]) == 31
11934 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11937 sar{l}\t{%2, %k0|%k0, %2}"
11938 [(set_attr "type" "imovx,ishift")
11939 (set_attr "prefix_0f" "0,*")
11940 (set_attr "length_immediate" "0,*")
11941 (set_attr "modrm" "0,1")
11942 (set_attr "mode" "SI")])
11944 (define_expand "ashrsi3"
11945 [(set (match_operand:SI 0 "nonimmediate_operand" "")
11946 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
11947 (match_operand:QI 2 "nonmemory_operand" "")))
11948 (clobber (reg:CC 17))]
11950 "ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;")
11952 (define_insn "*ashrsi3_1_one_bit"
11953 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
11954 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
11955 (match_operand:QI 2 "const_int_1_operand" "")))
11956 (clobber (reg:CC 17))]
11957 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11958 && (TARGET_SHIFT1 || optimize_size)"
11960 [(set_attr "type" "ishift")
11961 (set (attr "length")
11962 (if_then_else (match_operand:SI 0 "register_operand" "")
11964 (const_string "*")))])
11966 (define_insn "*ashrsi3_1_one_bit_zext"
11967 [(set (match_operand:DI 0 "register_operand" "=r")
11968 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11969 (match_operand:QI 2 "const_int_1_operand" ""))))
11970 (clobber (reg:CC 17))]
11971 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)
11972 && (TARGET_SHIFT1 || optimize_size)"
11974 [(set_attr "type" "ishift")
11975 (set_attr "length" "2")])
11977 (define_insn "*ashrsi3_1"
11978 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
11979 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
11980 (match_operand:QI 2 "nonmemory_operand" "I,c")))
11981 (clobber (reg:CC 17))]
11982 "ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11984 sar{l}\t{%2, %0|%0, %2}
11985 sar{l}\t{%b2, %0|%0, %b2}"
11986 [(set_attr "type" "ishift")
11987 (set_attr "mode" "SI")])
11989 (define_insn "*ashrsi3_1_zext"
11990 [(set (match_operand:DI 0 "register_operand" "=r,r")
11991 (zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
11992 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
11993 (clobber (reg:CC 17))]
11994 "TARGET_64BIT && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
11996 sar{l}\t{%2, %k0|%k0, %2}
11997 sar{l}\t{%b2, %k0|%k0, %b2}"
11998 [(set_attr "type" "ishift")
11999 (set_attr "mode" "SI")])
12001 ;; This pattern can't accept a variable shift count, since shifts by
12002 ;; zero don't affect the flags. We assume that shifts by constant
12003 ;; zero are optimized away.
12004 (define_insn "*ashrsi3_one_bit_cmp"
12007 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12008 (match_operand:QI 2 "const_int_1_operand" ""))
12010 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12011 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
12012 "ix86_match_ccmode (insn, CCGOCmode)
12013 && (TARGET_SHIFT1 || optimize_size)
12014 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12016 [(set_attr "type" "ishift")
12017 (set (attr "length")
12018 (if_then_else (match_operand:SI 0 "register_operand" "")
12020 (const_string "*")))])
12022 (define_insn "*ashrsi3_one_bit_cmp_zext"
12025 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12026 (match_operand:QI 2 "const_int_1_operand" ""))
12028 (set (match_operand:DI 0 "register_operand" "=r")
12029 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
12030 "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)
12031 && (TARGET_SHIFT1 || optimize_size)
12032 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12034 [(set_attr "type" "ishift")
12035 (set_attr "length" "2")])
12037 ;; This pattern can't accept a variable shift count, since shifts by
12038 ;; zero don't affect the flags. We assume that shifts by constant
12039 ;; zero are optimized away.
12040 (define_insn "*ashrsi3_cmp"
12043 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12044 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12046 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12047 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
12048 "ix86_match_ccmode (insn, CCGOCmode)
12049 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12050 "sar{l}\t{%2, %0|%0, %2}"
12051 [(set_attr "type" "ishift")
12052 (set_attr "mode" "SI")])
12054 (define_insn "*ashrsi3_cmp_zext"
12057 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12058 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12060 (set (match_operand:DI 0 "register_operand" "=r")
12061 (zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
12062 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12063 && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
12064 "sar{l}\t{%2, %k0|%k0, %2}"
12065 [(set_attr "type" "ishift")
12066 (set_attr "mode" "SI")])
12068 (define_expand "ashrhi3"
12069 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12070 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12071 (match_operand:QI 2 "nonmemory_operand" "")))
12072 (clobber (reg:CC 17))]
12073 "TARGET_HIMODE_MATH"
12074 "ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;")
12076 (define_insn "*ashrhi3_1_one_bit"
12077 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12078 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12079 (match_operand:QI 2 "const_int_1_operand" "")))
12080 (clobber (reg:CC 17))]
12081 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)
12082 && (TARGET_SHIFT1 || optimize_size)"
12084 [(set_attr "type" "ishift")
12085 (set (attr "length")
12086 (if_then_else (match_operand 0 "register_operand" "")
12088 (const_string "*")))])
12090 (define_insn "*ashrhi3_1"
12091 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12092 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12093 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12094 (clobber (reg:CC 17))]
12095 "ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12097 sar{w}\t{%2, %0|%0, %2}
12098 sar{w}\t{%b2, %0|%0, %b2}"
12099 [(set_attr "type" "ishift")
12100 (set_attr "mode" "HI")])
12102 ;; This pattern can't accept a variable shift count, since shifts by
12103 ;; zero don't affect the flags. We assume that shifts by constant
12104 ;; zero are optimized away.
12105 (define_insn "*ashrhi3_one_bit_cmp"
12108 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12109 (match_operand:QI 2 "const_int_1_operand" ""))
12111 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12112 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
12113 "ix86_match_ccmode (insn, CCGOCmode)
12114 && (TARGET_SHIFT1 || optimize_size)
12115 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12117 [(set_attr "type" "ishift")
12118 (set (attr "length")
12119 (if_then_else (match_operand 0 "register_operand" "")
12121 (const_string "*")))])
12123 ;; This pattern can't accept a variable shift count, since shifts by
12124 ;; zero don't affect the flags. We assume that shifts by constant
12125 ;; zero are optimized away.
12126 (define_insn "*ashrhi3_cmp"
12129 (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12130 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12132 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12133 (ashiftrt:HI (match_dup 1) (match_dup 2)))]
12134 "ix86_match_ccmode (insn, CCGOCmode)
12135 && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
12136 "sar{w}\t{%2, %0|%0, %2}"
12137 [(set_attr "type" "ishift")
12138 (set_attr "mode" "HI")])
12140 (define_expand "ashrqi3"
12141 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12142 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12143 (match_operand:QI 2 "nonmemory_operand" "")))
12144 (clobber (reg:CC 17))]
12145 "TARGET_QIMODE_MATH"
12146 "ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;")
12148 (define_insn "*ashrqi3_1_one_bit"
12149 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12150 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12151 (match_operand:QI 2 "const_int_1_operand" "")))
12152 (clobber (reg:CC 17))]
12153 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
12154 && (TARGET_SHIFT1 || optimize_size)"
12156 [(set_attr "type" "ishift")
12157 (set (attr "length")
12158 (if_then_else (match_operand 0 "register_operand" "")
12160 (const_string "*")))])
12162 (define_insn "*ashrqi3_1_one_bit_slp"
12163 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12164 (ashiftrt:QI (match_dup 0)
12165 (match_operand:QI 1 "const_int_1_operand" "")))
12166 (clobber (reg:CC 17))]
12167 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)
12168 && (! TARGET_PARTIAL_REG_STALL || optimize_size)
12169 && (TARGET_SHIFT1 || optimize_size)"
12171 [(set_attr "type" "ishift1")
12172 (set (attr "length")
12173 (if_then_else (match_operand 0 "register_operand" "")
12175 (const_string "*")))])
12177 (define_insn "*ashrqi3_1"
12178 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12179 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12180 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12181 (clobber (reg:CC 17))]
12182 "ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12184 sar{b}\t{%2, %0|%0, %2}
12185 sar{b}\t{%b2, %0|%0, %b2}"
12186 [(set_attr "type" "ishift")
12187 (set_attr "mode" "QI")])
12189 (define_insn "*ashrqi3_1_slp"
12190 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12191 (ashiftrt:QI (match_dup 0)
12192 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12193 (clobber (reg:CC 17))]
12194 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12195 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12197 sar{b}\t{%1, %0|%0, %1}
12198 sar{b}\t{%b1, %0|%0, %b1}"
12199 [(set_attr "type" "ishift1")
12200 (set_attr "mode" "QI")])
12202 ;; This pattern can't accept a variable shift count, since shifts by
12203 ;; zero don't affect the flags. We assume that shifts by constant
12204 ;; zero are optimized away.
12205 (define_insn "*ashrqi3_one_bit_cmp"
12208 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12209 (match_operand:QI 2 "const_int_1_operand" "I"))
12211 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12212 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
12213 "ix86_match_ccmode (insn, CCGOCmode)
12214 && (TARGET_SHIFT1 || optimize_size)
12215 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12217 [(set_attr "type" "ishift")
12218 (set (attr "length")
12219 (if_then_else (match_operand 0 "register_operand" "")
12221 (const_string "*")))])
12223 ;; This pattern can't accept a variable shift count, since shifts by
12224 ;; zero don't affect the flags. We assume that shifts by constant
12225 ;; zero are optimized away.
12226 (define_insn "*ashrqi3_cmp"
12229 (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12230 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12232 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12233 (ashiftrt:QI (match_dup 1) (match_dup 2)))]
12234 "ix86_match_ccmode (insn, CCGOCmode)
12235 && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
12236 "sar{b}\t{%2, %0|%0, %2}"
12237 [(set_attr "type" "ishift")
12238 (set_attr "mode" "QI")])
12240 ;; Logical shift instructions
12242 ;; See comment above `ashldi3' about how this works.
12244 (define_expand "lshrdi3"
12245 [(parallel [(set (match_operand:DI 0 "shiftdi_operand" "")
12246 (lshiftrt:DI (match_operand:DI 1 "shiftdi_operand" "")
12247 (match_operand:QI 2 "nonmemory_operand" "")))
12248 (clobber (reg:CC 17))])]
12251 if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
12253 emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
12256 ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
12260 (define_insn "*lshrdi3_1_one_bit_rex64"
12261 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12262 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12263 (match_operand:QI 2 "const_int_1_operand" "")))
12264 (clobber (reg:CC 17))]
12265 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12266 && (TARGET_SHIFT1 || optimize_size)"
12268 [(set_attr "type" "ishift")
12269 (set (attr "length")
12270 (if_then_else (match_operand:DI 0 "register_operand" "")
12272 (const_string "*")))])
12274 (define_insn "*lshrdi3_1_rex64"
12275 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12276 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12277 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12278 (clobber (reg:CC 17))]
12279 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12281 shr{q}\t{%2, %0|%0, %2}
12282 shr{q}\t{%b2, %0|%0, %b2}"
12283 [(set_attr "type" "ishift")
12284 (set_attr "mode" "DI")])
12286 ;; This pattern can't accept a variable shift count, since shifts by
12287 ;; zero don't affect the flags. We assume that shifts by constant
12288 ;; zero are optimized away.
12289 (define_insn "*lshrdi3_cmp_one_bit_rex64"
12292 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12293 (match_operand:QI 2 "const_int_1_operand" ""))
12295 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12296 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12297 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12298 && (TARGET_SHIFT1 || optimize_size)
12299 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12301 [(set_attr "type" "ishift")
12302 (set (attr "length")
12303 (if_then_else (match_operand:DI 0 "register_operand" "")
12305 (const_string "*")))])
12307 ;; This pattern can't accept a variable shift count, since shifts by
12308 ;; zero don't affect the flags. We assume that shifts by constant
12309 ;; zero are optimized away.
12310 (define_insn "*lshrdi3_cmp_rex64"
12313 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12314 (match_operand:QI 2 "const_int_operand" "e"))
12316 (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12317 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
12318 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12319 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12320 "shr{q}\t{%2, %0|%0, %2}"
12321 [(set_attr "type" "ishift")
12322 (set_attr "mode" "DI")])
12324 (define_insn "lshrdi3_1"
12325 [(set (match_operand:DI 0 "register_operand" "=r")
12326 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
12327 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12328 (clobber (match_scratch:SI 3 "=&r"))
12329 (clobber (reg:CC 17))]
12330 "!TARGET_64BIT && TARGET_CMOVE"
12332 [(set_attr "type" "multi")])
12334 (define_insn "*lshrdi3_2"
12335 [(set (match_operand:DI 0 "register_operand" "=r")
12336 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
12337 (match_operand:QI 2 "nonmemory_operand" "Jc")))
12338 (clobber (reg:CC 17))]
12341 [(set_attr "type" "multi")])
12344 [(set (match_operand:DI 0 "register_operand" "")
12345 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12346 (match_operand:QI 2 "nonmemory_operand" "")))
12347 (clobber (match_scratch:SI 3 ""))
12348 (clobber (reg:CC 17))]
12349 "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
12351 "ix86_split_lshrdi (operands, operands[3]); DONE;")
12354 [(set (match_operand:DI 0 "register_operand" "")
12355 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
12356 (match_operand:QI 2 "nonmemory_operand" "")))
12357 (clobber (reg:CC 17))]
12358 "!TARGET_64BIT && reload_completed"
12360 "ix86_split_lshrdi (operands, NULL_RTX); DONE;")
12362 (define_expand "lshrsi3"
12363 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12364 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "")
12365 (match_operand:QI 2 "nonmemory_operand" "")))
12366 (clobber (reg:CC 17))]
12368 "ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;")
12370 (define_insn "*lshrsi3_1_one_bit"
12371 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12372 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12373 (match_operand:QI 2 "const_int_1_operand" "")))
12374 (clobber (reg:CC 17))]
12375 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12376 && (TARGET_SHIFT1 || optimize_size)"
12378 [(set_attr "type" "ishift")
12379 (set (attr "length")
12380 (if_then_else (match_operand:SI 0 "register_operand" "")
12382 (const_string "*")))])
12384 (define_insn "*lshrsi3_1_one_bit_zext"
12385 [(set (match_operand:DI 0 "register_operand" "=r")
12386 (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
12387 (match_operand:QI 2 "const_int_1_operand" "")))
12388 (clobber (reg:CC 17))]
12389 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12390 && (TARGET_SHIFT1 || optimize_size)"
12392 [(set_attr "type" "ishift")
12393 (set_attr "length" "2")])
12395 (define_insn "*lshrsi3_1"
12396 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12397 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12398 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12399 (clobber (reg:CC 17))]
12400 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12402 shr{l}\t{%2, %0|%0, %2}
12403 shr{l}\t{%b2, %0|%0, %b2}"
12404 [(set_attr "type" "ishift")
12405 (set_attr "mode" "SI")])
12407 (define_insn "*lshrsi3_1_zext"
12408 [(set (match_operand:DI 0 "register_operand" "=r,r")
12410 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12411 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12412 (clobber (reg:CC 17))]
12413 "TARGET_64BIT && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12415 shr{l}\t{%2, %k0|%k0, %2}
12416 shr{l}\t{%b2, %k0|%k0, %b2}"
12417 [(set_attr "type" "ishift")
12418 (set_attr "mode" "SI")])
12420 ;; This pattern can't accept a variable shift count, since shifts by
12421 ;; zero don't affect the flags. We assume that shifts by constant
12422 ;; zero are optimized away.
12423 (define_insn "*lshrsi3_one_bit_cmp"
12426 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12427 (match_operand:QI 2 "const_int_1_operand" ""))
12429 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12430 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12431 "ix86_match_ccmode (insn, CCGOCmode)
12432 && (TARGET_SHIFT1 || optimize_size)
12433 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12435 [(set_attr "type" "ishift")
12436 (set (attr "length")
12437 (if_then_else (match_operand:SI 0 "register_operand" "")
12439 (const_string "*")))])
12441 (define_insn "*lshrsi3_cmp_one_bit_zext"
12444 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12445 (match_operand:QI 2 "const_int_1_operand" ""))
12447 (set (match_operand:DI 0 "register_operand" "=r")
12448 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12449 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12450 && (TARGET_SHIFT1 || optimize_size)
12451 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12453 [(set_attr "type" "ishift")
12454 (set_attr "length" "2")])
12456 ;; This pattern can't accept a variable shift count, since shifts by
12457 ;; zero don't affect the flags. We assume that shifts by constant
12458 ;; zero are optimized away.
12459 (define_insn "*lshrsi3_cmp"
12462 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12463 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12465 (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12466 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
12467 "ix86_match_ccmode (insn, CCGOCmode)
12468 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12469 "shr{l}\t{%2, %0|%0, %2}"
12470 [(set_attr "type" "ishift")
12471 (set_attr "mode" "SI")])
12473 (define_insn "*lshrsi3_cmp_zext"
12476 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12477 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12479 (set (match_operand:DI 0 "register_operand" "=r")
12480 (lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
12481 "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
12482 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12483 "shr{l}\t{%2, %k0|%k0, %2}"
12484 [(set_attr "type" "ishift")
12485 (set_attr "mode" "SI")])
12487 (define_expand "lshrhi3"
12488 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12489 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "")
12490 (match_operand:QI 2 "nonmemory_operand" "")))
12491 (clobber (reg:CC 17))]
12492 "TARGET_HIMODE_MATH"
12493 "ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;")
12495 (define_insn "*lshrhi3_1_one_bit"
12496 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12497 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12498 (match_operand:QI 2 "const_int_1_operand" "")))
12499 (clobber (reg:CC 17))]
12500 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)
12501 && (TARGET_SHIFT1 || optimize_size)"
12503 [(set_attr "type" "ishift")
12504 (set (attr "length")
12505 (if_then_else (match_operand 0 "register_operand" "")
12507 (const_string "*")))])
12509 (define_insn "*lshrhi3_1"
12510 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12511 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12512 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12513 (clobber (reg:CC 17))]
12514 "ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12516 shr{w}\t{%2, %0|%0, %2}
12517 shr{w}\t{%b2, %0|%0, %b2}"
12518 [(set_attr "type" "ishift")
12519 (set_attr "mode" "HI")])
12521 ;; This pattern can't accept a variable shift count, since shifts by
12522 ;; zero don't affect the flags. We assume that shifts by constant
12523 ;; zero are optimized away.
12524 (define_insn "*lshrhi3_one_bit_cmp"
12527 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12528 (match_operand:QI 2 "const_int_1_operand" ""))
12530 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12531 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12532 "ix86_match_ccmode (insn, CCGOCmode)
12533 && (TARGET_SHIFT1 || optimize_size)
12534 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12536 [(set_attr "type" "ishift")
12537 (set (attr "length")
12538 (if_then_else (match_operand:SI 0 "register_operand" "")
12540 (const_string "*")))])
12542 ;; This pattern can't accept a variable shift count, since shifts by
12543 ;; zero don't affect the flags. We assume that shifts by constant
12544 ;; zero are optimized away.
12545 (define_insn "*lshrhi3_cmp"
12548 (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12549 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12551 (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12552 (lshiftrt:HI (match_dup 1) (match_dup 2)))]
12553 "ix86_match_ccmode (insn, CCGOCmode)
12554 && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
12555 "shr{w}\t{%2, %0|%0, %2}"
12556 [(set_attr "type" "ishift")
12557 (set_attr "mode" "HI")])
12559 (define_expand "lshrqi3"
12560 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12561 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "")
12562 (match_operand:QI 2 "nonmemory_operand" "")))
12563 (clobber (reg:CC 17))]
12564 "TARGET_QIMODE_MATH"
12565 "ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;")
12567 (define_insn "*lshrqi3_1_one_bit"
12568 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12569 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12570 (match_operand:QI 2 "const_int_1_operand" "")))
12571 (clobber (reg:CC 17))]
12572 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)
12573 && (TARGET_SHIFT1 || optimize_size)"
12575 [(set_attr "type" "ishift")
12576 (set (attr "length")
12577 (if_then_else (match_operand 0 "register_operand" "")
12579 (const_string "*")))])
12581 (define_insn "*lshrqi3_1_one_bit_slp"
12582 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12583 (lshiftrt:QI (match_dup 0)
12584 (match_operand:QI 1 "const_int_1_operand" "")))
12585 (clobber (reg:CC 17))]
12586 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12587 && (TARGET_SHIFT1 || optimize_size)"
12589 [(set_attr "type" "ishift1")
12590 (set (attr "length")
12591 (if_then_else (match_operand 0 "register_operand" "")
12593 (const_string "*")))])
12595 (define_insn "*lshrqi3_1"
12596 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12597 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12598 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12599 (clobber (reg:CC 17))]
12600 "ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12602 shr{b}\t{%2, %0|%0, %2}
12603 shr{b}\t{%b2, %0|%0, %b2}"
12604 [(set_attr "type" "ishift")
12605 (set_attr "mode" "QI")])
12607 (define_insn "*lshrqi3_1_slp"
12608 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12609 (lshiftrt:QI (match_dup 0)
12610 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12611 (clobber (reg:CC 17))]
12612 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12613 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12615 shr{b}\t{%1, %0|%0, %1}
12616 shr{b}\t{%b1, %0|%0, %b1}"
12617 [(set_attr "type" "ishift1")
12618 (set_attr "mode" "QI")])
12620 ;; This pattern can't accept a variable shift count, since shifts by
12621 ;; zero don't affect the flags. We assume that shifts by constant
12622 ;; zero are optimized away.
12623 (define_insn "*lshrqi2_one_bit_cmp"
12626 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12627 (match_operand:QI 2 "const_int_1_operand" ""))
12629 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12630 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12631 "ix86_match_ccmode (insn, CCGOCmode)
12632 && (TARGET_SHIFT1 || optimize_size)
12633 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12635 [(set_attr "type" "ishift")
12636 (set (attr "length")
12637 (if_then_else (match_operand:SI 0 "register_operand" "")
12639 (const_string "*")))])
12641 ;; This pattern can't accept a variable shift count, since shifts by
12642 ;; zero don't affect the flags. We assume that shifts by constant
12643 ;; zero are optimized away.
12644 (define_insn "*lshrqi2_cmp"
12647 (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12648 (match_operand:QI 2 "const_int_1_31_operand" "I"))
12650 (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12651 (lshiftrt:QI (match_dup 1) (match_dup 2)))]
12652 "ix86_match_ccmode (insn, CCGOCmode)
12653 && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
12654 "shr{b}\t{%2, %0|%0, %2}"
12655 [(set_attr "type" "ishift")
12656 (set_attr "mode" "QI")])
12658 ;; Rotate instructions
12660 (define_expand "rotldi3"
12661 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12662 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "")
12663 (match_operand:QI 2 "nonmemory_operand" "")))
12664 (clobber (reg:CC 17))]
12666 "ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;")
12668 (define_insn "*rotlsi3_1_one_bit_rex64"
12669 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12670 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12671 (match_operand:QI 2 "const_int_1_operand" "")))
12672 (clobber (reg:CC 17))]
12673 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)
12674 && (TARGET_SHIFT1 || optimize_size)"
12676 [(set_attr "type" "rotate")
12677 (set (attr "length")
12678 (if_then_else (match_operand:DI 0 "register_operand" "")
12680 (const_string "*")))])
12682 (define_insn "*rotldi3_1_rex64"
12683 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12684 (rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12685 (match_operand:QI 2 "nonmemory_operand" "e,c")))
12686 (clobber (reg:CC 17))]
12687 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, DImode, operands)"
12689 rol{q}\t{%2, %0|%0, %2}
12690 rol{q}\t{%b2, %0|%0, %b2}"
12691 [(set_attr "type" "rotate")
12692 (set_attr "mode" "DI")])
12694 (define_expand "rotlsi3"
12695 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12696 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "")
12697 (match_operand:QI 2 "nonmemory_operand" "")))
12698 (clobber (reg:CC 17))]
12700 "ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;")
12702 (define_insn "*rotlsi3_1_one_bit"
12703 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12704 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12705 (match_operand:QI 2 "const_int_1_operand" "")))
12706 (clobber (reg:CC 17))]
12707 "ix86_binary_operator_ok (ROTATE, SImode, operands)
12708 && (TARGET_SHIFT1 || optimize_size)"
12710 [(set_attr "type" "rotate")
12711 (set (attr "length")
12712 (if_then_else (match_operand:SI 0 "register_operand" "")
12714 (const_string "*")))])
12716 (define_insn "*rotlsi3_1_one_bit_zext"
12717 [(set (match_operand:DI 0 "register_operand" "=r")
12719 (rotate:SI (match_operand:SI 1 "register_operand" "0")
12720 (match_operand:QI 2 "const_int_1_operand" ""))))
12721 (clobber (reg:CC 17))]
12722 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)
12723 && (TARGET_SHIFT1 || optimize_size)"
12725 [(set_attr "type" "rotate")
12726 (set_attr "length" "2")])
12728 (define_insn "*rotlsi3_1"
12729 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12730 (rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12731 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12732 (clobber (reg:CC 17))]
12733 "ix86_binary_operator_ok (ROTATE, SImode, operands)"
12735 rol{l}\t{%2, %0|%0, %2}
12736 rol{l}\t{%b2, %0|%0, %b2}"
12737 [(set_attr "type" "rotate")
12738 (set_attr "mode" "SI")])
12740 (define_insn "*rotlsi3_1_zext"
12741 [(set (match_operand:DI 0 "register_operand" "=r,r")
12743 (rotate:SI (match_operand:SI 1 "register_operand" "0,0")
12744 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12745 (clobber (reg:CC 17))]
12746 "TARGET_64BIT && ix86_binary_operator_ok (ROTATE, SImode, operands)"
12748 rol{l}\t{%2, %k0|%k0, %2}
12749 rol{l}\t{%b2, %k0|%k0, %b2}"
12750 [(set_attr "type" "rotate")
12751 (set_attr "mode" "SI")])
12753 (define_expand "rotlhi3"
12754 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12755 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "")
12756 (match_operand:QI 2 "nonmemory_operand" "")))
12757 (clobber (reg:CC 17))]
12758 "TARGET_HIMODE_MATH"
12759 "ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;")
12761 (define_insn "*rotlhi3_1_one_bit"
12762 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12763 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12764 (match_operand:QI 2 "const_int_1_operand" "")))
12765 (clobber (reg:CC 17))]
12766 "ix86_binary_operator_ok (ROTATE, HImode, operands)
12767 && (TARGET_SHIFT1 || optimize_size)"
12769 [(set_attr "type" "rotate")
12770 (set (attr "length")
12771 (if_then_else (match_operand 0 "register_operand" "")
12773 (const_string "*")))])
12775 (define_insn "*rotlhi3_1"
12776 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12777 (rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12778 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12779 (clobber (reg:CC 17))]
12780 "ix86_binary_operator_ok (ROTATE, HImode, operands)"
12782 rol{w}\t{%2, %0|%0, %2}
12783 rol{w}\t{%b2, %0|%0, %b2}"
12784 [(set_attr "type" "rotate")
12785 (set_attr "mode" "HI")])
12787 (define_expand "rotlqi3"
12788 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12789 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "")
12790 (match_operand:QI 2 "nonmemory_operand" "")))
12791 (clobber (reg:CC 17))]
12792 "TARGET_QIMODE_MATH"
12793 "ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;")
12795 (define_insn "*rotlqi3_1_one_bit_slp"
12796 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
12797 (rotate:QI (match_dup 0)
12798 (match_operand:QI 1 "const_int_1_operand" "")))
12799 (clobber (reg:CC 17))]
12800 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12801 && (TARGET_SHIFT1 || optimize_size)"
12803 [(set_attr "type" "rotate1")
12804 (set (attr "length")
12805 (if_then_else (match_operand 0 "register_operand" "")
12807 (const_string "*")))])
12809 (define_insn "*rotlqi3_1_one_bit"
12810 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12811 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12812 (match_operand:QI 2 "const_int_1_operand" "")))
12813 (clobber (reg:CC 17))]
12814 "ix86_binary_operator_ok (ROTATE, QImode, operands)
12815 && (TARGET_SHIFT1 || optimize_size)"
12817 [(set_attr "type" "rotate")
12818 (set (attr "length")
12819 (if_then_else (match_operand 0 "register_operand" "")
12821 (const_string "*")))])
12823 (define_insn "*rotlqi3_1_slp"
12824 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
12825 (rotate:QI (match_dup 0)
12826 (match_operand:QI 1 "nonmemory_operand" "I,c")))
12827 (clobber (reg:CC 17))]
12828 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
12829 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
12831 rol{b}\t{%1, %0|%0, %1}
12832 rol{b}\t{%b1, %0|%0, %b1}"
12833 [(set_attr "type" "rotate1")
12834 (set_attr "mode" "QI")])
12836 (define_insn "*rotlqi3_1"
12837 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
12838 (rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
12839 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12840 (clobber (reg:CC 17))]
12841 "ix86_binary_operator_ok (ROTATE, QImode, operands)"
12843 rol{b}\t{%2, %0|%0, %2}
12844 rol{b}\t{%b2, %0|%0, %b2}"
12845 [(set_attr "type" "rotate")
12846 (set_attr "mode" "QI")])
12848 (define_expand "rotrdi3"
12849 [(set (match_operand:DI 0 "nonimmediate_operand" "")
12850 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "")
12851 (match_operand:QI 2 "nonmemory_operand" "")))
12852 (clobber (reg:CC 17))]
12854 "ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;")
12856 (define_insn "*rotrdi3_1_one_bit_rex64"
12857 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
12858 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0")
12859 (match_operand:QI 2 "const_int_1_operand" "")))
12860 (clobber (reg:CC 17))]
12861 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)
12862 && (TARGET_SHIFT1 || optimize_size)"
12864 [(set_attr "type" "rotate")
12865 (set (attr "length")
12866 (if_then_else (match_operand:DI 0 "register_operand" "")
12868 (const_string "*")))])
12870 (define_insn "*rotrdi3_1_rex64"
12871 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm")
12872 (rotatert:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
12873 (match_operand:QI 2 "nonmemory_operand" "J,c")))
12874 (clobber (reg:CC 17))]
12875 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
12877 ror{q}\t{%2, %0|%0, %2}
12878 ror{q}\t{%b2, %0|%0, %b2}"
12879 [(set_attr "type" "rotate")
12880 (set_attr "mode" "DI")])
12882 (define_expand "rotrsi3"
12883 [(set (match_operand:SI 0 "nonimmediate_operand" "")
12884 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "")
12885 (match_operand:QI 2 "nonmemory_operand" "")))
12886 (clobber (reg:CC 17))]
12888 "ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;")
12890 (define_insn "*rotrsi3_1_one_bit"
12891 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
12892 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
12893 (match_operand:QI 2 "const_int_1_operand" "")))
12894 (clobber (reg:CC 17))]
12895 "ix86_binary_operator_ok (ROTATERT, SImode, operands)
12896 && (TARGET_SHIFT1 || optimize_size)"
12898 [(set_attr "type" "rotate")
12899 (set (attr "length")
12900 (if_then_else (match_operand:SI 0 "register_operand" "")
12902 (const_string "*")))])
12904 (define_insn "*rotrsi3_1_one_bit_zext"
12905 [(set (match_operand:DI 0 "register_operand" "=r")
12907 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
12908 (match_operand:QI 2 "const_int_1_operand" ""))))
12909 (clobber (reg:CC 17))]
12910 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)
12911 && (TARGET_SHIFT1 || optimize_size)"
12913 [(set_attr "type" "rotate")
12914 (set (attr "length")
12915 (if_then_else (match_operand:SI 0 "register_operand" "")
12917 (const_string "*")))])
12919 (define_insn "*rotrsi3_1"
12920 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm")
12921 (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
12922 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12923 (clobber (reg:CC 17))]
12924 "ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12926 ror{l}\t{%2, %0|%0, %2}
12927 ror{l}\t{%b2, %0|%0, %b2}"
12928 [(set_attr "type" "rotate")
12929 (set_attr "mode" "SI")])
12931 (define_insn "*rotrsi3_1_zext"
12932 [(set (match_operand:DI 0 "register_operand" "=r,r")
12934 (rotatert:SI (match_operand:SI 1 "register_operand" "0,0")
12935 (match_operand:QI 2 "nonmemory_operand" "I,c"))))
12936 (clobber (reg:CC 17))]
12937 "TARGET_64BIT && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
12939 ror{l}\t{%2, %k0|%k0, %2}
12940 ror{l}\t{%b2, %k0|%k0, %b2}"
12941 [(set_attr "type" "rotate")
12942 (set_attr "mode" "SI")])
12944 (define_expand "rotrhi3"
12945 [(set (match_operand:HI 0 "nonimmediate_operand" "")
12946 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "")
12947 (match_operand:QI 2 "nonmemory_operand" "")))
12948 (clobber (reg:CC 17))]
12949 "TARGET_HIMODE_MATH"
12950 "ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;")
12952 (define_insn "*rotrhi3_one_bit"
12953 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
12954 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
12955 (match_operand:QI 2 "const_int_1_operand" "")))
12956 (clobber (reg:CC 17))]
12957 "ix86_binary_operator_ok (ROTATERT, HImode, operands)
12958 && (TARGET_SHIFT1 || optimize_size)"
12960 [(set_attr "type" "rotate")
12961 (set (attr "length")
12962 (if_then_else (match_operand 0 "register_operand" "")
12964 (const_string "*")))])
12966 (define_insn "*rotrhi3"
12967 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm,rm")
12968 (rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0,0")
12969 (match_operand:QI 2 "nonmemory_operand" "I,c")))
12970 (clobber (reg:CC 17))]
12971 "ix86_binary_operator_ok (ROTATERT, HImode, operands)"
12973 ror{w}\t{%2, %0|%0, %2}
12974 ror{w}\t{%b2, %0|%0, %b2}"
12975 [(set_attr "type" "rotate")
12976 (set_attr "mode" "HI")])
12978 (define_expand "rotrqi3"
12979 [(set (match_operand:QI 0 "nonimmediate_operand" "")
12980 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "")
12981 (match_operand:QI 2 "nonmemory_operand" "")))
12982 (clobber (reg:CC 17))]
12983 "TARGET_QIMODE_MATH"
12984 "ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;")
12986 (define_insn "*rotrqi3_1_one_bit"
12987 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
12988 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
12989 (match_operand:QI 2 "const_int_1_operand" "")))
12990 (clobber (reg:CC 17))]
12991 "ix86_binary_operator_ok (ROTATERT, QImode, operands)
12992 && (TARGET_SHIFT1 || optimize_size)"
12994 [(set_attr "type" "rotate")
12995 (set (attr "length")
12996 (if_then_else (match_operand 0 "register_operand" "")
12998 (const_string "*")))])
13000 (define_insn "*rotrqi3_1_one_bit_slp"
13001 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
13002 (rotatert:QI (match_dup 0)
13003 (match_operand:QI 1 "const_int_1_operand" "")))
13004 (clobber (reg:CC 17))]
13005 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13006 && (TARGET_SHIFT1 || optimize_size)"
13008 [(set_attr "type" "rotate1")
13009 (set (attr "length")
13010 (if_then_else (match_operand 0 "register_operand" "")
13012 (const_string "*")))])
13014 (define_insn "*rotrqi3_1"
13015 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,qm")
13016 (rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0,0")
13017 (match_operand:QI 2 "nonmemory_operand" "I,c")))
13018 (clobber (reg:CC 17))]
13019 "ix86_binary_operator_ok (ROTATERT, QImode, operands)"
13021 ror{b}\t{%2, %0|%0, %2}
13022 ror{b}\t{%b2, %0|%0, %b2}"
13023 [(set_attr "type" "rotate")
13024 (set_attr "mode" "QI")])
13026 (define_insn "*rotrqi3_1_slp"
13027 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,qm"))
13028 (rotatert:QI (match_dup 0)
13029 (match_operand:QI 1 "nonmemory_operand" "I,c")))
13030 (clobber (reg:CC 17))]
13031 "(! TARGET_PARTIAL_REG_STALL || optimize_size)
13032 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
13034 ror{b}\t{%1, %0|%0, %1}
13035 ror{b}\t{%b1, %0|%0, %b1}"
13036 [(set_attr "type" "rotate1")
13037 (set_attr "mode" "QI")])
13039 ;; Bit set / bit test instructions
13041 (define_expand "extv"
13042 [(set (match_operand:SI 0 "register_operand" "")
13043 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
13044 (match_operand:SI 2 "immediate_operand" "")
13045 (match_operand:SI 3 "immediate_operand" "")))]
13048 /* Handle extractions from %ah et al. */
13049 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
13052 /* From mips.md: extract_bit_field doesn't verify that our source
13053 matches the predicate, so check it again here. */
13054 if (! register_operand (operands[1], VOIDmode))
13058 (define_expand "extzv"
13059 [(set (match_operand:SI 0 "register_operand" "")
13060 (zero_extract:SI (match_operand 1 "ext_register_operand" "")
13061 (match_operand:SI 2 "immediate_operand" "")
13062 (match_operand:SI 3 "immediate_operand" "")))]
13065 /* Handle extractions from %ah et al. */
13066 if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
13069 /* From mips.md: extract_bit_field doesn't verify that our source
13070 matches the predicate, so check it again here. */
13071 if (! register_operand (operands[1], VOIDmode))
13075 (define_expand "insv"
13076 [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
13077 (match_operand:SI 1 "immediate_operand" "")
13078 (match_operand:SI 2 "immediate_operand" ""))
13079 (match_operand:SI 3 "register_operand" ""))]
13082 /* Handle extractions from %ah et al. */
13083 if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
13086 /* From mips.md: insert_bit_field doesn't verify that our source
13087 matches the predicate, so check it again here. */
13088 if (! register_operand (operands[0], VOIDmode))
13092 ;; %%% bts, btr, btc, bt.
13094 ;; Store-flag instructions.
13096 ;; For all sCOND expanders, also expand the compare or test insn that
13097 ;; generates cc0. Generate an equality comparison if `seq' or `sne'.
13099 ;; %%% Do the expansion to SImode. If PII, do things the xor+setcc way
13100 ;; to avoid partial register stalls. Otherwise do things the setcc+movzx
13101 ;; way, which can later delete the movzx if only QImode is needed.
13103 (define_expand "seq"
13104 [(set (match_operand:QI 0 "register_operand" "")
13105 (eq:QI (reg:CC 17) (const_int 0)))]
13107 "if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;")
13109 (define_expand "sne"
13110 [(set (match_operand:QI 0 "register_operand" "")
13111 (ne:QI (reg:CC 17) (const_int 0)))]
13113 "if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;")
13115 (define_expand "sgt"
13116 [(set (match_operand:QI 0 "register_operand" "")
13117 (gt:QI (reg:CC 17) (const_int 0)))]
13119 "if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;")
13121 (define_expand "sgtu"
13122 [(set (match_operand:QI 0 "register_operand" "")
13123 (gtu:QI (reg:CC 17) (const_int 0)))]
13125 "if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;")
13127 (define_expand "slt"
13128 [(set (match_operand:QI 0 "register_operand" "")
13129 (lt:QI (reg:CC 17) (const_int 0)))]
13131 "if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;")
13133 (define_expand "sltu"
13134 [(set (match_operand:QI 0 "register_operand" "")
13135 (ltu:QI (reg:CC 17) (const_int 0)))]
13137 "if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;")
13139 (define_expand "sge"
13140 [(set (match_operand:QI 0 "register_operand" "")
13141 (ge:QI (reg:CC 17) (const_int 0)))]
13143 "if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;")
13145 (define_expand "sgeu"
13146 [(set (match_operand:QI 0 "register_operand" "")
13147 (geu:QI (reg:CC 17) (const_int 0)))]
13149 "if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;")
13151 (define_expand "sle"
13152 [(set (match_operand:QI 0 "register_operand" "")
13153 (le:QI (reg:CC 17) (const_int 0)))]
13155 "if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;")
13157 (define_expand "sleu"
13158 [(set (match_operand:QI 0 "register_operand" "")
13159 (leu:QI (reg:CC 17) (const_int 0)))]
13161 "if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;")
13163 (define_expand "sunordered"
13164 [(set (match_operand:QI 0 "register_operand" "")
13165 (unordered:QI (reg:CC 17) (const_int 0)))]
13166 "TARGET_80387 || TARGET_SSE"
13167 "if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;")
13169 (define_expand "sordered"
13170 [(set (match_operand:QI 0 "register_operand" "")
13171 (ordered:QI (reg:CC 17) (const_int 0)))]
13173 "if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;")
13175 (define_expand "suneq"
13176 [(set (match_operand:QI 0 "register_operand" "")
13177 (uneq:QI (reg:CC 17) (const_int 0)))]
13178 "TARGET_80387 || TARGET_SSE"
13179 "if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;")
13181 (define_expand "sunge"
13182 [(set (match_operand:QI 0 "register_operand" "")
13183 (unge:QI (reg:CC 17) (const_int 0)))]
13184 "TARGET_80387 || TARGET_SSE"
13185 "if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;")
13187 (define_expand "sungt"
13188 [(set (match_operand:QI 0 "register_operand" "")
13189 (ungt:QI (reg:CC 17) (const_int 0)))]
13190 "TARGET_80387 || TARGET_SSE"
13191 "if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;")
13193 (define_expand "sunle"
13194 [(set (match_operand:QI 0 "register_operand" "")
13195 (unle:QI (reg:CC 17) (const_int 0)))]
13196 "TARGET_80387 || TARGET_SSE"
13197 "if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;")
13199 (define_expand "sunlt"
13200 [(set (match_operand:QI 0 "register_operand" "")
13201 (unlt:QI (reg:CC 17) (const_int 0)))]
13202 "TARGET_80387 || TARGET_SSE"
13203 "if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;")
13205 (define_expand "sltgt"
13206 [(set (match_operand:QI 0 "register_operand" "")
13207 (ltgt:QI (reg:CC 17) (const_int 0)))]
13208 "TARGET_80387 || TARGET_SSE"
13209 "if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;")
13211 (define_insn "*setcc_1"
13212 [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
13213 (match_operator:QI 1 "ix86_comparison_operator"
13214 [(reg 17) (const_int 0)]))]
13217 [(set_attr "type" "setcc")
13218 (set_attr "mode" "QI")])
13220 (define_insn "setcc_2"
13221 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
13222 (match_operator:QI 1 "ix86_comparison_operator"
13223 [(reg 17) (const_int 0)]))]
13226 [(set_attr "type" "setcc")
13227 (set_attr "mode" "QI")])
13229 ;; In general it is not safe to assume too much about CCmode registers,
13230 ;; so simplify-rtx stops when it sees a second one. Under certain
13231 ;; conditions this is safe on x86, so help combine not create
13238 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13239 (ne:QI (match_operator 1 "ix86_comparison_operator"
13240 [(reg 17) (const_int 0)])
13243 [(set (match_dup 0) (match_dup 1))]
13245 PUT_MODE (operands[1], QImode);
13249 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
13250 (ne:QI (match_operator 1 "ix86_comparison_operator"
13251 [(reg 17) (const_int 0)])
13254 [(set (match_dup 0) (match_dup 1))]
13256 PUT_MODE (operands[1], QImode);
13260 [(set (match_operand:QI 0 "nonimmediate_operand" "")
13261 (eq:QI (match_operator 1 "ix86_comparison_operator"
13262 [(reg 17) (const_int 0)])
13265 [(set (match_dup 0) (match_dup 1))]
13267 rtx new_op1 = copy_rtx (operands[1]);
13268 operands[1] = new_op1;
13269 PUT_MODE (new_op1, QImode);
13270 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
13271 GET_MODE (XEXP (new_op1, 0))));
13273 /* Make sure that (a) the CCmode we have for the flags is strong
13274 enough for the reversed compare or (b) we have a valid FP compare. */
13275 if (! ix86_comparison_operator (new_op1, VOIDmode))
13280 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
13281 (eq:QI (match_operator 1 "ix86_comparison_operator"
13282 [(reg 17) (const_int 0)])
13285 [(set (match_dup 0) (match_dup 1))]
13287 rtx new_op1 = copy_rtx (operands[1]);
13288 operands[1] = new_op1;
13289 PUT_MODE (new_op1, QImode);
13290 PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
13291 GET_MODE (XEXP (new_op1, 0))));
13293 /* Make sure that (a) the CCmode we have for the flags is strong
13294 enough for the reversed compare or (b) we have a valid FP compare. */
13295 if (! ix86_comparison_operator (new_op1, VOIDmode))
13299 ;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
13300 ;; subsequent logical operations are used to imitate conditional moves.
13301 ;; 0xffffffff is NaN, but not in normalized form, so we can't represent
13302 ;; it directly. Further holding this value in pseudo register might bring
13303 ;; problem in implicit normalization in spill code.
13304 ;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
13305 ;; instructions after reload by splitting the conditional move patterns.
13307 (define_insn "*sse_setccsf"
13308 [(set (match_operand:SF 0 "register_operand" "=x")
13309 (match_operator:SF 1 "sse_comparison_operator"
13310 [(match_operand:SF 2 "register_operand" "0")
13311 (match_operand:SF 3 "nonimmediate_operand" "xm")]))]
13312 "TARGET_SSE && reload_completed"
13313 "cmp%D1ss\t{%3, %0|%0, %3}"
13314 [(set_attr "type" "ssecmp")
13315 (set_attr "mode" "SF")])
13317 (define_insn "*sse_setccdf"
13318 [(set (match_operand:DF 0 "register_operand" "=Y")
13319 (match_operator:DF 1 "sse_comparison_operator"
13320 [(match_operand:DF 2 "register_operand" "0")
13321 (match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
13322 "TARGET_SSE2 && reload_completed"
13323 "cmp%D1sd\t{%3, %0|%0, %3}"
13324 [(set_attr "type" "ssecmp")
13325 (set_attr "mode" "DF")])
13327 ;; Basic conditional jump instructions.
13328 ;; We ignore the overflow flag for signed branch instructions.
13330 ;; For all bCOND expanders, also expand the compare or test insn that
13331 ;; generates reg 17. Generate an equality comparison if `beq' or `bne'.
13333 (define_expand "beq"
13335 (if_then_else (match_dup 1)
13336 (label_ref (match_operand 0 "" ""))
13339 "ix86_expand_branch (EQ, operands[0]); DONE;")
13341 (define_expand "bne"
13343 (if_then_else (match_dup 1)
13344 (label_ref (match_operand 0 "" ""))
13347 "ix86_expand_branch (NE, operands[0]); DONE;")
13349 (define_expand "bgt"
13351 (if_then_else (match_dup 1)
13352 (label_ref (match_operand 0 "" ""))
13355 "ix86_expand_branch (GT, operands[0]); DONE;")
13357 (define_expand "bgtu"
13359 (if_then_else (match_dup 1)
13360 (label_ref (match_operand 0 "" ""))
13363 "ix86_expand_branch (GTU, operands[0]); DONE;")
13365 (define_expand "blt"
13367 (if_then_else (match_dup 1)
13368 (label_ref (match_operand 0 "" ""))
13371 "ix86_expand_branch (LT, operands[0]); DONE;")
13373 (define_expand "bltu"
13375 (if_then_else (match_dup 1)
13376 (label_ref (match_operand 0 "" ""))
13379 "ix86_expand_branch (LTU, operands[0]); DONE;")
13381 (define_expand "bge"
13383 (if_then_else (match_dup 1)
13384 (label_ref (match_operand 0 "" ""))
13387 "ix86_expand_branch (GE, operands[0]); DONE;")
13389 (define_expand "bgeu"
13391 (if_then_else (match_dup 1)
13392 (label_ref (match_operand 0 "" ""))
13395 "ix86_expand_branch (GEU, operands[0]); DONE;")
13397 (define_expand "ble"
13399 (if_then_else (match_dup 1)
13400 (label_ref (match_operand 0 "" ""))
13403 "ix86_expand_branch (LE, operands[0]); DONE;")
13405 (define_expand "bleu"
13407 (if_then_else (match_dup 1)
13408 (label_ref (match_operand 0 "" ""))
13411 "ix86_expand_branch (LEU, operands[0]); DONE;")
13413 (define_expand "bunordered"
13415 (if_then_else (match_dup 1)
13416 (label_ref (match_operand 0 "" ""))
13418 "TARGET_80387 || TARGET_SSE"
13419 "ix86_expand_branch (UNORDERED, operands[0]); DONE;")
13421 (define_expand "bordered"
13423 (if_then_else (match_dup 1)
13424 (label_ref (match_operand 0 "" ""))
13426 "TARGET_80387 || TARGET_SSE"
13427 "ix86_expand_branch (ORDERED, operands[0]); DONE;")
13429 (define_expand "buneq"
13431 (if_then_else (match_dup 1)
13432 (label_ref (match_operand 0 "" ""))
13434 "TARGET_80387 || TARGET_SSE"
13435 "ix86_expand_branch (UNEQ, operands[0]); DONE;")
13437 (define_expand "bunge"
13439 (if_then_else (match_dup 1)
13440 (label_ref (match_operand 0 "" ""))
13442 "TARGET_80387 || TARGET_SSE"
13443 "ix86_expand_branch (UNGE, operands[0]); DONE;")
13445 (define_expand "bungt"
13447 (if_then_else (match_dup 1)
13448 (label_ref (match_operand 0 "" ""))
13450 "TARGET_80387 || TARGET_SSE"
13451 "ix86_expand_branch (UNGT, operands[0]); DONE;")
13453 (define_expand "bunle"
13455 (if_then_else (match_dup 1)
13456 (label_ref (match_operand 0 "" ""))
13458 "TARGET_80387 || TARGET_SSE"
13459 "ix86_expand_branch (UNLE, operands[0]); DONE;")
13461 (define_expand "bunlt"
13463 (if_then_else (match_dup 1)
13464 (label_ref (match_operand 0 "" ""))
13466 "TARGET_80387 || TARGET_SSE"
13467 "ix86_expand_branch (UNLT, operands[0]); DONE;")
13469 (define_expand "bltgt"
13471 (if_then_else (match_dup 1)
13472 (label_ref (match_operand 0 "" ""))
13474 "TARGET_80387 || TARGET_SSE"
13475 "ix86_expand_branch (LTGT, operands[0]); DONE;")
13477 (define_insn "*jcc_1"
13479 (if_then_else (match_operator 1 "ix86_comparison_operator"
13480 [(reg 17) (const_int 0)])
13481 (label_ref (match_operand 0 "" ""))
13485 [(set_attr "type" "ibr")
13486 (set_attr "modrm" "0")
13487 (set (attr "length")
13488 (if_then_else (and (ge (minus (match_dup 0) (pc))
13490 (lt (minus (match_dup 0) (pc))
13495 (define_insn "*jcc_2"
13497 (if_then_else (match_operator 1 "ix86_comparison_operator"
13498 [(reg 17) (const_int 0)])
13500 (label_ref (match_operand 0 "" ""))))]
13503 [(set_attr "type" "ibr")
13504 (set_attr "modrm" "0")
13505 (set (attr "length")
13506 (if_then_else (and (ge (minus (match_dup 0) (pc))
13508 (lt (minus (match_dup 0) (pc))
13513 ;; In general it is not safe to assume too much about CCmode registers,
13514 ;; so simplify-rtx stops when it sees a second one. Under certain
13515 ;; conditions this is safe on x86, so help combine not create
13523 (if_then_else (ne (match_operator 0 "ix86_comparison_operator"
13524 [(reg 17) (const_int 0)])
13526 (label_ref (match_operand 1 "" ""))
13530 (if_then_else (match_dup 0)
13531 (label_ref (match_dup 1))
13534 PUT_MODE (operands[0], VOIDmode);
13539 (if_then_else (eq (match_operator 0 "ix86_comparison_operator"
13540 [(reg 17) (const_int 0)])
13542 (label_ref (match_operand 1 "" ""))
13546 (if_then_else (match_dup 0)
13547 (label_ref (match_dup 1))
13550 rtx new_op0 = copy_rtx (operands[0]);
13551 operands[0] = new_op0;
13552 PUT_MODE (new_op0, VOIDmode);
13553 PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
13554 GET_MODE (XEXP (new_op0, 0))));
13556 /* Make sure that (a) the CCmode we have for the flags is strong
13557 enough for the reversed compare or (b) we have a valid FP compare. */
13558 if (! ix86_comparison_operator (new_op0, VOIDmode))
13562 ;; Define combination compare-and-branch fp compare instructions to use
13563 ;; during early optimization. Splitting the operation apart early makes
13564 ;; for bad code when we want to reverse the operation.
13566 (define_insn "*fp_jcc_1"
13568 (if_then_else (match_operator 0 "comparison_operator"
13569 [(match_operand 1 "register_operand" "f")
13570 (match_operand 2 "register_operand" "f")])
13571 (label_ref (match_operand 3 "" ""))
13573 (clobber (reg:CCFP 18))
13574 (clobber (reg:CCFP 17))]
13575 "TARGET_CMOVE && TARGET_80387
13576 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13577 && FLOAT_MODE_P (GET_MODE (operands[1]))
13578 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13579 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13582 (define_insn "*fp_jcc_1_sse"
13584 (if_then_else (match_operator 0 "comparison_operator"
13585 [(match_operand 1 "register_operand" "f#x,x#f")
13586 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13587 (label_ref (match_operand 3 "" ""))
13589 (clobber (reg:CCFP 18))
13590 (clobber (reg:CCFP 17))]
13592 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13593 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13594 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13597 (define_insn "*fp_jcc_1_sse_only"
13599 (if_then_else (match_operator 0 "comparison_operator"
13600 [(match_operand 1 "register_operand" "x")
13601 (match_operand 2 "nonimmediate_operand" "xm")])
13602 (label_ref (match_operand 3 "" ""))
13604 (clobber (reg:CCFP 18))
13605 (clobber (reg:CCFP 17))]
13606 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13607 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13608 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13611 (define_insn "*fp_jcc_2"
13613 (if_then_else (match_operator 0 "comparison_operator"
13614 [(match_operand 1 "register_operand" "f")
13615 (match_operand 2 "register_operand" "f")])
13617 (label_ref (match_operand 3 "" ""))))
13618 (clobber (reg:CCFP 18))
13619 (clobber (reg:CCFP 17))]
13620 "TARGET_CMOVE && TARGET_80387
13621 && !SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13622 && FLOAT_MODE_P (GET_MODE (operands[1]))
13623 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13624 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13627 (define_insn "*fp_jcc_2_sse"
13629 (if_then_else (match_operator 0 "comparison_operator"
13630 [(match_operand 1 "register_operand" "f#x,x#f")
13631 (match_operand 2 "nonimmediate_operand" "f#x,xm#f")])
13633 (label_ref (match_operand 3 "" ""))))
13634 (clobber (reg:CCFP 18))
13635 (clobber (reg:CCFP 17))]
13637 && SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13638 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13639 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13642 (define_insn "*fp_jcc_2_sse_only"
13644 (if_then_else (match_operator 0 "comparison_operator"
13645 [(match_operand 1 "register_operand" "x")
13646 (match_operand 2 "nonimmediate_operand" "xm")])
13648 (label_ref (match_operand 3 "" ""))))
13649 (clobber (reg:CCFP 18))
13650 (clobber (reg:CCFP 17))]
13651 "SSE_FLOAT_MODE_P (GET_MODE (operands[1]))
13652 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13653 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13656 (define_insn "*fp_jcc_3"
13658 (if_then_else (match_operator 0 "comparison_operator"
13659 [(match_operand 1 "register_operand" "f")
13660 (match_operand 2 "nonimmediate_operand" "fm")])
13661 (label_ref (match_operand 3 "" ""))
13663 (clobber (reg:CCFP 18))
13664 (clobber (reg:CCFP 17))
13665 (clobber (match_scratch:HI 4 "=a"))]
13667 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13668 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13669 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13670 && SELECT_CC_MODE (GET_CODE (operands[0]),
13671 operands[1], operands[2]) == CCFPmode
13672 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13675 (define_insn "*fp_jcc_4"
13677 (if_then_else (match_operator 0 "comparison_operator"
13678 [(match_operand 1 "register_operand" "f")
13679 (match_operand 2 "nonimmediate_operand" "fm")])
13681 (label_ref (match_operand 3 "" ""))))
13682 (clobber (reg:CCFP 18))
13683 (clobber (reg:CCFP 17))
13684 (clobber (match_scratch:HI 4 "=a"))]
13686 && (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
13687 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13688 && !ix86_use_fcomi_compare (GET_CODE (operands[0]))
13689 && SELECT_CC_MODE (GET_CODE (operands[0]),
13690 operands[1], operands[2]) == CCFPmode
13691 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13694 (define_insn "*fp_jcc_5"
13696 (if_then_else (match_operator 0 "comparison_operator"
13697 [(match_operand 1 "register_operand" "f")
13698 (match_operand 2 "register_operand" "f")])
13699 (label_ref (match_operand 3 "" ""))
13701 (clobber (reg:CCFP 18))
13702 (clobber (reg:CCFP 17))
13703 (clobber (match_scratch:HI 4 "=a"))]
13705 && FLOAT_MODE_P (GET_MODE (operands[1]))
13706 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13707 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13710 (define_insn "*fp_jcc_6"
13712 (if_then_else (match_operator 0 "comparison_operator"
13713 [(match_operand 1 "register_operand" "f")
13714 (match_operand 2 "register_operand" "f")])
13716 (label_ref (match_operand 3 "" ""))))
13717 (clobber (reg:CCFP 18))
13718 (clobber (reg:CCFP 17))
13719 (clobber (match_scratch:HI 4 "=a"))]
13721 && FLOAT_MODE_P (GET_MODE (operands[1]))
13722 && GET_MODE (operands[1]) == GET_MODE (operands[2])
13723 && ix86_fp_jump_nontrivial_p (GET_CODE (operands[0]))"
13728 (if_then_else (match_operator 0 "comparison_operator"
13729 [(match_operand 1 "register_operand" "")
13730 (match_operand 2 "nonimmediate_operand" "")])
13731 (match_operand 3 "" "")
13732 (match_operand 4 "" "")))
13733 (clobber (reg:CCFP 18))
13734 (clobber (reg:CCFP 17))]
13738 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13739 operands[3], operands[4], NULL_RTX);
13745 (if_then_else (match_operator 0 "comparison_operator"
13746 [(match_operand 1 "register_operand" "")
13747 (match_operand 2 "nonimmediate_operand" "")])
13748 (match_operand 3 "" "")
13749 (match_operand 4 "" "")))
13750 (clobber (reg:CCFP 18))
13751 (clobber (reg:CCFP 17))
13752 (clobber (match_scratch:HI 5 "=a"))]
13755 (if_then_else (match_dup 6)
13759 ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
13760 operands[3], operands[4], operands[5]);
13764 ;; Unconditional and other jump instructions
13766 (define_insn "jump"
13768 (label_ref (match_operand 0 "" "")))]
13771 [(set_attr "type" "ibr")
13772 (set (attr "length")
13773 (if_then_else (and (ge (minus (match_dup 0) (pc))
13775 (lt (minus (match_dup 0) (pc))
13779 (set_attr "modrm" "0")])
13781 (define_expand "indirect_jump"
13782 [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))]
13786 (define_insn "*indirect_jump"
13787 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
13790 [(set_attr "type" "ibr")
13791 (set_attr "length_immediate" "0")])
13793 (define_insn "*indirect_jump_rtx64"
13794 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))]
13797 [(set_attr "type" "ibr")
13798 (set_attr "length_immediate" "0")])
13800 (define_expand "tablejump"
13801 [(parallel [(set (pc) (match_operand 0 "nonimmediate_operand" "rm"))
13802 (use (label_ref (match_operand 1 "" "")))])]
13805 /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
13806 relative. Convert the relative address to an absolute address. */
13810 enum rtx_code code;
13816 op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
13818 else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
13822 op1 = pic_offset_table_rtx;
13827 op0 = pic_offset_table_rtx;
13831 operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
13836 (define_insn "*tablejump_1"
13837 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
13838 (use (label_ref (match_operand 1 "" "")))]
13841 [(set_attr "type" "ibr")
13842 (set_attr "length_immediate" "0")])
13844 (define_insn "*tablejump_1_rtx64"
13845 [(set (pc) (match_operand:DI 0 "nonimmediate_operand" "rm"))
13846 (use (label_ref (match_operand 1 "" "")))]
13849 [(set_attr "type" "ibr")
13850 (set_attr "length_immediate" "0")])
13852 ;; Loop instruction
13854 ;; This is all complicated by the fact that since this is a jump insn
13855 ;; we must handle our own reloads.
13857 (define_expand "doloop_end"
13858 [(use (match_operand 0 "" "")) ; loop pseudo
13859 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13860 (use (match_operand 2 "" "")) ; max iterations
13861 (use (match_operand 3 "" "")) ; loop level
13862 (use (match_operand 4 "" ""))] ; label
13863 "!TARGET_64BIT && TARGET_USE_LOOP"
13866 /* Only use cloop on innermost loops. */
13867 if (INTVAL (operands[3]) > 1)
13869 if (GET_MODE (operands[0]) != SImode)
13871 emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
13876 (define_insn "doloop_end_internal"
13878 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,?*r,?*r")
13880 (label_ref (match_operand 0 "" ""))
13882 (set (match_operand:SI 2 "register_operand" "=1,1,*m*r")
13883 (plus:SI (match_dup 1)
13885 (clobber (match_scratch:SI 3 "=X,X,r"))
13886 (clobber (reg:CC 17))]
13887 "!TARGET_64BIT && TARGET_USE_LOOP"
13889 if (which_alternative != 0)
13891 if (get_attr_length (insn) == 2)
13892 return "%+loop\t%l0";
13894 return "dec{l}\t%1\;%+jne\t%l0";
13896 [(set_attr "ppro_uops" "many")
13897 (set (attr "length")
13898 (if_then_else (and (eq_attr "alternative" "0")
13899 (and (ge (minus (match_dup 0) (pc))
13901 (lt (minus (match_dup 0) (pc))
13905 ;; We don't know the type before shorten branches. Optimistically expect
13906 ;; the loop instruction to match.
13907 (set (attr "type") (const_string "ibr"))])
13911 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13913 (match_operand 0 "" "")
13916 (plus:SI (match_dup 1)
13918 (clobber (match_scratch:SI 2 ""))
13919 (clobber (reg:CC 17))]
13920 "!TARGET_64BIT && TARGET_USE_LOOP
13921 && reload_completed
13922 && REGNO (operands[1]) != 2"
13923 [(parallel [(set (reg:CCZ 17)
13924 (compare:CCZ (plus:SI (match_dup 1) (const_int -1))
13926 (set (match_dup 1) (plus:SI (match_dup 1) (const_int -1)))])
13927 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13934 (if_then_else (ne (match_operand:SI 1 "register_operand" "")
13936 (match_operand 0 "" "")
13938 (set (match_operand:SI 2 "nonimmediate_operand" "")
13939 (plus:SI (match_dup 1)
13941 (clobber (match_scratch:SI 3 ""))
13942 (clobber (reg:CC 17))]
13943 "!TARGET_64BIT && TARGET_USE_LOOP
13944 && reload_completed
13945 && (! REG_P (operands[2])
13946 || ! rtx_equal_p (operands[1], operands[2]))"
13947 [(set (match_dup 3) (match_dup 1))
13948 (parallel [(set (reg:CCZ 17)
13949 (compare:CCZ (plus:SI (match_dup 3) (const_int -1))
13951 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
13952 (set (match_dup 2) (match_dup 3))
13953 (set (pc) (if_then_else (ne (reg:CCZ 17) (const_int 0))
13958 ;; Convert setcc + movzbl to xor + setcc if operands don't overlap.
13961 [(set (reg 17) (match_operand 0 "" ""))
13962 (set (match_operand:QI 1 "register_operand" "")
13963 (match_operator:QI 2 "ix86_comparison_operator"
13964 [(reg 17) (const_int 0)]))
13965 (set (match_operand 3 "q_regs_operand" "")
13966 (zero_extend (match_dup 1)))]
13967 "(peep2_reg_dead_p (3, operands[1])
13968 || operands_match_p (operands[1], operands[3]))
13969 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13970 [(set (match_dup 4) (match_dup 0))
13971 (set (strict_low_part (match_dup 5))
13974 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13975 operands[5] = gen_lowpart (QImode, operands[3]);
13976 ix86_expand_clear (operands[3]);
13979 ;; Similar, but match zero_extendhisi2_and, which adds a clobber.
13982 [(set (reg 17) (match_operand 0 "" ""))
13983 (set (match_operand:QI 1 "register_operand" "")
13984 (match_operator:QI 2 "ix86_comparison_operator"
13985 [(reg 17) (const_int 0)]))
13986 (parallel [(set (match_operand 3 "q_regs_operand" "")
13987 (zero_extend (match_dup 1)))
13988 (clobber (reg:CC 17))])]
13989 "(peep2_reg_dead_p (3, operands[1])
13990 || operands_match_p (operands[1], operands[3]))
13991 && ! reg_overlap_mentioned_p (operands[3], operands[0])"
13992 [(set (match_dup 4) (match_dup 0))
13993 (set (strict_low_part (match_dup 5))
13996 operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
13997 operands[5] = gen_lowpart (QImode, operands[3]);
13998 ix86_expand_clear (operands[3]);
14001 ;; Call instructions.
14003 ;; The predicates normally associated with named expanders are not properly
14004 ;; checked for calls. This is a bug in the generic code, but it isn't that
14005 ;; easy to fix. Ignore it for now and be prepared to fix things up.
14007 ;; Call subroutine returning no value.
14009 (define_expand "call_pop"
14010 [(parallel [(call (match_operand:QI 0 "" "")
14011 (match_operand:SI 1 "" ""))
14013 (plus:SI (reg:SI 7)
14014 (match_operand:SI 3 "" "")))])]
14017 ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3], 0);
14021 (define_insn "*call_pop_0"
14022 [(call (mem:QI (match_operand:SI 0 "constant_call_address_operand" ""))
14023 (match_operand:SI 1 "" ""))
14024 (set (reg:SI 7) (plus:SI (reg:SI 7)
14025 (match_operand:SI 2 "immediate_operand" "")))]
14028 if (SIBLING_CALL_P (insn))
14031 return "call\t%P0";
14033 [(set_attr "type" "call")])
14035 (define_insn "*call_pop_1"
14036 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
14037 (match_operand:SI 1 "" ""))
14038 (set (reg:SI 7) (plus:SI (reg:SI 7)
14039 (match_operand:SI 2 "immediate_operand" "i")))]
14042 if (constant_call_address_operand (operands[0], Pmode))
14044 if (SIBLING_CALL_P (insn))
14047 return "call\t%P0";
14049 if (SIBLING_CALL_P (insn))
14052 return "call\t%A0";
14054 [(set_attr "type" "call")])
14056 (define_expand "call"
14057 [(call (match_operand:QI 0 "" "")
14058 (match_operand 1 "" ""))
14059 (use (match_operand 2 "" ""))]
14062 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 0);
14066 (define_expand "sibcall"
14067 [(call (match_operand:QI 0 "" "")
14068 (match_operand 1 "" ""))
14069 (use (match_operand 2 "" ""))]
14072 ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL, 1);
14076 (define_insn "*call_0"
14077 [(call (mem:QI (match_operand 0 "constant_call_address_operand" ""))
14078 (match_operand 1 "" ""))]
14081 if (SIBLING_CALL_P (insn))
14084 return "call\t%P0";
14086 [(set_attr "type" "call")])
14088 (define_insn "*call_1"
14089 [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
14090 (match_operand 1 "" ""))]
14091 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
14093 if (constant_call_address_operand (operands[0], QImode))
14094 return "call\t%P0";
14095 return "call\t%A0";
14097 [(set_attr "type" "call")])
14099 (define_insn "*sibcall_1"
14100 [(call (mem:QI (match_operand:SI 0 "sibcall_insn_operand" "s,c,d,a"))
14101 (match_operand 1 "" ""))]
14102 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
14104 if (constant_call_address_operand (operands[0], QImode))
14108 [(set_attr "type" "call")])
14110 (define_insn "*call_1_rex64"
14111 [(call (mem:QI (match_operand:DI 0 "call_insn_operand" "rsm"))
14112 (match_operand 1 "" ""))]
14113 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
14115 if (constant_call_address_operand (operands[0], QImode))
14116 return "call\t%P0";
14117 return "call\t%A0";
14119 [(set_attr "type" "call")])
14121 (define_insn "*sibcall_1_rex64"
14122 [(call (mem:QI (match_operand:DI 0 "constant_call_address_operand" ""))
14123 (match_operand 1 "" ""))]
14124 "SIBLING_CALL_P (insn) && TARGET_64BIT"
14126 [(set_attr "type" "call")])
14128 (define_insn "*sibcall_1_rex64_v"
14129 [(call (mem:QI (reg:DI 40))
14130 (match_operand 0 "" ""))]
14131 "SIBLING_CALL_P (insn) && TARGET_64BIT"
14133 [(set_attr "type" "call")])
14136 ;; Call subroutine, returning value in operand 0
14138 (define_expand "call_value_pop"
14139 [(parallel [(set (match_operand 0 "" "")
14140 (call (match_operand:QI 1 "" "")
14141 (match_operand:SI 2 "" "")))
14143 (plus:SI (reg:SI 7)
14144 (match_operand:SI 4 "" "")))])]
14147 ix86_expand_call (operands[0], operands[1], operands[2],
14148 operands[3], operands[4], 0);
14152 (define_expand "call_value"
14153 [(set (match_operand 0 "" "")
14154 (call (match_operand:QI 1 "" "")
14155 (match_operand:SI 2 "" "")))
14156 (use (match_operand:SI 3 "" ""))]
14157 ;; Operand 2 not used on the i386.
14160 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 0);
14164 (define_expand "sibcall_value"
14165 [(set (match_operand 0 "" "")
14166 (call (match_operand:QI 1 "" "")
14167 (match_operand:SI 2 "" "")))
14168 (use (match_operand:SI 3 "" ""))]
14169 ;; Operand 2 not used on the i386.
14172 ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL, 1);
14176 ;; Call subroutine returning any type.
14178 (define_expand "untyped_call"
14179 [(parallel [(call (match_operand 0 "" "")
14181 (match_operand 1 "" "")
14182 (match_operand 2 "" "")])]
14187 /* In order to give reg-stack an easier job in validating two
14188 coprocessor registers as containing a possible return value,
14189 simply pretend the untyped call returns a complex long double
14192 ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
14193 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
14194 operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
14197 for (i = 0; i < XVECLEN (operands[2], 0); i++)
14199 rtx set = XVECEXP (operands[2], 0, i);
14200 emit_move_insn (SET_DEST (set), SET_SRC (set));
14203 /* The optimizer does not know that the call sets the function value
14204 registers we stored in the result block. We avoid problems by
14205 claiming that all hard registers are used and clobbered at this
14207 emit_insn (gen_blockage (const0_rtx));
14212 ;; Prologue and epilogue instructions
14214 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
14215 ;; all of memory. This blocks insns from being moved across this point.
14217 (define_insn "blockage"
14218 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_BLOCKAGE)]
14221 [(set_attr "length" "0")])
14223 ;; Insn emitted into the body of a function to return from a function.
14224 ;; This is only done if the function's epilogue is known to be simple.
14225 ;; See comments for ix86_can_use_return_insn_p in i386.c.
14227 (define_expand "return"
14229 "ix86_can_use_return_insn_p ()"
14231 if (current_function_pops_args)
14233 rtx popc = GEN_INT (current_function_pops_args);
14234 emit_jump_insn (gen_return_pop_internal (popc));
14239 (define_insn "return_internal"
14243 [(set_attr "length" "1")
14244 (set_attr "length_immediate" "0")
14245 (set_attr "modrm" "0")])
14247 ;; Used by x86_machine_dependent_reorg to avoid penalty on single byte RET
14248 ;; instruction Athlon and K8 have.
14250 (define_insn "return_internal_long"
14252 (unspec [(const_int 0)] UNSPEC_REP)]
14255 [(set_attr "length" "1")
14256 (set_attr "length_immediate" "0")
14257 (set_attr "prefix_rep" "1")
14258 (set_attr "modrm" "0")])
14260 (define_insn "return_pop_internal"
14262 (use (match_operand:SI 0 "const_int_operand" ""))]
14265 [(set_attr "length" "3")
14266 (set_attr "length_immediate" "2")
14267 (set_attr "modrm" "0")])
14269 (define_insn "return_indirect_internal"
14271 (use (match_operand:SI 0 "register_operand" "r"))]
14274 [(set_attr "type" "ibr")
14275 (set_attr "length_immediate" "0")])
14281 [(set_attr "length" "1")
14282 (set_attr "length_immediate" "0")
14283 (set_attr "modrm" "0")
14284 (set_attr "ppro_uops" "one")])
14286 ;; Align to 16-byte boundary, max skip in op0. Used to avoid
14287 ;; branch prediction penalty for the third jump in a 16-byte
14290 (define_insn "align"
14291 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_ALIGN)]
14294 #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN
14295 ASM_OUTPUT_MAX_SKIP_ALIGN (asm_out_file, 4, (int)INTVAL (operands[0]));
14297 /* It is tempting to use ASM_OUTPUT_ALIGN here, but we don't want to do that.
14298 The align insn is used to avoid 3 jump instructions in the row to improve
14299 branch prediction and the benefits hardly outweight the cost of extra 8
14300 nops on the average inserted by full alignment pseudo operation. */
14304 [(set_attr "length" "16")])
14306 (define_expand "prologue"
14309 "ix86_expand_prologue (); DONE;")
14311 (define_insn "set_got"
14312 [(set (match_operand:SI 0 "register_operand" "=r")
14313 (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
14314 (clobber (reg:CC 17))]
14316 { return output_set_got (operands[0]); }
14317 [(set_attr "type" "multi")
14318 (set_attr "length" "12")])
14320 (define_expand "epilogue"
14323 "ix86_expand_epilogue (1); DONE;")
14325 (define_expand "sibcall_epilogue"
14328 "ix86_expand_epilogue (0); DONE;")
14330 (define_expand "eh_return"
14331 [(use (match_operand 0 "register_operand" ""))]
14334 rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
14336 /* Tricky bit: we write the address of the handler to which we will
14337 be returning into someone else's stack frame, one word below the
14338 stack address we wish to restore. */
14339 tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
14340 tmp = plus_constant (tmp, -UNITS_PER_WORD);
14341 tmp = gen_rtx_MEM (Pmode, tmp);
14342 emit_move_insn (tmp, ra);
14344 if (Pmode == SImode)
14345 emit_insn (gen_eh_return_si (sa));
14347 emit_insn (gen_eh_return_di (sa));
14352 (define_insn_and_split "eh_return_si"
14353 [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")]
14354 UNSPECV_EH_RETURN)]
14359 "ix86_expand_epilogue (2); DONE;")
14361 (define_insn_and_split "eh_return_di"
14362 [(unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
14363 UNSPECV_EH_RETURN)]
14368 "ix86_expand_epilogue (2); DONE;")
14370 (define_insn "leave"
14371 [(set (reg:SI 7) (plus:SI (reg:SI 6) (const_int 4)))
14372 (set (reg:SI 6) (mem:SI (reg:SI 6)))
14373 (clobber (mem:BLK (scratch)))]
14376 [(set_attr "type" "leave")])
14378 (define_insn "leave_rex64"
14379 [(set (reg:DI 7) (plus:DI (reg:DI 6) (const_int 8)))
14380 (set (reg:DI 6) (mem:DI (reg:DI 6)))
14381 (clobber (mem:BLK (scratch)))]
14384 [(set_attr "type" "leave")])
14386 (define_expand "ffssi2"
14388 [(set (match_operand:SI 0 "register_operand" "")
14389 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
14390 (clobber (match_scratch:SI 2 ""))
14391 (clobber (reg:CC 17))])]
14395 (define_insn_and_split "*ffs_cmove"
14396 [(set (match_operand:SI 0 "register_operand" "=r")
14397 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14398 (clobber (match_scratch:SI 2 "=&r"))
14399 (clobber (reg:CC 17))]
14402 "&& reload_completed"
14403 [(set (match_dup 2) (const_int -1))
14404 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14405 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14406 (set (match_dup 0) (if_then_else:SI
14407 (eq (reg:CCZ 17) (const_int 0))
14410 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14411 (clobber (reg:CC 17))])]
14414 (define_insn_and_split "*ffs_no_cmove"
14415 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
14416 (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14417 (clobber (match_scratch:SI 2 "=&r"))
14418 (clobber (reg:CC 17))]
14422 [(parallel [(set (match_dup 2) (const_int 0))
14423 (clobber (reg:CC 17))])
14424 (parallel [(set (reg:CCZ 17) (compare:CCZ (match_dup 1) (const_int 0)))
14425 (set (match_dup 0) (ctz:SI (match_dup 1)))])
14426 (set (strict_low_part (match_dup 3))
14427 (eq:QI (reg:CCZ 17) (const_int 0)))
14428 (parallel [(set (match_dup 2) (neg:SI (match_dup 2)))
14429 (clobber (reg:CC 17))])
14430 (parallel [(set (match_dup 0) (ior:SI (match_dup 0) (match_dup 2)))
14431 (clobber (reg:CC 17))])
14432 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
14433 (clobber (reg:CC 17))])]
14435 operands[3] = gen_lowpart (QImode, operands[2]);
14438 (define_insn "*ffssi_1"
14440 (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm")
14442 (set (match_operand:SI 0 "register_operand" "=r")
14443 (ctz:SI (match_dup 1)))]
14445 "bsf{l}\t{%1, %0|%0, %1}"
14446 [(set_attr "prefix_0f" "1")
14447 (set_attr "ppro_uops" "few")])
14449 (define_insn "ctzsi2"
14450 [(set (match_operand:SI 0 "register_operand" "=r")
14451 (ctz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
14452 (clobber (reg:CC 17))]
14454 "bsf{l}\t{%1, %0|%0, %1}"
14455 [(set_attr "prefix_0f" "1")
14456 (set_attr "ppro_uops" "few")])
14458 (define_expand "clzsi2"
14460 [(set (match_operand:SI 0 "register_operand" "")
14461 (minus:SI (const_int 31)
14462 (clz:SI (match_operand:SI 1 "nonimmediate_operand" ""))))
14463 (clobber (reg:CC 17))])
14465 [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
14466 (clobber (reg:CC 17))])]
14470 (define_insn "*bsr"
14471 [(set (match_operand:SI 0 "register_operand" "=r")
14472 (minus:SI (const_int 31)
14473 (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))))
14474 (clobber (reg:CC 17))]
14476 "bsr{l}\t{%1, %0|%0, %1}"
14477 [(set_attr "prefix_0f" "1")
14478 (set_attr "ppro_uops" "few")])
14480 ;; Thread-local storage patterns for ELF.
14482 ;; Note that these code sequences must appear exactly as shown
14483 ;; in order to allow linker relaxation.
14485 (define_insn "*tls_global_dynamic_32_gnu"
14486 [(set (match_operand:SI 0 "register_operand" "=a")
14487 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14488 (match_operand:SI 2 "tls_symbolic_operand" "")
14489 (match_operand:SI 3 "call_insn_operand" "")]
14491 (clobber (match_scratch:SI 4 "=d"))
14492 (clobber (match_scratch:SI 5 "=c"))
14493 (clobber (reg:CC 17))]
14494 "!TARGET_64BIT && TARGET_GNU_TLS"
14495 "lea{l}\t{%a2@TLSGD(,%1,1), %0|%0, %a2@TLSGD[%1*1]}\;call\t%P3"
14496 [(set_attr "type" "multi")
14497 (set_attr "length" "12")])
14499 (define_insn "*tls_global_dynamic_32_sun"
14500 [(set (match_operand:SI 0 "register_operand" "=a")
14501 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14502 (match_operand:SI 2 "tls_symbolic_operand" "")
14503 (match_operand:SI 3 "call_insn_operand" "")]
14505 (clobber (match_scratch:SI 4 "=d"))
14506 (clobber (match_scratch:SI 5 "=c"))
14507 (clobber (reg:CC 17))]
14508 "!TARGET_64BIT && TARGET_SUN_TLS"
14509 "lea{l}\t{%a2@DTLNDX(%1), %4|%4, %a2@DTLNDX[%1]}
14510 push{l}\t%4\;call\t%a2@TLSPLT\;pop{l}\t%4\;nop"
14511 [(set_attr "type" "multi")
14512 (set_attr "length" "14")])
14514 (define_expand "tls_global_dynamic_32"
14515 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14518 (match_operand:SI 1 "tls_symbolic_operand" "")
14521 (clobber (match_scratch:SI 4 ""))
14522 (clobber (match_scratch:SI 5 ""))
14523 (clobber (reg:CC 17))])]
14527 operands[2] = pic_offset_table_rtx;
14530 operands[2] = gen_reg_rtx (Pmode);
14531 emit_insn (gen_set_got (operands[2]));
14533 operands[3] = ix86_tls_get_addr ();
14536 (define_insn "*tls_global_dynamic_64"
14537 [(set (match_operand:DI 0 "register_operand" "=a")
14538 (call (mem:QI (match_operand:DI 2 "call_insn_operand" ""))
14539 (match_operand:DI 3 "" "")))
14540 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14543 ".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
14544 [(set_attr "type" "multi")
14545 (set_attr "length" "16")])
14547 (define_expand "tls_global_dynamic_64"
14548 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14549 (call (mem:QI (match_dup 2)) (const_int 0)))
14550 (unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
14554 operands[2] = ix86_tls_get_addr ();
14557 (define_insn "*tls_local_dynamic_base_32_gnu"
14558 [(set (match_operand:SI 0 "register_operand" "=a")
14559 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14560 (match_operand:SI 2 "call_insn_operand" "")]
14561 UNSPEC_TLS_LD_BASE))
14562 (clobber (match_scratch:SI 3 "=d"))
14563 (clobber (match_scratch:SI 4 "=c"))
14564 (clobber (reg:CC 17))]
14565 "!TARGET_64BIT && TARGET_GNU_TLS"
14566 "lea{l}\t{%&@TLSLDM(%1), %0|%0, %&@TLSLDM[%1]}\;call\t%P2"
14567 [(set_attr "type" "multi")
14568 (set_attr "length" "11")])
14570 (define_insn "*tls_local_dynamic_base_32_sun"
14571 [(set (match_operand:SI 0 "register_operand" "=a")
14572 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14573 (match_operand:SI 2 "call_insn_operand" "")]
14574 UNSPEC_TLS_LD_BASE))
14575 (clobber (match_scratch:SI 3 "=d"))
14576 (clobber (match_scratch:SI 4 "=c"))
14577 (clobber (reg:CC 17))]
14578 "!TARGET_64BIT && TARGET_SUN_TLS"
14579 "lea{l}\t{%&@TMDNX(%1), %3|%3, %&@TMDNX[%1]}
14580 push{l}\t%3\;call\t%&@TLSPLT\;pop{l}\t%3"
14581 [(set_attr "type" "multi")
14582 (set_attr "length" "13")])
14584 (define_expand "tls_local_dynamic_base_32"
14585 [(parallel [(set (match_operand:SI 0 "register_operand" "")
14586 (unspec:SI [(match_dup 1) (match_dup 2)]
14587 UNSPEC_TLS_LD_BASE))
14588 (clobber (match_scratch:SI 3 ""))
14589 (clobber (match_scratch:SI 4 ""))
14590 (clobber (reg:CC 17))])]
14594 operands[1] = pic_offset_table_rtx;
14597 operands[1] = gen_reg_rtx (Pmode);
14598 emit_insn (gen_set_got (operands[1]));
14600 operands[2] = ix86_tls_get_addr ();
14603 (define_insn "*tls_local_dynamic_base_64"
14604 [(set (match_operand:DI 0 "register_operand" "=a")
14605 (call (mem:QI (match_operand:DI 1 "call_insn_operand" ""))
14606 (match_operand:DI 2 "" "")))
14607 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
14609 "lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
14610 [(set_attr "type" "multi")
14611 (set_attr "length" "12")])
14613 (define_expand "tls_local_dynamic_base_64"
14614 [(parallel [(set (match_operand:DI 0 "register_operand" "")
14615 (call (mem:QI (match_dup 1)) (const_int 0)))
14616 (unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)])]
14619 operands[1] = ix86_tls_get_addr ();
14622 ;; Local dynamic of a single variable is a lose. Show combine how
14623 ;; to convert that back to global dynamic.
14625 (define_insn_and_split "*tls_local_dynamic_32_once"
14626 [(set (match_operand:SI 0 "register_operand" "=a")
14627 (plus:SI (unspec:SI [(match_operand:SI 1 "register_operand" "b")
14628 (match_operand:SI 2 "call_insn_operand" "")]
14629 UNSPEC_TLS_LD_BASE)
14630 (const:SI (unspec:SI
14631 [(match_operand:SI 3 "tls_symbolic_operand" "")]
14633 (clobber (match_scratch:SI 4 "=d"))
14634 (clobber (match_scratch:SI 5 "=c"))
14635 (clobber (reg:CC 17))]
14639 [(parallel [(set (match_dup 0)
14640 (unspec:SI [(match_dup 1) (match_dup 3) (match_dup 2)]
14642 (clobber (match_dup 4))
14643 (clobber (match_dup 5))
14644 (clobber (reg:CC 17))])]
14647 ;; Load and add the thread base pointer from %gs:0.
14649 (define_insn "*load_tp_si"
14650 [(set (match_operand:SI 0 "register_operand" "=r")
14651 (unspec:SI [(const_int 0)] UNSPEC_TP))]
14653 "mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14654 [(set_attr "type" "imov")
14655 (set_attr "modrm" "0")
14656 (set_attr "length" "7")
14657 (set_attr "memory" "load")
14658 (set_attr "imm_disp" "false")])
14660 (define_insn "*add_tp_si"
14661 [(set (match_operand:SI 0 "register_operand" "=r")
14662 (plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
14663 (match_operand:SI 1 "register_operand" "0")))
14664 (clobber (reg:CC 17))]
14666 "add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
14667 [(set_attr "type" "alu")
14668 (set_attr "modrm" "0")
14669 (set_attr "length" "7")
14670 (set_attr "memory" "load")
14671 (set_attr "imm_disp" "false")])
14673 (define_insn "*load_tp_di"
14674 [(set (match_operand:DI 0 "register_operand" "=r")
14675 (unspec:DI [(const_int 0)] UNSPEC_TP))]
14677 "mov{l}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14678 [(set_attr "type" "imov")
14679 (set_attr "modrm" "0")
14680 (set_attr "length" "7")
14681 (set_attr "memory" "load")
14682 (set_attr "imm_disp" "false")])
14684 (define_insn "*add_tp_di"
14685 [(set (match_operand:DI 0 "register_operand" "=r")
14686 (plus:DI (unspec:DI [(const_int 0)] UNSPEC_TP)
14687 (match_operand:DI 1 "register_operand" "0")))
14688 (clobber (reg:CC 17))]
14690 "add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
14691 [(set_attr "type" "alu")
14692 (set_attr "modrm" "0")
14693 (set_attr "length" "7")
14694 (set_attr "memory" "load")
14695 (set_attr "imm_disp" "false")])
14697 ;; These patterns match the binary 387 instructions for addM3, subM3,
14698 ;; mulM3 and divM3. There are three patterns for each of DFmode and
14699 ;; SFmode. The first is the normal insn, the second the same insn but
14700 ;; with one operand a conversion, and the third the same insn but with
14701 ;; the other operand a conversion. The conversion may be SFmode or
14702 ;; SImode if the target mode DFmode, but only SImode if the target mode
14705 ;; Gcc is slightly more smart about handling normal two address instructions
14706 ;; so use special patterns for add and mull.
14707 (define_insn "*fop_sf_comm_nosse"
14708 [(set (match_operand:SF 0 "register_operand" "=f")
14709 (match_operator:SF 3 "binary_fp_operator"
14710 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14711 (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
14712 "TARGET_80387 && !TARGET_SSE_MATH
14713 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14714 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14715 "* return output_387_binary_op (insn, operands);"
14716 [(set (attr "type")
14717 (if_then_else (match_operand:SF 3 "mult_operator" "")
14718 (const_string "fmul")
14719 (const_string "fop")))
14720 (set_attr "mode" "SF")])
14722 (define_insn "*fop_sf_comm"
14723 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
14724 (match_operator:SF 3 "binary_fp_operator"
14725 [(match_operand:SF 1 "nonimmediate_operand" "%0,0")
14726 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
14727 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14728 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14729 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14730 "* return output_387_binary_op (insn, operands);"
14731 [(set (attr "type")
14732 (if_then_else (eq_attr "alternative" "1")
14733 (if_then_else (match_operand:SF 3 "mult_operator" "")
14734 (const_string "ssemul")
14735 (const_string "sseadd"))
14736 (if_then_else (match_operand:SF 3 "mult_operator" "")
14737 (const_string "fmul")
14738 (const_string "fop"))))
14739 (set_attr "mode" "SF")])
14741 (define_insn "*fop_sf_comm_sse"
14742 [(set (match_operand:SF 0 "register_operand" "=x")
14743 (match_operator:SF 3 "binary_fp_operator"
14744 [(match_operand:SF 1 "nonimmediate_operand" "%0")
14745 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14746 "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14747 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14748 "* return output_387_binary_op (insn, operands);"
14749 [(set (attr "type")
14750 (if_then_else (match_operand:SF 3 "mult_operator" "")
14751 (const_string "ssemul")
14752 (const_string "sseadd")))
14753 (set_attr "mode" "SF")])
14755 (define_insn "*fop_df_comm_nosse"
14756 [(set (match_operand:DF 0 "register_operand" "=f")
14757 (match_operator:DF 3 "binary_fp_operator"
14758 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14759 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
14760 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14761 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14762 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14763 "* return output_387_binary_op (insn, operands);"
14764 [(set (attr "type")
14765 (if_then_else (match_operand:SF 3 "mult_operator" "")
14766 (const_string "fmul")
14767 (const_string "fop")))
14768 (set_attr "mode" "DF")])
14770 (define_insn "*fop_df_comm"
14771 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
14772 (match_operator:DF 3 "binary_fp_operator"
14773 [(match_operand:DF 1 "nonimmediate_operand" "%0,0")
14774 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
14775 "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
14776 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14777 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14778 "* return output_387_binary_op (insn, operands);"
14779 [(set (attr "type")
14780 (if_then_else (eq_attr "alternative" "1")
14781 (if_then_else (match_operand:SF 3 "mult_operator" "")
14782 (const_string "ssemul")
14783 (const_string "sseadd"))
14784 (if_then_else (match_operand:SF 3 "mult_operator" "")
14785 (const_string "fmul")
14786 (const_string "fop"))))
14787 (set_attr "mode" "DF")])
14789 (define_insn "*fop_df_comm_sse"
14790 [(set (match_operand:DF 0 "register_operand" "=Y")
14791 (match_operator:DF 3 "binary_fp_operator"
14792 [(match_operand:DF 1 "nonimmediate_operand" "%0")
14793 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14794 "TARGET_SSE2 && TARGET_SSE_MATH
14795 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
14796 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14797 "* return output_387_binary_op (insn, operands);"
14798 [(set (attr "type")
14799 (if_then_else (match_operand:SF 3 "mult_operator" "")
14800 (const_string "ssemul")
14801 (const_string "sseadd")))
14802 (set_attr "mode" "DF")])
14804 (define_insn "*fop_xf_comm"
14805 [(set (match_operand:XF 0 "register_operand" "=f")
14806 (match_operator:XF 3 "binary_fp_operator"
14807 [(match_operand:XF 1 "register_operand" "%0")
14808 (match_operand:XF 2 "register_operand" "f")]))]
14809 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
14810 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14811 "* return output_387_binary_op (insn, operands);"
14812 [(set (attr "type")
14813 (if_then_else (match_operand:XF 3 "mult_operator" "")
14814 (const_string "fmul")
14815 (const_string "fop")))
14816 (set_attr "mode" "XF")])
14818 (define_insn "*fop_tf_comm"
14819 [(set (match_operand:TF 0 "register_operand" "=f")
14820 (match_operator:TF 3 "binary_fp_operator"
14821 [(match_operand:TF 1 "register_operand" "%0")
14822 (match_operand:TF 2 "register_operand" "f")]))]
14823 "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
14824 "* return output_387_binary_op (insn, operands);"
14825 [(set (attr "type")
14826 (if_then_else (match_operand:TF 3 "mult_operator" "")
14827 (const_string "fmul")
14828 (const_string "fop")))
14829 (set_attr "mode" "XF")])
14831 (define_insn "*fop_sf_1_nosse"
14832 [(set (match_operand:SF 0 "register_operand" "=f,f")
14833 (match_operator:SF 3 "binary_fp_operator"
14834 [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
14835 (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
14836 "TARGET_80387 && !TARGET_SSE_MATH
14837 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14838 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14839 "* return output_387_binary_op (insn, operands);"
14840 [(set (attr "type")
14841 (cond [(match_operand:SF 3 "mult_operator" "")
14842 (const_string "fmul")
14843 (match_operand:SF 3 "div_operator" "")
14844 (const_string "fdiv")
14846 (const_string "fop")))
14847 (set_attr "mode" "SF")])
14849 (define_insn "*fop_sf_1"
14850 [(set (match_operand:SF 0 "register_operand" "=f,f,x")
14851 (match_operator:SF 3 "binary_fp_operator"
14852 [(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
14853 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
14854 "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14855 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14856 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14857 "* return output_387_binary_op (insn, operands);"
14858 [(set (attr "type")
14859 (cond [(and (eq_attr "alternative" "2")
14860 (match_operand:SF 3 "mult_operator" ""))
14861 (const_string "ssemul")
14862 (and (eq_attr "alternative" "2")
14863 (match_operand:SF 3 "div_operator" ""))
14864 (const_string "ssediv")
14865 (eq_attr "alternative" "2")
14866 (const_string "sseadd")
14867 (match_operand:SF 3 "mult_operator" "")
14868 (const_string "fmul")
14869 (match_operand:SF 3 "div_operator" "")
14870 (const_string "fdiv")
14872 (const_string "fop")))
14873 (set_attr "mode" "SF")])
14875 (define_insn "*fop_sf_1_sse"
14876 [(set (match_operand:SF 0 "register_operand" "=x")
14877 (match_operator:SF 3 "binary_fp_operator"
14878 [(match_operand:SF 1 "register_operand" "0")
14879 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
14881 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14882 "* return output_387_binary_op (insn, operands);"
14883 [(set (attr "type")
14884 (cond [(match_operand:SF 3 "mult_operator" "")
14885 (const_string "ssemul")
14886 (match_operand:SF 3 "div_operator" "")
14887 (const_string "ssediv")
14889 (const_string "sseadd")))
14890 (set_attr "mode" "SF")])
14892 ;; ??? Add SSE splitters for these!
14893 (define_insn "*fop_sf_2"
14894 [(set (match_operand:SF 0 "register_operand" "=f,f")
14895 (match_operator:SF 3 "binary_fp_operator"
14896 [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14897 (match_operand:SF 2 "register_operand" "0,0")]))]
14898 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14899 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14900 [(set (attr "type")
14901 (cond [(match_operand:SF 3 "mult_operator" "")
14902 (const_string "fmul")
14903 (match_operand:SF 3 "div_operator" "")
14904 (const_string "fdiv")
14906 (const_string "fop")))
14907 (set_attr "fp_int_src" "true")
14908 (set_attr "ppro_uops" "many")
14909 (set_attr "mode" "SI")])
14911 (define_insn "*fop_sf_3"
14912 [(set (match_operand:SF 0 "register_operand" "=f,f")
14913 (match_operator:SF 3 "binary_fp_operator"
14914 [(match_operand:SF 1 "register_operand" "0,0")
14915 (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
14916 "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
14917 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14918 [(set (attr "type")
14919 (cond [(match_operand:SF 3 "mult_operator" "")
14920 (const_string "fmul")
14921 (match_operand:SF 3 "div_operator" "")
14922 (const_string "fdiv")
14924 (const_string "fop")))
14925 (set_attr "fp_int_src" "true")
14926 (set_attr "ppro_uops" "many")
14927 (set_attr "mode" "SI")])
14929 (define_insn "*fop_df_1_nosse"
14930 [(set (match_operand:DF 0 "register_operand" "=f,f")
14931 (match_operator:DF 3 "binary_fp_operator"
14932 [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
14933 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
14934 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
14935 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14936 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14937 "* return output_387_binary_op (insn, operands);"
14938 [(set (attr "type")
14939 (cond [(match_operand:DF 3 "mult_operator" "")
14940 (const_string "fmul")
14941 (match_operand:DF 3 "div_operator" "")
14942 (const_string "fdiv")
14944 (const_string "fop")))
14945 (set_attr "mode" "DF")])
14948 (define_insn "*fop_df_1"
14949 [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
14950 (match_operator:DF 3 "binary_fp_operator"
14951 [(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
14952 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
14953 "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
14954 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
14955 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
14956 "* return output_387_binary_op (insn, operands);"
14957 [(set (attr "type")
14958 (cond [(and (eq_attr "alternative" "2")
14959 (match_operand:SF 3 "mult_operator" ""))
14960 (const_string "ssemul")
14961 (and (eq_attr "alternative" "2")
14962 (match_operand:SF 3 "div_operator" ""))
14963 (const_string "ssediv")
14964 (eq_attr "alternative" "2")
14965 (const_string "sseadd")
14966 (match_operand:DF 3 "mult_operator" "")
14967 (const_string "fmul")
14968 (match_operand:DF 3 "div_operator" "")
14969 (const_string "fdiv")
14971 (const_string "fop")))
14972 (set_attr "mode" "DF")])
14974 (define_insn "*fop_df_1_sse"
14975 [(set (match_operand:DF 0 "register_operand" "=Y")
14976 (match_operator:DF 3 "binary_fp_operator"
14977 [(match_operand:DF 1 "register_operand" "0")
14978 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
14979 "TARGET_SSE2 && TARGET_SSE_MATH
14980 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
14981 "* return output_387_binary_op (insn, operands);"
14982 [(set_attr "mode" "DF")
14984 (cond [(match_operand:SF 3 "mult_operator" "")
14985 (const_string "ssemul")
14986 (match_operand:SF 3 "div_operator" "")
14987 (const_string "ssediv")
14989 (const_string "sseadd")))])
14991 ;; ??? Add SSE splitters for these!
14992 (define_insn "*fop_df_2"
14993 [(set (match_operand:DF 0 "register_operand" "=f,f")
14994 (match_operator:DF 3 "binary_fp_operator"
14995 [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
14996 (match_operand:DF 2 "register_operand" "0,0")]))]
14997 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
14998 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
14999 [(set (attr "type")
15000 (cond [(match_operand:DF 3 "mult_operator" "")
15001 (const_string "fmul")
15002 (match_operand:DF 3 "div_operator" "")
15003 (const_string "fdiv")
15005 (const_string "fop")))
15006 (set_attr "fp_int_src" "true")
15007 (set_attr "ppro_uops" "many")
15008 (set_attr "mode" "SI")])
15010 (define_insn "*fop_df_3"
15011 [(set (match_operand:DF 0 "register_operand" "=f,f")
15012 (match_operator:DF 3 "binary_fp_operator"
15013 [(match_operand:DF 1 "register_operand" "0,0")
15014 (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
15015 "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
15016 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15017 [(set (attr "type")
15018 (cond [(match_operand:DF 3 "mult_operator" "")
15019 (const_string "fmul")
15020 (match_operand:DF 3 "div_operator" "")
15021 (const_string "fdiv")
15023 (const_string "fop")))
15024 (set_attr "fp_int_src" "true")
15025 (set_attr "ppro_uops" "many")
15026 (set_attr "mode" "SI")])
15028 (define_insn "*fop_df_4"
15029 [(set (match_operand:DF 0 "register_operand" "=f,f")
15030 (match_operator:DF 3 "binary_fp_operator"
15031 [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
15032 (match_operand:DF 2 "register_operand" "0,f")]))]
15033 "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
15034 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
15035 "* return output_387_binary_op (insn, operands);"
15036 [(set (attr "type")
15037 (cond [(match_operand:DF 3 "mult_operator" "")
15038 (const_string "fmul")
15039 (match_operand:DF 3 "div_operator" "")
15040 (const_string "fdiv")
15042 (const_string "fop")))
15043 (set_attr "mode" "SF")])
15045 (define_insn "*fop_df_5"
15046 [(set (match_operand:DF 0 "register_operand" "=f,f")
15047 (match_operator:DF 3 "binary_fp_operator"
15048 [(match_operand:DF 1 "register_operand" "0,f")
15050 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
15051 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
15052 "* return output_387_binary_op (insn, operands);"
15053 [(set (attr "type")
15054 (cond [(match_operand:DF 3 "mult_operator" "")
15055 (const_string "fmul")
15056 (match_operand:DF 3 "div_operator" "")
15057 (const_string "fdiv")
15059 (const_string "fop")))
15060 (set_attr "mode" "SF")])
15062 (define_insn "*fop_df_6"
15063 [(set (match_operand:DF 0 "register_operand" "=f,f")
15064 (match_operator:DF 3 "binary_fp_operator"
15066 (match_operand:SF 1 "register_operand" "0,f"))
15068 (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
15069 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
15070 "* return output_387_binary_op (insn, operands);"
15071 [(set (attr "type")
15072 (cond [(match_operand:DF 3 "mult_operator" "")
15073 (const_string "fmul")
15074 (match_operand:DF 3 "div_operator" "")
15075 (const_string "fdiv")
15077 (const_string "fop")))
15078 (set_attr "mode" "SF")])
15080 (define_insn "*fop_xf_1"
15081 [(set (match_operand:XF 0 "register_operand" "=f,f")
15082 (match_operator:XF 3 "binary_fp_operator"
15083 [(match_operand:XF 1 "register_operand" "0,f")
15084 (match_operand:XF 2 "register_operand" "f,0")]))]
15085 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387
15086 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
15087 "* return output_387_binary_op (insn, operands);"
15088 [(set (attr "type")
15089 (cond [(match_operand:XF 3 "mult_operator" "")
15090 (const_string "fmul")
15091 (match_operand:XF 3 "div_operator" "")
15092 (const_string "fdiv")
15094 (const_string "fop")))
15095 (set_attr "mode" "XF")])
15097 (define_insn "*fop_tf_1"
15098 [(set (match_operand:TF 0 "register_operand" "=f,f")
15099 (match_operator:TF 3 "binary_fp_operator"
15100 [(match_operand:TF 1 "register_operand" "0,f")
15101 (match_operand:TF 2 "register_operand" "f,0")]))]
15103 && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
15104 "* return output_387_binary_op (insn, operands);"
15105 [(set (attr "type")
15106 (cond [(match_operand:TF 3 "mult_operator" "")
15107 (const_string "fmul")
15108 (match_operand:TF 3 "div_operator" "")
15109 (const_string "fdiv")
15111 (const_string "fop")))
15112 (set_attr "mode" "XF")])
15114 (define_insn "*fop_xf_2"
15115 [(set (match_operand:XF 0 "register_operand" "=f,f")
15116 (match_operator:XF 3 "binary_fp_operator"
15117 [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
15118 (match_operand:XF 2 "register_operand" "0,0")]))]
15119 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && TARGET_USE_FIOP"
15120 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15121 [(set (attr "type")
15122 (cond [(match_operand:XF 3 "mult_operator" "")
15123 (const_string "fmul")
15124 (match_operand:XF 3 "div_operator" "")
15125 (const_string "fdiv")
15127 (const_string "fop")))
15128 (set_attr "fp_int_src" "true")
15129 (set_attr "mode" "SI")
15130 (set_attr "ppro_uops" "many")])
15132 (define_insn "*fop_tf_2"
15133 [(set (match_operand:TF 0 "register_operand" "=f,f")
15134 (match_operator:TF 3 "binary_fp_operator"
15135 [(float:TF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
15136 (match_operand:TF 2 "register_operand" "0,0")]))]
15137 "TARGET_80387 && TARGET_USE_FIOP"
15138 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15139 [(set (attr "type")
15140 (cond [(match_operand:TF 3 "mult_operator" "")
15141 (const_string "fmul")
15142 (match_operand:TF 3 "div_operator" "")
15143 (const_string "fdiv")
15145 (const_string "fop")))
15146 (set_attr "fp_int_src" "true")
15147 (set_attr "mode" "SI")
15148 (set_attr "ppro_uops" "many")])
15150 (define_insn "*fop_xf_3"
15151 [(set (match_operand:XF 0 "register_operand" "=f,f")
15152 (match_operator:XF 3 "binary_fp_operator"
15153 [(match_operand:XF 1 "register_operand" "0,0")
15154 (float:XF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
15155 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && TARGET_USE_FIOP"
15156 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15157 [(set (attr "type")
15158 (cond [(match_operand:XF 3 "mult_operator" "")
15159 (const_string "fmul")
15160 (match_operand:XF 3 "div_operator" "")
15161 (const_string "fdiv")
15163 (const_string "fop")))
15164 (set_attr "fp_int_src" "true")
15165 (set_attr "mode" "SI")
15166 (set_attr "ppro_uops" "many")])
15168 (define_insn "*fop_tf_3"
15169 [(set (match_operand:TF 0 "register_operand" "=f,f")
15170 (match_operator:TF 3 "binary_fp_operator"
15171 [(match_operand:TF 1 "register_operand" "0,0")
15172 (float:TF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
15173 "TARGET_80387 && TARGET_USE_FIOP"
15174 "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
15175 [(set (attr "type")
15176 (cond [(match_operand:TF 3 "mult_operator" "")
15177 (const_string "fmul")
15178 (match_operand:TF 3 "div_operator" "")
15179 (const_string "fdiv")
15181 (const_string "fop")))
15182 (set_attr "fp_int_src" "true")
15183 (set_attr "mode" "SI")
15184 (set_attr "ppro_uops" "many")])
15186 (define_insn "*fop_xf_4"
15187 [(set (match_operand:XF 0 "register_operand" "=f,f")
15188 (match_operator:XF 3 "binary_fp_operator"
15189 [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
15190 (match_operand:XF 2 "register_operand" "0,f")]))]
15191 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
15192 "* return output_387_binary_op (insn, operands);"
15193 [(set (attr "type")
15194 (cond [(match_operand:XF 3 "mult_operator" "")
15195 (const_string "fmul")
15196 (match_operand:XF 3 "div_operator" "")
15197 (const_string "fdiv")
15199 (const_string "fop")))
15200 (set_attr "mode" "SF")])
15202 (define_insn "*fop_tf_4"
15203 [(set (match_operand:TF 0 "register_operand" "=f,f")
15204 (match_operator:TF 3 "binary_fp_operator"
15205 [(float_extend:TF (match_operand 1 "nonimmediate_operand" "fm,0"))
15206 (match_operand:TF 2 "register_operand" "0,f")]))]
15208 "* return output_387_binary_op (insn, operands);"
15209 [(set (attr "type")
15210 (cond [(match_operand:TF 3 "mult_operator" "")
15211 (const_string "fmul")
15212 (match_operand:TF 3 "div_operator" "")
15213 (const_string "fdiv")
15215 (const_string "fop")))
15216 (set_attr "mode" "SF")])
15218 (define_insn "*fop_xf_5"
15219 [(set (match_operand:XF 0 "register_operand" "=f,f")
15220 (match_operator:XF 3 "binary_fp_operator"
15221 [(match_operand:XF 1 "register_operand" "0,f")
15223 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15224 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
15225 "* return output_387_binary_op (insn, operands);"
15226 [(set (attr "type")
15227 (cond [(match_operand:XF 3 "mult_operator" "")
15228 (const_string "fmul")
15229 (match_operand:XF 3 "div_operator" "")
15230 (const_string "fdiv")
15232 (const_string "fop")))
15233 (set_attr "mode" "SF")])
15235 (define_insn "*fop_tf_5"
15236 [(set (match_operand:TF 0 "register_operand" "=f,f")
15237 (match_operator:TF 3 "binary_fp_operator"
15238 [(match_operand:TF 1 "register_operand" "0,f")
15240 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15242 "* return output_387_binary_op (insn, operands);"
15243 [(set (attr "type")
15244 (cond [(match_operand:TF 3 "mult_operator" "")
15245 (const_string "fmul")
15246 (match_operand:TF 3 "div_operator" "")
15247 (const_string "fdiv")
15249 (const_string "fop")))
15250 (set_attr "mode" "SF")])
15252 (define_insn "*fop_xf_6"
15253 [(set (match_operand:XF 0 "register_operand" "=f,f")
15254 (match_operator:XF 3 "binary_fp_operator"
15256 (match_operand 1 "register_operand" "0,f"))
15258 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15259 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387"
15260 "* return output_387_binary_op (insn, operands);"
15261 [(set (attr "type")
15262 (cond [(match_operand:XF 3 "mult_operator" "")
15263 (const_string "fmul")
15264 (match_operand:XF 3 "div_operator" "")
15265 (const_string "fdiv")
15267 (const_string "fop")))
15268 (set_attr "mode" "SF")])
15270 (define_insn "*fop_tf_6"
15271 [(set (match_operand:TF 0 "register_operand" "=f,f")
15272 (match_operator:TF 3 "binary_fp_operator"
15274 (match_operand 1 "register_operand" "0,f"))
15276 (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
15278 "* return output_387_binary_op (insn, operands);"
15279 [(set (attr "type")
15280 (cond [(match_operand:TF 3 "mult_operator" "")
15281 (const_string "fmul")
15282 (match_operand:TF 3 "div_operator" "")
15283 (const_string "fdiv")
15285 (const_string "fop")))
15286 (set_attr "mode" "SF")])
15289 [(set (match_operand 0 "register_operand" "")
15290 (match_operator 3 "binary_fp_operator"
15291 [(float (match_operand:SI 1 "register_operand" ""))
15292 (match_operand 2 "register_operand" "")]))]
15293 "TARGET_80387 && reload_completed
15294 && FLOAT_MODE_P (GET_MODE (operands[0]))"
15297 operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
15298 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
15299 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15300 gen_rtx_fmt_ee (GET_CODE (operands[3]),
15301 GET_MODE (operands[3]),
15304 ix86_free_from_memory (GET_MODE (operands[1]));
15309 [(set (match_operand 0 "register_operand" "")
15310 (match_operator 3 "binary_fp_operator"
15311 [(match_operand 1 "register_operand" "")
15312 (float (match_operand:SI 2 "register_operand" ""))]))]
15313 "TARGET_80387 && reload_completed
15314 && FLOAT_MODE_P (GET_MODE (operands[0]))"
15317 operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
15318 operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
15319 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15320 gen_rtx_fmt_ee (GET_CODE (operands[3]),
15321 GET_MODE (operands[3]),
15324 ix86_free_from_memory (GET_MODE (operands[2]));
15328 ;; FPU special functions.
15330 (define_expand "sqrtsf2"
15331 [(set (match_operand:SF 0 "register_operand" "")
15332 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
15333 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
15335 if (!TARGET_SSE_MATH)
15336 operands[1] = force_reg (SFmode, operands[1]);
15339 (define_insn "sqrtsf2_1"
15340 [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
15341 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
15342 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15343 && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
15346 sqrtss\t{%1, %0|%0, %1}"
15347 [(set_attr "type" "fpspc,sse")
15348 (set_attr "mode" "SF,SF")
15349 (set_attr "athlon_decode" "direct,*")])
15351 (define_insn "sqrtsf2_1_sse_only"
15352 [(set (match_operand:SF 0 "register_operand" "=x")
15353 (sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
15354 "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
15355 "sqrtss\t{%1, %0|%0, %1}"
15356 [(set_attr "type" "sse")
15357 (set_attr "mode" "SF")
15358 (set_attr "athlon_decode" "*")])
15360 (define_insn "sqrtsf2_i387"
15361 [(set (match_operand:SF 0 "register_operand" "=f")
15362 (sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
15363 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15364 && !TARGET_SSE_MATH"
15366 [(set_attr "type" "fpspc")
15367 (set_attr "mode" "SF")
15368 (set_attr "athlon_decode" "direct")])
15370 (define_expand "sqrtdf2"
15371 [(set (match_operand:DF 0 "register_operand" "")
15372 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
15373 "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
15374 || (TARGET_SSE2 && TARGET_SSE_MATH)"
15376 if (!TARGET_SSE2 || !TARGET_SSE_MATH)
15377 operands[1] = force_reg (DFmode, operands[1]);
15380 (define_insn "sqrtdf2_1"
15381 [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
15382 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
15383 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15384 && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
15387 sqrtsd\t{%1, %0|%0, %1}"
15388 [(set_attr "type" "fpspc,sse")
15389 (set_attr "mode" "DF,DF")
15390 (set_attr "athlon_decode" "direct,*")])
15392 (define_insn "sqrtdf2_1_sse_only"
15393 [(set (match_operand:DF 0 "register_operand" "=Y")
15394 (sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
15395 "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
15396 "sqrtsd\t{%1, %0|%0, %1}"
15397 [(set_attr "type" "sse")
15398 (set_attr "mode" "DF")
15399 (set_attr "athlon_decode" "*")])
15401 (define_insn "sqrtdf2_i387"
15402 [(set (match_operand:DF 0 "register_operand" "=f")
15403 (sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
15404 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15405 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
15407 [(set_attr "type" "fpspc")
15408 (set_attr "mode" "DF")
15409 (set_attr "athlon_decode" "direct")])
15411 (define_insn "*sqrtextendsfdf2"
15412 [(set (match_operand:DF 0 "register_operand" "=f")
15413 (sqrt:DF (float_extend:DF
15414 (match_operand:SF 1 "register_operand" "0"))))]
15415 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15416 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
15418 [(set_attr "type" "fpspc")
15419 (set_attr "mode" "DF")
15420 (set_attr "athlon_decode" "direct")])
15422 (define_insn "sqrtxf2"
15423 [(set (match_operand:XF 0 "register_operand" "=f")
15424 (sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
15425 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15426 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
15428 [(set_attr "type" "fpspc")
15429 (set_attr "mode" "XF")
15430 (set_attr "athlon_decode" "direct")])
15432 (define_insn "sqrttf2"
15433 [(set (match_operand:TF 0 "register_operand" "=f")
15434 (sqrt:TF (match_operand:TF 1 "register_operand" "0")))]
15435 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15436 && (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
15438 [(set_attr "type" "fpspc")
15439 (set_attr "mode" "XF")
15440 (set_attr "athlon_decode" "direct")])
15442 (define_insn "*sqrtextenddfxf2"
15443 [(set (match_operand:XF 0 "register_operand" "=f")
15444 (sqrt:XF (float_extend:XF
15445 (match_operand:DF 1 "register_operand" "0"))))]
15446 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
15448 [(set_attr "type" "fpspc")
15449 (set_attr "mode" "XF")
15450 (set_attr "athlon_decode" "direct")])
15452 (define_insn "*sqrtextenddftf2"
15453 [(set (match_operand:TF 0 "register_operand" "=f")
15454 (sqrt:TF (float_extend:TF
15455 (match_operand:DF 1 "register_operand" "0"))))]
15456 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
15458 [(set_attr "type" "fpspc")
15459 (set_attr "mode" "XF")
15460 (set_attr "athlon_decode" "direct")])
15462 (define_insn "*sqrtextendsfxf2"
15463 [(set (match_operand:XF 0 "register_operand" "=f")
15464 (sqrt:XF (float_extend:XF
15465 (match_operand:SF 1 "register_operand" "0"))))]
15466 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
15468 [(set_attr "type" "fpspc")
15469 (set_attr "mode" "XF")
15470 (set_attr "athlon_decode" "direct")])
15472 (define_insn "*sqrtextendsftf2"
15473 [(set (match_operand:TF 0 "register_operand" "=f")
15474 (sqrt:TF (float_extend:TF
15475 (match_operand:SF 1 "register_operand" "0"))))]
15476 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
15478 [(set_attr "type" "fpspc")
15479 (set_attr "mode" "XF")
15480 (set_attr "athlon_decode" "direct")])
15482 (define_insn "sindf2"
15483 [(set (match_operand:DF 0 "register_operand" "=f")
15484 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
15485 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15486 && flag_unsafe_math_optimizations"
15488 [(set_attr "type" "fpspc")
15489 (set_attr "mode" "DF")])
15491 (define_insn "sinsf2"
15492 [(set (match_operand:SF 0 "register_operand" "=f")
15493 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
15494 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15495 && flag_unsafe_math_optimizations"
15497 [(set_attr "type" "fpspc")
15498 (set_attr "mode" "SF")])
15500 (define_insn "*sinextendsfdf2"
15501 [(set (match_operand:DF 0 "register_operand" "=f")
15502 (unspec:DF [(float_extend:DF
15503 (match_operand:SF 1 "register_operand" "0"))]
15505 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15506 && flag_unsafe_math_optimizations"
15508 [(set_attr "type" "fpspc")
15509 (set_attr "mode" "DF")])
15511 (define_insn "sinxf2"
15512 [(set (match_operand:XF 0 "register_operand" "=f")
15513 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
15514 "!TARGET_128BIT_LONG_DOUBLE && TARGET_80387 && !TARGET_NO_FANCY_MATH_387
15515 && flag_unsafe_math_optimizations"
15517 [(set_attr "type" "fpspc")
15518 (set_attr "mode" "XF")])
15520 (define_insn "sintf2"
15521 [(set (match_operand:TF 0 "register_operand" "=f")
15522 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_SIN))]
15523 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15524 && flag_unsafe_math_optimizations"
15526 [(set_attr "type" "fpspc")
15527 (set_attr "mode" "XF")])
15529 (define_insn "cosdf2"
15530 [(set (match_operand:DF 0 "register_operand" "=f")
15531 (unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
15532 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15533 && flag_unsafe_math_optimizations"
15535 [(set_attr "type" "fpspc")
15536 (set_attr "mode" "DF")])
15538 (define_insn "cossf2"
15539 [(set (match_operand:SF 0 "register_operand" "=f")
15540 (unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
15541 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15542 && flag_unsafe_math_optimizations"
15544 [(set_attr "type" "fpspc")
15545 (set_attr "mode" "SF")])
15547 (define_insn "*cosextendsfdf2"
15548 [(set (match_operand:DF 0 "register_operand" "=f")
15549 (unspec:DF [(float_extend:DF
15550 (match_operand:SF 1 "register_operand" "0"))]
15552 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15553 && flag_unsafe_math_optimizations"
15555 [(set_attr "type" "fpspc")
15556 (set_attr "mode" "DF")])
15558 (define_insn "cosxf2"
15559 [(set (match_operand:XF 0 "register_operand" "=f")
15560 (unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
15561 "!TARGET_128BIT_LONG_DOUBLE && ! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15562 && flag_unsafe_math_optimizations"
15564 [(set_attr "type" "fpspc")
15565 (set_attr "mode" "XF")])
15567 (define_insn "costf2"
15568 [(set (match_operand:TF 0 "register_operand" "=f")
15569 (unspec:TF [(match_operand:TF 1 "register_operand" "0")] UNSPEC_COS))]
15570 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15571 && flag_unsafe_math_optimizations"
15573 [(set_attr "type" "fpspc")
15574 (set_attr "mode" "XF")])
15576 (define_insn "atan2df3"
15577 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
15578 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15579 (match_operand:DF 1 "register_operand" "u")]
15581 (clobber (match_dup 1))])]
15582 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15583 && flag_unsafe_math_optimizations"
15585 [(set_attr "type" "fpspc")
15586 (set_attr "mode" "DF")])
15588 (define_insn "atan2sf3"
15589 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
15590 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15591 (match_operand:SF 1 "register_operand" "u")]
15593 (clobber (match_dup 1))])]
15594 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15595 && flag_unsafe_math_optimizations"
15597 [(set_attr "type" "fpspc")
15598 (set_attr "mode" "SF")])
15600 (define_insn "atan2xf3"
15601 [(parallel [(set (match_operand:XF 0 "register_operand" "=f")
15602 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15603 (match_operand:XF 1 "register_operand" "u")]
15605 (clobber (match_dup 1))])]
15606 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15607 && flag_unsafe_math_optimizations"
15609 [(set_attr "type" "fpspc")
15610 (set_attr "mode" "XF")])
15612 (define_insn "atan2tf3"
15613 [(parallel [(set (match_operand:TF 0 "register_operand" "=f")
15614 (unspec:TF [(match_operand:TF 2 "register_operand" "0")
15615 (match_operand:TF 1 "register_operand" "u")]
15617 (clobber (match_dup 1))])]
15618 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15619 && flag_unsafe_math_optimizations"
15621 [(set_attr "type" "fpspc")
15622 (set_attr "mode" "XF")])
15624 (define_insn "*fyl2x_sfxf3"
15625 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
15626 (unspec:SF [(match_operand:SF 2 "register_operand" "0")
15627 (match_operand:XF 1 "register_operand" "u")]
15629 (clobber (match_dup 1))])]
15630 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15631 && flag_unsafe_math_optimizations"
15633 [(set_attr "type" "fpspc")
15634 (set_attr "mode" "SF")])
15636 (define_insn "*fyl2x_dfxf3"
15637 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
15638 (unspec:DF [(match_operand:DF 2 "register_operand" "0")
15639 (match_operand:XF 1 "register_operand" "u")]
15641 (clobber (match_dup 1))])]
15642 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15643 && flag_unsafe_math_optimizations"
15645 [(set_attr "type" "fpspc")
15646 (set_attr "mode" "DF")])
15648 (define_insn "*fyl2x_xf3"
15649 [(parallel [(set (match_operand:XF 0 "register_operand" "=f")
15650 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15651 (match_operand:XF 1 "register_operand" "u")]
15653 (clobber (match_dup 1))])]
15654 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15655 && flag_unsafe_math_optimizations"
15657 [(set_attr "type" "fpspc")
15658 (set_attr "mode" "XF")])
15660 (define_insn "*fyl2x_tfxf3"
15661 [(parallel [(set (match_operand:TF 0 "register_operand" "=f")
15662 (unspec:TF [(match_operand:TF 2 "register_operand" "0")
15663 (match_operand:XF 1 "register_operand" "u")]
15665 (clobber (match_dup 1))])]
15666 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15667 && flag_unsafe_math_optimizations"
15669 [(set_attr "type" "fpspc")
15670 (set_attr "mode" "XF")])
15672 (define_expand "logsf2"
15673 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15674 (unspec:SF [(match_operand:SF 1 "register_operand" "")
15675 (match_dup 2)] UNSPEC_FYL2X))
15676 (clobber (match_dup 2))])]
15677 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15678 && flag_unsafe_math_optimizations"
15682 operands[2] = gen_reg_rtx (XFmode);
15683 temp = standard_80387_constant_rtx (4); /* fldln2 */
15684 emit_move_insn (operands[2], temp);
15687 (define_expand "logdf2"
15688 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15689 (unspec:DF [(match_operand:DF 1 "register_operand" "")
15690 (match_dup 2)] UNSPEC_FYL2X))
15691 (clobber (match_dup 2))])]
15692 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15693 && flag_unsafe_math_optimizations"
15697 operands[2] = gen_reg_rtx (XFmode);
15698 temp = standard_80387_constant_rtx (4); /* fldln2 */
15699 emit_move_insn (operands[2], temp);
15702 (define_expand "logxf2"
15703 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15704 (unspec:XF [(match_operand:XF 1 "register_operand" "")
15705 (match_dup 2)] UNSPEC_FYL2X))
15706 (clobber (match_dup 2))])]
15707 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15708 && flag_unsafe_math_optimizations"
15712 operands[2] = gen_reg_rtx (XFmode);
15713 temp = standard_80387_constant_rtx (4); /* fldln2 */
15714 emit_move_insn (operands[2], temp);
15717 (define_expand "logtf2"
15718 [(parallel [(set (match_operand:TF 0 "register_operand" "")
15719 (unspec:TF [(match_operand:TF 1 "register_operand" "")
15720 (match_dup 2)] UNSPEC_FYL2X))
15721 (clobber (match_dup 2))])]
15722 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15723 && flag_unsafe_math_optimizations"
15727 operands[2] = gen_reg_rtx (XFmode);
15728 temp = standard_80387_constant_rtx (4); /* fldln2 */
15729 emit_move_insn (operands[2], temp);
15732 (define_insn "*fscale_sfxf3"
15733 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
15734 (unspec:SF [(match_operand:XF 2 "register_operand" "0")
15735 (match_operand:XF 1 "register_operand" "u")]
15737 (clobber (match_dup 1))])]
15738 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15739 && flag_unsafe_math_optimizations"
15740 "fscale\;fstp\t%y1"
15741 [(set_attr "type" "fpspc")
15742 (set_attr "mode" "SF")])
15744 (define_insn "*fscale_dfxf3"
15745 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
15746 (unspec:DF [(match_operand:XF 2 "register_operand" "0")
15747 (match_operand:XF 1 "register_operand" "u")]
15749 (clobber (match_dup 1))])]
15750 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15751 && flag_unsafe_math_optimizations"
15752 "fscale\;fstp\t%y1"
15753 [(set_attr "type" "fpspc")
15754 (set_attr "mode" "DF")])
15756 (define_insn "*fscale_xf3"
15757 [(parallel [(set (match_operand:XF 0 "register_operand" "=f")
15758 (unspec:XF [(match_operand:XF 2 "register_operand" "0")
15759 (match_operand:XF 1 "register_operand" "u")]
15761 (clobber (match_dup 1))])]
15762 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15763 && flag_unsafe_math_optimizations"
15764 "fscale\;fstp\t%y1"
15765 [(set_attr "type" "fpspc")
15766 (set_attr "mode" "XF")])
15768 (define_insn "*frndintxf2"
15769 [(set (match_operand:XF 0 "register_operand" "=f")
15770 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15772 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15773 && flag_unsafe_math_optimizations"
15775 [(set_attr "type" "fpspc")
15776 (set_attr "mode" "XF")])
15778 (define_insn "*f2xm1xf2"
15779 [(set (match_operand:XF 0 "register_operand" "=f")
15780 (unspec:XF [(match_operand:XF 1 "register_operand" "0")]
15782 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15783 && flag_unsafe_math_optimizations"
15785 [(set_attr "type" "fpspc")
15786 (set_attr "mode" "XF")])
15788 (define_expand "expsf2"
15789 [(set (match_dup 2)
15790 (float_extend:XF (match_operand:SF 1 "register_operand" "")))
15791 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15792 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15793 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15794 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15795 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15796 (parallel [(set (match_operand:SF 0 "register_operand" "")
15797 (unspec:SF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
15798 (clobber (match_dup 5))])]
15799 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15800 && flag_unsafe_math_optimizations"
15805 for (i=2; i<10; i++)
15806 operands[i] = gen_reg_rtx (XFmode);
15807 temp = standard_80387_constant_rtx (5); /* fldl2e */
15808 emit_move_insn (operands[3], temp);
15809 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15812 (define_expand "expdf2"
15813 [(set (match_dup 2)
15814 (float_extend:XF (match_operand:DF 1 "register_operand" "")))
15815 (set (match_dup 4) (mult:XF (match_dup 2) (match_dup 3)))
15816 (set (match_dup 5) (unspec:XF [(match_dup 4)] UNSPEC_FRNDINT))
15817 (set (match_dup 6) (minus:XF (match_dup 4) (match_dup 5)))
15818 (set (match_dup 7) (unspec:XF [(match_dup 6)] UNSPEC_F2XM1))
15819 (set (match_dup 9) (plus:XF (match_dup 7) (match_dup 8)))
15820 (parallel [(set (match_operand:DF 0 "register_operand" "")
15821 (unspec:DF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
15822 (clobber (match_dup 5))])]
15823 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15824 && flag_unsafe_math_optimizations"
15829 for (i=2; i<10; i++)
15830 operands[i] = gen_reg_rtx (XFmode);
15831 temp = standard_80387_constant_rtx (5); /* fldl2e */
15832 emit_move_insn (operands[3], temp);
15833 emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
15836 (define_expand "expxf2"
15837 [(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
15839 (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT))
15840 (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4)))
15841 (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1))
15842 (set (match_dup 8) (plus:XF (match_dup 6) (match_dup 7)))
15843 (parallel [(set (match_operand:XF 0 "register_operand" "")
15844 (unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
15845 (clobber (match_dup 4))])]
15846 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15847 && flag_unsafe_math_optimizations"
15852 for (i=2; i<9; i++)
15853 operands[i] = gen_reg_rtx (XFmode);
15854 temp = standard_80387_constant_rtx (5); /* fldl2e */
15855 emit_move_insn (operands[2], temp);
15856 emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */
15859 (define_expand "atansf2"
15860 [(parallel [(set (match_operand:SF 0 "register_operand" "")
15861 (unspec:SF [(match_dup 2)
15862 (match_operand:SF 1 "register_operand" "")]
15864 (clobber (match_dup 1))])]
15865 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15866 && flag_unsafe_math_optimizations"
15868 operands[2] = gen_reg_rtx (SFmode);
15869 emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
15872 (define_expand "atandf2"
15873 [(parallel [(set (match_operand:DF 0 "register_operand" "")
15874 (unspec:DF [(match_dup 2)
15875 (match_operand:DF 1 "register_operand" "")]
15877 (clobber (match_dup 1))])]
15878 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15879 && flag_unsafe_math_optimizations"
15881 operands[2] = gen_reg_rtx (DFmode);
15882 emit_move_insn (operands[2], CONST1_RTX (DFmode)); /* fld1 */
15885 (define_expand "atanxf2"
15886 [(parallel [(set (match_operand:XF 0 "register_operand" "")
15887 (unspec:XF [(match_dup 2)
15888 (match_operand:XF 1 "register_operand" "")]
15890 (clobber (match_dup 1))])]
15891 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15892 && flag_unsafe_math_optimizations"
15894 operands[2] = gen_reg_rtx (XFmode);
15895 emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
15898 (define_expand "atantf2"
15899 [(parallel [(set (match_operand:TF 0 "register_operand" "")
15900 (unspec:TF [(match_dup 2)
15901 (match_operand:TF 1 "register_operand" "")]
15903 (clobber (match_dup 1))])]
15904 "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
15905 && flag_unsafe_math_optimizations"
15907 operands[2] = gen_reg_rtx (TFmode);
15908 emit_move_insn (operands[2], CONST1_RTX (TFmode)); /* fld1 */
15911 ;; Block operation instructions
15914 [(set (reg:SI 19) (const_int 0))]
15917 [(set_attr "type" "cld")])
15919 (define_expand "movstrsi"
15920 [(use (match_operand:BLK 0 "memory_operand" ""))
15921 (use (match_operand:BLK 1 "memory_operand" ""))
15922 (use (match_operand:SI 2 "nonmemory_operand" ""))
15923 (use (match_operand:SI 3 "const_int_operand" ""))]
15926 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15932 (define_expand "movstrdi"
15933 [(use (match_operand:BLK 0 "memory_operand" ""))
15934 (use (match_operand:BLK 1 "memory_operand" ""))
15935 (use (match_operand:DI 2 "nonmemory_operand" ""))
15936 (use (match_operand:DI 3 "const_int_operand" ""))]
15939 if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
15945 ;; Most CPUs don't like single string operations
15946 ;; Handle this case here to simplify previous expander.
15948 (define_expand "strmovdi_rex64"
15949 [(set (match_dup 2)
15950 (mem:DI (match_operand:DI 1 "register_operand" "")))
15951 (set (mem:DI (match_operand:DI 0 "register_operand" ""))
15953 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
15954 (clobber (reg:CC 17))])
15955 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 8)))
15956 (clobber (reg:CC 17))])]
15959 if (TARGET_SINGLE_STRINGOP || optimize_size)
15961 emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
15966 operands[2] = gen_reg_rtx (DImode);
15970 (define_expand "strmovsi"
15971 [(set (match_dup 2)
15972 (mem:SI (match_operand:SI 1 "register_operand" "")))
15973 (set (mem:SI (match_operand:SI 0 "register_operand" ""))
15975 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
15976 (clobber (reg:CC 17))])
15977 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))
15978 (clobber (reg:CC 17))])]
15983 emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
15986 if (TARGET_SINGLE_STRINGOP || optimize_size)
15988 emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
15993 operands[2] = gen_reg_rtx (SImode);
15996 (define_expand "strmovsi_rex64"
15997 [(set (match_dup 2)
15998 (mem:SI (match_operand:DI 1 "register_operand" "")))
15999 (set (mem:SI (match_operand:DI 0 "register_operand" ""))
16001 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
16002 (clobber (reg:CC 17))])
16003 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 4)))
16004 (clobber (reg:CC 17))])]
16007 if (TARGET_SINGLE_STRINGOP || optimize_size)
16009 emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
16014 operands[2] = gen_reg_rtx (SImode);
16017 (define_expand "strmovhi"
16018 [(set (match_dup 2)
16019 (mem:HI (match_operand:SI 1 "register_operand" "")))
16020 (set (mem:HI (match_operand:SI 0 "register_operand" ""))
16022 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
16023 (clobber (reg:CC 17))])
16024 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
16025 (clobber (reg:CC 17))])]
16030 emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
16033 if (TARGET_SINGLE_STRINGOP || optimize_size)
16035 emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
16040 operands[2] = gen_reg_rtx (HImode);
16043 (define_expand "strmovhi_rex64"
16044 [(set (match_dup 2)
16045 (mem:HI (match_operand:DI 1 "register_operand" "")))
16046 (set (mem:HI (match_operand:DI 0 "register_operand" ""))
16048 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
16049 (clobber (reg:CC 17))])
16050 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 2)))
16051 (clobber (reg:CC 17))])]
16054 if (TARGET_SINGLE_STRINGOP || optimize_size)
16056 emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
16061 operands[2] = gen_reg_rtx (HImode);
16064 (define_expand "strmovqi"
16065 [(set (match_dup 2)
16066 (mem:QI (match_operand:SI 1 "register_operand" "")))
16067 (set (mem:QI (match_operand:SI 0 "register_operand" ""))
16069 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
16070 (clobber (reg:CC 17))])
16071 (parallel [(set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))
16072 (clobber (reg:CC 17))])]
16077 emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
16080 if (TARGET_SINGLE_STRINGOP || optimize_size)
16082 emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
16087 operands[2] = gen_reg_rtx (QImode);
16090 (define_expand "strmovqi_rex64"
16091 [(set (match_dup 2)
16092 (mem:QI (match_operand:DI 1 "register_operand" "")))
16093 (set (mem:QI (match_operand:DI 0 "register_operand" ""))
16095 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
16096 (clobber (reg:CC 17))])
16097 (parallel [(set (match_dup 1) (plus:DI (match_dup 1) (const_int 1)))
16098 (clobber (reg:CC 17))])]
16101 if (TARGET_SINGLE_STRINGOP || optimize_size)
16103 emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
16108 operands[2] = gen_reg_rtx (QImode);
16111 (define_insn "strmovdi_rex_1"
16112 [(set (mem:DI (match_operand:DI 2 "register_operand" "0"))
16113 (mem:DI (match_operand:DI 3 "register_operand" "1")))
16114 (set (match_operand:DI 0 "register_operand" "=D")
16115 (plus:DI (match_dup 2)
16117 (set (match_operand:DI 1 "register_operand" "=S")
16118 (plus:DI (match_dup 3)
16121 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16123 [(set_attr "type" "str")
16124 (set_attr "mode" "DI")
16125 (set_attr "memory" "both")])
16127 (define_insn "strmovsi_1"
16128 [(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
16129 (mem:SI (match_operand:SI 3 "register_operand" "1")))
16130 (set (match_operand:SI 0 "register_operand" "=D")
16131 (plus:SI (match_dup 2)
16133 (set (match_operand:SI 1 "register_operand" "=S")
16134 (plus:SI (match_dup 3)
16137 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16139 [(set_attr "type" "str")
16140 (set_attr "mode" "SI")
16141 (set_attr "memory" "both")])
16143 (define_insn "strmovsi_rex_1"
16144 [(set (mem:SI (match_operand:DI 2 "register_operand" "0"))
16145 (mem:SI (match_operand:DI 3 "register_operand" "1")))
16146 (set (match_operand:DI 0 "register_operand" "=D")
16147 (plus:DI (match_dup 2)
16149 (set (match_operand:DI 1 "register_operand" "=S")
16150 (plus:DI (match_dup 3)
16153 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16155 [(set_attr "type" "str")
16156 (set_attr "mode" "SI")
16157 (set_attr "memory" "both")])
16159 (define_insn "strmovhi_1"
16160 [(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
16161 (mem:HI (match_operand:SI 3 "register_operand" "1")))
16162 (set (match_operand:SI 0 "register_operand" "=D")
16163 (plus:SI (match_dup 2)
16165 (set (match_operand:SI 1 "register_operand" "=S")
16166 (plus:SI (match_dup 3)
16169 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16171 [(set_attr "type" "str")
16172 (set_attr "memory" "both")
16173 (set_attr "mode" "HI")])
16175 (define_insn "strmovhi_rex_1"
16176 [(set (mem:HI (match_operand:DI 2 "register_operand" "0"))
16177 (mem:HI (match_operand:DI 3 "register_operand" "1")))
16178 (set (match_operand:DI 0 "register_operand" "=D")
16179 (plus:DI (match_dup 2)
16181 (set (match_operand:DI 1 "register_operand" "=S")
16182 (plus:DI (match_dup 3)
16185 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16187 [(set_attr "type" "str")
16188 (set_attr "memory" "both")
16189 (set_attr "mode" "HI")])
16191 (define_insn "strmovqi_1"
16192 [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
16193 (mem:QI (match_operand:SI 3 "register_operand" "1")))
16194 (set (match_operand:SI 0 "register_operand" "=D")
16195 (plus:SI (match_dup 2)
16197 (set (match_operand:SI 1 "register_operand" "=S")
16198 (plus:SI (match_dup 3)
16201 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16203 [(set_attr "type" "str")
16204 (set_attr "memory" "both")
16205 (set_attr "mode" "QI")])
16207 (define_insn "strmovqi_rex_1"
16208 [(set (mem:QI (match_operand:DI 2 "register_operand" "0"))
16209 (mem:QI (match_operand:DI 3 "register_operand" "1")))
16210 (set (match_operand:DI 0 "register_operand" "=D")
16211 (plus:DI (match_dup 2)
16213 (set (match_operand:DI 1 "register_operand" "=S")
16214 (plus:DI (match_dup 3)
16217 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16219 [(set_attr "type" "str")
16220 (set_attr "memory" "both")
16221 (set_attr "mode" "QI")])
16223 (define_insn "rep_movdi_rex64"
16224 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16225 (set (match_operand:DI 0 "register_operand" "=D")
16226 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16228 (match_operand:DI 3 "register_operand" "0")))
16229 (set (match_operand:DI 1 "register_operand" "=S")
16230 (plus:DI (ashift:DI (match_dup 5) (const_int 3))
16231 (match_operand:DI 4 "register_operand" "1")))
16232 (set (mem:BLK (match_dup 3))
16233 (mem:BLK (match_dup 4)))
16234 (use (match_dup 5))
16237 "{rep\;movsq|rep movsq}"
16238 [(set_attr "type" "str")
16239 (set_attr "prefix_rep" "1")
16240 (set_attr "memory" "both")
16241 (set_attr "mode" "DI")])
16243 (define_insn "rep_movsi"
16244 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16245 (set (match_operand:SI 0 "register_operand" "=D")
16246 (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
16248 (match_operand:SI 3 "register_operand" "0")))
16249 (set (match_operand:SI 1 "register_operand" "=S")
16250 (plus:SI (ashift:SI (match_dup 5) (const_int 2))
16251 (match_operand:SI 4 "register_operand" "1")))
16252 (set (mem:BLK (match_dup 3))
16253 (mem:BLK (match_dup 4)))
16254 (use (match_dup 5))
16257 "{rep\;movsl|rep movsd}"
16258 [(set_attr "type" "str")
16259 (set_attr "prefix_rep" "1")
16260 (set_attr "memory" "both")
16261 (set_attr "mode" "SI")])
16263 (define_insn "rep_movsi_rex64"
16264 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16265 (set (match_operand:DI 0 "register_operand" "=D")
16266 (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
16268 (match_operand:DI 3 "register_operand" "0")))
16269 (set (match_operand:DI 1 "register_operand" "=S")
16270 (plus:DI (ashift:DI (match_dup 5) (const_int 2))
16271 (match_operand:DI 4 "register_operand" "1")))
16272 (set (mem:BLK (match_dup 3))
16273 (mem:BLK (match_dup 4)))
16274 (use (match_dup 5))
16277 "{rep\;movsl|rep movsd}"
16278 [(set_attr "type" "str")
16279 (set_attr "prefix_rep" "1")
16280 (set_attr "memory" "both")
16281 (set_attr "mode" "SI")])
16283 (define_insn "rep_movqi"
16284 [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
16285 (set (match_operand:SI 0 "register_operand" "=D")
16286 (plus:SI (match_operand:SI 3 "register_operand" "0")
16287 (match_operand:SI 5 "register_operand" "2")))
16288 (set (match_operand:SI 1 "register_operand" "=S")
16289 (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
16290 (set (mem:BLK (match_dup 3))
16291 (mem:BLK (match_dup 4)))
16292 (use (match_dup 5))
16295 "{rep\;movsb|rep movsb}"
16296 [(set_attr "type" "str")
16297 (set_attr "prefix_rep" "1")
16298 (set_attr "memory" "both")
16299 (set_attr "mode" "SI")])
16301 (define_insn "rep_movqi_rex64"
16302 [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
16303 (set (match_operand:DI 0 "register_operand" "=D")
16304 (plus:DI (match_operand:DI 3 "register_operand" "0")
16305 (match_operand:DI 5 "register_operand" "2")))
16306 (set (match_operand:DI 1 "register_operand" "=S")
16307 (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
16308 (set (mem:BLK (match_dup 3))
16309 (mem:BLK (match_dup 4)))
16310 (use (match_dup 5))
16313 "{rep\;movsb|rep movsb}"
16314 [(set_attr "type" "str")
16315 (set_attr "prefix_rep" "1")
16316 (set_attr "memory" "both")
16317 (set_attr "mode" "SI")])
16319 (define_expand "clrstrsi"
16320 [(use (match_operand:BLK 0 "memory_operand" ""))
16321 (use (match_operand:SI 1 "nonmemory_operand" ""))
16322 (use (match_operand 2 "const_int_operand" ""))]
16325 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
16331 (define_expand "clrstrdi"
16332 [(use (match_operand:BLK 0 "memory_operand" ""))
16333 (use (match_operand:DI 1 "nonmemory_operand" ""))
16334 (use (match_operand 2 "const_int_operand" ""))]
16337 if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
16343 ;; Most CPUs don't like single string operations
16344 ;; Handle this case here to simplify previous expander.
16346 (define_expand "strsetdi_rex64"
16347 [(set (mem:DI (match_operand:DI 0 "register_operand" ""))
16348 (match_operand:DI 1 "register_operand" ""))
16349 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 8)))
16350 (clobber (reg:CC 17))])]
16353 if (TARGET_SINGLE_STRINGOP || optimize_size)
16355 emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
16360 (define_expand "strsetsi"
16361 [(set (mem:SI (match_operand:SI 0 "register_operand" ""))
16362 (match_operand:SI 1 "register_operand" ""))
16363 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 4)))
16364 (clobber (reg:CC 17))])]
16369 emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
16372 else if (TARGET_SINGLE_STRINGOP || optimize_size)
16374 emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
16379 (define_expand "strsetsi_rex64"
16380 [(set (mem:SI (match_operand:DI 0 "register_operand" ""))
16381 (match_operand:SI 1 "register_operand" ""))
16382 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 4)))
16383 (clobber (reg:CC 17))])]
16386 if (TARGET_SINGLE_STRINGOP || optimize_size)
16388 emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
16393 (define_expand "strsethi"
16394 [(set (mem:HI (match_operand:SI 0 "register_operand" ""))
16395 (match_operand:HI 1 "register_operand" ""))
16396 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 2)))
16397 (clobber (reg:CC 17))])]
16402 emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
16405 else if (TARGET_SINGLE_STRINGOP || optimize_size)
16407 emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
16412 (define_expand "strsethi_rex64"
16413 [(set (mem:HI (match_operand:DI 0 "register_operand" ""))
16414 (match_operand:HI 1 "register_operand" ""))
16415 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 2)))
16416 (clobber (reg:CC 17))])]
16419 if (TARGET_SINGLE_STRINGOP || optimize_size)
16421 emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
16426 (define_expand "strsetqi"
16427 [(set (mem:QI (match_operand:SI 0 "register_operand" ""))
16428 (match_operand:QI 1 "register_operand" ""))
16429 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))
16430 (clobber (reg:CC 17))])]
16435 emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
16438 else if (TARGET_SINGLE_STRINGOP || optimize_size)
16440 emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
16445 (define_expand "strsetqi_rex64"
16446 [(set (mem:QI (match_operand:DI 0 "register_operand" ""))
16447 (match_operand:QI 1 "register_operand" ""))
16448 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (const_int 1)))
16449 (clobber (reg:CC 17))])]
16452 if (TARGET_SINGLE_STRINGOP || optimize_size)
16454 emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
16459 (define_insn "strsetdi_rex_1"
16460 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
16461 (match_operand:SI 2 "register_operand" "a"))
16462 (set (match_operand:DI 0 "register_operand" "=D")
16463 (plus:DI (match_dup 1)
16466 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16468 [(set_attr "type" "str")
16469 (set_attr "memory" "store")
16470 (set_attr "mode" "DI")])
16472 (define_insn "strsetsi_1"
16473 [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
16474 (match_operand:SI 2 "register_operand" "a"))
16475 (set (match_operand:SI 0 "register_operand" "=D")
16476 (plus:SI (match_dup 1)
16479 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16481 [(set_attr "type" "str")
16482 (set_attr "memory" "store")
16483 (set_attr "mode" "SI")])
16485 (define_insn "strsetsi_rex_1"
16486 [(set (mem:SI (match_operand:DI 1 "register_operand" "0"))
16487 (match_operand:SI 2 "register_operand" "a"))
16488 (set (match_operand:DI 0 "register_operand" "=D")
16489 (plus:DI (match_dup 1)
16492 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16494 [(set_attr "type" "str")
16495 (set_attr "memory" "store")
16496 (set_attr "mode" "SI")])
16498 (define_insn "strsethi_1"
16499 [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
16500 (match_operand:HI 2 "register_operand" "a"))
16501 (set (match_operand:SI 0 "register_operand" "=D")
16502 (plus:SI (match_dup 1)
16505 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16507 [(set_attr "type" "str")
16508 (set_attr "memory" "store")
16509 (set_attr "mode" "HI")])
16511 (define_insn "strsethi_rex_1"
16512 [(set (mem:HI (match_operand:DI 1 "register_operand" "0"))
16513 (match_operand:HI 2 "register_operand" "a"))
16514 (set (match_operand:DI 0 "register_operand" "=D")
16515 (plus:DI (match_dup 1)
16518 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16520 [(set_attr "type" "str")
16521 (set_attr "memory" "store")
16522 (set_attr "mode" "HI")])
16524 (define_insn "strsetqi_1"
16525 [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
16526 (match_operand:QI 2 "register_operand" "a"))
16527 (set (match_operand:SI 0 "register_operand" "=D")
16528 (plus:SI (match_dup 1)
16531 "!TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16533 [(set_attr "type" "str")
16534 (set_attr "memory" "store")
16535 (set_attr "mode" "QI")])
16537 (define_insn "strsetqi_rex_1"
16538 [(set (mem:QI (match_operand:DI 1 "register_operand" "0"))
16539 (match_operand:QI 2 "register_operand" "a"))
16540 (set (match_operand:DI 0 "register_operand" "=D")
16541 (plus:DI (match_dup 1)
16544 "TARGET_64BIT && (TARGET_SINGLE_STRINGOP || optimize_size)"
16546 [(set_attr "type" "str")
16547 (set_attr "memory" "store")
16548 (set_attr "mode" "QI")])
16550 (define_insn "rep_stosdi_rex64"
16551 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16552 (set (match_operand:DI 0 "register_operand" "=D")
16553 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16555 (match_operand:DI 3 "register_operand" "0")))
16556 (set (mem:BLK (match_dup 3))
16558 (use (match_operand:DI 2 "register_operand" "a"))
16559 (use (match_dup 4))
16562 "{rep\;stosq|rep stosq}"
16563 [(set_attr "type" "str")
16564 (set_attr "prefix_rep" "1")
16565 (set_attr "memory" "store")
16566 (set_attr "mode" "DI")])
16568 (define_insn "rep_stossi"
16569 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
16570 (set (match_operand:SI 0 "register_operand" "=D")
16571 (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
16573 (match_operand:SI 3 "register_operand" "0")))
16574 (set (mem:BLK (match_dup 3))
16576 (use (match_operand:SI 2 "register_operand" "a"))
16577 (use (match_dup 4))
16580 "{rep\;stosl|rep stosd}"
16581 [(set_attr "type" "str")
16582 (set_attr "prefix_rep" "1")
16583 (set_attr "memory" "store")
16584 (set_attr "mode" "SI")])
16586 (define_insn "rep_stossi_rex64"
16587 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16588 (set (match_operand:DI 0 "register_operand" "=D")
16589 (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
16591 (match_operand:DI 3 "register_operand" "0")))
16592 (set (mem:BLK (match_dup 3))
16594 (use (match_operand:SI 2 "register_operand" "a"))
16595 (use (match_dup 4))
16598 "{rep\;stosl|rep stosd}"
16599 [(set_attr "type" "str")
16600 (set_attr "prefix_rep" "1")
16601 (set_attr "memory" "store")
16602 (set_attr "mode" "SI")])
16604 (define_insn "rep_stosqi"
16605 [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
16606 (set (match_operand:SI 0 "register_operand" "=D")
16607 (plus:SI (match_operand:SI 3 "register_operand" "0")
16608 (match_operand:SI 4 "register_operand" "1")))
16609 (set (mem:BLK (match_dup 3))
16611 (use (match_operand:QI 2 "register_operand" "a"))
16612 (use (match_dup 4))
16615 "{rep\;stosb|rep stosb}"
16616 [(set_attr "type" "str")
16617 (set_attr "prefix_rep" "1")
16618 (set_attr "memory" "store")
16619 (set_attr "mode" "QI")])
16621 (define_insn "rep_stosqi_rex64"
16622 [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
16623 (set (match_operand:DI 0 "register_operand" "=D")
16624 (plus:DI (match_operand:DI 3 "register_operand" "0")
16625 (match_operand:DI 4 "register_operand" "1")))
16626 (set (mem:BLK (match_dup 3))
16628 (use (match_operand:QI 2 "register_operand" "a"))
16629 (use (match_dup 4))
16632 "{rep\;stosb|rep stosb}"
16633 [(set_attr "type" "str")
16634 (set_attr "prefix_rep" "1")
16635 (set_attr "memory" "store")
16636 (set_attr "mode" "QI")])
16638 (define_expand "cmpstrsi"
16639 [(set (match_operand:SI 0 "register_operand" "")
16640 (compare:SI (match_operand:BLK 1 "general_operand" "")
16641 (match_operand:BLK 2 "general_operand" "")))
16642 (use (match_operand 3 "general_operand" ""))
16643 (use (match_operand 4 "immediate_operand" ""))]
16646 rtx addr1, addr2, out, outlow, count, countreg, align;
16648 /* Can't use this if the user has appropriated esi or edi. */
16649 if (global_regs[4] || global_regs[5])
16653 if (GET_CODE (out) != REG)
16654 out = gen_reg_rtx (SImode);
16656 addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
16657 addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
16659 count = operands[3];
16660 countreg = ix86_zero_extend_to_Pmode (count);
16662 /* %%% Iff we are testing strict equality, we can use known alignment
16663 to good advantage. This may be possible with combine, particularly
16664 once cc0 is dead. */
16665 align = operands[4];
16667 emit_insn (gen_cld ());
16668 if (GET_CODE (count) == CONST_INT)
16670 if (INTVAL (count) == 0)
16672 emit_move_insn (operands[0], const0_rtx);
16676 emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
16677 addr1, addr2, countreg));
16679 emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
16680 addr1, addr2, countreg));
16686 emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
16687 emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
16688 addr1, addr2, countreg));
16692 emit_insn (gen_cmpsi_1 (countreg, countreg));
16693 emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
16694 addr1, addr2, countreg));
16698 outlow = gen_lowpart (QImode, out);
16699 emit_insn (gen_cmpintqi (outlow));
16700 emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
16702 if (operands[0] != out)
16703 emit_move_insn (operands[0], out);
16708 ;; Produce a tri-state integer (-1, 0, 1) from condition codes.
16710 (define_expand "cmpintqi"
16711 [(set (match_dup 1)
16712 (gtu:QI (reg:CC 17) (const_int 0)))
16714 (ltu:QI (reg:CC 17) (const_int 0)))
16715 (parallel [(set (match_operand:QI 0 "register_operand" "")
16716 (minus:QI (match_dup 1)
16718 (clobber (reg:CC 17))])]
16720 "operands[1] = gen_reg_rtx (QImode);
16721 operands[2] = gen_reg_rtx (QImode);")
16723 ;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
16724 ;; zero. Emit extra code to make sure that a zero-length compare is EQ.
16726 (define_insn "cmpstrqi_nz_1"
16728 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16729 (mem:BLK (match_operand:SI 5 "register_operand" "1"))))
16730 (use (match_operand:SI 6 "register_operand" "2"))
16731 (use (match_operand:SI 3 "immediate_operand" "i"))
16733 (clobber (match_operand:SI 0 "register_operand" "=S"))
16734 (clobber (match_operand:SI 1 "register_operand" "=D"))
16735 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16738 [(set_attr "type" "str")
16739 (set_attr "mode" "QI")
16740 (set_attr "prefix_rep" "1")])
16742 (define_insn "cmpstrqi_nz_rex_1"
16744 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16745 (mem:BLK (match_operand:DI 5 "register_operand" "1"))))
16746 (use (match_operand:DI 6 "register_operand" "2"))
16747 (use (match_operand:SI 3 "immediate_operand" "i"))
16749 (clobber (match_operand:DI 0 "register_operand" "=S"))
16750 (clobber (match_operand:DI 1 "register_operand" "=D"))
16751 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16754 [(set_attr "type" "str")
16755 (set_attr "mode" "QI")
16756 (set_attr "prefix_rep" "1")])
16758 ;; The same, but the count is not known to not be zero.
16760 (define_insn "cmpstrqi_1"
16762 (if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
16764 (compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
16765 (mem:BLK (match_operand:SI 5 "register_operand" "1")))
16767 (use (match_operand:SI 3 "immediate_operand" "i"))
16770 (clobber (match_operand:SI 0 "register_operand" "=S"))
16771 (clobber (match_operand:SI 1 "register_operand" "=D"))
16772 (clobber (match_operand:SI 2 "register_operand" "=c"))]
16775 [(set_attr "type" "str")
16776 (set_attr "mode" "QI")
16777 (set_attr "prefix_rep" "1")])
16779 (define_insn "cmpstrqi_rex_1"
16781 (if_then_else:CC (ne (match_operand:DI 6 "register_operand" "2")
16783 (compare:CC (mem:BLK (match_operand:DI 4 "register_operand" "0"))
16784 (mem:BLK (match_operand:DI 5 "register_operand" "1")))
16786 (use (match_operand:SI 3 "immediate_operand" "i"))
16789 (clobber (match_operand:DI 0 "register_operand" "=S"))
16790 (clobber (match_operand:DI 1 "register_operand" "=D"))
16791 (clobber (match_operand:DI 2 "register_operand" "=c"))]
16794 [(set_attr "type" "str")
16795 (set_attr "mode" "QI")
16796 (set_attr "prefix_rep" "1")])
16798 (define_expand "strlensi"
16799 [(set (match_operand:SI 0 "register_operand" "")
16800 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
16801 (match_operand:QI 2 "immediate_operand" "")
16802 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16805 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16811 (define_expand "strlendi"
16812 [(set (match_operand:DI 0 "register_operand" "")
16813 (unspec:DI [(match_operand:BLK 1 "general_operand" "")
16814 (match_operand:QI 2 "immediate_operand" "")
16815 (match_operand 3 "immediate_operand" "")] UNSPEC_SCAS))]
16818 if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
16824 (define_insn "strlenqi_1"
16825 [(set (match_operand:SI 0 "register_operand" "=&c")
16826 (unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
16827 (match_operand:QI 2 "register_operand" "a")
16828 (match_operand:SI 3 "immediate_operand" "i")
16829 (match_operand:SI 4 "register_operand" "0")] UNSPEC_SCAS))
16831 (clobber (match_operand:SI 1 "register_operand" "=D"))
16832 (clobber (reg:CC 17))]
16835 [(set_attr "type" "str")
16836 (set_attr "mode" "QI")
16837 (set_attr "prefix_rep" "1")])
16839 (define_insn "strlenqi_rex_1"
16840 [(set (match_operand:DI 0 "register_operand" "=&c")
16841 (unspec:DI [(mem:BLK (match_operand:DI 5 "register_operand" "1"))
16842 (match_operand:QI 2 "register_operand" "a")
16843 (match_operand:DI 3 "immediate_operand" "i")
16844 (match_operand:DI 4 "register_operand" "0")] UNSPEC_SCAS))
16846 (clobber (match_operand:DI 1 "register_operand" "=D"))
16847 (clobber (reg:CC 17))]
16850 [(set_attr "type" "str")
16851 (set_attr "mode" "QI")
16852 (set_attr "prefix_rep" "1")])
16854 ;; Peephole optimizations to clean up after cmpstr*. This should be
16855 ;; handled in combine, but it is not currently up to the task.
16856 ;; When used for their truth value, the cmpstr* expanders generate
16865 ;; The intermediate three instructions are unnecessary.
16867 ;; This one handles cmpstr*_nz_1...
16871 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16872 (mem:BLK (match_operand 5 "register_operand" ""))))
16873 (use (match_operand 6 "register_operand" ""))
16874 (use (match_operand:SI 3 "immediate_operand" ""))
16876 (clobber (match_operand 0 "register_operand" ""))
16877 (clobber (match_operand 1 "register_operand" ""))
16878 (clobber (match_operand 2 "register_operand" ""))])
16879 (set (match_operand:QI 7 "register_operand" "")
16880 (gtu:QI (reg:CC 17) (const_int 0)))
16881 (set (match_operand:QI 8 "register_operand" "")
16882 (ltu:QI (reg:CC 17) (const_int 0)))
16884 (compare (match_dup 7) (match_dup 8)))
16886 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16889 (compare:CC (mem:BLK (match_dup 4))
16890 (mem:BLK (match_dup 5))))
16891 (use (match_dup 6))
16892 (use (match_dup 3))
16894 (clobber (match_dup 0))
16895 (clobber (match_dup 1))
16896 (clobber (match_dup 2))])]
16899 ;; ...and this one handles cmpstr*_1.
16903 (if_then_else:CC (ne (match_operand 6 "register_operand" "")
16905 (compare:CC (mem:BLK (match_operand 4 "register_operand" ""))
16906 (mem:BLK (match_operand 5 "register_operand" "")))
16908 (use (match_operand:SI 3 "immediate_operand" ""))
16911 (clobber (match_operand 0 "register_operand" ""))
16912 (clobber (match_operand 1 "register_operand" ""))
16913 (clobber (match_operand 2 "register_operand" ""))])
16914 (set (match_operand:QI 7 "register_operand" "")
16915 (gtu:QI (reg:CC 17) (const_int 0)))
16916 (set (match_operand:QI 8 "register_operand" "")
16917 (ltu:QI (reg:CC 17) (const_int 0)))
16919 (compare (match_dup 7) (match_dup 8)))
16921 "peep2_reg_dead_p (4, operands[7]) && peep2_reg_dead_p (4, operands[8])"
16924 (if_then_else:CC (ne (match_dup 6)
16926 (compare:CC (mem:BLK (match_dup 4))
16927 (mem:BLK (match_dup 5)))
16929 (use (match_dup 3))
16932 (clobber (match_dup 0))
16933 (clobber (match_dup 1))
16934 (clobber (match_dup 2))])]
16939 ;; Conditional move instructions.
16941 (define_expand "movdicc"
16942 [(set (match_operand:DI 0 "register_operand" "")
16943 (if_then_else:DI (match_operand 1 "comparison_operator" "")
16944 (match_operand:DI 2 "general_operand" "")
16945 (match_operand:DI 3 "general_operand" "")))]
16947 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16949 (define_insn "x86_movdicc_0_m1_rex64"
16950 [(set (match_operand:DI 0 "register_operand" "=r")
16951 (if_then_else:DI (match_operand 1 "ix86_carry_flag_operator" "")
16954 (clobber (reg:CC 17))]
16957 ; Since we don't have the proper number of operands for an alu insn,
16958 ; fill in all the blanks.
16959 [(set_attr "type" "alu")
16960 (set_attr "pent_pair" "pu")
16961 (set_attr "memory" "none")
16962 (set_attr "imm_disp" "false")
16963 (set_attr "mode" "DI")
16964 (set_attr "length_immediate" "0")])
16966 (define_insn "movdicc_c_rex64"
16967 [(set (match_operand:DI 0 "register_operand" "=r,r")
16968 (if_then_else:DI (match_operator 1 "ix86_comparison_operator"
16969 [(reg 17) (const_int 0)])
16970 (match_operand:DI 2 "nonimmediate_operand" "rm,0")
16971 (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
16972 "TARGET_64BIT && TARGET_CMOVE
16973 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
16975 cmov%O2%C1\t{%2, %0|%0, %2}
16976 cmov%O2%c1\t{%3, %0|%0, %3}"
16977 [(set_attr "type" "icmov")
16978 (set_attr "mode" "DI")])
16980 (define_expand "movsicc"
16981 [(set (match_operand:SI 0 "register_operand" "")
16982 (if_then_else:SI (match_operand 1 "comparison_operator" "")
16983 (match_operand:SI 2 "general_operand" "")
16984 (match_operand:SI 3 "general_operand" "")))]
16986 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
16988 ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing
16989 ;; the register first winds up with `sbbl $0,reg', which is also weird.
16990 ;; So just document what we're doing explicitly.
16992 (define_insn "x86_movsicc_0_m1"
16993 [(set (match_operand:SI 0 "register_operand" "=r")
16994 (if_then_else:SI (match_operand 1 "ix86_carry_flag_operator" "")
16997 (clobber (reg:CC 17))]
17000 ; Since we don't have the proper number of operands for an alu insn,
17001 ; fill in all the blanks.
17002 [(set_attr "type" "alu")
17003 (set_attr "pent_pair" "pu")
17004 (set_attr "memory" "none")
17005 (set_attr "imm_disp" "false")
17006 (set_attr "mode" "SI")
17007 (set_attr "length_immediate" "0")])
17009 (define_insn "*movsicc_noc"
17010 [(set (match_operand:SI 0 "register_operand" "=r,r")
17011 (if_then_else:SI (match_operator 1 "ix86_comparison_operator"
17012 [(reg 17) (const_int 0)])
17013 (match_operand:SI 2 "nonimmediate_operand" "rm,0")
17014 (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
17016 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17018 cmov%O2%C1\t{%2, %0|%0, %2}
17019 cmov%O2%c1\t{%3, %0|%0, %3}"
17020 [(set_attr "type" "icmov")
17021 (set_attr "mode" "SI")])
17023 (define_expand "movhicc"
17024 [(set (match_operand:HI 0 "register_operand" "")
17025 (if_then_else:HI (match_operand 1 "comparison_operator" "")
17026 (match_operand:HI 2 "general_operand" "")
17027 (match_operand:HI 3 "general_operand" "")))]
17028 "TARGET_HIMODE_MATH"
17029 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17031 (define_insn "*movhicc_noc"
17032 [(set (match_operand:HI 0 "register_operand" "=r,r")
17033 (if_then_else:HI (match_operator 1 "ix86_comparison_operator"
17034 [(reg 17) (const_int 0)])
17035 (match_operand:HI 2 "nonimmediate_operand" "rm,0")
17036 (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
17038 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17040 cmov%O2%C1\t{%2, %0|%0, %2}
17041 cmov%O2%c1\t{%3, %0|%0, %3}"
17042 [(set_attr "type" "icmov")
17043 (set_attr "mode" "HI")])
17045 (define_expand "movqicc"
17046 [(set (match_operand:QI 0 "register_operand" "")
17047 (if_then_else:QI (match_operand 1 "comparison_operator" "")
17048 (match_operand:QI 2 "general_operand" "")
17049 (match_operand:QI 3 "general_operand" "")))]
17050 "TARGET_QIMODE_MATH"
17051 "if (!ix86_expand_int_movcc (operands)) FAIL; DONE;")
17053 (define_insn_and_split "*movqicc_noc"
17054 [(set (match_operand:QI 0 "register_operand" "=r,r")
17055 (if_then_else:QI (match_operator 1 "ix86_comparison_operator"
17056 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17057 (match_operand:QI 2 "register_operand" "r,0")
17058 (match_operand:QI 3 "register_operand" "0,r")))]
17059 "TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
17061 "&& reload_completed"
17062 [(set (match_dup 0)
17063 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17066 "operands[0] = gen_lowpart (SImode, operands[0]);
17067 operands[2] = gen_lowpart (SImode, operands[2]);
17068 operands[3] = gen_lowpart (SImode, operands[3]);"
17069 [(set_attr "type" "icmov")
17070 (set_attr "mode" "SI")])
17072 (define_expand "movsfcc"
17073 [(set (match_operand:SF 0 "register_operand" "")
17074 (if_then_else:SF (match_operand 1 "comparison_operator" "")
17075 (match_operand:SF 2 "register_operand" "")
17076 (match_operand:SF 3 "register_operand" "")))]
17078 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17080 (define_insn "*movsfcc_1"
17081 [(set (match_operand:SF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17082 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17083 [(reg 17) (const_int 0)])
17084 (match_operand:SF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17085 (match_operand:SF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17087 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17089 fcmov%F1\t{%2, %0|%0, %2}
17090 fcmov%f1\t{%3, %0|%0, %3}
17091 cmov%O2%C1\t{%2, %0|%0, %2}
17092 cmov%O2%c1\t{%3, %0|%0, %3}"
17093 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17094 (set_attr "mode" "SF,SF,SI,SI")])
17096 (define_expand "movdfcc"
17097 [(set (match_operand:DF 0 "register_operand" "")
17098 (if_then_else:DF (match_operand 1 "comparison_operator" "")
17099 (match_operand:DF 2 "register_operand" "")
17100 (match_operand:DF 3 "register_operand" "")))]
17102 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17104 (define_insn "*movdfcc_1"
17105 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,&r#f,&r#f")
17106 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17107 [(reg 17) (const_int 0)])
17108 (match_operand:DF 2 "nonimmediate_operand" "f#r,0,rm#f,0")
17109 (match_operand:DF 3 "nonimmediate_operand" "0,f#r,0,rm#f")))]
17110 "!TARGET_64BIT && TARGET_CMOVE
17111 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17113 fcmov%F1\t{%2, %0|%0, %2}
17114 fcmov%f1\t{%3, %0|%0, %3}
17117 [(set_attr "type" "fcmov,fcmov,multi,multi")
17118 (set_attr "mode" "DF")])
17120 (define_insn "*movdfcc_1_rex64"
17121 [(set (match_operand:DF 0 "register_operand" "=f#r,f#r,r#f,r#f")
17122 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17123 [(reg 17) (const_int 0)])
17124 (match_operand:DF 2 "nonimmediate_operand" "f#r,0#r,rm#f,0#f")
17125 (match_operand:DF 3 "nonimmediate_operand" "0#r,f#r,0#f,rm#f")))]
17126 "TARGET_64BIT && TARGET_CMOVE
17127 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17129 fcmov%F1\t{%2, %0|%0, %2}
17130 fcmov%f1\t{%3, %0|%0, %3}
17131 cmov%O2%C1\t{%2, %0|%0, %2}
17132 cmov%O2%c1\t{%3, %0|%0, %3}"
17133 [(set_attr "type" "fcmov,fcmov,icmov,icmov")
17134 (set_attr "mode" "DF")])
17137 [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
17138 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17139 [(match_operand 4 "flags_reg_operand" "") (const_int 0)])
17140 (match_operand:DF 2 "nonimmediate_operand" "")
17141 (match_operand:DF 3 "nonimmediate_operand" "")))]
17142 "!TARGET_64BIT && reload_completed"
17143 [(set (match_dup 2)
17144 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17148 (if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
17151 "split_di (operands+2, 1, operands+5, operands+6);
17152 split_di (operands+3, 1, operands+7, operands+8);
17153 split_di (operands, 1, operands+2, operands+3);")
17155 (define_expand "movxfcc"
17156 [(set (match_operand:XF 0 "register_operand" "")
17157 (if_then_else:XF (match_operand 1 "comparison_operator" "")
17158 (match_operand:XF 2 "register_operand" "")
17159 (match_operand:XF 3 "register_operand" "")))]
17160 "!TARGET_128BIT_LONG_DOUBLE && TARGET_CMOVE"
17161 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17163 (define_expand "movtfcc"
17164 [(set (match_operand:TF 0 "register_operand" "")
17165 (if_then_else:TF (match_operand 1 "comparison_operator" "")
17166 (match_operand:TF 2 "register_operand" "")
17167 (match_operand:TF 3 "register_operand" "")))]
17169 "if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;")
17171 (define_insn "*movxfcc_1"
17172 [(set (match_operand:XF 0 "register_operand" "=f,f")
17173 (if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
17174 [(reg 17) (const_int 0)])
17175 (match_operand:XF 2 "register_operand" "f,0")
17176 (match_operand:XF 3 "register_operand" "0,f")))]
17177 "!TARGET_128BIT_LONG_DOUBLE && TARGET_CMOVE"
17179 fcmov%F1\t{%2, %0|%0, %2}
17180 fcmov%f1\t{%3, %0|%0, %3}"
17181 [(set_attr "type" "fcmov")
17182 (set_attr "mode" "XF")])
17184 (define_insn "*movtfcc_1"
17185 [(set (match_operand:TF 0 "register_operand" "=f,f")
17186 (if_then_else:TF (match_operator 1 "fcmov_comparison_operator"
17187 [(reg 17) (const_int 0)])
17188 (match_operand:TF 2 "register_operand" "f,0")
17189 (match_operand:TF 3 "register_operand" "0,f")))]
17192 fcmov%F1\t{%2, %0|%0, %2}
17193 fcmov%f1\t{%3, %0|%0, %3}"
17194 [(set_attr "type" "fcmov")
17195 (set_attr "mode" "XF")])
17197 (define_expand "minsf3"
17199 (set (match_operand:SF 0 "register_operand" "")
17200 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17201 (match_operand:SF 2 "nonimmediate_operand" ""))
17204 (clobber (reg:CC 17))])]
17208 (define_insn "*minsf"
17209 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17210 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0,0,f#x")
17211 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17214 (clobber (reg:CC 17))]
17215 "TARGET_SSE && TARGET_IEEE_FP"
17218 (define_insn "*minsf_nonieee"
17219 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17220 (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17221 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17224 (clobber (reg:CC 17))]
17225 "TARGET_SSE && !TARGET_IEEE_FP
17226 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17230 [(set (match_operand:SF 0 "register_operand" "")
17231 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17232 (match_operand:SF 2 "nonimmediate_operand" ""))
17233 (match_operand:SF 3 "register_operand" "")
17234 (match_operand:SF 4 "nonimmediate_operand" "")))
17235 (clobber (reg:CC 17))]
17236 "SSE_REG_P (operands[0]) && reload_completed
17237 && ((operands_match_p (operands[1], operands[3])
17238 && operands_match_p (operands[2], operands[4]))
17239 || (operands_match_p (operands[1], operands[4])
17240 && operands_match_p (operands[2], operands[3])))"
17241 [(set (match_dup 0)
17242 (if_then_else:SF (lt (match_dup 1)
17247 ;; Conditional addition patterns
17248 (define_expand "addqicc"
17249 [(match_operand:QI 0 "register_operand" "")
17250 (match_operand 1 "comparison_operator" "")
17251 (match_operand:QI 2 "register_operand" "")
17252 (match_operand:QI 3 "const_int_operand" "")]
17254 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17256 (define_expand "addhicc"
17257 [(match_operand:HI 0 "register_operand" "")
17258 (match_operand 1 "comparison_operator" "")
17259 (match_operand:HI 2 "register_operand" "")
17260 (match_operand:HI 3 "const_int_operand" "")]
17262 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17264 (define_expand "addsicc"
17265 [(match_operand:SI 0 "register_operand" "")
17266 (match_operand 1 "comparison_operator" "")
17267 (match_operand:SI 2 "register_operand" "")
17268 (match_operand:SI 3 "const_int_operand" "")]
17270 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17272 (define_expand "adddicc"
17273 [(match_operand:DI 0 "register_operand" "")
17274 (match_operand 1 "comparison_operator" "")
17275 (match_operand:DI 2 "register_operand" "")
17276 (match_operand:DI 3 "const_int_operand" "")]
17278 "if (!ix86_expand_int_addcc (operands)) FAIL; DONE;")
17280 ;; We can't represent the LT test directly. Do this by swapping the operands.
17283 [(set (match_operand:SF 0 "fp_register_operand" "")
17284 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "")
17285 (match_operand:SF 2 "register_operand" ""))
17286 (match_operand:SF 3 "register_operand" "")
17287 (match_operand:SF 4 "register_operand" "")))
17288 (clobber (reg:CC 17))]
17290 && ((operands_match_p (operands[1], operands[3])
17291 && operands_match_p (operands[2], operands[4]))
17292 || (operands_match_p (operands[1], operands[4])
17293 && operands_match_p (operands[2], operands[3])))"
17294 [(set (reg:CCFP 17)
17295 (compare:CCFP (match_dup 2)
17298 (if_then_else:SF (ge (reg:CCFP 17) (const_int 0))
17302 (define_insn "*minsf_sse"
17303 [(set (match_operand:SF 0 "register_operand" "=x")
17304 (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "0")
17305 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17308 "TARGET_SSE && reload_completed"
17309 "minss\t{%2, %0|%0, %2}"
17310 [(set_attr "type" "sse")
17311 (set_attr "mode" "SF")])
17313 (define_expand "mindf3"
17315 (set (match_operand:DF 0 "register_operand" "")
17316 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17317 (match_operand:DF 2 "nonimmediate_operand" ""))
17320 (clobber (reg:CC 17))])]
17321 "TARGET_SSE2 && TARGET_SSE_MATH"
17324 (define_insn "*mindf"
17325 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17326 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17327 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17330 (clobber (reg:CC 17))]
17331 "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
17334 (define_insn "*mindf_nonieee"
17335 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17336 (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17337 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17340 (clobber (reg:CC 17))]
17341 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17342 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17346 [(set (match_operand:DF 0 "register_operand" "")
17347 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17348 (match_operand:DF 2 "nonimmediate_operand" ""))
17349 (match_operand:DF 3 "register_operand" "")
17350 (match_operand:DF 4 "nonimmediate_operand" "")))
17351 (clobber (reg:CC 17))]
17352 "SSE_REG_P (operands[0]) && reload_completed
17353 && ((operands_match_p (operands[1], operands[3])
17354 && operands_match_p (operands[2], operands[4]))
17355 || (operands_match_p (operands[1], operands[4])
17356 && operands_match_p (operands[2], operands[3])))"
17357 [(set (match_dup 0)
17358 (if_then_else:DF (lt (match_dup 1)
17363 ;; We can't represent the LT test directly. Do this by swapping the operands.
17365 [(set (match_operand:DF 0 "fp_register_operand" "")
17366 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "")
17367 (match_operand:DF 2 "register_operand" ""))
17368 (match_operand:DF 3 "register_operand" "")
17369 (match_operand:DF 4 "register_operand" "")))
17370 (clobber (reg:CC 17))]
17372 && ((operands_match_p (operands[1], operands[3])
17373 && operands_match_p (operands[2], operands[4]))
17374 || (operands_match_p (operands[1], operands[4])
17375 && operands_match_p (operands[2], operands[3])))"
17376 [(set (reg:CCFP 17)
17377 (compare:CCFP (match_dup 2)
17380 (if_then_else:DF (ge (reg:CCFP 17) (const_int 0))
17384 (define_insn "*mindf_sse"
17385 [(set (match_operand:DF 0 "register_operand" "=Y")
17386 (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "0")
17387 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17390 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17391 "minsd\t{%2, %0|%0, %2}"
17392 [(set_attr "type" "sse")
17393 (set_attr "mode" "DF")])
17395 (define_expand "maxsf3"
17397 (set (match_operand:SF 0 "register_operand" "")
17398 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17399 (match_operand:SF 2 "nonimmediate_operand" ""))
17402 (clobber (reg:CC 17))])]
17406 (define_insn "*maxsf"
17407 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x,f#x")
17408 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0,0,f#x")
17409 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x,0"))
17412 (clobber (reg:CC 17))]
17413 "TARGET_SSE && TARGET_IEEE_FP"
17416 (define_insn "*maxsf_nonieee"
17417 [(set (match_operand:SF 0 "register_operand" "=x#f,f#x")
17418 (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0")
17419 (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x"))
17422 (clobber (reg:CC 17))]
17423 "TARGET_SSE && !TARGET_IEEE_FP
17424 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17428 [(set (match_operand:SF 0 "register_operand" "")
17429 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17430 (match_operand:SF 2 "nonimmediate_operand" ""))
17431 (match_operand:SF 3 "register_operand" "")
17432 (match_operand:SF 4 "nonimmediate_operand" "")))
17433 (clobber (reg:CC 17))]
17434 "SSE_REG_P (operands[0]) && reload_completed
17435 && ((operands_match_p (operands[1], operands[3])
17436 && operands_match_p (operands[2], operands[4]))
17437 || (operands_match_p (operands[1], operands[4])
17438 && operands_match_p (operands[2], operands[3])))"
17439 [(set (match_dup 0)
17440 (if_then_else:SF (gt (match_dup 1)
17446 [(set (match_operand:SF 0 "fp_register_operand" "")
17447 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "")
17448 (match_operand:SF 2 "register_operand" ""))
17449 (match_operand:SF 3 "register_operand" "")
17450 (match_operand:SF 4 "register_operand" "")))
17451 (clobber (reg:CC 17))]
17453 && ((operands_match_p (operands[1], operands[3])
17454 && operands_match_p (operands[2], operands[4]))
17455 || (operands_match_p (operands[1], operands[4])
17456 && operands_match_p (operands[2], operands[3])))"
17457 [(set (reg:CCFP 17)
17458 (compare:CCFP (match_dup 1)
17461 (if_then_else:SF (gt (reg:CCFP 17) (const_int 0))
17465 (define_insn "*maxsf_sse"
17466 [(set (match_operand:SF 0 "register_operand" "=x")
17467 (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "0")
17468 (match_operand:SF 2 "nonimmediate_operand" "xm"))
17471 "TARGET_SSE && reload_completed"
17472 "maxss\t{%2, %0|%0, %2}"
17473 [(set_attr "type" "sse")
17474 (set_attr "mode" "SF")])
17476 (define_expand "maxdf3"
17478 (set (match_operand:DF 0 "register_operand" "")
17479 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17480 (match_operand:DF 2 "nonimmediate_operand" ""))
17483 (clobber (reg:CC 17))])]
17484 "TARGET_SSE2 && TARGET_SSE_MATH"
17487 (define_insn "*maxdf"
17488 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y,f#Y")
17489 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0,0,f#Y")
17490 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y,0"))
17493 (clobber (reg:CC 17))]
17494 "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
17497 (define_insn "*maxdf_nonieee"
17498 [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y")
17499 (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0")
17500 (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y"))
17503 (clobber (reg:CC 17))]
17504 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP
17505 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
17509 [(set (match_operand:DF 0 "register_operand" "")
17510 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17511 (match_operand:DF 2 "nonimmediate_operand" ""))
17512 (match_operand:DF 3 "register_operand" "")
17513 (match_operand:DF 4 "nonimmediate_operand" "")))
17514 (clobber (reg:CC 17))]
17515 "SSE_REG_P (operands[0]) && reload_completed
17516 && ((operands_match_p (operands[1], operands[3])
17517 && operands_match_p (operands[2], operands[4]))
17518 || (operands_match_p (operands[1], operands[4])
17519 && operands_match_p (operands[2], operands[3])))"
17520 [(set (match_dup 0)
17521 (if_then_else:DF (gt (match_dup 1)
17527 [(set (match_operand:DF 0 "fp_register_operand" "")
17528 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "")
17529 (match_operand:DF 2 "register_operand" ""))
17530 (match_operand:DF 3 "register_operand" "")
17531 (match_operand:DF 4 "register_operand" "")))
17532 (clobber (reg:CC 17))]
17534 && ((operands_match_p (operands[1], operands[3])
17535 && operands_match_p (operands[2], operands[4]))
17536 || (operands_match_p (operands[1], operands[4])
17537 && operands_match_p (operands[2], operands[3])))"
17538 [(set (reg:CCFP 17)
17539 (compare:CCFP (match_dup 1)
17542 (if_then_else:DF (gt (reg:CCFP 17) (const_int 0))
17546 (define_insn "*maxdf_sse"
17547 [(set (match_operand:DF 0 "register_operand" "=Y")
17548 (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "0")
17549 (match_operand:DF 2 "nonimmediate_operand" "Ym"))
17552 "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
17553 "maxsd\t{%2, %0|%0, %2}"
17554 [(set_attr "type" "sse")
17555 (set_attr "mode" "DF")])
17557 ;; Misc patterns (?)
17559 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
17560 ;; Otherwise there will be nothing to keep
17562 ;; [(set (reg ebp) (reg esp))]
17563 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
17564 ;; (clobber (eflags)]
17565 ;; [(set (mem (plus (reg ebp) (const_int -160000))) (const_int 0))]
17567 ;; in proper program order.
17568 (define_expand "pro_epilogue_adjust_stack"
17569 [(parallel [(set (match_operand:SI 0 "register_operand" "=r,r")
17570 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
17571 (match_operand:SI 2 "immediate_operand" "i,i")))
17572 (clobber (reg:CC 17))
17573 (clobber (mem:BLK (scratch)))])]
17578 emit_insn (gen_pro_epilogue_adjust_stack_rex64
17579 (operands[0], operands[1], operands[2]));
17584 (define_insn "*pro_epilogue_adjust_stack_1"
17585 [(set (match_operand:SI 0 "register_operand" "=r,r")
17586 (plus:SI (match_operand:SI 1 "register_operand" "0,r")
17587 (match_operand:SI 2 "immediate_operand" "i,i")))
17588 (clobber (reg:CC 17))
17589 (clobber (mem:BLK (scratch)))]
17592 switch (get_attr_type (insn))
17595 return "mov{l}\t{%1, %0|%0, %1}";
17598 if (GET_CODE (operands[2]) == CONST_INT
17599 && (INTVAL (operands[2]) == 128
17600 || (INTVAL (operands[2]) < 0
17601 && INTVAL (operands[2]) != -128)))
17603 operands[2] = GEN_INT (-INTVAL (operands[2]));
17604 return "sub{l}\t{%2, %0|%0, %2}";
17606 return "add{l}\t{%2, %0|%0, %2}";
17609 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
17610 return "lea{l}\t{%a2, %0|%0, %a2}";
17616 [(set (attr "type")
17617 (cond [(eq_attr "alternative" "0")
17618 (const_string "alu")
17619 (match_operand:SI 2 "const0_operand" "")
17620 (const_string "imov")
17622 (const_string "lea")))
17623 (set_attr "mode" "SI")])
17625 (define_insn "pro_epilogue_adjust_stack_rex64"
17626 [(set (match_operand:DI 0 "register_operand" "=r,r")
17627 (plus:DI (match_operand:DI 1 "register_operand" "0,r")
17628 (match_operand:DI 2 "x86_64_immediate_operand" "e,e")))
17629 (clobber (reg:CC 17))
17630 (clobber (mem:BLK (scratch)))]
17633 switch (get_attr_type (insn))
17636 return "mov{q}\t{%1, %0|%0, %1}";
17639 if (GET_CODE (operands[2]) == CONST_INT
17640 && (INTVAL (operands[2]) == 128
17641 || (INTVAL (operands[2]) < 0
17642 && INTVAL (operands[2]) != -128)))
17644 operands[2] = GEN_INT (-INTVAL (operands[2]));
17645 return "sub{q}\t{%2, %0|%0, %2}";
17647 return "add{q}\t{%2, %0|%0, %2}";
17650 operands[2] = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
17651 return "lea{q}\t{%a2, %0|%0, %a2}";
17657 [(set (attr "type")
17658 (cond [(eq_attr "alternative" "0")
17659 (const_string "alu")
17660 (match_operand:DI 2 "const0_operand" "")
17661 (const_string "imov")
17663 (const_string "lea")))
17664 (set_attr "mode" "DI")])
17667 ;; Placeholder for the conditional moves. This one is split either to SSE
17668 ;; based moves emulation or to usual cmove sequence. Little bit unfortunate
17669 ;; fact is that compares supported by the cmp??ss instructions are exactly
17670 ;; swapped of those supported by cmove sequence.
17671 ;; The EQ/NE comparisons also needs bit care, since they are not directly
17672 ;; supported by i387 comparisons and we do need to emit two conditional moves
17675 (define_insn "sse_movsfcc"
17676 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
17677 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17678 [(match_operand:SF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
17679 (match_operand:SF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
17680 (match_operand:SF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
17681 (match_operand:SF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
17682 (clobber (match_scratch:SF 6 "=2,&4,X,X,X,X,X,X,X,X"))
17683 (clobber (reg:CC 17))]
17685 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
17686 /* Avoid combine from being smart and converting min/max
17687 instruction patterns into conditional moves. */
17688 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
17689 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
17690 || !rtx_equal_p (operands[4], operands[2])
17691 || !rtx_equal_p (operands[5], operands[3]))
17692 && (!TARGET_IEEE_FP
17693 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
17696 (define_insn "sse_movsfcc_eq"
17697 [(set (match_operand:SF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
17698 (if_then_else:SF (eq (match_operand:SF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
17699 (match_operand:SF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
17700 (match_operand:SF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
17701 (match_operand:SF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
17702 (clobber (match_scratch:SF 5 "=1,&3,X,X,X,X"))
17703 (clobber (reg:CC 17))]
17705 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17708 (define_insn "sse_movdfcc"
17709 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
17710 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17711 [(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
17712 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
17713 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
17714 (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
17715 (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
17716 (clobber (reg:CC 17))]
17718 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)
17719 /* Avoid combine from being smart and converting min/max
17720 instruction patterns into conditional moves. */
17721 && ((GET_CODE (operands[1]) != LT && GET_CODE (operands[1]) != GT
17722 && GET_CODE (operands[1]) != UNLE && GET_CODE (operands[1]) != UNGE)
17723 || !rtx_equal_p (operands[4], operands[2])
17724 || !rtx_equal_p (operands[5], operands[3]))
17725 && (!TARGET_IEEE_FP
17726 || (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE))"
17729 (define_insn "sse_movdfcc_eq"
17730 [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
17731 (if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
17732 (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
17733 (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
17734 (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
17735 (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
17736 (clobber (reg:CC 17))]
17738 && (GET_CODE (operands[2]) != MEM || GET_CODE (operands[3]) != MEM)"
17741 ;; For non-sse moves just expand the usual cmove sequence.
17743 [(set (match_operand 0 "register_operand" "")
17744 (if_then_else (match_operator 1 "comparison_operator"
17745 [(match_operand 4 "nonimmediate_operand" "")
17746 (match_operand 5 "register_operand" "")])
17747 (match_operand 2 "nonimmediate_operand" "")
17748 (match_operand 3 "nonimmediate_operand" "")))
17749 (clobber (match_operand 6 "" ""))
17750 (clobber (reg:CC 17))]
17751 "!SSE_REG_P (operands[0]) && reload_completed
17752 && VALID_SSE_REG_MODE (GET_MODE (operands[0]))"
17755 ix86_compare_op0 = operands[5];
17756 ix86_compare_op1 = operands[4];
17757 operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
17758 VOIDmode, operands[5], operands[4]);
17759 ix86_expand_fp_movcc (operands);
17763 ;; Split SSE based conditional move into sequence:
17764 ;; cmpCC op0, op4 - set op0 to 0 or ffffffff depending on the comparison
17765 ;; and op2, op0 - zero op2 if comparison was false
17766 ;; nand op0, op3 - load op3 to op0 if comparison was false
17767 ;; or op2, op0 - get the nonzero one into the result.
17769 [(set (match_operand 0 "register_operand" "")
17770 (if_then_else (match_operator 1 "sse_comparison_operator"
17771 [(match_operand 4 "register_operand" "")
17772 (match_operand 5 "nonimmediate_operand" "")])
17773 (match_operand 2 "register_operand" "")
17774 (match_operand 3 "register_operand" "")))
17775 (clobber (match_operand 6 "" ""))
17776 (clobber (reg:CC 17))]
17777 "SSE_REG_P (operands[0]) && reload_completed"
17778 [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)]))
17779 (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0)
17780 (subreg:TI (match_dup 4) 0)))
17781 (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0))
17782 (subreg:TI (match_dup 3) 0)))
17783 (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
17784 (subreg:TI (match_dup 7) 0)))]
17786 if (GET_MODE (operands[2]) == DFmode
17787 && TARGET_SSE_PARTIAL_REGS && !optimize_size)
17789 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17790 emit_insn (gen_sse2_unpcklpd (op, op, op));
17791 op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17792 emit_insn (gen_sse2_unpcklpd (op, op, op));
17795 /* If op2 == op3, op3 would be clobbered before it is used. */
17796 if (operands_match_p (operands[2], operands[3]))
17798 emit_move_insn (operands[0], operands[2]);
17802 PUT_MODE (operands[1], GET_MODE (operands[0]));
17803 if (operands_match_p (operands[0], operands[4]))
17804 operands[6] = operands[4], operands[7] = operands[2];
17806 operands[6] = operands[2], operands[7] = operands[4];
17809 ;; Special case of conditional move we can handle effectively.
17810 ;; Do not brother with the integer/floating point case, since these are
17811 ;; bot considerably slower, unlike in the generic case.
17812 (define_insn "*sse_movsfcc_const0_1"
17813 [(set (match_operand:SF 0 "register_operand" "=&x")
17814 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17815 [(match_operand:SF 4 "register_operand" "0")
17816 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17817 (match_operand:SF 2 "register_operand" "x")
17818 (match_operand:SF 3 "const0_operand" "X")))]
17822 (define_insn "*sse_movsfcc_const0_2"
17823 [(set (match_operand:SF 0 "register_operand" "=&x")
17824 (if_then_else:SF (match_operator 1 "sse_comparison_operator"
17825 [(match_operand:SF 4 "register_operand" "0")
17826 (match_operand:SF 5 "nonimmediate_operand" "xm")])
17827 (match_operand:SF 2 "const0_operand" "X")
17828 (match_operand:SF 3 "register_operand" "x")))]
17832 (define_insn "*sse_movsfcc_const0_3"
17833 [(set (match_operand:SF 0 "register_operand" "=&x")
17834 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17835 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17836 (match_operand:SF 5 "register_operand" "0")])
17837 (match_operand:SF 2 "register_operand" "x")
17838 (match_operand:SF 3 "const0_operand" "X")))]
17842 (define_insn "*sse_movsfcc_const0_4"
17843 [(set (match_operand:SF 0 "register_operand" "=&x")
17844 (if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
17845 [(match_operand:SF 4 "nonimmediate_operand" "xm")
17846 (match_operand:SF 5 "register_operand" "0")])
17847 (match_operand:SF 2 "const0_operand" "X")
17848 (match_operand:SF 3 "register_operand" "x")))]
17852 (define_insn "*sse_movdfcc_const0_1"
17853 [(set (match_operand:DF 0 "register_operand" "=&Y")
17854 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17855 [(match_operand:DF 4 "register_operand" "0")
17856 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17857 (match_operand:DF 2 "register_operand" "Y")
17858 (match_operand:DF 3 "const0_operand" "X")))]
17862 (define_insn "*sse_movdfcc_const0_2"
17863 [(set (match_operand:DF 0 "register_operand" "=&Y")
17864 (if_then_else:DF (match_operator 1 "sse_comparison_operator"
17865 [(match_operand:DF 4 "register_operand" "0")
17866 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
17867 (match_operand:DF 2 "const0_operand" "X")
17868 (match_operand:DF 3 "register_operand" "Y")))]
17872 (define_insn "*sse_movdfcc_const0_3"
17873 [(set (match_operand:DF 0 "register_operand" "=&Y")
17874 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17875 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17876 (match_operand:DF 5 "register_operand" "0")])
17877 (match_operand:DF 2 "register_operand" "Y")
17878 (match_operand:DF 3 "const0_operand" "X")))]
17882 (define_insn "*sse_movdfcc_const0_4"
17883 [(set (match_operand:DF 0 "register_operand" "=&Y")
17884 (if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
17885 [(match_operand:DF 4 "nonimmediate_operand" "Ym")
17886 (match_operand:DF 5 "register_operand" "0")])
17887 (match_operand:DF 2 "const0_operand" "X")
17888 (match_operand:DF 3 "register_operand" "Y")))]
17893 [(set (match_operand 0 "register_operand" "")
17894 (if_then_else (match_operator 1 "comparison_operator"
17895 [(match_operand 4 "nonimmediate_operand" "")
17896 (match_operand 5 "nonimmediate_operand" "")])
17897 (match_operand 2 "nonmemory_operand" "")
17898 (match_operand 3 "nonmemory_operand" "")))]
17899 "SSE_REG_P (operands[0]) && reload_completed
17900 && (const0_operand (operands[2], GET_MODE (operands[0]))
17901 || const0_operand (operands[3], GET_MODE (operands[0])))"
17902 [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
17903 (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6)
17906 if (TARGET_SSE_PARTIAL_REGS && !optimize_size
17907 && GET_MODE (operands[2]) == DFmode)
17909 if (REG_P (operands[2]))
17911 rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
17912 emit_insn (gen_sse2_unpcklpd (op, op, op));
17914 if (REG_P (operands[3]))
17916 rtx op = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0);
17917 emit_insn (gen_sse2_unpcklpd (op, op, op));
17920 PUT_MODE (operands[1], GET_MODE (operands[0]));
17921 if (!sse_comparison_operator (operands[1], VOIDmode)
17922 || !rtx_equal_p (operands[0], operands[4]))
17924 rtx tmp = operands[5];
17925 operands[5] = operands[4];
17927 PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
17929 if (!rtx_equal_p (operands[0], operands[4]))
17931 if (const0_operand (operands[2], GET_MODE (operands[0])))
17933 operands[7] = operands[3];
17934 operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
17939 operands[7] = operands[2];
17940 operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
17942 operands[7] = simplify_gen_subreg (TImode, operands[7],
17943 GET_MODE (operands[7]), 0);
17946 (define_expand "allocate_stack_worker"
17947 [(match_operand:SI 0 "register_operand" "")]
17948 "TARGET_STACK_PROBE"
17951 emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
17953 emit_insn (gen_allocate_stack_worker_1 (operands[0]));
17957 (define_insn "allocate_stack_worker_1"
17958 [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17959 (set (reg:SI 7) (minus:SI (reg:SI 7) (match_dup 0)))
17960 (clobber (match_dup 0))
17961 (clobber (reg:CC 17))]
17962 "!TARGET_64BIT && TARGET_STACK_PROBE"
17964 [(set_attr "type" "multi")
17965 (set_attr "length" "5")])
17967 (define_insn "allocate_stack_worker_rex64"
17968 [(unspec:DI [(match_operand:DI 0 "register_operand" "a")] UNSPEC_STACK_PROBE)
17969 (set (reg:DI 7) (minus:DI (reg:DI 7) (match_dup 0)))
17970 (clobber (match_dup 0))
17971 (clobber (reg:CC 17))]
17972 "TARGET_64BIT && TARGET_STACK_PROBE"
17974 [(set_attr "type" "multi")
17975 (set_attr "length" "5")])
17977 (define_expand "allocate_stack"
17978 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
17979 (minus:SI (reg:SI 7)
17980 (match_operand:SI 1 "general_operand" "")))
17981 (clobber (reg:CC 17))])
17982 (parallel [(set (reg:SI 7)
17983 (minus:SI (reg:SI 7) (match_dup 1)))
17984 (clobber (reg:CC 17))])]
17985 "TARGET_STACK_PROBE"
17987 #ifdef CHECK_STACK_LIMIT
17988 if (GET_CODE (operands[1]) == CONST_INT
17989 && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
17990 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
17994 emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
17997 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
18001 (define_expand "builtin_setjmp_receiver"
18002 [(label_ref (match_operand 0 "" ""))]
18003 "!TARGET_64BIT && flag_pic"
18005 emit_insn (gen_set_got (pic_offset_table_rtx));
18009 ;; Avoid redundant prefixes by splitting HImode arithmetic to SImode.
18012 [(set (match_operand 0 "register_operand" "")
18013 (match_operator 3 "promotable_binary_operator"
18014 [(match_operand 1 "register_operand" "")
18015 (match_operand 2 "aligned_operand" "")]))
18016 (clobber (reg:CC 17))]
18017 "! TARGET_PARTIAL_REG_STALL && reload_completed
18018 && ((GET_MODE (operands[0]) == HImode
18019 && ((!optimize_size && !TARGET_FAST_PREFIX)
18020 || GET_CODE (operands[2]) != CONST_INT
18021 || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')))
18022 || (GET_MODE (operands[0]) == QImode
18023 && (TARGET_PROMOTE_QImode || optimize_size)))"
18024 [(parallel [(set (match_dup 0)
18025 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18026 (clobber (reg:CC 17))])]
18027 "operands[0] = gen_lowpart (SImode, operands[0]);
18028 operands[1] = gen_lowpart (SImode, operands[1]);
18029 if (GET_CODE (operands[3]) != ASHIFT)
18030 operands[2] = gen_lowpart (SImode, operands[2]);
18031 PUT_MODE (operands[3], SImode);")
18033 ; Promote the QImode tests, as i386 has encoding of the AND
18034 ; instruction with 32-bit sign-extended immediate and thus the
18035 ; instruction size is unchanged, except in the %eax case for
18036 ; which it is increased by one byte, hence the ! optimize_size.
18039 (compare (and (match_operand 1 "aligned_operand" "")
18040 (match_operand 2 "const_int_operand" ""))
18042 (set (match_operand 0 "register_operand" "")
18043 (and (match_dup 1) (match_dup 2)))]
18044 "! TARGET_PARTIAL_REG_STALL && reload_completed
18045 /* Ensure that the operand will remain sign-extended immediate. */
18046 && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)
18048 && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX)
18049 || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))"
18050 [(parallel [(set (reg:CCNO 17)
18051 (compare:CCNO (and:SI (match_dup 1) (match_dup 2))
18054 (and:SI (match_dup 1) (match_dup 2)))])]
18056 = gen_int_mode (INTVAL (operands[2])
18057 & GET_MODE_MASK (GET_MODE (operands[0])),
18059 operands[0] = gen_lowpart (SImode, operands[0]);
18060 operands[1] = gen_lowpart (SImode, operands[1]);")
18062 ; Don't promote the QImode tests, as i386 doesn't have encoding of
18063 ; the TEST instruction with 32-bit sign-extended immediate and thus
18064 ; the instruction size would at least double, which is not what we
18065 ; want even with ! optimize_size.
18068 (compare (and (match_operand:HI 0 "aligned_operand" "")
18069 (match_operand:HI 1 "const_int_operand" ""))
18071 "! TARGET_PARTIAL_REG_STALL && reload_completed
18072 /* Ensure that the operand will remain sign-extended immediate. */
18073 && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)
18074 && ! TARGET_FAST_PREFIX
18075 && ! optimize_size"
18076 [(set (reg:CCNO 17)
18077 (compare:CCNO (and:SI (match_dup 0) (match_dup 1))
18080 = gen_int_mode (INTVAL (operands[1])
18081 & GET_MODE_MASK (GET_MODE (operands[0])),
18083 operands[0] = gen_lowpart (SImode, operands[0]);")
18086 [(set (match_operand 0 "register_operand" "")
18087 (neg (match_operand 1 "register_operand" "")))
18088 (clobber (reg:CC 17))]
18089 "! TARGET_PARTIAL_REG_STALL && reload_completed
18090 && (GET_MODE (operands[0]) == HImode
18091 || (GET_MODE (operands[0]) == QImode
18092 && (TARGET_PROMOTE_QImode || optimize_size)))"
18093 [(parallel [(set (match_dup 0)
18094 (neg:SI (match_dup 1)))
18095 (clobber (reg:CC 17))])]
18096 "operands[0] = gen_lowpart (SImode, operands[0]);
18097 operands[1] = gen_lowpart (SImode, operands[1]);")
18100 [(set (match_operand 0 "register_operand" "")
18101 (not (match_operand 1 "register_operand" "")))]
18102 "! TARGET_PARTIAL_REG_STALL && reload_completed
18103 && (GET_MODE (operands[0]) == HImode
18104 || (GET_MODE (operands[0]) == QImode
18105 && (TARGET_PROMOTE_QImode || optimize_size)))"
18106 [(set (match_dup 0)
18107 (not:SI (match_dup 1)))]
18108 "operands[0] = gen_lowpart (SImode, operands[0]);
18109 operands[1] = gen_lowpart (SImode, operands[1]);")
18112 [(set (match_operand 0 "register_operand" "")
18113 (if_then_else (match_operator 1 "comparison_operator"
18114 [(reg 17) (const_int 0)])
18115 (match_operand 2 "register_operand" "")
18116 (match_operand 3 "register_operand" "")))]
18117 "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
18118 && (GET_MODE (operands[0]) == HImode
18119 || (GET_MODE (operands[0]) == QImode
18120 && (TARGET_PROMOTE_QImode || optimize_size)))"
18121 [(set (match_dup 0)
18122 (if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
18123 "operands[0] = gen_lowpart (SImode, operands[0]);
18124 operands[2] = gen_lowpart (SImode, operands[2]);
18125 operands[3] = gen_lowpart (SImode, operands[3]);")
18128 ;; RTL Peephole optimizations, run before sched2. These primarily look to
18129 ;; transform a complex memory operation into two memory to register operations.
18131 ;; Don't push memory operands
18133 [(set (match_operand:SI 0 "push_operand" "")
18134 (match_operand:SI 1 "memory_operand" ""))
18135 (match_scratch:SI 2 "r")]
18136 "! optimize_size && ! TARGET_PUSH_MEMORY"
18137 [(set (match_dup 2) (match_dup 1))
18138 (set (match_dup 0) (match_dup 2))]
18142 [(set (match_operand:DI 0 "push_operand" "")
18143 (match_operand:DI 1 "memory_operand" ""))
18144 (match_scratch:DI 2 "r")]
18145 "! optimize_size && ! TARGET_PUSH_MEMORY"
18146 [(set (match_dup 2) (match_dup 1))
18147 (set (match_dup 0) (match_dup 2))]
18150 ;; We need to handle SFmode only, because DFmode and XFmode is split to
18153 [(set (match_operand:SF 0 "push_operand" "")
18154 (match_operand:SF 1 "memory_operand" ""))
18155 (match_scratch:SF 2 "r")]
18156 "! optimize_size && ! TARGET_PUSH_MEMORY"
18157 [(set (match_dup 2) (match_dup 1))
18158 (set (match_dup 0) (match_dup 2))]
18162 [(set (match_operand:HI 0 "push_operand" "")
18163 (match_operand:HI 1 "memory_operand" ""))
18164 (match_scratch:HI 2 "r")]
18165 "! optimize_size && ! TARGET_PUSH_MEMORY"
18166 [(set (match_dup 2) (match_dup 1))
18167 (set (match_dup 0) (match_dup 2))]
18171 [(set (match_operand:QI 0 "push_operand" "")
18172 (match_operand:QI 1 "memory_operand" ""))
18173 (match_scratch:QI 2 "q")]
18174 "! optimize_size && ! TARGET_PUSH_MEMORY"
18175 [(set (match_dup 2) (match_dup 1))
18176 (set (match_dup 0) (match_dup 2))]
18179 ;; Don't move an immediate directly to memory when the instruction
18182 [(match_scratch:SI 1 "r")
18183 (set (match_operand:SI 0 "memory_operand" "")
18186 && ! TARGET_USE_MOV0
18187 && TARGET_SPLIT_LONG_MOVES
18188 && get_attr_length (insn) >= ix86_cost->large_insn
18189 && peep2_regno_dead_p (0, FLAGS_REG)"
18190 [(parallel [(set (match_dup 1) (const_int 0))
18191 (clobber (reg:CC 17))])
18192 (set (match_dup 0) (match_dup 1))]
18196 [(match_scratch:HI 1 "r")
18197 (set (match_operand:HI 0 "memory_operand" "")
18200 && ! TARGET_USE_MOV0
18201 && TARGET_SPLIT_LONG_MOVES
18202 && get_attr_length (insn) >= ix86_cost->large_insn
18203 && peep2_regno_dead_p (0, FLAGS_REG)"
18204 [(parallel [(set (match_dup 2) (const_int 0))
18205 (clobber (reg:CC 17))])
18206 (set (match_dup 0) (match_dup 1))]
18207 "operands[2] = gen_lowpart (SImode, operands[1]);")
18210 [(match_scratch:QI 1 "q")
18211 (set (match_operand:QI 0 "memory_operand" "")
18214 && ! TARGET_USE_MOV0
18215 && TARGET_SPLIT_LONG_MOVES
18216 && get_attr_length (insn) >= ix86_cost->large_insn
18217 && peep2_regno_dead_p (0, FLAGS_REG)"
18218 [(parallel [(set (match_dup 2) (const_int 0))
18219 (clobber (reg:CC 17))])
18220 (set (match_dup 0) (match_dup 1))]
18221 "operands[2] = gen_lowpart (SImode, operands[1]);")
18224 [(match_scratch:SI 2 "r")
18225 (set (match_operand:SI 0 "memory_operand" "")
18226 (match_operand:SI 1 "immediate_operand" ""))]
18228 && get_attr_length (insn) >= ix86_cost->large_insn
18229 && TARGET_SPLIT_LONG_MOVES"
18230 [(set (match_dup 2) (match_dup 1))
18231 (set (match_dup 0) (match_dup 2))]
18235 [(match_scratch:HI 2 "r")
18236 (set (match_operand:HI 0 "memory_operand" "")
18237 (match_operand:HI 1 "immediate_operand" ""))]
18238 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
18239 && TARGET_SPLIT_LONG_MOVES"
18240 [(set (match_dup 2) (match_dup 1))
18241 (set (match_dup 0) (match_dup 2))]
18245 [(match_scratch:QI 2 "q")
18246 (set (match_operand:QI 0 "memory_operand" "")
18247 (match_operand:QI 1 "immediate_operand" ""))]
18248 "! optimize_size && get_attr_length (insn) >= ix86_cost->large_insn
18249 && TARGET_SPLIT_LONG_MOVES"
18250 [(set (match_dup 2) (match_dup 1))
18251 (set (match_dup 0) (match_dup 2))]
18254 ;; Don't compare memory with zero, load and use a test instead.
18257 (compare (match_operand:SI 0 "memory_operand" "")
18259 (match_scratch:SI 3 "r")]
18260 "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size"
18261 [(set (match_dup 3) (match_dup 0))
18262 (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))]
18265 ;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
18266 ;; Don't split NOTs with a displacement operand, because resulting XOR
18267 ;; will not be pairable anyway.
18269 ;; On AMD K6, NOT is vector decoded with memory operand that can not be
18270 ;; represented using a modRM byte. The XOR replacement is long decoded,
18271 ;; so this split helps here as well.
18273 ;; Note: Can't do this as a regular split because we can't get proper
18274 ;; lifetime information then.
18277 [(set (match_operand:SI 0 "nonimmediate_operand" "")
18278 (not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
18280 && peep2_regno_dead_p (0, FLAGS_REG)
18281 && ((TARGET_PENTIUM
18282 && (GET_CODE (operands[0]) != MEM
18283 || !memory_displacement_operand (operands[0], SImode)))
18284 || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
18285 [(parallel [(set (match_dup 0)
18286 (xor:SI (match_dup 1) (const_int -1)))
18287 (clobber (reg:CC 17))])]
18291 [(set (match_operand:HI 0 "nonimmediate_operand" "")
18292 (not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
18294 && peep2_regno_dead_p (0, FLAGS_REG)
18295 && ((TARGET_PENTIUM
18296 && (GET_CODE (operands[0]) != MEM
18297 || !memory_displacement_operand (operands[0], HImode)))
18298 || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
18299 [(parallel [(set (match_dup 0)
18300 (xor:HI (match_dup 1) (const_int -1)))
18301 (clobber (reg:CC 17))])]
18305 [(set (match_operand:QI 0 "nonimmediate_operand" "")
18306 (not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
18308 && peep2_regno_dead_p (0, FLAGS_REG)
18309 && ((TARGET_PENTIUM
18310 && (GET_CODE (operands[0]) != MEM
18311 || !memory_displacement_operand (operands[0], QImode)))
18312 || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
18313 [(parallel [(set (match_dup 0)
18314 (xor:QI (match_dup 1) (const_int -1)))
18315 (clobber (reg:CC 17))])]
18318 ;; Non pairable "test imm, reg" instructions can be translated to
18319 ;; "and imm, reg" if reg dies. The "and" form is also shorter (one
18320 ;; byte opcode instead of two, have a short form for byte operands),
18321 ;; so do it for other CPUs as well. Given that the value was dead,
18322 ;; this should not create any new dependencies. Pass on the sub-word
18323 ;; versions if we're concerned about partial register stalls.
18327 (compare (and:SI (match_operand:SI 0 "register_operand" "")
18328 (match_operand:SI 1 "immediate_operand" ""))
18330 "ix86_match_ccmode (insn, CCNOmode)
18331 && (true_regnum (operands[0]) != 0
18332 || (GET_CODE (operands[1]) == CONST_INT
18333 && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')))
18334 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18336 [(set (reg:CCNO 17)
18337 (compare:CCNO (and:SI (match_dup 0)
18341 (and:SI (match_dup 0) (match_dup 1)))])]
18344 ;; We don't need to handle HImode case, because it will be promoted to SImode
18345 ;; on ! TARGET_PARTIAL_REG_STALL
18349 (compare (and:QI (match_operand:QI 0 "register_operand" "")
18350 (match_operand:QI 1 "immediate_operand" ""))
18352 "! TARGET_PARTIAL_REG_STALL
18353 && ix86_match_ccmode (insn, CCNOmode)
18354 && true_regnum (operands[0]) != 0
18355 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18357 [(set (reg:CCNO 17)
18358 (compare:CCNO (and:QI (match_dup 0)
18362 (and:QI (match_dup 0) (match_dup 1)))])]
18370 (match_operand 0 "ext_register_operand" "")
18373 (match_operand 1 "const_int_operand" ""))
18375 "! TARGET_PARTIAL_REG_STALL
18376 && ix86_match_ccmode (insn, CCNOmode)
18377 && true_regnum (operands[0]) != 0
18378 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18379 [(parallel [(set (reg:CCNO 17)
18388 (set (zero_extract:SI (match_dup 0)
18399 ;; Don't do logical operations with memory inputs.
18401 [(match_scratch:SI 2 "r")
18402 (parallel [(set (match_operand:SI 0 "register_operand" "")
18403 (match_operator:SI 3 "arith_or_logical_operator"
18405 (match_operand:SI 1 "memory_operand" "")]))
18406 (clobber (reg:CC 17))])]
18407 "! optimize_size && ! TARGET_READ_MODIFY"
18408 [(set (match_dup 2) (match_dup 1))
18409 (parallel [(set (match_dup 0)
18410 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
18411 (clobber (reg:CC 17))])]
18415 [(match_scratch:SI 2 "r")
18416 (parallel [(set (match_operand:SI 0 "register_operand" "")
18417 (match_operator:SI 3 "arith_or_logical_operator"
18418 [(match_operand:SI 1 "memory_operand" "")
18420 (clobber (reg:CC 17))])]
18421 "! optimize_size && ! TARGET_READ_MODIFY"
18422 [(set (match_dup 2) (match_dup 1))
18423 (parallel [(set (match_dup 0)
18424 (match_op_dup 3 [(match_dup 2) (match_dup 0)]))
18425 (clobber (reg:CC 17))])]
18428 ; Don't do logical operations with memory outputs
18430 ; These two don't make sense for PPro/PII -- we're expanding a 4-uop
18431 ; instruction into two 1-uop insns plus a 2-uop insn. That last has
18432 ; the same decoder scheduling characteristics as the original.
18435 [(match_scratch:SI 2 "r")
18436 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18437 (match_operator:SI 3 "arith_or_logical_operator"
18439 (match_operand:SI 1 "nonmemory_operand" "")]))
18440 (clobber (reg:CC 17))])]
18441 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18442 [(set (match_dup 2) (match_dup 0))
18443 (parallel [(set (match_dup 2)
18444 (match_op_dup 3 [(match_dup 2) (match_dup 1)]))
18445 (clobber (reg:CC 17))])
18446 (set (match_dup 0) (match_dup 2))]
18450 [(match_scratch:SI 2 "r")
18451 (parallel [(set (match_operand:SI 0 "memory_operand" "")
18452 (match_operator:SI 3 "arith_or_logical_operator"
18453 [(match_operand:SI 1 "nonmemory_operand" "")
18455 (clobber (reg:CC 17))])]
18456 "! optimize_size && ! TARGET_READ_MODIFY_WRITE"
18457 [(set (match_dup 2) (match_dup 0))
18458 (parallel [(set (match_dup 2)
18459 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
18460 (clobber (reg:CC 17))])
18461 (set (match_dup 0) (match_dup 2))]
18464 ;; Attempt to always use XOR for zeroing registers.
18466 [(set (match_operand 0 "register_operand" "")
18468 "(GET_MODE (operands[0]) == QImode
18469 || GET_MODE (operands[0]) == HImode
18470 || GET_MODE (operands[0]) == SImode
18471 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
18472 && (! TARGET_USE_MOV0 || optimize_size)
18473 && peep2_regno_dead_p (0, FLAGS_REG)"
18474 [(parallel [(set (match_dup 0) (const_int 0))
18475 (clobber (reg:CC 17))])]
18476 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
18480 [(set (strict_low_part (match_operand 0 "register_operand" ""))
18482 "(GET_MODE (operands[0]) == QImode
18483 || GET_MODE (operands[0]) == HImode)
18484 && (! TARGET_USE_MOV0 || optimize_size)
18485 && peep2_regno_dead_p (0, FLAGS_REG)"
18486 [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
18487 (clobber (reg:CC 17))])])
18489 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
18491 [(set (match_operand 0 "register_operand" "")
18493 "(GET_MODE (operands[0]) == HImode
18494 || GET_MODE (operands[0]) == SImode
18495 || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
18496 && (optimize_size || TARGET_PENTIUM)
18497 && peep2_regno_dead_p (0, FLAGS_REG)"
18498 [(parallel [(set (match_dup 0) (const_int -1))
18499 (clobber (reg:CC 17))])]
18500 "operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
18503 ;; Attempt to convert simple leas to adds. These can be created by
18506 [(set (match_operand:SI 0 "register_operand" "")
18507 (plus:SI (match_dup 0)
18508 (match_operand:SI 1 "nonmemory_operand" "")))]
18509 "peep2_regno_dead_p (0, FLAGS_REG)"
18510 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
18511 (clobber (reg:CC 17))])]
18515 [(set (match_operand:SI 0 "register_operand" "")
18516 (subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
18517 (match_operand:DI 2 "nonmemory_operand" "")) 0))]
18518 "peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
18519 [(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
18520 (clobber (reg:CC 17))])]
18521 "operands[2] = gen_lowpart (SImode, operands[2]);")
18524 [(set (match_operand:DI 0 "register_operand" "")
18525 (plus:DI (match_dup 0)
18526 (match_operand:DI 1 "x86_64_general_operand" "")))]
18527 "peep2_regno_dead_p (0, FLAGS_REG)"
18528 [(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
18529 (clobber (reg:CC 17))])]
18533 [(set (match_operand:SI 0 "register_operand" "")
18534 (mult:SI (match_dup 0)
18535 (match_operand:SI 1 "const_int_operand" "")))]
18536 "exact_log2 (INTVAL (operands[1])) >= 0
18537 && peep2_regno_dead_p (0, FLAGS_REG)"
18538 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
18539 (clobber (reg:CC 17))])]
18540 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
18543 [(set (match_operand:DI 0 "register_operand" "")
18544 (mult:DI (match_dup 0)
18545 (match_operand:DI 1 "const_int_operand" "")))]
18546 "exact_log2 (INTVAL (operands[1])) >= 0
18547 && peep2_regno_dead_p (0, FLAGS_REG)"
18548 [(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
18549 (clobber (reg:CC 17))])]
18550 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
18553 [(set (match_operand:SI 0 "register_operand" "")
18554 (subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
18555 (match_operand:DI 2 "const_int_operand" "")) 0))]
18556 "exact_log2 (INTVAL (operands[2])) >= 0
18557 && REGNO (operands[0]) == REGNO (operands[1])
18558 && peep2_regno_dead_p (0, FLAGS_REG)"
18559 [(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
18560 (clobber (reg:CC 17))])]
18561 "operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));")
18563 ;; The ESP adjustments can be done by the push and pop instructions. Resulting
18564 ;; code is shorter, since push is only 1 byte, while add imm, %esp 3 bytes. On
18565 ;; many CPUs it is also faster, since special hardware to avoid esp
18566 ;; dependencies is present.
18568 ;; While some of these conversions may be done using splitters, we use peepholes
18569 ;; in order to allow combine_stack_adjustments pass to see nonobfuscated RTL.
18571 ;; Convert prologue esp subtractions to push.
18572 ;; We need register to push. In order to keep verify_flow_info happy we have
18574 ;; - use scratch and clobber it in order to avoid dependencies
18575 ;; - use already live register
18576 ;; We can't use the second way right now, since there is no reliable way how to
18577 ;; verify that given register is live. First choice will also most likely in
18578 ;; fewer dependencies. On the place of esp adjustments it is very likely that
18579 ;; call clobbered registers are dead. We may want to use base pointer as an
18580 ;; alternative when no register is available later.
18583 [(match_scratch:SI 0 "r")
18584 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
18585 (clobber (reg:CC 17))
18586 (clobber (mem:BLK (scratch)))])]
18587 "optimize_size || !TARGET_SUB_ESP_4"
18588 [(clobber (match_dup 0))
18589 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18590 (clobber (mem:BLK (scratch)))])])
18593 [(match_scratch:SI 0 "r")
18594 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18595 (clobber (reg:CC 17))
18596 (clobber (mem:BLK (scratch)))])]
18597 "optimize_size || !TARGET_SUB_ESP_8"
18598 [(clobber (match_dup 0))
18599 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18600 (parallel [(set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18601 (clobber (mem:BLK (scratch)))])])
18603 ;; Convert esp subtractions to push.
18605 [(match_scratch:SI 0 "r")
18606 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -4)))
18607 (clobber (reg:CC 17))])]
18608 "optimize_size || !TARGET_SUB_ESP_4"
18609 [(clobber (match_dup 0))
18610 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
18613 [(match_scratch:SI 0 "r")
18614 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -8)))
18615 (clobber (reg:CC 17))])]
18616 "optimize_size || !TARGET_SUB_ESP_8"
18617 [(clobber (match_dup 0))
18618 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))
18619 (set (mem:SI (pre_dec:SI (reg:SI 7))) (match_dup 0))])
18621 ;; Convert epilogue deallocator to pop.
18623 [(match_scratch:SI 0 "r")
18624 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18625 (clobber (reg:CC 17))
18626 (clobber (mem:BLK (scratch)))])]
18627 "optimize_size || !TARGET_ADD_ESP_4"
18628 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18629 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18630 (clobber (mem:BLK (scratch)))])]
18633 ;; Two pops case is tricky, since pop causes dependency on destination register.
18634 ;; We use two registers if available.
18636 [(match_scratch:SI 0 "r")
18637 (match_scratch:SI 1 "r")
18638 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18639 (clobber (reg:CC 17))
18640 (clobber (mem:BLK (scratch)))])]
18641 "optimize_size || !TARGET_ADD_ESP_8"
18642 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18643 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18644 (clobber (mem:BLK (scratch)))])
18645 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
18646 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18650 [(match_scratch:SI 0 "r")
18651 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18652 (clobber (reg:CC 17))
18653 (clobber (mem:BLK (scratch)))])]
18655 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18656 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18657 (clobber (mem:BLK (scratch)))])
18658 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18659 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18662 ;; Convert esp additions to pop.
18664 [(match_scratch:SI 0 "r")
18665 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))
18666 (clobber (reg:CC 17))])]
18668 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18669 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18672 ;; Two pops case is tricky, since pop causes dependency on destination register.
18673 ;; We use two registers if available.
18675 [(match_scratch:SI 0 "r")
18676 (match_scratch:SI 1 "r")
18677 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18678 (clobber (reg:CC 17))])]
18680 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18681 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
18682 (parallel [(set (match_dup 1) (mem:SI (reg:SI 7)))
18683 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18687 [(match_scratch:SI 0 "r")
18688 (parallel [(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 8)))
18689 (clobber (reg:CC 17))])]
18691 [(parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18692 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])
18693 (parallel [(set (match_dup 0) (mem:SI (reg:SI 7)))
18694 (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
18697 ;; Convert compares with 1 to shorter inc/dec operations when CF is not
18698 ;; required and register dies.
18701 (compare (match_operand:SI 0 "register_operand" "")
18702 (match_operand:SI 1 "incdec_operand" "")))]
18703 "ix86_match_ccmode (insn, CCGCmode)
18704 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18705 [(parallel [(set (reg:CCGC 17)
18706 (compare:CCGC (match_dup 0)
18708 (clobber (match_dup 0))])]
18713 (compare (match_operand:HI 0 "register_operand" "")
18714 (match_operand:HI 1 "incdec_operand" "")))]
18715 "ix86_match_ccmode (insn, CCGCmode)
18716 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18717 [(parallel [(set (reg:CCGC 17)
18718 (compare:CCGC (match_dup 0)
18720 (clobber (match_dup 0))])]
18725 (compare (match_operand:QI 0 "register_operand" "")
18726 (match_operand:QI 1 "incdec_operand" "")))]
18727 "ix86_match_ccmode (insn, CCGCmode)
18728 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18729 [(parallel [(set (reg:CCGC 17)
18730 (compare:CCGC (match_dup 0)
18732 (clobber (match_dup 0))])]
18735 ;; Convert compares with 128 to shorter add -128
18738 (compare (match_operand:SI 0 "register_operand" "")
18740 "ix86_match_ccmode (insn, CCGCmode)
18741 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18742 [(parallel [(set (reg:CCGC 17)
18743 (compare:CCGC (match_dup 0)
18745 (clobber (match_dup 0))])]
18750 (compare (match_operand:HI 0 "register_operand" "")
18752 "ix86_match_ccmode (insn, CCGCmode)
18753 && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
18754 [(parallel [(set (reg:CCGC 17)
18755 (compare:CCGC (match_dup 0)
18757 (clobber (match_dup 0))])]
18761 [(match_scratch:DI 0 "r")
18762 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18763 (clobber (reg:CC 17))
18764 (clobber (mem:BLK (scratch)))])]
18765 "optimize_size || !TARGET_SUB_ESP_4"
18766 [(clobber (match_dup 0))
18767 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18768 (clobber (mem:BLK (scratch)))])])
18771 [(match_scratch:DI 0 "r")
18772 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18773 (clobber (reg:CC 17))
18774 (clobber (mem:BLK (scratch)))])]
18775 "optimize_size || !TARGET_SUB_ESP_8"
18776 [(clobber (match_dup 0))
18777 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18778 (parallel [(set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18779 (clobber (mem:BLK (scratch)))])])
18781 ;; Convert esp subtractions to push.
18783 [(match_scratch:DI 0 "r")
18784 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -8)))
18785 (clobber (reg:CC 17))])]
18786 "optimize_size || !TARGET_SUB_ESP_4"
18787 [(clobber (match_dup 0))
18788 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18791 [(match_scratch:DI 0 "r")
18792 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int -16)))
18793 (clobber (reg:CC 17))])]
18794 "optimize_size || !TARGET_SUB_ESP_8"
18795 [(clobber (match_dup 0))
18796 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))
18797 (set (mem:DI (pre_dec:DI (reg:DI 7))) (match_dup 0))])
18799 ;; Convert epilogue deallocator to pop.
18801 [(match_scratch:DI 0 "r")
18802 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18803 (clobber (reg:CC 17))
18804 (clobber (mem:BLK (scratch)))])]
18805 "optimize_size || !TARGET_ADD_ESP_4"
18806 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18807 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18808 (clobber (mem:BLK (scratch)))])]
18811 ;; Two pops case is tricky, since pop causes dependency on destination register.
18812 ;; We use two registers if available.
18814 [(match_scratch:DI 0 "r")
18815 (match_scratch:DI 1 "r")
18816 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18817 (clobber (reg:CC 17))
18818 (clobber (mem:BLK (scratch)))])]
18819 "optimize_size || !TARGET_ADD_ESP_8"
18820 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18821 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18822 (clobber (mem:BLK (scratch)))])
18823 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18824 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18828 [(match_scratch:DI 0 "r")
18829 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18830 (clobber (reg:CC 17))
18831 (clobber (mem:BLK (scratch)))])]
18833 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18834 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18835 (clobber (mem:BLK (scratch)))])
18836 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18837 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18840 ;; Convert esp additions to pop.
18842 [(match_scratch:DI 0 "r")
18843 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))
18844 (clobber (reg:CC 17))])]
18846 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18847 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18850 ;; Two pops case is tricky, since pop causes dependency on destination register.
18851 ;; We use two registers if available.
18853 [(match_scratch:DI 0 "r")
18854 (match_scratch:DI 1 "r")
18855 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18856 (clobber (reg:CC 17))])]
18858 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18859 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18860 (parallel [(set (match_dup 1) (mem:DI (reg:DI 7)))
18861 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18865 [(match_scratch:DI 0 "r")
18866 (parallel [(set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 16)))
18867 (clobber (reg:CC 17))])]
18869 [(parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18870 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])
18871 (parallel [(set (match_dup 0) (mem:DI (reg:DI 7)))
18872 (set (reg:DI 7) (plus:DI (reg:DI 7) (const_int 8)))])]
18875 ;; Imul $32bit_imm, mem, reg is vector decoded, while
18876 ;; imul $32bit_imm, reg, reg is direct decoded.
18878 [(match_scratch:DI 3 "r")
18879 (parallel [(set (match_operand:DI 0 "register_operand" "")
18880 (mult:DI (match_operand:DI 1 "memory_operand" "")
18881 (match_operand:DI 2 "immediate_operand" "")))
18882 (clobber (reg:CC 17))])]
18883 "TARGET_K8 && !optimize_size
18884 && (GET_CODE (operands[2]) != CONST_INT
18885 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18886 [(set (match_dup 3) (match_dup 1))
18887 (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
18888 (clobber (reg:CC 17))])]
18892 [(match_scratch:SI 3 "r")
18893 (parallel [(set (match_operand:SI 0 "register_operand" "")
18894 (mult:SI (match_operand:SI 1 "memory_operand" "")
18895 (match_operand:SI 2 "immediate_operand" "")))
18896 (clobber (reg:CC 17))])]
18897 "TARGET_K8 && !optimize_size
18898 && (GET_CODE (operands[2]) != CONST_INT
18899 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18900 [(set (match_dup 3) (match_dup 1))
18901 (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
18902 (clobber (reg:CC 17))])]
18906 [(match_scratch:SI 3 "r")
18907 (parallel [(set (match_operand:DI 0 "register_operand" "")
18909 (mult:SI (match_operand:SI 1 "memory_operand" "")
18910 (match_operand:SI 2 "immediate_operand" ""))))
18911 (clobber (reg:CC 17))])]
18912 "TARGET_K8 && !optimize_size
18913 && (GET_CODE (operands[2]) != CONST_INT
18914 || !CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))"
18915 [(set (match_dup 3) (match_dup 1))
18916 (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
18917 (clobber (reg:CC 17))])]
18920 ;; imul $8/16bit_imm, regmem, reg is vector decoded.
18921 ;; Convert it into imul reg, reg
18922 ;; It would be better to force assembler to encode instruction using long
18923 ;; immediate, but there is apparently no way to do so.
18925 [(parallel [(set (match_operand:DI 0 "register_operand" "")
18926 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
18927 (match_operand:DI 2 "const_int_operand" "")))
18928 (clobber (reg:CC 17))])
18929 (match_scratch:DI 3 "r")]
18930 "TARGET_K8 && !optimize_size
18931 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18932 [(set (match_dup 3) (match_dup 2))
18933 (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
18934 (clobber (reg:CC 17))])]
18936 if (!rtx_equal_p (operands[0], operands[1]))
18937 emit_move_insn (operands[0], operands[1]);
18941 [(parallel [(set (match_operand:SI 0 "register_operand" "")
18942 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
18943 (match_operand:SI 2 "const_int_operand" "")))
18944 (clobber (reg:CC 17))])
18945 (match_scratch:SI 3 "r")]
18946 "TARGET_K8 && !optimize_size
18947 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
18948 [(set (match_dup 3) (match_dup 2))
18949 (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
18950 (clobber (reg:CC 17))])]
18952 if (!rtx_equal_p (operands[0], operands[1]))
18953 emit_move_insn (operands[0], operands[1]);
18957 [(parallel [(set (match_operand:HI 0 "register_operand" "")
18958 (mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
18959 (match_operand:HI 2 "immediate_operand" "")))
18960 (clobber (reg:CC 17))])
18961 (match_scratch:HI 3 "r")]
18962 "TARGET_K8 && !optimize_size"
18963 [(set (match_dup 3) (match_dup 2))
18964 (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
18965 (clobber (reg:CC 17))])]
18967 if (!rtx_equal_p (operands[0], operands[1]))
18968 emit_move_insn (operands[0], operands[1]);
18971 ;; Call-value patterns last so that the wildcard operand does not
18972 ;; disrupt insn-recog's switch tables.
18974 (define_insn "*call_value_pop_0"
18975 [(set (match_operand 0 "" "")
18976 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
18977 (match_operand:SI 2 "" "")))
18978 (set (reg:SI 7) (plus:SI (reg:SI 7)
18979 (match_operand:SI 3 "immediate_operand" "")))]
18982 if (SIBLING_CALL_P (insn))
18985 return "call\t%P1";
18987 [(set_attr "type" "callv")])
18989 (define_insn "*call_value_pop_1"
18990 [(set (match_operand 0 "" "")
18991 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
18992 (match_operand:SI 2 "" "")))
18993 (set (reg:SI 7) (plus:SI (reg:SI 7)
18994 (match_operand:SI 3 "immediate_operand" "i")))]
18997 if (constant_call_address_operand (operands[1], QImode))
18999 if (SIBLING_CALL_P (insn))
19002 return "call\t%P1";
19004 if (SIBLING_CALL_P (insn))
19007 return "call\t%A1";
19009 [(set_attr "type" "callv")])
19011 (define_insn "*call_value_0"
19012 [(set (match_operand 0 "" "")
19013 (call (mem:QI (match_operand:SI 1 "constant_call_address_operand" ""))
19014 (match_operand:SI 2 "" "")))]
19017 if (SIBLING_CALL_P (insn))
19020 return "call\t%P1";
19022 [(set_attr "type" "callv")])
19024 (define_insn "*call_value_0_rex64"
19025 [(set (match_operand 0 "" "")
19026 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19027 (match_operand:DI 2 "const_int_operand" "")))]
19030 if (SIBLING_CALL_P (insn))
19033 return "call\t%P1";
19035 [(set_attr "type" "callv")])
19037 (define_insn "*call_value_1"
19038 [(set (match_operand 0 "" "")
19039 (call (mem:QI (match_operand:SI 1 "call_insn_operand" "rsm"))
19040 (match_operand:SI 2 "" "")))]
19041 "!SIBLING_CALL_P (insn) && !TARGET_64BIT"
19043 if (constant_call_address_operand (operands[1], QImode))
19044 return "call\t%P1";
19045 return "call\t%*%1";
19047 [(set_attr "type" "callv")])
19049 (define_insn "*sibcall_value_1"
19050 [(set (match_operand 0 "" "")
19051 (call (mem:QI (match_operand:SI 1 "sibcall_insn_operand" "s,c,d,a"))
19052 (match_operand:SI 2 "" "")))]
19053 "SIBLING_CALL_P (insn) && !TARGET_64BIT"
19055 if (constant_call_address_operand (operands[1], QImode))
19057 return "jmp\t%*%1";
19059 [(set_attr "type" "callv")])
19061 (define_insn "*call_value_1_rex64"
19062 [(set (match_operand 0 "" "")
19063 (call (mem:QI (match_operand:DI 1 "call_insn_operand" "rsm"))
19064 (match_operand:DI 2 "" "")))]
19065 "!SIBLING_CALL_P (insn) && TARGET_64BIT"
19067 if (constant_call_address_operand (operands[1], QImode))
19068 return "call\t%P1";
19069 return "call\t%A1";
19071 [(set_attr "type" "callv")])
19073 (define_insn "*sibcall_value_1_rex64"
19074 [(set (match_operand 0 "" "")
19075 (call (mem:QI (match_operand:DI 1 "constant_call_address_operand" ""))
19076 (match_operand:DI 2 "" "")))]
19077 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19079 [(set_attr "type" "callv")])
19081 (define_insn "*sibcall_value_1_rex64_v"
19082 [(set (match_operand 0 "" "")
19083 (call (mem:QI (reg:DI 40))
19084 (match_operand:DI 1 "" "")))]
19085 "SIBLING_CALL_P (insn) && TARGET_64BIT"
19087 [(set_attr "type" "callv")])
19089 (define_insn "trap"
19090 [(trap_if (const_int 1) (const_int 5))]
19094 ;;; ix86 doesn't have conditional trap instructions, but we fake them
19095 ;;; for the sake of bounds checking. By emitting bounds checks as
19096 ;;; conditional traps rather than as conditional jumps around
19097 ;;; unconditional traps we avoid introducing spurious basic-block
19098 ;;; boundaries and facilitate elimination of redundant checks. In
19099 ;;; honor of the too-inflexible-for-BPs `bound' instruction, we use
19102 ;;; FIXME: Static branch prediction rules for ix86 are such that
19103 ;;; forward conditional branches predict as untaken. As implemented
19104 ;;; below, pseudo conditional traps violate that rule. We should use
19105 ;;; .pushsection/.popsection to place all of the `int 5's in a special
19106 ;;; section loaded at the end of the text segment and branch forward
19107 ;;; there on bounds-failure, and then jump back immediately (in case
19108 ;;; the system chooses to ignore bounds violations, or to report
19109 ;;; violations and continue execution).
19111 (define_expand "conditional_trap"
19112 [(trap_if (match_operator 0 "comparison_operator"
19113 [(match_dup 2) (const_int 0)])
19114 (match_operand 1 "const_int_operand" ""))]
19117 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
19118 ix86_expand_compare (GET_CODE (operands[0]),
19124 (define_insn "*conditional_trap_1"
19125 [(trap_if (match_operator 0 "comparison_operator"
19126 [(reg 17) (const_int 0)])
19127 (match_operand 1 "const_int_operand" ""))]
19130 operands[2] = gen_label_rtx ();
19131 output_asm_insn ("j%c0\t%l2\; int\t%1", operands);
19132 (*targetm.asm_out.internal_label) (asm_out_file, "L",
19133 CODE_LABEL_NUMBER (operands[2]));
19137 ;; Pentium III SIMD instructions.
19139 ;; Moves for SSE/MMX regs.
19141 (define_insn "movv4sf_internal"
19142 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
19143 (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))]
19147 movaps\t{%1, %0|%0, %1}
19148 movaps\t{%1, %0|%0, %1}"
19149 [(set_attr "type" "ssemov")
19150 (set_attr "mode" "V4SF")])
19153 [(set (match_operand:V4SF 0 "register_operand" "")
19154 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
19156 [(set (match_dup 0)
19158 (vec_duplicate:V4SF (match_dup 1))
19162 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
19163 operands[2] = CONST0_RTX (V4SFmode);
19166 (define_insn "movv4si_internal"
19167 [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m")
19168 (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))]
19171 switch (which_alternative)
19174 if (get_attr_mode (insn) == MODE_V4SF)
19175 return "xorps\t%0, %0";
19177 return "pxor\t%0, %0";
19180 if (get_attr_mode (insn) == MODE_V4SF)
19181 return "movaps\t{%1, %0|%0, %1}";
19183 return "movdqa\t{%1, %0|%0, %1}";
19188 [(set_attr "type" "ssemov")
19190 (cond [(eq_attr "alternative" "0,1")
19192 (ne (symbol_ref "optimize_size")
19194 (const_string "V4SF")
19195 (const_string "TI"))
19196 (eq_attr "alternative" "2")
19198 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19200 (ne (symbol_ref "optimize_size")
19202 (const_string "V4SF")
19203 (const_string "TI"))]
19204 (const_string "TI")))])
19206 (define_insn "movv2di_internal"
19207 [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m")
19208 (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))]
19211 switch (which_alternative)
19214 if (get_attr_mode (insn) == MODE_V4SF)
19215 return "xorps\t%0, %0";
19217 return "pxor\t%0, %0";
19220 if (get_attr_mode (insn) == MODE_V4SF)
19221 return "movaps\t{%1, %0|%0, %1}";
19223 return "movdqa\t{%1, %0|%0, %1}";
19228 [(set_attr "type" "ssemov")
19230 (cond [(eq_attr "alternative" "0,1")
19232 (ne (symbol_ref "optimize_size")
19234 (const_string "V4SF")
19235 (const_string "TI"))
19236 (eq_attr "alternative" "2")
19238 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19240 (ne (symbol_ref "optimize_size")
19242 (const_string "V4SF")
19243 (const_string "TI"))]
19244 (const_string "TI")))])
19247 [(set (match_operand:V2DF 0 "register_operand" "")
19248 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
19250 [(set (match_dup 0)
19252 (vec_duplicate:V2DF (match_dup 1))
19256 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
19257 operands[2] = CONST0_RTX (V2DFmode);
19260 (define_insn "movv8qi_internal"
19261 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m")
19262 (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))]
19264 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19267 movq\t{%1, %0|%0, %1}
19268 movq\t{%1, %0|%0, %1}"
19269 [(set_attr "type" "mmxmov")
19270 (set_attr "mode" "DI")])
19272 (define_insn "movv4hi_internal"
19273 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m")
19274 (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))]
19276 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19279 movq\t{%1, %0|%0, %1}
19280 movq\t{%1, %0|%0, %1}"
19281 [(set_attr "type" "mmxmov")
19282 (set_attr "mode" "DI")])
19284 (define_insn "movv2si_internal"
19285 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m")
19286 (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))]
19288 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19291 movq\t{%1, %0|%0, %1}
19292 movq\t{%1, %0|%0, %1}"
19293 [(set_attr "type" "mmxcvt")
19294 (set_attr "mode" "DI")])
19296 (define_insn "movv2sf_internal"
19297 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m")
19298 (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))]
19300 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19303 movq\t{%1, %0|%0, %1}
19304 movq\t{%1, %0|%0, %1}"
19305 [(set_attr "type" "mmxcvt")
19306 (set_attr "mode" "DI")])
19308 (define_expand "movti"
19309 [(set (match_operand:TI 0 "nonimmediate_operand" "")
19310 (match_operand:TI 1 "nonimmediate_operand" ""))]
19311 "TARGET_SSE || TARGET_64BIT"
19314 ix86_expand_move (TImode, operands);
19316 ix86_expand_vector_move (TImode, operands);
19320 (define_insn "movv2df_internal"
19321 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
19322 (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))]
19324 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19326 switch (which_alternative)
19329 if (get_attr_mode (insn) == MODE_V4SF)
19330 return "xorps\t%0, %0";
19332 return "xorpd\t%0, %0";
19335 if (get_attr_mode (insn) == MODE_V4SF)
19336 return "movaps\t{%1, %0|%0, %1}";
19338 return "movapd\t{%1, %0|%0, %1}";
19343 [(set_attr "type" "ssemov")
19345 (cond [(eq_attr "alternative" "0,1")
19347 (ne (symbol_ref "optimize_size")
19349 (const_string "V4SF")
19350 (const_string "V2DF"))
19351 (eq_attr "alternative" "2")
19353 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19355 (ne (symbol_ref "optimize_size")
19357 (const_string "V4SF")
19358 (const_string "V2DF"))]
19359 (const_string "V2DF")))])
19361 (define_insn "movv8hi_internal"
19362 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m")
19363 (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))]
19365 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19367 switch (which_alternative)
19370 if (get_attr_mode (insn) == MODE_V4SF)
19371 return "xorps\t%0, %0";
19373 return "pxor\t%0, %0";
19376 if (get_attr_mode (insn) == MODE_V4SF)
19377 return "movaps\t{%1, %0|%0, %1}";
19379 return "movdqa\t{%1, %0|%0, %1}";
19384 [(set_attr "type" "ssemov")
19386 (cond [(eq_attr "alternative" "0,1")
19388 (ne (symbol_ref "optimize_size")
19390 (const_string "V4SF")
19391 (const_string "TI"))
19392 (eq_attr "alternative" "2")
19394 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19396 (ne (symbol_ref "optimize_size")
19398 (const_string "V4SF")
19399 (const_string "TI"))]
19400 (const_string "TI")))])
19402 (define_insn "movv16qi_internal"
19403 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m")
19404 (match_operand:V16QI 1 "nonimmediate_operand" "C,xm,x"))]
19406 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19408 switch (which_alternative)
19411 if (get_attr_mode (insn) == MODE_V4SF)
19412 return "xorps\t%0, %0";
19414 return "pxor\t%0, %0";
19417 if (get_attr_mode (insn) == MODE_V4SF)
19418 return "movaps\t{%1, %0|%0, %1}";
19420 return "movdqa\t{%1, %0|%0, %1}";
19425 [(set_attr "type" "ssemov")
19427 (cond [(eq_attr "alternative" "0,1")
19429 (ne (symbol_ref "optimize_size")
19431 (const_string "V4SF")
19432 (const_string "TI"))
19433 (eq_attr "alternative" "2")
19435 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19437 (ne (symbol_ref "optimize_size")
19439 (const_string "V4SF")
19440 (const_string "TI"))]
19441 (const_string "TI")))])
19443 (define_expand "movv2df"
19444 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
19445 (match_operand:V2DF 1 "nonimmediate_operand" ""))]
19448 ix86_expand_vector_move (V2DFmode, operands);
19452 (define_expand "movv8hi"
19453 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
19454 (match_operand:V8HI 1 "nonimmediate_operand" ""))]
19457 ix86_expand_vector_move (V8HImode, operands);
19461 (define_expand "movv16qi"
19462 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
19463 (match_operand:V16QI 1 "nonimmediate_operand" ""))]
19466 ix86_expand_vector_move (V16QImode, operands);
19470 (define_expand "movv4sf"
19471 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
19472 (match_operand:V4SF 1 "nonimmediate_operand" ""))]
19475 ix86_expand_vector_move (V4SFmode, operands);
19479 (define_expand "movv4si"
19480 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
19481 (match_operand:V4SI 1 "nonimmediate_operand" ""))]
19484 ix86_expand_vector_move (V4SImode, operands);
19488 (define_expand "movv2di"
19489 [(set (match_operand:V2DI 0 "nonimmediate_operand" "")
19490 (match_operand:V2DI 1 "nonimmediate_operand" ""))]
19493 ix86_expand_vector_move (V2DImode, operands);
19497 (define_expand "movv2si"
19498 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
19499 (match_operand:V2SI 1 "nonimmediate_operand" ""))]
19502 ix86_expand_vector_move (V2SImode, operands);
19506 (define_expand "movv4hi"
19507 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
19508 (match_operand:V4HI 1 "nonimmediate_operand" ""))]
19511 ix86_expand_vector_move (V4HImode, operands);
19515 (define_expand "movv8qi"
19516 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
19517 (match_operand:V8QI 1 "nonimmediate_operand" ""))]
19520 ix86_expand_vector_move (V8QImode, operands);
19524 (define_expand "movv2sf"
19525 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
19526 (match_operand:V2SF 1 "nonimmediate_operand" ""))]
19529 ix86_expand_vector_move (V2SFmode, operands);
19533 (define_insn "*pushti"
19534 [(set (match_operand:TI 0 "push_operand" "=<")
19535 (match_operand:TI 1 "register_operand" "x"))]
19539 (define_insn "*pushv2df"
19540 [(set (match_operand:V2DF 0 "push_operand" "=<")
19541 (match_operand:V2DF 1 "register_operand" "x"))]
19545 (define_insn "*pushv2di"
19546 [(set (match_operand:V2DI 0 "push_operand" "=<")
19547 (match_operand:V2DI 1 "register_operand" "x"))]
19551 (define_insn "*pushv8hi"
19552 [(set (match_operand:V8HI 0 "push_operand" "=<")
19553 (match_operand:V8HI 1 "register_operand" "x"))]
19557 (define_insn "*pushv16qi"
19558 [(set (match_operand:V16QI 0 "push_operand" "=<")
19559 (match_operand:V16QI 1 "register_operand" "x"))]
19563 (define_insn "*pushv4sf"
19564 [(set (match_operand:V4SF 0 "push_operand" "=<")
19565 (match_operand:V4SF 1 "register_operand" "x"))]
19569 (define_insn "*pushv4si"
19570 [(set (match_operand:V4SI 0 "push_operand" "=<")
19571 (match_operand:V4SI 1 "register_operand" "x"))]
19575 (define_insn "*pushv2si"
19576 [(set (match_operand:V2SI 0 "push_operand" "=<")
19577 (match_operand:V2SI 1 "register_operand" "y"))]
19581 (define_insn "*pushv4hi"
19582 [(set (match_operand:V4HI 0 "push_operand" "=<")
19583 (match_operand:V4HI 1 "register_operand" "y"))]
19587 (define_insn "*pushv8qi"
19588 [(set (match_operand:V8QI 0 "push_operand" "=<")
19589 (match_operand:V8QI 1 "register_operand" "y"))]
19593 (define_insn "*pushv2sf"
19594 [(set (match_operand:V2SF 0 "push_operand" "=<")
19595 (match_operand:V2SF 1 "register_operand" "y"))]
19600 [(set (match_operand 0 "push_operand" "")
19601 (match_operand 1 "register_operand" ""))]
19602 "!TARGET_64BIT && reload_completed
19603 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
19604 [(set (reg:SI 7) (plus:SI (reg:SI 7) (match_dup 3)))
19605 (set (match_dup 2) (match_dup 1))]
19606 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
19607 stack_pointer_rtx);
19608 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
19611 [(set (match_operand 0 "push_operand" "")
19612 (match_operand 1 "register_operand" ""))]
19613 "TARGET_64BIT && reload_completed
19614 && (SSE_REG_P (operands[1]) || MMX_REG_P (operands[1]))"
19615 [(set (reg:DI 7) (plus:DI (reg:DI 7) (match_dup 3)))
19616 (set (match_dup 2) (match_dup 1))]
19617 "operands[2] = change_address (operands[0], GET_MODE (operands[0]),
19618 stack_pointer_rtx);
19619 operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));")
19622 (define_insn "movti_internal"
19623 [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m")
19624 (match_operand:TI 1 "vector_move_operand" "C,xm,x"))]
19625 "TARGET_SSE && !TARGET_64BIT
19626 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19628 switch (which_alternative)
19631 if (get_attr_mode (insn) == MODE_V4SF)
19632 return "xorps\t%0, %0";
19634 return "pxor\t%0, %0";
19637 if (get_attr_mode (insn) == MODE_V4SF)
19638 return "movaps\t{%1, %0|%0, %1}";
19640 return "movdqa\t{%1, %0|%0, %1}";
19645 [(set_attr "type" "ssemov,ssemov,ssemov")
19647 (cond [(eq_attr "alternative" "0,1")
19649 (ne (symbol_ref "optimize_size")
19651 (const_string "V4SF")
19652 (const_string "TI"))
19653 (eq_attr "alternative" "2")
19655 (ne (symbol_ref "optimize_size")
19657 (const_string "V4SF")
19658 (const_string "TI"))]
19659 (const_string "TI")))])
19661 (define_insn "*movti_rex64"
19662 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,x,xm")
19663 (match_operand:TI 1 "general_operand" "riFo,riF,C,xm,x"))]
19665 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19667 switch (which_alternative)
19673 if (get_attr_mode (insn) == MODE_V4SF)
19674 return "xorps\t%0, %0";
19676 return "pxor\t%0, %0";
19679 if (get_attr_mode (insn) == MODE_V4SF)
19680 return "movaps\t{%1, %0|%0, %1}";
19682 return "movdqa\t{%1, %0|%0, %1}";
19687 [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
19689 (cond [(eq_attr "alternative" "2,3")
19691 (ne (symbol_ref "optimize_size")
19693 (const_string "V4SF")
19694 (const_string "TI"))
19695 (eq_attr "alternative" "4")
19697 (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
19699 (ne (symbol_ref "optimize_size")
19701 (const_string "V4SF")
19702 (const_string "TI"))]
19703 (const_string "DI")))])
19706 [(set (match_operand:TI 0 "nonimmediate_operand" "")
19707 (match_operand:TI 1 "general_operand" ""))]
19708 "reload_completed && !SSE_REG_P (operands[0])
19709 && !SSE_REG_P (operands[1])"
19711 "ix86_split_long_move (operands); DONE;")
19713 ;; These two patterns are useful for specifying exactly whether to use
19714 ;; movaps or movups
19715 (define_expand "sse_movaps"
19716 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
19717 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
19721 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
19723 rtx tmp = gen_reg_rtx (V4SFmode);
19724 emit_insn (gen_sse_movaps (tmp, operands[1]));
19725 emit_move_insn (operands[0], tmp);
19730 (define_insn "*sse_movaps_1"
19731 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19732 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19735 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19736 "movaps\t{%1, %0|%0, %1}"
19737 [(set_attr "type" "ssemov,ssemov")
19738 (set_attr "mode" "V4SF")])
19740 (define_expand "sse_movups"
19741 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
19742 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "")]
19746 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
19748 rtx tmp = gen_reg_rtx (V4SFmode);
19749 emit_insn (gen_sse_movups (tmp, operands[1]));
19750 emit_move_insn (operands[0], tmp);
19755 (define_insn "*sse_movups_1"
19756 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19757 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm,x")]
19760 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
19761 "movups\t{%1, %0|%0, %1}"
19762 [(set_attr "type" "ssecvt,ssecvt")
19763 (set_attr "mode" "V4SF")])
19765 ;; SSE Strange Moves.
19767 (define_insn "sse_movmskps"
19768 [(set (match_operand:SI 0 "register_operand" "=r")
19769 (unspec:SI [(match_operand:V4SF 1 "register_operand" "x")]
19772 "movmskps\t{%1, %0|%0, %1}"
19773 [(set_attr "type" "ssecvt")
19774 (set_attr "mode" "V4SF")])
19776 (define_insn "mmx_pmovmskb"
19777 [(set (match_operand:SI 0 "register_operand" "=r")
19778 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")]
19780 "TARGET_SSE || TARGET_3DNOW_A"
19781 "pmovmskb\t{%1, %0|%0, %1}"
19782 [(set_attr "type" "ssecvt")
19783 (set_attr "mode" "V4SF")])
19786 (define_insn "mmx_maskmovq"
19787 [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
19788 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19789 (match_operand:V8QI 2 "register_operand" "y")]
19791 "(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
19792 ;; @@@ check ordering of operands in intel/nonintel syntax
19793 "maskmovq\t{%2, %1|%1, %2}"
19794 [(set_attr "type" "mmxcvt")
19795 (set_attr "mode" "DI")])
19797 (define_insn "mmx_maskmovq_rex"
19798 [(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
19799 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
19800 (match_operand:V8QI 2 "register_operand" "y")]
19802 "(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
19803 ;; @@@ check ordering of operands in intel/nonintel syntax
19804 "maskmovq\t{%2, %1|%1, %2}"
19805 [(set_attr "type" "mmxcvt")
19806 (set_attr "mode" "DI")])
19808 (define_insn "sse_movntv4sf"
19809 [(set (match_operand:V4SF 0 "memory_operand" "=m")
19810 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")]
19813 "movntps\t{%1, %0|%0, %1}"
19814 [(set_attr "type" "ssemov")
19815 (set_attr "mode" "V4SF")])
19817 (define_insn "sse_movntdi"
19818 [(set (match_operand:DI 0 "memory_operand" "=m")
19819 (unspec:DI [(match_operand:DI 1 "register_operand" "y")]
19821 "TARGET_SSE || TARGET_3DNOW_A"
19822 "movntq\t{%1, %0|%0, %1}"
19823 [(set_attr "type" "mmxmov")
19824 (set_attr "mode" "DI")])
19826 (define_insn "sse_movhlps"
19827 [(set (match_operand:V4SF 0 "register_operand" "=x")
19829 (match_operand:V4SF 1 "register_operand" "0")
19830 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19831 (parallel [(const_int 2)
19837 "movhlps\t{%2, %0|%0, %2}"
19838 [(set_attr "type" "ssecvt")
19839 (set_attr "mode" "V4SF")])
19841 (define_insn "sse_movlhps"
19842 [(set (match_operand:V4SF 0 "register_operand" "=x")
19844 (match_operand:V4SF 1 "register_operand" "0")
19845 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
19846 (parallel [(const_int 2)
19852 "movlhps\t{%2, %0|%0, %2}"
19853 [(set_attr "type" "ssecvt")
19854 (set_attr "mode" "V4SF")])
19856 (define_insn "sse_movhps"
19857 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19859 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19860 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19863 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19864 "movhps\t{%2, %0|%0, %2}"
19865 [(set_attr "type" "ssecvt")
19866 (set_attr "mode" "V4SF")])
19868 (define_insn "sse_movlps"
19869 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
19871 (match_operand:V4SF 1 "nonimmediate_operand" "0,0")
19872 (match_operand:V4SF 2 "nonimmediate_operand" "m,x")
19875 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
19876 "movlps\t{%2, %0|%0, %2}"
19877 [(set_attr "type" "ssecvt")
19878 (set_attr "mode" "V4SF")])
19880 (define_expand "sse_loadss"
19881 [(match_operand:V4SF 0 "register_operand" "")
19882 (match_operand:SF 1 "memory_operand" "")]
19885 emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
19886 CONST0_RTX (V4SFmode)));
19890 (define_insn "sse_loadss_1"
19891 [(set (match_operand:V4SF 0 "register_operand" "=x")
19893 (vec_duplicate:V4SF (match_operand:SF 1 "memory_operand" "m"))
19894 (match_operand:V4SF 2 "const0_operand" "X")
19897 "movss\t{%1, %0|%0, %1}"
19898 [(set_attr "type" "ssemov")
19899 (set_attr "mode" "SF")])
19901 (define_insn "sse_movss"
19902 [(set (match_operand:V4SF 0 "register_operand" "=x")
19904 (match_operand:V4SF 1 "register_operand" "0")
19905 (match_operand:V4SF 2 "register_operand" "x")
19908 "movss\t{%2, %0|%0, %2}"
19909 [(set_attr "type" "ssemov")
19910 (set_attr "mode" "SF")])
19912 (define_insn "sse_storess"
19913 [(set (match_operand:SF 0 "memory_operand" "=m")
19915 (match_operand:V4SF 1 "register_operand" "x")
19916 (parallel [(const_int 0)])))]
19918 "movss\t{%1, %0|%0, %1}"
19919 [(set_attr "type" "ssemov")
19920 (set_attr "mode" "SF")])
19922 (define_insn "sse_shufps"
19923 [(set (match_operand:V4SF 0 "register_operand" "=x")
19924 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0")
19925 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
19926 (match_operand:SI 3 "immediate_operand" "i")]
19929 ;; @@@ check operand order for intel/nonintel syntax
19930 "shufps\t{%3, %2, %0|%0, %2, %3}"
19931 [(set_attr "type" "ssecvt")
19932 (set_attr "mode" "V4SF")])
19937 (define_insn "addv4sf3"
19938 [(set (match_operand:V4SF 0 "register_operand" "=x")
19939 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19940 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19942 "addps\t{%2, %0|%0, %2}"
19943 [(set_attr "type" "sseadd")
19944 (set_attr "mode" "V4SF")])
19946 (define_insn "vmaddv4sf3"
19947 [(set (match_operand:V4SF 0 "register_operand" "=x")
19949 (plus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19950 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19954 "addss\t{%2, %0|%0, %2}"
19955 [(set_attr "type" "sseadd")
19956 (set_attr "mode" "SF")])
19958 (define_insn "subv4sf3"
19959 [(set (match_operand:V4SF 0 "register_operand" "=x")
19960 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19961 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19963 "subps\t{%2, %0|%0, %2}"
19964 [(set_attr "type" "sseadd")
19965 (set_attr "mode" "V4SF")])
19967 (define_insn "vmsubv4sf3"
19968 [(set (match_operand:V4SF 0 "register_operand" "=x")
19970 (minus:V4SF (match_operand:V4SF 1 "register_operand" "0")
19971 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19975 "subss\t{%2, %0|%0, %2}"
19976 [(set_attr "type" "sseadd")
19977 (set_attr "mode" "SF")])
19979 (define_insn "mulv4sf3"
19980 [(set (match_operand:V4SF 0 "register_operand" "=x")
19981 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19982 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
19984 "mulps\t{%2, %0|%0, %2}"
19985 [(set_attr "type" "ssemul")
19986 (set_attr "mode" "V4SF")])
19988 (define_insn "vmmulv4sf3"
19989 [(set (match_operand:V4SF 0 "register_operand" "=x")
19991 (mult:V4SF (match_operand:V4SF 1 "register_operand" "0")
19992 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
19996 "mulss\t{%2, %0|%0, %2}"
19997 [(set_attr "type" "ssemul")
19998 (set_attr "mode" "SF")])
20000 (define_insn "divv4sf3"
20001 [(set (match_operand:V4SF 0 "register_operand" "=x")
20002 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
20003 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20005 "divps\t{%2, %0|%0, %2}"
20006 [(set_attr "type" "ssediv")
20007 (set_attr "mode" "V4SF")])
20009 (define_insn "vmdivv4sf3"
20010 [(set (match_operand:V4SF 0 "register_operand" "=x")
20012 (div:V4SF (match_operand:V4SF 1 "register_operand" "0")
20013 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20017 "divss\t{%2, %0|%0, %2}"
20018 [(set_attr "type" "ssediv")
20019 (set_attr "mode" "SF")])
20022 ;; SSE square root/reciprocal
20024 (define_insn "rcpv4sf2"
20025 [(set (match_operand:V4SF 0 "register_operand" "=x")
20027 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
20029 "rcpps\t{%1, %0|%0, %1}"
20030 [(set_attr "type" "sse")
20031 (set_attr "mode" "V4SF")])
20033 (define_insn "vmrcpv4sf2"
20034 [(set (match_operand:V4SF 0 "register_operand" "=x")
20036 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20038 (match_operand:V4SF 2 "register_operand" "0")
20041 "rcpss\t{%1, %0|%0, %1}"
20042 [(set_attr "type" "sse")
20043 (set_attr "mode" "SF")])
20045 (define_insn "rsqrtv4sf2"
20046 [(set (match_operand:V4SF 0 "register_operand" "=x")
20048 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
20050 "rsqrtps\t{%1, %0|%0, %1}"
20051 [(set_attr "type" "sse")
20052 (set_attr "mode" "V4SF")])
20054 (define_insn "vmrsqrtv4sf2"
20055 [(set (match_operand:V4SF 0 "register_operand" "=x")
20057 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20059 (match_operand:V4SF 2 "register_operand" "0")
20062 "rsqrtss\t{%1, %0|%0, %1}"
20063 [(set_attr "type" "sse")
20064 (set_attr "mode" "SF")])
20066 (define_insn "sqrtv4sf2"
20067 [(set (match_operand:V4SF 0 "register_operand" "=x")
20068 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
20070 "sqrtps\t{%1, %0|%0, %1}"
20071 [(set_attr "type" "sse")
20072 (set_attr "mode" "V4SF")])
20074 (define_insn "vmsqrtv4sf2"
20075 [(set (match_operand:V4SF 0 "register_operand" "=x")
20077 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
20078 (match_operand:V4SF 2 "register_operand" "0")
20081 "sqrtss\t{%1, %0|%0, %1}"
20082 [(set_attr "type" "sse")
20083 (set_attr "mode" "SF")])
20085 ;; SSE logical operations.
20087 ;; SSE defines logical operations on floating point values. This brings
20088 ;; interesting challenge to RTL representation where logicals are only valid
20089 ;; on integral types. We deal with this by representing the floating point
20090 ;; logical as logical on arguments casted to TImode as this is what hardware
20091 ;; really does. Unfortunately hardware requires the type information to be
20092 ;; present and thus we must avoid subregs from being simplified and eliminated
20093 ;; in later compilation phases.
20095 ;; We have following variants from each instruction:
20096 ;; sse_andsf3 - the operation taking V4SF vector operands
20097 ;; and doing TImode cast on them
20098 ;; *sse_andsf3_memory - the operation taking one memory operand casted to
20099 ;; TImode, since backend insist on eliminating casts
20100 ;; on memory operands
20101 ;; sse_andti3_sf_1 - the operation taking SF scalar operands.
20102 ;; We can not accept memory operand here as instruction reads
20103 ;; whole scalar. This is generated only post reload by GCC
20104 ;; scalar float operations that expands to logicals (fabs)
20105 ;; sse_andti3_sf_2 - the operation taking SF scalar input and TImode
20106 ;; memory operand. Eventually combine can be able
20107 ;; to synthesize these using splitter.
20108 ;; sse2_anddf3, *sse2_anddf3_memory
20111 ;; These are not called andti3 etc. because we really really don't want
20112 ;; the compiler to widen DImode ands to TImode ands and then try to move
20113 ;; into DImode subregs of SSE registers, and them together, and move out
20114 ;; of DImode subregs again!
20115 ;; SSE1 single precision floating point logical operation
20116 (define_expand "sse_andv4sf3"
20117 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
20118 (and:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
20119 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
20123 (define_insn "*sse_andv4sf3"
20124 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
20125 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20126 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20128 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20129 "andps\t{%2, %0|%0, %2}"
20130 [(set_attr "type" "sselog")
20131 (set_attr "mode" "V4SF")])
20133 (define_insn "*sse_andsf3"
20134 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
20135 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20136 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20138 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20139 "andps\t{%2, %0|%0, %2}"
20140 [(set_attr "type" "sselog")
20141 (set_attr "mode" "V4SF")])
20143 (define_expand "sse_nandv4sf3"
20144 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
20145 (and:TI (not:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0))
20146 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
20150 (define_insn "*sse_nandv4sf3"
20151 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
20152 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
20153 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20155 "andnps\t{%2, %0|%0, %2}"
20156 [(set_attr "type" "sselog")
20157 (set_attr "mode" "V4SF")])
20159 (define_insn "*sse_nandsf3"
20160 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
20161 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
20162 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20164 "andnps\t{%2, %0|%0, %2}"
20165 [(set_attr "type" "sselog")
20166 (set_attr "mode" "V4SF")])
20168 (define_expand "sse_iorv4sf3"
20169 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
20170 (ior:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
20171 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
20175 (define_insn "*sse_iorv4sf3"
20176 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
20177 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20178 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20180 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20181 "orps\t{%2, %0|%0, %2}"
20182 [(set_attr "type" "sselog")
20183 (set_attr "mode" "V4SF")])
20185 (define_insn "*sse_iorsf3"
20186 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
20187 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20188 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20190 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20191 "orps\t{%2, %0|%0, %2}"
20192 [(set_attr "type" "sselog")
20193 (set_attr "mode" "V4SF")])
20195 (define_expand "sse_xorv4sf3"
20196 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0)
20197 (xor:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)
20198 (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))]
20200 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20203 (define_insn "*sse_xorv4sf3"
20204 [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0)
20205 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20206 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20208 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20209 "xorps\t{%2, %0|%0, %2}"
20210 [(set_attr "type" "sselog")
20211 (set_attr "mode" "V4SF")])
20213 (define_insn "*sse_xorsf3"
20214 [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
20215 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20216 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20218 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20219 "xorps\t{%2, %0|%0, %2}"
20220 [(set_attr "type" "sselog")
20221 (set_attr "mode" "V4SF")])
20223 ;; SSE2 double precision floating point logical operation
20225 (define_expand "sse2_andv2df3"
20226 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
20227 (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
20228 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
20232 (define_insn "*sse2_andv2df3"
20233 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
20234 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20235 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20237 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20238 "andpd\t{%2, %0|%0, %2}"
20239 [(set_attr "type" "sselog")
20240 (set_attr "mode" "V2DF")])
20242 (define_insn "*sse2_andv2df3"
20243 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
20244 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20245 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20247 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20248 "andpd\t{%2, %0|%0, %2}"
20249 [(set_attr "type" "sselog")
20250 (set_attr "mode" "V2DF")])
20252 (define_expand "sse2_nandv2df3"
20253 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
20254 (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0))
20255 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
20259 (define_insn "*sse2_nandv2df3"
20260 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
20261 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
20262 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20264 "andnpd\t{%2, %0|%0, %2}"
20265 [(set_attr "type" "sselog")
20266 (set_attr "mode" "V2DF")])
20268 (define_insn "*sse_nandti3_df"
20269 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
20270 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
20271 (match_operand:TI 2 "nonimmediate_operand" "Ym")))]
20273 "andnpd\t{%2, %0|%0, %2}"
20274 [(set_attr "type" "sselog")
20275 (set_attr "mode" "V2DF")])
20277 (define_expand "sse2_iorv2df3"
20278 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
20279 (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)
20280 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
20284 (define_insn "*sse2_iorv2df3"
20285 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
20286 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20287 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20289 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20290 "orpd\t{%2, %0|%0, %2}"
20291 [(set_attr "type" "sselog")
20292 (set_attr "mode" "V2DF")])
20294 (define_insn "*sse2_iordf3"
20295 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
20296 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20297 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20299 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20300 "orpd\t{%2, %0|%0, %2}"
20301 [(set_attr "type" "sselog")
20302 (set_attr "mode" "V2DF")])
20304 (define_expand "sse2_xorv2df3"
20305 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0)
20306 (xor:TI (subreg:TI (match_operand:V2DF 1 "nonimmediate_operand" "") 0)
20307 (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))]
20311 (define_insn "*sse2_xorv2df3"
20312 [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0)
20313 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20314 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20316 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20317 "xorpd\t{%2, %0|%0, %2}"
20318 [(set_attr "type" "sselog")
20319 (set_attr "mode" "V2DF")])
20321 (define_insn "*sse2_xordf3"
20322 [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0)
20323 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20324 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20326 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20327 "xorpd\t{%2, %0|%0, %2}"
20328 [(set_attr "type" "sselog")
20329 (set_attr "mode" "V2DF")])
20331 ;; SSE2 integral logicals. These patterns must always come after floating
20332 ;; point ones since we don't want compiler to use integer opcodes on floating
20333 ;; point SSE values to avoid matching of subregs in the match_operand.
20334 (define_insn "*sse2_andti3"
20335 [(set (match_operand:TI 0 "register_operand" "=x")
20336 (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20337 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20339 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20340 "pand\t{%2, %0|%0, %2}"
20341 [(set_attr "type" "sselog")
20342 (set_attr "mode" "TI")])
20344 (define_insn "sse2_andv2di3"
20345 [(set (match_operand:V2DI 0 "register_operand" "=x")
20346 (and:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20347 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20349 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20350 "pand\t{%2, %0|%0, %2}"
20351 [(set_attr "type" "sselog")
20352 (set_attr "mode" "TI")])
20354 (define_insn "*sse2_nandti3"
20355 [(set (match_operand:TI 0 "register_operand" "=x")
20356 (and:TI (not:TI (match_operand:TI 1 "register_operand" "0"))
20357 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20359 "pandn\t{%2, %0|%0, %2}"
20360 [(set_attr "type" "sselog")
20361 (set_attr "mode" "TI")])
20363 (define_insn "sse2_nandv2di3"
20364 [(set (match_operand:V2DI 0 "register_operand" "=x")
20365 (and:V2DI (not:V2DI (match_operand:V2DI 1 "register_operand" "0"))
20366 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20368 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20369 "pandn\t{%2, %0|%0, %2}"
20370 [(set_attr "type" "sselog")
20371 (set_attr "mode" "TI")])
20373 (define_insn "*sse2_iorti3"
20374 [(set (match_operand:TI 0 "register_operand" "=x")
20375 (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20376 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20378 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20379 "por\t{%2, %0|%0, %2}"
20380 [(set_attr "type" "sselog")
20381 (set_attr "mode" "TI")])
20383 (define_insn "sse2_iorv2di3"
20384 [(set (match_operand:V2DI 0 "register_operand" "=x")
20385 (ior:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20386 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20388 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20389 "por\t{%2, %0|%0, %2}"
20390 [(set_attr "type" "sselog")
20391 (set_attr "mode" "TI")])
20393 (define_insn "*sse2_xorti3"
20394 [(set (match_operand:TI 0 "register_operand" "=x")
20395 (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
20396 (match_operand:TI 2 "nonimmediate_operand" "xm")))]
20398 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20399 "pxor\t{%2, %0|%0, %2}"
20400 [(set_attr "type" "sselog")
20401 (set_attr "mode" "TI")])
20403 (define_insn "sse2_xorv2di3"
20404 [(set (match_operand:V2DI 0 "register_operand" "=x")
20405 (xor:V2DI (match_operand:V2DI 1 "nonimmediate_operand" "%0")
20406 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
20408 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
20409 "pxor\t{%2, %0|%0, %2}"
20410 [(set_attr "type" "sselog")
20411 (set_attr "mode" "TI")])
20413 ;; Use xor, but don't show input operands so they aren't live before
20415 (define_insn "sse_clrv4sf"
20416 [(set (match_operand:V4SF 0 "register_operand" "=x")
20417 (match_operand:V4SF 1 "const0_operand" "X"))]
20420 if (get_attr_mode (insn) == MODE_TI)
20421 return "pxor\t{%0, %0|%0, %0}";
20423 return "xorps\t{%0, %0|%0, %0}";
20425 [(set_attr "type" "sselog")
20426 (set_attr "memory" "none")
20429 (and (and (ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
20431 (ne (symbol_ref "TARGET_SSE2")
20433 (eq (symbol_ref "optimize_size")
20435 (const_string "TI")
20436 (const_string "V4SF")))])
20438 ;; Use xor, but don't show input operands so they aren't live before
20440 (define_insn "sse_clrv2df"
20441 [(set (match_operand:V2DF 0 "register_operand" "=x")
20442 (unspec:V2DF [(const_int 0)] UNSPEC_NOP))]
20444 "xorpd\t{%0, %0|%0, %0}"
20445 [(set_attr "type" "sselog")
20446 (set_attr "memory" "none")
20447 (set_attr "mode" "V4SF")])
20449 ;; SSE mask-generating compares
20451 (define_insn "maskcmpv4sf3"
20452 [(set (match_operand:V4SI 0 "register_operand" "=x")
20453 (match_operator:V4SI 3 "sse_comparison_operator"
20454 [(match_operand:V4SF 1 "register_operand" "0")
20455 (match_operand:V4SF 2 "register_operand" "x")]))]
20457 "cmp%D3ps\t{%2, %0|%0, %2}"
20458 [(set_attr "type" "ssecmp")
20459 (set_attr "mode" "V4SF")])
20461 (define_insn "maskncmpv4sf3"
20462 [(set (match_operand:V4SI 0 "register_operand" "=x")
20464 (match_operator:V4SI 3 "sse_comparison_operator"
20465 [(match_operand:V4SF 1 "register_operand" "0")
20466 (match_operand:V4SF 2 "register_operand" "x")])))]
20469 if (GET_CODE (operands[3]) == UNORDERED)
20470 return "cmpordps\t{%2, %0|%0, %2}";
20472 return "cmpn%D3ps\t{%2, %0|%0, %2}";
20474 [(set_attr "type" "ssecmp")
20475 (set_attr "mode" "V4SF")])
20477 (define_insn "vmmaskcmpv4sf3"
20478 [(set (match_operand:V4SI 0 "register_operand" "=x")
20480 (match_operator:V4SI 3 "sse_comparison_operator"
20481 [(match_operand:V4SF 1 "register_operand" "0")
20482 (match_operand:V4SF 2 "register_operand" "x")])
20483 (subreg:V4SI (match_dup 1) 0)
20486 "cmp%D3ss\t{%2, %0|%0, %2}"
20487 [(set_attr "type" "ssecmp")
20488 (set_attr "mode" "SF")])
20490 (define_insn "vmmaskncmpv4sf3"
20491 [(set (match_operand:V4SI 0 "register_operand" "=x")
20494 (match_operator:V4SI 3 "sse_comparison_operator"
20495 [(match_operand:V4SF 1 "register_operand" "0")
20496 (match_operand:V4SF 2 "register_operand" "x")]))
20497 (subreg:V4SI (match_dup 1) 0)
20501 if (GET_CODE (operands[3]) == UNORDERED)
20502 return "cmpordss\t{%2, %0|%0, %2}";
20504 return "cmpn%D3ss\t{%2, %0|%0, %2}";
20506 [(set_attr "type" "ssecmp")
20507 (set_attr "mode" "SF")])
20509 (define_insn "sse_comi"
20510 [(set (reg:CCFP 17)
20511 (compare:CCFP (vec_select:SF
20512 (match_operand:V4SF 0 "register_operand" "x")
20513 (parallel [(const_int 0)]))
20515 (match_operand:V4SF 1 "register_operand" "x")
20516 (parallel [(const_int 0)]))))]
20518 "comiss\t{%1, %0|%0, %1}"
20519 [(set_attr "type" "ssecomi")
20520 (set_attr "mode" "SF")])
20522 (define_insn "sse_ucomi"
20523 [(set (reg:CCFPU 17)
20524 (compare:CCFPU (vec_select:SF
20525 (match_operand:V4SF 0 "register_operand" "x")
20526 (parallel [(const_int 0)]))
20528 (match_operand:V4SF 1 "register_operand" "x")
20529 (parallel [(const_int 0)]))))]
20531 "ucomiss\t{%1, %0|%0, %1}"
20532 [(set_attr "type" "ssecomi")
20533 (set_attr "mode" "SF")])
20538 (define_insn "sse_unpckhps"
20539 [(set (match_operand:V4SF 0 "register_operand" "=x")
20541 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
20542 (parallel [(const_int 2)
20546 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20547 (parallel [(const_int 0)
20553 "unpckhps\t{%2, %0|%0, %2}"
20554 [(set_attr "type" "ssecvt")
20555 (set_attr "mode" "V4SF")])
20557 (define_insn "sse_unpcklps"
20558 [(set (match_operand:V4SF 0 "register_operand" "=x")
20560 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "0")
20561 (parallel [(const_int 0)
20565 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "x")
20566 (parallel [(const_int 2)
20572 "unpcklps\t{%2, %0|%0, %2}"
20573 [(set_attr "type" "ssecvt")
20574 (set_attr "mode" "V4SF")])
20579 (define_insn "smaxv4sf3"
20580 [(set (match_operand:V4SF 0 "register_operand" "=x")
20581 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
20582 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20584 "maxps\t{%2, %0|%0, %2}"
20585 [(set_attr "type" "sse")
20586 (set_attr "mode" "V4SF")])
20588 (define_insn "vmsmaxv4sf3"
20589 [(set (match_operand:V4SF 0 "register_operand" "=x")
20591 (smax:V4SF (match_operand:V4SF 1 "register_operand" "0")
20592 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20596 "maxss\t{%2, %0|%0, %2}"
20597 [(set_attr "type" "sse")
20598 (set_attr "mode" "SF")])
20600 (define_insn "sminv4sf3"
20601 [(set (match_operand:V4SF 0 "register_operand" "=x")
20602 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
20603 (match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
20605 "minps\t{%2, %0|%0, %2}"
20606 [(set_attr "type" "sse")
20607 (set_attr "mode" "V4SF")])
20609 (define_insn "vmsminv4sf3"
20610 [(set (match_operand:V4SF 0 "register_operand" "=x")
20612 (smin:V4SF (match_operand:V4SF 1 "register_operand" "0")
20613 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
20617 "minss\t{%2, %0|%0, %2}"
20618 [(set_attr "type" "sse")
20619 (set_attr "mode" "SF")])
20621 ;; SSE <-> integer/MMX conversions
20623 (define_insn "cvtpi2ps"
20624 [(set (match_operand:V4SF 0 "register_operand" "=x")
20626 (match_operand:V4SF 1 "register_operand" "0")
20627 (vec_duplicate:V4SF
20628 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
20631 "cvtpi2ps\t{%2, %0|%0, %2}"
20632 [(set_attr "type" "ssecvt")
20633 (set_attr "mode" "V4SF")])
20635 (define_insn "cvtps2pi"
20636 [(set (match_operand:V2SI 0 "register_operand" "=y")
20638 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
20639 (parallel [(const_int 0) (const_int 1)])))]
20641 "cvtps2pi\t{%1, %0|%0, %1}"
20642 [(set_attr "type" "ssecvt")
20643 (set_attr "mode" "V4SF")])
20645 (define_insn "cvttps2pi"
20646 [(set (match_operand:V2SI 0 "register_operand" "=y")
20648 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
20650 (parallel [(const_int 0) (const_int 1)])))]
20652 "cvttps2pi\t{%1, %0|%0, %1}"
20653 [(set_attr "type" "ssecvt")
20654 (set_attr "mode" "SF")])
20656 (define_insn "cvtsi2ss"
20657 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
20659 (match_operand:V4SF 1 "register_operand" "0,0")
20660 (vec_duplicate:V4SF
20661 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
20664 "cvtsi2ss\t{%2, %0|%0, %2}"
20665 [(set_attr "type" "sseicvt")
20666 (set_attr "athlon_decode" "vector,double")
20667 (set_attr "mode" "SF")])
20669 (define_insn "cvtsi2ssq"
20670 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
20672 (match_operand:V4SF 1 "register_operand" "0,0")
20673 (vec_duplicate:V4SF
20674 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
20676 "TARGET_SSE && TARGET_64BIT"
20677 "cvtsi2ssq\t{%2, %0|%0, %2}"
20678 [(set_attr "type" "sseicvt")
20679 (set_attr "athlon_decode" "vector,double")
20680 (set_attr "mode" "SF")])
20682 (define_insn "cvtss2si"
20683 [(set (match_operand:SI 0 "register_operand" "=r,r")
20685 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20686 (parallel [(const_int 0)])))]
20688 "cvtss2si\t{%1, %0|%0, %1}"
20689 [(set_attr "type" "sseicvt")
20690 (set_attr "athlon_decode" "double,vector")
20691 (set_attr "mode" "SI")])
20693 (define_insn "cvtss2siq"
20694 [(set (match_operand:DI 0 "register_operand" "=r,r")
20696 (fix:V4DI (match_operand:V4SF 1 "nonimmediate_operand" "x,m"))
20697 (parallel [(const_int 0)])))]
20699 "cvtss2siq\t{%1, %0|%0, %1}"
20700 [(set_attr "type" "sseicvt")
20701 (set_attr "athlon_decode" "double,vector")
20702 (set_attr "mode" "DI")])
20704 (define_insn "cvttss2si"
20705 [(set (match_operand:SI 0 "register_operand" "=r,r")
20707 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20709 (parallel [(const_int 0)])))]
20711 "cvttss2si\t{%1, %0|%0, %1}"
20712 [(set_attr "type" "sseicvt")
20713 (set_attr "mode" "SF")
20714 (set_attr "athlon_decode" "double,vector")])
20716 (define_insn "cvttss2siq"
20717 [(set (match_operand:DI 0 "register_operand" "=r,r")
20719 (unspec:V4DI [(match_operand:V4SF 1 "nonimmediate_operand" "x,xm")]
20721 (parallel [(const_int 0)])))]
20722 "TARGET_SSE && TARGET_64BIT"
20723 "cvttss2siq\t{%1, %0|%0, %1}"
20724 [(set_attr "type" "sseicvt")
20725 (set_attr "mode" "SF")
20726 (set_attr "athlon_decode" "double,vector")])
20733 (define_insn "addv8qi3"
20734 [(set (match_operand:V8QI 0 "register_operand" "=y")
20735 (plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20736 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20738 "paddb\t{%2, %0|%0, %2}"
20739 [(set_attr "type" "mmxadd")
20740 (set_attr "mode" "DI")])
20742 (define_insn "addv4hi3"
20743 [(set (match_operand:V4HI 0 "register_operand" "=y")
20744 (plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20745 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20747 "paddw\t{%2, %0|%0, %2}"
20748 [(set_attr "type" "mmxadd")
20749 (set_attr "mode" "DI")])
20751 (define_insn "addv2si3"
20752 [(set (match_operand:V2SI 0 "register_operand" "=y")
20753 (plus:V2SI (match_operand:V2SI 1 "register_operand" "%0")
20754 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20756 "paddd\t{%2, %0|%0, %2}"
20757 [(set_attr "type" "mmxadd")
20758 (set_attr "mode" "DI")])
20760 (define_insn "mmx_adddi3"
20761 [(set (match_operand:DI 0 "register_operand" "=y")
20763 [(plus:DI (match_operand:DI 1 "register_operand" "%0")
20764 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20767 "paddq\t{%2, %0|%0, %2}"
20768 [(set_attr "type" "mmxadd")
20769 (set_attr "mode" "DI")])
20771 (define_insn "ssaddv8qi3"
20772 [(set (match_operand:V8QI 0 "register_operand" "=y")
20773 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20774 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20776 "paddsb\t{%2, %0|%0, %2}"
20777 [(set_attr "type" "mmxadd")
20778 (set_attr "mode" "DI")])
20780 (define_insn "ssaddv4hi3"
20781 [(set (match_operand:V4HI 0 "register_operand" "=y")
20782 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20783 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20785 "paddsw\t{%2, %0|%0, %2}"
20786 [(set_attr "type" "mmxadd")
20787 (set_attr "mode" "DI")])
20789 (define_insn "usaddv8qi3"
20790 [(set (match_operand:V8QI 0 "register_operand" "=y")
20791 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "%0")
20792 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20794 "paddusb\t{%2, %0|%0, %2}"
20795 [(set_attr "type" "mmxadd")
20796 (set_attr "mode" "DI")])
20798 (define_insn "usaddv4hi3"
20799 [(set (match_operand:V4HI 0 "register_operand" "=y")
20800 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "%0")
20801 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20803 "paddusw\t{%2, %0|%0, %2}"
20804 [(set_attr "type" "mmxadd")
20805 (set_attr "mode" "DI")])
20807 (define_insn "subv8qi3"
20808 [(set (match_operand:V8QI 0 "register_operand" "=y")
20809 (minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20810 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20812 "psubb\t{%2, %0|%0, %2}"
20813 [(set_attr "type" "mmxadd")
20814 (set_attr "mode" "DI")])
20816 (define_insn "subv4hi3"
20817 [(set (match_operand:V4HI 0 "register_operand" "=y")
20818 (minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20819 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20821 "psubw\t{%2, %0|%0, %2}"
20822 [(set_attr "type" "mmxadd")
20823 (set_attr "mode" "DI")])
20825 (define_insn "subv2si3"
20826 [(set (match_operand:V2SI 0 "register_operand" "=y")
20827 (minus:V2SI (match_operand:V2SI 1 "register_operand" "0")
20828 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
20830 "psubd\t{%2, %0|%0, %2}"
20831 [(set_attr "type" "mmxadd")
20832 (set_attr "mode" "DI")])
20834 (define_insn "mmx_subdi3"
20835 [(set (match_operand:DI 0 "register_operand" "=y")
20837 [(minus:DI (match_operand:DI 1 "register_operand" "0")
20838 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20841 "psubq\t{%2, %0|%0, %2}"
20842 [(set_attr "type" "mmxadd")
20843 (set_attr "mode" "DI")])
20845 (define_insn "sssubv8qi3"
20846 [(set (match_operand:V8QI 0 "register_operand" "=y")
20847 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20848 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20850 "psubsb\t{%2, %0|%0, %2}"
20851 [(set_attr "type" "mmxadd")
20852 (set_attr "mode" "DI")])
20854 (define_insn "sssubv4hi3"
20855 [(set (match_operand:V4HI 0 "register_operand" "=y")
20856 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20857 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20859 "psubsw\t{%2, %0|%0, %2}"
20860 [(set_attr "type" "mmxadd")
20861 (set_attr "mode" "DI")])
20863 (define_insn "ussubv8qi3"
20864 [(set (match_operand:V8QI 0 "register_operand" "=y")
20865 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "0")
20866 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
20868 "psubusb\t{%2, %0|%0, %2}"
20869 [(set_attr "type" "mmxadd")
20870 (set_attr "mode" "DI")])
20872 (define_insn "ussubv4hi3"
20873 [(set (match_operand:V4HI 0 "register_operand" "=y")
20874 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "0")
20875 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20877 "psubusw\t{%2, %0|%0, %2}"
20878 [(set_attr "type" "mmxadd")
20879 (set_attr "mode" "DI")])
20881 (define_insn "mulv4hi3"
20882 [(set (match_operand:V4HI 0 "register_operand" "=y")
20883 (mult:V4HI (match_operand:V4HI 1 "register_operand" "0")
20884 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
20886 "pmullw\t{%2, %0|%0, %2}"
20887 [(set_attr "type" "mmxmul")
20888 (set_attr "mode" "DI")])
20890 (define_insn "smulv4hi3_highpart"
20891 [(set (match_operand:V4HI 0 "register_operand" "=y")
20894 (mult:V4SI (sign_extend:V4SI
20895 (match_operand:V4HI 1 "register_operand" "0"))
20897 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20900 "pmulhw\t{%2, %0|%0, %2}"
20901 [(set_attr "type" "mmxmul")
20902 (set_attr "mode" "DI")])
20904 (define_insn "umulv4hi3_highpart"
20905 [(set (match_operand:V4HI 0 "register_operand" "=y")
20908 (mult:V4SI (zero_extend:V4SI
20909 (match_operand:V4HI 1 "register_operand" "0"))
20911 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
20913 "TARGET_SSE || TARGET_3DNOW_A"
20914 "pmulhuw\t{%2, %0|%0, %2}"
20915 [(set_attr "type" "mmxmul")
20916 (set_attr "mode" "DI")])
20918 (define_insn "mmx_pmaddwd"
20919 [(set (match_operand:V2SI 0 "register_operand" "=y")
20923 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "0")
20924 (parallel [(const_int 0) (const_int 2)])))
20926 (vec_select:V2HI (match_operand:V4HI 2 "nonimmediate_operand" "ym")
20927 (parallel [(const_int 0) (const_int 2)]))))
20929 (sign_extend:V2SI (vec_select:V2HI (match_dup 1)
20930 (parallel [(const_int 1)
20932 (sign_extend:V2SI (vec_select:V2HI (match_dup 2)
20933 (parallel [(const_int 1)
20934 (const_int 3)]))))))]
20936 "pmaddwd\t{%2, %0|%0, %2}"
20937 [(set_attr "type" "mmxmul")
20938 (set_attr "mode" "DI")])
20941 ;; MMX logical operations
20942 ;; Note we don't want to declare these as regular iordi3 insns to prevent
20943 ;; normal code that also wants to use the FPU from getting broken.
20944 ;; The UNSPECs are there to prevent the combiner from getting overly clever.
20945 (define_insn "mmx_iordi3"
20946 [(set (match_operand:DI 0 "register_operand" "=y")
20948 [(ior:DI (match_operand:DI 1 "register_operand" "%0")
20949 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20952 "por\t{%2, %0|%0, %2}"
20953 [(set_attr "type" "mmxadd")
20954 (set_attr "mode" "DI")])
20956 (define_insn "mmx_xordi3"
20957 [(set (match_operand:DI 0 "register_operand" "=y")
20959 [(xor:DI (match_operand:DI 1 "register_operand" "%0")
20960 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20963 "pxor\t{%2, %0|%0, %2}"
20964 [(set_attr "type" "mmxadd")
20965 (set_attr "mode" "DI")
20966 (set_attr "memory" "none")])
20968 ;; Same as pxor, but don't show input operands so that we don't think
20970 (define_insn "mmx_clrdi"
20971 [(set (match_operand:DI 0 "register_operand" "=y")
20972 (unspec:DI [(const_int 0)] UNSPEC_NOP))]
20974 "pxor\t{%0, %0|%0, %0}"
20975 [(set_attr "type" "mmxadd")
20976 (set_attr "mode" "DI")
20977 (set_attr "memory" "none")])
20979 (define_insn "mmx_anddi3"
20980 [(set (match_operand:DI 0 "register_operand" "=y")
20982 [(and:DI (match_operand:DI 1 "register_operand" "%0")
20983 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20986 "pand\t{%2, %0|%0, %2}"
20987 [(set_attr "type" "mmxadd")
20988 (set_attr "mode" "DI")])
20990 (define_insn "mmx_nanddi3"
20991 [(set (match_operand:DI 0 "register_operand" "=y")
20993 [(and:DI (not:DI (match_operand:DI 1 "register_operand" "0"))
20994 (match_operand:DI 2 "nonimmediate_operand" "ym"))]
20997 "pandn\t{%2, %0|%0, %2}"
20998 [(set_attr "type" "mmxadd")
20999 (set_attr "mode" "DI")])
21002 ;; MMX unsigned averages/sum of absolute differences
21004 (define_insn "mmx_uavgv8qi3"
21005 [(set (match_operand:V8QI 0 "register_operand" "=y")
21007 (plus:V8QI (plus:V8QI
21008 (match_operand:V8QI 1 "register_operand" "0")
21009 (match_operand:V8QI 2 "nonimmediate_operand" "ym"))
21010 (const_vector:V8QI [(const_int 1)
21019 "TARGET_SSE || TARGET_3DNOW_A"
21020 "pavgb\t{%2, %0|%0, %2}"
21021 [(set_attr "type" "mmxshft")
21022 (set_attr "mode" "DI")])
21024 (define_insn "mmx_uavgv4hi3"
21025 [(set (match_operand:V4HI 0 "register_operand" "=y")
21027 (plus:V4HI (plus:V4HI
21028 (match_operand:V4HI 1 "register_operand" "0")
21029 (match_operand:V4HI 2 "nonimmediate_operand" "ym"))
21030 (const_vector:V4HI [(const_int 1)
21035 "TARGET_SSE || TARGET_3DNOW_A"
21036 "pavgw\t{%2, %0|%0, %2}"
21037 [(set_attr "type" "mmxshft")
21038 (set_attr "mode" "DI")])
21040 (define_insn "mmx_psadbw"
21041 [(set (match_operand:DI 0 "register_operand" "=y")
21042 (unspec:DI [(match_operand:V8QI 1 "register_operand" "0")
21043 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
21045 "TARGET_SSE || TARGET_3DNOW_A"
21046 "psadbw\t{%2, %0|%0, %2}"
21047 [(set_attr "type" "mmxshft")
21048 (set_attr "mode" "DI")])
21051 ;; MMX insert/extract/shuffle
21053 (define_insn "mmx_pinsrw"
21054 [(set (match_operand:V4HI 0 "register_operand" "=y")
21055 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
21056 (vec_duplicate:V4HI
21057 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
21058 (match_operand:SI 3 "immediate_operand" "i")))]
21059 "TARGET_SSE || TARGET_3DNOW_A"
21060 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
21061 [(set_attr "type" "mmxcvt")
21062 (set_attr "mode" "DI")])
21064 (define_insn "mmx_pextrw"
21065 [(set (match_operand:SI 0 "register_operand" "=r")
21066 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
21068 [(match_operand:SI 2 "immediate_operand" "i")]))))]
21069 "TARGET_SSE || TARGET_3DNOW_A"
21070 "pextrw\t{%2, %1, %0|%0, %1, %2}"
21071 [(set_attr "type" "mmxcvt")
21072 (set_attr "mode" "DI")])
21074 (define_insn "mmx_pshufw"
21075 [(set (match_operand:V4HI 0 "register_operand" "=y")
21076 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "0")
21077 (match_operand:SI 2 "immediate_operand" "i")]
21079 "TARGET_SSE || TARGET_3DNOW_A"
21080 "pshufw\t{%2, %1, %0|%0, %1, %2}"
21081 [(set_attr "type" "mmxcvt")
21082 (set_attr "mode" "DI")])
21085 ;; MMX mask-generating comparisons
21087 (define_insn "eqv8qi3"
21088 [(set (match_operand:V8QI 0 "register_operand" "=y")
21089 (eq:V8QI (match_operand:V8QI 1 "register_operand" "0")
21090 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21092 "pcmpeqb\t{%2, %0|%0, %2}"
21093 [(set_attr "type" "mmxcmp")
21094 (set_attr "mode" "DI")])
21096 (define_insn "eqv4hi3"
21097 [(set (match_operand:V4HI 0 "register_operand" "=y")
21098 (eq:V4HI (match_operand:V4HI 1 "register_operand" "0")
21099 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21101 "pcmpeqw\t{%2, %0|%0, %2}"
21102 [(set_attr "type" "mmxcmp")
21103 (set_attr "mode" "DI")])
21105 (define_insn "eqv2si3"
21106 [(set (match_operand:V2SI 0 "register_operand" "=y")
21107 (eq:V2SI (match_operand:V2SI 1 "register_operand" "0")
21108 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21110 "pcmpeqd\t{%2, %0|%0, %2}"
21111 [(set_attr "type" "mmxcmp")
21112 (set_attr "mode" "DI")])
21114 (define_insn "gtv8qi3"
21115 [(set (match_operand:V8QI 0 "register_operand" "=y")
21116 (gt:V8QI (match_operand:V8QI 1 "register_operand" "0")
21117 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21119 "pcmpgtb\t{%2, %0|%0, %2}"
21120 [(set_attr "type" "mmxcmp")
21121 (set_attr "mode" "DI")])
21123 (define_insn "gtv4hi3"
21124 [(set (match_operand:V4HI 0 "register_operand" "=y")
21125 (gt:V4HI (match_operand:V4HI 1 "register_operand" "0")
21126 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21128 "pcmpgtw\t{%2, %0|%0, %2}"
21129 [(set_attr "type" "mmxcmp")
21130 (set_attr "mode" "DI")])
21132 (define_insn "gtv2si3"
21133 [(set (match_operand:V2SI 0 "register_operand" "=y")
21134 (gt:V2SI (match_operand:V2SI 1 "register_operand" "0")
21135 (match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
21137 "pcmpgtd\t{%2, %0|%0, %2}"
21138 [(set_attr "type" "mmxcmp")
21139 (set_attr "mode" "DI")])
21142 ;; MMX max/min insns
21144 (define_insn "umaxv8qi3"
21145 [(set (match_operand:V8QI 0 "register_operand" "=y")
21146 (umax:V8QI (match_operand:V8QI 1 "register_operand" "0")
21147 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21148 "TARGET_SSE || TARGET_3DNOW_A"
21149 "pmaxub\t{%2, %0|%0, %2}"
21150 [(set_attr "type" "mmxadd")
21151 (set_attr "mode" "DI")])
21153 (define_insn "smaxv4hi3"
21154 [(set (match_operand:V4HI 0 "register_operand" "=y")
21155 (smax:V4HI (match_operand:V4HI 1 "register_operand" "0")
21156 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21157 "TARGET_SSE || TARGET_3DNOW_A"
21158 "pmaxsw\t{%2, %0|%0, %2}"
21159 [(set_attr "type" "mmxadd")
21160 (set_attr "mode" "DI")])
21162 (define_insn "uminv8qi3"
21163 [(set (match_operand:V8QI 0 "register_operand" "=y")
21164 (umin:V8QI (match_operand:V8QI 1 "register_operand" "0")
21165 (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
21166 "TARGET_SSE || TARGET_3DNOW_A"
21167 "pminub\t{%2, %0|%0, %2}"
21168 [(set_attr "type" "mmxadd")
21169 (set_attr "mode" "DI")])
21171 (define_insn "sminv4hi3"
21172 [(set (match_operand:V4HI 0 "register_operand" "=y")
21173 (smin:V4HI (match_operand:V4HI 1 "register_operand" "0")
21174 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
21175 "TARGET_SSE || TARGET_3DNOW_A"
21176 "pminsw\t{%2, %0|%0, %2}"
21177 [(set_attr "type" "mmxadd")
21178 (set_attr "mode" "DI")])
21183 (define_insn "ashrv4hi3"
21184 [(set (match_operand:V4HI 0 "register_operand" "=y")
21185 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
21186 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21188 "psraw\t{%2, %0|%0, %2}"
21189 [(set_attr "type" "mmxshft")
21190 (set_attr "mode" "DI")])
21192 (define_insn "ashrv2si3"
21193 [(set (match_operand:V2SI 0 "register_operand" "=y")
21194 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
21195 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21197 "psrad\t{%2, %0|%0, %2}"
21198 [(set_attr "type" "mmxshft")
21199 (set_attr "mode" "DI")])
21201 (define_insn "lshrv4hi3"
21202 [(set (match_operand:V4HI 0 "register_operand" "=y")
21203 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "0")
21204 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21206 "psrlw\t{%2, %0|%0, %2}"
21207 [(set_attr "type" "mmxshft")
21208 (set_attr "mode" "DI")])
21210 (define_insn "lshrv2si3"
21211 [(set (match_operand:V2SI 0 "register_operand" "=y")
21212 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "0")
21213 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21215 "psrld\t{%2, %0|%0, %2}"
21216 [(set_attr "type" "mmxshft")
21217 (set_attr "mode" "DI")])
21219 ;; See logical MMX insns.
21220 (define_insn "mmx_lshrdi3"
21221 [(set (match_operand:DI 0 "register_operand" "=y")
21223 [(lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
21224 (match_operand:DI 2 "nonmemory_operand" "yi"))]
21227 "psrlq\t{%2, %0|%0, %2}"
21228 [(set_attr "type" "mmxshft")
21229 (set_attr "mode" "DI")])
21231 (define_insn "ashlv4hi3"
21232 [(set (match_operand:V4HI 0 "register_operand" "=y")
21233 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "0")
21234 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21236 "psllw\t{%2, %0|%0, %2}"
21237 [(set_attr "type" "mmxshft")
21238 (set_attr "mode" "DI")])
21240 (define_insn "ashlv2si3"
21241 [(set (match_operand:V2SI 0 "register_operand" "=y")
21242 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "0")
21243 (match_operand:DI 2 "nonmemory_operand" "yi")))]
21245 "pslld\t{%2, %0|%0, %2}"
21246 [(set_attr "type" "mmxshft")
21247 (set_attr "mode" "DI")])
21249 ;; See logical MMX insns.
21250 (define_insn "mmx_ashldi3"
21251 [(set (match_operand:DI 0 "register_operand" "=y")
21253 [(ashift:DI (match_operand:DI 1 "register_operand" "0")
21254 (match_operand:DI 2 "nonmemory_operand" "yi"))]
21257 "psllq\t{%2, %0|%0, %2}"
21258 [(set_attr "type" "mmxshft")
21259 (set_attr "mode" "DI")])
21262 ;; MMX pack/unpack insns.
21264 (define_insn "mmx_packsswb"
21265 [(set (match_operand:V8QI 0 "register_operand" "=y")
21267 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
21268 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
21270 "packsswb\t{%2, %0|%0, %2}"
21271 [(set_attr "type" "mmxshft")
21272 (set_attr "mode" "DI")])
21274 (define_insn "mmx_packssdw"
21275 [(set (match_operand:V4HI 0 "register_operand" "=y")
21277 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "0"))
21278 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
21280 "packssdw\t{%2, %0|%0, %2}"
21281 [(set_attr "type" "mmxshft")
21282 (set_attr "mode" "DI")])
21284 (define_insn "mmx_packuswb"
21285 [(set (match_operand:V8QI 0 "register_operand" "=y")
21287 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "0"))
21288 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
21290 "packuswb\t{%2, %0|%0, %2}"
21291 [(set_attr "type" "mmxshft")
21292 (set_attr "mode" "DI")])
21294 (define_insn "mmx_punpckhbw"
21295 [(set (match_operand:V8QI 0 "register_operand" "=y")
21297 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
21298 (parallel [(const_int 4)
21306 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
21307 (parallel [(const_int 0)
21317 "punpckhbw\t{%2, %0|%0, %2}"
21318 [(set_attr "type" "mmxcvt")
21319 (set_attr "mode" "DI")])
21321 (define_insn "mmx_punpckhwd"
21322 [(set (match_operand:V4HI 0 "register_operand" "=y")
21324 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
21325 (parallel [(const_int 0)
21329 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
21330 (parallel [(const_int 2)
21336 "punpckhwd\t{%2, %0|%0, %2}"
21337 [(set_attr "type" "mmxcvt")
21338 (set_attr "mode" "DI")])
21340 (define_insn "mmx_punpckhdq"
21341 [(set (match_operand:V2SI 0 "register_operand" "=y")
21343 (match_operand:V2SI 1 "register_operand" "0")
21344 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
21345 (parallel [(const_int 1)
21349 "punpckhdq\t{%2, %0|%0, %2}"
21350 [(set_attr "type" "mmxcvt")
21351 (set_attr "mode" "DI")])
21353 (define_insn "mmx_punpcklbw"
21354 [(set (match_operand:V8QI 0 "register_operand" "=y")
21356 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "0")
21357 (parallel [(const_int 0)
21365 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
21366 (parallel [(const_int 4)
21376 "punpcklbw\t{%2, %0|%0, %2}"
21377 [(set_attr "type" "mmxcvt")
21378 (set_attr "mode" "DI")])
21380 (define_insn "mmx_punpcklwd"
21381 [(set (match_operand:V4HI 0 "register_operand" "=y")
21383 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "0")
21384 (parallel [(const_int 2)
21388 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
21389 (parallel [(const_int 0)
21395 "punpcklwd\t{%2, %0|%0, %2}"
21396 [(set_attr "type" "mmxcvt")
21397 (set_attr "mode" "DI")])
21399 (define_insn "mmx_punpckldq"
21400 [(set (match_operand:V2SI 0 "register_operand" "=y")
21402 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "0")
21403 (parallel [(const_int 1)
21405 (match_operand:V2SI 2 "register_operand" "y")
21408 "punpckldq\t{%2, %0|%0, %2}"
21409 [(set_attr "type" "mmxcvt")
21410 (set_attr "mode" "DI")])
21413 ;; Miscellaneous stuff
21415 (define_insn "emms"
21416 [(unspec_volatile [(const_int 0)] UNSPECV_EMMS)
21417 (clobber (reg:XF 8))
21418 (clobber (reg:XF 9))
21419 (clobber (reg:XF 10))
21420 (clobber (reg:XF 11))
21421 (clobber (reg:XF 12))
21422 (clobber (reg:XF 13))
21423 (clobber (reg:XF 14))
21424 (clobber (reg:XF 15))
21425 (clobber (reg:DI 29))
21426 (clobber (reg:DI 30))
21427 (clobber (reg:DI 31))
21428 (clobber (reg:DI 32))
21429 (clobber (reg:DI 33))
21430 (clobber (reg:DI 34))
21431 (clobber (reg:DI 35))
21432 (clobber (reg:DI 36))]
21435 [(set_attr "type" "mmx")
21436 (set_attr "memory" "unknown")])
21438 (define_insn "ldmxcsr"
21439 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
21443 [(set_attr "type" "sse")
21444 (set_attr "memory" "load")])
21446 (define_insn "stmxcsr"
21447 [(set (match_operand:SI 0 "memory_operand" "=m")
21448 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
21451 [(set_attr "type" "sse")
21452 (set_attr "memory" "store")])
21454 (define_expand "sfence"
21455 [(set (match_dup 0)
21456 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
21457 "TARGET_SSE || TARGET_3DNOW_A"
21459 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
21460 MEM_VOLATILE_P (operands[0]) = 1;
21463 (define_insn "*sfence_insn"
21464 [(set (match_operand:BLK 0 "" "")
21465 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
21466 "TARGET_SSE || TARGET_3DNOW_A"
21468 [(set_attr "type" "sse")
21469 (set_attr "memory" "unknown")])
21471 (define_expand "sse_prologue_save"
21472 [(parallel [(set (match_operand:BLK 0 "" "")
21473 (unspec:BLK [(reg:DI 21)
21480 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21481 (use (match_operand:DI 1 "register_operand" ""))
21482 (use (match_operand:DI 2 "immediate_operand" ""))
21483 (use (label_ref:DI (match_operand 3 "" "")))])]
21487 (define_insn "*sse_prologue_save_insn"
21488 [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
21489 (match_operand:DI 4 "const_int_operand" "n")))
21490 (unspec:BLK [(reg:DI 21)
21497 (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
21498 (use (match_operand:DI 1 "register_operand" "r"))
21499 (use (match_operand:DI 2 "const_int_operand" "i"))
21500 (use (label_ref:DI (match_operand 3 "" "X")))]
21502 && INTVAL (operands[4]) + SSE_REGPARM_MAX * 16 - 16 < 128
21503 && INTVAL (operands[4]) + INTVAL (operands[2]) * 16 >= -128"
21507 operands[0] = gen_rtx_MEM (Pmode,
21508 gen_rtx_PLUS (Pmode, operands[0], operands[4]));
21509 output_asm_insn (\"jmp\\t%A1\", operands);
21510 for (i = SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
21512 operands[4] = adjust_address (operands[0], DImode, i*16);
21513 operands[5] = gen_rtx_REG (TImode, SSE_REGNO (i));
21514 PUT_MODE (operands[4], TImode);
21515 if (GET_CODE (XEXP (operands[0], 0)) != PLUS)
21516 output_asm_insn (\"rex\", operands);
21517 output_asm_insn (\"movaps\\t{%5, %4|%4, %5}\", operands);
21519 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
21520 CODE_LABEL_NUMBER (operands[3]));
21524 [(set_attr "type" "other")
21525 (set_attr "length_immediate" "0")
21526 (set_attr "length_address" "0")
21527 (set_attr "length" "135")
21528 (set_attr "memory" "store")
21529 (set_attr "modrm" "0")
21530 (set_attr "mode" "DI")])
21532 ;; 3Dnow! instructions
21534 (define_insn "addv2sf3"
21535 [(set (match_operand:V2SF 0 "register_operand" "=y")
21536 (plus:V2SF (match_operand:V2SF 1 "register_operand" "0")
21537 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21539 "pfadd\\t{%2, %0|%0, %2}"
21540 [(set_attr "type" "mmxadd")
21541 (set_attr "mode" "V2SF")])
21543 (define_insn "subv2sf3"
21544 [(set (match_operand:V2SF 0 "register_operand" "=y")
21545 (minus:V2SF (match_operand:V2SF 1 "register_operand" "0")
21546 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21548 "pfsub\\t{%2, %0|%0, %2}"
21549 [(set_attr "type" "mmxadd")
21550 (set_attr "mode" "V2SF")])
21552 (define_insn "subrv2sf3"
21553 [(set (match_operand:V2SF 0 "register_operand" "=y")
21554 (minus:V2SF (match_operand:V2SF 2 "nonimmediate_operand" "ym")
21555 (match_operand:V2SF 1 "register_operand" "0")))]
21557 "pfsubr\\t{%2, %0|%0, %2}"
21558 [(set_attr "type" "mmxadd")
21559 (set_attr "mode" "V2SF")])
21561 (define_insn "gtv2sf3"
21562 [(set (match_operand:V2SI 0 "register_operand" "=y")
21563 (gt:V2SI (match_operand:V2SF 1 "register_operand" "0")
21564 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21566 "pfcmpgt\\t{%2, %0|%0, %2}"
21567 [(set_attr "type" "mmxcmp")
21568 (set_attr "mode" "V2SF")])
21570 (define_insn "gev2sf3"
21571 [(set (match_operand:V2SI 0 "register_operand" "=y")
21572 (ge:V2SI (match_operand:V2SF 1 "register_operand" "0")
21573 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21575 "pfcmpge\\t{%2, %0|%0, %2}"
21576 [(set_attr "type" "mmxcmp")
21577 (set_attr "mode" "V2SF")])
21579 (define_insn "eqv2sf3"
21580 [(set (match_operand:V2SI 0 "register_operand" "=y")
21581 (eq:V2SI (match_operand:V2SF 1 "register_operand" "0")
21582 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21584 "pfcmpeq\\t{%2, %0|%0, %2}"
21585 [(set_attr "type" "mmxcmp")
21586 (set_attr "mode" "V2SF")])
21588 (define_insn "pfmaxv2sf3"
21589 [(set (match_operand:V2SF 0 "register_operand" "=y")
21590 (smax:V2SF (match_operand:V2SF 1 "register_operand" "0")
21591 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21593 "pfmax\\t{%2, %0|%0, %2}"
21594 [(set_attr "type" "mmxadd")
21595 (set_attr "mode" "V2SF")])
21597 (define_insn "pfminv2sf3"
21598 [(set (match_operand:V2SF 0 "register_operand" "=y")
21599 (smin:V2SF (match_operand:V2SF 1 "register_operand" "0")
21600 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21602 "pfmin\\t{%2, %0|%0, %2}"
21603 [(set_attr "type" "mmxadd")
21604 (set_attr "mode" "V2SF")])
21606 (define_insn "mulv2sf3"
21607 [(set (match_operand:V2SF 0 "register_operand" "=y")
21608 (mult:V2SF (match_operand:V2SF 1 "register_operand" "0")
21609 (match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
21611 "pfmul\\t{%2, %0|%0, %2}"
21612 [(set_attr "type" "mmxmul")
21613 (set_attr "mode" "V2SF")])
21615 (define_insn "femms"
21616 [(unspec_volatile [(const_int 0)] UNSPECV_FEMMS)
21617 (clobber (reg:XF 8))
21618 (clobber (reg:XF 9))
21619 (clobber (reg:XF 10))
21620 (clobber (reg:XF 11))
21621 (clobber (reg:XF 12))
21622 (clobber (reg:XF 13))
21623 (clobber (reg:XF 14))
21624 (clobber (reg:XF 15))
21625 (clobber (reg:DI 29))
21626 (clobber (reg:DI 30))
21627 (clobber (reg:DI 31))
21628 (clobber (reg:DI 32))
21629 (clobber (reg:DI 33))
21630 (clobber (reg:DI 34))
21631 (clobber (reg:DI 35))
21632 (clobber (reg:DI 36))]
21635 [(set_attr "type" "mmx")
21636 (set_attr "memory" "none")])
21638 (define_insn "pf2id"
21639 [(set (match_operand:V2SI 0 "register_operand" "=y")
21640 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
21642 "pf2id\\t{%1, %0|%0, %1}"
21643 [(set_attr "type" "mmxcvt")
21644 (set_attr "mode" "V2SF")])
21646 (define_insn "pf2iw"
21647 [(set (match_operand:V2SI 0 "register_operand" "=y")
21650 (fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
21652 "pf2iw\\t{%1, %0|%0, %1}"
21653 [(set_attr "type" "mmxcvt")
21654 (set_attr "mode" "V2SF")])
21656 (define_insn "pfacc"
21657 [(set (match_operand:V2SF 0 "register_operand" "=y")
21660 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21661 (parallel [(const_int 0)]))
21662 (vec_select:SF (match_dup 1)
21663 (parallel [(const_int 1)])))
21665 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21666 (parallel [(const_int 0)]))
21667 (vec_select:SF (match_dup 2)
21668 (parallel [(const_int 1)])))))]
21670 "pfacc\\t{%2, %0|%0, %2}"
21671 [(set_attr "type" "mmxadd")
21672 (set_attr "mode" "V2SF")])
21674 (define_insn "pfnacc"
21675 [(set (match_operand:V2SF 0 "register_operand" "=y")
21678 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21679 (parallel [(const_int 0)]))
21680 (vec_select:SF (match_dup 1)
21681 (parallel [(const_int 1)])))
21683 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21684 (parallel [(const_int 0)]))
21685 (vec_select:SF (match_dup 2)
21686 (parallel [(const_int 1)])))))]
21688 "pfnacc\\t{%2, %0|%0, %2}"
21689 [(set_attr "type" "mmxadd")
21690 (set_attr "mode" "V2SF")])
21692 (define_insn "pfpnacc"
21693 [(set (match_operand:V2SF 0 "register_operand" "=y")
21696 (vec_select:SF (match_operand:V2SF 1 "register_operand" "0")
21697 (parallel [(const_int 0)]))
21698 (vec_select:SF (match_dup 1)
21699 (parallel [(const_int 1)])))
21701 (vec_select:SF (match_operand:V2SF 2 "nonimmediate_operand" "y")
21702 (parallel [(const_int 0)]))
21703 (vec_select:SF (match_dup 2)
21704 (parallel [(const_int 1)])))))]
21706 "pfpnacc\\t{%2, %0|%0, %2}"
21707 [(set_attr "type" "mmxadd")
21708 (set_attr "mode" "V2SF")])
21710 (define_insn "pi2fw"
21711 [(set (match_operand:V2SF 0 "register_operand" "=y")
21716 (vec_select:SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21717 (parallel [(const_int 0)]))))
21720 (vec_select:SI (match_dup 1)
21721 (parallel [(const_int 1)])))))))]
21723 "pi2fw\\t{%1, %0|%0, %1}"
21724 [(set_attr "type" "mmxcvt")
21725 (set_attr "mode" "V2SF")])
21727 (define_insn "floatv2si2"
21728 [(set (match_operand:V2SF 0 "register_operand" "=y")
21729 (float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
21731 "pi2fd\\t{%1, %0|%0, %1}"
21732 [(set_attr "type" "mmxcvt")
21733 (set_attr "mode" "V2SF")])
21735 ;; This insn is identical to pavgb in operation, but the opcode is
21736 ;; different. To avoid accidentally matching pavgb, use an unspec.
21738 (define_insn "pavgusb"
21739 [(set (match_operand:V8QI 0 "register_operand" "=y")
21741 [(match_operand:V8QI 1 "register_operand" "0")
21742 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
21745 "pavgusb\\t{%2, %0|%0, %2}"
21746 [(set_attr "type" "mmxshft")
21747 (set_attr "mode" "TI")])
21749 ;; 3DNow reciprocal and sqrt
21751 (define_insn "pfrcpv2sf2"
21752 [(set (match_operand:V2SF 0 "register_operand" "=y")
21753 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21756 "pfrcp\\t{%1, %0|%0, %1}"
21757 [(set_attr "type" "mmx")
21758 (set_attr "mode" "TI")])
21760 (define_insn "pfrcpit1v2sf3"
21761 [(set (match_operand:V2SF 0 "register_operand" "=y")
21762 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21763 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21766 "pfrcpit1\\t{%2, %0|%0, %2}"
21767 [(set_attr "type" "mmx")
21768 (set_attr "mode" "TI")])
21770 (define_insn "pfrcpit2v2sf3"
21771 [(set (match_operand:V2SF 0 "register_operand" "=y")
21772 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21773 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21776 "pfrcpit2\\t{%2, %0|%0, %2}"
21777 [(set_attr "type" "mmx")
21778 (set_attr "mode" "TI")])
21780 (define_insn "pfrsqrtv2sf2"
21781 [(set (match_operand:V2SF 0 "register_operand" "=y")
21782 (unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")]
21785 "pfrsqrt\\t{%1, %0|%0, %1}"
21786 [(set_attr "type" "mmx")
21787 (set_attr "mode" "TI")])
21789 (define_insn "pfrsqit1v2sf3"
21790 [(set (match_operand:V2SF 0 "register_operand" "=y")
21791 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "0")
21792 (match_operand:V2SF 2 "nonimmediate_operand" "ym")]
21795 "pfrsqit1\\t{%2, %0|%0, %2}"
21796 [(set_attr "type" "mmx")
21797 (set_attr "mode" "TI")])
21799 (define_insn "pmulhrwv4hi3"
21800 [(set (match_operand:V4HI 0 "register_operand" "=y")
21806 (match_operand:V4HI 1 "register_operand" "0"))
21808 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
21809 (const_vector:V4SI [(const_int 32768)
21812 (const_int 32768)]))
21815 "pmulhrw\\t{%2, %0|%0, %2}"
21816 [(set_attr "type" "mmxmul")
21817 (set_attr "mode" "TI")])
21819 (define_insn "pswapdv2si2"
21820 [(set (match_operand:V2SI 0 "register_operand" "=y")
21821 (vec_select:V2SI (match_operand:V2SI 1 "nonimmediate_operand" "ym")
21822 (parallel [(const_int 1) (const_int 0)])))]
21824 "pswapd\\t{%1, %0|%0, %1}"
21825 [(set_attr "type" "mmxcvt")
21826 (set_attr "mode" "TI")])
21828 (define_insn "pswapdv2sf2"
21829 [(set (match_operand:V2SF 0 "register_operand" "=y")
21830 (vec_select:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "ym")
21831 (parallel [(const_int 1) (const_int 0)])))]
21833 "pswapd\\t{%1, %0|%0, %1}"
21834 [(set_attr "type" "mmxcvt")
21835 (set_attr "mode" "TI")])
21837 (define_expand "prefetch"
21838 [(prefetch (match_operand 0 "address_operand" "")
21839 (match_operand:SI 1 "const_int_operand" "")
21840 (match_operand:SI 2 "const_int_operand" ""))]
21841 "TARGET_PREFETCH_SSE || TARGET_3DNOW"
21843 int rw = INTVAL (operands[1]);
21844 int locality = INTVAL (operands[2]);
21846 if (rw != 0 && rw != 1)
21848 if (locality < 0 || locality > 3)
21850 if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
21853 /* Use 3dNOW prefetch in case we are asking for write prefetch not
21854 suported by SSE counterpart or the SSE prefetch is not available
21855 (K6 machines). Otherwise use SSE prefetch as it allows specifying
21857 if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
21858 operands[2] = GEN_INT (3);
21860 operands[1] = const0_rtx;
21863 (define_insn "*prefetch_sse"
21864 [(prefetch (match_operand:SI 0 "address_operand" "p")
21866 (match_operand:SI 1 "const_int_operand" ""))]
21867 "TARGET_PREFETCH_SSE && !TARGET_64BIT"
21869 static const char * const patterns[4] = {
21870 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21873 int locality = INTVAL (operands[1]);
21874 if (locality < 0 || locality > 3)
21877 return patterns[locality];
21879 [(set_attr "type" "sse")
21880 (set_attr "memory" "none")])
21882 (define_insn "*prefetch_sse_rex"
21883 [(prefetch (match_operand:DI 0 "address_operand" "p")
21885 (match_operand:SI 1 "const_int_operand" ""))]
21886 "TARGET_PREFETCH_SSE && TARGET_64BIT"
21888 static const char * const patterns[4] = {
21889 "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
21892 int locality = INTVAL (operands[1]);
21893 if (locality < 0 || locality > 3)
21896 return patterns[locality];
21898 [(set_attr "type" "sse")
21899 (set_attr "memory" "none")])
21901 (define_insn "*prefetch_3dnow"
21902 [(prefetch (match_operand:SI 0 "address_operand" "p")
21903 (match_operand:SI 1 "const_int_operand" "n")
21905 "TARGET_3DNOW && !TARGET_64BIT"
21907 if (INTVAL (operands[1]) == 0)
21908 return "prefetch\t%a0";
21910 return "prefetchw\t%a0";
21912 [(set_attr "type" "mmx")
21913 (set_attr "memory" "none")])
21915 (define_insn "*prefetch_3dnow_rex"
21916 [(prefetch (match_operand:DI 0 "address_operand" "p")
21917 (match_operand:SI 1 "const_int_operand" "n")
21919 "TARGET_3DNOW && TARGET_64BIT"
21921 if (INTVAL (operands[1]) == 0)
21922 return "prefetch\t%a0";
21924 return "prefetchw\t%a0";
21926 [(set_attr "type" "mmx")
21927 (set_attr "memory" "none")])
21931 (define_insn "addv2df3"
21932 [(set (match_operand:V2DF 0 "register_operand" "=x")
21933 (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21934 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21936 "addpd\t{%2, %0|%0, %2}"
21937 [(set_attr "type" "sseadd")
21938 (set_attr "mode" "V2DF")])
21940 (define_insn "vmaddv2df3"
21941 [(set (match_operand:V2DF 0 "register_operand" "=x")
21942 (vec_merge:V2DF (plus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21943 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21947 "addsd\t{%2, %0|%0, %2}"
21948 [(set_attr "type" "sseadd")
21949 (set_attr "mode" "DF")])
21951 (define_insn "subv2df3"
21952 [(set (match_operand:V2DF 0 "register_operand" "=x")
21953 (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21954 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21956 "subpd\t{%2, %0|%0, %2}"
21957 [(set_attr "type" "sseadd")
21958 (set_attr "mode" "V2DF")])
21960 (define_insn "vmsubv2df3"
21961 [(set (match_operand:V2DF 0 "register_operand" "=x")
21962 (vec_merge:V2DF (minus:V2DF (match_operand:V2DF 1 "register_operand" "0")
21963 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21967 "subsd\t{%2, %0|%0, %2}"
21968 [(set_attr "type" "sseadd")
21969 (set_attr "mode" "DF")])
21971 (define_insn "mulv2df3"
21972 [(set (match_operand:V2DF 0 "register_operand" "=x")
21973 (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21974 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21976 "mulpd\t{%2, %0|%0, %2}"
21977 [(set_attr "type" "ssemul")
21978 (set_attr "mode" "V2DF")])
21980 (define_insn "vmmulv2df3"
21981 [(set (match_operand:V2DF 0 "register_operand" "=x")
21982 (vec_merge:V2DF (mult:V2DF (match_operand:V2DF 1 "register_operand" "0")
21983 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
21987 "mulsd\t{%2, %0|%0, %2}"
21988 [(set_attr "type" "ssemul")
21989 (set_attr "mode" "DF")])
21991 (define_insn "divv2df3"
21992 [(set (match_operand:V2DF 0 "register_operand" "=x")
21993 (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
21994 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
21996 "divpd\t{%2, %0|%0, %2}"
21997 [(set_attr "type" "ssediv")
21998 (set_attr "mode" "V2DF")])
22000 (define_insn "vmdivv2df3"
22001 [(set (match_operand:V2DF 0 "register_operand" "=x")
22002 (vec_merge:V2DF (div:V2DF (match_operand:V2DF 1 "register_operand" "0")
22003 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22007 "divsd\t{%2, %0|%0, %2}"
22008 [(set_attr "type" "ssediv")
22009 (set_attr "mode" "DF")])
22013 (define_insn "smaxv2df3"
22014 [(set (match_operand:V2DF 0 "register_operand" "=x")
22015 (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
22016 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22018 "maxpd\t{%2, %0|%0, %2}"
22019 [(set_attr "type" "sseadd")
22020 (set_attr "mode" "V2DF")])
22022 (define_insn "vmsmaxv2df3"
22023 [(set (match_operand:V2DF 0 "register_operand" "=x")
22024 (vec_merge:V2DF (smax:V2DF (match_operand:V2DF 1 "register_operand" "0")
22025 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22029 "maxsd\t{%2, %0|%0, %2}"
22030 [(set_attr "type" "sseadd")
22031 (set_attr "mode" "DF")])
22033 (define_insn "sminv2df3"
22034 [(set (match_operand:V2DF 0 "register_operand" "=x")
22035 (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
22036 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))]
22038 "minpd\t{%2, %0|%0, %2}"
22039 [(set_attr "type" "sseadd")
22040 (set_attr "mode" "V2DF")])
22042 (define_insn "vmsminv2df3"
22043 [(set (match_operand:V2DF 0 "register_operand" "=x")
22044 (vec_merge:V2DF (smin:V2DF (match_operand:V2DF 1 "register_operand" "0")
22045 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
22049 "minsd\t{%2, %0|%0, %2}"
22050 [(set_attr "type" "sseadd")
22051 (set_attr "mode" "DF")])
22052 ;; SSE2 square root. There doesn't appear to be an extension for the
22053 ;; reciprocal/rsqrt instructions if the Intel manual is to be believed.
22055 (define_insn "sqrtv2df2"
22056 [(set (match_operand:V2DF 0 "register_operand" "=x")
22057 (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm")))]
22059 "sqrtpd\t{%1, %0|%0, %1}"
22060 [(set_attr "type" "sse")
22061 (set_attr "mode" "V2DF")])
22063 (define_insn "vmsqrtv2df2"
22064 [(set (match_operand:V2DF 0 "register_operand" "=x")
22065 (vec_merge:V2DF (sqrt:V2DF (match_operand:V2DF 1 "register_operand" "xm"))
22066 (match_operand:V2DF 2 "register_operand" "0")
22069 "sqrtsd\t{%1, %0|%0, %1}"
22070 [(set_attr "type" "sse")
22071 (set_attr "mode" "SF")])
22073 ;; SSE mask-generating compares
22075 (define_insn "maskcmpv2df3"
22076 [(set (match_operand:V2DI 0 "register_operand" "=x")
22077 (match_operator:V2DI 3 "sse_comparison_operator"
22078 [(match_operand:V2DF 1 "register_operand" "0")
22079 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))]
22081 "cmp%D3pd\t{%2, %0|%0, %2}"
22082 [(set_attr "type" "ssecmp")
22083 (set_attr "mode" "V2DF")])
22085 (define_insn "maskncmpv2df3"
22086 [(set (match_operand:V2DI 0 "register_operand" "=x")
22088 (match_operator:V2DI 3 "sse_comparison_operator"
22089 [(match_operand:V2DF 1 "register_operand" "0")
22090 (match_operand:V2DF 2 "nonimmediate_operand" "x")])))]
22093 if (GET_CODE (operands[3]) == UNORDERED)
22094 return "cmpordps\t{%2, %0|%0, %2}";
22096 return "cmpn%D3pd\t{%2, %0|%0, %2}";
22098 [(set_attr "type" "ssecmp")
22099 (set_attr "mode" "V2DF")])
22101 (define_insn "vmmaskcmpv2df3"
22102 [(set (match_operand:V2DI 0 "register_operand" "=x")
22104 (match_operator:V2DI 3 "sse_comparison_operator"
22105 [(match_operand:V2DF 1 "register_operand" "0")
22106 (match_operand:V2DF 2 "nonimmediate_operand" "x")])
22107 (subreg:V2DI (match_dup 1) 0)
22110 "cmp%D3sd\t{%2, %0|%0, %2}"
22111 [(set_attr "type" "ssecmp")
22112 (set_attr "mode" "DF")])
22114 (define_insn "vmmaskncmpv2df3"
22115 [(set (match_operand:V2DI 0 "register_operand" "=x")
22118 (match_operator:V2DI 3 "sse_comparison_operator"
22119 [(match_operand:V2DF 1 "register_operand" "0")
22120 (match_operand:V2DF 2 "nonimmediate_operand" "x")]))
22121 (subreg:V2DI (match_dup 1) 0)
22125 if (GET_CODE (operands[3]) == UNORDERED)
22126 return "cmpordsd\t{%2, %0|%0, %2}";
22128 return "cmpn%D3sd\t{%2, %0|%0, %2}";
22130 [(set_attr "type" "ssecmp")
22131 (set_attr "mode" "DF")])
22133 (define_insn "sse2_comi"
22134 [(set (reg:CCFP 17)
22135 (compare:CCFP (vec_select:DF
22136 (match_operand:V2DF 0 "register_operand" "x")
22137 (parallel [(const_int 0)]))
22139 (match_operand:V2DF 1 "register_operand" "x")
22140 (parallel [(const_int 0)]))))]
22142 "comisd\t{%1, %0|%0, %1}"
22143 [(set_attr "type" "ssecomi")
22144 (set_attr "mode" "DF")])
22146 (define_insn "sse2_ucomi"
22147 [(set (reg:CCFPU 17)
22148 (compare:CCFPU (vec_select:DF
22149 (match_operand:V2DF 0 "register_operand" "x")
22150 (parallel [(const_int 0)]))
22152 (match_operand:V2DF 1 "register_operand" "x")
22153 (parallel [(const_int 0)]))))]
22155 "ucomisd\t{%1, %0|%0, %1}"
22156 [(set_attr "type" "ssecomi")
22157 (set_attr "mode" "DF")])
22159 ;; SSE Strange Moves.
22161 (define_insn "sse2_movmskpd"
22162 [(set (match_operand:SI 0 "register_operand" "=r")
22163 (unspec:SI [(match_operand:V2DF 1 "register_operand" "x")]
22166 "movmskpd\t{%1, %0|%0, %1}"
22167 [(set_attr "type" "ssecvt")
22168 (set_attr "mode" "V2DF")])
22170 (define_insn "sse2_pmovmskb"
22171 [(set (match_operand:SI 0 "register_operand" "=r")
22172 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
22175 "pmovmskb\t{%1, %0|%0, %1}"
22176 [(set_attr "type" "ssecvt")
22177 (set_attr "mode" "V2DF")])
22179 (define_insn "sse2_maskmovdqu"
22180 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
22181 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
22182 (match_operand:V16QI 2 "register_operand" "x")]
22185 ;; @@@ check ordering of operands in intel/nonintel syntax
22186 "maskmovdqu\t{%2, %1|%1, %2}"
22187 [(set_attr "type" "ssecvt")
22188 (set_attr "mode" "TI")])
22190 (define_insn "sse2_maskmovdqu_rex64"
22191 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
22192 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
22193 (match_operand:V16QI 2 "register_operand" "x")]
22196 ;; @@@ check ordering of operands in intel/nonintel syntax
22197 "maskmovdqu\t{%2, %1|%1, %2}"
22198 [(set_attr "type" "ssecvt")
22199 (set_attr "mode" "TI")])
22201 (define_insn "sse2_movntv2df"
22202 [(set (match_operand:V2DF 0 "memory_operand" "=m")
22203 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "x")]
22206 "movntpd\t{%1, %0|%0, %1}"
22207 [(set_attr "type" "ssecvt")
22208 (set_attr "mode" "V2DF")])
22210 (define_insn "sse2_movntv2di"
22211 [(set (match_operand:V2DI 0 "memory_operand" "=m")
22212 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
22215 "movntdq\t{%1, %0|%0, %1}"
22216 [(set_attr "type" "ssecvt")
22217 (set_attr "mode" "TI")])
22219 (define_insn "sse2_movntsi"
22220 [(set (match_operand:SI 0 "memory_operand" "=m")
22221 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
22224 "movnti\t{%1, %0|%0, %1}"
22225 [(set_attr "type" "ssecvt")
22226 (set_attr "mode" "V2DF")])
22228 ;; SSE <-> integer/MMX conversions
22230 ;; Conversions between SI and SF
22232 (define_insn "cvtdq2ps"
22233 [(set (match_operand:V4SF 0 "register_operand" "=x")
22234 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
22236 "cvtdq2ps\t{%1, %0|%0, %1}"
22237 [(set_attr "type" "ssecvt")
22238 (set_attr "mode" "V2DF")])
22240 (define_insn "cvtps2dq"
22241 [(set (match_operand:V4SI 0 "register_operand" "=x")
22242 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
22244 "cvtps2dq\t{%1, %0|%0, %1}"
22245 [(set_attr "type" "ssecvt")
22246 (set_attr "mode" "TI")])
22248 (define_insn "cvttps2dq"
22249 [(set (match_operand:V4SI 0 "register_operand" "=x")
22250 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
22253 "cvttps2dq\t{%1, %0|%0, %1}"
22254 [(set_attr "type" "ssecvt")
22255 (set_attr "mode" "TI")])
22257 ;; Conversions between SI and DF
22259 (define_insn "cvtdq2pd"
22260 [(set (match_operand:V2DF 0 "register_operand" "=x")
22261 (float:V2DF (vec_select:V2SI
22262 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
22265 (const_int 1)]))))]
22267 "cvtdq2pd\t{%1, %0|%0, %1}"
22268 [(set_attr "type" "ssecvt")
22269 (set_attr "mode" "V2DF")])
22271 (define_insn "cvtpd2dq"
22272 [(set (match_operand:V4SI 0 "register_operand" "=x")
22274 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
22275 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
22277 "cvtpd2dq\t{%1, %0|%0, %1}"
22278 [(set_attr "type" "ssecvt")
22279 (set_attr "mode" "TI")])
22281 (define_insn "cvttpd2dq"
22282 [(set (match_operand:V4SI 0 "register_operand" "=x")
22284 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
22286 (const_vector:V2SI [(const_int 0) (const_int 0)])))]
22288 "cvttpd2dq\t{%1, %0|%0, %1}"
22289 [(set_attr "type" "ssecvt")
22290 (set_attr "mode" "TI")])
22292 (define_insn "cvtpd2pi"
22293 [(set (match_operand:V2SI 0 "register_operand" "=y")
22294 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
22296 "cvtpd2pi\t{%1, %0|%0, %1}"
22297 [(set_attr "type" "ssecvt")
22298 (set_attr "mode" "TI")])
22300 (define_insn "cvttpd2pi"
22301 [(set (match_operand:V2SI 0 "register_operand" "=y")
22302 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
22305 "cvttpd2pi\t{%1, %0|%0, %1}"
22306 [(set_attr "type" "ssecvt")
22307 (set_attr "mode" "TI")])
22309 (define_insn "cvtpi2pd"
22310 [(set (match_operand:V2DF 0 "register_operand" "=x")
22311 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
22313 "cvtpi2pd\t{%1, %0|%0, %1}"
22314 [(set_attr "type" "ssecvt")
22315 (set_attr "mode" "TI")])
22317 ;; Conversions between SI and DF
22319 (define_insn "cvtsd2si"
22320 [(set (match_operand:SI 0 "register_operand" "=r,r")
22321 (fix:SI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
22322 (parallel [(const_int 0)]))))]
22324 "cvtsd2si\t{%1, %0|%0, %1}"
22325 [(set_attr "type" "sseicvt")
22326 (set_attr "athlon_decode" "double,vector")
22327 (set_attr "mode" "SI")])
22329 (define_insn "cvtsd2siq"
22330 [(set (match_operand:DI 0 "register_operand" "=r,r")
22331 (fix:DI (vec_select:DF (match_operand:V2DF 1 "register_operand" "x,m")
22332 (parallel [(const_int 0)]))))]
22333 "TARGET_SSE2 && TARGET_64BIT"
22334 "cvtsd2siq\t{%1, %0|%0, %1}"
22335 [(set_attr "type" "sseicvt")
22336 (set_attr "athlon_decode" "double,vector")
22337 (set_attr "mode" "DI")])
22339 (define_insn "cvttsd2si"
22340 [(set (match_operand:SI 0 "register_operand" "=r,r")
22341 (unspec:SI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
22342 (parallel [(const_int 0)]))] UNSPEC_FIX))]
22344 "cvttsd2si\t{%1, %0|%0, %1}"
22345 [(set_attr "type" "sseicvt")
22346 (set_attr "mode" "SI")
22347 (set_attr "athlon_decode" "double,vector")])
22349 (define_insn "cvttsd2siq"
22350 [(set (match_operand:DI 0 "register_operand" "=r,r")
22351 (unspec:DI [(vec_select:DF (match_operand:V2DF 1 "register_operand" "x,xm")
22352 (parallel [(const_int 0)]))] UNSPEC_FIX))]
22353 "TARGET_SSE2 && TARGET_64BIT"
22354 "cvttsd2siq\t{%1, %0|%0, %1}"
22355 [(set_attr "type" "sseicvt")
22356 (set_attr "mode" "DI")
22357 (set_attr "athlon_decode" "double,vector")])
22359 (define_insn "cvtsi2sd"
22360 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
22361 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
22362 (vec_duplicate:V2DF
22364 (match_operand:SI 2 "nonimmediate_operand" "r,rm")))
22367 "cvtsi2sd\t{%2, %0|%0, %2}"
22368 [(set_attr "type" "sseicvt")
22369 (set_attr "mode" "DF")
22370 (set_attr "athlon_decode" "double,direct")])
22372 (define_insn "cvtsi2sdq"
22373 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
22374 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0,0")
22375 (vec_duplicate:V2DF
22377 (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
22379 "TARGET_SSE2 && TARGET_64BIT"
22380 "cvtsi2sdq\t{%2, %0|%0, %2}"
22381 [(set_attr "type" "sseicvt")
22382 (set_attr "mode" "DF")
22383 (set_attr "athlon_decode" "double,direct")])
22385 ;; Conversions between SF and DF
22387 (define_insn "cvtsd2ss"
22388 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
22389 (vec_merge:V4SF (match_operand:V4SF 1 "register_operand" "0,0")
22390 (vec_duplicate:V4SF
22391 (float_truncate:V2SF
22392 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm")))
22395 "cvtsd2ss\t{%2, %0|%0, %2}"
22396 [(set_attr "type" "ssecvt")
22397 (set_attr "athlon_decode" "vector,double")
22398 (set_attr "mode" "SF")])
22400 (define_insn "cvtss2sd"
22401 [(set (match_operand:V2DF 0 "register_operand" "=x")
22402 (vec_merge:V2DF (match_operand:V2DF 1 "register_operand" "0")
22405 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
22406 (parallel [(const_int 0)
22410 "cvtss2sd\t{%2, %0|%0, %2}"
22411 [(set_attr "type" "ssecvt")
22412 (set_attr "mode" "DF")])
22414 (define_insn "cvtpd2ps"
22415 [(set (match_operand:V4SF 0 "register_operand" "=x")
22418 (subreg:V2SI (float_truncate:V2SF
22419 (match_operand:V2DF 1 "nonimmediate_operand" "xm")) 0)
22420 (const_vector:V2SI [(const_int 0) (const_int 0)])) 0))]
22422 "cvtpd2ps\t{%1, %0|%0, %1}"
22423 [(set_attr "type" "ssecvt")
22424 (set_attr "mode" "V4SF")])
22426 (define_insn "cvtps2pd"
22427 [(set (match_operand:V2DF 0 "register_operand" "=x")
22429 (vec_select:V2SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")
22430 (parallel [(const_int 0)
22431 (const_int 1)]))))]
22433 "cvtps2pd\t{%1, %0|%0, %1}"
22434 [(set_attr "type" "ssecvt")
22435 (set_attr "mode" "V2DF")])
22437 ;; SSE2 variants of MMX insns
22441 (define_insn "addv16qi3"
22442 [(set (match_operand:V16QI 0 "register_operand" "=x")
22443 (plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22444 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22446 "paddb\t{%2, %0|%0, %2}"
22447 [(set_attr "type" "sseiadd")
22448 (set_attr "mode" "TI")])
22450 (define_insn "addv8hi3"
22451 [(set (match_operand:V8HI 0 "register_operand" "=x")
22452 (plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22453 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22455 "paddw\t{%2, %0|%0, %2}"
22456 [(set_attr "type" "sseiadd")
22457 (set_attr "mode" "TI")])
22459 (define_insn "addv4si3"
22460 [(set (match_operand:V4SI 0 "register_operand" "=x")
22461 (plus:V4SI (match_operand:V4SI 1 "register_operand" "%0")
22462 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22464 "paddd\t{%2, %0|%0, %2}"
22465 [(set_attr "type" "sseiadd")
22466 (set_attr "mode" "TI")])
22468 (define_insn "addv2di3"
22469 [(set (match_operand:V2DI 0 "register_operand" "=x")
22470 (plus:V2DI (match_operand:V2DI 1 "register_operand" "%0")
22471 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
22473 "paddq\t{%2, %0|%0, %2}"
22474 [(set_attr "type" "sseiadd")
22475 (set_attr "mode" "TI")])
22477 (define_insn "ssaddv16qi3"
22478 [(set (match_operand:V16QI 0 "register_operand" "=x")
22479 (ss_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22480 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22482 "paddsb\t{%2, %0|%0, %2}"
22483 [(set_attr "type" "sseiadd")
22484 (set_attr "mode" "TI")])
22486 (define_insn "ssaddv8hi3"
22487 [(set (match_operand:V8HI 0 "register_operand" "=x")
22488 (ss_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22489 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22491 "paddsw\t{%2, %0|%0, %2}"
22492 [(set_attr "type" "sseiadd")
22493 (set_attr "mode" "TI")])
22495 (define_insn "usaddv16qi3"
22496 [(set (match_operand:V16QI 0 "register_operand" "=x")
22497 (us_plus:V16QI (match_operand:V16QI 1 "register_operand" "%0")
22498 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22500 "paddusb\t{%2, %0|%0, %2}"
22501 [(set_attr "type" "sseiadd")
22502 (set_attr "mode" "TI")])
22504 (define_insn "usaddv8hi3"
22505 [(set (match_operand:V8HI 0 "register_operand" "=x")
22506 (us_plus:V8HI (match_operand:V8HI 1 "register_operand" "%0")
22507 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22509 "paddusw\t{%2, %0|%0, %2}"
22510 [(set_attr "type" "sseiadd")
22511 (set_attr "mode" "TI")])
22513 (define_insn "subv16qi3"
22514 [(set (match_operand:V16QI 0 "register_operand" "=x")
22515 (minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22516 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22518 "psubb\t{%2, %0|%0, %2}"
22519 [(set_attr "type" "sseiadd")
22520 (set_attr "mode" "TI")])
22522 (define_insn "subv8hi3"
22523 [(set (match_operand:V8HI 0 "register_operand" "=x")
22524 (minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22525 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22527 "psubw\t{%2, %0|%0, %2}"
22528 [(set_attr "type" "sseiadd")
22529 (set_attr "mode" "TI")])
22531 (define_insn "subv4si3"
22532 [(set (match_operand:V4SI 0 "register_operand" "=x")
22533 (minus:V4SI (match_operand:V4SI 1 "register_operand" "0")
22534 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22536 "psubd\t{%2, %0|%0, %2}"
22537 [(set_attr "type" "sseiadd")
22538 (set_attr "mode" "TI")])
22540 (define_insn "subv2di3"
22541 [(set (match_operand:V2DI 0 "register_operand" "=x")
22542 (minus:V2DI (match_operand:V2DI 1 "register_operand" "0")
22543 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
22545 "psubq\t{%2, %0|%0, %2}"
22546 [(set_attr "type" "sseiadd")
22547 (set_attr "mode" "TI")])
22549 (define_insn "sssubv16qi3"
22550 [(set (match_operand:V16QI 0 "register_operand" "=x")
22551 (ss_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22552 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22554 "psubsb\t{%2, %0|%0, %2}"
22555 [(set_attr "type" "sseiadd")
22556 (set_attr "mode" "TI")])
22558 (define_insn "sssubv8hi3"
22559 [(set (match_operand:V8HI 0 "register_operand" "=x")
22560 (ss_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22561 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22563 "psubsw\t{%2, %0|%0, %2}"
22564 [(set_attr "type" "sseiadd")
22565 (set_attr "mode" "TI")])
22567 (define_insn "ussubv16qi3"
22568 [(set (match_operand:V16QI 0 "register_operand" "=x")
22569 (us_minus:V16QI (match_operand:V16QI 1 "register_operand" "0")
22570 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22572 "psubusb\t{%2, %0|%0, %2}"
22573 [(set_attr "type" "sseiadd")
22574 (set_attr "mode" "TI")])
22576 (define_insn "ussubv8hi3"
22577 [(set (match_operand:V8HI 0 "register_operand" "=x")
22578 (us_minus:V8HI (match_operand:V8HI 1 "register_operand" "0")
22579 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22581 "psubusw\t{%2, %0|%0, %2}"
22582 [(set_attr "type" "sseiadd")
22583 (set_attr "mode" "TI")])
22585 (define_insn "mulv8hi3"
22586 [(set (match_operand:V8HI 0 "register_operand" "=x")
22587 (mult:V8HI (match_operand:V8HI 1 "register_operand" "0")
22588 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22590 "pmullw\t{%2, %0|%0, %2}"
22591 [(set_attr "type" "sseimul")
22592 (set_attr "mode" "TI")])
22594 (define_insn "smulv8hi3_highpart"
22595 [(set (match_operand:V8HI 0 "register_operand" "=x")
22598 (mult:V8SI (sign_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
22599 (sign_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
22602 "pmulhw\t{%2, %0|%0, %2}"
22603 [(set_attr "type" "sseimul")
22604 (set_attr "mode" "TI")])
22606 (define_insn "umulv8hi3_highpart"
22607 [(set (match_operand:V8HI 0 "register_operand" "=x")
22610 (mult:V8SI (zero_extend:V8SI (match_operand:V8HI 1 "register_operand" "0"))
22611 (zero_extend:V8SI (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
22614 "pmulhuw\t{%2, %0|%0, %2}"
22615 [(set_attr "type" "sseimul")
22616 (set_attr "mode" "TI")])
22618 (define_insn "sse2_umulsidi3"
22619 [(set (match_operand:DI 0 "register_operand" "=y")
22620 (mult:DI (zero_extend:DI (vec_select:SI
22621 (match_operand:V2SI 1 "register_operand" "0")
22622 (parallel [(const_int 0)])))
22623 (zero_extend:DI (vec_select:SI
22624 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
22625 (parallel [(const_int 0)])))))]
22627 "pmuludq\t{%2, %0|%0, %2}"
22628 [(set_attr "type" "sseimul")
22629 (set_attr "mode" "TI")])
22631 (define_insn "sse2_umulv2siv2di3"
22632 [(set (match_operand:V2DI 0 "register_operand" "=x")
22633 (mult:V2DI (zero_extend:V2DI
22635 (match_operand:V4SI 1 "register_operand" "0")
22636 (parallel [(const_int 0) (const_int 2)])))
22639 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
22640 (parallel [(const_int 0) (const_int 2)])))))]
22642 "pmuludq\t{%2, %0|%0, %2}"
22643 [(set_attr "type" "sseimul")
22644 (set_attr "mode" "TI")])
22646 (define_insn "sse2_pmaddwd"
22647 [(set (match_operand:V4SI 0 "register_operand" "=x")
22650 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 1 "register_operand" "0")
22651 (parallel [(const_int 0)
22655 (sign_extend:V4SI (vec_select:V4HI (match_operand:V8HI 2 "nonimmediate_operand" "xm")
22656 (parallel [(const_int 0)
22661 (sign_extend:V4SI (vec_select:V4HI (match_dup 1)
22662 (parallel [(const_int 1)
22666 (sign_extend:V4SI (vec_select:V4HI (match_dup 2)
22667 (parallel [(const_int 1)
22670 (const_int 7)]))))))]
22672 "pmaddwd\t{%2, %0|%0, %2}"
22673 [(set_attr "type" "sseiadd")
22674 (set_attr "mode" "TI")])
22676 ;; Same as pxor, but don't show input operands so that we don't think
22678 (define_insn "sse2_clrti"
22679 [(set (match_operand:TI 0 "register_operand" "=x") (const_int 0))]
22682 if (get_attr_mode (insn) == MODE_TI)
22683 return "pxor\t%0, %0";
22685 return "xorps\t%0, %0";
22687 [(set_attr "type" "ssemov")
22688 (set_attr "memory" "none")
22691 (ne (symbol_ref "optimize_size")
22693 (const_string "V4SF")
22694 (const_string "TI")))])
22696 ;; MMX unsigned averages/sum of absolute differences
22698 (define_insn "sse2_uavgv16qi3"
22699 [(set (match_operand:V16QI 0 "register_operand" "=x")
22701 (plus:V16QI (plus:V16QI
22702 (match_operand:V16QI 1 "register_operand" "0")
22703 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
22704 (const_vector:V16QI [(const_int 1) (const_int 1)
22705 (const_int 1) (const_int 1)
22706 (const_int 1) (const_int 1)
22707 (const_int 1) (const_int 1)
22708 (const_int 1) (const_int 1)
22709 (const_int 1) (const_int 1)
22710 (const_int 1) (const_int 1)
22711 (const_int 1) (const_int 1)]))
22714 "pavgb\t{%2, %0|%0, %2}"
22715 [(set_attr "type" "sseiadd")
22716 (set_attr "mode" "TI")])
22718 (define_insn "sse2_uavgv8hi3"
22719 [(set (match_operand:V8HI 0 "register_operand" "=x")
22721 (plus:V8HI (plus:V8HI
22722 (match_operand:V8HI 1 "register_operand" "0")
22723 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
22724 (const_vector:V8HI [(const_int 1) (const_int 1)
22725 (const_int 1) (const_int 1)
22726 (const_int 1) (const_int 1)
22727 (const_int 1) (const_int 1)]))
22730 "pavgw\t{%2, %0|%0, %2}"
22731 [(set_attr "type" "sseiadd")
22732 (set_attr "mode" "TI")])
22734 ;; @@@ this isn't the right representation.
22735 (define_insn "sse2_psadbw"
22736 [(set (match_operand:V2DI 0 "register_operand" "=x")
22737 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
22738 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
22741 "psadbw\t{%2, %0|%0, %2}"
22742 [(set_attr "type" "sseiadd")
22743 (set_attr "mode" "TI")])
22746 ;; MMX insert/extract/shuffle
22748 (define_insn "sse2_pinsrw"
22749 [(set (match_operand:V8HI 0 "register_operand" "=x")
22750 (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
22751 (vec_duplicate:V8HI
22753 (match_operand:SI 2 "nonimmediate_operand" "rm")))
22754 (match_operand:SI 3 "immediate_operand" "i")))]
22756 "pinsrw\t{%3, %2, %0|%0, %2, %3}"
22757 [(set_attr "type" "ssecvt")
22758 (set_attr "mode" "TI")])
22760 (define_insn "sse2_pextrw"
22761 [(set (match_operand:SI 0 "register_operand" "=r")
22763 (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
22765 [(match_operand:SI 2 "immediate_operand" "i")]))))]
22767 "pextrw\t{%2, %1, %0|%0, %1, %2}"
22768 [(set_attr "type" "ssecvt")
22769 (set_attr "mode" "TI")])
22771 (define_insn "sse2_pshufd"
22772 [(set (match_operand:V4SI 0 "register_operand" "=x")
22773 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0")
22774 (match_operand:SI 2 "immediate_operand" "i")]
22777 "pshufd\t{%2, %1, %0|%0, %1, %2}"
22778 [(set_attr "type" "ssecvt")
22779 (set_attr "mode" "TI")])
22781 (define_insn "sse2_pshuflw"
22782 [(set (match_operand:V8HI 0 "register_operand" "=x")
22783 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22784 (match_operand:SI 2 "immediate_operand" "i")]
22787 "pshuflw\t{%2, %1, %0|%0, %1, %2}"
22788 [(set_attr "type" "ssecvt")
22789 (set_attr "mode" "TI")])
22791 (define_insn "sse2_pshufhw"
22792 [(set (match_operand:V8HI 0 "register_operand" "=x")
22793 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "0")
22794 (match_operand:SI 2 "immediate_operand" "i")]
22797 "pshufhw\t{%2, %1, %0|%0, %1, %2}"
22798 [(set_attr "type" "ssecvt")
22799 (set_attr "mode" "TI")])
22801 ;; MMX mask-generating comparisons
22803 (define_insn "eqv16qi3"
22804 [(set (match_operand:V16QI 0 "register_operand" "=x")
22805 (eq:V16QI (match_operand:V16QI 1 "register_operand" "0")
22806 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22808 "pcmpeqb\t{%2, %0|%0, %2}"
22809 [(set_attr "type" "ssecmp")
22810 (set_attr "mode" "TI")])
22812 (define_insn "eqv8hi3"
22813 [(set (match_operand:V8HI 0 "register_operand" "=x")
22814 (eq:V8HI (match_operand:V8HI 1 "register_operand" "0")
22815 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22817 "pcmpeqw\t{%2, %0|%0, %2}"
22818 [(set_attr "type" "ssecmp")
22819 (set_attr "mode" "TI")])
22821 (define_insn "eqv4si3"
22822 [(set (match_operand:V4SI 0 "register_operand" "=x")
22823 (eq:V4SI (match_operand:V4SI 1 "register_operand" "0")
22824 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22826 "pcmpeqd\t{%2, %0|%0, %2}"
22827 [(set_attr "type" "ssecmp")
22828 (set_attr "mode" "TI")])
22830 (define_insn "gtv16qi3"
22831 [(set (match_operand:V16QI 0 "register_operand" "=x")
22832 (gt:V16QI (match_operand:V16QI 1 "register_operand" "0")
22833 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22835 "pcmpgtb\t{%2, %0|%0, %2}"
22836 [(set_attr "type" "ssecmp")
22837 (set_attr "mode" "TI")])
22839 (define_insn "gtv8hi3"
22840 [(set (match_operand:V8HI 0 "register_operand" "=x")
22841 (gt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22842 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22844 "pcmpgtw\t{%2, %0|%0, %2}"
22845 [(set_attr "type" "ssecmp")
22846 (set_attr "mode" "TI")])
22848 (define_insn "gtv4si3"
22849 [(set (match_operand:V4SI 0 "register_operand" "=x")
22850 (gt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22851 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
22853 "pcmpgtd\t{%2, %0|%0, %2}"
22854 [(set_attr "type" "ssecmp")
22855 (set_attr "mode" "TI")])
22858 ;; MMX max/min insns
22860 (define_insn "umaxv16qi3"
22861 [(set (match_operand:V16QI 0 "register_operand" "=x")
22862 (umax:V16QI (match_operand:V16QI 1 "register_operand" "0")
22863 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22865 "pmaxub\t{%2, %0|%0, %2}"
22866 [(set_attr "type" "sseiadd")
22867 (set_attr "mode" "TI")])
22869 (define_insn "smaxv8hi3"
22870 [(set (match_operand:V8HI 0 "register_operand" "=x")
22871 (smax:V8HI (match_operand:V8HI 1 "register_operand" "0")
22872 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22874 "pmaxsw\t{%2, %0|%0, %2}"
22875 [(set_attr "type" "sseiadd")
22876 (set_attr "mode" "TI")])
22878 (define_insn "uminv16qi3"
22879 [(set (match_operand:V16QI 0 "register_operand" "=x")
22880 (umin:V16QI (match_operand:V16QI 1 "register_operand" "0")
22881 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
22883 "pminub\t{%2, %0|%0, %2}"
22884 [(set_attr "type" "sseiadd")
22885 (set_attr "mode" "TI")])
22887 (define_insn "sminv8hi3"
22888 [(set (match_operand:V8HI 0 "register_operand" "=x")
22889 (smin:V8HI (match_operand:V8HI 1 "register_operand" "0")
22890 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
22892 "pminsw\t{%2, %0|%0, %2}"
22893 [(set_attr "type" "sseiadd")
22894 (set_attr "mode" "TI")])
22899 (define_insn "ashrv8hi3"
22900 [(set (match_operand:V8HI 0 "register_operand" "=x")
22901 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22902 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22904 "psraw\t{%2, %0|%0, %2}"
22905 [(set_attr "type" "sseishft")
22906 (set_attr "mode" "TI")])
22908 (define_insn "ashrv4si3"
22909 [(set (match_operand:V4SI 0 "register_operand" "=x")
22910 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22911 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22913 "psrad\t{%2, %0|%0, %2}"
22914 [(set_attr "type" "sseishft")
22915 (set_attr "mode" "TI")])
22917 (define_insn "lshrv8hi3"
22918 [(set (match_operand:V8HI 0 "register_operand" "=x")
22919 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22920 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22922 "psrlw\t{%2, %0|%0, %2}"
22923 [(set_attr "type" "sseishft")
22924 (set_attr "mode" "TI")])
22926 (define_insn "lshrv4si3"
22927 [(set (match_operand:V4SI 0 "register_operand" "=x")
22928 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22929 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22931 "psrld\t{%2, %0|%0, %2}"
22932 [(set_attr "type" "sseishft")
22933 (set_attr "mode" "TI")])
22935 (define_insn "lshrv2di3"
22936 [(set (match_operand:V2DI 0 "register_operand" "=x")
22937 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
22938 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22940 "psrlq\t{%2, %0|%0, %2}"
22941 [(set_attr "type" "sseishft")
22942 (set_attr "mode" "TI")])
22944 (define_insn "ashlv8hi3"
22945 [(set (match_operand:V8HI 0 "register_operand" "=x")
22946 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
22947 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22949 "psllw\t{%2, %0|%0, %2}"
22950 [(set_attr "type" "sseishft")
22951 (set_attr "mode" "TI")])
22953 (define_insn "ashlv4si3"
22954 [(set (match_operand:V4SI 0 "register_operand" "=x")
22955 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
22956 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22958 "pslld\t{%2, %0|%0, %2}"
22959 [(set_attr "type" "sseishft")
22960 (set_attr "mode" "TI")])
22962 (define_insn "ashlv2di3"
22963 [(set (match_operand:V2DI 0 "register_operand" "=x")
22964 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
22965 (match_operand:TI 2 "nonmemory_operand" "xi")))]
22967 "psllq\t{%2, %0|%0, %2}"
22968 [(set_attr "type" "sseishft")
22969 (set_attr "mode" "TI")])
22971 (define_insn "ashrv8hi3_ti"
22972 [(set (match_operand:V8HI 0 "register_operand" "=x")
22973 (ashiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22974 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22976 "psraw\t{%2, %0|%0, %2}"
22977 [(set_attr "type" "sseishft")
22978 (set_attr "mode" "TI")])
22980 (define_insn "ashrv4si3_ti"
22981 [(set (match_operand:V4SI 0 "register_operand" "=x")
22982 (ashiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
22983 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22985 "psrad\t{%2, %0|%0, %2}"
22986 [(set_attr "type" "sseishft")
22987 (set_attr "mode" "TI")])
22989 (define_insn "lshrv8hi3_ti"
22990 [(set (match_operand:V8HI 0 "register_operand" "=x")
22991 (lshiftrt:V8HI (match_operand:V8HI 1 "register_operand" "0")
22992 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
22994 "psrlw\t{%2, %0|%0, %2}"
22995 [(set_attr "type" "sseishft")
22996 (set_attr "mode" "TI")])
22998 (define_insn "lshrv4si3_ti"
22999 [(set (match_operand:V4SI 0 "register_operand" "=x")
23000 (lshiftrt:V4SI (match_operand:V4SI 1 "register_operand" "0")
23001 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23003 "psrld\t{%2, %0|%0, %2}"
23004 [(set_attr "type" "sseishft")
23005 (set_attr "mode" "TI")])
23007 (define_insn "lshrv2di3_ti"
23008 [(set (match_operand:V2DI 0 "register_operand" "=x")
23009 (lshiftrt:V2DI (match_operand:V2DI 1 "register_operand" "0")
23010 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23012 "psrlq\t{%2, %0|%0, %2}"
23013 [(set_attr "type" "sseishft")
23014 (set_attr "mode" "TI")])
23016 (define_insn "ashlv8hi3_ti"
23017 [(set (match_operand:V8HI 0 "register_operand" "=x")
23018 (ashift:V8HI (match_operand:V8HI 1 "register_operand" "0")
23019 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23021 "psllw\t{%2, %0|%0, %2}"
23022 [(set_attr "type" "sseishft")
23023 (set_attr "mode" "TI")])
23025 (define_insn "ashlv4si3_ti"
23026 [(set (match_operand:V4SI 0 "register_operand" "=x")
23027 (ashift:V4SI (match_operand:V4SI 1 "register_operand" "0")
23028 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23030 "pslld\t{%2, %0|%0, %2}"
23031 [(set_attr "type" "sseishft")
23032 (set_attr "mode" "TI")])
23034 (define_insn "ashlv2di3_ti"
23035 [(set (match_operand:V2DI 0 "register_operand" "=x")
23036 (ashift:V2DI (match_operand:V2DI 1 "register_operand" "0")
23037 (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
23039 "psllq\t{%2, %0|%0, %2}"
23040 [(set_attr "type" "sseishft")
23041 (set_attr "mode" "TI")])
23043 ;; See logical MMX insns for the reason for the unspec. Strictly speaking
23044 ;; we wouldn't need here it since we never generate TImode arithmetic.
23046 ;; There has to be some kind of prize for the weirdest new instruction...
23047 (define_insn "sse2_ashlti3"
23048 [(set (match_operand:TI 0 "register_operand" "=x")
23050 [(ashift:TI (match_operand:TI 1 "register_operand" "0")
23051 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
23052 (const_int 8)))] UNSPEC_NOP))]
23054 "pslldq\t{%2, %0|%0, %2}"
23055 [(set_attr "type" "sseishft")
23056 (set_attr "mode" "TI")])
23058 (define_insn "sse2_lshrti3"
23059 [(set (match_operand:TI 0 "register_operand" "=x")
23061 [(lshiftrt:TI (match_operand:TI 1 "register_operand" "0")
23062 (mult:SI (match_operand:SI 2 "immediate_operand" "i")
23063 (const_int 8)))] UNSPEC_NOP))]
23065 "psrldq\t{%2, %0|%0, %2}"
23066 [(set_attr "type" "sseishft")
23067 (set_attr "mode" "TI")])
23071 (define_insn "sse2_unpckhpd"
23072 [(set (match_operand:V2DF 0 "register_operand" "=x")
23074 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
23075 (parallel [(const_int 1)]))
23076 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
23077 (parallel [(const_int 0)]))))]
23079 "unpckhpd\t{%2, %0|%0, %2}"
23080 [(set_attr "type" "ssecvt")
23081 (set_attr "mode" "TI")])
23083 (define_insn "sse2_unpcklpd"
23084 [(set (match_operand:V2DF 0 "register_operand" "=x")
23086 (vec_select:DF (match_operand:V2DF 1 "register_operand" "0")
23087 (parallel [(const_int 0)]))
23088 (vec_select:DF (match_operand:V2DF 2 "register_operand" "x")
23089 (parallel [(const_int 1)]))))]
23091 "unpcklpd\t{%2, %0|%0, %2}"
23092 [(set_attr "type" "ssecvt")
23093 (set_attr "mode" "TI")])
23095 ;; MMX pack/unpack insns.
23097 (define_insn "sse2_packsswb"
23098 [(set (match_operand:V16QI 0 "register_operand" "=x")
23100 (ss_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
23101 (ss_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
23103 "packsswb\t{%2, %0|%0, %2}"
23104 [(set_attr "type" "ssecvt")
23105 (set_attr "mode" "TI")])
23107 (define_insn "sse2_packssdw"
23108 [(set (match_operand:V8HI 0 "register_operand" "=x")
23110 (ss_truncate:V4HI (match_operand:V4SI 1 "register_operand" "0"))
23111 (ss_truncate:V4HI (match_operand:V4SI 2 "register_operand" "x"))))]
23113 "packssdw\t{%2, %0|%0, %2}"
23114 [(set_attr "type" "ssecvt")
23115 (set_attr "mode" "TI")])
23117 (define_insn "sse2_packuswb"
23118 [(set (match_operand:V16QI 0 "register_operand" "=x")
23120 (us_truncate:V8QI (match_operand:V8HI 1 "register_operand" "0"))
23121 (us_truncate:V8QI (match_operand:V8HI 2 "register_operand" "x"))))]
23123 "packuswb\t{%2, %0|%0, %2}"
23124 [(set_attr "type" "ssecvt")
23125 (set_attr "mode" "TI")])
23127 (define_insn "sse2_punpckhbw"
23128 [(set (match_operand:V16QI 0 "register_operand" "=x")
23130 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
23131 (parallel [(const_int 8) (const_int 0)
23132 (const_int 9) (const_int 1)
23133 (const_int 10) (const_int 2)
23134 (const_int 11) (const_int 3)
23135 (const_int 12) (const_int 4)
23136 (const_int 13) (const_int 5)
23137 (const_int 14) (const_int 6)
23138 (const_int 15) (const_int 7)]))
23139 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
23140 (parallel [(const_int 0) (const_int 8)
23141 (const_int 1) (const_int 9)
23142 (const_int 2) (const_int 10)
23143 (const_int 3) (const_int 11)
23144 (const_int 4) (const_int 12)
23145 (const_int 5) (const_int 13)
23146 (const_int 6) (const_int 14)
23147 (const_int 7) (const_int 15)]))
23148 (const_int 21845)))]
23150 "punpckhbw\t{%2, %0|%0, %2}"
23151 [(set_attr "type" "ssecvt")
23152 (set_attr "mode" "TI")])
23154 (define_insn "sse2_punpckhwd"
23155 [(set (match_operand:V8HI 0 "register_operand" "=x")
23157 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
23158 (parallel [(const_int 4) (const_int 0)
23159 (const_int 5) (const_int 1)
23160 (const_int 6) (const_int 2)
23161 (const_int 7) (const_int 3)]))
23162 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
23163 (parallel [(const_int 0) (const_int 4)
23164 (const_int 1) (const_int 5)
23165 (const_int 2) (const_int 6)
23166 (const_int 3) (const_int 7)]))
23169 "punpckhwd\t{%2, %0|%0, %2}"
23170 [(set_attr "type" "ssecvt")
23171 (set_attr "mode" "TI")])
23173 (define_insn "sse2_punpckhdq"
23174 [(set (match_operand:V4SI 0 "register_operand" "=x")
23176 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
23177 (parallel [(const_int 2) (const_int 0)
23178 (const_int 3) (const_int 1)]))
23179 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
23180 (parallel [(const_int 0) (const_int 2)
23181 (const_int 1) (const_int 3)]))
23184 "punpckhdq\t{%2, %0|%0, %2}"
23185 [(set_attr "type" "ssecvt")
23186 (set_attr "mode" "TI")])
23188 (define_insn "sse2_punpcklbw"
23189 [(set (match_operand:V16QI 0 "register_operand" "=x")
23191 (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "0")
23192 (parallel [(const_int 0) (const_int 8)
23193 (const_int 1) (const_int 9)
23194 (const_int 2) (const_int 10)
23195 (const_int 3) (const_int 11)
23196 (const_int 4) (const_int 12)
23197 (const_int 5) (const_int 13)
23198 (const_int 6) (const_int 14)
23199 (const_int 7) (const_int 15)]))
23200 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "x")
23201 (parallel [(const_int 8) (const_int 0)
23202 (const_int 9) (const_int 1)
23203 (const_int 10) (const_int 2)
23204 (const_int 11) (const_int 3)
23205 (const_int 12) (const_int 4)
23206 (const_int 13) (const_int 5)
23207 (const_int 14) (const_int 6)
23208 (const_int 15) (const_int 7)]))
23209 (const_int 21845)))]
23211 "punpcklbw\t{%2, %0|%0, %2}"
23212 [(set_attr "type" "ssecvt")
23213 (set_attr "mode" "TI")])
23215 (define_insn "sse2_punpcklwd"
23216 [(set (match_operand:V8HI 0 "register_operand" "=x")
23218 (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "0")
23219 (parallel [(const_int 0) (const_int 4)
23220 (const_int 1) (const_int 5)
23221 (const_int 2) (const_int 6)
23222 (const_int 3) (const_int 7)]))
23223 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "x")
23224 (parallel [(const_int 4) (const_int 0)
23225 (const_int 5) (const_int 1)
23226 (const_int 6) (const_int 2)
23227 (const_int 7) (const_int 3)]))
23230 "punpcklwd\t{%2, %0|%0, %2}"
23231 [(set_attr "type" "ssecvt")
23232 (set_attr "mode" "TI")])
23234 (define_insn "sse2_punpckldq"
23235 [(set (match_operand:V4SI 0 "register_operand" "=x")
23237 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "0")
23238 (parallel [(const_int 0) (const_int 2)
23239 (const_int 1) (const_int 3)]))
23240 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "x")
23241 (parallel [(const_int 2) (const_int 0)
23242 (const_int 3) (const_int 1)]))
23245 "punpckldq\t{%2, %0|%0, %2}"
23246 [(set_attr "type" "ssecvt")
23247 (set_attr "mode" "TI")])
23249 (define_insn "sse2_punpcklqdq"
23250 [(set (match_operand:V2DI 0 "register_operand" "=x")
23252 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
23253 (parallel [(const_int 1)
23255 (match_operand:V2DI 1 "register_operand" "0")
23258 "punpcklqdq\t{%2, %0|%0, %2}"
23259 [(set_attr "type" "ssecvt")
23260 (set_attr "mode" "TI")])
23262 (define_insn "sse2_punpckhqdq"
23263 [(set (match_operand:V2DI 0 "register_operand" "=x")
23265 (match_operand:V2DI 1 "register_operand" "0")
23266 (vec_select:V2DI (match_operand:V2DI 2 "register_operand" "x")
23267 (parallel [(const_int 1)
23271 "punpckhqdq\t{%2, %0|%0, %2}"
23272 [(set_attr "type" "ssecvt")
23273 (set_attr "mode" "TI")])
23277 (define_insn "sse2_movapd"
23278 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23279 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
23282 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23283 "movapd\t{%1, %0|%0, %1}"
23284 [(set_attr "type" "ssemov")
23285 (set_attr "mode" "V2DF")])
23287 (define_insn "sse2_movupd"
23288 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23289 (unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm,x")]
23292 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23293 "movupd\t{%1, %0|%0, %1}"
23294 [(set_attr "type" "ssecvt")
23295 (set_attr "mode" "V2DF")])
23297 (define_insn "sse2_movdqa"
23298 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
23299 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
23302 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23303 "movdqa\t{%1, %0|%0, %1}"
23304 [(set_attr "type" "ssemov")
23305 (set_attr "mode" "TI")])
23307 (define_insn "sse2_movdqu"
23308 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
23309 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
23312 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
23313 "movdqu\t{%1, %0|%0, %1}"
23314 [(set_attr "type" "ssecvt")
23315 (set_attr "mode" "TI")])
23317 (define_insn "sse2_movdq2q"
23318 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y")
23319 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x")
23320 (parallel [(const_int 0)])))]
23321 "TARGET_SSE2 && !TARGET_64BIT"
23323 movq\t{%1, %0|%0, %1}
23324 movdq2q\t{%1, %0|%0, %1}"
23325 [(set_attr "type" "ssecvt")
23326 (set_attr "mode" "TI")])
23328 (define_insn "sse2_movdq2q_rex64"
23329 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,y,r")
23330 (vec_select:DI (match_operand:V2DI 1 "register_operand" "x,x,x")
23331 (parallel [(const_int 0)])))]
23332 "TARGET_SSE2 && TARGET_64BIT"
23334 movq\t{%1, %0|%0, %1}
23335 movdq2q\t{%1, %0|%0, %1}
23336 movd\t{%1, %0|%0, %1}"
23337 [(set_attr "type" "ssecvt")
23338 (set_attr "mode" "TI")])
23340 (define_insn "sse2_movq2dq"
23341 [(set (match_operand:V2DI 0 "register_operand" "=x,?x")
23342 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y")
23344 "TARGET_SSE2 && !TARGET_64BIT"
23346 movq\t{%1, %0|%0, %1}
23347 movq2dq\t{%1, %0|%0, %1}"
23348 [(set_attr "type" "ssecvt,ssemov")
23349 (set_attr "mode" "TI")])
23351 (define_insn "sse2_movq2dq_rex64"
23352 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x")
23353 (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" "m,y,r")
23355 "TARGET_SSE2 && TARGET_64BIT"
23357 movq\t{%1, %0|%0, %1}
23358 movq2dq\t{%1, %0|%0, %1}
23359 movd\t{%1, %0|%0, %1}"
23360 [(set_attr "type" "ssecvt,ssemov,ssecvt")
23361 (set_attr "mode" "TI")])
23363 (define_insn "sse2_movq"
23364 [(set (match_operand:V2DI 0 "register_operand" "=x")
23365 (vec_concat:V2DI (vec_select:DI
23366 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
23367 (parallel [(const_int 0)]))
23370 "movq\t{%1, %0|%0, %1}"
23371 [(set_attr "type" "ssemov")
23372 (set_attr "mode" "TI")])
23374 (define_insn "sse2_loadd"
23375 [(set (match_operand:V4SI 0 "register_operand" "=x")
23377 (vec_duplicate:V4SI (match_operand:SI 1 "nonimmediate_operand" "mr"))
23378 (const_vector:V4SI [(const_int 0)
23384 "movd\t{%1, %0|%0, %1}"
23385 [(set_attr "type" "ssemov")
23386 (set_attr "mode" "TI")])
23388 (define_insn "sse2_stored"
23389 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
23391 (match_operand:V4SI 1 "register_operand" "x")
23392 (parallel [(const_int 0)])))]
23394 "movd\t{%1, %0|%0, %1}"
23395 [(set_attr "type" "ssemov")
23396 (set_attr "mode" "TI")])
23398 (define_insn "sse2_movhpd"
23399 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23401 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
23402 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
23404 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
23405 "movhpd\t{%2, %0|%0, %2}"
23406 [(set_attr "type" "ssecvt")
23407 (set_attr "mode" "V2DF")])
23409 (define_insn "sse2_movlpd"
23410 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,m")
23412 (match_operand:V2DF 1 "nonimmediate_operand" "0,0")
23413 (match_operand:V2DF 2 "nonimmediate_operand" "m,x")
23415 "TARGET_SSE2 && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
23416 "movlpd\t{%2, %0|%0, %2}"
23417 [(set_attr "type" "ssecvt")
23418 (set_attr "mode" "V2DF")])
23420 (define_expand "sse2_loadsd"
23421 [(match_operand:V2DF 0 "register_operand" "")
23422 (match_operand:DF 1 "memory_operand" "")]
23425 emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
23426 CONST0_RTX (V2DFmode)));
23430 (define_insn "sse2_loadsd_1"
23431 [(set (match_operand:V2DF 0 "register_operand" "=x")
23433 (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m"))
23434 (match_operand:V2DF 2 "const0_operand" "X")
23437 "movsd\t{%1, %0|%0, %1}"
23438 [(set_attr "type" "ssecvt")
23439 (set_attr "mode" "DF")])
23441 (define_insn "sse2_movsd"
23442 [(set (match_operand:V2DF 0 "register_operand" "=x")
23444 (match_operand:V2DF 1 "register_operand" "0")
23445 (match_operand:V2DF 2 "register_operand" "x")
23448 "movsd\t{%2, %0|%0, %2}"
23449 [(set_attr "type" "ssecvt")
23450 (set_attr "mode" "DF")])
23452 (define_insn "sse2_storesd"
23453 [(set (match_operand:DF 0 "memory_operand" "=m")
23455 (match_operand:V2DF 1 "register_operand" "x")
23456 (parallel [(const_int 0)])))]
23458 "movsd\t{%1, %0|%0, %1}"
23459 [(set_attr "type" "ssecvt")
23460 (set_attr "mode" "DF")])
23462 (define_insn "sse2_shufpd"
23463 [(set (match_operand:V2DF 0 "register_operand" "=x")
23464 (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0")
23465 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
23466 (match_operand:SI 3 "immediate_operand" "i")]
23469 ;; @@@ check operand order for intel/nonintel syntax
23470 "shufpd\t{%3, %2, %0|%0, %2, %3}"
23471 [(set_attr "type" "ssecvt")
23472 (set_attr "mode" "V2DF")])
23474 (define_insn "sse2_clflush"
23475 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
23479 [(set_attr "type" "sse")
23480 (set_attr "memory" "unknown")])
23482 (define_expand "sse2_mfence"
23483 [(set (match_dup 0)
23484 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
23487 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
23488 MEM_VOLATILE_P (operands[0]) = 1;
23491 (define_insn "*mfence_insn"
23492 [(set (match_operand:BLK 0 "" "")
23493 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
23496 [(set_attr "type" "sse")
23497 (set_attr "memory" "unknown")])
23499 (define_expand "sse2_lfence"
23500 [(set (match_dup 0)
23501 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
23504 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
23505 MEM_VOLATILE_P (operands[0]) = 1;
23508 (define_insn "*lfence_insn"
23509 [(set (match_operand:BLK 0 "" "")
23510 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
23513 [(set_attr "type" "sse")
23514 (set_attr "memory" "unknown")])