1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 Under Section 7 of GPL version 3, you are granted additional
19 permissions described in the GCC Runtime Library Exception, version
20 3.1, as published by the Free Software Foundation.
22 You should have received a copy of the GNU General Public License and
23 a copy of the GCC Runtime Library Exception along with this program;
24 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
25 <http://www.gnu.org/licenses/>. */
27 /* The purpose of this file is to define the characteristics of the i386,
28 independent of assembler syntax or operating system.
30 Three other files build on this one to describe a specific assembler syntax:
31 bsd386.h, att386.h, and sun386.h.
33 The actual tm.h file for a particular system should include
34 this file, and then the file for the appropriate assembler syntax.
36 Many macros that specify assembler syntax are omitted entirely from
37 this file because they really belong in the files for particular
38 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
39 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
40 that start with ASM_ or end in ASM_OP. */
42 /* Redefines for option macros. */
44 #define TARGET_64BIT OPTION_ISA_64BIT
45 #define TARGET_MMX OPTION_ISA_MMX
46 #define TARGET_3DNOW OPTION_ISA_3DNOW
47 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
48 #define TARGET_SSE OPTION_ISA_SSE
49 #define TARGET_SSE2 OPTION_ISA_SSE2
50 #define TARGET_SSE3 OPTION_ISA_SSE3
51 #define TARGET_SSSE3 OPTION_ISA_SSSE3
52 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1
53 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2
54 #define TARGET_AVX OPTION_ISA_AVX
55 #define TARGET_FMA OPTION_ISA_FMA
56 #define TARGET_SSE4A OPTION_ISA_SSE4A
57 #define TARGET_SSE5 OPTION_ISA_SSE5
58 #define TARGET_ROUND OPTION_ISA_ROUND
59 #define TARGET_ABM OPTION_ISA_ABM
60 #define TARGET_POPCNT OPTION_ISA_POPCNT
61 #define TARGET_SAHF OPTION_ISA_SAHF
62 #define TARGET_MOVBE OPTION_ISA_MOVBE
63 #define TARGET_CRC32 OPTION_ISA_CRC32
64 #define TARGET_AES OPTION_ISA_AES
65 #define TARGET_PCLMUL OPTION_ISA_PCLMUL
66 #define TARGET_CMPXCHG16B OPTION_ISA_CX16
69 /* SSE5 and SSE4.1 define the same round instructions */
70 #define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE5)
71 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
73 #include "config/vxworks-dummy.h"
75 /* Algorithm to expand string function with. */
88 #define NAX_STRINGOP_ALGS 4
90 /* Specify what algorithm to use for stringops on known size.
91 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
92 known at compile time or estimated via feedback, the SIZE array
93 is walked in order until MAX is greater then the estimate (or -1
94 means infinity). Corresponding ALG is used then.
95 For example initializer:
96 {{256, loop}, {-1, rep_prefix_4_byte}}
97 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
101 const enum stringop_alg unknown_size;
102 const struct stringop_strategy {
104 const enum stringop_alg alg;
105 } size [NAX_STRINGOP_ALGS];
108 /* Define the specific costs for a given cpu */
110 struct processor_costs {
111 const int add; /* cost of an add instruction */
112 const int lea; /* cost of a lea instruction */
113 const int shift_var; /* variable shift costs */
114 const int shift_const; /* constant shift costs */
115 const int mult_init[5]; /* cost of starting a multiply
116 in QImode, HImode, SImode, DImode, TImode*/
117 const int mult_bit; /* cost of multiply per each bit set */
118 const int divide[5]; /* cost of a divide/mod
119 in QImode, HImode, SImode, DImode, TImode*/
120 int movsx; /* The cost of movsx operation. */
121 int movzx; /* The cost of movzx operation. */
122 const int large_insn; /* insns larger than this cost more */
123 const int move_ratio; /* The threshold of number of scalar
124 memory-to-memory move insns. */
125 const int movzbl_load; /* cost of loading using movzbl */
126 const int int_load[3]; /* cost of loading integer registers
127 in QImode, HImode and SImode relative
128 to reg-reg move (2). */
129 const int int_store[3]; /* cost of storing integer register
130 in QImode, HImode and SImode */
131 const int fp_move; /* cost of reg,reg fld/fst */
132 const int fp_load[3]; /* cost of loading FP register
133 in SFmode, DFmode and XFmode */
134 const int fp_store[3]; /* cost of storing FP register
135 in SFmode, DFmode and XFmode */
136 const int mmx_move; /* cost of moving MMX register. */
137 const int mmx_load[2]; /* cost of loading MMX register
138 in SImode and DImode */
139 const int mmx_store[2]; /* cost of storing MMX register
140 in SImode and DImode */
141 const int sse_move; /* cost of moving SSE register. */
142 const int sse_load[3]; /* cost of loading SSE register
143 in SImode, DImode and TImode*/
144 const int sse_store[3]; /* cost of storing SSE register
145 in SImode, DImode and TImode*/
146 const int mmxsse_to_integer; /* cost of moving mmxsse register to
147 integer and vice versa. */
148 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
149 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
150 const int prefetch_block; /* bytes moved to cache for prefetch. */
151 const int simultaneous_prefetches; /* number of parallel prefetch
153 const int branch_cost; /* Default value for BRANCH_COST. */
154 const int fadd; /* cost of FADD and FSUB instructions. */
155 const int fmul; /* cost of FMUL instruction. */
156 const int fdiv; /* cost of FDIV instruction. */
157 const int fabs; /* cost of FABS instruction. */
158 const int fchs; /* cost of FCHS instruction. */
159 const int fsqrt; /* cost of FSQRT instruction. */
160 /* Specify what algorithm
161 to use for stringops on unknown size. */
162 struct stringop_algs memcpy[2], memset[2];
163 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
165 const int scalar_load_cost; /* Cost of scalar load. */
166 const int scalar_store_cost; /* Cost of scalar store. */
167 const int vec_stmt_cost; /* Cost of any vector operation, excluding
168 load, store, vector-to-scalar and
169 scalar-to-vector operation. */
170 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
171 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
172 const int vec_align_load_cost; /* Cost of aligned vector load. */
173 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
174 const int vec_store_cost; /* Cost of vector store. */
175 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
177 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
178 vectorizer cost model. */
181 extern const struct processor_costs *ix86_cost;
182 extern const struct processor_costs ix86_size_cost;
184 #define ix86_cur_cost() \
185 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
187 /* Macros used in the machine description to test the flags. */
189 /* configure can arrange to make this 2, to force a 486. */
191 #ifndef TARGET_CPU_DEFAULT
192 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
195 #ifndef TARGET_FPMATH_DEFAULT
196 #define TARGET_FPMATH_DEFAULT \
197 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
200 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
202 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
203 compile-time constant. */
207 #define TARGET_64BIT 1
209 #define TARGET_64BIT 0
212 #ifndef TARGET_BI_ARCH
214 #if TARGET_64BIT_DEFAULT
215 #define TARGET_64BIT 1
217 #define TARGET_64BIT 0
222 #define HAS_LONG_COND_BRANCH 1
223 #define HAS_LONG_UNCOND_BRANCH 1
225 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
226 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
227 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
228 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
229 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
230 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
231 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
232 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
233 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
234 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
235 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
236 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
237 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
238 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
239 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
240 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
241 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
243 /* Feature tests against the various tunings. */
244 enum ix86_tune_indices {
246 X86_TUNE_PUSH_MEMORY,
247 X86_TUNE_ZERO_EXTEND_WITH_AND,
248 X86_TUNE_UNROLL_STRLEN,
249 X86_TUNE_DEEP_BRANCH_PREDICTION,
250 X86_TUNE_BRANCH_PREDICTION_HINTS,
251 X86_TUNE_DOUBLE_WITH_ADD,
254 X86_TUNE_PARTIAL_REG_STALL,
255 X86_TUNE_PARTIAL_FLAG_REG_STALL,
256 X86_TUNE_USE_HIMODE_FIOP,
257 X86_TUNE_USE_SIMODE_FIOP,
261 X86_TUNE_SPLIT_LONG_MOVES,
262 X86_TUNE_READ_MODIFY_WRITE,
263 X86_TUNE_READ_MODIFY,
264 X86_TUNE_PROMOTE_QIMODE,
265 X86_TUNE_FAST_PREFIX,
266 X86_TUNE_SINGLE_STRINGOP,
267 X86_TUNE_QIMODE_MATH,
268 X86_TUNE_HIMODE_MATH,
269 X86_TUNE_PROMOTE_QI_REGS,
270 X86_TUNE_PROMOTE_HI_REGS,
275 X86_TUNE_INTEGER_DFMODE_MOVES,
276 X86_TUNE_PARTIAL_REG_DEPENDENCY,
277 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
278 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
279 X86_TUNE_SSE_SPLIT_REGS,
280 X86_TUNE_SSE_TYPELESS_STORES,
281 X86_TUNE_SSE_LOAD0_BY_PXOR,
282 X86_TUNE_MEMORY_MISMATCH_STALL,
283 X86_TUNE_PROLOGUE_USING_MOVE,
284 X86_TUNE_EPILOGUE_USING_MOVE,
287 X86_TUNE_INTER_UNIT_MOVES,
288 X86_TUNE_INTER_UNIT_CONVERSIONS,
289 X86_TUNE_FOUR_JUMP_LIMIT,
293 X86_TUNE_PAD_RETURNS,
294 X86_TUNE_EXT_80387_CONSTANTS,
295 X86_TUNE_SHORTEN_X87_SSE,
296 X86_TUNE_AVOID_VECTOR_DECODE,
297 X86_TUNE_PROMOTE_HIMODE_IMUL,
298 X86_TUNE_SLOW_IMUL_IMM32_MEM,
299 X86_TUNE_SLOW_IMUL_IMM8,
300 X86_TUNE_MOVE_M1_VIA_OR,
301 X86_TUNE_NOT_UNPAIRABLE,
302 X86_TUNE_NOT_VECTORMODE,
303 X86_TUNE_USE_VECTOR_FP_CONVERTS,
304 X86_TUNE_USE_VECTOR_CONVERTS,
305 X86_TUNE_FUSE_CMP_AND_BRANCH,
311 extern unsigned char ix86_tune_features[X86_TUNE_LAST];
313 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
314 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
315 #define TARGET_ZERO_EXTEND_WITH_AND \
316 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
317 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
318 #define TARGET_DEEP_BRANCH_PREDICTION \
319 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
320 #define TARGET_BRANCH_PREDICTION_HINTS \
321 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
322 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
323 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
324 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
325 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
326 #define TARGET_PARTIAL_FLAG_REG_STALL \
327 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
328 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
329 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
330 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
331 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
332 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
333 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
334 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
335 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
336 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
337 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
338 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
339 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
340 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
341 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
342 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
343 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4]
344 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8]
345 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4]
346 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8]
347 #define TARGET_INTEGER_DFMODE_MOVES \
348 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
349 #define TARGET_PARTIAL_REG_DEPENDENCY \
350 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
351 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
352 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
353 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
354 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
355 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
356 #define TARGET_SSE_TYPELESS_STORES \
357 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
358 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
359 #define TARGET_MEMORY_MISMATCH_STALL \
360 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
361 #define TARGET_PROLOGUE_USING_MOVE \
362 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
363 #define TARGET_EPILOGUE_USING_MOVE \
364 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
365 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
366 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
367 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
368 #define TARGET_INTER_UNIT_CONVERSIONS\
369 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
370 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
371 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
372 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
373 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
374 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
375 #define TARGET_EXT_80387_CONSTANTS \
376 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
377 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
378 #define TARGET_AVOID_VECTOR_DECODE \
379 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
380 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
381 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
382 #define TARGET_SLOW_IMUL_IMM32_MEM \
383 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
384 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
385 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
386 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
387 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
388 #define TARGET_USE_VECTOR_FP_CONVERTS \
389 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
390 #define TARGET_USE_VECTOR_CONVERTS \
391 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
392 #define TARGET_FUSE_CMP_AND_BRANCH \
393 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
394 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
396 /* Feature tests against the various architecture variations. */
397 enum ix86_arch_indices {
398 X86_ARCH_CMOVE, /* || TARGET_SSE */
407 extern unsigned char ix86_arch_features[X86_ARCH_LAST];
409 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
410 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
411 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
412 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
413 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
415 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
417 extern int x86_prefetch_sse;
419 #define TARGET_PREFETCH_SSE x86_prefetch_sse
421 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
423 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
424 #define TARGET_MIX_SSE_I387 \
425 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
427 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
428 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
429 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
430 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
432 extern int ix86_isa_flags;
434 #ifndef TARGET_64BIT_DEFAULT
435 #define TARGET_64BIT_DEFAULT 0
437 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
438 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
441 /* Fence to use after loop using storent. */
443 extern tree x86_mfence;
444 #define FENCE_FOLLOWING_MOVNT x86_mfence
446 /* Once GDB has been enhanced to deal with functions without frame
447 pointers, we can change this to allow for elimination of
448 the frame pointer in leaf functions. */
449 #define TARGET_DEFAULT 0
451 /* Extra bits to force. */
452 #define TARGET_SUBTARGET_DEFAULT 0
453 #define TARGET_SUBTARGET_ISA_DEFAULT 0
455 /* Extra bits to force on w/ 32-bit mode. */
456 #define TARGET_SUBTARGET32_DEFAULT 0
457 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
459 /* Extra bits to force on w/ 64-bit mode. */
460 #define TARGET_SUBTARGET64_DEFAULT 0
461 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
463 /* This is not really a target flag, but is done this way so that
464 it's analogous to similar code for Mach-O on PowerPC. darwin.h
465 redefines this to 1. */
466 #define TARGET_MACHO 0
468 /* Likewise, for the Windows 64-bit ABI. */
469 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
471 /* Available call abi. */
478 /* The abi used by target. */
479 extern enum calling_abi ix86_abi;
481 /* The default abi used by target. */
482 #define DEFAULT_ABI SYSV_ABI
484 /* Subtargets may reset this to 1 in order to enable 96-bit long double
485 with the rounding mode forced to 53 bits. */
486 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
488 /* Sometimes certain combinations of command options do not make
489 sense on a particular target machine. You can define a macro
490 `OVERRIDE_OPTIONS' to take account of this. This macro, if
491 defined, is executed once just after all the command options have
494 Don't use this macro to turn on various extra optimizations for
495 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
497 #define OVERRIDE_OPTIONS override_options (true)
499 /* Define this to change the optimizations performed by default. */
500 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
501 optimization_options ((LEVEL), (SIZE))
503 /* -march=native handling only makes sense with compiler running on
504 an x86 or x86_64 chip. If changing this condition, also change
505 the condition in driver-i386.c. */
506 #if defined(__i386__) || defined(__x86_64__)
507 /* In driver-i386.c. */
508 extern const char *host_detect_local_cpu (int argc, const char **argv);
509 #define EXTRA_SPEC_FUNCTIONS \
510 { "local_cpu_detect", host_detect_local_cpu },
511 #define HAVE_LOCAL_CPU_DETECT
514 #if TARGET_64BIT_DEFAULT
515 #define OPT_ARCH64 "!m32"
516 #define OPT_ARCH32 "m32"
518 #define OPT_ARCH64 "m64"
519 #define OPT_ARCH32 "!m64"
522 /* Support for configure-time defaults of some command line options.
523 The order here is important so that -march doesn't squash the
524 tune or cpu values. */
525 #define OPTION_DEFAULT_SPECS \
526 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
527 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
528 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
529 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
530 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
531 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
532 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
533 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
534 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
536 /* Specs for the compiler proper */
539 #define CC1_CPU_SPEC_1 "\
541 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \
543 %{mintel-syntax:-masm=intel \
544 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
545 %{mno-intel-syntax:-masm=att \
546 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
548 #ifndef HAVE_LOCAL_CPU_DETECT
549 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
551 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
552 "%{march=native:%<march=native %:local_cpu_detect(arch) \
553 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
554 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
558 /* Target CPU builtins. */
559 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
561 /* Target Pragmas. */
562 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
564 enum target_cpu_default
566 TARGET_CPU_DEFAULT_generic = 0,
568 TARGET_CPU_DEFAULT_i386,
569 TARGET_CPU_DEFAULT_i486,
570 TARGET_CPU_DEFAULT_pentium,
571 TARGET_CPU_DEFAULT_pentium_mmx,
572 TARGET_CPU_DEFAULT_pentiumpro,
573 TARGET_CPU_DEFAULT_pentium2,
574 TARGET_CPU_DEFAULT_pentium3,
575 TARGET_CPU_DEFAULT_pentium4,
576 TARGET_CPU_DEFAULT_pentium_m,
577 TARGET_CPU_DEFAULT_prescott,
578 TARGET_CPU_DEFAULT_nocona,
579 TARGET_CPU_DEFAULT_core2,
580 TARGET_CPU_DEFAULT_atom,
582 TARGET_CPU_DEFAULT_geode,
583 TARGET_CPU_DEFAULT_k6,
584 TARGET_CPU_DEFAULT_k6_2,
585 TARGET_CPU_DEFAULT_k6_3,
586 TARGET_CPU_DEFAULT_athlon,
587 TARGET_CPU_DEFAULT_athlon_sse,
588 TARGET_CPU_DEFAULT_k8,
589 TARGET_CPU_DEFAULT_amdfam10,
591 TARGET_CPU_DEFAULT_max
595 #define CC1_SPEC "%(cc1_cpu) "
598 /* This macro defines names of additional specifications to put in the
599 specs that can be used in various specifications like CC1_SPEC. Its
600 definition is an initializer with a subgrouping for each command option.
602 Each subgrouping contains a string constant, that defines the
603 specification name, and a string constant that used by the GCC driver
606 Do not define this macro if it does not need to do anything. */
608 #ifndef SUBTARGET_EXTRA_SPECS
609 #define SUBTARGET_EXTRA_SPECS
612 #define EXTRA_SPECS \
613 { "cc1_cpu", CC1_CPU_SPEC }, \
614 SUBTARGET_EXTRA_SPECS
617 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
618 FPU, assume that the fpcw is set to extended precision; when using
619 only SSE, rounding is correct; when using both SSE and the FPU,
620 the rounding precision is indeterminate, since either may be chosen
621 apparently at random. */
622 #define TARGET_FLT_EVAL_METHOD \
623 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
625 /* Whether to allow x87 floating-point arithmetic on MODE (one of
626 SFmode, DFmode and XFmode) in the current excess precision
628 #define X87_ENABLE_ARITH(MODE) \
629 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode)
631 /* Likewise, whether to allow direct conversions from integer mode
632 IMODE (HImode, SImode or DImode) to MODE. */
633 #define X87_ENABLE_FLOAT(MODE, IMODE) \
634 (flag_excess_precision == EXCESS_PRECISION_FAST \
635 || (MODE) == XFmode \
636 || ((MODE) == DFmode && (IMODE) == SImode) \
637 || (IMODE) == HImode)
639 /* target machine storage layout */
641 #define SHORT_TYPE_SIZE 16
642 #define INT_TYPE_SIZE 32
643 #define FLOAT_TYPE_SIZE 32
644 #define LONG_TYPE_SIZE BITS_PER_WORD
645 #define DOUBLE_TYPE_SIZE 64
646 #define LONG_LONG_TYPE_SIZE 64
647 #define LONG_DOUBLE_TYPE_SIZE 80
649 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE
651 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
652 #define MAX_BITS_PER_WORD 64
654 #define MAX_BITS_PER_WORD 32
657 /* Define this if most significant byte of a word is the lowest numbered. */
658 /* That is true on the 80386. */
660 #define BITS_BIG_ENDIAN 0
662 /* Define this if most significant byte of a word is the lowest numbered. */
663 /* That is not true on the 80386. */
664 #define BYTES_BIG_ENDIAN 0
666 /* Define this if most significant word of a multiword number is the lowest
668 /* Not true for 80386 */
669 #define WORDS_BIG_ENDIAN 0
671 /* Width of a word, in units (bytes). */
672 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
674 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
676 #define MIN_UNITS_PER_WORD 4
679 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
680 #define PARM_BOUNDARY BITS_PER_WORD
682 /* Boundary (in *bits*) on which stack pointer should be aligned. */
683 #define STACK_BOUNDARY \
684 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
686 /* Stack boundary of the main function guaranteed by OS. */
687 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
689 /* Minimum stack boundary. */
690 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
692 /* Boundary (in *bits*) on which the stack pointer prefers to be
693 aligned; the compiler cannot rely on having this alignment. */
694 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
696 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
697 both 32bit and 64bit, to support codes that need 128 bit stack
698 alignment for SSE instructions, but can't realign the stack. */
699 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128
701 /* 1 if -mstackrealign should be turned on by default. It will
702 generate an alternate prologue and epilogue that realigns the
703 runtime stack if nessary. This supports mixing codes that keep a
704 4-byte aligned stack, as specified by i386 psABI, with codes that
705 need a 16-byte aligned stack, as required by SSE instructions. If
706 STACK_REALIGN_DEFAULT is 1 and PREFERRED_STACK_BOUNDARY_DEFAULT is
707 128, stacks for all functions may be realigned. */
708 #define STACK_REALIGN_DEFAULT 0
710 /* Boundary (in *bits*) on which the incoming stack is aligned. */
711 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
713 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
714 mandatory for the 64-bit ABI, and may or may not be true for other
715 operating systems. */
716 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
718 /* Minimum allocation boundary for the code of a function. */
719 #define FUNCTION_BOUNDARY 8
721 /* C++ stores the virtual bit in the lowest bit of function pointers. */
722 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
724 /* Alignment of field after `int : 0' in a structure. */
726 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
728 /* Minimum size in bits of the largest boundary to which any
729 and all fundamental data types supported by the hardware
730 might need to be aligned. No data type wants to be aligned
733 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
734 and Pentium Pro XFmode values at 128 bit boundaries. */
736 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256: 128)
738 /* Maximum stack alignment. */
739 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
741 /* Alignment value for attribute ((aligned)). It is a constant since
742 it is the part of the ABI. We shouldn't change it with -mavx. */
743 #define ATTRIBUTE_ALIGNED_VALUE 128
745 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
746 #define ALIGN_MODE_128(MODE) \
747 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
749 /* The published ABIs say that doubles should be aligned on word
750 boundaries, so lower the alignment for structure fields unless
751 -malign-double is set. */
753 /* ??? Blah -- this macro is used directly by libobjc. Since it
754 supports no vector modes, cut out the complexity and fall back
755 on BIGGEST_FIELD_ALIGNMENT. */
756 #ifdef IN_TARGET_LIBS
758 #define BIGGEST_FIELD_ALIGNMENT 128
760 #define BIGGEST_FIELD_ALIGNMENT 32
763 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
764 x86_field_alignment (FIELD, COMPUTED)
767 /* If defined, a C expression to compute the alignment given to a
768 constant that is being placed in memory. EXP is the constant
769 and ALIGN is the alignment that the object would ordinarily have.
770 The value of this macro is used instead of that alignment to align
773 If this macro is not defined, then ALIGN is used.
775 The typical use of this macro is to increase alignment for string
776 constants to be word aligned so that `strcpy' calls that copy
777 constants can be done inline. */
779 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
781 /* If defined, a C expression to compute the alignment for a static
782 variable. TYPE is the data type, and ALIGN is the alignment that
783 the object would ordinarily have. The value of this macro is used
784 instead of that alignment to align the object.
786 If this macro is not defined, then ALIGN is used.
788 One use of this macro is to increase alignment of medium-size
789 data to make it all fit in fewer cache lines. Another is to
790 cause character arrays to be word-aligned so that `strcpy' calls
791 that copy constants to character arrays can be done inline. */
793 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
795 /* If defined, a C expression to compute the alignment for a local
796 variable. TYPE is the data type, and ALIGN is the alignment that
797 the object would ordinarily have. The value of this macro is used
798 instead of that alignment to align the object.
800 If this macro is not defined, then ALIGN is used.
802 One use of this macro is to increase alignment of medium-size
803 data to make it all fit in fewer cache lines. */
805 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
806 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
808 /* If defined, a C expression to compute the alignment for stack slot.
809 TYPE is the data type, MODE is the widest mode available, and ALIGN
810 is the alignment that the slot would ordinarily have. The value of
811 this macro is used instead of that alignment to align the slot.
813 If this macro is not defined, then ALIGN is used when TYPE is NULL,
814 Otherwise, LOCAL_ALIGNMENT will be used.
816 One use of this macro is to set alignment of stack slot to the
817 maximum alignment of all possible modes which the slot may have. */
819 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
820 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
822 /* If defined, a C expression to compute the alignment for a local
825 If this macro is not defined, then
826 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.
828 One use of this macro is to increase alignment of medium-size
829 data to make it all fit in fewer cache lines. */
831 #define LOCAL_DECL_ALIGNMENT(DECL) \
832 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))
834 /* If defined, a C expression to compute the minimum required alignment
835 for dynamic stack realignment purposes for EXP (a TYPE or DECL),
836 MODE, assuming normal alignment ALIGN.
838 If this macro is not defined, then (ALIGN) will be used. */
840 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \
841 ix86_minimum_alignment (EXP, MODE, ALIGN)
844 /* If defined, a C expression that gives the alignment boundary, in
845 bits, of an argument with the specified mode and type. If it is
846 not defined, `PARM_BOUNDARY' is used for all arguments. */
848 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
849 ix86_function_arg_boundary ((MODE), (TYPE))
851 /* Set this nonzero if move instructions will actually fail to work
852 when given unaligned data. */
853 #define STRICT_ALIGNMENT 0
855 /* If bit field type is int, don't let it cross an int,
856 and give entire struct the alignment of an int. */
857 /* Required on the 386 since it doesn't have bit-field insns. */
858 #define PCC_BITFIELD_TYPE_MATTERS 1
860 /* Standard register usage. */
862 /* This processor has special stack-like registers. See reg-stack.c
867 #define IS_STACK_MODE(MODE) \
868 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
869 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
872 /* Number of actual hardware registers.
873 The hardware registers are assigned numbers for the compiler
874 from 0 to just below FIRST_PSEUDO_REGISTER.
875 All registers that the compiler knows about must be given numbers,
876 even those that are not normally considered general registers.
878 In the 80386 we give the 8 general purpose registers the numbers 0-7.
879 We number the floating point registers 8-15.
880 Note that registers 0-7 can be accessed as a short or int,
881 while only 0-3 may be used with byte `mov' instructions.
883 Reg 16 does not correspond to any hardware register, but instead
884 appears in the RTL as an argument pointer prior to reload, and is
885 eliminated during reloading in favor of either the stack or frame
888 #define FIRST_PSEUDO_REGISTER 53
890 /* Number of hardware registers that go into the DWARF-2 unwind info.
891 If not defined, equals FIRST_PSEUDO_REGISTER. */
893 #define DWARF_FRAME_REGISTERS 17
895 /* 1 for registers that have pervasive standard uses
896 and are not available for the register allocator.
897 On the 80386, the stack pointer is such, as is the arg pointer.
899 The value is zero if the register is not fixed on either 32 or
900 64 bit targets, one if the register if fixed on both 32 and 64
901 bit targets, two if it is only fixed on 32bit targets and three
902 if its only fixed on 64bit targets.
903 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
905 #define FIXED_REGISTERS \
906 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
907 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
908 /*arg,flags,fpsr,fpcr,frame*/ \
910 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
911 0, 0, 0, 0, 0, 0, 0, 0, \
912 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
913 0, 0, 0, 0, 0, 0, 0, 0, \
914 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
915 2, 2, 2, 2, 2, 2, 2, 2, \
916 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
917 2, 2, 2, 2, 2, 2, 2, 2 }
920 /* 1 for registers not available across function calls.
921 These must include the FIXED_REGISTERS and also any
922 registers that can be used without being saved.
923 The latter must include the registers where values are returned
924 and the register where structure-value addresses are passed.
925 Aside from that, you can include as many other registers as you like.
927 The value is zero if the register is not call used on either 32 or
928 64 bit targets, one if the register if call used on both 32 and 64
929 bit targets, two if it is only call used on 32bit targets and three
930 if its only call used on 64bit targets.
931 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
933 #define CALL_USED_REGISTERS \
934 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
935 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
936 /*arg,flags,fpsr,fpcr,frame*/ \
938 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
939 1, 1, 1, 1, 1, 1, 1, 1, \
940 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
941 1, 1, 1, 1, 1, 1, 1, 1, \
942 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
943 1, 1, 1, 1, 2, 2, 2, 2, \
944 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
945 1, 1, 1, 1, 1, 1, 1, 1 }
947 /* Order in which to allocate registers. Each register must be
948 listed once, even those in FIXED_REGISTERS. List frame pointer
949 late and fixed registers last. Note that, in general, we prefer
950 registers listed in CALL_USED_REGISTERS, keeping the others
951 available for storage of persistent values.
953 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
954 so this is just empty initializer for array. */
956 #define REG_ALLOC_ORDER \
957 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
958 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
959 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
962 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
963 to be rearranged based on a particular function. When using sse math,
964 we want to allocate SSE before x87 registers and vice versa. */
966 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
969 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
971 /* Macro to conditionally modify fixed_regs/call_used_regs. */
972 #define CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage ()
974 /* Return number of consecutive hard regs needed starting at reg REGNO
975 to hold something of mode MODE.
976 This is ordinarily the length in words of a value of mode MODE
977 but can be less for certain modes in special long registers.
979 Actually there are no two word move instructions for consecutive
980 registers. And only registers 0-3 may have mov byte instructions
984 #define HARD_REGNO_NREGS(REGNO, MODE) \
985 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
986 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
987 : ((MODE) == XFmode \
988 ? (TARGET_64BIT ? 2 : 3) \
990 ? (TARGET_64BIT ? 4 : 6) \
991 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
993 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
994 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
995 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
997 : ((MODE) == XFmode || (MODE) == XCmode)) \
1000 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1002 #define VALID_AVX256_REG_MODE(MODE) \
1003 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1004 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)
1006 #define VALID_SSE2_REG_MODE(MODE) \
1007 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1008 || (MODE) == V2DImode || (MODE) == DFmode)
1010 #define VALID_SSE_REG_MODE(MODE) \
1011 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1012 || (MODE) == SFmode || (MODE) == TFmode)
1014 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1015 ((MODE) == V2SFmode || (MODE) == SFmode)
1017 #define VALID_MMX_REG_MODE(MODE) \
1018 ((MODE == V1DImode) || (MODE) == DImode \
1019 || (MODE) == V2SImode || (MODE) == SImode \
1020 || (MODE) == V4HImode || (MODE) == V8QImode)
1022 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
1023 place emms and femms instructions.
1024 FIXME: AVX has 32byte floating point vector operations and 16byte
1025 integer vector operations. But vectorizer doesn't support
1026 different sizes for integer and floating point vectors. We limit
1027 vector size to 16byte. */
1028 #define UNITS_PER_SIMD_WORD(MODE) \
1029 (TARGET_AVX ? (((MODE) == DFmode || (MODE) == SFmode) ? 16 : 16) \
1030 : (TARGET_SSE ? 16 : UNITS_PER_WORD))
1032 #define VALID_DFP_MODE_P(MODE) \
1033 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1035 #define VALID_FP_MODE_P(MODE) \
1036 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1037 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1039 #define VALID_INT_MODE_P(MODE) \
1040 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1041 || (MODE) == DImode \
1042 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1043 || (MODE) == CDImode \
1044 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1045 || (MODE) == TFmode || (MODE) == TCmode)))
1047 /* Return true for modes passed in SSE registers. */
1048 #define SSE_REG_MODE_P(MODE) \
1049 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1050 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1051 || (MODE) == V4SFmode || (MODE) == V4SImode || (MODE) == V32QImode \
1052 || (MODE) == V16HImode || (MODE) == V8SImode || (MODE) == V4DImode \
1053 || (MODE) == V8SFmode || (MODE) == V4DFmode)
1055 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1057 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1058 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1060 /* Value is 1 if it is a good idea to tie two pseudo registers
1061 when one has mode MODE1 and one has mode MODE2.
1062 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1063 for any hard reg, then this must be 0 for correct output. */
1065 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1067 /* It is possible to write patterns to move flags; but until someone
1069 #define AVOID_CCMODE_COPIES
1071 /* Specify the modes required to caller save a given hard regno.
1072 We do this on i386 to prevent flags from being saved at all.
1074 Kill any attempts to combine saving of modes. */
1076 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1077 (CC_REGNO_P (REGNO) ? VOIDmode \
1078 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1079 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1080 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1081 : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode \
1084 /* Specify the registers used for certain standard purposes.
1085 The values of these macros are register numbers. */
1087 /* on the 386 the pc register is %eip, and is not usable as a general
1088 register. The ordinary mov instructions won't work */
1089 /* #define PC_REGNUM */
1091 /* Register to use for pushing function arguments. */
1092 #define STACK_POINTER_REGNUM 7
1094 /* Base register for access to local variables of the function. */
1095 #define HARD_FRAME_POINTER_REGNUM 6
1097 /* Base register for access to local variables of the function. */
1098 #define FRAME_POINTER_REGNUM 20
1100 /* First floating point reg */
1101 #define FIRST_FLOAT_REG 8
1103 /* First & last stack-like regs */
1104 #define FIRST_STACK_REG FIRST_FLOAT_REG
1105 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1107 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1108 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1110 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1111 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1113 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1114 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1116 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1117 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1119 /* Override this in other tm.h files to cope with various OS lossage
1120 requiring a frame pointer. */
1121 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1122 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1125 /* Make sure we can access arbitrary call frames. */
1126 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1128 /* Base register for access to arguments of the function. */
1129 #define ARG_POINTER_REGNUM 16
1131 /* Register in which static-chain is passed to a function.
1132 We do use ECX as static chain register for 32 bit ABI. On the
1133 64bit ABI, ECX is an argument register, so we use R10 instead. */
1134 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? R10_REG : CX_REG)
1136 /* Register to hold the addressing base for position independent
1137 code access to data items. We don't use PIC pointer for 64bit
1138 mode. Define the regnum to dummy value to prevent gcc from
1139 pessimizing code dealing with EBX.
1141 To avoid clobbering a call-saved register unnecessarily, we renumber
1142 the pic register when possible. The change is visible after the
1143 prologue has been emitted. */
1145 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG
1147 #define PIC_OFFSET_TABLE_REGNUM \
1148 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1149 || !flag_pic ? INVALID_REGNUM \
1150 : reload_completed ? REGNO (pic_offset_table_rtx) \
1151 : REAL_PIC_OFFSET_TABLE_REGNUM)
1153 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1155 /* This is overridden by <cygwin.h>. */
1156 #define MS_AGGREGATE_RETURN 0
1158 /* This is overridden by <netware.h>. */
1159 #define KEEP_AGGREGATE_RETURN_POINTER 0
1161 /* Define the classes of registers for register constraints in the
1162 machine description. Also define ranges of constants.
1164 One of the classes must always be named ALL_REGS and include all hard regs.
1165 If there is more than one class, another class must be named NO_REGS
1166 and contain no registers.
1168 The name GENERAL_REGS must be the name of a class (or an alias for
1169 another name such as ALL_REGS). This is the class of registers
1170 that is allowed by "g" or "r" in a register constraint.
1171 Also, registers outside this class are allocated only when
1172 instructions express preferences for them.
1174 The classes must be numbered in nondecreasing order; that is,
1175 a larger-numbered class must never be contained completely
1176 in a smaller-numbered class.
1178 For any two classes, it is very desirable that there be another
1179 class that represents their union.
1181 It might seem that class BREG is unnecessary, since no useful 386
1182 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1183 and the "b" register constraint is useful in asms for syscalls.
1185 The flags, fpsr and fpcr registers are in no class. */
1190 AREG, DREG, CREG, BREG, SIREG, DIREG,
1191 AD_REGS, /* %eax/%edx for DImode */
1192 CLOBBERED_REGS, /* call-clobbered integers */
1193 Q_REGS, /* %eax %ebx %ecx %edx */
1194 NON_Q_REGS, /* %esi %edi %ebp %esp */
1195 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1196 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1197 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1198 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1209 ALL_REGS, LIM_REG_CLASSES
1212 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1214 #define INTEGER_CLASS_P(CLASS) \
1215 reg_class_subset_p ((CLASS), GENERAL_REGS)
1216 #define FLOAT_CLASS_P(CLASS) \
1217 reg_class_subset_p ((CLASS), FLOAT_REGS)
1218 #define SSE_CLASS_P(CLASS) \
1219 reg_class_subset_p ((CLASS), SSE_REGS)
1220 #define MMX_CLASS_P(CLASS) \
1221 ((CLASS) == MMX_REGS)
1222 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1223 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1224 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1225 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1226 #define MAYBE_SSE_CLASS_P(CLASS) \
1227 reg_classes_intersect_p (SSE_REGS, (CLASS))
1228 #define MAYBE_MMX_CLASS_P(CLASS) \
1229 reg_classes_intersect_p (MMX_REGS, (CLASS))
1231 #define Q_CLASS_P(CLASS) \
1232 reg_class_subset_p ((CLASS), Q_REGS)
1234 /* Give names of register classes as strings for dump file. */
1236 #define REG_CLASS_NAMES \
1238 "AREG", "DREG", "CREG", "BREG", \
1242 "Q_REGS", "NON_Q_REGS", \
1246 "FP_TOP_REG", "FP_SECOND_REG", \
1251 "FP_TOP_SSE_REGS", \
1252 "FP_SECOND_SSE_REGS", \
1256 "FLOAT_INT_SSE_REGS", \
1259 /* Define which registers fit in which classes. This is an initializer
1260 for a vector of HARD_REG_SET of length N_REG_CLASSES.
1262 Note that the default setting of CLOBBERED_REGS is for 32-bit; this
1263 is adjusted by CONDITIONAL_REGISTER_USAGE for the 64-bit ABI in effect. */
1265 #define REG_CLASS_CONTENTS \
1267 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1268 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1269 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1270 { 0x03, 0x0 }, /* AD_REGS */ \
1271 { 0x07, 0x0 }, /* CLOBBERED_REGS */ \
1272 { 0x0f, 0x0 }, /* Q_REGS */ \
1273 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1274 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1275 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1276 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1277 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1278 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1279 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1280 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1281 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1282 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1283 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1284 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1285 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1286 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1287 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1288 { 0xffffffff,0x1fffff } \
1291 /* The following macro defines cover classes for Integrated Register
1292 Allocator. Cover classes is a set of non-intersected register
1293 classes covering all hard registers used for register allocation
1294 purpose. Any move between two registers of a cover class should be
1295 cheaper than load or store of the registers. The macro value is
1296 array of register classes with LIM_REG_CLASSES used as the end
1299 #define IRA_COVER_CLASSES \
1301 GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES \
1304 /* The same information, inverted:
1305 Return the class number of the smallest class containing
1306 reg number REGNO. This could be a conditional expression
1307 or could index an array. */
1309 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1311 /* When defined, the compiler allows registers explicitly used in the
1312 rtl to be used as spill registers but prevents the compiler from
1313 extending the lifetime of these registers. */
1315 #define SMALL_REGISTER_CLASSES 1
1317 #define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG)
1319 #define GENERAL_REGNO_P(N) \
1320 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1322 #define GENERAL_REG_P(X) \
1323 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1325 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1327 #define REX_INT_REGNO_P(N) \
1328 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1329 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1331 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1332 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1333 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1334 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1336 #define X87_FLOAT_MODE_P(MODE) \
1337 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1339 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1340 #define SSE_REGNO_P(N) \
1341 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1342 || REX_SSE_REGNO_P (N))
1344 #define REX_SSE_REGNO_P(N) \
1345 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1347 #define SSE_REGNO(N) \
1348 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1350 #define SSE_FLOAT_MODE_P(MODE) \
1351 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1353 #define SSE_VEC_FLOAT_MODE_P(MODE) \
1354 ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode))
1356 #define AVX_FLOAT_MODE_P(MODE) \
1357 (TARGET_AVX && ((MODE) == SFmode || (MODE) == DFmode))
1359 #define AVX128_VEC_FLOAT_MODE_P(MODE) \
1360 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode))
1362 #define AVX256_VEC_FLOAT_MODE_P(MODE) \
1363 (TARGET_AVX && ((MODE) == V8SFmode || (MODE) == V4DFmode))
1365 #define AVX_VEC_FLOAT_MODE_P(MODE) \
1366 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1367 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1369 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1370 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1372 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1373 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1375 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1377 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1378 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1380 /* The class value for index registers, and the one for base regs. */
1382 #define INDEX_REG_CLASS INDEX_REGS
1383 #define BASE_REG_CLASS GENERAL_REGS
1385 /* Place additional restrictions on the register class to use when it
1386 is necessary to be able to hold a value of mode MODE in a reload
1387 register for which class CLASS would ordinarily be used. */
1389 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1390 ((MODE) == QImode && !TARGET_64BIT \
1391 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1392 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1395 /* Given an rtx X being reloaded into a reg required to be
1396 in class CLASS, return the class of reg to actually use.
1397 In general this is just CLASS; but on some machines
1398 in some cases it is preferable to use a more restrictive class.
1399 On the 80386 series, we prevent floating constants from being
1400 reloaded into floating registers (since no move-insn can do that)
1401 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1403 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1404 QImode must go into class Q_REGS.
1405 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1406 movdf to do mem-to-mem moves through integer regs. */
1408 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1409 ix86_preferred_reload_class ((X), (CLASS))
1411 /* Discourage putting floating-point values in SSE registers unless
1412 SSE math is being used, and likewise for the 387 registers. */
1414 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1415 ix86_preferred_output_reload_class ((X), (CLASS))
1417 /* If we are copying between general and FP registers, we need a memory
1418 location. The same is true for SSE and MMX registers. */
1419 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1420 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1422 /* Get_secondary_mem widens integral modes to BITS_PER_WORD.
1423 There is no need to emit full 64 bit move on 64 bit targets
1424 for integral modes that can be moved using 32 bit move. */
1425 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1426 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \
1427 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1430 /* Return the maximum number of consecutive registers
1431 needed to represent mode MODE in a register of class CLASS. */
1432 /* On the 80386, this is the size of MODE in words,
1433 except in the FP regs, where a single reg is always enough. */
1434 #define CLASS_MAX_NREGS(CLASS, MODE) \
1435 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1436 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1437 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1438 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1440 /* A C expression whose value is nonzero if pseudos that have been
1441 assigned to registers of class CLASS would likely be spilled
1442 because registers of CLASS are needed for spill registers.
1444 The default value of this macro returns 1 if CLASS has exactly one
1445 register and zero otherwise. On most machines, this default
1446 should be used. Only define this macro to some other expression
1447 if pseudo allocated by `local-alloc.c' end up in memory because
1448 their hard registers were needed for spill registers. If this
1449 macro returns nonzero for those classes, those pseudos will only
1450 be allocated by `global.c', which knows how to reallocate the
1451 pseudo to another register. If there would not be another
1452 register available for reallocation, you should not change the
1453 definition of this macro since the only effect of such a
1454 definition would be to slow down register allocation. */
1456 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1457 (((CLASS) == AREG) \
1458 || ((CLASS) == DREG) \
1459 || ((CLASS) == CREG) \
1460 || ((CLASS) == BREG) \
1461 || ((CLASS) == AD_REGS) \
1462 || ((CLASS) == SIREG) \
1463 || ((CLASS) == DIREG) \
1464 || ((CLASS) == SSE_FIRST_REG) \
1465 || ((CLASS) == FP_TOP_REG) \
1466 || ((CLASS) == FP_SECOND_REG))
1468 /* Return a class of registers that cannot change FROM mode to TO mode. */
1470 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1471 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1473 /* Stack layout; function entry, exit and calling. */
1475 /* Define this if pushing a word on the stack
1476 makes the stack pointer a smaller address. */
1477 #define STACK_GROWS_DOWNWARD
1479 /* Define this to nonzero if the nominal address of the stack frame
1480 is at the high-address end of the local variables;
1481 that is, each additional local variable allocated
1482 goes at a more negative offset in the frame. */
1483 #define FRAME_GROWS_DOWNWARD 1
1485 /* Offset within stack frame to start allocating local variables at.
1486 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1487 first local allocated. Otherwise, it is the offset to the BEGINNING
1488 of the first local allocated. */
1489 #define STARTING_FRAME_OFFSET 0
1491 /* If we generate an insn to push BYTES bytes,
1492 this says how many the stack pointer really advances by.
1493 On 386, we have pushw instruction that decrements by exactly 2 no
1494 matter what the position was, there is no pushb.
1495 But as CIE data alignment factor on this arch is -4, we need to make
1496 sure all stack pointer adjustments are in multiple of 4.
1498 For 64bit ABI we round up to 8 bytes.
1501 #define PUSH_ROUNDING(BYTES) \
1503 ? (((BYTES) + 7) & (-8)) \
1504 : (((BYTES) + 3) & (-4)))
1506 /* If defined, the maximum amount of space required for outgoing arguments will
1507 be computed and placed into the variable
1508 `crtl->outgoing_args_size'. No space will be pushed onto the
1509 stack for each call; instead, the function prologue should increase the stack
1510 frame size by this amount.
1512 MS ABI seem to require 16 byte alignment everywhere except for function
1513 prologue and apilogue. This is not possible without
1514 ACCUMULATE_OUTGOING_ARGS. */
1516 #define ACCUMULATE_OUTGOING_ARGS \
1517 (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI)
1519 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1520 instructions to pass outgoing arguments. */
1522 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1524 /* We want the stack and args grow in opposite directions, even if
1526 #define PUSH_ARGS_REVERSED 1
1528 /* Offset of first parameter from the argument pointer register value. */
1529 #define FIRST_PARM_OFFSET(FNDECL) 0
1531 /* Define this macro if functions should assume that stack space has been
1532 allocated for arguments even when their values are passed in registers.
1534 The value of this macro is the size, in bytes, of the area reserved for
1535 arguments passed in registers for the function represented by FNDECL.
1537 This space can be allocated by the caller, or be a part of the
1538 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1540 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1542 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1543 (ix86_function_type_abi (FNTYPE) == MS_ABI)
1545 /* Value is the number of bytes of arguments automatically
1546 popped when returning from a subroutine call.
1547 FUNDECL is the declaration node of the function (as a tree),
1548 FUNTYPE is the data type of the function (as a tree),
1549 or for a library call it is an identifier node for the subroutine name.
1550 SIZE is the number of bytes of arguments passed on the stack.
1552 On the 80386, the RTD insn may be used to pop them if the number
1553 of args is fixed, but if the number is variable then the caller
1554 must pop them all. RTD can't be used for library calls now
1555 because the library is compiled with the Unix compiler.
1556 Use of RTD is a selectable option, since it is incompatible with
1557 standard Unix calling sequences. If the option is not selected,
1558 the caller must always pop the args.
1560 The attribute stdcall is equivalent to RTD on a per module basis. */
1562 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1563 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1565 #define FUNCTION_VALUE_REGNO_P(N) ix86_function_value_regno_p (N)
1567 /* Define how to find the value returned by a library function
1568 assuming the value has mode MODE. */
1570 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1572 /* Define the size of the result block used for communication between
1573 untyped_call and untyped_return. The block contains a DImode value
1574 followed by the block used by fnsave and frstor. */
1576 #define APPLY_RESULT_SIZE (8+108)
1578 /* 1 if N is a possible register number for function argument passing. */
1579 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1581 /* Define a data type for recording info about an argument list
1582 during the scan of that argument list. This data type should
1583 hold all necessary information about the function itself
1584 and about the args processed so far, enough to enable macros
1585 such as FUNCTION_ARG to determine where the next arg should go. */
1587 typedef struct ix86_args {
1588 int words; /* # words passed so far */
1589 int nregs; /* # registers available for passing */
1590 int regno; /* next available register number */
1591 int fastcall; /* fastcall calling convention is used */
1592 int sse_words; /* # sse words passed so far */
1593 int sse_nregs; /* # sse registers available for passing */
1594 int warn_avx; /* True when we want to warn about AVX ABI. */
1595 int warn_sse; /* True when we want to warn about SSE ABI. */
1596 int warn_mmx; /* True when we want to warn about MMX ABI. */
1597 int sse_regno; /* next available sse register number */
1598 int mmx_words; /* # mmx words passed so far */
1599 int mmx_nregs; /* # mmx registers available for passing */
1600 int mmx_regno; /* next available mmx register number */
1601 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1602 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1603 be passed in SSE registers. Otherwise 0. */
1604 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1605 MS_ABI for ms abi. */
1608 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1609 for a call to a function whose data type is FNTYPE.
1610 For a library call, FNTYPE is 0. */
1612 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1613 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1615 /* Update the data in CUM to advance over an argument
1616 of mode MODE and data type TYPE.
1617 (TYPE is null for libcalls where that information may not be available.) */
1619 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1620 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1622 /* Define where to put the arguments to a function.
1623 Value is zero to push the argument on the stack,
1624 or a hard register in which to store the argument.
1626 MODE is the argument's machine mode.
1627 TYPE is the data type of the argument (as a tree).
1628 This is null for libcalls where that information may
1630 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1631 the preceding args and about the function being called.
1632 NAMED is nonzero if this argument is a named parameter
1633 (otherwise it is an extra parameter matching an ellipsis). */
1635 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1636 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1638 #define TARGET_ASM_FILE_END ix86_file_end
1639 #define NEED_INDICATE_EXEC_STACK 0
1641 /* Output assembler code to FILE to increment profiler label # LABELNO
1642 for profiling a function entry. */
1644 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1646 #define MCOUNT_NAME "_mcount"
1648 #define PROFILE_COUNT_REGISTER "edx"
1650 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1651 the stack pointer does not matter. The value is tested only in
1652 functions that have frame pointers.
1653 No definition is equivalent to always zero. */
1654 /* Note on the 386 it might be more efficient not to define this since
1655 we have to restore it ourselves from the frame pointer, in order to
1658 #define EXIT_IGNORE_STACK 1
1660 /* Output assembler code for a block containing the constant parts
1661 of a trampoline, leaving space for the variable parts. */
1663 /* On the 386, the trampoline contains two instructions:
1666 The trampoline is generated entirely at runtime. The operand of JMP
1667 is the address of FUNCTION relative to the instruction following the
1668 JMP (which is 5 bytes long). */
1670 /* Length in units of the trampoline for entering a nested function. */
1672 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1674 /* Emit RTL insns to initialize the variable parts of a trampoline.
1675 FNADDR is an RTX for the address of the function's pure code.
1676 CXT is an RTX for the static chain value for the function. */
1678 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1679 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1681 /* Definitions for register eliminations.
1683 This is an array of structures. Each structure initializes one pair
1684 of eliminable registers. The "from" register number is given first,
1685 followed by "to". Eliminations of the same "from" register are listed
1686 in order of preference.
1688 There are two registers that can always be eliminated on the i386.
1689 The frame pointer and the arg pointer can be replaced by either the
1690 hard frame pointer or to the stack pointer, depending upon the
1691 circumstances. The hard frame pointer is not used before reload and
1692 so it is not eligible for elimination. */
1694 #define ELIMINABLE_REGS \
1695 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1696 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1697 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1698 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1700 /* Given FROM and TO register numbers, say whether this elimination is
1703 #define CAN_ELIMINATE(FROM, TO) ix86_can_eliminate ((FROM), (TO))
1705 /* Define the offset between two registers, one to be eliminated, and the other
1706 its replacement, at the start of a routine. */
1708 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1709 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1711 /* Addressing modes, and classification of registers for them. */
1713 /* Macros to check register numbers against specific register classes. */
1715 /* These assume that REGNO is a hard or pseudo reg number.
1716 They give nonzero only if REGNO is a hard reg of the suitable class
1717 or a pseudo reg currently allocated to a suitable hard reg.
1718 Since they use reg_renumber, they are safe only once reg_renumber
1719 has been allocated, which happens in local-alloc.c. */
1721 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1722 ((REGNO) < STACK_POINTER_REGNUM \
1723 || REX_INT_REGNO_P (REGNO) \
1724 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1725 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1727 #define REGNO_OK_FOR_BASE_P(REGNO) \
1728 (GENERAL_REGNO_P (REGNO) \
1729 || (REGNO) == ARG_POINTER_REGNUM \
1730 || (REGNO) == FRAME_POINTER_REGNUM \
1731 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1733 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1734 and check its validity for a certain class.
1735 We have two alternate definitions for each of them.
1736 The usual definition accepts all pseudo regs; the other rejects
1737 them unless they have been allocated suitable hard regs.
1738 The symbol REG_OK_STRICT causes the latter definition to be used.
1740 Most source files want to accept pseudo regs in the hope that
1741 they will get allocated to the class that the insn wants them to be in.
1742 Source files for reload pass need to be strict.
1743 After reload, it makes no difference, since pseudo regs have
1744 been eliminated by then. */
1747 /* Non strict versions, pseudos are ok. */
1748 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1749 (REGNO (X) < STACK_POINTER_REGNUM \
1750 || REX_INT_REGNO_P (REGNO (X)) \
1751 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1753 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1754 (GENERAL_REGNO_P (REGNO (X)) \
1755 || REGNO (X) == ARG_POINTER_REGNUM \
1756 || REGNO (X) == FRAME_POINTER_REGNUM \
1757 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1759 /* Strict versions, hard registers only */
1760 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1761 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1763 #ifndef REG_OK_STRICT
1764 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1765 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1768 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1769 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1772 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1773 that is a valid memory address for an instruction.
1774 The MODE argument is the machine mode for the MEM expression
1775 that wants to use this address.
1777 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P,
1778 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1780 See legitimize_pic_address in i386.c for details as to what
1781 constitutes a legitimate address when -fpic is used. */
1783 #define MAX_REGS_PER_ADDRESS 2
1785 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1787 /* Nonzero if the constant value X is a legitimate general operand.
1788 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1790 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1792 /* If defined, a C expression to determine the base term of address X.
1793 This macro is used in only one place: `find_base_term' in alias.c.
1795 It is always safe for this macro to not be defined. It exists so
1796 that alias analysis can understand machine-dependent addresses.
1798 The typical use of this macro is to handle addresses containing
1799 a label_ref or symbol_ref within an UNSPEC. */
1801 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1803 /* Nonzero if the constant value X is a legitimate general operand
1804 when generating PIC code. It is given that flag_pic is on and
1805 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1807 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1809 #define SYMBOLIC_CONST(X) \
1810 (GET_CODE (X) == SYMBOL_REF \
1811 || GET_CODE (X) == LABEL_REF \
1812 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1814 /* Max number of args passed in registers. If this is more than 3, we will
1815 have problems with ebx (register #4), since it is a caller save register and
1816 is also used as the pic register in ELF. So for now, don't allow more than
1817 3 registers to be passed in registers. */
1819 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1820 #define X86_64_REGPARM_MAX 6
1821 #define X86_64_MS_REGPARM_MAX 4
1823 #define X86_32_REGPARM_MAX 3
1825 #define REGPARM_MAX \
1826 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_REGPARM_MAX \
1827 : X86_64_REGPARM_MAX) \
1828 : X86_32_REGPARM_MAX)
1830 #define X86_64_SSE_REGPARM_MAX 8
1831 #define X86_64_MS_SSE_REGPARM_MAX 4
1833 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? 3 : 0)
1835 #define SSE_REGPARM_MAX \
1836 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_SSE_REGPARM_MAX \
1837 : X86_64_SSE_REGPARM_MAX) \
1838 : X86_32_SSE_REGPARM_MAX)
1840 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1843 /* Specify the machine mode that this machine uses
1844 for the index in the tablejump instruction. */
1845 #define CASE_VECTOR_MODE \
1846 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1848 /* Define this as 1 if `char' should by default be signed; else as 0. */
1849 #define DEFAULT_SIGNED_CHAR 1
1851 /* Max number of bytes we can move from memory to memory
1852 in one reasonably fast instruction. */
1855 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1856 move efficiently, as opposed to MOVE_MAX which is the maximum
1857 number of bytes we can move with a single instruction. */
1858 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1860 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1861 move-instruction pairs, we will do a movmem or libcall instead.
1862 Increasing the value will always make code faster, but eventually
1863 incurs high cost in increased code size.
1865 If you don't define this, a reasonable default is used. */
1867 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1869 /* If a clear memory operation would take CLEAR_RATIO or more simple
1870 move-instruction sequences, we will do a clrmem or libcall instead. */
1872 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
1874 /* Define if shifts truncate the shift count
1875 which implies one can omit a sign-extension or zero-extension
1876 of a shift count. */
1877 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1879 /* #define SHIFT_COUNT_TRUNCATED */
1881 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1882 is done just by pretending it is already truncated. */
1883 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1885 /* A macro to update M and UNSIGNEDP when an object whose type is
1886 TYPE and which has the specified mode and signedness is to be
1887 stored in a register. This macro is only called when TYPE is a
1890 On i386 it is sometimes useful to promote HImode and QImode
1891 quantities to SImode. The choice depends on target type. */
1893 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1895 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1896 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1900 /* Specify the machine mode that pointers have.
1901 After generation of rtl, the compiler makes no further distinction
1902 between pointers and any other objects of this machine mode. */
1903 #define Pmode (TARGET_64BIT ? DImode : SImode)
1905 /* A function address in a call instruction
1906 is a byte address (for indexing purposes)
1907 so give the MEM rtx a byte's mode. */
1908 #define FUNCTION_MODE QImode
1910 /* A C expression for the cost of moving data from a register in class FROM to
1911 one in class TO. The classes are expressed using the enumeration values
1912 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1913 interpreted relative to that.
1915 It is not required that the cost always equal 2 when FROM is the same as TO;
1916 on some machines it is expensive to move between registers if they are not
1917 general registers. */
1919 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1920 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1922 /* A C expression for the cost of moving data of mode M between a
1923 register and memory. A value of 2 is the default; this cost is
1924 relative to those in `REGISTER_MOVE_COST'.
1926 If moving between registers and memory is more expensive than
1927 between two registers, you should define this macro to express the
1930 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1931 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1933 /* A C expression for the cost of a branch instruction. A value of 1
1934 is the default; other values are interpreted relative to that. */
1936 #define BRANCH_COST(speed_p, predictable_p) \
1937 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1939 /* Define this macro as a C expression which is nonzero if accessing
1940 less than a word of memory (i.e. a `char' or a `short') is no
1941 faster than accessing a word of memory, i.e., if such access
1942 require more than one instruction or if there is no difference in
1943 cost between byte and (aligned) word loads.
1945 When this macro is not defined, the compiler will access a field by
1946 finding the smallest containing object; when it is defined, a
1947 fullword load will be used if alignment permits. Unless bytes
1948 accesses are faster than word accesses, using word accesses is
1949 preferable since it may eliminate subsequent memory access if
1950 subsequent accesses occur to other fields in the same word of the
1951 structure, but to different bytes. */
1953 #define SLOW_BYTE_ACCESS 0
1955 /* Nonzero if access to memory by shorts is slow and undesirable. */
1956 #define SLOW_SHORT_ACCESS 0
1958 /* Define this macro to be the value 1 if unaligned accesses have a
1959 cost many times greater than aligned accesses, for example if they
1960 are emulated in a trap handler.
1962 When this macro is nonzero, the compiler will act as if
1963 `STRICT_ALIGNMENT' were nonzero when generating code for block
1964 moves. This can cause significantly more instructions to be
1965 produced. Therefore, do not set this macro nonzero if unaligned
1966 accesses only add a cycle or two to the time for a memory access.
1968 If the value of this macro is always zero, it need not be defined. */
1970 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1972 /* Define this macro if it is as good or better to call a constant
1973 function address than to call an address kept in a register.
1975 Desirable on the 386 because a CALL with a constant address is
1976 faster than one with a register address. */
1978 #define NO_FUNCTION_CSE
1980 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1981 return the mode to be used for the comparison.
1983 For floating-point equality comparisons, CCFPEQmode should be used.
1984 VOIDmode should be used in all other cases.
1986 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1987 possible, to allow for more combinations. */
1989 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1991 /* Return nonzero if MODE implies a floating point inequality can be
1994 #define REVERSIBLE_CC_MODE(MODE) 1
1996 /* A C expression whose value is reversed condition code of the CODE for
1997 comparison done in CC_MODE mode. */
1998 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2001 /* Control the assembler format that we output, to the extent
2002 this does not vary between assemblers. */
2004 /* How to refer to registers in assembler output.
2005 This sequence is indexed by compiler's hard-register-number (see above). */
2007 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2008 For non floating point regs, the following are the HImode names.
2010 For float regs, the stack top is sometimes referred to as "%st(0)"
2011 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2013 #define HI_REGISTER_NAMES \
2014 {"ax","dx","cx","bx","si","di","bp","sp", \
2015 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2016 "argp", "flags", "fpsr", "fpcr", "frame", \
2017 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2018 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2019 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2020 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2022 #define REGISTER_NAMES HI_REGISTER_NAMES
2024 /* Table of additional register names to use in user input. */
2026 #define ADDITIONAL_REGISTER_NAMES \
2027 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2028 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2029 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2030 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2031 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2032 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2034 /* Note we are omitting these since currently I don't know how
2035 to get gcc to use these, since they want the same but different
2036 number as al, and ax.
2039 #define QI_REGISTER_NAMES \
2040 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2042 /* These parallel the array above, and can be used to access bits 8:15
2043 of regs 0 through 3. */
2045 #define QI_HIGH_REGISTER_NAMES \
2046 {"ah", "dh", "ch", "bh", }
2048 /* How to renumber registers for dbx and gdb. */
2050 #define DBX_REGISTER_NUMBER(N) \
2051 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2053 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2054 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2055 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2057 /* Before the prologue, RA is at 0(%esp). */
2058 #define INCOMING_RETURN_ADDR_RTX \
2059 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2061 /* After the prologue, RA is at -4(AP) in the current frame. */
2062 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2064 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2065 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2067 /* PC is dbx register 8; let's use that column for RA. */
2068 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2070 /* Before the prologue, the top of the frame is at 4(%esp). */
2071 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2073 /* Describe how we implement __builtin_eh_return. */
2074 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2075 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2078 /* Select a format to encode pointers in exception handling data. CODE
2079 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2080 true if the symbol may be affected by dynamic relocations.
2082 ??? All x86 object file formats are capable of representing this.
2083 After all, the relocation needed is the same as for the call insn.
2084 Whether or not a particular assembler allows us to enter such, I
2085 guess we'll have to see. */
2086 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2087 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2089 /* This is how to output an insn to push a register on the stack.
2090 It need not be very fast code. */
2092 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2095 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2096 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2098 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2101 /* This is how to output an insn to pop a register from the stack.
2102 It need not be very fast code. */
2104 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2107 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2108 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2110 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2113 /* This is how to output an element of a case-vector that is absolute. */
2115 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2116 ix86_output_addr_vec_elt ((FILE), (VALUE))
2118 /* This is how to output an element of a case-vector that is relative. */
2120 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2121 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2123 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is
2126 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
2128 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
2137 /* A C statement or statements which output an assembler instruction
2138 opcode to the stdio stream STREAM. The macro-operand PTR is a
2139 variable of type `char *' which points to the opcode name in
2140 its "internal" form--the form that is written in the machine
2143 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2144 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2146 /* A C statement to output to the stdio stream FILE an assembler
2147 command to pad the location counter to a multiple of 1<<LOG
2148 bytes if it is within MAX_SKIP bytes. */
2150 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2151 #undef ASM_OUTPUT_MAX_SKIP_PAD
2152 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \
2155 if ((MAX_SKIP) == 0) \
2156 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2158 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \
2162 /* Under some conditions we need jump tables in the text section,
2163 because the assembler cannot handle label differences between
2164 sections. This is the case for x86_64 on Mach-O for example. */
2166 #define JUMP_TABLES_IN_TEXT_SECTION \
2167 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2168 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2170 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2171 and switch back. For x86 we do this only to save a few bytes that
2172 would otherwise be unused in the text section. */
2173 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2174 asm (SECTION_OP "\n\t" \
2175 "call " USER_LABEL_PREFIX #FUNC "\n" \
2176 TEXT_SECTION_ASM_OP);
2178 /* Print operand X (an rtx) in assembler syntax to file FILE.
2179 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2180 Effect of various CODE letters is described in i386.c near
2181 print_operand function. */
2183 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2184 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';')
2186 #define PRINT_OPERAND(FILE, X, CODE) \
2187 print_operand ((FILE), (X), (CODE))
2189 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2190 print_operand_address ((FILE), (ADDR))
2192 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2194 if (! output_addr_const_extra (FILE, (X))) \
2198 /* Which processor to schedule for. The cpu attribute defines a list that
2199 mirrors this list, so changes to i386.md must be made at the same time. */
2203 PROCESSOR_I386 = 0, /* 80386 */
2204 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2206 PROCESSOR_PENTIUMPRO,
2214 PROCESSOR_GENERIC32,
2215 PROCESSOR_GENERIC64,
2221 extern enum processor_type ix86_tune;
2222 extern enum processor_type ix86_arch;
2230 extern enum fpmath_unit ix86_fpmath;
2239 extern enum tls_dialect ix86_tls_dialect;
2242 CM_32, /* The traditional 32-bit ABI. */
2243 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2244 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2245 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2246 CM_LARGE, /* No assumptions. */
2247 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2248 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2249 CM_LARGE_PIC /* No assumptions. */
2252 extern enum cmodel ix86_cmodel;
2254 /* Size of the RED_ZONE area. */
2255 #define RED_ZONE_SIZE 128
2256 /* Reserved area of the red zone for temporaries. */
2257 #define RED_ZONE_RESERVE 8
2264 extern enum asm_dialect ix86_asm_dialect;
2265 extern unsigned int ix86_preferred_stack_boundary;
2266 extern unsigned int ix86_incoming_stack_boundary;
2267 extern int ix86_branch_cost, ix86_section_threshold;
2269 /* Smallest class containing REGNO. */
2270 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2272 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2273 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2275 enum ix86_fpcmp_strategy {
2281 /* To properly truncate FP values into integers, we need to set i387 control
2282 word. We can't emit proper mode switching code before reload, as spills
2283 generated by reload may truncate values incorrectly, but we still can avoid
2284 redundant computation of new control word by the mode switching pass.
2285 The fldcw instructions are still emitted redundantly, but this is probably
2286 not going to be noticeable problem, as most CPUs do have fast path for
2289 The machinery is to emit simple truncation instructions and split them
2290 before reload to instructions having USEs of two memory locations that
2291 are filled by this code to old and new control word.
2293 Post-reload pass may be later used to eliminate the redundant fildcw if
2305 enum ix86_stack_slot
2314 MAX_386_STACK_LOCALS
2317 /* Define this macro if the port needs extra instructions inserted
2318 for mode switching in an optimizing compilation. */
2320 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2321 ix86_optimize_mode_switching[(ENTITY)]
2323 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2324 initializer for an array of integers. Each initializer element N
2325 refers to an entity that needs mode switching, and specifies the
2326 number of different modes that might need to be set for this
2327 entity. The position of the initializer in the initializer -
2328 starting counting at zero - determines the integer that is used to
2329 refer to the mode-switched entity in question. */
2331 #define NUM_MODES_FOR_MODE_SWITCHING \
2332 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2334 /* ENTITY is an integer specifying a mode-switched entity. If
2335 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2336 return an integer value not larger than the corresponding element
2337 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2338 must be switched into prior to the execution of INSN. */
2340 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2342 /* This macro specifies the order in which modes for ENTITY are
2343 processed. 0 is the highest priority. */
2345 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2347 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2348 is the set of hard registers live at the point where the insn(s)
2349 are to be inserted. */
2351 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2352 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2353 ? emit_i387_cw_initialization (MODE), 0 \
2357 /* Avoid renaming of stack registers, as doing so in combination with
2358 scheduling just increases amount of live registers at time and in
2359 the turn amount of fxch instructions needed.
2361 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2363 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2364 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2367 #define FASTCALL_PREFIX '@'
2369 /* Machine specific CFA tracking during prologue/epilogue generation. */
2371 #ifndef USED_FOR_TARGET
2372 struct GTY(()) machine_cfa_state
2375 HOST_WIDE_INT offset;
2378 struct GTY(()) machine_function {
2379 struct stack_local_entry *stack_locals;
2380 const char *some_ld_name;
2381 int varargs_gpr_size;
2382 int varargs_fpr_size;
2383 int accesses_prev_frame;
2384 int optimize_mode_switching[MAX_386_ENTITIES];
2386 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2387 expander to determine the style used. */
2388 int use_fast_prologue_epilogue;
2389 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2391 int use_fast_prologue_epilogue_nregs;
2392 /* If true, the current function needs the default PIC register, not
2393 an alternate register (on x86) and must not use the red zone (on
2394 x86_64), even if it's a leaf function. We don't want the
2395 function to be regarded as non-leaf because TLS calls need not
2396 affect register allocation. This flag is set when a TLS call
2397 instruction is expanded within a function, and never reset, even
2398 if all such instructions are optimized away. Use the
2399 ix86_current_function_calls_tls_descriptor macro for a better
2401 int tls_descriptor_call_expanded_p;
2402 /* This value is used for amd64 targets and specifies the current abi
2403 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2404 enum calling_abi call_abi;
2405 struct machine_cfa_state cfa;
2409 #define ix86_stack_locals (cfun->machine->stack_locals)
2410 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2411 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2412 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2413 #define ix86_current_function_needs_cld (cfun->machine->needs_cld)
2414 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2415 (cfun->machine->tls_descriptor_call_expanded_p)
2416 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2417 calls are optimized away, we try to detect cases in which it was
2418 optimized away. Since such instructions (use (reg REG_SP)), we can
2419 verify whether there's any such instruction live by testing that
2421 #define ix86_current_function_calls_tls_descriptor \
2422 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2423 #define ix86_cfa_state (&cfun->machine->cfa)
2425 /* Control behavior of x86_file_start. */
2426 #define X86_FILE_START_VERSION_DIRECTIVE false
2427 #define X86_FILE_START_FLTUSED false
2429 /* Flag to mark data that is in the large address area. */
2430 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2431 #define SYMBOL_REF_FAR_ADDR_P(X) \
2432 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2434 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2435 have defined always, to avoid ifdefing. */
2436 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2437 #define SYMBOL_REF_DLLIMPORT_P(X) \
2438 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2440 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2441 #define SYMBOL_REF_DLLEXPORT_P(X) \
2442 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2444 /* Model costs for vectorizer. */
2446 /* Cost of conditional branch. */
2447 #undef TARG_COND_BRANCH_COST
2448 #define TARG_COND_BRANCH_COST ix86_cost->branch_cost
2450 /* Enum through the target specific extra va_list types.
2451 Please, do not iterate the base va_list type name. */
2452 #define TARGET_ENUM_VA_LIST(IDX, PNAME, PTYPE) \
2453 (TARGET_64BIT ? ix86_enum_va_list (IDX, PNAME, PTYPE) : 0)
2455 /* Cost of any scalar operation, excluding load and store. */
2456 #undef TARG_SCALAR_STMT_COST
2457 #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost
2459 /* Cost of scalar load. */
2460 #undef TARG_SCALAR_LOAD_COST
2461 #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost
2463 /* Cost of scalar store. */
2464 #undef TARG_SCALAR_STORE_COST
2465 #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost
2467 /* Cost of any vector operation, excluding load, store or vector to scalar
2469 #undef TARG_VEC_STMT_COST
2470 #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost
2472 /* Cost of vector to scalar operation. */
2473 #undef TARG_VEC_TO_SCALAR_COST
2474 #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost
2476 /* Cost of scalar to vector operation. */
2477 #undef TARG_SCALAR_TO_VEC_COST
2478 #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost
2480 /* Cost of aligned vector load. */
2481 #undef TARG_VEC_LOAD_COST
2482 #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost
2484 /* Cost of misaligned vector load. */
2485 #undef TARG_VEC_UNALIGNED_LOAD_COST
2486 #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost
2488 /* Cost of vector store. */
2489 #undef TARG_VEC_STORE_COST
2490 #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost
2492 /* Cost of conditional taken branch for vectorizer cost model. */
2493 #undef TARG_COND_TAKEN_BRANCH_COST
2494 #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost
2496 /* Cost of conditional not taken branch for vectorizer cost model. */
2497 #undef TARG_COND_NOT_TAKEN_BRANCH_COST
2498 #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost