1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Redefines for option macros. */
39 #define TARGET_64BIT OPTION_ISA_64BIT
40 #define TARGET_MMX OPTION_ISA_MMX
41 #define TARGET_3DNOW OPTION_ISA_3DNOW
42 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
43 #define TARGET_SSE OPTION_ISA_SSE
44 #define TARGET_SSE2 OPTION_ISA_SSE2
45 #define TARGET_SSE3 OPTION_ISA_SSE3
46 #define TARGET_SSSE3 OPTION_ISA_SSSE3
47 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1
48 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2
49 #define TARGET_SSE4A OPTION_ISA_SSE4A
51 #include "config/vxworks-dummy.h"
53 /* Algorithm to expand string function with. */
66 #define NAX_STRINGOP_ALGS 4
68 /* Specify what algorithm to use for stringops on known size.
69 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
70 known at compile time or estimated via feedback, the SIZE array
71 is walked in order until MAX is greater then the estimate (or -1
72 means infinity). Corresponding ALG is used then.
73 For example initializer:
74 {{256, loop}, {-1, rep_prefix_4_byte}}
75 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
79 const enum stringop_alg unknown_size;
80 const struct stringop_strategy {
82 const enum stringop_alg alg;
83 } size [NAX_STRINGOP_ALGS];
86 /* Define the specific costs for a given cpu */
88 struct processor_costs {
89 const int add; /* cost of an add instruction */
90 const int lea; /* cost of a lea instruction */
91 const int shift_var; /* variable shift costs */
92 const int shift_const; /* constant shift costs */
93 const int mult_init[5]; /* cost of starting a multiply
94 in QImode, HImode, SImode, DImode, TImode*/
95 const int mult_bit; /* cost of multiply per each bit set */
96 const int divide[5]; /* cost of a divide/mod
97 in QImode, HImode, SImode, DImode, TImode*/
98 int movsx; /* The cost of movsx operation. */
99 int movzx; /* The cost of movzx operation. */
100 const int large_insn; /* insns larger than this cost more */
101 const int move_ratio; /* The threshold of number of scalar
102 memory-to-memory move insns. */
103 const int movzbl_load; /* cost of loading using movzbl */
104 const int int_load[3]; /* cost of loading integer registers
105 in QImode, HImode and SImode relative
106 to reg-reg move (2). */
107 const int int_store[3]; /* cost of storing integer register
108 in QImode, HImode and SImode */
109 const int fp_move; /* cost of reg,reg fld/fst */
110 const int fp_load[3]; /* cost of loading FP register
111 in SFmode, DFmode and XFmode */
112 const int fp_store[3]; /* cost of storing FP register
113 in SFmode, DFmode and XFmode */
114 const int mmx_move; /* cost of moving MMX register. */
115 const int mmx_load[2]; /* cost of loading MMX register
116 in SImode and DImode */
117 const int mmx_store[2]; /* cost of storing MMX register
118 in SImode and DImode */
119 const int sse_move; /* cost of moving SSE register. */
120 const int sse_load[3]; /* cost of loading SSE register
121 in SImode, DImode and TImode*/
122 const int sse_store[3]; /* cost of storing SSE register
123 in SImode, DImode and TImode*/
124 const int mmxsse_to_integer; /* cost of moving mmxsse register to
125 integer and vice versa. */
126 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
127 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
128 const int prefetch_block; /* bytes moved to cache for prefetch. */
129 const int simultaneous_prefetches; /* number of parallel prefetch
131 const int branch_cost; /* Default value for BRANCH_COST. */
132 const int fadd; /* cost of FADD and FSUB instructions. */
133 const int fmul; /* cost of FMUL instruction. */
134 const int fdiv; /* cost of FDIV instruction. */
135 const int fabs; /* cost of FABS instruction. */
136 const int fchs; /* cost of FCHS instruction. */
137 const int fsqrt; /* cost of FSQRT instruction. */
138 /* Specify what algorithm
139 to use for stringops on unknown size. */
140 struct stringop_algs memcpy[2], memset[2];
143 extern const struct processor_costs *ix86_cost;
145 /* Macros used in the machine description to test the flags. */
147 /* configure can arrange to make this 2, to force a 486. */
149 #ifndef TARGET_CPU_DEFAULT
150 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
153 #ifndef TARGET_FPMATH_DEFAULT
154 #define TARGET_FPMATH_DEFAULT \
155 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
158 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
160 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
161 compile-time constant. */
165 #define TARGET_64BIT 1
167 #define TARGET_64BIT 0
170 #ifndef TARGET_BI_ARCH
172 #if TARGET_64BIT_DEFAULT
173 #define TARGET_64BIT 1
175 #define TARGET_64BIT 0
180 #define HAS_LONG_COND_BRANCH 1
181 #define HAS_LONG_UNCOND_BRANCH 1
183 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
184 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
185 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
186 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
187 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
188 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
189 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
190 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
191 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
192 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
193 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
194 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
195 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
196 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
197 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
198 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
200 /* Feature tests against the various tunings. */
201 enum ix86_tune_indices {
203 X86_TUNE_PUSH_MEMORY,
204 X86_TUNE_ZERO_EXTEND_WITH_AND,
205 X86_TUNE_USE_BIT_TEST,
206 X86_TUNE_UNROLL_STRLEN,
207 X86_TUNE_DEEP_BRANCH_PREDICTION,
208 X86_TUNE_BRANCH_PREDICTION_HINTS,
209 X86_TUNE_DOUBLE_WITH_ADD,
212 X86_TUNE_PARTIAL_REG_STALL,
213 X86_TUNE_PARTIAL_FLAG_REG_STALL,
214 X86_TUNE_USE_HIMODE_FIOP,
215 X86_TUNE_USE_SIMODE_FIOP,
219 X86_TUNE_SPLIT_LONG_MOVES,
220 X86_TUNE_READ_MODIFY_WRITE,
221 X86_TUNE_READ_MODIFY,
222 X86_TUNE_PROMOTE_QIMODE,
223 X86_TUNE_FAST_PREFIX,
224 X86_TUNE_SINGLE_STRINGOP,
225 X86_TUNE_QIMODE_MATH,
226 X86_TUNE_HIMODE_MATH,
227 X86_TUNE_PROMOTE_QI_REGS,
228 X86_TUNE_PROMOTE_HI_REGS,
233 X86_TUNE_INTEGER_DFMODE_MOVES,
234 X86_TUNE_PARTIAL_REG_DEPENDENCY,
235 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
236 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
237 X86_TUNE_SSE_SPLIT_REGS,
238 X86_TUNE_SSE_TYPELESS_STORES,
239 X86_TUNE_SSE_LOAD0_BY_PXOR,
240 X86_TUNE_MEMORY_MISMATCH_STALL,
241 X86_TUNE_PROLOGUE_USING_MOVE,
242 X86_TUNE_EPILOGUE_USING_MOVE,
245 X86_TUNE_INTER_UNIT_MOVES,
246 X86_TUNE_FOUR_JUMP_LIMIT,
250 X86_TUNE_PAD_RETURNS,
251 X86_TUNE_EXT_80387_CONSTANTS,
252 X86_TUNE_SHORTEN_X87_SSE,
253 X86_TUNE_AVOID_VECTOR_DECODE,
254 X86_TUNE_PROMOTE_HIMODE_IMUL,
255 X86_TUNE_SLOW_IMUL_IMM32_MEM,
256 X86_TUNE_SLOW_IMUL_IMM8,
257 X86_TUNE_MOVE_M1_VIA_OR,
258 X86_TUNE_NOT_UNPAIRABLE,
259 X86_TUNE_NOT_VECTORMODE,
264 extern unsigned int ix86_tune_features[X86_TUNE_LAST];
266 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
267 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
268 #define TARGET_ZERO_EXTEND_WITH_AND \
269 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
270 #define TARGET_USE_BIT_TEST ix86_tune_features[X86_TUNE_USE_BIT_TEST]
271 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
272 #define TARGET_DEEP_BRANCH_PREDICTION \
273 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
274 #define TARGET_BRANCH_PREDICTION_HINTS \
275 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
276 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
277 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
278 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
279 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
280 #define TARGET_PARTIAL_FLAG_REG_STALL \
281 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
282 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
283 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
284 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
285 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
286 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
287 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
288 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
289 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
290 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
291 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
292 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
293 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
294 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
295 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
296 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
297 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4]
298 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8]
299 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4]
300 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8]
301 #define TARGET_INTEGER_DFMODE_MOVES \
302 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
303 #define TARGET_PARTIAL_REG_DEPENDENCY \
304 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
305 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
306 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
307 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
308 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
309 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
310 #define TARGET_SSE_TYPELESS_STORES \
311 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
312 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
313 #define TARGET_MEMORY_MISMATCH_STALL \
314 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
315 #define TARGET_PROLOGUE_USING_MOVE \
316 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
317 #define TARGET_EPILOGUE_USING_MOVE \
318 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
319 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
320 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
321 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
322 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
323 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
324 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
325 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
326 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
327 #define TARGET_EXT_80387_CONSTANTS \
328 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
329 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
330 #define TARGET_AVOID_VECTOR_DECODE \
331 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
332 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
333 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
334 #define TARGET_SLOW_IMUL_IMM32_MEM \
335 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
336 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
337 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
338 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
339 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
341 /* Feature tests against the various architecture variations. */
342 enum ix86_arch_indices {
343 X86_ARCH_CMOVE, /* || TARGET_SSE */
352 extern unsigned int ix86_arch_features[X86_ARCH_LAST];
354 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
355 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
356 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
357 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
358 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
360 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
362 extern int x86_prefetch_sse;
364 #define TARGET_ABM x86_abm
365 #define TARGET_CMPXCHG16B x86_cmpxchg16b
366 #define TARGET_POPCNT x86_popcnt
367 #define TARGET_PREFETCH_SSE x86_prefetch_sse
368 #define TARGET_SAHF x86_sahf
369 #define TARGET_RECIP x86_recip
371 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
373 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
374 #define TARGET_MIX_SSE_I387 \
375 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
377 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
378 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
379 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
380 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
382 extern int ix86_isa_flags;
384 #ifndef TARGET_64BIT_DEFAULT
385 #define TARGET_64BIT_DEFAULT 0
387 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
388 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
391 /* Fence to use after loop using storent. */
393 extern tree x86_mfence;
394 #define FENCE_FOLLOWING_MOVNT x86_mfence
396 /* Once GDB has been enhanced to deal with functions without frame
397 pointers, we can change this to allow for elimination of
398 the frame pointer in leaf functions. */
399 #define TARGET_DEFAULT 0
401 /* Extra bits to force. */
402 #define TARGET_SUBTARGET_DEFAULT 0
403 #define TARGET_SUBTARGET_ISA_DEFAULT 0
405 /* Extra bits to force on w/ 32-bit mode. */
406 #define TARGET_SUBTARGET32_DEFAULT 0
407 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
409 /* Extra bits to force on w/ 64-bit mode. */
410 #define TARGET_SUBTARGET64_DEFAULT 0
411 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
413 /* This is not really a target flag, but is done this way so that
414 it's analogous to similar code for Mach-O on PowerPC. darwin.h
415 redefines this to 1. */
416 #define TARGET_MACHO 0
418 /* Likewise, for the Windows 64-bit ABI. */
419 #define TARGET_64BIT_MS_ABI 0
421 /* Subtargets may reset this to 1 in order to enable 96-bit long double
422 with the rounding mode forced to 53 bits. */
423 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
425 /* Sometimes certain combinations of command options do not make
426 sense on a particular target machine. You can define a macro
427 `OVERRIDE_OPTIONS' to take account of this. This macro, if
428 defined, is executed once just after all the command options have
431 Don't use this macro to turn on various extra optimizations for
432 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
434 #define OVERRIDE_OPTIONS override_options ()
436 /* Define this to change the optimizations performed by default. */
437 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
438 optimization_options ((LEVEL), (SIZE))
440 /* -march=native handling only makes sense with compiler running on
441 an x86 or x86_64 chip. If changing this condition, also change
442 the condition in driver-i386.c. */
443 #if defined(__i386__) || defined(__x86_64__)
444 /* In driver-i386.c. */
445 extern const char *host_detect_local_cpu (int argc, const char **argv);
446 #define EXTRA_SPEC_FUNCTIONS \
447 { "local_cpu_detect", host_detect_local_cpu },
448 #define HAVE_LOCAL_CPU_DETECT
451 /* Support for configure-time defaults of some command line options.
452 The order here is important so that -march doesn't squash the
453 tune or cpu values. */
454 #define OPTION_DEFAULT_SPECS \
455 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
456 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
457 {"arch", "%{!march=*:-march=%(VALUE)}"}
459 /* Specs for the compiler proper */
462 #define CC1_CPU_SPEC_1 "\
464 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \
466 %{mintel-syntax:-masm=intel \
467 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
468 %{mno-intel-syntax:-masm=att \
469 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
471 #ifndef HAVE_LOCAL_CPU_DETECT
472 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
474 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
475 "%{march=native:%<march=native %:local_cpu_detect(arch) \
476 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
477 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
481 /* Target CPU builtins. */
482 #define TARGET_CPU_CPP_BUILTINS() \
485 size_t arch_len = strlen (ix86_arch_string); \
486 size_t tune_len = strlen (ix86_tune_string); \
487 int last_arch_char = ix86_arch_string[arch_len - 1]; \
488 int last_tune_char = ix86_tune_string[tune_len - 1]; \
492 builtin_assert ("cpu=x86_64"); \
493 builtin_assert ("machine=x86_64"); \
494 builtin_define ("__amd64"); \
495 builtin_define ("__amd64__"); \
496 builtin_define ("__x86_64"); \
497 builtin_define ("__x86_64__"); \
501 builtin_assert ("cpu=i386"); \
502 builtin_assert ("machine=i386"); \
503 builtin_define_std ("i386"); \
506 /* Built-ins based on -mtune= (or -march= if no \
509 builtin_define ("__tune_i386__"); \
510 else if (TARGET_486) \
511 builtin_define ("__tune_i486__"); \
512 else if (TARGET_PENTIUM) \
514 builtin_define ("__tune_i586__"); \
515 builtin_define ("__tune_pentium__"); \
516 if (last_tune_char == 'x') \
517 builtin_define ("__tune_pentium_mmx__"); \
519 else if (TARGET_PENTIUMPRO) \
521 builtin_define ("__tune_i686__"); \
522 builtin_define ("__tune_pentiumpro__"); \
523 switch (last_tune_char) \
526 builtin_define ("__tune_pentium3__"); \
529 builtin_define ("__tune_pentium2__"); \
533 else if (TARGET_GEODE) \
535 builtin_define ("__tune_geode__"); \
537 else if (TARGET_K6) \
539 builtin_define ("__tune_k6__"); \
540 if (last_tune_char == '2') \
541 builtin_define ("__tune_k6_2__"); \
542 else if (last_tune_char == '3') \
543 builtin_define ("__tune_k6_3__"); \
545 else if (TARGET_ATHLON) \
547 builtin_define ("__tune_athlon__"); \
548 /* Only plain "athlon" lacks SSE. */ \
549 if (last_tune_char != 'n') \
550 builtin_define ("__tune_athlon_sse__"); \
552 else if (TARGET_K8) \
553 builtin_define ("__tune_k8__"); \
554 else if (TARGET_AMDFAM10) \
555 builtin_define ("__tune_amdfam10__"); \
556 else if (TARGET_PENTIUM4) \
557 builtin_define ("__tune_pentium4__"); \
558 else if (TARGET_NOCONA) \
559 builtin_define ("__tune_nocona__"); \
560 else if (TARGET_CORE2) \
561 builtin_define ("__tune_core2__"); \
564 builtin_define ("__MMX__"); \
566 builtin_define ("__3dNOW__"); \
567 if (TARGET_3DNOW_A) \
568 builtin_define ("__3dNOW_A__"); \
570 builtin_define ("__SSE__"); \
572 builtin_define ("__SSE2__"); \
574 builtin_define ("__SSE3__"); \
576 builtin_define ("__SSSE3__"); \
578 builtin_define ("__SSE4_1__"); \
580 builtin_define ("__SSE4_2__"); \
582 builtin_define ("__SSE4A__"); \
583 if (TARGET_SSE_MATH && TARGET_SSE) \
584 builtin_define ("__SSE_MATH__"); \
585 if (TARGET_SSE_MATH && TARGET_SSE2) \
586 builtin_define ("__SSE2_MATH__"); \
588 /* Built-ins based on -march=. */ \
589 if (ix86_arch == PROCESSOR_I486) \
591 builtin_define ("__i486"); \
592 builtin_define ("__i486__"); \
594 else if (ix86_arch == PROCESSOR_PENTIUM) \
596 builtin_define ("__i586"); \
597 builtin_define ("__i586__"); \
598 builtin_define ("__pentium"); \
599 builtin_define ("__pentium__"); \
600 if (last_arch_char == 'x') \
601 builtin_define ("__pentium_mmx__"); \
603 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
605 builtin_define ("__i686"); \
606 builtin_define ("__i686__"); \
607 builtin_define ("__pentiumpro"); \
608 builtin_define ("__pentiumpro__"); \
610 else if (ix86_arch == PROCESSOR_GEODE) \
612 builtin_define ("__geode"); \
613 builtin_define ("__geode__"); \
615 else if (ix86_arch == PROCESSOR_K6) \
618 builtin_define ("__k6"); \
619 builtin_define ("__k6__"); \
620 if (last_arch_char == '2') \
621 builtin_define ("__k6_2__"); \
622 else if (last_arch_char == '3') \
623 builtin_define ("__k6_3__"); \
625 else if (ix86_arch == PROCESSOR_ATHLON) \
627 builtin_define ("__athlon"); \
628 builtin_define ("__athlon__"); \
629 /* Only plain "athlon" lacks SSE. */ \
630 if (last_arch_char != 'n') \
631 builtin_define ("__athlon_sse__"); \
633 else if (ix86_arch == PROCESSOR_K8) \
635 builtin_define ("__k8"); \
636 builtin_define ("__k8__"); \
638 else if (ix86_arch == PROCESSOR_AMDFAM10) \
640 builtin_define ("__amdfam10"); \
641 builtin_define ("__amdfam10__"); \
643 else if (ix86_arch == PROCESSOR_PENTIUM4) \
645 builtin_define ("__pentium4"); \
646 builtin_define ("__pentium4__"); \
648 else if (ix86_arch == PROCESSOR_NOCONA) \
650 builtin_define ("__nocona"); \
651 builtin_define ("__nocona__"); \
653 else if (ix86_arch == PROCESSOR_CORE2) \
655 builtin_define ("__core2"); \
656 builtin_define ("__core2__"); \
661 #define TARGET_CPU_DEFAULT_i386 0
662 #define TARGET_CPU_DEFAULT_i486 1
663 #define TARGET_CPU_DEFAULT_pentium 2
664 #define TARGET_CPU_DEFAULT_pentium_mmx 3
665 #define TARGET_CPU_DEFAULT_pentiumpro 4
666 #define TARGET_CPU_DEFAULT_pentium2 5
667 #define TARGET_CPU_DEFAULT_pentium3 6
668 #define TARGET_CPU_DEFAULT_pentium4 7
669 #define TARGET_CPU_DEFAULT_geode 8
670 #define TARGET_CPU_DEFAULT_k6 9
671 #define TARGET_CPU_DEFAULT_k6_2 10
672 #define TARGET_CPU_DEFAULT_k6_3 11
673 #define TARGET_CPU_DEFAULT_athlon 12
674 #define TARGET_CPU_DEFAULT_athlon_sse 13
675 #define TARGET_CPU_DEFAULT_k8 14
676 #define TARGET_CPU_DEFAULT_pentium_m 15
677 #define TARGET_CPU_DEFAULT_prescott 16
678 #define TARGET_CPU_DEFAULT_nocona 17
679 #define TARGET_CPU_DEFAULT_core2 18
680 #define TARGET_CPU_DEFAULT_generic 19
681 #define TARGET_CPU_DEFAULT_amdfam10 20
683 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
684 "pentiumpro", "pentium2", "pentium3", \
685 "pentium4", "geode", "k6", "k6-2", "k6-3", \
686 "athlon", "athlon-4", "k8", \
687 "pentium-m", "prescott", "nocona", \
688 "core2", "generic", "amdfam10"}
691 #define CC1_SPEC "%(cc1_cpu) "
694 /* This macro defines names of additional specifications to put in the
695 specs that can be used in various specifications like CC1_SPEC. Its
696 definition is an initializer with a subgrouping for each command option.
698 Each subgrouping contains a string constant, that defines the
699 specification name, and a string constant that used by the GCC driver
702 Do not define this macro if it does not need to do anything. */
704 #ifndef SUBTARGET_EXTRA_SPECS
705 #define SUBTARGET_EXTRA_SPECS
708 #define EXTRA_SPECS \
709 { "cc1_cpu", CC1_CPU_SPEC }, \
710 SUBTARGET_EXTRA_SPECS
712 /* target machine storage layout */
714 #define LONG_DOUBLE_TYPE_SIZE 80
716 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
717 FPU, assume that the fpcw is set to extended precision; when using
718 only SSE, rounding is correct; when using both SSE and the FPU,
719 the rounding precision is indeterminate, since either may be chosen
720 apparently at random. */
721 #define TARGET_FLT_EVAL_METHOD \
722 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
724 #define SHORT_TYPE_SIZE 16
725 #define INT_TYPE_SIZE 32
726 #define FLOAT_TYPE_SIZE 32
727 #define LONG_TYPE_SIZE BITS_PER_WORD
728 #define DOUBLE_TYPE_SIZE 64
729 #define LONG_LONG_TYPE_SIZE 64
731 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
732 #define MAX_BITS_PER_WORD 64
734 #define MAX_BITS_PER_WORD 32
737 /* Define this if most significant byte of a word is the lowest numbered. */
738 /* That is true on the 80386. */
740 #define BITS_BIG_ENDIAN 0
742 /* Define this if most significant byte of a word is the lowest numbered. */
743 /* That is not true on the 80386. */
744 #define BYTES_BIG_ENDIAN 0
746 /* Define this if most significant word of a multiword number is the lowest
748 /* Not true for 80386 */
749 #define WORDS_BIG_ENDIAN 0
751 /* Width of a word, in units (bytes). */
752 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
754 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
756 #define MIN_UNITS_PER_WORD 4
759 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
760 #define PARM_BOUNDARY BITS_PER_WORD
762 /* Boundary (in *bits*) on which stack pointer should be aligned. */
763 #define STACK_BOUNDARY BITS_PER_WORD
765 /* Boundary (in *bits*) on which the stack pointer prefers to be
766 aligned; the compiler cannot rely on having this alignment. */
767 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
769 /* As of July 2001, many runtimes do not align the stack properly when
770 entering main. This causes expand_main_function to forcibly align
771 the stack, which results in aligned frames for functions called from
772 main, though it does nothing for the alignment of main itself. */
773 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
774 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
776 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
777 mandatory for the 64-bit ABI, and may or may not be true for other
778 operating systems. */
779 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
781 /* Minimum allocation boundary for the code of a function. */
782 #define FUNCTION_BOUNDARY 8
784 /* C++ stores the virtual bit in the lowest bit of function pointers. */
785 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
787 /* Alignment of field after `int : 0' in a structure. */
789 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
791 /* Minimum size in bits of the largest boundary to which any
792 and all fundamental data types supported by the hardware
793 might need to be aligned. No data type wants to be aligned
796 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
797 and Pentium Pro XFmode values at 128 bit boundaries. */
799 #define BIGGEST_ALIGNMENT 128
801 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
802 #define ALIGN_MODE_128(MODE) \
803 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
805 /* The published ABIs say that doubles should be aligned on word
806 boundaries, so lower the alignment for structure fields unless
807 -malign-double is set. */
809 /* ??? Blah -- this macro is used directly by libobjc. Since it
810 supports no vector modes, cut out the complexity and fall back
811 on BIGGEST_FIELD_ALIGNMENT. */
812 #ifdef IN_TARGET_LIBS
814 #define BIGGEST_FIELD_ALIGNMENT 128
816 #define BIGGEST_FIELD_ALIGNMENT 32
819 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
820 x86_field_alignment (FIELD, COMPUTED)
823 /* If defined, a C expression to compute the alignment given to a
824 constant that is being placed in memory. EXP is the constant
825 and ALIGN is the alignment that the object would ordinarily have.
826 The value of this macro is used instead of that alignment to align
829 If this macro is not defined, then ALIGN is used.
831 The typical use of this macro is to increase alignment for string
832 constants to be word aligned so that `strcpy' calls that copy
833 constants can be done inline. */
835 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
837 /* If defined, a C expression to compute the alignment for a static
838 variable. TYPE is the data type, and ALIGN is the alignment that
839 the object would ordinarily have. The value of this macro is used
840 instead of that alignment to align the object.
842 If this macro is not defined, then ALIGN is used.
844 One use of this macro is to increase alignment of medium-size
845 data to make it all fit in fewer cache lines. Another is to
846 cause character arrays to be word-aligned so that `strcpy' calls
847 that copy constants to character arrays can be done inline. */
849 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
851 /* If defined, a C expression to compute the alignment for a local
852 variable. TYPE is the data type, and ALIGN is the alignment that
853 the object would ordinarily have. The value of this macro is used
854 instead of that alignment to align the object.
856 If this macro is not defined, then ALIGN is used.
858 One use of this macro is to increase alignment of medium-size
859 data to make it all fit in fewer cache lines. */
861 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
863 /* If defined, a C expression that gives the alignment boundary, in
864 bits, of an argument with the specified mode and type. If it is
865 not defined, `PARM_BOUNDARY' is used for all arguments. */
867 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
868 ix86_function_arg_boundary ((MODE), (TYPE))
870 /* Set this nonzero if move instructions will actually fail to work
871 when given unaligned data. */
872 #define STRICT_ALIGNMENT 0
874 /* If bit field type is int, don't let it cross an int,
875 and give entire struct the alignment of an int. */
876 /* Required on the 386 since it doesn't have bit-field insns. */
877 #define PCC_BITFIELD_TYPE_MATTERS 1
879 /* Standard register usage. */
881 /* This processor has special stack-like registers. See reg-stack.c
885 #define IS_STACK_MODE(MODE) \
886 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
887 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
890 /* Number of actual hardware registers.
891 The hardware registers are assigned numbers for the compiler
892 from 0 to just below FIRST_PSEUDO_REGISTER.
893 All registers that the compiler knows about must be given numbers,
894 even those that are not normally considered general registers.
896 In the 80386 we give the 8 general purpose registers the numbers 0-7.
897 We number the floating point registers 8-15.
898 Note that registers 0-7 can be accessed as a short or int,
899 while only 0-3 may be used with byte `mov' instructions.
901 Reg 16 does not correspond to any hardware register, but instead
902 appears in the RTL as an argument pointer prior to reload, and is
903 eliminated during reloading in favor of either the stack or frame
906 #define FIRST_PSEUDO_REGISTER 53
908 /* Number of hardware registers that go into the DWARF-2 unwind info.
909 If not defined, equals FIRST_PSEUDO_REGISTER. */
911 #define DWARF_FRAME_REGISTERS 17
913 /* 1 for registers that have pervasive standard uses
914 and are not available for the register allocator.
915 On the 80386, the stack pointer is such, as is the arg pointer.
917 The value is zero if the register is not fixed on either 32 or
918 64 bit targets, one if the register if fixed on both 32 and 64
919 bit targets, two if it is only fixed on 32bit targets and three
920 if its only fixed on 64bit targets.
921 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
923 #define FIXED_REGISTERS \
924 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
925 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
926 /*arg,flags,fpsr,fpcr,frame*/ \
928 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
929 0, 0, 0, 0, 0, 0, 0, 0, \
930 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
931 0, 0, 0, 0, 0, 0, 0, 0, \
932 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
933 2, 2, 2, 2, 2, 2, 2, 2, \
934 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
935 2, 2, 2, 2, 2, 2, 2, 2}
938 /* 1 for registers not available across function calls.
939 These must include the FIXED_REGISTERS and also any
940 registers that can be used without being saved.
941 The latter must include the registers where values are returned
942 and the register where structure-value addresses are passed.
943 Aside from that, you can include as many other registers as you like.
945 The value is zero if the register is not call used on either 32 or
946 64 bit targets, one if the register if call used on both 32 and 64
947 bit targets, two if it is only call used on 32bit targets and three
948 if its only call used on 64bit targets.
949 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
951 #define CALL_USED_REGISTERS \
952 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
953 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
954 /*arg,flags,fpsr,fpcr,frame*/ \
956 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
957 1, 1, 1, 1, 1, 1, 1, 1, \
958 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
959 1, 1, 1, 1, 1, 1, 1, 1, \
960 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
961 1, 1, 1, 1, 2, 2, 2, 2, \
962 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
963 1, 1, 1, 1, 1, 1, 1, 1} \
965 /* Order in which to allocate registers. Each register must be
966 listed once, even those in FIXED_REGISTERS. List frame pointer
967 late and fixed registers last. Note that, in general, we prefer
968 registers listed in CALL_USED_REGISTERS, keeping the others
969 available for storage of persistent values.
971 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
972 so this is just empty initializer for array. */
974 #define REG_ALLOC_ORDER \
975 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
976 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
977 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
980 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
981 to be rearranged based on a particular function. When using sse math,
982 we want to allocate SSE before x87 registers and vice versa. */
984 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
987 /* Macro to conditionally modify fixed_regs/call_used_regs. */
988 #define CONDITIONAL_REGISTER_USAGE \
992 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
994 if (fixed_regs[i] > 1) \
995 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
996 if (call_used_regs[i] > 1) \
997 call_used_regs[i] = (call_used_regs[i] \
998 == (TARGET_64BIT ? 3 : 2)); \
1000 j = PIC_OFFSET_TABLE_REGNUM; \
1001 if (j != INVALID_REGNUM) \
1003 fixed_regs[j] = 1; \
1004 call_used_regs[j] = 1; \
1009 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1010 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
1011 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1016 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1017 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
1018 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1020 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
1024 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
1025 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1026 if (TEST_HARD_REG_BIT (x, i)) \
1027 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1029 if (! TARGET_64BIT) \
1032 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
1033 reg_names[i] = ""; \
1034 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
1035 reg_names[i] = ""; \
1037 if (TARGET_64BIT_MS_ABI) \
1039 call_used_regs[4 /*RSI*/] = 0; \
1040 call_used_regs[5 /*RDI*/] = 0; \
1044 /* Return number of consecutive hard regs needed starting at reg REGNO
1045 to hold something of mode MODE.
1046 This is ordinarily the length in words of a value of mode MODE
1047 but can be less for certain modes in special long registers.
1049 Actually there are no two word move instructions for consecutive
1050 registers. And only registers 0-3 may have mov byte instructions
1054 #define HARD_REGNO_NREGS(REGNO, MODE) \
1055 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1056 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1057 : ((MODE) == XFmode \
1058 ? (TARGET_64BIT ? 2 : 3) \
1059 : (MODE) == XCmode \
1060 ? (TARGET_64BIT ? 4 : 6) \
1061 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1063 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1064 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
1065 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1067 : ((MODE) == XFmode || (MODE) == XCmode)) \
1070 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1072 #define VALID_SSE2_REG_MODE(MODE) \
1073 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1074 || (MODE) == V2DImode || (MODE) == DFmode)
1076 #define VALID_SSE_REG_MODE(MODE) \
1077 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1078 || (MODE) == SFmode || (MODE) == TFmode)
1080 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1081 ((MODE) == V2SFmode || (MODE) == SFmode)
1083 #define VALID_MMX_REG_MODE(MODE) \
1084 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1085 || (MODE) == V2SImode || (MODE) == SImode)
1087 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
1088 place emms and femms instructions. */
1089 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
1091 #define VALID_FP_MODE_P(MODE) \
1092 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1093 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1095 #define VALID_INT_MODE_P(MODE) \
1096 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1097 || (MODE) == DImode \
1098 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1099 || (MODE) == CDImode \
1100 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1101 || (MODE) == TFmode || (MODE) == TCmode)))
1103 /* Return true for modes passed in SSE registers. */
1104 #define SSE_REG_MODE_P(MODE) \
1105 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1106 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1107 || (MODE) == V4SFmode || (MODE) == V4SImode)
1109 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1111 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1112 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1114 /* Value is 1 if it is a good idea to tie two pseudo registers
1115 when one has mode MODE1 and one has mode MODE2.
1116 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1117 for any hard reg, then this must be 0 for correct output. */
1119 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1121 /* It is possible to write patterns to move flags; but until someone
1123 #define AVOID_CCMODE_COPIES
1125 /* Specify the modes required to caller save a given hard regno.
1126 We do this on i386 to prevent flags from being saved at all.
1128 Kill any attempts to combine saving of modes. */
1130 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1131 (CC_REGNO_P (REGNO) ? VOIDmode \
1132 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1133 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
1134 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1135 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1137 /* Specify the registers used for certain standard purposes.
1138 The values of these macros are register numbers. */
1140 /* on the 386 the pc register is %eip, and is not usable as a general
1141 register. The ordinary mov instructions won't work */
1142 /* #define PC_REGNUM */
1144 /* Register to use for pushing function arguments. */
1145 #define STACK_POINTER_REGNUM 7
1147 /* Base register for access to local variables of the function. */
1148 #define HARD_FRAME_POINTER_REGNUM 6
1150 /* Base register for access to local variables of the function. */
1151 #define FRAME_POINTER_REGNUM 20
1153 /* First floating point reg */
1154 #define FIRST_FLOAT_REG 8
1156 /* First & last stack-like regs */
1157 #define FIRST_STACK_REG FIRST_FLOAT_REG
1158 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1160 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1161 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1163 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1164 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1166 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1167 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1169 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1170 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1172 /* Value should be nonzero if functions must have frame pointers.
1173 Zero means the frame pointer need not be set up (and parms
1174 may be accessed via the stack pointer) in functions that seem suitable.
1175 This is computed in `reload', in reload1.c. */
1176 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1178 /* Override this in other tm.h files to cope with various OS lossage
1179 requiring a frame pointer. */
1180 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1181 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1184 /* Make sure we can access arbitrary call frames. */
1185 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1187 /* Base register for access to arguments of the function. */
1188 #define ARG_POINTER_REGNUM 16
1190 /* Register in which static-chain is passed to a function.
1191 We do use ECX as static chain register for 32 bit ABI. On the
1192 64bit ABI, ECX is an argument register, so we use R10 instead. */
1193 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1195 /* Register to hold the addressing base for position independent
1196 code access to data items. We don't use PIC pointer for 64bit
1197 mode. Define the regnum to dummy value to prevent gcc from
1198 pessimizing code dealing with EBX.
1200 To avoid clobbering a call-saved register unnecessarily, we renumber
1201 the pic register when possible. The change is visible after the
1202 prologue has been emitted. */
1204 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1206 #define PIC_OFFSET_TABLE_REGNUM \
1207 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1208 || !flag_pic ? INVALID_REGNUM \
1209 : reload_completed ? REGNO (pic_offset_table_rtx) \
1210 : REAL_PIC_OFFSET_TABLE_REGNUM)
1212 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1214 /* A C expression which can inhibit the returning of certain function
1215 values in registers, based on the type of value. A nonzero value
1216 says to return the function value in memory, just as large
1217 structures are always returned. Here TYPE will be a C expression
1218 of type `tree', representing the data type of the value.
1220 Note that values of mode `BLKmode' must be explicitly handled by
1221 this macro. Also, the option `-fpcc-struct-return' takes effect
1222 regardless of this macro. On most systems, it is possible to
1223 leave the macro undefined; this causes a default definition to be
1224 used, whose value is the constant 1 for `BLKmode' values, and 0
1227 Do not use this macro to indicate that structures and unions
1228 should always be returned in memory. You should instead use
1229 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1231 #define RETURN_IN_MEMORY(TYPE) \
1232 ix86_return_in_memory (TYPE)
1234 /* This is overridden by <cygwin.h>. */
1235 #define MS_AGGREGATE_RETURN 0
1237 /* This is overridden by <netware.h>. */
1238 #define KEEP_AGGREGATE_RETURN_POINTER 0
1240 /* Define the classes of registers for register constraints in the
1241 machine description. Also define ranges of constants.
1243 One of the classes must always be named ALL_REGS and include all hard regs.
1244 If there is more than one class, another class must be named NO_REGS
1245 and contain no registers.
1247 The name GENERAL_REGS must be the name of a class (or an alias for
1248 another name such as ALL_REGS). This is the class of registers
1249 that is allowed by "g" or "r" in a register constraint.
1250 Also, registers outside this class are allocated only when
1251 instructions express preferences for them.
1253 The classes must be numbered in nondecreasing order; that is,
1254 a larger-numbered class must never be contained completely
1255 in a smaller-numbered class.
1257 For any two classes, it is very desirable that there be another
1258 class that represents their union.
1260 It might seem that class BREG is unnecessary, since no useful 386
1261 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1262 and the "b" register constraint is useful in asms for syscalls.
1264 The flags, fpsr and fpcr registers are in no class. */
1269 AREG, DREG, CREG, BREG, SIREG, DIREG,
1270 AD_REGS, /* %eax/%edx for DImode */
1271 Q_REGS, /* %eax %ebx %ecx %edx */
1272 NON_Q_REGS, /* %esi %edi %ebp %esp */
1273 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1274 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1275 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1276 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1287 ALL_REGS, LIM_REG_CLASSES
1290 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1292 #define INTEGER_CLASS_P(CLASS) \
1293 reg_class_subset_p ((CLASS), GENERAL_REGS)
1294 #define FLOAT_CLASS_P(CLASS) \
1295 reg_class_subset_p ((CLASS), FLOAT_REGS)
1296 #define SSE_CLASS_P(CLASS) \
1297 reg_class_subset_p ((CLASS), SSE_REGS)
1298 #define MMX_CLASS_P(CLASS) \
1299 ((CLASS) == MMX_REGS)
1300 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1301 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1302 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1303 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1304 #define MAYBE_SSE_CLASS_P(CLASS) \
1305 reg_classes_intersect_p (SSE_REGS, (CLASS))
1306 #define MAYBE_MMX_CLASS_P(CLASS) \
1307 reg_classes_intersect_p (MMX_REGS, (CLASS))
1309 #define Q_CLASS_P(CLASS) \
1310 reg_class_subset_p ((CLASS), Q_REGS)
1312 /* Give names of register classes as strings for dump file. */
1314 #define REG_CLASS_NAMES \
1316 "AREG", "DREG", "CREG", "BREG", \
1319 "Q_REGS", "NON_Q_REGS", \
1323 "FP_TOP_REG", "FP_SECOND_REG", \
1328 "FP_TOP_SSE_REGS", \
1329 "FP_SECOND_SSE_REGS", \
1333 "FLOAT_INT_SSE_REGS", \
1336 /* Define which registers fit in which classes.
1337 This is an initializer for a vector of HARD_REG_SET
1338 of length N_REG_CLASSES. */
1340 #define REG_CLASS_CONTENTS \
1342 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1343 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1344 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1345 { 0x03, 0x0 }, /* AD_REGS */ \
1346 { 0x0f, 0x0 }, /* Q_REGS */ \
1347 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1348 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1349 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1350 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1351 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1352 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1353 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1354 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1355 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1356 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1357 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1358 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1359 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1360 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1361 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1362 { 0xffffffff,0x1fffff } \
1365 /* The same information, inverted:
1366 Return the class number of the smallest class containing
1367 reg number REGNO. This could be a conditional expression
1368 or could index an array. */
1370 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1372 /* When defined, the compiler allows registers explicitly used in the
1373 rtl to be used as spill registers but prevents the compiler from
1374 extending the lifetime of these registers. */
1376 #define SMALL_REGISTER_CLASSES 1
1378 #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
1380 #define GENERAL_REGNO_P(N) \
1381 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1383 #define GENERAL_REG_P(X) \
1384 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1386 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1388 #define REX_INT_REGNO_P(N) \
1389 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1390 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1392 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1393 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1394 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1395 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1397 #define X87_FLOAT_MODE_P(MODE) \
1398 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1400 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1401 #define SSE_REGNO_P(N) \
1402 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1403 || REX_SSE_REGNO_P (N))
1405 #define REX_SSE_REGNO_P(N) \
1406 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1408 #define SSE_REGNO(N) \
1409 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1411 #define SSE_FLOAT_MODE_P(MODE) \
1412 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1414 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1415 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1417 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1418 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1420 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1422 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1423 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1425 /* The class value for index registers, and the one for base regs. */
1427 #define INDEX_REG_CLASS INDEX_REGS
1428 #define BASE_REG_CLASS GENERAL_REGS
1430 /* Place additional restrictions on the register class to use when it
1431 is necessary to be able to hold a value of mode MODE in a reload
1432 register for which class CLASS would ordinarily be used. */
1434 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1435 ((MODE) == QImode && !TARGET_64BIT \
1436 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1437 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1440 /* Given an rtx X being reloaded into a reg required to be
1441 in class CLASS, return the class of reg to actually use.
1442 In general this is just CLASS; but on some machines
1443 in some cases it is preferable to use a more restrictive class.
1444 On the 80386 series, we prevent floating constants from being
1445 reloaded into floating registers (since no move-insn can do that)
1446 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1448 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1449 QImode must go into class Q_REGS.
1450 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1451 movdf to do mem-to-mem moves through integer regs. */
1453 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1454 ix86_preferred_reload_class ((X), (CLASS))
1456 /* Discourage putting floating-point values in SSE registers unless
1457 SSE math is being used, and likewise for the 387 registers. */
1459 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1460 ix86_preferred_output_reload_class ((X), (CLASS))
1462 /* If we are copying between general and FP registers, we need a memory
1463 location. The same is true for SSE and MMX registers. */
1464 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1465 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1467 /* QImode spills from non-QI registers need a scratch. This does not
1468 happen often -- the only example so far requires an uninitialized
1471 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1472 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1473 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1476 /* Return the maximum number of consecutive registers
1477 needed to represent mode MODE in a register of class CLASS. */
1478 /* On the 80386, this is the size of MODE in words,
1479 except in the FP regs, where a single reg is always enough. */
1480 #define CLASS_MAX_NREGS(CLASS, MODE) \
1481 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1482 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1483 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1484 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1486 /* A C expression whose value is nonzero if pseudos that have been
1487 assigned to registers of class CLASS would likely be spilled
1488 because registers of CLASS are needed for spill registers.
1490 The default value of this macro returns 1 if CLASS has exactly one
1491 register and zero otherwise. On most machines, this default
1492 should be used. Only define this macro to some other expression
1493 if pseudo allocated by `local-alloc.c' end up in memory because
1494 their hard registers were needed for spill registers. If this
1495 macro returns nonzero for those classes, those pseudos will only
1496 be allocated by `global.c', which knows how to reallocate the
1497 pseudo to another register. If there would not be another
1498 register available for reallocation, you should not change the
1499 definition of this macro since the only effect of such a
1500 definition would be to slow down register allocation. */
1502 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1503 (((CLASS) == AREG) \
1504 || ((CLASS) == DREG) \
1505 || ((CLASS) == CREG) \
1506 || ((CLASS) == BREG) \
1507 || ((CLASS) == AD_REGS) \
1508 || ((CLASS) == SIREG) \
1509 || ((CLASS) == DIREG) \
1510 || ((CLASS) == FP_TOP_REG) \
1511 || ((CLASS) == FP_SECOND_REG))
1513 /* Return a class of registers that cannot change FROM mode to TO mode. */
1515 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1516 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1518 /* Stack layout; function entry, exit and calling. */
1520 /* Define this if pushing a word on the stack
1521 makes the stack pointer a smaller address. */
1522 #define STACK_GROWS_DOWNWARD
1524 /* Define this to nonzero if the nominal address of the stack frame
1525 is at the high-address end of the local variables;
1526 that is, each additional local variable allocated
1527 goes at a more negative offset in the frame. */
1528 #define FRAME_GROWS_DOWNWARD 1
1530 /* Offset within stack frame to start allocating local variables at.
1531 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1532 first local allocated. Otherwise, it is the offset to the BEGINNING
1533 of the first local allocated. */
1534 #define STARTING_FRAME_OFFSET 0
1536 /* If we generate an insn to push BYTES bytes,
1537 this says how many the stack pointer really advances by.
1538 On 386, we have pushw instruction that decrements by exactly 2 no
1539 matter what the position was, there is no pushb.
1540 But as CIE data alignment factor on this arch is -4, we need to make
1541 sure all stack pointer adjustments are in multiple of 4.
1543 For 64bit ABI we round up to 8 bytes.
1546 #define PUSH_ROUNDING(BYTES) \
1548 ? (((BYTES) + 7) & (-8)) \
1549 : (((BYTES) + 3) & (-4)))
1551 /* If defined, the maximum amount of space required for outgoing arguments will
1552 be computed and placed into the variable
1553 `current_function_outgoing_args_size'. No space will be pushed onto the
1554 stack for each call; instead, the function prologue should increase the stack
1555 frame size by this amount. */
1557 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1559 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1560 instructions to pass outgoing arguments. */
1562 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1564 /* We want the stack and args grow in opposite directions, even if
1566 #define PUSH_ARGS_REVERSED 1
1568 /* Offset of first parameter from the argument pointer register value. */
1569 #define FIRST_PARM_OFFSET(FNDECL) 0
1571 /* Define this macro if functions should assume that stack space has been
1572 allocated for arguments even when their values are passed in registers.
1574 The value of this macro is the size, in bytes, of the area reserved for
1575 arguments passed in registers for the function represented by FNDECL.
1577 This space can be allocated by the caller, or be a part of the
1578 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1580 #define REG_PARM_STACK_SPACE(FNDECL) 0
1582 /* Value is the number of bytes of arguments automatically
1583 popped when returning from a subroutine call.
1584 FUNDECL is the declaration node of the function (as a tree),
1585 FUNTYPE is the data type of the function (as a tree),
1586 or for a library call it is an identifier node for the subroutine name.
1587 SIZE is the number of bytes of arguments passed on the stack.
1589 On the 80386, the RTD insn may be used to pop them if the number
1590 of args is fixed, but if the number is variable then the caller
1591 must pop them all. RTD can't be used for library calls now
1592 because the library is compiled with the Unix compiler.
1593 Use of RTD is a selectable option, since it is incompatible with
1594 standard Unix calling sequences. If the option is not selected,
1595 the caller must always pop the args.
1597 The attribute stdcall is equivalent to RTD on a per module basis. */
1599 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1600 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1602 #define FUNCTION_VALUE_REGNO_P(N) \
1603 ix86_function_value_regno_p (N)
1605 /* Define how to find the value returned by a library function
1606 assuming the value has mode MODE. */
1608 #define LIBCALL_VALUE(MODE) \
1609 ix86_libcall_value (MODE)
1611 /* Define the size of the result block used for communication between
1612 untyped_call and untyped_return. The block contains a DImode value
1613 followed by the block used by fnsave and frstor. */
1615 #define APPLY_RESULT_SIZE (8+108)
1617 /* 1 if N is a possible register number for function argument passing. */
1618 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1620 /* Define a data type for recording info about an argument list
1621 during the scan of that argument list. This data type should
1622 hold all necessary information about the function itself
1623 and about the args processed so far, enough to enable macros
1624 such as FUNCTION_ARG to determine where the next arg should go. */
1626 typedef struct ix86_args {
1627 int words; /* # words passed so far */
1628 int nregs; /* # registers available for passing */
1629 int regno; /* next available register number */
1630 int fastcall; /* fastcall calling convention is used */
1631 int sse_words; /* # sse words passed so far */
1632 int sse_nregs; /* # sse registers available for passing */
1633 int warn_sse; /* True when we want to warn about SSE ABI. */
1634 int warn_mmx; /* True when we want to warn about MMX ABI. */
1635 int sse_regno; /* next available sse register number */
1636 int mmx_words; /* # mmx words passed so far */
1637 int mmx_nregs; /* # mmx registers available for passing */
1638 int mmx_regno; /* next available mmx register number */
1639 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1640 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1641 be passed in SSE registers. Otherwise 0. */
1644 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1645 for a call to a function whose data type is FNTYPE.
1646 For a library call, FNTYPE is 0. */
1648 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1649 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1651 /* Update the data in CUM to advance over an argument
1652 of mode MODE and data type TYPE.
1653 (TYPE is null for libcalls where that information may not be available.) */
1655 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1656 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1658 /* Define where to put the arguments to a function.
1659 Value is zero to push the argument on the stack,
1660 or a hard register in which to store the argument.
1662 MODE is the argument's machine mode.
1663 TYPE is the data type of the argument (as a tree).
1664 This is null for libcalls where that information may
1666 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1667 the preceding args and about the function being called.
1668 NAMED is nonzero if this argument is a named parameter
1669 (otherwise it is an extra parameter matching an ellipsis). */
1671 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1672 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1674 /* Implement `va_start' for varargs and stdarg. */
1675 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1676 ix86_va_start (VALIST, NEXTARG)
1678 #define TARGET_ASM_FILE_END ix86_file_end
1679 #define NEED_INDICATE_EXEC_STACK 0
1681 /* Output assembler code to FILE to increment profiler label # LABELNO
1682 for profiling a function entry. */
1684 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1686 #define MCOUNT_NAME "_mcount"
1688 #define PROFILE_COUNT_REGISTER "edx"
1690 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1691 the stack pointer does not matter. The value is tested only in
1692 functions that have frame pointers.
1693 No definition is equivalent to always zero. */
1694 /* Note on the 386 it might be more efficient not to define this since
1695 we have to restore it ourselves from the frame pointer, in order to
1698 #define EXIT_IGNORE_STACK 1
1700 /* Output assembler code for a block containing the constant parts
1701 of a trampoline, leaving space for the variable parts. */
1703 /* On the 386, the trampoline contains two instructions:
1706 The trampoline is generated entirely at runtime. The operand of JMP
1707 is the address of FUNCTION relative to the instruction following the
1708 JMP (which is 5 bytes long). */
1710 /* Length in units of the trampoline for entering a nested function. */
1712 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1714 /* Emit RTL insns to initialize the variable parts of a trampoline.
1715 FNADDR is an RTX for the address of the function's pure code.
1716 CXT is an RTX for the static chain value for the function. */
1718 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1719 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1721 /* Definitions for register eliminations.
1723 This is an array of structures. Each structure initializes one pair
1724 of eliminable registers. The "from" register number is given first,
1725 followed by "to". Eliminations of the same "from" register are listed
1726 in order of preference.
1728 There are two registers that can always be eliminated on the i386.
1729 The frame pointer and the arg pointer can be replaced by either the
1730 hard frame pointer or to the stack pointer, depending upon the
1731 circumstances. The hard frame pointer is not used before reload and
1732 so it is not eligible for elimination. */
1734 #define ELIMINABLE_REGS \
1735 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1736 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1737 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1738 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1740 /* Given FROM and TO register numbers, say whether this elimination is
1741 allowed. Frame pointer elimination is automatically handled.
1743 All other eliminations are valid. */
1745 #define CAN_ELIMINATE(FROM, TO) \
1746 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1748 /* Define the offset between two registers, one to be eliminated, and the other
1749 its replacement, at the start of a routine. */
1751 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1752 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1754 /* Addressing modes, and classification of registers for them. */
1756 /* Macros to check register numbers against specific register classes. */
1758 /* These assume that REGNO is a hard or pseudo reg number.
1759 They give nonzero only if REGNO is a hard reg of the suitable class
1760 or a pseudo reg currently allocated to a suitable hard reg.
1761 Since they use reg_renumber, they are safe only once reg_renumber
1762 has been allocated, which happens in local-alloc.c. */
1764 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1765 ((REGNO) < STACK_POINTER_REGNUM \
1766 || REX_INT_REGNO_P (REGNO) \
1767 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1768 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1770 #define REGNO_OK_FOR_BASE_P(REGNO) \
1771 (GENERAL_REGNO_P (REGNO) \
1772 || (REGNO) == ARG_POINTER_REGNUM \
1773 || (REGNO) == FRAME_POINTER_REGNUM \
1774 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1776 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1777 and check its validity for a certain class.
1778 We have two alternate definitions for each of them.
1779 The usual definition accepts all pseudo regs; the other rejects
1780 them unless they have been allocated suitable hard regs.
1781 The symbol REG_OK_STRICT causes the latter definition to be used.
1783 Most source files want to accept pseudo regs in the hope that
1784 they will get allocated to the class that the insn wants them to be in.
1785 Source files for reload pass need to be strict.
1786 After reload, it makes no difference, since pseudo regs have
1787 been eliminated by then. */
1790 /* Non strict versions, pseudos are ok. */
1791 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1792 (REGNO (X) < STACK_POINTER_REGNUM \
1793 || REX_INT_REGNO_P (REGNO (X)) \
1794 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1796 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1797 (GENERAL_REGNO_P (REGNO (X)) \
1798 || REGNO (X) == ARG_POINTER_REGNUM \
1799 || REGNO (X) == FRAME_POINTER_REGNUM \
1800 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1802 /* Strict versions, hard registers only */
1803 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1804 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1806 #ifndef REG_OK_STRICT
1807 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1808 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1811 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1812 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1815 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1816 that is a valid memory address for an instruction.
1817 The MODE argument is the machine mode for the MEM expression
1818 that wants to use this address.
1820 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1821 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1823 See legitimize_pic_address in i386.c for details as to what
1824 constitutes a legitimate address when -fpic is used. */
1826 #define MAX_REGS_PER_ADDRESS 2
1828 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1830 /* Nonzero if the constant value X is a legitimate general operand.
1831 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1833 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1835 #ifdef REG_OK_STRICT
1836 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1838 if (legitimate_address_p ((MODE), (X), 1)) \
1843 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1845 if (legitimate_address_p ((MODE), (X), 0)) \
1851 /* If defined, a C expression to determine the base term of address X.
1852 This macro is used in only one place: `find_base_term' in alias.c.
1854 It is always safe for this macro to not be defined. It exists so
1855 that alias analysis can understand machine-dependent addresses.
1857 The typical use of this macro is to handle addresses containing
1858 a label_ref or symbol_ref within an UNSPEC. */
1860 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1862 /* Try machine-dependent ways of modifying an illegitimate address
1863 to be legitimate. If we find one, return the new, valid address.
1864 This macro is used in only one place: `memory_address' in explow.c.
1866 OLDX is the address as it was before break_out_memory_refs was called.
1867 In some cases it is useful to look at this to decide what needs to be done.
1869 MODE and WIN are passed so that this macro can use
1870 GO_IF_LEGITIMATE_ADDRESS.
1872 It is always safe for this macro to do nothing. It exists to recognize
1873 opportunities to optimize the output.
1875 For the 80386, we handle X+REG by loading X into a register R and
1876 using R+REG. R will go in a general reg and indexing will be used.
1877 However, if REG is a broken-out memory address or multiplication,
1878 nothing needs to be done because REG can certainly go in a general reg.
1880 When -fpic is used, special handling is needed for symbolic references.
1881 See comments by legitimize_pic_address in i386.c for details. */
1883 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1885 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1886 if (memory_address_p ((MODE), (X))) \
1890 /* Nonzero if the constant value X is a legitimate general operand
1891 when generating PIC code. It is given that flag_pic is on and
1892 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1894 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1896 #define SYMBOLIC_CONST(X) \
1897 (GET_CODE (X) == SYMBOL_REF \
1898 || GET_CODE (X) == LABEL_REF \
1899 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1901 /* Go to LABEL if ADDR (a legitimate address expression)
1902 has an effect that depends on the machine mode it is used for.
1903 On the 80386, only postdecrement and postincrement address depend thus
1904 (the amount of decrement or increment being the length of the operand).
1905 These are now caught in recog.c. */
1906 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
1908 /* Max number of args passed in registers. If this is more than 3, we will
1909 have problems with ebx (register #4), since it is a caller save register and
1910 is also used as the pic register in ELF. So for now, don't allow more than
1911 3 registers to be passed in registers. */
1913 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1915 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1917 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1920 /* Specify the machine mode that this machine uses
1921 for the index in the tablejump instruction. */
1922 #define CASE_VECTOR_MODE \
1923 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1925 /* Define this as 1 if `char' should by default be signed; else as 0. */
1926 #define DEFAULT_SIGNED_CHAR 1
1928 /* Max number of bytes we can move from memory to memory
1929 in one reasonably fast instruction. */
1932 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1933 move efficiently, as opposed to MOVE_MAX which is the maximum
1934 number of bytes we can move with a single instruction. */
1935 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1937 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1938 move-instruction pairs, we will do a movmem or libcall instead.
1939 Increasing the value will always make code faster, but eventually
1940 incurs high cost in increased code size.
1942 If you don't define this, a reasonable default is used. */
1944 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1946 /* If a clear memory operation would take CLEAR_RATIO or more simple
1947 move-instruction sequences, we will do a clrmem or libcall instead. */
1949 #define CLEAR_RATIO (optimize_size ? 2 \
1950 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1952 /* Define if shifts truncate the shift count
1953 which implies one can omit a sign-extension or zero-extension
1954 of a shift count. */
1955 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1957 /* #define SHIFT_COUNT_TRUNCATED */
1959 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1960 is done just by pretending it is already truncated. */
1961 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1963 /* A macro to update M and UNSIGNEDP when an object whose type is
1964 TYPE and which has the specified mode and signedness is to be
1965 stored in a register. This macro is only called when TYPE is a
1968 On i386 it is sometimes useful to promote HImode and QImode
1969 quantities to SImode. The choice depends on target type. */
1971 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1973 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1974 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1978 /* Specify the machine mode that pointers have.
1979 After generation of rtl, the compiler makes no further distinction
1980 between pointers and any other objects of this machine mode. */
1981 #define Pmode (TARGET_64BIT ? DImode : SImode)
1983 /* A function address in a call instruction
1984 is a byte address (for indexing purposes)
1985 so give the MEM rtx a byte's mode. */
1986 #define FUNCTION_MODE QImode
1988 /* A C expression for the cost of moving data from a register in class FROM to
1989 one in class TO. The classes are expressed using the enumeration values
1990 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1991 interpreted relative to that.
1993 It is not required that the cost always equal 2 when FROM is the same as TO;
1994 on some machines it is expensive to move between registers if they are not
1995 general registers. */
1997 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1998 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2000 /* A C expression for the cost of moving data of mode M between a
2001 register and memory. A value of 2 is the default; this cost is
2002 relative to those in `REGISTER_MOVE_COST'.
2004 If moving between registers and memory is more expensive than
2005 between two registers, you should define this macro to express the
2008 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2009 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2011 /* A C expression for the cost of a branch instruction. A value of 1
2012 is the default; other values are interpreted relative to that. */
2014 #define BRANCH_COST ix86_branch_cost
2016 /* Define this macro as a C expression which is nonzero if accessing
2017 less than a word of memory (i.e. a `char' or a `short') is no
2018 faster than accessing a word of memory, i.e., if such access
2019 require more than one instruction or if there is no difference in
2020 cost between byte and (aligned) word loads.
2022 When this macro is not defined, the compiler will access a field by
2023 finding the smallest containing object; when it is defined, a
2024 fullword load will be used if alignment permits. Unless bytes
2025 accesses are faster than word accesses, using word accesses is
2026 preferable since it may eliminate subsequent memory access if
2027 subsequent accesses occur to other fields in the same word of the
2028 structure, but to different bytes. */
2030 #define SLOW_BYTE_ACCESS 0
2032 /* Nonzero if access to memory by shorts is slow and undesirable. */
2033 #define SLOW_SHORT_ACCESS 0
2035 /* Define this macro to be the value 1 if unaligned accesses have a
2036 cost many times greater than aligned accesses, for example if they
2037 are emulated in a trap handler.
2039 When this macro is nonzero, the compiler will act as if
2040 `STRICT_ALIGNMENT' were nonzero when generating code for block
2041 moves. This can cause significantly more instructions to be
2042 produced. Therefore, do not set this macro nonzero if unaligned
2043 accesses only add a cycle or two to the time for a memory access.
2045 If the value of this macro is always zero, it need not be defined. */
2047 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2049 /* Define this macro if it is as good or better to call a constant
2050 function address than to call an address kept in a register.
2052 Desirable on the 386 because a CALL with a constant address is
2053 faster than one with a register address. */
2055 #define NO_FUNCTION_CSE
2057 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2058 return the mode to be used for the comparison.
2060 For floating-point equality comparisons, CCFPEQmode should be used.
2061 VOIDmode should be used in all other cases.
2063 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2064 possible, to allow for more combinations. */
2066 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2068 /* Canonicalize overflow checks to save on the insn patterns. We change
2069 "a + b < b" into "a + b < a" and "a + b >= b" into "a + b >= a". */
2070 #define CANONICALIZE_COMPARISON(code, op0, op1) \
2072 if ((code == LTU || code == GEU) \
2073 && GET_CODE (op0) == PLUS \
2074 && rtx_equal_p (op1, XEXP (op0, 1))) \
2075 op1 = XEXP (op0, 0); \
2078 /* Return nonzero if MODE implies a floating point inequality can be
2081 #define REVERSIBLE_CC_MODE(MODE) 1
2083 /* A C expression whose value is reversed condition code of the CODE for
2084 comparison done in CC_MODE mode. */
2085 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2088 /* Control the assembler format that we output, to the extent
2089 this does not vary between assemblers. */
2091 /* How to refer to registers in assembler output.
2092 This sequence is indexed by compiler's hard-register-number (see above). */
2094 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2095 For non floating point regs, the following are the HImode names.
2097 For float regs, the stack top is sometimes referred to as "%st(0)"
2098 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2100 #define HI_REGISTER_NAMES \
2101 {"ax","dx","cx","bx","si","di","bp","sp", \
2102 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2103 "argp", "flags", "fpsr", "fpcr", "frame", \
2104 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2105 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2106 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2107 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2109 #define REGISTER_NAMES HI_REGISTER_NAMES
2111 /* Table of additional register names to use in user input. */
2113 #define ADDITIONAL_REGISTER_NAMES \
2114 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2115 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2116 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2117 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2118 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2119 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2121 /* Note we are omitting these since currently I don't know how
2122 to get gcc to use these, since they want the same but different
2123 number as al, and ax.
2126 #define QI_REGISTER_NAMES \
2127 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2129 /* These parallel the array above, and can be used to access bits 8:15
2130 of regs 0 through 3. */
2132 #define QI_HIGH_REGISTER_NAMES \
2133 {"ah", "dh", "ch", "bh", }
2135 /* How to renumber registers for dbx and gdb. */
2137 #define DBX_REGISTER_NUMBER(N) \
2138 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2140 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2141 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2142 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2144 /* Before the prologue, RA is at 0(%esp). */
2145 #define INCOMING_RETURN_ADDR_RTX \
2146 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2148 /* After the prologue, RA is at -4(AP) in the current frame. */
2149 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2151 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2152 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2154 /* PC is dbx register 8; let's use that column for RA. */
2155 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2157 /* Before the prologue, the top of the frame is at 4(%esp). */
2158 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2160 /* Describe how we implement __builtin_eh_return. */
2161 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2162 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2165 /* Select a format to encode pointers in exception handling data. CODE
2166 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2167 true if the symbol may be affected by dynamic relocations.
2169 ??? All x86 object file formats are capable of representing this.
2170 After all, the relocation needed is the same as for the call insn.
2171 Whether or not a particular assembler allows us to enter such, I
2172 guess we'll have to see. */
2173 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2174 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2176 /* This is how to output an insn to push a register on the stack.
2177 It need not be very fast code. */
2179 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2182 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2183 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2185 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2188 /* This is how to output an insn to pop a register from the stack.
2189 It need not be very fast code. */
2191 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2194 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2195 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2197 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2200 /* This is how to output an element of a case-vector that is absolute. */
2202 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2203 ix86_output_addr_vec_elt ((FILE), (VALUE))
2205 /* This is how to output an element of a case-vector that is relative. */
2207 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2208 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2210 /* Under some conditions we need jump tables in the text section,
2211 because the assembler cannot handle label differences between
2212 sections. This is the case for x86_64 on Mach-O for example. */
2214 #define JUMP_TABLES_IN_TEXT_SECTION \
2215 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2216 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2218 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2219 and switch back. For x86 we do this only to save a few bytes that
2220 would otherwise be unused in the text section. */
2221 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2222 asm (SECTION_OP "\n\t" \
2223 "call " USER_LABEL_PREFIX #FUNC "\n" \
2224 TEXT_SECTION_ASM_OP);
2226 /* Print operand X (an rtx) in assembler syntax to file FILE.
2227 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2228 Effect of various CODE letters is described in i386.c near
2229 print_operand function. */
2231 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2232 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';')
2234 #define PRINT_OPERAND(FILE, X, CODE) \
2235 print_operand ((FILE), (X), (CODE))
2237 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2238 print_operand_address ((FILE), (ADDR))
2240 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2242 if (! output_addr_const_extra (FILE, (X))) \
2246 /* Which processor to schedule for. The cpu attribute defines a list that
2247 mirrors this list, so changes to i386.md must be made at the same time. */
2251 PROCESSOR_I386, /* 80386 */
2252 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2254 PROCESSOR_PENTIUMPRO,
2262 PROCESSOR_GENERIC32,
2263 PROCESSOR_GENERIC64,
2268 extern enum processor_type ix86_tune;
2269 extern enum processor_type ix86_arch;
2277 extern enum fpmath_unit ix86_fpmath;
2286 extern enum tls_dialect ix86_tls_dialect;
2289 CM_32, /* The traditional 32-bit ABI. */
2290 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2291 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2292 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2293 CM_LARGE, /* No assumptions. */
2294 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2295 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2296 CM_LARGE_PIC /* No assumptions. */
2299 extern enum cmodel ix86_cmodel;
2301 /* Size of the RED_ZONE area. */
2302 #define RED_ZONE_SIZE 128
2303 /* Reserved area of the red zone for temporaries. */
2304 #define RED_ZONE_RESERVE 8
2311 extern enum asm_dialect ix86_asm_dialect;
2312 extern unsigned int ix86_preferred_stack_boundary;
2313 extern int ix86_branch_cost, ix86_section_threshold;
2315 /* Smallest class containing REGNO. */
2316 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2318 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2319 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2320 extern rtx ix86_compare_emitted;
2322 /* To properly truncate FP values into integers, we need to set i387 control
2323 word. We can't emit proper mode switching code before reload, as spills
2324 generated by reload may truncate values incorrectly, but we still can avoid
2325 redundant computation of new control word by the mode switching pass.
2326 The fldcw instructions are still emitted redundantly, but this is probably
2327 not going to be noticeable problem, as most CPUs do have fast path for
2330 The machinery is to emit simple truncation instructions and split them
2331 before reload to instructions having USEs of two memory locations that
2332 are filled by this code to old and new control word.
2334 Post-reload pass may be later used to eliminate the redundant fildcw if
2346 enum ix86_stack_slot
2355 MAX_386_STACK_LOCALS
2358 /* Define this macro if the port needs extra instructions inserted
2359 for mode switching in an optimizing compilation. */
2361 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2362 ix86_optimize_mode_switching[(ENTITY)]
2364 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2365 initializer for an array of integers. Each initializer element N
2366 refers to an entity that needs mode switching, and specifies the
2367 number of different modes that might need to be set for this
2368 entity. The position of the initializer in the initializer -
2369 starting counting at zero - determines the integer that is used to
2370 refer to the mode-switched entity in question. */
2372 #define NUM_MODES_FOR_MODE_SWITCHING \
2373 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2375 /* ENTITY is an integer specifying a mode-switched entity. If
2376 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2377 return an integer value not larger than the corresponding element
2378 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2379 must be switched into prior to the execution of INSN. */
2381 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2383 /* This macro specifies the order in which modes for ENTITY are
2384 processed. 0 is the highest priority. */
2386 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2388 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2389 is the set of hard registers live at the point where the insn(s)
2390 are to be inserted. */
2392 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2393 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2394 ? emit_i387_cw_initialization (MODE), 0 \
2398 /* Avoid renaming of stack registers, as doing so in combination with
2399 scheduling just increases amount of live registers at time and in
2400 the turn amount of fxch instructions needed.
2402 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2404 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2405 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2408 #define FASTCALL_PREFIX '@'
2410 struct machine_function GTY(())
2412 struct stack_local_entry *stack_locals;
2413 const char *some_ld_name;
2414 rtx force_align_arg_pointer;
2415 int save_varrargs_registers;
2416 int accesses_prev_frame;
2417 int optimize_mode_switching[MAX_386_ENTITIES];
2418 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2419 determine the style used. */
2420 int use_fast_prologue_epilogue;
2421 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2423 int use_fast_prologue_epilogue_nregs;
2424 /* If true, the current function needs the default PIC register, not
2425 an alternate register (on x86) and must not use the red zone (on
2426 x86_64), even if it's a leaf function. We don't want the
2427 function to be regarded as non-leaf because TLS calls need not
2428 affect register allocation. This flag is set when a TLS call
2429 instruction is expanded within a function, and never reset, even
2430 if all such instructions are optimized away. Use the
2431 ix86_current_function_calls_tls_descriptor macro for a better
2433 int tls_descriptor_call_expanded_p;
2436 #define ix86_stack_locals (cfun->machine->stack_locals)
2437 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2438 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2439 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2440 (cfun->machine->tls_descriptor_call_expanded_p)
2441 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2442 calls are optimized away, we try to detect cases in which it was
2443 optimized away. Since such instructions (use (reg REG_SP)), we can
2444 verify whether there's any such instruction live by testing that
2446 #define ix86_current_function_calls_tls_descriptor \
2447 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2449 /* Control behavior of x86_file_start. */
2450 #define X86_FILE_START_VERSION_DIRECTIVE false
2451 #define X86_FILE_START_FLTUSED false
2453 /* Flag to mark data that is in the large address area. */
2454 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2455 #define SYMBOL_REF_FAR_ADDR_P(X) \
2456 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2458 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2459 have defined always, to avoid ifdefing. */
2460 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2461 #define SYMBOL_REF_DLLIMPORT_P(X) \
2462 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2464 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2465 #define SYMBOL_REF_DLLEXPORT_P(X) \
2466 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
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