1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Define the specific costs for a given cpu */
39 struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init[5]; /* cost of starting a multiply
45 in QImode, HImode, SImode, DImode, TImode*/
46 const int mult_bit; /* cost of multiply per each bit set */
47 const int divide[5]; /* cost of a divide/mod
48 in QImode, HImode, SImode, DImode, TImode*/
49 int movsx; /* The cost of movsx operation. */
50 int movzx; /* The cost of movzx operation. */
51 const int large_insn; /* insns larger than this cost more */
52 const int move_ratio; /* The threshold of number of scalar
53 memory-to-memory move insns. */
54 const int movzbl_load; /* cost of loading using movzbl */
55 const int int_load[3]; /* cost of loading integer registers
56 in QImode, HImode and SImode relative
57 to reg-reg move (2). */
58 const int int_store[3]; /* cost of storing integer register
59 in QImode, HImode and SImode */
60 const int fp_move; /* cost of reg,reg fld/fst */
61 const int fp_load[3]; /* cost of loading FP register
62 in SFmode, DFmode and XFmode */
63 const int fp_store[3]; /* cost of storing FP register
64 in SFmode, DFmode and XFmode */
65 const int mmx_move; /* cost of moving MMX register. */
66 const int mmx_load[2]; /* cost of loading MMX register
67 in SImode and DImode */
68 const int mmx_store[2]; /* cost of storing MMX register
69 in SImode and DImode */
70 const int sse_move; /* cost of moving SSE register. */
71 const int sse_load[3]; /* cost of loading SSE register
72 in SImode, DImode and TImode*/
73 const int sse_store[3]; /* cost of storing SSE register
74 in SImode, DImode and TImode*/
75 const int mmxsse_to_integer; /* cost of moving mmxsse register to
76 integer and vice versa. */
77 const int prefetch_block; /* bytes moved to cache for prefetch. */
78 const int simultaneous_prefetches; /* number of parallel prefetch
80 const int branch_cost; /* Default value for BRANCH_COST. */
81 const int fadd; /* cost of FADD and FSUB instructions. */
82 const int fmul; /* cost of FMUL instruction. */
83 const int fdiv; /* cost of FDIV instruction. */
84 const int fabs; /* cost of FABS instruction. */
85 const int fchs; /* cost of FCHS instruction. */
86 const int fsqrt; /* cost of FSQRT instruction. */
89 extern const struct processor_costs *ix86_cost;
91 /* Run-time compilation parameters selecting different hardware subsets. */
93 extern int target_flags;
95 /* Macros used in the machine description to test the flags. */
97 /* configure can arrange to make this 2, to force a 486. */
99 #ifndef TARGET_CPU_DEFAULT
100 #define TARGET_CPU_DEFAULT 0
103 /* Masks for the -m switches */
104 #define MASK_80387 0x00000001 /* Hardware floating point */
105 #define MASK_RTD 0x00000002 /* Use ret that pops args */
106 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
107 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
108 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
109 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
110 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
111 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
112 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
113 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
114 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
115 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
116 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
117 #define MASK_MMX 0x00002000 /* Support MMX regs/builtins */
118 #define MASK_SSE 0x00004000 /* Support SSE regs/builtins */
119 #define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */
120 #define MASK_3DNOW 0x00010000 /* Support 3Dnow builtins */
121 #define MASK_3DNOW_A 0x00020000 /* Support Athlon 3Dnow builtins */
122 #define MASK_128BIT_LONG_DOUBLE 0x00040000 /* long double size is 128bit */
123 #define MASK_64BIT 0x00080000 /* Produce 64bit code */
124 #define MASK_MS_BITFIELD_LAYOUT 0x00100000 /* Use native (MS) bitfield layout */
126 /* Unused: 0x03e0000 */
128 /* ... overlap with subtarget options starts by 0x04000000. */
129 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
131 /* Use the floating point instructions */
132 #define TARGET_80387 (target_flags & MASK_80387)
134 /* Compile using ret insn that pops args.
135 This will not work unless you use prototypes at least
136 for all functions that can take varying numbers of args. */
137 #define TARGET_RTD (target_flags & MASK_RTD)
139 /* Align doubles to a two word boundary. This breaks compatibility with
140 the published ABI's for structures containing doubles, but produces
141 faster code on the pentium. */
142 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
144 /* Use push instructions to save outgoing args. */
145 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
147 /* Accumulate stack adjustments to prologue/epilogue. */
148 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
149 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
151 /* Put uninitialized locals into bss, not data.
152 Meaningful only on svr3. */
153 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
155 /* Use IEEE floating point comparisons. These handle correctly the cases
156 where the result of a comparison is unordered. Normally SIGFPE is
157 generated in such cases, in which case this isn't needed. */
158 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
160 /* Functions that return a floating point value may return that value
161 in the 387 FPU or in 386 integer registers. If set, this flag causes
162 the 387 to be used, which is compatible with most calling conventions. */
163 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
165 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
166 This mode wastes cache, but avoid misaligned data accesses and simplifies
167 address calculations. */
168 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
170 /* Disable generation of FP sin, cos and sqrt operations for 387.
171 This is because FreeBSD lacks these in the math-emulator-code */
172 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
174 /* Don't create frame pointers for leaf functions */
175 #define TARGET_OMIT_LEAF_FRAME_POINTER \
176 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
178 /* Debug GO_IF_LEGITIMATE_ADDRESS */
179 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
181 /* Debug FUNCTION_ARG macros */
182 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
184 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
185 compile-time constant. */
188 #define TARGET_64BIT 1
190 #define TARGET_64BIT 0
193 #ifdef TARGET_BI_ARCH
194 #define TARGET_64BIT (target_flags & MASK_64BIT)
196 #if TARGET_64BIT_DEFAULT
197 #define TARGET_64BIT 1
199 #define TARGET_64BIT 0
204 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
205 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
206 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
207 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
208 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
209 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
210 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
211 #define TARGET_K8 (ix86_cpu == PROCESSOR_K8)
212 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
214 #define CPUMASK (1 << ix86_cpu)
215 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
216 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
217 extern const int x86_branch_hints, x86_unroll_strlen;
218 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
219 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
220 extern const int x86_use_cltd, x86_read_modify_write;
221 extern const int x86_read_modify, x86_split_long_moves;
222 extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
223 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
224 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
225 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
226 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
227 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
228 extern const int x86_epilogue_using_move, x86_decompose_lea;
229 extern const int x86_arch_always_fancy_math_387, x86_shift1;
230 extern const int x86_sse_partial_reg_dependency, x86_sse_partial_regs;
231 extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
232 extern const int x86_use_ffreep, x86_sse_partial_regs_for_cvtsd2ss;
233 extern const int x86_inter_unit_moves;
234 extern int x86_prefetch_sse;
236 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
237 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
238 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
239 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
240 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
241 /* For sane SSE instruction set generation we need fcomi instruction. It is
242 safe to enable all CMOVE instructions. */
243 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
244 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
245 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
246 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
247 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
248 #define TARGET_MOVX (x86_movx & CPUMASK)
249 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
250 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
251 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
252 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
253 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
254 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
255 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
256 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
257 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
258 #define TARGET_FAST_PREFIX (x86_fast_prefix & CPUMASK)
259 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
260 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
261 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
262 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
263 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
264 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
265 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
266 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
267 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
268 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
269 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
270 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
271 (x86_sse_partial_reg_dependency & CPUMASK)
272 #define TARGET_SSE_PARTIAL_REGS (x86_sse_partial_regs & CPUMASK)
273 #define TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS \
274 (x86_sse_partial_regs_for_cvtsd2ss & CPUMASK)
275 #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & CPUMASK)
276 #define TARGET_SSE_TYPELESS_LOAD0 (x86_sse_typeless_load0 & CPUMASK)
277 #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & CPUMASK)
278 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
279 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
280 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
281 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
282 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
283 #define TARGET_SHIFT1 (x86_shift1 & CPUMASK)
284 #define TARGET_USE_FFREEP (x86_use_ffreep & CPUMASK)
285 #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & CPUMASK)
286 #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & CPUMASK)
288 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
290 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
291 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
293 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
295 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
296 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
297 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
298 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
299 && (ix86_fpmath & FPMATH_387))
300 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
301 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
302 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
304 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
306 #define TARGET_USE_MS_BITFIELD_LAYOUT (target_flags & MASK_MS_BITFIELD_LAYOUT)
308 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
309 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
311 /* WARNING: Do not mark empty strings for translation, as calling
312 gettext on an empty string does NOT return an empty
316 #define TARGET_SWITCHES \
317 { { "80387", MASK_80387, N_("Use hardware fp") }, \
318 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
319 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
320 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
321 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
322 { "386", 0, "" /*Deprecated.*/}, \
323 { "486", 0, "" /*Deprecated.*/}, \
324 { "pentium", 0, "" /*Deprecated.*/}, \
325 { "pentiumpro", 0, "" /*Deprecated.*/}, \
326 { "intel-syntax", 0, "" /*Deprecated.*/}, \
327 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
329 N_("Alternate calling convention") }, \
330 { "no-rtd", -MASK_RTD, \
331 N_("Use normal calling convention") }, \
332 { "align-double", MASK_ALIGN_DOUBLE, \
333 N_("Align some doubles on dword boundary") }, \
334 { "no-align-double", -MASK_ALIGN_DOUBLE, \
335 N_("Align doubles on word boundary") }, \
336 { "svr3-shlib", MASK_SVR3_SHLIB, \
337 N_("Uninitialized locals in .bss") }, \
338 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
339 N_("Uninitialized locals in .data") }, \
340 { "ieee-fp", MASK_IEEE_FP, \
341 N_("Use IEEE math for fp comparisons") }, \
342 { "no-ieee-fp", -MASK_IEEE_FP, \
343 N_("Do not use IEEE math for fp comparisons") }, \
344 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
345 N_("Return values of functions in FPU registers") }, \
346 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
347 N_("Do not return values of functions in FPU registers")}, \
348 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
349 N_("Do not generate sin, cos, sqrt for FPU") }, \
350 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
351 N_("Generate sin, cos, sqrt for FPU")}, \
352 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
353 N_("Omit the frame pointer in leaf functions") }, \
354 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
355 { "stack-arg-probe", MASK_STACK_PROBE, \
356 N_("Enable stack probing") }, \
357 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
358 { "windows", 0, 0 /* undocumented */ }, \
359 { "dll", 0, 0 /* undocumented */ }, \
360 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
361 N_("Align destination of the string operations") }, \
362 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
363 N_("Do not align destination of the string operations") }, \
364 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
365 N_("Inline all known string operations") }, \
366 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
367 N_("Do not inline all known string operations") }, \
368 { "push-args", -MASK_NO_PUSH_ARGS, \
369 N_("Use push instructions to save outgoing arguments") }, \
370 { "no-push-args", MASK_NO_PUSH_ARGS, \
371 N_("Do not use push instructions to save outgoing arguments") }, \
372 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
373 N_("Use push instructions to save outgoing arguments") }, \
374 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
375 N_("Do not use push instructions to save outgoing arguments") }, \
377 N_("Support MMX built-in functions") }, \
378 { "no-mmx", -MASK_MMX, \
379 N_("Do not support MMX built-in functions") }, \
380 { "3dnow", MASK_3DNOW, \
381 N_("Support 3DNow! built-in functions") }, \
382 { "no-3dnow", -MASK_3DNOW, \
383 N_("Do not support 3DNow! built-in functions") }, \
385 N_("Support MMX and SSE built-in functions and code generation") }, \
386 { "no-sse", -MASK_SSE, \
387 N_("Do not support MMX and SSE built-in functions and code generation") },\
388 { "sse2", MASK_SSE2, \
389 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
390 { "no-sse2", -MASK_SSE2, \
391 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
392 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
393 N_("sizeof(long double) is 16") }, \
394 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
395 N_("sizeof(long double) is 12") }, \
396 { "64", MASK_64BIT, \
397 N_("Generate 64bit x86-64 code") }, \
398 { "32", -MASK_64BIT, \
399 N_("Generate 32bit i386 code") }, \
400 { "ms-bitfields", MASK_MS_BITFIELD_LAYOUT, \
401 N_("Use native (MS) bitfield layout") }, \
402 { "no-ms-bitfields", -MASK_MS_BITFIELD_LAYOUT, \
403 N_("Use gcc default bitfield layout") }, \
404 { "red-zone", -MASK_NO_RED_ZONE, \
405 N_("Use red-zone in the x86-64 code") }, \
406 { "no-red-zone", MASK_NO_RED_ZONE, \
407 N_("Do not use red-zone in the x86-64 code") }, \
409 { "", TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT, 0 }}
411 #ifndef TARGET_64BIT_DEFAULT
412 #define TARGET_64BIT_DEFAULT 0
415 /* Once GDB has been enhanced to deal with functions without frame
416 pointers, we can change this to allow for elimination of
417 the frame pointer in leaf functions. */
418 #define TARGET_DEFAULT 0
420 /* This is not really a target flag, but is done this way so that
421 it's analogous to similar code for Mach-O on PowerPC. darwin.h
422 redefines this to 1. */
423 #define TARGET_MACHO 0
425 /* This macro is similar to `TARGET_SWITCHES' but defines names of
426 command options that have values. Its definition is an
427 initializer with a subgrouping for each command option.
429 Each subgrouping contains a string constant, that defines the
430 fixed part of the option name, and the address of a variable. The
431 variable, type `char *', is set to the variable part of the given
432 option if the fixed part matches. The actual option name is made
433 by appending `-m' to the specified name. */
434 #define TARGET_OPTIONS \
435 { { "cpu=", &ix86_cpu_string, \
436 N_("Schedule code for given CPU")}, \
437 { "fpmath=", &ix86_fpmath_string, \
438 N_("Generate floating point mathematics using given instruction set")},\
439 { "arch=", &ix86_arch_string, \
440 N_("Generate code for given CPU")}, \
441 { "regparm=", &ix86_regparm_string, \
442 N_("Number of registers used to pass integer arguments") }, \
443 { "align-loops=", &ix86_align_loops_string, \
444 N_("Loop code aligned to this power of 2") }, \
445 { "align-jumps=", &ix86_align_jumps_string, \
446 N_("Jump targets are aligned to this power of 2") }, \
447 { "align-functions=", &ix86_align_funcs_string, \
448 N_("Function starts are aligned to this power of 2") }, \
449 { "preferred-stack-boundary=", \
450 &ix86_preferred_stack_boundary_string, \
451 N_("Attempt to keep stack aligned to this power of 2") }, \
452 { "branch-cost=", &ix86_branch_cost_string, \
453 N_("Branches are this expensive (1-5, arbitrary units)") }, \
454 { "cmodel=", &ix86_cmodel_string, \
455 N_("Use given x86-64 code model") }, \
456 { "debug-arg", &ix86_debug_arg_string, \
457 "" /* Undocumented. */ }, \
458 { "debug-addr", &ix86_debug_addr_string, \
459 "" /* Undocumented. */ }, \
460 { "asm=", &ix86_asm_string, \
461 N_("Use given assembler dialect") }, \
462 { "tls-dialect=", &ix86_tls_dialect_string, \
463 N_("Use given thread-local storage dialect") }, \
467 /* Sometimes certain combinations of command options do not make
468 sense on a particular target machine. You can define a macro
469 `OVERRIDE_OPTIONS' to take account of this. This macro, if
470 defined, is executed once just after all the command options have
473 Don't use this macro to turn on various extra optimizations for
474 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
476 #define OVERRIDE_OPTIONS override_options ()
478 /* These are meant to be redefined in the host dependent files */
479 #define SUBTARGET_SWITCHES
480 #define SUBTARGET_OPTIONS
482 /* Define this to change the optimizations performed by default. */
483 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
484 optimization_options ((LEVEL), (SIZE))
486 /* Specs for the compiler proper */
489 #define CC1_CPU_SPEC "\
492 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
494 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
495 %{mpentium:-mcpu=pentium \
496 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
497 %{mpentiumpro:-mcpu=pentiumpro \
498 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
499 %{mintel-syntax:-masm=intel \
500 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
501 %{mno-intel-syntax:-masm=att \
502 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
505 /* Target CPU builtins. */
506 #define TARGET_CPU_CPP_BUILTINS() \
509 size_t arch_len = strlen (ix86_arch_string); \
510 size_t cpu_len = strlen (ix86_cpu_string); \
511 int last_arch_char = ix86_arch_string[arch_len - 1]; \
512 int last_cpu_char = ix86_cpu_string[cpu_len - 1]; \
516 builtin_assert ("cpu=x86_64"); \
517 builtin_assert ("machine=x86_64"); \
518 builtin_define ("__x86_64"); \
519 builtin_define ("__x86_64__"); \
523 builtin_assert ("cpu=i386"); \
524 builtin_assert ("machine=i386"); \
525 builtin_define_std ("i386"); \
528 /* Built-ins based on -mcpu= (or -march= if no \
531 builtin_define ("__tune_i386__"); \
532 else if (TARGET_486) \
533 builtin_define ("__tune_i486__"); \
534 else if (TARGET_PENTIUM) \
536 builtin_define ("__tune_i586__"); \
537 builtin_define ("__tune_pentium__"); \
538 if (last_cpu_char == 'x') \
539 builtin_define ("__tune_pentium_mmx__"); \
541 else if (TARGET_PENTIUMPRO) \
543 builtin_define ("__tune_i686__"); \
544 builtin_define ("__tune_pentiumpro__"); \
545 switch (last_cpu_char) \
548 builtin_define ("__tune_pentium3__"); \
551 builtin_define ("__tune_pentium2__"); \
555 else if (TARGET_K6) \
557 builtin_define ("__tune_k6__"); \
558 if (last_cpu_char == '2') \
559 builtin_define ("__tune_k6_2__"); \
560 else if (last_cpu_char == '3') \
561 builtin_define ("__tune_k6_3__"); \
563 else if (TARGET_ATHLON) \
565 builtin_define ("__tune_athlon__"); \
566 /* Only plain "athlon" lacks SSE. */ \
567 if (last_cpu_char != 'n') \
568 builtin_define ("__tune_athlon_sse__"); \
570 else if (TARGET_K8) \
571 builtin_define ("__tune_k8__"); \
572 else if (TARGET_PENTIUM4) \
573 builtin_define ("__tune_pentium4__"); \
576 builtin_define ("__MMX__"); \
578 builtin_define ("__3dNOW__"); \
579 if (TARGET_3DNOW_A) \
580 builtin_define ("__3dNOW_A__"); \
582 builtin_define ("__SSE__"); \
584 builtin_define ("__SSE2__"); \
585 if (TARGET_SSE_MATH && TARGET_SSE) \
586 builtin_define ("__SSE_MATH__"); \
587 if (TARGET_SSE_MATH && TARGET_SSE2) \
588 builtin_define ("__SSE2_MATH__"); \
590 /* Built-ins based on -march=. */ \
591 if (ix86_arch == PROCESSOR_I486) \
593 builtin_define ("__i486"); \
594 builtin_define ("__i486__"); \
596 else if (ix86_arch == PROCESSOR_PENTIUM) \
598 builtin_define ("__i586"); \
599 builtin_define ("__i586__"); \
600 builtin_define ("__pentium"); \
601 builtin_define ("__pentium__"); \
602 if (last_arch_char == 'x') \
603 builtin_define ("__pentium_mmx__"); \
605 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
607 builtin_define ("__i686"); \
608 builtin_define ("__i686__"); \
609 builtin_define ("__pentiumpro"); \
610 builtin_define ("__pentiumpro__"); \
612 else if (ix86_arch == PROCESSOR_K6) \
615 builtin_define ("__k6"); \
616 builtin_define ("__k6__"); \
617 if (last_arch_char == '2') \
618 builtin_define ("__k6_2__"); \
619 else if (last_arch_char == '3') \
620 builtin_define ("__k6_3__"); \
622 else if (ix86_arch == PROCESSOR_ATHLON) \
624 builtin_define ("__athlon"); \
625 builtin_define ("__athlon__"); \
626 /* Only plain "athlon" lacks SSE. */ \
627 if (last_arch_char != 'n') \
628 builtin_define ("__athlon_sse__"); \
630 else if (ix86_arch == PROCESSOR_K8) \
632 builtin_define ("__k8"); \
633 builtin_define ("__k8__"); \
635 else if (ix86_arch == PROCESSOR_PENTIUM4) \
637 builtin_define ("__pentium4"); \
638 builtin_define ("__pentium4__"); \
643 #define TARGET_CPU_DEFAULT_i386 0
644 #define TARGET_CPU_DEFAULT_i486 1
645 #define TARGET_CPU_DEFAULT_pentium 2
646 #define TARGET_CPU_DEFAULT_pentium_mmx 3
647 #define TARGET_CPU_DEFAULT_pentiumpro 4
648 #define TARGET_CPU_DEFAULT_pentium2 5
649 #define TARGET_CPU_DEFAULT_pentium3 6
650 #define TARGET_CPU_DEFAULT_pentium4 7
651 #define TARGET_CPU_DEFAULT_k6 8
652 #define TARGET_CPU_DEFAULT_k6_2 9
653 #define TARGET_CPU_DEFAULT_k6_3 10
654 #define TARGET_CPU_DEFAULT_athlon 11
655 #define TARGET_CPU_DEFAULT_athlon_sse 12
656 #define TARGET_CPU_DEFAULT_k8 13
658 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
659 "pentiumpro", "pentium2", "pentium3", \
660 "pentium4", "k6", "k6-2", "k6-3",\
661 "athlon", "athlon-4", "k8"}
664 #define CC1_SPEC "%(cc1_cpu) "
667 /* This macro defines names of additional specifications to put in the
668 specs that can be used in various specifications like CC1_SPEC. Its
669 definition is an initializer with a subgrouping for each command option.
671 Each subgrouping contains a string constant, that defines the
672 specification name, and a string constant that used by the GNU CC driver
675 Do not define this macro if it does not need to do anything. */
677 #ifndef SUBTARGET_EXTRA_SPECS
678 #define SUBTARGET_EXTRA_SPECS
681 #define EXTRA_SPECS \
682 { "cc1_cpu", CC1_CPU_SPEC }, \
683 SUBTARGET_EXTRA_SPECS
685 /* target machine storage layout */
687 /* Define for XFmode or TFmode extended real floating point support.
688 The XFmode is specified by i386 ABI, while TFmode may be faster
689 due to alignment and simplifications in the address calculations. */
690 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
691 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
693 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
695 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
698 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
699 FPU, assume that the fpcw is set to extended precision; when using
700 only SSE, rounding is correct; when using both SSE and the FPU,
701 the rounding precision is indeterminate, since either may be chosen
702 apparently at random. */
703 #define TARGET_FLT_EVAL_METHOD \
704 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 1 : 2)
706 #define SHORT_TYPE_SIZE 16
707 #define INT_TYPE_SIZE 32
708 #define FLOAT_TYPE_SIZE 32
709 #define LONG_TYPE_SIZE BITS_PER_WORD
710 #define MAX_WCHAR_TYPE_SIZE 32
711 #define DOUBLE_TYPE_SIZE 64
712 #define LONG_LONG_TYPE_SIZE 64
714 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
715 #define MAX_BITS_PER_WORD 64
716 #define MAX_LONG_TYPE_SIZE 64
718 #define MAX_BITS_PER_WORD 32
719 #define MAX_LONG_TYPE_SIZE 32
722 /* Define this if most significant byte of a word is the lowest numbered. */
723 /* That is true on the 80386. */
725 #define BITS_BIG_ENDIAN 0
727 /* Define this if most significant byte of a word is the lowest numbered. */
728 /* That is not true on the 80386. */
729 #define BYTES_BIG_ENDIAN 0
731 /* Define this if most significant word of a multiword number is the lowest
733 /* Not true for 80386 */
734 #define WORDS_BIG_ENDIAN 0
736 /* Width of a word, in units (bytes). */
737 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
739 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
741 #define MIN_UNITS_PER_WORD 4
744 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
745 #define PARM_BOUNDARY BITS_PER_WORD
747 /* Boundary (in *bits*) on which stack pointer should be aligned. */
748 #define STACK_BOUNDARY BITS_PER_WORD
750 /* Boundary (in *bits*) on which the stack pointer prefers to be
751 aligned; the compiler cannot rely on having this alignment. */
752 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
754 /* As of July 2001, many runtimes to not align the stack properly when
755 entering main. This causes expand_main_function to forcibly align
756 the stack, which results in aligned frames for functions called from
757 main, though it does nothing for the alignment of main itself. */
758 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
759 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
761 /* Minimum allocation boundary for the code of a function. */
762 #define FUNCTION_BOUNDARY 8
764 /* C++ stores the virtual bit in the lowest bit of function pointers. */
765 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
767 /* Alignment of field after `int : 0' in a structure. */
769 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
771 /* Minimum size in bits of the largest boundary to which any
772 and all fundamental data types supported by the hardware
773 might need to be aligned. No data type wants to be aligned
776 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
777 and Pentium Pro XFmode values at 128 bit boundaries. */
779 #define BIGGEST_ALIGNMENT 128
781 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
782 #define ALIGN_MODE_128(MODE) \
783 ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE))
785 /* The published ABIs say that doubles should be aligned on word
786 boundaries, so lower the alignment for structure fields unless
787 -malign-double is set. */
789 /* ??? Blah -- this macro is used directly by libobjc. Since it
790 supports no vector modes, cut out the complexity and fall back
791 on BIGGEST_FIELD_ALIGNMENT. */
792 #ifdef IN_TARGET_LIBS
794 #define BIGGEST_FIELD_ALIGNMENT 128
796 #define BIGGEST_FIELD_ALIGNMENT 32
799 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
800 x86_field_alignment (FIELD, COMPUTED)
803 /* If defined, a C expression to compute the alignment given to a
804 constant that is being placed in memory. EXP is the constant
805 and ALIGN is the alignment that the object would ordinarily have.
806 The value of this macro is used instead of that alignment to align
809 If this macro is not defined, then ALIGN is used.
811 The typical use of this macro is to increase alignment for string
812 constants to be word aligned so that `strcpy' calls that copy
813 constants can be done inline. */
815 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
817 /* If defined, a C expression to compute the alignment for a static
818 variable. TYPE is the data type, and ALIGN is the alignment that
819 the object would ordinarily have. The value of this macro is used
820 instead of that alignment to align the object.
822 If this macro is not defined, then ALIGN is used.
824 One use of this macro is to increase alignment of medium-size
825 data to make it all fit in fewer cache lines. Another is to
826 cause character arrays to be word-aligned so that `strcpy' calls
827 that copy constants to character arrays can be done inline. */
829 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
831 /* If defined, a C expression to compute the alignment for a local
832 variable. TYPE is the data type, and ALIGN is the alignment that
833 the object would ordinarily have. The value of this macro is used
834 instead of that alignment to align the object.
836 If this macro is not defined, then ALIGN is used.
838 One use of this macro is to increase alignment of medium-size
839 data to make it all fit in fewer cache lines. */
841 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
843 /* If defined, a C expression that gives the alignment boundary, in
844 bits, of an argument with the specified mode and type. If it is
845 not defined, `PARM_BOUNDARY' is used for all arguments. */
847 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
848 ix86_function_arg_boundary ((MODE), (TYPE))
850 /* Set this nonzero if move instructions will actually fail to work
851 when given unaligned data. */
852 #define STRICT_ALIGNMENT 0
854 /* If bit field type is int, don't let it cross an int,
855 and give entire struct the alignment of an int. */
856 /* Required on the 386 since it doesn't have bit-field insns. */
857 #define PCC_BITFIELD_TYPE_MATTERS 1
859 /* Standard register usage. */
861 /* This processor has special stack-like registers. See reg-stack.c
865 #define IS_STACK_MODE(MODE) \
866 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
869 /* Number of actual hardware registers.
870 The hardware registers are assigned numbers for the compiler
871 from 0 to just below FIRST_PSEUDO_REGISTER.
872 All registers that the compiler knows about must be given numbers,
873 even those that are not normally considered general registers.
875 In the 80386 we give the 8 general purpose registers the numbers 0-7.
876 We number the floating point registers 8-15.
877 Note that registers 0-7 can be accessed as a short or int,
878 while only 0-3 may be used with byte `mov' instructions.
880 Reg 16 does not correspond to any hardware register, but instead
881 appears in the RTL as an argument pointer prior to reload, and is
882 eliminated during reloading in favor of either the stack or frame
885 #define FIRST_PSEUDO_REGISTER 53
887 /* Number of hardware registers that go into the DWARF-2 unwind info.
888 If not defined, equals FIRST_PSEUDO_REGISTER. */
890 #define DWARF_FRAME_REGISTERS 17
892 /* 1 for registers that have pervasive standard uses
893 and are not available for the register allocator.
894 On the 80386, the stack pointer is such, as is the arg pointer.
896 The value is a mask - bit 1 is set for fixed registers
897 for 32bit target, while 2 is set for fixed registers for 64bit.
898 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
900 #define FIXED_REGISTERS \
901 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
902 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
903 /*arg,flags,fpsr,dir,frame*/ \
905 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
906 0, 0, 0, 0, 0, 0, 0, 0, \
907 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
908 0, 0, 0, 0, 0, 0, 0, 0, \
909 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
910 1, 1, 1, 1, 1, 1, 1, 1, \
911 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
912 1, 1, 1, 1, 1, 1, 1, 1}
915 /* 1 for registers not available across function calls.
916 These must include the FIXED_REGISTERS and also any
917 registers that can be used without being saved.
918 The latter must include the registers where values are returned
919 and the register where structure-value addresses are passed.
920 Aside from that, you can include as many other registers as you like.
922 The value is a mask - bit 1 is set for call used
923 for 32bit target, while 2 is set for call used for 64bit.
924 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
926 #define CALL_USED_REGISTERS \
927 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
928 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
929 /*arg,flags,fpsr,dir,frame*/ \
931 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
932 3, 3, 3, 3, 3, 3, 3, 3, \
933 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
934 3, 3, 3, 3, 3, 3, 3, 3, \
935 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
936 3, 3, 3, 3, 1, 1, 1, 1, \
937 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
938 3, 3, 3, 3, 3, 3, 3, 3} \
940 /* Order in which to allocate registers. Each register must be
941 listed once, even those in FIXED_REGISTERS. List frame pointer
942 late and fixed registers last. Note that, in general, we prefer
943 registers listed in CALL_USED_REGISTERS, keeping the others
944 available for storage of persistent values.
946 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
947 so this is just empty initializer for array. */
949 #define REG_ALLOC_ORDER \
950 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
951 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
952 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
955 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
956 to be rearranged based on a particular function. When using sse math,
957 we want to allocate SSE before x87 registers and vice vera. */
959 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
962 /* Macro to conditionally modify fixed_regs/call_used_regs. */
963 #define CONDITIONAL_REGISTER_USAGE \
966 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
968 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
969 call_used_regs[i] = (call_used_regs[i] \
970 & (TARGET_64BIT ? 2 : 1)) != 0; \
972 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
974 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
975 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
980 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
981 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
982 fixed_regs[i] = call_used_regs[i] = 1; \
987 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
988 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
989 fixed_regs[i] = call_used_regs[i] = 1; \
991 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
995 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
996 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
997 if (TEST_HARD_REG_BIT (x, i)) \
998 fixed_regs[i] = call_used_regs[i] = 1; \
1002 /* Return number of consecutive hard regs needed starting at reg REGNO
1003 to hold something of mode MODE.
1004 This is ordinarily the length in words of a value of mode MODE
1005 but can be less for certain modes in special long registers.
1007 Actually there are no two word move instructions for consecutive
1008 registers. And only registers 0-3 may have mov byte instructions
1012 #define HARD_REGNO_NREGS(REGNO, MODE) \
1013 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1014 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1015 : ((MODE) == TFmode \
1016 ? (TARGET_64BIT ? 2 : 3) \
1017 : (MODE) == TCmode \
1018 ? (TARGET_64BIT ? 4 : 6) \
1019 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1021 #define VALID_SSE2_REG_MODE(MODE) \
1022 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1023 || (MODE) == V2DImode)
1025 #define VALID_SSE_REG_MODE(MODE) \
1026 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1027 || (MODE) == SFmode \
1028 /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \
1029 || VALID_SSE2_REG_MODE (MODE) \
1030 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
1032 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1033 ((MODE) == V2SFmode || (MODE) == SFmode)
1035 #define VALID_MMX_REG_MODE(MODE) \
1036 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1037 || (MODE) == V2SImode || (MODE) == SImode)
1039 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1040 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
1041 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
1042 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1044 #define VALID_FP_MODE_P(MODE) \
1045 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
1046 || (!TARGET_64BIT && (MODE) == XFmode) \
1047 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
1048 || (!TARGET_64BIT && (MODE) == XCmode))
1050 #define VALID_INT_MODE_P(MODE) \
1051 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1052 || (MODE) == DImode \
1053 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1054 || (MODE) == CDImode \
1055 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
1057 /* Return true for modes passed in SSE registers. */
1058 #define SSE_REG_MODE_P(MODE) \
1059 ((MODE) == TImode || (MODE) == V16QImode \
1060 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1061 || (MODE) == V4SFmode || (MODE) == V4SImode)
1063 /* Return true for modes passed in MMX registers. */
1064 #define MMX_REG_MODE_P(MODE) \
1065 ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \
1066 || (MODE) == V2SFmode)
1068 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1070 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1071 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1073 /* Value is 1 if it is a good idea to tie two pseudo registers
1074 when one has mode MODE1 and one has mode MODE2.
1075 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1076 for any hard reg, then this must be 0 for correct output. */
1078 #define MODES_TIEABLE_P(MODE1, MODE2) \
1079 ((MODE1) == (MODE2) \
1080 || (((MODE1) == HImode || (MODE1) == SImode \
1081 || ((MODE1) == QImode \
1082 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1083 || ((MODE1) == DImode && TARGET_64BIT)) \
1084 && ((MODE2) == HImode || (MODE2) == SImode \
1085 || ((MODE1) == QImode \
1086 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1087 || ((MODE2) == DImode && TARGET_64BIT))))
1090 /* Specify the modes required to caller save a given hard regno.
1091 We do this on i386 to prevent flags from being saved at all.
1093 Kill any attempts to combine saving of modes. */
1095 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1096 (CC_REGNO_P (REGNO) ? VOIDmode \
1097 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1098 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1099 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1100 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1102 /* Specify the registers used for certain standard purposes.
1103 The values of these macros are register numbers. */
1105 /* on the 386 the pc register is %eip, and is not usable as a general
1106 register. The ordinary mov instructions won't work */
1107 /* #define PC_REGNUM */
1109 /* Register to use for pushing function arguments. */
1110 #define STACK_POINTER_REGNUM 7
1112 /* Base register for access to local variables of the function. */
1113 #define HARD_FRAME_POINTER_REGNUM 6
1115 /* Base register for access to local variables of the function. */
1116 #define FRAME_POINTER_REGNUM 20
1118 /* First floating point reg */
1119 #define FIRST_FLOAT_REG 8
1121 /* First & last stack-like regs */
1122 #define FIRST_STACK_REG FIRST_FLOAT_REG
1123 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1125 #define FLAGS_REG 17
1127 #define DIRFLAG_REG 19
1129 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1130 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1132 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1133 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1135 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1136 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1138 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1139 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1141 /* Value should be nonzero if functions must have frame pointers.
1142 Zero means the frame pointer need not be set up (and parms
1143 may be accessed via the stack pointer) in functions that seem suitable.
1144 This is computed in `reload', in reload1.c. */
1145 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1147 /* Override this in other tm.h files to cope with various OS losage
1148 requiring a frame pointer. */
1149 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1150 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1153 /* Make sure we can access arbitrary call frames. */
1154 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1156 /* Base register for access to arguments of the function. */
1157 #define ARG_POINTER_REGNUM 16
1159 /* Register in which static-chain is passed to a function.
1160 We do use ECX as static chain register for 32 bit ABI. On the
1161 64bit ABI, ECX is an argument register, so we use R10 instead. */
1162 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1164 /* Register to hold the addressing base for position independent
1165 code access to data items. We don't use PIC pointer for 64bit
1166 mode. Define the regnum to dummy value to prevent gcc from
1167 pessimizing code dealing with EBX.
1169 To avoid clobbering a call-saved register unnecessarily, we renumber
1170 the pic register when possible. The change is visible after the
1171 prologue has been emitted. */
1173 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1175 #define PIC_OFFSET_TABLE_REGNUM \
1176 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \
1177 : reload_completed ? REGNO (pic_offset_table_rtx) \
1178 : REAL_PIC_OFFSET_TABLE_REGNUM)
1180 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1182 /* Register in which address to store a structure value
1183 arrives in the function. On the 386, the prologue
1184 copies this from the stack to register %eax. */
1185 #define STRUCT_VALUE_INCOMING 0
1187 /* Place in which caller passes the structure value address.
1188 0 means push the value on the stack like an argument. */
1189 #define STRUCT_VALUE 0
1191 /* A C expression which can inhibit the returning of certain function
1192 values in registers, based on the type of value. A nonzero value
1193 says to return the function value in memory, just as large
1194 structures are always returned. Here TYPE will be a C expression
1195 of type `tree', representing the data type of the value.
1197 Note that values of mode `BLKmode' must be explicitly handled by
1198 this macro. Also, the option `-fpcc-struct-return' takes effect
1199 regardless of this macro. On most systems, it is possible to
1200 leave the macro undefined; this causes a default definition to be
1201 used, whose value is the constant 1 for `BLKmode' values, and 0
1204 Do not use this macro to indicate that structures and unions
1205 should always be returned in memory. You should instead use
1206 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1208 #define RETURN_IN_MEMORY(TYPE) \
1209 ix86_return_in_memory (TYPE)
1211 /* This is overriden by <cygwin.h>. */
1212 #define MS_AGGREGATE_RETURN 0
1215 /* Define the classes of registers for register constraints in the
1216 machine description. Also define ranges of constants.
1218 One of the classes must always be named ALL_REGS and include all hard regs.
1219 If there is more than one class, another class must be named NO_REGS
1220 and contain no registers.
1222 The name GENERAL_REGS must be the name of a class (or an alias for
1223 another name such as ALL_REGS). This is the class of registers
1224 that is allowed by "g" or "r" in a register constraint.
1225 Also, registers outside this class are allocated only when
1226 instructions express preferences for them.
1228 The classes must be numbered in nondecreasing order; that is,
1229 a larger-numbered class must never be contained completely
1230 in a smaller-numbered class.
1232 For any two classes, it is very desirable that there be another
1233 class that represents their union.
1235 It might seem that class BREG is unnecessary, since no useful 386
1236 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1237 and the "b" register constraint is useful in asms for syscalls.
1239 The flags and fpsr registers are in no class. */
1244 AREG, DREG, CREG, BREG, SIREG, DIREG,
1245 AD_REGS, /* %eax/%edx for DImode */
1246 Q_REGS, /* %eax %ebx %ecx %edx */
1247 NON_Q_REGS, /* %esi %edi %ebp %esp */
1248 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1249 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1250 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1251 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1261 ALL_REGS, LIM_REG_CLASSES
1264 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1266 #define INTEGER_CLASS_P(CLASS) \
1267 reg_class_subset_p ((CLASS), GENERAL_REGS)
1268 #define FLOAT_CLASS_P(CLASS) \
1269 reg_class_subset_p ((CLASS), FLOAT_REGS)
1270 #define SSE_CLASS_P(CLASS) \
1271 reg_class_subset_p ((CLASS), SSE_REGS)
1272 #define MMX_CLASS_P(CLASS) \
1273 reg_class_subset_p ((CLASS), MMX_REGS)
1274 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1275 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1276 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1277 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1278 #define MAYBE_SSE_CLASS_P(CLASS) \
1279 reg_classes_intersect_p (SSE_REGS, (CLASS))
1280 #define MAYBE_MMX_CLASS_P(CLASS) \
1281 reg_classes_intersect_p (MMX_REGS, (CLASS))
1283 #define Q_CLASS_P(CLASS) \
1284 reg_class_subset_p ((CLASS), Q_REGS)
1286 /* Give names of register classes as strings for dump file. */
1288 #define REG_CLASS_NAMES \
1290 "AREG", "DREG", "CREG", "BREG", \
1293 "Q_REGS", "NON_Q_REGS", \
1297 "FP_TOP_REG", "FP_SECOND_REG", \
1301 "FP_TOP_SSE_REGS", \
1302 "FP_SECOND_SSE_REGS", \
1306 "FLOAT_INT_SSE_REGS", \
1309 /* Define which registers fit in which classes.
1310 This is an initializer for a vector of HARD_REG_SET
1311 of length N_REG_CLASSES. */
1313 #define REG_CLASS_CONTENTS \
1315 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1316 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1317 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1318 { 0x03, 0x0 }, /* AD_REGS */ \
1319 { 0x0f, 0x0 }, /* Q_REGS */ \
1320 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1321 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1322 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1323 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1324 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1325 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1326 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1327 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1328 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1329 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1330 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1331 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1332 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1333 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1334 { 0xffffffff,0x1fffff } \
1337 /* The same information, inverted:
1338 Return the class number of the smallest class containing
1339 reg number REGNO. This could be a conditional expression
1340 or could index an array. */
1342 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1344 /* When defined, the compiler allows registers explicitly used in the
1345 rtl to be used as spill registers but prevents the compiler from
1346 extending the lifetime of these registers. */
1348 #define SMALL_REGISTER_CLASSES 1
1350 #define QI_REG_P(X) \
1351 (REG_P (X) && REGNO (X) < 4)
1353 #define GENERAL_REGNO_P(N) \
1354 ((N) < 8 || REX_INT_REGNO_P (N))
1356 #define GENERAL_REG_P(X) \
1357 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1359 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1361 #define NON_QI_REG_P(X) \
1362 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1364 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1365 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1367 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1368 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1369 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1370 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1372 #define SSE_REGNO_P(N) \
1373 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1374 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1376 #define REX_SSE_REGNO_P(N) \
1377 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
1379 #define SSE_REGNO(N) \
1380 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1381 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1383 #define SSE_FLOAT_MODE_P(MODE) \
1384 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1386 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1387 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1389 #define STACK_REG_P(XOP) \
1391 REGNO (XOP) >= FIRST_STACK_REG && \
1392 REGNO (XOP) <= LAST_STACK_REG)
1394 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1396 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1398 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1399 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1401 /* Indicate whether hard register numbered REG_NO should be converted
1403 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1404 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1406 /* The class value for index registers, and the one for base regs. */
1408 #define INDEX_REG_CLASS INDEX_REGS
1409 #define BASE_REG_CLASS GENERAL_REGS
1411 /* Get reg_class from a letter such as appears in the machine description. */
1413 #define REG_CLASS_FROM_LETTER(C) \
1414 ((C) == 'r' ? GENERAL_REGS : \
1415 (C) == 'R' ? LEGACY_REGS : \
1416 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1417 (C) == 'Q' ? Q_REGS : \
1418 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1421 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1424 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1427 (C) == 'a' ? AREG : \
1428 (C) == 'b' ? BREG : \
1429 (C) == 'c' ? CREG : \
1430 (C) == 'd' ? DREG : \
1431 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1432 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1433 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1434 (C) == 'A' ? AD_REGS : \
1435 (C) == 'D' ? DIREG : \
1436 (C) == 'S' ? SIREG : NO_REGS)
1438 /* The letters I, J, K, L and M in a register constraint string
1439 can be used to stand for particular ranges of immediate operands.
1440 This macro defines what the ranges are.
1441 C is the letter, and VALUE is a constant value.
1442 Return 1 if VALUE is in the range specified by C.
1444 I is for non-DImode shifts.
1445 J is for DImode shifts.
1446 K is for signed imm8 operands.
1447 L is for andsi as zero-extending move.
1448 M is for shifts that can be executed by the "lea" opcode.
1449 N is for immediate operands for out/in instructions (0-255)
1452 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1453 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1454 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1455 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1456 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1457 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1458 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1461 /* Similar, but for floating constants, and defining letters G and H.
1462 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1463 TARGET_387 isn't set, because the stack register converter may need to
1464 load 0.0 into the function value register. */
1466 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1467 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1470 /* A C expression that defines the optional machine-dependent
1471 constraint letters that can be used to segregate specific types of
1472 operands, usually memory references, for the target machine. Any
1473 letter that is not elsewhere defined and not matched by
1474 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1477 If it is required for a particular target machine, it should
1478 return 1 if VALUE corresponds to the operand type represented by
1479 the constraint letter C. If C is not defined as an extra
1480 constraint, the value returned should be 0 regardless of VALUE. */
1482 #define EXTRA_CONSTRAINT(VALUE, D) \
1483 ((D) == 'e' ? x86_64_sign_extended_value (VALUE) \
1484 : (D) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1485 : (D) == 'C' ? standard_sse_constant_p (VALUE) \
1488 /* Place additional restrictions on the register class to use when it
1489 is necessary to be able to hold a value of mode MODE in a reload
1490 register for which class CLASS would ordinarily be used. */
1492 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1493 ((MODE) == QImode && !TARGET_64BIT \
1494 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1495 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1498 /* Given an rtx X being reloaded into a reg required to be
1499 in class CLASS, return the class of reg to actually use.
1500 In general this is just CLASS; but on some machines
1501 in some cases it is preferable to use a more restrictive class.
1502 On the 80386 series, we prevent floating constants from being
1503 reloaded into floating registers (since no move-insn can do that)
1504 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1506 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1507 QImode must go into class Q_REGS.
1508 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1509 movdf to do mem-to-mem moves through integer regs. */
1511 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1512 ix86_preferred_reload_class ((X), (CLASS))
1514 /* If we are copying between general and FP registers, we need a memory
1515 location. The same is true for SSE and MMX registers. */
1516 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1517 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1519 /* QImode spills from non-QI registers need a scratch. This does not
1520 happen often -- the only example so far requires an uninitialized
1523 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1524 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1525 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1528 /* Return the maximum number of consecutive registers
1529 needed to represent mode MODE in a register of class CLASS. */
1530 /* On the 80386, this is the size of MODE in words,
1531 except in the FP regs, where a single reg is always enough.
1532 The TFmodes are really just 80bit values, so we use only 3 registers
1533 to hold them, instead of 4, as the size would suggest.
1535 #define CLASS_MAX_NREGS(CLASS, MODE) \
1536 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1537 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1538 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1539 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1541 /* A C expression whose value is nonzero if pseudos that have been
1542 assigned to registers of class CLASS would likely be spilled
1543 because registers of CLASS are needed for spill registers.
1545 The default value of this macro returns 1 if CLASS has exactly one
1546 register and zero otherwise. On most machines, this default
1547 should be used. Only define this macro to some other expression
1548 if pseudo allocated by `local-alloc.c' end up in memory because
1549 their hard registers were needed for spill registers. If this
1550 macro returns nonzero for those classes, those pseudos will only
1551 be allocated by `global.c', which knows how to reallocate the
1552 pseudo to another register. If there would not be another
1553 register available for reallocation, you should not change the
1554 definition of this macro since the only effect of such a
1555 definition would be to slow down register allocation. */
1557 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1558 (((CLASS) == AREG) \
1559 || ((CLASS) == DREG) \
1560 || ((CLASS) == CREG) \
1561 || ((CLASS) == BREG) \
1562 || ((CLASS) == AD_REGS) \
1563 || ((CLASS) == SIREG) \
1564 || ((CLASS) == DIREG))
1566 /* Return a class of registers that cannot change FROM mode to TO mode.
1568 x87 registers can't do subreg as all values are reformated to extended
1569 precision. XMM registers does not support with nonzero offsets equal
1570 to 4, 8 and 12 otherwise valid for integer registers. Since we can't
1571 determine these, prohibit all nonparadoxical subregs changing size. */
1573 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1574 (GET_MODE_SIZE (TO) < GET_MODE_SIZE (FROM) \
1575 ? reg_classes_intersect_p (FLOAT_SSE_REGS, (CLASS)) \
1576 || MAYBE_MMX_CLASS_P (CLASS) \
1577 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1578 ? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0)
1580 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1581 to automatically clobber for all asms.
1583 We do this in the new i386 backend to maintain source compatibility
1584 with the old cc0-based compiler. */
1586 #define MD_ASM_CLOBBERS(CLOBBERS) \
1588 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1590 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1592 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1596 /* Stack layout; function entry, exit and calling. */
1598 /* Define this if pushing a word on the stack
1599 makes the stack pointer a smaller address. */
1600 #define STACK_GROWS_DOWNWARD
1602 /* Define this if the nominal address of the stack frame
1603 is at the high-address end of the local variables;
1604 that is, each additional local variable allocated
1605 goes at a more negative offset in the frame. */
1606 #define FRAME_GROWS_DOWNWARD
1608 /* Offset within stack frame to start allocating local variables at.
1609 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1610 first local allocated. Otherwise, it is the offset to the BEGINNING
1611 of the first local allocated. */
1612 #define STARTING_FRAME_OFFSET 0
1614 /* If we generate an insn to push BYTES bytes,
1615 this says how many the stack pointer really advances by.
1616 On 386 pushw decrements by exactly 2 no matter what the position was.
1617 On the 386 there is no pushb; we use pushw instead, and this
1618 has the effect of rounding up to 2.
1620 For 64bit ABI we round up to 8 bytes.
1623 #define PUSH_ROUNDING(BYTES) \
1625 ? (((BYTES) + 7) & (-8)) \
1626 : (((BYTES) + 1) & (-2)))
1628 /* If defined, the maximum amount of space required for outgoing arguments will
1629 be computed and placed into the variable
1630 `current_function_outgoing_args_size'. No space will be pushed onto the
1631 stack for each call; instead, the function prologue should increase the stack
1632 frame size by this amount. */
1634 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1636 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1637 instructions to pass outgoing arguments. */
1639 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1641 /* We want the stack and args grow in opposite directions, even if
1643 #define PUSH_ARGS_REVERSED 1
1645 /* Offset of first parameter from the argument pointer register value. */
1646 #define FIRST_PARM_OFFSET(FNDECL) 0
1648 /* Define this macro if functions should assume that stack space has been
1649 allocated for arguments even when their values are passed in registers.
1651 The value of this macro is the size, in bytes, of the area reserved for
1652 arguments passed in registers for the function represented by FNDECL.
1654 This space can be allocated by the caller, or be a part of the
1655 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1657 #define REG_PARM_STACK_SPACE(FNDECL) 0
1659 /* Define as a C expression that evaluates to nonzero if we do not know how
1660 to pass TYPE solely in registers. The file expr.h defines a
1661 definition that is usually appropriate, refer to expr.h for additional
1662 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1663 computed in the stack and then loaded into a register. */
1664 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1666 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1667 || TREE_ADDRESSABLE (TYPE) \
1668 || ((MODE) == TImode) \
1669 || ((MODE) == BLKmode \
1671 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1672 && 0 == (int_size_in_bytes (TYPE) \
1673 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1674 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1675 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1677 /* Value is the number of bytes of arguments automatically
1678 popped when returning from a subroutine call.
1679 FUNDECL is the declaration node of the function (as a tree),
1680 FUNTYPE is the data type of the function (as a tree),
1681 or for a library call it is an identifier node for the subroutine name.
1682 SIZE is the number of bytes of arguments passed on the stack.
1684 On the 80386, the RTD insn may be used to pop them if the number
1685 of args is fixed, but if the number is variable then the caller
1686 must pop them all. RTD can't be used for library calls now
1687 because the library is compiled with the Unix compiler.
1688 Use of RTD is a selectable option, since it is incompatible with
1689 standard Unix calling sequences. If the option is not selected,
1690 the caller must always pop the args.
1692 The attribute stdcall is equivalent to RTD on a per module basis. */
1694 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1695 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1697 /* Define how to find the value returned by a function.
1698 VALTYPE is the data type of the value (as a tree).
1699 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1700 otherwise, FUNC is 0. */
1701 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1702 ix86_function_value (VALTYPE)
1704 #define FUNCTION_VALUE_REGNO_P(N) \
1705 ix86_function_value_regno_p (N)
1707 /* Define how to find the value returned by a library function
1708 assuming the value has mode MODE. */
1710 #define LIBCALL_VALUE(MODE) \
1711 ix86_libcall_value (MODE)
1713 /* Define the size of the result block used for communication between
1714 untyped_call and untyped_return. The block contains a DImode value
1715 followed by the block used by fnsave and frstor. */
1717 #define APPLY_RESULT_SIZE (8+108)
1719 /* 1 if N is a possible register number for function argument passing. */
1720 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1722 /* Define a data type for recording info about an argument list
1723 during the scan of that argument list. This data type should
1724 hold all necessary information about the function itself
1725 and about the args processed so far, enough to enable macros
1726 such as FUNCTION_ARG to determine where the next arg should go. */
1728 typedef struct ix86_args {
1729 int words; /* # words passed so far */
1730 int nregs; /* # registers available for passing */
1731 int regno; /* next available register number */
1732 int fastcall; /* fastcall calling convention is used */
1733 int sse_words; /* # sse words passed so far */
1734 int sse_nregs; /* # sse registers available for passing */
1735 int sse_regno; /* next available sse register number */
1736 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1739 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1740 for a call to a function whose data type is FNTYPE.
1741 For a library call, FNTYPE is 0. */
1743 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1744 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
1746 /* Update the data in CUM to advance over an argument
1747 of mode MODE and data type TYPE.
1748 (TYPE is null for libcalls where that information may not be available.) */
1750 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1751 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1753 /* Define where to put the arguments to a function.
1754 Value is zero to push the argument on the stack,
1755 or a hard register in which to store the argument.
1757 MODE is the argument's machine mode.
1758 TYPE is the data type of the argument (as a tree).
1759 This is null for libcalls where that information may
1761 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1762 the preceding args and about the function being called.
1763 NAMED is nonzero if this argument is a named parameter
1764 (otherwise it is an extra parameter matching an ellipsis). */
1766 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1767 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1769 /* For an arg passed partly in registers and partly in memory,
1770 this is the number of registers used.
1771 For args passed entirely in registers or entirely in memory, zero. */
1773 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1775 /* A C expression that indicates when an argument must be passed by
1776 reference. If nonzero for an argument, a copy of that argument is
1777 made in memory and a pointer to the argument is passed instead of
1778 the argument itself. The pointer is passed in whatever way is
1779 appropriate for passing a pointer to that type. */
1781 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1782 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1784 /* Perform any needed actions needed for a function that is receiving a
1785 variable number of arguments.
1789 MODE and TYPE are the mode and type of the current parameter.
1791 PRETEND_SIZE is a variable that should be set to the amount of stack
1792 that must be pushed by the prolog to pretend that our caller pushed
1795 Normally, this macro will push all remaining incoming registers on the
1796 stack and set PRETEND_SIZE to the length of the registers pushed. */
1798 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1799 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1802 /* Define the `__builtin_va_list' type for the ABI. */
1803 #define BUILD_VA_LIST_TYPE(VALIST) \
1804 ((VALIST) = ix86_build_va_list ())
1806 /* Implement `va_start' for varargs and stdarg. */
1807 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1808 ix86_va_start (VALIST, NEXTARG)
1810 /* Implement `va_arg'. */
1811 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1812 ix86_va_arg ((VALIST), (TYPE))
1814 /* This macro is invoked at the end of compilation. It is used here to
1815 output code for -fpic that will load the return address into %ebx. */
1818 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1820 /* Output assembler code to FILE to increment profiler label # LABELNO
1821 for profiling a function entry. */
1823 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1825 #define MCOUNT_NAME "_mcount"
1827 #define PROFILE_COUNT_REGISTER "edx"
1829 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1830 the stack pointer does not matter. The value is tested only in
1831 functions that have frame pointers.
1832 No definition is equivalent to always zero. */
1833 /* Note on the 386 it might be more efficient not to define this since
1834 we have to restore it ourselves from the frame pointer, in order to
1837 #define EXIT_IGNORE_STACK 1
1839 /* Output assembler code for a block containing the constant parts
1840 of a trampoline, leaving space for the variable parts. */
1842 /* On the 386, the trampoline contains two instructions:
1845 The trampoline is generated entirely at runtime. The operand of JMP
1846 is the address of FUNCTION relative to the instruction following the
1847 JMP (which is 5 bytes long). */
1849 /* Length in units of the trampoline for entering a nested function. */
1851 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1853 /* Emit RTL insns to initialize the variable parts of a trampoline.
1854 FNADDR is an RTX for the address of the function's pure code.
1855 CXT is an RTX for the static chain value for the function. */
1857 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1858 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1860 /* Definitions for register eliminations.
1862 This is an array of structures. Each structure initializes one pair
1863 of eliminable registers. The "from" register number is given first,
1864 followed by "to". Eliminations of the same "from" register are listed
1865 in order of preference.
1867 There are two registers that can always be eliminated on the i386.
1868 The frame pointer and the arg pointer can be replaced by either the
1869 hard frame pointer or to the stack pointer, depending upon the
1870 circumstances. The hard frame pointer is not used before reload and
1871 so it is not eligible for elimination. */
1873 #define ELIMINABLE_REGS \
1874 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1875 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1876 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1877 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1879 /* Given FROM and TO register numbers, say whether this elimination is
1880 allowed. Frame pointer elimination is automatically handled.
1882 All other eliminations are valid. */
1884 #define CAN_ELIMINATE(FROM, TO) \
1885 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1887 /* Define the offset between two registers, one to be eliminated, and the other
1888 its replacement, at the start of a routine. */
1890 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1891 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1893 /* Addressing modes, and classification of registers for them. */
1895 /* Macros to check register numbers against specific register classes. */
1897 /* These assume that REGNO is a hard or pseudo reg number.
1898 They give nonzero only if REGNO is a hard reg of the suitable class
1899 or a pseudo reg currently allocated to a suitable hard reg.
1900 Since they use reg_renumber, they are safe only once reg_renumber
1901 has been allocated, which happens in local-alloc.c. */
1903 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1904 ((REGNO) < STACK_POINTER_REGNUM \
1905 || (REGNO >= FIRST_REX_INT_REG \
1906 && (REGNO) <= LAST_REX_INT_REG) \
1907 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1908 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1909 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1911 #define REGNO_OK_FOR_BASE_P(REGNO) \
1912 ((REGNO) <= STACK_POINTER_REGNUM \
1913 || (REGNO) == ARG_POINTER_REGNUM \
1914 || (REGNO) == FRAME_POINTER_REGNUM \
1915 || (REGNO >= FIRST_REX_INT_REG \
1916 && (REGNO) <= LAST_REX_INT_REG) \
1917 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1918 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1919 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1921 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1922 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1923 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1924 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1926 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1927 and check its validity for a certain class.
1928 We have two alternate definitions for each of them.
1929 The usual definition accepts all pseudo regs; the other rejects
1930 them unless they have been allocated suitable hard regs.
1931 The symbol REG_OK_STRICT causes the latter definition to be used.
1933 Most source files want to accept pseudo regs in the hope that
1934 they will get allocated to the class that the insn wants them to be in.
1935 Source files for reload pass need to be strict.
1936 After reload, it makes no difference, since pseudo regs have
1937 been eliminated by then. */
1940 /* Non strict versions, pseudos are ok */
1941 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1942 (REGNO (X) < STACK_POINTER_REGNUM \
1943 || (REGNO (X) >= FIRST_REX_INT_REG \
1944 && REGNO (X) <= LAST_REX_INT_REG) \
1945 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1947 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1948 (REGNO (X) <= STACK_POINTER_REGNUM \
1949 || REGNO (X) == ARG_POINTER_REGNUM \
1950 || REGNO (X) == FRAME_POINTER_REGNUM \
1951 || (REGNO (X) >= FIRST_REX_INT_REG \
1952 && REGNO (X) <= LAST_REX_INT_REG) \
1953 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1955 /* Strict versions, hard registers only */
1956 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1957 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1959 #ifndef REG_OK_STRICT
1960 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1961 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1964 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1965 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1968 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1969 that is a valid memory address for an instruction.
1970 The MODE argument is the machine mode for the MEM expression
1971 that wants to use this address.
1973 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1974 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1976 See legitimize_pic_address in i386.c for details as to what
1977 constitutes a legitimate address when -fpic is used. */
1979 #define MAX_REGS_PER_ADDRESS 2
1981 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1983 /* Nonzero if the constant value X is a legitimate general operand.
1984 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1986 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1988 #ifdef REG_OK_STRICT
1989 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1991 if (legitimate_address_p ((MODE), (X), 1)) \
1996 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1998 if (legitimate_address_p ((MODE), (X), 0)) \
2004 /* If defined, a C expression to determine the base term of address X.
2005 This macro is used in only one place: `find_base_term' in alias.c.
2007 It is always safe for this macro to not be defined. It exists so
2008 that alias analysis can understand machine-dependent addresses.
2010 The typical use of this macro is to handle addresses containing
2011 a label_ref or symbol_ref within an UNSPEC. */
2013 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
2015 /* Try machine-dependent ways of modifying an illegitimate address
2016 to be legitimate. If we find one, return the new, valid address.
2017 This macro is used in only one place: `memory_address' in explow.c.
2019 OLDX is the address as it was before break_out_memory_refs was called.
2020 In some cases it is useful to look at this to decide what needs to be done.
2022 MODE and WIN are passed so that this macro can use
2023 GO_IF_LEGITIMATE_ADDRESS.
2025 It is always safe for this macro to do nothing. It exists to recognize
2026 opportunities to optimize the output.
2028 For the 80386, we handle X+REG by loading X into a register R and
2029 using R+REG. R will go in a general reg and indexing will be used.
2030 However, if REG is a broken-out memory address or multiplication,
2031 nothing needs to be done because REG can certainly go in a general reg.
2033 When -fpic is used, special handling is needed for symbolic references.
2034 See comments by legitimize_pic_address in i386.c for details. */
2036 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2038 (X) = legitimize_address ((X), (OLDX), (MODE)); \
2039 if (memory_address_p ((MODE), (X))) \
2043 #define REWRITE_ADDRESS(X) rewrite_address (X)
2045 /* Nonzero if the constant value X is a legitimate general operand
2046 when generating PIC code. It is given that flag_pic is on and
2047 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2049 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
2051 #define SYMBOLIC_CONST(X) \
2052 (GET_CODE (X) == SYMBOL_REF \
2053 || GET_CODE (X) == LABEL_REF \
2054 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2056 /* Go to LABEL if ADDR (a legitimate address expression)
2057 has an effect that depends on the machine mode it is used for.
2058 On the 80386, only postdecrement and postincrement address depend thus
2059 (the amount of decrement or increment being the length of the operand). */
2060 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2062 if (GET_CODE (ADDR) == POST_INC \
2063 || GET_CODE (ADDR) == POST_DEC) \
2067 /* Codes for all the SSE/MMX builtins. */
2079 IX86_BUILTIN_CMPEQPS,
2080 IX86_BUILTIN_CMPLTPS,
2081 IX86_BUILTIN_CMPLEPS,
2082 IX86_BUILTIN_CMPGTPS,
2083 IX86_BUILTIN_CMPGEPS,
2084 IX86_BUILTIN_CMPNEQPS,
2085 IX86_BUILTIN_CMPNLTPS,
2086 IX86_BUILTIN_CMPNLEPS,
2087 IX86_BUILTIN_CMPNGTPS,
2088 IX86_BUILTIN_CMPNGEPS,
2089 IX86_BUILTIN_CMPORDPS,
2090 IX86_BUILTIN_CMPUNORDPS,
2091 IX86_BUILTIN_CMPNEPS,
2092 IX86_BUILTIN_CMPEQSS,
2093 IX86_BUILTIN_CMPLTSS,
2094 IX86_BUILTIN_CMPLESS,
2095 IX86_BUILTIN_CMPNEQSS,
2096 IX86_BUILTIN_CMPNLTSS,
2097 IX86_BUILTIN_CMPNLESS,
2098 IX86_BUILTIN_CMPORDSS,
2099 IX86_BUILTIN_CMPUNORDSS,
2100 IX86_BUILTIN_CMPNESS,
2102 IX86_BUILTIN_COMIEQSS,
2103 IX86_BUILTIN_COMILTSS,
2104 IX86_BUILTIN_COMILESS,
2105 IX86_BUILTIN_COMIGTSS,
2106 IX86_BUILTIN_COMIGESS,
2107 IX86_BUILTIN_COMINEQSS,
2108 IX86_BUILTIN_UCOMIEQSS,
2109 IX86_BUILTIN_UCOMILTSS,
2110 IX86_BUILTIN_UCOMILESS,
2111 IX86_BUILTIN_UCOMIGTSS,
2112 IX86_BUILTIN_UCOMIGESS,
2113 IX86_BUILTIN_UCOMINEQSS,
2115 IX86_BUILTIN_CVTPI2PS,
2116 IX86_BUILTIN_CVTPS2PI,
2117 IX86_BUILTIN_CVTSI2SS,
2118 IX86_BUILTIN_CVTSS2SI,
2119 IX86_BUILTIN_CVTTPS2PI,
2120 IX86_BUILTIN_CVTTSS2SI,
2127 IX86_BUILTIN_LOADAPS,
2128 IX86_BUILTIN_LOADUPS,
2129 IX86_BUILTIN_STOREAPS,
2130 IX86_BUILTIN_STOREUPS,
2131 IX86_BUILTIN_LOADSS,
2132 IX86_BUILTIN_STORESS,
2135 IX86_BUILTIN_MOVHLPS,
2136 IX86_BUILTIN_MOVLHPS,
2137 IX86_BUILTIN_LOADHPS,
2138 IX86_BUILTIN_LOADLPS,
2139 IX86_BUILTIN_STOREHPS,
2140 IX86_BUILTIN_STORELPS,
2142 IX86_BUILTIN_MASKMOVQ,
2143 IX86_BUILTIN_MOVMSKPS,
2144 IX86_BUILTIN_PMOVMSKB,
2146 IX86_BUILTIN_MOVNTPS,
2147 IX86_BUILTIN_MOVNTQ,
2149 IX86_BUILTIN_LOADDQA,
2150 IX86_BUILTIN_LOADDQU,
2151 IX86_BUILTIN_STOREDQA,
2152 IX86_BUILTIN_STOREDQU,
2155 IX86_BUILTIN_STORED,
2159 IX86_BUILTIN_PACKSSWB,
2160 IX86_BUILTIN_PACKSSDW,
2161 IX86_BUILTIN_PACKUSWB,
2166 IX86_BUILTIN_PADDSB,
2167 IX86_BUILTIN_PADDSW,
2168 IX86_BUILTIN_PADDUSB,
2169 IX86_BUILTIN_PADDUSW,
2173 IX86_BUILTIN_PSUBSB,
2174 IX86_BUILTIN_PSUBSW,
2175 IX86_BUILTIN_PSUBUSB,
2176 IX86_BUILTIN_PSUBUSW,
2186 IX86_BUILTIN_PCMPEQB,
2187 IX86_BUILTIN_PCMPEQW,
2188 IX86_BUILTIN_PCMPEQD,
2189 IX86_BUILTIN_PCMPGTB,
2190 IX86_BUILTIN_PCMPGTW,
2191 IX86_BUILTIN_PCMPGTD,
2193 IX86_BUILTIN_PEXTRW,
2194 IX86_BUILTIN_PINSRW,
2196 IX86_BUILTIN_PMADDWD,
2198 IX86_BUILTIN_PMAXSW,
2199 IX86_BUILTIN_PMAXUB,
2200 IX86_BUILTIN_PMINSW,
2201 IX86_BUILTIN_PMINUB,
2203 IX86_BUILTIN_PMULHUW,
2204 IX86_BUILTIN_PMULHW,
2205 IX86_BUILTIN_PMULLW,
2207 IX86_BUILTIN_PSADBW,
2208 IX86_BUILTIN_PSHUFW,
2218 IX86_BUILTIN_PSLLWI,
2219 IX86_BUILTIN_PSLLDI,
2220 IX86_BUILTIN_PSLLQI,
2221 IX86_BUILTIN_PSRAWI,
2222 IX86_BUILTIN_PSRADI,
2223 IX86_BUILTIN_PSRLWI,
2224 IX86_BUILTIN_PSRLDI,
2225 IX86_BUILTIN_PSRLQI,
2227 IX86_BUILTIN_PUNPCKHBW,
2228 IX86_BUILTIN_PUNPCKHWD,
2229 IX86_BUILTIN_PUNPCKHDQ,
2230 IX86_BUILTIN_PUNPCKLBW,
2231 IX86_BUILTIN_PUNPCKLWD,
2232 IX86_BUILTIN_PUNPCKLDQ,
2234 IX86_BUILTIN_SHUFPS,
2238 IX86_BUILTIN_RSQRTPS,
2239 IX86_BUILTIN_RSQRTSS,
2240 IX86_BUILTIN_SQRTPS,
2241 IX86_BUILTIN_SQRTSS,
2243 IX86_BUILTIN_UNPCKHPS,
2244 IX86_BUILTIN_UNPCKLPS,
2247 IX86_BUILTIN_ANDNPS,
2252 IX86_BUILTIN_LDMXCSR,
2253 IX86_BUILTIN_STMXCSR,
2254 IX86_BUILTIN_SFENCE,
2256 /* 3DNow! Original */
2258 IX86_BUILTIN_PAVGUSB,
2262 IX86_BUILTIN_PFCMPEQ,
2263 IX86_BUILTIN_PFCMPGE,
2264 IX86_BUILTIN_PFCMPGT,
2269 IX86_BUILTIN_PFRCPIT1,
2270 IX86_BUILTIN_PFRCPIT2,
2271 IX86_BUILTIN_PFRSQIT1,
2272 IX86_BUILTIN_PFRSQRT,
2274 IX86_BUILTIN_PFSUBR,
2276 IX86_BUILTIN_PMULHRW,
2278 /* 3DNow! Athlon Extensions */
2280 IX86_BUILTIN_PFNACC,
2281 IX86_BUILTIN_PFPNACC,
2283 IX86_BUILTIN_PSWAPDSI,
2284 IX86_BUILTIN_PSWAPDSF,
2286 IX86_BUILTIN_SSE_ZERO,
2287 IX86_BUILTIN_MMX_ZERO,
2299 IX86_BUILTIN_CMPEQPD,
2300 IX86_BUILTIN_CMPLTPD,
2301 IX86_BUILTIN_CMPLEPD,
2302 IX86_BUILTIN_CMPGTPD,
2303 IX86_BUILTIN_CMPGEPD,
2304 IX86_BUILTIN_CMPNEQPD,
2305 IX86_BUILTIN_CMPNLTPD,
2306 IX86_BUILTIN_CMPNLEPD,
2307 IX86_BUILTIN_CMPNGTPD,
2308 IX86_BUILTIN_CMPNGEPD,
2309 IX86_BUILTIN_CMPORDPD,
2310 IX86_BUILTIN_CMPUNORDPD,
2311 IX86_BUILTIN_CMPNEPD,
2312 IX86_BUILTIN_CMPEQSD,
2313 IX86_BUILTIN_CMPLTSD,
2314 IX86_BUILTIN_CMPLESD,
2315 IX86_BUILTIN_CMPNEQSD,
2316 IX86_BUILTIN_CMPNLTSD,
2317 IX86_BUILTIN_CMPNLESD,
2318 IX86_BUILTIN_CMPORDSD,
2319 IX86_BUILTIN_CMPUNORDSD,
2320 IX86_BUILTIN_CMPNESD,
2322 IX86_BUILTIN_COMIEQSD,
2323 IX86_BUILTIN_COMILTSD,
2324 IX86_BUILTIN_COMILESD,
2325 IX86_BUILTIN_COMIGTSD,
2326 IX86_BUILTIN_COMIGESD,
2327 IX86_BUILTIN_COMINEQSD,
2328 IX86_BUILTIN_UCOMIEQSD,
2329 IX86_BUILTIN_UCOMILTSD,
2330 IX86_BUILTIN_UCOMILESD,
2331 IX86_BUILTIN_UCOMIGTSD,
2332 IX86_BUILTIN_UCOMIGESD,
2333 IX86_BUILTIN_UCOMINEQSD,
2341 IX86_BUILTIN_ANDNPD,
2345 IX86_BUILTIN_SQRTPD,
2346 IX86_BUILTIN_SQRTSD,
2348 IX86_BUILTIN_UNPCKHPD,
2349 IX86_BUILTIN_UNPCKLPD,
2351 IX86_BUILTIN_SHUFPD,
2353 IX86_BUILTIN_LOADAPD,
2354 IX86_BUILTIN_LOADUPD,
2355 IX86_BUILTIN_STOREAPD,
2356 IX86_BUILTIN_STOREUPD,
2357 IX86_BUILTIN_LOADSD,
2358 IX86_BUILTIN_STORESD,
2361 IX86_BUILTIN_LOADHPD,
2362 IX86_BUILTIN_LOADLPD,
2363 IX86_BUILTIN_STOREHPD,
2364 IX86_BUILTIN_STORELPD,
2366 IX86_BUILTIN_CVTDQ2PD,
2367 IX86_BUILTIN_CVTDQ2PS,
2369 IX86_BUILTIN_CVTPD2DQ,
2370 IX86_BUILTIN_CVTPD2PI,
2371 IX86_BUILTIN_CVTPD2PS,
2372 IX86_BUILTIN_CVTTPD2DQ,
2373 IX86_BUILTIN_CVTTPD2PI,
2375 IX86_BUILTIN_CVTPI2PD,
2376 IX86_BUILTIN_CVTSI2SD,
2378 IX86_BUILTIN_CVTSD2SI,
2379 IX86_BUILTIN_CVTSD2SS,
2380 IX86_BUILTIN_CVTSS2SD,
2381 IX86_BUILTIN_CVTTSD2SI,
2383 IX86_BUILTIN_CVTPS2DQ,
2384 IX86_BUILTIN_CVTPS2PD,
2385 IX86_BUILTIN_CVTTPS2DQ,
2387 IX86_BUILTIN_MOVNTI,
2388 IX86_BUILTIN_MOVNTPD,
2389 IX86_BUILTIN_MOVNTDQ,
2391 IX86_BUILTIN_SETPD1,
2394 IX86_BUILTIN_SETRPD,
2395 IX86_BUILTIN_LOADPD1,
2396 IX86_BUILTIN_LOADRPD,
2397 IX86_BUILTIN_STOREPD1,
2398 IX86_BUILTIN_STORERPD,
2401 IX86_BUILTIN_MASKMOVDQU,
2402 IX86_BUILTIN_MOVMSKPD,
2403 IX86_BUILTIN_PMOVMSKB128,
2404 IX86_BUILTIN_MOVQ2DQ,
2405 IX86_BUILTIN_MOVDQ2Q,
2407 IX86_BUILTIN_PACKSSWB128,
2408 IX86_BUILTIN_PACKSSDW128,
2409 IX86_BUILTIN_PACKUSWB128,
2411 IX86_BUILTIN_PADDB128,
2412 IX86_BUILTIN_PADDW128,
2413 IX86_BUILTIN_PADDD128,
2414 IX86_BUILTIN_PADDQ128,
2415 IX86_BUILTIN_PADDSB128,
2416 IX86_BUILTIN_PADDSW128,
2417 IX86_BUILTIN_PADDUSB128,
2418 IX86_BUILTIN_PADDUSW128,
2419 IX86_BUILTIN_PSUBB128,
2420 IX86_BUILTIN_PSUBW128,
2421 IX86_BUILTIN_PSUBD128,
2422 IX86_BUILTIN_PSUBQ128,
2423 IX86_BUILTIN_PSUBSB128,
2424 IX86_BUILTIN_PSUBSW128,
2425 IX86_BUILTIN_PSUBUSB128,
2426 IX86_BUILTIN_PSUBUSW128,
2428 IX86_BUILTIN_PAND128,
2429 IX86_BUILTIN_PANDN128,
2430 IX86_BUILTIN_POR128,
2431 IX86_BUILTIN_PXOR128,
2433 IX86_BUILTIN_PAVGB128,
2434 IX86_BUILTIN_PAVGW128,
2436 IX86_BUILTIN_PCMPEQB128,
2437 IX86_BUILTIN_PCMPEQW128,
2438 IX86_BUILTIN_PCMPEQD128,
2439 IX86_BUILTIN_PCMPGTB128,
2440 IX86_BUILTIN_PCMPGTW128,
2441 IX86_BUILTIN_PCMPGTD128,
2443 IX86_BUILTIN_PEXTRW128,
2444 IX86_BUILTIN_PINSRW128,
2446 IX86_BUILTIN_PMADDWD128,
2448 IX86_BUILTIN_PMAXSW128,
2449 IX86_BUILTIN_PMAXUB128,
2450 IX86_BUILTIN_PMINSW128,
2451 IX86_BUILTIN_PMINUB128,
2453 IX86_BUILTIN_PMULUDQ,
2454 IX86_BUILTIN_PMULUDQ128,
2455 IX86_BUILTIN_PMULHUW128,
2456 IX86_BUILTIN_PMULHW128,
2457 IX86_BUILTIN_PMULLW128,
2459 IX86_BUILTIN_PSADBW128,
2460 IX86_BUILTIN_PSHUFHW,
2461 IX86_BUILTIN_PSHUFLW,
2462 IX86_BUILTIN_PSHUFD,
2464 IX86_BUILTIN_PSLLW128,
2465 IX86_BUILTIN_PSLLD128,
2466 IX86_BUILTIN_PSLLQ128,
2467 IX86_BUILTIN_PSRAW128,
2468 IX86_BUILTIN_PSRAD128,
2469 IX86_BUILTIN_PSRLW128,
2470 IX86_BUILTIN_PSRLD128,
2471 IX86_BUILTIN_PSRLQ128,
2472 IX86_BUILTIN_PSLLDQI128,
2473 IX86_BUILTIN_PSLLWI128,
2474 IX86_BUILTIN_PSLLDI128,
2475 IX86_BUILTIN_PSLLQI128,
2476 IX86_BUILTIN_PSRAWI128,
2477 IX86_BUILTIN_PSRADI128,
2478 IX86_BUILTIN_PSRLDQI128,
2479 IX86_BUILTIN_PSRLWI128,
2480 IX86_BUILTIN_PSRLDI128,
2481 IX86_BUILTIN_PSRLQI128,
2483 IX86_BUILTIN_PUNPCKHBW128,
2484 IX86_BUILTIN_PUNPCKHWD128,
2485 IX86_BUILTIN_PUNPCKHDQ128,
2486 IX86_BUILTIN_PUNPCKHQDQ128,
2487 IX86_BUILTIN_PUNPCKLBW128,
2488 IX86_BUILTIN_PUNPCKLWD128,
2489 IX86_BUILTIN_PUNPCKLDQ128,
2490 IX86_BUILTIN_PUNPCKLQDQ128,
2492 IX86_BUILTIN_CLFLUSH,
2493 IX86_BUILTIN_MFENCE,
2494 IX86_BUILTIN_LFENCE,
2499 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
2500 #define TARGET_STRIP_NAME_ENCODING ix86_strip_name_encoding
2502 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2504 const char *xname = (NAME); \
2505 if (xname[0] == '%') \
2507 if (xname[0] == '*') \
2510 fputs (user_label_prefix, FILE); \
2511 fputs (xname, FILE); \
2514 /* Max number of args passed in registers. If this is more than 3, we will
2515 have problems with ebx (register #4), since it is a caller save register and
2516 is also used as the pic register in ELF. So for now, don't allow more than
2517 3 registers to be passed in registers. */
2519 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2521 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2524 /* Specify the machine mode that this machine uses
2525 for the index in the tablejump instruction. */
2526 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2528 /* Define as C expression which evaluates to nonzero if the tablejump
2529 instruction expects the table to contain offsets from the address of the
2531 Do not define this if the table should contain absolute addresses. */
2532 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2534 /* Define this as 1 if `char' should by default be signed; else as 0. */
2535 #define DEFAULT_SIGNED_CHAR 1
2537 /* Number of bytes moved into a data cache for a single prefetch operation. */
2538 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2540 /* Number of prefetch operations that can be done in parallel. */
2541 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2543 /* Max number of bytes we can move from memory to memory
2544 in one reasonably fast instruction. */
2547 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2548 move efficiently, as opposed to MOVE_MAX which is the maximum
2549 number of bytes we can move with a single instruction. */
2550 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2552 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2553 move-instruction pairs, we will do a movstr or libcall instead.
2554 Increasing the value will always make code faster, but eventually
2555 incurs high cost in increased code size.
2557 If you don't define this, a reasonable default is used. */
2559 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2561 /* Define if shifts truncate the shift count
2562 which implies one can omit a sign-extension or zero-extension
2563 of a shift count. */
2564 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2566 /* #define SHIFT_COUNT_TRUNCATED */
2568 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2569 is done just by pretending it is already truncated. */
2570 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2572 /* We assume that the store-condition-codes instructions store 0 for false
2573 and some other value for true. This is the value stored for true. */
2575 #define STORE_FLAG_VALUE 1
2577 /* When a prototype says `char' or `short', really pass an `int'.
2578 (The 386 can't easily push less than an int.) */
2580 #define PROMOTE_PROTOTYPES 1
2582 /* A macro to update M and UNSIGNEDP when an object whose type is
2583 TYPE and which has the specified mode and signedness is to be
2584 stored in a register. This macro is only called when TYPE is a
2587 On i386 it is sometimes useful to promote HImode and QImode
2588 quantities to SImode. The choice depends on target type. */
2590 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2592 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2593 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2597 /* Specify the machine mode that pointers have.
2598 After generation of rtl, the compiler makes no further distinction
2599 between pointers and any other objects of this machine mode. */
2600 #define Pmode (TARGET_64BIT ? DImode : SImode)
2602 /* A function address in a call instruction
2603 is a byte address (for indexing purposes)
2604 so give the MEM rtx a byte's mode. */
2605 #define FUNCTION_MODE QImode
2607 /* A C expression for the cost of moving data from a register in class FROM to
2608 one in class TO. The classes are expressed using the enumeration values
2609 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2610 interpreted relative to that.
2612 It is not required that the cost always equal 2 when FROM is the same as TO;
2613 on some machines it is expensive to move between registers if they are not
2614 general registers. */
2616 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2617 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2619 /* A C expression for the cost of moving data of mode M between a
2620 register and memory. A value of 2 is the default; this cost is
2621 relative to those in `REGISTER_MOVE_COST'.
2623 If moving between registers and memory is more expensive than
2624 between two registers, you should define this macro to express the
2627 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2628 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2630 /* A C expression for the cost of a branch instruction. A value of 1
2631 is the default; other values are interpreted relative to that. */
2633 #define BRANCH_COST ix86_branch_cost
2635 /* Define this macro as a C expression which is nonzero if accessing
2636 less than a word of memory (i.e. a `char' or a `short') is no
2637 faster than accessing a word of memory, i.e., if such access
2638 require more than one instruction or if there is no difference in
2639 cost between byte and (aligned) word loads.
2641 When this macro is not defined, the compiler will access a field by
2642 finding the smallest containing object; when it is defined, a
2643 fullword load will be used if alignment permits. Unless bytes
2644 accesses are faster than word accesses, using word accesses is
2645 preferable since it may eliminate subsequent memory access if
2646 subsequent accesses occur to other fields in the same word of the
2647 structure, but to different bytes. */
2649 #define SLOW_BYTE_ACCESS 0
2651 /* Nonzero if access to memory by shorts is slow and undesirable. */
2652 #define SLOW_SHORT_ACCESS 0
2654 /* Define this macro to be the value 1 if unaligned accesses have a
2655 cost many times greater than aligned accesses, for example if they
2656 are emulated in a trap handler.
2658 When this macro is nonzero, the compiler will act as if
2659 `STRICT_ALIGNMENT' were nonzero when generating code for block
2660 moves. This can cause significantly more instructions to be
2661 produced. Therefore, do not set this macro nonzero if unaligned
2662 accesses only add a cycle or two to the time for a memory access.
2664 If the value of this macro is always zero, it need not be defined. */
2666 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2668 /* Define this macro to inhibit strength reduction of memory
2669 addresses. (On some machines, such strength reduction seems to do
2670 harm rather than good.) */
2672 /* #define DONT_REDUCE_ADDR */
2674 /* Define this macro if it is as good or better to call a constant
2675 function address than to call an address kept in a register.
2677 Desirable on the 386 because a CALL with a constant address is
2678 faster than one with a register address. */
2680 #define NO_FUNCTION_CSE
2682 /* Define this macro if it is as good or better for a function to call
2683 itself with an explicit address than to call an address kept in a
2686 #define NO_RECURSIVE_FUNCTION_CSE
2688 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2689 return the mode to be used for the comparison.
2691 For floating-point equality comparisons, CCFPEQmode should be used.
2692 VOIDmode should be used in all other cases.
2694 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2695 possible, to allow for more combinations. */
2697 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2699 /* Return nonzero if MODE implies a floating point inequality can be
2702 #define REVERSIBLE_CC_MODE(MODE) 1
2704 /* A C expression whose value is reversed condition code of the CODE for
2705 comparison done in CC_MODE mode. */
2706 #define REVERSE_CONDITION(CODE, MODE) \
2707 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2708 : reverse_condition_maybe_unordered (CODE))
2711 /* Control the assembler format that we output, to the extent
2712 this does not vary between assemblers. */
2714 /* How to refer to registers in assembler output.
2715 This sequence is indexed by compiler's hard-register-number (see above). */
2717 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2718 For non floating point regs, the following are the HImode names.
2720 For float regs, the stack top is sometimes referred to as "%st(0)"
2721 instead of just "%st". PRINT_REG handles this with the "y" code. */
2723 #undef HI_REGISTER_NAMES
2724 #define HI_REGISTER_NAMES \
2725 {"ax","dx","cx","bx","si","di","bp","sp", \
2726 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2727 "flags","fpsr", "dirflag", "frame", \
2728 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2729 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2730 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2731 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2733 #define REGISTER_NAMES HI_REGISTER_NAMES
2735 /* Table of additional register names to use in user input. */
2737 #define ADDITIONAL_REGISTER_NAMES \
2738 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2739 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2740 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2741 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2742 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2743 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2744 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2745 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2747 /* Note we are omitting these since currently I don't know how
2748 to get gcc to use these, since they want the same but different
2749 number as al, and ax.
2752 #define QI_REGISTER_NAMES \
2753 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2755 /* These parallel the array above, and can be used to access bits 8:15
2756 of regs 0 through 3. */
2758 #define QI_HIGH_REGISTER_NAMES \
2759 {"ah", "dh", "ch", "bh", }
2761 /* How to renumber registers for dbx and gdb. */
2763 #define DBX_REGISTER_NUMBER(N) \
2764 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2766 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2767 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2768 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2770 /* Before the prologue, RA is at 0(%esp). */
2771 #define INCOMING_RETURN_ADDR_RTX \
2772 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2774 /* After the prologue, RA is at -4(AP) in the current frame. */
2775 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2777 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2778 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2780 /* PC is dbx register 8; let's use that column for RA. */
2781 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2783 /* Before the prologue, the top of the frame is at 4(%esp). */
2784 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2786 /* Describe how we implement __builtin_eh_return. */
2787 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2788 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2791 /* Select a format to encode pointers in exception handling data. CODE
2792 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2793 true if the symbol may be affected by dynamic relocations.
2795 ??? All x86 object file formats are capable of representing this.
2796 After all, the relocation needed is the same as for the call insn.
2797 Whether or not a particular assembler allows us to enter such, I
2798 guess we'll have to see. */
2799 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2801 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2804 /* This is how to output an insn to push a register on the stack.
2805 It need not be very fast code. */
2807 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2810 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2811 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2813 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2816 /* This is how to output an insn to pop a register from the stack.
2817 It need not be very fast code. */
2819 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2822 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2823 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2825 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2828 /* This is how to output an element of a case-vector that is absolute. */
2830 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2831 ix86_output_addr_vec_elt ((FILE), (VALUE))
2833 /* This is how to output an element of a case-vector that is relative. */
2835 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2836 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2838 /* Under some conditions we need jump tables in the text section, because
2839 the assembler cannot handle label differences between sections. */
2841 #define JUMP_TABLES_IN_TEXT_SECTION \
2842 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2844 /* A C statement that outputs an address constant appropriate to
2845 for DWARF debugging. */
2847 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
2848 i386_dwarf_output_addr_const ((FILE), (X))
2850 /* Emit a dtp-relative reference to a TLS variable. */
2853 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
2854 i386_output_dwarf_dtprel (FILE, SIZE, X)
2857 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2858 and switch back. For x86 we do this only to save a few bytes that
2859 would otherwise be unused in the text section. */
2860 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2861 asm (SECTION_OP "\n\t" \
2862 "call " USER_LABEL_PREFIX #FUNC "\n" \
2863 TEXT_SECTION_ASM_OP);
2865 /* Print operand X (an rtx) in assembler syntax to file FILE.
2866 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2867 Effect of various CODE letters is described in i386.c near
2868 print_operand function. */
2870 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2871 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2873 /* Print the name of a register based on its machine mode and number.
2874 If CODE is 'w', pretend the mode is HImode.
2875 If CODE is 'b', pretend the mode is QImode.
2876 If CODE is 'k', pretend the mode is SImode.
2877 If CODE is 'q', pretend the mode is DImode.
2878 If CODE is 'h', pretend the reg is the `high' byte register.
2879 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2881 #define PRINT_REG(X, CODE, FILE) \
2882 print_reg ((X), (CODE), (FILE))
2884 #define PRINT_OPERAND(FILE, X, CODE) \
2885 print_operand ((FILE), (X), (CODE))
2887 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2888 print_operand_address ((FILE), (ADDR))
2890 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2892 if (! output_addr_const_extra (FILE, (X))) \
2896 /* Print the name of a register for based on its machine mode and number.
2897 This macro is used to print debugging output.
2898 This macro is different from PRINT_REG in that it may be used in
2899 programs that are not linked with aux-output.o. */
2901 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2902 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2903 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2904 fprintf ((FILE), "%d ", REGNO (X)); \
2905 if (REGNO (X) == FLAGS_REG) \
2906 { fputs ("flags", (FILE)); break; } \
2907 if (REGNO (X) == DIRFLAG_REG) \
2908 { fputs ("dirflag", (FILE)); break; } \
2909 if (REGNO (X) == FPSR_REG) \
2910 { fputs ("fpsr", (FILE)); break; } \
2911 if (REGNO (X) == ARG_POINTER_REGNUM) \
2912 { fputs ("argp", (FILE)); break; } \
2913 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2914 { fputs ("frame", (FILE)); break; } \
2915 if (STACK_TOP_P (X)) \
2916 { fputs ("st(0)", (FILE)); break; } \
2918 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
2919 if (REX_INT_REG_P (X)) \
2921 switch (GET_MODE_SIZE (GET_MODE (X))) \
2925 fprintf ((FILE), "r%i", REGNO (X) \
2926 - FIRST_REX_INT_REG + 8); \
2929 fprintf ((FILE), "r%id", REGNO (X) \
2930 - FIRST_REX_INT_REG + 8); \
2933 fprintf ((FILE), "r%iw", REGNO (X) \
2934 - FIRST_REX_INT_REG + 8); \
2937 fprintf ((FILE), "r%ib", REGNO (X) \
2938 - FIRST_REX_INT_REG + 8); \
2943 switch (GET_MODE_SIZE (GET_MODE (X))) \
2946 fputs ("r", (FILE)); \
2947 fputs (hi_name[REGNO (X)], (FILE)); \
2950 fputs ("e", (FILE)); \
2952 fputs (hi_name[REGNO (X)], (FILE)); \
2955 fputs (qi_name[REGNO (X)], (FILE)); \
2960 /* a letter which is not needed by the normal asm syntax, which
2961 we can use for operand syntax in the extended asm */
2963 #define ASM_OPERAND_LETTER '#'
2964 #define RET return ""
2965 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2967 /* Define the codes that are matched by predicates in i386.c. */
2969 #define PREDICATE_CODES \
2970 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
2971 SYMBOL_REF, LABEL_REF, CONST}}, \
2972 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
2973 SYMBOL_REF, LABEL_REF, CONST}}, \
2974 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
2975 SYMBOL_REF, LABEL_REF, CONST}}, \
2976 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
2977 SYMBOL_REF, LABEL_REF, CONST}}, \
2978 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
2979 SYMBOL_REF, LABEL_REF, CONST}}, \
2980 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
2981 SYMBOL_REF, LABEL_REF, CONST}}, \
2982 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
2983 SYMBOL_REF, LABEL_REF}}, \
2984 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
2985 {"const_int_1_operand", {CONST_INT}}, \
2986 {"const_int_1_31_operand", {CONST_INT}}, \
2987 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2988 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2989 LABEL_REF, SUBREG, REG, MEM}}, \
2990 {"pic_symbolic_operand", {CONST}}, \
2991 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
2992 {"sibcall_insn_operand", {REG, SUBREG, SYMBOL_REF}}, \
2993 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
2994 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
2995 {"const1_operand", {CONST_INT}}, \
2996 {"const248_operand", {CONST_INT}}, \
2997 {"incdec_operand", {CONST_INT}}, \
2998 {"mmx_reg_operand", {REG}}, \
2999 {"reg_no_sp_operand", {SUBREG, REG}}, \
3000 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3001 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3002 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3003 {"index_register_operand", {SUBREG, REG}}, \
3004 {"flags_reg_operand", {REG}}, \
3005 {"q_regs_operand", {SUBREG, REG}}, \
3006 {"non_q_regs_operand", {SUBREG, REG}}, \
3007 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3008 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3009 GE, UNGE, LTGT, UNEQ}}, \
3010 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3011 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3013 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3014 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3015 UNGE, UNGT, LTGT, UNEQ }}, \
3016 {"ix86_carry_flag_operator", {LTU, LT, UNLT, GT, UNGT, LE, UNLE, \
3017 GE, UNGE, LTGT, UNEQ}}, \
3018 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3019 {"ext_register_operand", {SUBREG, REG}}, \
3020 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3021 {"mult_operator", {MULT}}, \
3022 {"div_operator", {DIV}}, \
3023 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3024 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3025 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3026 LSHIFTRT, ROTATERT}}, \
3027 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3028 {"memory_displacement_operand", {MEM}}, \
3029 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3030 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3031 {"long_memory_operand", {MEM}}, \
3032 {"tls_symbolic_operand", {SYMBOL_REF}}, \
3033 {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3034 {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3035 {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \
3036 {"local_exec_symbolic_operand", {SYMBOL_REF}}, \
3037 {"any_fp_register_operand", {REG}}, \
3038 {"register_and_not_any_fp_reg_operand", {REG}}, \
3039 {"fp_register_operand", {REG}}, \
3040 {"register_and_not_fp_reg_operand", {REG}}, \
3041 {"zero_extended_scalar_load_operand", {MEM}}, \
3043 /* A list of predicates that do special things with modes, and so
3044 should not elicit warnings for VOIDmode match_operand. */
3046 #define SPECIAL_MODE_PREDICATES \
3047 "ext_register_operand",
3049 /* Which processor to schedule for. The cpu attribute defines a list that
3050 mirrors this list, so changes to i386.md must be made at the same time. */
3054 PROCESSOR_I386, /* 80386 */
3055 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
3057 PROCESSOR_PENTIUMPRO,
3065 extern enum processor_type ix86_cpu;
3066 extern const char *ix86_cpu_string;
3068 extern enum processor_type ix86_arch;
3069 extern const char *ix86_arch_string;
3077 extern enum fpmath_unit ix86_fpmath;
3078 extern const char *ix86_fpmath_string;
3086 extern enum tls_dialect ix86_tls_dialect;
3087 extern const char *ix86_tls_dialect_string;
3090 CM_32, /* The traditional 32-bit ABI. */
3091 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
3092 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
3093 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
3094 CM_LARGE, /* No assumptions. */
3095 CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */
3098 extern enum cmodel ix86_cmodel;
3099 extern const char *ix86_cmodel_string;
3101 /* Size of the RED_ZONE area. */
3102 #define RED_ZONE_SIZE 128
3103 /* Reserved area of the red zone for temporaries. */
3104 #define RED_ZONE_RESERVE 8
3111 extern const char *ix86_asm_string;
3112 extern enum asm_dialect ix86_asm_dialect;
3114 extern int ix86_regparm;
3115 extern const char *ix86_regparm_string;
3117 extern int ix86_preferred_stack_boundary;
3118 extern const char *ix86_preferred_stack_boundary_string;
3120 extern int ix86_branch_cost;
3121 extern const char *ix86_branch_cost_string;
3123 extern const char *ix86_debug_arg_string;
3124 extern const char *ix86_debug_addr_string;
3126 /* Obsoleted by -f options. Remove before 3.2 ships. */
3127 extern const char *ix86_align_loops_string;
3128 extern const char *ix86_align_jumps_string;
3129 extern const char *ix86_align_funcs_string;
3131 /* Smallest class containing REGNO. */
3132 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
3134 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3135 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3137 /* To properly truncate FP values into integers, we need to set i387 control
3138 word. We can't emit proper mode switching code before reload, as spills
3139 generated by reload may truncate values incorrectly, but we still can avoid
3140 redundant computation of new control word by the mode switching pass.
3141 The fldcw instructions are still emitted redundantly, but this is probably
3142 not going to be noticeable problem, as most CPUs do have fast path for
3145 The machinery is to emit simple truncation instructions and split them
3146 before reload to instructions having USEs of two memory locations that
3147 are filled by this code to old and new control word.
3149 Post-reload pass may be later used to eliminate the redundant fildcw if
3152 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3154 /* Define this macro if the port needs extra instructions inserted
3155 for mode switching in an optimizing compilation. */
3157 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3159 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3160 initializer for an array of integers. Each initializer element N
3161 refers to an entity that needs mode switching, and specifies the
3162 number of different modes that might need to be set for this
3163 entity. The position of the initializer in the initializer -
3164 starting counting at zero - determines the integer that is used to
3165 refer to the mode-switched entity in question. */
3167 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3169 /* ENTITY is an integer specifying a mode-switched entity. If
3170 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3171 return an integer value not larger than the corresponding element
3172 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3173 must be switched into prior to the execution of INSN. */
3175 #define MODE_NEEDED(ENTITY, I) \
3176 (GET_CODE (I) == CALL_INSN \
3177 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3178 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3179 ? FP_CW_UNINITIALIZED \
3180 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3184 /* This macro specifies the order in which modes for ENTITY are
3185 processed. 0 is the highest priority. */
3187 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3189 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3190 is the set of hard registers live at the point where the insn(s)
3191 are to be inserted. */
3193 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3194 ((MODE) == FP_CW_STORED \
3195 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3196 assign_386_stack_local (HImode, 2)), 0\
3199 /* Avoid renaming of stack registers, as doing so in combination with
3200 scheduling just increases amount of live registers at time and in
3201 the turn amount of fxch instructions needed.
3203 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3205 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3206 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
3209 #define MACHINE_DEPENDENT_REORG(X) x86_machine_dependent_reorg(X)
3211 #define DLL_IMPORT_EXPORT_PREFIX '#'
3213 #define FASTCALL_PREFIX '@'
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