1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Define the specific costs for a given cpu */
39 struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init[5]; /* cost of starting a multiply
45 in QImode, HImode, SImode, DImode, TImode*/
46 const int mult_bit; /* cost of multiply per each bit set */
47 const int divide[5]; /* cost of a divide/mod
48 in QImode, HImode, SImode, DImode, TImode*/
49 int movsx; /* The cost of movsx operation. */
50 int movzx; /* The cost of movzx operation. */
51 const int large_insn; /* insns larger than this cost more */
52 const int move_ratio; /* The threshold of number of scalar
53 memory-to-memory move insns. */
54 const int movzbl_load; /* cost of loading using movzbl */
55 const int int_load[3]; /* cost of loading integer registers
56 in QImode, HImode and SImode relative
57 to reg-reg move (2). */
58 const int int_store[3]; /* cost of storing integer register
59 in QImode, HImode and SImode */
60 const int fp_move; /* cost of reg,reg fld/fst */
61 const int fp_load[3]; /* cost of loading FP register
62 in SFmode, DFmode and XFmode */
63 const int fp_store[3]; /* cost of storing FP register
64 in SFmode, DFmode and XFmode */
65 const int mmx_move; /* cost of moving MMX register. */
66 const int mmx_load[2]; /* cost of loading MMX register
67 in SImode and DImode */
68 const int mmx_store[2]; /* cost of storing MMX register
69 in SImode and DImode */
70 const int sse_move; /* cost of moving SSE register. */
71 const int sse_load[3]; /* cost of loading SSE register
72 in SImode, DImode and TImode*/
73 const int sse_store[3]; /* cost of storing SSE register
74 in SImode, DImode and TImode*/
75 const int mmxsse_to_integer; /* cost of moving mmxsse register to
76 integer and vice versa. */
77 const int prefetch_block; /* bytes moved to cache for prefetch. */
78 const int simultaneous_prefetches; /* number of parallel prefetch
80 const int branch_cost; /* Default value for BRANCH_COST. */
81 const int fadd; /* cost of FADD and FSUB instructions. */
82 const int fmul; /* cost of FMUL instruction. */
83 const int fdiv; /* cost of FDIV instruction. */
84 const int fabs; /* cost of FABS instruction. */
85 const int fchs; /* cost of FCHS instruction. */
86 const int fsqrt; /* cost of FSQRT instruction. */
89 extern const struct processor_costs *ix86_cost;
91 /* Run-time compilation parameters selecting different hardware subsets. */
93 extern int target_flags;
95 /* Macros used in the machine description to test the flags. */
97 /* configure can arrange to make this 2, to force a 486. */
99 #ifndef TARGET_CPU_DEFAULT
100 #ifdef TARGET_64BIT_DEFAULT
101 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_k8
103 #define TARGET_CPU_DEFAULT 0
107 /* Masks for the -m switches */
108 #define MASK_80387 0x00000001 /* Hardware floating point */
109 #define MASK_RTD 0x00000002 /* Use ret that pops args */
110 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
111 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
112 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
113 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
114 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
115 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
116 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
117 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
118 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
119 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
120 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
121 #define MASK_MMX 0x00002000 /* Support MMX regs/builtins */
122 #define MASK_SSE 0x00004000 /* Support SSE regs/builtins */
123 #define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */
124 #define MASK_PNI 0x00010000 /* Support PNI regs/builtins */
125 #define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */
126 #define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */
127 #define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
128 #define MASK_64BIT 0x00100000 /* Produce 64bit code */
129 #define MASK_MS_BITFIELD_LAYOUT 0x00200000 /* Use native (MS) bitfield layout */
130 #define MASK_TLS_DIRECT_SEG_REFS 0x00400000 /* Avoid adding %gs:0 */
132 /* Unused: 0x03e0000 */
134 /* ... overlap with subtarget options starts by 0x04000000. */
135 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
137 /* Use the floating point instructions */
138 #define TARGET_80387 (target_flags & MASK_80387)
140 /* Compile using ret insn that pops args.
141 This will not work unless you use prototypes at least
142 for all functions that can take varying numbers of args. */
143 #define TARGET_RTD (target_flags & MASK_RTD)
145 /* Align doubles to a two word boundary. This breaks compatibility with
146 the published ABI's for structures containing doubles, but produces
147 faster code on the pentium. */
148 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
150 /* Use push instructions to save outgoing args. */
151 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
153 /* Accumulate stack adjustments to prologue/epilogue. */
154 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
155 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
157 /* Put uninitialized locals into bss, not data.
158 Meaningful only on svr3. */
159 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
161 /* Use IEEE floating point comparisons. These handle correctly the cases
162 where the result of a comparison is unordered. Normally SIGFPE is
163 generated in such cases, in which case this isn't needed. */
164 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
166 /* Functions that return a floating point value may return that value
167 in the 387 FPU or in 386 integer registers. If set, this flag causes
168 the 387 to be used, which is compatible with most calling conventions. */
169 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
171 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
172 This mode wastes cache, but avoid misaligned data accesses and simplifies
173 address calculations. */
174 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
176 /* Disable generation of FP sin, cos and sqrt operations for 387.
177 This is because FreeBSD lacks these in the math-emulator-code */
178 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
180 /* Don't create frame pointers for leaf functions */
181 #define TARGET_OMIT_LEAF_FRAME_POINTER \
182 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
184 /* Debug GO_IF_LEGITIMATE_ADDRESS */
185 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
187 /* Debug FUNCTION_ARG macros */
188 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
190 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
191 compile-time constant. */
194 #define TARGET_64BIT 1
196 #define TARGET_64BIT 0
199 #ifdef TARGET_BI_ARCH
200 #define TARGET_64BIT (target_flags & MASK_64BIT)
202 #if TARGET_64BIT_DEFAULT
203 #define TARGET_64BIT 1
205 #define TARGET_64BIT 0
210 /* Avoid adding %gs:0 in TLS references; use %gs:address directly. */
211 #define TARGET_TLS_DIRECT_SEG_REFS (target_flags & MASK_TLS_DIRECT_SEG_REFS)
213 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
214 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
215 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
216 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
217 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
218 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
219 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
220 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
221 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
223 #define TUNEMASK (1 << ix86_tune)
224 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
225 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
226 extern const int x86_branch_hints, x86_unroll_strlen;
227 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
228 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
229 extern const int x86_use_cltd, x86_read_modify_write;
230 extern const int x86_read_modify, x86_split_long_moves;
231 extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
232 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
233 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
234 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
235 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
236 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
237 extern const int x86_epilogue_using_move, x86_decompose_lea;
238 extern const int x86_arch_always_fancy_math_387, x86_shift1;
239 extern const int x86_sse_partial_reg_dependency, x86_sse_partial_regs;
240 extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
241 extern const int x86_use_ffreep, x86_sse_partial_regs_for_cvtsd2ss;
242 extern const int x86_inter_unit_moves;
243 extern int x86_prefetch_sse;
245 #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
246 #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
247 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
248 #define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
249 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
250 /* For sane SSE instruction set generation we need fcomi instruction. It is
251 safe to enable all CMOVE instructions. */
252 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
253 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
254 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
255 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
256 #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
257 #define TARGET_MOVX (x86_movx & TUNEMASK)
258 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
259 #define TARGET_USE_LOOP (x86_use_loop & TUNEMASK)
260 #define TARGET_USE_FIOP (x86_use_fiop & TUNEMASK)
261 #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
262 #define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
263 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
264 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
265 #define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
266 #define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
267 #define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
268 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
269 #define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
270 #define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
271 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
272 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
273 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
274 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
275 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
276 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
277 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
278 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
279 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
280 (x86_sse_partial_reg_dependency & TUNEMASK)
281 #define TARGET_SSE_PARTIAL_REGS (x86_sse_partial_regs & TUNEMASK)
282 #define TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS \
283 (x86_sse_partial_regs_for_cvtsd2ss & TUNEMASK)
284 #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
285 #define TARGET_SSE_TYPELESS_LOAD0 (x86_sse_typeless_load0 & TUNEMASK)
286 #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
287 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
288 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
289 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
290 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & TUNEMASK)
291 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
292 #define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
293 #define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
294 #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
295 #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
297 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
299 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
300 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
302 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
304 #define TARGET_SSE ((target_flags & MASK_SSE) != 0)
305 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
306 #define TARGET_PNI ((target_flags & MASK_PNI) != 0)
307 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
308 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
309 && (ix86_fpmath & FPMATH_387))
310 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
311 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
312 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
314 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
316 #define TARGET_USE_MS_BITFIELD_LAYOUT (target_flags & MASK_MS_BITFIELD_LAYOUT)
318 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
319 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
321 /* WARNING: Do not mark empty strings for translation, as calling
322 gettext on an empty string does NOT return an empty
326 #define TARGET_SWITCHES \
327 { { "80387", MASK_80387, N_("Use hardware fp") }, \
328 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
329 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
330 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
331 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
332 { "386", 0, "" /*Deprecated.*/}, \
333 { "486", 0, "" /*Deprecated.*/}, \
334 { "pentium", 0, "" /*Deprecated.*/}, \
335 { "pentiumpro", 0, "" /*Deprecated.*/}, \
336 { "intel-syntax", 0, "" /*Deprecated.*/}, \
337 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
339 N_("Alternate calling convention") }, \
340 { "no-rtd", -MASK_RTD, \
341 N_("Use normal calling convention") }, \
342 { "align-double", MASK_ALIGN_DOUBLE, \
343 N_("Align some doubles on dword boundary") }, \
344 { "no-align-double", -MASK_ALIGN_DOUBLE, \
345 N_("Align doubles on word boundary") }, \
346 { "svr3-shlib", MASK_SVR3_SHLIB, \
347 N_("Uninitialized locals in .bss") }, \
348 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
349 N_("Uninitialized locals in .data") }, \
350 { "ieee-fp", MASK_IEEE_FP, \
351 N_("Use IEEE math for fp comparisons") }, \
352 { "no-ieee-fp", -MASK_IEEE_FP, \
353 N_("Do not use IEEE math for fp comparisons") }, \
354 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
355 N_("Return values of functions in FPU registers") }, \
356 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
357 N_("Do not return values of functions in FPU registers")}, \
358 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
359 N_("Do not generate sin, cos, sqrt for FPU") }, \
360 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
361 N_("Generate sin, cos, sqrt for FPU")}, \
362 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
363 N_("Omit the frame pointer in leaf functions") }, \
364 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
365 { "stack-arg-probe", MASK_STACK_PROBE, \
366 N_("Enable stack probing") }, \
367 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
368 { "windows", 0, 0 /* undocumented */ }, \
369 { "dll", 0, 0 /* undocumented */ }, \
370 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
371 N_("Align destination of the string operations") }, \
372 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
373 N_("Do not align destination of the string operations") }, \
374 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
375 N_("Inline all known string operations") }, \
376 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
377 N_("Do not inline all known string operations") }, \
378 { "push-args", -MASK_NO_PUSH_ARGS, \
379 N_("Use push instructions to save outgoing arguments") }, \
380 { "no-push-args", MASK_NO_PUSH_ARGS, \
381 N_("Do not use push instructions to save outgoing arguments") }, \
382 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
383 N_("Use push instructions to save outgoing arguments") }, \
384 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
385 N_("Do not use push instructions to save outgoing arguments") }, \
387 N_("Support MMX built-in functions") }, \
388 { "no-mmx", -MASK_MMX, \
389 N_("Do not support MMX built-in functions") }, \
390 { "3dnow", MASK_3DNOW, \
391 N_("Support 3DNow! built-in functions") }, \
392 { "no-3dnow", -MASK_3DNOW, \
393 N_("Do not support 3DNow! built-in functions") }, \
395 N_("Support MMX and SSE built-in functions and code generation") }, \
396 { "no-sse", -MASK_SSE, \
397 N_("Do not support MMX and SSE built-in functions and code generation") },\
398 { "sse2", MASK_SSE2, \
399 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
400 { "no-sse2", -MASK_SSE2, \
401 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
403 N_("Support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\
404 { "no-pni", -MASK_PNI, \
405 N_("Do not support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\
406 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
407 N_("sizeof(long double) is 16") }, \
408 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
409 N_("sizeof(long double) is 12") }, \
410 { "64", MASK_64BIT, \
411 N_("Generate 64bit x86-64 code") }, \
412 { "32", -MASK_64BIT, \
413 N_("Generate 32bit i386 code") }, \
414 { "ms-bitfields", MASK_MS_BITFIELD_LAYOUT, \
415 N_("Use native (MS) bitfield layout") }, \
416 { "no-ms-bitfields", -MASK_MS_BITFIELD_LAYOUT, \
417 N_("Use gcc default bitfield layout") }, \
418 { "red-zone", -MASK_NO_RED_ZONE, \
419 N_("Use red-zone in the x86-64 code") }, \
420 { "no-red-zone", MASK_NO_RED_ZONE, \
421 N_("Do not use red-zone in the x86-64 code") }, \
422 { "tls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS, \
423 N_("Use direct references against %gs when accessing tls data") }, \
424 { "no-tls-direct-seg-refs", -MASK_TLS_DIRECT_SEG_REFS, \
425 N_("Do not use direct references against %gs when accessing tls data") }, \
428 TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT \
429 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT, 0 }}
431 #ifndef TARGET_64BIT_DEFAULT
432 #define TARGET_64BIT_DEFAULT 0
434 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
435 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
438 /* Once GDB has been enhanced to deal with functions without frame
439 pointers, we can change this to allow for elimination of
440 the frame pointer in leaf functions. */
441 #define TARGET_DEFAULT 0
443 /* This is not really a target flag, but is done this way so that
444 it's analogous to similar code for Mach-O on PowerPC. darwin.h
445 redefines this to 1. */
446 #define TARGET_MACHO 0
448 /* This macro is similar to `TARGET_SWITCHES' but defines names of
449 command options that have values. Its definition is an
450 initializer with a subgrouping for each command option.
452 Each subgrouping contains a string constant, that defines the
453 fixed part of the option name, and the address of a variable. The
454 variable, type `char *', is set to the variable part of the given
455 option if the fixed part matches. The actual option name is made
456 by appending `-m' to the specified name. */
457 #define TARGET_OPTIONS \
458 { { "tune=", &ix86_tune_string, \
459 N_("Schedule code for given CPU"), 0}, \
460 { "fpmath=", &ix86_fpmath_string, \
461 N_("Generate floating point mathematics using given instruction set"), 0},\
462 { "arch=", &ix86_arch_string, \
463 N_("Generate code for given CPU"), 0}, \
464 { "regparm=", &ix86_regparm_string, \
465 N_("Number of registers used to pass integer arguments"), 0},\
466 { "align-loops=", &ix86_align_loops_string, \
467 N_("Loop code aligned to this power of 2"), 0}, \
468 { "align-jumps=", &ix86_align_jumps_string, \
469 N_("Jump targets are aligned to this power of 2"), 0}, \
470 { "align-functions=", &ix86_align_funcs_string, \
471 N_("Function starts are aligned to this power of 2"), 0}, \
472 { "preferred-stack-boundary=", \
473 &ix86_preferred_stack_boundary_string, \
474 N_("Attempt to keep stack aligned to this power of 2"), 0}, \
475 { "branch-cost=", &ix86_branch_cost_string, \
476 N_("Branches are this expensive (1-5, arbitrary units)"), 0},\
477 { "cmodel=", &ix86_cmodel_string, \
478 N_("Use given x86-64 code model"), 0}, \
479 { "debug-arg", &ix86_debug_arg_string, \
480 "" /* Undocumented. */, 0}, \
481 { "debug-addr", &ix86_debug_addr_string, \
482 "" /* Undocumented. */, 0}, \
483 { "asm=", &ix86_asm_string, \
484 N_("Use given assembler dialect"), 0}, \
485 { "tls-dialect=", &ix86_tls_dialect_string, \
486 N_("Use given thread-local storage dialect"), 0}, \
490 /* Sometimes certain combinations of command options do not make
491 sense on a particular target machine. You can define a macro
492 `OVERRIDE_OPTIONS' to take account of this. This macro, if
493 defined, is executed once just after all the command options have
496 Don't use this macro to turn on various extra optimizations for
497 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
499 #define OVERRIDE_OPTIONS override_options ()
501 /* These are meant to be redefined in the host dependent files */
502 #define SUBTARGET_SWITCHES
503 #define SUBTARGET_OPTIONS
505 /* Define this to change the optimizations performed by default. */
506 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
507 optimization_options ((LEVEL), (SIZE))
509 /* Support for configure-time defaults of some command line options. */
510 #define OPTION_DEFAULT_SPECS \
511 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
512 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
513 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }
515 /* Specs for the compiler proper */
518 #define CC1_CPU_SPEC "\
521 %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
523 %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
524 %{mpentium:-mtune=pentium \
525 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
526 %{mpentiumpro:-mtune=pentiumpro \
527 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
529 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
531 %{mintel-syntax:-masm=intel \
532 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
533 %{mno-intel-syntax:-masm=att \
534 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
537 /* Target CPU builtins. */
538 #define TARGET_CPU_CPP_BUILTINS() \
541 size_t arch_len = strlen (ix86_arch_string); \
542 size_t tune_len = strlen (ix86_tune_string); \
543 int last_arch_char = ix86_arch_string[arch_len - 1]; \
544 int last_tune_char = ix86_tune_string[tune_len - 1]; \
548 builtin_assert ("cpu=x86_64"); \
549 builtin_define ("__amd64"); \
550 builtin_define ("__amd64__"); \
551 builtin_define ("__x86_64"); \
552 builtin_define ("__x86_64__"); \
553 builtin_define ("__amd64"); \
554 builtin_define ("__amd64__"); \
558 builtin_assert ("cpu=i386"); \
559 builtin_assert ("machine=i386"); \
560 builtin_define_std ("i386"); \
563 /* Built-ins based on -mtune= (or -march= if no \
566 builtin_define ("__tune_i386__"); \
567 else if (TARGET_486) \
568 builtin_define ("__tune_i486__"); \
569 else if (TARGET_PENTIUM) \
571 builtin_define ("__tune_i586__"); \
572 builtin_define ("__tune_pentium__"); \
573 if (last_tune_char == 'x') \
574 builtin_define ("__tune_pentium_mmx__"); \
576 else if (TARGET_PENTIUMPRO) \
578 builtin_define ("__tune_i686__"); \
579 builtin_define ("__tune_pentiumpro__"); \
580 switch (last_tune_char) \
583 builtin_define ("__tune_pentium3__"); \
586 builtin_define ("__tune_pentium2__"); \
590 else if (TARGET_K6) \
592 builtin_define ("__tune_k6__"); \
593 if (last_tune_char == '2') \
594 builtin_define ("__tune_k6_2__"); \
595 else if (last_tune_char == '3') \
596 builtin_define ("__tune_k6_3__"); \
598 else if (TARGET_ATHLON) \
600 builtin_define ("__tune_athlon__"); \
601 /* Only plain "athlon" lacks SSE. */ \
602 if (last_tune_char != 'n') \
603 builtin_define ("__tune_athlon_sse__"); \
605 else if (TARGET_K8) \
606 builtin_define ("__tune_k8__"); \
607 else if (TARGET_PENTIUM4) \
608 builtin_define ("__tune_pentium4__"); \
611 builtin_define ("__MMX__"); \
613 builtin_define ("__3dNOW__"); \
614 if (TARGET_3DNOW_A) \
615 builtin_define ("__3dNOW_A__"); \
617 builtin_define ("__SSE__"); \
619 builtin_define ("__SSE2__"); \
621 builtin_define ("__PNI__"); \
622 if (TARGET_SSE_MATH && TARGET_SSE) \
623 builtin_define ("__SSE_MATH__"); \
624 if (TARGET_SSE_MATH && TARGET_SSE2) \
625 builtin_define ("__SSE2_MATH__"); \
627 /* Built-ins based on -march=. */ \
628 if (ix86_arch == PROCESSOR_I486) \
630 builtin_define ("__i486"); \
631 builtin_define ("__i486__"); \
633 else if (ix86_arch == PROCESSOR_PENTIUM) \
635 builtin_define ("__i586"); \
636 builtin_define ("__i586__"); \
637 builtin_define ("__pentium"); \
638 builtin_define ("__pentium__"); \
639 if (last_arch_char == 'x') \
640 builtin_define ("__pentium_mmx__"); \
642 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
644 builtin_define ("__i686"); \
645 builtin_define ("__i686__"); \
646 builtin_define ("__pentiumpro"); \
647 builtin_define ("__pentiumpro__"); \
649 else if (ix86_arch == PROCESSOR_K6) \
652 builtin_define ("__k6"); \
653 builtin_define ("__k6__"); \
654 if (last_arch_char == '2') \
655 builtin_define ("__k6_2__"); \
656 else if (last_arch_char == '3') \
657 builtin_define ("__k6_3__"); \
659 else if (ix86_arch == PROCESSOR_ATHLON) \
661 builtin_define ("__athlon"); \
662 builtin_define ("__athlon__"); \
663 /* Only plain "athlon" lacks SSE. */ \
664 if (last_arch_char != 'n') \
665 builtin_define ("__athlon_sse__"); \
667 else if (ix86_arch == PROCESSOR_K8) \
669 builtin_define ("__k8"); \
670 builtin_define ("__k8__"); \
672 else if (ix86_arch == PROCESSOR_PENTIUM4) \
674 builtin_define ("__pentium4"); \
675 builtin_define ("__pentium4__"); \
680 #define TARGET_CPU_DEFAULT_i386 0
681 #define TARGET_CPU_DEFAULT_i486 1
682 #define TARGET_CPU_DEFAULT_pentium 2
683 #define TARGET_CPU_DEFAULT_pentium_mmx 3
684 #define TARGET_CPU_DEFAULT_pentiumpro 4
685 #define TARGET_CPU_DEFAULT_pentium2 5
686 #define TARGET_CPU_DEFAULT_pentium3 6
687 #define TARGET_CPU_DEFAULT_pentium4 7
688 #define TARGET_CPU_DEFAULT_k6 8
689 #define TARGET_CPU_DEFAULT_k6_2 9
690 #define TARGET_CPU_DEFAULT_k6_3 10
691 #define TARGET_CPU_DEFAULT_athlon 11
692 #define TARGET_CPU_DEFAULT_athlon_sse 12
693 #define TARGET_CPU_DEFAULT_k8 13
695 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
696 "pentiumpro", "pentium2", "pentium3", \
697 "pentium4", "k6", "k6-2", "k6-3",\
698 "athlon", "athlon-4", "k8"}
701 #define CC1_SPEC "%(cc1_cpu) "
704 /* This macro defines names of additional specifications to put in the
705 specs that can be used in various specifications like CC1_SPEC. Its
706 definition is an initializer with a subgrouping for each command option.
708 Each subgrouping contains a string constant, that defines the
709 specification name, and a string constant that used by the GCC driver
712 Do not define this macro if it does not need to do anything. */
714 #ifndef SUBTARGET_EXTRA_SPECS
715 #define SUBTARGET_EXTRA_SPECS
718 #define EXTRA_SPECS \
719 { "cc1_cpu", CC1_CPU_SPEC }, \
720 SUBTARGET_EXTRA_SPECS
722 /* target machine storage layout */
724 /* Define for XFmode or TFmode extended real floating point support.
725 The XFmode is specified by i386 ABI, while TFmode may be faster
726 due to alignment and simplifications in the address calculations. */
727 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
728 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
730 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
732 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
735 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
736 FPU, assume that the fpcw is set to extended precision; when using
737 only SSE, rounding is correct; when using both SSE and the FPU,
738 the rounding precision is indeterminate, since either may be chosen
739 apparently at random. */
740 #define TARGET_FLT_EVAL_METHOD \
741 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
743 #define SHORT_TYPE_SIZE 16
744 #define INT_TYPE_SIZE 32
745 #define FLOAT_TYPE_SIZE 32
746 #define LONG_TYPE_SIZE BITS_PER_WORD
747 #define MAX_WCHAR_TYPE_SIZE 32
748 #define DOUBLE_TYPE_SIZE 64
749 #define LONG_LONG_TYPE_SIZE 64
751 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
752 #define MAX_BITS_PER_WORD 64
753 #define MAX_LONG_TYPE_SIZE 64
755 #define MAX_BITS_PER_WORD 32
756 #define MAX_LONG_TYPE_SIZE 32
759 /* Define this if most significant byte of a word is the lowest numbered. */
760 /* That is true on the 80386. */
762 #define BITS_BIG_ENDIAN 0
764 /* Define this if most significant byte of a word is the lowest numbered. */
765 /* That is not true on the 80386. */
766 #define BYTES_BIG_ENDIAN 0
768 /* Define this if most significant word of a multiword number is the lowest
770 /* Not true for 80386 */
771 #define WORDS_BIG_ENDIAN 0
773 /* Width of a word, in units (bytes). */
774 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
776 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
778 #define MIN_UNITS_PER_WORD 4
781 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
782 #define PARM_BOUNDARY BITS_PER_WORD
784 /* Boundary (in *bits*) on which stack pointer should be aligned. */
785 #define STACK_BOUNDARY BITS_PER_WORD
787 /* Boundary (in *bits*) on which the stack pointer prefers to be
788 aligned; the compiler cannot rely on having this alignment. */
789 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
791 /* As of July 2001, many runtimes to not align the stack properly when
792 entering main. This causes expand_main_function to forcibly align
793 the stack, which results in aligned frames for functions called from
794 main, though it does nothing for the alignment of main itself. */
795 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
796 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
798 /* Minimum allocation boundary for the code of a function. */
799 #define FUNCTION_BOUNDARY 8
801 /* C++ stores the virtual bit in the lowest bit of function pointers. */
802 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
804 /* Alignment of field after `int : 0' in a structure. */
806 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
808 /* Minimum size in bits of the largest boundary to which any
809 and all fundamental data types supported by the hardware
810 might need to be aligned. No data type wants to be aligned
813 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
814 and Pentium Pro XFmode values at 128 bit boundaries. */
816 #define BIGGEST_ALIGNMENT 128
818 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
819 #define ALIGN_MODE_128(MODE) \
820 ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE))
822 /* The published ABIs say that doubles should be aligned on word
823 boundaries, so lower the alignment for structure fields unless
824 -malign-double is set. */
826 /* ??? Blah -- this macro is used directly by libobjc. Since it
827 supports no vector modes, cut out the complexity and fall back
828 on BIGGEST_FIELD_ALIGNMENT. */
829 #ifdef IN_TARGET_LIBS
831 #define BIGGEST_FIELD_ALIGNMENT 128
833 #define BIGGEST_FIELD_ALIGNMENT 32
836 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
837 x86_field_alignment (FIELD, COMPUTED)
840 /* If defined, a C expression to compute the alignment given to a
841 constant that is being placed in memory. EXP is the constant
842 and ALIGN is the alignment that the object would ordinarily have.
843 The value of this macro is used instead of that alignment to align
846 If this macro is not defined, then ALIGN is used.
848 The typical use of this macro is to increase alignment for string
849 constants to be word aligned so that `strcpy' calls that copy
850 constants can be done inline. */
852 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
854 /* If defined, a C expression to compute the alignment for a static
855 variable. TYPE is the data type, and ALIGN is the alignment that
856 the object would ordinarily have. The value of this macro is used
857 instead of that alignment to align the object.
859 If this macro is not defined, then ALIGN is used.
861 One use of this macro is to increase alignment of medium-size
862 data to make it all fit in fewer cache lines. Another is to
863 cause character arrays to be word-aligned so that `strcpy' calls
864 that copy constants to character arrays can be done inline. */
866 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
868 /* If defined, a C expression to compute the alignment for a local
869 variable. TYPE is the data type, and ALIGN is the alignment that
870 the object would ordinarily have. The value of this macro is used
871 instead of that alignment to align the object.
873 If this macro is not defined, then ALIGN is used.
875 One use of this macro is to increase alignment of medium-size
876 data to make it all fit in fewer cache lines. */
878 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
880 /* If defined, a C expression that gives the alignment boundary, in
881 bits, of an argument with the specified mode and type. If it is
882 not defined, `PARM_BOUNDARY' is used for all arguments. */
884 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
885 ix86_function_arg_boundary ((MODE), (TYPE))
887 /* Set this nonzero if move instructions will actually fail to work
888 when given unaligned data. */
889 #define STRICT_ALIGNMENT 0
891 /* If bit field type is int, don't let it cross an int,
892 and give entire struct the alignment of an int. */
893 /* Required on the 386 since it doesn't have bit-field insns. */
894 #define PCC_BITFIELD_TYPE_MATTERS 1
896 /* Standard register usage. */
898 /* This processor has special stack-like registers. See reg-stack.c
902 #define IS_STACK_MODE(MODE) \
903 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
906 /* Number of actual hardware registers.
907 The hardware registers are assigned numbers for the compiler
908 from 0 to just below FIRST_PSEUDO_REGISTER.
909 All registers that the compiler knows about must be given numbers,
910 even those that are not normally considered general registers.
912 In the 80386 we give the 8 general purpose registers the numbers 0-7.
913 We number the floating point registers 8-15.
914 Note that registers 0-7 can be accessed as a short or int,
915 while only 0-3 may be used with byte `mov' instructions.
917 Reg 16 does not correspond to any hardware register, but instead
918 appears in the RTL as an argument pointer prior to reload, and is
919 eliminated during reloading in favor of either the stack or frame
922 #define FIRST_PSEUDO_REGISTER 53
924 /* Number of hardware registers that go into the DWARF-2 unwind info.
925 If not defined, equals FIRST_PSEUDO_REGISTER. */
927 #define DWARF_FRAME_REGISTERS 17
929 /* 1 for registers that have pervasive standard uses
930 and are not available for the register allocator.
931 On the 80386, the stack pointer is such, as is the arg pointer.
933 The value is a mask - bit 1 is set for fixed registers
934 for 32bit target, while 2 is set for fixed registers for 64bit.
935 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
937 #define FIXED_REGISTERS \
938 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
939 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
940 /*arg,flags,fpsr,dir,frame*/ \
942 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
943 0, 0, 0, 0, 0, 0, 0, 0, \
944 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
945 0, 0, 0, 0, 0, 0, 0, 0, \
946 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
947 1, 1, 1, 1, 1, 1, 1, 1, \
948 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
949 1, 1, 1, 1, 1, 1, 1, 1}
952 /* 1 for registers not available across function calls.
953 These must include the FIXED_REGISTERS and also any
954 registers that can be used without being saved.
955 The latter must include the registers where values are returned
956 and the register where structure-value addresses are passed.
957 Aside from that, you can include as many other registers as you like.
959 The value is a mask - bit 1 is set for call used
960 for 32bit target, while 2 is set for call used for 64bit.
961 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
963 #define CALL_USED_REGISTERS \
964 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
965 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
966 /*arg,flags,fpsr,dir,frame*/ \
968 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
969 3, 3, 3, 3, 3, 3, 3, 3, \
970 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
971 3, 3, 3, 3, 3, 3, 3, 3, \
972 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
973 3, 3, 3, 3, 1, 1, 1, 1, \
974 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
975 3, 3, 3, 3, 3, 3, 3, 3} \
977 /* Order in which to allocate registers. Each register must be
978 listed once, even those in FIXED_REGISTERS. List frame pointer
979 late and fixed registers last. Note that, in general, we prefer
980 registers listed in CALL_USED_REGISTERS, keeping the others
981 available for storage of persistent values.
983 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
984 so this is just empty initializer for array. */
986 #define REG_ALLOC_ORDER \
987 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
988 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
989 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
992 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
993 to be rearranged based on a particular function. When using sse math,
994 we want to allocate SSE before x87 registers and vice vera. */
996 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
999 /* Macro to conditionally modify fixed_regs/call_used_regs. */
1000 #define CONDITIONAL_REGISTER_USAGE \
1003 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1005 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
1006 call_used_regs[i] = (call_used_regs[i] \
1007 & (TARGET_64BIT ? 2 : 1)) != 0; \
1009 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1011 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1012 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1017 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1018 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
1019 fixed_regs[i] = call_used_regs[i] = 1; \
1024 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1025 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
1026 fixed_regs[i] = call_used_regs[i] = 1; \
1028 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
1032 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
1033 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1034 if (TEST_HARD_REG_BIT (x, i)) \
1035 fixed_regs[i] = call_used_regs[i] = 1; \
1039 /* Return number of consecutive hard regs needed starting at reg REGNO
1040 to hold something of mode MODE.
1041 This is ordinarily the length in words of a value of mode MODE
1042 but can be less for certain modes in special long registers.
1044 Actually there are no two word move instructions for consecutive
1045 registers. And only registers 0-3 may have mov byte instructions
1049 #define HARD_REGNO_NREGS(REGNO, MODE) \
1050 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1051 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1052 : ((MODE) == TFmode \
1053 ? (TARGET_64BIT ? 2 : 3) \
1054 : (MODE) == TCmode \
1055 ? (TARGET_64BIT ? 4 : 6) \
1056 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1058 #define VALID_SSE2_REG_MODE(MODE) \
1059 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1060 || (MODE) == V2DImode)
1062 #define VALID_SSE_REG_MODE(MODE) \
1063 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1064 || (MODE) == SFmode \
1065 /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \
1066 || VALID_SSE2_REG_MODE (MODE) \
1067 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
1069 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1070 ((MODE) == V2SFmode || (MODE) == SFmode)
1072 #define VALID_MMX_REG_MODE(MODE) \
1073 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1074 || (MODE) == V2SImode || (MODE) == SImode)
1076 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1077 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
1078 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
1079 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1081 #define VALID_FP_MODE_P(MODE) \
1082 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
1083 || (!TARGET_64BIT && (MODE) == XFmode) \
1084 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
1085 || (!TARGET_64BIT && (MODE) == XCmode))
1087 #define VALID_INT_MODE_P(MODE) \
1088 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1089 || (MODE) == DImode \
1090 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1091 || (MODE) == CDImode \
1092 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
1094 /* Return true for modes passed in SSE registers. */
1095 #define SSE_REG_MODE_P(MODE) \
1096 ((MODE) == TImode || (MODE) == V16QImode \
1097 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1098 || (MODE) == V4SFmode || (MODE) == V4SImode)
1100 /* Return true for modes passed in MMX registers. */
1101 #define MMX_REG_MODE_P(MODE) \
1102 ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \
1103 || (MODE) == V2SFmode)
1105 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1107 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1108 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1110 /* Value is 1 if it is a good idea to tie two pseudo registers
1111 when one has mode MODE1 and one has mode MODE2.
1112 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1113 for any hard reg, then this must be 0 for correct output. */
1115 #define MODES_TIEABLE_P(MODE1, MODE2) \
1116 ((MODE1) == (MODE2) \
1117 || (((MODE1) == HImode || (MODE1) == SImode \
1118 || ((MODE1) == QImode \
1119 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1120 || ((MODE1) == DImode && TARGET_64BIT)) \
1121 && ((MODE2) == HImode || (MODE2) == SImode \
1122 || ((MODE2) == QImode \
1123 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1124 || ((MODE2) == DImode && TARGET_64BIT))))
1126 /* It is possible to write patterns to move flags; but until someone
1128 #define AVOID_CCMODE_COPIES
1130 /* Specify the modes required to caller save a given hard regno.
1131 We do this on i386 to prevent flags from being saved at all.
1133 Kill any attempts to combine saving of modes. */
1135 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1136 (CC_REGNO_P (REGNO) ? VOIDmode \
1137 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1138 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
1139 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1140 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1142 /* Specify the registers used for certain standard purposes.
1143 The values of these macros are register numbers. */
1145 /* on the 386 the pc register is %eip, and is not usable as a general
1146 register. The ordinary mov instructions won't work */
1147 /* #define PC_REGNUM */
1149 /* Register to use for pushing function arguments. */
1150 #define STACK_POINTER_REGNUM 7
1152 /* Base register for access to local variables of the function. */
1153 #define HARD_FRAME_POINTER_REGNUM 6
1155 /* Base register for access to local variables of the function. */
1156 #define FRAME_POINTER_REGNUM 20
1158 /* First floating point reg */
1159 #define FIRST_FLOAT_REG 8
1161 /* First & last stack-like regs */
1162 #define FIRST_STACK_REG FIRST_FLOAT_REG
1163 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1165 #define FLAGS_REG 17
1167 #define DIRFLAG_REG 19
1169 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1170 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1172 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1173 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1175 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1176 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1178 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1179 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1181 /* Value should be nonzero if functions must have frame pointers.
1182 Zero means the frame pointer need not be set up (and parms
1183 may be accessed via the stack pointer) in functions that seem suitable.
1184 This is computed in `reload', in reload1.c. */
1185 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1187 /* Override this in other tm.h files to cope with various OS losage
1188 requiring a frame pointer. */
1189 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1190 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1193 /* Make sure we can access arbitrary call frames. */
1194 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1196 /* Base register for access to arguments of the function. */
1197 #define ARG_POINTER_REGNUM 16
1199 /* Register in which static-chain is passed to a function.
1200 We do use ECX as static chain register for 32 bit ABI. On the
1201 64bit ABI, ECX is an argument register, so we use R10 instead. */
1202 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1204 /* Register to hold the addressing base for position independent
1205 code access to data items. We don't use PIC pointer for 64bit
1206 mode. Define the regnum to dummy value to prevent gcc from
1207 pessimizing code dealing with EBX.
1209 To avoid clobbering a call-saved register unnecessarily, we renumber
1210 the pic register when possible. The change is visible after the
1211 prologue has been emitted. */
1213 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1215 #define PIC_OFFSET_TABLE_REGNUM \
1216 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \
1217 : reload_completed ? REGNO (pic_offset_table_rtx) \
1218 : REAL_PIC_OFFSET_TABLE_REGNUM)
1220 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1222 /* Register in which address to store a structure value
1223 arrives in the function. On the 386, the prologue
1224 copies this from the stack to register %eax. */
1225 #define STRUCT_VALUE_INCOMING 0
1227 /* Place in which caller passes the structure value address.
1228 0 means push the value on the stack like an argument. */
1229 #define STRUCT_VALUE 0
1231 /* A C expression which can inhibit the returning of certain function
1232 values in registers, based on the type of value. A nonzero value
1233 says to return the function value in memory, just as large
1234 structures are always returned. Here TYPE will be a C expression
1235 of type `tree', representing the data type of the value.
1237 Note that values of mode `BLKmode' must be explicitly handled by
1238 this macro. Also, the option `-fpcc-struct-return' takes effect
1239 regardless of this macro. On most systems, it is possible to
1240 leave the macro undefined; this causes a default definition to be
1241 used, whose value is the constant 1 for `BLKmode' values, and 0
1244 Do not use this macro to indicate that structures and unions
1245 should always be returned in memory. You should instead use
1246 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1248 #define RETURN_IN_MEMORY(TYPE) \
1249 ix86_return_in_memory (TYPE)
1251 /* This is overridden by <cygwin.h>. */
1252 #define MS_AGGREGATE_RETURN 0
1255 /* Define the classes of registers for register constraints in the
1256 machine description. Also define ranges of constants.
1258 One of the classes must always be named ALL_REGS and include all hard regs.
1259 If there is more than one class, another class must be named NO_REGS
1260 and contain no registers.
1262 The name GENERAL_REGS must be the name of a class (or an alias for
1263 another name such as ALL_REGS). This is the class of registers
1264 that is allowed by "g" or "r" in a register constraint.
1265 Also, registers outside this class are allocated only when
1266 instructions express preferences for them.
1268 The classes must be numbered in nondecreasing order; that is,
1269 a larger-numbered class must never be contained completely
1270 in a smaller-numbered class.
1272 For any two classes, it is very desirable that there be another
1273 class that represents their union.
1275 It might seem that class BREG is unnecessary, since no useful 386
1276 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1277 and the "b" register constraint is useful in asms for syscalls.
1279 The flags and fpsr registers are in no class. */
1284 AREG, DREG, CREG, BREG, SIREG, DIREG,
1285 AD_REGS, /* %eax/%edx for DImode */
1286 Q_REGS, /* %eax %ebx %ecx %edx */
1287 NON_Q_REGS, /* %esi %edi %ebp %esp */
1288 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1289 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1290 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1291 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1301 ALL_REGS, LIM_REG_CLASSES
1304 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1306 #define INTEGER_CLASS_P(CLASS) \
1307 reg_class_subset_p ((CLASS), GENERAL_REGS)
1308 #define FLOAT_CLASS_P(CLASS) \
1309 reg_class_subset_p ((CLASS), FLOAT_REGS)
1310 #define SSE_CLASS_P(CLASS) \
1311 reg_class_subset_p ((CLASS), SSE_REGS)
1312 #define MMX_CLASS_P(CLASS) \
1313 reg_class_subset_p ((CLASS), MMX_REGS)
1314 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1315 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1316 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1317 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1318 #define MAYBE_SSE_CLASS_P(CLASS) \
1319 reg_classes_intersect_p (SSE_REGS, (CLASS))
1320 #define MAYBE_MMX_CLASS_P(CLASS) \
1321 reg_classes_intersect_p (MMX_REGS, (CLASS))
1323 #define Q_CLASS_P(CLASS) \
1324 reg_class_subset_p ((CLASS), Q_REGS)
1326 /* Give names of register classes as strings for dump file. */
1328 #define REG_CLASS_NAMES \
1330 "AREG", "DREG", "CREG", "BREG", \
1333 "Q_REGS", "NON_Q_REGS", \
1337 "FP_TOP_REG", "FP_SECOND_REG", \
1341 "FP_TOP_SSE_REGS", \
1342 "FP_SECOND_SSE_REGS", \
1346 "FLOAT_INT_SSE_REGS", \
1349 /* Define which registers fit in which classes.
1350 This is an initializer for a vector of HARD_REG_SET
1351 of length N_REG_CLASSES. */
1353 #define REG_CLASS_CONTENTS \
1355 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1356 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1357 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1358 { 0x03, 0x0 }, /* AD_REGS */ \
1359 { 0x0f, 0x0 }, /* Q_REGS */ \
1360 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1361 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1362 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1363 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1364 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1365 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1366 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1367 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1368 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1369 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1370 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1371 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1372 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1373 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1374 { 0xffffffff,0x1fffff } \
1377 /* The same information, inverted:
1378 Return the class number of the smallest class containing
1379 reg number REGNO. This could be a conditional expression
1380 or could index an array. */
1382 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1384 /* When defined, the compiler allows registers explicitly used in the
1385 rtl to be used as spill registers but prevents the compiler from
1386 extending the lifetime of these registers. */
1388 #define SMALL_REGISTER_CLASSES 1
1390 #define QI_REG_P(X) \
1391 (REG_P (X) && REGNO (X) < 4)
1393 #define GENERAL_REGNO_P(N) \
1394 ((N) < 8 || REX_INT_REGNO_P (N))
1396 #define GENERAL_REG_P(X) \
1397 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1399 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1401 #define NON_QI_REG_P(X) \
1402 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1404 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1405 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1407 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1408 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1409 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1410 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1412 #define SSE_REGNO_P(N) \
1413 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1414 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1416 #define REX_SSE_REGNO_P(N) \
1417 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
1419 #define SSE_REGNO(N) \
1420 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1421 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1423 #define SSE_FLOAT_MODE_P(MODE) \
1424 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1426 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1427 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1429 #define STACK_REG_P(XOP) \
1431 REGNO (XOP) >= FIRST_STACK_REG && \
1432 REGNO (XOP) <= LAST_STACK_REG)
1434 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1436 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1438 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1439 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1441 /* Indicate whether hard register numbered REG_NO should be converted
1443 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1444 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1446 /* The class value for index registers, and the one for base regs. */
1448 #define INDEX_REG_CLASS INDEX_REGS
1449 #define BASE_REG_CLASS GENERAL_REGS
1451 /* Get reg_class from a letter such as appears in the machine description. */
1453 #define REG_CLASS_FROM_LETTER(C) \
1454 ((C) == 'r' ? GENERAL_REGS : \
1455 (C) == 'R' ? LEGACY_REGS : \
1456 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1457 (C) == 'Q' ? Q_REGS : \
1458 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1461 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1464 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1467 (C) == 'a' ? AREG : \
1468 (C) == 'b' ? BREG : \
1469 (C) == 'c' ? CREG : \
1470 (C) == 'd' ? DREG : \
1471 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1472 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1473 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1474 (C) == 'A' ? AD_REGS : \
1475 (C) == 'D' ? DIREG : \
1476 (C) == 'S' ? SIREG : NO_REGS)
1478 /* The letters I, J, K, L and M in a register constraint string
1479 can be used to stand for particular ranges of immediate operands.
1480 This macro defines what the ranges are.
1481 C is the letter, and VALUE is a constant value.
1482 Return 1 if VALUE is in the range specified by C.
1484 I is for non-DImode shifts.
1485 J is for DImode shifts.
1486 K is for signed imm8 operands.
1487 L is for andsi as zero-extending move.
1488 M is for shifts that can be executed by the "lea" opcode.
1489 N is for immediate operands for out/in instructions (0-255)
1492 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1493 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1494 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1495 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1496 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1497 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1498 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1501 /* Similar, but for floating constants, and defining letters G and H.
1502 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1503 TARGET_387 isn't set, because the stack register converter may need to
1504 load 0.0 into the function value register. */
1506 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1507 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1510 /* A C expression that defines the optional machine-dependent
1511 constraint letters that can be used to segregate specific types of
1512 operands, usually memory references, for the target machine. Any
1513 letter that is not elsewhere defined and not matched by
1514 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1517 If it is required for a particular target machine, it should
1518 return 1 if VALUE corresponds to the operand type represented by
1519 the constraint letter C. If C is not defined as an extra
1520 constraint, the value returned should be 0 regardless of VALUE. */
1522 #define EXTRA_CONSTRAINT(VALUE, D) \
1523 ((D) == 'e' ? x86_64_sign_extended_value (VALUE) \
1524 : (D) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1525 : (D) == 'C' ? standard_sse_constant_p (VALUE) \
1528 /* Place additional restrictions on the register class to use when it
1529 is necessary to be able to hold a value of mode MODE in a reload
1530 register for which class CLASS would ordinarily be used. */
1532 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1533 ((MODE) == QImode && !TARGET_64BIT \
1534 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1535 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1538 /* Given an rtx X being reloaded into a reg required to be
1539 in class CLASS, return the class of reg to actually use.
1540 In general this is just CLASS; but on some machines
1541 in some cases it is preferable to use a more restrictive class.
1542 On the 80386 series, we prevent floating constants from being
1543 reloaded into floating registers (since no move-insn can do that)
1544 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1546 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1547 QImode must go into class Q_REGS.
1548 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1549 movdf to do mem-to-mem moves through integer regs. */
1551 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1552 ix86_preferred_reload_class ((X), (CLASS))
1554 /* If we are copying between general and FP registers, we need a memory
1555 location. The same is true for SSE and MMX registers. */
1556 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1557 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1559 /* QImode spills from non-QI registers need a scratch. This does not
1560 happen often -- the only example so far requires an uninitialized
1563 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1564 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1565 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1568 /* Return the maximum number of consecutive registers
1569 needed to represent mode MODE in a register of class CLASS. */
1570 /* On the 80386, this is the size of MODE in words,
1571 except in the FP regs, where a single reg is always enough.
1572 The TFmodes are really just 80bit values, so we use only 3 registers
1573 to hold them, instead of 4, as the size would suggest.
1575 #define CLASS_MAX_NREGS(CLASS, MODE) \
1576 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1577 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1578 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1579 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1581 /* A C expression whose value is nonzero if pseudos that have been
1582 assigned to registers of class CLASS would likely be spilled
1583 because registers of CLASS are needed for spill registers.
1585 The default value of this macro returns 1 if CLASS has exactly one
1586 register and zero otherwise. On most machines, this default
1587 should be used. Only define this macro to some other expression
1588 if pseudo allocated by `local-alloc.c' end up in memory because
1589 their hard registers were needed for spill registers. If this
1590 macro returns nonzero for those classes, those pseudos will only
1591 be allocated by `global.c', which knows how to reallocate the
1592 pseudo to another register. If there would not be another
1593 register available for reallocation, you should not change the
1594 definition of this macro since the only effect of such a
1595 definition would be to slow down register allocation. */
1597 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1598 (((CLASS) == AREG) \
1599 || ((CLASS) == DREG) \
1600 || ((CLASS) == CREG) \
1601 || ((CLASS) == BREG) \
1602 || ((CLASS) == AD_REGS) \
1603 || ((CLASS) == SIREG) \
1604 || ((CLASS) == DIREG))
1606 /* Return a class of registers that cannot change FROM mode to TO mode.
1608 x87 registers can't do subreg as all values are reformated to extended
1609 precision. XMM registers does not support with nonzero offsets equal
1610 to 4, 8 and 12 otherwise valid for integer registers. Since we can't
1611 determine these, prohibit all nonparadoxical subregs changing size. */
1613 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1614 (GET_MODE_SIZE (TO) < GET_MODE_SIZE (FROM) \
1615 ? reg_classes_intersect_p (FLOAT_SSE_REGS, (CLASS)) \
1616 || MAYBE_MMX_CLASS_P (CLASS) \
1617 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1618 ? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0)
1620 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1621 to automatically clobber for all asms.
1623 We do this in the new i386 backend to maintain source compatibility
1624 with the old cc0-based compiler. */
1626 #define MD_ASM_CLOBBERS(CLOBBERS) \
1628 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1630 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1632 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1636 /* Stack layout; function entry, exit and calling. */
1638 /* Define this if pushing a word on the stack
1639 makes the stack pointer a smaller address. */
1640 #define STACK_GROWS_DOWNWARD
1642 /* Define this if the nominal address of the stack frame
1643 is at the high-address end of the local variables;
1644 that is, each additional local variable allocated
1645 goes at a more negative offset in the frame. */
1646 #define FRAME_GROWS_DOWNWARD
1648 /* Offset within stack frame to start allocating local variables at.
1649 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1650 first local allocated. Otherwise, it is the offset to the BEGINNING
1651 of the first local allocated. */
1652 #define STARTING_FRAME_OFFSET 0
1654 /* If we generate an insn to push BYTES bytes,
1655 this says how many the stack pointer really advances by.
1656 On 386 pushw decrements by exactly 2 no matter what the position was.
1657 On the 386 there is no pushb; we use pushw instead, and this
1658 has the effect of rounding up to 2.
1660 For 64bit ABI we round up to 8 bytes.
1663 #define PUSH_ROUNDING(BYTES) \
1665 ? (((BYTES) + 7) & (-8)) \
1666 : (((BYTES) + 1) & (-2)))
1668 /* If defined, the maximum amount of space required for outgoing arguments will
1669 be computed and placed into the variable
1670 `current_function_outgoing_args_size'. No space will be pushed onto the
1671 stack for each call; instead, the function prologue should increase the stack
1672 frame size by this amount. */
1674 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1676 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1677 instructions to pass outgoing arguments. */
1679 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1681 /* We want the stack and args grow in opposite directions, even if
1683 #define PUSH_ARGS_REVERSED 1
1685 /* Offset of first parameter from the argument pointer register value. */
1686 #define FIRST_PARM_OFFSET(FNDECL) 0
1688 /* Define this macro if functions should assume that stack space has been
1689 allocated for arguments even when their values are passed in registers.
1691 The value of this macro is the size, in bytes, of the area reserved for
1692 arguments passed in registers for the function represented by FNDECL.
1694 This space can be allocated by the caller, or be a part of the
1695 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1697 #define REG_PARM_STACK_SPACE(FNDECL) 0
1699 /* Define as a C expression that evaluates to nonzero if we do not know how
1700 to pass TYPE solely in registers. The file expr.h defines a
1701 definition that is usually appropriate, refer to expr.h for additional
1702 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1703 computed in the stack and then loaded into a register. */
1704 #define MUST_PASS_IN_STACK(MODE, TYPE) ix86_must_pass_in_stack ((MODE), (TYPE))
1706 /* Value is the number of bytes of arguments automatically
1707 popped when returning from a subroutine call.
1708 FUNDECL is the declaration node of the function (as a tree),
1709 FUNTYPE is the data type of the function (as a tree),
1710 or for a library call it is an identifier node for the subroutine name.
1711 SIZE is the number of bytes of arguments passed on the stack.
1713 On the 80386, the RTD insn may be used to pop them if the number
1714 of args is fixed, but if the number is variable then the caller
1715 must pop them all. RTD can't be used for library calls now
1716 because the library is compiled with the Unix compiler.
1717 Use of RTD is a selectable option, since it is incompatible with
1718 standard Unix calling sequences. If the option is not selected,
1719 the caller must always pop the args.
1721 The attribute stdcall is equivalent to RTD on a per module basis. */
1723 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1724 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1726 /* Define how to find the value returned by a function.
1727 VALTYPE is the data type of the value (as a tree).
1728 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1729 otherwise, FUNC is 0. */
1730 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1731 ix86_function_value (VALTYPE)
1733 #define FUNCTION_VALUE_REGNO_P(N) \
1734 ix86_function_value_regno_p (N)
1736 /* Define how to find the value returned by a library function
1737 assuming the value has mode MODE. */
1739 #define LIBCALL_VALUE(MODE) \
1740 ix86_libcall_value (MODE)
1742 /* Define the size of the result block used for communication between
1743 untyped_call and untyped_return. The block contains a DImode value
1744 followed by the block used by fnsave and frstor. */
1746 #define APPLY_RESULT_SIZE (8+108)
1748 /* 1 if N is a possible register number for function argument passing. */
1749 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1751 /* Define a data type for recording info about an argument list
1752 during the scan of that argument list. This data type should
1753 hold all necessary information about the function itself
1754 and about the args processed so far, enough to enable macros
1755 such as FUNCTION_ARG to determine where the next arg should go. */
1757 typedef struct ix86_args {
1758 int words; /* # words passed so far */
1759 int nregs; /* # registers available for passing */
1760 int regno; /* next available register number */
1761 int fastcall; /* fastcall calling convention is used */
1762 int sse_words; /* # sse words passed so far */
1763 int sse_nregs; /* # sse registers available for passing */
1764 int sse_regno; /* next available sse register number */
1765 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1768 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1769 for a call to a function whose data type is FNTYPE.
1770 For a library call, FNTYPE is 0. */
1772 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
1773 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1775 /* Update the data in CUM to advance over an argument
1776 of mode MODE and data type TYPE.
1777 (TYPE is null for libcalls where that information may not be available.) */
1779 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1780 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1782 /* Define where to put the arguments to a function.
1783 Value is zero to push the argument on the stack,
1784 or a hard register in which to store the argument.
1786 MODE is the argument's machine mode.
1787 TYPE is the data type of the argument (as a tree).
1788 This is null for libcalls where that information may
1790 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1791 the preceding args and about the function being called.
1792 NAMED is nonzero if this argument is a named parameter
1793 (otherwise it is an extra parameter matching an ellipsis). */
1795 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1796 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1798 /* For an arg passed partly in registers and partly in memory,
1799 this is the number of registers used.
1800 For args passed entirely in registers or entirely in memory, zero. */
1802 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1804 /* A C expression that indicates when an argument must be passed by
1805 reference. If nonzero for an argument, a copy of that argument is
1806 made in memory and a pointer to the argument is passed instead of
1807 the argument itself. The pointer is passed in whatever way is
1808 appropriate for passing a pointer to that type. */
1810 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1811 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1813 /* Perform any needed actions needed for a function that is receiving a
1814 variable number of arguments.
1818 MODE and TYPE are the mode and type of the current parameter.
1820 PRETEND_SIZE is a variable that should be set to the amount of stack
1821 that must be pushed by the prolog to pretend that our caller pushed
1824 Normally, this macro will push all remaining incoming registers on the
1825 stack and set PRETEND_SIZE to the length of the registers pushed. */
1827 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1828 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1831 /* Implement `va_start' for varargs and stdarg. */
1832 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1833 ix86_va_start (VALIST, NEXTARG)
1835 /* Implement `va_arg'. */
1836 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1837 ix86_va_arg ((VALIST), (TYPE))
1839 #define TARGET_ASM_FILE_END ix86_file_end
1840 #define NEED_INDICATE_EXEC_STACK 0
1842 /* Output assembler code to FILE to increment profiler label # LABELNO
1843 for profiling a function entry. */
1845 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1847 #define MCOUNT_NAME "_mcount"
1849 #define PROFILE_COUNT_REGISTER "edx"
1851 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1852 the stack pointer does not matter. The value is tested only in
1853 functions that have frame pointers.
1854 No definition is equivalent to always zero. */
1855 /* Note on the 386 it might be more efficient not to define this since
1856 we have to restore it ourselves from the frame pointer, in order to
1859 #define EXIT_IGNORE_STACK 1
1861 /* Output assembler code for a block containing the constant parts
1862 of a trampoline, leaving space for the variable parts. */
1864 /* On the 386, the trampoline contains two instructions:
1867 The trampoline is generated entirely at runtime. The operand of JMP
1868 is the address of FUNCTION relative to the instruction following the
1869 JMP (which is 5 bytes long). */
1871 /* Length in units of the trampoline for entering a nested function. */
1873 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1875 /* Emit RTL insns to initialize the variable parts of a trampoline.
1876 FNADDR is an RTX for the address of the function's pure code.
1877 CXT is an RTX for the static chain value for the function. */
1879 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1880 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1882 /* Definitions for register eliminations.
1884 This is an array of structures. Each structure initializes one pair
1885 of eliminable registers. The "from" register number is given first,
1886 followed by "to". Eliminations of the same "from" register are listed
1887 in order of preference.
1889 There are two registers that can always be eliminated on the i386.
1890 The frame pointer and the arg pointer can be replaced by either the
1891 hard frame pointer or to the stack pointer, depending upon the
1892 circumstances. The hard frame pointer is not used before reload and
1893 so it is not eligible for elimination. */
1895 #define ELIMINABLE_REGS \
1896 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1897 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1898 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1899 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1901 /* Given FROM and TO register numbers, say whether this elimination is
1902 allowed. Frame pointer elimination is automatically handled.
1904 All other eliminations are valid. */
1906 #define CAN_ELIMINATE(FROM, TO) \
1907 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1909 /* Define the offset between two registers, one to be eliminated, and the other
1910 its replacement, at the start of a routine. */
1912 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1913 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1915 /* Addressing modes, and classification of registers for them. */
1917 /* Macros to check register numbers against specific register classes. */
1919 /* These assume that REGNO is a hard or pseudo reg number.
1920 They give nonzero only if REGNO is a hard reg of the suitable class
1921 or a pseudo reg currently allocated to a suitable hard reg.
1922 Since they use reg_renumber, they are safe only once reg_renumber
1923 has been allocated, which happens in local-alloc.c. */
1925 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1926 ((REGNO) < STACK_POINTER_REGNUM \
1927 || (REGNO >= FIRST_REX_INT_REG \
1928 && (REGNO) <= LAST_REX_INT_REG) \
1929 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1930 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1931 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1933 #define REGNO_OK_FOR_BASE_P(REGNO) \
1934 ((REGNO) <= STACK_POINTER_REGNUM \
1935 || (REGNO) == ARG_POINTER_REGNUM \
1936 || (REGNO) == FRAME_POINTER_REGNUM \
1937 || (REGNO >= FIRST_REX_INT_REG \
1938 && (REGNO) <= LAST_REX_INT_REG) \
1939 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1940 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1941 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1943 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1944 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1945 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1946 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1948 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1949 and check its validity for a certain class.
1950 We have two alternate definitions for each of them.
1951 The usual definition accepts all pseudo regs; the other rejects
1952 them unless they have been allocated suitable hard regs.
1953 The symbol REG_OK_STRICT causes the latter definition to be used.
1955 Most source files want to accept pseudo regs in the hope that
1956 they will get allocated to the class that the insn wants them to be in.
1957 Source files for reload pass need to be strict.
1958 After reload, it makes no difference, since pseudo regs have
1959 been eliminated by then. */
1962 /* Non strict versions, pseudos are ok */
1963 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1964 (REGNO (X) < STACK_POINTER_REGNUM \
1965 || (REGNO (X) >= FIRST_REX_INT_REG \
1966 && REGNO (X) <= LAST_REX_INT_REG) \
1967 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1969 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1970 (REGNO (X) <= STACK_POINTER_REGNUM \
1971 || REGNO (X) == ARG_POINTER_REGNUM \
1972 || REGNO (X) == FRAME_POINTER_REGNUM \
1973 || (REGNO (X) >= FIRST_REX_INT_REG \
1974 && REGNO (X) <= LAST_REX_INT_REG) \
1975 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1977 /* Strict versions, hard registers only */
1978 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1979 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1981 #ifndef REG_OK_STRICT
1982 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1983 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1986 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1987 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1990 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1991 that is a valid memory address for an instruction.
1992 The MODE argument is the machine mode for the MEM expression
1993 that wants to use this address.
1995 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1996 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1998 See legitimize_pic_address in i386.c for details as to what
1999 constitutes a legitimate address when -fpic is used. */
2001 #define MAX_REGS_PER_ADDRESS 2
2003 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
2005 /* Nonzero if the constant value X is a legitimate general operand.
2006 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2008 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
2010 #ifdef REG_OK_STRICT
2011 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2013 if (legitimate_address_p ((MODE), (X), 1)) \
2018 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2020 if (legitimate_address_p ((MODE), (X), 0)) \
2026 /* If defined, a C expression to determine the base term of address X.
2027 This macro is used in only one place: `find_base_term' in alias.c.
2029 It is always safe for this macro to not be defined. It exists so
2030 that alias analysis can understand machine-dependent addresses.
2032 The typical use of this macro is to handle addresses containing
2033 a label_ref or symbol_ref within an UNSPEC. */
2035 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
2037 /* Try machine-dependent ways of modifying an illegitimate address
2038 to be legitimate. If we find one, return the new, valid address.
2039 This macro is used in only one place: `memory_address' in explow.c.
2041 OLDX is the address as it was before break_out_memory_refs was called.
2042 In some cases it is useful to look at this to decide what needs to be done.
2044 MODE and WIN are passed so that this macro can use
2045 GO_IF_LEGITIMATE_ADDRESS.
2047 It is always safe for this macro to do nothing. It exists to recognize
2048 opportunities to optimize the output.
2050 For the 80386, we handle X+REG by loading X into a register R and
2051 using R+REG. R will go in a general reg and indexing will be used.
2052 However, if REG is a broken-out memory address or multiplication,
2053 nothing needs to be done because REG can certainly go in a general reg.
2055 When -fpic is used, special handling is needed for symbolic references.
2056 See comments by legitimize_pic_address in i386.c for details. */
2058 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2060 (X) = legitimize_address ((X), (OLDX), (MODE)); \
2061 if (memory_address_p ((MODE), (X))) \
2065 #define REWRITE_ADDRESS(X) rewrite_address (X)
2067 /* Nonzero if the constant value X is a legitimate general operand
2068 when generating PIC code. It is given that flag_pic is on and
2069 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2071 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
2073 #define SYMBOLIC_CONST(X) \
2074 (GET_CODE (X) == SYMBOL_REF \
2075 || GET_CODE (X) == LABEL_REF \
2076 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2078 /* Go to LABEL if ADDR (a legitimate address expression)
2079 has an effect that depends on the machine mode it is used for.
2080 On the 80386, only postdecrement and postincrement address depend thus
2081 (the amount of decrement or increment being the length of the operand). */
2082 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2084 if (GET_CODE (ADDR) == POST_INC \
2085 || GET_CODE (ADDR) == POST_DEC) \
2089 /* Codes for all the SSE/MMX builtins. */
2101 IX86_BUILTIN_CMPEQPS,
2102 IX86_BUILTIN_CMPLTPS,
2103 IX86_BUILTIN_CMPLEPS,
2104 IX86_BUILTIN_CMPGTPS,
2105 IX86_BUILTIN_CMPGEPS,
2106 IX86_BUILTIN_CMPNEQPS,
2107 IX86_BUILTIN_CMPNLTPS,
2108 IX86_BUILTIN_CMPNLEPS,
2109 IX86_BUILTIN_CMPNGTPS,
2110 IX86_BUILTIN_CMPNGEPS,
2111 IX86_BUILTIN_CMPORDPS,
2112 IX86_BUILTIN_CMPUNORDPS,
2113 IX86_BUILTIN_CMPNEPS,
2114 IX86_BUILTIN_CMPEQSS,
2115 IX86_BUILTIN_CMPLTSS,
2116 IX86_BUILTIN_CMPLESS,
2117 IX86_BUILTIN_CMPNEQSS,
2118 IX86_BUILTIN_CMPNLTSS,
2119 IX86_BUILTIN_CMPNLESS,
2120 IX86_BUILTIN_CMPORDSS,
2121 IX86_BUILTIN_CMPUNORDSS,
2122 IX86_BUILTIN_CMPNESS,
2124 IX86_BUILTIN_COMIEQSS,
2125 IX86_BUILTIN_COMILTSS,
2126 IX86_BUILTIN_COMILESS,
2127 IX86_BUILTIN_COMIGTSS,
2128 IX86_BUILTIN_COMIGESS,
2129 IX86_BUILTIN_COMINEQSS,
2130 IX86_BUILTIN_UCOMIEQSS,
2131 IX86_BUILTIN_UCOMILTSS,
2132 IX86_BUILTIN_UCOMILESS,
2133 IX86_BUILTIN_UCOMIGTSS,
2134 IX86_BUILTIN_UCOMIGESS,
2135 IX86_BUILTIN_UCOMINEQSS,
2137 IX86_BUILTIN_CVTPI2PS,
2138 IX86_BUILTIN_CVTPS2PI,
2139 IX86_BUILTIN_CVTSI2SS,
2140 IX86_BUILTIN_CVTSI642SS,
2141 IX86_BUILTIN_CVTSS2SI,
2142 IX86_BUILTIN_CVTSS2SI64,
2143 IX86_BUILTIN_CVTTPS2PI,
2144 IX86_BUILTIN_CVTTSS2SI,
2145 IX86_BUILTIN_CVTTSS2SI64,
2152 IX86_BUILTIN_LOADAPS,
2153 IX86_BUILTIN_LOADUPS,
2154 IX86_BUILTIN_STOREAPS,
2155 IX86_BUILTIN_STOREUPS,
2156 IX86_BUILTIN_LOADSS,
2157 IX86_BUILTIN_STORESS,
2160 IX86_BUILTIN_MOVHLPS,
2161 IX86_BUILTIN_MOVLHPS,
2162 IX86_BUILTIN_LOADHPS,
2163 IX86_BUILTIN_LOADLPS,
2164 IX86_BUILTIN_STOREHPS,
2165 IX86_BUILTIN_STORELPS,
2167 IX86_BUILTIN_MASKMOVQ,
2168 IX86_BUILTIN_MOVMSKPS,
2169 IX86_BUILTIN_PMOVMSKB,
2171 IX86_BUILTIN_MOVNTPS,
2172 IX86_BUILTIN_MOVNTQ,
2174 IX86_BUILTIN_LOADDQA,
2175 IX86_BUILTIN_LOADDQU,
2176 IX86_BUILTIN_STOREDQA,
2177 IX86_BUILTIN_STOREDQU,
2180 IX86_BUILTIN_STORED,
2184 IX86_BUILTIN_PACKSSWB,
2185 IX86_BUILTIN_PACKSSDW,
2186 IX86_BUILTIN_PACKUSWB,
2192 IX86_BUILTIN_PADDSB,
2193 IX86_BUILTIN_PADDSW,
2194 IX86_BUILTIN_PADDUSB,
2195 IX86_BUILTIN_PADDUSW,
2200 IX86_BUILTIN_PSUBSB,
2201 IX86_BUILTIN_PSUBSW,
2202 IX86_BUILTIN_PSUBUSB,
2203 IX86_BUILTIN_PSUBUSW,
2213 IX86_BUILTIN_PCMPEQB,
2214 IX86_BUILTIN_PCMPEQW,
2215 IX86_BUILTIN_PCMPEQD,
2216 IX86_BUILTIN_PCMPGTB,
2217 IX86_BUILTIN_PCMPGTW,
2218 IX86_BUILTIN_PCMPGTD,
2220 IX86_BUILTIN_PEXTRW,
2221 IX86_BUILTIN_PINSRW,
2223 IX86_BUILTIN_PMADDWD,
2225 IX86_BUILTIN_PMAXSW,
2226 IX86_BUILTIN_PMAXUB,
2227 IX86_BUILTIN_PMINSW,
2228 IX86_BUILTIN_PMINUB,
2230 IX86_BUILTIN_PMULHUW,
2231 IX86_BUILTIN_PMULHW,
2232 IX86_BUILTIN_PMULLW,
2234 IX86_BUILTIN_PSADBW,
2235 IX86_BUILTIN_PSHUFW,
2245 IX86_BUILTIN_PSLLWI,
2246 IX86_BUILTIN_PSLLDI,
2247 IX86_BUILTIN_PSLLQI,
2248 IX86_BUILTIN_PSRAWI,
2249 IX86_BUILTIN_PSRADI,
2250 IX86_BUILTIN_PSRLWI,
2251 IX86_BUILTIN_PSRLDI,
2252 IX86_BUILTIN_PSRLQI,
2254 IX86_BUILTIN_PUNPCKHBW,
2255 IX86_BUILTIN_PUNPCKHWD,
2256 IX86_BUILTIN_PUNPCKHDQ,
2257 IX86_BUILTIN_PUNPCKLBW,
2258 IX86_BUILTIN_PUNPCKLWD,
2259 IX86_BUILTIN_PUNPCKLDQ,
2261 IX86_BUILTIN_SHUFPS,
2265 IX86_BUILTIN_RSQRTPS,
2266 IX86_BUILTIN_RSQRTSS,
2267 IX86_BUILTIN_SQRTPS,
2268 IX86_BUILTIN_SQRTSS,
2270 IX86_BUILTIN_UNPCKHPS,
2271 IX86_BUILTIN_UNPCKLPS,
2274 IX86_BUILTIN_ANDNPS,
2279 IX86_BUILTIN_LDMXCSR,
2280 IX86_BUILTIN_STMXCSR,
2281 IX86_BUILTIN_SFENCE,
2283 /* 3DNow! Original */
2285 IX86_BUILTIN_PAVGUSB,
2289 IX86_BUILTIN_PFCMPEQ,
2290 IX86_BUILTIN_PFCMPGE,
2291 IX86_BUILTIN_PFCMPGT,
2296 IX86_BUILTIN_PFRCPIT1,
2297 IX86_BUILTIN_PFRCPIT2,
2298 IX86_BUILTIN_PFRSQIT1,
2299 IX86_BUILTIN_PFRSQRT,
2301 IX86_BUILTIN_PFSUBR,
2303 IX86_BUILTIN_PMULHRW,
2305 /* 3DNow! Athlon Extensions */
2307 IX86_BUILTIN_PFNACC,
2308 IX86_BUILTIN_PFPNACC,
2310 IX86_BUILTIN_PSWAPDSI,
2311 IX86_BUILTIN_PSWAPDSF,
2313 IX86_BUILTIN_SSE_ZERO,
2314 IX86_BUILTIN_MMX_ZERO,
2326 IX86_BUILTIN_CMPEQPD,
2327 IX86_BUILTIN_CMPLTPD,
2328 IX86_BUILTIN_CMPLEPD,
2329 IX86_BUILTIN_CMPGTPD,
2330 IX86_BUILTIN_CMPGEPD,
2331 IX86_BUILTIN_CMPNEQPD,
2332 IX86_BUILTIN_CMPNLTPD,
2333 IX86_BUILTIN_CMPNLEPD,
2334 IX86_BUILTIN_CMPNGTPD,
2335 IX86_BUILTIN_CMPNGEPD,
2336 IX86_BUILTIN_CMPORDPD,
2337 IX86_BUILTIN_CMPUNORDPD,
2338 IX86_BUILTIN_CMPNEPD,
2339 IX86_BUILTIN_CMPEQSD,
2340 IX86_BUILTIN_CMPLTSD,
2341 IX86_BUILTIN_CMPLESD,
2342 IX86_BUILTIN_CMPNEQSD,
2343 IX86_BUILTIN_CMPNLTSD,
2344 IX86_BUILTIN_CMPNLESD,
2345 IX86_BUILTIN_CMPORDSD,
2346 IX86_BUILTIN_CMPUNORDSD,
2347 IX86_BUILTIN_CMPNESD,
2349 IX86_BUILTIN_COMIEQSD,
2350 IX86_BUILTIN_COMILTSD,
2351 IX86_BUILTIN_COMILESD,
2352 IX86_BUILTIN_COMIGTSD,
2353 IX86_BUILTIN_COMIGESD,
2354 IX86_BUILTIN_COMINEQSD,
2355 IX86_BUILTIN_UCOMIEQSD,
2356 IX86_BUILTIN_UCOMILTSD,
2357 IX86_BUILTIN_UCOMILESD,
2358 IX86_BUILTIN_UCOMIGTSD,
2359 IX86_BUILTIN_UCOMIGESD,
2360 IX86_BUILTIN_UCOMINEQSD,
2368 IX86_BUILTIN_ANDNPD,
2372 IX86_BUILTIN_SQRTPD,
2373 IX86_BUILTIN_SQRTSD,
2375 IX86_BUILTIN_UNPCKHPD,
2376 IX86_BUILTIN_UNPCKLPD,
2378 IX86_BUILTIN_SHUFPD,
2380 IX86_BUILTIN_LOADAPD,
2381 IX86_BUILTIN_LOADUPD,
2382 IX86_BUILTIN_STOREAPD,
2383 IX86_BUILTIN_STOREUPD,
2384 IX86_BUILTIN_LOADSD,
2385 IX86_BUILTIN_STORESD,
2388 IX86_BUILTIN_LOADHPD,
2389 IX86_BUILTIN_LOADLPD,
2390 IX86_BUILTIN_STOREHPD,
2391 IX86_BUILTIN_STORELPD,
2393 IX86_BUILTIN_CVTDQ2PD,
2394 IX86_BUILTIN_CVTDQ2PS,
2396 IX86_BUILTIN_CVTPD2DQ,
2397 IX86_BUILTIN_CVTPD2PI,
2398 IX86_BUILTIN_CVTPD2PS,
2399 IX86_BUILTIN_CVTTPD2DQ,
2400 IX86_BUILTIN_CVTTPD2PI,
2402 IX86_BUILTIN_CVTPI2PD,
2403 IX86_BUILTIN_CVTSI2SD,
2404 IX86_BUILTIN_CVTSI642SD,
2406 IX86_BUILTIN_CVTSD2SI,
2407 IX86_BUILTIN_CVTSD2SI64,
2408 IX86_BUILTIN_CVTSD2SS,
2409 IX86_BUILTIN_CVTSS2SD,
2410 IX86_BUILTIN_CVTTSD2SI,
2411 IX86_BUILTIN_CVTTSD2SI64,
2413 IX86_BUILTIN_CVTPS2DQ,
2414 IX86_BUILTIN_CVTPS2PD,
2415 IX86_BUILTIN_CVTTPS2DQ,
2417 IX86_BUILTIN_MOVNTI,
2418 IX86_BUILTIN_MOVNTPD,
2419 IX86_BUILTIN_MOVNTDQ,
2421 IX86_BUILTIN_SETPD1,
2424 IX86_BUILTIN_SETRPD,
2425 IX86_BUILTIN_LOADPD1,
2426 IX86_BUILTIN_LOADRPD,
2427 IX86_BUILTIN_STOREPD1,
2428 IX86_BUILTIN_STORERPD,
2431 IX86_BUILTIN_MASKMOVDQU,
2432 IX86_BUILTIN_MOVMSKPD,
2433 IX86_BUILTIN_PMOVMSKB128,
2434 IX86_BUILTIN_MOVQ2DQ,
2435 IX86_BUILTIN_MOVDQ2Q,
2437 IX86_BUILTIN_PACKSSWB128,
2438 IX86_BUILTIN_PACKSSDW128,
2439 IX86_BUILTIN_PACKUSWB128,
2441 IX86_BUILTIN_PADDB128,
2442 IX86_BUILTIN_PADDW128,
2443 IX86_BUILTIN_PADDD128,
2444 IX86_BUILTIN_PADDQ128,
2445 IX86_BUILTIN_PADDSB128,
2446 IX86_BUILTIN_PADDSW128,
2447 IX86_BUILTIN_PADDUSB128,
2448 IX86_BUILTIN_PADDUSW128,
2449 IX86_BUILTIN_PSUBB128,
2450 IX86_BUILTIN_PSUBW128,
2451 IX86_BUILTIN_PSUBD128,
2452 IX86_BUILTIN_PSUBQ128,
2453 IX86_BUILTIN_PSUBSB128,
2454 IX86_BUILTIN_PSUBSW128,
2455 IX86_BUILTIN_PSUBUSB128,
2456 IX86_BUILTIN_PSUBUSW128,
2458 IX86_BUILTIN_PAND128,
2459 IX86_BUILTIN_PANDN128,
2460 IX86_BUILTIN_POR128,
2461 IX86_BUILTIN_PXOR128,
2463 IX86_BUILTIN_PAVGB128,
2464 IX86_BUILTIN_PAVGW128,
2466 IX86_BUILTIN_PCMPEQB128,
2467 IX86_BUILTIN_PCMPEQW128,
2468 IX86_BUILTIN_PCMPEQD128,
2469 IX86_BUILTIN_PCMPGTB128,
2470 IX86_BUILTIN_PCMPGTW128,
2471 IX86_BUILTIN_PCMPGTD128,
2473 IX86_BUILTIN_PEXTRW128,
2474 IX86_BUILTIN_PINSRW128,
2476 IX86_BUILTIN_PMADDWD128,
2478 IX86_BUILTIN_PMAXSW128,
2479 IX86_BUILTIN_PMAXUB128,
2480 IX86_BUILTIN_PMINSW128,
2481 IX86_BUILTIN_PMINUB128,
2483 IX86_BUILTIN_PMULUDQ,
2484 IX86_BUILTIN_PMULUDQ128,
2485 IX86_BUILTIN_PMULHUW128,
2486 IX86_BUILTIN_PMULHW128,
2487 IX86_BUILTIN_PMULLW128,
2489 IX86_BUILTIN_PSADBW128,
2490 IX86_BUILTIN_PSHUFHW,
2491 IX86_BUILTIN_PSHUFLW,
2492 IX86_BUILTIN_PSHUFD,
2494 IX86_BUILTIN_PSLLW128,
2495 IX86_BUILTIN_PSLLD128,
2496 IX86_BUILTIN_PSLLQ128,
2497 IX86_BUILTIN_PSRAW128,
2498 IX86_BUILTIN_PSRAD128,
2499 IX86_BUILTIN_PSRLW128,
2500 IX86_BUILTIN_PSRLD128,
2501 IX86_BUILTIN_PSRLQ128,
2502 IX86_BUILTIN_PSLLDQI128,
2503 IX86_BUILTIN_PSLLWI128,
2504 IX86_BUILTIN_PSLLDI128,
2505 IX86_BUILTIN_PSLLQI128,
2506 IX86_BUILTIN_PSRAWI128,
2507 IX86_BUILTIN_PSRADI128,
2508 IX86_BUILTIN_PSRLDQI128,
2509 IX86_BUILTIN_PSRLWI128,
2510 IX86_BUILTIN_PSRLDI128,
2511 IX86_BUILTIN_PSRLQI128,
2513 IX86_BUILTIN_PUNPCKHBW128,
2514 IX86_BUILTIN_PUNPCKHWD128,
2515 IX86_BUILTIN_PUNPCKHDQ128,
2516 IX86_BUILTIN_PUNPCKHQDQ128,
2517 IX86_BUILTIN_PUNPCKLBW128,
2518 IX86_BUILTIN_PUNPCKLWD128,
2519 IX86_BUILTIN_PUNPCKLDQ128,
2520 IX86_BUILTIN_PUNPCKLQDQ128,
2522 IX86_BUILTIN_CLFLUSH,
2523 IX86_BUILTIN_MFENCE,
2524 IX86_BUILTIN_LFENCE,
2526 /* Prescott New Instructions. */
2527 IX86_BUILTIN_ADDSUBPS,
2528 IX86_BUILTIN_HADDPS,
2529 IX86_BUILTIN_HSUBPS,
2530 IX86_BUILTIN_MOVSHDUP,
2531 IX86_BUILTIN_MOVSLDUP,
2532 IX86_BUILTIN_ADDSUBPD,
2533 IX86_BUILTIN_HADDPD,
2534 IX86_BUILTIN_HSUBPD,
2535 IX86_BUILTIN_LOADDDUP,
2536 IX86_BUILTIN_MOVDDUP,
2539 IX86_BUILTIN_MONITOR,
2545 /* Max number of args passed in registers. If this is more than 3, we will
2546 have problems with ebx (register #4), since it is a caller save register and
2547 is also used as the pic register in ELF. So for now, don't allow more than
2548 3 registers to be passed in registers. */
2550 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2552 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2555 /* Specify the machine mode that this machine uses
2556 for the index in the tablejump instruction. */
2557 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2559 /* Define as C expression which evaluates to nonzero if the tablejump
2560 instruction expects the table to contain offsets from the address of the
2562 Do not define this if the table should contain absolute addresses. */
2563 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2565 /* Define this as 1 if `char' should by default be signed; else as 0. */
2566 #define DEFAULT_SIGNED_CHAR 1
2568 /* Number of bytes moved into a data cache for a single prefetch operation. */
2569 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2571 /* Number of prefetch operations that can be done in parallel. */
2572 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2574 /* Max number of bytes we can move from memory to memory
2575 in one reasonably fast instruction. */
2578 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2579 move efficiently, as opposed to MOVE_MAX which is the maximum
2580 number of bytes we can move with a single instruction. */
2581 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2583 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2584 move-instruction pairs, we will do a movstr or libcall instead.
2585 Increasing the value will always make code faster, but eventually
2586 incurs high cost in increased code size.
2588 If you don't define this, a reasonable default is used. */
2590 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2592 /* Define if shifts truncate the shift count
2593 which implies one can omit a sign-extension or zero-extension
2594 of a shift count. */
2595 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2597 /* #define SHIFT_COUNT_TRUNCATED */
2599 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2600 is done just by pretending it is already truncated. */
2601 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2603 /* When a prototype says `char' or `short', really pass an `int'.
2604 (The 386 can't easily push less than an int.) */
2606 #define PROMOTE_PROTOTYPES 1
2608 /* A macro to update M and UNSIGNEDP when an object whose type is
2609 TYPE and which has the specified mode and signedness is to be
2610 stored in a register. This macro is only called when TYPE is a
2613 On i386 it is sometimes useful to promote HImode and QImode
2614 quantities to SImode. The choice depends on target type. */
2616 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2618 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2619 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2623 /* Specify the machine mode that pointers have.
2624 After generation of rtl, the compiler makes no further distinction
2625 between pointers and any other objects of this machine mode. */
2626 #define Pmode (TARGET_64BIT ? DImode : SImode)
2628 /* A function address in a call instruction
2629 is a byte address (for indexing purposes)
2630 so give the MEM rtx a byte's mode. */
2631 #define FUNCTION_MODE QImode
2633 /* A C expression for the cost of moving data from a register in class FROM to
2634 one in class TO. The classes are expressed using the enumeration values
2635 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2636 interpreted relative to that.
2638 It is not required that the cost always equal 2 when FROM is the same as TO;
2639 on some machines it is expensive to move between registers if they are not
2640 general registers. */
2642 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2643 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2645 /* A C expression for the cost of moving data of mode M between a
2646 register and memory. A value of 2 is the default; this cost is
2647 relative to those in `REGISTER_MOVE_COST'.
2649 If moving between registers and memory is more expensive than
2650 between two registers, you should define this macro to express the
2653 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2654 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2656 /* A C expression for the cost of a branch instruction. A value of 1
2657 is the default; other values are interpreted relative to that. */
2659 #define BRANCH_COST ix86_branch_cost
2661 /* Define this macro as a C expression which is nonzero if accessing
2662 less than a word of memory (i.e. a `char' or a `short') is no
2663 faster than accessing a word of memory, i.e., if such access
2664 require more than one instruction or if there is no difference in
2665 cost between byte and (aligned) word loads.
2667 When this macro is not defined, the compiler will access a field by
2668 finding the smallest containing object; when it is defined, a
2669 fullword load will be used if alignment permits. Unless bytes
2670 accesses are faster than word accesses, using word accesses is
2671 preferable since it may eliminate subsequent memory access if
2672 subsequent accesses occur to other fields in the same word of the
2673 structure, but to different bytes. */
2675 #define SLOW_BYTE_ACCESS 0
2677 /* Nonzero if access to memory by shorts is slow and undesirable. */
2678 #define SLOW_SHORT_ACCESS 0
2680 /* Define this macro to be the value 1 if unaligned accesses have a
2681 cost many times greater than aligned accesses, for example if they
2682 are emulated in a trap handler.
2684 When this macro is nonzero, the compiler will act as if
2685 `STRICT_ALIGNMENT' were nonzero when generating code for block
2686 moves. This can cause significantly more instructions to be
2687 produced. Therefore, do not set this macro nonzero if unaligned
2688 accesses only add a cycle or two to the time for a memory access.
2690 If the value of this macro is always zero, it need not be defined. */
2692 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2694 /* Define this macro if it is as good or better to call a constant
2695 function address than to call an address kept in a register.
2697 Desirable on the 386 because a CALL with a constant address is
2698 faster than one with a register address. */
2700 #define NO_FUNCTION_CSE
2702 /* Define this macro if it is as good or better for a function to call
2703 itself with an explicit address than to call an address kept in a
2706 #define NO_RECURSIVE_FUNCTION_CSE
2708 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2709 return the mode to be used for the comparison.
2711 For floating-point equality comparisons, CCFPEQmode should be used.
2712 VOIDmode should be used in all other cases.
2714 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2715 possible, to allow for more combinations. */
2717 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2719 /* Return nonzero if MODE implies a floating point inequality can be
2722 #define REVERSIBLE_CC_MODE(MODE) 1
2724 /* A C expression whose value is reversed condition code of the CODE for
2725 comparison done in CC_MODE mode. */
2726 #define REVERSE_CONDITION(CODE, MODE) \
2727 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2728 : reverse_condition_maybe_unordered (CODE))
2731 /* Control the assembler format that we output, to the extent
2732 this does not vary between assemblers. */
2734 /* How to refer to registers in assembler output.
2735 This sequence is indexed by compiler's hard-register-number (see above). */
2737 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2738 For non floating point regs, the following are the HImode names.
2740 For float regs, the stack top is sometimes referred to as "%st(0)"
2741 instead of just "%st". PRINT_REG handles this with the "y" code. */
2743 #undef HI_REGISTER_NAMES
2744 #define HI_REGISTER_NAMES \
2745 {"ax","dx","cx","bx","si","di","bp","sp", \
2746 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2747 "argp", "flags", "fpsr", "dirflag", "frame", \
2748 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2749 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2750 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2751 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2753 #define REGISTER_NAMES HI_REGISTER_NAMES
2755 /* Table of additional register names to use in user input. */
2757 #define ADDITIONAL_REGISTER_NAMES \
2758 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2759 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2760 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2761 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2762 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2763 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2764 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2765 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2767 /* Note we are omitting these since currently I don't know how
2768 to get gcc to use these, since they want the same but different
2769 number as al, and ax.
2772 #define QI_REGISTER_NAMES \
2773 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2775 /* These parallel the array above, and can be used to access bits 8:15
2776 of regs 0 through 3. */
2778 #define QI_HIGH_REGISTER_NAMES \
2779 {"ah", "dh", "ch", "bh", }
2781 /* How to renumber registers for dbx and gdb. */
2783 #define DBX_REGISTER_NUMBER(N) \
2784 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2786 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2787 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2788 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2790 /* Before the prologue, RA is at 0(%esp). */
2791 #define INCOMING_RETURN_ADDR_RTX \
2792 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2794 /* After the prologue, RA is at -4(AP) in the current frame. */
2795 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2797 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2798 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2800 /* PC is dbx register 8; let's use that column for RA. */
2801 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2803 /* Before the prologue, the top of the frame is at 4(%esp). */
2804 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2806 /* Describe how we implement __builtin_eh_return. */
2807 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2808 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2811 /* Select a format to encode pointers in exception handling data. CODE
2812 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2813 true if the symbol may be affected by dynamic relocations.
2815 ??? All x86 object file formats are capable of representing this.
2816 After all, the relocation needed is the same as for the call insn.
2817 Whether or not a particular assembler allows us to enter such, I
2818 guess we'll have to see. */
2819 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2821 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2824 /* This is how to output an insn to push a register on the stack.
2825 It need not be very fast code. */
2827 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2830 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2831 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2833 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2836 /* This is how to output an insn to pop a register from the stack.
2837 It need not be very fast code. */
2839 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2842 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2843 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2845 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2848 /* This is how to output an element of a case-vector that is absolute. */
2850 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2851 ix86_output_addr_vec_elt ((FILE), (VALUE))
2853 /* This is how to output an element of a case-vector that is relative. */
2855 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2856 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2858 /* Under some conditions we need jump tables in the text section, because
2859 the assembler cannot handle label differences between sections. */
2861 #define JUMP_TABLES_IN_TEXT_SECTION \
2862 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2864 /* A C statement that outputs an address constant appropriate to
2865 for DWARF debugging. */
2867 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
2868 i386_dwarf_output_addr_const ((FILE), (X))
2870 /* Emit a dtp-relative reference to a TLS variable. */
2873 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
2874 i386_output_dwarf_dtprel (FILE, SIZE, X)
2877 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2878 and switch back. For x86 we do this only to save a few bytes that
2879 would otherwise be unused in the text section. */
2880 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2881 asm (SECTION_OP "\n\t" \
2882 "call " USER_LABEL_PREFIX #FUNC "\n" \
2883 TEXT_SECTION_ASM_OP);
2885 /* Print operand X (an rtx) in assembler syntax to file FILE.
2886 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2887 Effect of various CODE letters is described in i386.c near
2888 print_operand function. */
2890 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2891 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2893 /* Print the name of a register based on its machine mode and number.
2894 If CODE is 'w', pretend the mode is HImode.
2895 If CODE is 'b', pretend the mode is QImode.
2896 If CODE is 'k', pretend the mode is SImode.
2897 If CODE is 'q', pretend the mode is DImode.
2898 If CODE is 'h', pretend the reg is the `high' byte register.
2899 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2901 #define PRINT_REG(X, CODE, FILE) \
2902 print_reg ((X), (CODE), (FILE))
2904 #define PRINT_OPERAND(FILE, X, CODE) \
2905 print_operand ((FILE), (X), (CODE))
2907 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2908 print_operand_address ((FILE), (ADDR))
2910 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2912 if (! output_addr_const_extra (FILE, (X))) \
2916 /* Print the name of a register for based on its machine mode and number.
2917 This macro is used to print debugging output.
2918 This macro is different from PRINT_REG in that it may be used in
2919 programs that are not linked with aux-output.o. */
2921 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2922 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2923 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2924 fprintf ((FILE), "%d ", REGNO (X)); \
2925 if (REGNO (X) == FLAGS_REG) \
2926 { fputs ("flags", (FILE)); break; } \
2927 if (REGNO (X) == DIRFLAG_REG) \
2928 { fputs ("dirflag", (FILE)); break; } \
2929 if (REGNO (X) == FPSR_REG) \
2930 { fputs ("fpsr", (FILE)); break; } \
2931 if (REGNO (X) == ARG_POINTER_REGNUM) \
2932 { fputs ("argp", (FILE)); break; } \
2933 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2934 { fputs ("frame", (FILE)); break; } \
2935 if (STACK_TOP_P (X)) \
2936 { fputs ("st(0)", (FILE)); break; } \
2938 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
2939 if (REX_INT_REG_P (X)) \
2941 switch (GET_MODE_SIZE (GET_MODE (X))) \
2945 fprintf ((FILE), "r%i", REGNO (X) \
2946 - FIRST_REX_INT_REG + 8); \
2949 fprintf ((FILE), "r%id", REGNO (X) \
2950 - FIRST_REX_INT_REG + 8); \
2953 fprintf ((FILE), "r%iw", REGNO (X) \
2954 - FIRST_REX_INT_REG + 8); \
2957 fprintf ((FILE), "r%ib", REGNO (X) \
2958 - FIRST_REX_INT_REG + 8); \
2963 switch (GET_MODE_SIZE (GET_MODE (X))) \
2966 fputs ("r", (FILE)); \
2967 fputs (hi_name[REGNO (X)], (FILE)); \
2970 fputs ("e", (FILE)); \
2972 fputs (hi_name[REGNO (X)], (FILE)); \
2975 fputs (qi_name[REGNO (X)], (FILE)); \
2980 /* a letter which is not needed by the normal asm syntax, which
2981 we can use for operand syntax in the extended asm */
2983 #define ASM_OPERAND_LETTER '#'
2984 #define RET return ""
2985 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2987 /* Define the codes that are matched by predicates in i386.c. */
2989 #define PREDICATE_CODES \
2990 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
2991 SYMBOL_REF, LABEL_REF, CONST}}, \
2992 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
2993 SYMBOL_REF, LABEL_REF, CONST}}, \
2994 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
2995 SYMBOL_REF, LABEL_REF, CONST}}, \
2996 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
2997 SYMBOL_REF, LABEL_REF, CONST}}, \
2998 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
2999 SYMBOL_REF, LABEL_REF, CONST}}, \
3000 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3001 SYMBOL_REF, LABEL_REF, CONST}}, \
3002 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3003 SYMBOL_REF, LABEL_REF}}, \
3004 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3005 {"const_int_1_operand", {CONST_INT}}, \
3006 {"const_int_1_31_operand", {CONST_INT}}, \
3007 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3008 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3009 LABEL_REF, SUBREG, REG, MEM}}, \
3010 {"pic_symbolic_operand", {CONST}}, \
3011 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3012 {"sibcall_insn_operand", {REG, SUBREG, SYMBOL_REF}}, \
3013 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3014 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3015 {"const1_operand", {CONST_INT}}, \
3016 {"const248_operand", {CONST_INT}}, \
3017 {"const_0_to_3_operand", {CONST_INT}}, \
3018 {"const_0_to_7_operand", {CONST_INT}}, \
3019 {"const_0_to_15_operand", {CONST_INT}}, \
3020 {"const_0_to_255_operand", {CONST_INT}}, \
3021 {"incdec_operand", {CONST_INT}}, \
3022 {"mmx_reg_operand", {REG}}, \
3023 {"reg_no_sp_operand", {SUBREG, REG}}, \
3024 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3025 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3026 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3027 {"index_register_operand", {SUBREG, REG}}, \
3028 {"flags_reg_operand", {REG}}, \
3029 {"q_regs_operand", {SUBREG, REG}}, \
3030 {"non_q_regs_operand", {SUBREG, REG}}, \
3031 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3032 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3033 GE, UNGE, LTGT, UNEQ}}, \
3034 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3035 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3037 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3038 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3039 UNGE, UNGT, LTGT, UNEQ }}, \
3040 {"ix86_carry_flag_operator", {LTU, LT, UNLT, GT, UNGT, LE, UNLE, \
3041 GE, UNGE, LTGT, UNEQ}}, \
3042 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3043 {"ext_register_operand", {SUBREG, REG}}, \
3044 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3045 {"mult_operator", {MULT}}, \
3046 {"div_operator", {DIV}}, \
3047 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3048 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3049 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3050 LSHIFTRT, ROTATERT}}, \
3051 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3052 {"memory_displacement_operand", {MEM}}, \
3053 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3054 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3055 {"long_memory_operand", {MEM}}, \
3056 {"tls_symbolic_operand", {SYMBOL_REF}}, \
3057 {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3058 {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3059 {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \
3060 {"local_exec_symbolic_operand", {SYMBOL_REF}}, \
3061 {"any_fp_register_operand", {REG}}, \
3062 {"register_and_not_any_fp_reg_operand", {REG}}, \
3063 {"fp_register_operand", {REG}}, \
3064 {"register_and_not_fp_reg_operand", {REG}}, \
3065 {"zero_extended_scalar_load_operand", {MEM}}, \
3066 {"vector_move_operand", {CONST_VECTOR, SUBREG, REG, MEM}}, \
3067 {"no_seg_address_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3068 LABEL_REF, SUBREG, REG, MEM, PLUS, MULT}},
3070 /* A list of predicates that do special things with modes, and so
3071 should not elicit warnings for VOIDmode match_operand. */
3073 #define SPECIAL_MODE_PREDICATES \
3074 "ext_register_operand",
3076 /* Which processor to schedule for. The cpu attribute defines a list that
3077 mirrors this list, so changes to i386.md must be made at the same time. */
3081 PROCESSOR_I386, /* 80386 */
3082 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
3084 PROCESSOR_PENTIUMPRO,
3092 extern enum processor_type ix86_tune;
3093 extern const char *ix86_tune_string;
3095 extern enum processor_type ix86_arch;
3096 extern const char *ix86_arch_string;
3104 extern enum fpmath_unit ix86_fpmath;
3105 extern const char *ix86_fpmath_string;
3113 extern enum tls_dialect ix86_tls_dialect;
3114 extern const char *ix86_tls_dialect_string;
3117 CM_32, /* The traditional 32-bit ABI. */
3118 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
3119 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
3120 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
3121 CM_LARGE, /* No assumptions. */
3122 CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */
3125 extern enum cmodel ix86_cmodel;
3126 extern const char *ix86_cmodel_string;
3128 /* Size of the RED_ZONE area. */
3129 #define RED_ZONE_SIZE 128
3130 /* Reserved area of the red zone for temporaries. */
3131 #define RED_ZONE_RESERVE 8
3138 extern const char *ix86_asm_string;
3139 extern enum asm_dialect ix86_asm_dialect;
3141 extern int ix86_regparm;
3142 extern const char *ix86_regparm_string;
3144 extern int ix86_preferred_stack_boundary;
3145 extern const char *ix86_preferred_stack_boundary_string;
3147 extern int ix86_branch_cost;
3148 extern const char *ix86_branch_cost_string;
3150 extern const char *ix86_debug_arg_string;
3151 extern const char *ix86_debug_addr_string;
3153 /* Obsoleted by -f options. Remove before 3.2 ships. */
3154 extern const char *ix86_align_loops_string;
3155 extern const char *ix86_align_jumps_string;
3156 extern const char *ix86_align_funcs_string;
3158 /* Smallest class containing REGNO. */
3159 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
3161 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3162 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3164 /* To properly truncate FP values into integers, we need to set i387 control
3165 word. We can't emit proper mode switching code before reload, as spills
3166 generated by reload may truncate values incorrectly, but we still can avoid
3167 redundant computation of new control word by the mode switching pass.
3168 The fldcw instructions are still emitted redundantly, but this is probably
3169 not going to be noticeable problem, as most CPUs do have fast path for
3172 The machinery is to emit simple truncation instructions and split them
3173 before reload to instructions having USEs of two memory locations that
3174 are filled by this code to old and new control word.
3176 Post-reload pass may be later used to eliminate the redundant fildcw if
3179 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3181 /* Define this macro if the port needs extra instructions inserted
3182 for mode switching in an optimizing compilation. */
3184 #define OPTIMIZE_MODE_SWITCHING(ENTITY) ix86_optimize_mode_switching
3186 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3187 initializer for an array of integers. Each initializer element N
3188 refers to an entity that needs mode switching, and specifies the
3189 number of different modes that might need to be set for this
3190 entity. The position of the initializer in the initializer -
3191 starting counting at zero - determines the integer that is used to
3192 refer to the mode-switched entity in question. */
3194 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3196 /* ENTITY is an integer specifying a mode-switched entity. If
3197 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3198 return an integer value not larger than the corresponding element
3199 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3200 must be switched into prior to the execution of INSN. */
3202 #define MODE_NEEDED(ENTITY, I) \
3203 (GET_CODE (I) == CALL_INSN \
3204 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3205 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3206 ? FP_CW_UNINITIALIZED \
3207 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3211 /* This macro specifies the order in which modes for ENTITY are
3212 processed. 0 is the highest priority. */
3214 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3216 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3217 is the set of hard registers live at the point where the insn(s)
3218 are to be inserted. */
3220 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3221 ((MODE) == FP_CW_STORED \
3222 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3223 assign_386_stack_local (HImode, 2)), 0\
3226 /* Avoid renaming of stack registers, as doing so in combination with
3227 scheduling just increases amount of live registers at time and in
3228 the turn amount of fxch instructions needed.
3230 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3232 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3233 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
3236 #define DLL_IMPORT_EXPORT_PREFIX '#'
3238 #define FASTCALL_PREFIX '@'
3240 struct machine_function GTY(())
3242 struct stack_local_entry *stack_locals;
3243 const char *some_ld_name;
3244 int save_varrargs_registers;
3245 int accesses_prev_frame;
3246 int optimize_mode_switching;
3247 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
3248 determine the style used. */
3249 int use_fast_prologue_epilogue;
3250 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
3252 int use_fast_prologue_epilogue_nregs;
3255 #define ix86_stack_locals (cfun->machine->stack_locals)
3256 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
3257 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
3259 /* Control behavior of x86_file_start. */
3260 #define X86_FILE_START_VERSION_DIRECTIVE false
3261 #define X86_FILE_START_FLTUSED false
OSDN Git Service
