1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Define the specific costs for a given cpu */
39 struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init[5]; /* cost of starting a multiply
45 in QImode, HImode, SImode, DImode, TImode*/
46 const int mult_bit; /* cost of multiply per each bit set */
47 const int divide[5]; /* cost of a divide/mod
48 in QImode, HImode, SImode, DImode, TImode*/
49 int movsx; /* The cost of movsx operation. */
50 int movzx; /* The cost of movzx operation. */
51 const int large_insn; /* insns larger than this cost more */
52 const int move_ratio; /* The threshold of number of scalar
53 memory-to-memory move insns. */
54 const int movzbl_load; /* cost of loading using movzbl */
55 const int int_load[3]; /* cost of loading integer registers
56 in QImode, HImode and SImode relative
57 to reg-reg move (2). */
58 const int int_store[3]; /* cost of storing integer register
59 in QImode, HImode and SImode */
60 const int fp_move; /* cost of reg,reg fld/fst */
61 const int fp_load[3]; /* cost of loading FP register
62 in SFmode, DFmode and XFmode */
63 const int fp_store[3]; /* cost of storing FP register
64 in SFmode, DFmode and XFmode */
65 const int mmx_move; /* cost of moving MMX register. */
66 const int mmx_load[2]; /* cost of loading MMX register
67 in SImode and DImode */
68 const int mmx_store[2]; /* cost of storing MMX register
69 in SImode and DImode */
70 const int sse_move; /* cost of moving SSE register. */
71 const int sse_load[3]; /* cost of loading SSE register
72 in SImode, DImode and TImode*/
73 const int sse_store[3]; /* cost of storing SSE register
74 in SImode, DImode and TImode*/
75 const int mmxsse_to_integer; /* cost of moving mmxsse register to
76 integer and vice versa. */
77 const int prefetch_block; /* bytes moved to cache for prefetch. */
78 const int simultaneous_prefetches; /* number of parallel prefetch
80 const int branch_cost; /* Default value for BRANCH_COST. */
81 const int fadd; /* cost of FADD and FSUB instructions. */
82 const int fmul; /* cost of FMUL instruction. */
83 const int fdiv; /* cost of FDIV instruction. */
84 const int fabs; /* cost of FABS instruction. */
85 const int fchs; /* cost of FCHS instruction. */
86 const int fsqrt; /* cost of FSQRT instruction. */
89 extern const struct processor_costs *ix86_cost;
91 /* Macros used in the machine description to test the flags. */
93 /* configure can arrange to make this 2, to force a 486. */
95 #ifndef TARGET_CPU_DEFAULT
96 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
99 #ifndef TARGET_FPMATH_DEFAULT
100 #define TARGET_FPMATH_DEFAULT \
101 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
104 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
106 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
107 compile-time constant. */
111 #define TARGET_64BIT 1
113 #define TARGET_64BIT 0
116 #ifndef TARGET_BI_ARCH
118 #if TARGET_64BIT_DEFAULT
119 #define TARGET_64BIT 1
121 #define TARGET_64BIT 0
126 #define HAS_LONG_COND_BRANCH 1
127 #define HAS_LONG_UNCOND_BRANCH 1
129 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
130 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
131 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
132 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
133 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
134 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
135 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
136 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
137 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
138 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
139 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
140 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
141 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
143 #define TUNEMASK (1 << ix86_tune)
144 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
145 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
146 extern const int x86_branch_hints, x86_unroll_strlen;
147 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
148 extern const int x86_use_himode_fiop, x86_use_simode_fiop;
149 extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write;
150 extern const int x86_read_modify, x86_split_long_moves;
151 extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
152 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
153 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
154 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
155 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
156 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
157 extern const int x86_epilogue_using_move, x86_decompose_lea;
158 extern const int x86_arch_always_fancy_math_387, x86_shift1;
159 extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
160 extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
161 extern const int x86_use_ffreep;
162 extern const int x86_inter_unit_moves, x86_schedule;
163 extern const int x86_use_bt;
164 extern const int x86_cmpxchg, x86_cmpxchg8b, x86_cmpxchg16b, x86_xadd;
165 extern const int x86_use_incdec;
166 extern const int x86_pad_returns;
167 extern const int x86_partial_flag_reg_stall;
168 extern int x86_prefetch_sse;
170 #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
171 #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
172 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
173 #define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
174 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
175 /* For sane SSE instruction set generation we need fcomi instruction. It is
176 safe to enable all CMOVE instructions. */
177 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
178 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
179 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
180 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
181 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
182 #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
183 #define TARGET_MOVX (x86_movx & TUNEMASK)
184 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
185 #define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK)
186 #define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK)
187 #define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK)
188 #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
189 #define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
190 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
191 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
192 #define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
193 #define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
194 #define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
195 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
196 #define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
197 #define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
198 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
199 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
200 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
201 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
202 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
203 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
204 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
205 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
206 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
207 (x86_sse_partial_reg_dependency & TUNEMASK)
208 #define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
209 #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
210 #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
211 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
212 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
213 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
214 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
215 #define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
216 #define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
217 #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
218 #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
219 #define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
220 #define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
221 #define TARGET_USE_BT (x86_use_bt & TUNEMASK)
222 #define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK)
223 #define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK)
225 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
227 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
228 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
229 && (ix86_fpmath & FPMATH_387))
231 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
232 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
233 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
234 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
236 #define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
237 #define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch))
238 #define TARGET_CMPXCHG16B (x86_cmpxchg16b & (1 << ix86_arch))
239 #define TARGET_XADD (x86_xadd & (1 << ix86_arch))
241 #ifndef TARGET_64BIT_DEFAULT
242 #define TARGET_64BIT_DEFAULT 0
244 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
245 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
248 /* Once GDB has been enhanced to deal with functions without frame
249 pointers, we can change this to allow for elimination of
250 the frame pointer in leaf functions. */
251 #define TARGET_DEFAULT 0
253 /* This is not really a target flag, but is done this way so that
254 it's analogous to similar code for Mach-O on PowerPC. darwin.h
255 redefines this to 1. */
256 #define TARGET_MACHO 0
258 /* Subtargets may reset this to 1 in order to enable 96-bit long double
259 with the rounding mode forced to 53 bits. */
260 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
262 /* Sometimes certain combinations of command options do not make
263 sense on a particular target machine. You can define a macro
264 `OVERRIDE_OPTIONS' to take account of this. This macro, if
265 defined, is executed once just after all the command options have
268 Don't use this macro to turn on various extra optimizations for
269 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
271 #define OVERRIDE_OPTIONS override_options ()
273 /* Define this to change the optimizations performed by default. */
274 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
275 optimization_options ((LEVEL), (SIZE))
277 /* -march=native handling only makes sense with a native compiler. */
278 #ifndef CROSS_COMPILE
279 /* In driver-i386.c. */
280 extern const char *host_detect_local_cpu (int argc, const char **argv);
281 #define EXTRA_SPEC_FUNCTIONS \
282 { "local_cpu_detect", host_detect_local_cpu },
285 /* Support for configure-time defaults of some command line options.
286 The order here is important so that -march doesn't squash the
287 tune or cpu values. */
288 #define OPTION_DEFAULT_SPECS \
289 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
290 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
291 {"arch", "%{!march=*:-march=%(VALUE)}"}
293 /* Specs for the compiler proper */
296 #define CC1_CPU_SPEC_1 "\
299 %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
301 %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
302 %{mpentium:-mtune=pentium \
303 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
304 %{mpentiumpro:-mtune=pentiumpro \
305 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
307 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
309 %{mintel-syntax:-masm=intel \
310 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
311 %{mno-intel-syntax:-masm=att \
312 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
315 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
317 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
318 "%{march=native:%<march=native %:local_cpu_detect(arch)} \
319 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
323 /* Target CPU builtins. */
324 #define TARGET_CPU_CPP_BUILTINS() \
327 size_t arch_len = strlen (ix86_arch_string); \
328 size_t tune_len = strlen (ix86_tune_string); \
329 int last_arch_char = ix86_arch_string[arch_len - 1]; \
330 int last_tune_char = ix86_tune_string[tune_len - 1]; \
334 builtin_assert ("cpu=x86_64"); \
335 builtin_assert ("machine=x86_64"); \
336 builtin_define ("__amd64"); \
337 builtin_define ("__amd64__"); \
338 builtin_define ("__x86_64"); \
339 builtin_define ("__x86_64__"); \
343 builtin_assert ("cpu=i386"); \
344 builtin_assert ("machine=i386"); \
345 builtin_define_std ("i386"); \
348 /* Built-ins based on -mtune= (or -march= if no \
351 builtin_define ("__tune_i386__"); \
352 else if (TARGET_486) \
353 builtin_define ("__tune_i486__"); \
354 else if (TARGET_PENTIUM) \
356 builtin_define ("__tune_i586__"); \
357 builtin_define ("__tune_pentium__"); \
358 if (last_tune_char == 'x') \
359 builtin_define ("__tune_pentium_mmx__"); \
361 else if (TARGET_PENTIUMPRO) \
363 builtin_define ("__tune_i686__"); \
364 builtin_define ("__tune_pentiumpro__"); \
365 switch (last_tune_char) \
368 builtin_define ("__tune_pentium3__"); \
371 builtin_define ("__tune_pentium2__"); \
375 else if (TARGET_K6) \
377 builtin_define ("__tune_k6__"); \
378 if (last_tune_char == '2') \
379 builtin_define ("__tune_k6_2__"); \
380 else if (last_tune_char == '3') \
381 builtin_define ("__tune_k6_3__"); \
383 else if (TARGET_ATHLON) \
385 builtin_define ("__tune_athlon__"); \
386 /* Only plain "athlon" lacks SSE. */ \
387 if (last_tune_char != 'n') \
388 builtin_define ("__tune_athlon_sse__"); \
390 else if (TARGET_K8) \
391 builtin_define ("__tune_k8__"); \
392 else if (TARGET_PENTIUM4) \
393 builtin_define ("__tune_pentium4__"); \
394 else if (TARGET_NOCONA) \
395 builtin_define ("__tune_nocona__"); \
398 builtin_define ("__MMX__"); \
400 builtin_define ("__3dNOW__"); \
401 if (TARGET_3DNOW_A) \
402 builtin_define ("__3dNOW_A__"); \
404 builtin_define ("__SSE__"); \
406 builtin_define ("__SSE2__"); \
408 builtin_define ("__SSE3__"); \
409 if (TARGET_SSE_MATH && TARGET_SSE) \
410 builtin_define ("__SSE_MATH__"); \
411 if (TARGET_SSE_MATH && TARGET_SSE2) \
412 builtin_define ("__SSE2_MATH__"); \
414 /* Built-ins based on -march=. */ \
415 if (ix86_arch == PROCESSOR_I486) \
417 builtin_define ("__i486"); \
418 builtin_define ("__i486__"); \
420 else if (ix86_arch == PROCESSOR_PENTIUM) \
422 builtin_define ("__i586"); \
423 builtin_define ("__i586__"); \
424 builtin_define ("__pentium"); \
425 builtin_define ("__pentium__"); \
426 if (last_arch_char == 'x') \
427 builtin_define ("__pentium_mmx__"); \
429 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
431 builtin_define ("__i686"); \
432 builtin_define ("__i686__"); \
433 builtin_define ("__pentiumpro"); \
434 builtin_define ("__pentiumpro__"); \
436 else if (ix86_arch == PROCESSOR_K6) \
439 builtin_define ("__k6"); \
440 builtin_define ("__k6__"); \
441 if (last_arch_char == '2') \
442 builtin_define ("__k6_2__"); \
443 else if (last_arch_char == '3') \
444 builtin_define ("__k6_3__"); \
446 else if (ix86_arch == PROCESSOR_ATHLON) \
448 builtin_define ("__athlon"); \
449 builtin_define ("__athlon__"); \
450 /* Only plain "athlon" lacks SSE. */ \
451 if (last_arch_char != 'n') \
452 builtin_define ("__athlon_sse__"); \
454 else if (ix86_arch == PROCESSOR_K8) \
456 builtin_define ("__k8"); \
457 builtin_define ("__k8__"); \
459 else if (ix86_arch == PROCESSOR_PENTIUM4) \
461 builtin_define ("__pentium4"); \
462 builtin_define ("__pentium4__"); \
464 else if (ix86_arch == PROCESSOR_NOCONA) \
466 builtin_define ("__nocona"); \
467 builtin_define ("__nocona__"); \
472 #define TARGET_CPU_DEFAULT_i386 0
473 #define TARGET_CPU_DEFAULT_i486 1
474 #define TARGET_CPU_DEFAULT_pentium 2
475 #define TARGET_CPU_DEFAULT_pentium_mmx 3
476 #define TARGET_CPU_DEFAULT_pentiumpro 4
477 #define TARGET_CPU_DEFAULT_pentium2 5
478 #define TARGET_CPU_DEFAULT_pentium3 6
479 #define TARGET_CPU_DEFAULT_pentium4 7
480 #define TARGET_CPU_DEFAULT_k6 8
481 #define TARGET_CPU_DEFAULT_k6_2 9
482 #define TARGET_CPU_DEFAULT_k6_3 10
483 #define TARGET_CPU_DEFAULT_athlon 11
484 #define TARGET_CPU_DEFAULT_athlon_sse 12
485 #define TARGET_CPU_DEFAULT_k8 13
486 #define TARGET_CPU_DEFAULT_pentium_m 14
487 #define TARGET_CPU_DEFAULT_prescott 15
488 #define TARGET_CPU_DEFAULT_nocona 16
489 #define TARGET_CPU_DEFAULT_generic 17
491 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
492 "pentiumpro", "pentium2", "pentium3", \
493 "pentium4", "k6", "k6-2", "k6-3",\
494 "athlon", "athlon-4", "k8", \
495 "pentium-m", "prescott", "nocona", \
499 #define CC1_SPEC "%(cc1_cpu) "
502 /* This macro defines names of additional specifications to put in the
503 specs that can be used in various specifications like CC1_SPEC. Its
504 definition is an initializer with a subgrouping for each command option.
506 Each subgrouping contains a string constant, that defines the
507 specification name, and a string constant that used by the GCC driver
510 Do not define this macro if it does not need to do anything. */
512 #ifndef SUBTARGET_EXTRA_SPECS
513 #define SUBTARGET_EXTRA_SPECS
516 #define EXTRA_SPECS \
517 { "cc1_cpu", CC1_CPU_SPEC }, \
518 SUBTARGET_EXTRA_SPECS
520 /* target machine storage layout */
522 #define LONG_DOUBLE_TYPE_SIZE 80
524 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
525 FPU, assume that the fpcw is set to extended precision; when using
526 only SSE, rounding is correct; when using both SSE and the FPU,
527 the rounding precision is indeterminate, since either may be chosen
528 apparently at random. */
529 #define TARGET_FLT_EVAL_METHOD \
530 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
532 #define SHORT_TYPE_SIZE 16
533 #define INT_TYPE_SIZE 32
534 #define FLOAT_TYPE_SIZE 32
535 #define LONG_TYPE_SIZE BITS_PER_WORD
536 #define DOUBLE_TYPE_SIZE 64
537 #define LONG_LONG_TYPE_SIZE 64
539 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
540 #define MAX_BITS_PER_WORD 64
542 #define MAX_BITS_PER_WORD 32
545 /* Define this if most significant byte of a word is the lowest numbered. */
546 /* That is true on the 80386. */
548 #define BITS_BIG_ENDIAN 0
550 /* Define this if most significant byte of a word is the lowest numbered. */
551 /* That is not true on the 80386. */
552 #define BYTES_BIG_ENDIAN 0
554 /* Define this if most significant word of a multiword number is the lowest
556 /* Not true for 80386 */
557 #define WORDS_BIG_ENDIAN 0
559 /* Width of a word, in units (bytes). */
560 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
562 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
564 #define MIN_UNITS_PER_WORD 4
567 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
568 #define PARM_BOUNDARY BITS_PER_WORD
570 /* Boundary (in *bits*) on which stack pointer should be aligned. */
571 #define STACK_BOUNDARY BITS_PER_WORD
573 /* Boundary (in *bits*) on which the stack pointer prefers to be
574 aligned; the compiler cannot rely on having this alignment. */
575 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
577 /* As of July 2001, many runtimes do not align the stack properly when
578 entering main. This causes expand_main_function to forcibly align
579 the stack, which results in aligned frames for functions called from
580 main, though it does nothing for the alignment of main itself. */
581 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
582 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
584 /* Minimum allocation boundary for the code of a function. */
585 #define FUNCTION_BOUNDARY 8
587 /* C++ stores the virtual bit in the lowest bit of function pointers. */
588 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
590 /* Alignment of field after `int : 0' in a structure. */
592 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
594 /* Minimum size in bits of the largest boundary to which any
595 and all fundamental data types supported by the hardware
596 might need to be aligned. No data type wants to be aligned
599 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
600 and Pentium Pro XFmode values at 128 bit boundaries. */
602 #define BIGGEST_ALIGNMENT 128
604 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
605 #define ALIGN_MODE_128(MODE) \
606 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
608 /* The published ABIs say that doubles should be aligned on word
609 boundaries, so lower the alignment for structure fields unless
610 -malign-double is set. */
612 /* ??? Blah -- this macro is used directly by libobjc. Since it
613 supports no vector modes, cut out the complexity and fall back
614 on BIGGEST_FIELD_ALIGNMENT. */
615 #ifdef IN_TARGET_LIBS
617 #define BIGGEST_FIELD_ALIGNMENT 128
619 #define BIGGEST_FIELD_ALIGNMENT 32
622 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
623 x86_field_alignment (FIELD, COMPUTED)
626 /* If defined, a C expression to compute the alignment given to a
627 constant that is being placed in memory. EXP is the constant
628 and ALIGN is the alignment that the object would ordinarily have.
629 The value of this macro is used instead of that alignment to align
632 If this macro is not defined, then ALIGN is used.
634 The typical use of this macro is to increase alignment for string
635 constants to be word aligned so that `strcpy' calls that copy
636 constants can be done inline. */
638 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
640 /* If defined, a C expression to compute the alignment for a static
641 variable. TYPE is the data type, and ALIGN is the alignment that
642 the object would ordinarily have. The value of this macro is used
643 instead of that alignment to align the object.
645 If this macro is not defined, then ALIGN is used.
647 One use of this macro is to increase alignment of medium-size
648 data to make it all fit in fewer cache lines. Another is to
649 cause character arrays to be word-aligned so that `strcpy' calls
650 that copy constants to character arrays can be done inline. */
652 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
654 /* If defined, a C expression to compute the alignment for a local
655 variable. TYPE is the data type, and ALIGN is the alignment that
656 the object would ordinarily have. The value of this macro is used
657 instead of that alignment to align the object.
659 If this macro is not defined, then ALIGN is used.
661 One use of this macro is to increase alignment of medium-size
662 data to make it all fit in fewer cache lines. */
664 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
666 /* If defined, a C expression that gives the alignment boundary, in
667 bits, of an argument with the specified mode and type. If it is
668 not defined, `PARM_BOUNDARY' is used for all arguments. */
670 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
671 ix86_function_arg_boundary ((MODE), (TYPE))
673 /* Set this nonzero if move instructions will actually fail to work
674 when given unaligned data. */
675 #define STRICT_ALIGNMENT 0
677 /* If bit field type is int, don't let it cross an int,
678 and give entire struct the alignment of an int. */
679 /* Required on the 386 since it doesn't have bit-field insns. */
680 #define PCC_BITFIELD_TYPE_MATTERS 1
682 /* Standard register usage. */
684 /* This processor has special stack-like registers. See reg-stack.c
688 #define IS_STACK_MODE(MODE) \
689 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
690 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
693 /* Number of actual hardware registers.
694 The hardware registers are assigned numbers for the compiler
695 from 0 to just below FIRST_PSEUDO_REGISTER.
696 All registers that the compiler knows about must be given numbers,
697 even those that are not normally considered general registers.
699 In the 80386 we give the 8 general purpose registers the numbers 0-7.
700 We number the floating point registers 8-15.
701 Note that registers 0-7 can be accessed as a short or int,
702 while only 0-3 may be used with byte `mov' instructions.
704 Reg 16 does not correspond to any hardware register, but instead
705 appears in the RTL as an argument pointer prior to reload, and is
706 eliminated during reloading in favor of either the stack or frame
709 #define FIRST_PSEUDO_REGISTER 53
711 /* Number of hardware registers that go into the DWARF-2 unwind info.
712 If not defined, equals FIRST_PSEUDO_REGISTER. */
714 #define DWARF_FRAME_REGISTERS 17
716 /* 1 for registers that have pervasive standard uses
717 and are not available for the register allocator.
718 On the 80386, the stack pointer is such, as is the arg pointer.
720 The value is zero if the register is not fixed on either 32 or
721 64 bit targets, one if the register if fixed on both 32 and 64
722 bit targets, two if it is only fixed on 32bit targets and three
723 if its only fixed on 64bit targets.
724 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
726 #define FIXED_REGISTERS \
727 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
728 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
729 /*arg,flags,fpsr,dir,frame*/ \
731 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
732 0, 0, 0, 0, 0, 0, 0, 0, \
733 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
734 0, 0, 0, 0, 0, 0, 0, 0, \
735 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
736 2, 2, 2, 2, 2, 2, 2, 2, \
737 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
738 2, 2, 2, 2, 2, 2, 2, 2}
741 /* 1 for registers not available across function calls.
742 These must include the FIXED_REGISTERS and also any
743 registers that can be used without being saved.
744 The latter must include the registers where values are returned
745 and the register where structure-value addresses are passed.
746 Aside from that, you can include as many other registers as you like.
748 The value is zero if the register is not call used on either 32 or
749 64 bit targets, one if the register if call used on both 32 and 64
750 bit targets, two if it is only call used on 32bit targets and three
751 if its only call used on 64bit targets.
752 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
754 #define CALL_USED_REGISTERS \
755 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
756 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
757 /*arg,flags,fpsr,dir,frame*/ \
759 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
760 1, 1, 1, 1, 1, 1, 1, 1, \
761 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
762 1, 1, 1, 1, 1, 1, 1, 1, \
763 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
764 1, 1, 1, 1, 2, 2, 2, 2, \
765 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
766 1, 1, 1, 1, 1, 1, 1, 1} \
768 /* Order in which to allocate registers. Each register must be
769 listed once, even those in FIXED_REGISTERS. List frame pointer
770 late and fixed registers last. Note that, in general, we prefer
771 registers listed in CALL_USED_REGISTERS, keeping the others
772 available for storage of persistent values.
774 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
775 so this is just empty initializer for array. */
777 #define REG_ALLOC_ORDER \
778 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
779 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
780 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
783 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
784 to be rearranged based on a particular function. When using sse math,
785 we want to allocate SSE before x87 registers and vice vera. */
787 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
790 /* Macro to conditionally modify fixed_regs/call_used_regs. */
791 #define CONDITIONAL_REGISTER_USAGE \
794 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
796 if (fixed_regs[i] > 1) \
797 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
798 if (call_used_regs[i] > 1) \
799 call_used_regs[i] = (call_used_regs[i] \
800 == (TARGET_64BIT ? 3 : 2)); \
802 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
804 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
805 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
810 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
811 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
812 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
817 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
818 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
819 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
821 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
825 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
826 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
827 if (TEST_HARD_REG_BIT (x, i)) \
828 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
830 if (! TARGET_64BIT) \
833 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
835 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
840 /* Return number of consecutive hard regs needed starting at reg REGNO
841 to hold something of mode MODE.
842 This is ordinarily the length in words of a value of mode MODE
843 but can be less for certain modes in special long registers.
845 Actually there are no two word move instructions for consecutive
846 registers. And only registers 0-3 may have mov byte instructions
850 #define HARD_REGNO_NREGS(REGNO, MODE) \
851 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
852 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
853 : ((MODE) == XFmode \
854 ? (TARGET_64BIT ? 2 : 3) \
856 ? (TARGET_64BIT ? 4 : 6) \
857 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
859 #define VALID_SSE2_REG_MODE(MODE) \
860 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
861 || (MODE) == V2DImode || (MODE) == DFmode)
863 #define VALID_SSE_REG_MODE(MODE) \
864 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
865 || (MODE) == SFmode || (MODE) == TFmode)
867 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
868 ((MODE) == V2SFmode || (MODE) == SFmode)
870 #define VALID_MMX_REG_MODE(MODE) \
871 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
872 || (MODE) == V2SImode || (MODE) == SImode)
874 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
875 place emms and femms instructions. */
876 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
878 #define VALID_FP_MODE_P(MODE) \
879 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
880 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
882 #define VALID_INT_MODE_P(MODE) \
883 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
884 || (MODE) == DImode \
885 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
886 || (MODE) == CDImode \
887 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
888 || (MODE) == TFmode || (MODE) == TCmode)))
890 /* Return true for modes passed in SSE registers. */
891 #define SSE_REG_MODE_P(MODE) \
892 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
893 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
894 || (MODE) == V4SFmode || (MODE) == V4SImode)
896 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
898 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
899 ix86_hard_regno_mode_ok ((REGNO), (MODE))
901 /* Value is 1 if it is a good idea to tie two pseudo registers
902 when one has mode MODE1 and one has mode MODE2.
903 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
904 for any hard reg, then this must be 0 for correct output. */
906 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
908 /* It is possible to write patterns to move flags; but until someone
910 #define AVOID_CCMODE_COPIES
912 /* Specify the modes required to caller save a given hard regno.
913 We do this on i386 to prevent flags from being saved at all.
915 Kill any attempts to combine saving of modes. */
917 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
918 (CC_REGNO_P (REGNO) ? VOIDmode \
919 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
920 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
921 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
922 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
924 /* Specify the registers used for certain standard purposes.
925 The values of these macros are register numbers. */
927 /* on the 386 the pc register is %eip, and is not usable as a general
928 register. The ordinary mov instructions won't work */
929 /* #define PC_REGNUM */
931 /* Register to use for pushing function arguments. */
932 #define STACK_POINTER_REGNUM 7
934 /* Base register for access to local variables of the function. */
935 #define HARD_FRAME_POINTER_REGNUM 6
937 /* Base register for access to local variables of the function. */
938 #define FRAME_POINTER_REGNUM 20
940 /* First floating point reg */
941 #define FIRST_FLOAT_REG 8
943 /* First & last stack-like regs */
944 #define FIRST_STACK_REG FIRST_FLOAT_REG
945 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
947 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
948 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
950 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
951 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
953 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
954 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
956 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
957 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
959 /* Value should be nonzero if functions must have frame pointers.
960 Zero means the frame pointer need not be set up (and parms
961 may be accessed via the stack pointer) in functions that seem suitable.
962 This is computed in `reload', in reload1.c. */
963 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
965 /* Override this in other tm.h files to cope with various OS lossage
966 requiring a frame pointer. */
967 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
968 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
971 /* Make sure we can access arbitrary call frames. */
972 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
974 /* Base register for access to arguments of the function. */
975 #define ARG_POINTER_REGNUM 16
977 /* Register in which static-chain is passed to a function.
978 We do use ECX as static chain register for 32 bit ABI. On the
979 64bit ABI, ECX is an argument register, so we use R10 instead. */
980 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
982 /* Register to hold the addressing base for position independent
983 code access to data items. We don't use PIC pointer for 64bit
984 mode. Define the regnum to dummy value to prevent gcc from
985 pessimizing code dealing with EBX.
987 To avoid clobbering a call-saved register unnecessarily, we renumber
988 the pic register when possible. The change is visible after the
989 prologue has been emitted. */
991 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
993 #define PIC_OFFSET_TABLE_REGNUM \
994 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
995 || !flag_pic ? INVALID_REGNUM \
996 : reload_completed ? REGNO (pic_offset_table_rtx) \
997 : REAL_PIC_OFFSET_TABLE_REGNUM)
999 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1001 /* A C expression which can inhibit the returning of certain function
1002 values in registers, based on the type of value. A nonzero value
1003 says to return the function value in memory, just as large
1004 structures are always returned. Here TYPE will be a C expression
1005 of type `tree', representing the data type of the value.
1007 Note that values of mode `BLKmode' must be explicitly handled by
1008 this macro. Also, the option `-fpcc-struct-return' takes effect
1009 regardless of this macro. On most systems, it is possible to
1010 leave the macro undefined; this causes a default definition to be
1011 used, whose value is the constant 1 for `BLKmode' values, and 0
1014 Do not use this macro to indicate that structures and unions
1015 should always be returned in memory. You should instead use
1016 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1018 #define RETURN_IN_MEMORY(TYPE) \
1019 ix86_return_in_memory (TYPE)
1021 /* This is overridden by <cygwin.h>. */
1022 #define MS_AGGREGATE_RETURN 0
1024 /* This is overridden by <netware.h>. */
1025 #define KEEP_AGGREGATE_RETURN_POINTER 0
1027 /* Define the classes of registers for register constraints in the
1028 machine description. Also define ranges of constants.
1030 One of the classes must always be named ALL_REGS and include all hard regs.
1031 If there is more than one class, another class must be named NO_REGS
1032 and contain no registers.
1034 The name GENERAL_REGS must be the name of a class (or an alias for
1035 another name such as ALL_REGS). This is the class of registers
1036 that is allowed by "g" or "r" in a register constraint.
1037 Also, registers outside this class are allocated only when
1038 instructions express preferences for them.
1040 The classes must be numbered in nondecreasing order; that is,
1041 a larger-numbered class must never be contained completely
1042 in a smaller-numbered class.
1044 For any two classes, it is very desirable that there be another
1045 class that represents their union.
1047 It might seem that class BREG is unnecessary, since no useful 386
1048 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1049 and the "b" register constraint is useful in asms for syscalls.
1051 The flags and fpsr registers are in no class. */
1056 AREG, DREG, CREG, BREG, SIREG, DIREG,
1057 AD_REGS, /* %eax/%edx for DImode */
1058 Q_REGS, /* %eax %ebx %ecx %edx */
1059 NON_Q_REGS, /* %esi %edi %ebp %esp */
1060 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1061 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1062 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1063 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1073 ALL_REGS, LIM_REG_CLASSES
1076 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1078 #define INTEGER_CLASS_P(CLASS) \
1079 reg_class_subset_p ((CLASS), GENERAL_REGS)
1080 #define FLOAT_CLASS_P(CLASS) \
1081 reg_class_subset_p ((CLASS), FLOAT_REGS)
1082 #define SSE_CLASS_P(CLASS) \
1083 ((CLASS) == SSE_REGS)
1084 #define MMX_CLASS_P(CLASS) \
1085 ((CLASS) == MMX_REGS)
1086 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1087 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1088 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1089 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1090 #define MAYBE_SSE_CLASS_P(CLASS) \
1091 reg_classes_intersect_p (SSE_REGS, (CLASS))
1092 #define MAYBE_MMX_CLASS_P(CLASS) \
1093 reg_classes_intersect_p (MMX_REGS, (CLASS))
1095 #define Q_CLASS_P(CLASS) \
1096 reg_class_subset_p ((CLASS), Q_REGS)
1098 /* Give names of register classes as strings for dump file. */
1100 #define REG_CLASS_NAMES \
1102 "AREG", "DREG", "CREG", "BREG", \
1105 "Q_REGS", "NON_Q_REGS", \
1109 "FP_TOP_REG", "FP_SECOND_REG", \
1113 "FP_TOP_SSE_REGS", \
1114 "FP_SECOND_SSE_REGS", \
1118 "FLOAT_INT_SSE_REGS", \
1121 /* Define which registers fit in which classes.
1122 This is an initializer for a vector of HARD_REG_SET
1123 of length N_REG_CLASSES. */
1125 #define REG_CLASS_CONTENTS \
1127 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1128 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1129 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1130 { 0x03, 0x0 }, /* AD_REGS */ \
1131 { 0x0f, 0x0 }, /* Q_REGS */ \
1132 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1133 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1134 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1135 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1136 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1137 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1138 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1139 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1140 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1141 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1142 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1143 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1144 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1145 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1146 { 0xffffffff,0x1fffff } \
1149 /* The same information, inverted:
1150 Return the class number of the smallest class containing
1151 reg number REGNO. This could be a conditional expression
1152 or could index an array. */
1154 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1156 /* When defined, the compiler allows registers explicitly used in the
1157 rtl to be used as spill registers but prevents the compiler from
1158 extending the lifetime of these registers. */
1160 #define SMALL_REGISTER_CLASSES 1
1162 #define QI_REG_P(X) \
1163 (REG_P (X) && REGNO (X) < 4)
1165 #define GENERAL_REGNO_P(N) \
1166 ((N) < 8 || REX_INT_REGNO_P (N))
1168 #define GENERAL_REG_P(X) \
1169 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1171 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1173 #define NON_QI_REG_P(X) \
1174 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1176 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1177 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1179 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1180 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1181 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1182 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1184 #define SSE_REGNO_P(N) \
1185 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1186 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1188 #define REX_SSE_REGNO_P(N) \
1189 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
1191 #define SSE_REGNO(N) \
1192 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1193 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1195 #define SSE_FLOAT_MODE_P(MODE) \
1196 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1198 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1199 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1201 #define STACK_REG_P(XOP) \
1203 REGNO (XOP) >= FIRST_STACK_REG && \
1204 REGNO (XOP) <= LAST_STACK_REG)
1206 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1208 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1210 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1211 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1213 /* The class value for index registers, and the one for base regs. */
1215 #define INDEX_REG_CLASS INDEX_REGS
1216 #define BASE_REG_CLASS GENERAL_REGS
1218 /* Place additional restrictions on the register class to use when it
1219 is necessary to be able to hold a value of mode MODE in a reload
1220 register for which class CLASS would ordinarily be used. */
1222 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1223 ((MODE) == QImode && !TARGET_64BIT \
1224 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1225 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1228 /* Given an rtx X being reloaded into a reg required to be
1229 in class CLASS, return the class of reg to actually use.
1230 In general this is just CLASS; but on some machines
1231 in some cases it is preferable to use a more restrictive class.
1232 On the 80386 series, we prevent floating constants from being
1233 reloaded into floating registers (since no move-insn can do that)
1234 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1236 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1237 QImode must go into class Q_REGS.
1238 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1239 movdf to do mem-to-mem moves through integer regs. */
1241 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1242 ix86_preferred_reload_class ((X), (CLASS))
1244 /* Discourage putting floating-point values in SSE registers unless
1245 SSE math is being used, and likewise for the 387 registers. */
1247 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1248 ix86_preferred_output_reload_class ((X), (CLASS))
1250 /* If we are copying between general and FP registers, we need a memory
1251 location. The same is true for SSE and MMX registers. */
1252 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1253 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1255 /* QImode spills from non-QI registers need a scratch. This does not
1256 happen often -- the only example so far requires an uninitialized
1259 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1260 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1261 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1264 /* Return the maximum number of consecutive registers
1265 needed to represent mode MODE in a register of class CLASS. */
1266 /* On the 80386, this is the size of MODE in words,
1267 except in the FP regs, where a single reg is always enough. */
1268 #define CLASS_MAX_NREGS(CLASS, MODE) \
1269 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1270 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1271 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1272 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1274 /* A C expression whose value is nonzero if pseudos that have been
1275 assigned to registers of class CLASS would likely be spilled
1276 because registers of CLASS are needed for spill registers.
1278 The default value of this macro returns 1 if CLASS has exactly one
1279 register and zero otherwise. On most machines, this default
1280 should be used. Only define this macro to some other expression
1281 if pseudo allocated by `local-alloc.c' end up in memory because
1282 their hard registers were needed for spill registers. If this
1283 macro returns nonzero for those classes, those pseudos will only
1284 be allocated by `global.c', which knows how to reallocate the
1285 pseudo to another register. If there would not be another
1286 register available for reallocation, you should not change the
1287 definition of this macro since the only effect of such a
1288 definition would be to slow down register allocation. */
1290 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1291 (((CLASS) == AREG) \
1292 || ((CLASS) == DREG) \
1293 || ((CLASS) == CREG) \
1294 || ((CLASS) == BREG) \
1295 || ((CLASS) == AD_REGS) \
1296 || ((CLASS) == SIREG) \
1297 || ((CLASS) == DIREG) \
1298 || ((CLASS) == FP_TOP_REG) \
1299 || ((CLASS) == FP_SECOND_REG))
1301 /* Return a class of registers that cannot change FROM mode to TO mode. */
1303 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1304 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1306 /* Stack layout; function entry, exit and calling. */
1308 /* Define this if pushing a word on the stack
1309 makes the stack pointer a smaller address. */
1310 #define STACK_GROWS_DOWNWARD
1312 /* Define this to nonzero if the nominal address of the stack frame
1313 is at the high-address end of the local variables;
1314 that is, each additional local variable allocated
1315 goes at a more negative offset in the frame. */
1316 #define FRAME_GROWS_DOWNWARD 1
1318 /* Offset within stack frame to start allocating local variables at.
1319 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1320 first local allocated. Otherwise, it is the offset to the BEGINNING
1321 of the first local allocated. */
1322 #define STARTING_FRAME_OFFSET 0
1324 /* If we generate an insn to push BYTES bytes,
1325 this says how many the stack pointer really advances by.
1326 On 386, we have pushw instruction that decrements by exactly 2 no
1327 matter what the position was, there is no pushb.
1328 But as CIE data alignment factor on this arch is -4, we need to make
1329 sure all stack pointer adjustments are in multiple of 4.
1331 For 64bit ABI we round up to 8 bytes.
1334 #define PUSH_ROUNDING(BYTES) \
1336 ? (((BYTES) + 7) & (-8)) \
1337 : (((BYTES) + 3) & (-4)))
1339 /* If defined, the maximum amount of space required for outgoing arguments will
1340 be computed and placed into the variable
1341 `current_function_outgoing_args_size'. No space will be pushed onto the
1342 stack for each call; instead, the function prologue should increase the stack
1343 frame size by this amount. */
1345 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1347 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1348 instructions to pass outgoing arguments. */
1350 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1352 /* We want the stack and args grow in opposite directions, even if
1354 #define PUSH_ARGS_REVERSED 1
1356 /* Offset of first parameter from the argument pointer register value. */
1357 #define FIRST_PARM_OFFSET(FNDECL) 0
1359 /* Define this macro if functions should assume that stack space has been
1360 allocated for arguments even when their values are passed in registers.
1362 The value of this macro is the size, in bytes, of the area reserved for
1363 arguments passed in registers for the function represented by FNDECL.
1365 This space can be allocated by the caller, or be a part of the
1366 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1368 #define REG_PARM_STACK_SPACE(FNDECL) 0
1370 /* Value is the number of bytes of arguments automatically
1371 popped when returning from a subroutine call.
1372 FUNDECL is the declaration node of the function (as a tree),
1373 FUNTYPE is the data type of the function (as a tree),
1374 or for a library call it is an identifier node for the subroutine name.
1375 SIZE is the number of bytes of arguments passed on the stack.
1377 On the 80386, the RTD insn may be used to pop them if the number
1378 of args is fixed, but if the number is variable then the caller
1379 must pop them all. RTD can't be used for library calls now
1380 because the library is compiled with the Unix compiler.
1381 Use of RTD is a selectable option, since it is incompatible with
1382 standard Unix calling sequences. If the option is not selected,
1383 the caller must always pop the args.
1385 The attribute stdcall is equivalent to RTD on a per module basis. */
1387 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1388 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1390 #define FUNCTION_VALUE_REGNO_P(N) \
1391 ix86_function_value_regno_p (N)
1393 /* Define how to find the value returned by a library function
1394 assuming the value has mode MODE. */
1396 #define LIBCALL_VALUE(MODE) \
1397 ix86_libcall_value (MODE)
1399 /* Define the size of the result block used for communication between
1400 untyped_call and untyped_return. The block contains a DImode value
1401 followed by the block used by fnsave and frstor. */
1403 #define APPLY_RESULT_SIZE (8+108)
1405 /* 1 if N is a possible register number for function argument passing. */
1406 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1408 /* Define a data type for recording info about an argument list
1409 during the scan of that argument list. This data type should
1410 hold all necessary information about the function itself
1411 and about the args processed so far, enough to enable macros
1412 such as FUNCTION_ARG to determine where the next arg should go. */
1414 typedef struct ix86_args {
1415 int words; /* # words passed so far */
1416 int nregs; /* # registers available for passing */
1417 int regno; /* next available register number */
1418 int fastcall; /* fastcall calling convention is used */
1419 int sse_words; /* # sse words passed so far */
1420 int sse_nregs; /* # sse registers available for passing */
1421 int warn_sse; /* True when we want to warn about SSE ABI. */
1422 int warn_mmx; /* True when we want to warn about MMX ABI. */
1423 int sse_regno; /* next available sse register number */
1424 int mmx_words; /* # mmx words passed so far */
1425 int mmx_nregs; /* # mmx registers available for passing */
1426 int mmx_regno; /* next available mmx register number */
1427 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1428 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1429 be passed in SSE registers. Otherwise 0. */
1432 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1433 for a call to a function whose data type is FNTYPE.
1434 For a library call, FNTYPE is 0. */
1436 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1437 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1439 /* Update the data in CUM to advance over an argument
1440 of mode MODE and data type TYPE.
1441 (TYPE is null for libcalls where that information may not be available.) */
1443 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1444 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1446 /* Define where to put the arguments to a function.
1447 Value is zero to push the argument on the stack,
1448 or a hard register in which to store the argument.
1450 MODE is the argument's machine mode.
1451 TYPE is the data type of the argument (as a tree).
1452 This is null for libcalls where that information may
1454 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1455 the preceding args and about the function being called.
1456 NAMED is nonzero if this argument is a named parameter
1457 (otherwise it is an extra parameter matching an ellipsis). */
1459 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1460 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1462 /* Implement `va_start' for varargs and stdarg. */
1463 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1464 ix86_va_start (VALIST, NEXTARG)
1466 #define TARGET_ASM_FILE_END ix86_file_end
1467 #define NEED_INDICATE_EXEC_STACK 0
1469 /* Output assembler code to FILE to increment profiler label # LABELNO
1470 for profiling a function entry. */
1472 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1474 #define MCOUNT_NAME "_mcount"
1476 #define PROFILE_COUNT_REGISTER "edx"
1478 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1479 the stack pointer does not matter. The value is tested only in
1480 functions that have frame pointers.
1481 No definition is equivalent to always zero. */
1482 /* Note on the 386 it might be more efficient not to define this since
1483 we have to restore it ourselves from the frame pointer, in order to
1486 #define EXIT_IGNORE_STACK 1
1488 /* Output assembler code for a block containing the constant parts
1489 of a trampoline, leaving space for the variable parts. */
1491 /* On the 386, the trampoline contains two instructions:
1494 The trampoline is generated entirely at runtime. The operand of JMP
1495 is the address of FUNCTION relative to the instruction following the
1496 JMP (which is 5 bytes long). */
1498 /* Length in units of the trampoline for entering a nested function. */
1500 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1502 /* Emit RTL insns to initialize the variable parts of a trampoline.
1503 FNADDR is an RTX for the address of the function's pure code.
1504 CXT is an RTX for the static chain value for the function. */
1506 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1507 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1509 /* Definitions for register eliminations.
1511 This is an array of structures. Each structure initializes one pair
1512 of eliminable registers. The "from" register number is given first,
1513 followed by "to". Eliminations of the same "from" register are listed
1514 in order of preference.
1516 There are two registers that can always be eliminated on the i386.
1517 The frame pointer and the arg pointer can be replaced by either the
1518 hard frame pointer or to the stack pointer, depending upon the
1519 circumstances. The hard frame pointer is not used before reload and
1520 so it is not eligible for elimination. */
1522 #define ELIMINABLE_REGS \
1523 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1524 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1525 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1526 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1528 /* Given FROM and TO register numbers, say whether this elimination is
1529 allowed. Frame pointer elimination is automatically handled.
1531 All other eliminations are valid. */
1533 #define CAN_ELIMINATE(FROM, TO) \
1534 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1536 /* Define the offset between two registers, one to be eliminated, and the other
1537 its replacement, at the start of a routine. */
1539 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1540 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1542 /* Addressing modes, and classification of registers for them. */
1544 /* Macros to check register numbers against specific register classes. */
1546 /* These assume that REGNO is a hard or pseudo reg number.
1547 They give nonzero only if REGNO is a hard reg of the suitable class
1548 or a pseudo reg currently allocated to a suitable hard reg.
1549 Since they use reg_renumber, they are safe only once reg_renumber
1550 has been allocated, which happens in local-alloc.c. */
1552 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1553 ((REGNO) < STACK_POINTER_REGNUM \
1554 || (REGNO >= FIRST_REX_INT_REG \
1555 && (REGNO) <= LAST_REX_INT_REG) \
1556 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1557 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1558 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1560 #define REGNO_OK_FOR_BASE_P(REGNO) \
1561 ((REGNO) <= STACK_POINTER_REGNUM \
1562 || (REGNO) == ARG_POINTER_REGNUM \
1563 || (REGNO) == FRAME_POINTER_REGNUM \
1564 || (REGNO >= FIRST_REX_INT_REG \
1565 && (REGNO) <= LAST_REX_INT_REG) \
1566 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1567 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1568 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1570 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1571 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1572 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1573 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1575 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1576 and check its validity for a certain class.
1577 We have two alternate definitions for each of them.
1578 The usual definition accepts all pseudo regs; the other rejects
1579 them unless they have been allocated suitable hard regs.
1580 The symbol REG_OK_STRICT causes the latter definition to be used.
1582 Most source files want to accept pseudo regs in the hope that
1583 they will get allocated to the class that the insn wants them to be in.
1584 Source files for reload pass need to be strict.
1585 After reload, it makes no difference, since pseudo regs have
1586 been eliminated by then. */
1589 /* Non strict versions, pseudos are ok. */
1590 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1591 (REGNO (X) < STACK_POINTER_REGNUM \
1592 || (REGNO (X) >= FIRST_REX_INT_REG \
1593 && REGNO (X) <= LAST_REX_INT_REG) \
1594 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1596 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1597 (REGNO (X) <= STACK_POINTER_REGNUM \
1598 || REGNO (X) == ARG_POINTER_REGNUM \
1599 || REGNO (X) == FRAME_POINTER_REGNUM \
1600 || (REGNO (X) >= FIRST_REX_INT_REG \
1601 && REGNO (X) <= LAST_REX_INT_REG) \
1602 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1604 /* Strict versions, hard registers only */
1605 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1606 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1608 #ifndef REG_OK_STRICT
1609 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1610 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1613 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1614 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1617 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1618 that is a valid memory address for an instruction.
1619 The MODE argument is the machine mode for the MEM expression
1620 that wants to use this address.
1622 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1623 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1625 See legitimize_pic_address in i386.c for details as to what
1626 constitutes a legitimate address when -fpic is used. */
1628 #define MAX_REGS_PER_ADDRESS 2
1630 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1632 /* Nonzero if the constant value X is a legitimate general operand.
1633 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1635 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1637 #ifdef REG_OK_STRICT
1638 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1640 if (legitimate_address_p ((MODE), (X), 1)) \
1645 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1647 if (legitimate_address_p ((MODE), (X), 0)) \
1653 /* If defined, a C expression to determine the base term of address X.
1654 This macro is used in only one place: `find_base_term' in alias.c.
1656 It is always safe for this macro to not be defined. It exists so
1657 that alias analysis can understand machine-dependent addresses.
1659 The typical use of this macro is to handle addresses containing
1660 a label_ref or symbol_ref within an UNSPEC. */
1662 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1664 /* Try machine-dependent ways of modifying an illegitimate address
1665 to be legitimate. If we find one, return the new, valid address.
1666 This macro is used in only one place: `memory_address' in explow.c.
1668 OLDX is the address as it was before break_out_memory_refs was called.
1669 In some cases it is useful to look at this to decide what needs to be done.
1671 MODE and WIN are passed so that this macro can use
1672 GO_IF_LEGITIMATE_ADDRESS.
1674 It is always safe for this macro to do nothing. It exists to recognize
1675 opportunities to optimize the output.
1677 For the 80386, we handle X+REG by loading X into a register R and
1678 using R+REG. R will go in a general reg and indexing will be used.
1679 However, if REG is a broken-out memory address or multiplication,
1680 nothing needs to be done because REG can certainly go in a general reg.
1682 When -fpic is used, special handling is needed for symbolic references.
1683 See comments by legitimize_pic_address in i386.c for details. */
1685 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1687 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1688 if (memory_address_p ((MODE), (X))) \
1692 #define REWRITE_ADDRESS(X) rewrite_address (X)
1694 /* Nonzero if the constant value X is a legitimate general operand
1695 when generating PIC code. It is given that flag_pic is on and
1696 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1698 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1700 #define SYMBOLIC_CONST(X) \
1701 (GET_CODE (X) == SYMBOL_REF \
1702 || GET_CODE (X) == LABEL_REF \
1703 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1705 /* Go to LABEL if ADDR (a legitimate address expression)
1706 has an effect that depends on the machine mode it is used for.
1707 On the 80386, only postdecrement and postincrement address depend thus
1708 (the amount of decrement or increment being the length of the operand). */
1709 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1711 if (GET_CODE (ADDR) == POST_INC \
1712 || GET_CODE (ADDR) == POST_DEC) \
1716 /* Max number of args passed in registers. If this is more than 3, we will
1717 have problems with ebx (register #4), since it is a caller save register and
1718 is also used as the pic register in ELF. So for now, don't allow more than
1719 3 registers to be passed in registers. */
1721 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1723 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1725 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1728 /* Specify the machine mode that this machine uses
1729 for the index in the tablejump instruction. */
1730 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
1732 /* Define this as 1 if `char' should by default be signed; else as 0. */
1733 #define DEFAULT_SIGNED_CHAR 1
1735 /* Number of bytes moved into a data cache for a single prefetch operation. */
1736 #define PREFETCH_BLOCK ix86_cost->prefetch_block
1738 /* Number of prefetch operations that can be done in parallel. */
1739 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
1741 /* Max number of bytes we can move from memory to memory
1742 in one reasonably fast instruction. */
1745 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1746 move efficiently, as opposed to MOVE_MAX which is the maximum
1747 number of bytes we can move with a single instruction. */
1748 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1750 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1751 move-instruction pairs, we will do a movmem or libcall instead.
1752 Increasing the value will always make code faster, but eventually
1753 incurs high cost in increased code size.
1755 If you don't define this, a reasonable default is used. */
1757 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1759 /* If a clear memory operation would take CLEAR_RATIO or more simple
1760 move-instruction sequences, we will do a clrmem or libcall instead. */
1762 #define CLEAR_RATIO (optimize_size ? 2 \
1763 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1765 /* Define if shifts truncate the shift count
1766 which implies one can omit a sign-extension or zero-extension
1767 of a shift count. */
1768 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1770 /* #define SHIFT_COUNT_TRUNCATED */
1772 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1773 is done just by pretending it is already truncated. */
1774 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1776 /* A macro to update M and UNSIGNEDP when an object whose type is
1777 TYPE and which has the specified mode and signedness is to be
1778 stored in a register. This macro is only called when TYPE is a
1781 On i386 it is sometimes useful to promote HImode and QImode
1782 quantities to SImode. The choice depends on target type. */
1784 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1786 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1787 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1791 /* Specify the machine mode that pointers have.
1792 After generation of rtl, the compiler makes no further distinction
1793 between pointers and any other objects of this machine mode. */
1794 #define Pmode (TARGET_64BIT ? DImode : SImode)
1796 /* A function address in a call instruction
1797 is a byte address (for indexing purposes)
1798 so give the MEM rtx a byte's mode. */
1799 #define FUNCTION_MODE QImode
1801 /* A C expression for the cost of moving data from a register in class FROM to
1802 one in class TO. The classes are expressed using the enumeration values
1803 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1804 interpreted relative to that.
1806 It is not required that the cost always equal 2 when FROM is the same as TO;
1807 on some machines it is expensive to move between registers if they are not
1808 general registers. */
1810 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1811 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1813 /* A C expression for the cost of moving data of mode M between a
1814 register and memory. A value of 2 is the default; this cost is
1815 relative to those in `REGISTER_MOVE_COST'.
1817 If moving between registers and memory is more expensive than
1818 between two registers, you should define this macro to express the
1821 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1822 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1824 /* A C expression for the cost of a branch instruction. A value of 1
1825 is the default; other values are interpreted relative to that. */
1827 #define BRANCH_COST ix86_branch_cost
1829 /* Define this macro as a C expression which is nonzero if accessing
1830 less than a word of memory (i.e. a `char' or a `short') is no
1831 faster than accessing a word of memory, i.e., if such access
1832 require more than one instruction or if there is no difference in
1833 cost between byte and (aligned) word loads.
1835 When this macro is not defined, the compiler will access a field by
1836 finding the smallest containing object; when it is defined, a
1837 fullword load will be used if alignment permits. Unless bytes
1838 accesses are faster than word accesses, using word accesses is
1839 preferable since it may eliminate subsequent memory access if
1840 subsequent accesses occur to other fields in the same word of the
1841 structure, but to different bytes. */
1843 #define SLOW_BYTE_ACCESS 0
1845 /* Nonzero if access to memory by shorts is slow and undesirable. */
1846 #define SLOW_SHORT_ACCESS 0
1848 /* Define this macro to be the value 1 if unaligned accesses have a
1849 cost many times greater than aligned accesses, for example if they
1850 are emulated in a trap handler.
1852 When this macro is nonzero, the compiler will act as if
1853 `STRICT_ALIGNMENT' were nonzero when generating code for block
1854 moves. This can cause significantly more instructions to be
1855 produced. Therefore, do not set this macro nonzero if unaligned
1856 accesses only add a cycle or two to the time for a memory access.
1858 If the value of this macro is always zero, it need not be defined. */
1860 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1862 /* Define this macro if it is as good or better to call a constant
1863 function address than to call an address kept in a register.
1865 Desirable on the 386 because a CALL with a constant address is
1866 faster than one with a register address. */
1868 #define NO_FUNCTION_CSE
1870 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1871 return the mode to be used for the comparison.
1873 For floating-point equality comparisons, CCFPEQmode should be used.
1874 VOIDmode should be used in all other cases.
1876 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1877 possible, to allow for more combinations. */
1879 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1881 /* Return nonzero if MODE implies a floating point inequality can be
1884 #define REVERSIBLE_CC_MODE(MODE) 1
1886 /* A C expression whose value is reversed condition code of the CODE for
1887 comparison done in CC_MODE mode. */
1888 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1891 /* Control the assembler format that we output, to the extent
1892 this does not vary between assemblers. */
1894 /* How to refer to registers in assembler output.
1895 This sequence is indexed by compiler's hard-register-number (see above). */
1897 /* In order to refer to the first 8 regs as 32 bit regs, prefix an "e".
1898 For non floating point regs, the following are the HImode names.
1900 For float regs, the stack top is sometimes referred to as "%st(0)"
1901 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
1903 #define HI_REGISTER_NAMES \
1904 {"ax","dx","cx","bx","si","di","bp","sp", \
1905 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1906 "argp", "flags", "fpsr", "dirflag", "frame", \
1907 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1908 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
1909 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1910 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1912 #define REGISTER_NAMES HI_REGISTER_NAMES
1914 /* Table of additional register names to use in user input. */
1916 #define ADDITIONAL_REGISTER_NAMES \
1917 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1918 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1919 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1920 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1921 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1922 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1924 /* Note we are omitting these since currently I don't know how
1925 to get gcc to use these, since they want the same but different
1926 number as al, and ax.
1929 #define QI_REGISTER_NAMES \
1930 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1932 /* These parallel the array above, and can be used to access bits 8:15
1933 of regs 0 through 3. */
1935 #define QI_HIGH_REGISTER_NAMES \
1936 {"ah", "dh", "ch", "bh", }
1938 /* How to renumber registers for dbx and gdb. */
1940 #define DBX_REGISTER_NUMBER(N) \
1941 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
1943 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
1944 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
1945 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
1947 /* Before the prologue, RA is at 0(%esp). */
1948 #define INCOMING_RETURN_ADDR_RTX \
1949 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1951 /* After the prologue, RA is at -4(AP) in the current frame. */
1952 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1954 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
1955 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
1957 /* PC is dbx register 8; let's use that column for RA. */
1958 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
1960 /* Before the prologue, the top of the frame is at 4(%esp). */
1961 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
1963 /* Describe how we implement __builtin_eh_return. */
1964 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
1965 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
1968 /* Select a format to encode pointers in exception handling data. CODE
1969 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1970 true if the symbol may be affected by dynamic relocations.
1972 ??? All x86 object file formats are capable of representing this.
1973 After all, the relocation needed is the same as for the call insn.
1974 Whether or not a particular assembler allows us to enter such, I
1975 guess we'll have to see. */
1976 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1977 asm_preferred_eh_data_format ((CODE), (GLOBAL))
1979 /* This is how to output an insn to push a register on the stack.
1980 It need not be very fast code. */
1982 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
1985 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
1986 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
1988 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
1991 /* This is how to output an insn to pop a register from the stack.
1992 It need not be very fast code. */
1994 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
1997 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
1998 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2000 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2003 /* This is how to output an element of a case-vector that is absolute. */
2005 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2006 ix86_output_addr_vec_elt ((FILE), (VALUE))
2008 /* This is how to output an element of a case-vector that is relative. */
2010 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2011 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2013 /* Under some conditions we need jump tables in the text section,
2014 because the assembler cannot handle label differences between
2015 sections. This is the case for x86_64 on Mach-O for example. */
2017 #define JUMP_TABLES_IN_TEXT_SECTION \
2018 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2019 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2021 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2022 and switch back. For x86 we do this only to save a few bytes that
2023 would otherwise be unused in the text section. */
2024 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2025 asm (SECTION_OP "\n\t" \
2026 "call " USER_LABEL_PREFIX #FUNC "\n" \
2027 TEXT_SECTION_ASM_OP);
2029 /* Print operand X (an rtx) in assembler syntax to file FILE.
2030 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2031 Effect of various CODE letters is described in i386.c near
2032 print_operand function. */
2034 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2035 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2037 #define PRINT_OPERAND(FILE, X, CODE) \
2038 print_operand ((FILE), (X), (CODE))
2040 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2041 print_operand_address ((FILE), (ADDR))
2043 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2045 if (! output_addr_const_extra (FILE, (X))) \
2049 /* a letter which is not needed by the normal asm syntax, which
2050 we can use for operand syntax in the extended asm */
2052 #define ASM_OPERAND_LETTER '#'
2053 #define RET return ""
2054 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2056 /* Which processor to schedule for. The cpu attribute defines a list that
2057 mirrors this list, so changes to i386.md must be made at the same time. */
2061 PROCESSOR_I386, /* 80386 */
2062 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2064 PROCESSOR_PENTIUMPRO,
2070 PROCESSOR_GENERIC32,
2071 PROCESSOR_GENERIC64,
2075 extern enum processor_type ix86_tune;
2076 extern enum processor_type ix86_arch;
2084 extern enum fpmath_unit ix86_fpmath;
2093 extern enum tls_dialect ix86_tls_dialect;
2096 CM_32, /* The traditional 32-bit ABI. */
2097 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2098 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2099 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2100 CM_LARGE, /* No assumptions. */
2101 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2102 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */
2105 extern enum cmodel ix86_cmodel;
2107 /* Size of the RED_ZONE area. */
2108 #define RED_ZONE_SIZE 128
2109 /* Reserved area of the red zone for temporaries. */
2110 #define RED_ZONE_RESERVE 8
2117 extern enum asm_dialect ix86_asm_dialect;
2118 extern unsigned int ix86_preferred_stack_boundary;
2119 extern int ix86_branch_cost, ix86_section_threshold;
2121 /* Smallest class containing REGNO. */
2122 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2124 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2125 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2126 extern rtx ix86_compare_emitted;
2128 /* To properly truncate FP values into integers, we need to set i387 control
2129 word. We can't emit proper mode switching code before reload, as spills
2130 generated by reload may truncate values incorrectly, but we still can avoid
2131 redundant computation of new control word by the mode switching pass.
2132 The fldcw instructions are still emitted redundantly, but this is probably
2133 not going to be noticeable problem, as most CPUs do have fast path for
2136 The machinery is to emit simple truncation instructions and split them
2137 before reload to instructions having USEs of two memory locations that
2138 are filled by this code to old and new control word.
2140 Post-reload pass may be later used to eliminate the redundant fildcw if
2152 enum ix86_stack_slot
2160 MAX_386_STACK_LOCALS
2163 /* Define this macro if the port needs extra instructions inserted
2164 for mode switching in an optimizing compilation. */
2166 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2167 ix86_optimize_mode_switching[(ENTITY)]
2169 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2170 initializer for an array of integers. Each initializer element N
2171 refers to an entity that needs mode switching, and specifies the
2172 number of different modes that might need to be set for this
2173 entity. The position of the initializer in the initializer -
2174 starting counting at zero - determines the integer that is used to
2175 refer to the mode-switched entity in question. */
2177 #define NUM_MODES_FOR_MODE_SWITCHING \
2178 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2180 /* ENTITY is an integer specifying a mode-switched entity. If
2181 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2182 return an integer value not larger than the corresponding element
2183 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2184 must be switched into prior to the execution of INSN. */
2186 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2188 /* This macro specifies the order in which modes for ENTITY are
2189 processed. 0 is the highest priority. */
2191 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2193 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2194 is the set of hard registers live at the point where the insn(s)
2195 are to be inserted. */
2197 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2198 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2199 ? emit_i387_cw_initialization (MODE), 0 \
2203 /* Avoid renaming of stack registers, as doing so in combination with
2204 scheduling just increases amount of live registers at time and in
2205 the turn amount of fxch instructions needed.
2207 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2209 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2210 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
2213 #define DLL_IMPORT_EXPORT_PREFIX '#'
2215 #define FASTCALL_PREFIX '@'
2217 struct machine_function GTY(())
2219 struct stack_local_entry *stack_locals;
2220 const char *some_ld_name;
2221 rtx force_align_arg_pointer;
2222 int save_varrargs_registers;
2223 int accesses_prev_frame;
2224 int optimize_mode_switching[MAX_386_ENTITIES];
2225 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2226 determine the style used. */
2227 int use_fast_prologue_epilogue;
2228 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2230 int use_fast_prologue_epilogue_nregs;
2231 /* If true, the current function needs the default PIC register, not
2232 an alternate register (on x86) and must not use the red zone (on
2233 x86_64), even if it's a leaf function. We don't want the
2234 function to be regarded as non-leaf because TLS calls need not
2235 affect register allocation. This flag is set when a TLS call
2236 instruction is expanded within a function, and never reset, even
2237 if all such instructions are optimized away. Use the
2238 ix86_current_function_calls_tls_descriptor macro for a better
2240 int tls_descriptor_call_expanded_p;
2243 #define ix86_stack_locals (cfun->machine->stack_locals)
2244 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2245 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2246 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2247 (cfun->machine->tls_descriptor_call_expanded_p)
2248 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2249 calls are optimized away, we try to detect cases in which it was
2250 optimized away. Since such instructions (use (reg REG_SP)), we can
2251 verify whether there's any such instruction live by testing that
2253 #define ix86_current_function_calls_tls_descriptor \
2254 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
2256 /* Control behavior of x86_file_start. */
2257 #define X86_FILE_START_VERSION_DIRECTIVE false
2258 #define X86_FILE_START_FLTUSED false
2260 /* Flag to mark data that is in the large address area. */
2261 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2262 #define SYMBOL_REF_FAR_ADDR_P(X) \
2263 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)