1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) X
48 #define HALF_PIC_FINISH(STREAM)
51 /* Define the specific costs for a given cpu */
53 struct processor_costs {
54 int add; /* cost of an add instruction */
55 int lea; /* cost of a lea instruction */
56 int shift_var; /* variable shift costs */
57 int shift_const; /* constant shift costs */
58 int mult_init; /* cost of starting a multiply */
59 int mult_bit; /* cost of multiply per each bit set */
60 int divide; /* cost of a divide/mod */
61 int large_insn; /* insns larger than this cost more */
62 int move_ratio; /* The threshold of number of scalar
63 memory-to-memory move insns. */
64 int movzbl_load; /* cost of loading using movzbl */
65 int int_load[3]; /* cost of loading integer registers
66 in QImode, HImode and SImode relative
67 to reg-reg move (2). */
68 int int_store[3]; /* cost of storing integer register
69 in QImode, HImode and SImode */
70 int fp_move; /* cost of reg,reg fld/fst */
71 int fp_load[3]; /* cost of loading FP register
72 in SFmode, DFmode and XFmode */
73 int fp_store[3]; /* cost of storing FP register
74 in SFmode, DFmode and XFmode */
75 int mmx_move; /* cost of moving MMX register. */
76 int mmx_load[2]; /* cost of loading MMX register
77 in SImode and DImode */
78 int mmx_store[2]; /* cost of storing MMX register
79 in SImode and DImode */
80 int sse_move; /* cost of moving SSE register. */
81 int sse_load[3]; /* cost of loading SSE register
82 in SImode, DImode and TImode*/
83 int sse_store[3]; /* cost of storing SSE register
84 in SImode, DImode and TImode*/
85 int mmxsse_to_integer; /* cost of moving mmxsse register to
86 integer and vice versa. */
89 extern struct processor_costs *ix86_cost;
91 /* Run-time compilation parameters selecting different hardware subsets. */
93 extern int target_flags;
95 /* Macros used in the machine description to test the flags. */
97 /* configure can arrange to make this 2, to force a 486. */
99 #ifndef TARGET_CPU_DEFAULT
100 #define TARGET_CPU_DEFAULT 0
103 /* Masks for the -m switches */
104 #define MASK_80387 0x00000001 /* Hardware floating point */
105 #define MASK_RTD 0x00000002 /* Use ret that pops args */
106 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
107 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
108 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
109 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
110 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
111 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
112 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
113 #define MASK_NO_ALIGN_STROPS 0x00001000 /* Enable aligning of string ops. */
114 #define MASK_INLINE_ALL_STROPS 0x00002000 /* Inline stringops in all cases */
115 #define MASK_NO_PUSH_ARGS 0x00004000 /* Use push instructions */
116 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00008000/* Accumulate outgoing args */
117 #define MASK_NO_ACCUMULATE_OUTGOING_ARGS 0x00010000
118 #define MASK_MMX 0x00020000 /* Support MMX regs/builtins */
119 #define MASK_SSE 0x00040000 /* Support SSE regs/builtins */
120 #define MASK_SSE2 0x00080000 /* Support SSE2 regs/builtins */
121 #define MASK_128BIT_LONG_DOUBLE 0x00100000 /* long double size is 128bit */
122 #define MASK_MIX_SSE_I387 0x00200000 /* Mix SSE and i387 instructions */
123 #define MASK_64BIT 0x00400000 /* Produce 64bit code */
124 #define MASK_NO_RED_ZONE 0x00800000 /* Do not use red zone */
126 /* Temporary codegen switches */
127 #define MASK_INTEL_SYNTAX 0x00000200
128 #define MASK_DEBUG_ARG 0x00000400 /* function_arg */
129 #define MASK_DEBUG_ADDR 0x00000800 /* GO_IF_LEGITIMATE_ADDRESS */
131 /* Use the floating point instructions */
132 #define TARGET_80387 (target_flags & MASK_80387)
134 /* Compile using ret insn that pops args.
135 This will not work unless you use prototypes at least
136 for all functions that can take varying numbers of args. */
137 #define TARGET_RTD (target_flags & MASK_RTD)
139 /* Align doubles to a two word boundary. This breaks compatibility with
140 the published ABI's for structures containing doubles, but produces
141 faster code on the pentium. */
142 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
144 /* Use push instructions to save outgoing args. */
145 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
147 /* Accumulate stack adjustments to prologue/epilogue. */
148 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
149 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
151 /* Put uninitialized locals into bss, not data.
152 Meaningful only on svr3. */
153 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
155 /* Use IEEE floating point comparisons. These handle correctly the cases
156 where the result of a comparison is unordered. Normally SIGFPE is
157 generated in such cases, in which case this isn't needed. */
158 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
160 /* Functions that return a floating point value may return that value
161 in the 387 FPU or in 386 integer registers. If set, this flag causes
162 the 387 to be used, which is compatible with most calling conventions. */
163 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
165 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
166 This mode wastes cache, but avoid missaligned data accesses and simplifies
167 address calculations. */
168 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
170 /* Disable generation of FP sin, cos and sqrt operations for 387.
171 This is because FreeBSD lacks these in the math-emulator-code */
172 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
174 /* Don't create frame pointers for leaf functions */
175 #define TARGET_OMIT_LEAF_FRAME_POINTER \
176 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
178 /* Debug GO_IF_LEGITIMATE_ADDRESS */
179 #define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR)
181 /* Debug FUNCTION_ARG macros */
182 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
184 /* 64bit Sledgehammer mode */
185 #ifdef TARGET_BI_ARCH
186 #define TARGET_64BIT (target_flags & MASK_64BIT)
188 #ifdef TARGET_64BIT_DEFAULT
189 #define TARGET_64BIT 1
191 #define TARGET_64BIT 0
195 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
196 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
197 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
198 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
199 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
200 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
201 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
203 #define CPUMASK (1 << ix86_cpu)
204 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
205 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
206 extern const int x86_branch_hints, x86_unroll_strlen;
207 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
208 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
209 extern const int x86_use_cltd, x86_read_modify_write;
210 extern const int x86_read_modify, x86_split_long_moves;
211 extern const int x86_promote_QImode, x86_single_stringop;
212 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
213 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
214 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
215 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
216 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
217 extern const int x86_epilogue_using_move;
219 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
220 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
221 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
222 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
223 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
224 /* For sane SSE instruction set generation we need fcomi instruction. It is
225 safe to enable all CMOVE instructions. */
226 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
227 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
228 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
229 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
230 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
231 #define TARGET_MOVX (x86_movx & CPUMASK)
232 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
233 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
234 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
235 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
236 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
237 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
238 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
239 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
240 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
241 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
242 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
243 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
244 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
245 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
246 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
247 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
248 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
249 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
250 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
251 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
252 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
253 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
254 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
256 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
258 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
259 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
261 #define ASSEMBLER_DIALECT ((target_flags & MASK_INTEL_SYNTAX) != 0)
263 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
264 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
265 #define TARGET_MIX_SSE_I387 ((target_flags & MASK_MIX_SSE_I387) != 0)
266 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
268 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
270 #define TARGET_SWITCHES \
271 { { "80387", MASK_80387, N_("Use hardware fp") }, \
272 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
273 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
274 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
275 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
276 { "386", 0, N_("Same as -mcpu=i386") }, \
277 { "486", 0, N_("Same as -mcpu=i486") }, \
278 { "pentium", 0, N_("Same as -mcpu=pentium") }, \
279 { "pentiumpro", 0, N_("Same as -mcpu=pentiumpro") }, \
281 N_("Alternate calling convention") }, \
282 { "no-rtd", -MASK_RTD, \
283 N_("Use normal calling convention") }, \
284 { "align-double", MASK_ALIGN_DOUBLE, \
285 N_("Align some doubles on dword boundary") }, \
286 { "no-align-double", -MASK_ALIGN_DOUBLE, \
287 N_("Align doubles on word boundary") }, \
288 { "svr3-shlib", MASK_SVR3_SHLIB, \
289 N_("Uninitialized locals in .bss") }, \
290 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
291 N_("Uninitialized locals in .data") }, \
292 { "ieee-fp", MASK_IEEE_FP, \
293 N_("Use IEEE math for fp comparisons") }, \
294 { "no-ieee-fp", -MASK_IEEE_FP, \
295 N_("Do not use IEEE math for fp comparisons") }, \
296 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
297 N_("Return values of functions in FPU registers") }, \
298 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
299 N_("Do not return values of functions in FPU registers")}, \
300 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
301 N_("Do not generate sin, cos, sqrt for FPU") }, \
302 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
303 N_("Generate sin, cos, sqrt for FPU")}, \
304 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
305 N_("Omit the frame pointer in leaf functions") }, \
306 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
307 { "debug-addr", MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
308 { "no-debug-addr", -MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
309 { "debug-arg", MASK_DEBUG_ARG, 0 /* undocumented */ }, \
310 { "no-debug-arg", -MASK_DEBUG_ARG, 0 /* undocumented */ }, \
311 { "stack-arg-probe", MASK_STACK_PROBE, \
312 N_("Enable stack probing") }, \
313 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
314 { "windows", 0, 0 /* undocumented */ }, \
315 { "dll", 0, 0 /* undocumented */ }, \
316 { "intel-syntax", MASK_INTEL_SYNTAX, \
317 N_("Emit Intel syntax assembler opcodes") }, \
318 { "no-intel-syntax", -MASK_INTEL_SYNTAX, "" }, \
319 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
320 N_("Align destination of the string operations") }, \
321 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
322 N_("Do not align destination of the string operations") }, \
323 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
324 N_("Inline all known string operations") }, \
325 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
326 N_("Do not inline all known string operations") }, \
327 { "push-args", -MASK_NO_PUSH_ARGS, \
328 N_("Use push instructions to save outgoing arguments") }, \
329 { "no-push-args", MASK_NO_PUSH_ARGS, \
330 N_("Do not use push instructions to save outgoing arguments") }, \
331 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
332 N_("Use push instructions to save outgoing arguments") }, \
333 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
334 N_("Do not use push instructions to save outgoing arguments") }, \
335 { "mmx", MASK_MMX, N_("Support MMX builtins") }, \
336 { "no-mmx", -MASK_MMX, \
337 N_("Do not support MMX builtins") }, \
339 N_("Support MMX and SSE builtins and code generation") }, \
340 { "no-sse", -MASK_SSE, \
341 N_("Do not support MMX and SSE builtins and code generation") }, \
342 { "sse2", MASK_SSE2, \
343 N_("Support MMX, SSE and SSE2 builtins and code generation") }, \
344 { "no-sse2", -MASK_SSE2, \
345 N_("Do not support MMX, SSE and SSE2 builtins and code generation") }, \
346 { "mix-sse-i387", MASK_MIX_SSE_I387, \
347 N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
348 { "nomix-sse-i387", -MASK_MIX_SSE_I387, \
349 N_("Use both SSE and i387 instruction sets for floating point arithmetics") },\
350 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
351 N_("sizeof(long double) is 16.") }, \
352 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
353 N_("sizeof(long double) is 12.") }, \
354 { "64", MASK_64BIT, \
355 N_("Generate 64bit x86-64 code") }, \
356 { "32", -MASK_64BIT, \
357 N_("Generate 32bit i386 code") }, \
358 { "red-zone", -MASK_NO_RED_ZONE, \
359 N_("Use red-zone in the x86-64 code") }, \
360 { "no-red-zone", MASK_NO_RED_ZONE, \
361 N_("do not use red-zone in the x86-64 code") }, \
363 { "", TARGET_DEFAULT, 0 }}
365 #ifdef TARGET_64BIT_DEFAULT
366 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
368 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
371 /* Which processor to schedule for. The cpu attribute defines a list that
372 mirrors this list, so changes to i386.md must be made at the same time. */
376 PROCESSOR_I386, /* 80386 */
377 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
379 PROCESSOR_PENTIUMPRO,
386 extern enum processor_type ix86_cpu;
388 extern int ix86_arch;
390 /* This macro is similar to `TARGET_SWITCHES' but defines names of
391 command options that have values. Its definition is an
392 initializer with a subgrouping for each command option.
394 Each subgrouping contains a string constant, that defines the
395 fixed part of the option name, and the address of a variable. The
396 variable, type `char *', is set to the variable part of the given
397 option if the fixed part matches. The actual option name is made
398 by appending `-m' to the specified name. */
399 #define TARGET_OPTIONS \
400 { { "cpu=", &ix86_cpu_string, \
401 N_("Schedule code for given CPU")}, \
402 { "arch=", &ix86_arch_string, \
403 N_("Generate code for given CPU")}, \
404 { "regparm=", &ix86_regparm_string, \
405 N_("Number of registers used to pass integer arguments") }, \
406 { "align-loops=", &ix86_align_loops_string, \
407 N_("Loop code aligned to this power of 2") }, \
408 { "align-jumps=", &ix86_align_jumps_string, \
409 N_("Jump targets are aligned to this power of 2") }, \
410 { "align-functions=", &ix86_align_funcs_string, \
411 N_("Function starts are aligned to this power of 2") }, \
412 { "preferred-stack-boundary=", \
413 &ix86_preferred_stack_boundary_string, \
414 N_("Attempt to keep stack aligned to this power of 2") }, \
415 { "branch-cost=", &ix86_branch_cost_string, \
416 N_("Branches are this expensive (1-5, arbitrary units)") }, \
417 { "cmodel=", &ix86_cmodel_string, \
418 N_("Use given x86-64 code model") }, \
422 /* Sometimes certain combinations of command options do not make
423 sense on a particular target machine. You can define a macro
424 `OVERRIDE_OPTIONS' to take account of this. This macro, if
425 defined, is executed once just after all the command options have
428 Don't use this macro to turn on various extra optimizations for
429 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
431 #define OVERRIDE_OPTIONS override_options ()
433 /* These are meant to be redefined in the host dependent files */
434 #define SUBTARGET_SWITCHES
435 #define SUBTARGET_OPTIONS
437 /* Define this to change the optimizations performed by default. */
438 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
440 /* Specs for the compiler proper */
443 #define CC1_CPU_SPEC "\
446 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
448 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
449 %{mpentium:-mcpu=pentium \
450 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
451 %{mpentiumpro:-mcpu=pentiumpro \
452 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}}"
455 #ifndef CPP_CPU_DEFAULT_SPEC
456 #if TARGET_CPU_DEFAULT == 1
457 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
459 #if TARGET_CPU_DEFAULT == 2
460 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
462 #if TARGET_CPU_DEFAULT == 3
463 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
465 #if TARGET_CPU_DEFAULT == 4
466 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
468 #if TARGET_CPU_DEFAULT == 5
469 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
471 #if TARGET_CPU_DEFAULT == 6
472 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
474 #ifndef CPP_CPU_DEFAULT_SPEC
475 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
477 #endif /* CPP_CPU_DEFAULT_SPEC */
479 #ifdef NO_BUILTIN_SIZE_TYPE
480 #define CPP_CPU32_SIZE_TYPE_SPEC \
481 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
482 #define CPP_CPU64_SIZE_TYPE_SPEC \
483 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int"
485 #define CPP_CPU32_SIZE_TYPE_SPEC ""
486 #define CPP_CPU64_SIZE_TYPE_SPEC ""
489 #define CPP_CPU32_SPEC \
490 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
491 -D__i386__ %(cpp_cpu32sizet)"
493 #define CPP_CPU64_SPEC \
494 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)"
496 #define CPP_CPUCOMMON_SPEC "\
497 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
498 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
499 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
500 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
501 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
502 -D__pentiumpro -D__pentiumpro__ \
503 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
504 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
505 %{march=athlon:-D__athlon -D__athlon__ %{!mcpu*:-D__tune_athlon__ }}\
506 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
507 %{m386|mcpu=i386:-D__tune_i386__ }\
508 %{m486|mcpu=i486:-D__tune_i486__ }\
509 %{mpentium|mcpu=pentium|mcpu=i586:-D__tune_i586__ -D__tune_pentium__ }\
510 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686:-D__tune_i686__ -D__tune_pentiumpro__ }\
511 %{mcpu=k6:-D__tune_k6__ }\
512 %{mcpu=athlon:-D__tune_athlon__ }\
513 %{mcpu=pentium4:-D__tune_pentium4__ }\
514 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
517 #ifdef TARGET_BI_ARCH
518 #ifdef TARGET_64BIT_DEFAULT
519 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
521 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
524 #ifdef TARGET_64BIT_DEFAULT
525 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
527 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
533 #define CC1_SPEC "%(cc1_cpu) "
536 /* This macro defines names of additional specifications to put in the
537 specs that can be used in various specifications like CC1_SPEC. Its
538 definition is an initializer with a subgrouping for each command option.
540 Each subgrouping contains a string constant, that defines the
541 specification name, and a string constant that used by the GNU CC driver
544 Do not define this macro if it does not need to do anything. */
546 #ifndef SUBTARGET_EXTRA_SPECS
547 #define SUBTARGET_EXTRA_SPECS
550 #define EXTRA_SPECS \
551 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
552 { "cpp_cpu", CPP_CPU_SPEC }, \
553 { "cpp_cpu32", CPP_CPU32_SPEC }, \
554 { "cpp_cpu64", CPP_CPU64_SPEC }, \
555 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \
556 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \
557 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
558 { "cc1_cpu", CC1_CPU_SPEC }, \
559 SUBTARGET_EXTRA_SPECS
561 /* target machine storage layout */
563 /* Define for XFmode or TFmode extended real floating point support.
564 This will automatically cause REAL_ARITHMETIC to be defined.
566 The XFmode is specified by i386 ABI, while TFmode may be faster
567 due to alignment and simplifications in the address calculations.
569 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
570 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
572 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
574 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
576 /* Tell real.c that this is the 80-bit Intel extended float format
577 packaged in a 128-bit or 96bit entity. */
578 #define INTEL_EXTENDED_IEEE_FORMAT 1
581 #define SHORT_TYPE_SIZE 16
582 #define INT_TYPE_SIZE 32
583 #define FLOAT_TYPE_SIZE 32
584 #define LONG_TYPE_SIZE BITS_PER_WORD
585 #define MAX_WCHAR_TYPE_SIZE 32
586 #define DOUBLE_TYPE_SIZE 64
587 #define LONG_LONG_TYPE_SIZE 64
589 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
590 #define MAX_BITS_PER_WORD 64
591 #define MAX_LONG_TYPE_SIZE 64
593 #define MAX_BITS_PER_WORD 32
594 #define MAX_LONG_TYPE_SIZE 32
597 /* Define if you don't want extended real, but do want to use the
598 software floating point emulator for REAL_ARITHMETIC and
599 decimal <-> binary conversion. */
600 /* #define REAL_ARITHMETIC */
602 /* Define this if most significant byte of a word is the lowest numbered. */
603 /* That is true on the 80386. */
605 #define BITS_BIG_ENDIAN 0
607 /* Define this if most significant byte of a word is the lowest numbered. */
608 /* That is not true on the 80386. */
609 #define BYTES_BIG_ENDIAN 0
611 /* Define this if most significant word of a multiword number is the lowest
613 /* Not true for 80386 */
614 #define WORDS_BIG_ENDIAN 0
616 /* number of bits in an addressable storage unit */
617 #define BITS_PER_UNIT 8
619 /* Width in bits of a "word", which is the contents of a machine register.
620 Note that this is not necessarily the width of data type `int';
621 if using 16-bit ints on a 80386, this would still be 32.
622 But on a machine with 16-bit registers, this would be 16. */
623 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
625 /* Width of a word, in units (bytes). */
626 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
627 #define MIN_UNITS_PER_WORD 4
629 /* Width in bits of a pointer.
630 See also the macro `Pmode' defined below. */
631 #define POINTER_SIZE BITS_PER_WORD
633 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
634 #define PARM_BOUNDARY BITS_PER_WORD
636 /* Boundary (in *bits*) on which stack pointer should be aligned. */
637 #define STACK_BOUNDARY BITS_PER_WORD
639 /* Boundary (in *bits*) on which the stack pointer preferrs to be
640 aligned; the compiler cannot rely on having this alignment. */
641 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
643 /* As of July 2001, many runtimes to not align the stack properly when
644 entering main. This causes expand_main_function to forcably align
645 the stack, which results in aligned frames for functions called from
646 main, though it does nothing for the alignment of main itself. */
647 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
648 (ix86_preferred_stack_boundary > STACK_BOUNDARY)
650 /* Allocation boundary for the code of a function. */
651 #define FUNCTION_BOUNDARY 16
653 /* Alignment of field after `int : 0' in a structure. */
655 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
657 /* Minimum size in bits of the largest boundary to which any
658 and all fundamental data types supported by the hardware
659 might need to be aligned. No data type wants to be aligned
662 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
663 and Pentium Pro XFmode values at 128 bit boundaries. */
665 #define BIGGEST_ALIGNMENT 128
667 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
668 #define ALIGN_MODE_128(MODE) \
669 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
670 || (MODE) == V4SFmode || (MODE) == V4SImode)
672 /* The published ABIs say that doubles should be aligned on word
673 boundaries, so lower the aligment for structure fields unless
674 -malign-double is set. */
675 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
676 constant. Use the smaller value in that context. */
677 #ifndef IN_TARGET_LIBS
678 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
680 #define BIGGEST_FIELD_ALIGNMENT 32
683 /* If defined, a C expression to compute the alignment given to a
684 constant that is being placed in memory. EXP is the constant
685 and ALIGN is the alignment that the object would ordinarily have.
686 The value of this macro is used instead of that alignment to align
689 If this macro is not defined, then ALIGN is used.
691 The typical use of this macro is to increase alignment for string
692 constants to be word aligned so that `strcpy' calls that copy
693 constants can be done inline. */
695 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment (EXP, ALIGN)
697 /* If defined, a C expression to compute the alignment for a static
698 variable. TYPE is the data type, and ALIGN is the alignment that
699 the object would ordinarily have. The value of this macro is used
700 instead of that alignment to align the object.
702 If this macro is not defined, then ALIGN is used.
704 One use of this macro is to increase alignment of medium-size
705 data to make it all fit in fewer cache lines. Another is to
706 cause character arrays to be word-aligned so that `strcpy' calls
707 that copy constants to character arrays can be done inline. */
709 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment (TYPE, ALIGN)
711 /* If defined, a C expression to compute the alignment for a local
712 variable. TYPE is the data type, and ALIGN is the alignment that
713 the object would ordinarily have. The value of this macro is used
714 instead of that alignment to align the object.
716 If this macro is not defined, then ALIGN is used.
718 One use of this macro is to increase alignment of medium-size
719 data to make it all fit in fewer cache lines. */
721 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment (TYPE, ALIGN)
723 /* Set this non-zero if move instructions will actually fail to work
724 when given unaligned data. */
725 #define STRICT_ALIGNMENT 0
727 /* If bit field type is int, don't let it cross an int,
728 and give entire struct the alignment of an int. */
729 /* Required on the 386 since it doesn't have bitfield insns. */
730 #define PCC_BITFIELD_TYPE_MATTERS 1
732 /* Standard register usage. */
734 /* This processor has special stack-like registers. See reg-stack.c
738 #define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode \
739 || mode==XFmode || mode==TFmode)
741 /* Number of actual hardware registers.
742 The hardware registers are assigned numbers for the compiler
743 from 0 to just below FIRST_PSEUDO_REGISTER.
744 All registers that the compiler knows about must be given numbers,
745 even those that are not normally considered general registers.
747 In the 80386 we give the 8 general purpose registers the numbers 0-7.
748 We number the floating point registers 8-15.
749 Note that registers 0-7 can be accessed as a short or int,
750 while only 0-3 may be used with byte `mov' instructions.
752 Reg 16 does not correspond to any hardware register, but instead
753 appears in the RTL as an argument pointer prior to reload, and is
754 eliminated during reloading in favor of either the stack or frame
757 #define FIRST_PSEUDO_REGISTER 53
759 /* Number of hardware registers that go into the DWARF-2 unwind info.
760 If not defined, equals FIRST_PSEUDO_REGISTER. */
762 #define DWARF_FRAME_REGISTERS 17
764 /* 1 for registers that have pervasive standard uses
765 and are not available for the register allocator.
766 On the 80386, the stack pointer is such, as is the arg pointer.
768 The value is an mask - bit 1 is set for fixed registers
769 for 32bit target, while 2 is set for fixed registers for 64bit.
770 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
772 #define FIXED_REGISTERS \
773 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
774 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
775 /*arg,flags,fpsr,dir,frame*/ \
777 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
778 0, 0, 0, 0, 0, 0, 0, 0, \
779 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
780 0, 0, 0, 0, 0, 0, 0, 0, \
781 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
782 1, 1, 1, 1, 1, 1, 1, 1, \
783 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
784 1, 1, 1, 1, 1, 1, 1, 1}
787 /* 1 for registers not available across function calls.
788 These must include the FIXED_REGISTERS and also any
789 registers that can be used without being saved.
790 The latter must include the registers where values are returned
791 and the register where structure-value addresses are passed.
792 Aside from that, you can include as many other registers as you like.
794 The value is an mask - bit 1 is set for call used
795 for 32bit target, while 2 is set for call used for 64bit.
796 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
798 #define CALL_USED_REGISTERS \
799 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
800 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
801 /*arg,flags,fpsr,dir,frame*/ \
803 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
804 3, 3, 3, 3, 3, 3, 3, 3, \
805 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
806 3, 3, 3, 3, 3, 3, 3, 3, \
807 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
808 3, 3, 3, 3, 1, 1, 1, 1, \
809 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
810 3, 3, 3, 3, 3, 3, 3, 3} \
812 /* Order in which to allocate registers. Each register must be
813 listed once, even those in FIXED_REGISTERS. List frame pointer
814 late and fixed registers last. Note that, in general, we prefer
815 registers listed in CALL_USED_REGISTERS, keeping the others
816 available for storage of persistent values.
818 Three different versions of REG_ALLOC_ORDER have been tried:
820 If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
821 but slower code on simple functions returning values in eax.
823 If the order is eax, ecx, edx, ... it causes reload to abort when compiling
824 perl 4.036 due to not being able to create a DImode register (to hold a 2
827 If the order is eax, edx, ecx, ... it produces better code for simple
828 functions, and a slightly slower compiler. Users complained about the code
829 generated by allocating edx first, so restore the 'natural' order of things. */
831 #define REG_ALLOC_ORDER \
834 /* bx,si,di,bp,sp,*/ \
838 /*r12,r15,r14,r13*/ \
840 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
841 21, 22, 23, 24, 25, 26, 27, 28, \
842 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
843 45, 46, 47, 48, 49, 50, 51, 52, \
844 /*st,st1,st2,st3,st4,st5,st6,st7*/ \
845 8, 9, 10, 11, 12, 13, 14, 15, \
846 /*,arg,cc,fpsr,dir,frame*/ \
848 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
849 29, 30, 31, 32, 33, 34, 35, 36 }
851 /* Macro to conditionally modify fixed_regs/call_used_regs. */
852 #define CONDITIONAL_REGISTER_USAGE \
855 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
857 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
858 call_used_regs[i] = (call_used_regs[i] \
859 & (TARGET_64BIT ? 2 : 1)) != 0; \
863 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
864 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
869 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
870 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
871 fixed_regs[i] = call_used_regs[i] = 1; \
876 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
877 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
878 fixed_regs[i] = call_used_regs[i] = 1; \
880 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
884 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
885 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
886 if (TEST_HARD_REG_BIT (x, i)) \
887 fixed_regs[i] = call_used_regs[i] = 1; \
891 /* Return number of consecutive hard regs needed starting at reg REGNO
892 to hold something of mode MODE.
893 This is ordinarily the length in words of a value of mode MODE
894 but can be less for certain modes in special long registers.
896 Actually there are no two word move instructions for consecutive
897 registers. And only registers 0-3 may have mov byte instructions
901 #define HARD_REGNO_NREGS(REGNO, MODE) \
902 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
903 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
905 ? (TARGET_64BIT ? 2 : 3) \
907 ? (TARGET_64BIT ? 4 : 6) \
908 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
910 #define VALID_SSE_REG_MODE(MODE) \
911 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
912 || (MODE) == SFmode \
913 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
915 #define VALID_MMX_REG_MODE(MODE) \
916 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
917 || (MODE) == V2SImode || (MODE) == SImode)
919 #define VECTOR_MODE_SUPPORTED_P(MODE) \
920 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
921 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 : 0)
923 #define VALID_FP_MODE_P(mode) \
924 ((mode) == SFmode || (mode) == DFmode || (mode) == TFmode \
925 || (!TARGET_64BIT && (mode) == XFmode) \
926 || (mode) == SCmode || (mode) == DCmode || (mode) == TCmode\
927 || (!TARGET_64BIT && (mode) == XCmode))
929 #define VALID_INT_MODE_P(mode) \
930 ((mode) == QImode || (mode) == HImode || (mode) == SImode \
931 || (mode) == DImode \
932 || (mode) == CQImode || (mode) == CHImode || (mode) == CSImode \
933 || (mode) == CDImode)
935 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
937 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
938 ix86_hard_regno_mode_ok (REGNO, MODE)
940 /* Value is 1 if it is a good idea to tie two pseudo registers
941 when one has mode MODE1 and one has mode MODE2.
942 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
943 for any hard reg, then this must be 0 for correct output. */
945 #define MODES_TIEABLE_P(MODE1, MODE2) \
946 ((MODE1) == (MODE2) \
947 || (((MODE1) == HImode || (MODE1) == SImode \
948 || ((MODE1) == QImode \
949 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
950 || ((MODE1) == DImode && TARGET_64BIT)) \
951 && ((MODE2) == HImode || (MODE2) == SImode \
952 || ((MODE1) == QImode \
953 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
954 || ((MODE2) == DImode && TARGET_64BIT))))
957 /* Specify the modes required to caller save a given hard regno.
958 We do this on i386 to prevent flags from being saved at all.
960 Kill any attempts to combine saving of modes. */
962 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
963 (CC_REGNO_P (REGNO) ? VOIDmode \
964 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
965 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
966 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
967 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
969 /* Specify the registers used for certain standard purposes.
970 The values of these macros are register numbers. */
972 /* on the 386 the pc register is %eip, and is not usable as a general
973 register. The ordinary mov instructions won't work */
974 /* #define PC_REGNUM */
976 /* Register to use for pushing function arguments. */
977 #define STACK_POINTER_REGNUM 7
979 /* Base register for access to local variables of the function. */
980 #define HARD_FRAME_POINTER_REGNUM 6
982 /* Base register for access to local variables of the function. */
983 #define FRAME_POINTER_REGNUM 20
985 /* First floating point reg */
986 #define FIRST_FLOAT_REG 8
988 /* First & last stack-like regs */
989 #define FIRST_STACK_REG FIRST_FLOAT_REG
990 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
994 #define DIRFLAG_REG 19
996 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
997 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
999 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1000 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1002 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1003 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1005 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1006 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1008 /* Value should be nonzero if functions must have frame pointers.
1009 Zero means the frame pointer need not be set up (and parms
1010 may be accessed via the stack pointer) in functions that seem suitable.
1011 This is computed in `reload', in reload1.c. */
1012 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1014 /* Override this in other tm.h files to cope with various OS losage
1015 requiring a frame pointer. */
1016 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1017 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1020 /* Make sure we can access arbitrary call frames. */
1021 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1023 /* Base register for access to arguments of the function. */
1024 #define ARG_POINTER_REGNUM 16
1026 /* Register in which static-chain is passed to a function.
1027 We do use ECX as static chain register for 32 bit ABI. On the
1028 64bit ABI, ECX is an argument register, so we use R10 instead. */
1029 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1031 /* Register to hold the addressing base for position independent
1032 code access to data items.
1033 We don't use PIC pointer for 64bit mode. Define the regnum to
1034 dummy value to prevent gcc from pesimizing code dealing with EBX.
1036 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
1038 /* Register in which address to store a structure value
1039 arrives in the function. On the 386, the prologue
1040 copies this from the stack to register %eax. */
1041 #define STRUCT_VALUE_INCOMING 0
1043 /* Place in which caller passes the structure value address.
1044 0 means push the value on the stack like an argument. */
1045 #define STRUCT_VALUE 0
1047 /* A C expression which can inhibit the returning of certain function
1048 values in registers, based on the type of value. A nonzero value
1049 says to return the function value in memory, just as large
1050 structures are always returned. Here TYPE will be a C expression
1051 of type `tree', representing the data type of the value.
1053 Note that values of mode `BLKmode' must be explicitly handled by
1054 this macro. Also, the option `-fpcc-struct-return' takes effect
1055 regardless of this macro. On most systems, it is possible to
1056 leave the macro undefined; this causes a default definition to be
1057 used, whose value is the constant 1 for `BLKmode' values, and 0
1060 Do not use this macro to indicate that structures and unions
1061 should always be returned in memory. You should instead use
1062 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1064 #define RETURN_IN_MEMORY(TYPE) \
1065 ((TYPE_MODE (TYPE) == BLKmode) \
1066 || (VECTOR_MODE_P (TYPE_MODE (TYPE)) && int_size_in_bytes (TYPE) == 8)\
1067 || (int_size_in_bytes (TYPE) > 12 && TYPE_MODE (TYPE) != TImode \
1068 && TYPE_MODE (TYPE) != TFmode && ! VECTOR_MODE_P (TYPE_MODE (TYPE))))
1071 /* Define the classes of registers for register constraints in the
1072 machine description. Also define ranges of constants.
1074 One of the classes must always be named ALL_REGS and include all hard regs.
1075 If there is more than one class, another class must be named NO_REGS
1076 and contain no registers.
1078 The name GENERAL_REGS must be the name of a class (or an alias for
1079 another name such as ALL_REGS). This is the class of registers
1080 that is allowed by "g" or "r" in a register constraint.
1081 Also, registers outside this class are allocated only when
1082 instructions express preferences for them.
1084 The classes must be numbered in nondecreasing order; that is,
1085 a larger-numbered class must never be contained completely
1086 in a smaller-numbered class.
1088 For any two classes, it is very desirable that there be another
1089 class that represents their union.
1091 It might seem that class BREG is unnecessary, since no useful 386
1092 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1093 and the "b" register constraint is useful in asms for syscalls.
1095 The flags and fpsr registers are in no class. */
1100 AREG, DREG, CREG, BREG, SIREG, DIREG,
1101 AD_REGS, /* %eax/%edx for DImode */
1102 Q_REGS, /* %eax %ebx %ecx %edx */
1103 NON_Q_REGS, /* %esi %edi %ebp %esp */
1104 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1105 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1106 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1107 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1117 ALL_REGS, LIM_REG_CLASSES
1120 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1122 #define INTEGER_CLASS_P(CLASS) (reg_class_subset_p (CLASS, GENERAL_REGS))
1123 #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
1124 #define SSE_CLASS_P(CLASS) (reg_class_subset_p (CLASS, SSE_REGS))
1125 #define MMX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, MMX_REGS))
1126 #define MAYBE_INTEGER_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, GENERAL_REGS))
1127 #define MAYBE_FLOAT_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, FLOAT_REGS))
1128 #define MAYBE_SSE_CLASS_P(CLASS) (reg_classes_intersect_p (SSE_REGS, CLASS))
1129 #define MAYBE_MMX_CLASS_P(CLASS) (reg_classes_intersect_p (MMX_REGS, CLASS))
1131 #define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS))
1133 /* Give names of register classes as strings for dump file. */
1135 #define REG_CLASS_NAMES \
1137 "AREG", "DREG", "CREG", "BREG", \
1140 "Q_REGS", "NON_Q_REGS", \
1144 "FP_TOP_REG", "FP_SECOND_REG", \
1148 "FP_TOP_SSE_REGS", \
1149 "FP_SECOND_SSE_REGS", \
1153 "FLOAT_INT_SSE_REGS", \
1156 /* Define which registers fit in which classes.
1157 This is an initializer for a vector of HARD_REG_SET
1158 of length N_REG_CLASSES. */
1160 #define REG_CLASS_CONTENTS \
1162 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1163 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1164 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1165 { 0x03, 0x0 }, /* AD_REGS */ \
1166 { 0x0f, 0x0 }, /* Q_REGS */ \
1167 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1168 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1169 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1170 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1171 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1172 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1173 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1174 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1175 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1176 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1177 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1178 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1179 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1180 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1181 { 0xffffffff,0x1fffff } \
1184 /* The same information, inverted:
1185 Return the class number of the smallest class containing
1186 reg number REGNO. This could be a conditional expression
1187 or could index an array. */
1189 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1191 /* When defined, the compiler allows registers explicitly used in the
1192 rtl to be used as spill registers but prevents the compiler from
1193 extending the lifetime of these registers. */
1195 #define SMALL_REGISTER_CLASSES 1
1197 #define QI_REG_P(X) \
1198 (REG_P (X) && REGNO (X) < 4)
1200 #define GENERAL_REGNO_P(n) \
1201 ((n) < 8 || REX_INT_REGNO_P (n))
1203 #define GENERAL_REG_P(X) \
1204 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1206 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1208 #define NON_QI_REG_P(X) \
1209 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1211 #define REX_INT_REGNO_P(n) ((n) >= FIRST_REX_INT_REG && (n) <= LAST_REX_INT_REG)
1212 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1214 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1215 #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
1216 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1217 #define ANY_FP_REGNO_P(n) (FP_REGNO_P (n) || SSE_REGNO_P (n))
1219 #define SSE_REGNO_P(n) \
1220 (((n) >= FIRST_SSE_REG && (n) <= LAST_SSE_REG) \
1221 || ((n) >= FIRST_REX_SSE_REG && (n) <= LAST_REX_SSE_REG))
1223 #define SSE_REGNO(n) \
1224 ((n) < 8 ? FIRST_SSE_REG + (n) : FIRST_REX_SSE_REG + (n) - 8)
1225 #define SSE_REG_P(n) (REG_P (n) && SSE_REGNO_P (REGNO (n)))
1227 #define SSE_FLOAT_MODE_P(m) \
1228 ((TARGET_SSE && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
1230 #define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
1231 #define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
1233 #define STACK_REG_P(xop) (REG_P (xop) && \
1234 REGNO (xop) >= FIRST_STACK_REG && \
1235 REGNO (xop) <= LAST_STACK_REG)
1237 #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
1239 #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
1241 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1242 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1244 /* Indicate whether hard register numbered REG_NO should be converted
1246 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1247 (REG_NO == FLAGS_REG || REG_NO == ARG_POINTER_REGNUM)
1249 /* The class value for index registers, and the one for base regs. */
1251 #define INDEX_REG_CLASS INDEX_REGS
1252 #define BASE_REG_CLASS GENERAL_REGS
1254 /* Get reg_class from a letter such as appears in the machine description. */
1256 #define REG_CLASS_FROM_LETTER(C) \
1257 ((C) == 'r' ? GENERAL_REGS : \
1258 (C) == 'R' ? LEGACY_REGS : \
1259 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1260 (C) == 'Q' ? Q_REGS : \
1261 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1264 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1267 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1270 (C) == 'a' ? AREG : \
1271 (C) == 'b' ? BREG : \
1272 (C) == 'c' ? CREG : \
1273 (C) == 'd' ? DREG : \
1274 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1275 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1276 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1277 (C) == 'A' ? AD_REGS : \
1278 (C) == 'D' ? DIREG : \
1279 (C) == 'S' ? SIREG : NO_REGS)
1281 /* The letters I, J, K, L and M in a register constraint string
1282 can be used to stand for particular ranges of immediate operands.
1283 This macro defines what the ranges are.
1284 C is the letter, and VALUE is a constant value.
1285 Return 1 if VALUE is in the range specified by C.
1287 I is for non-DImode shifts.
1288 J is for DImode shifts.
1289 K is for signed imm8 operands.
1290 L is for andsi as zero-extending move.
1291 M is for shifts that can be executed by the "lea" opcode.
1292 N is for immedaite operands for out/in instructions (0-255)
1295 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1296 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1297 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1298 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1299 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1300 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1301 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1304 /* Similar, but for floating constants, and defining letters G and H.
1305 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1306 TARGET_387 isn't set, because the stack register converter may need to
1307 load 0.0 into the function value register. */
1309 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1310 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1311 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1313 /* A C expression that defines the optional machine-dependent
1314 constraint letters that can be used to segregate specific types of
1315 operands, usually memory references, for the target machine. Any
1316 letter that is not elsewhere defined and not matched by
1317 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1320 If it is required for a particular target machine, it should
1321 return 1 if VALUE corresponds to the operand type represented by
1322 the constraint letter C. If C is not defined as an extra
1323 constraint, the value returned should be 0 regardless of VALUE. */
1325 #define EXTRA_CONSTRAINT(VALUE, C) \
1326 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1327 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1330 /* Place additional restrictions on the register class to use when it
1331 is necessary to be able to hold a value of mode MODE in a reload
1332 register for which class CLASS would ordinarily be used. */
1334 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1335 ((MODE) == QImode && !TARGET_64BIT \
1336 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
1339 /* Given an rtx X being reloaded into a reg required to be
1340 in class CLASS, return the class of reg to actually use.
1341 In general this is just CLASS; but on some machines
1342 in some cases it is preferable to use a more restrictive class.
1343 On the 80386 series, we prevent floating constants from being
1344 reloaded into floating registers (since no move-insn can do that)
1345 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1347 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1348 QImode must go into class Q_REGS.
1349 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1350 movdf to do mem-to-mem moves through integer regs. */
1352 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1353 ix86_preferred_reload_class (X, CLASS)
1355 /* If we are copying between general and FP registers, we need a memory
1356 location. The same is true for SSE and MMX registers. */
1357 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1358 ix86_secondary_memory_needed (CLASS1, CLASS2, MODE, 1)
1360 /* QImode spills from non-QI registers need a scratch. This does not
1361 happen often -- the only example so far requires an uninitialized
1364 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
1365 ((CLASS) == GENERAL_REGS && !TARGET_64BIT && (MODE) == QImode \
1368 /* Return the maximum number of consecutive registers
1369 needed to represent mode MODE in a register of class CLASS. */
1370 /* On the 80386, this is the size of MODE in words,
1371 except in the FP regs, where a single reg is always enough.
1372 The TFmodes are really just 80bit values, so we use only 3 registers
1373 to hold them, instead of 4, as the size would suggest.
1375 #define CLASS_MAX_NREGS(CLASS, MODE) \
1376 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1377 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1378 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1379 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1381 /* A C expression whose value is nonzero if pseudos that have been
1382 assigned to registers of class CLASS would likely be spilled
1383 because registers of CLASS are needed for spill registers.
1385 The default value of this macro returns 1 if CLASS has exactly one
1386 register and zero otherwise. On most machines, this default
1387 should be used. Only define this macro to some other expression
1388 if pseudo allocated by `local-alloc.c' end up in memory because
1389 their hard registers were needed for spill registers. If this
1390 macro returns nonzero for those classes, those pseudos will only
1391 be allocated by `global.c', which knows how to reallocate the
1392 pseudo to another register. If there would not be another
1393 register available for reallocation, you should not change the
1394 definition of this macro since the only effect of such a
1395 definition would be to slow down register allocation. */
1397 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1398 (((CLASS) == AREG) \
1399 || ((CLASS) == DREG) \
1400 || ((CLASS) == CREG) \
1401 || ((CLASS) == BREG) \
1402 || ((CLASS) == AD_REGS) \
1403 || ((CLASS) == SIREG) \
1404 || ((CLASS) == DIREG))
1406 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1407 to automatically clobber for all asms.
1409 We do this in the new i386 backend to maintain source compatibility
1410 with the old cc0-based compiler. */
1412 #define MD_ASM_CLOBBERS(CLOBBERS) \
1414 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), (CLOBBERS));\
1415 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), (CLOBBERS)); \
1416 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), (CLOBBERS)); \
1419 /* Stack layout; function entry, exit and calling. */
1421 /* Define this if pushing a word on the stack
1422 makes the stack pointer a smaller address. */
1423 #define STACK_GROWS_DOWNWARD
1425 /* Define this if the nominal address of the stack frame
1426 is at the high-address end of the local variables;
1427 that is, each additional local variable allocated
1428 goes at a more negative offset in the frame. */
1429 #define FRAME_GROWS_DOWNWARD
1431 /* Offset within stack frame to start allocating local variables at.
1432 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1433 first local allocated. Otherwise, it is the offset to the BEGINNING
1434 of the first local allocated. */
1435 #define STARTING_FRAME_OFFSET 0
1437 /* If we generate an insn to push BYTES bytes,
1438 this says how many the stack pointer really advances by.
1439 On 386 pushw decrements by exactly 2 no matter what the position was.
1440 On the 386 there is no pushb; we use pushw instead, and this
1441 has the effect of rounding up to 2.
1443 For 64bit ABI we round up to 8 bytes.
1446 #define PUSH_ROUNDING(BYTES) \
1448 ? (((BYTES) + 7) & (-8)) \
1449 : (((BYTES) + 1) & (-2)))
1451 /* If defined, the maximum amount of space required for outgoing arguments will
1452 be computed and placed into the variable
1453 `current_function_outgoing_args_size'. No space will be pushed onto the
1454 stack for each call; instead, the function prologue should increase the stack
1455 frame size by this amount. */
1457 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1459 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1460 instructions to pass outgoing arguments. */
1462 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1464 /* Offset of first parameter from the argument pointer register value. */
1465 #define FIRST_PARM_OFFSET(FNDECL) 0
1467 /* Define this macro if functions should assume that stack space has been
1468 allocated for arguments even when their values are passed in registers.
1470 The value of this macro is the size, in bytes, of the area reserved for
1471 arguments passed in registers for the function represented by FNDECL.
1473 This space can be allocated by the caller, or be a part of the
1474 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1476 #define REG_PARM_STACK_SPACE(FNDECL) 0
1478 /* Define as a C expression that evaluates to nonzero if we do not know how
1479 to pass TYPE solely in registers. The file expr.h defines a
1480 definition that is usually appropriate, refer to expr.h for additional
1481 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1482 computed in the stack and then loaded into a register. */
1483 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1485 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1486 || TREE_ADDRESSABLE (TYPE) \
1487 || ((MODE) == TImode) \
1488 || ((MODE) == BLKmode \
1489 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1490 && 0 == (int_size_in_bytes (TYPE) \
1491 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1492 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1493 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1495 /* Value is the number of bytes of arguments automatically
1496 popped when returning from a subroutine call.
1497 FUNDECL is the declaration node of the function (as a tree),
1498 FUNTYPE is the data type of the function (as a tree),
1499 or for a library call it is an identifier node for the subroutine name.
1500 SIZE is the number of bytes of arguments passed on the stack.
1502 On the 80386, the RTD insn may be used to pop them if the number
1503 of args is fixed, but if the number is variable then the caller
1504 must pop them all. RTD can't be used for library calls now
1505 because the library is compiled with the Unix compiler.
1506 Use of RTD is a selectable option, since it is incompatible with
1507 standard Unix calling sequences. If the option is not selected,
1508 the caller must always pop the args.
1510 The attribute stdcall is equivalent to RTD on a per module basis. */
1512 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
1513 (ix86_return_pops_args (FUNDECL, FUNTYPE, SIZE))
1515 /* Define how to find the value returned by a function.
1516 VALTYPE is the data type of the value (as a tree).
1517 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1518 otherwise, FUNC is 0. */
1519 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1520 gen_rtx_REG (TYPE_MODE (VALTYPE), \
1521 VALUE_REGNO (TYPE_MODE (VALTYPE)))
1523 /* Define how to find the value returned by a library function
1524 assuming the value has mode MODE. */
1526 #define LIBCALL_VALUE(MODE) \
1527 gen_rtx_REG (MODE, VALUE_REGNO (MODE))
1529 /* Define the size of the result block used for communication between
1530 untyped_call and untyped_return. The block contains a DImode value
1531 followed by the block used by fnsave and frstor. */
1533 #define APPLY_RESULT_SIZE (8+108)
1535 /* 1 if N is a possible register number for function argument passing. */
1536 #define FUNCTION_ARG_REGNO_P(N) ((N) < REGPARM_MAX)
1538 /* Define a data type for recording info about an argument list
1539 during the scan of that argument list. This data type should
1540 hold all necessary information about the function itself
1541 and about the args processed so far, enough to enable macros
1542 such as FUNCTION_ARG to determine where the next arg should go. */
1544 typedef struct ix86_args {
1545 int words; /* # words passed so far */
1546 int nregs; /* # registers available for passing */
1547 int regno; /* next available register number */
1548 int sse_words; /* # sse words passed so far */
1549 int sse_nregs; /* # sse registers available for passing */
1550 int sse_regno; /* next available sse register number */
1553 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1554 for a call to a function whose data type is FNTYPE.
1555 For a library call, FNTYPE is 0. */
1557 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1558 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1560 /* Update the data in CUM to advance over an argument
1561 of mode MODE and data type TYPE.
1562 (TYPE is null for libcalls where that information may not be available.) */
1564 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1565 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
1567 /* Define where to put the arguments to a function.
1568 Value is zero to push the argument on the stack,
1569 or a hard register in which to store the argument.
1571 MODE is the argument's machine mode.
1572 TYPE is the data type of the argument (as a tree).
1573 This is null for libcalls where that information may
1575 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1576 the preceding args and about the function being called.
1577 NAMED is nonzero if this argument is a named parameter
1578 (otherwise it is an extra parameter matching an ellipsis). */
1580 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1581 (function_arg (&CUM, MODE, TYPE, NAMED))
1583 /* For an arg passed partly in registers and partly in memory,
1584 this is the number of registers used.
1585 For args passed entirely in registers or entirely in memory, zero. */
1587 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1589 /* If PIC, we cannot make sibling calls to global functions
1590 because the PLT requires %ebx live.
1591 If we are returning floats on the register stack, we cannot make
1592 sibling calls to functions that return floats. (The stack adjust
1593 instruction will wind up after the sibcall jump, and not be executed.) */
1594 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1596 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1597 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1598 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1599 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1601 /* This macro is invoked at the end of compilation. It is used here to
1602 output code for -fpic that will load the return address into %ebx. */
1605 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1607 /* Output assembler code to FILE to increment profiler label # LABELNO
1608 for profiling a function entry. */
1610 #define FUNCTION_PROFILER(FILE, LABELNO) \
1614 fprintf (FILE, "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1615 LPREFIX, (LABELNO)); \
1616 fprintf (FILE, "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1620 fprintf (FILE, "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1621 fprintf (FILE, "\tcall\t_mcount\n"); \
1626 /* There are three profiling modes for basic blocks available.
1627 The modes are selected at compile time by using the options
1628 -a or -ax of the gnu compiler.
1629 The variable `profile_block_flag' will be set according to the
1632 profile_block_flag == 0, no option used:
1636 profile_block_flag == 1, -a option used.
1638 Count frequency of execution of every basic block.
1640 profile_block_flag == 2, -ax option used.
1642 Generate code to allow several different profiling modes at run time.
1643 Available modes are:
1644 Produce a trace of all basic blocks.
1645 Count frequency of jump instructions executed.
1646 In every mode it is possible to start profiling upon entering
1647 certain functions and to disable profiling of some other functions.
1649 The result of basic-block profiling will be written to a file `bb.out'.
1650 If the -ax option is used parameters for the profiling will be read
1655 /* The following macro shall output assembler code to FILE
1656 to initialize basic-block profiling. */
1658 #undef FUNCTION_BLOCK_PROFILER
1659 #define FUNCTION_BLOCK_PROFILER(FILE, BLOCK_OR_LABEL) \
1660 ix86_output_function_block_profiler (FILE, BLOCK_OR_LABEL)
1662 /* The following macro shall output assembler code to FILE
1663 to increment a counter associated with basic block number BLOCKNO. */
1665 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1666 ix86_output_block_profiler (FILE, BLOCKNO)
1668 /* The following macro shall output rtl for the epilogue
1669 to indicate a return from function during basic-block profiling.
1671 If profiling_block_flag == 2:
1673 Output assembler code to call function `__bb_trace_ret'.
1675 Note that function `__bb_trace_ret' must not change the
1676 machine state, especially the flag register. To grant
1677 this, you must output code to save and restore registers
1678 either in this macro or in the macros MACHINE_STATE_SAVE
1679 and MACHINE_STATE_RESTORE. The last two macros will be
1680 used in the function `__bb_trace_ret', so you must make
1681 sure that the function prologue does not change any
1682 register prior to saving it with MACHINE_STATE_SAVE.
1684 else if profiling_block_flag != 0:
1686 The macro will not be used, so it need not distinguish
1690 #define FUNCTION_BLOCK_PROFILER_EXIT \
1691 emit_call_insn (gen_call (gen_rtx_MEM (QImode, \
1692 gen_rtx_SYMBOL_REF (VOIDmode, "__bb_trace_ret")), \
1693 const0_rtx, constm1_rtx))
1695 /* The function `__bb_trace_func' is called in every basic block
1696 and is not allowed to change the machine state. Saving (restoring)
1697 the state can either be done in the BLOCK_PROFILER macro,
1698 before calling function (rsp. after returning from function)
1699 `__bb_trace_func', or it can be done inside the function by
1700 defining the macros:
1702 MACHINE_STATE_SAVE(ID)
1703 MACHINE_STATE_RESTORE(ID)
1705 In the latter case care must be taken, that the prologue code
1706 of function `__bb_trace_func' does not already change the
1707 state prior to saving it with MACHINE_STATE_SAVE.
1709 The parameter `ID' is a string identifying a unique macro use.
1711 On the i386 the initialization code at the begin of
1712 function `__bb_trace_func' contains a `sub' instruction
1713 therefore we handle save and restore of the flag register
1714 in the BLOCK_PROFILER macro.
1716 Note that ebx, esi, and edi are callee-save, so we don't have to
1717 preserve them explicitly. */
1719 #define MACHINE_STATE_SAVE(ID) \
1721 register int eax_ __asm__("eax"); \
1722 register int ecx_ __asm__("ecx"); \
1723 register int edx_ __asm__("edx"); \
1724 __asm__ __volatile__ ("\
1728 : : "r"(eax_), "r"(ecx_), "r"(edx_)); \
1731 #define MACHINE_STATE_RESTORE(ID) \
1733 register int eax_ __asm__("eax"); \
1734 register int ecx_ __asm__("ecx"); \
1735 register int edx_ __asm__("edx"); \
1736 __asm__ __volatile__ ("\
1740 : "=r"(eax_), "=r"(ecx_), "=r"(edx_)); \
1743 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1744 the stack pointer does not matter. The value is tested only in
1745 functions that have frame pointers.
1746 No definition is equivalent to always zero. */
1747 /* Note on the 386 it might be more efficient not to define this since
1748 we have to restore it ourselves from the frame pointer, in order to
1751 #define EXIT_IGNORE_STACK 1
1753 /* Output assembler code for a block containing the constant parts
1754 of a trampoline, leaving space for the variable parts. */
1756 /* On the 386, the trampoline contains two instructions:
1759 The trampoline is generated entirely at runtime. The operand of JMP
1760 is the address of FUNCTION relative to the instruction following the
1761 JMP (which is 5 bytes long). */
1763 /* Length in units of the trampoline for entering a nested function. */
1765 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1767 /* Emit RTL insns to initialize the variable parts of a trampoline.
1768 FNADDR is an RTX for the address of the function's pure code.
1769 CXT is an RTX for the static chain value for the function. */
1771 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1772 x86_initialize_trampoline (TRAMP, FNADDR, CXT)
1774 /* Definitions for register eliminations.
1776 This is an array of structures. Each structure initializes one pair
1777 of eliminable registers. The "from" register number is given first,
1778 followed by "to". Eliminations of the same "from" register are listed
1779 in order of preference.
1781 There are two registers that can always be eliminated on the i386.
1782 The frame pointer and the arg pointer can be replaced by either the
1783 hard frame pointer or to the stack pointer, depending upon the
1784 circumstances. The hard frame pointer is not used before reload and
1785 so it is not eligible for elimination. */
1787 #define ELIMINABLE_REGS \
1788 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1789 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1790 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1791 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1793 /* Given FROM and TO register numbers, say whether this elimination is
1794 allowed. Frame pointer elimination is automatically handled.
1796 All other eliminations are valid. */
1798 #define CAN_ELIMINATE(FROM, TO) \
1799 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1801 /* Define the offset between two registers, one to be eliminated, and the other
1802 its replacement, at the start of a routine. */
1804 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1805 (OFFSET) = ix86_initial_elimination_offset (FROM, TO)
1807 /* Addressing modes, and classification of registers for them. */
1809 /* #define HAVE_POST_INCREMENT 0 */
1810 /* #define HAVE_POST_DECREMENT 0 */
1812 /* #define HAVE_PRE_DECREMENT 0 */
1813 /* #define HAVE_PRE_INCREMENT 0 */
1815 /* Macros to check register numbers against specific register classes. */
1817 /* These assume that REGNO is a hard or pseudo reg number.
1818 They give nonzero only if REGNO is a hard reg of the suitable class
1819 or a pseudo reg currently allocated to a suitable hard reg.
1820 Since they use reg_renumber, they are safe only once reg_renumber
1821 has been allocated, which happens in local-alloc.c. */
1823 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1824 ((REGNO) < STACK_POINTER_REGNUM \
1825 || (REGNO >= FIRST_REX_INT_REG \
1826 && (REGNO) <= LAST_REX_INT_REG) \
1827 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1828 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1829 || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
1831 #define REGNO_OK_FOR_BASE_P(REGNO) \
1832 ((REGNO) <= STACK_POINTER_REGNUM \
1833 || (REGNO) == ARG_POINTER_REGNUM \
1834 || (REGNO) == FRAME_POINTER_REGNUM \
1835 || (REGNO >= FIRST_REX_INT_REG \
1836 && (REGNO) <= LAST_REX_INT_REG) \
1837 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1838 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1839 || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
1841 #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
1842 #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
1844 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1845 and check its validity for a certain class.
1846 We have two alternate definitions for each of them.
1847 The usual definition accepts all pseudo regs; the other rejects
1848 them unless they have been allocated suitable hard regs.
1849 The symbol REG_OK_STRICT causes the latter definition to be used.
1851 Most source files want to accept pseudo regs in the hope that
1852 they will get allocated to the class that the insn wants them to be in.
1853 Source files for reload pass need to be strict.
1854 After reload, it makes no difference, since pseudo regs have
1855 been eliminated by then. */
1858 /* Non strict versions, pseudos are ok */
1859 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1860 (REGNO (X) < STACK_POINTER_REGNUM \
1861 || (REGNO (X) >= FIRST_REX_INT_REG \
1862 && REGNO (X) <= LAST_REX_INT_REG) \
1863 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1865 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1866 (REGNO (X) <= STACK_POINTER_REGNUM \
1867 || REGNO (X) == ARG_POINTER_REGNUM \
1868 || REGNO (X) == FRAME_POINTER_REGNUM \
1869 || (REGNO (X) >= FIRST_REX_INT_REG \
1870 && REGNO (X) <= LAST_REX_INT_REG) \
1871 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1873 /* Strict versions, hard registers only */
1874 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1875 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1877 #ifndef REG_OK_STRICT
1878 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1879 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1882 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1883 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1886 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1887 that is a valid memory address for an instruction.
1888 The MODE argument is the machine mode for the MEM expression
1889 that wants to use this address.
1891 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1892 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1894 See legitimize_pic_address in i386.c for details as to what
1895 constitutes a legitimate address when -fpic is used. */
1897 #define MAX_REGS_PER_ADDRESS 2
1899 #define CONSTANT_ADDRESS_P(X) \
1900 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1901 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1902 || GET_CODE (X) == CONST_DOUBLE)
1904 /* Nonzero if the constant value X is a legitimate general operand.
1905 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1907 #define LEGITIMATE_CONSTANT_P(X) 1
1909 #ifdef REG_OK_STRICT
1910 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1912 if (legitimate_address_p (MODE, X, 1)) \
1917 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1919 if (legitimate_address_p (MODE, X, 0)) \
1925 /* If defined, a C expression to determine the base term of address X.
1926 This macro is used in only one place: `find_base_term' in alias.c.
1928 It is always safe for this macro to not be defined. It exists so
1929 that alias analysis can understand machine-dependent addresses.
1931 The typical use of this macro is to handle addresses containing
1932 a label_ref or symbol_ref within an UNSPEC. */
1934 #define FIND_BASE_TERM(X) ix86_find_base_term (x)
1936 /* Try machine-dependent ways of modifying an illegitimate address
1937 to be legitimate. If we find one, return the new, valid address.
1938 This macro is used in only one place: `memory_address' in explow.c.
1940 OLDX is the address as it was before break_out_memory_refs was called.
1941 In some cases it is useful to look at this to decide what needs to be done.
1943 MODE and WIN are passed so that this macro can use
1944 GO_IF_LEGITIMATE_ADDRESS.
1946 It is always safe for this macro to do nothing. It exists to recognize
1947 opportunities to optimize the output.
1949 For the 80386, we handle X+REG by loading X into a register R and
1950 using R+REG. R will go in a general reg and indexing will be used.
1951 However, if REG is a broken-out memory address or multiplication,
1952 nothing needs to be done because REG can certainly go in a general reg.
1954 When -fpic is used, special handling is needed for symbolic references.
1955 See comments by legitimize_pic_address in i386.c for details. */
1957 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1959 (X) = legitimize_address (X, OLDX, MODE); \
1960 if (memory_address_p (MODE, X)) \
1964 #define REWRITE_ADDRESS(x) rewrite_address(x)
1966 /* Nonzero if the constant value X is a legitimate general operand
1967 when generating PIC code. It is given that flag_pic is on and
1968 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1970 #define LEGITIMATE_PIC_OPERAND_P(X) \
1971 (! SYMBOLIC_CONST (X) \
1972 || legitimate_pic_address_disp_p (X))
1974 #define SYMBOLIC_CONST(X) \
1975 (GET_CODE (X) == SYMBOL_REF \
1976 || GET_CODE (X) == LABEL_REF \
1977 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1979 /* Go to LABEL if ADDR (a legitimate address expression)
1980 has an effect that depends on the machine mode it is used for.
1981 On the 80386, only postdecrement and postincrement address depend thus
1982 (the amount of decrement or increment being the length of the operand). */
1983 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1984 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
1986 /* Codes for all the SSE/MMX builtins. */
1998 IX86_BUILTIN_CMPEQPS,
1999 IX86_BUILTIN_CMPLTPS,
2000 IX86_BUILTIN_CMPLEPS,
2001 IX86_BUILTIN_CMPGTPS,
2002 IX86_BUILTIN_CMPGEPS,
2003 IX86_BUILTIN_CMPNEQPS,
2004 IX86_BUILTIN_CMPNLTPS,
2005 IX86_BUILTIN_CMPNLEPS,
2006 IX86_BUILTIN_CMPNGTPS,
2007 IX86_BUILTIN_CMPNGEPS,
2008 IX86_BUILTIN_CMPORDPS,
2009 IX86_BUILTIN_CMPUNORDPS,
2010 IX86_BUILTIN_CMPNEPS,
2011 IX86_BUILTIN_CMPEQSS,
2012 IX86_BUILTIN_CMPLTSS,
2013 IX86_BUILTIN_CMPLESS,
2014 IX86_BUILTIN_CMPGTSS,
2015 IX86_BUILTIN_CMPGESS,
2016 IX86_BUILTIN_CMPNEQSS,
2017 IX86_BUILTIN_CMPNLTSS,
2018 IX86_BUILTIN_CMPNLESS,
2019 IX86_BUILTIN_CMPNGTSS,
2020 IX86_BUILTIN_CMPNGESS,
2021 IX86_BUILTIN_CMPORDSS,
2022 IX86_BUILTIN_CMPUNORDSS,
2023 IX86_BUILTIN_CMPNESS,
2025 IX86_BUILTIN_COMIEQSS,
2026 IX86_BUILTIN_COMILTSS,
2027 IX86_BUILTIN_COMILESS,
2028 IX86_BUILTIN_COMIGTSS,
2029 IX86_BUILTIN_COMIGESS,
2030 IX86_BUILTIN_COMINEQSS,
2031 IX86_BUILTIN_UCOMIEQSS,
2032 IX86_BUILTIN_UCOMILTSS,
2033 IX86_BUILTIN_UCOMILESS,
2034 IX86_BUILTIN_UCOMIGTSS,
2035 IX86_BUILTIN_UCOMIGESS,
2036 IX86_BUILTIN_UCOMINEQSS,
2038 IX86_BUILTIN_CVTPI2PS,
2039 IX86_BUILTIN_CVTPS2PI,
2040 IX86_BUILTIN_CVTSI2SS,
2041 IX86_BUILTIN_CVTSS2SI,
2042 IX86_BUILTIN_CVTTPS2PI,
2043 IX86_BUILTIN_CVTTSS2SI,
2044 IX86_BUILTIN_M_FROM_INT,
2045 IX86_BUILTIN_M_TO_INT,
2052 IX86_BUILTIN_LOADAPS,
2053 IX86_BUILTIN_LOADUPS,
2054 IX86_BUILTIN_STOREAPS,
2055 IX86_BUILTIN_STOREUPS,
2056 IX86_BUILTIN_LOADSS,
2057 IX86_BUILTIN_STORESS,
2060 IX86_BUILTIN_MOVHLPS,
2061 IX86_BUILTIN_MOVLHPS,
2062 IX86_BUILTIN_LOADHPS,
2063 IX86_BUILTIN_LOADLPS,
2064 IX86_BUILTIN_STOREHPS,
2065 IX86_BUILTIN_STORELPS,
2067 IX86_BUILTIN_MASKMOVQ,
2068 IX86_BUILTIN_MOVMSKPS,
2069 IX86_BUILTIN_PMOVMSKB,
2071 IX86_BUILTIN_MOVNTPS,
2072 IX86_BUILTIN_MOVNTQ,
2074 IX86_BUILTIN_PACKSSWB,
2075 IX86_BUILTIN_PACKSSDW,
2076 IX86_BUILTIN_PACKUSWB,
2081 IX86_BUILTIN_PADDSB,
2082 IX86_BUILTIN_PADDSW,
2083 IX86_BUILTIN_PADDUSB,
2084 IX86_BUILTIN_PADDUSW,
2088 IX86_BUILTIN_PSUBSB,
2089 IX86_BUILTIN_PSUBSW,
2090 IX86_BUILTIN_PSUBUSB,
2091 IX86_BUILTIN_PSUBUSW,
2101 IX86_BUILTIN_PCMPEQB,
2102 IX86_BUILTIN_PCMPEQW,
2103 IX86_BUILTIN_PCMPEQD,
2104 IX86_BUILTIN_PCMPGTB,
2105 IX86_BUILTIN_PCMPGTW,
2106 IX86_BUILTIN_PCMPGTD,
2108 IX86_BUILTIN_PEXTRW,
2109 IX86_BUILTIN_PINSRW,
2111 IX86_BUILTIN_PMADDWD,
2113 IX86_BUILTIN_PMAXSW,
2114 IX86_BUILTIN_PMAXUB,
2115 IX86_BUILTIN_PMINSW,
2116 IX86_BUILTIN_PMINUB,
2118 IX86_BUILTIN_PMULHUW,
2119 IX86_BUILTIN_PMULHW,
2120 IX86_BUILTIN_PMULLW,
2122 IX86_BUILTIN_PSADBW,
2123 IX86_BUILTIN_PSHUFW,
2133 IX86_BUILTIN_PSLLWI,
2134 IX86_BUILTIN_PSLLDI,
2135 IX86_BUILTIN_PSLLQI,
2136 IX86_BUILTIN_PSRAWI,
2137 IX86_BUILTIN_PSRADI,
2138 IX86_BUILTIN_PSRLWI,
2139 IX86_BUILTIN_PSRLDI,
2140 IX86_BUILTIN_PSRLQI,
2142 IX86_BUILTIN_PUNPCKHBW,
2143 IX86_BUILTIN_PUNPCKHWD,
2144 IX86_BUILTIN_PUNPCKHDQ,
2145 IX86_BUILTIN_PUNPCKLBW,
2146 IX86_BUILTIN_PUNPCKLWD,
2147 IX86_BUILTIN_PUNPCKLDQ,
2149 IX86_BUILTIN_SHUFPS,
2153 IX86_BUILTIN_RSQRTPS,
2154 IX86_BUILTIN_RSQRTSS,
2155 IX86_BUILTIN_SQRTPS,
2156 IX86_BUILTIN_SQRTSS,
2158 IX86_BUILTIN_UNPCKHPS,
2159 IX86_BUILTIN_UNPCKLPS,
2162 IX86_BUILTIN_ANDNPS,
2167 IX86_BUILTIN_LDMXCSR,
2168 IX86_BUILTIN_STMXCSR,
2169 IX86_BUILTIN_SFENCE,
2170 IX86_BUILTIN_PREFETCH,
2172 /* Composite builtins, expand to more than one insn. */
2173 IX86_BUILTIN_SETPS1,
2176 IX86_BUILTIN_SETRPS,
2177 IX86_BUILTIN_LOADPS1,
2178 IX86_BUILTIN_LOADRPS,
2179 IX86_BUILTIN_STOREPS1,
2180 IX86_BUILTIN_STORERPS,
2182 IX86_BUILTIN_MMX_ZERO,
2187 /* Define this macro if references to a symbol must be treated
2188 differently depending on something about the variable or
2189 function named by the symbol (such as what section it is in).
2191 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2192 so that we may access it directly in the GOT. */
2194 #define ENCODE_SECTION_INFO(DECL) \
2199 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2200 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2202 if (GET_CODE (rtl) == MEM) \
2204 if (TARGET_DEBUG_ADDR \
2205 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2207 fprintf (stderr, "Encode %s, public = %d\n", \
2208 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2209 TREE_PUBLIC (DECL)); \
2212 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2213 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2214 || ! TREE_PUBLIC (DECL)); \
2220 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2221 codes once the function is being compiled into assembly code, but
2222 not before. (It is not done before, because in the case of
2223 compiling an inline function, it would lead to multiple PIC
2224 prologues being included in functions which used inline functions
2225 and were compiled to assembly language.) */
2227 #define FINALIZE_PIC \
2230 current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \
2235 /* Max number of args passed in registers. If this is more than 3, we will
2236 have problems with ebx (register #4), since it is a caller save register and
2237 is also used as the pic register in ELF. So for now, don't allow more than
2238 3 registers to be passed in registers. */
2240 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2242 #define SSE_REGPARM_MAX (TARGET_64BIT ? 16 : 0)
2245 /* Specify the machine mode that this machine uses
2246 for the index in the tablejump instruction. */
2247 #define CASE_VECTOR_MODE Pmode
2249 /* Define as C expression which evaluates to nonzero if the tablejump
2250 instruction expects the table to contain offsets from the address of the
2252 Do not define this if the table should contain absolute addresses. */
2253 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2255 /* Specify the tree operation to be used to convert reals to integers.
2256 This should be changed to take advantage of fist --wfs ??
2258 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2260 /* This is the kind of divide that is easiest to do in the general case. */
2261 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2263 /* Define this as 1 if `char' should by default be signed; else as 0. */
2264 #define DEFAULT_SIGNED_CHAR 1
2266 /* Max number of bytes we can move from memory to memory
2267 in one reasonably fast instruction. */
2270 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2271 move efficiently, as opposed to MOVE_MAX which is the maximum
2272 number of bytes we can move with a single instruction. */
2273 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2275 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2276 move-instruction pairs, we will do a movstr or libcall instead.
2277 Increasing the value will always make code faster, but eventually
2278 incurs high cost in increased code size.
2280 If you don't define this, a reasonable default is used. */
2282 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2284 /* Define if shifts truncate the shift count
2285 which implies one can omit a sign-extension or zero-extension
2286 of a shift count. */
2287 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2289 /* #define SHIFT_COUNT_TRUNCATED */
2291 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2292 is done just by pretending it is already truncated. */
2293 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2295 /* We assume that the store-condition-codes instructions store 0 for false
2296 and some other value for true. This is the value stored for true. */
2298 #define STORE_FLAG_VALUE 1
2300 /* When a prototype says `char' or `short', really pass an `int'.
2301 (The 386 can't easily push less than an int.) */
2303 #define PROMOTE_PROTOTYPES 1
2305 /* A macro to update M and UNSIGNEDP when an object whose type is
2306 TYPE and which has the specified mode and signedness is to be
2307 stored in a register. This macro is only called when TYPE is a
2310 On i386 it is sometimes usefull to promote HImode and QImode
2311 quantities to SImode. The choice depends on target type. */
2313 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2314 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2315 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2318 /* Specify the machine mode that pointers have.
2319 After generation of rtl, the compiler makes no further distinction
2320 between pointers and any other objects of this machine mode. */
2321 #define Pmode (TARGET_64BIT ? DImode : SImode)
2323 /* A function address in a call instruction
2324 is a byte address (for indexing purposes)
2325 so give the MEM rtx a byte's mode. */
2326 #define FUNCTION_MODE QImode
2328 /* A part of a C `switch' statement that describes the relative costs
2329 of constant RTL expressions. It must contain `case' labels for
2330 expression codes `const_int', `const', `symbol_ref', `label_ref'
2331 and `const_double'. Each case must ultimately reach a `return'
2332 statement to return the relative cost of the use of that kind of
2333 constant value in an expression. The cost may depend on the
2334 precise value of the constant, which is available for examination
2335 in X, and the rtx code of the expression in which it is contained,
2336 found in OUTER_CODE.
2338 CODE is the expression code--redundant, since it can be obtained
2339 with `GET_CODE (X)'. */
2341 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2346 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2348 case CONST_DOUBLE: \
2351 if (GET_MODE (RTX) == VOIDmode) \
2354 code = standard_80387_constant_p (RTX); \
2355 return code == 1 ? 1 : \
2360 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2361 #define TOPLEVEL_COSTS_N_INSNS(N) \
2362 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2364 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2365 This can be used, for example, to indicate how costly a multiply
2366 instruction is. In writing this macro, you can use the construct
2367 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2368 instructions. OUTER_CODE is the code of the expression in which X
2371 This macro is optional; do not define it if the default cost
2372 assumptions are adequate for the target machine. */
2374 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2376 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2377 && GET_MODE (XEXP (X, 0)) == SImode) \
2379 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2381 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2382 if (value == 2 || value == 3) \
2383 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2385 /* fall through */ \
2391 if (GET_MODE (XEXP (X, 0)) == DImode) \
2393 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2395 if (INTVAL (XEXP (X, 1)) > 32) \
2396 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2398 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2402 if (GET_CODE (XEXP (X, 1)) == AND) \
2403 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2405 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2410 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2411 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2413 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2418 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2420 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2423 while (value != 0) \
2429 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2430 + nbits * ix86_cost->mult_bit); \
2432 else /* This is arbitrary */ \
2433 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2434 + 7 * ix86_cost->mult_bit); \
2440 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2443 if (GET_CODE (XEXP (X, 0)) == PLUS \
2444 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2445 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2446 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2448 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1)); \
2449 if (val == 2 || val == 4 || val == 8) \
2451 return (COSTS_N_INSNS (ix86_cost->lea) \
2452 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2453 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), OUTER_CODE) \
2454 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2457 else if (GET_CODE (XEXP (X, 0)) == MULT \
2458 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2460 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2461 if (val == 2 || val == 4 || val == 8) \
2463 return (COSTS_N_INSNS (ix86_cost->lea) \
2464 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2465 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2468 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2470 return (COSTS_N_INSNS (ix86_cost->lea) \
2471 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2472 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2473 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2476 /* fall through */ \
2481 if (GET_MODE (X) == DImode) \
2482 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2483 + (rtx_cost (XEXP (X, 0), OUTER_CODE) \
2484 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2485 + (rtx_cost (XEXP (X, 1), OUTER_CODE) \
2486 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2488 /* fall through */ \
2491 if (GET_MODE (X) == DImode) \
2492 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2493 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2499 /* An expression giving the cost of an addressing mode that contains
2500 ADDRESS. If not defined, the cost is computed from the ADDRESS
2501 expression and the `CONST_COSTS' values.
2503 For most CISC machines, the default cost is a good approximation
2504 of the true cost of the addressing mode. However, on RISC
2505 machines, all instructions normally have the same length and
2506 execution time. Hence all addresses will have equal costs.
2508 In cases where more than one form of an address is known, the form
2509 with the lowest cost will be used. If multiple forms have the
2510 same, lowest, cost, the one that is the most complex will be used.
2512 For example, suppose an address that is equal to the sum of a
2513 register and a constant is used twice in the same basic block.
2514 When this macro is not defined, the address will be computed in a
2515 register and memory references will be indirect through that
2516 register. On machines where the cost of the addressing mode
2517 containing the sum is no higher than that of a simple indirect
2518 reference, this will produce an additional instruction and
2519 possibly require an additional register. Proper specification of
2520 this macro eliminates this overhead for such machines.
2522 Similar use of this macro is made in strength reduction of loops.
2524 ADDRESS need not be valid as an address. In such a case, the cost
2525 is not relevant and can be any value; invalid addresses need not be
2526 assigned a different cost.
2528 On machines where an address involving more than one register is as
2529 cheap as an address computation involving only one register,
2530 defining `ADDRESS_COST' to reflect this can cause two registers to
2531 be live over a region of code where only one would have been if
2532 `ADDRESS_COST' were not defined in that manner. This effect should
2533 be considered in the definition of this macro. Equivalent costs
2534 should probably only be given to addresses with different numbers
2535 of registers on machines with lots of registers.
2537 This macro will normally either not be defined or be defined as a
2540 For i386, it is better to use a complex address than let gcc copy
2541 the address into a reg and make a new pseudo. But not if the address
2542 requires to two regs - that would mean more pseudos with longer
2545 #define ADDRESS_COST(RTX) \
2546 ix86_address_cost (RTX)
2548 /* A C expression for the cost of moving data from a register in class FROM to
2549 one in class TO. The classes are expressed using the enumeration values
2550 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2551 interpreted relative to that.
2553 It is not required that the cost always equal 2 when FROM is the same as TO;
2554 on some machines it is expensive to move between registers if they are not
2555 general registers. */
2557 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2558 ix86_register_move_cost (MODE, CLASS1, CLASS2)
2560 /* A C expression for the cost of moving data of mode M between a
2561 register and memory. A value of 2 is the default; this cost is
2562 relative to those in `REGISTER_MOVE_COST'.
2564 If moving between registers and memory is more expensive than
2565 between two registers, you should define this macro to express the
2568 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
2569 ix86_memory_move_cost (MODE, CLASS, IN)
2571 /* A C expression for the cost of a branch instruction. A value of 1
2572 is the default; other values are interpreted relative to that. */
2574 #define BRANCH_COST ix86_branch_cost
2576 /* Define this macro as a C expression which is nonzero if accessing
2577 less than a word of memory (i.e. a `char' or a `short') is no
2578 faster than accessing a word of memory, i.e., if such access
2579 require more than one instruction or if there is no difference in
2580 cost between byte and (aligned) word loads.
2582 When this macro is not defined, the compiler will access a field by
2583 finding the smallest containing object; when it is defined, a
2584 fullword load will be used if alignment permits. Unless bytes
2585 accesses are faster than word accesses, using word accesses is
2586 preferable since it may eliminate subsequent memory access if
2587 subsequent accesses occur to other fields in the same word of the
2588 structure, but to different bytes. */
2590 #define SLOW_BYTE_ACCESS 0
2592 /* Nonzero if access to memory by shorts is slow and undesirable. */
2593 #define SLOW_SHORT_ACCESS 0
2595 /* Define this macro if zero-extension (of a `char' or `short' to an
2596 `int') can be done faster if the destination is a register that is
2599 If you define this macro, you must have instruction patterns that
2600 recognize RTL structures like this:
2602 (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
2604 and likewise for `HImode'. */
2606 /* #define SLOW_ZERO_EXTEND */
2608 /* Define this macro to be the value 1 if unaligned accesses have a
2609 cost many times greater than aligned accesses, for example if they
2610 are emulated in a trap handler.
2612 When this macro is non-zero, the compiler will act as if
2613 `STRICT_ALIGNMENT' were non-zero when generating code for block
2614 moves. This can cause significantly more instructions to be
2615 produced. Therefore, do not set this macro non-zero if unaligned
2616 accesses only add a cycle or two to the time for a memory access.
2618 If the value of this macro is always zero, it need not be defined. */
2620 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2622 /* Define this macro to inhibit strength reduction of memory
2623 addresses. (On some machines, such strength reduction seems to do
2624 harm rather than good.) */
2626 /* #define DONT_REDUCE_ADDR */
2628 /* Define this macro if it is as good or better to call a constant
2629 function address than to call an address kept in a register.
2631 Desirable on the 386 because a CALL with a constant address is
2632 faster than one with a register address. */
2634 #define NO_FUNCTION_CSE
2636 /* Define this macro if it is as good or better for a function to call
2637 itself with an explicit address than to call an address kept in a
2640 #define NO_RECURSIVE_FUNCTION_CSE
2642 /* Add any extra modes needed to represent the condition code.
2644 For the i386, we need separate modes when floating-point
2645 equality comparisons are being done.
2647 Add CCNO to indicate comparisons against zero that requires
2648 Overflow flag to be unset. Sign bit test is used instead and
2649 thus can be used to form "a&b>0" type of tests.
2651 Add CCGC to indicate comparisons agains zero that allows
2652 unspecified garbage in the Carry flag. This mode is used
2653 by inc/dec instructions.
2655 Add CCGOC to indicate comparisons agains zero that allows
2656 unspecified garbage in the Carry and Overflow flag. This
2657 mode is used to simulate comparisons of (a-b) and (a+b)
2658 against zero using sub/cmp/add operations.
2660 Add CCZ to indicate that only the Zero flag is valid. */
2662 #define EXTRA_CC_MODES \
2663 CC(CCGCmode, "CCGC") \
2664 CC(CCGOCmode, "CCGOC") \
2665 CC(CCNOmode, "CCNO") \
2666 CC(CCZmode, "CCZ") \
2667 CC(CCFPmode, "CCFP") \
2668 CC(CCFPUmode, "CCFPU")
2670 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2671 return the mode to be used for the comparison.
2673 For floating-point equality comparisons, CCFPEQmode should be used.
2674 VOIDmode should be used in all other cases.
2676 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2677 possible, to allow for more combinations. */
2679 #define SELECT_CC_MODE(OP,X,Y) ix86_cc_mode (OP, X, Y)
2681 /* Return non-zero if MODE implies a floating point inequality can be
2684 #define REVERSIBLE_CC_MODE(MODE) 1
2686 /* A C expression whose value is reversed condition code of the CODE for
2687 comparison done in CC_MODE mode. */
2688 #define REVERSE_CONDITION(CODE, MODE) \
2689 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2690 : reverse_condition_maybe_unordered (CODE))
2693 /* Control the assembler format that we output, to the extent
2694 this does not vary between assemblers. */
2696 /* How to refer to registers in assembler output.
2697 This sequence is indexed by compiler's hard-register-number (see above). */
2699 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2700 For non floating point regs, the following are the HImode names.
2702 For float regs, the stack top is sometimes referred to as "%st(0)"
2703 instead of just "%st". PRINT_REG handles this with the "y" code. */
2705 #undef HI_REGISTER_NAMES
2706 #define HI_REGISTER_NAMES \
2707 {"ax","dx","cx","bx","si","di","bp","sp", \
2708 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2709 "flags","fpsr", "dirflag", "frame", \
2710 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2711 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2712 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2713 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2715 #define REGISTER_NAMES HI_REGISTER_NAMES
2717 /* Table of additional register names to use in user input. */
2719 #define ADDITIONAL_REGISTER_NAMES \
2720 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2721 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2722 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2723 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2724 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2725 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2726 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2727 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2729 /* Note we are omitting these since currently I don't know how
2730 to get gcc to use these, since they want the same but different
2731 number as al, and ax.
2734 #define QI_REGISTER_NAMES \
2735 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2737 /* These parallel the array above, and can be used to access bits 8:15
2738 of regs 0 through 3. */
2740 #define QI_HIGH_REGISTER_NAMES \
2741 {"ah", "dh", "ch", "bh", }
2743 /* How to renumber registers for dbx and gdb. */
2745 #define DBX_REGISTER_NUMBER(n) \
2746 (TARGET_64BIT ? dbx64_register_map[n] : dbx_register_map[n])
2748 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2749 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2750 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2752 /* Before the prologue, RA is at 0(%esp). */
2753 #define INCOMING_RETURN_ADDR_RTX \
2754 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2756 /* After the prologue, RA is at -4(AP) in the current frame. */
2757 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2759 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2760 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2762 /* PC is dbx register 8; let's use that column for RA. */
2763 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2765 /* Before the prologue, the top of the frame is at 4(%esp). */
2766 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2768 /* Describe how we implement __builtin_eh_return. */
2769 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2770 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2772 /* Select a format to encode pointers in exception handling data. CODE
2773 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2774 true if the symbol may be affected by dynamic relocations.
2776 ??? All x86 object file formats are capable of representing this.
2777 After all, the relocation needed is the same as for the call insn.
2778 Whether or not a particular assembler allows us to enter such, I
2779 guess we'll have to see. */
2780 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2781 (flag_pic ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel \
2784 /* This is how to output the definition of a user-level label named NAME,
2785 such as the label on a static function or variable NAME. */
2787 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2788 (assemble_name (FILE, NAME), fputs (":\n", FILE))
2790 /* This is how to output an assembler line defining a `double' constant. */
2792 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2794 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
2795 fprintf (FILE, "%s0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \
2798 /* This is how to output a `long double' extended real constant. */
2800 #undef ASM_OUTPUT_LONG_DOUBLE
2801 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2803 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
2804 if (TARGET_128BIT_LONG_DOUBLE) \
2805 fprintf (FILE, "%s0x%lx,0x%lx,0x%lx,0x0\n", ASM_LONG, l[0], l[1], l[2]); \
2807 fprintf (FILE, "%s0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \
2810 /* This is how to output an assembler line defining a `float' constant. */
2812 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2814 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2815 fprintf ((FILE), "%s0x%lx\n", ASM_LONG, l); \
2818 /* Store in OUTPUT a string (made with alloca) containing
2819 an assembler-name for a local static variable named NAME.
2820 LABELNO is an integer which is different for each call. */
2822 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2823 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2824 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2826 /* This is how to output an assembler line defining an `int' constant. */
2828 #define ASM_OUTPUT_INT(FILE,VALUE) \
2829 ( fputs (ASM_LONG, FILE), \
2830 output_addr_const (FILE,(VALUE)), \
2833 /* Likewise for `char' and `short' constants. */
2835 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2836 ( fputs (ASM_SHORT, FILE), \
2837 output_addr_const (FILE,(VALUE)), \
2840 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2841 ( fputs (ASM_BYTE_OP, FILE), \
2842 output_addr_const (FILE, (VALUE)), \
2845 /* Given that x86 natively supports unaligned data, it's reasonable to
2846 assume that all x86 assemblers don't auto-align data. Thus the
2847 unaligned output macros required by dwarf2 frame unwind information
2848 degenerate to the macros used above. */
2849 #define UNALIGNED_SHORT_ASM_OP ASM_SHORT
2850 #define UNALIGNED_INT_ASM_OP ASM_LONG
2851 #define INT_ASM_OP ASM_LONG
2853 /* This is how to output an assembler line for a numeric constant byte. */
2855 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2856 asm_fprintf ((FILE), "%s0x%x\n", ASM_BYTE_OP, (VALUE))
2858 /* This is how to output an insn to push a register on the stack.
2859 It need not be very fast code. */
2861 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2862 asm_fprintf (FILE, "\tpush{l}\t%%e%s\n", reg_names[REGNO])
2864 /* This is how to output an insn to pop a register from the stack.
2865 It need not be very fast code. */
2867 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2868 asm_fprintf (FILE, "\tpop{l}\t%%e%s\n", reg_names[REGNO])
2870 /* This is how to output an element of a case-vector that is absolute.
2873 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2874 fprintf (FILE, "%s%s%d\n", ASM_LONG, LPREFIX, VALUE)
2876 /* This is how to output an element of a case-vector that is relative.
2877 We don't use these on the 386 yet, because the ATT assembler can't do
2878 forward reference the differences.
2881 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2882 fprintf (FILE, "%s%s%d-%s%d\n",ASM_LONG, LPREFIX, VALUE, LPREFIX, REL)
2884 /* A C statement that outputs an address constant appropriate to
2885 for DWARF debugging. */
2887 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,X) \
2888 i386_dwarf_output_addr_const((FILE),(X))
2890 /* Either simplify a location expression, or return the original. */
2892 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2893 i386_simplify_dwarf_addr(X)
2895 /* Print operand X (an rtx) in assembler syntax to file FILE.
2896 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2897 Effect of various CODE letters is described in i386.c near
2898 print_operand function. */
2900 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2901 ((CODE) == '*' || (CODE) == '+')
2903 /* Print the name of a register based on its machine mode and number.
2904 If CODE is 'w', pretend the mode is HImode.
2905 If CODE is 'b', pretend the mode is QImode.
2906 If CODE is 'k', pretend the mode is SImode.
2907 If CODE is 'q', pretend the mode is DImode.
2908 If CODE is 'h', pretend the reg is the `high' byte register.
2909 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2911 #define PRINT_REG(X, CODE, FILE) \
2912 print_reg (X, CODE, FILE)
2914 #define PRINT_OPERAND(FILE, X, CODE) \
2915 print_operand (FILE, X, CODE)
2917 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2918 print_operand_address (FILE, ADDR)
2920 /* Print the name of a register for based on its machine mode and number.
2921 This macro is used to print debugging output.
2922 This macro is different from PRINT_REG in that it may be used in
2923 programs that are not linked with aux-output.o. */
2925 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2926 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2927 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2928 fprintf (FILE, "%d ", REGNO (X)); \
2929 if (REGNO (X) == FLAGS_REG) \
2930 { fputs ("flags", FILE); break; } \
2931 if (REGNO (X) == DIRFLAG_REG) \
2932 { fputs ("dirflag", FILE); break; } \
2933 if (REGNO (X) == FPSR_REG) \
2934 { fputs ("fpsr", FILE); break; } \
2935 if (REGNO (X) == ARG_POINTER_REGNUM) \
2936 { fputs ("argp", FILE); break; } \
2937 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2938 { fputs ("frame", FILE); break; } \
2939 if (STACK_TOP_P (X)) \
2940 { fputs ("st(0)", FILE); break; } \
2942 { fputs (hi_name[REGNO(X)], FILE); break; } \
2943 if (REX_INT_REG_P (X)) \
2945 switch (GET_MODE_SIZE (GET_MODE (X))) \
2949 fprintf (FILE, "r%i", REGNO (X) \
2950 - FIRST_REX_INT_REG + 8); \
2953 fprintf (FILE, "r%id", REGNO (X) \
2954 - FIRST_REX_INT_REG + 8); \
2957 fprintf (FILE, "r%iw", REGNO (X) \
2958 - FIRST_REX_INT_REG + 8); \
2961 fprintf (FILE, "r%ib", REGNO (X) \
2962 - FIRST_REX_INT_REG + 8); \
2967 switch (GET_MODE_SIZE (GET_MODE (X))) \
2970 fputs ("r", FILE); \
2971 fputs (hi_name[REGNO (X)], FILE); \
2974 fputs ("e", FILE); \
2976 fputs (hi_name[REGNO (X)], FILE); \
2979 fputs (qi_name[REGNO (X)], FILE); \
2984 /* a letter which is not needed by the normal asm syntax, which
2985 we can use for operand syntax in the extended asm */
2987 #define ASM_OPERAND_LETTER '#'
2988 #define RET return ""
2989 #define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx))
2991 /* Define the codes that are matched by predicates in i386.c. */
2993 #define PREDICATE_CODES \
2994 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
2995 SYMBOL_REF, LABEL_REF, CONST}}, \
2996 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
2997 SYMBOL_REF, LABEL_REF, CONST}}, \
2998 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
2999 SYMBOL_REF, LABEL_REF, CONST}}, \
3000 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3001 SYMBOL_REF, LABEL_REF, CONST}}, \
3002 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3003 SYMBOL_REF, LABEL_REF, CONST}}, \
3004 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3005 SYMBOL_REF, LABEL_REF, CONST}}, \
3006 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3007 SYMBOL_REF, LABEL_REF}}, \
3008 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3009 {"const_int_1_operand", {CONST_INT}}, \
3010 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3011 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3012 LABEL_REF, SUBREG, REG, MEM}}, \
3013 {"pic_symbolic_operand", {CONST}}, \
3014 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3015 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3016 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3017 {"const1_operand", {CONST_INT}}, \
3018 {"const248_operand", {CONST_INT}}, \
3019 {"incdec_operand", {CONST_INT}}, \
3020 {"mmx_reg_operand", {REG}}, \
3021 {"reg_no_sp_operand", {SUBREG, REG}}, \
3022 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3023 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3024 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3025 {"q_regs_operand", {SUBREG, REG}}, \
3026 {"non_q_regs_operand", {SUBREG, REG}}, \
3027 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3028 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3029 GE, UNGE, LTGT, UNEQ}}, \
3030 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3031 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3033 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3034 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3035 UNGE, UNGT, LTGT, UNEQ }}, \
3036 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3037 {"ext_register_operand", {SUBREG, REG}}, \
3038 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3039 {"mult_operator", {MULT}}, \
3040 {"div_operator", {DIV}}, \
3041 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3042 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3043 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3044 LSHIFTRT, ROTATERT}}, \
3045 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3046 {"memory_displacement_operand", {MEM}}, \
3047 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3048 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3049 {"long_memory_operand", {MEM}},
3051 /* A list of predicates that do special things with modes, and so
3052 should not elicit warnings for VOIDmode match_operand. */
3054 #define SPECIAL_MODE_PREDICATES \
3055 "ext_register_operand",
3057 /* CM_32 is used by 32bit ABI
3058 CM_SMALL is small model assuming that all code and data fits in the first
3059 31bits of address space.
3060 CM_KERNEL is model assuming that all code and data fits in the negative
3061 31bits of address space.
3062 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3063 space. Size of data is unlimited.
3064 CM_LARGE is model making no assumptions about size of particular sections.
3066 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3067 tables first in 31bits of address space.
3078 /* Size of the RED_ZONE area. */
3079 #define RED_ZONE_SIZE 128
3080 /* Reserved area of the red zone for temporaries. */
3081 #define RED_ZONE_RESERVE 8
3082 /* Valud of -mcmodel specified by user. */
3083 extern const char *ix86_cmodel_string;
3084 extern enum cmodel ix86_cmodel;
3086 /* Variables in i386.c */
3087 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3088 extern const char *ix86_arch_string; /* for -march=<xxx> */
3089 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3090 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3091 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3092 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3093 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3094 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3095 extern int ix86_regparm; /* ix86_regparm_string as a number */
3096 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3097 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3098 extern const char * const hi_reg_name[]; /* names for 16 bit regs */
3099 extern const char * const qi_reg_name[]; /* names for 8 bit regs (low) */
3100 extern const char * const qi_high_reg_name[]; /* names for 8 bit regs (high) */
3101 extern enum reg_class const regclass_map[]; /* smalled class containing REGNO */
3102 extern struct rtx_def *ix86_compare_op0; /* operand 0 for comparisons */
3103 extern struct rtx_def *ix86_compare_op1; /* operand 1 for comparisons */
3105 /* To properly truncate FP values into integers, we need to set i387 control
3106 word. We can't emit proper mode switching code before reload, as spills
3107 generated by reload may truncate values incorrectly, but we still can avoid
3108 redundant computation of new control word by the mode switching pass.
3109 The fldcw instructions are still emitted redundantly, but this is probably
3110 not going to be noticeable problem, as most CPUs do have fast path for
3113 The machinery is to emit simple truncation instructions and split them
3114 before reload to instructions having USEs of two memory locations that
3115 are filled by this code to old and new control word.
3117 Post-reload pass may be later used to eliminate the redundant fildcw if
3120 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3122 /* Define this macro if the port needs extra instructions inserted
3123 for mode switching in an optimizing compilation. */
3125 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3127 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3128 initializer for an array of integers. Each initializer element N
3129 refers to an entity that needs mode switching, and specifies the
3130 number of different modes that might need to be set for this
3131 entity. The position of the initializer in the initializer -
3132 starting counting at zero - determines the integer that is used to
3133 refer to the mode-switched entity in question. */
3135 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3137 /* ENTITY is an integer specifying a mode-switched entity. If
3138 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3139 return an integer value not larger than the corresponding element
3140 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3141 must be switched into prior to the execution of INSN. */
3143 #define MODE_NEEDED(ENTITY, I) \
3144 (GET_CODE (I) == CALL_INSN \
3145 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3146 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3147 ? FP_CW_UNINITIALIZED \
3148 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3152 /* This macro specifies the order in which modes for ENTITY are
3153 processed. 0 is the highest priority. */
3155 #define MODE_PRIORITY_TO_MODE(ENTITY, N) N
3157 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3158 is the set of hard registers live at the point where the insn(s)
3159 are to be inserted. */
3161 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3162 (MODE == FP_CW_STORED \
3163 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3164 assign_386_stack_local (HImode, 2)), 0\
3167 /* Avoid renaming of stack registers, as doing so in combination with
3168 scheduling just increases amount of live registers at time and in
3169 the turn amount of fxch instructions needed.
3171 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3173 #define HARD_REGNO_RENAME_OK(src,target) \
3174 ((src) < FIRST_STACK_REG || (src) > LAST_STACK_REG)
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