1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) (X)
48 #define HALF_PIC_FINISH(STREAM)
51 /* Define the specific costs for a given cpu */
53 struct processor_costs {
54 const int add; /* cost of an add instruction */
55 const int lea; /* cost of a lea instruction */
56 const int shift_var; /* variable shift costs */
57 const int shift_const; /* constant shift costs */
58 const int mult_init; /* cost of starting a multiply */
59 const int mult_bit; /* cost of multiply per each bit set */
60 const int divide; /* cost of a divide/mod */
61 int movsx; /* The cost of movsx operation. */
62 int movzx; /* The cost of movzx operation. */
63 const int large_insn; /* insns larger than this cost more */
64 const int move_ratio; /* The threshold of number of scalar
65 memory-to-memory move insns. */
66 const int movzbl_load; /* cost of loading using movzbl */
67 const int int_load[3]; /* cost of loading integer registers
68 in QImode, HImode and SImode relative
69 to reg-reg move (2). */
70 const int int_store[3]; /* cost of storing integer register
71 in QImode, HImode and SImode */
72 const int fp_move; /* cost of reg,reg fld/fst */
73 const int fp_load[3]; /* cost of loading FP register
74 in SFmode, DFmode and XFmode */
75 const int fp_store[3]; /* cost of storing FP register
76 in SFmode, DFmode and XFmode */
77 const int mmx_move; /* cost of moving MMX register. */
78 const int mmx_load[2]; /* cost of loading MMX register
79 in SImode and DImode */
80 const int mmx_store[2]; /* cost of storing MMX register
81 in SImode and DImode */
82 const int sse_move; /* cost of moving SSE register. */
83 const int sse_load[3]; /* cost of loading SSE register
84 in SImode, DImode and TImode*/
85 const int sse_store[3]; /* cost of storing SSE register
86 in SImode, DImode and TImode*/
87 const int mmxsse_to_integer; /* cost of moving mmxsse register to
88 integer and vice versa. */
89 const int prefetch_block; /* bytes moved to cache for prefetch. */
90 const int simultaneous_prefetches; /* number of parallel prefetch
94 extern const struct processor_costs *ix86_cost;
96 /* Run-time compilation parameters selecting different hardware subsets. */
98 extern int target_flags;
100 /* Macros used in the machine description to test the flags. */
102 /* configure can arrange to make this 2, to force a 486. */
104 #ifndef TARGET_CPU_DEFAULT
105 #define TARGET_CPU_DEFAULT 0
108 /* Masks for the -m switches */
109 #define MASK_80387 0x00000001 /* Hardware floating point */
110 #define MASK_RTD 0x00000002 /* Use ret that pops args */
111 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
112 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
113 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
114 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
115 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
116 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
117 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
118 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
119 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
120 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
121 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
122 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
123 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
124 #define MASK_MMX_SET 0x00008000
125 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
126 #define MASK_SSE_SET 0x00020000
127 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
128 #define MASK_SSE2_SET 0x00080000
129 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
130 #define MASK_3DNOW_SET 0x00200000
131 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
132 #define MASK_3DNOW_A_SET 0x00800000
133 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
134 #define MASK_64BIT 0x02000000 /* Produce 64bit code */
135 /* ... overlap with subtarget options starts by 0x04000000. */
136 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
138 /* Use the floating point instructions */
139 #define TARGET_80387 (target_flags & MASK_80387)
141 /* Compile using ret insn that pops args.
142 This will not work unless you use prototypes at least
143 for all functions that can take varying numbers of args. */
144 #define TARGET_RTD (target_flags & MASK_RTD)
146 /* Align doubles to a two word boundary. This breaks compatibility with
147 the published ABI's for structures containing doubles, but produces
148 faster code on the pentium. */
149 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
151 /* Use push instructions to save outgoing args. */
152 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
154 /* Accumulate stack adjustments to prologue/epilogue. */
155 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
156 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
158 /* Put uninitialized locals into bss, not data.
159 Meaningful only on svr3. */
160 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
162 /* Use IEEE floating point comparisons. These handle correctly the cases
163 where the result of a comparison is unordered. Normally SIGFPE is
164 generated in such cases, in which case this isn't needed. */
165 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
167 /* Functions that return a floating point value may return that value
168 in the 387 FPU or in 386 integer registers. If set, this flag causes
169 the 387 to be used, which is compatible with most calling conventions. */
170 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
172 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
173 This mode wastes cache, but avoid misaligned data accesses and simplifies
174 address calculations. */
175 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
177 /* Disable generation of FP sin, cos and sqrt operations for 387.
178 This is because FreeBSD lacks these in the math-emulator-code */
179 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
181 /* Don't create frame pointers for leaf functions */
182 #define TARGET_OMIT_LEAF_FRAME_POINTER \
183 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
185 /* Debug GO_IF_LEGITIMATE_ADDRESS */
186 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
188 /* Debug FUNCTION_ARG macros */
189 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
191 /* 64bit Sledgehammer mode */
192 #ifdef TARGET_BI_ARCH
193 #define TARGET_64BIT (target_flags & MASK_64BIT)
195 #ifdef TARGET_64BIT_DEFAULT
196 #define TARGET_64BIT 1
198 #define TARGET_64BIT 0
202 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
203 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
204 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
205 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
206 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
207 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
208 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
210 #define CPUMASK (1 << ix86_cpu)
211 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
212 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
213 extern const int x86_branch_hints, x86_unroll_strlen;
214 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
215 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
216 extern const int x86_use_cltd, x86_read_modify_write;
217 extern const int x86_read_modify, x86_split_long_moves;
218 extern const int x86_promote_QImode, x86_single_stringop;
219 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
220 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
221 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
222 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
223 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
224 extern const int x86_epilogue_using_move, x86_decompose_lea;
225 extern const int x86_arch_always_fancy_math_387;
226 extern int x86_prefetch_sse;
228 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
229 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
230 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
231 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
232 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
233 /* For sane SSE instruction set generation we need fcomi instruction. It is
234 safe to enable all CMOVE instructions. */
235 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
236 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
237 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
238 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
239 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
240 #define TARGET_MOVX (x86_movx & CPUMASK)
241 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
242 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
243 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
244 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
245 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
246 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
247 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
248 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
249 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
250 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
251 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
252 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
253 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
254 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
255 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
256 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
257 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
258 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
259 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
260 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
261 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
262 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
263 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
264 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
265 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
267 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
269 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
270 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
272 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
274 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
275 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
276 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
277 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
278 && (ix86_fpmath & FPMATH_387))
279 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
280 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
281 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
283 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
285 /* WARNING: Do not mark empty strings for translation, as calling
286 gettext on an empty string does NOT return an empty
290 #define TARGET_SWITCHES \
291 { { "80387", MASK_80387, N_("Use hardware fp") }, \
292 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
293 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
294 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
295 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
296 { "386", 0, "" /*Deprecated.*/}, \
297 { "486", 0, "" /*Deprecated.*/}, \
298 { "pentium", 0, "" /*Deprecated.*/}, \
299 { "pentiumpro", 0, "" /*Deprecated.*/}, \
300 { "intel-syntax", 0, "" /*Deprecated.*/}, \
301 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
303 N_("Alternate calling convention") }, \
304 { "no-rtd", -MASK_RTD, \
305 N_("Use normal calling convention") }, \
306 { "align-double", MASK_ALIGN_DOUBLE, \
307 N_("Align some doubles on dword boundary") }, \
308 { "no-align-double", -MASK_ALIGN_DOUBLE, \
309 N_("Align doubles on word boundary") }, \
310 { "svr3-shlib", MASK_SVR3_SHLIB, \
311 N_("Uninitialized locals in .bss") }, \
312 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
313 N_("Uninitialized locals in .data") }, \
314 { "ieee-fp", MASK_IEEE_FP, \
315 N_("Use IEEE math for fp comparisons") }, \
316 { "no-ieee-fp", -MASK_IEEE_FP, \
317 N_("Do not use IEEE math for fp comparisons") }, \
318 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
319 N_("Return values of functions in FPU registers") }, \
320 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
321 N_("Do not return values of functions in FPU registers")}, \
322 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
323 N_("Do not generate sin, cos, sqrt for FPU") }, \
324 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
325 N_("Generate sin, cos, sqrt for FPU")}, \
326 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
327 N_("Omit the frame pointer in leaf functions") }, \
328 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
329 { "stack-arg-probe", MASK_STACK_PROBE, \
330 N_("Enable stack probing") }, \
331 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
332 { "windows", 0, 0 /* undocumented */ }, \
333 { "dll", 0, 0 /* undocumented */ }, \
334 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
335 N_("Align destination of the string operations") }, \
336 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
337 N_("Do not align destination of the string operations") }, \
338 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
339 N_("Inline all known string operations") }, \
340 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
341 N_("Do not inline all known string operations") }, \
342 { "push-args", -MASK_NO_PUSH_ARGS, \
343 N_("Use push instructions to save outgoing arguments") }, \
344 { "no-push-args", MASK_NO_PUSH_ARGS, \
345 N_("Do not use push instructions to save outgoing arguments") }, \
346 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
347 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
348 N_("Use push instructions to save outgoing arguments") }, \
349 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
350 N_("Do not use push instructions to save outgoing arguments") }, \
351 { "mmx", MASK_MMX | MASK_MMX_SET, \
352 N_("Support MMX built-in functions") }, \
353 { "no-mmx", -MASK_MMX, \
354 N_("Do not support MMX built-in functions") }, \
355 { "no-mmx", MASK_MMX_SET, "" }, \
356 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
357 N_("Support 3DNow! built-in functions") }, \
358 { "no-3dnow", -MASK_3DNOW, "" }, \
359 { "no-3dnow", MASK_3DNOW_SET, \
360 N_("Do not support 3DNow! built-in functions") }, \
361 { "sse", MASK_SSE | MASK_SSE_SET, \
362 N_("Support MMX and SSE built-in functions and code generation") }, \
363 { "no-sse", -MASK_SSE, "" }, \
364 { "no-sse", MASK_SSE_SET, \
365 N_("Do not support MMX and SSE built-in functions and code generation") },\
366 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
367 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
368 { "no-sse2", -MASK_SSE2, "" }, \
369 { "no-sse2", MASK_SSE2_SET, \
370 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
371 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
372 N_("sizeof(long double) is 16") }, \
373 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
374 N_("sizeof(long double) is 12") }, \
375 { "64", MASK_64BIT, \
376 N_("Generate 64bit x86-64 code") }, \
377 { "32", -MASK_64BIT, \
378 N_("Generate 32bit i386 code") }, \
379 { "red-zone", -MASK_NO_RED_ZONE, \
380 N_("Use red-zone in the x86-64 code") }, \
381 { "no-red-zone", MASK_NO_RED_ZONE, \
382 N_("Do not use red-zone in the x86-64 code") }, \
384 { "", TARGET_DEFAULT, 0 }}
386 #ifdef TARGET_64BIT_DEFAULT
387 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
389 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
392 /* Which processor to schedule for. The cpu attribute defines a list that
393 mirrors this list, so changes to i386.md must be made at the same time. */
397 PROCESSOR_I386, /* 80386 */
398 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
400 PROCESSOR_PENTIUMPRO,
412 extern enum processor_type ix86_cpu;
413 extern enum fpmath_unit ix86_fpmath;
415 extern int ix86_arch;
417 /* This macro is similar to `TARGET_SWITCHES' but defines names of
418 command options that have values. Its definition is an
419 initializer with a subgrouping for each command option.
421 Each subgrouping contains a string constant, that defines the
422 fixed part of the option name, and the address of a variable. The
423 variable, type `char *', is set to the variable part of the given
424 option if the fixed part matches. The actual option name is made
425 by appending `-m' to the specified name. */
426 #define TARGET_OPTIONS \
427 { { "cpu=", &ix86_cpu_string, \
428 N_("Schedule code for given CPU")}, \
429 { "fpmath=", &ix86_fpmath_string, \
430 N_("Generate floating point mathematics using given instruction set")},\
431 { "arch=", &ix86_arch_string, \
432 N_("Generate code for given CPU")}, \
433 { "regparm=", &ix86_regparm_string, \
434 N_("Number of registers used to pass integer arguments") }, \
435 { "align-loops=", &ix86_align_loops_string, \
436 N_("Loop code aligned to this power of 2") }, \
437 { "align-jumps=", &ix86_align_jumps_string, \
438 N_("Jump targets are aligned to this power of 2") }, \
439 { "align-functions=", &ix86_align_funcs_string, \
440 N_("Function starts are aligned to this power of 2") }, \
441 { "preferred-stack-boundary=", \
442 &ix86_preferred_stack_boundary_string, \
443 N_("Attempt to keep stack aligned to this power of 2") }, \
444 { "branch-cost=", &ix86_branch_cost_string, \
445 N_("Branches are this expensive (1-5, arbitrary units)") }, \
446 { "cmodel=", &ix86_cmodel_string, \
447 N_("Use given x86-64 code model") }, \
448 { "debug-arg", &ix86_debug_arg_string, \
449 "" /* Undocumented. */ }, \
450 { "debug-addr", &ix86_debug_addr_string, \
451 "" /* Undocumented. */ }, \
452 { "asm=", &ix86_asm_string, \
453 N_("Use given assembler dialect") }, \
457 /* Sometimes certain combinations of command options do not make
458 sense on a particular target machine. You can define a macro
459 `OVERRIDE_OPTIONS' to take account of this. This macro, if
460 defined, is executed once just after all the command options have
463 Don't use this macro to turn on various extra optimizations for
464 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
466 #define OVERRIDE_OPTIONS override_options ()
468 /* These are meant to be redefined in the host dependent files */
469 #define SUBTARGET_SWITCHES
470 #define SUBTARGET_OPTIONS
472 /* Define this to change the optimizations performed by default. */
473 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
474 optimization_options ((LEVEL), (SIZE))
476 /* Specs for the compiler proper */
479 #define CC1_CPU_SPEC "\
482 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
484 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
485 %{mpentium:-mcpu=pentium \
486 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
487 %{mpentiumpro:-mcpu=pentiumpro \
488 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
489 %{mintel-syntax:-masm=intel \
490 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
491 %{mno-intel-syntax:-masm=att \
492 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
495 #define TARGET_CPU_DEFAULT_i386 0
496 #define TARGET_CPU_DEFAULT_i486 1
497 #define TARGET_CPU_DEFAULT_pentium 2
498 #define TARGET_CPU_DEFAULT_pentium_mmx 3
499 #define TARGET_CPU_DEFAULT_pentiumpro 4
500 #define TARGET_CPU_DEFAULT_pentium2 5
501 #define TARGET_CPU_DEFAULT_pentium3 6
502 #define TARGET_CPU_DEFAULT_pentium4 7
503 #define TARGET_CPU_DEFAULT_k6 8
504 #define TARGET_CPU_DEFAULT_k6_2 9
505 #define TARGET_CPU_DEFAULT_k6_3 10
506 #define TARGET_CPU_DEFAULT_athlon 11
507 #define TARGET_CPU_DEFAULT_athlon_sse 12
509 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
510 "pentiumpro", "pentium2", "pentium3", \
511 "pentium4", "k6", "k6-2", "k6-3",\
512 "athlon", "athlon-4"}
513 #ifndef CPP_CPU_DEFAULT_SPEC
514 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
515 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
517 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
518 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
520 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
521 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
523 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
524 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
526 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
527 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
530 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
531 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
532 -D__tune_pentium2__ -D__tune_pentium3__"
534 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
535 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
537 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
538 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
540 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
541 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
543 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
544 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
546 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
547 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
549 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
550 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
552 #ifndef CPP_CPU_DEFAULT_SPEC
553 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
555 #endif /* CPP_CPU_DEFAULT_SPEC */
557 #ifdef TARGET_BI_ARCH
558 #define NO_BUILTIN_SIZE_TYPE
559 #define NO_BUILTIN_PTRDIFF_TYPE
562 #ifdef NO_BUILTIN_SIZE_TYPE
563 #define CPP_CPU32_SIZE_TYPE_SPEC \
564 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
565 #define CPP_CPU64_SIZE_TYPE_SPEC \
566 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int"
568 #define CPP_CPU32_SIZE_TYPE_SPEC ""
569 #define CPP_CPU64_SIZE_TYPE_SPEC ""
572 #define CPP_CPU32_SPEC \
573 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
574 -D__i386__ %(cpp_cpu32sizet)"
576 #define CPP_CPU64_SPEC \
577 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)"
579 #define CPP_CPUCOMMON_SPEC "\
580 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
581 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
582 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
583 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
584 %{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
586 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
587 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
588 -D__pentiumpro -D__pentiumpro__ \
589 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
590 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
591 %{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
592 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
593 %{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
594 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
595 %{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
596 %{!mcpu*:-D__tune_athlon__ }}\
597 %{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
599 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
600 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
601 %{m386|mcpu=i386:-D__tune_i386__ }\
602 %{m486|mcpu=i486:-D__tune_i486__ }\
603 %{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
604 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
605 -D__tune_pentiumpro__ }\
606 %{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
607 %{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
609 %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
610 -D__tune_athlon_sse__ }\
611 %{mcpu=pentium4:-D__tune_pentium4__ }\
612 %{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
614 %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
615 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
616 |march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
617 %{march=k6-2|march=k6-3\
618 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
619 |march=athlon-mp: -D__3dNOW__ }\
620 %{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
621 |march=athlon-mp: -D__3dNOW_A__ }\
622 %{march=pentium4: -D__SSE2__ }\
623 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
626 #ifdef TARGET_BI_ARCH
627 #ifdef TARGET_64BIT_DEFAULT
628 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
630 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
633 #ifdef TARGET_64BIT_DEFAULT
634 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
636 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
642 #define CC1_SPEC "%(cc1_cpu) "
645 /* This macro defines names of additional specifications to put in the
646 specs that can be used in various specifications like CC1_SPEC. Its
647 definition is an initializer with a subgrouping for each command option.
649 Each subgrouping contains a string constant, that defines the
650 specification name, and a string constant that used by the GNU CC driver
653 Do not define this macro if it does not need to do anything. */
655 #ifndef SUBTARGET_EXTRA_SPECS
656 #define SUBTARGET_EXTRA_SPECS
659 #define EXTRA_SPECS \
660 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
661 { "cpp_cpu", CPP_CPU_SPEC }, \
662 { "cpp_cpu32", CPP_CPU32_SPEC }, \
663 { "cpp_cpu64", CPP_CPU64_SPEC }, \
664 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \
665 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \
666 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
667 { "cc1_cpu", CC1_CPU_SPEC }, \
668 SUBTARGET_EXTRA_SPECS
670 /* target machine storage layout */
672 /* Define for XFmode or TFmode extended real floating point support.
673 The XFmode is specified by i386 ABI, while TFmode may be faster
674 due to alignment and simplifications in the address calculations.
676 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
677 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
679 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
681 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
683 /* Tell real.c that this is the 80-bit Intel extended float format
684 packaged in a 128-bit or 96bit entity. */
685 #define INTEL_EXTENDED_IEEE_FORMAT 1
688 #define SHORT_TYPE_SIZE 16
689 #define INT_TYPE_SIZE 32
690 #define FLOAT_TYPE_SIZE 32
691 #define LONG_TYPE_SIZE BITS_PER_WORD
692 #define MAX_WCHAR_TYPE_SIZE 32
693 #define DOUBLE_TYPE_SIZE 64
694 #define LONG_LONG_TYPE_SIZE 64
696 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
697 #define MAX_BITS_PER_WORD 64
698 #define MAX_LONG_TYPE_SIZE 64
700 #define MAX_BITS_PER_WORD 32
701 #define MAX_LONG_TYPE_SIZE 32
704 /* Define this if most significant byte of a word is the lowest numbered. */
705 /* That is true on the 80386. */
707 #define BITS_BIG_ENDIAN 0
709 /* Define this if most significant byte of a word is the lowest numbered. */
710 /* That is not true on the 80386. */
711 #define BYTES_BIG_ENDIAN 0
713 /* Define this if most significant word of a multiword number is the lowest
715 /* Not true for 80386 */
716 #define WORDS_BIG_ENDIAN 0
718 /* Width of a word, in units (bytes). */
719 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
720 #define MIN_UNITS_PER_WORD 4
722 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
723 #define PARM_BOUNDARY BITS_PER_WORD
725 /* Boundary (in *bits*) on which stack pointer should be aligned. */
726 #define STACK_BOUNDARY BITS_PER_WORD
728 /* Boundary (in *bits*) on which the stack pointer preferrs to be
729 aligned; the compiler cannot rely on having this alignment. */
730 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
732 /* As of July 2001, many runtimes to not align the stack properly when
733 entering main. This causes expand_main_function to forcably align
734 the stack, which results in aligned frames for functions called from
735 main, though it does nothing for the alignment of main itself. */
736 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
737 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
739 /* Allocation boundary for the code of a function. */
740 #define FUNCTION_BOUNDARY 16
742 /* Alignment of field after `int : 0' in a structure. */
744 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
746 /* Minimum size in bits of the largest boundary to which any
747 and all fundamental data types supported by the hardware
748 might need to be aligned. No data type wants to be aligned
751 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
752 and Pentium Pro XFmode values at 128 bit boundaries. */
754 #define BIGGEST_ALIGNMENT 128
756 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
757 #define ALIGN_MODE_128(MODE) \
758 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
759 || (MODE) == V4SFmode || (MODE) == V4SImode)
761 /* The published ABIs say that doubles should be aligned on word
762 boundaries, so lower the aligment for structure fields unless
763 -malign-double is set. */
764 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
765 constant. Use the smaller value in that context. */
766 #ifndef IN_TARGET_LIBS
767 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
769 #define BIGGEST_FIELD_ALIGNMENT 32
772 /* If defined, a C expression to compute the alignment given to a
773 constant that is being placed in memory. EXP is the constant
774 and ALIGN is the alignment that the object would ordinarily have.
775 The value of this macro is used instead of that alignment to align
778 If this macro is not defined, then ALIGN is used.
780 The typical use of this macro is to increase alignment for string
781 constants to be word aligned so that `strcpy' calls that copy
782 constants can be done inline. */
784 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
786 /* If defined, a C expression to compute the alignment for a static
787 variable. TYPE is the data type, and ALIGN is the alignment that
788 the object would ordinarily have. The value of this macro is used
789 instead of that alignment to align the object.
791 If this macro is not defined, then ALIGN is used.
793 One use of this macro is to increase alignment of medium-size
794 data to make it all fit in fewer cache lines. Another is to
795 cause character arrays to be word-aligned so that `strcpy' calls
796 that copy constants to character arrays can be done inline. */
798 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
800 /* If defined, a C expression to compute the alignment for a local
801 variable. TYPE is the data type, and ALIGN is the alignment that
802 the object would ordinarily have. The value of this macro is used
803 instead of that alignment to align the object.
805 If this macro is not defined, then ALIGN is used.
807 One use of this macro is to increase alignment of medium-size
808 data to make it all fit in fewer cache lines. */
810 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
812 /* If defined, a C expression that gives the alignment boundary, in
813 bits, of an argument with the specified mode and type. If it is
814 not defined, `PARM_BOUNDARY' is used for all arguments. */
816 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
817 ix86_function_arg_boundary ((MODE), (TYPE))
819 /* Set this non-zero if move instructions will actually fail to work
820 when given unaligned data. */
821 #define STRICT_ALIGNMENT 0
823 /* If bit field type is int, don't let it cross an int,
824 and give entire struct the alignment of an int. */
825 /* Required on the 386 since it doesn't have bitfield insns. */
826 #define PCC_BITFIELD_TYPE_MATTERS 1
828 /* Standard register usage. */
830 /* This processor has special stack-like registers. See reg-stack.c
834 #define IS_STACK_MODE(MODE) \
835 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
838 /* Number of actual hardware registers.
839 The hardware registers are assigned numbers for the compiler
840 from 0 to just below FIRST_PSEUDO_REGISTER.
841 All registers that the compiler knows about must be given numbers,
842 even those that are not normally considered general registers.
844 In the 80386 we give the 8 general purpose registers the numbers 0-7.
845 We number the floating point registers 8-15.
846 Note that registers 0-7 can be accessed as a short or int,
847 while only 0-3 may be used with byte `mov' instructions.
849 Reg 16 does not correspond to any hardware register, but instead
850 appears in the RTL as an argument pointer prior to reload, and is
851 eliminated during reloading in favor of either the stack or frame
854 #define FIRST_PSEUDO_REGISTER 53
856 /* Number of hardware registers that go into the DWARF-2 unwind info.
857 If not defined, equals FIRST_PSEUDO_REGISTER. */
859 #define DWARF_FRAME_REGISTERS 17
861 /* 1 for registers that have pervasive standard uses
862 and are not available for the register allocator.
863 On the 80386, the stack pointer is such, as is the arg pointer.
865 The value is an mask - bit 1 is set for fixed registers
866 for 32bit target, while 2 is set for fixed registers for 64bit.
867 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
869 #define FIXED_REGISTERS \
870 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
871 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
872 /*arg,flags,fpsr,dir,frame*/ \
874 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
875 0, 0, 0, 0, 0, 0, 0, 0, \
876 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
877 0, 0, 0, 0, 0, 0, 0, 0, \
878 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
879 1, 1, 1, 1, 1, 1, 1, 1, \
880 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
881 1, 1, 1, 1, 1, 1, 1, 1}
884 /* 1 for registers not available across function calls.
885 These must include the FIXED_REGISTERS and also any
886 registers that can be used without being saved.
887 The latter must include the registers where values are returned
888 and the register where structure-value addresses are passed.
889 Aside from that, you can include as many other registers as you like.
891 The value is an mask - bit 1 is set for call used
892 for 32bit target, while 2 is set for call used for 64bit.
893 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
895 #define CALL_USED_REGISTERS \
896 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
897 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
898 /*arg,flags,fpsr,dir,frame*/ \
900 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
901 3, 3, 3, 3, 3, 3, 3, 3, \
902 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
903 3, 3, 3, 3, 3, 3, 3, 3, \
904 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
905 3, 3, 3, 3, 1, 1, 1, 1, \
906 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
907 3, 3, 3, 3, 3, 3, 3, 3} \
909 /* Order in which to allocate registers. Each register must be
910 listed once, even those in FIXED_REGISTERS. List frame pointer
911 late and fixed registers last. Note that, in general, we prefer
912 registers listed in CALL_USED_REGISTERS, keeping the others
913 available for storage of persistent values.
915 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
916 so this is just empty initializer for array. */
918 #define REG_ALLOC_ORDER \
919 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
920 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
921 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
924 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
925 to be rearranged based on a particular function. When using sse math,
926 we want to allocase SSE before x87 registers and vice vera. */
928 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
931 /* Macro to conditionally modify fixed_regs/call_used_regs. */
932 #define CONDITIONAL_REGISTER_USAGE \
935 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
937 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
938 call_used_regs[i] = (call_used_regs[i] \
939 & (TARGET_64BIT ? 2 : 1)) != 0; \
941 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
943 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
944 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
949 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
950 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
951 fixed_regs[i] = call_used_regs[i] = 1; \
956 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
957 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
958 fixed_regs[i] = call_used_regs[i] = 1; \
960 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
964 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
965 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
966 if (TEST_HARD_REG_BIT (x, i)) \
967 fixed_regs[i] = call_used_regs[i] = 1; \
971 /* Return number of consecutive hard regs needed starting at reg REGNO
972 to hold something of mode MODE.
973 This is ordinarily the length in words of a value of mode MODE
974 but can be less for certain modes in special long registers.
976 Actually there are no two word move instructions for consecutive
977 registers. And only registers 0-3 may have mov byte instructions
981 #define HARD_REGNO_NREGS(REGNO, MODE) \
982 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
983 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
984 : ((MODE) == TFmode \
985 ? (TARGET_64BIT ? 2 : 3) \
987 ? (TARGET_64BIT ? 4 : 6) \
988 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
990 #define VALID_SSE_REG_MODE(MODE) \
991 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
992 || (MODE) == SFmode \
993 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
995 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
996 ((MODE) == V2SFmode || (MODE) == SFmode)
998 #define VALID_MMX_REG_MODE(MODE) \
999 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1000 || (MODE) == V2SImode || (MODE) == SImode)
1002 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1003 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
1004 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
1005 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1007 #define VALID_FP_MODE_P(MODE) \
1008 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
1009 || (!TARGET_64BIT && (MODE) == XFmode) \
1010 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
1011 || (!TARGET_64BIT && (MODE) == XCmode))
1013 #define VALID_INT_MODE_P(MODE) \
1014 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1015 || (MODE) == DImode \
1016 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1017 || (MODE) == CDImode \
1018 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
1020 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1022 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1023 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1025 /* Value is 1 if it is a good idea to tie two pseudo registers
1026 when one has mode MODE1 and one has mode MODE2.
1027 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1028 for any hard reg, then this must be 0 for correct output. */
1030 #define MODES_TIEABLE_P(MODE1, MODE2) \
1031 ((MODE1) == (MODE2) \
1032 || (((MODE1) == HImode || (MODE1) == SImode \
1033 || ((MODE1) == QImode \
1034 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1035 || ((MODE1) == DImode && TARGET_64BIT)) \
1036 && ((MODE2) == HImode || (MODE2) == SImode \
1037 || ((MODE1) == QImode \
1038 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1039 || ((MODE2) == DImode && TARGET_64BIT))))
1042 /* Specify the modes required to caller save a given hard regno.
1043 We do this on i386 to prevent flags from being saved at all.
1045 Kill any attempts to combine saving of modes. */
1047 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1048 (CC_REGNO_P (REGNO) ? VOIDmode \
1049 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1050 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1051 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1052 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1054 /* Specify the registers used for certain standard purposes.
1055 The values of these macros are register numbers. */
1057 /* on the 386 the pc register is %eip, and is not usable as a general
1058 register. The ordinary mov instructions won't work */
1059 /* #define PC_REGNUM */
1061 /* Register to use for pushing function arguments. */
1062 #define STACK_POINTER_REGNUM 7
1064 /* Base register for access to local variables of the function. */
1065 #define HARD_FRAME_POINTER_REGNUM 6
1067 /* Base register for access to local variables of the function. */
1068 #define FRAME_POINTER_REGNUM 20
1070 /* First floating point reg */
1071 #define FIRST_FLOAT_REG 8
1073 /* First & last stack-like regs */
1074 #define FIRST_STACK_REG FIRST_FLOAT_REG
1075 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1077 #define FLAGS_REG 17
1079 #define DIRFLAG_REG 19
1081 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1082 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1084 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1085 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1087 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1088 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1090 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1091 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1093 /* Value should be nonzero if functions must have frame pointers.
1094 Zero means the frame pointer need not be set up (and parms
1095 may be accessed via the stack pointer) in functions that seem suitable.
1096 This is computed in `reload', in reload1.c. */
1097 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1099 /* Override this in other tm.h files to cope with various OS losage
1100 requiring a frame pointer. */
1101 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1102 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1105 /* Make sure we can access arbitrary call frames. */
1106 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1108 /* Base register for access to arguments of the function. */
1109 #define ARG_POINTER_REGNUM 16
1111 /* Register in which static-chain is passed to a function.
1112 We do use ECX as static chain register for 32 bit ABI. On the
1113 64bit ABI, ECX is an argument register, so we use R10 instead. */
1114 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1116 /* Register to hold the addressing base for position independent
1117 code access to data items. We don't use PIC pointer for 64bit
1118 mode. Define the regnum to dummy value to prevent gcc from
1119 pessimizing code dealing with EBX. */
1120 #define PIC_OFFSET_TABLE_REGNUM \
1121 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM : 3)
1123 /* Register in which address to store a structure value
1124 arrives in the function. On the 386, the prologue
1125 copies this from the stack to register %eax. */
1126 #define STRUCT_VALUE_INCOMING 0
1128 /* Place in which caller passes the structure value address.
1129 0 means push the value on the stack like an argument. */
1130 #define STRUCT_VALUE 0
1132 /* A C expression which can inhibit the returning of certain function
1133 values in registers, based on the type of value. A nonzero value
1134 says to return the function value in memory, just as large
1135 structures are always returned. Here TYPE will be a C expression
1136 of type `tree', representing the data type of the value.
1138 Note that values of mode `BLKmode' must be explicitly handled by
1139 this macro. Also, the option `-fpcc-struct-return' takes effect
1140 regardless of this macro. On most systems, it is possible to
1141 leave the macro undefined; this causes a default definition to be
1142 used, whose value is the constant 1 for `BLKmode' values, and 0
1145 Do not use this macro to indicate that structures and unions
1146 should always be returned in memory. You should instead use
1147 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1149 #define RETURN_IN_MEMORY(TYPE) \
1150 ix86_return_in_memory (TYPE)
1153 /* Define the classes of registers for register constraints in the
1154 machine description. Also define ranges of constants.
1156 One of the classes must always be named ALL_REGS and include all hard regs.
1157 If there is more than one class, another class must be named NO_REGS
1158 and contain no registers.
1160 The name GENERAL_REGS must be the name of a class (or an alias for
1161 another name such as ALL_REGS). This is the class of registers
1162 that is allowed by "g" or "r" in a register constraint.
1163 Also, registers outside this class are allocated only when
1164 instructions express preferences for them.
1166 The classes must be numbered in nondecreasing order; that is,
1167 a larger-numbered class must never be contained completely
1168 in a smaller-numbered class.
1170 For any two classes, it is very desirable that there be another
1171 class that represents their union.
1173 It might seem that class BREG is unnecessary, since no useful 386
1174 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1175 and the "b" register constraint is useful in asms for syscalls.
1177 The flags and fpsr registers are in no class. */
1182 AREG, DREG, CREG, BREG, SIREG, DIREG,
1183 AD_REGS, /* %eax/%edx for DImode */
1184 Q_REGS, /* %eax %ebx %ecx %edx */
1185 NON_Q_REGS, /* %esi %edi %ebp %esp */
1186 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1187 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1188 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1189 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1199 ALL_REGS, LIM_REG_CLASSES
1202 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1204 #define INTEGER_CLASS_P(CLASS) \
1205 reg_class_subset_p ((CLASS), GENERAL_REGS)
1206 #define FLOAT_CLASS_P(CLASS) \
1207 reg_class_subset_p ((CLASS), FLOAT_REGS)
1208 #define SSE_CLASS_P(CLASS) \
1209 reg_class_subset_p ((CLASS), SSE_REGS)
1210 #define MMX_CLASS_P(CLASS) \
1211 reg_class_subset_p ((CLASS), MMX_REGS)
1212 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1213 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1214 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1215 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1216 #define MAYBE_SSE_CLASS_P(CLASS) \
1217 reg_classes_intersect_p (SSE_REGS, (CLASS))
1218 #define MAYBE_MMX_CLASS_P(CLASS) \
1219 reg_classes_intersect_p (MMX_REGS, (CLASS))
1221 #define Q_CLASS_P(CLASS) \
1222 reg_class_subset_p ((CLASS), Q_REGS)
1224 /* Give names of register classes as strings for dump file. */
1226 #define REG_CLASS_NAMES \
1228 "AREG", "DREG", "CREG", "BREG", \
1231 "Q_REGS", "NON_Q_REGS", \
1235 "FP_TOP_REG", "FP_SECOND_REG", \
1239 "FP_TOP_SSE_REGS", \
1240 "FP_SECOND_SSE_REGS", \
1244 "FLOAT_INT_SSE_REGS", \
1247 /* Define which registers fit in which classes.
1248 This is an initializer for a vector of HARD_REG_SET
1249 of length N_REG_CLASSES. */
1251 #define REG_CLASS_CONTENTS \
1253 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1254 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1255 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1256 { 0x03, 0x0 }, /* AD_REGS */ \
1257 { 0x0f, 0x0 }, /* Q_REGS */ \
1258 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1259 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1260 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1261 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1262 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1263 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1264 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1265 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1266 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1267 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1268 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1269 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1270 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1271 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1272 { 0xffffffff,0x1fffff } \
1275 /* The same information, inverted:
1276 Return the class number of the smallest class containing
1277 reg number REGNO. This could be a conditional expression
1278 or could index an array. */
1280 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1282 /* When defined, the compiler allows registers explicitly used in the
1283 rtl to be used as spill registers but prevents the compiler from
1284 extending the lifetime of these registers. */
1286 #define SMALL_REGISTER_CLASSES 1
1288 #define QI_REG_P(X) \
1289 (REG_P (X) && REGNO (X) < 4)
1291 #define GENERAL_REGNO_P(N) \
1292 ((N) < 8 || REX_INT_REGNO_P (N))
1294 #define GENERAL_REG_P(X) \
1295 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1297 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1299 #define NON_QI_REG_P(X) \
1300 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1302 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1303 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1305 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1306 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1307 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1308 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1310 #define SSE_REGNO_P(N) \
1311 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1312 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1314 #define SSE_REGNO(N) \
1315 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1316 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1318 #define SSE_FLOAT_MODE_P(MODE) \
1319 ((TARGET_SSE_MATH && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1321 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1322 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1324 #define STACK_REG_P(XOP) \
1326 REGNO (XOP) >= FIRST_STACK_REG && \
1327 REGNO (XOP) <= LAST_STACK_REG)
1329 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1331 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1333 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1334 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1336 /* Indicate whether hard register numbered REG_NO should be converted
1338 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1339 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1341 /* The class value for index registers, and the one for base regs. */
1343 #define INDEX_REG_CLASS INDEX_REGS
1344 #define BASE_REG_CLASS GENERAL_REGS
1346 /* Get reg_class from a letter such as appears in the machine description. */
1348 #define REG_CLASS_FROM_LETTER(C) \
1349 ((C) == 'r' ? GENERAL_REGS : \
1350 (C) == 'R' ? LEGACY_REGS : \
1351 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1352 (C) == 'Q' ? Q_REGS : \
1353 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1356 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1359 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1362 (C) == 'a' ? AREG : \
1363 (C) == 'b' ? BREG : \
1364 (C) == 'c' ? CREG : \
1365 (C) == 'd' ? DREG : \
1366 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1367 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1368 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1369 (C) == 'A' ? AD_REGS : \
1370 (C) == 'D' ? DIREG : \
1371 (C) == 'S' ? SIREG : NO_REGS)
1373 /* The letters I, J, K, L and M in a register constraint string
1374 can be used to stand for particular ranges of immediate operands.
1375 This macro defines what the ranges are.
1376 C is the letter, and VALUE is a constant value.
1377 Return 1 if VALUE is in the range specified by C.
1379 I is for non-DImode shifts.
1380 J is for DImode shifts.
1381 K is for signed imm8 operands.
1382 L is for andsi as zero-extending move.
1383 M is for shifts that can be executed by the "lea" opcode.
1384 N is for immedaite operands for out/in instructions (0-255)
1387 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1388 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1389 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1390 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1391 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1392 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1393 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1396 /* Similar, but for floating constants, and defining letters G and H.
1397 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1398 TARGET_387 isn't set, because the stack register converter may need to
1399 load 0.0 into the function value register. */
1401 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1402 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1403 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1405 /* A C expression that defines the optional machine-dependent
1406 constraint letters that can be used to segregate specific types of
1407 operands, usually memory references, for the target machine. Any
1408 letter that is not elsewhere defined and not matched by
1409 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1412 If it is required for a particular target machine, it should
1413 return 1 if VALUE corresponds to the operand type represented by
1414 the constraint letter C. If C is not defined as an extra
1415 constraint, the value returned should be 0 regardless of VALUE. */
1417 #define EXTRA_CONSTRAINT(VALUE, C) \
1418 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1419 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1422 /* Place additional restrictions on the register class to use when it
1423 is necessary to be able to hold a value of mode MODE in a reload
1424 register for which class CLASS would ordinarily be used. */
1426 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1427 ((MODE) == QImode && !TARGET_64BIT \
1428 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1429 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1432 /* Given an rtx X being reloaded into a reg required to be
1433 in class CLASS, return the class of reg to actually use.
1434 In general this is just CLASS; but on some machines
1435 in some cases it is preferable to use a more restrictive class.
1436 On the 80386 series, we prevent floating constants from being
1437 reloaded into floating registers (since no move-insn can do that)
1438 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1440 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1441 QImode must go into class Q_REGS.
1442 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1443 movdf to do mem-to-mem moves through integer regs. */
1445 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1446 ix86_preferred_reload_class ((X), (CLASS))
1448 /* If we are copying between general and FP registers, we need a memory
1449 location. The same is true for SSE and MMX registers. */
1450 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1451 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1453 /* QImode spills from non-QI registers need a scratch. This does not
1454 happen often -- the only example so far requires an uninitialized
1457 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1458 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1459 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1462 /* Return the maximum number of consecutive registers
1463 needed to represent mode MODE in a register of class CLASS. */
1464 /* On the 80386, this is the size of MODE in words,
1465 except in the FP regs, where a single reg is always enough.
1466 The TFmodes are really just 80bit values, so we use only 3 registers
1467 to hold them, instead of 4, as the size would suggest.
1469 #define CLASS_MAX_NREGS(CLASS, MODE) \
1470 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1471 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1472 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1473 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1475 /* A C expression whose value is nonzero if pseudos that have been
1476 assigned to registers of class CLASS would likely be spilled
1477 because registers of CLASS are needed for spill registers.
1479 The default value of this macro returns 1 if CLASS has exactly one
1480 register and zero otherwise. On most machines, this default
1481 should be used. Only define this macro to some other expression
1482 if pseudo allocated by `local-alloc.c' end up in memory because
1483 their hard registers were needed for spill registers. If this
1484 macro returns nonzero for those classes, those pseudos will only
1485 be allocated by `global.c', which knows how to reallocate the
1486 pseudo to another register. If there would not be another
1487 register available for reallocation, you should not change the
1488 definition of this macro since the only effect of such a
1489 definition would be to slow down register allocation. */
1491 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1492 (((CLASS) == AREG) \
1493 || ((CLASS) == DREG) \
1494 || ((CLASS) == CREG) \
1495 || ((CLASS) == BREG) \
1496 || ((CLASS) == AD_REGS) \
1497 || ((CLASS) == SIREG) \
1498 || ((CLASS) == DIREG))
1500 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1501 to automatically clobber for all asms.
1503 We do this in the new i386 backend to maintain source compatibility
1504 with the old cc0-based compiler. */
1506 #define MD_ASM_CLOBBERS(CLOBBERS) \
1508 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1510 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1512 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1516 /* Stack layout; function entry, exit and calling. */
1518 /* Define this if pushing a word on the stack
1519 makes the stack pointer a smaller address. */
1520 #define STACK_GROWS_DOWNWARD
1522 /* Define this if the nominal address of the stack frame
1523 is at the high-address end of the local variables;
1524 that is, each additional local variable allocated
1525 goes at a more negative offset in the frame. */
1526 #define FRAME_GROWS_DOWNWARD
1528 /* Offset within stack frame to start allocating local variables at.
1529 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1530 first local allocated. Otherwise, it is the offset to the BEGINNING
1531 of the first local allocated. */
1532 #define STARTING_FRAME_OFFSET 0
1534 /* If we generate an insn to push BYTES bytes,
1535 this says how many the stack pointer really advances by.
1536 On 386 pushw decrements by exactly 2 no matter what the position was.
1537 On the 386 there is no pushb; we use pushw instead, and this
1538 has the effect of rounding up to 2.
1540 For 64bit ABI we round up to 8 bytes.
1543 #define PUSH_ROUNDING(BYTES) \
1545 ? (((BYTES) + 7) & (-8)) \
1546 : (((BYTES) + 1) & (-2)))
1548 /* If defined, the maximum amount of space required for outgoing arguments will
1549 be computed and placed into the variable
1550 `current_function_outgoing_args_size'. No space will be pushed onto the
1551 stack for each call; instead, the function prologue should increase the stack
1552 frame size by this amount. */
1554 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1556 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1557 instructions to pass outgoing arguments. */
1559 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1561 /* Offset of first parameter from the argument pointer register value. */
1562 #define FIRST_PARM_OFFSET(FNDECL) 0
1564 /* Define this macro if functions should assume that stack space has been
1565 allocated for arguments even when their values are passed in registers.
1567 The value of this macro is the size, in bytes, of the area reserved for
1568 arguments passed in registers for the function represented by FNDECL.
1570 This space can be allocated by the caller, or be a part of the
1571 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1573 #define REG_PARM_STACK_SPACE(FNDECL) 0
1575 /* Define as a C expression that evaluates to nonzero if we do not know how
1576 to pass TYPE solely in registers. The file expr.h defines a
1577 definition that is usually appropriate, refer to expr.h for additional
1578 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1579 computed in the stack and then loaded into a register. */
1580 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1582 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1583 || TREE_ADDRESSABLE (TYPE) \
1584 || ((MODE) == TImode) \
1585 || ((MODE) == BLKmode \
1587 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1588 && 0 == (int_size_in_bytes (TYPE) \
1589 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1590 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1591 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1593 /* Value is the number of bytes of arguments automatically
1594 popped when returning from a subroutine call.
1595 FUNDECL is the declaration node of the function (as a tree),
1596 FUNTYPE is the data type of the function (as a tree),
1597 or for a library call it is an identifier node for the subroutine name.
1598 SIZE is the number of bytes of arguments passed on the stack.
1600 On the 80386, the RTD insn may be used to pop them if the number
1601 of args is fixed, but if the number is variable then the caller
1602 must pop them all. RTD can't be used for library calls now
1603 because the library is compiled with the Unix compiler.
1604 Use of RTD is a selectable option, since it is incompatible with
1605 standard Unix calling sequences. If the option is not selected,
1606 the caller must always pop the args.
1608 The attribute stdcall is equivalent to RTD on a per module basis. */
1610 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1611 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1613 /* Define how to find the value returned by a function.
1614 VALTYPE is the data type of the value (as a tree).
1615 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1616 otherwise, FUNC is 0. */
1617 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1618 ix86_function_value (VALTYPE)
1620 #define FUNCTION_VALUE_REGNO_P(N) \
1621 ix86_function_value_regno_p (N)
1623 /* Define how to find the value returned by a library function
1624 assuming the value has mode MODE. */
1626 #define LIBCALL_VALUE(MODE) \
1627 ix86_libcall_value (MODE)
1629 /* Define the size of the result block used for communication between
1630 untyped_call and untyped_return. The block contains a DImode value
1631 followed by the block used by fnsave and frstor. */
1633 #define APPLY_RESULT_SIZE (8+108)
1635 /* 1 if N is a possible register number for function argument passing. */
1636 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1638 /* Define a data type for recording info about an argument list
1639 during the scan of that argument list. This data type should
1640 hold all necessary information about the function itself
1641 and about the args processed so far, enough to enable macros
1642 such as FUNCTION_ARG to determine where the next arg should go. */
1644 typedef struct ix86_args {
1645 int words; /* # words passed so far */
1646 int nregs; /* # registers available for passing */
1647 int regno; /* next available register number */
1648 int sse_words; /* # sse words passed so far */
1649 int sse_nregs; /* # sse registers available for passing */
1650 int sse_regno; /* next available sse register number */
1651 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1654 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1655 for a call to a function whose data type is FNTYPE.
1656 For a library call, FNTYPE is 0. */
1658 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1659 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
1661 /* Update the data in CUM to advance over an argument
1662 of mode MODE and data type TYPE.
1663 (TYPE is null for libcalls where that information may not be available.) */
1665 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1666 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1668 /* Define where to put the arguments to a function.
1669 Value is zero to push the argument on the stack,
1670 or a hard register in which to store the argument.
1672 MODE is the argument's machine mode.
1673 TYPE is the data type of the argument (as a tree).
1674 This is null for libcalls where that information may
1676 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1677 the preceding args and about the function being called.
1678 NAMED is nonzero if this argument is a named parameter
1679 (otherwise it is an extra parameter matching an ellipsis). */
1681 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1682 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1684 /* For an arg passed partly in registers and partly in memory,
1685 this is the number of registers used.
1686 For args passed entirely in registers or entirely in memory, zero. */
1688 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1690 /* If PIC, we cannot make sibling calls to global functions
1691 because the PLT requires %ebx live.
1692 If we are returning floats on the register stack, we cannot make
1693 sibling calls to functions that return floats. (The stack adjust
1694 instruction will wind up after the sibcall jump, and not be executed.) */
1695 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1697 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1698 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1699 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1700 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1702 /* Perform any needed actions needed for a function that is receiving a
1703 variable number of arguments.
1707 MODE and TYPE are the mode and type of the current parameter.
1709 PRETEND_SIZE is a variable that should be set to the amount of stack
1710 that must be pushed by the prolog to pretend that our caller pushed
1713 Normally, this macro will push all remaining incoming registers on the
1714 stack and set PRETEND_SIZE to the length of the registers pushed. */
1716 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1717 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1720 /* Define the `__builtin_va_list' type for the ABI. */
1721 #define BUILD_VA_LIST_TYPE(VALIST) \
1722 ((VALIST) = ix86_build_va_list ())
1724 /* Implement `va_start' for varargs and stdarg. */
1725 #define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \
1726 ix86_va_start ((STDARG), (VALIST), (NEXTARG))
1728 /* Implement `va_arg'. */
1729 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1730 ix86_va_arg ((VALIST), (TYPE))
1732 /* This macro is invoked at the end of compilation. It is used here to
1733 output code for -fpic that will load the return address into %ebx. */
1736 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1738 /* Output assembler code to FILE to increment profiler label # LABELNO
1739 for profiling a function entry. */
1741 #define FUNCTION_PROFILER(FILE, LABELNO) \
1745 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1746 LPREFIX, (LABELNO)); \
1747 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1751 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1752 fprintf ((FILE), "\tcall\t_mcount\n"); \
1756 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1757 the stack pointer does not matter. The value is tested only in
1758 functions that have frame pointers.
1759 No definition is equivalent to always zero. */
1760 /* Note on the 386 it might be more efficient not to define this since
1761 we have to restore it ourselves from the frame pointer, in order to
1764 #define EXIT_IGNORE_STACK 1
1766 /* Output assembler code for a block containing the constant parts
1767 of a trampoline, leaving space for the variable parts. */
1769 /* On the 386, the trampoline contains two instructions:
1772 The trampoline is generated entirely at runtime. The operand of JMP
1773 is the address of FUNCTION relative to the instruction following the
1774 JMP (which is 5 bytes long). */
1776 /* Length in units of the trampoline for entering a nested function. */
1778 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1780 /* Emit RTL insns to initialize the variable parts of a trampoline.
1781 FNADDR is an RTX for the address of the function's pure code.
1782 CXT is an RTX for the static chain value for the function. */
1784 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1785 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1787 /* Definitions for register eliminations.
1789 This is an array of structures. Each structure initializes one pair
1790 of eliminable registers. The "from" register number is given first,
1791 followed by "to". Eliminations of the same "from" register are listed
1792 in order of preference.
1794 There are two registers that can always be eliminated on the i386.
1795 The frame pointer and the arg pointer can be replaced by either the
1796 hard frame pointer or to the stack pointer, depending upon the
1797 circumstances. The hard frame pointer is not used before reload and
1798 so it is not eligible for elimination. */
1800 #define ELIMINABLE_REGS \
1801 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1802 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1803 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1804 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1806 /* Given FROM and TO register numbers, say whether this elimination is
1807 allowed. Frame pointer elimination is automatically handled.
1809 All other eliminations are valid. */
1811 #define CAN_ELIMINATE(FROM, TO) \
1812 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1814 /* Define the offset between two registers, one to be eliminated, and the other
1815 its replacement, at the start of a routine. */
1817 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1818 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1820 /* Addressing modes, and classification of registers for them. */
1822 /* #define HAVE_POST_INCREMENT 0 */
1823 /* #define HAVE_POST_DECREMENT 0 */
1825 /* #define HAVE_PRE_DECREMENT 0 */
1826 /* #define HAVE_PRE_INCREMENT 0 */
1828 /* Macros to check register numbers against specific register classes. */
1830 /* These assume that REGNO is a hard or pseudo reg number.
1831 They give nonzero only if REGNO is a hard reg of the suitable class
1832 or a pseudo reg currently allocated to a suitable hard reg.
1833 Since they use reg_renumber, they are safe only once reg_renumber
1834 has been allocated, which happens in local-alloc.c. */
1836 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1837 ((REGNO) < STACK_POINTER_REGNUM \
1838 || (REGNO >= FIRST_REX_INT_REG \
1839 && (REGNO) <= LAST_REX_INT_REG) \
1840 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1841 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1842 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1844 #define REGNO_OK_FOR_BASE_P(REGNO) \
1845 ((REGNO) <= STACK_POINTER_REGNUM \
1846 || (REGNO) == ARG_POINTER_REGNUM \
1847 || (REGNO) == FRAME_POINTER_REGNUM \
1848 || (REGNO >= FIRST_REX_INT_REG \
1849 && (REGNO) <= LAST_REX_INT_REG) \
1850 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1851 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1852 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1854 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1855 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1856 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1857 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1859 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1860 and check its validity for a certain class.
1861 We have two alternate definitions for each of them.
1862 The usual definition accepts all pseudo regs; the other rejects
1863 them unless they have been allocated suitable hard regs.
1864 The symbol REG_OK_STRICT causes the latter definition to be used.
1866 Most source files want to accept pseudo regs in the hope that
1867 they will get allocated to the class that the insn wants them to be in.
1868 Source files for reload pass need to be strict.
1869 After reload, it makes no difference, since pseudo regs have
1870 been eliminated by then. */
1873 /* Non strict versions, pseudos are ok */
1874 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1875 (REGNO (X) < STACK_POINTER_REGNUM \
1876 || (REGNO (X) >= FIRST_REX_INT_REG \
1877 && REGNO (X) <= LAST_REX_INT_REG) \
1878 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1880 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1881 (REGNO (X) <= STACK_POINTER_REGNUM \
1882 || REGNO (X) == ARG_POINTER_REGNUM \
1883 || REGNO (X) == FRAME_POINTER_REGNUM \
1884 || (REGNO (X) >= FIRST_REX_INT_REG \
1885 && REGNO (X) <= LAST_REX_INT_REG) \
1886 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1888 /* Strict versions, hard registers only */
1889 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1890 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1892 #ifndef REG_OK_STRICT
1893 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1894 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1897 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1898 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1901 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1902 that is a valid memory address for an instruction.
1903 The MODE argument is the machine mode for the MEM expression
1904 that wants to use this address.
1906 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1907 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1909 See legitimize_pic_address in i386.c for details as to what
1910 constitutes a legitimate address when -fpic is used. */
1912 #define MAX_REGS_PER_ADDRESS 2
1914 #define CONSTANT_ADDRESS_P(X) \
1915 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1916 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1917 || GET_CODE (X) == CONST_DOUBLE)
1919 /* Nonzero if the constant value X is a legitimate general operand.
1920 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1922 #define LEGITIMATE_CONSTANT_P(X) 1
1924 #ifdef REG_OK_STRICT
1925 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1927 if (legitimate_address_p ((MODE), (X), 1)) \
1932 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1934 if (legitimate_address_p ((MODE), (X), 0)) \
1940 /* If defined, a C expression to determine the base term of address X.
1941 This macro is used in only one place: `find_base_term' in alias.c.
1943 It is always safe for this macro to not be defined. It exists so
1944 that alias analysis can understand machine-dependent addresses.
1946 The typical use of this macro is to handle addresses containing
1947 a label_ref or symbol_ref within an UNSPEC. */
1949 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1951 /* Try machine-dependent ways of modifying an illegitimate address
1952 to be legitimate. If we find one, return the new, valid address.
1953 This macro is used in only one place: `memory_address' in explow.c.
1955 OLDX is the address as it was before break_out_memory_refs was called.
1956 In some cases it is useful to look at this to decide what needs to be done.
1958 MODE and WIN are passed so that this macro can use
1959 GO_IF_LEGITIMATE_ADDRESS.
1961 It is always safe for this macro to do nothing. It exists to recognize
1962 opportunities to optimize the output.
1964 For the 80386, we handle X+REG by loading X into a register R and
1965 using R+REG. R will go in a general reg and indexing will be used.
1966 However, if REG is a broken-out memory address or multiplication,
1967 nothing needs to be done because REG can certainly go in a general reg.
1969 When -fpic is used, special handling is needed for symbolic references.
1970 See comments by legitimize_pic_address in i386.c for details. */
1972 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1974 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1975 if (memory_address_p ((MODE), (X))) \
1979 #define REWRITE_ADDRESS(X) rewrite_address (X)
1981 /* Nonzero if the constant value X is a legitimate general operand
1982 when generating PIC code. It is given that flag_pic is on and
1983 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1985 #define LEGITIMATE_PIC_OPERAND_P(X) \
1986 (! SYMBOLIC_CONST (X) \
1987 || legitimate_pic_address_disp_p (X))
1989 #define SYMBOLIC_CONST(X) \
1990 (GET_CODE (X) == SYMBOL_REF \
1991 || GET_CODE (X) == LABEL_REF \
1992 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1994 /* Go to LABEL if ADDR (a legitimate address expression)
1995 has an effect that depends on the machine mode it is used for.
1996 On the 80386, only postdecrement and postincrement address depend thus
1997 (the amount of decrement or increment being the length of the operand). */
1998 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2000 if (GET_CODE (ADDR) == POST_INC \
2001 || GET_CODE (ADDR) == POST_DEC) \
2005 /* Codes for all the SSE/MMX builtins. */
2017 IX86_BUILTIN_CMPEQPS,
2018 IX86_BUILTIN_CMPLTPS,
2019 IX86_BUILTIN_CMPLEPS,
2020 IX86_BUILTIN_CMPGTPS,
2021 IX86_BUILTIN_CMPGEPS,
2022 IX86_BUILTIN_CMPNEQPS,
2023 IX86_BUILTIN_CMPNLTPS,
2024 IX86_BUILTIN_CMPNLEPS,
2025 IX86_BUILTIN_CMPNGTPS,
2026 IX86_BUILTIN_CMPNGEPS,
2027 IX86_BUILTIN_CMPORDPS,
2028 IX86_BUILTIN_CMPUNORDPS,
2029 IX86_BUILTIN_CMPNEPS,
2030 IX86_BUILTIN_CMPEQSS,
2031 IX86_BUILTIN_CMPLTSS,
2032 IX86_BUILTIN_CMPLESS,
2033 IX86_BUILTIN_CMPGTSS,
2034 IX86_BUILTIN_CMPGESS,
2035 IX86_BUILTIN_CMPNEQSS,
2036 IX86_BUILTIN_CMPNLTSS,
2037 IX86_BUILTIN_CMPNLESS,
2038 IX86_BUILTIN_CMPNGTSS,
2039 IX86_BUILTIN_CMPNGESS,
2040 IX86_BUILTIN_CMPORDSS,
2041 IX86_BUILTIN_CMPUNORDSS,
2042 IX86_BUILTIN_CMPNESS,
2044 IX86_BUILTIN_COMIEQSS,
2045 IX86_BUILTIN_COMILTSS,
2046 IX86_BUILTIN_COMILESS,
2047 IX86_BUILTIN_COMIGTSS,
2048 IX86_BUILTIN_COMIGESS,
2049 IX86_BUILTIN_COMINEQSS,
2050 IX86_BUILTIN_UCOMIEQSS,
2051 IX86_BUILTIN_UCOMILTSS,
2052 IX86_BUILTIN_UCOMILESS,
2053 IX86_BUILTIN_UCOMIGTSS,
2054 IX86_BUILTIN_UCOMIGESS,
2055 IX86_BUILTIN_UCOMINEQSS,
2057 IX86_BUILTIN_CVTPI2PS,
2058 IX86_BUILTIN_CVTPS2PI,
2059 IX86_BUILTIN_CVTSI2SS,
2060 IX86_BUILTIN_CVTSS2SI,
2061 IX86_BUILTIN_CVTTPS2PI,
2062 IX86_BUILTIN_CVTTSS2SI,
2069 IX86_BUILTIN_LOADAPS,
2070 IX86_BUILTIN_LOADUPS,
2071 IX86_BUILTIN_STOREAPS,
2072 IX86_BUILTIN_STOREUPS,
2073 IX86_BUILTIN_LOADSS,
2074 IX86_BUILTIN_STORESS,
2077 IX86_BUILTIN_MOVHLPS,
2078 IX86_BUILTIN_MOVLHPS,
2079 IX86_BUILTIN_LOADHPS,
2080 IX86_BUILTIN_LOADLPS,
2081 IX86_BUILTIN_STOREHPS,
2082 IX86_BUILTIN_STORELPS,
2084 IX86_BUILTIN_MASKMOVQ,
2085 IX86_BUILTIN_MOVMSKPS,
2086 IX86_BUILTIN_PMOVMSKB,
2088 IX86_BUILTIN_MOVNTPS,
2089 IX86_BUILTIN_MOVNTQ,
2091 IX86_BUILTIN_PACKSSWB,
2092 IX86_BUILTIN_PACKSSDW,
2093 IX86_BUILTIN_PACKUSWB,
2098 IX86_BUILTIN_PADDSB,
2099 IX86_BUILTIN_PADDSW,
2100 IX86_BUILTIN_PADDUSB,
2101 IX86_BUILTIN_PADDUSW,
2105 IX86_BUILTIN_PSUBSB,
2106 IX86_BUILTIN_PSUBSW,
2107 IX86_BUILTIN_PSUBUSB,
2108 IX86_BUILTIN_PSUBUSW,
2118 IX86_BUILTIN_PCMPEQB,
2119 IX86_BUILTIN_PCMPEQW,
2120 IX86_BUILTIN_PCMPEQD,
2121 IX86_BUILTIN_PCMPGTB,
2122 IX86_BUILTIN_PCMPGTW,
2123 IX86_BUILTIN_PCMPGTD,
2125 IX86_BUILTIN_PEXTRW,
2126 IX86_BUILTIN_PINSRW,
2128 IX86_BUILTIN_PMADDWD,
2130 IX86_BUILTIN_PMAXSW,
2131 IX86_BUILTIN_PMAXUB,
2132 IX86_BUILTIN_PMINSW,
2133 IX86_BUILTIN_PMINUB,
2135 IX86_BUILTIN_PMULHUW,
2136 IX86_BUILTIN_PMULHW,
2137 IX86_BUILTIN_PMULLW,
2139 IX86_BUILTIN_PSADBW,
2140 IX86_BUILTIN_PSHUFW,
2150 IX86_BUILTIN_PSLLWI,
2151 IX86_BUILTIN_PSLLDI,
2152 IX86_BUILTIN_PSLLQI,
2153 IX86_BUILTIN_PSRAWI,
2154 IX86_BUILTIN_PSRADI,
2155 IX86_BUILTIN_PSRLWI,
2156 IX86_BUILTIN_PSRLDI,
2157 IX86_BUILTIN_PSRLQI,
2159 IX86_BUILTIN_PUNPCKHBW,
2160 IX86_BUILTIN_PUNPCKHWD,
2161 IX86_BUILTIN_PUNPCKHDQ,
2162 IX86_BUILTIN_PUNPCKLBW,
2163 IX86_BUILTIN_PUNPCKLWD,
2164 IX86_BUILTIN_PUNPCKLDQ,
2166 IX86_BUILTIN_SHUFPS,
2170 IX86_BUILTIN_RSQRTPS,
2171 IX86_BUILTIN_RSQRTSS,
2172 IX86_BUILTIN_SQRTPS,
2173 IX86_BUILTIN_SQRTSS,
2175 IX86_BUILTIN_UNPCKHPS,
2176 IX86_BUILTIN_UNPCKLPS,
2179 IX86_BUILTIN_ANDNPS,
2184 IX86_BUILTIN_LDMXCSR,
2185 IX86_BUILTIN_STMXCSR,
2186 IX86_BUILTIN_SFENCE,
2188 /* 3DNow! Original */
2190 IX86_BUILTIN_PAVGUSB,
2194 IX86_BUILTIN_PFCMPEQ,
2195 IX86_BUILTIN_PFCMPGE,
2196 IX86_BUILTIN_PFCMPGT,
2201 IX86_BUILTIN_PFRCPIT1,
2202 IX86_BUILTIN_PFRCPIT2,
2203 IX86_BUILTIN_PFRSQIT1,
2204 IX86_BUILTIN_PFRSQRT,
2206 IX86_BUILTIN_PFSUBR,
2208 IX86_BUILTIN_PMULHRW,
2210 /* 3DNow! Athlon Extensions */
2212 IX86_BUILTIN_PFNACC,
2213 IX86_BUILTIN_PFPNACC,
2215 IX86_BUILTIN_PSWAPDSI,
2216 IX86_BUILTIN_PSWAPDSF,
2218 IX86_BUILTIN_SSE_ZERO,
2219 IX86_BUILTIN_MMX_ZERO,
2224 /* Define this macro if references to a symbol must be treated
2225 differently depending on something about the variable or
2226 function named by the symbol (such as what section it is in).
2228 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2229 so that we may access it directly in the GOT. */
2231 #define ENCODE_SECTION_INFO(DECL, FIRST) \
2235 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2236 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2238 if (GET_CODE (rtl) == MEM) \
2240 if (TARGET_DEBUG_ADDR \
2241 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2243 fprintf (stderr, "Encode %s, public = %d\n", \
2244 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2245 TREE_PUBLIC (DECL)); \
2248 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2249 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2250 || ! TREE_PUBLIC (DECL) \
2251 || MODULE_LOCAL_P (DECL)); \
2256 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2257 codes once the function is being compiled into assembly code, but
2258 not before. (It is not done before, because in the case of
2259 compiling an inline function, it would lead to multiple PIC
2260 prologues being included in functions which used inline functions
2261 and were compiled to assembly language.) */
2263 #define FINALIZE_PIC \
2264 (current_function_uses_pic_offset_table |= current_function_profile)
2267 /* Max number of args passed in registers. If this is more than 3, we will
2268 have problems with ebx (register #4), since it is a caller save register and
2269 is also used as the pic register in ELF. So for now, don't allow more than
2270 3 registers to be passed in registers. */
2272 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2274 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2277 /* Specify the machine mode that this machine uses
2278 for the index in the tablejump instruction. */
2279 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2281 /* Define as C expression which evaluates to nonzero if the tablejump
2282 instruction expects the table to contain offsets from the address of the
2284 Do not define this if the table should contain absolute addresses. */
2285 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2287 /* Define this as 1 if `char' should by default be signed; else as 0. */
2288 #define DEFAULT_SIGNED_CHAR 1
2290 /* Number of bytes moved into a data cache for a single prefetch operation. */
2291 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2293 /* Number of prefetch operations that can be done in parallel. */
2294 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2296 /* Max number of bytes we can move from memory to memory
2297 in one reasonably fast instruction. */
2300 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2301 move efficiently, as opposed to MOVE_MAX which is the maximum
2302 number of bytes we can move with a single instruction. */
2303 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2305 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2306 move-instruction pairs, we will do a movstr or libcall instead.
2307 Increasing the value will always make code faster, but eventually
2308 incurs high cost in increased code size.
2310 If you don't define this, a reasonable default is used. */
2312 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2314 /* Define if shifts truncate the shift count
2315 which implies one can omit a sign-extension or zero-extension
2316 of a shift count. */
2317 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2319 /* #define SHIFT_COUNT_TRUNCATED */
2321 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2322 is done just by pretending it is already truncated. */
2323 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2325 /* We assume that the store-condition-codes instructions store 0 for false
2326 and some other value for true. This is the value stored for true. */
2328 #define STORE_FLAG_VALUE 1
2330 /* When a prototype says `char' or `short', really pass an `int'.
2331 (The 386 can't easily push less than an int.) */
2333 #define PROMOTE_PROTOTYPES 1
2335 /* A macro to update M and UNSIGNEDP when an object whose type is
2336 TYPE and which has the specified mode and signedness is to be
2337 stored in a register. This macro is only called when TYPE is a
2340 On i386 it is sometimes useful to promote HImode and QImode
2341 quantities to SImode. The choice depends on target type. */
2343 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2345 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2346 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2350 /* Specify the machine mode that pointers have.
2351 After generation of rtl, the compiler makes no further distinction
2352 between pointers and any other objects of this machine mode. */
2353 #define Pmode (TARGET_64BIT ? DImode : SImode)
2355 /* A function address in a call instruction
2356 is a byte address (for indexing purposes)
2357 so give the MEM rtx a byte's mode. */
2358 #define FUNCTION_MODE QImode
2360 /* A part of a C `switch' statement that describes the relative costs
2361 of constant RTL expressions. It must contain `case' labels for
2362 expression codes `const_int', `const', `symbol_ref', `label_ref'
2363 and `const_double'. Each case must ultimately reach a `return'
2364 statement to return the relative cost of the use of that kind of
2365 constant value in an expression. The cost may depend on the
2366 precise value of the constant, which is available for examination
2367 in X, and the rtx code of the expression in which it is contained,
2368 found in OUTER_CODE.
2370 CODE is the expression code--redundant, since it can be obtained
2371 with `GET_CODE (X)'. */
2373 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2378 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2380 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2382 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2384 case CONST_DOUBLE: \
2387 if (GET_MODE (RTX) == VOIDmode) \
2390 code = standard_80387_constant_p (RTX); \
2391 return code == 1 ? 1 : \
2396 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2397 #define TOPLEVEL_COSTS_N_INSNS(N) \
2398 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2400 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2401 This can be used, for example, to indicate how costly a multiply
2402 instruction is. In writing this macro, you can use the construct
2403 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2404 instructions. OUTER_CODE is the code of the expression in which X
2407 This macro is optional; do not define it if the default cost
2408 assumptions are adequate for the target machine. */
2410 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2412 /* The zero extensions is often completely free on x86_64, so make \
2413 it as cheap as possible. */ \
2414 if (TARGET_64BIT && GET_MODE (X) == DImode \
2415 && GET_MODE (XEXP (X, 0)) == SImode) \
2417 total = 1; goto egress_rtx_costs; \
2420 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2421 ix86_cost->add : ix86_cost->movzx); \
2424 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2427 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2428 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2430 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2432 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2433 if ((value == 2 || value == 3) \
2434 && !TARGET_DECOMPOSE_LEA \
2435 && ix86_cost->lea <= ix86_cost->shift_const) \
2436 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2438 /* fall through */ \
2444 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2446 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2448 if (INTVAL (XEXP (X, 1)) > 32) \
2449 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2451 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2455 if (GET_CODE (XEXP (X, 1)) == AND) \
2456 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2458 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2463 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2464 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2466 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2471 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2473 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2476 while (value != 0) \
2482 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2483 + nbits * ix86_cost->mult_bit); \
2485 else /* This is arbitrary */ \
2486 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2487 + 7 * ix86_cost->mult_bit); \
2493 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2496 if (!TARGET_DECOMPOSE_LEA \
2497 && INTEGRAL_MODE_P (GET_MODE (X)) \
2498 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2500 if (GET_CODE (XEXP (X, 0)) == PLUS \
2501 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2502 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2503 && CONSTANT_P (XEXP (X, 1))) \
2505 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2506 if (val == 2 || val == 4 || val == 8) \
2508 return (COSTS_N_INSNS (ix86_cost->lea) \
2509 + rtx_cost (XEXP (XEXP (X, 0), 1), \
2511 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \
2513 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2516 else if (GET_CODE (XEXP (X, 0)) == MULT \
2517 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2519 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2520 if (val == 2 || val == 4 || val == 8) \
2522 return (COSTS_N_INSNS (ix86_cost->lea) \
2523 + rtx_cost (XEXP (XEXP (X, 0), 0), \
2525 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2528 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2530 return (COSTS_N_INSNS (ix86_cost->lea) \
2531 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \
2532 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \
2533 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2537 /* fall through */ \
2542 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2543 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2544 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \
2545 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2546 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \
2547 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2549 /* fall through */ \
2552 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2553 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2554 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2560 /* An expression giving the cost of an addressing mode that contains
2561 ADDRESS. If not defined, the cost is computed from the ADDRESS
2562 expression and the `CONST_COSTS' values.
2564 For most CISC machines, the default cost is a good approximation
2565 of the true cost of the addressing mode. However, on RISC
2566 machines, all instructions normally have the same length and
2567 execution time. Hence all addresses will have equal costs.
2569 In cases where more than one form of an address is known, the form
2570 with the lowest cost will be used. If multiple forms have the
2571 same, lowest, cost, the one that is the most complex will be used.
2573 For example, suppose an address that is equal to the sum of a
2574 register and a constant is used twice in the same basic block.
2575 When this macro is not defined, the address will be computed in a
2576 register and memory references will be indirect through that
2577 register. On machines where the cost of the addressing mode
2578 containing the sum is no higher than that of a simple indirect
2579 reference, this will produce an additional instruction and
2580 possibly require an additional register. Proper specification of
2581 this macro eliminates this overhead for such machines.
2583 Similar use of this macro is made in strength reduction of loops.
2585 ADDRESS need not be valid as an address. In such a case, the cost
2586 is not relevant and can be any value; invalid addresses need not be
2587 assigned a different cost.
2589 On machines where an address involving more than one register is as
2590 cheap as an address computation involving only one register,
2591 defining `ADDRESS_COST' to reflect this can cause two registers to
2592 be live over a region of code where only one would have been if
2593 `ADDRESS_COST' were not defined in that manner. This effect should
2594 be considered in the definition of this macro. Equivalent costs
2595 should probably only be given to addresses with different numbers
2596 of registers on machines with lots of registers.
2598 This macro will normally either not be defined or be defined as a
2601 For i386, it is better to use a complex address than let gcc copy
2602 the address into a reg and make a new pseudo. But not if the address
2603 requires to two regs - that would mean more pseudos with longer
2606 #define ADDRESS_COST(RTX) \
2607 ix86_address_cost (RTX)
2609 /* A C expression for the cost of moving data from a register in class FROM to
2610 one in class TO. The classes are expressed using the enumeration values
2611 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2612 interpreted relative to that.
2614 It is not required that the cost always equal 2 when FROM is the same as TO;
2615 on some machines it is expensive to move between registers if they are not
2616 general registers. */
2618 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2619 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2621 /* A C expression for the cost of moving data of mode M between a
2622 register and memory. A value of 2 is the default; this cost is
2623 relative to those in `REGISTER_MOVE_COST'.
2625 If moving between registers and memory is more expensive than
2626 between two registers, you should define this macro to express the
2629 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2630 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2632 /* A C expression for the cost of a branch instruction. A value of 1
2633 is the default; other values are interpreted relative to that. */
2635 #define BRANCH_COST ix86_branch_cost
2637 /* Define this macro as a C expression which is nonzero if accessing
2638 less than a word of memory (i.e. a `char' or a `short') is no
2639 faster than accessing a word of memory, i.e., if such access
2640 require more than one instruction or if there is no difference in
2641 cost between byte and (aligned) word loads.
2643 When this macro is not defined, the compiler will access a field by
2644 finding the smallest containing object; when it is defined, a
2645 fullword load will be used if alignment permits. Unless bytes
2646 accesses are faster than word accesses, using word accesses is
2647 preferable since it may eliminate subsequent memory access if
2648 subsequent accesses occur to other fields in the same word of the
2649 structure, but to different bytes. */
2651 #define SLOW_BYTE_ACCESS 0
2653 /* Nonzero if access to memory by shorts is slow and undesirable. */
2654 #define SLOW_SHORT_ACCESS 0
2656 /* Define this macro to be the value 1 if unaligned accesses have a
2657 cost many times greater than aligned accesses, for example if they
2658 are emulated in a trap handler.
2660 When this macro is non-zero, the compiler will act as if
2661 `STRICT_ALIGNMENT' were non-zero when generating code for block
2662 moves. This can cause significantly more instructions to be
2663 produced. Therefore, do not set this macro non-zero if unaligned
2664 accesses only add a cycle or two to the time for a memory access.
2666 If the value of this macro is always zero, it need not be defined. */
2668 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2670 /* Define this macro to inhibit strength reduction of memory
2671 addresses. (On some machines, such strength reduction seems to do
2672 harm rather than good.) */
2674 /* #define DONT_REDUCE_ADDR */
2676 /* Define this macro if it is as good or better to call a constant
2677 function address than to call an address kept in a register.
2679 Desirable on the 386 because a CALL with a constant address is
2680 faster than one with a register address. */
2682 #define NO_FUNCTION_CSE
2684 /* Define this macro if it is as good or better for a function to call
2685 itself with an explicit address than to call an address kept in a
2688 #define NO_RECURSIVE_FUNCTION_CSE
2690 /* Add any extra modes needed to represent the condition code.
2692 For the i386, we need separate modes when floating-point
2693 equality comparisons are being done.
2695 Add CCNO to indicate comparisons against zero that requires
2696 Overflow flag to be unset. Sign bit test is used instead and
2697 thus can be used to form "a&b>0" type of tests.
2699 Add CCGC to indicate comparisons agains zero that allows
2700 unspecified garbage in the Carry flag. This mode is used
2701 by inc/dec instructions.
2703 Add CCGOC to indicate comparisons agains zero that allows
2704 unspecified garbage in the Carry and Overflow flag. This
2705 mode is used to simulate comparisons of (a-b) and (a+b)
2706 against zero using sub/cmp/add operations.
2708 Add CCZ to indicate that only the Zero flag is valid. */
2710 #define EXTRA_CC_MODES \
2711 CC (CCGCmode, "CCGC") \
2712 CC (CCGOCmode, "CCGOC") \
2713 CC (CCNOmode, "CCNO") \
2714 CC (CCZmode, "CCZ") \
2715 CC (CCFPmode, "CCFP") \
2716 CC (CCFPUmode, "CCFPU")
2718 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2719 return the mode to be used for the comparison.
2721 For floating-point equality comparisons, CCFPEQmode should be used.
2722 VOIDmode should be used in all other cases.
2724 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2725 possible, to allow for more combinations. */
2727 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2729 /* Return non-zero if MODE implies a floating point inequality can be
2732 #define REVERSIBLE_CC_MODE(MODE) 1
2734 /* A C expression whose value is reversed condition code of the CODE for
2735 comparison done in CC_MODE mode. */
2736 #define REVERSE_CONDITION(CODE, MODE) \
2737 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2738 : reverse_condition_maybe_unordered (CODE))
2741 /* Control the assembler format that we output, to the extent
2742 this does not vary between assemblers. */
2744 /* How to refer to registers in assembler output.
2745 This sequence is indexed by compiler's hard-register-number (see above). */
2747 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2748 For non floating point regs, the following are the HImode names.
2750 For float regs, the stack top is sometimes referred to as "%st(0)"
2751 instead of just "%st". PRINT_REG handles this with the "y" code. */
2753 #undef HI_REGISTER_NAMES
2754 #define HI_REGISTER_NAMES \
2755 {"ax","dx","cx","bx","si","di","bp","sp", \
2756 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2757 "flags","fpsr", "dirflag", "frame", \
2758 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2759 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2760 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2761 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2763 #define REGISTER_NAMES HI_REGISTER_NAMES
2765 /* Table of additional register names to use in user input. */
2767 #define ADDITIONAL_REGISTER_NAMES \
2768 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2769 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2770 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2771 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2772 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2773 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2774 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2775 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2777 /* Note we are omitting these since currently I don't know how
2778 to get gcc to use these, since they want the same but different
2779 number as al, and ax.
2782 #define QI_REGISTER_NAMES \
2783 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2785 /* These parallel the array above, and can be used to access bits 8:15
2786 of regs 0 through 3. */
2788 #define QI_HIGH_REGISTER_NAMES \
2789 {"ah", "dh", "ch", "bh", }
2791 /* How to renumber registers for dbx and gdb. */
2793 #define DBX_REGISTER_NUMBER(N) \
2794 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2796 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2797 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2798 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2800 /* Before the prologue, RA is at 0(%esp). */
2801 #define INCOMING_RETURN_ADDR_RTX \
2802 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2804 /* After the prologue, RA is at -4(AP) in the current frame. */
2805 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2807 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2808 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2810 /* PC is dbx register 8; let's use that column for RA. */
2811 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2813 /* Before the prologue, the top of the frame is at 4(%esp). */
2814 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2816 /* Describe how we implement __builtin_eh_return. */
2817 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2818 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2821 /* Select a format to encode pointers in exception handling data. CODE
2822 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2823 true if the symbol may be affected by dynamic relocations.
2825 ??? All x86 object file formats are capable of representing this.
2826 After all, the relocation needed is the same as for the call insn.
2827 Whether or not a particular assembler allows us to enter such, I
2828 guess we'll have to see. */
2829 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2831 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2834 /* This is how to output the definition of a user-level label named NAME,
2835 such as the label on a static function or variable NAME. */
2837 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2838 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE)))
2840 /* Store in OUTPUT a string (made with alloca) containing
2841 an assembler-name for a local static variable named NAME.
2842 LABELNO is an integer which is different for each call. */
2844 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2845 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2846 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2848 /* This is how to output an insn to push a register on the stack.
2849 It need not be very fast code. */
2851 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2852 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)])
2854 /* This is how to output an insn to pop a register from the stack.
2855 It need not be very fast code. */
2857 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2858 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)])
2860 /* This is how to output an element of a case-vector that is absolute. */
2862 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2863 ix86_output_addr_vec_elt ((FILE), (VALUE))
2865 /* This is how to output an element of a case-vector that is relative. */
2867 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2868 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2870 /* Under some conditions we need jump tables in the text section, because
2871 the assembler cannot handle label differences between sections. */
2873 #define JUMP_TABLES_IN_TEXT_SECTION \
2874 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2876 /* A C statement that outputs an address constant appropriate to
2877 for DWARF debugging. */
2879 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
2880 i386_dwarf_output_addr_const ((FILE), (X))
2882 /* Either simplify a location expression, or return the original. */
2884 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2885 i386_simplify_dwarf_addr (X)
2887 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2888 and switch back. For x86 we do this only to save a few bytes that
2889 would otherwise be unused in the text section. */
2890 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2891 asm (SECTION_OP "\n\t" \
2892 "call " USER_LABEL_PREFIX #FUNC "\n" \
2893 TEXT_SECTION_ASM_OP);
2895 /* Print operand X (an rtx) in assembler syntax to file FILE.
2896 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2897 Effect of various CODE letters is described in i386.c near
2898 print_operand function. */
2900 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2901 ((CODE) == '*' || (CODE) == '+')
2903 /* Print the name of a register based on its machine mode and number.
2904 If CODE is 'w', pretend the mode is HImode.
2905 If CODE is 'b', pretend the mode is QImode.
2906 If CODE is 'k', pretend the mode is SImode.
2907 If CODE is 'q', pretend the mode is DImode.
2908 If CODE is 'h', pretend the reg is the `high' byte register.
2909 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2911 #define PRINT_REG(X, CODE, FILE) \
2912 print_reg ((X), (CODE), (FILE))
2914 #define PRINT_OPERAND(FILE, X, CODE) \
2915 print_operand ((FILE), (X), (CODE))
2917 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2918 print_operand_address ((FILE), (ADDR))
2920 /* Print the name of a register for based on its machine mode and number.
2921 This macro is used to print debugging output.
2922 This macro is different from PRINT_REG in that it may be used in
2923 programs that are not linked with aux-output.o. */
2925 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2926 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2927 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2928 fprintf ((FILE), "%d ", REGNO (X)); \
2929 if (REGNO (X) == FLAGS_REG) \
2930 { fputs ("flags", (FILE)); break; } \
2931 if (REGNO (X) == DIRFLAG_REG) \
2932 { fputs ("dirflag", (FILE)); break; } \
2933 if (REGNO (X) == FPSR_REG) \
2934 { fputs ("fpsr", (FILE)); break; } \
2935 if (REGNO (X) == ARG_POINTER_REGNUM) \
2936 { fputs ("argp", (FILE)); break; } \
2937 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2938 { fputs ("frame", (FILE)); break; } \
2939 if (STACK_TOP_P (X)) \
2940 { fputs ("st(0)", (FILE)); break; } \
2942 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
2943 if (REX_INT_REG_P (X)) \
2945 switch (GET_MODE_SIZE (GET_MODE (X))) \
2949 fprintf ((FILE), "r%i", REGNO (X) \
2950 - FIRST_REX_INT_REG + 8); \
2953 fprintf ((FILE), "r%id", REGNO (X) \
2954 - FIRST_REX_INT_REG + 8); \
2957 fprintf ((FILE), "r%iw", REGNO (X) \
2958 - FIRST_REX_INT_REG + 8); \
2961 fprintf ((FILE), "r%ib", REGNO (X) \
2962 - FIRST_REX_INT_REG + 8); \
2967 switch (GET_MODE_SIZE (GET_MODE (X))) \
2970 fputs ("r", (FILE)); \
2971 fputs (hi_name[REGNO (X)], (FILE)); \
2974 fputs ("e", (FILE)); \
2976 fputs (hi_name[REGNO (X)], (FILE)); \
2979 fputs (qi_name[REGNO (X)], (FILE)); \
2984 /* a letter which is not needed by the normal asm syntax, which
2985 we can use for operand syntax in the extended asm */
2987 #define ASM_OPERAND_LETTER '#'
2988 #define RET return ""
2989 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2991 /* Define the codes that are matched by predicates in i386.c. */
2993 #define PREDICATE_CODES \
2994 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
2995 SYMBOL_REF, LABEL_REF, CONST}}, \
2996 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
2997 SYMBOL_REF, LABEL_REF, CONST}}, \
2998 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
2999 SYMBOL_REF, LABEL_REF, CONST}}, \
3000 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3001 SYMBOL_REF, LABEL_REF, CONST}}, \
3002 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3003 SYMBOL_REF, LABEL_REF, CONST}}, \
3004 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3005 SYMBOL_REF, LABEL_REF, CONST}}, \
3006 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3007 SYMBOL_REF, LABEL_REF}}, \
3008 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3009 {"const_int_1_operand", {CONST_INT}}, \
3010 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3011 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3012 LABEL_REF, SUBREG, REG, MEM}}, \
3013 {"pic_symbolic_operand", {CONST}}, \
3014 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3015 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3016 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3017 {"const1_operand", {CONST_INT}}, \
3018 {"const248_operand", {CONST_INT}}, \
3019 {"incdec_operand", {CONST_INT}}, \
3020 {"mmx_reg_operand", {REG}}, \
3021 {"reg_no_sp_operand", {SUBREG, REG}}, \
3022 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3023 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3024 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3025 {"q_regs_operand", {SUBREG, REG}}, \
3026 {"non_q_regs_operand", {SUBREG, REG}}, \
3027 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3028 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3029 GE, UNGE, LTGT, UNEQ}}, \
3030 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3031 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3033 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3034 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3035 UNGE, UNGT, LTGT, UNEQ }}, \
3036 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3037 {"ext_register_operand", {SUBREG, REG}}, \
3038 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3039 {"mult_operator", {MULT}}, \
3040 {"div_operator", {DIV}}, \
3041 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3042 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3043 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3044 LSHIFTRT, ROTATERT}}, \
3045 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3046 {"memory_displacement_operand", {MEM}}, \
3047 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3048 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3049 {"long_memory_operand", {MEM}},
3051 /* A list of predicates that do special things with modes, and so
3052 should not elicit warnings for VOIDmode match_operand. */
3054 #define SPECIAL_MODE_PREDICATES \
3055 "ext_register_operand",
3057 /* CM_32 is used by 32bit ABI
3058 CM_SMALL is small model assuming that all code and data fits in the first
3059 31bits of address space.
3060 CM_KERNEL is model assuming that all code and data fits in the negative
3061 31bits of address space.
3062 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3063 space. Size of data is unlimited.
3064 CM_LARGE is model making no assumptions about size of particular sections.
3066 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3067 tables first in 31bits of address space.
3078 /* Size of the RED_ZONE area. */
3079 #define RED_ZONE_SIZE 128
3080 /* Reserved area of the red zone for temporaries. */
3081 #define RED_ZONE_RESERVE 8
3082 extern const char *ix86_debug_arg_string, *ix86_debug_addr_string;
3088 extern const char *ix86_asm_string;
3089 extern enum asm_dialect ix86_asm_dialect;
3090 /* Value of -mcmodel specified by user. */
3091 extern const char *ix86_cmodel_string;
3092 extern enum cmodel ix86_cmodel;
3094 /* Variables in i386.c */
3095 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3096 extern const char *ix86_arch_string; /* for -march=<xxx> */
3097 extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
3098 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3099 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3100 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3101 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3102 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3103 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3104 extern int ix86_regparm; /* ix86_regparm_string as a number */
3105 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3106 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3107 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */
3108 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3109 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3111 /* To properly truncate FP values into integers, we need to set i387 control
3112 word. We can't emit proper mode switching code before reload, as spills
3113 generated by reload may truncate values incorrectly, but we still can avoid
3114 redundant computation of new control word by the mode switching pass.
3115 The fldcw instructions are still emitted redundantly, but this is probably
3116 not going to be noticeable problem, as most CPUs do have fast path for
3119 The machinery is to emit simple truncation instructions and split them
3120 before reload to instructions having USEs of two memory locations that
3121 are filled by this code to old and new control word.
3123 Post-reload pass may be later used to eliminate the redundant fildcw if
3126 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3128 /* Define this macro if the port needs extra instructions inserted
3129 for mode switching in an optimizing compilation. */
3131 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3133 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3134 initializer for an array of integers. Each initializer element N
3135 refers to an entity that needs mode switching, and specifies the
3136 number of different modes that might need to be set for this
3137 entity. The position of the initializer in the initializer -
3138 starting counting at zero - determines the integer that is used to
3139 refer to the mode-switched entity in question. */
3141 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3143 /* ENTITY is an integer specifying a mode-switched entity. If
3144 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3145 return an integer value not larger than the corresponding element
3146 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3147 must be switched into prior to the execution of INSN. */
3149 #define MODE_NEEDED(ENTITY, I) \
3150 (GET_CODE (I) == CALL_INSN \
3151 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3152 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3153 ? FP_CW_UNINITIALIZED \
3154 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3158 /* This macro specifies the order in which modes for ENTITY are
3159 processed. 0 is the highest priority. */
3161 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3163 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3164 is the set of hard registers live at the point where the insn(s)
3165 are to be inserted. */
3167 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3168 ((MODE) == FP_CW_STORED \
3169 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3170 assign_386_stack_local (HImode, 2)), 0\
3173 /* Avoid renaming of stack registers, as doing so in combination with
3174 scheduling just increases amount of live registers at time and in
3175 the turn amount of fxch instructions needed.
3177 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3179 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3180 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
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