1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Redefines for option macros. */
39 #define TARGET_64BIT OPTION_ISA_64BIT
40 #define TARGET_MMX OPTION_ISA_MMX
41 #define TARGET_3DNOW OPTION_ISA_3DNOW
42 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
43 #define TARGET_SSE OPTION_ISA_SSE
44 #define TARGET_SSE2 OPTION_ISA_SSE2
45 #define TARGET_SSE3 OPTION_ISA_SSE3
46 #define TARGET_SSSE3 OPTION_ISA_SSSE3
47 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1
48 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2
49 #define TARGET_AVX OPTION_ISA_AVX
50 #define TARGET_FMA OPTION_ISA_FMA
51 #define TARGET_SSE4A OPTION_ISA_SSE4A
52 #define TARGET_SSE5 OPTION_ISA_SSE5
53 #define TARGET_ROUND OPTION_ISA_ROUND
54 #define TARGET_ABM OPTION_ISA_ABM
55 #define TARGET_POPCNT OPTION_ISA_POPCNT
56 #define TARGET_SAHF OPTION_ISA_SAHF
57 #define TARGET_AES OPTION_ISA_AES
58 #define TARGET_PCLMUL OPTION_ISA_PCLMUL
59 #define TARGET_CMPXCHG16B OPTION_ISA_CX16
62 /* SSE5 and SSE4.1 define the same round instructions */
63 #define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE5)
64 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
66 #include "config/vxworks-dummy.h"
68 /* Algorithm to expand string function with. */
81 #define NAX_STRINGOP_ALGS 4
83 /* Specify what algorithm to use for stringops on known size.
84 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
85 known at compile time or estimated via feedback, the SIZE array
86 is walked in order until MAX is greater then the estimate (or -1
87 means infinity). Corresponding ALG is used then.
88 For example initializer:
89 {{256, loop}, {-1, rep_prefix_4_byte}}
90 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
94 const enum stringop_alg unknown_size;
95 const struct stringop_strategy {
97 const enum stringop_alg alg;
98 } size [NAX_STRINGOP_ALGS];
101 /* Define the specific costs for a given cpu */
103 struct processor_costs {
104 const int add; /* cost of an add instruction */
105 const int lea; /* cost of a lea instruction */
106 const int shift_var; /* variable shift costs */
107 const int shift_const; /* constant shift costs */
108 const int mult_init[5]; /* cost of starting a multiply
109 in QImode, HImode, SImode, DImode, TImode*/
110 const int mult_bit; /* cost of multiply per each bit set */
111 const int divide[5]; /* cost of a divide/mod
112 in QImode, HImode, SImode, DImode, TImode*/
113 int movsx; /* The cost of movsx operation. */
114 int movzx; /* The cost of movzx operation. */
115 const int large_insn; /* insns larger than this cost more */
116 const int move_ratio; /* The threshold of number of scalar
117 memory-to-memory move insns. */
118 const int movzbl_load; /* cost of loading using movzbl */
119 const int int_load[3]; /* cost of loading integer registers
120 in QImode, HImode and SImode relative
121 to reg-reg move (2). */
122 const int int_store[3]; /* cost of storing integer register
123 in QImode, HImode and SImode */
124 const int fp_move; /* cost of reg,reg fld/fst */
125 const int fp_load[3]; /* cost of loading FP register
126 in SFmode, DFmode and XFmode */
127 const int fp_store[3]; /* cost of storing FP register
128 in SFmode, DFmode and XFmode */
129 const int mmx_move; /* cost of moving MMX register. */
130 const int mmx_load[2]; /* cost of loading MMX register
131 in SImode and DImode */
132 const int mmx_store[2]; /* cost of storing MMX register
133 in SImode and DImode */
134 const int sse_move; /* cost of moving SSE register. */
135 const int sse_load[3]; /* cost of loading SSE register
136 in SImode, DImode and TImode*/
137 const int sse_store[3]; /* cost of storing SSE register
138 in SImode, DImode and TImode*/
139 const int mmxsse_to_integer; /* cost of moving mmxsse register to
140 integer and vice versa. */
141 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
142 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
143 const int prefetch_block; /* bytes moved to cache for prefetch. */
144 const int simultaneous_prefetches; /* number of parallel prefetch
146 const int branch_cost; /* Default value for BRANCH_COST. */
147 const int fadd; /* cost of FADD and FSUB instructions. */
148 const int fmul; /* cost of FMUL instruction. */
149 const int fdiv; /* cost of FDIV instruction. */
150 const int fabs; /* cost of FABS instruction. */
151 const int fchs; /* cost of FCHS instruction. */
152 const int fsqrt; /* cost of FSQRT instruction. */
153 /* Specify what algorithm
154 to use for stringops on unknown size. */
155 struct stringop_algs memcpy[2], memset[2];
156 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
158 const int scalar_load_cost; /* Cost of scalar load. */
159 const int scalar_store_cost; /* Cost of scalar store. */
160 const int vec_stmt_cost; /* Cost of any vector operation, excluding
161 load, store, vector-to-scalar and
162 scalar-to-vector operation. */
163 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
164 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
165 const int vec_align_load_cost; /* Cost of aligned vector load. */
166 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
167 const int vec_store_cost; /* Cost of vector store. */
168 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
170 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
171 vectorizer cost model. */
174 extern const struct processor_costs *ix86_cost;
175 extern const struct processor_costs ix86_size_cost;
177 #define ix86_cur_cost() \
178 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)
180 /* Macros used in the machine description to test the flags. */
182 /* configure can arrange to make this 2, to force a 486. */
184 #ifndef TARGET_CPU_DEFAULT
185 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
188 #ifndef TARGET_FPMATH_DEFAULT
189 #define TARGET_FPMATH_DEFAULT \
190 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
193 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
195 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
196 compile-time constant. */
200 #define TARGET_64BIT 1
202 #define TARGET_64BIT 0
205 #ifndef TARGET_BI_ARCH
207 #if TARGET_64BIT_DEFAULT
208 #define TARGET_64BIT 1
210 #define TARGET_64BIT 0
215 #define HAS_LONG_COND_BRANCH 1
216 #define HAS_LONG_UNCOND_BRANCH 1
218 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
219 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
220 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
221 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
222 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
223 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
224 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
225 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
226 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
227 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
228 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
229 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
230 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
231 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
232 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
233 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
235 /* Feature tests against the various tunings. */
236 enum ix86_tune_indices {
238 X86_TUNE_PUSH_MEMORY,
239 X86_TUNE_ZERO_EXTEND_WITH_AND,
240 X86_TUNE_UNROLL_STRLEN,
241 X86_TUNE_DEEP_BRANCH_PREDICTION,
242 X86_TUNE_BRANCH_PREDICTION_HINTS,
243 X86_TUNE_DOUBLE_WITH_ADD,
246 X86_TUNE_PARTIAL_REG_STALL,
247 X86_TUNE_PARTIAL_FLAG_REG_STALL,
248 X86_TUNE_USE_HIMODE_FIOP,
249 X86_TUNE_USE_SIMODE_FIOP,
253 X86_TUNE_SPLIT_LONG_MOVES,
254 X86_TUNE_READ_MODIFY_WRITE,
255 X86_TUNE_READ_MODIFY,
256 X86_TUNE_PROMOTE_QIMODE,
257 X86_TUNE_FAST_PREFIX,
258 X86_TUNE_SINGLE_STRINGOP,
259 X86_TUNE_QIMODE_MATH,
260 X86_TUNE_HIMODE_MATH,
261 X86_TUNE_PROMOTE_QI_REGS,
262 X86_TUNE_PROMOTE_HI_REGS,
267 X86_TUNE_INTEGER_DFMODE_MOVES,
268 X86_TUNE_PARTIAL_REG_DEPENDENCY,
269 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
270 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
271 X86_TUNE_SSE_SPLIT_REGS,
272 X86_TUNE_SSE_TYPELESS_STORES,
273 X86_TUNE_SSE_LOAD0_BY_PXOR,
274 X86_TUNE_MEMORY_MISMATCH_STALL,
275 X86_TUNE_PROLOGUE_USING_MOVE,
276 X86_TUNE_EPILOGUE_USING_MOVE,
279 X86_TUNE_INTER_UNIT_MOVES,
280 X86_TUNE_INTER_UNIT_CONVERSIONS,
281 X86_TUNE_FOUR_JUMP_LIMIT,
285 X86_TUNE_PAD_RETURNS,
286 X86_TUNE_EXT_80387_CONSTANTS,
287 X86_TUNE_SHORTEN_X87_SSE,
288 X86_TUNE_AVOID_VECTOR_DECODE,
289 X86_TUNE_PROMOTE_HIMODE_IMUL,
290 X86_TUNE_SLOW_IMUL_IMM32_MEM,
291 X86_TUNE_SLOW_IMUL_IMM8,
292 X86_TUNE_MOVE_M1_VIA_OR,
293 X86_TUNE_NOT_UNPAIRABLE,
294 X86_TUNE_NOT_VECTORMODE,
295 X86_TUNE_USE_VECTOR_FP_CONVERTS,
296 X86_TUNE_USE_VECTOR_CONVERTS,
297 X86_TUNE_FUSE_CMP_AND_BRANCH,
302 extern unsigned char ix86_tune_features[X86_TUNE_LAST];
304 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
305 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
306 #define TARGET_ZERO_EXTEND_WITH_AND \
307 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
308 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
309 #define TARGET_DEEP_BRANCH_PREDICTION \
310 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
311 #define TARGET_BRANCH_PREDICTION_HINTS \
312 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
313 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
314 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
315 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
316 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
317 #define TARGET_PARTIAL_FLAG_REG_STALL \
318 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
319 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
320 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
321 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
322 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
323 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
324 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
325 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
326 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
327 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
328 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
329 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
330 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
331 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
332 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
333 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
334 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4]
335 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8]
336 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4]
337 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8]
338 #define TARGET_INTEGER_DFMODE_MOVES \
339 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
340 #define TARGET_PARTIAL_REG_DEPENDENCY \
341 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
342 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
343 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
344 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
345 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
346 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
347 #define TARGET_SSE_TYPELESS_STORES \
348 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
349 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
350 #define TARGET_MEMORY_MISMATCH_STALL \
351 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
352 #define TARGET_PROLOGUE_USING_MOVE \
353 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
354 #define TARGET_EPILOGUE_USING_MOVE \
355 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
356 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
357 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
358 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
359 #define TARGET_INTER_UNIT_CONVERSIONS\
360 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
361 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
362 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
363 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
364 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
365 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
366 #define TARGET_EXT_80387_CONSTANTS \
367 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
368 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
369 #define TARGET_AVOID_VECTOR_DECODE \
370 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
371 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
372 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
373 #define TARGET_SLOW_IMUL_IMM32_MEM \
374 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
375 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
376 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
377 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
378 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
379 #define TARGET_USE_VECTOR_FP_CONVERTS \
380 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]
381 #define TARGET_USE_VECTOR_CONVERTS \
382 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
383 #define TARGET_FUSE_CMP_AND_BRANCH \
384 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
386 /* Feature tests against the various architecture variations. */
387 enum ix86_arch_indices {
388 X86_ARCH_CMOVE, /* || TARGET_SSE */
397 extern unsigned char ix86_arch_features[X86_ARCH_LAST];
399 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
400 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
401 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
402 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
403 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
405 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
407 extern int x86_prefetch_sse;
409 #define TARGET_PREFETCH_SSE x86_prefetch_sse
411 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
413 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
414 #define TARGET_MIX_SSE_I387 \
415 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
417 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
418 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
419 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
420 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
422 extern int ix86_isa_flags;
424 #ifndef TARGET_64BIT_DEFAULT
425 #define TARGET_64BIT_DEFAULT 0
427 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
428 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
431 /* Fence to use after loop using storent. */
433 extern tree x86_mfence;
434 #define FENCE_FOLLOWING_MOVNT x86_mfence
436 /* Once GDB has been enhanced to deal with functions without frame
437 pointers, we can change this to allow for elimination of
438 the frame pointer in leaf functions. */
439 #define TARGET_DEFAULT 0
441 /* Extra bits to force. */
442 #define TARGET_SUBTARGET_DEFAULT 0
443 #define TARGET_SUBTARGET_ISA_DEFAULT 0
445 /* Extra bits to force on w/ 32-bit mode. */
446 #define TARGET_SUBTARGET32_DEFAULT 0
447 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
449 /* Extra bits to force on w/ 64-bit mode. */
450 #define TARGET_SUBTARGET64_DEFAULT 0
451 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
453 /* This is not really a target flag, but is done this way so that
454 it's analogous to similar code for Mach-O on PowerPC. darwin.h
455 redefines this to 1. */
456 #define TARGET_MACHO 0
458 /* Likewise, for the Windows 64-bit ABI. */
459 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
461 /* Available call abi. */
468 /* The default abi form used by target. */
469 #define DEFAULT_ABI SYSV_ABI
471 /* Subtargets may reset this to 1 in order to enable 96-bit long double
472 with the rounding mode forced to 53 bits. */
473 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
475 /* Sometimes certain combinations of command options do not make
476 sense on a particular target machine. You can define a macro
477 `OVERRIDE_OPTIONS' to take account of this. This macro, if
478 defined, is executed once just after all the command options have
481 Don't use this macro to turn on various extra optimizations for
482 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
484 #define OVERRIDE_OPTIONS override_options (true)
486 /* Define this to change the optimizations performed by default. */
487 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
488 optimization_options ((LEVEL), (SIZE))
490 /* -march=native handling only makes sense with compiler running on
491 an x86 or x86_64 chip. If changing this condition, also change
492 the condition in driver-i386.c. */
493 #if defined(__i386__) || defined(__x86_64__)
494 /* In driver-i386.c. */
495 extern const char *host_detect_local_cpu (int argc, const char **argv);
496 #define EXTRA_SPEC_FUNCTIONS \
497 { "local_cpu_detect", host_detect_local_cpu },
498 #define HAVE_LOCAL_CPU_DETECT
501 #if TARGET_64BIT_DEFAULT
502 #define OPT_ARCH64 "!m32"
503 #define OPT_ARCH32 "m32"
505 #define OPT_ARCH64 "m64"
506 #define OPT_ARCH32 "!m64"
509 /* Support for configure-time defaults of some command line options.
510 The order here is important so that -march doesn't squash the
511 tune or cpu values. */
512 #define OPTION_DEFAULT_SPECS \
513 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
514 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
515 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
516 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
517 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
518 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \
519 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
520 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \
521 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},
523 /* Specs for the compiler proper */
526 #define CC1_CPU_SPEC_1 "\
528 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \
530 %{mintel-syntax:-masm=intel \
531 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
532 %{mno-intel-syntax:-masm=att \
533 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
535 #ifndef HAVE_LOCAL_CPU_DETECT
536 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
538 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
539 "%{march=native:%<march=native %:local_cpu_detect(arch) \
540 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
541 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
545 /* Target CPU builtins. */
546 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
548 /* Target Pragmas. */
549 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
551 enum target_cpu_default
553 TARGET_CPU_DEFAULT_generic = 0,
555 TARGET_CPU_DEFAULT_i386,
556 TARGET_CPU_DEFAULT_i486,
557 TARGET_CPU_DEFAULT_pentium,
558 TARGET_CPU_DEFAULT_pentium_mmx,
559 TARGET_CPU_DEFAULT_pentiumpro,
560 TARGET_CPU_DEFAULT_pentium2,
561 TARGET_CPU_DEFAULT_pentium3,
562 TARGET_CPU_DEFAULT_pentium4,
563 TARGET_CPU_DEFAULT_pentium_m,
564 TARGET_CPU_DEFAULT_prescott,
565 TARGET_CPU_DEFAULT_nocona,
566 TARGET_CPU_DEFAULT_core2,
568 TARGET_CPU_DEFAULT_geode,
569 TARGET_CPU_DEFAULT_k6,
570 TARGET_CPU_DEFAULT_k6_2,
571 TARGET_CPU_DEFAULT_k6_3,
572 TARGET_CPU_DEFAULT_athlon,
573 TARGET_CPU_DEFAULT_athlon_sse,
574 TARGET_CPU_DEFAULT_k8,
575 TARGET_CPU_DEFAULT_amdfam10,
577 TARGET_CPU_DEFAULT_max
581 #define CC1_SPEC "%(cc1_cpu) "
584 /* This macro defines names of additional specifications to put in the
585 specs that can be used in various specifications like CC1_SPEC. Its
586 definition is an initializer with a subgrouping for each command option.
588 Each subgrouping contains a string constant, that defines the
589 specification name, and a string constant that used by the GCC driver
592 Do not define this macro if it does not need to do anything. */
594 #ifndef SUBTARGET_EXTRA_SPECS
595 #define SUBTARGET_EXTRA_SPECS
598 #define EXTRA_SPECS \
599 { "cc1_cpu", CC1_CPU_SPEC }, \
600 SUBTARGET_EXTRA_SPECS
603 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
604 FPU, assume that the fpcw is set to extended precision; when using
605 only SSE, rounding is correct; when using both SSE and the FPU,
606 the rounding precision is indeterminate, since either may be chosen
607 apparently at random. */
608 #define TARGET_FLT_EVAL_METHOD \
609 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
611 /* target machine storage layout */
613 #define SHORT_TYPE_SIZE 16
614 #define INT_TYPE_SIZE 32
615 #define FLOAT_TYPE_SIZE 32
616 #define LONG_TYPE_SIZE BITS_PER_WORD
617 #define DOUBLE_TYPE_SIZE 64
618 #define LONG_LONG_TYPE_SIZE 64
619 #define LONG_DOUBLE_TYPE_SIZE 80
621 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE
623 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
624 #define MAX_BITS_PER_WORD 64
626 #define MAX_BITS_PER_WORD 32
629 /* Define this if most significant byte of a word is the lowest numbered. */
630 /* That is true on the 80386. */
632 #define BITS_BIG_ENDIAN 0
634 /* Define this if most significant byte of a word is the lowest numbered. */
635 /* That is not true on the 80386. */
636 #define BYTES_BIG_ENDIAN 0
638 /* Define this if most significant word of a multiword number is the lowest
640 /* Not true for 80386 */
641 #define WORDS_BIG_ENDIAN 0
643 /* Width of a word, in units (bytes). */
644 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
646 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
648 #define MIN_UNITS_PER_WORD 4
651 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
652 #define PARM_BOUNDARY BITS_PER_WORD
654 /* Boundary (in *bits*) on which stack pointer should be aligned. */
655 #define STACK_BOUNDARY \
656 (TARGET_64BIT && DEFAULT_ABI == MS_ABI ? 128 : BITS_PER_WORD)
658 /* Stack boundary of the main function guaranteed by OS. */
659 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
661 /* Minimum stack boundary. */
662 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
664 /* Boundary (in *bits*) on which the stack pointer prefers to be
665 aligned; the compiler cannot rely on having this alignment. */
666 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
668 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for
669 both 32bit and 64bit, to support codes that need 128 bit stack
670 alignment for SSE instructions, but can't realign the stack. */
671 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128
673 /* 1 if -mstackrealign should be turned on by default. It will
674 generate an alternate prologue and epilogue that realigns the
675 runtime stack if nessary. This supports mixing codes that keep a
676 4-byte aligned stack, as specified by i386 psABI, with codes that
677 need a 16-byte aligned stack, as required by SSE instructions. If
678 STACK_REALIGN_DEFAULT is 1 and PREFERRED_STACK_BOUNDARY_DEFAULT is
679 128, stacks for all functions may be realigned. */
680 #define STACK_REALIGN_DEFAULT 0
682 /* Boundary (in *bits*) on which the incoming stack is aligned. */
683 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary
685 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
686 mandatory for the 64-bit ABI, and may or may not be true for other
687 operating systems. */
688 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
690 /* Minimum allocation boundary for the code of a function. */
691 #define FUNCTION_BOUNDARY 8
693 /* C++ stores the virtual bit in the lowest bit of function pointers. */
694 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
696 /* Alignment of field after `int : 0' in a structure. */
698 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
700 /* Minimum size in bits of the largest boundary to which any
701 and all fundamental data types supported by the hardware
702 might need to be aligned. No data type wants to be aligned
705 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
706 and Pentium Pro XFmode values at 128 bit boundaries. */
708 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256: 128)
710 /* Maximum stack alignment. */
711 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT
713 /* Alignment value for attribute ((aligned)). It is a constant since
714 it is the part of the ABI. We shouldn't change it with -mavx. */
715 #define ATTRIBUTE_ALIGNED_VALUE 128
717 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
718 #define ALIGN_MODE_128(MODE) \
719 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
721 /* The published ABIs say that doubles should be aligned on word
722 boundaries, so lower the alignment for structure fields unless
723 -malign-double is set. */
725 /* ??? Blah -- this macro is used directly by libobjc. Since it
726 supports no vector modes, cut out the complexity and fall back
727 on BIGGEST_FIELD_ALIGNMENT. */
728 #ifdef IN_TARGET_LIBS
730 #define BIGGEST_FIELD_ALIGNMENT 128
732 #define BIGGEST_FIELD_ALIGNMENT 32
735 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
736 x86_field_alignment (FIELD, COMPUTED)
739 /* If defined, a C expression to compute the alignment given to a
740 constant that is being placed in memory. EXP is the constant
741 and ALIGN is the alignment that the object would ordinarily have.
742 The value of this macro is used instead of that alignment to align
745 If this macro is not defined, then ALIGN is used.
747 The typical use of this macro is to increase alignment for string
748 constants to be word aligned so that `strcpy' calls that copy
749 constants can be done inline. */
751 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
753 /* If defined, a C expression to compute the alignment for a static
754 variable. TYPE is the data type, and ALIGN is the alignment that
755 the object would ordinarily have. The value of this macro is used
756 instead of that alignment to align the object.
758 If this macro is not defined, then ALIGN is used.
760 One use of this macro is to increase alignment of medium-size
761 data to make it all fit in fewer cache lines. Another is to
762 cause character arrays to be word-aligned so that `strcpy' calls
763 that copy constants to character arrays can be done inline. */
765 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
767 /* If defined, a C expression to compute the alignment for a local
768 variable. TYPE is the data type, and ALIGN is the alignment that
769 the object would ordinarily have. The value of this macro is used
770 instead of that alignment to align the object.
772 If this macro is not defined, then ALIGN is used.
774 One use of this macro is to increase alignment of medium-size
775 data to make it all fit in fewer cache lines. */
777 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
778 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
780 /* If defined, a C expression to compute the alignment for stack slot.
781 TYPE is the data type, MODE is the widest mode available, and ALIGN
782 is the alignment that the slot would ordinarily have. The value of
783 this macro is used instead of that alignment to align the slot.
785 If this macro is not defined, then ALIGN is used when TYPE is NULL,
786 Otherwise, LOCAL_ALIGNMENT will be used.
788 One use of this macro is to set alignment of stack slot to the
789 maximum alignment of all possible modes which the slot may have. */
791 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
792 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
794 /* If defined, a C expression that gives the alignment boundary, in
795 bits, of an argument with the specified mode and type. If it is
796 not defined, `PARM_BOUNDARY' is used for all arguments. */
798 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
799 ix86_function_arg_boundary ((MODE), (TYPE))
801 /* Set this nonzero if move instructions will actually fail to work
802 when given unaligned data. */
803 #define STRICT_ALIGNMENT 0
805 /* If bit field type is int, don't let it cross an int,
806 and give entire struct the alignment of an int. */
807 /* Required on the 386 since it doesn't have bit-field insns. */
808 #define PCC_BITFIELD_TYPE_MATTERS 1
810 /* Standard register usage. */
812 /* This processor has special stack-like registers. See reg-stack.c
817 #define IS_STACK_MODE(MODE) \
818 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
819 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
822 /* Number of actual hardware registers.
823 The hardware registers are assigned numbers for the compiler
824 from 0 to just below FIRST_PSEUDO_REGISTER.
825 All registers that the compiler knows about must be given numbers,
826 even those that are not normally considered general registers.
828 In the 80386 we give the 8 general purpose registers the numbers 0-7.
829 We number the floating point registers 8-15.
830 Note that registers 0-7 can be accessed as a short or int,
831 while only 0-3 may be used with byte `mov' instructions.
833 Reg 16 does not correspond to any hardware register, but instead
834 appears in the RTL as an argument pointer prior to reload, and is
835 eliminated during reloading in favor of either the stack or frame
838 #define FIRST_PSEUDO_REGISTER 53
840 /* Number of hardware registers that go into the DWARF-2 unwind info.
841 If not defined, equals FIRST_PSEUDO_REGISTER. */
843 #define DWARF_FRAME_REGISTERS 17
845 /* 1 for registers that have pervasive standard uses
846 and are not available for the register allocator.
847 On the 80386, the stack pointer is such, as is the arg pointer.
849 The value is zero if the register is not fixed on either 32 or
850 64 bit targets, one if the register if fixed on both 32 and 64
851 bit targets, two if it is only fixed on 32bit targets and three
852 if its only fixed on 64bit targets.
853 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
855 #define FIXED_REGISTERS \
856 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
857 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
858 /*arg,flags,fpsr,fpcr,frame*/ \
860 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
861 0, 0, 0, 0, 0, 0, 0, 0, \
862 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
863 0, 0, 0, 0, 0, 0, 0, 0, \
864 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
865 2, 2, 2, 2, 2, 2, 2, 2, \
866 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
867 2, 2, 2, 2, 2, 2, 2, 2 }
870 /* 1 for registers not available across function calls.
871 These must include the FIXED_REGISTERS and also any
872 registers that can be used without being saved.
873 The latter must include the registers where values are returned
874 and the register where structure-value addresses are passed.
875 Aside from that, you can include as many other registers as you like.
877 The value is zero if the register is not call used on either 32 or
878 64 bit targets, one if the register if call used on both 32 and 64
879 bit targets, two if it is only call used on 32bit targets and three
880 if its only call used on 64bit targets.
881 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
883 #define CALL_USED_REGISTERS \
884 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
885 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
886 /*arg,flags,fpsr,fpcr,frame*/ \
888 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
889 1, 1, 1, 1, 1, 1, 1, 1, \
890 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
891 1, 1, 1, 1, 1, 1, 1, 1, \
892 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
893 1, 1, 1, 1, 2, 2, 2, 2, \
894 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
895 1, 1, 1, 1, 1, 1, 1, 1 }
897 /* Order in which to allocate registers. Each register must be
898 listed once, even those in FIXED_REGISTERS. List frame pointer
899 late and fixed registers last. Note that, in general, we prefer
900 registers listed in CALL_USED_REGISTERS, keeping the others
901 available for storage of persistent values.
903 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
904 so this is just empty initializer for array. */
906 #define REG_ALLOC_ORDER \
907 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
908 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
909 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
912 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
913 to be rearranged based on a particular function. When using sse math,
914 we want to allocate SSE before x87 registers and vice versa. */
916 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
919 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
921 /* Macro to conditionally modify fixed_regs/call_used_regs. */
922 #define CONDITIONAL_REGISTER_USAGE \
926 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
928 if (fixed_regs[i] > 1) \
929 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
930 if (call_used_regs[i] > 1) \
931 call_used_regs[i] = (call_used_regs[i] \
932 == (TARGET_64BIT ? 3 : 2)); \
934 j = PIC_OFFSET_TABLE_REGNUM; \
935 if (j != INVALID_REGNUM) \
937 fixed_regs[j] = call_used_regs[j] = 1; \
940 && ((cfun && cfun->machine->call_abi == MS_ABI) \
941 || (!cfun && DEFAULT_ABI == MS_ABI))) \
943 call_used_regs[4 /*RSI*/] = 0; \
944 call_used_regs[5 /*RDI*/] = 0; \
945 for (i = 0; i < 8; i++) \
946 call_used_regs[45+i] = 0; \
947 call_used_regs[27 /*XMM6*/] = 0; \
948 call_used_regs[28 /*XMM7*/] = 0; \
951 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
952 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
953 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
955 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
956 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
957 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
958 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387)) \
961 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
962 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
963 if (TEST_HARD_REG_BIT (x, i)) \
964 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
966 if (! TARGET_64BIT) \
968 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
970 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
975 /* Return number of consecutive hard regs needed starting at reg REGNO
976 to hold something of mode MODE.
977 This is ordinarily the length in words of a value of mode MODE
978 but can be less for certain modes in special long registers.
980 Actually there are no two word move instructions for consecutive
981 registers. And only registers 0-3 may have mov byte instructions
985 #define HARD_REGNO_NREGS(REGNO, MODE) \
986 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
987 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
988 : ((MODE) == XFmode \
989 ? (TARGET_64BIT ? 2 : 3) \
991 ? (TARGET_64BIT ? 4 : 6) \
992 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
994 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
995 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
996 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
998 : ((MODE) == XFmode || (MODE) == XCmode)) \
1001 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1003 #define VALID_AVX256_REG_MODE(MODE) \
1004 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \
1005 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)
1007 #define VALID_SSE2_REG_MODE(MODE) \
1008 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1009 || (MODE) == V2DImode || (MODE) == DFmode)
1011 #define VALID_SSE_REG_MODE(MODE) \
1012 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1013 || (MODE) == SFmode || (MODE) == TFmode)
1015 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1016 ((MODE) == V2SFmode || (MODE) == SFmode)
1018 #define VALID_MMX_REG_MODE(MODE) \
1019 ((MODE == V1DImode) || (MODE) == DImode \
1020 || (MODE) == V2SImode || (MODE) == SImode \
1021 || (MODE) == V4HImode || (MODE) == V8QImode)
1023 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
1024 place emms and femms instructions.
1025 FIXME: AVX has 32byte floating point vector operations and 16byte
1026 integer vector operations. But vectorizer doesn't support
1027 different sizes for integer and floating point vectors. We limit
1028 vector size to 16byte. */
1029 #define UNITS_PER_SIMD_WORD(MODE) \
1030 (TARGET_AVX ? (((MODE) == DFmode || (MODE) == SFmode) ? 16 : 16) \
1031 : (TARGET_SSE ? 16 : UNITS_PER_WORD))
1033 #define VALID_DFP_MODE_P(MODE) \
1034 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1036 #define VALID_FP_MODE_P(MODE) \
1037 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1038 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1040 #define VALID_INT_MODE_P(MODE) \
1041 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1042 || (MODE) == DImode \
1043 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1044 || (MODE) == CDImode \
1045 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1046 || (MODE) == TFmode || (MODE) == TCmode)))
1048 /* Return true for modes passed in SSE registers. */
1049 #define SSE_REG_MODE_P(MODE) \
1050 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1051 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1052 || (MODE) == V4SFmode || (MODE) == V4SImode || (MODE) == V32QImode \
1053 || (MODE) == V16HImode || (MODE) == V8SImode || (MODE) == V4DImode \
1054 || (MODE) == V8SFmode || (MODE) == V4DFmode)
1056 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1058 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1059 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1061 /* Value is 1 if it is a good idea to tie two pseudo registers
1062 when one has mode MODE1 and one has mode MODE2.
1063 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1064 for any hard reg, then this must be 0 for correct output. */
1066 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1068 /* It is possible to write patterns to move flags; but until someone
1070 #define AVOID_CCMODE_COPIES
1072 /* Specify the modes required to caller save a given hard regno.
1073 We do this on i386 to prevent flags from being saved at all.
1075 Kill any attempts to combine saving of modes. */
1077 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1078 (CC_REGNO_P (REGNO) ? VOIDmode \
1079 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1080 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1081 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1082 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1085 /* Specify the registers used for certain standard purposes.
1086 The values of these macros are register numbers. */
1088 /* on the 386 the pc register is %eip, and is not usable as a general
1089 register. The ordinary mov instructions won't work */
1090 /* #define PC_REGNUM */
1092 /* Register to use for pushing function arguments. */
1093 #define STACK_POINTER_REGNUM 7
1095 /* Base register for access to local variables of the function. */
1096 #define HARD_FRAME_POINTER_REGNUM 6
1098 /* Base register for access to local variables of the function. */
1099 #define FRAME_POINTER_REGNUM 20
1101 /* First floating point reg */
1102 #define FIRST_FLOAT_REG 8
1104 /* First & last stack-like regs */
1105 #define FIRST_STACK_REG FIRST_FLOAT_REG
1106 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1108 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1109 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1111 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1112 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1114 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1115 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1117 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1118 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1120 /* Value should be nonzero if functions must have frame pointers.
1121 Zero means the frame pointer need not be set up (and parms
1122 may be accessed via the stack pointer) in functions that seem suitable.
1123 This is computed in `reload', in reload1.c. */
1124 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1126 /* Override this in other tm.h files to cope with various OS lossage
1127 requiring a frame pointer. */
1128 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1129 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1132 /* Make sure we can access arbitrary call frames. */
1133 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1135 /* Base register for access to arguments of the function. */
1136 #define ARG_POINTER_REGNUM 16
1138 /* Register in which static-chain is passed to a function.
1139 We do use ECX as static chain register for 32 bit ABI. On the
1140 64bit ABI, ECX is an argument register, so we use R10 instead. */
1141 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? R10_REG : CX_REG)
1143 /* Register to hold the addressing base for position independent
1144 code access to data items. We don't use PIC pointer for 64bit
1145 mode. Define the regnum to dummy value to prevent gcc from
1146 pessimizing code dealing with EBX.
1148 To avoid clobbering a call-saved register unnecessarily, we renumber
1149 the pic register when possible. The change is visible after the
1150 prologue has been emitted. */
1152 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG
1154 #define PIC_OFFSET_TABLE_REGNUM \
1155 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1156 || !flag_pic ? INVALID_REGNUM \
1157 : reload_completed ? REGNO (pic_offset_table_rtx) \
1158 : REAL_PIC_OFFSET_TABLE_REGNUM)
1160 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1162 /* This is overridden by <cygwin.h>. */
1163 #define MS_AGGREGATE_RETURN 0
1165 /* This is overridden by <netware.h>. */
1166 #define KEEP_AGGREGATE_RETURN_POINTER 0
1168 /* Define the classes of registers for register constraints in the
1169 machine description. Also define ranges of constants.
1171 One of the classes must always be named ALL_REGS and include all hard regs.
1172 If there is more than one class, another class must be named NO_REGS
1173 and contain no registers.
1175 The name GENERAL_REGS must be the name of a class (or an alias for
1176 another name such as ALL_REGS). This is the class of registers
1177 that is allowed by "g" or "r" in a register constraint.
1178 Also, registers outside this class are allocated only when
1179 instructions express preferences for them.
1181 The classes must be numbered in nondecreasing order; that is,
1182 a larger-numbered class must never be contained completely
1183 in a smaller-numbered class.
1185 For any two classes, it is very desirable that there be another
1186 class that represents their union.
1188 It might seem that class BREG is unnecessary, since no useful 386
1189 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1190 and the "b" register constraint is useful in asms for syscalls.
1192 The flags, fpsr and fpcr registers are in no class. */
1197 AREG, DREG, CREG, BREG, SIREG, DIREG,
1198 AD_REGS, /* %eax/%edx for DImode */
1199 Q_REGS, /* %eax %ebx %ecx %edx */
1200 NON_Q_REGS, /* %esi %edi %ebp %esp */
1201 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1202 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1203 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1204 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1215 ALL_REGS, LIM_REG_CLASSES
1218 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1220 #define INTEGER_CLASS_P(CLASS) \
1221 reg_class_subset_p ((CLASS), GENERAL_REGS)
1222 #define FLOAT_CLASS_P(CLASS) \
1223 reg_class_subset_p ((CLASS), FLOAT_REGS)
1224 #define SSE_CLASS_P(CLASS) \
1225 reg_class_subset_p ((CLASS), SSE_REGS)
1226 #define MMX_CLASS_P(CLASS) \
1227 ((CLASS) == MMX_REGS)
1228 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1229 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1230 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1231 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1232 #define MAYBE_SSE_CLASS_P(CLASS) \
1233 reg_classes_intersect_p (SSE_REGS, (CLASS))
1234 #define MAYBE_MMX_CLASS_P(CLASS) \
1235 reg_classes_intersect_p (MMX_REGS, (CLASS))
1237 #define Q_CLASS_P(CLASS) \
1238 reg_class_subset_p ((CLASS), Q_REGS)
1240 /* Give names of register classes as strings for dump file. */
1242 #define REG_CLASS_NAMES \
1244 "AREG", "DREG", "CREG", "BREG", \
1247 "Q_REGS", "NON_Q_REGS", \
1251 "FP_TOP_REG", "FP_SECOND_REG", \
1256 "FP_TOP_SSE_REGS", \
1257 "FP_SECOND_SSE_REGS", \
1261 "FLOAT_INT_SSE_REGS", \
1264 /* Define which registers fit in which classes.
1265 This is an initializer for a vector of HARD_REG_SET
1266 of length N_REG_CLASSES. */
1268 #define REG_CLASS_CONTENTS \
1270 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1271 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1272 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1273 { 0x03, 0x0 }, /* AD_REGS */ \
1274 { 0x0f, 0x0 }, /* Q_REGS */ \
1275 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1276 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1277 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1278 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1279 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1280 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1281 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1282 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1283 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1284 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1285 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1286 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1287 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1288 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1289 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1290 { 0xffffffff,0x1fffff } \
1293 /* The following macro defines cover classes for Integrated Register
1294 Allocator. Cover classes is a set of non-intersected register
1295 classes covering all hard registers used for register allocation
1296 purpose. Any move between two registers of a cover class should be
1297 cheaper than load or store of the registers. The macro value is
1298 array of register classes with LIM_REG_CLASSES used as the end
1301 #define IRA_COVER_CLASSES \
1303 GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES \
1306 /* The same information, inverted:
1307 Return the class number of the smallest class containing
1308 reg number REGNO. This could be a conditional expression
1309 or could index an array. */
1311 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1313 /* When defined, the compiler allows registers explicitly used in the
1314 rtl to be used as spill registers but prevents the compiler from
1315 extending the lifetime of these registers. */
1317 #define SMALL_REGISTER_CLASSES 1
1319 #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
1321 #define GENERAL_REGNO_P(N) \
1322 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1324 #define GENERAL_REG_P(X) \
1325 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1327 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1329 #define REX_INT_REGNO_P(N) \
1330 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1331 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1333 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1334 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1335 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1336 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1338 #define X87_FLOAT_MODE_P(MODE) \
1339 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1341 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1342 #define SSE_REGNO_P(N) \
1343 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1344 || REX_SSE_REGNO_P (N))
1346 #define REX_SSE_REGNO_P(N) \
1347 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1349 #define SSE_REGNO(N) \
1350 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1352 #define SSE_FLOAT_MODE_P(MODE) \
1353 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1355 #define SSE_VEC_FLOAT_MODE_P(MODE) \
1356 ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode))
1358 #define AVX_FLOAT_MODE_P(MODE) \
1359 (TARGET_AVX && ((MODE) == SFmode || (MODE) == DFmode))
1361 #define AVX128_VEC_FLOAT_MODE_P(MODE) \
1362 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode))
1364 #define AVX256_VEC_FLOAT_MODE_P(MODE) \
1365 (TARGET_AVX && ((MODE) == V8SFmode || (MODE) == V4DFmode))
1367 #define AVX_VEC_FLOAT_MODE_P(MODE) \
1368 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \
1369 || (MODE) == V8SFmode || (MODE) == V4DFmode))
1371 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1372 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1374 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1375 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1377 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1379 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1380 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1382 /* The class value for index registers, and the one for base regs. */
1384 #define INDEX_REG_CLASS INDEX_REGS
1385 #define BASE_REG_CLASS GENERAL_REGS
1387 /* Place additional restrictions on the register class to use when it
1388 is necessary to be able to hold a value of mode MODE in a reload
1389 register for which class CLASS would ordinarily be used. */
1391 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1392 ((MODE) == QImode && !TARGET_64BIT \
1393 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1394 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1397 /* Given an rtx X being reloaded into a reg required to be
1398 in class CLASS, return the class of reg to actually use.
1399 In general this is just CLASS; but on some machines
1400 in some cases it is preferable to use a more restrictive class.
1401 On the 80386 series, we prevent floating constants from being
1402 reloaded into floating registers (since no move-insn can do that)
1403 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1405 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1406 QImode must go into class Q_REGS.
1407 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1408 movdf to do mem-to-mem moves through integer regs. */
1410 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1411 ix86_preferred_reload_class ((X), (CLASS))
1413 /* Discourage putting floating-point values in SSE registers unless
1414 SSE math is being used, and likewise for the 387 registers. */
1416 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1417 ix86_preferred_output_reload_class ((X), (CLASS))
1419 /* If we are copying between general and FP registers, we need a memory
1420 location. The same is true for SSE and MMX registers. */
1421 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1422 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1424 /* Get_secondary_mem widens integral modes to BITS_PER_WORD.
1425 There is no need to emit full 64 bit move on 64 bit targets
1426 for integral modes that can be moved using 32 bit move. */
1427 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1428 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \
1429 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1432 /* Return the maximum number of consecutive registers
1433 needed to represent mode MODE in a register of class CLASS. */
1434 /* On the 80386, this is the size of MODE in words,
1435 except in the FP regs, where a single reg is always enough. */
1436 #define CLASS_MAX_NREGS(CLASS, MODE) \
1437 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1438 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1439 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1440 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1442 /* A C expression whose value is nonzero if pseudos that have been
1443 assigned to registers of class CLASS would likely be spilled
1444 because registers of CLASS are needed for spill registers.
1446 The default value of this macro returns 1 if CLASS has exactly one
1447 register and zero otherwise. On most machines, this default
1448 should be used. Only define this macro to some other expression
1449 if pseudo allocated by `local-alloc.c' end up in memory because
1450 their hard registers were needed for spill registers. If this
1451 macro returns nonzero for those classes, those pseudos will only
1452 be allocated by `global.c', which knows how to reallocate the
1453 pseudo to another register. If there would not be another
1454 register available for reallocation, you should not change the
1455 definition of this macro since the only effect of such a
1456 definition would be to slow down register allocation. */
1458 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1459 (((CLASS) == AREG) \
1460 || ((CLASS) == DREG) \
1461 || ((CLASS) == CREG) \
1462 || ((CLASS) == BREG) \
1463 || ((CLASS) == AD_REGS) \
1464 || ((CLASS) == SIREG) \
1465 || ((CLASS) == DIREG) \
1466 || ((CLASS) == FP_TOP_REG) \
1467 || ((CLASS) == FP_SECOND_REG))
1469 /* Return a class of registers that cannot change FROM mode to TO mode. */
1471 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1472 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1474 /* Stack layout; function entry, exit and calling. */
1476 /* Define this if pushing a word on the stack
1477 makes the stack pointer a smaller address. */
1478 #define STACK_GROWS_DOWNWARD
1480 /* Define this to nonzero if the nominal address of the stack frame
1481 is at the high-address end of the local variables;
1482 that is, each additional local variable allocated
1483 goes at a more negative offset in the frame. */
1484 #define FRAME_GROWS_DOWNWARD 1
1486 /* Offset within stack frame to start allocating local variables at.
1487 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1488 first local allocated. Otherwise, it is the offset to the BEGINNING
1489 of the first local allocated. */
1490 #define STARTING_FRAME_OFFSET 0
1492 /* If we generate an insn to push BYTES bytes,
1493 this says how many the stack pointer really advances by.
1494 On 386, we have pushw instruction that decrements by exactly 2 no
1495 matter what the position was, there is no pushb.
1496 But as CIE data alignment factor on this arch is -4, we need to make
1497 sure all stack pointer adjustments are in multiple of 4.
1499 For 64bit ABI we round up to 8 bytes.
1502 #define PUSH_ROUNDING(BYTES) \
1504 ? (((BYTES) + 7) & (-8)) \
1505 : (((BYTES) + 3) & (-4)))
1507 /* If defined, the maximum amount of space required for outgoing arguments will
1508 be computed and placed into the variable
1509 `crtl->outgoing_args_size'. No space will be pushed onto the
1510 stack for each call; instead, the function prologue should increase the stack
1511 frame size by this amount.
1513 MS ABI seem to require 16 byte alignment everywhere except for function
1514 prologue and apilogue. This is not possible without
1515 ACCUMULATE_OUTGOING_ARGS. */
1517 #define ACCUMULATE_OUTGOING_ARGS (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI)
1519 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1520 instructions to pass outgoing arguments. */
1522 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1524 /* We want the stack and args grow in opposite directions, even if
1526 #define PUSH_ARGS_REVERSED 1
1528 /* Offset of first parameter from the argument pointer register value. */
1529 #define FIRST_PARM_OFFSET(FNDECL) 0
1531 /* Define this macro if functions should assume that stack space has been
1532 allocated for arguments even when their values are passed in registers.
1534 The value of this macro is the size, in bytes, of the area reserved for
1535 arguments passed in registers for the function represented by FNDECL.
1537 This space can be allocated by the caller, or be a part of the
1538 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1540 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1542 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \
1543 (ix86_function_type_abi (FNTYPE) == MS_ABI)
1545 /* Value is the number of bytes of arguments automatically
1546 popped when returning from a subroutine call.
1547 FUNDECL is the declaration node of the function (as a tree),
1548 FUNTYPE is the data type of the function (as a tree),
1549 or for a library call it is an identifier node for the subroutine name.
1550 SIZE is the number of bytes of arguments passed on the stack.
1552 On the 80386, the RTD insn may be used to pop them if the number
1553 of args is fixed, but if the number is variable then the caller
1554 must pop them all. RTD can't be used for library calls now
1555 because the library is compiled with the Unix compiler.
1556 Use of RTD is a selectable option, since it is incompatible with
1557 standard Unix calling sequences. If the option is not selected,
1558 the caller must always pop the args.
1560 The attribute stdcall is equivalent to RTD on a per module basis. */
1562 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1563 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1565 #define FUNCTION_VALUE_REGNO_P(N) ix86_function_value_regno_p (N)
1567 /* Define how to find the value returned by a library function
1568 assuming the value has mode MODE. */
1570 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE)
1572 /* Define the size of the result block used for communication between
1573 untyped_call and untyped_return. The block contains a DImode value
1574 followed by the block used by fnsave and frstor. */
1576 #define APPLY_RESULT_SIZE (8+108)
1578 /* 1 if N is a possible register number for function argument passing. */
1579 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1581 /* Define a data type for recording info about an argument list
1582 during the scan of that argument list. This data type should
1583 hold all necessary information about the function itself
1584 and about the args processed so far, enough to enable macros
1585 such as FUNCTION_ARG to determine where the next arg should go. */
1587 typedef struct ix86_args {
1588 int words; /* # words passed so far */
1589 int nregs; /* # registers available for passing */
1590 int regno; /* next available register number */
1591 int fastcall; /* fastcall calling convention is used */
1592 int sse_words; /* # sse words passed so far */
1593 int sse_nregs; /* # sse registers available for passing */
1594 int warn_avx; /* True when we want to warn about AVX ABI. */
1595 int warn_sse; /* True when we want to warn about SSE ABI. */
1596 int warn_mmx; /* True when we want to warn about MMX ABI. */
1597 int sse_regno; /* next available sse register number */
1598 int mmx_words; /* # mmx words passed so far */
1599 int mmx_nregs; /* # mmx registers available for passing */
1600 int mmx_regno; /* next available mmx register number */
1601 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1602 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1603 be passed in SSE registers. Otherwise 0. */
1604 int call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1605 MS_ABI for ms abi. */
1608 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1609 for a call to a function whose data type is FNTYPE.
1610 For a library call, FNTYPE is 0. */
1612 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1613 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1615 /* Update the data in CUM to advance over an argument
1616 of mode MODE and data type TYPE.
1617 (TYPE is null for libcalls where that information may not be available.) */
1619 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1620 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1622 /* Define where to put the arguments to a function.
1623 Value is zero to push the argument on the stack,
1624 or a hard register in which to store the argument.
1626 MODE is the argument's machine mode.
1627 TYPE is the data type of the argument (as a tree).
1628 This is null for libcalls where that information may
1630 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1631 the preceding args and about the function being called.
1632 NAMED is nonzero if this argument is a named parameter
1633 (otherwise it is an extra parameter matching an ellipsis). */
1635 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1636 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1638 #define TARGET_ASM_FILE_END ix86_file_end
1639 #define NEED_INDICATE_EXEC_STACK 0
1641 /* Output assembler code to FILE to increment profiler label # LABELNO
1642 for profiling a function entry. */
1644 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1646 #define MCOUNT_NAME "_mcount"
1648 #define PROFILE_COUNT_REGISTER "edx"
1650 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1651 the stack pointer does not matter. The value is tested only in
1652 functions that have frame pointers.
1653 No definition is equivalent to always zero. */
1654 /* Note on the 386 it might be more efficient not to define this since
1655 we have to restore it ourselves from the frame pointer, in order to
1658 #define EXIT_IGNORE_STACK 1
1660 /* Output assembler code for a block containing the constant parts
1661 of a trampoline, leaving space for the variable parts. */
1663 /* On the 386, the trampoline contains two instructions:
1666 The trampoline is generated entirely at runtime. The operand of JMP
1667 is the address of FUNCTION relative to the instruction following the
1668 JMP (which is 5 bytes long). */
1670 /* Length in units of the trampoline for entering a nested function. */
1672 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1674 /* Emit RTL insns to initialize the variable parts of a trampoline.
1675 FNADDR is an RTX for the address of the function's pure code.
1676 CXT is an RTX for the static chain value for the function. */
1678 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1679 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1681 /* Definitions for register eliminations.
1683 This is an array of structures. Each structure initializes one pair
1684 of eliminable registers. The "from" register number is given first,
1685 followed by "to". Eliminations of the same "from" register are listed
1686 in order of preference.
1688 There are two registers that can always be eliminated on the i386.
1689 The frame pointer and the arg pointer can be replaced by either the
1690 hard frame pointer or to the stack pointer, depending upon the
1691 circumstances. The hard frame pointer is not used before reload and
1692 so it is not eligible for elimination. */
1694 #define ELIMINABLE_REGS \
1695 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1696 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1697 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1698 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1700 /* Given FROM and TO register numbers, say whether this elimination is
1703 #define CAN_ELIMINATE(FROM, TO) ix86_can_eliminate ((FROM), (TO))
1705 /* Define the offset between two registers, one to be eliminated, and the other
1706 its replacement, at the start of a routine. */
1708 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1709 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1711 /* Addressing modes, and classification of registers for them. */
1713 /* Macros to check register numbers against specific register classes. */
1715 /* These assume that REGNO is a hard or pseudo reg number.
1716 They give nonzero only if REGNO is a hard reg of the suitable class
1717 or a pseudo reg currently allocated to a suitable hard reg.
1718 Since they use reg_renumber, they are safe only once reg_renumber
1719 has been allocated, which happens in local-alloc.c. */
1721 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1722 ((REGNO) < STACK_POINTER_REGNUM \
1723 || REX_INT_REGNO_P (REGNO) \
1724 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1725 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1727 #define REGNO_OK_FOR_BASE_P(REGNO) \
1728 (GENERAL_REGNO_P (REGNO) \
1729 || (REGNO) == ARG_POINTER_REGNUM \
1730 || (REGNO) == FRAME_POINTER_REGNUM \
1731 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1733 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1734 and check its validity for a certain class.
1735 We have two alternate definitions for each of them.
1736 The usual definition accepts all pseudo regs; the other rejects
1737 them unless they have been allocated suitable hard regs.
1738 The symbol REG_OK_STRICT causes the latter definition to be used.
1740 Most source files want to accept pseudo regs in the hope that
1741 they will get allocated to the class that the insn wants them to be in.
1742 Source files for reload pass need to be strict.
1743 After reload, it makes no difference, since pseudo regs have
1744 been eliminated by then. */
1747 /* Non strict versions, pseudos are ok. */
1748 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1749 (REGNO (X) < STACK_POINTER_REGNUM \
1750 || REX_INT_REGNO_P (REGNO (X)) \
1751 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1753 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1754 (GENERAL_REGNO_P (REGNO (X)) \
1755 || REGNO (X) == ARG_POINTER_REGNUM \
1756 || REGNO (X) == FRAME_POINTER_REGNUM \
1757 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1759 /* Strict versions, hard registers only */
1760 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1761 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1763 #ifndef REG_OK_STRICT
1764 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1765 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1768 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1769 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1772 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1773 that is a valid memory address for an instruction.
1774 The MODE argument is the machine mode for the MEM expression
1775 that wants to use this address.
1777 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1778 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1780 See legitimize_pic_address in i386.c for details as to what
1781 constitutes a legitimate address when -fpic is used. */
1783 #define MAX_REGS_PER_ADDRESS 2
1785 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1787 /* Nonzero if the constant value X is a legitimate general operand.
1788 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1790 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1792 #ifdef REG_OK_STRICT
1793 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1795 if (legitimate_address_p ((MODE), (X), 1)) \
1800 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1802 if (legitimate_address_p ((MODE), (X), 0)) \
1808 /* If defined, a C expression to determine the base term of address X.
1809 This macro is used in only one place: `find_base_term' in alias.c.
1811 It is always safe for this macro to not be defined. It exists so
1812 that alias analysis can understand machine-dependent addresses.
1814 The typical use of this macro is to handle addresses containing
1815 a label_ref or symbol_ref within an UNSPEC. */
1817 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1819 /* Try machine-dependent ways of modifying an illegitimate address
1820 to be legitimate. If we find one, return the new, valid address.
1821 This macro is used in only one place: `memory_address' in explow.c.
1823 OLDX is the address as it was before break_out_memory_refs was called.
1824 In some cases it is useful to look at this to decide what needs to be done.
1826 MODE and WIN are passed so that this macro can use
1827 GO_IF_LEGITIMATE_ADDRESS.
1829 It is always safe for this macro to do nothing. It exists to recognize
1830 opportunities to optimize the output.
1832 For the 80386, we handle X+REG by loading X into a register R and
1833 using R+REG. R will go in a general reg and indexing will be used.
1834 However, if REG is a broken-out memory address or multiplication,
1835 nothing needs to be done because REG can certainly go in a general reg.
1837 When -fpic is used, special handling is needed for symbolic references.
1838 See comments by legitimize_pic_address in i386.c for details. */
1840 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1842 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1843 if (memory_address_p ((MODE), (X))) \
1847 /* Nonzero if the constant value X is a legitimate general operand
1848 when generating PIC code. It is given that flag_pic is on and
1849 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1851 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1853 #define SYMBOLIC_CONST(X) \
1854 (GET_CODE (X) == SYMBOL_REF \
1855 || GET_CODE (X) == LABEL_REF \
1856 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1858 /* Go to LABEL if ADDR (a legitimate address expression)
1859 has an effect that depends on the machine mode it is used for.
1860 On the 80386, only postdecrement and postincrement address depend thus
1861 (the amount of decrement or increment being the length of the operand).
1862 These are now caught in recog.c. */
1863 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
1865 /* Max number of args passed in registers. If this is more than 3, we will
1866 have problems with ebx (register #4), since it is a caller save register and
1867 is also used as the pic register in ELF. So for now, don't allow more than
1868 3 registers to be passed in registers. */
1870 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1871 #define X86_64_REGPARM_MAX 6
1872 #define X64_REGPARM_MAX 4
1873 #define X86_32_REGPARM_MAX 3
1875 #define X86_64_SSE_REGPARM_MAX 8
1876 #define X64_SSE_REGPARM_MAX 4
1877 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? 3 : 0)
1879 #define REGPARM_MAX \
1880 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_REGPARM_MAX \
1881 : X86_64_REGPARM_MAX) \
1882 : X86_32_REGPARM_MAX)
1884 #define SSE_REGPARM_MAX \
1885 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_SSE_REGPARM_MAX \
1886 : X86_64_SSE_REGPARM_MAX) \
1887 : X86_32_SSE_REGPARM_MAX)
1889 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1892 /* Specify the machine mode that this machine uses
1893 for the index in the tablejump instruction. */
1894 #define CASE_VECTOR_MODE \
1895 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1897 /* Define this as 1 if `char' should by default be signed; else as 0. */
1898 #define DEFAULT_SIGNED_CHAR 1
1900 /* Max number of bytes we can move from memory to memory
1901 in one reasonably fast instruction. */
1904 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1905 move efficiently, as opposed to MOVE_MAX which is the maximum
1906 number of bytes we can move with a single instruction. */
1907 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1909 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1910 move-instruction pairs, we will do a movmem or libcall instead.
1911 Increasing the value will always make code faster, but eventually
1912 incurs high cost in increased code size.
1914 If you don't define this, a reasonable default is used. */
1916 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3)
1918 /* If a clear memory operation would take CLEAR_RATIO or more simple
1919 move-instruction sequences, we will do a clrmem or libcall instead. */
1921 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)
1923 /* Define if shifts truncate the shift count
1924 which implies one can omit a sign-extension or zero-extension
1925 of a shift count. */
1926 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1928 /* #define SHIFT_COUNT_TRUNCATED */
1930 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1931 is done just by pretending it is already truncated. */
1932 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1934 /* A macro to update M and UNSIGNEDP when an object whose type is
1935 TYPE and which has the specified mode and signedness is to be
1936 stored in a register. This macro is only called when TYPE is a
1939 On i386 it is sometimes useful to promote HImode and QImode
1940 quantities to SImode. The choice depends on target type. */
1942 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1944 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1945 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1949 /* Specify the machine mode that pointers have.
1950 After generation of rtl, the compiler makes no further distinction
1951 between pointers and any other objects of this machine mode. */
1952 #define Pmode (TARGET_64BIT ? DImode : SImode)
1954 /* A function address in a call instruction
1955 is a byte address (for indexing purposes)
1956 so give the MEM rtx a byte's mode. */
1957 #define FUNCTION_MODE QImode
1959 /* A C expression for the cost of moving data from a register in class FROM to
1960 one in class TO. The classes are expressed using the enumeration values
1961 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1962 interpreted relative to that.
1964 It is not required that the cost always equal 2 when FROM is the same as TO;
1965 on some machines it is expensive to move between registers if they are not
1966 general registers. */
1968 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1969 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1971 /* A C expression for the cost of moving data of mode M between a
1972 register and memory. A value of 2 is the default; this cost is
1973 relative to those in `REGISTER_MOVE_COST'.
1975 If moving between registers and memory is more expensive than
1976 between two registers, you should define this macro to express the
1979 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1980 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1982 /* A C expression for the cost of a branch instruction. A value of 1
1983 is the default; other values are interpreted relative to that. */
1985 #define BRANCH_COST(speed_p, predictable_p) \
1986 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost)
1988 /* Define this macro as a C expression which is nonzero if accessing
1989 less than a word of memory (i.e. a `char' or a `short') is no
1990 faster than accessing a word of memory, i.e., if such access
1991 require more than one instruction or if there is no difference in
1992 cost between byte and (aligned) word loads.
1994 When this macro is not defined, the compiler will access a field by
1995 finding the smallest containing object; when it is defined, a
1996 fullword load will be used if alignment permits. Unless bytes
1997 accesses are faster than word accesses, using word accesses is
1998 preferable since it may eliminate subsequent memory access if
1999 subsequent accesses occur to other fields in the same word of the
2000 structure, but to different bytes. */
2002 #define SLOW_BYTE_ACCESS 0
2004 /* Nonzero if access to memory by shorts is slow and undesirable. */
2005 #define SLOW_SHORT_ACCESS 0
2007 /* Define this macro to be the value 1 if unaligned accesses have a
2008 cost many times greater than aligned accesses, for example if they
2009 are emulated in a trap handler.
2011 When this macro is nonzero, the compiler will act as if
2012 `STRICT_ALIGNMENT' were nonzero when generating code for block
2013 moves. This can cause significantly more instructions to be
2014 produced. Therefore, do not set this macro nonzero if unaligned
2015 accesses only add a cycle or two to the time for a memory access.
2017 If the value of this macro is always zero, it need not be defined. */
2019 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2021 /* Define this macro if it is as good or better to call a constant
2022 function address than to call an address kept in a register.
2024 Desirable on the 386 because a CALL with a constant address is
2025 faster than one with a register address. */
2027 #define NO_FUNCTION_CSE
2029 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2030 return the mode to be used for the comparison.
2032 For floating-point equality comparisons, CCFPEQmode should be used.
2033 VOIDmode should be used in all other cases.
2035 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2036 possible, to allow for more combinations. */
2038 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2040 /* Return nonzero if MODE implies a floating point inequality can be
2043 #define REVERSIBLE_CC_MODE(MODE) 1
2045 /* A C expression whose value is reversed condition code of the CODE for
2046 comparison done in CC_MODE mode. */
2047 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2050 /* Control the assembler format that we output, to the extent
2051 this does not vary between assemblers. */
2053 /* How to refer to registers in assembler output.
2054 This sequence is indexed by compiler's hard-register-number (see above). */
2056 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2057 For non floating point regs, the following are the HImode names.
2059 For float regs, the stack top is sometimes referred to as "%st(0)"
2060 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2062 #define HI_REGISTER_NAMES \
2063 {"ax","dx","cx","bx","si","di","bp","sp", \
2064 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2065 "argp", "flags", "fpsr", "fpcr", "frame", \
2066 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2067 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2068 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2069 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2071 #define REGISTER_NAMES HI_REGISTER_NAMES
2073 /* Table of additional register names to use in user input. */
2075 #define ADDITIONAL_REGISTER_NAMES \
2076 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2077 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2078 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2079 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2080 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2081 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2083 /* Note we are omitting these since currently I don't know how
2084 to get gcc to use these, since they want the same but different
2085 number as al, and ax.
2088 #define QI_REGISTER_NAMES \
2089 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2091 /* These parallel the array above, and can be used to access bits 8:15
2092 of regs 0 through 3. */
2094 #define QI_HIGH_REGISTER_NAMES \
2095 {"ah", "dh", "ch", "bh", }
2097 /* How to renumber registers for dbx and gdb. */
2099 #define DBX_REGISTER_NUMBER(N) \
2100 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2102 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2103 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2104 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2106 /* Before the prologue, RA is at 0(%esp). */
2107 #define INCOMING_RETURN_ADDR_RTX \
2108 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2110 /* After the prologue, RA is at -4(AP) in the current frame. */
2111 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2113 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2114 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2116 /* PC is dbx register 8; let's use that column for RA. */
2117 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2119 /* Before the prologue, the top of the frame is at 4(%esp). */
2120 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2122 /* Describe how we implement __builtin_eh_return. */
2123 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2124 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2127 /* Select a format to encode pointers in exception handling data. CODE
2128 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2129 true if the symbol may be affected by dynamic relocations.
2131 ??? All x86 object file formats are capable of representing this.
2132 After all, the relocation needed is the same as for the call insn.
2133 Whether or not a particular assembler allows us to enter such, I
2134 guess we'll have to see. */
2135 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2136 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2138 /* This is how to output an insn to push a register on the stack.
2139 It need not be very fast code. */
2141 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2144 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2145 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2147 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2150 /* This is how to output an insn to pop a register from the stack.
2151 It need not be very fast code. */
2153 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2156 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2157 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2159 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2162 /* This is how to output an element of a case-vector that is absolute. */
2164 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2165 ix86_output_addr_vec_elt ((FILE), (VALUE))
2167 /* This is how to output an element of a case-vector that is relative. */
2169 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2170 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2172 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is
2175 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \
2177 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \
2186 /* A C statement or statements which output an assembler instruction
2187 opcode to the stdio stream STREAM. The macro-operand PTR is a
2188 variable of type `char *' which points to the opcode name in
2189 its "internal" form--the form that is written in the machine
2192 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \
2193 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR))
2195 /* Under some conditions we need jump tables in the text section,
2196 because the assembler cannot handle label differences between
2197 sections. This is the case for x86_64 on Mach-O for example. */
2199 #define JUMP_TABLES_IN_TEXT_SECTION \
2200 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2201 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2203 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2204 and switch back. For x86 we do this only to save a few bytes that
2205 would otherwise be unused in the text section. */
2206 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2207 asm (SECTION_OP "\n\t" \
2208 "call " USER_LABEL_PREFIX #FUNC "\n" \
2209 TEXT_SECTION_ASM_OP);
2211 /* Print operand X (an rtx) in assembler syntax to file FILE.
2212 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2213 Effect of various CODE letters is described in i386.c near
2214 print_operand function. */
2216 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2217 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';')
2219 #define PRINT_OPERAND(FILE, X, CODE) \
2220 print_operand ((FILE), (X), (CODE))
2222 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2223 print_operand_address ((FILE), (ADDR))
2225 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2227 if (! output_addr_const_extra (FILE, (X))) \
2231 /* Which processor to schedule for. The cpu attribute defines a list that
2232 mirrors this list, so changes to i386.md must be made at the same time. */
2236 PROCESSOR_I386 = 0, /* 80386 */
2237 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2239 PROCESSOR_PENTIUMPRO,
2247 PROCESSOR_GENERIC32,
2248 PROCESSOR_GENERIC64,
2253 extern enum processor_type ix86_tune;
2254 extern enum processor_type ix86_arch;
2262 extern enum fpmath_unit ix86_fpmath;
2271 extern enum tls_dialect ix86_tls_dialect;
2274 CM_32, /* The traditional 32-bit ABI. */
2275 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2276 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2277 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2278 CM_LARGE, /* No assumptions. */
2279 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2280 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2281 CM_LARGE_PIC /* No assumptions. */
2284 extern enum cmodel ix86_cmodel;
2286 /* Size of the RED_ZONE area. */
2287 #define RED_ZONE_SIZE 128
2288 /* Reserved area of the red zone for temporaries. */
2289 #define RED_ZONE_RESERVE 8
2296 extern enum asm_dialect ix86_asm_dialect;
2297 extern unsigned int ix86_preferred_stack_boundary;
2298 extern unsigned int ix86_incoming_stack_boundary;
2299 extern int ix86_branch_cost, ix86_section_threshold;
2301 /* Smallest class containing REGNO. */
2302 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2304 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2305 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2306 extern rtx ix86_compare_emitted;
2308 /* To properly truncate FP values into integers, we need to set i387 control
2309 word. We can't emit proper mode switching code before reload, as spills
2310 generated by reload may truncate values incorrectly, but we still can avoid
2311 redundant computation of new control word by the mode switching pass.
2312 The fldcw instructions are still emitted redundantly, but this is probably
2313 not going to be noticeable problem, as most CPUs do have fast path for
2316 The machinery is to emit simple truncation instructions and split them
2317 before reload to instructions having USEs of two memory locations that
2318 are filled by this code to old and new control word.
2320 Post-reload pass may be later used to eliminate the redundant fildcw if
2332 enum ix86_stack_slot
2341 MAX_386_STACK_LOCALS
2344 /* Define this macro if the port needs extra instructions inserted
2345 for mode switching in an optimizing compilation. */
2347 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2348 ix86_optimize_mode_switching[(ENTITY)]
2350 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2351 initializer for an array of integers. Each initializer element N
2352 refers to an entity that needs mode switching, and specifies the
2353 number of different modes that might need to be set for this
2354 entity. The position of the initializer in the initializer -
2355 starting counting at zero - determines the integer that is used to
2356 refer to the mode-switched entity in question. */
2358 #define NUM_MODES_FOR_MODE_SWITCHING \
2359 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2361 /* ENTITY is an integer specifying a mode-switched entity. If
2362 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2363 return an integer value not larger than the corresponding element
2364 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2365 must be switched into prior to the execution of INSN. */
2367 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2369 /* This macro specifies the order in which modes for ENTITY are
2370 processed. 0 is the highest priority. */
2372 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2374 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2375 is the set of hard registers live at the point where the insn(s)
2376 are to be inserted. */
2378 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2379 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2380 ? emit_i387_cw_initialization (MODE), 0 \
2384 /* Avoid renaming of stack registers, as doing so in combination with
2385 scheduling just increases amount of live registers at time and in
2386 the turn amount of fxch instructions needed.
2388 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2390 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2391 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2394 #define FASTCALL_PREFIX '@'
2396 struct machine_function GTY(())
2398 struct stack_local_entry *stack_locals;
2399 const char *some_ld_name;
2400 int varargs_gpr_size;
2401 int varargs_fpr_size;
2402 int accesses_prev_frame;
2403 int optimize_mode_switching[MAX_386_ENTITIES];
2405 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2406 expander to determine the style used. */
2407 int use_fast_prologue_epilogue;
2408 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2410 int use_fast_prologue_epilogue_nregs;
2411 /* If true, the current function needs the default PIC register, not
2412 an alternate register (on x86) and must not use the red zone (on
2413 x86_64), even if it's a leaf function. We don't want the
2414 function to be regarded as non-leaf because TLS calls need not
2415 affect register allocation. This flag is set when a TLS call
2416 instruction is expanded within a function, and never reset, even
2417 if all such instructions are optimized away. Use the
2418 ix86_current_function_calls_tls_descriptor macro for a better
2420 int tls_descriptor_call_expanded_p;
2421 /* This value is used for amd64 targets and specifies the current abi
2422 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2426 #define ix86_stack_locals (cfun->machine->stack_locals)
2427 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size)
2428 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size)
2429 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2430 #define ix86_current_function_needs_cld (cfun->machine->needs_cld)
2431 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2432 (cfun->machine->tls_descriptor_call_expanded_p)
2433 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2434 calls are optimized away, we try to detect cases in which it was
2435 optimized away. Since such instructions (use (reg REG_SP)), we can
2436 verify whether there's any such instruction live by testing that
2438 #define ix86_current_function_calls_tls_descriptor \
2439 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2441 /* Control behavior of x86_file_start. */
2442 #define X86_FILE_START_VERSION_DIRECTIVE false
2443 #define X86_FILE_START_FLTUSED false
2445 /* Flag to mark data that is in the large address area. */
2446 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2447 #define SYMBOL_REF_FAR_ADDR_P(X) \
2448 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2450 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2451 have defined always, to avoid ifdefing. */
2452 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2453 #define SYMBOL_REF_DLLIMPORT_P(X) \
2454 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2456 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2457 #define SYMBOL_REF_DLLEXPORT_P(X) \
2458 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2460 /* Model costs for vectorizer. */
2462 /* Cost of conditional branch. */
2463 #undef TARG_COND_BRANCH_COST
2464 #define TARG_COND_BRANCH_COST ix86_cost->branch_cost
2466 /* Enum through the target specific extra va_list types.
2467 Please, do not iterate the base va_list type name. */
2468 #define TARGET_ENUM_VA_LIST(IDX, PNAME, PTYPE) \
2469 (TARGET_64BIT ? ix86_enum_va_list (IDX, PNAME, PTYPE) : 0)
2471 /* Cost of any scalar operation, excluding load and store. */
2472 #undef TARG_SCALAR_STMT_COST
2473 #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost
2475 /* Cost of scalar load. */
2476 #undef TARG_SCALAR_LOAD_COST
2477 #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost
2479 /* Cost of scalar store. */
2480 #undef TARG_SCALAR_STORE_COST
2481 #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost
2483 /* Cost of any vector operation, excluding load, store or vector to scalar
2485 #undef TARG_VEC_STMT_COST
2486 #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost
2488 /* Cost of vector to scalar operation. */
2489 #undef TARG_VEC_TO_SCALAR_COST
2490 #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost
2492 /* Cost of scalar to vector operation. */
2493 #undef TARG_SCALAR_TO_VEC_COST
2494 #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost
2496 /* Cost of aligned vector load. */
2497 #undef TARG_VEC_LOAD_COST
2498 #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost
2500 /* Cost of misaligned vector load. */
2501 #undef TARG_VEC_UNALIGNED_LOAD_COST
2502 #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost
2504 /* Cost of vector store. */
2505 #undef TARG_VEC_STORE_COST
2506 #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost
2508 /* Cost of conditional taken branch for vectorizer cost model. */
2509 #undef TARG_COND_TAKEN_BRANCH_COST
2510 #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost
2512 /* Cost of conditional not taken branch for vectorizer cost model. */
2513 #undef TARG_COND_NOT_TAKEN_BRANCH_COST
2514 #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost