1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) X
48 #define HALF_PIC_FINISH(STREAM)
51 /* Define the specific costs for a given cpu */
53 struct processor_costs {
54 const int add; /* cost of an add instruction */
55 const int lea; /* cost of a lea instruction */
56 const int shift_var; /* variable shift costs */
57 const int shift_const; /* constant shift costs */
58 const int mult_init; /* cost of starting a multiply */
59 const int mult_bit; /* cost of multiply per each bit set */
60 const int divide; /* cost of a divide/mod */
61 int movsx; /* The cost of movsx operation. */
62 int movzx; /* The cost of movzx operation. */
63 const int large_insn; /* insns larger than this cost more */
64 const int move_ratio; /* The threshold of number of scalar
65 memory-to-memory move insns. */
66 const int movzbl_load; /* cost of loading using movzbl */
67 const int int_load[3]; /* cost of loading integer registers
68 in QImode, HImode and SImode relative
69 to reg-reg move (2). */
70 const int int_store[3]; /* cost of storing integer register
71 in QImode, HImode and SImode */
72 const int fp_move; /* cost of reg,reg fld/fst */
73 const int fp_load[3]; /* cost of loading FP register
74 in SFmode, DFmode and XFmode */
75 const int fp_store[3]; /* cost of storing FP register
76 in SFmode, DFmode and XFmode */
77 const int mmx_move; /* cost of moving MMX register. */
78 const int mmx_load[2]; /* cost of loading MMX register
79 in SImode and DImode */
80 const int mmx_store[2]; /* cost of storing MMX register
81 in SImode and DImode */
82 const int sse_move; /* cost of moving SSE register. */
83 const int sse_load[3]; /* cost of loading SSE register
84 in SImode, DImode and TImode*/
85 const int sse_store[3]; /* cost of storing SSE register
86 in SImode, DImode and TImode*/
87 const int mmxsse_to_integer; /* cost of moving mmxsse register to
88 integer and vice versa. */
89 const int prefetch_block; /* bytes moved to cache for prefetch. */
90 const int simultaneous_prefetches; /* number of parallel prefetch
94 extern const struct processor_costs *ix86_cost;
96 /* Run-time compilation parameters selecting different hardware subsets. */
98 extern int target_flags;
100 /* Macros used in the machine description to test the flags. */
102 /* configure can arrange to make this 2, to force a 486. */
104 #ifndef TARGET_CPU_DEFAULT
105 #define TARGET_CPU_DEFAULT 0
108 /* Masks for the -m switches */
109 #define MASK_80387 0x00000001 /* Hardware floating point */
110 #define MASK_RTD 0x00000002 /* Use ret that pops args */
111 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
112 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
113 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
114 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
115 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
116 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
117 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
118 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
119 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
120 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
121 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
122 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
123 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
124 #define MASK_MMX_SET 0x00008000
125 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
126 #define MASK_SSE_SET 0x00020000
127 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
128 #define MASK_SSE2_SET 0x00080000
129 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
130 #define MASK_3DNOW_SET 0x00200000
131 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
132 #define MASK_3DNOW_A_SET 0x00800000
133 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
134 #define MASK_MIX_SSE_I387 0x02000000 /* Mix SSE and i387 instructions */
135 #define MASK_64BIT 0x04000000 /* Produce 64bit code */
136 #define MASK_NO_RED_ZONE 0x08000000 /* Do not use red zone */
138 /* Temporary codegen switches */
139 #define MASK_INTEL_SYNTAX 0x10000000
140 #define MASK_DEBUG_ARG 0x20000000 /* function_arg */
141 #define MASK_DEBUG_ADDR 0x40000000 /* GO_IF_LEGITIMATE_ADDRESS */
143 /* Use the floating point instructions */
144 #define TARGET_80387 (target_flags & MASK_80387)
146 /* Compile using ret insn that pops args.
147 This will not work unless you use prototypes at least
148 for all functions that can take varying numbers of args. */
149 #define TARGET_RTD (target_flags & MASK_RTD)
151 /* Align doubles to a two word boundary. This breaks compatibility with
152 the published ABI's for structures containing doubles, but produces
153 faster code on the pentium. */
154 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
156 /* Use push instructions to save outgoing args. */
157 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
159 /* Accumulate stack adjustments to prologue/epilogue. */
160 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
161 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
163 /* Put uninitialized locals into bss, not data.
164 Meaningful only on svr3. */
165 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
167 /* Use IEEE floating point comparisons. These handle correctly the cases
168 where the result of a comparison is unordered. Normally SIGFPE is
169 generated in such cases, in which case this isn't needed. */
170 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
172 /* Functions that return a floating point value may return that value
173 in the 387 FPU or in 386 integer registers. If set, this flag causes
174 the 387 to be used, which is compatible with most calling conventions. */
175 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
177 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
178 This mode wastes cache, but avoid misaligned data accesses and simplifies
179 address calculations. */
180 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
182 /* Disable generation of FP sin, cos and sqrt operations for 387.
183 This is because FreeBSD lacks these in the math-emulator-code */
184 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
186 /* Don't create frame pointers for leaf functions */
187 #define TARGET_OMIT_LEAF_FRAME_POINTER \
188 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
190 /* Debug GO_IF_LEGITIMATE_ADDRESS */
191 #define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR)
193 /* Debug FUNCTION_ARG macros */
194 #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG)
196 /* 64bit Sledgehammer mode */
197 #ifdef TARGET_BI_ARCH
198 #define TARGET_64BIT (target_flags & MASK_64BIT)
200 #ifdef TARGET_64BIT_DEFAULT
201 #define TARGET_64BIT 1
203 #define TARGET_64BIT 0
207 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
208 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
209 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
210 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
211 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
212 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
213 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
215 #define CPUMASK (1 << ix86_cpu)
216 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
217 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
218 extern const int x86_branch_hints, x86_unroll_strlen;
219 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
220 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
221 extern const int x86_use_cltd, x86_read_modify_write;
222 extern const int x86_read_modify, x86_split_long_moves;
223 extern const int x86_promote_QImode, x86_single_stringop;
224 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
225 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
226 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
227 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
228 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
229 extern const int x86_epilogue_using_move, x86_decompose_lea;
230 extern int x86_prefetch_sse;
232 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
233 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
234 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
235 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
236 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
237 /* For sane SSE instruction set generation we need fcomi instruction. It is
238 safe to enable all CMOVE instructions. */
239 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
240 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
241 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
242 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
243 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
244 #define TARGET_MOVX (x86_movx & CPUMASK)
245 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
246 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
247 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
248 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
249 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
250 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
251 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
252 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
253 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
254 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
255 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
256 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
257 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
258 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
259 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
260 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
261 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
262 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
263 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
264 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
265 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
266 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
267 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
268 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
269 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
271 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
273 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
274 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
276 #define ASSEMBLER_DIALECT ((target_flags & MASK_INTEL_SYNTAX) != 0)
278 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
279 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
280 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
281 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
282 && (ix86_fpmath & FPMATH_387))
283 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
284 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
285 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
287 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
289 #define TARGET_SWITCHES \
290 { { "80387", MASK_80387, N_("Use hardware fp") }, \
291 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
292 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
293 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
294 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
295 { "386", 0, N_("Same as -mcpu=i386") }, \
296 { "486", 0, N_("Same as -mcpu=i486") }, \
297 { "pentium", 0, N_("Same as -mcpu=pentium") }, \
298 { "pentiumpro", 0, N_("Same as -mcpu=pentiumpro") }, \
300 N_("Alternate calling convention") }, \
301 { "no-rtd", -MASK_RTD, \
302 N_("Use normal calling convention") }, \
303 { "align-double", MASK_ALIGN_DOUBLE, \
304 N_("Align some doubles on dword boundary") }, \
305 { "no-align-double", -MASK_ALIGN_DOUBLE, \
306 N_("Align doubles on word boundary") }, \
307 { "svr3-shlib", MASK_SVR3_SHLIB, \
308 N_("Uninitialized locals in .bss") }, \
309 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
310 N_("Uninitialized locals in .data") }, \
311 { "ieee-fp", MASK_IEEE_FP, \
312 N_("Use IEEE math for fp comparisons") }, \
313 { "no-ieee-fp", -MASK_IEEE_FP, \
314 N_("Do not use IEEE math for fp comparisons") }, \
315 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
316 N_("Return values of functions in FPU registers") }, \
317 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
318 N_("Do not return values of functions in FPU registers")}, \
319 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
320 N_("Do not generate sin, cos, sqrt for FPU") }, \
321 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
322 N_("Generate sin, cos, sqrt for FPU")}, \
323 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
324 N_("Omit the frame pointer in leaf functions") }, \
325 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
326 { "debug-addr", MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
327 { "no-debug-addr", -MASK_DEBUG_ADDR, 0 /* undocumented */ }, \
328 { "debug-arg", MASK_DEBUG_ARG, 0 /* undocumented */ }, \
329 { "no-debug-arg", -MASK_DEBUG_ARG, 0 /* undocumented */ }, \
330 { "stack-arg-probe", MASK_STACK_PROBE, \
331 N_("Enable stack probing") }, \
332 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
333 { "windows", 0, 0 /* undocumented */ }, \
334 { "dll", 0, 0 /* undocumented */ }, \
335 { "intel-syntax", MASK_INTEL_SYNTAX, \
336 N_("Emit Intel syntax assembler opcodes") }, \
337 { "no-intel-syntax", -MASK_INTEL_SYNTAX, "" }, \
338 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
339 N_("Align destination of the string operations") }, \
340 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
341 N_("Do not align destination of the string operations") }, \
342 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
343 N_("Inline all known string operations") }, \
344 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
345 N_("Do not inline all known string operations") }, \
346 { "push-args", -MASK_NO_PUSH_ARGS, \
347 N_("Use push instructions to save outgoing arguments") }, \
348 { "no-push-args", MASK_NO_PUSH_ARGS, \
349 N_("Do not use push instructions to save outgoing arguments") }, \
350 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
351 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
352 N_("Use push instructions to save outgoing arguments") }, \
353 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
354 N_("Do not use push instructions to save outgoing arguments") }, \
355 { "mmx", MASK_MMX | MASK_MMX_SET, \
356 N_("Support MMX built-in functions") }, \
357 { "no-mmx", -MASK_MMX, \
358 N_("Do not support MMX built-in functions") }, \
359 { "no-mmx", MASK_MMX_SET, N_("") }, \
360 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
361 N_("Support 3DNow! built-in functions") }, \
362 { "no-3dnow", -MASK_3DNOW, N_("") }, \
363 { "no-3dnow", MASK_3DNOW_SET, \
364 N_("Do not support 3DNow! built-in functions") }, \
365 { "sse", MASK_SSE | MASK_SSE_SET, \
366 N_("Support MMX and SSE built-in functions and code generation") }, \
367 { "no-sse", -MASK_SSE, N_("") }, \
368 { "no-sse", MASK_SSE_SET, \
369 N_("Do not support MMX and SSE built-in functions and code generation") },\
370 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
371 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
372 { "no-sse2", -MASK_SSE2, N_("") }, \
373 { "no-sse2", MASK_SSE2_SET, \
374 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
375 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
376 N_("sizeof(long double) is 16") }, \
377 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
378 N_("sizeof(long double) is 12") }, \
379 { "64", MASK_64BIT, \
380 N_("Generate 64bit x86-64 code") }, \
381 { "32", -MASK_64BIT, \
382 N_("Generate 32bit i386 code") }, \
383 { "red-zone", -MASK_NO_RED_ZONE, \
384 N_("Use red-zone in the x86-64 code") }, \
385 { "no-red-zone", MASK_NO_RED_ZONE, \
386 N_("Do not use red-zone in the x86-64 code") }, \
388 { "", TARGET_DEFAULT, 0 }}
390 #ifdef TARGET_64BIT_DEFAULT
391 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
393 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
396 /* Which processor to schedule for. The cpu attribute defines a list that
397 mirrors this list, so changes to i386.md must be made at the same time. */
401 PROCESSOR_I386, /* 80386 */
402 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
404 PROCESSOR_PENTIUMPRO,
416 extern enum processor_type ix86_cpu;
417 extern enum fpmath_unit ix86_fpmath;
419 extern int ix86_arch;
421 /* This macro is similar to `TARGET_SWITCHES' but defines names of
422 command options that have values. Its definition is an
423 initializer with a subgrouping for each command option.
425 Each subgrouping contains a string constant, that defines the
426 fixed part of the option name, and the address of a variable. The
427 variable, type `char *', is set to the variable part of the given
428 option if the fixed part matches. The actual option name is made
429 by appending `-m' to the specified name. */
430 #define TARGET_OPTIONS \
431 { { "cpu=", &ix86_cpu_string, \
432 N_("Schedule code for given CPU")}, \
433 { "fpmath=", &ix86_fpmath_string, \
434 N_("Generate floating point mathematics using given instruction set")},\
435 { "arch=", &ix86_arch_string, \
436 N_("Generate code for given CPU")}, \
437 { "regparm=", &ix86_regparm_string, \
438 N_("Number of registers used to pass integer arguments") }, \
439 { "align-loops=", &ix86_align_loops_string, \
440 N_("Loop code aligned to this power of 2") }, \
441 { "align-jumps=", &ix86_align_jumps_string, \
442 N_("Jump targets are aligned to this power of 2") }, \
443 { "align-functions=", &ix86_align_funcs_string, \
444 N_("Function starts are aligned to this power of 2") }, \
445 { "preferred-stack-boundary=", \
446 &ix86_preferred_stack_boundary_string, \
447 N_("Attempt to keep stack aligned to this power of 2") }, \
448 { "branch-cost=", &ix86_branch_cost_string, \
449 N_("Branches are this expensive (1-5, arbitrary units)") }, \
450 { "cmodel=", &ix86_cmodel_string, \
451 N_("Use given x86-64 code model") }, \
455 /* Sometimes certain combinations of command options do not make
456 sense on a particular target machine. You can define a macro
457 `OVERRIDE_OPTIONS' to take account of this. This macro, if
458 defined, is executed once just after all the command options have
461 Don't use this macro to turn on various extra optimizations for
462 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
464 #define OVERRIDE_OPTIONS override_options ()
466 /* These are meant to be redefined in the host dependent files */
467 #define SUBTARGET_SWITCHES
468 #define SUBTARGET_OPTIONS
470 /* Define this to change the optimizations performed by default. */
471 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
473 /* Specs for the compiler proper */
476 #define CC1_CPU_SPEC "\
479 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
481 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
482 %{mpentium:-mcpu=pentium \
483 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
484 %{mpentiumpro:-mcpu=pentiumpro \
485 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}}"
488 #define TARGET_CPU_DEFAULT_i386 0
489 #define TARGET_CPU_DEFAULT_i486 1
490 #define TARGET_CPU_DEFAULT_pentium 2
491 #define TARGET_CPU_DEFAULT_pentiumpro 3
492 #define TARGET_CPU_DEFAULT_pentium2 4
493 #define TARGET_CPU_DEFAULT_pentium3 5
494 #define TARGET_CPU_DEFAULT_pentium4 6
495 #define TARGET_CPU_DEFAULT_k6 7
496 #define TARGET_CPU_DEFAULT_k6_2 8
497 #define TARGET_CPU_DEFAULT_k6_3 9
498 #define TARGET_CPU_DEFAULT_athlon 10
499 #define TARGET_CPU_DEFAULT_athlon_sse 11
501 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
502 "pentiumpro", "pentium2", "pentium3", \
503 "pentium4", "k6", "k6-2", "k6-3",\
504 "athlon", "athlon-4"}
505 #ifndef CPP_CPU_DEFAULT_SPEC
506 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
507 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
509 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
510 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
512 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
513 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
515 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
516 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
518 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
519 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
522 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
523 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
524 -D__tune_pentium2__ -D__tune_pentium3__"
526 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
527 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
529 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
530 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
532 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
533 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
535 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
536 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
538 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
539 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
541 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
542 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
544 #ifndef CPP_CPU_DEFAULT_SPEC
545 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
547 #endif /* CPP_CPU_DEFAULT_SPEC */
549 #ifdef TARGET_BI_ARCH
550 #define NO_BUILTIN_SIZE_TYPE
551 #define NO_BUILTIN_PTRDIFF_TYPE
554 #ifdef NO_BUILTIN_SIZE_TYPE
555 #define CPP_CPU32_SIZE_TYPE_SPEC \
556 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
557 #define CPP_CPU64_SIZE_TYPE_SPEC \
558 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int"
560 #define CPP_CPU32_SIZE_TYPE_SPEC ""
561 #define CPP_CPU64_SIZE_TYPE_SPEC ""
564 #define CPP_CPU32_SPEC \
565 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
566 -D__i386__ %(cpp_cpu32sizet)"
568 #define CPP_CPU64_SPEC \
569 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)"
571 #define CPP_CPUCOMMON_SPEC "\
572 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
573 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
574 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
575 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
576 %{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
578 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
579 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
580 -D__pentiumpro -D__pentiumpro__ \
581 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
582 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
583 %{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
584 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
585 %{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
586 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
587 %{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
588 %{!mcpu*:-D__tune_athlon__ }}\
589 %{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
591 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
592 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
593 %{m386|mcpu=i386:-D__tune_i386__ }\
594 %{m486|mcpu=i486:-D__tune_i486__ }\
595 %{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
596 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
597 -D__tune_pentiumpro__ }\
598 %{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
599 %{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
601 %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
602 -D__tune_athlon_sse__ }\
603 %{mcpu=pentium4:-D__tune_pentium4__ }\
604 %{march=march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
606 %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
607 march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
608 |march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
609 %{march=k6-2|march=k6-3\
610 march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
611 |march=athlon-mp: -D__3dNOW__ }\
612 %{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
613 |march=athlon-mp: -D__3dNOW_A__ }\
614 %{march=mcpu=pentium4: -D__SSE2__ }\
615 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
618 #ifdef TARGET_BI_ARCH
619 #ifdef TARGET_64BIT_DEFAULT
620 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
622 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
625 #ifdef TARGET_64BIT_DEFAULT
626 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
628 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
634 #define CC1_SPEC "%(cc1_cpu) "
637 /* This macro defines names of additional specifications to put in the
638 specs that can be used in various specifications like CC1_SPEC. Its
639 definition is an initializer with a subgrouping for each command option.
641 Each subgrouping contains a string constant, that defines the
642 specification name, and a string constant that used by the GNU CC driver
645 Do not define this macro if it does not need to do anything. */
647 #ifndef SUBTARGET_EXTRA_SPECS
648 #define SUBTARGET_EXTRA_SPECS
651 #define EXTRA_SPECS \
652 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
653 { "cpp_cpu", CPP_CPU_SPEC }, \
654 { "cpp_cpu32", CPP_CPU32_SPEC }, \
655 { "cpp_cpu64", CPP_CPU64_SPEC }, \
656 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \
657 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \
658 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
659 { "cc1_cpu", CC1_CPU_SPEC }, \
660 SUBTARGET_EXTRA_SPECS
662 /* target machine storage layout */
664 /* Define for XFmode or TFmode extended real floating point support.
665 This will automatically cause REAL_ARITHMETIC to be defined.
667 The XFmode is specified by i386 ABI, while TFmode may be faster
668 due to alignment and simplifications in the address calculations.
670 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
671 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
673 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
675 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
677 /* Tell real.c that this is the 80-bit Intel extended float format
678 packaged in a 128-bit or 96bit entity. */
679 #define INTEL_EXTENDED_IEEE_FORMAT 1
682 #define SHORT_TYPE_SIZE 16
683 #define INT_TYPE_SIZE 32
684 #define FLOAT_TYPE_SIZE 32
685 #define LONG_TYPE_SIZE BITS_PER_WORD
686 #define MAX_WCHAR_TYPE_SIZE 32
687 #define DOUBLE_TYPE_SIZE 64
688 #define LONG_LONG_TYPE_SIZE 64
690 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
691 #define MAX_BITS_PER_WORD 64
692 #define MAX_LONG_TYPE_SIZE 64
694 #define MAX_BITS_PER_WORD 32
695 #define MAX_LONG_TYPE_SIZE 32
698 /* Define if you don't want extended real, but do want to use the
699 software floating point emulator for REAL_ARITHMETIC and
700 decimal <-> binary conversion. */
701 /* #define REAL_ARITHMETIC */
703 /* Define this if most significant byte of a word is the lowest numbered. */
704 /* That is true on the 80386. */
706 #define BITS_BIG_ENDIAN 0
708 /* Define this if most significant byte of a word is the lowest numbered. */
709 /* That is not true on the 80386. */
710 #define BYTES_BIG_ENDIAN 0
712 /* Define this if most significant word of a multiword number is the lowest
714 /* Not true for 80386 */
715 #define WORDS_BIG_ENDIAN 0
717 /* number of bits in an addressable storage unit */
718 #define BITS_PER_UNIT 8
720 /* Width in bits of a "word", which is the contents of a machine register.
721 Note that this is not necessarily the width of data type `int';
722 if using 16-bit ints on a 80386, this would still be 32.
723 But on a machine with 16-bit registers, this would be 16. */
724 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
726 /* Width of a word, in units (bytes). */
727 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
728 #define MIN_UNITS_PER_WORD 4
730 /* Width in bits of a pointer.
731 See also the macro `Pmode' defined below. */
732 #define POINTER_SIZE BITS_PER_WORD
734 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
735 #define PARM_BOUNDARY BITS_PER_WORD
737 /* Boundary (in *bits*) on which stack pointer should be aligned. */
738 #define STACK_BOUNDARY BITS_PER_WORD
740 /* Boundary (in *bits*) on which the stack pointer preferrs to be
741 aligned; the compiler cannot rely on having this alignment. */
742 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
744 /* As of July 2001, many runtimes to not align the stack properly when
745 entering main. This causes expand_main_function to forcably align
746 the stack, which results in aligned frames for functions called from
747 main, though it does nothing for the alignment of main itself. */
748 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
749 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
751 /* Allocation boundary for the code of a function. */
752 #define FUNCTION_BOUNDARY 16
754 /* Alignment of field after `int : 0' in a structure. */
756 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
758 /* Minimum size in bits of the largest boundary to which any
759 and all fundamental data types supported by the hardware
760 might need to be aligned. No data type wants to be aligned
763 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
764 and Pentium Pro XFmode values at 128 bit boundaries. */
766 #define BIGGEST_ALIGNMENT 128
768 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
769 #define ALIGN_MODE_128(MODE) \
770 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
771 || (MODE) == V4SFmode || (MODE) == V4SImode)
773 /* The published ABIs say that doubles should be aligned on word
774 boundaries, so lower the aligment for structure fields unless
775 -malign-double is set. */
776 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
777 constant. Use the smaller value in that context. */
778 #ifndef IN_TARGET_LIBS
779 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
781 #define BIGGEST_FIELD_ALIGNMENT 32
784 /* If defined, a C expression to compute the alignment given to a
785 constant that is being placed in memory. EXP is the constant
786 and ALIGN is the alignment that the object would ordinarily have.
787 The value of this macro is used instead of that alignment to align
790 If this macro is not defined, then ALIGN is used.
792 The typical use of this macro is to increase alignment for string
793 constants to be word aligned so that `strcpy' calls that copy
794 constants can be done inline. */
796 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment (EXP, ALIGN)
798 /* If defined, a C expression to compute the alignment for a static
799 variable. TYPE is the data type, and ALIGN is the alignment that
800 the object would ordinarily have. The value of this macro is used
801 instead of that alignment to align the object.
803 If this macro is not defined, then ALIGN is used.
805 One use of this macro is to increase alignment of medium-size
806 data to make it all fit in fewer cache lines. Another is to
807 cause character arrays to be word-aligned so that `strcpy' calls
808 that copy constants to character arrays can be done inline. */
810 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment (TYPE, ALIGN)
812 /* If defined, a C expression to compute the alignment for a local
813 variable. TYPE is the data type, and ALIGN is the alignment that
814 the object would ordinarily have. The value of this macro is used
815 instead of that alignment to align the object.
817 If this macro is not defined, then ALIGN is used.
819 One use of this macro is to increase alignment of medium-size
820 data to make it all fit in fewer cache lines. */
822 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment (TYPE, ALIGN)
824 /* If defined, a C expression that gives the alignment boundary, in
825 bits, of an argument with the specified mode and type. If it is
826 not defined, `PARM_BOUNDARY' is used for all arguments. */
828 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) ix86_function_arg_boundary (MODE, TYPE)
830 /* Set this non-zero if move instructions will actually fail to work
831 when given unaligned data. */
832 #define STRICT_ALIGNMENT 0
834 /* If bit field type is int, don't let it cross an int,
835 and give entire struct the alignment of an int. */
836 /* Required on the 386 since it doesn't have bitfield insns. */
837 #define PCC_BITFIELD_TYPE_MATTERS 1
839 /* Standard register usage. */
841 /* This processor has special stack-like registers. See reg-stack.c
845 #define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode \
846 || mode==XFmode || mode==TFmode)
848 /* Number of actual hardware registers.
849 The hardware registers are assigned numbers for the compiler
850 from 0 to just below FIRST_PSEUDO_REGISTER.
851 All registers that the compiler knows about must be given numbers,
852 even those that are not normally considered general registers.
854 In the 80386 we give the 8 general purpose registers the numbers 0-7.
855 We number the floating point registers 8-15.
856 Note that registers 0-7 can be accessed as a short or int,
857 while only 0-3 may be used with byte `mov' instructions.
859 Reg 16 does not correspond to any hardware register, but instead
860 appears in the RTL as an argument pointer prior to reload, and is
861 eliminated during reloading in favor of either the stack or frame
864 #define FIRST_PSEUDO_REGISTER 53
866 /* Number of hardware registers that go into the DWARF-2 unwind info.
867 If not defined, equals FIRST_PSEUDO_REGISTER. */
869 #define DWARF_FRAME_REGISTERS 17
871 /* 1 for registers that have pervasive standard uses
872 and are not available for the register allocator.
873 On the 80386, the stack pointer is such, as is the arg pointer.
875 The value is an mask - bit 1 is set for fixed registers
876 for 32bit target, while 2 is set for fixed registers for 64bit.
877 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
879 #define FIXED_REGISTERS \
880 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
881 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
882 /*arg,flags,fpsr,dir,frame*/ \
884 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
885 0, 0, 0, 0, 0, 0, 0, 0, \
886 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
887 0, 0, 0, 0, 0, 0, 0, 0, \
888 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
889 1, 1, 1, 1, 1, 1, 1, 1, \
890 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
891 1, 1, 1, 1, 1, 1, 1, 1}
894 /* 1 for registers not available across function calls.
895 These must include the FIXED_REGISTERS and also any
896 registers that can be used without being saved.
897 The latter must include the registers where values are returned
898 and the register where structure-value addresses are passed.
899 Aside from that, you can include as many other registers as you like.
901 The value is an mask - bit 1 is set for call used
902 for 32bit target, while 2 is set for call used for 64bit.
903 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
905 #define CALL_USED_REGISTERS \
906 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
907 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
908 /*arg,flags,fpsr,dir,frame*/ \
910 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
911 3, 3, 3, 3, 3, 3, 3, 3, \
912 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
913 3, 3, 3, 3, 3, 3, 3, 3, \
914 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
915 3, 3, 3, 3, 1, 1, 1, 1, \
916 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
917 3, 3, 3, 3, 3, 3, 3, 3} \
919 /* Order in which to allocate registers. Each register must be
920 listed once, even those in FIXED_REGISTERS. List frame pointer
921 late and fixed registers last. Note that, in general, we prefer
922 registers listed in CALL_USED_REGISTERS, keeping the others
923 available for storage of persistent values.
925 Three different versions of REG_ALLOC_ORDER have been tried:
927 If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
928 but slower code on simple functions returning values in eax.
930 If the order is eax, ecx, edx, ... it causes reload to abort when compiling
931 perl 4.036 due to not being able to create a DImode register (to hold a 2
934 If the order is eax, edx, ecx, ... it produces better code for simple
935 functions, and a slightly slower compiler. Users complained about the code
936 generated by allocating edx first, so restore the 'natural' order of things. */
938 #define REG_ALLOC_ORDER \
941 /* bx,si,di,bp,sp,*/ \
945 /*r12,r15,r14,r13*/ \
947 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
948 21, 22, 23, 24, 25, 26, 27, 28, \
949 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
950 45, 46, 47, 48, 49, 50, 51, 52, \
951 /*st,st1,st2,st3,st4,st5,st6,st7*/ \
952 8, 9, 10, 11, 12, 13, 14, 15, \
953 /*,arg,cc,fpsr,dir,frame*/ \
955 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
956 29, 30, 31, 32, 33, 34, 35, 36 }
958 /* Macro to conditionally modify fixed_regs/call_used_regs. */
959 #define CONDITIONAL_REGISTER_USAGE \
962 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
964 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
965 call_used_regs[i] = (call_used_regs[i] \
966 & (TARGET_64BIT ? 2 : 1)) != 0; \
970 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
971 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
976 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
977 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
978 fixed_regs[i] = call_used_regs[i] = 1; \
983 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
984 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
985 fixed_regs[i] = call_used_regs[i] = 1; \
987 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
991 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
992 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
993 if (TEST_HARD_REG_BIT (x, i)) \
994 fixed_regs[i] = call_used_regs[i] = 1; \
998 /* Return number of consecutive hard regs needed starting at reg REGNO
999 to hold something of mode MODE.
1000 This is ordinarily the length in words of a value of mode MODE
1001 but can be less for certain modes in special long registers.
1003 Actually there are no two word move instructions for consecutive
1004 registers. And only registers 0-3 may have mov byte instructions
1008 #define HARD_REGNO_NREGS(REGNO, MODE) \
1009 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1010 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1012 ? (TARGET_64BIT ? 2 : 3) \
1014 ? (TARGET_64BIT ? 4 : 6) \
1015 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1017 #define VALID_SSE_REG_MODE(MODE) \
1018 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1019 || (MODE) == SFmode \
1020 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
1022 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1023 ((MODE) == V2SFmode || (MODE) == SFmode)
1025 #define VALID_MMX_REG_MODE(MODE) \
1026 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1027 || (MODE) == V2SImode || (MODE) == SImode)
1029 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1030 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
1031 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
1032 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1034 #define VALID_FP_MODE_P(mode) \
1035 ((mode) == SFmode || (mode) == DFmode || (mode) == TFmode \
1036 || (!TARGET_64BIT && (mode) == XFmode) \
1037 || (mode) == SCmode || (mode) == DCmode || (mode) == TCmode\
1038 || (!TARGET_64BIT && (mode) == XCmode))
1040 #define VALID_INT_MODE_P(mode) \
1041 ((mode) == QImode || (mode) == HImode || (mode) == SImode \
1042 || (mode) == DImode \
1043 || (mode) == CQImode || (mode) == CHImode || (mode) == CSImode \
1044 || (mode) == CDImode \
1045 || (TARGET_64BIT && ((mode) == TImode || (mode) == CTImode)))
1047 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1049 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1050 ix86_hard_regno_mode_ok (REGNO, MODE)
1052 /* Value is 1 if it is a good idea to tie two pseudo registers
1053 when one has mode MODE1 and one has mode MODE2.
1054 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1055 for any hard reg, then this must be 0 for correct output. */
1057 #define MODES_TIEABLE_P(MODE1, MODE2) \
1058 ((MODE1) == (MODE2) \
1059 || (((MODE1) == HImode || (MODE1) == SImode \
1060 || ((MODE1) == QImode \
1061 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1062 || ((MODE1) == DImode && TARGET_64BIT)) \
1063 && ((MODE2) == HImode || (MODE2) == SImode \
1064 || ((MODE1) == QImode \
1065 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1066 || ((MODE2) == DImode && TARGET_64BIT))))
1069 /* Specify the modes required to caller save a given hard regno.
1070 We do this on i386 to prevent flags from being saved at all.
1072 Kill any attempts to combine saving of modes. */
1074 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1075 (CC_REGNO_P (REGNO) ? VOIDmode \
1076 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1077 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1078 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1079 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1081 /* Specify the registers used for certain standard purposes.
1082 The values of these macros are register numbers. */
1084 /* on the 386 the pc register is %eip, and is not usable as a general
1085 register. The ordinary mov instructions won't work */
1086 /* #define PC_REGNUM */
1088 /* Register to use for pushing function arguments. */
1089 #define STACK_POINTER_REGNUM 7
1091 /* Base register for access to local variables of the function. */
1092 #define HARD_FRAME_POINTER_REGNUM 6
1094 /* Base register for access to local variables of the function. */
1095 #define FRAME_POINTER_REGNUM 20
1097 /* First floating point reg */
1098 #define FIRST_FLOAT_REG 8
1100 /* First & last stack-like regs */
1101 #define FIRST_STACK_REG FIRST_FLOAT_REG
1102 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1104 #define FLAGS_REG 17
1106 #define DIRFLAG_REG 19
1108 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1109 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1111 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1112 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1114 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1115 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1117 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1118 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1120 /* Value should be nonzero if functions must have frame pointers.
1121 Zero means the frame pointer need not be set up (and parms
1122 may be accessed via the stack pointer) in functions that seem suitable.
1123 This is computed in `reload', in reload1.c. */
1124 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1126 /* Override this in other tm.h files to cope with various OS losage
1127 requiring a frame pointer. */
1128 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1129 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1132 /* Make sure we can access arbitrary call frames. */
1133 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1135 /* Base register for access to arguments of the function. */
1136 #define ARG_POINTER_REGNUM 16
1138 /* Register in which static-chain is passed to a function.
1139 We do use ECX as static chain register for 32 bit ABI. On the
1140 64bit ABI, ECX is an argument register, so we use R10 instead. */
1141 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1143 /* Register to hold the addressing base for position independent
1144 code access to data items.
1145 We don't use PIC pointer for 64bit mode. Define the regnum to
1146 dummy value to prevent gcc from pessimizing code dealing with EBX.
1148 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
1150 /* Register in which address to store a structure value
1151 arrives in the function. On the 386, the prologue
1152 copies this from the stack to register %eax. */
1153 #define STRUCT_VALUE_INCOMING 0
1155 /* Place in which caller passes the structure value address.
1156 0 means push the value on the stack like an argument. */
1157 #define STRUCT_VALUE 0
1159 /* A C expression which can inhibit the returning of certain function
1160 values in registers, based on the type of value. A nonzero value
1161 says to return the function value in memory, just as large
1162 structures are always returned. Here TYPE will be a C expression
1163 of type `tree', representing the data type of the value.
1165 Note that values of mode `BLKmode' must be explicitly handled by
1166 this macro. Also, the option `-fpcc-struct-return' takes effect
1167 regardless of this macro. On most systems, it is possible to
1168 leave the macro undefined; this causes a default definition to be
1169 used, whose value is the constant 1 for `BLKmode' values, and 0
1172 Do not use this macro to indicate that structures and unions
1173 should always be returned in memory. You should instead use
1174 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1176 #define RETURN_IN_MEMORY(TYPE) \
1177 ix86_return_in_memory (TYPE)
1180 /* Define the classes of registers for register constraints in the
1181 machine description. Also define ranges of constants.
1183 One of the classes must always be named ALL_REGS and include all hard regs.
1184 If there is more than one class, another class must be named NO_REGS
1185 and contain no registers.
1187 The name GENERAL_REGS must be the name of a class (or an alias for
1188 another name such as ALL_REGS). This is the class of registers
1189 that is allowed by "g" or "r" in a register constraint.
1190 Also, registers outside this class are allocated only when
1191 instructions express preferences for them.
1193 The classes must be numbered in nondecreasing order; that is,
1194 a larger-numbered class must never be contained completely
1195 in a smaller-numbered class.
1197 For any two classes, it is very desirable that there be another
1198 class that represents their union.
1200 It might seem that class BREG is unnecessary, since no useful 386
1201 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1202 and the "b" register constraint is useful in asms for syscalls.
1204 The flags and fpsr registers are in no class. */
1209 AREG, DREG, CREG, BREG, SIREG, DIREG,
1210 AD_REGS, /* %eax/%edx for DImode */
1211 Q_REGS, /* %eax %ebx %ecx %edx */
1212 NON_Q_REGS, /* %esi %edi %ebp %esp */
1213 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1214 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1215 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1216 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1226 ALL_REGS, LIM_REG_CLASSES
1229 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1231 #define INTEGER_CLASS_P(CLASS) (reg_class_subset_p (CLASS, GENERAL_REGS))
1232 #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
1233 #define SSE_CLASS_P(CLASS) (reg_class_subset_p (CLASS, SSE_REGS))
1234 #define MMX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, MMX_REGS))
1235 #define MAYBE_INTEGER_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, GENERAL_REGS))
1236 #define MAYBE_FLOAT_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, FLOAT_REGS))
1237 #define MAYBE_SSE_CLASS_P(CLASS) (reg_classes_intersect_p (SSE_REGS, CLASS))
1238 #define MAYBE_MMX_CLASS_P(CLASS) (reg_classes_intersect_p (MMX_REGS, CLASS))
1240 #define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS))
1242 /* Give names of register classes as strings for dump file. */
1244 #define REG_CLASS_NAMES \
1246 "AREG", "DREG", "CREG", "BREG", \
1249 "Q_REGS", "NON_Q_REGS", \
1253 "FP_TOP_REG", "FP_SECOND_REG", \
1257 "FP_TOP_SSE_REGS", \
1258 "FP_SECOND_SSE_REGS", \
1262 "FLOAT_INT_SSE_REGS", \
1265 /* Define which registers fit in which classes.
1266 This is an initializer for a vector of HARD_REG_SET
1267 of length N_REG_CLASSES. */
1269 #define REG_CLASS_CONTENTS \
1271 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1272 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1273 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1274 { 0x03, 0x0 }, /* AD_REGS */ \
1275 { 0x0f, 0x0 }, /* Q_REGS */ \
1276 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1277 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1278 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1279 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1280 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1281 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1282 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1283 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1284 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1285 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1286 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1287 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1288 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1289 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1290 { 0xffffffff,0x1fffff } \
1293 /* The same information, inverted:
1294 Return the class number of the smallest class containing
1295 reg number REGNO. This could be a conditional expression
1296 or could index an array. */
1298 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1300 /* When defined, the compiler allows registers explicitly used in the
1301 rtl to be used as spill registers but prevents the compiler from
1302 extending the lifetime of these registers. */
1304 #define SMALL_REGISTER_CLASSES 1
1306 #define QI_REG_P(X) \
1307 (REG_P (X) && REGNO (X) < 4)
1309 #define GENERAL_REGNO_P(n) \
1310 ((n) < 8 || REX_INT_REGNO_P (n))
1312 #define GENERAL_REG_P(X) \
1313 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1315 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1317 #define NON_QI_REG_P(X) \
1318 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1320 #define REX_INT_REGNO_P(n) ((n) >= FIRST_REX_INT_REG && (n) <= LAST_REX_INT_REG)
1321 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1323 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1324 #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
1325 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1326 #define ANY_FP_REGNO_P(n) (FP_REGNO_P (n) || SSE_REGNO_P (n))
1328 #define SSE_REGNO_P(n) \
1329 (((n) >= FIRST_SSE_REG && (n) <= LAST_SSE_REG) \
1330 || ((n) >= FIRST_REX_SSE_REG && (n) <= LAST_REX_SSE_REG))
1332 #define SSE_REGNO(n) \
1333 ((n) < 8 ? FIRST_SSE_REG + (n) : FIRST_REX_SSE_REG + (n) - 8)
1334 #define SSE_REG_P(n) (REG_P (n) && SSE_REGNO_P (REGNO (n)))
1336 #define SSE_FLOAT_MODE_P(m) \
1337 ((TARGET_SSE_MATH && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
1339 #define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
1340 #define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
1342 #define STACK_REG_P(xop) (REG_P (xop) && \
1343 REGNO (xop) >= FIRST_STACK_REG && \
1344 REGNO (xop) <= LAST_STACK_REG)
1346 #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
1348 #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
1350 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1351 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1353 /* Indicate whether hard register numbered REG_NO should be converted
1355 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1356 (REG_NO == FLAGS_REG || REG_NO == ARG_POINTER_REGNUM)
1358 /* The class value for index registers, and the one for base regs. */
1360 #define INDEX_REG_CLASS INDEX_REGS
1361 #define BASE_REG_CLASS GENERAL_REGS
1363 /* Get reg_class from a letter such as appears in the machine description. */
1365 #define REG_CLASS_FROM_LETTER(C) \
1366 ((C) == 'r' ? GENERAL_REGS : \
1367 (C) == 'R' ? LEGACY_REGS : \
1368 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1369 (C) == 'Q' ? Q_REGS : \
1370 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1373 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1376 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1379 (C) == 'a' ? AREG : \
1380 (C) == 'b' ? BREG : \
1381 (C) == 'c' ? CREG : \
1382 (C) == 'd' ? DREG : \
1383 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1384 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1385 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1386 (C) == 'A' ? AD_REGS : \
1387 (C) == 'D' ? DIREG : \
1388 (C) == 'S' ? SIREG : NO_REGS)
1390 /* The letters I, J, K, L and M in a register constraint string
1391 can be used to stand for particular ranges of immediate operands.
1392 This macro defines what the ranges are.
1393 C is the letter, and VALUE is a constant value.
1394 Return 1 if VALUE is in the range specified by C.
1396 I is for non-DImode shifts.
1397 J is for DImode shifts.
1398 K is for signed imm8 operands.
1399 L is for andsi as zero-extending move.
1400 M is for shifts that can be executed by the "lea" opcode.
1401 N is for immedaite operands for out/in instructions (0-255)
1404 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1405 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1406 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1407 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1408 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1409 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1410 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1413 /* Similar, but for floating constants, and defining letters G and H.
1414 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1415 TARGET_387 isn't set, because the stack register converter may need to
1416 load 0.0 into the function value register. */
1418 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1419 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1420 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1422 /* A C expression that defines the optional machine-dependent
1423 constraint letters that can be used to segregate specific types of
1424 operands, usually memory references, for the target machine. Any
1425 letter that is not elsewhere defined and not matched by
1426 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1429 If it is required for a particular target machine, it should
1430 return 1 if VALUE corresponds to the operand type represented by
1431 the constraint letter C. If C is not defined as an extra
1432 constraint, the value returned should be 0 regardless of VALUE. */
1434 #define EXTRA_CONSTRAINT(VALUE, C) \
1435 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1436 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1439 /* Place additional restrictions on the register class to use when it
1440 is necessary to be able to hold a value of mode MODE in a reload
1441 register for which class CLASS would ordinarily be used. */
1443 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1444 ((MODE) == QImode && !TARGET_64BIT \
1445 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
1448 /* Given an rtx X being reloaded into a reg required to be
1449 in class CLASS, return the class of reg to actually use.
1450 In general this is just CLASS; but on some machines
1451 in some cases it is preferable to use a more restrictive class.
1452 On the 80386 series, we prevent floating constants from being
1453 reloaded into floating registers (since no move-insn can do that)
1454 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1456 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1457 QImode must go into class Q_REGS.
1458 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1459 movdf to do mem-to-mem moves through integer regs. */
1461 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1462 ix86_preferred_reload_class (X, CLASS)
1464 /* If we are copying between general and FP registers, we need a memory
1465 location. The same is true for SSE and MMX registers. */
1466 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1467 ix86_secondary_memory_needed (CLASS1, CLASS2, MODE, 1)
1469 /* QImode spills from non-QI registers need a scratch. This does not
1470 happen often -- the only example so far requires an uninitialized
1473 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
1474 ((CLASS) == GENERAL_REGS && !TARGET_64BIT && (MODE) == QImode \
1477 /* Return the maximum number of consecutive registers
1478 needed to represent mode MODE in a register of class CLASS. */
1479 /* On the 80386, this is the size of MODE in words,
1480 except in the FP regs, where a single reg is always enough.
1481 The TFmodes are really just 80bit values, so we use only 3 registers
1482 to hold them, instead of 4, as the size would suggest.
1484 #define CLASS_MAX_NREGS(CLASS, MODE) \
1485 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1486 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1487 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1488 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1490 /* A C expression whose value is nonzero if pseudos that have been
1491 assigned to registers of class CLASS would likely be spilled
1492 because registers of CLASS are needed for spill registers.
1494 The default value of this macro returns 1 if CLASS has exactly one
1495 register and zero otherwise. On most machines, this default
1496 should be used. Only define this macro to some other expression
1497 if pseudo allocated by `local-alloc.c' end up in memory because
1498 their hard registers were needed for spill registers. If this
1499 macro returns nonzero for those classes, those pseudos will only
1500 be allocated by `global.c', which knows how to reallocate the
1501 pseudo to another register. If there would not be another
1502 register available for reallocation, you should not change the
1503 definition of this macro since the only effect of such a
1504 definition would be to slow down register allocation. */
1506 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1507 (((CLASS) == AREG) \
1508 || ((CLASS) == DREG) \
1509 || ((CLASS) == CREG) \
1510 || ((CLASS) == BREG) \
1511 || ((CLASS) == AD_REGS) \
1512 || ((CLASS) == SIREG) \
1513 || ((CLASS) == DIREG))
1515 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1516 to automatically clobber for all asms.
1518 We do this in the new i386 backend to maintain source compatibility
1519 with the old cc0-based compiler. */
1521 #define MD_ASM_CLOBBERS(CLOBBERS) \
1523 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), (CLOBBERS));\
1524 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), (CLOBBERS)); \
1525 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), (CLOBBERS)); \
1528 /* Stack layout; function entry, exit and calling. */
1530 /* Define this if pushing a word on the stack
1531 makes the stack pointer a smaller address. */
1532 #define STACK_GROWS_DOWNWARD
1534 /* Define this if the nominal address of the stack frame
1535 is at the high-address end of the local variables;
1536 that is, each additional local variable allocated
1537 goes at a more negative offset in the frame. */
1538 #define FRAME_GROWS_DOWNWARD
1540 /* Offset within stack frame to start allocating local variables at.
1541 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1542 first local allocated. Otherwise, it is the offset to the BEGINNING
1543 of the first local allocated. */
1544 #define STARTING_FRAME_OFFSET 0
1546 /* If we generate an insn to push BYTES bytes,
1547 this says how many the stack pointer really advances by.
1548 On 386 pushw decrements by exactly 2 no matter what the position was.
1549 On the 386 there is no pushb; we use pushw instead, and this
1550 has the effect of rounding up to 2.
1552 For 64bit ABI we round up to 8 bytes.
1555 #define PUSH_ROUNDING(BYTES) \
1557 ? (((BYTES) + 7) & (-8)) \
1558 : (((BYTES) + 1) & (-2)))
1560 /* If defined, the maximum amount of space required for outgoing arguments will
1561 be computed and placed into the variable
1562 `current_function_outgoing_args_size'. No space will be pushed onto the
1563 stack for each call; instead, the function prologue should increase the stack
1564 frame size by this amount. */
1566 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1568 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1569 instructions to pass outgoing arguments. */
1571 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1573 /* Offset of first parameter from the argument pointer register value. */
1574 #define FIRST_PARM_OFFSET(FNDECL) 0
1576 /* Define this macro if functions should assume that stack space has been
1577 allocated for arguments even when their values are passed in registers.
1579 The value of this macro is the size, in bytes, of the area reserved for
1580 arguments passed in registers for the function represented by FNDECL.
1582 This space can be allocated by the caller, or be a part of the
1583 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1585 #define REG_PARM_STACK_SPACE(FNDECL) 0
1587 /* Define as a C expression that evaluates to nonzero if we do not know how
1588 to pass TYPE solely in registers. The file expr.h defines a
1589 definition that is usually appropriate, refer to expr.h for additional
1590 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1591 computed in the stack and then loaded into a register. */
1592 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1594 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1595 || TREE_ADDRESSABLE (TYPE) \
1596 || ((MODE) == TImode) \
1597 || ((MODE) == BLKmode \
1598 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1599 && 0 == (int_size_in_bytes (TYPE) \
1600 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1601 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1602 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1604 /* Value is the number of bytes of arguments automatically
1605 popped when returning from a subroutine call.
1606 FUNDECL is the declaration node of the function (as a tree),
1607 FUNTYPE is the data type of the function (as a tree),
1608 or for a library call it is an identifier node for the subroutine name.
1609 SIZE is the number of bytes of arguments passed on the stack.
1611 On the 80386, the RTD insn may be used to pop them if the number
1612 of args is fixed, but if the number is variable then the caller
1613 must pop them all. RTD can't be used for library calls now
1614 because the library is compiled with the Unix compiler.
1615 Use of RTD is a selectable option, since it is incompatible with
1616 standard Unix calling sequences. If the option is not selected,
1617 the caller must always pop the args.
1619 The attribute stdcall is equivalent to RTD on a per module basis. */
1621 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
1622 (ix86_return_pops_args (FUNDECL, FUNTYPE, SIZE))
1624 /* Define how to find the value returned by a function.
1625 VALTYPE is the data type of the value (as a tree).
1626 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1627 otherwise, FUNC is 0. */
1628 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1629 ix86_function_value (VALTYPE)
1631 #define FUNCTION_VALUE_REGNO_P(N) \
1632 ix86_function_value_regno_p (N)
1634 /* Define how to find the value returned by a library function
1635 assuming the value has mode MODE. */
1637 #define LIBCALL_VALUE(MODE) \
1638 ix86_libcall_value (MODE)
1640 /* Define the size of the result block used for communication between
1641 untyped_call and untyped_return. The block contains a DImode value
1642 followed by the block used by fnsave and frstor. */
1644 #define APPLY_RESULT_SIZE (8+108)
1646 /* 1 if N is a possible register number for function argument passing. */
1647 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1649 /* Define a data type for recording info about an argument list
1650 during the scan of that argument list. This data type should
1651 hold all necessary information about the function itself
1652 and about the args processed so far, enough to enable macros
1653 such as FUNCTION_ARG to determine where the next arg should go. */
1655 typedef struct ix86_args {
1656 int words; /* # words passed so far */
1657 int nregs; /* # registers available for passing */
1658 int regno; /* next available register number */
1659 int sse_words; /* # sse words passed so far */
1660 int sse_nregs; /* # sse registers available for passing */
1661 int sse_regno; /* next available sse register number */
1662 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1665 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1666 for a call to a function whose data type is FNTYPE.
1667 For a library call, FNTYPE is 0. */
1669 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1670 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1672 /* Update the data in CUM to advance over an argument
1673 of mode MODE and data type TYPE.
1674 (TYPE is null for libcalls where that information may not be available.) */
1676 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1677 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
1679 /* Define where to put the arguments to a function.
1680 Value is zero to push the argument on the stack,
1681 or a hard register in which to store the argument.
1683 MODE is the argument's machine mode.
1684 TYPE is the data type of the argument (as a tree).
1685 This is null for libcalls where that information may
1687 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1688 the preceding args and about the function being called.
1689 NAMED is nonzero if this argument is a named parameter
1690 (otherwise it is an extra parameter matching an ellipsis). */
1692 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1693 (function_arg (&CUM, MODE, TYPE, NAMED))
1695 /* For an arg passed partly in registers and partly in memory,
1696 this is the number of registers used.
1697 For args passed entirely in registers or entirely in memory, zero. */
1699 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1701 /* If PIC, we cannot make sibling calls to global functions
1702 because the PLT requires %ebx live.
1703 If we are returning floats on the register stack, we cannot make
1704 sibling calls to functions that return floats. (The stack adjust
1705 instruction will wind up after the sibcall jump, and not be executed.) */
1706 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1708 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1709 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1710 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1711 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1713 /* Perform any needed actions needed for a function that is receiving a
1714 variable number of arguments.
1718 MODE and TYPE are the mode and type of the current parameter.
1720 PRETEND_SIZE is a variable that should be set to the amount of stack
1721 that must be pushed by the prolog to pretend that our caller pushed
1724 Normally, this macro will push all remaining incoming registers on the
1725 stack and set PRETEND_SIZE to the length of the registers pushed. */
1727 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1728 ix86_setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1730 /* Define the `__builtin_va_list' type for the ABI. */
1731 #define BUILD_VA_LIST_TYPE(VALIST) \
1732 (VALIST) = ix86_build_va_list ()
1734 /* Implement `va_start' for varargs and stdarg. */
1735 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1736 ix86_va_start (stdarg, valist, nextarg)
1738 /* Implement `va_arg'. */
1739 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1740 ix86_va_arg (valist, type)
1742 /* This macro is invoked at the end of compilation. It is used here to
1743 output code for -fpic that will load the return address into %ebx. */
1746 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1748 /* Output assembler code to FILE to increment profiler label # LABELNO
1749 for profiling a function entry. */
1751 #define FUNCTION_PROFILER(FILE, LABELNO) \
1755 fprintf (FILE, "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1756 LPREFIX, (LABELNO)); \
1757 fprintf (FILE, "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1761 fprintf (FILE, "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1762 fprintf (FILE, "\tcall\t_mcount\n"); \
1766 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1767 the stack pointer does not matter. The value is tested only in
1768 functions that have frame pointers.
1769 No definition is equivalent to always zero. */
1770 /* Note on the 386 it might be more efficient not to define this since
1771 we have to restore it ourselves from the frame pointer, in order to
1774 #define EXIT_IGNORE_STACK 1
1776 /* Output assembler code for a block containing the constant parts
1777 of a trampoline, leaving space for the variable parts. */
1779 /* On the 386, the trampoline contains two instructions:
1782 The trampoline is generated entirely at runtime. The operand of JMP
1783 is the address of FUNCTION relative to the instruction following the
1784 JMP (which is 5 bytes long). */
1786 /* Length in units of the trampoline for entering a nested function. */
1788 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1790 /* Emit RTL insns to initialize the variable parts of a trampoline.
1791 FNADDR is an RTX for the address of the function's pure code.
1792 CXT is an RTX for the static chain value for the function. */
1794 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1795 x86_initialize_trampoline (TRAMP, FNADDR, CXT)
1797 /* Definitions for register eliminations.
1799 This is an array of structures. Each structure initializes one pair
1800 of eliminable registers. The "from" register number is given first,
1801 followed by "to". Eliminations of the same "from" register are listed
1802 in order of preference.
1804 There are two registers that can always be eliminated on the i386.
1805 The frame pointer and the arg pointer can be replaced by either the
1806 hard frame pointer or to the stack pointer, depending upon the
1807 circumstances. The hard frame pointer is not used before reload and
1808 so it is not eligible for elimination. */
1810 #define ELIMINABLE_REGS \
1811 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1812 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1813 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1814 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1816 /* Given FROM and TO register numbers, say whether this elimination is
1817 allowed. Frame pointer elimination is automatically handled.
1819 All other eliminations are valid. */
1821 #define CAN_ELIMINATE(FROM, TO) \
1822 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1824 /* Define the offset between two registers, one to be eliminated, and the other
1825 its replacement, at the start of a routine. */
1827 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1828 (OFFSET) = ix86_initial_elimination_offset (FROM, TO)
1830 /* Addressing modes, and classification of registers for them. */
1832 /* #define HAVE_POST_INCREMENT 0 */
1833 /* #define HAVE_POST_DECREMENT 0 */
1835 /* #define HAVE_PRE_DECREMENT 0 */
1836 /* #define HAVE_PRE_INCREMENT 0 */
1838 /* Macros to check register numbers against specific register classes. */
1840 /* These assume that REGNO is a hard or pseudo reg number.
1841 They give nonzero only if REGNO is a hard reg of the suitable class
1842 or a pseudo reg currently allocated to a suitable hard reg.
1843 Since they use reg_renumber, they are safe only once reg_renumber
1844 has been allocated, which happens in local-alloc.c. */
1846 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1847 ((REGNO) < STACK_POINTER_REGNUM \
1848 || (REGNO >= FIRST_REX_INT_REG \
1849 && (REGNO) <= LAST_REX_INT_REG) \
1850 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1851 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1852 || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
1854 #define REGNO_OK_FOR_BASE_P(REGNO) \
1855 ((REGNO) <= STACK_POINTER_REGNUM \
1856 || (REGNO) == ARG_POINTER_REGNUM \
1857 || (REGNO) == FRAME_POINTER_REGNUM \
1858 || (REGNO >= FIRST_REX_INT_REG \
1859 && (REGNO) <= LAST_REX_INT_REG) \
1860 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1861 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1862 || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
1864 #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
1865 #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
1867 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1868 and check its validity for a certain class.
1869 We have two alternate definitions for each of them.
1870 The usual definition accepts all pseudo regs; the other rejects
1871 them unless they have been allocated suitable hard regs.
1872 The symbol REG_OK_STRICT causes the latter definition to be used.
1874 Most source files want to accept pseudo regs in the hope that
1875 they will get allocated to the class that the insn wants them to be in.
1876 Source files for reload pass need to be strict.
1877 After reload, it makes no difference, since pseudo regs have
1878 been eliminated by then. */
1881 /* Non strict versions, pseudos are ok */
1882 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1883 (REGNO (X) < STACK_POINTER_REGNUM \
1884 || (REGNO (X) >= FIRST_REX_INT_REG \
1885 && REGNO (X) <= LAST_REX_INT_REG) \
1886 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1888 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1889 (REGNO (X) <= STACK_POINTER_REGNUM \
1890 || REGNO (X) == ARG_POINTER_REGNUM \
1891 || REGNO (X) == FRAME_POINTER_REGNUM \
1892 || (REGNO (X) >= FIRST_REX_INT_REG \
1893 && REGNO (X) <= LAST_REX_INT_REG) \
1894 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1896 /* Strict versions, hard registers only */
1897 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1898 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1900 #ifndef REG_OK_STRICT
1901 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1902 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1905 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1906 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1909 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1910 that is a valid memory address for an instruction.
1911 The MODE argument is the machine mode for the MEM expression
1912 that wants to use this address.
1914 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1915 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1917 See legitimize_pic_address in i386.c for details as to what
1918 constitutes a legitimate address when -fpic is used. */
1920 #define MAX_REGS_PER_ADDRESS 2
1922 #define CONSTANT_ADDRESS_P(X) \
1923 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1924 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1925 || GET_CODE (X) == CONST_DOUBLE)
1927 /* Nonzero if the constant value X is a legitimate general operand.
1928 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1930 #define LEGITIMATE_CONSTANT_P(X) 1
1932 #ifdef REG_OK_STRICT
1933 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1935 if (legitimate_address_p (MODE, X, 1)) \
1940 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1942 if (legitimate_address_p (MODE, X, 0)) \
1948 /* If defined, a C expression to determine the base term of address X.
1949 This macro is used in only one place: `find_base_term' in alias.c.
1951 It is always safe for this macro to not be defined. It exists so
1952 that alias analysis can understand machine-dependent addresses.
1954 The typical use of this macro is to handle addresses containing
1955 a label_ref or symbol_ref within an UNSPEC. */
1957 #define FIND_BASE_TERM(X) ix86_find_base_term (x)
1959 /* Try machine-dependent ways of modifying an illegitimate address
1960 to be legitimate. If we find one, return the new, valid address.
1961 This macro is used in only one place: `memory_address' in explow.c.
1963 OLDX is the address as it was before break_out_memory_refs was called.
1964 In some cases it is useful to look at this to decide what needs to be done.
1966 MODE and WIN are passed so that this macro can use
1967 GO_IF_LEGITIMATE_ADDRESS.
1969 It is always safe for this macro to do nothing. It exists to recognize
1970 opportunities to optimize the output.
1972 For the 80386, we handle X+REG by loading X into a register R and
1973 using R+REG. R will go in a general reg and indexing will be used.
1974 However, if REG is a broken-out memory address or multiplication,
1975 nothing needs to be done because REG can certainly go in a general reg.
1977 When -fpic is used, special handling is needed for symbolic references.
1978 See comments by legitimize_pic_address in i386.c for details. */
1980 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1982 (X) = legitimize_address (X, OLDX, MODE); \
1983 if (memory_address_p (MODE, X)) \
1987 #define REWRITE_ADDRESS(x) rewrite_address(x)
1989 /* Nonzero if the constant value X is a legitimate general operand
1990 when generating PIC code. It is given that flag_pic is on and
1991 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1993 #define LEGITIMATE_PIC_OPERAND_P(X) \
1994 (! SYMBOLIC_CONST (X) \
1995 || legitimate_pic_address_disp_p (X))
1997 #define SYMBOLIC_CONST(X) \
1998 (GET_CODE (X) == SYMBOL_REF \
1999 || GET_CODE (X) == LABEL_REF \
2000 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2002 /* Go to LABEL if ADDR (a legitimate address expression)
2003 has an effect that depends on the machine mode it is used for.
2004 On the 80386, only postdecrement and postincrement address depend thus
2005 (the amount of decrement or increment being the length of the operand). */
2006 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2007 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
2009 /* Codes for all the SSE/MMX builtins. */
2021 IX86_BUILTIN_CMPEQPS,
2022 IX86_BUILTIN_CMPLTPS,
2023 IX86_BUILTIN_CMPLEPS,
2024 IX86_BUILTIN_CMPGTPS,
2025 IX86_BUILTIN_CMPGEPS,
2026 IX86_BUILTIN_CMPNEQPS,
2027 IX86_BUILTIN_CMPNLTPS,
2028 IX86_BUILTIN_CMPNLEPS,
2029 IX86_BUILTIN_CMPNGTPS,
2030 IX86_BUILTIN_CMPNGEPS,
2031 IX86_BUILTIN_CMPORDPS,
2032 IX86_BUILTIN_CMPUNORDPS,
2033 IX86_BUILTIN_CMPNEPS,
2034 IX86_BUILTIN_CMPEQSS,
2035 IX86_BUILTIN_CMPLTSS,
2036 IX86_BUILTIN_CMPLESS,
2037 IX86_BUILTIN_CMPGTSS,
2038 IX86_BUILTIN_CMPGESS,
2039 IX86_BUILTIN_CMPNEQSS,
2040 IX86_BUILTIN_CMPNLTSS,
2041 IX86_BUILTIN_CMPNLESS,
2042 IX86_BUILTIN_CMPNGTSS,
2043 IX86_BUILTIN_CMPNGESS,
2044 IX86_BUILTIN_CMPORDSS,
2045 IX86_BUILTIN_CMPUNORDSS,
2046 IX86_BUILTIN_CMPNESS,
2048 IX86_BUILTIN_COMIEQSS,
2049 IX86_BUILTIN_COMILTSS,
2050 IX86_BUILTIN_COMILESS,
2051 IX86_BUILTIN_COMIGTSS,
2052 IX86_BUILTIN_COMIGESS,
2053 IX86_BUILTIN_COMINEQSS,
2054 IX86_BUILTIN_UCOMIEQSS,
2055 IX86_BUILTIN_UCOMILTSS,
2056 IX86_BUILTIN_UCOMILESS,
2057 IX86_BUILTIN_UCOMIGTSS,
2058 IX86_BUILTIN_UCOMIGESS,
2059 IX86_BUILTIN_UCOMINEQSS,
2061 IX86_BUILTIN_CVTPI2PS,
2062 IX86_BUILTIN_CVTPS2PI,
2063 IX86_BUILTIN_CVTSI2SS,
2064 IX86_BUILTIN_CVTSS2SI,
2065 IX86_BUILTIN_CVTTPS2PI,
2066 IX86_BUILTIN_CVTTSS2SI,
2067 IX86_BUILTIN_M_FROM_INT,
2068 IX86_BUILTIN_M_TO_INT,
2075 IX86_BUILTIN_LOADAPS,
2076 IX86_BUILTIN_LOADUPS,
2077 IX86_BUILTIN_STOREAPS,
2078 IX86_BUILTIN_STOREUPS,
2079 IX86_BUILTIN_LOADSS,
2080 IX86_BUILTIN_STORESS,
2083 IX86_BUILTIN_MOVHLPS,
2084 IX86_BUILTIN_MOVLHPS,
2085 IX86_BUILTIN_LOADHPS,
2086 IX86_BUILTIN_LOADLPS,
2087 IX86_BUILTIN_STOREHPS,
2088 IX86_BUILTIN_STORELPS,
2090 IX86_BUILTIN_MASKMOVQ,
2091 IX86_BUILTIN_MOVMSKPS,
2092 IX86_BUILTIN_PMOVMSKB,
2094 IX86_BUILTIN_MOVNTPS,
2095 IX86_BUILTIN_MOVNTQ,
2097 IX86_BUILTIN_PACKSSWB,
2098 IX86_BUILTIN_PACKSSDW,
2099 IX86_BUILTIN_PACKUSWB,
2104 IX86_BUILTIN_PADDSB,
2105 IX86_BUILTIN_PADDSW,
2106 IX86_BUILTIN_PADDUSB,
2107 IX86_BUILTIN_PADDUSW,
2111 IX86_BUILTIN_PSUBSB,
2112 IX86_BUILTIN_PSUBSW,
2113 IX86_BUILTIN_PSUBUSB,
2114 IX86_BUILTIN_PSUBUSW,
2124 IX86_BUILTIN_PCMPEQB,
2125 IX86_BUILTIN_PCMPEQW,
2126 IX86_BUILTIN_PCMPEQD,
2127 IX86_BUILTIN_PCMPGTB,
2128 IX86_BUILTIN_PCMPGTW,
2129 IX86_BUILTIN_PCMPGTD,
2131 IX86_BUILTIN_PEXTRW,
2132 IX86_BUILTIN_PINSRW,
2134 IX86_BUILTIN_PMADDWD,
2136 IX86_BUILTIN_PMAXSW,
2137 IX86_BUILTIN_PMAXUB,
2138 IX86_BUILTIN_PMINSW,
2139 IX86_BUILTIN_PMINUB,
2141 IX86_BUILTIN_PMULHUW,
2142 IX86_BUILTIN_PMULHW,
2143 IX86_BUILTIN_PMULLW,
2145 IX86_BUILTIN_PSADBW,
2146 IX86_BUILTIN_PSHUFW,
2156 IX86_BUILTIN_PSLLWI,
2157 IX86_BUILTIN_PSLLDI,
2158 IX86_BUILTIN_PSLLQI,
2159 IX86_BUILTIN_PSRAWI,
2160 IX86_BUILTIN_PSRADI,
2161 IX86_BUILTIN_PSRLWI,
2162 IX86_BUILTIN_PSRLDI,
2163 IX86_BUILTIN_PSRLQI,
2165 IX86_BUILTIN_PUNPCKHBW,
2166 IX86_BUILTIN_PUNPCKHWD,
2167 IX86_BUILTIN_PUNPCKHDQ,
2168 IX86_BUILTIN_PUNPCKLBW,
2169 IX86_BUILTIN_PUNPCKLWD,
2170 IX86_BUILTIN_PUNPCKLDQ,
2172 IX86_BUILTIN_SHUFPS,
2176 IX86_BUILTIN_RSQRTPS,
2177 IX86_BUILTIN_RSQRTSS,
2178 IX86_BUILTIN_SQRTPS,
2179 IX86_BUILTIN_SQRTSS,
2181 IX86_BUILTIN_UNPCKHPS,
2182 IX86_BUILTIN_UNPCKLPS,
2185 IX86_BUILTIN_ANDNPS,
2190 IX86_BUILTIN_LDMXCSR,
2191 IX86_BUILTIN_STMXCSR,
2192 IX86_BUILTIN_SFENCE,
2193 IX86_BUILTIN_PREFETCH,
2195 /* 3DNow! Original */
2197 IX86_BUILTIN_PAVGUSB,
2201 IX86_BUILTIN_PFCMPEQ,
2202 IX86_BUILTIN_PFCMPGE,
2203 IX86_BUILTIN_PFCMPGT,
2208 IX86_BUILTIN_PFRCPIT1,
2209 IX86_BUILTIN_PFRCPIT2,
2210 IX86_BUILTIN_PFRSQIT1,
2211 IX86_BUILTIN_PFRSQRT,
2213 IX86_BUILTIN_PFSUBR,
2215 IX86_BUILTIN_PMULHRW,
2216 IX86_BUILTIN_PREFETCH_3DNOW, /* PREFETCH already used */
2217 IX86_BUILTIN_PREFETCHW,
2219 /* 3DNow! Athlon Extensions */
2221 IX86_BUILTIN_PFNACC,
2222 IX86_BUILTIN_PFPNACC,
2224 IX86_BUILTIN_PSWAPDSI,
2225 IX86_BUILTIN_PSWAPDSF,
2227 /* Composite builtins, expand to more than one insn. */
2228 IX86_BUILTIN_SETPS1,
2231 IX86_BUILTIN_SETRPS,
2232 IX86_BUILTIN_LOADPS1,
2233 IX86_BUILTIN_LOADRPS,
2234 IX86_BUILTIN_STOREPS1,
2235 IX86_BUILTIN_STORERPS,
2237 IX86_BUILTIN_MMX_ZERO,
2242 /* Define this macro if references to a symbol must be treated
2243 differently depending on something about the variable or
2244 function named by the symbol (such as what section it is in).
2246 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2247 so that we may access it directly in the GOT. */
2249 #define ENCODE_SECTION_INFO(DECL) \
2254 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2255 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2257 if (GET_CODE (rtl) == MEM) \
2259 if (TARGET_DEBUG_ADDR \
2260 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2262 fprintf (stderr, "Encode %s, public = %d\n", \
2263 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2264 TREE_PUBLIC (DECL)); \
2267 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2268 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2269 || ! TREE_PUBLIC (DECL)); \
2275 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2276 codes once the function is being compiled into assembly code, but
2277 not before. (It is not done before, because in the case of
2278 compiling an inline function, it would lead to multiple PIC
2279 prologues being included in functions which used inline functions
2280 and were compiled to assembly language.) */
2282 #define FINALIZE_PIC \
2285 current_function_uses_pic_offset_table |= profile_flag; \
2290 /* Max number of args passed in registers. If this is more than 3, we will
2291 have problems with ebx (register #4), since it is a caller save register and
2292 is also used as the pic register in ELF. So for now, don't allow more than
2293 3 registers to be passed in registers. */
2295 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2297 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2300 /* Specify the machine mode that this machine uses
2301 for the index in the tablejump instruction. */
2302 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2304 /* Define as C expression which evaluates to nonzero if the tablejump
2305 instruction expects the table to contain offsets from the address of the
2307 Do not define this if the table should contain absolute addresses. */
2308 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2310 /* Specify the tree operation to be used to convert reals to integers.
2311 This should be changed to take advantage of fist --wfs ??
2313 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2315 /* This is the kind of divide that is easiest to do in the general case. */
2316 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2318 /* Define this as 1 if `char' should by default be signed; else as 0. */
2319 #define DEFAULT_SIGNED_CHAR 1
2321 /* Number of bytes moved into a data cache for a single prefetch operation. */
2322 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2324 /* Number of prefetch operations that can be done in parallel. */
2325 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2327 /* Max number of bytes we can move from memory to memory
2328 in one reasonably fast instruction. */
2331 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2332 move efficiently, as opposed to MOVE_MAX which is the maximum
2333 number of bytes we can move with a single instruction. */
2334 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2336 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2337 move-instruction pairs, we will do a movstr or libcall instead.
2338 Increasing the value will always make code faster, but eventually
2339 incurs high cost in increased code size.
2341 If you don't define this, a reasonable default is used. */
2343 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2345 /* Define if shifts truncate the shift count
2346 which implies one can omit a sign-extension or zero-extension
2347 of a shift count. */
2348 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2350 /* #define SHIFT_COUNT_TRUNCATED */
2352 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2353 is done just by pretending it is already truncated. */
2354 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2356 /* We assume that the store-condition-codes instructions store 0 for false
2357 and some other value for true. This is the value stored for true. */
2359 #define STORE_FLAG_VALUE 1
2361 /* When a prototype says `char' or `short', really pass an `int'.
2362 (The 386 can't easily push less than an int.) */
2364 #define PROMOTE_PROTOTYPES 1
2366 /* A macro to update M and UNSIGNEDP when an object whose type is
2367 TYPE and which has the specified mode and signedness is to be
2368 stored in a register. This macro is only called when TYPE is a
2371 On i386 it is sometimes useful to promote HImode and QImode
2372 quantities to SImode. The choice depends on target type. */
2374 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2375 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2376 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2379 /* Specify the machine mode that pointers have.
2380 After generation of rtl, the compiler makes no further distinction
2381 between pointers and any other objects of this machine mode. */
2382 #define Pmode (TARGET_64BIT ? DImode : SImode)
2384 /* A function address in a call instruction
2385 is a byte address (for indexing purposes)
2386 so give the MEM rtx a byte's mode. */
2387 #define FUNCTION_MODE QImode
2389 /* A part of a C `switch' statement that describes the relative costs
2390 of constant RTL expressions. It must contain `case' labels for
2391 expression codes `const_int', `const', `symbol_ref', `label_ref'
2392 and `const_double'. Each case must ultimately reach a `return'
2393 statement to return the relative cost of the use of that kind of
2394 constant value in an expression. The cost may depend on the
2395 precise value of the constant, which is available for examination
2396 in X, and the rtx code of the expression in which it is contained,
2397 found in OUTER_CODE.
2399 CODE is the expression code--redundant, since it can be obtained
2400 with `GET_CODE (X)'. */
2402 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2407 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2409 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2411 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2413 case CONST_DOUBLE: \
2416 if (GET_MODE (RTX) == VOIDmode) \
2419 code = standard_80387_constant_p (RTX); \
2420 return code == 1 ? 1 : \
2425 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2426 #define TOPLEVEL_COSTS_N_INSNS(N) \
2427 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2429 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2430 This can be used, for example, to indicate how costly a multiply
2431 instruction is. In writing this macro, you can use the construct
2432 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2433 instructions. OUTER_CODE is the code of the expression in which X
2436 This macro is optional; do not define it if the default cost
2437 assumptions are adequate for the target machine. */
2439 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2441 /* The zero extensions is often completely free on x86_64, so make \
2442 it as cheap as possible. */ \
2443 if (TARGET_64BIT && GET_MODE (X) == DImode \
2444 && GET_MODE (XEXP (X, 0)) == SImode) \
2446 total = 1; goto egress_rtx_costs; \
2449 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2450 ix86_cost->add : ix86_cost->movzx); \
2453 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2456 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2457 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2459 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2461 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2462 if ((value == 2 || value == 3) \
2463 && !TARGET_DECOMPOSE_LEA \
2464 && ix86_cost->lea <= ix86_cost->shift_const) \
2465 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2467 /* fall through */ \
2473 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2475 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2477 if (INTVAL (XEXP (X, 1)) > 32) \
2478 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2480 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2484 if (GET_CODE (XEXP (X, 1)) == AND) \
2485 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2487 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2492 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2493 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2495 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2500 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2502 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2505 while (value != 0) \
2511 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2512 + nbits * ix86_cost->mult_bit); \
2514 else /* This is arbitrary */ \
2515 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2516 + 7 * ix86_cost->mult_bit); \
2522 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2525 if (!TARGET_DECOMPOSE_LEA \
2526 && INTEGRAL_MODE_P (GET_MODE (X)) \
2527 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2529 if (GET_CODE (XEXP (X, 0)) == PLUS \
2530 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2531 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2532 && CONSTANT_P (XEXP (X, 1))) \
2534 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2535 if (val == 2 || val == 4 || val == 8) \
2537 return (COSTS_N_INSNS (ix86_cost->lea) \
2538 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2539 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), OUTER_CODE) \
2540 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2543 else if (GET_CODE (XEXP (X, 0)) == MULT \
2544 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2546 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2547 if (val == 2 || val == 4 || val == 8) \
2549 return (COSTS_N_INSNS (ix86_cost->lea) \
2550 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2551 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2554 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2556 return (COSTS_N_INSNS (ix86_cost->lea) \
2557 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2558 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2559 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2563 /* fall through */ \
2568 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2569 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2570 + (rtx_cost (XEXP (X, 0), OUTER_CODE) \
2571 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2572 + (rtx_cost (XEXP (X, 1), OUTER_CODE) \
2573 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2575 /* fall through */ \
2578 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2579 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2580 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2586 /* An expression giving the cost of an addressing mode that contains
2587 ADDRESS. If not defined, the cost is computed from the ADDRESS
2588 expression and the `CONST_COSTS' values.
2590 For most CISC machines, the default cost is a good approximation
2591 of the true cost of the addressing mode. However, on RISC
2592 machines, all instructions normally have the same length and
2593 execution time. Hence all addresses will have equal costs.
2595 In cases where more than one form of an address is known, the form
2596 with the lowest cost will be used. If multiple forms have the
2597 same, lowest, cost, the one that is the most complex will be used.
2599 For example, suppose an address that is equal to the sum of a
2600 register and a constant is used twice in the same basic block.
2601 When this macro is not defined, the address will be computed in a
2602 register and memory references will be indirect through that
2603 register. On machines where the cost of the addressing mode
2604 containing the sum is no higher than that of a simple indirect
2605 reference, this will produce an additional instruction and
2606 possibly require an additional register. Proper specification of
2607 this macro eliminates this overhead for such machines.
2609 Similar use of this macro is made in strength reduction of loops.
2611 ADDRESS need not be valid as an address. In such a case, the cost
2612 is not relevant and can be any value; invalid addresses need not be
2613 assigned a different cost.
2615 On machines where an address involving more than one register is as
2616 cheap as an address computation involving only one register,
2617 defining `ADDRESS_COST' to reflect this can cause two registers to
2618 be live over a region of code where only one would have been if
2619 `ADDRESS_COST' were not defined in that manner. This effect should
2620 be considered in the definition of this macro. Equivalent costs
2621 should probably only be given to addresses with different numbers
2622 of registers on machines with lots of registers.
2624 This macro will normally either not be defined or be defined as a
2627 For i386, it is better to use a complex address than let gcc copy
2628 the address into a reg and make a new pseudo. But not if the address
2629 requires to two regs - that would mean more pseudos with longer
2632 #define ADDRESS_COST(RTX) \
2633 ix86_address_cost (RTX)
2635 /* A C expression for the cost of moving data from a register in class FROM to
2636 one in class TO. The classes are expressed using the enumeration values
2637 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2638 interpreted relative to that.
2640 It is not required that the cost always equal 2 when FROM is the same as TO;
2641 on some machines it is expensive to move between registers if they are not
2642 general registers. */
2644 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2645 ix86_register_move_cost (MODE, CLASS1, CLASS2)
2647 /* A C expression for the cost of moving data of mode M between a
2648 register and memory. A value of 2 is the default; this cost is
2649 relative to those in `REGISTER_MOVE_COST'.
2651 If moving between registers and memory is more expensive than
2652 between two registers, you should define this macro to express the
2655 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
2656 ix86_memory_move_cost (MODE, CLASS, IN)
2658 /* A C expression for the cost of a branch instruction. A value of 1
2659 is the default; other values are interpreted relative to that. */
2661 #define BRANCH_COST ix86_branch_cost
2663 /* Define this macro as a C expression which is nonzero if accessing
2664 less than a word of memory (i.e. a `char' or a `short') is no
2665 faster than accessing a word of memory, i.e., if such access
2666 require more than one instruction or if there is no difference in
2667 cost between byte and (aligned) word loads.
2669 When this macro is not defined, the compiler will access a field by
2670 finding the smallest containing object; when it is defined, a
2671 fullword load will be used if alignment permits. Unless bytes
2672 accesses are faster than word accesses, using word accesses is
2673 preferable since it may eliminate subsequent memory access if
2674 subsequent accesses occur to other fields in the same word of the
2675 structure, but to different bytes. */
2677 #define SLOW_BYTE_ACCESS 0
2679 /* Nonzero if access to memory by shorts is slow and undesirable. */
2680 #define SLOW_SHORT_ACCESS 0
2682 /* Define this macro if zero-extension (of a `char' or `short' to an
2683 `int') can be done faster if the destination is a register that is
2686 If you define this macro, you must have instruction patterns that
2687 recognize RTL structures like this:
2689 (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
2691 and likewise for `HImode'. */
2693 /* #define SLOW_ZERO_EXTEND */
2695 /* Define this macro to be the value 1 if unaligned accesses have a
2696 cost many times greater than aligned accesses, for example if they
2697 are emulated in a trap handler.
2699 When this macro is non-zero, the compiler will act as if
2700 `STRICT_ALIGNMENT' were non-zero when generating code for block
2701 moves. This can cause significantly more instructions to be
2702 produced. Therefore, do not set this macro non-zero if unaligned
2703 accesses only add a cycle or two to the time for a memory access.
2705 If the value of this macro is always zero, it need not be defined. */
2707 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2709 /* Define this macro to inhibit strength reduction of memory
2710 addresses. (On some machines, such strength reduction seems to do
2711 harm rather than good.) */
2713 /* #define DONT_REDUCE_ADDR */
2715 /* Define this macro if it is as good or better to call a constant
2716 function address than to call an address kept in a register.
2718 Desirable on the 386 because a CALL with a constant address is
2719 faster than one with a register address. */
2721 #define NO_FUNCTION_CSE
2723 /* Define this macro if it is as good or better for a function to call
2724 itself with an explicit address than to call an address kept in a
2727 #define NO_RECURSIVE_FUNCTION_CSE
2729 /* Add any extra modes needed to represent the condition code.
2731 For the i386, we need separate modes when floating-point
2732 equality comparisons are being done.
2734 Add CCNO to indicate comparisons against zero that requires
2735 Overflow flag to be unset. Sign bit test is used instead and
2736 thus can be used to form "a&b>0" type of tests.
2738 Add CCGC to indicate comparisons agains zero that allows
2739 unspecified garbage in the Carry flag. This mode is used
2740 by inc/dec instructions.
2742 Add CCGOC to indicate comparisons agains zero that allows
2743 unspecified garbage in the Carry and Overflow flag. This
2744 mode is used to simulate comparisons of (a-b) and (a+b)
2745 against zero using sub/cmp/add operations.
2747 Add CCZ to indicate that only the Zero flag is valid. */
2749 #define EXTRA_CC_MODES \
2750 CC(CCGCmode, "CCGC") \
2751 CC(CCGOCmode, "CCGOC") \
2752 CC(CCNOmode, "CCNO") \
2753 CC(CCZmode, "CCZ") \
2754 CC(CCFPmode, "CCFP") \
2755 CC(CCFPUmode, "CCFPU")
2757 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2758 return the mode to be used for the comparison.
2760 For floating-point equality comparisons, CCFPEQmode should be used.
2761 VOIDmode should be used in all other cases.
2763 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2764 possible, to allow for more combinations. */
2766 #define SELECT_CC_MODE(OP,X,Y) ix86_cc_mode (OP, X, Y)
2768 /* Return non-zero if MODE implies a floating point inequality can be
2771 #define REVERSIBLE_CC_MODE(MODE) 1
2773 /* A C expression whose value is reversed condition code of the CODE for
2774 comparison done in CC_MODE mode. */
2775 #define REVERSE_CONDITION(CODE, MODE) \
2776 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2777 : reverse_condition_maybe_unordered (CODE))
2780 /* Control the assembler format that we output, to the extent
2781 this does not vary between assemblers. */
2783 /* How to refer to registers in assembler output.
2784 This sequence is indexed by compiler's hard-register-number (see above). */
2786 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2787 For non floating point regs, the following are the HImode names.
2789 For float regs, the stack top is sometimes referred to as "%st(0)"
2790 instead of just "%st". PRINT_REG handles this with the "y" code. */
2792 #undef HI_REGISTER_NAMES
2793 #define HI_REGISTER_NAMES \
2794 {"ax","dx","cx","bx","si","di","bp","sp", \
2795 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2796 "flags","fpsr", "dirflag", "frame", \
2797 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2798 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2799 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2800 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2802 #define REGISTER_NAMES HI_REGISTER_NAMES
2804 /* Table of additional register names to use in user input. */
2806 #define ADDITIONAL_REGISTER_NAMES \
2807 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2808 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2809 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2810 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2811 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2812 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2813 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2814 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2816 /* Note we are omitting these since currently I don't know how
2817 to get gcc to use these, since they want the same but different
2818 number as al, and ax.
2821 #define QI_REGISTER_NAMES \
2822 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2824 /* These parallel the array above, and can be used to access bits 8:15
2825 of regs 0 through 3. */
2827 #define QI_HIGH_REGISTER_NAMES \
2828 {"ah", "dh", "ch", "bh", }
2830 /* How to renumber registers for dbx and gdb. */
2832 #define DBX_REGISTER_NUMBER(n) \
2833 (TARGET_64BIT ? dbx64_register_map[n] : dbx_register_map[n])
2835 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2836 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2837 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2839 /* Before the prologue, RA is at 0(%esp). */
2840 #define INCOMING_RETURN_ADDR_RTX \
2841 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2843 /* After the prologue, RA is at -4(AP) in the current frame. */
2844 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2846 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2847 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2849 /* PC is dbx register 8; let's use that column for RA. */
2850 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2852 /* Before the prologue, the top of the frame is at 4(%esp). */
2853 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2855 /* Describe how we implement __builtin_eh_return. */
2856 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2857 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2860 /* Select a format to encode pointers in exception handling data. CODE
2861 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2862 true if the symbol may be affected by dynamic relocations.
2864 ??? All x86 object file formats are capable of representing this.
2865 After all, the relocation needed is the same as for the call insn.
2866 Whether or not a particular assembler allows us to enter such, I
2867 guess we'll have to see. */
2868 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2870 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2873 /* This is how to output the definition of a user-level label named NAME,
2874 such as the label on a static function or variable NAME. */
2876 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2877 (assemble_name (FILE, NAME), fputs (":\n", FILE))
2879 /* This is how to output an assembler line defining a `double' constant. */
2881 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2883 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
2884 fprintf (FILE, "%s0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \
2887 /* This is how to output a `long double' extended real constant. */
2889 #undef ASM_OUTPUT_LONG_DOUBLE
2890 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2892 REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \
2893 if (TARGET_128BIT_LONG_DOUBLE) \
2894 fprintf (FILE, "%s0x%lx,0x%lx,0x%lx,0x0\n", ASM_LONG, l[0], l[1], l[2]); \
2896 fprintf (FILE, "%s0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \
2899 /* This is how to output an assembler line defining a `float' constant. */
2901 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2903 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
2904 fprintf ((FILE), "%s0x%lx\n", ASM_LONG, l); \
2907 /* Store in OUTPUT a string (made with alloca) containing
2908 an assembler-name for a local static variable named NAME.
2909 LABELNO is an integer which is different for each call. */
2911 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2912 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2913 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2915 /* This is how to output an assembler line defining an `int' constant. */
2917 #define ASM_OUTPUT_INT(FILE,VALUE) \
2918 ( fputs (ASM_LONG, FILE), \
2919 output_addr_const (FILE,(VALUE)), \
2922 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2923 ( fprintf (FILE, "%s\t", ASM_QUAD), \
2924 output_addr_const (FILE,(VALUE)), \
2927 /* Likewise for `char' and `short' constants. */
2929 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2930 ( fputs (ASM_SHORT, FILE), \
2931 output_addr_const (FILE,(VALUE)), \
2934 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2935 ( fputs (ASM_BYTE_OP, FILE), \
2936 output_addr_const (FILE, (VALUE)), \
2939 /* Given that x86 natively supports unaligned data, it's reasonable to
2940 assume that all x86 assemblers don't auto-align data. Thus the
2941 unaligned output macros required by dwarf2 frame unwind information
2942 degenerate to the macros used above. */
2943 #define UNALIGNED_SHORT_ASM_OP ASM_SHORT
2944 #define UNALIGNED_INT_ASM_OP ASM_LONG
2946 /* This is how to output an assembler line for a numeric constant byte. */
2948 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2949 asm_fprintf ((FILE), "%s0x%x\n", ASM_BYTE_OP, (int) (VALUE))
2951 /* This is how to output an insn to push a register on the stack.
2952 It need not be very fast code. */
2954 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2955 asm_fprintf (FILE, "\tpush{l}\t%%e%s\n", reg_names[REGNO])
2957 /* This is how to output an insn to pop a register from the stack.
2958 It need not be very fast code. */
2960 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2961 asm_fprintf (FILE, "\tpop{l}\t%%e%s\n", reg_names[REGNO])
2963 /* This is how to output an element of a case-vector that is absolute. */
2965 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2966 ix86_output_addr_vec_elt (FILE, VALUE)
2968 /* This is how to output an element of a case-vector that is relative. */
2970 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2971 ix86_output_addr_diff_elt (FILE, VALUE, REL)
2973 /* Under some conditions we need jump tables in the text section, because
2974 the assembler cannot handle label differences between sections. */
2976 #define JUMP_TABLES_IN_TEXT_SECTION \
2977 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2979 /* A C statement that outputs an address constant appropriate to
2980 for DWARF debugging. */
2982 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,X) \
2983 i386_dwarf_output_addr_const((FILE),(X))
2985 /* Either simplify a location expression, or return the original. */
2987 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2988 i386_simplify_dwarf_addr(X)
2990 /* Print operand X (an rtx) in assembler syntax to file FILE.
2991 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2992 Effect of various CODE letters is described in i386.c near
2993 print_operand function. */
2995 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2996 ((CODE) == '*' || (CODE) == '+')
2998 /* Print the name of a register based on its machine mode and number.
2999 If CODE is 'w', pretend the mode is HImode.
3000 If CODE is 'b', pretend the mode is QImode.
3001 If CODE is 'k', pretend the mode is SImode.
3002 If CODE is 'q', pretend the mode is DImode.
3003 If CODE is 'h', pretend the reg is the `high' byte register.
3004 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
3006 #define PRINT_REG(X, CODE, FILE) \
3007 print_reg (X, CODE, FILE)
3009 #define PRINT_OPERAND(FILE, X, CODE) \
3010 print_operand (FILE, X, CODE)
3012 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3013 print_operand_address (FILE, ADDR)
3015 /* Print the name of a register for based on its machine mode and number.
3016 This macro is used to print debugging output.
3017 This macro is different from PRINT_REG in that it may be used in
3018 programs that are not linked with aux-output.o. */
3020 #define DEBUG_PRINT_REG(X, CODE, FILE) \
3021 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
3022 static const char * const qi_name[] = QI_REGISTER_NAMES; \
3023 fprintf (FILE, "%d ", REGNO (X)); \
3024 if (REGNO (X) == FLAGS_REG) \
3025 { fputs ("flags", FILE); break; } \
3026 if (REGNO (X) == DIRFLAG_REG) \
3027 { fputs ("dirflag", FILE); break; } \
3028 if (REGNO (X) == FPSR_REG) \
3029 { fputs ("fpsr", FILE); break; } \
3030 if (REGNO (X) == ARG_POINTER_REGNUM) \
3031 { fputs ("argp", FILE); break; } \
3032 if (REGNO (X) == FRAME_POINTER_REGNUM) \
3033 { fputs ("frame", FILE); break; } \
3034 if (STACK_TOP_P (X)) \
3035 { fputs ("st(0)", FILE); break; } \
3037 { fputs (hi_name[REGNO(X)], FILE); break; } \
3038 if (REX_INT_REG_P (X)) \
3040 switch (GET_MODE_SIZE (GET_MODE (X))) \
3044 fprintf (FILE, "r%i", REGNO (X) \
3045 - FIRST_REX_INT_REG + 8); \
3048 fprintf (FILE, "r%id", REGNO (X) \
3049 - FIRST_REX_INT_REG + 8); \
3052 fprintf (FILE, "r%iw", REGNO (X) \
3053 - FIRST_REX_INT_REG + 8); \
3056 fprintf (FILE, "r%ib", REGNO (X) \
3057 - FIRST_REX_INT_REG + 8); \
3062 switch (GET_MODE_SIZE (GET_MODE (X))) \
3065 fputs ("r", FILE); \
3066 fputs (hi_name[REGNO (X)], FILE); \
3069 fputs ("e", FILE); \
3071 fputs (hi_name[REGNO (X)], FILE); \
3074 fputs (qi_name[REGNO (X)], FILE); \
3079 /* a letter which is not needed by the normal asm syntax, which
3080 we can use for operand syntax in the extended asm */
3082 #define ASM_OPERAND_LETTER '#'
3083 #define RET return ""
3084 #define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx))
3086 /* Define the codes that are matched by predicates in i386.c. */
3088 #define PREDICATE_CODES \
3089 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3090 SYMBOL_REF, LABEL_REF, CONST}}, \
3091 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3092 SYMBOL_REF, LABEL_REF, CONST}}, \
3093 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3094 SYMBOL_REF, LABEL_REF, CONST}}, \
3095 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3096 SYMBOL_REF, LABEL_REF, CONST}}, \
3097 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3098 SYMBOL_REF, LABEL_REF, CONST}}, \
3099 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3100 SYMBOL_REF, LABEL_REF, CONST}}, \
3101 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3102 SYMBOL_REF, LABEL_REF}}, \
3103 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3104 {"const_int_1_operand", {CONST_INT}}, \
3105 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3106 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3107 LABEL_REF, SUBREG, REG, MEM}}, \
3108 {"pic_symbolic_operand", {CONST}}, \
3109 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3110 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3111 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3112 {"const1_operand", {CONST_INT}}, \
3113 {"const248_operand", {CONST_INT}}, \
3114 {"incdec_operand", {CONST_INT}}, \
3115 {"mmx_reg_operand", {REG}}, \
3116 {"reg_no_sp_operand", {SUBREG, REG}}, \
3117 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3118 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3119 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3120 {"q_regs_operand", {SUBREG, REG}}, \
3121 {"non_q_regs_operand", {SUBREG, REG}}, \
3122 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3123 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3124 GE, UNGE, LTGT, UNEQ}}, \
3125 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3126 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3128 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3129 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3130 UNGE, UNGT, LTGT, UNEQ }}, \
3131 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3132 {"ext_register_operand", {SUBREG, REG}}, \
3133 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3134 {"mult_operator", {MULT}}, \
3135 {"div_operator", {DIV}}, \
3136 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3137 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3138 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3139 LSHIFTRT, ROTATERT}}, \
3140 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3141 {"memory_displacement_operand", {MEM}}, \
3142 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3143 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3144 {"long_memory_operand", {MEM}},
3146 /* A list of predicates that do special things with modes, and so
3147 should not elicit warnings for VOIDmode match_operand. */
3149 #define SPECIAL_MODE_PREDICATES \
3150 "ext_register_operand",
3152 /* CM_32 is used by 32bit ABI
3153 CM_SMALL is small model assuming that all code and data fits in the first
3154 31bits of address space.
3155 CM_KERNEL is model assuming that all code and data fits in the negative
3156 31bits of address space.
3157 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3158 space. Size of data is unlimited.
3159 CM_LARGE is model making no assumptions about size of particular sections.
3161 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3162 tables first in 31bits of address space.
3173 /* Size of the RED_ZONE area. */
3174 #define RED_ZONE_SIZE 128
3175 /* Reserved area of the red zone for temporaries. */
3176 #define RED_ZONE_RESERVE 8
3177 /* Valud of -mcmodel specified by user. */
3178 extern const char *ix86_cmodel_string;
3179 extern enum cmodel ix86_cmodel;
3181 /* Variables in i386.c */
3182 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3183 extern const char *ix86_arch_string; /* for -march=<xxx> */
3184 extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
3185 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3186 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3187 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3188 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3189 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3190 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3191 extern int ix86_regparm; /* ix86_regparm_string as a number */
3192 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3193 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3194 extern enum reg_class const regclass_map[]; /* smalled class containing REGNO */
3195 extern struct rtx_def *ix86_compare_op0; /* operand 0 for comparisons */
3196 extern struct rtx_def *ix86_compare_op1; /* operand 1 for comparisons */
3198 /* To properly truncate FP values into integers, we need to set i387 control
3199 word. We can't emit proper mode switching code before reload, as spills
3200 generated by reload may truncate values incorrectly, but we still can avoid
3201 redundant computation of new control word by the mode switching pass.
3202 The fldcw instructions are still emitted redundantly, but this is probably
3203 not going to be noticeable problem, as most CPUs do have fast path for
3206 The machinery is to emit simple truncation instructions and split them
3207 before reload to instructions having USEs of two memory locations that
3208 are filled by this code to old and new control word.
3210 Post-reload pass may be later used to eliminate the redundant fildcw if
3213 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3215 /* Define this macro if the port needs extra instructions inserted
3216 for mode switching in an optimizing compilation. */
3218 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3220 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3221 initializer for an array of integers. Each initializer element N
3222 refers to an entity that needs mode switching, and specifies the
3223 number of different modes that might need to be set for this
3224 entity. The position of the initializer in the initializer -
3225 starting counting at zero - determines the integer that is used to
3226 refer to the mode-switched entity in question. */
3228 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3230 /* ENTITY is an integer specifying a mode-switched entity. If
3231 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3232 return an integer value not larger than the corresponding element
3233 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3234 must be switched into prior to the execution of INSN. */
3236 #define MODE_NEEDED(ENTITY, I) \
3237 (GET_CODE (I) == CALL_INSN \
3238 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3239 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3240 ? FP_CW_UNINITIALIZED \
3241 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3245 /* This macro specifies the order in which modes for ENTITY are
3246 processed. 0 is the highest priority. */
3248 #define MODE_PRIORITY_TO_MODE(ENTITY, N) N
3250 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3251 is the set of hard registers live at the point where the insn(s)
3252 are to be inserted. */
3254 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3255 (MODE == FP_CW_STORED \
3256 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3257 assign_386_stack_local (HImode, 2)), 0\
3260 /* Avoid renaming of stack registers, as doing so in combination with
3261 scheduling just increases amount of live registers at time and in
3262 the turn amount of fxch instructions needed.
3264 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3266 #define HARD_REGNO_RENAME_OK(src,target) \
3267 ((src) < FIRST_STACK_REG || (src) > LAST_STACK_REG)
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