1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Redefines for option macros. */
39 #define TARGET_64BIT OPTION_ISA_64BIT
40 #define TARGET_MMX OPTION_ISA_MMX
41 #define TARGET_3DNOW OPTION_ISA_3DNOW
42 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
43 #define TARGET_SSE OPTION_ISA_SSE
44 #define TARGET_SSE2 OPTION_ISA_SSE2
45 #define TARGET_SSE3 OPTION_ISA_SSE3
46 #define TARGET_SSSE3 OPTION_ISA_SSSE3
47 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1
48 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2
49 #define TARGET_SSE4A OPTION_ISA_SSE4A
50 #define TARGET_SSE5 OPTION_ISA_SSE5
51 #define TARGET_ROUND OPTION_ISA_ROUND
53 /* SSE5 and SSE4.1 define the same round instructions */
54 #define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE5)
55 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
57 #include "config/vxworks-dummy.h"
59 /* Algorithm to expand string function with. */
72 #define NAX_STRINGOP_ALGS 4
74 /* Specify what algorithm to use for stringops on known size.
75 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
76 known at compile time or estimated via feedback, the SIZE array
77 is walked in order until MAX is greater then the estimate (or -1
78 means infinity). Corresponding ALG is used then.
79 For example initializer:
80 {{256, loop}, {-1, rep_prefix_4_byte}}
81 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
85 const enum stringop_alg unknown_size;
86 const struct stringop_strategy {
88 const enum stringop_alg alg;
89 } size [NAX_STRINGOP_ALGS];
92 /* Define the specific costs for a given cpu */
94 struct processor_costs {
95 const int add; /* cost of an add instruction */
96 const int lea; /* cost of a lea instruction */
97 const int shift_var; /* variable shift costs */
98 const int shift_const; /* constant shift costs */
99 const int mult_init[5]; /* cost of starting a multiply
100 in QImode, HImode, SImode, DImode, TImode*/
101 const int mult_bit; /* cost of multiply per each bit set */
102 const int divide[5]; /* cost of a divide/mod
103 in QImode, HImode, SImode, DImode, TImode*/
104 int movsx; /* The cost of movsx operation. */
105 int movzx; /* The cost of movzx operation. */
106 const int large_insn; /* insns larger than this cost more */
107 const int move_ratio; /* The threshold of number of scalar
108 memory-to-memory move insns. */
109 const int movzbl_load; /* cost of loading using movzbl */
110 const int int_load[3]; /* cost of loading integer registers
111 in QImode, HImode and SImode relative
112 to reg-reg move (2). */
113 const int int_store[3]; /* cost of storing integer register
114 in QImode, HImode and SImode */
115 const int fp_move; /* cost of reg,reg fld/fst */
116 const int fp_load[3]; /* cost of loading FP register
117 in SFmode, DFmode and XFmode */
118 const int fp_store[3]; /* cost of storing FP register
119 in SFmode, DFmode and XFmode */
120 const int mmx_move; /* cost of moving MMX register. */
121 const int mmx_load[2]; /* cost of loading MMX register
122 in SImode and DImode */
123 const int mmx_store[2]; /* cost of storing MMX register
124 in SImode and DImode */
125 const int sse_move; /* cost of moving SSE register. */
126 const int sse_load[3]; /* cost of loading SSE register
127 in SImode, DImode and TImode*/
128 const int sse_store[3]; /* cost of storing SSE register
129 in SImode, DImode and TImode*/
130 const int mmxsse_to_integer; /* cost of moving mmxsse register to
131 integer and vice versa. */
132 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
133 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
134 const int prefetch_block; /* bytes moved to cache for prefetch. */
135 const int simultaneous_prefetches; /* number of parallel prefetch
137 const int branch_cost; /* Default value for BRANCH_COST. */
138 const int fadd; /* cost of FADD and FSUB instructions. */
139 const int fmul; /* cost of FMUL instruction. */
140 const int fdiv; /* cost of FDIV instruction. */
141 const int fabs; /* cost of FABS instruction. */
142 const int fchs; /* cost of FCHS instruction. */
143 const int fsqrt; /* cost of FSQRT instruction. */
144 /* Specify what algorithm
145 to use for stringops on unknown size. */
146 struct stringop_algs memcpy[2], memset[2];
147 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
149 const int scalar_load_cost; /* Cost of scalar load. */
150 const int scalar_store_cost; /* Cost of scalar store. */
151 const int vec_stmt_cost; /* Cost of any vector operation, excluding
152 load, store, vector-to-scalar and
153 scalar-to-vector operation. */
154 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
155 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
156 const int vec_align_load_cost; /* Cost of aligned vector load. */
157 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
158 const int vec_store_cost; /* Cost of vector store. */
159 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
161 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
162 vectorizer cost model. */
165 extern const struct processor_costs *ix86_cost;
167 /* Macros used in the machine description to test the flags. */
169 /* configure can arrange to make this 2, to force a 486. */
171 #ifndef TARGET_CPU_DEFAULT
172 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
175 #ifndef TARGET_FPMATH_DEFAULT
176 #define TARGET_FPMATH_DEFAULT \
177 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
180 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
182 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
183 compile-time constant. */
187 #define TARGET_64BIT 1
189 #define TARGET_64BIT 0
192 #ifndef TARGET_BI_ARCH
194 #if TARGET_64BIT_DEFAULT
195 #define TARGET_64BIT 1
197 #define TARGET_64BIT 0
202 #define HAS_LONG_COND_BRANCH 1
203 #define HAS_LONG_UNCOND_BRANCH 1
205 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
206 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
207 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
208 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
209 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
210 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
211 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
212 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
213 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
214 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
215 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
216 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
217 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
218 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
219 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
220 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
222 /* Feature tests against the various tunings. */
223 enum ix86_tune_indices {
225 X86_TUNE_PUSH_MEMORY,
226 X86_TUNE_ZERO_EXTEND_WITH_AND,
227 X86_TUNE_USE_BIT_TEST,
228 X86_TUNE_UNROLL_STRLEN,
229 X86_TUNE_DEEP_BRANCH_PREDICTION,
230 X86_TUNE_BRANCH_PREDICTION_HINTS,
231 X86_TUNE_DOUBLE_WITH_ADD,
234 X86_TUNE_PARTIAL_REG_STALL,
235 X86_TUNE_PARTIAL_FLAG_REG_STALL,
236 X86_TUNE_USE_HIMODE_FIOP,
237 X86_TUNE_USE_SIMODE_FIOP,
241 X86_TUNE_SPLIT_LONG_MOVES,
242 X86_TUNE_READ_MODIFY_WRITE,
243 X86_TUNE_READ_MODIFY,
244 X86_TUNE_PROMOTE_QIMODE,
245 X86_TUNE_FAST_PREFIX,
246 X86_TUNE_SINGLE_STRINGOP,
247 X86_TUNE_QIMODE_MATH,
248 X86_TUNE_HIMODE_MATH,
249 X86_TUNE_PROMOTE_QI_REGS,
250 X86_TUNE_PROMOTE_HI_REGS,
255 X86_TUNE_INTEGER_DFMODE_MOVES,
256 X86_TUNE_PARTIAL_REG_DEPENDENCY,
257 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
258 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
259 X86_TUNE_SSE_SPLIT_REGS,
260 X86_TUNE_SSE_TYPELESS_STORES,
261 X86_TUNE_SSE_LOAD0_BY_PXOR,
262 X86_TUNE_MEMORY_MISMATCH_STALL,
263 X86_TUNE_PROLOGUE_USING_MOVE,
264 X86_TUNE_EPILOGUE_USING_MOVE,
267 X86_TUNE_INTER_UNIT_MOVES,
268 X86_TUNE_INTER_UNIT_CONVERSIONS,
269 X86_TUNE_FOUR_JUMP_LIMIT,
273 X86_TUNE_PAD_RETURNS,
274 X86_TUNE_EXT_80387_CONSTANTS,
275 X86_TUNE_SHORTEN_X87_SSE,
276 X86_TUNE_AVOID_VECTOR_DECODE,
277 X86_TUNE_PROMOTE_HIMODE_IMUL,
278 X86_TUNE_SLOW_IMUL_IMM32_MEM,
279 X86_TUNE_SLOW_IMUL_IMM8,
280 X86_TUNE_MOVE_M1_VIA_OR,
281 X86_TUNE_NOT_UNPAIRABLE,
282 X86_TUNE_NOT_VECTORMODE,
283 X86_TUNE_USE_VECTOR_CONVERTS,
288 extern unsigned int ix86_tune_features[X86_TUNE_LAST];
290 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
291 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
292 #define TARGET_ZERO_EXTEND_WITH_AND \
293 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
294 #define TARGET_USE_BIT_TEST ix86_tune_features[X86_TUNE_USE_BIT_TEST]
295 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
296 #define TARGET_DEEP_BRANCH_PREDICTION \
297 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
298 #define TARGET_BRANCH_PREDICTION_HINTS \
299 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
300 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
301 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
302 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
303 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
304 #define TARGET_PARTIAL_FLAG_REG_STALL \
305 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
306 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
307 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
308 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
309 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
310 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
311 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
312 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
313 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
314 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
315 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
316 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
317 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
318 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
319 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
320 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
321 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4]
322 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8]
323 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4]
324 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8]
325 #define TARGET_INTEGER_DFMODE_MOVES \
326 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
327 #define TARGET_PARTIAL_REG_DEPENDENCY \
328 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
329 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
330 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
331 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
332 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
333 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
334 #define TARGET_SSE_TYPELESS_STORES \
335 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
336 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
337 #define TARGET_MEMORY_MISMATCH_STALL \
338 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
339 #define TARGET_PROLOGUE_USING_MOVE \
340 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
341 #define TARGET_EPILOGUE_USING_MOVE \
342 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
343 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
344 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
345 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
346 #define TARGET_INTER_UNIT_CONVERSIONS\
347 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
348 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
349 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
350 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
351 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
352 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
353 #define TARGET_EXT_80387_CONSTANTS \
354 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
355 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
356 #define TARGET_AVOID_VECTOR_DECODE \
357 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
358 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
359 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
360 #define TARGET_SLOW_IMUL_IMM32_MEM \
361 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
362 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
363 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
364 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
365 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
366 #define TARGET_USE_VECTOR_CONVERTS ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
368 /* Feature tests against the various architecture variations. */
369 enum ix86_arch_indices {
370 X86_ARCH_CMOVE, /* || TARGET_SSE */
379 extern unsigned int ix86_arch_features[X86_ARCH_LAST];
381 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
382 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
383 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
384 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
385 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
387 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
389 extern int x86_prefetch_sse;
391 #define TARGET_ABM x86_abm
392 #define TARGET_CMPXCHG16B x86_cmpxchg16b
393 #define TARGET_POPCNT x86_popcnt
394 #define TARGET_PREFETCH_SSE x86_prefetch_sse
395 #define TARGET_SAHF x86_sahf
396 #define TARGET_RECIP x86_recip
397 #define TARGET_FUSED_MADD x86_fused_muladd
399 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
401 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
402 #define TARGET_MIX_SSE_I387 \
403 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
405 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
406 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
407 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
408 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
410 extern int ix86_isa_flags;
412 #ifndef TARGET_64BIT_DEFAULT
413 #define TARGET_64BIT_DEFAULT 0
415 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
416 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
419 /* Fence to use after loop using storent. */
421 extern tree x86_mfence;
422 #define FENCE_FOLLOWING_MOVNT x86_mfence
424 /* Once GDB has been enhanced to deal with functions without frame
425 pointers, we can change this to allow for elimination of
426 the frame pointer in leaf functions. */
427 #define TARGET_DEFAULT 0
429 /* Extra bits to force. */
430 #define TARGET_SUBTARGET_DEFAULT 0
431 #define TARGET_SUBTARGET_ISA_DEFAULT 0
433 /* Extra bits to force on w/ 32-bit mode. */
434 #define TARGET_SUBTARGET32_DEFAULT 0
435 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
437 /* Extra bits to force on w/ 64-bit mode. */
438 #define TARGET_SUBTARGET64_DEFAULT 0
439 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
441 /* This is not really a target flag, but is done this way so that
442 it's analogous to similar code for Mach-O on PowerPC. darwin.h
443 redefines this to 1. */
444 #define TARGET_MACHO 0
446 /* Likewise, for the Windows 64-bit ABI. */
447 #define TARGET_64BIT_MS_ABI 0
449 /* Subtargets may reset this to 1 in order to enable 96-bit long double
450 with the rounding mode forced to 53 bits. */
451 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
453 /* Sometimes certain combinations of command options do not make
454 sense on a particular target machine. You can define a macro
455 `OVERRIDE_OPTIONS' to take account of this. This macro, if
456 defined, is executed once just after all the command options have
459 Don't use this macro to turn on various extra optimizations for
460 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
462 #define OVERRIDE_OPTIONS override_options ()
464 /* Define this to change the optimizations performed by default. */
465 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
466 optimization_options ((LEVEL), (SIZE))
468 /* -march=native handling only makes sense with compiler running on
469 an x86 or x86_64 chip. If changing this condition, also change
470 the condition in driver-i386.c. */
471 #if defined(__i386__) || defined(__x86_64__)
472 /* In driver-i386.c. */
473 extern const char *host_detect_local_cpu (int argc, const char **argv);
474 #define EXTRA_SPEC_FUNCTIONS \
475 { "local_cpu_detect", host_detect_local_cpu },
476 #define HAVE_LOCAL_CPU_DETECT
479 /* Support for configure-time defaults of some command line options.
480 The order here is important so that -march doesn't squash the
481 tune or cpu values. */
482 #define OPTION_DEFAULT_SPECS \
483 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
484 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
485 {"arch", "%{!march=*:-march=%(VALUE)}"}
487 /* Specs for the compiler proper */
490 #define CC1_CPU_SPEC_1 "\
492 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \
494 %{mintel-syntax:-masm=intel \
495 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
496 %{mno-intel-syntax:-masm=att \
497 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
499 #ifndef HAVE_LOCAL_CPU_DETECT
500 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
502 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
503 "%{march=native:%<march=native %:local_cpu_detect(arch) \
504 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
505 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
509 /* Target CPU builtins. */
510 #define TARGET_CPU_CPP_BUILTINS() \
513 size_t arch_len = strlen (ix86_arch_string); \
514 size_t tune_len = strlen (ix86_tune_string); \
515 int last_arch_char = ix86_arch_string[arch_len - 1]; \
516 int last_tune_char = ix86_tune_string[tune_len - 1]; \
520 builtin_assert ("cpu=x86_64"); \
521 builtin_assert ("machine=x86_64"); \
522 builtin_define ("__amd64"); \
523 builtin_define ("__amd64__"); \
524 builtin_define ("__x86_64"); \
525 builtin_define ("__x86_64__"); \
529 builtin_assert ("cpu=i386"); \
530 builtin_assert ("machine=i386"); \
531 builtin_define_std ("i386"); \
534 /* Built-ins based on -march=. */ \
537 case PROCESSOR_I386: \
539 case PROCESSOR_I486: \
540 builtin_define ("__i486"); \
541 builtin_define ("__i486__"); \
543 case PROCESSOR_PENTIUM: \
544 builtin_define ("__i586"); \
545 builtin_define ("__i586__"); \
546 builtin_define ("__pentium"); \
547 builtin_define ("__pentium__"); \
548 if (last_arch_char == 'x') \
549 builtin_define ("__pentium_mmx__"); \
551 case PROCESSOR_PENTIUMPRO: \
552 builtin_define ("__i686"); \
553 builtin_define ("__i686__"); \
554 builtin_define ("__pentiumpro"); \
555 builtin_define ("__pentiumpro__"); \
557 case PROCESSOR_GEODE: \
558 builtin_define ("__geode"); \
559 builtin_define ("__geode__"); \
562 builtin_define ("__k6"); \
563 builtin_define ("__k6__"); \
564 if (last_arch_char == '2') \
565 builtin_define ("__k6_2__"); \
566 else if (last_arch_char == '3') \
567 builtin_define ("__k6_3__"); \
569 case PROCESSOR_ATHLON: \
570 builtin_define ("__athlon"); \
571 builtin_define ("__athlon__"); \
572 /* Only plain "athlon" lacks SSE. */ \
573 if (last_arch_char != 'n') \
574 builtin_define ("__athlon_sse__"); \
577 builtin_define ("__k8"); \
578 builtin_define ("__k8__"); \
580 case PROCESSOR_AMDFAM10: \
581 builtin_define ("__amdfam10"); \
582 builtin_define ("__amdfam10__"); \
584 case PROCESSOR_PENTIUM4: \
585 builtin_define ("__pentium4"); \
586 builtin_define ("__pentium4__"); \
588 case PROCESSOR_NOCONA: \
589 builtin_define ("__nocona"); \
590 builtin_define ("__nocona__"); \
592 case PROCESSOR_CORE2: \
593 builtin_define ("__core2"); \
594 builtin_define ("__core2__"); \
596 case PROCESSOR_GENERIC32: \
597 case PROCESSOR_GENERIC64: \
598 case PROCESSOR_max: \
599 gcc_unreachable (); \
602 /* Built-ins based on -mtune=. */ \
605 case PROCESSOR_I386: \
606 builtin_define ("__tune_i386__"); \
608 case PROCESSOR_I486: \
609 builtin_define ("__tune_i486__"); \
611 case PROCESSOR_PENTIUM: \
612 builtin_define ("__tune_i586__"); \
613 builtin_define ("__tune_pentium__"); \
614 if (last_tune_char == 'x') \
615 builtin_define ("__tune_pentium_mmx__"); \
617 case PROCESSOR_PENTIUMPRO: \
618 builtin_define ("__tune_i686__"); \
619 builtin_define ("__tune_pentiumpro__"); \
620 switch (last_tune_char) \
623 builtin_define ("__tune_pentium3__"); \
626 builtin_define ("__tune_pentium2__"); \
630 case PROCESSOR_GEODE: \
631 builtin_define ("__tune_geode__"); \
634 builtin_define ("__tune_k6__"); \
635 if (last_tune_char == '2') \
636 builtin_define ("__tune_k6_2__"); \
637 else if (last_tune_char == '3') \
638 builtin_define ("__tune_k6_3__"); \
640 case PROCESSOR_ATHLON: \
641 builtin_define ("__tune_athlon__"); \
642 /* Only plain "athlon" lacks SSE. */ \
643 if (last_tune_char != 'n') \
644 builtin_define ("__tune_athlon_sse__"); \
647 builtin_define ("__tune_k8__"); \
649 case PROCESSOR_AMDFAM10: \
650 builtin_define ("__tune_amdfam10__"); \
652 case PROCESSOR_PENTIUM4: \
653 builtin_define ("__tune_pentium4__"); \
655 case PROCESSOR_NOCONA: \
656 builtin_define ("__tune_nocona__"); \
658 case PROCESSOR_CORE2: \
659 builtin_define ("__tune_core2__"); \
661 case PROCESSOR_GENERIC32: \
662 case PROCESSOR_GENERIC64: \
664 case PROCESSOR_max: \
665 gcc_unreachable (); \
669 builtin_define ("__MMX__"); \
671 builtin_define ("__3dNOW__"); \
672 if (TARGET_3DNOW_A) \
673 builtin_define ("__3dNOW_A__"); \
675 builtin_define ("__SSE__"); \
677 builtin_define ("__SSE2__"); \
679 builtin_define ("__SSE3__"); \
681 builtin_define ("__SSSE3__"); \
683 builtin_define ("__SSE4_1__"); \
685 builtin_define ("__SSE4_2__"); \
687 builtin_define ("__SSE4A__"); \
689 builtin_define ("__SSE5__"); \
690 if (TARGET_SSE_MATH && TARGET_SSE) \
691 builtin_define ("__SSE_MATH__"); \
692 if (TARGET_SSE_MATH && TARGET_SSE2) \
693 builtin_define ("__SSE2_MATH__"); \
697 enum target_cpu_default
699 TARGET_CPU_DEFAULT_generic = 0,
701 TARGET_CPU_DEFAULT_i386,
702 TARGET_CPU_DEFAULT_i486,
703 TARGET_CPU_DEFAULT_pentium,
704 TARGET_CPU_DEFAULT_pentium_mmx,
705 TARGET_CPU_DEFAULT_pentiumpro,
706 TARGET_CPU_DEFAULT_pentium2,
707 TARGET_CPU_DEFAULT_pentium3,
708 TARGET_CPU_DEFAULT_pentium4,
709 TARGET_CPU_DEFAULT_pentium_m,
710 TARGET_CPU_DEFAULT_prescott,
711 TARGET_CPU_DEFAULT_nocona,
712 TARGET_CPU_DEFAULT_core2,
714 TARGET_CPU_DEFAULT_geode,
715 TARGET_CPU_DEFAULT_k6,
716 TARGET_CPU_DEFAULT_k6_2,
717 TARGET_CPU_DEFAULT_k6_3,
718 TARGET_CPU_DEFAULT_athlon,
719 TARGET_CPU_DEFAULT_athlon_sse,
720 TARGET_CPU_DEFAULT_k8,
721 TARGET_CPU_DEFAULT_amdfam10,
723 TARGET_CPU_DEFAULT_max
727 #define CC1_SPEC "%(cc1_cpu) "
730 /* This macro defines names of additional specifications to put in the
731 specs that can be used in various specifications like CC1_SPEC. Its
732 definition is an initializer with a subgrouping for each command option.
734 Each subgrouping contains a string constant, that defines the
735 specification name, and a string constant that used by the GCC driver
738 Do not define this macro if it does not need to do anything. */
740 #ifndef SUBTARGET_EXTRA_SPECS
741 #define SUBTARGET_EXTRA_SPECS
744 #define EXTRA_SPECS \
745 { "cc1_cpu", CC1_CPU_SPEC }, \
746 SUBTARGET_EXTRA_SPECS
749 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
750 FPU, assume that the fpcw is set to extended precision; when using
751 only SSE, rounding is correct; when using both SSE and the FPU,
752 the rounding precision is indeterminate, since either may be chosen
753 apparently at random. */
754 #define TARGET_FLT_EVAL_METHOD \
755 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
757 /* target machine storage layout */
759 #define SHORT_TYPE_SIZE 16
760 #define INT_TYPE_SIZE 32
761 #define FLOAT_TYPE_SIZE 32
762 #define LONG_TYPE_SIZE BITS_PER_WORD
763 #define DOUBLE_TYPE_SIZE 64
764 #define LONG_LONG_TYPE_SIZE 64
765 #define LONG_DOUBLE_TYPE_SIZE 80
767 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE
769 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
770 #define MAX_BITS_PER_WORD 64
772 #define MAX_BITS_PER_WORD 32
775 /* Define this if most significant byte of a word is the lowest numbered. */
776 /* That is true on the 80386. */
778 #define BITS_BIG_ENDIAN 0
780 /* Define this if most significant byte of a word is the lowest numbered. */
781 /* That is not true on the 80386. */
782 #define BYTES_BIG_ENDIAN 0
784 /* Define this if most significant word of a multiword number is the lowest
786 /* Not true for 80386 */
787 #define WORDS_BIG_ENDIAN 0
789 /* Width of a word, in units (bytes). */
790 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
792 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
794 #define MIN_UNITS_PER_WORD 4
797 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
798 #define PARM_BOUNDARY BITS_PER_WORD
800 /* Boundary (in *bits*) on which stack pointer should be aligned. */
801 #define STACK_BOUNDARY BITS_PER_WORD
803 /* Boundary (in *bits*) on which the stack pointer prefers to be
804 aligned; the compiler cannot rely on having this alignment. */
805 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
807 /* As of July 2001, many runtimes do not align the stack properly when
808 entering main. This causes expand_main_function to forcibly align
809 the stack, which results in aligned frames for functions called from
810 main, though it does nothing for the alignment of main itself. */
811 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
812 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
814 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
815 mandatory for the 64-bit ABI, and may or may not be true for other
816 operating systems. */
817 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
819 /* Minimum allocation boundary for the code of a function. */
820 #define FUNCTION_BOUNDARY 8
822 /* C++ stores the virtual bit in the lowest bit of function pointers. */
823 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
825 /* Alignment of field after `int : 0' in a structure. */
827 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
829 /* Minimum size in bits of the largest boundary to which any
830 and all fundamental data types supported by the hardware
831 might need to be aligned. No data type wants to be aligned
834 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
835 and Pentium Pro XFmode values at 128 bit boundaries. */
837 #define BIGGEST_ALIGNMENT 128
839 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
840 #define ALIGN_MODE_128(MODE) \
841 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
843 /* The published ABIs say that doubles should be aligned on word
844 boundaries, so lower the alignment for structure fields unless
845 -malign-double is set. */
847 /* ??? Blah -- this macro is used directly by libobjc. Since it
848 supports no vector modes, cut out the complexity and fall back
849 on BIGGEST_FIELD_ALIGNMENT. */
850 #ifdef IN_TARGET_LIBS
852 #define BIGGEST_FIELD_ALIGNMENT 128
854 #define BIGGEST_FIELD_ALIGNMENT 32
857 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
858 x86_field_alignment (FIELD, COMPUTED)
861 /* If defined, a C expression to compute the alignment given to a
862 constant that is being placed in memory. EXP is the constant
863 and ALIGN is the alignment that the object would ordinarily have.
864 The value of this macro is used instead of that alignment to align
867 If this macro is not defined, then ALIGN is used.
869 The typical use of this macro is to increase alignment for string
870 constants to be word aligned so that `strcpy' calls that copy
871 constants can be done inline. */
873 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
875 /* If defined, a C expression to compute the alignment for a static
876 variable. TYPE is the data type, and ALIGN is the alignment that
877 the object would ordinarily have. The value of this macro is used
878 instead of that alignment to align the object.
880 If this macro is not defined, then ALIGN is used.
882 One use of this macro is to increase alignment of medium-size
883 data to make it all fit in fewer cache lines. Another is to
884 cause character arrays to be word-aligned so that `strcpy' calls
885 that copy constants to character arrays can be done inline. */
887 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
889 /* If defined, a C expression to compute the alignment for a local
890 variable. TYPE is the data type, and ALIGN is the alignment that
891 the object would ordinarily have. The value of this macro is used
892 instead of that alignment to align the object.
894 If this macro is not defined, then ALIGN is used.
896 One use of this macro is to increase alignment of medium-size
897 data to make it all fit in fewer cache lines. */
899 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
901 /* If defined, a C expression that gives the alignment boundary, in
902 bits, of an argument with the specified mode and type. If it is
903 not defined, `PARM_BOUNDARY' is used for all arguments. */
905 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
906 ix86_function_arg_boundary ((MODE), (TYPE))
908 /* Set this nonzero if move instructions will actually fail to work
909 when given unaligned data. */
910 #define STRICT_ALIGNMENT 0
912 /* If bit field type is int, don't let it cross an int,
913 and give entire struct the alignment of an int. */
914 /* Required on the 386 since it doesn't have bit-field insns. */
915 #define PCC_BITFIELD_TYPE_MATTERS 1
917 /* Standard register usage. */
919 /* This processor has special stack-like registers. See reg-stack.c
924 #define IS_STACK_MODE(MODE) \
925 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
926 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
929 /* Number of actual hardware registers.
930 The hardware registers are assigned numbers for the compiler
931 from 0 to just below FIRST_PSEUDO_REGISTER.
932 All registers that the compiler knows about must be given numbers,
933 even those that are not normally considered general registers.
935 In the 80386 we give the 8 general purpose registers the numbers 0-7.
936 We number the floating point registers 8-15.
937 Note that registers 0-7 can be accessed as a short or int,
938 while only 0-3 may be used with byte `mov' instructions.
940 Reg 16 does not correspond to any hardware register, but instead
941 appears in the RTL as an argument pointer prior to reload, and is
942 eliminated during reloading in favor of either the stack or frame
945 #define FIRST_PSEUDO_REGISTER 53
947 /* Number of hardware registers that go into the DWARF-2 unwind info.
948 If not defined, equals FIRST_PSEUDO_REGISTER. */
950 #define DWARF_FRAME_REGISTERS 17
952 /* 1 for registers that have pervasive standard uses
953 and are not available for the register allocator.
954 On the 80386, the stack pointer is such, as is the arg pointer.
956 The value is zero if the register is not fixed on either 32 or
957 64 bit targets, one if the register if fixed on both 32 and 64
958 bit targets, two if it is only fixed on 32bit targets and three
959 if its only fixed on 64bit targets.
960 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
962 #define FIXED_REGISTERS \
963 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
964 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
965 /*arg,flags,fpsr,fpcr,frame*/ \
967 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
968 0, 0, 0, 0, 0, 0, 0, 0, \
969 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
970 0, 0, 0, 0, 0, 0, 0, 0, \
971 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
972 2, 2, 2, 2, 2, 2, 2, 2, \
973 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
974 2, 2, 2, 2, 2, 2, 2, 2 }
977 /* 1 for registers not available across function calls.
978 These must include the FIXED_REGISTERS and also any
979 registers that can be used without being saved.
980 The latter must include the registers where values are returned
981 and the register where structure-value addresses are passed.
982 Aside from that, you can include as many other registers as you like.
984 The value is zero if the register is not call used on either 32 or
985 64 bit targets, one if the register if call used on both 32 and 64
986 bit targets, two if it is only call used on 32bit targets and three
987 if its only call used on 64bit targets.
988 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
990 #define CALL_USED_REGISTERS \
991 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
992 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
993 /*arg,flags,fpsr,fpcr,frame*/ \
995 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
996 1, 1, 1, 1, 1, 1, 1, 1, \
997 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
998 1, 1, 1, 1, 1, 1, 1, 1, \
999 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1000 1, 1, 1, 1, 2, 2, 2, 2, \
1001 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
1002 1, 1, 1, 1, 1, 1, 1, 1 }
1004 /* Order in which to allocate registers. Each register must be
1005 listed once, even those in FIXED_REGISTERS. List frame pointer
1006 late and fixed registers last. Note that, in general, we prefer
1007 registers listed in CALL_USED_REGISTERS, keeping the others
1008 available for storage of persistent values.
1010 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
1011 so this is just empty initializer for array. */
1013 #define REG_ALLOC_ORDER \
1014 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
1015 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
1016 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1017 48, 49, 50, 51, 52 }
1019 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1020 to be rearranged based on a particular function. When using sse math,
1021 we want to allocate SSE before x87 registers and vice versa. */
1023 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
1026 /* Macro to conditionally modify fixed_regs/call_used_regs. */
1027 #define CONDITIONAL_REGISTER_USAGE \
1031 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1033 if (fixed_regs[i] > 1) \
1034 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
1035 if (call_used_regs[i] > 1) \
1036 call_used_regs[i] = (call_used_regs[i] \
1037 == (TARGET_64BIT ? 3 : 2)); \
1039 j = PIC_OFFSET_TABLE_REGNUM; \
1040 if (j != INVALID_REGNUM) \
1042 fixed_regs[j] = 1; \
1043 call_used_regs[j] = 1; \
1048 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1049 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
1050 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1055 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1056 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
1057 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1059 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
1063 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
1064 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1065 if (TEST_HARD_REG_BIT (x, i)) \
1066 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1068 if (! TARGET_64BIT) \
1071 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
1072 reg_names[i] = ""; \
1073 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
1074 reg_names[i] = ""; \
1076 if (TARGET_64BIT_MS_ABI) \
1078 call_used_regs[4 /*RSI*/] = 0; \
1079 call_used_regs[5 /*RDI*/] = 0; \
1083 /* Return number of consecutive hard regs needed starting at reg REGNO
1084 to hold something of mode MODE.
1085 This is ordinarily the length in words of a value of mode MODE
1086 but can be less for certain modes in special long registers.
1088 Actually there are no two word move instructions for consecutive
1089 registers. And only registers 0-3 may have mov byte instructions
1093 #define HARD_REGNO_NREGS(REGNO, MODE) \
1094 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1095 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1096 : ((MODE) == XFmode \
1097 ? (TARGET_64BIT ? 2 : 3) \
1098 : (MODE) == XCmode \
1099 ? (TARGET_64BIT ? 4 : 6) \
1100 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1102 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1103 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
1104 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1106 : ((MODE) == XFmode || (MODE) == XCmode)) \
1109 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1111 #define VALID_SSE2_REG_MODE(MODE) \
1112 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1113 || (MODE) == V2DImode || (MODE) == DFmode)
1115 #define VALID_SSE_REG_MODE(MODE) \
1116 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1117 || (MODE) == SFmode || (MODE) == TFmode)
1119 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1120 ((MODE) == V2SFmode || (MODE) == SFmode)
1122 #define VALID_MMX_REG_MODE(MODE) \
1123 ((MODE == V1DImode) || (MODE) == DImode \
1124 || (MODE) == V2SImode || (MODE) == SImode \
1125 || (MODE) == V4HImode || (MODE) == V8QImode)
1127 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
1128 place emms and femms instructions. */
1129 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
1131 #define VALID_DFP_MODE_P(MODE) \
1132 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1134 #define VALID_FP_MODE_P(MODE) \
1135 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1136 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1138 #define VALID_INT_MODE_P(MODE) \
1139 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1140 || (MODE) == DImode \
1141 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1142 || (MODE) == CDImode \
1143 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1144 || (MODE) == TFmode || (MODE) == TCmode)))
1146 /* Return true for modes passed in SSE registers. */
1147 #define SSE_REG_MODE_P(MODE) \
1148 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1149 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1150 || (MODE) == V4SFmode || (MODE) == V4SImode)
1152 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1154 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1155 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1157 /* Value is 1 if it is a good idea to tie two pseudo registers
1158 when one has mode MODE1 and one has mode MODE2.
1159 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1160 for any hard reg, then this must be 0 for correct output. */
1162 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1164 /* It is possible to write patterns to move flags; but until someone
1166 #define AVOID_CCMODE_COPIES
1168 /* Specify the modes required to caller save a given hard regno.
1169 We do this on i386 to prevent flags from being saved at all.
1171 Kill any attempts to combine saving of modes. */
1173 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1174 (CC_REGNO_P (REGNO) ? VOIDmode \
1175 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1176 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1177 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1178 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1181 /* Specify the registers used for certain standard purposes.
1182 The values of these macros are register numbers. */
1184 /* on the 386 the pc register is %eip, and is not usable as a general
1185 register. The ordinary mov instructions won't work */
1186 /* #define PC_REGNUM */
1188 /* Register to use for pushing function arguments. */
1189 #define STACK_POINTER_REGNUM 7
1191 /* Base register for access to local variables of the function. */
1192 #define HARD_FRAME_POINTER_REGNUM 6
1194 /* Base register for access to local variables of the function. */
1195 #define FRAME_POINTER_REGNUM 20
1197 /* First floating point reg */
1198 #define FIRST_FLOAT_REG 8
1200 /* First & last stack-like regs */
1201 #define FIRST_STACK_REG FIRST_FLOAT_REG
1202 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1204 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1205 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1207 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1208 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1210 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1211 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1213 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1214 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1216 /* Value should be nonzero if functions must have frame pointers.
1217 Zero means the frame pointer need not be set up (and parms
1218 may be accessed via the stack pointer) in functions that seem suitable.
1219 This is computed in `reload', in reload1.c. */
1220 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1222 /* Override this in other tm.h files to cope with various OS lossage
1223 requiring a frame pointer. */
1224 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1225 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1228 /* Make sure we can access arbitrary call frames. */
1229 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1231 /* Base register for access to arguments of the function. */
1232 #define ARG_POINTER_REGNUM 16
1234 /* Register in which static-chain is passed to a function.
1235 We do use ECX as static chain register for 32 bit ABI. On the
1236 64bit ABI, ECX is an argument register, so we use R10 instead. */
1237 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1239 /* Register to hold the addressing base for position independent
1240 code access to data items. We don't use PIC pointer for 64bit
1241 mode. Define the regnum to dummy value to prevent gcc from
1242 pessimizing code dealing with EBX.
1244 To avoid clobbering a call-saved register unnecessarily, we renumber
1245 the pic register when possible. The change is visible after the
1246 prologue has been emitted. */
1248 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1250 #define PIC_OFFSET_TABLE_REGNUM \
1251 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1252 || !flag_pic ? INVALID_REGNUM \
1253 : reload_completed ? REGNO (pic_offset_table_rtx) \
1254 : REAL_PIC_OFFSET_TABLE_REGNUM)
1256 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1258 /* A C expression which can inhibit the returning of certain function
1259 values in registers, based on the type of value. A nonzero value
1260 says to return the function value in memory, just as large
1261 structures are always returned. Here TYPE will be a C expression
1262 of type `tree', representing the data type of the value.
1264 Note that values of mode `BLKmode' must be explicitly handled by
1265 this macro. Also, the option `-fpcc-struct-return' takes effect
1266 regardless of this macro. On most systems, it is possible to
1267 leave the macro undefined; this causes a default definition to be
1268 used, whose value is the constant 1 for `BLKmode' values, and 0
1271 Do not use this macro to indicate that structures and unions
1272 should always be returned in memory. You should instead use
1273 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1275 #define RETURN_IN_MEMORY(TYPE) \
1276 ix86_return_in_memory (TYPE)
1278 /* This is overridden by <cygwin.h>. */
1279 #define MS_AGGREGATE_RETURN 0
1281 /* This is overridden by <netware.h>. */
1282 #define KEEP_AGGREGATE_RETURN_POINTER 0
1284 /* Define the classes of registers for register constraints in the
1285 machine description. Also define ranges of constants.
1287 One of the classes must always be named ALL_REGS and include all hard regs.
1288 If there is more than one class, another class must be named NO_REGS
1289 and contain no registers.
1291 The name GENERAL_REGS must be the name of a class (or an alias for
1292 another name such as ALL_REGS). This is the class of registers
1293 that is allowed by "g" or "r" in a register constraint.
1294 Also, registers outside this class are allocated only when
1295 instructions express preferences for them.
1297 The classes must be numbered in nondecreasing order; that is,
1298 a larger-numbered class must never be contained completely
1299 in a smaller-numbered class.
1301 For any two classes, it is very desirable that there be another
1302 class that represents their union.
1304 It might seem that class BREG is unnecessary, since no useful 386
1305 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1306 and the "b" register constraint is useful in asms for syscalls.
1308 The flags, fpsr and fpcr registers are in no class. */
1313 AREG, DREG, CREG, BREG, SIREG, DIREG,
1314 AD_REGS, /* %eax/%edx for DImode */
1315 Q_REGS, /* %eax %ebx %ecx %edx */
1316 NON_Q_REGS, /* %esi %edi %ebp %esp */
1317 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1318 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1319 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1320 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1331 ALL_REGS, LIM_REG_CLASSES
1334 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1336 #define INTEGER_CLASS_P(CLASS) \
1337 reg_class_subset_p ((CLASS), GENERAL_REGS)
1338 #define FLOAT_CLASS_P(CLASS) \
1339 reg_class_subset_p ((CLASS), FLOAT_REGS)
1340 #define SSE_CLASS_P(CLASS) \
1341 reg_class_subset_p ((CLASS), SSE_REGS)
1342 #define MMX_CLASS_P(CLASS) \
1343 ((CLASS) == MMX_REGS)
1344 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1345 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1346 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1347 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1348 #define MAYBE_SSE_CLASS_P(CLASS) \
1349 reg_classes_intersect_p (SSE_REGS, (CLASS))
1350 #define MAYBE_MMX_CLASS_P(CLASS) \
1351 reg_classes_intersect_p (MMX_REGS, (CLASS))
1353 #define Q_CLASS_P(CLASS) \
1354 reg_class_subset_p ((CLASS), Q_REGS)
1356 /* Give names of register classes as strings for dump file. */
1358 #define REG_CLASS_NAMES \
1360 "AREG", "DREG", "CREG", "BREG", \
1363 "Q_REGS", "NON_Q_REGS", \
1367 "FP_TOP_REG", "FP_SECOND_REG", \
1372 "FP_TOP_SSE_REGS", \
1373 "FP_SECOND_SSE_REGS", \
1377 "FLOAT_INT_SSE_REGS", \
1380 /* Define which registers fit in which classes.
1381 This is an initializer for a vector of HARD_REG_SET
1382 of length N_REG_CLASSES. */
1384 #define REG_CLASS_CONTENTS \
1386 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1387 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1388 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1389 { 0x03, 0x0 }, /* AD_REGS */ \
1390 { 0x0f, 0x0 }, /* Q_REGS */ \
1391 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1392 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1393 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1394 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1395 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1396 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1397 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1398 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1399 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1400 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1401 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1402 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1403 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1404 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1405 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1406 { 0xffffffff,0x1fffff } \
1409 /* The same information, inverted:
1410 Return the class number of the smallest class containing
1411 reg number REGNO. This could be a conditional expression
1412 or could index an array. */
1414 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1416 /* When defined, the compiler allows registers explicitly used in the
1417 rtl to be used as spill registers but prevents the compiler from
1418 extending the lifetime of these registers. */
1420 #define SMALL_REGISTER_CLASSES 1
1422 #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
1424 #define GENERAL_REGNO_P(N) \
1425 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1427 #define GENERAL_REG_P(X) \
1428 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1430 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1432 #define REX_INT_REGNO_P(N) \
1433 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1434 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1436 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1437 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1438 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1439 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1441 #define X87_FLOAT_MODE_P(MODE) \
1442 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1444 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1445 #define SSE_REGNO_P(N) \
1446 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1447 || REX_SSE_REGNO_P (N))
1449 #define REX_SSE_REGNO_P(N) \
1450 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1452 #define SSE_REGNO(N) \
1453 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1455 #define SSE_FLOAT_MODE_P(MODE) \
1456 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1458 #define SSE_VEC_FLOAT_MODE_P(MODE) \
1459 ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode))
1461 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1462 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1464 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1465 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1467 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1469 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1470 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1472 /* The class value for index registers, and the one for base regs. */
1474 #define INDEX_REG_CLASS INDEX_REGS
1475 #define BASE_REG_CLASS GENERAL_REGS
1477 /* Place additional restrictions on the register class to use when it
1478 is necessary to be able to hold a value of mode MODE in a reload
1479 register for which class CLASS would ordinarily be used. */
1481 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1482 ((MODE) == QImode && !TARGET_64BIT \
1483 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1484 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1487 /* Given an rtx X being reloaded into a reg required to be
1488 in class CLASS, return the class of reg to actually use.
1489 In general this is just CLASS; but on some machines
1490 in some cases it is preferable to use a more restrictive class.
1491 On the 80386 series, we prevent floating constants from being
1492 reloaded into floating registers (since no move-insn can do that)
1493 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1495 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1496 QImode must go into class Q_REGS.
1497 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1498 movdf to do mem-to-mem moves through integer regs. */
1500 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1501 ix86_preferred_reload_class ((X), (CLASS))
1503 /* Discourage putting floating-point values in SSE registers unless
1504 SSE math is being used, and likewise for the 387 registers. */
1506 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1507 ix86_preferred_output_reload_class ((X), (CLASS))
1509 /* If we are copying between general and FP registers, we need a memory
1510 location. The same is true for SSE and MMX registers. */
1511 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1512 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1514 /* QImode spills from non-QI registers need a scratch. This does not
1515 happen often -- the only example so far requires an uninitialized
1518 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1519 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1520 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1523 /* Return the maximum number of consecutive registers
1524 needed to represent mode MODE in a register of class CLASS. */
1525 /* On the 80386, this is the size of MODE in words,
1526 except in the FP regs, where a single reg is always enough. */
1527 #define CLASS_MAX_NREGS(CLASS, MODE) \
1528 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1529 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1530 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1531 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1533 /* A C expression whose value is nonzero if pseudos that have been
1534 assigned to registers of class CLASS would likely be spilled
1535 because registers of CLASS are needed for spill registers.
1537 The default value of this macro returns 1 if CLASS has exactly one
1538 register and zero otherwise. On most machines, this default
1539 should be used. Only define this macro to some other expression
1540 if pseudo allocated by `local-alloc.c' end up in memory because
1541 their hard registers were needed for spill registers. If this
1542 macro returns nonzero for those classes, those pseudos will only
1543 be allocated by `global.c', which knows how to reallocate the
1544 pseudo to another register. If there would not be another
1545 register available for reallocation, you should not change the
1546 definition of this macro since the only effect of such a
1547 definition would be to slow down register allocation. */
1549 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1550 (((CLASS) == AREG) \
1551 || ((CLASS) == DREG) \
1552 || ((CLASS) == CREG) \
1553 || ((CLASS) == BREG) \
1554 || ((CLASS) == AD_REGS) \
1555 || ((CLASS) == SIREG) \
1556 || ((CLASS) == DIREG) \
1557 || ((CLASS) == FP_TOP_REG) \
1558 || ((CLASS) == FP_SECOND_REG))
1560 /* Return a class of registers that cannot change FROM mode to TO mode. */
1562 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1563 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1565 /* Stack layout; function entry, exit and calling. */
1567 /* Define this if pushing a word on the stack
1568 makes the stack pointer a smaller address. */
1569 #define STACK_GROWS_DOWNWARD
1571 /* Define this to nonzero if the nominal address of the stack frame
1572 is at the high-address end of the local variables;
1573 that is, each additional local variable allocated
1574 goes at a more negative offset in the frame. */
1575 #define FRAME_GROWS_DOWNWARD 1
1577 /* Offset within stack frame to start allocating local variables at.
1578 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1579 first local allocated. Otherwise, it is the offset to the BEGINNING
1580 of the first local allocated. */
1581 #define STARTING_FRAME_OFFSET 0
1583 /* If we generate an insn to push BYTES bytes,
1584 this says how many the stack pointer really advances by.
1585 On 386, we have pushw instruction that decrements by exactly 2 no
1586 matter what the position was, there is no pushb.
1587 But as CIE data alignment factor on this arch is -4, we need to make
1588 sure all stack pointer adjustments are in multiple of 4.
1590 For 64bit ABI we round up to 8 bytes.
1593 #define PUSH_ROUNDING(BYTES) \
1595 ? (((BYTES) + 7) & (-8)) \
1596 : (((BYTES) + 3) & (-4)))
1598 /* If defined, the maximum amount of space required for outgoing arguments will
1599 be computed and placed into the variable
1600 `current_function_outgoing_args_size'. No space will be pushed onto the
1601 stack for each call; instead, the function prologue should increase the stack
1602 frame size by this amount. */
1604 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1606 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1607 instructions to pass outgoing arguments. */
1609 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1611 /* We want the stack and args grow in opposite directions, even if
1613 #define PUSH_ARGS_REVERSED 1
1615 /* Offset of first parameter from the argument pointer register value. */
1616 #define FIRST_PARM_OFFSET(FNDECL) 0
1618 /* Define this macro if functions should assume that stack space has been
1619 allocated for arguments even when their values are passed in registers.
1621 The value of this macro is the size, in bytes, of the area reserved for
1622 arguments passed in registers for the function represented by FNDECL.
1624 This space can be allocated by the caller, or be a part of the
1625 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1627 #define REG_PARM_STACK_SPACE(FNDECL) 0
1629 /* Value is the number of bytes of arguments automatically
1630 popped when returning from a subroutine call.
1631 FUNDECL is the declaration node of the function (as a tree),
1632 FUNTYPE is the data type of the function (as a tree),
1633 or for a library call it is an identifier node for the subroutine name.
1634 SIZE is the number of bytes of arguments passed on the stack.
1636 On the 80386, the RTD insn may be used to pop them if the number
1637 of args is fixed, but if the number is variable then the caller
1638 must pop them all. RTD can't be used for library calls now
1639 because the library is compiled with the Unix compiler.
1640 Use of RTD is a selectable option, since it is incompatible with
1641 standard Unix calling sequences. If the option is not selected,
1642 the caller must always pop the args.
1644 The attribute stdcall is equivalent to RTD on a per module basis. */
1646 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1647 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1649 #define FUNCTION_VALUE_REGNO_P(N) \
1650 ix86_function_value_regno_p (N)
1652 /* Define how to find the value returned by a library function
1653 assuming the value has mode MODE. */
1655 #define LIBCALL_VALUE(MODE) \
1656 ix86_libcall_value (MODE)
1658 /* Define the size of the result block used for communication between
1659 untyped_call and untyped_return. The block contains a DImode value
1660 followed by the block used by fnsave and frstor. */
1662 #define APPLY_RESULT_SIZE (8+108)
1664 /* 1 if N is a possible register number for function argument passing. */
1665 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1667 /* Define a data type for recording info about an argument list
1668 during the scan of that argument list. This data type should
1669 hold all necessary information about the function itself
1670 and about the args processed so far, enough to enable macros
1671 such as FUNCTION_ARG to determine where the next arg should go. */
1673 typedef struct ix86_args {
1674 int words; /* # words passed so far */
1675 int nregs; /* # registers available for passing */
1676 int regno; /* next available register number */
1677 int fastcall; /* fastcall calling convention is used */
1678 int sse_words; /* # sse words passed so far */
1679 int sse_nregs; /* # sse registers available for passing */
1680 int warn_sse; /* True when we want to warn about SSE ABI. */
1681 int warn_mmx; /* True when we want to warn about MMX ABI. */
1682 int sse_regno; /* next available sse register number */
1683 int mmx_words; /* # mmx words passed so far */
1684 int mmx_nregs; /* # mmx registers available for passing */
1685 int mmx_regno; /* next available mmx register number */
1686 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1687 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1688 be passed in SSE registers. Otherwise 0. */
1691 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1692 for a call to a function whose data type is FNTYPE.
1693 For a library call, FNTYPE is 0. */
1695 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1696 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1698 /* Update the data in CUM to advance over an argument
1699 of mode MODE and data type TYPE.
1700 (TYPE is null for libcalls where that information may not be available.) */
1702 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1703 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1705 /* Define where to put the arguments to a function.
1706 Value is zero to push the argument on the stack,
1707 or a hard register in which to store the argument.
1709 MODE is the argument's machine mode.
1710 TYPE is the data type of the argument (as a tree).
1711 This is null for libcalls where that information may
1713 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1714 the preceding args and about the function being called.
1715 NAMED is nonzero if this argument is a named parameter
1716 (otherwise it is an extra parameter matching an ellipsis). */
1718 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1719 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1721 #define TARGET_ASM_FILE_END ix86_file_end
1722 #define NEED_INDICATE_EXEC_STACK 0
1724 /* Output assembler code to FILE to increment profiler label # LABELNO
1725 for profiling a function entry. */
1727 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1729 #define MCOUNT_NAME "_mcount"
1731 #define PROFILE_COUNT_REGISTER "edx"
1733 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1734 the stack pointer does not matter. The value is tested only in
1735 functions that have frame pointers.
1736 No definition is equivalent to always zero. */
1737 /* Note on the 386 it might be more efficient not to define this since
1738 we have to restore it ourselves from the frame pointer, in order to
1741 #define EXIT_IGNORE_STACK 1
1743 /* Output assembler code for a block containing the constant parts
1744 of a trampoline, leaving space for the variable parts. */
1746 /* On the 386, the trampoline contains two instructions:
1749 The trampoline is generated entirely at runtime. The operand of JMP
1750 is the address of FUNCTION relative to the instruction following the
1751 JMP (which is 5 bytes long). */
1753 /* Length in units of the trampoline for entering a nested function. */
1755 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1757 /* Emit RTL insns to initialize the variable parts of a trampoline.
1758 FNADDR is an RTX for the address of the function's pure code.
1759 CXT is an RTX for the static chain value for the function. */
1761 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1762 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1764 /* Definitions for register eliminations.
1766 This is an array of structures. Each structure initializes one pair
1767 of eliminable registers. The "from" register number is given first,
1768 followed by "to". Eliminations of the same "from" register are listed
1769 in order of preference.
1771 There are two registers that can always be eliminated on the i386.
1772 The frame pointer and the arg pointer can be replaced by either the
1773 hard frame pointer or to the stack pointer, depending upon the
1774 circumstances. The hard frame pointer is not used before reload and
1775 so it is not eligible for elimination. */
1777 #define ELIMINABLE_REGS \
1778 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1779 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1780 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1781 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1783 /* Given FROM and TO register numbers, say whether this elimination is
1784 allowed. Frame pointer elimination is automatically handled.
1786 All other eliminations are valid. */
1788 #define CAN_ELIMINATE(FROM, TO) \
1789 ((TO) == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1)
1791 /* Define the offset between two registers, one to be eliminated, and the other
1792 its replacement, at the start of a routine. */
1794 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1795 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1797 /* Addressing modes, and classification of registers for them. */
1799 /* Macros to check register numbers against specific register classes. */
1801 /* These assume that REGNO is a hard or pseudo reg number.
1802 They give nonzero only if REGNO is a hard reg of the suitable class
1803 or a pseudo reg currently allocated to a suitable hard reg.
1804 Since they use reg_renumber, they are safe only once reg_renumber
1805 has been allocated, which happens in local-alloc.c. */
1807 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1808 ((REGNO) < STACK_POINTER_REGNUM \
1809 || REX_INT_REGNO_P (REGNO) \
1810 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1811 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1813 #define REGNO_OK_FOR_BASE_P(REGNO) \
1814 (GENERAL_REGNO_P (REGNO) \
1815 || (REGNO) == ARG_POINTER_REGNUM \
1816 || (REGNO) == FRAME_POINTER_REGNUM \
1817 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1819 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1820 and check its validity for a certain class.
1821 We have two alternate definitions for each of them.
1822 The usual definition accepts all pseudo regs; the other rejects
1823 them unless they have been allocated suitable hard regs.
1824 The symbol REG_OK_STRICT causes the latter definition to be used.
1826 Most source files want to accept pseudo regs in the hope that
1827 they will get allocated to the class that the insn wants them to be in.
1828 Source files for reload pass need to be strict.
1829 After reload, it makes no difference, since pseudo regs have
1830 been eliminated by then. */
1833 /* Non strict versions, pseudos are ok. */
1834 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1835 (REGNO (X) < STACK_POINTER_REGNUM \
1836 || REX_INT_REGNO_P (REGNO (X)) \
1837 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1839 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1840 (GENERAL_REGNO_P (REGNO (X)) \
1841 || REGNO (X) == ARG_POINTER_REGNUM \
1842 || REGNO (X) == FRAME_POINTER_REGNUM \
1843 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1845 /* Strict versions, hard registers only */
1846 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1847 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1849 #ifndef REG_OK_STRICT
1850 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1851 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1854 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1855 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1858 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1859 that is a valid memory address for an instruction.
1860 The MODE argument is the machine mode for the MEM expression
1861 that wants to use this address.
1863 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1864 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1866 See legitimize_pic_address in i386.c for details as to what
1867 constitutes a legitimate address when -fpic is used. */
1869 #define MAX_REGS_PER_ADDRESS 2
1871 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1873 /* Nonzero if the constant value X is a legitimate general operand.
1874 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1876 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1878 #ifdef REG_OK_STRICT
1879 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1881 if (legitimate_address_p ((MODE), (X), 1)) \
1886 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1888 if (legitimate_address_p ((MODE), (X), 0)) \
1894 /* If defined, a C expression to determine the base term of address X.
1895 This macro is used in only one place: `find_base_term' in alias.c.
1897 It is always safe for this macro to not be defined. It exists so
1898 that alias analysis can understand machine-dependent addresses.
1900 The typical use of this macro is to handle addresses containing
1901 a label_ref or symbol_ref within an UNSPEC. */
1903 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1905 /* Try machine-dependent ways of modifying an illegitimate address
1906 to be legitimate. If we find one, return the new, valid address.
1907 This macro is used in only one place: `memory_address' in explow.c.
1909 OLDX is the address as it was before break_out_memory_refs was called.
1910 In some cases it is useful to look at this to decide what needs to be done.
1912 MODE and WIN are passed so that this macro can use
1913 GO_IF_LEGITIMATE_ADDRESS.
1915 It is always safe for this macro to do nothing. It exists to recognize
1916 opportunities to optimize the output.
1918 For the 80386, we handle X+REG by loading X into a register R and
1919 using R+REG. R will go in a general reg and indexing will be used.
1920 However, if REG is a broken-out memory address or multiplication,
1921 nothing needs to be done because REG can certainly go in a general reg.
1923 When -fpic is used, special handling is needed for symbolic references.
1924 See comments by legitimize_pic_address in i386.c for details. */
1926 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1928 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1929 if (memory_address_p ((MODE), (X))) \
1933 /* Nonzero if the constant value X is a legitimate general operand
1934 when generating PIC code. It is given that flag_pic is on and
1935 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1937 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1939 #define SYMBOLIC_CONST(X) \
1940 (GET_CODE (X) == SYMBOL_REF \
1941 || GET_CODE (X) == LABEL_REF \
1942 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1944 /* Go to LABEL if ADDR (a legitimate address expression)
1945 has an effect that depends on the machine mode it is used for.
1946 On the 80386, only postdecrement and postincrement address depend thus
1947 (the amount of decrement or increment being the length of the operand).
1948 These are now caught in recog.c. */
1949 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
1951 /* Max number of args passed in registers. If this is more than 3, we will
1952 have problems with ebx (register #4), since it is a caller save register and
1953 is also used as the pic register in ELF. So for now, don't allow more than
1954 3 registers to be passed in registers. */
1956 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1958 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1960 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1963 /* Specify the machine mode that this machine uses
1964 for the index in the tablejump instruction. */
1965 #define CASE_VECTOR_MODE \
1966 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1968 /* Define this as 1 if `char' should by default be signed; else as 0. */
1969 #define DEFAULT_SIGNED_CHAR 1
1971 /* Max number of bytes we can move from memory to memory
1972 in one reasonably fast instruction. */
1975 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1976 move efficiently, as opposed to MOVE_MAX which is the maximum
1977 number of bytes we can move with a single instruction. */
1978 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1980 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1981 move-instruction pairs, we will do a movmem or libcall instead.
1982 Increasing the value will always make code faster, but eventually
1983 incurs high cost in increased code size.
1985 If you don't define this, a reasonable default is used. */
1987 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1989 /* If a clear memory operation would take CLEAR_RATIO or more simple
1990 move-instruction sequences, we will do a clrmem or libcall instead. */
1992 #define CLEAR_RATIO (optimize_size ? 2 : MIN (6, ix86_cost->move_ratio))
1994 /* Define if shifts truncate the shift count
1995 which implies one can omit a sign-extension or zero-extension
1996 of a shift count. */
1997 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1999 /* #define SHIFT_COUNT_TRUNCATED */
2001 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2002 is done just by pretending it is already truncated. */
2003 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2005 /* A macro to update M and UNSIGNEDP when an object whose type is
2006 TYPE and which has the specified mode and signedness is to be
2007 stored in a register. This macro is only called when TYPE is a
2010 On i386 it is sometimes useful to promote HImode and QImode
2011 quantities to SImode. The choice depends on target type. */
2013 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2015 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2016 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2020 /* Specify the machine mode that pointers have.
2021 After generation of rtl, the compiler makes no further distinction
2022 between pointers and any other objects of this machine mode. */
2023 #define Pmode (TARGET_64BIT ? DImode : SImode)
2025 /* A function address in a call instruction
2026 is a byte address (for indexing purposes)
2027 so give the MEM rtx a byte's mode. */
2028 #define FUNCTION_MODE QImode
2030 /* A C expression for the cost of moving data from a register in class FROM to
2031 one in class TO. The classes are expressed using the enumeration values
2032 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2033 interpreted relative to that.
2035 It is not required that the cost always equal 2 when FROM is the same as TO;
2036 on some machines it is expensive to move between registers if they are not
2037 general registers. */
2039 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2040 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2042 /* A C expression for the cost of moving data of mode M between a
2043 register and memory. A value of 2 is the default; this cost is
2044 relative to those in `REGISTER_MOVE_COST'.
2046 If moving between registers and memory is more expensive than
2047 between two registers, you should define this macro to express the
2050 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2051 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2053 /* A C expression for the cost of a branch instruction. A value of 1
2054 is the default; other values are interpreted relative to that. */
2056 #define BRANCH_COST ix86_branch_cost
2058 /* Define this macro as a C expression which is nonzero if accessing
2059 less than a word of memory (i.e. a `char' or a `short') is no
2060 faster than accessing a word of memory, i.e., if such access
2061 require more than one instruction or if there is no difference in
2062 cost between byte and (aligned) word loads.
2064 When this macro is not defined, the compiler will access a field by
2065 finding the smallest containing object; when it is defined, a
2066 fullword load will be used if alignment permits. Unless bytes
2067 accesses are faster than word accesses, using word accesses is
2068 preferable since it may eliminate subsequent memory access if
2069 subsequent accesses occur to other fields in the same word of the
2070 structure, but to different bytes. */
2072 #define SLOW_BYTE_ACCESS 0
2074 /* Nonzero if access to memory by shorts is slow and undesirable. */
2075 #define SLOW_SHORT_ACCESS 0
2077 /* Define this macro to be the value 1 if unaligned accesses have a
2078 cost many times greater than aligned accesses, for example if they
2079 are emulated in a trap handler.
2081 When this macro is nonzero, the compiler will act as if
2082 `STRICT_ALIGNMENT' were nonzero when generating code for block
2083 moves. This can cause significantly more instructions to be
2084 produced. Therefore, do not set this macro nonzero if unaligned
2085 accesses only add a cycle or two to the time for a memory access.
2087 If the value of this macro is always zero, it need not be defined. */
2089 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2091 /* Define this macro if it is as good or better to call a constant
2092 function address than to call an address kept in a register.
2094 Desirable on the 386 because a CALL with a constant address is
2095 faster than one with a register address. */
2097 #define NO_FUNCTION_CSE
2099 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2100 return the mode to be used for the comparison.
2102 For floating-point equality comparisons, CCFPEQmode should be used.
2103 VOIDmode should be used in all other cases.
2105 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2106 possible, to allow for more combinations. */
2108 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2110 /* Return nonzero if MODE implies a floating point inequality can be
2113 #define REVERSIBLE_CC_MODE(MODE) 1
2115 /* A C expression whose value is reversed condition code of the CODE for
2116 comparison done in CC_MODE mode. */
2117 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2120 /* Control the assembler format that we output, to the extent
2121 this does not vary between assemblers. */
2123 /* How to refer to registers in assembler output.
2124 This sequence is indexed by compiler's hard-register-number (see above). */
2126 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2127 For non floating point regs, the following are the HImode names.
2129 For float regs, the stack top is sometimes referred to as "%st(0)"
2130 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2132 #define HI_REGISTER_NAMES \
2133 {"ax","dx","cx","bx","si","di","bp","sp", \
2134 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2135 "argp", "flags", "fpsr", "fpcr", "frame", \
2136 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2137 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2138 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2139 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2141 #define REGISTER_NAMES HI_REGISTER_NAMES
2143 /* Table of additional register names to use in user input. */
2145 #define ADDITIONAL_REGISTER_NAMES \
2146 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2147 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2148 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2149 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2150 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2151 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2153 /* Note we are omitting these since currently I don't know how
2154 to get gcc to use these, since they want the same but different
2155 number as al, and ax.
2158 #define QI_REGISTER_NAMES \
2159 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2161 /* These parallel the array above, and can be used to access bits 8:15
2162 of regs 0 through 3. */
2164 #define QI_HIGH_REGISTER_NAMES \
2165 {"ah", "dh", "ch", "bh", }
2167 /* How to renumber registers for dbx and gdb. */
2169 #define DBX_REGISTER_NUMBER(N) \
2170 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2172 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2173 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2174 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2176 /* Before the prologue, RA is at 0(%esp). */
2177 #define INCOMING_RETURN_ADDR_RTX \
2178 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2180 /* After the prologue, RA is at -4(AP) in the current frame. */
2181 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2183 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2184 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2186 /* PC is dbx register 8; let's use that column for RA. */
2187 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2189 /* Before the prologue, the top of the frame is at 4(%esp). */
2190 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2192 /* Describe how we implement __builtin_eh_return. */
2193 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2194 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2197 /* Select a format to encode pointers in exception handling data. CODE
2198 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2199 true if the symbol may be affected by dynamic relocations.
2201 ??? All x86 object file formats are capable of representing this.
2202 After all, the relocation needed is the same as for the call insn.
2203 Whether or not a particular assembler allows us to enter such, I
2204 guess we'll have to see. */
2205 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2206 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2208 /* This is how to output an insn to push a register on the stack.
2209 It need not be very fast code. */
2211 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2214 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2215 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2217 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2220 /* This is how to output an insn to pop a register from the stack.
2221 It need not be very fast code. */
2223 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2226 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2227 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2229 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2232 /* This is how to output an element of a case-vector that is absolute. */
2234 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2235 ix86_output_addr_vec_elt ((FILE), (VALUE))
2237 /* This is how to output an element of a case-vector that is relative. */
2239 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2240 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2242 /* Under some conditions we need jump tables in the text section,
2243 because the assembler cannot handle label differences between
2244 sections. This is the case for x86_64 on Mach-O for example. */
2246 #define JUMP_TABLES_IN_TEXT_SECTION \
2247 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2248 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2250 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2251 and switch back. For x86 we do this only to save a few bytes that
2252 would otherwise be unused in the text section. */
2253 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2254 asm (SECTION_OP "\n\t" \
2255 "call " USER_LABEL_PREFIX #FUNC "\n" \
2256 TEXT_SECTION_ASM_OP);
2258 /* Print operand X (an rtx) in assembler syntax to file FILE.
2259 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2260 Effect of various CODE letters is described in i386.c near
2261 print_operand function. */
2263 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2264 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';')
2266 #define PRINT_OPERAND(FILE, X, CODE) \
2267 print_operand ((FILE), (X), (CODE))
2269 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2270 print_operand_address ((FILE), (ADDR))
2272 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2274 if (! output_addr_const_extra (FILE, (X))) \
2278 /* Which processor to schedule for. The cpu attribute defines a list that
2279 mirrors this list, so changes to i386.md must be made at the same time. */
2283 PROCESSOR_I386 = 0, /* 80386 */
2284 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2286 PROCESSOR_PENTIUMPRO,
2294 PROCESSOR_GENERIC32,
2295 PROCESSOR_GENERIC64,
2300 extern enum processor_type ix86_tune;
2301 extern enum processor_type ix86_arch;
2309 extern enum fpmath_unit ix86_fpmath;
2318 extern enum tls_dialect ix86_tls_dialect;
2321 CM_32, /* The traditional 32-bit ABI. */
2322 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2323 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2324 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2325 CM_LARGE, /* No assumptions. */
2326 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2327 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2328 CM_LARGE_PIC /* No assumptions. */
2331 extern enum cmodel ix86_cmodel;
2333 /* Size of the RED_ZONE area. */
2334 #define RED_ZONE_SIZE 128
2335 /* Reserved area of the red zone for temporaries. */
2336 #define RED_ZONE_RESERVE 8
2343 extern enum asm_dialect ix86_asm_dialect;
2344 extern unsigned int ix86_preferred_stack_boundary;
2345 extern int ix86_branch_cost, ix86_section_threshold;
2347 /* Smallest class containing REGNO. */
2348 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2350 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2351 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2352 extern rtx ix86_compare_emitted;
2354 /* To properly truncate FP values into integers, we need to set i387 control
2355 word. We can't emit proper mode switching code before reload, as spills
2356 generated by reload may truncate values incorrectly, but we still can avoid
2357 redundant computation of new control word by the mode switching pass.
2358 The fldcw instructions are still emitted redundantly, but this is probably
2359 not going to be noticeable problem, as most CPUs do have fast path for
2362 The machinery is to emit simple truncation instructions and split them
2363 before reload to instructions having USEs of two memory locations that
2364 are filled by this code to old and new control word.
2366 Post-reload pass may be later used to eliminate the redundant fildcw if
2378 enum ix86_stack_slot
2387 MAX_386_STACK_LOCALS
2390 /* Define this macro if the port needs extra instructions inserted
2391 for mode switching in an optimizing compilation. */
2393 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2394 ix86_optimize_mode_switching[(ENTITY)]
2396 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2397 initializer for an array of integers. Each initializer element N
2398 refers to an entity that needs mode switching, and specifies the
2399 number of different modes that might need to be set for this
2400 entity. The position of the initializer in the initializer -
2401 starting counting at zero - determines the integer that is used to
2402 refer to the mode-switched entity in question. */
2404 #define NUM_MODES_FOR_MODE_SWITCHING \
2405 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2407 /* ENTITY is an integer specifying a mode-switched entity. If
2408 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2409 return an integer value not larger than the corresponding element
2410 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2411 must be switched into prior to the execution of INSN. */
2413 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2415 /* This macro specifies the order in which modes for ENTITY are
2416 processed. 0 is the highest priority. */
2418 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2420 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2421 is the set of hard registers live at the point where the insn(s)
2422 are to be inserted. */
2424 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2425 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2426 ? emit_i387_cw_initialization (MODE), 0 \
2430 /* Avoid renaming of stack registers, as doing so in combination with
2431 scheduling just increases amount of live registers at time and in
2432 the turn amount of fxch instructions needed.
2434 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2436 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2437 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2440 #define FASTCALL_PREFIX '@'
2442 struct machine_function GTY(())
2444 struct stack_local_entry *stack_locals;
2445 const char *some_ld_name;
2446 rtx force_align_arg_pointer;
2447 int save_varrargs_registers;
2448 int accesses_prev_frame;
2449 int optimize_mode_switching[MAX_386_ENTITIES];
2450 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2451 determine the style used. */
2452 int use_fast_prologue_epilogue;
2453 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2455 int use_fast_prologue_epilogue_nregs;
2456 /* If true, the current function needs the default PIC register, not
2457 an alternate register (on x86) and must not use the red zone (on
2458 x86_64), even if it's a leaf function. We don't want the
2459 function to be regarded as non-leaf because TLS calls need not
2460 affect register allocation. This flag is set when a TLS call
2461 instruction is expanded within a function, and never reset, even
2462 if all such instructions are optimized away. Use the
2463 ix86_current_function_calls_tls_descriptor macro for a better
2465 int tls_descriptor_call_expanded_p;
2468 #define ix86_stack_locals (cfun->machine->stack_locals)
2469 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2470 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2471 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2472 (cfun->machine->tls_descriptor_call_expanded_p)
2473 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2474 calls are optimized away, we try to detect cases in which it was
2475 optimized away. Since such instructions (use (reg REG_SP)), we can
2476 verify whether there's any such instruction live by testing that
2478 #define ix86_current_function_calls_tls_descriptor \
2479 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2481 /* Control behavior of x86_file_start. */
2482 #define X86_FILE_START_VERSION_DIRECTIVE false
2483 #define X86_FILE_START_FLTUSED false
2485 /* Flag to mark data that is in the large address area. */
2486 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2487 #define SYMBOL_REF_FAR_ADDR_P(X) \
2488 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2490 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2491 have defined always, to avoid ifdefing. */
2492 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2493 #define SYMBOL_REF_DLLIMPORT_P(X) \
2494 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2496 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2497 #define SYMBOL_REF_DLLEXPORT_P(X) \
2498 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2500 /* Model costs for vectorizer. */
2502 /* Cost of conditional branch. */
2503 #undef TARG_COND_BRANCH_COST
2504 #define TARG_COND_BRANCH_COST ix86_cost->branch_cost
2506 /* Cost of any scalar operation, excluding load and store. */
2507 #undef TARG_SCALAR_STMT_COST
2508 #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost
2510 /* Cost of scalar load. */
2511 #undef TARG_SCALAR_LOAD_COST
2512 #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost
2514 /* Cost of scalar store. */
2515 #undef TARG_SCALAR_STORE_COST
2516 #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost
2518 /* Cost of any vector operation, excluding load, store or vector to scalar
2520 #undef TARG_VEC_STMT_COST
2521 #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost
2523 /* Cost of vector to scalar operation. */
2524 #undef TARG_VEC_TO_SCALAR_COST
2525 #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost
2527 /* Cost of scalar to vector operation. */
2528 #undef TARG_SCALAR_TO_VEC_COST
2529 #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost
2531 /* Cost of aligned vector load. */
2532 #undef TARG_VEC_LOAD_COST
2533 #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost
2535 /* Cost of misaligned vector load. */
2536 #undef TARG_VEC_UNALIGNED_LOAD_COST
2537 #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost
2539 /* Cost of vector store. */
2540 #undef TARG_VEC_STORE_COST
2541 #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost
2543 /* Cost of conditional taken branch for vectorizer cost model. */
2544 #undef TARG_COND_TAKEN_BRANCH_COST
2545 #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost
2547 /* Cost of conditional not taken branch for vectorizer cost model. */
2548 #undef TARG_COND_NOT_TAKEN_BRANCH_COST
2549 #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost
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