1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
23 /* Algorithm to expand string function with. */
35 #define NAX_STRINGOP_ALGS 4
36 /* Specify what algorithm to use for stringops on known size.
37 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
38 known at compile time or estimated via feedback, the SIZE array
39 is walked in order until MAX is greater then the estimate (or -1
40 means infinity). Corresponding ALG is used then.
41 For example initializer:
42 {{256, loop}, {-1, rep_prefix_4_byte}}
43 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
48 const enum stringop_alg unknown_size;
49 const struct stringop_strategy {
51 const enum stringop_alg alg;
52 } size [NAX_STRINGOP_ALGS];
55 /* The purpose of this file is to define the characteristics of the i386,
56 independent of assembler syntax or operating system.
58 Three other files build on this one to describe a specific assembler syntax:
59 bsd386.h, att386.h, and sun386.h.
61 The actual tm.h file for a particular system should include
62 this file, and then the file for the appropriate assembler syntax.
64 Many macros that specify assembler syntax are omitted entirely from
65 this file because they really belong in the files for particular
66 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
67 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
68 that start with ASM_ or end in ASM_OP. */
70 /* Define the specific costs for a given cpu */
72 struct processor_costs {
73 const int add; /* cost of an add instruction */
74 const int lea; /* cost of a lea instruction */
75 const int shift_var; /* variable shift costs */
76 const int shift_const; /* constant shift costs */
77 const int mult_init[5]; /* cost of starting a multiply
78 in QImode, HImode, SImode, DImode, TImode*/
79 const int mult_bit; /* cost of multiply per each bit set */
80 const int divide[5]; /* cost of a divide/mod
81 in QImode, HImode, SImode, DImode, TImode*/
82 int movsx; /* The cost of movsx operation. */
83 int movzx; /* The cost of movzx operation. */
84 const int large_insn; /* insns larger than this cost more */
85 const int move_ratio; /* The threshold of number of scalar
86 memory-to-memory move insns. */
87 const int movzbl_load; /* cost of loading using movzbl */
88 const int int_load[3]; /* cost of loading integer registers
89 in QImode, HImode and SImode relative
90 to reg-reg move (2). */
91 const int int_store[3]; /* cost of storing integer register
92 in QImode, HImode and SImode */
93 const int fp_move; /* cost of reg,reg fld/fst */
94 const int fp_load[3]; /* cost of loading FP register
95 in SFmode, DFmode and XFmode */
96 const int fp_store[3]; /* cost of storing FP register
97 in SFmode, DFmode and XFmode */
98 const int mmx_move; /* cost of moving MMX register. */
99 const int mmx_load[2]; /* cost of loading MMX register
100 in SImode and DImode */
101 const int mmx_store[2]; /* cost of storing MMX register
102 in SImode and DImode */
103 const int sse_move; /* cost of moving SSE register. */
104 const int sse_load[3]; /* cost of loading SSE register
105 in SImode, DImode and TImode*/
106 const int sse_store[3]; /* cost of storing SSE register
107 in SImode, DImode and TImode*/
108 const int mmxsse_to_integer; /* cost of moving mmxsse register to
109 integer and vice versa. */
110 const int prefetch_block; /* bytes moved to cache for prefetch. */
111 const int simultaneous_prefetches; /* number of parallel prefetch
113 const int branch_cost; /* Default value for BRANCH_COST. */
114 const int fadd; /* cost of FADD and FSUB instructions. */
115 const int fmul; /* cost of FMUL instruction. */
116 const int fdiv; /* cost of FDIV instruction. */
117 const int fabs; /* cost of FABS instruction. */
118 const int fchs; /* cost of FCHS instruction. */
119 const int fsqrt; /* cost of FSQRT instruction. */
120 /* Specify what algorithm
121 to use for stringops on unknown size. */
122 struct stringop_algs memcpy[2], memset[2];
125 extern const struct processor_costs *ix86_cost;
127 /* Macros used in the machine description to test the flags. */
129 /* configure can arrange to make this 2, to force a 486. */
131 #ifndef TARGET_CPU_DEFAULT
132 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
135 #ifndef TARGET_FPMATH_DEFAULT
136 #define TARGET_FPMATH_DEFAULT \
137 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
140 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
142 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
143 compile-time constant. */
147 #define TARGET_64BIT 1
149 #define TARGET_64BIT 0
152 #ifndef TARGET_BI_ARCH
154 #if TARGET_64BIT_DEFAULT
155 #define TARGET_64BIT 1
157 #define TARGET_64BIT 0
162 #define HAS_LONG_COND_BRANCH 1
163 #define HAS_LONG_UNCOND_BRANCH 1
165 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
166 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
167 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
168 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
169 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
170 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
171 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
172 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
173 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
174 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
175 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
176 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
177 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
178 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
179 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
180 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
182 #define TUNEMASK (1 << ix86_tune)
183 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
184 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
185 extern const int x86_branch_hints, x86_unroll_strlen;
186 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
187 extern const int x86_use_himode_fiop, x86_use_simode_fiop;
188 extern const int x86_use_mov0, x86_use_cltd, x86_read_modify_write;
189 extern const int x86_read_modify, x86_split_long_moves;
190 extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
191 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
192 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
193 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
194 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
195 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
196 extern const int x86_epilogue_using_move, x86_decompose_lea;
197 extern const int x86_arch_always_fancy_math_387, x86_shift1;
198 extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
199 extern const int x86_sse_unaligned_move_optimal;
200 extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
201 extern const int x86_use_ffreep;
202 extern const int x86_inter_unit_moves, x86_schedule;
203 extern const int x86_use_bt;
204 extern const int x86_cmpxchg, x86_cmpxchg8b, x86_xadd;
205 extern const int x86_use_incdec;
206 extern const int x86_pad_returns;
207 extern const int x86_bswap;
208 extern const int x86_partial_flag_reg_stall;
209 extern int x86_prefetch_sse, x86_cmpxchg16b;
211 #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
212 #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
213 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
214 #define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
215 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
216 /* For sane SSE instruction set generation we need fcomi instruction. It is
217 safe to enable all CMOVE instructions. */
218 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
219 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
220 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
221 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
222 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
223 #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
224 #define TARGET_MOVX (x86_movx & TUNEMASK)
225 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
226 #define TARGET_PARTIAL_FLAG_REG_STALL (x86_partial_flag_reg_stall & TUNEMASK)
227 #define TARGET_USE_HIMODE_FIOP (x86_use_himode_fiop & TUNEMASK)
228 #define TARGET_USE_SIMODE_FIOP (x86_use_simode_fiop & TUNEMASK)
229 #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
230 #define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
231 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
232 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
233 #define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
234 #define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
235 #define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
236 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
237 #define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
238 #define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
239 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
240 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
241 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
242 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
243 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
244 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
245 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
246 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
247 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
248 (x86_sse_partial_reg_dependency & TUNEMASK)
249 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
250 (x86_sse_unaligned_move_optimal & TUNEMASK)
251 #define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
252 #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
253 #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
254 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
255 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
256 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
257 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
258 #define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
259 #define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
260 #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
261 #define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
262 #define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
263 #define TARGET_USE_BT (x86_use_bt & TUNEMASK)
264 #define TARGET_USE_INCDEC (x86_use_incdec & TUNEMASK)
265 #define TARGET_PAD_RETURNS (x86_pad_returns & TUNEMASK)
267 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
269 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
270 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
271 && (ix86_fpmath & FPMATH_387))
273 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
274 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
275 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
276 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
278 #define TARGET_CMPXCHG (x86_cmpxchg & (1 << ix86_arch))
279 #define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch))
280 #define TARGET_CMPXCHG16B (x86_cmpxchg16b)
281 #define TARGET_XADD (x86_xadd & (1 << ix86_arch))
282 #define TARGET_BSWAP (x86_bswap & (1 << ix86_arch))
284 #ifndef TARGET_64BIT_DEFAULT
285 #define TARGET_64BIT_DEFAULT 0
287 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
288 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
291 /* Once GDB has been enhanced to deal with functions without frame
292 pointers, we can change this to allow for elimination of
293 the frame pointer in leaf functions. */
294 #define TARGET_DEFAULT 0
296 /* This is not really a target flag, but is done this way so that
297 it's analogous to similar code for Mach-O on PowerPC. darwin.h
298 redefines this to 1. */
299 #define TARGET_MACHO 0
301 /* Subtargets may reset this to 1 in order to enable 96-bit long double
302 with the rounding mode forced to 53 bits. */
303 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
305 /* Sometimes certain combinations of command options do not make
306 sense on a particular target machine. You can define a macro
307 `OVERRIDE_OPTIONS' to take account of this. This macro, if
308 defined, is executed once just after all the command options have
311 Don't use this macro to turn on various extra optimizations for
312 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
314 #define OVERRIDE_OPTIONS override_options ()
316 /* Define this to change the optimizations performed by default. */
317 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
318 optimization_options ((LEVEL), (SIZE))
320 /* -march=native handling only makes sense with compiler running on
321 an x86 or x86_64 chip. If changing this condition, also change
322 the condition in driver-i386.c. */
323 #if defined(__i386__) || defined(__x86_64__)
324 /* In driver-i386.c. */
325 extern const char *host_detect_local_cpu (int argc, const char **argv);
326 #define EXTRA_SPEC_FUNCTIONS \
327 { "local_cpu_detect", host_detect_local_cpu },
328 #define HAVE_LOCAL_CPU_DETECT
331 /* Support for configure-time defaults of some command line options.
332 The order here is important so that -march doesn't squash the
333 tune or cpu values. */
334 #define OPTION_DEFAULT_SPECS \
335 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
336 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
337 {"arch", "%{!march=*:-march=%(VALUE)}"}
339 /* Specs for the compiler proper */
342 #define CC1_CPU_SPEC_1 "\
345 %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
347 %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
348 %{mpentium:-mtune=pentium \
349 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
350 %{mpentiumpro:-mtune=pentiumpro \
351 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
353 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
355 %{mintel-syntax:-masm=intel \
356 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
357 %{mno-intel-syntax:-masm=att \
358 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
360 #ifndef HAVE_LOCAL_CPU_DETECT
361 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
363 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
364 "%{march=native:%<march=native %:local_cpu_detect(arch) \
365 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
366 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
370 /* Target CPU builtins. */
371 #define TARGET_CPU_CPP_BUILTINS() \
374 size_t arch_len = strlen (ix86_arch_string); \
375 size_t tune_len = strlen (ix86_tune_string); \
376 int last_arch_char = ix86_arch_string[arch_len - 1]; \
377 int last_tune_char = ix86_tune_string[tune_len - 1]; \
381 builtin_assert ("cpu=x86_64"); \
382 builtin_assert ("machine=x86_64"); \
383 builtin_define ("__amd64"); \
384 builtin_define ("__amd64__"); \
385 builtin_define ("__x86_64"); \
386 builtin_define ("__x86_64__"); \
390 builtin_assert ("cpu=i386"); \
391 builtin_assert ("machine=i386"); \
392 builtin_define_std ("i386"); \
395 /* Built-ins based on -mtune= (or -march= if no \
398 builtin_define ("__tune_i386__"); \
399 else if (TARGET_486) \
400 builtin_define ("__tune_i486__"); \
401 else if (TARGET_PENTIUM) \
403 builtin_define ("__tune_i586__"); \
404 builtin_define ("__tune_pentium__"); \
405 if (last_tune_char == 'x') \
406 builtin_define ("__tune_pentium_mmx__"); \
408 else if (TARGET_PENTIUMPRO) \
410 builtin_define ("__tune_i686__"); \
411 builtin_define ("__tune_pentiumpro__"); \
412 switch (last_tune_char) \
415 builtin_define ("__tune_pentium3__"); \
418 builtin_define ("__tune_pentium2__"); \
422 else if (TARGET_GEODE) \
424 builtin_define ("__tune_geode__"); \
426 else if (TARGET_K6) \
428 builtin_define ("__tune_k6__"); \
429 if (last_tune_char == '2') \
430 builtin_define ("__tune_k6_2__"); \
431 else if (last_tune_char == '3') \
432 builtin_define ("__tune_k6_3__"); \
434 else if (TARGET_ATHLON) \
436 builtin_define ("__tune_athlon__"); \
437 /* Only plain "athlon" lacks SSE. */ \
438 if (last_tune_char != 'n') \
439 builtin_define ("__tune_athlon_sse__"); \
441 else if (TARGET_K8) \
442 builtin_define ("__tune_k8__"); \
443 else if (TARGET_AMDFAM10) \
444 builtin_define ("__tune_amdfam10__"); \
445 else if (TARGET_PENTIUM4) \
446 builtin_define ("__tune_pentium4__"); \
447 else if (TARGET_NOCONA) \
448 builtin_define ("__tune_nocona__"); \
449 else if (TARGET_CORE2) \
450 builtin_define ("__tune_core2__"); \
453 builtin_define ("__MMX__"); \
455 builtin_define ("__3dNOW__"); \
456 if (TARGET_3DNOW_A) \
457 builtin_define ("__3dNOW_A__"); \
459 builtin_define ("__SSE__"); \
461 builtin_define ("__SSE2__"); \
463 builtin_define ("__SSE3__"); \
465 builtin_define ("__SSSE3__"); \
467 builtin_define ("__SSE4A__"); \
468 if (TARGET_SSE_MATH && TARGET_SSE) \
469 builtin_define ("__SSE_MATH__"); \
470 if (TARGET_SSE_MATH && TARGET_SSE2) \
471 builtin_define ("__SSE2_MATH__"); \
473 /* Built-ins based on -march=. */ \
474 if (ix86_arch == PROCESSOR_I486) \
476 builtin_define ("__i486"); \
477 builtin_define ("__i486__"); \
479 else if (ix86_arch == PROCESSOR_PENTIUM) \
481 builtin_define ("__i586"); \
482 builtin_define ("__i586__"); \
483 builtin_define ("__pentium"); \
484 builtin_define ("__pentium__"); \
485 if (last_arch_char == 'x') \
486 builtin_define ("__pentium_mmx__"); \
488 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
490 builtin_define ("__i686"); \
491 builtin_define ("__i686__"); \
492 builtin_define ("__pentiumpro"); \
493 builtin_define ("__pentiumpro__"); \
495 else if (ix86_arch == PROCESSOR_GEODE) \
497 builtin_define ("__geode"); \
498 builtin_define ("__geode__"); \
500 else if (ix86_arch == PROCESSOR_K6) \
503 builtin_define ("__k6"); \
504 builtin_define ("__k6__"); \
505 if (last_arch_char == '2') \
506 builtin_define ("__k6_2__"); \
507 else if (last_arch_char == '3') \
508 builtin_define ("__k6_3__"); \
510 else if (ix86_arch == PROCESSOR_ATHLON) \
512 builtin_define ("__athlon"); \
513 builtin_define ("__athlon__"); \
514 /* Only plain "athlon" lacks SSE. */ \
515 if (last_arch_char != 'n') \
516 builtin_define ("__athlon_sse__"); \
518 else if (ix86_arch == PROCESSOR_K8) \
520 builtin_define ("__k8"); \
521 builtin_define ("__k8__"); \
523 else if (ix86_arch == PROCESSOR_AMDFAM10) \
525 builtin_define ("__amdfam10"); \
526 builtin_define ("__amdfam10__"); \
528 else if (ix86_arch == PROCESSOR_PENTIUM4) \
530 builtin_define ("__pentium4"); \
531 builtin_define ("__pentium4__"); \
533 else if (ix86_arch == PROCESSOR_NOCONA) \
535 builtin_define ("__nocona"); \
536 builtin_define ("__nocona__"); \
538 else if (ix86_arch == PROCESSOR_CORE2) \
540 builtin_define ("__core2"); \
541 builtin_define ("__core2__"); \
546 #define TARGET_CPU_DEFAULT_i386 0
547 #define TARGET_CPU_DEFAULT_i486 1
548 #define TARGET_CPU_DEFAULT_pentium 2
549 #define TARGET_CPU_DEFAULT_pentium_mmx 3
550 #define TARGET_CPU_DEFAULT_pentiumpro 4
551 #define TARGET_CPU_DEFAULT_pentium2 5
552 #define TARGET_CPU_DEFAULT_pentium3 6
553 #define TARGET_CPU_DEFAULT_pentium4 7
554 #define TARGET_CPU_DEFAULT_geode 8
555 #define TARGET_CPU_DEFAULT_k6 9
556 #define TARGET_CPU_DEFAULT_k6_2 10
557 #define TARGET_CPU_DEFAULT_k6_3 11
558 #define TARGET_CPU_DEFAULT_athlon 12
559 #define TARGET_CPU_DEFAULT_athlon_sse 13
560 #define TARGET_CPU_DEFAULT_k8 14
561 #define TARGET_CPU_DEFAULT_pentium_m 15
562 #define TARGET_CPU_DEFAULT_prescott 16
563 #define TARGET_CPU_DEFAULT_nocona 17
564 #define TARGET_CPU_DEFAULT_core2 18
565 #define TARGET_CPU_DEFAULT_generic 19
566 #define TARGET_CPU_DEFAULT_amdfam10 20
568 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
569 "pentiumpro", "pentium2", "pentium3", \
570 "pentium4", "geode", "k6", "k6-2", "k6-3", \
571 "athlon", "athlon-4", "k8", \
572 "pentium-m", "prescott", "nocona", \
573 "core2", "generic", "amdfam10"}
576 #define CC1_SPEC "%(cc1_cpu) "
579 /* This macro defines names of additional specifications to put in the
580 specs that can be used in various specifications like CC1_SPEC. Its
581 definition is an initializer with a subgrouping for each command option.
583 Each subgrouping contains a string constant, that defines the
584 specification name, and a string constant that used by the GCC driver
587 Do not define this macro if it does not need to do anything. */
589 #ifndef SUBTARGET_EXTRA_SPECS
590 #define SUBTARGET_EXTRA_SPECS
593 #define EXTRA_SPECS \
594 { "cc1_cpu", CC1_CPU_SPEC }, \
595 SUBTARGET_EXTRA_SPECS
597 /* target machine storage layout */
599 #define LONG_DOUBLE_TYPE_SIZE 80
601 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
602 FPU, assume that the fpcw is set to extended precision; when using
603 only SSE, rounding is correct; when using both SSE and the FPU,
604 the rounding precision is indeterminate, since either may be chosen
605 apparently at random. */
606 #define TARGET_FLT_EVAL_METHOD \
607 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
609 #define SHORT_TYPE_SIZE 16
610 #define INT_TYPE_SIZE 32
611 #define FLOAT_TYPE_SIZE 32
612 #define LONG_TYPE_SIZE BITS_PER_WORD
613 #define DOUBLE_TYPE_SIZE 64
614 #define LONG_LONG_TYPE_SIZE 64
616 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
617 #define MAX_BITS_PER_WORD 64
619 #define MAX_BITS_PER_WORD 32
622 /* Define this if most significant byte of a word is the lowest numbered. */
623 /* That is true on the 80386. */
625 #define BITS_BIG_ENDIAN 0
627 /* Define this if most significant byte of a word is the lowest numbered. */
628 /* That is not true on the 80386. */
629 #define BYTES_BIG_ENDIAN 0
631 /* Define this if most significant word of a multiword number is the lowest
633 /* Not true for 80386 */
634 #define WORDS_BIG_ENDIAN 0
636 /* Width of a word, in units (bytes). */
637 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
639 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
641 #define MIN_UNITS_PER_WORD 4
644 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
645 #define PARM_BOUNDARY BITS_PER_WORD
647 /* Boundary (in *bits*) on which stack pointer should be aligned. */
648 #define STACK_BOUNDARY BITS_PER_WORD
650 /* Boundary (in *bits*) on which the stack pointer prefers to be
651 aligned; the compiler cannot rely on having this alignment. */
652 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
654 /* As of July 2001, many runtimes do not align the stack properly when
655 entering main. This causes expand_main_function to forcibly align
656 the stack, which results in aligned frames for functions called from
657 main, though it does nothing for the alignment of main itself. */
658 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
659 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
661 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
662 mandatory for the 64-bit ABI, and may or may not be true for other
663 operating systems. */
664 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
666 /* Minimum allocation boundary for the code of a function. */
667 #define FUNCTION_BOUNDARY 8
669 /* C++ stores the virtual bit in the lowest bit of function pointers. */
670 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
672 /* Alignment of field after `int : 0' in a structure. */
674 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
676 /* Minimum size in bits of the largest boundary to which any
677 and all fundamental data types supported by the hardware
678 might need to be aligned. No data type wants to be aligned
681 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
682 and Pentium Pro XFmode values at 128 bit boundaries. */
684 #define BIGGEST_ALIGNMENT 128
686 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
687 #define ALIGN_MODE_128(MODE) \
688 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
690 /* The published ABIs say that doubles should be aligned on word
691 boundaries, so lower the alignment for structure fields unless
692 -malign-double is set. */
694 /* ??? Blah -- this macro is used directly by libobjc. Since it
695 supports no vector modes, cut out the complexity and fall back
696 on BIGGEST_FIELD_ALIGNMENT. */
697 #ifdef IN_TARGET_LIBS
699 #define BIGGEST_FIELD_ALIGNMENT 128
701 #define BIGGEST_FIELD_ALIGNMENT 32
704 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
705 x86_field_alignment (FIELD, COMPUTED)
708 /* If defined, a C expression to compute the alignment given to a
709 constant that is being placed in memory. EXP is the constant
710 and ALIGN is the alignment that the object would ordinarily have.
711 The value of this macro is used instead of that alignment to align
714 If this macro is not defined, then ALIGN is used.
716 The typical use of this macro is to increase alignment for string
717 constants to be word aligned so that `strcpy' calls that copy
718 constants can be done inline. */
720 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
722 /* If defined, a C expression to compute the alignment for a static
723 variable. TYPE is the data type, and ALIGN is the alignment that
724 the object would ordinarily have. The value of this macro is used
725 instead of that alignment to align the object.
727 If this macro is not defined, then ALIGN is used.
729 One use of this macro is to increase alignment of medium-size
730 data to make it all fit in fewer cache lines. Another is to
731 cause character arrays to be word-aligned so that `strcpy' calls
732 that copy constants to character arrays can be done inline. */
734 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
736 /* If defined, a C expression to compute the alignment for a local
737 variable. TYPE is the data type, and ALIGN is the alignment that
738 the object would ordinarily have. The value of this macro is used
739 instead of that alignment to align the object.
741 If this macro is not defined, then ALIGN is used.
743 One use of this macro is to increase alignment of medium-size
744 data to make it all fit in fewer cache lines. */
746 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
748 /* If defined, a C expression that gives the alignment boundary, in
749 bits, of an argument with the specified mode and type. If it is
750 not defined, `PARM_BOUNDARY' is used for all arguments. */
752 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
753 ix86_function_arg_boundary ((MODE), (TYPE))
755 /* Set this nonzero if move instructions will actually fail to work
756 when given unaligned data. */
757 #define STRICT_ALIGNMENT 0
759 /* If bit field type is int, don't let it cross an int,
760 and give entire struct the alignment of an int. */
761 /* Required on the 386 since it doesn't have bit-field insns. */
762 #define PCC_BITFIELD_TYPE_MATTERS 1
764 /* Standard register usage. */
766 /* This processor has special stack-like registers. See reg-stack.c
770 #define IS_STACK_MODE(MODE) \
771 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
772 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
775 /* Number of actual hardware registers.
776 The hardware registers are assigned numbers for the compiler
777 from 0 to just below FIRST_PSEUDO_REGISTER.
778 All registers that the compiler knows about must be given numbers,
779 even those that are not normally considered general registers.
781 In the 80386 we give the 8 general purpose registers the numbers 0-7.
782 We number the floating point registers 8-15.
783 Note that registers 0-7 can be accessed as a short or int,
784 while only 0-3 may be used with byte `mov' instructions.
786 Reg 16 does not correspond to any hardware register, but instead
787 appears in the RTL as an argument pointer prior to reload, and is
788 eliminated during reloading in favor of either the stack or frame
791 #define FIRST_PSEUDO_REGISTER 53
793 /* Number of hardware registers that go into the DWARF-2 unwind info.
794 If not defined, equals FIRST_PSEUDO_REGISTER. */
796 #define DWARF_FRAME_REGISTERS 17
798 /* 1 for registers that have pervasive standard uses
799 and are not available for the register allocator.
800 On the 80386, the stack pointer is such, as is the arg pointer.
802 The value is zero if the register is not fixed on either 32 or
803 64 bit targets, one if the register if fixed on both 32 and 64
804 bit targets, two if it is only fixed on 32bit targets and three
805 if its only fixed on 64bit targets.
806 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
808 #define FIXED_REGISTERS \
809 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
810 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
811 /*arg,flags,fpsr,fpcr,frame*/ \
813 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
814 0, 0, 0, 0, 0, 0, 0, 0, \
815 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
816 0, 0, 0, 0, 0, 0, 0, 0, \
817 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
818 2, 2, 2, 2, 2, 2, 2, 2, \
819 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
820 2, 2, 2, 2, 2, 2, 2, 2}
823 /* 1 for registers not available across function calls.
824 These must include the FIXED_REGISTERS and also any
825 registers that can be used without being saved.
826 The latter must include the registers where values are returned
827 and the register where structure-value addresses are passed.
828 Aside from that, you can include as many other registers as you like.
830 The value is zero if the register is not call used on either 32 or
831 64 bit targets, one if the register if call used on both 32 and 64
832 bit targets, two if it is only call used on 32bit targets and three
833 if its only call used on 64bit targets.
834 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
836 #define CALL_USED_REGISTERS \
837 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
838 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
839 /*arg,flags,fpsr,fpcr,frame*/ \
841 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
842 1, 1, 1, 1, 1, 1, 1, 1, \
843 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
844 1, 1, 1, 1, 1, 1, 1, 1, \
845 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
846 1, 1, 1, 1, 2, 2, 2, 2, \
847 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
848 1, 1, 1, 1, 1, 1, 1, 1} \
850 /* Order in which to allocate registers. Each register must be
851 listed once, even those in FIXED_REGISTERS. List frame pointer
852 late and fixed registers last. Note that, in general, we prefer
853 registers listed in CALL_USED_REGISTERS, keeping the others
854 available for storage of persistent values.
856 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
857 so this is just empty initializer for array. */
859 #define REG_ALLOC_ORDER \
860 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
861 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
862 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
865 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
866 to be rearranged based on a particular function. When using sse math,
867 we want to allocate SSE before x87 registers and vice versa. */
869 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
872 /* Macro to conditionally modify fixed_regs/call_used_regs. */
873 #define CONDITIONAL_REGISTER_USAGE \
877 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
879 if (fixed_regs[i] > 1) \
880 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
881 if (call_used_regs[i] > 1) \
882 call_used_regs[i] = (call_used_regs[i] \
883 == (TARGET_64BIT ? 3 : 2)); \
885 j = PIC_OFFSET_TABLE_REGNUM; \
886 if (j != INVALID_REGNUM) \
889 call_used_regs[j] = 1; \
894 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
895 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
896 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
901 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
902 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
903 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
905 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
909 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
910 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
911 if (TEST_HARD_REG_BIT (x, i)) \
912 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
914 if (! TARGET_64BIT) \
917 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
919 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
924 /* Return number of consecutive hard regs needed starting at reg REGNO
925 to hold something of mode MODE.
926 This is ordinarily the length in words of a value of mode MODE
927 but can be less for certain modes in special long registers.
929 Actually there are no two word move instructions for consecutive
930 registers. And only registers 0-3 may have mov byte instructions
934 #define HARD_REGNO_NREGS(REGNO, MODE) \
935 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
936 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
937 : ((MODE) == XFmode \
938 ? (TARGET_64BIT ? 2 : 3) \
940 ? (TARGET_64BIT ? 4 : 6) \
941 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
943 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
944 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
945 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
947 : ((MODE) == XFmode || (MODE) == XCmode)) \
950 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
952 #define VALID_SSE2_REG_MODE(MODE) \
953 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
954 || (MODE) == V2DImode || (MODE) == DFmode)
956 #define VALID_SSE_REG_MODE(MODE) \
957 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
958 || (MODE) == SFmode || (MODE) == TFmode)
960 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
961 ((MODE) == V2SFmode || (MODE) == SFmode)
963 #define VALID_MMX_REG_MODE(MODE) \
964 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
965 || (MODE) == V2SImode || (MODE) == SImode)
967 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
968 place emms and femms instructions. */
969 #define UNITS_PER_SIMD_WORD (TARGET_SSE ? 16 : UNITS_PER_WORD)
971 #define VALID_FP_MODE_P(MODE) \
972 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
973 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
975 #define VALID_INT_MODE_P(MODE) \
976 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
977 || (MODE) == DImode \
978 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
979 || (MODE) == CDImode \
980 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
981 || (MODE) == TFmode || (MODE) == TCmode)))
983 /* Return true for modes passed in SSE registers. */
984 #define SSE_REG_MODE_P(MODE) \
985 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
986 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
987 || (MODE) == V4SFmode || (MODE) == V4SImode)
989 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
991 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
992 ix86_hard_regno_mode_ok ((REGNO), (MODE))
994 /* Value is 1 if it is a good idea to tie two pseudo registers
995 when one has mode MODE1 and one has mode MODE2.
996 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
997 for any hard reg, then this must be 0 for correct output. */
999 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1001 /* It is possible to write patterns to move flags; but until someone
1003 #define AVOID_CCMODE_COPIES
1005 /* Specify the modes required to caller save a given hard regno.
1006 We do this on i386 to prevent flags from being saved at all.
1008 Kill any attempts to combine saving of modes. */
1010 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1011 (CC_REGNO_P (REGNO) ? VOIDmode \
1012 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1013 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
1014 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1015 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1017 /* Specify the registers used for certain standard purposes.
1018 The values of these macros are register numbers. */
1020 /* on the 386 the pc register is %eip, and is not usable as a general
1021 register. The ordinary mov instructions won't work */
1022 /* #define PC_REGNUM */
1024 /* Register to use for pushing function arguments. */
1025 #define STACK_POINTER_REGNUM 7
1027 /* Base register for access to local variables of the function. */
1028 #define HARD_FRAME_POINTER_REGNUM 6
1030 /* Base register for access to local variables of the function. */
1031 #define FRAME_POINTER_REGNUM 20
1033 /* First floating point reg */
1034 #define FIRST_FLOAT_REG 8
1036 /* First & last stack-like regs */
1037 #define FIRST_STACK_REG FIRST_FLOAT_REG
1038 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1040 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1041 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1043 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1044 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1046 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1047 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1049 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1050 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1052 /* Value should be nonzero if functions must have frame pointers.
1053 Zero means the frame pointer need not be set up (and parms
1054 may be accessed via the stack pointer) in functions that seem suitable.
1055 This is computed in `reload', in reload1.c. */
1056 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1058 /* Override this in other tm.h files to cope with various OS lossage
1059 requiring a frame pointer. */
1060 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1061 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1064 /* Make sure we can access arbitrary call frames. */
1065 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1067 /* Base register for access to arguments of the function. */
1068 #define ARG_POINTER_REGNUM 16
1070 /* Register in which static-chain is passed to a function.
1071 We do use ECX as static chain register for 32 bit ABI. On the
1072 64bit ABI, ECX is an argument register, so we use R10 instead. */
1073 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1075 /* Register to hold the addressing base for position independent
1076 code access to data items. We don't use PIC pointer for 64bit
1077 mode. Define the regnum to dummy value to prevent gcc from
1078 pessimizing code dealing with EBX.
1080 To avoid clobbering a call-saved register unnecessarily, we renumber
1081 the pic register when possible. The change is visible after the
1082 prologue has been emitted. */
1084 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1086 #define PIC_OFFSET_TABLE_REGNUM \
1087 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1088 || !flag_pic ? INVALID_REGNUM \
1089 : reload_completed ? REGNO (pic_offset_table_rtx) \
1090 : REAL_PIC_OFFSET_TABLE_REGNUM)
1092 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1094 /* A C expression which can inhibit the returning of certain function
1095 values in registers, based on the type of value. A nonzero value
1096 says to return the function value in memory, just as large
1097 structures are always returned. Here TYPE will be a C expression
1098 of type `tree', representing the data type of the value.
1100 Note that values of mode `BLKmode' must be explicitly handled by
1101 this macro. Also, the option `-fpcc-struct-return' takes effect
1102 regardless of this macro. On most systems, it is possible to
1103 leave the macro undefined; this causes a default definition to be
1104 used, whose value is the constant 1 for `BLKmode' values, and 0
1107 Do not use this macro to indicate that structures and unions
1108 should always be returned in memory. You should instead use
1109 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1111 #define RETURN_IN_MEMORY(TYPE) \
1112 ix86_return_in_memory (TYPE)
1114 /* This is overridden by <cygwin.h>. */
1115 #define MS_AGGREGATE_RETURN 0
1117 /* This is overridden by <netware.h>. */
1118 #define KEEP_AGGREGATE_RETURN_POINTER 0
1120 /* Define the classes of registers for register constraints in the
1121 machine description. Also define ranges of constants.
1123 One of the classes must always be named ALL_REGS and include all hard regs.
1124 If there is more than one class, another class must be named NO_REGS
1125 and contain no registers.
1127 The name GENERAL_REGS must be the name of a class (or an alias for
1128 another name such as ALL_REGS). This is the class of registers
1129 that is allowed by "g" or "r" in a register constraint.
1130 Also, registers outside this class are allocated only when
1131 instructions express preferences for them.
1133 The classes must be numbered in nondecreasing order; that is,
1134 a larger-numbered class must never be contained completely
1135 in a smaller-numbered class.
1137 For any two classes, it is very desirable that there be another
1138 class that represents their union.
1140 It might seem that class BREG is unnecessary, since no useful 386
1141 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1142 and the "b" register constraint is useful in asms for syscalls.
1144 The flags, fpsr and fpcr registers are in no class. */
1149 AREG, DREG, CREG, BREG, SIREG, DIREG,
1150 AD_REGS, /* %eax/%edx for DImode */
1151 Q_REGS, /* %eax %ebx %ecx %edx */
1152 NON_Q_REGS, /* %esi %edi %ebp %esp */
1153 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1154 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1155 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1156 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1166 ALL_REGS, LIM_REG_CLASSES
1169 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1171 #define INTEGER_CLASS_P(CLASS) \
1172 reg_class_subset_p ((CLASS), GENERAL_REGS)
1173 #define FLOAT_CLASS_P(CLASS) \
1174 reg_class_subset_p ((CLASS), FLOAT_REGS)
1175 #define SSE_CLASS_P(CLASS) \
1176 ((CLASS) == SSE_REGS)
1177 #define MMX_CLASS_P(CLASS) \
1178 ((CLASS) == MMX_REGS)
1179 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1180 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1181 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1182 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1183 #define MAYBE_SSE_CLASS_P(CLASS) \
1184 reg_classes_intersect_p (SSE_REGS, (CLASS))
1185 #define MAYBE_MMX_CLASS_P(CLASS) \
1186 reg_classes_intersect_p (MMX_REGS, (CLASS))
1188 #define Q_CLASS_P(CLASS) \
1189 reg_class_subset_p ((CLASS), Q_REGS)
1191 /* Give names of register classes as strings for dump file. */
1193 #define REG_CLASS_NAMES \
1195 "AREG", "DREG", "CREG", "BREG", \
1198 "Q_REGS", "NON_Q_REGS", \
1202 "FP_TOP_REG", "FP_SECOND_REG", \
1206 "FP_TOP_SSE_REGS", \
1207 "FP_SECOND_SSE_REGS", \
1211 "FLOAT_INT_SSE_REGS", \
1214 /* Define which registers fit in which classes.
1215 This is an initializer for a vector of HARD_REG_SET
1216 of length N_REG_CLASSES. */
1218 #define REG_CLASS_CONTENTS \
1220 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1221 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1222 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1223 { 0x03, 0x0 }, /* AD_REGS */ \
1224 { 0x0f, 0x0 }, /* Q_REGS */ \
1225 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1226 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1227 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1228 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1229 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1230 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1231 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1232 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1233 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1234 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1235 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1236 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1237 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1238 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1239 { 0xffffffff,0x1fffff } \
1242 /* The same information, inverted:
1243 Return the class number of the smallest class containing
1244 reg number REGNO. This could be a conditional expression
1245 or could index an array. */
1247 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1249 /* When defined, the compiler allows registers explicitly used in the
1250 rtl to be used as spill registers but prevents the compiler from
1251 extending the lifetime of these registers. */
1253 #define SMALL_REGISTER_CLASSES 1
1255 #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
1257 #define GENERAL_REGNO_P(N) \
1258 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1260 #define GENERAL_REG_P(X) \
1261 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1263 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1265 #define REX_INT_REGNO_P(N) \
1266 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1267 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1269 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1270 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1271 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1272 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1274 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1275 #define SSE_REGNO_P(N) \
1276 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1277 || REX_SSE_REGNO_P (N))
1279 #define REX_SSE_REGNO_P(N) \
1280 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1282 #define SSE_REGNO(N) \
1283 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1285 #define SSE_FLOAT_MODE_P(MODE) \
1286 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1288 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1289 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1291 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1292 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1294 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1296 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1297 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1299 /* The class value for index registers, and the one for base regs. */
1301 #define INDEX_REG_CLASS INDEX_REGS
1302 #define BASE_REG_CLASS GENERAL_REGS
1304 /* Place additional restrictions on the register class to use when it
1305 is necessary to be able to hold a value of mode MODE in a reload
1306 register for which class CLASS would ordinarily be used. */
1308 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1309 ((MODE) == QImode && !TARGET_64BIT \
1310 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1311 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1314 /* Given an rtx X being reloaded into a reg required to be
1315 in class CLASS, return the class of reg to actually use.
1316 In general this is just CLASS; but on some machines
1317 in some cases it is preferable to use a more restrictive class.
1318 On the 80386 series, we prevent floating constants from being
1319 reloaded into floating registers (since no move-insn can do that)
1320 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1322 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1323 QImode must go into class Q_REGS.
1324 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1325 movdf to do mem-to-mem moves through integer regs. */
1327 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1328 ix86_preferred_reload_class ((X), (CLASS))
1330 /* Discourage putting floating-point values in SSE registers unless
1331 SSE math is being used, and likewise for the 387 registers. */
1333 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1334 ix86_preferred_output_reload_class ((X), (CLASS))
1336 /* If we are copying between general and FP registers, we need a memory
1337 location. The same is true for SSE and MMX registers. */
1338 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1339 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1341 /* QImode spills from non-QI registers need a scratch. This does not
1342 happen often -- the only example so far requires an uninitialized
1345 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1346 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1347 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1350 /* Return the maximum number of consecutive registers
1351 needed to represent mode MODE in a register of class CLASS. */
1352 /* On the 80386, this is the size of MODE in words,
1353 except in the FP regs, where a single reg is always enough. */
1354 #define CLASS_MAX_NREGS(CLASS, MODE) \
1355 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1356 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1357 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1358 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1360 /* A C expression whose value is nonzero if pseudos that have been
1361 assigned to registers of class CLASS would likely be spilled
1362 because registers of CLASS are needed for spill registers.
1364 The default value of this macro returns 1 if CLASS has exactly one
1365 register and zero otherwise. On most machines, this default
1366 should be used. Only define this macro to some other expression
1367 if pseudo allocated by `local-alloc.c' end up in memory because
1368 their hard registers were needed for spill registers. If this
1369 macro returns nonzero for those classes, those pseudos will only
1370 be allocated by `global.c', which knows how to reallocate the
1371 pseudo to another register. If there would not be another
1372 register available for reallocation, you should not change the
1373 definition of this macro since the only effect of such a
1374 definition would be to slow down register allocation. */
1376 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1377 (((CLASS) == AREG) \
1378 || ((CLASS) == DREG) \
1379 || ((CLASS) == CREG) \
1380 || ((CLASS) == BREG) \
1381 || ((CLASS) == AD_REGS) \
1382 || ((CLASS) == SIREG) \
1383 || ((CLASS) == DIREG) \
1384 || ((CLASS) == FP_TOP_REG) \
1385 || ((CLASS) == FP_SECOND_REG))
1387 /* Return a class of registers that cannot change FROM mode to TO mode. */
1389 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1390 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1392 /* Stack layout; function entry, exit and calling. */
1394 /* Define this if pushing a word on the stack
1395 makes the stack pointer a smaller address. */
1396 #define STACK_GROWS_DOWNWARD
1398 /* Define this to nonzero if the nominal address of the stack frame
1399 is at the high-address end of the local variables;
1400 that is, each additional local variable allocated
1401 goes at a more negative offset in the frame. */
1402 #define FRAME_GROWS_DOWNWARD 1
1404 /* Offset within stack frame to start allocating local variables at.
1405 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1406 first local allocated. Otherwise, it is the offset to the BEGINNING
1407 of the first local allocated. */
1408 #define STARTING_FRAME_OFFSET 0
1410 /* If we generate an insn to push BYTES bytes,
1411 this says how many the stack pointer really advances by.
1412 On 386, we have pushw instruction that decrements by exactly 2 no
1413 matter what the position was, there is no pushb.
1414 But as CIE data alignment factor on this arch is -4, we need to make
1415 sure all stack pointer adjustments are in multiple of 4.
1417 For 64bit ABI we round up to 8 bytes.
1420 #define PUSH_ROUNDING(BYTES) \
1422 ? (((BYTES) + 7) & (-8)) \
1423 : (((BYTES) + 3) & (-4)))
1425 /* If defined, the maximum amount of space required for outgoing arguments will
1426 be computed and placed into the variable
1427 `current_function_outgoing_args_size'. No space will be pushed onto the
1428 stack for each call; instead, the function prologue should increase the stack
1429 frame size by this amount. */
1431 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1433 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1434 instructions to pass outgoing arguments. */
1436 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1438 /* We want the stack and args grow in opposite directions, even if
1440 #define PUSH_ARGS_REVERSED 1
1442 /* Offset of first parameter from the argument pointer register value. */
1443 #define FIRST_PARM_OFFSET(FNDECL) 0
1445 /* Define this macro if functions should assume that stack space has been
1446 allocated for arguments even when their values are passed in registers.
1448 The value of this macro is the size, in bytes, of the area reserved for
1449 arguments passed in registers for the function represented by FNDECL.
1451 This space can be allocated by the caller, or be a part of the
1452 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1454 #define REG_PARM_STACK_SPACE(FNDECL) 0
1456 /* Value is the number of bytes of arguments automatically
1457 popped when returning from a subroutine call.
1458 FUNDECL is the declaration node of the function (as a tree),
1459 FUNTYPE is the data type of the function (as a tree),
1460 or for a library call it is an identifier node for the subroutine name.
1461 SIZE is the number of bytes of arguments passed on the stack.
1463 On the 80386, the RTD insn may be used to pop them if the number
1464 of args is fixed, but if the number is variable then the caller
1465 must pop them all. RTD can't be used for library calls now
1466 because the library is compiled with the Unix compiler.
1467 Use of RTD is a selectable option, since it is incompatible with
1468 standard Unix calling sequences. If the option is not selected,
1469 the caller must always pop the args.
1471 The attribute stdcall is equivalent to RTD on a per module basis. */
1473 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1474 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1476 #define FUNCTION_VALUE_REGNO_P(N) \
1477 ix86_function_value_regno_p (N)
1479 /* Define how to find the value returned by a library function
1480 assuming the value has mode MODE. */
1482 #define LIBCALL_VALUE(MODE) \
1483 ix86_libcall_value (MODE)
1485 /* Define the size of the result block used for communication between
1486 untyped_call and untyped_return. The block contains a DImode value
1487 followed by the block used by fnsave and frstor. */
1489 #define APPLY_RESULT_SIZE (8+108)
1491 /* 1 if N is a possible register number for function argument passing. */
1492 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1494 /* Define a data type for recording info about an argument list
1495 during the scan of that argument list. This data type should
1496 hold all necessary information about the function itself
1497 and about the args processed so far, enough to enable macros
1498 such as FUNCTION_ARG to determine where the next arg should go. */
1500 typedef struct ix86_args {
1501 int words; /* # words passed so far */
1502 int nregs; /* # registers available for passing */
1503 int regno; /* next available register number */
1504 int fastcall; /* fastcall calling convention is used */
1505 int sse_words; /* # sse words passed so far */
1506 int sse_nregs; /* # sse registers available for passing */
1507 int warn_sse; /* True when we want to warn about SSE ABI. */
1508 int warn_mmx; /* True when we want to warn about MMX ABI. */
1509 int sse_regno; /* next available sse register number */
1510 int mmx_words; /* # mmx words passed so far */
1511 int mmx_nregs; /* # mmx registers available for passing */
1512 int mmx_regno; /* next available mmx register number */
1513 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1514 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1515 be passed in SSE registers. Otherwise 0. */
1518 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1519 for a call to a function whose data type is FNTYPE.
1520 For a library call, FNTYPE is 0. */
1522 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1523 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1525 /* Update the data in CUM to advance over an argument
1526 of mode MODE and data type TYPE.
1527 (TYPE is null for libcalls where that information may not be available.) */
1529 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1530 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1532 /* Define where to put the arguments to a function.
1533 Value is zero to push the argument on the stack,
1534 or a hard register in which to store the argument.
1536 MODE is the argument's machine mode.
1537 TYPE is the data type of the argument (as a tree).
1538 This is null for libcalls where that information may
1540 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1541 the preceding args and about the function being called.
1542 NAMED is nonzero if this argument is a named parameter
1543 (otherwise it is an extra parameter matching an ellipsis). */
1545 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1546 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1548 /* Implement `va_start' for varargs and stdarg. */
1549 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1550 ix86_va_start (VALIST, NEXTARG)
1552 #define TARGET_ASM_FILE_END ix86_file_end
1553 #define NEED_INDICATE_EXEC_STACK 0
1555 /* Output assembler code to FILE to increment profiler label # LABELNO
1556 for profiling a function entry. */
1558 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1560 #define MCOUNT_NAME "_mcount"
1562 #define PROFILE_COUNT_REGISTER "edx"
1564 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1565 the stack pointer does not matter. The value is tested only in
1566 functions that have frame pointers.
1567 No definition is equivalent to always zero. */
1568 /* Note on the 386 it might be more efficient not to define this since
1569 we have to restore it ourselves from the frame pointer, in order to
1572 #define EXIT_IGNORE_STACK 1
1574 /* Output assembler code for a block containing the constant parts
1575 of a trampoline, leaving space for the variable parts. */
1577 /* On the 386, the trampoline contains two instructions:
1580 The trampoline is generated entirely at runtime. The operand of JMP
1581 is the address of FUNCTION relative to the instruction following the
1582 JMP (which is 5 bytes long). */
1584 /* Length in units of the trampoline for entering a nested function. */
1586 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1588 /* Emit RTL insns to initialize the variable parts of a trampoline.
1589 FNADDR is an RTX for the address of the function's pure code.
1590 CXT is an RTX for the static chain value for the function. */
1592 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1593 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1595 /* Definitions for register eliminations.
1597 This is an array of structures. Each structure initializes one pair
1598 of eliminable registers. The "from" register number is given first,
1599 followed by "to". Eliminations of the same "from" register are listed
1600 in order of preference.
1602 There are two registers that can always be eliminated on the i386.
1603 The frame pointer and the arg pointer can be replaced by either the
1604 hard frame pointer or to the stack pointer, depending upon the
1605 circumstances. The hard frame pointer is not used before reload and
1606 so it is not eligible for elimination. */
1608 #define ELIMINABLE_REGS \
1609 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1610 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1611 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1612 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1614 /* Given FROM and TO register numbers, say whether this elimination is
1615 allowed. Frame pointer elimination is automatically handled.
1617 All other eliminations are valid. */
1619 #define CAN_ELIMINATE(FROM, TO) \
1620 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1622 /* Define the offset between two registers, one to be eliminated, and the other
1623 its replacement, at the start of a routine. */
1625 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1626 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1628 /* Addressing modes, and classification of registers for them. */
1630 /* Macros to check register numbers against specific register classes. */
1632 /* These assume that REGNO is a hard or pseudo reg number.
1633 They give nonzero only if REGNO is a hard reg of the suitable class
1634 or a pseudo reg currently allocated to a suitable hard reg.
1635 Since they use reg_renumber, they are safe only once reg_renumber
1636 has been allocated, which happens in local-alloc.c. */
1638 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1639 ((REGNO) < STACK_POINTER_REGNUM \
1640 || REX_INT_REGNO_P (REGNO) \
1641 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1642 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1644 #define REGNO_OK_FOR_BASE_P(REGNO) \
1645 (GENERAL_REGNO_P (REGNO) \
1646 || (REGNO) == ARG_POINTER_REGNUM \
1647 || (REGNO) == FRAME_POINTER_REGNUM \
1648 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1650 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1651 and check its validity for a certain class.
1652 We have two alternate definitions for each of them.
1653 The usual definition accepts all pseudo regs; the other rejects
1654 them unless they have been allocated suitable hard regs.
1655 The symbol REG_OK_STRICT causes the latter definition to be used.
1657 Most source files want to accept pseudo regs in the hope that
1658 they will get allocated to the class that the insn wants them to be in.
1659 Source files for reload pass need to be strict.
1660 After reload, it makes no difference, since pseudo regs have
1661 been eliminated by then. */
1664 /* Non strict versions, pseudos are ok. */
1665 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1666 (REGNO (X) < STACK_POINTER_REGNUM \
1667 || REX_INT_REGNO_P (REGNO (X)) \
1668 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1670 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1671 (GENERAL_REGNO_P (REGNO (X)) \
1672 || REGNO (X) == ARG_POINTER_REGNUM \
1673 || REGNO (X) == FRAME_POINTER_REGNUM \
1674 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1676 /* Strict versions, hard registers only */
1677 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1678 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1680 #ifndef REG_OK_STRICT
1681 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1682 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1685 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1686 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1689 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1690 that is a valid memory address for an instruction.
1691 The MODE argument is the machine mode for the MEM expression
1692 that wants to use this address.
1694 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1695 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1697 See legitimize_pic_address in i386.c for details as to what
1698 constitutes a legitimate address when -fpic is used. */
1700 #define MAX_REGS_PER_ADDRESS 2
1702 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1704 /* Nonzero if the constant value X is a legitimate general operand.
1705 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1707 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1709 #ifdef REG_OK_STRICT
1710 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1712 if (legitimate_address_p ((MODE), (X), 1)) \
1717 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1719 if (legitimate_address_p ((MODE), (X), 0)) \
1725 /* If defined, a C expression to determine the base term of address X.
1726 This macro is used in only one place: `find_base_term' in alias.c.
1728 It is always safe for this macro to not be defined. It exists so
1729 that alias analysis can understand machine-dependent addresses.
1731 The typical use of this macro is to handle addresses containing
1732 a label_ref or symbol_ref within an UNSPEC. */
1734 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1736 /* Try machine-dependent ways of modifying an illegitimate address
1737 to be legitimate. If we find one, return the new, valid address.
1738 This macro is used in only one place: `memory_address' in explow.c.
1740 OLDX is the address as it was before break_out_memory_refs was called.
1741 In some cases it is useful to look at this to decide what needs to be done.
1743 MODE and WIN are passed so that this macro can use
1744 GO_IF_LEGITIMATE_ADDRESS.
1746 It is always safe for this macro to do nothing. It exists to recognize
1747 opportunities to optimize the output.
1749 For the 80386, we handle X+REG by loading X into a register R and
1750 using R+REG. R will go in a general reg and indexing will be used.
1751 However, if REG is a broken-out memory address or multiplication,
1752 nothing needs to be done because REG can certainly go in a general reg.
1754 When -fpic is used, special handling is needed for symbolic references.
1755 See comments by legitimize_pic_address in i386.c for details. */
1757 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1759 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1760 if (memory_address_p ((MODE), (X))) \
1764 /* Nonzero if the constant value X is a legitimate general operand
1765 when generating PIC code. It is given that flag_pic is on and
1766 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1768 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1770 #define SYMBOLIC_CONST(X) \
1771 (GET_CODE (X) == SYMBOL_REF \
1772 || GET_CODE (X) == LABEL_REF \
1773 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1775 /* Go to LABEL if ADDR (a legitimate address expression)
1776 has an effect that depends on the machine mode it is used for.
1777 On the 80386, only postdecrement and postincrement address depend thus
1778 (the amount of decrement or increment being the length of the operand).
1779 These are now caught in recog.c. */
1780 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
1782 /* Max number of args passed in registers. If this is more than 3, we will
1783 have problems with ebx (register #4), since it is a caller save register and
1784 is also used as the pic register in ELF. So for now, don't allow more than
1785 3 registers to be passed in registers. */
1787 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
1789 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
1791 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1794 /* Specify the machine mode that this machine uses
1795 for the index in the tablejump instruction. */
1796 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
1798 /* Define this as 1 if `char' should by default be signed; else as 0. */
1799 #define DEFAULT_SIGNED_CHAR 1
1801 /* Max number of bytes we can move from memory to memory
1802 in one reasonably fast instruction. */
1805 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
1806 move efficiently, as opposed to MOVE_MAX which is the maximum
1807 number of bytes we can move with a single instruction. */
1808 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
1810 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1811 move-instruction pairs, we will do a movmem or libcall instead.
1812 Increasing the value will always make code faster, but eventually
1813 incurs high cost in increased code size.
1815 If you don't define this, a reasonable default is used. */
1817 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
1819 /* If a clear memory operation would take CLEAR_RATIO or more simple
1820 move-instruction sequences, we will do a clrmem or libcall instead. */
1822 #define CLEAR_RATIO (optimize_size ? 2 \
1823 : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
1825 /* Define if shifts truncate the shift count
1826 which implies one can omit a sign-extension or zero-extension
1827 of a shift count. */
1828 /* On i386, shifts do truncate the count. But bit opcodes don't. */
1830 /* #define SHIFT_COUNT_TRUNCATED */
1832 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1833 is done just by pretending it is already truncated. */
1834 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1836 /* A macro to update M and UNSIGNEDP when an object whose type is
1837 TYPE and which has the specified mode and signedness is to be
1838 stored in a register. This macro is only called when TYPE is a
1841 On i386 it is sometimes useful to promote HImode and QImode
1842 quantities to SImode. The choice depends on target type. */
1844 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1846 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
1847 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
1851 /* Specify the machine mode that pointers have.
1852 After generation of rtl, the compiler makes no further distinction
1853 between pointers and any other objects of this machine mode. */
1854 #define Pmode (TARGET_64BIT ? DImode : SImode)
1856 /* A function address in a call instruction
1857 is a byte address (for indexing purposes)
1858 so give the MEM rtx a byte's mode. */
1859 #define FUNCTION_MODE QImode
1861 /* A C expression for the cost of moving data from a register in class FROM to
1862 one in class TO. The classes are expressed using the enumeration values
1863 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1864 interpreted relative to that.
1866 It is not required that the cost always equal 2 when FROM is the same as TO;
1867 on some machines it is expensive to move between registers if they are not
1868 general registers. */
1870 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1871 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
1873 /* A C expression for the cost of moving data of mode M between a
1874 register and memory. A value of 2 is the default; this cost is
1875 relative to those in `REGISTER_MOVE_COST'.
1877 If moving between registers and memory is more expensive than
1878 between two registers, you should define this macro to express the
1881 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1882 ix86_memory_move_cost ((MODE), (CLASS), (IN))
1884 /* A C expression for the cost of a branch instruction. A value of 1
1885 is the default; other values are interpreted relative to that. */
1887 #define BRANCH_COST ix86_branch_cost
1889 /* Define this macro as a C expression which is nonzero if accessing
1890 less than a word of memory (i.e. a `char' or a `short') is no
1891 faster than accessing a word of memory, i.e., if such access
1892 require more than one instruction or if there is no difference in
1893 cost between byte and (aligned) word loads.
1895 When this macro is not defined, the compiler will access a field by
1896 finding the smallest containing object; when it is defined, a
1897 fullword load will be used if alignment permits. Unless bytes
1898 accesses are faster than word accesses, using word accesses is
1899 preferable since it may eliminate subsequent memory access if
1900 subsequent accesses occur to other fields in the same word of the
1901 structure, but to different bytes. */
1903 #define SLOW_BYTE_ACCESS 0
1905 /* Nonzero if access to memory by shorts is slow and undesirable. */
1906 #define SLOW_SHORT_ACCESS 0
1908 /* Define this macro to be the value 1 if unaligned accesses have a
1909 cost many times greater than aligned accesses, for example if they
1910 are emulated in a trap handler.
1912 When this macro is nonzero, the compiler will act as if
1913 `STRICT_ALIGNMENT' were nonzero when generating code for block
1914 moves. This can cause significantly more instructions to be
1915 produced. Therefore, do not set this macro nonzero if unaligned
1916 accesses only add a cycle or two to the time for a memory access.
1918 If the value of this macro is always zero, it need not be defined. */
1920 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
1922 /* Define this macro if it is as good or better to call a constant
1923 function address than to call an address kept in a register.
1925 Desirable on the 386 because a CALL with a constant address is
1926 faster than one with a register address. */
1928 #define NO_FUNCTION_CSE
1930 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1931 return the mode to be used for the comparison.
1933 For floating-point equality comparisons, CCFPEQmode should be used.
1934 VOIDmode should be used in all other cases.
1936 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
1937 possible, to allow for more combinations. */
1939 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
1941 /* Return nonzero if MODE implies a floating point inequality can be
1944 #define REVERSIBLE_CC_MODE(MODE) 1
1946 /* A C expression whose value is reversed condition code of the CODE for
1947 comparison done in CC_MODE mode. */
1948 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
1951 /* Control the assembler format that we output, to the extent
1952 this does not vary between assemblers. */
1954 /* How to refer to registers in assembler output.
1955 This sequence is indexed by compiler's hard-register-number (see above). */
1957 /* In order to refer to the first 8 regs as 32 bit regs, prefix an "e".
1958 For non floating point regs, the following are the HImode names.
1960 For float regs, the stack top is sometimes referred to as "%st(0)"
1961 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
1963 #define HI_REGISTER_NAMES \
1964 {"ax","dx","cx","bx","si","di","bp","sp", \
1965 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
1966 "argp", "flags", "fpsr", "fpcr", "frame", \
1967 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
1968 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
1969 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1970 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
1972 #define REGISTER_NAMES HI_REGISTER_NAMES
1974 /* Table of additional register names to use in user input. */
1976 #define ADDITIONAL_REGISTER_NAMES \
1977 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
1978 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
1979 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
1980 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
1981 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
1982 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
1984 /* Note we are omitting these since currently I don't know how
1985 to get gcc to use these, since they want the same but different
1986 number as al, and ax.
1989 #define QI_REGISTER_NAMES \
1990 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
1992 /* These parallel the array above, and can be used to access bits 8:15
1993 of regs 0 through 3. */
1995 #define QI_HIGH_REGISTER_NAMES \
1996 {"ah", "dh", "ch", "bh", }
1998 /* How to renumber registers for dbx and gdb. */
2000 #define DBX_REGISTER_NUMBER(N) \
2001 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2003 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2004 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2005 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2007 /* Before the prologue, RA is at 0(%esp). */
2008 #define INCOMING_RETURN_ADDR_RTX \
2009 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2011 /* After the prologue, RA is at -4(AP) in the current frame. */
2012 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2014 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2015 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2017 /* PC is dbx register 8; let's use that column for RA. */
2018 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2020 /* Before the prologue, the top of the frame is at 4(%esp). */
2021 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2023 /* Describe how we implement __builtin_eh_return. */
2024 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2025 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2028 /* Select a format to encode pointers in exception handling data. CODE
2029 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2030 true if the symbol may be affected by dynamic relocations.
2032 ??? All x86 object file formats are capable of representing this.
2033 After all, the relocation needed is the same as for the call insn.
2034 Whether or not a particular assembler allows us to enter such, I
2035 guess we'll have to see. */
2036 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2037 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2039 /* This is how to output an insn to push a register on the stack.
2040 It need not be very fast code. */
2042 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2045 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2046 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2048 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2051 /* This is how to output an insn to pop a register from the stack.
2052 It need not be very fast code. */
2054 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2057 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2058 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2060 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2063 /* This is how to output an element of a case-vector that is absolute. */
2065 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2066 ix86_output_addr_vec_elt ((FILE), (VALUE))
2068 /* This is how to output an element of a case-vector that is relative. */
2070 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2071 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2073 /* Under some conditions we need jump tables in the text section,
2074 because the assembler cannot handle label differences between
2075 sections. This is the case for x86_64 on Mach-O for example. */
2077 #define JUMP_TABLES_IN_TEXT_SECTION \
2078 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2079 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2081 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2082 and switch back. For x86 we do this only to save a few bytes that
2083 would otherwise be unused in the text section. */
2084 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2085 asm (SECTION_OP "\n\t" \
2086 "call " USER_LABEL_PREFIX #FUNC "\n" \
2087 TEXT_SECTION_ASM_OP);
2089 /* Print operand X (an rtx) in assembler syntax to file FILE.
2090 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2091 Effect of various CODE letters is described in i386.c near
2092 print_operand function. */
2094 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2095 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2097 #define PRINT_OPERAND(FILE, X, CODE) \
2098 print_operand ((FILE), (X), (CODE))
2100 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2101 print_operand_address ((FILE), (ADDR))
2103 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2105 if (! output_addr_const_extra (FILE, (X))) \
2109 /* Which processor to schedule for. The cpu attribute defines a list that
2110 mirrors this list, so changes to i386.md must be made at the same time. */
2114 PROCESSOR_I386, /* 80386 */
2115 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2117 PROCESSOR_PENTIUMPRO,
2125 PROCESSOR_GENERIC32,
2126 PROCESSOR_GENERIC64,
2131 extern enum processor_type ix86_tune;
2132 extern enum processor_type ix86_arch;
2140 extern enum fpmath_unit ix86_fpmath;
2149 extern enum tls_dialect ix86_tls_dialect;
2152 CM_32, /* The traditional 32-bit ABI. */
2153 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2154 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2155 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2156 CM_LARGE, /* No assumptions. */
2157 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2158 CM_MEDIUM_PIC /* Assumes code+got/plt fits in a 31 bit region. */
2161 extern enum cmodel ix86_cmodel;
2163 /* Size of the RED_ZONE area. */
2164 #define RED_ZONE_SIZE 128
2165 /* Reserved area of the red zone for temporaries. */
2166 #define RED_ZONE_RESERVE 8
2173 extern enum asm_dialect ix86_asm_dialect;
2174 extern unsigned int ix86_preferred_stack_boundary;
2175 extern int ix86_branch_cost, ix86_section_threshold;
2177 /* Smallest class containing REGNO. */
2178 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2180 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2181 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2182 extern rtx ix86_compare_emitted;
2184 /* To properly truncate FP values into integers, we need to set i387 control
2185 word. We can't emit proper mode switching code before reload, as spills
2186 generated by reload may truncate values incorrectly, but we still can avoid
2187 redundant computation of new control word by the mode switching pass.
2188 The fldcw instructions are still emitted redundantly, but this is probably
2189 not going to be noticeable problem, as most CPUs do have fast path for
2192 The machinery is to emit simple truncation instructions and split them
2193 before reload to instructions having USEs of two memory locations that
2194 are filled by this code to old and new control word.
2196 Post-reload pass may be later used to eliminate the redundant fildcw if
2208 enum ix86_stack_slot
2216 MAX_386_STACK_LOCALS
2219 /* Define this macro if the port needs extra instructions inserted
2220 for mode switching in an optimizing compilation. */
2222 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2223 ix86_optimize_mode_switching[(ENTITY)]
2225 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2226 initializer for an array of integers. Each initializer element N
2227 refers to an entity that needs mode switching, and specifies the
2228 number of different modes that might need to be set for this
2229 entity. The position of the initializer in the initializer -
2230 starting counting at zero - determines the integer that is used to
2231 refer to the mode-switched entity in question. */
2233 #define NUM_MODES_FOR_MODE_SWITCHING \
2234 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2236 /* ENTITY is an integer specifying a mode-switched entity. If
2237 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2238 return an integer value not larger than the corresponding element
2239 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2240 must be switched into prior to the execution of INSN. */
2242 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2244 /* This macro specifies the order in which modes for ENTITY are
2245 processed. 0 is the highest priority. */
2247 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2249 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2250 is the set of hard registers live at the point where the insn(s)
2251 are to be inserted. */
2253 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2254 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2255 ? emit_i387_cw_initialization (MODE), 0 \
2259 /* Avoid renaming of stack registers, as doing so in combination with
2260 scheduling just increases amount of live registers at time and in
2261 the turn amount of fxch instructions needed.
2263 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2265 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2266 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2269 #define DLL_IMPORT_EXPORT_PREFIX '#'
2271 #define FASTCALL_PREFIX '@'
2273 struct machine_function GTY(())
2275 struct stack_local_entry *stack_locals;
2276 const char *some_ld_name;
2277 rtx force_align_arg_pointer;
2278 int save_varrargs_registers;
2279 int accesses_prev_frame;
2280 int optimize_mode_switching[MAX_386_ENTITIES];
2281 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
2282 determine the style used. */
2283 int use_fast_prologue_epilogue;
2284 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2286 int use_fast_prologue_epilogue_nregs;
2287 /* If true, the current function needs the default PIC register, not
2288 an alternate register (on x86) and must not use the red zone (on
2289 x86_64), even if it's a leaf function. We don't want the
2290 function to be regarded as non-leaf because TLS calls need not
2291 affect register allocation. This flag is set when a TLS call
2292 instruction is expanded within a function, and never reset, even
2293 if all such instructions are optimized away. Use the
2294 ix86_current_function_calls_tls_descriptor macro for a better
2296 int tls_descriptor_call_expanded_p;
2299 #define ix86_stack_locals (cfun->machine->stack_locals)
2300 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2301 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2302 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2303 (cfun->machine->tls_descriptor_call_expanded_p)
2304 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2305 calls are optimized away, we try to detect cases in which it was
2306 optimized away. Since such instructions (use (reg REG_SP)), we can
2307 verify whether there's any such instruction live by testing that
2309 #define ix86_current_function_calls_tls_descriptor \
2310 (ix86_tls_descriptor_calls_expanded_in_cfun && regs_ever_live[SP_REG])
2312 /* Control behavior of x86_file_start. */
2313 #define X86_FILE_START_VERSION_DIRECTIVE false
2314 #define X86_FILE_START_FLTUSED false
2316 /* Flag to mark data that is in the large address area. */
2317 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2318 #define SYMBOL_REF_FAR_ADDR_P(X) \
2319 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
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