1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) X
48 #define HALF_PIC_FINISH(STREAM)
51 /* Define the specific costs for a given cpu */
53 struct processor_costs {
54 const int add; /* cost of an add instruction */
55 const int lea; /* cost of a lea instruction */
56 const int shift_var; /* variable shift costs */
57 const int shift_const; /* constant shift costs */
58 const int mult_init; /* cost of starting a multiply */
59 const int mult_bit; /* cost of multiply per each bit set */
60 const int divide; /* cost of a divide/mod */
61 int movsx; /* The cost of movsx operation. */
62 int movzx; /* The cost of movzx operation. */
63 const int large_insn; /* insns larger than this cost more */
64 const int move_ratio; /* The threshold of number of scalar
65 memory-to-memory move insns. */
66 const int movzbl_load; /* cost of loading using movzbl */
67 const int int_load[3]; /* cost of loading integer registers
68 in QImode, HImode and SImode relative
69 to reg-reg move (2). */
70 const int int_store[3]; /* cost of storing integer register
71 in QImode, HImode and SImode */
72 const int fp_move; /* cost of reg,reg fld/fst */
73 const int fp_load[3]; /* cost of loading FP register
74 in SFmode, DFmode and XFmode */
75 const int fp_store[3]; /* cost of storing FP register
76 in SFmode, DFmode and XFmode */
77 const int mmx_move; /* cost of moving MMX register. */
78 const int mmx_load[2]; /* cost of loading MMX register
79 in SImode and DImode */
80 const int mmx_store[2]; /* cost of storing MMX register
81 in SImode and DImode */
82 const int sse_move; /* cost of moving SSE register. */
83 const int sse_load[3]; /* cost of loading SSE register
84 in SImode, DImode and TImode*/
85 const int sse_store[3]; /* cost of storing SSE register
86 in SImode, DImode and TImode*/
87 const int mmxsse_to_integer; /* cost of moving mmxsse register to
88 integer and vice versa. */
89 const int prefetch_block; /* bytes moved to cache for prefetch. */
90 const int simultaneous_prefetches; /* number of parallel prefetch
94 extern const struct processor_costs *ix86_cost;
96 /* Run-time compilation parameters selecting different hardware subsets. */
98 extern int target_flags;
100 /* Macros used in the machine description to test the flags. */
102 /* configure can arrange to make this 2, to force a 486. */
104 #ifndef TARGET_CPU_DEFAULT
105 #define TARGET_CPU_DEFAULT 0
108 /* Masks for the -m switches */
109 #define MASK_80387 0x00000001 /* Hardware floating point */
110 #define MASK_RTD 0x00000002 /* Use ret that pops args */
111 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
112 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
113 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
114 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
115 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
116 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
117 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
118 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
119 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
120 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
121 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
122 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
123 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
124 #define MASK_MMX_SET 0x00008000
125 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
126 #define MASK_SSE_SET 0x00020000
127 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
128 #define MASK_SSE2_SET 0x00080000
129 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
130 #define MASK_3DNOW_SET 0x00200000
131 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
132 #define MASK_3DNOW_A_SET 0x00800000
133 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
134 #define MASK_64BIT 0x02000000 /* Produce 64bit code */
135 /* ... overlap with subtarget options starts by 0x04000000. */
136 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
138 /* Use the floating point instructions */
139 #define TARGET_80387 (target_flags & MASK_80387)
141 /* Compile using ret insn that pops args.
142 This will not work unless you use prototypes at least
143 for all functions that can take varying numbers of args. */
144 #define TARGET_RTD (target_flags & MASK_RTD)
146 /* Align doubles to a two word boundary. This breaks compatibility with
147 the published ABI's for structures containing doubles, but produces
148 faster code on the pentium. */
149 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
151 /* Use push instructions to save outgoing args. */
152 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
154 /* Accumulate stack adjustments to prologue/epilogue. */
155 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
156 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
158 /* Put uninitialized locals into bss, not data.
159 Meaningful only on svr3. */
160 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
162 /* Use IEEE floating point comparisons. These handle correctly the cases
163 where the result of a comparison is unordered. Normally SIGFPE is
164 generated in such cases, in which case this isn't needed. */
165 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
167 /* Functions that return a floating point value may return that value
168 in the 387 FPU or in 386 integer registers. If set, this flag causes
169 the 387 to be used, which is compatible with most calling conventions. */
170 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
172 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
173 This mode wastes cache, but avoid misaligned data accesses and simplifies
174 address calculations. */
175 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
177 /* Disable generation of FP sin, cos and sqrt operations for 387.
178 This is because FreeBSD lacks these in the math-emulator-code */
179 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
181 /* Don't create frame pointers for leaf functions */
182 #define TARGET_OMIT_LEAF_FRAME_POINTER \
183 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
185 /* Debug GO_IF_LEGITIMATE_ADDRESS */
186 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
188 /* Debug FUNCTION_ARG macros */
189 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
191 /* 64bit Sledgehammer mode */
192 #ifdef TARGET_BI_ARCH
193 #define TARGET_64BIT (target_flags & MASK_64BIT)
195 #ifdef TARGET_64BIT_DEFAULT
196 #define TARGET_64BIT 1
198 #define TARGET_64BIT 0
202 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
203 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
204 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
205 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
206 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
207 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
208 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
210 #define CPUMASK (1 << ix86_cpu)
211 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
212 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
213 extern const int x86_branch_hints, x86_unroll_strlen;
214 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
215 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
216 extern const int x86_use_cltd, x86_read_modify_write;
217 extern const int x86_read_modify, x86_split_long_moves;
218 extern const int x86_promote_QImode, x86_single_stringop;
219 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
220 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
221 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
222 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
223 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
224 extern const int x86_epilogue_using_move, x86_decompose_lea;
225 extern int x86_prefetch_sse;
227 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
228 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
229 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
230 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
231 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
232 /* For sane SSE instruction set generation we need fcomi instruction. It is
233 safe to enable all CMOVE instructions. */
234 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
235 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
236 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
237 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
238 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
239 #define TARGET_MOVX (x86_movx & CPUMASK)
240 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
241 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
242 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
243 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
244 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
245 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
246 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
247 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
248 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
249 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
250 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
251 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
252 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
253 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
254 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
255 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
256 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
257 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
258 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
259 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
260 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
261 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
262 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
263 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
264 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
266 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
268 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
269 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
271 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
273 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
274 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
275 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
276 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
277 && (ix86_fpmath & FPMATH_387))
278 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
279 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
280 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
282 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
284 #define TARGET_SWITCHES \
285 { { "80387", MASK_80387, N_("Use hardware fp") }, \
286 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
287 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
288 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
289 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
290 { "386", 0, N_("") /*Deprecated.*/}, \
291 { "486", 0, N_("") /*Deprecated.*/}, \
292 { "pentium", 0, N_("") /*Deprecated.*/}, \
293 { "pentiumpro", 0, N_("") /*Deprecated.*/}, \
294 { "intel-syntax", 0, N_("") /*Deprecated.*/}, \
295 { "no-intel-syntax", 0, N_("") /*Deprecated.*/}, \
297 N_("Alternate calling convention") }, \
298 { "no-rtd", -MASK_RTD, \
299 N_("Use normal calling convention") }, \
300 { "align-double", MASK_ALIGN_DOUBLE, \
301 N_("Align some doubles on dword boundary") }, \
302 { "no-align-double", -MASK_ALIGN_DOUBLE, \
303 N_("Align doubles on word boundary") }, \
304 { "svr3-shlib", MASK_SVR3_SHLIB, \
305 N_("Uninitialized locals in .bss") }, \
306 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
307 N_("Uninitialized locals in .data") }, \
308 { "ieee-fp", MASK_IEEE_FP, \
309 N_("Use IEEE math for fp comparisons") }, \
310 { "no-ieee-fp", -MASK_IEEE_FP, \
311 N_("Do not use IEEE math for fp comparisons") }, \
312 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
313 N_("Return values of functions in FPU registers") }, \
314 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
315 N_("Do not return values of functions in FPU registers")}, \
316 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
317 N_("Do not generate sin, cos, sqrt for FPU") }, \
318 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
319 N_("Generate sin, cos, sqrt for FPU")}, \
320 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
321 N_("Omit the frame pointer in leaf functions") }, \
322 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
323 { "stack-arg-probe", MASK_STACK_PROBE, \
324 N_("Enable stack probing") }, \
325 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
326 { "windows", 0, 0 /* undocumented */ }, \
327 { "dll", 0, 0 /* undocumented */ }, \
328 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
329 N_("Align destination of the string operations") }, \
330 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
331 N_("Do not align destination of the string operations") }, \
332 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
333 N_("Inline all known string operations") }, \
334 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
335 N_("Do not inline all known string operations") }, \
336 { "push-args", -MASK_NO_PUSH_ARGS, \
337 N_("Use push instructions to save outgoing arguments") }, \
338 { "no-push-args", MASK_NO_PUSH_ARGS, \
339 N_("Do not use push instructions to save outgoing arguments") }, \
340 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
341 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
342 N_("Use push instructions to save outgoing arguments") }, \
343 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
344 N_("Do not use push instructions to save outgoing arguments") }, \
345 { "mmx", MASK_MMX | MASK_MMX_SET, \
346 N_("Support MMX built-in functions") }, \
347 { "no-mmx", -MASK_MMX, \
348 N_("Do not support MMX built-in functions") }, \
349 { "no-mmx", MASK_MMX_SET, N_("") }, \
350 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
351 N_("Support 3DNow! built-in functions") }, \
352 { "no-3dnow", -MASK_3DNOW, N_("") }, \
353 { "no-3dnow", MASK_3DNOW_SET, \
354 N_("Do not support 3DNow! built-in functions") }, \
355 { "sse", MASK_SSE | MASK_SSE_SET, \
356 N_("Support MMX and SSE built-in functions and code generation") }, \
357 { "no-sse", -MASK_SSE, N_("") }, \
358 { "no-sse", MASK_SSE_SET, \
359 N_("Do not support MMX and SSE built-in functions and code generation") },\
360 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
361 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
362 { "no-sse2", -MASK_SSE2, N_("") }, \
363 { "no-sse2", MASK_SSE2_SET, \
364 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
365 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
366 N_("sizeof(long double) is 16") }, \
367 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
368 N_("sizeof(long double) is 12") }, \
369 { "64", MASK_64BIT, \
370 N_("Generate 64bit x86-64 code") }, \
371 { "32", -MASK_64BIT, \
372 N_("Generate 32bit i386 code") }, \
373 { "red-zone", -MASK_NO_RED_ZONE, \
374 N_("Use red-zone in the x86-64 code") }, \
375 { "no-red-zone", MASK_NO_RED_ZONE, \
376 N_("Do not use red-zone in the x86-64 code") }, \
378 { "", TARGET_DEFAULT, 0 }}
380 #ifdef TARGET_64BIT_DEFAULT
381 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
383 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
386 /* Which processor to schedule for. The cpu attribute defines a list that
387 mirrors this list, so changes to i386.md must be made at the same time. */
391 PROCESSOR_I386, /* 80386 */
392 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
394 PROCESSOR_PENTIUMPRO,
406 extern enum processor_type ix86_cpu;
407 extern enum fpmath_unit ix86_fpmath;
409 extern int ix86_arch;
411 /* This macro is similar to `TARGET_SWITCHES' but defines names of
412 command options that have values. Its definition is an
413 initializer with a subgrouping for each command option.
415 Each subgrouping contains a string constant, that defines the
416 fixed part of the option name, and the address of a variable. The
417 variable, type `char *', is set to the variable part of the given
418 option if the fixed part matches. The actual option name is made
419 by appending `-m' to the specified name. */
420 #define TARGET_OPTIONS \
421 { { "cpu=", &ix86_cpu_string, \
422 N_("Schedule code for given CPU")}, \
423 { "fpmath=", &ix86_fpmath_string, \
424 N_("Generate floating point mathematics using given instruction set")},\
425 { "arch=", &ix86_arch_string, \
426 N_("Generate code for given CPU")}, \
427 { "regparm=", &ix86_regparm_string, \
428 N_("Number of registers used to pass integer arguments") }, \
429 { "align-loops=", &ix86_align_loops_string, \
430 N_("Loop code aligned to this power of 2") }, \
431 { "align-jumps=", &ix86_align_jumps_string, \
432 N_("Jump targets are aligned to this power of 2") }, \
433 { "align-functions=", &ix86_align_funcs_string, \
434 N_("Function starts are aligned to this power of 2") }, \
435 { "preferred-stack-boundary=", \
436 &ix86_preferred_stack_boundary_string, \
437 N_("Attempt to keep stack aligned to this power of 2") }, \
438 { "branch-cost=", &ix86_branch_cost_string, \
439 N_("Branches are this expensive (1-5, arbitrary units)") }, \
440 { "cmodel=", &ix86_cmodel_string, \
441 N_("Use given x86-64 code model") }, \
442 { "debug-arg", &ix86_debug_arg_string, \
443 N_("" /* Undocumented. */) }, \
444 { "debug-addr", &ix86_debug_addr_string, \
445 N_("" /* Undocumented. */) }, \
446 { "asm=", &ix86_asm_string, \
447 N_("Use given assembler dialect") }, \
451 /* Sometimes certain combinations of command options do not make
452 sense on a particular target machine. You can define a macro
453 `OVERRIDE_OPTIONS' to take account of this. This macro, if
454 defined, is executed once just after all the command options have
457 Don't use this macro to turn on various extra optimizations for
458 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
460 #define OVERRIDE_OPTIONS override_options ()
462 /* These are meant to be redefined in the host dependent files */
463 #define SUBTARGET_SWITCHES
464 #define SUBTARGET_OPTIONS
466 /* Define this to change the optimizations performed by default. */
467 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
469 /* Specs for the compiler proper */
472 #define CC1_CPU_SPEC "\
475 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
477 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
478 %{mpentium:-mcpu=pentium \
479 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
480 %{mpentiumpro:-mcpu=pentiumpro \
481 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
482 %{mintel-syntax:-masm=intel \
483 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
484 %{mno-intel-syntax:-masm=att \
485 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
488 #define TARGET_CPU_DEFAULT_i386 0
489 #define TARGET_CPU_DEFAULT_i486 1
490 #define TARGET_CPU_DEFAULT_pentium 2
491 #define TARGET_CPU_DEFAULT_pentium_mmx 3
492 #define TARGET_CPU_DEFAULT_pentiumpro 4
493 #define TARGET_CPU_DEFAULT_pentium2 5
494 #define TARGET_CPU_DEFAULT_pentium3 6
495 #define TARGET_CPU_DEFAULT_pentium4 7
496 #define TARGET_CPU_DEFAULT_k6 8
497 #define TARGET_CPU_DEFAULT_k6_2 9
498 #define TARGET_CPU_DEFAULT_k6_3 10
499 #define TARGET_CPU_DEFAULT_athlon 11
500 #define TARGET_CPU_DEFAULT_athlon_sse 12
502 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
503 "pentiumpro", "pentium2", "pentium3", \
504 "pentium4", "k6", "k6-2", "k6-3",\
505 "athlon", "athlon-4"}
506 #ifndef CPP_CPU_DEFAULT_SPEC
507 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
508 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
510 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
511 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
513 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
514 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
516 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
517 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
519 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
520 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
523 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
524 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
525 -D__tune_pentium2__ -D__tune_pentium3__"
527 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
528 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
530 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
531 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
533 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
534 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
536 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
537 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
539 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
540 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
542 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
543 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
545 #ifndef CPP_CPU_DEFAULT_SPEC
546 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
548 #endif /* CPP_CPU_DEFAULT_SPEC */
550 #ifdef TARGET_BI_ARCH
551 #define NO_BUILTIN_SIZE_TYPE
552 #define NO_BUILTIN_PTRDIFF_TYPE
555 #ifdef NO_BUILTIN_SIZE_TYPE
556 #define CPP_CPU32_SIZE_TYPE_SPEC \
557 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
558 #define CPP_CPU64_SIZE_TYPE_SPEC \
559 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int"
561 #define CPP_CPU32_SIZE_TYPE_SPEC ""
562 #define CPP_CPU64_SIZE_TYPE_SPEC ""
565 #define CPP_CPU32_SPEC \
566 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
567 -D__i386__ %(cpp_cpu32sizet)"
569 #define CPP_CPU64_SPEC \
570 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)"
572 #define CPP_CPUCOMMON_SPEC "\
573 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
574 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
575 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
576 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
577 %{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
579 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
580 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
581 -D__pentiumpro -D__pentiumpro__ \
582 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
583 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
584 %{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
585 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
586 %{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
587 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
588 %{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
589 %{!mcpu*:-D__tune_athlon__ }}\
590 %{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
592 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
593 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
594 %{m386|mcpu=i386:-D__tune_i386__ }\
595 %{m486|mcpu=i486:-D__tune_i486__ }\
596 %{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
597 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
598 -D__tune_pentiumpro__ }\
599 %{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
600 %{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
602 %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
603 -D__tune_athlon_sse__ }\
604 %{mcpu=pentium4:-D__tune_pentium4__ }\
605 %{march=march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
607 %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
608 march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
609 |march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
610 %{march=k6-2|march=k6-3\
611 march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
612 |march=athlon-mp: -D__3dNOW__ }\
613 %{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
614 |march=athlon-mp: -D__3dNOW_A__ }\
615 %{march=mcpu=pentium4: -D__SSE2__ }\
616 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
619 #ifdef TARGET_BI_ARCH
620 #ifdef TARGET_64BIT_DEFAULT
621 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
623 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
626 #ifdef TARGET_64BIT_DEFAULT
627 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
629 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
635 #define CC1_SPEC "%(cc1_cpu) "
638 /* This macro defines names of additional specifications to put in the
639 specs that can be used in various specifications like CC1_SPEC. Its
640 definition is an initializer with a subgrouping for each command option.
642 Each subgrouping contains a string constant, that defines the
643 specification name, and a string constant that used by the GNU CC driver
646 Do not define this macro if it does not need to do anything. */
648 #ifndef SUBTARGET_EXTRA_SPECS
649 #define SUBTARGET_EXTRA_SPECS
652 #define EXTRA_SPECS \
653 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
654 { "cpp_cpu", CPP_CPU_SPEC }, \
655 { "cpp_cpu32", CPP_CPU32_SPEC }, \
656 { "cpp_cpu64", CPP_CPU64_SPEC }, \
657 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \
658 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \
659 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
660 { "cc1_cpu", CC1_CPU_SPEC }, \
661 SUBTARGET_EXTRA_SPECS
663 /* target machine storage layout */
665 /* Define for XFmode or TFmode extended real floating point support.
666 This will automatically cause REAL_ARITHMETIC to be defined.
668 The XFmode is specified by i386 ABI, while TFmode may be faster
669 due to alignment and simplifications in the address calculations.
671 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
672 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
674 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
676 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
678 /* Tell real.c that this is the 80-bit Intel extended float format
679 packaged in a 128-bit or 96bit entity. */
680 #define INTEL_EXTENDED_IEEE_FORMAT 1
683 #define SHORT_TYPE_SIZE 16
684 #define INT_TYPE_SIZE 32
685 #define FLOAT_TYPE_SIZE 32
686 #define LONG_TYPE_SIZE BITS_PER_WORD
687 #define MAX_WCHAR_TYPE_SIZE 32
688 #define DOUBLE_TYPE_SIZE 64
689 #define LONG_LONG_TYPE_SIZE 64
691 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
692 #define MAX_BITS_PER_WORD 64
693 #define MAX_LONG_TYPE_SIZE 64
695 #define MAX_BITS_PER_WORD 32
696 #define MAX_LONG_TYPE_SIZE 32
699 /* Define if you don't want extended real, but do want to use the
700 software floating point emulator for REAL_ARITHMETIC and
701 decimal <-> binary conversion. */
702 /* #define REAL_ARITHMETIC */
704 /* Define this if most significant byte of a word is the lowest numbered. */
705 /* That is true on the 80386. */
707 #define BITS_BIG_ENDIAN 0
709 /* Define this if most significant byte of a word is the lowest numbered. */
710 /* That is not true on the 80386. */
711 #define BYTES_BIG_ENDIAN 0
713 /* Define this if most significant word of a multiword number is the lowest
715 /* Not true for 80386 */
716 #define WORDS_BIG_ENDIAN 0
718 /* number of bits in an addressable storage unit */
719 #define BITS_PER_UNIT 8
721 /* Width in bits of a "word", which is the contents of a machine register.
722 Note that this is not necessarily the width of data type `int';
723 if using 16-bit ints on a 80386, this would still be 32.
724 But on a machine with 16-bit registers, this would be 16. */
725 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
727 /* Width of a word, in units (bytes). */
728 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
729 #define MIN_UNITS_PER_WORD 4
731 /* Width in bits of a pointer.
732 See also the macro `Pmode' defined below. */
733 #define POINTER_SIZE BITS_PER_WORD
735 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
736 #define PARM_BOUNDARY BITS_PER_WORD
738 /* Boundary (in *bits*) on which stack pointer should be aligned. */
739 #define STACK_BOUNDARY BITS_PER_WORD
741 /* Boundary (in *bits*) on which the stack pointer preferrs to be
742 aligned; the compiler cannot rely on having this alignment. */
743 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
745 /* As of July 2001, many runtimes to not align the stack properly when
746 entering main. This causes expand_main_function to forcably align
747 the stack, which results in aligned frames for functions called from
748 main, though it does nothing for the alignment of main itself. */
749 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
750 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
752 /* Allocation boundary for the code of a function. */
753 #define FUNCTION_BOUNDARY 16
755 /* Alignment of field after `int : 0' in a structure. */
757 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
759 /* Minimum size in bits of the largest boundary to which any
760 and all fundamental data types supported by the hardware
761 might need to be aligned. No data type wants to be aligned
764 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
765 and Pentium Pro XFmode values at 128 bit boundaries. */
767 #define BIGGEST_ALIGNMENT 128
769 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
770 #define ALIGN_MODE_128(MODE) \
771 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
772 || (MODE) == V4SFmode || (MODE) == V4SImode)
774 /* The published ABIs say that doubles should be aligned on word
775 boundaries, so lower the aligment for structure fields unless
776 -malign-double is set. */
777 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
778 constant. Use the smaller value in that context. */
779 #ifndef IN_TARGET_LIBS
780 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
782 #define BIGGEST_FIELD_ALIGNMENT 32
785 /* If defined, a C expression to compute the alignment given to a
786 constant that is being placed in memory. EXP is the constant
787 and ALIGN is the alignment that the object would ordinarily have.
788 The value of this macro is used instead of that alignment to align
791 If this macro is not defined, then ALIGN is used.
793 The typical use of this macro is to increase alignment for string
794 constants to be word aligned so that `strcpy' calls that copy
795 constants can be done inline. */
797 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment (EXP, ALIGN)
799 /* If defined, a C expression to compute the alignment for a static
800 variable. TYPE is the data type, and ALIGN is the alignment that
801 the object would ordinarily have. The value of this macro is used
802 instead of that alignment to align the object.
804 If this macro is not defined, then ALIGN is used.
806 One use of this macro is to increase alignment of medium-size
807 data to make it all fit in fewer cache lines. Another is to
808 cause character arrays to be word-aligned so that `strcpy' calls
809 that copy constants to character arrays can be done inline. */
811 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment (TYPE, ALIGN)
813 /* If defined, a C expression to compute the alignment for a local
814 variable. TYPE is the data type, and ALIGN is the alignment that
815 the object would ordinarily have. The value of this macro is used
816 instead of that alignment to align the object.
818 If this macro is not defined, then ALIGN is used.
820 One use of this macro is to increase alignment of medium-size
821 data to make it all fit in fewer cache lines. */
823 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment (TYPE, ALIGN)
825 /* If defined, a C expression that gives the alignment boundary, in
826 bits, of an argument with the specified mode and type. If it is
827 not defined, `PARM_BOUNDARY' is used for all arguments. */
829 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) ix86_function_arg_boundary (MODE, TYPE)
831 /* Set this non-zero if move instructions will actually fail to work
832 when given unaligned data. */
833 #define STRICT_ALIGNMENT 0
835 /* If bit field type is int, don't let it cross an int,
836 and give entire struct the alignment of an int. */
837 /* Required on the 386 since it doesn't have bitfield insns. */
838 #define PCC_BITFIELD_TYPE_MATTERS 1
840 /* Standard register usage. */
842 /* This processor has special stack-like registers. See reg-stack.c
846 #define IS_STACK_MODE(mode) (mode==DFmode || mode==SFmode \
847 || mode==XFmode || mode==TFmode)
849 /* Number of actual hardware registers.
850 The hardware registers are assigned numbers for the compiler
851 from 0 to just below FIRST_PSEUDO_REGISTER.
852 All registers that the compiler knows about must be given numbers,
853 even those that are not normally considered general registers.
855 In the 80386 we give the 8 general purpose registers the numbers 0-7.
856 We number the floating point registers 8-15.
857 Note that registers 0-7 can be accessed as a short or int,
858 while only 0-3 may be used with byte `mov' instructions.
860 Reg 16 does not correspond to any hardware register, but instead
861 appears in the RTL as an argument pointer prior to reload, and is
862 eliminated during reloading in favor of either the stack or frame
865 #define FIRST_PSEUDO_REGISTER 53
867 /* Number of hardware registers that go into the DWARF-2 unwind info.
868 If not defined, equals FIRST_PSEUDO_REGISTER. */
870 #define DWARF_FRAME_REGISTERS 17
872 /* 1 for registers that have pervasive standard uses
873 and are not available for the register allocator.
874 On the 80386, the stack pointer is such, as is the arg pointer.
876 The value is an mask - bit 1 is set for fixed registers
877 for 32bit target, while 2 is set for fixed registers for 64bit.
878 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
880 #define FIXED_REGISTERS \
881 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
882 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
883 /*arg,flags,fpsr,dir,frame*/ \
885 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
886 0, 0, 0, 0, 0, 0, 0, 0, \
887 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
888 0, 0, 0, 0, 0, 0, 0, 0, \
889 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
890 1, 1, 1, 1, 1, 1, 1, 1, \
891 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
892 1, 1, 1, 1, 1, 1, 1, 1}
895 /* 1 for registers not available across function calls.
896 These must include the FIXED_REGISTERS and also any
897 registers that can be used without being saved.
898 The latter must include the registers where values are returned
899 and the register where structure-value addresses are passed.
900 Aside from that, you can include as many other registers as you like.
902 The value is an mask - bit 1 is set for call used
903 for 32bit target, while 2 is set for call used for 64bit.
904 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
906 #define CALL_USED_REGISTERS \
907 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
908 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
909 /*arg,flags,fpsr,dir,frame*/ \
911 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
912 3, 3, 3, 3, 3, 3, 3, 3, \
913 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
914 3, 3, 3, 3, 3, 3, 3, 3, \
915 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
916 3, 3, 3, 3, 1, 1, 1, 1, \
917 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
918 3, 3, 3, 3, 3, 3, 3, 3} \
920 /* Order in which to allocate registers. Each register must be
921 listed once, even those in FIXED_REGISTERS. List frame pointer
922 late and fixed registers last. Note that, in general, we prefer
923 registers listed in CALL_USED_REGISTERS, keeping the others
924 available for storage of persistent values.
926 Three different versions of REG_ALLOC_ORDER have been tried:
928 If the order is edx, ecx, eax, ... it produces a slightly faster compiler,
929 but slower code on simple functions returning values in eax.
931 If the order is eax, ecx, edx, ... it causes reload to abort when compiling
932 perl 4.036 due to not being able to create a DImode register (to hold a 2
935 If the order is eax, edx, ecx, ... it produces better code for simple
936 functions, and a slightly slower compiler. Users complained about the code
937 generated by allocating edx first, so restore the 'natural' order of things. */
939 #define REG_ALLOC_ORDER \
942 /* bx,si,di,bp,sp,*/ \
946 /*r12,r15,r14,r13*/ \
948 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
949 21, 22, 23, 24, 25, 26, 27, 28, \
950 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
951 45, 46, 47, 48, 49, 50, 51, 52, \
952 /*st,st1,st2,st3,st4,st5,st6,st7*/ \
953 8, 9, 10, 11, 12, 13, 14, 15, \
954 /*,arg,cc,fpsr,dir,frame*/ \
956 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
957 29, 30, 31, 32, 33, 34, 35, 36 }
959 /* Macro to conditionally modify fixed_regs/call_used_regs. */
960 #define CONDITIONAL_REGISTER_USAGE \
963 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
965 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
966 call_used_regs[i] = (call_used_regs[i] \
967 & (TARGET_64BIT ? 2 : 1)) != 0; \
971 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
972 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
977 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
978 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
979 fixed_regs[i] = call_used_regs[i] = 1; \
984 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
985 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
986 fixed_regs[i] = call_used_regs[i] = 1; \
988 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
992 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
993 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
994 if (TEST_HARD_REG_BIT (x, i)) \
995 fixed_regs[i] = call_used_regs[i] = 1; \
999 /* Return number of consecutive hard regs needed starting at reg REGNO
1000 to hold something of mode MODE.
1001 This is ordinarily the length in words of a value of mode MODE
1002 but can be less for certain modes in special long registers.
1004 Actually there are no two word move instructions for consecutive
1005 registers. And only registers 0-3 may have mov byte instructions
1009 #define HARD_REGNO_NREGS(REGNO, MODE) \
1010 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1011 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1013 ? (TARGET_64BIT ? 2 : 3) \
1015 ? (TARGET_64BIT ? 4 : 6) \
1016 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1018 #define VALID_SSE_REG_MODE(MODE) \
1019 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1020 || (MODE) == SFmode \
1021 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
1023 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1024 ((MODE) == V2SFmode || (MODE) == SFmode)
1026 #define VALID_MMX_REG_MODE(MODE) \
1027 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1028 || (MODE) == V2SImode || (MODE) == SImode)
1030 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1031 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
1032 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
1033 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1035 #define VALID_FP_MODE_P(mode) \
1036 ((mode) == SFmode || (mode) == DFmode || (mode) == TFmode \
1037 || (!TARGET_64BIT && (mode) == XFmode) \
1038 || (mode) == SCmode || (mode) == DCmode || (mode) == TCmode\
1039 || (!TARGET_64BIT && (mode) == XCmode))
1041 #define VALID_INT_MODE_P(mode) \
1042 ((mode) == QImode || (mode) == HImode || (mode) == SImode \
1043 || (mode) == DImode \
1044 || (mode) == CQImode || (mode) == CHImode || (mode) == CSImode \
1045 || (mode) == CDImode \
1046 || (TARGET_64BIT && ((mode) == TImode || (mode) == CTImode)))
1048 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1050 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1051 ix86_hard_regno_mode_ok (REGNO, MODE)
1053 /* Value is 1 if it is a good idea to tie two pseudo registers
1054 when one has mode MODE1 and one has mode MODE2.
1055 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1056 for any hard reg, then this must be 0 for correct output. */
1058 #define MODES_TIEABLE_P(MODE1, MODE2) \
1059 ((MODE1) == (MODE2) \
1060 || (((MODE1) == HImode || (MODE1) == SImode \
1061 || ((MODE1) == QImode \
1062 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1063 || ((MODE1) == DImode && TARGET_64BIT)) \
1064 && ((MODE2) == HImode || (MODE2) == SImode \
1065 || ((MODE1) == QImode \
1066 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1067 || ((MODE2) == DImode && TARGET_64BIT))))
1070 /* Specify the modes required to caller save a given hard regno.
1071 We do this on i386 to prevent flags from being saved at all.
1073 Kill any attempts to combine saving of modes. */
1075 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1076 (CC_REGNO_P (REGNO) ? VOIDmode \
1077 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1078 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1079 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1080 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1082 /* Specify the registers used for certain standard purposes.
1083 The values of these macros are register numbers. */
1085 /* on the 386 the pc register is %eip, and is not usable as a general
1086 register. The ordinary mov instructions won't work */
1087 /* #define PC_REGNUM */
1089 /* Register to use for pushing function arguments. */
1090 #define STACK_POINTER_REGNUM 7
1092 /* Base register for access to local variables of the function. */
1093 #define HARD_FRAME_POINTER_REGNUM 6
1095 /* Base register for access to local variables of the function. */
1096 #define FRAME_POINTER_REGNUM 20
1098 /* First floating point reg */
1099 #define FIRST_FLOAT_REG 8
1101 /* First & last stack-like regs */
1102 #define FIRST_STACK_REG FIRST_FLOAT_REG
1103 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1105 #define FLAGS_REG 17
1107 #define DIRFLAG_REG 19
1109 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1110 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1112 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1113 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1115 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1116 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1118 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1119 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1121 /* Value should be nonzero if functions must have frame pointers.
1122 Zero means the frame pointer need not be set up (and parms
1123 may be accessed via the stack pointer) in functions that seem suitable.
1124 This is computed in `reload', in reload1.c. */
1125 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1127 /* Override this in other tm.h files to cope with various OS losage
1128 requiring a frame pointer. */
1129 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1130 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1133 /* Make sure we can access arbitrary call frames. */
1134 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1136 /* Base register for access to arguments of the function. */
1137 #define ARG_POINTER_REGNUM 16
1139 /* Register in which static-chain is passed to a function.
1140 We do use ECX as static chain register for 32 bit ABI. On the
1141 64bit ABI, ECX is an argument register, so we use R10 instead. */
1142 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1144 /* Register to hold the addressing base for position independent
1145 code access to data items.
1146 We don't use PIC pointer for 64bit mode. Define the regnum to
1147 dummy value to prevent gcc from pessimizing code dealing with EBX.
1149 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
1151 /* Register in which address to store a structure value
1152 arrives in the function. On the 386, the prologue
1153 copies this from the stack to register %eax. */
1154 #define STRUCT_VALUE_INCOMING 0
1156 /* Place in which caller passes the structure value address.
1157 0 means push the value on the stack like an argument. */
1158 #define STRUCT_VALUE 0
1160 /* A C expression which can inhibit the returning of certain function
1161 values in registers, based on the type of value. A nonzero value
1162 says to return the function value in memory, just as large
1163 structures are always returned. Here TYPE will be a C expression
1164 of type `tree', representing the data type of the value.
1166 Note that values of mode `BLKmode' must be explicitly handled by
1167 this macro. Also, the option `-fpcc-struct-return' takes effect
1168 regardless of this macro. On most systems, it is possible to
1169 leave the macro undefined; this causes a default definition to be
1170 used, whose value is the constant 1 for `BLKmode' values, and 0
1173 Do not use this macro to indicate that structures and unions
1174 should always be returned in memory. You should instead use
1175 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1177 #define RETURN_IN_MEMORY(TYPE) \
1178 ix86_return_in_memory (TYPE)
1181 /* Define the classes of registers for register constraints in the
1182 machine description. Also define ranges of constants.
1184 One of the classes must always be named ALL_REGS and include all hard regs.
1185 If there is more than one class, another class must be named NO_REGS
1186 and contain no registers.
1188 The name GENERAL_REGS must be the name of a class (or an alias for
1189 another name such as ALL_REGS). This is the class of registers
1190 that is allowed by "g" or "r" in a register constraint.
1191 Also, registers outside this class are allocated only when
1192 instructions express preferences for them.
1194 The classes must be numbered in nondecreasing order; that is,
1195 a larger-numbered class must never be contained completely
1196 in a smaller-numbered class.
1198 For any two classes, it is very desirable that there be another
1199 class that represents their union.
1201 It might seem that class BREG is unnecessary, since no useful 386
1202 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1203 and the "b" register constraint is useful in asms for syscalls.
1205 The flags and fpsr registers are in no class. */
1210 AREG, DREG, CREG, BREG, SIREG, DIREG,
1211 AD_REGS, /* %eax/%edx for DImode */
1212 Q_REGS, /* %eax %ebx %ecx %edx */
1213 NON_Q_REGS, /* %esi %edi %ebp %esp */
1214 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1215 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1216 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1217 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1227 ALL_REGS, LIM_REG_CLASSES
1230 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1232 #define INTEGER_CLASS_P(CLASS) (reg_class_subset_p (CLASS, GENERAL_REGS))
1233 #define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS))
1234 #define SSE_CLASS_P(CLASS) (reg_class_subset_p (CLASS, SSE_REGS))
1235 #define MMX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, MMX_REGS))
1236 #define MAYBE_INTEGER_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, GENERAL_REGS))
1237 #define MAYBE_FLOAT_CLASS_P(CLASS) (reg_classes_intersect_p (CLASS, FLOAT_REGS))
1238 #define MAYBE_SSE_CLASS_P(CLASS) (reg_classes_intersect_p (SSE_REGS, CLASS))
1239 #define MAYBE_MMX_CLASS_P(CLASS) (reg_classes_intersect_p (MMX_REGS, CLASS))
1241 #define Q_CLASS_P(CLASS) (reg_class_subset_p (CLASS, Q_REGS))
1243 /* Give names of register classes as strings for dump file. */
1245 #define REG_CLASS_NAMES \
1247 "AREG", "DREG", "CREG", "BREG", \
1250 "Q_REGS", "NON_Q_REGS", \
1254 "FP_TOP_REG", "FP_SECOND_REG", \
1258 "FP_TOP_SSE_REGS", \
1259 "FP_SECOND_SSE_REGS", \
1263 "FLOAT_INT_SSE_REGS", \
1266 /* Define which registers fit in which classes.
1267 This is an initializer for a vector of HARD_REG_SET
1268 of length N_REG_CLASSES. */
1270 #define REG_CLASS_CONTENTS \
1272 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1273 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1274 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1275 { 0x03, 0x0 }, /* AD_REGS */ \
1276 { 0x0f, 0x0 }, /* Q_REGS */ \
1277 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1278 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1279 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1280 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1281 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1282 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1283 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1284 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1285 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1286 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1287 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1288 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1289 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1290 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1291 { 0xffffffff,0x1fffff } \
1294 /* The same information, inverted:
1295 Return the class number of the smallest class containing
1296 reg number REGNO. This could be a conditional expression
1297 or could index an array. */
1299 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1301 /* When defined, the compiler allows registers explicitly used in the
1302 rtl to be used as spill registers but prevents the compiler from
1303 extending the lifetime of these registers. */
1305 #define SMALL_REGISTER_CLASSES 1
1307 #define QI_REG_P(X) \
1308 (REG_P (X) && REGNO (X) < 4)
1310 #define GENERAL_REGNO_P(n) \
1311 ((n) < 8 || REX_INT_REGNO_P (n))
1313 #define GENERAL_REG_P(X) \
1314 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1316 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1318 #define NON_QI_REG_P(X) \
1319 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1321 #define REX_INT_REGNO_P(n) ((n) >= FIRST_REX_INT_REG && (n) <= LAST_REX_INT_REG)
1322 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1324 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1325 #define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG)
1326 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1327 #define ANY_FP_REGNO_P(n) (FP_REGNO_P (n) || SSE_REGNO_P (n))
1329 #define SSE_REGNO_P(n) \
1330 (((n) >= FIRST_SSE_REG && (n) <= LAST_SSE_REG) \
1331 || ((n) >= FIRST_REX_SSE_REG && (n) <= LAST_REX_SSE_REG))
1333 #define SSE_REGNO(n) \
1334 ((n) < 8 ? FIRST_SSE_REG + (n) : FIRST_REX_SSE_REG + (n) - 8)
1335 #define SSE_REG_P(n) (REG_P (n) && SSE_REGNO_P (REGNO (n)))
1337 #define SSE_FLOAT_MODE_P(m) \
1338 ((TARGET_SSE_MATH && (m) == SFmode) || (TARGET_SSE2 && (m) == DFmode))
1340 #define MMX_REGNO_P(n) ((n) >= FIRST_MMX_REG && (n) <= LAST_MMX_REG)
1341 #define MMX_REG_P(xop) (REG_P (xop) && MMX_REGNO_P (REGNO (xop)))
1343 #define STACK_REG_P(xop) (REG_P (xop) && \
1344 REGNO (xop) >= FIRST_STACK_REG && \
1345 REGNO (xop) <= LAST_STACK_REG)
1347 #define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop))
1349 #define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG)
1351 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1352 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1354 /* Indicate whether hard register numbered REG_NO should be converted
1356 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1357 (REG_NO == FLAGS_REG || REG_NO == ARG_POINTER_REGNUM)
1359 /* The class value for index registers, and the one for base regs. */
1361 #define INDEX_REG_CLASS INDEX_REGS
1362 #define BASE_REG_CLASS GENERAL_REGS
1364 /* Get reg_class from a letter such as appears in the machine description. */
1366 #define REG_CLASS_FROM_LETTER(C) \
1367 ((C) == 'r' ? GENERAL_REGS : \
1368 (C) == 'R' ? LEGACY_REGS : \
1369 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1370 (C) == 'Q' ? Q_REGS : \
1371 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1374 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1377 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1380 (C) == 'a' ? AREG : \
1381 (C) == 'b' ? BREG : \
1382 (C) == 'c' ? CREG : \
1383 (C) == 'd' ? DREG : \
1384 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1385 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1386 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1387 (C) == 'A' ? AD_REGS : \
1388 (C) == 'D' ? DIREG : \
1389 (C) == 'S' ? SIREG : NO_REGS)
1391 /* The letters I, J, K, L and M in a register constraint string
1392 can be used to stand for particular ranges of immediate operands.
1393 This macro defines what the ranges are.
1394 C is the letter, and VALUE is a constant value.
1395 Return 1 if VALUE is in the range specified by C.
1397 I is for non-DImode shifts.
1398 J is for DImode shifts.
1399 K is for signed imm8 operands.
1400 L is for andsi as zero-extending move.
1401 M is for shifts that can be executed by the "lea" opcode.
1402 N is for immedaite operands for out/in instructions (0-255)
1405 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1406 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1407 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1408 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1409 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1410 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1411 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1414 /* Similar, but for floating constants, and defining letters G and H.
1415 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1416 TARGET_387 isn't set, because the stack register converter may need to
1417 load 0.0 into the function value register. */
1419 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1420 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1421 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1423 /* A C expression that defines the optional machine-dependent
1424 constraint letters that can be used to segregate specific types of
1425 operands, usually memory references, for the target machine. Any
1426 letter that is not elsewhere defined and not matched by
1427 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1430 If it is required for a particular target machine, it should
1431 return 1 if VALUE corresponds to the operand type represented by
1432 the constraint letter C. If C is not defined as an extra
1433 constraint, the value returned should be 0 regardless of VALUE. */
1435 #define EXTRA_CONSTRAINT(VALUE, C) \
1436 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1437 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1440 /* Place additional restrictions on the register class to use when it
1441 is necessary to be able to hold a value of mode MODE in a reload
1442 register for which class CLASS would ordinarily be used. */
1444 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1445 ((MODE) == QImode && !TARGET_64BIT \
1446 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
1449 /* Given an rtx X being reloaded into a reg required to be
1450 in class CLASS, return the class of reg to actually use.
1451 In general this is just CLASS; but on some machines
1452 in some cases it is preferable to use a more restrictive class.
1453 On the 80386 series, we prevent floating constants from being
1454 reloaded into floating registers (since no move-insn can do that)
1455 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1457 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1458 QImode must go into class Q_REGS.
1459 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1460 movdf to do mem-to-mem moves through integer regs. */
1462 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1463 ix86_preferred_reload_class (X, CLASS)
1465 /* If we are copying between general and FP registers, we need a memory
1466 location. The same is true for SSE and MMX registers. */
1467 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1468 ix86_secondary_memory_needed (CLASS1, CLASS2, MODE, 1)
1470 /* QImode spills from non-QI registers need a scratch. This does not
1471 happen often -- the only example so far requires an uninitialized
1474 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
1475 ((CLASS) == GENERAL_REGS && !TARGET_64BIT && (MODE) == QImode \
1478 /* Return the maximum number of consecutive registers
1479 needed to represent mode MODE in a register of class CLASS. */
1480 /* On the 80386, this is the size of MODE in words,
1481 except in the FP regs, where a single reg is always enough.
1482 The TFmodes are really just 80bit values, so we use only 3 registers
1483 to hold them, instead of 4, as the size would suggest.
1485 #define CLASS_MAX_NREGS(CLASS, MODE) \
1486 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1487 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1488 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1489 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1491 /* A C expression whose value is nonzero if pseudos that have been
1492 assigned to registers of class CLASS would likely be spilled
1493 because registers of CLASS are needed for spill registers.
1495 The default value of this macro returns 1 if CLASS has exactly one
1496 register and zero otherwise. On most machines, this default
1497 should be used. Only define this macro to some other expression
1498 if pseudo allocated by `local-alloc.c' end up in memory because
1499 their hard registers were needed for spill registers. If this
1500 macro returns nonzero for those classes, those pseudos will only
1501 be allocated by `global.c', which knows how to reallocate the
1502 pseudo to another register. If there would not be another
1503 register available for reallocation, you should not change the
1504 definition of this macro since the only effect of such a
1505 definition would be to slow down register allocation. */
1507 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1508 (((CLASS) == AREG) \
1509 || ((CLASS) == DREG) \
1510 || ((CLASS) == CREG) \
1511 || ((CLASS) == BREG) \
1512 || ((CLASS) == AD_REGS) \
1513 || ((CLASS) == SIREG) \
1514 || ((CLASS) == DIREG))
1516 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1517 to automatically clobber for all asms.
1519 We do this in the new i386 backend to maintain source compatibility
1520 with the old cc0-based compiler. */
1522 #define MD_ASM_CLOBBERS(CLOBBERS) \
1524 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), (CLOBBERS));\
1525 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), (CLOBBERS)); \
1526 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), (CLOBBERS)); \
1529 /* Stack layout; function entry, exit and calling. */
1531 /* Define this if pushing a word on the stack
1532 makes the stack pointer a smaller address. */
1533 #define STACK_GROWS_DOWNWARD
1535 /* Define this if the nominal address of the stack frame
1536 is at the high-address end of the local variables;
1537 that is, each additional local variable allocated
1538 goes at a more negative offset in the frame. */
1539 #define FRAME_GROWS_DOWNWARD
1541 /* Offset within stack frame to start allocating local variables at.
1542 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1543 first local allocated. Otherwise, it is the offset to the BEGINNING
1544 of the first local allocated. */
1545 #define STARTING_FRAME_OFFSET 0
1547 /* If we generate an insn to push BYTES bytes,
1548 this says how many the stack pointer really advances by.
1549 On 386 pushw decrements by exactly 2 no matter what the position was.
1550 On the 386 there is no pushb; we use pushw instead, and this
1551 has the effect of rounding up to 2.
1553 For 64bit ABI we round up to 8 bytes.
1556 #define PUSH_ROUNDING(BYTES) \
1558 ? (((BYTES) + 7) & (-8)) \
1559 : (((BYTES) + 1) & (-2)))
1561 /* If defined, the maximum amount of space required for outgoing arguments will
1562 be computed and placed into the variable
1563 `current_function_outgoing_args_size'. No space will be pushed onto the
1564 stack for each call; instead, the function prologue should increase the stack
1565 frame size by this amount. */
1567 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1569 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1570 instructions to pass outgoing arguments. */
1572 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1574 /* Offset of first parameter from the argument pointer register value. */
1575 #define FIRST_PARM_OFFSET(FNDECL) 0
1577 /* Define this macro if functions should assume that stack space has been
1578 allocated for arguments even when their values are passed in registers.
1580 The value of this macro is the size, in bytes, of the area reserved for
1581 arguments passed in registers for the function represented by FNDECL.
1583 This space can be allocated by the caller, or be a part of the
1584 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1586 #define REG_PARM_STACK_SPACE(FNDECL) 0
1588 /* Define as a C expression that evaluates to nonzero if we do not know how
1589 to pass TYPE solely in registers. The file expr.h defines a
1590 definition that is usually appropriate, refer to expr.h for additional
1591 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1592 computed in the stack and then loaded into a register. */
1593 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1595 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1596 || TREE_ADDRESSABLE (TYPE) \
1597 || ((MODE) == TImode) \
1598 || ((MODE) == BLKmode \
1599 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1600 && 0 == (int_size_in_bytes (TYPE) \
1601 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1602 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1603 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1605 /* Value is the number of bytes of arguments automatically
1606 popped when returning from a subroutine call.
1607 FUNDECL is the declaration node of the function (as a tree),
1608 FUNTYPE is the data type of the function (as a tree),
1609 or for a library call it is an identifier node for the subroutine name.
1610 SIZE is the number of bytes of arguments passed on the stack.
1612 On the 80386, the RTD insn may be used to pop them if the number
1613 of args is fixed, but if the number is variable then the caller
1614 must pop them all. RTD can't be used for library calls now
1615 because the library is compiled with the Unix compiler.
1616 Use of RTD is a selectable option, since it is incompatible with
1617 standard Unix calling sequences. If the option is not selected,
1618 the caller must always pop the args.
1620 The attribute stdcall is equivalent to RTD on a per module basis. */
1622 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
1623 (ix86_return_pops_args (FUNDECL, FUNTYPE, SIZE))
1625 /* Define how to find the value returned by a function.
1626 VALTYPE is the data type of the value (as a tree).
1627 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1628 otherwise, FUNC is 0. */
1629 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1630 ix86_function_value (VALTYPE)
1632 #define FUNCTION_VALUE_REGNO_P(N) \
1633 ix86_function_value_regno_p (N)
1635 /* Define how to find the value returned by a library function
1636 assuming the value has mode MODE. */
1638 #define LIBCALL_VALUE(MODE) \
1639 ix86_libcall_value (MODE)
1641 /* Define the size of the result block used for communication between
1642 untyped_call and untyped_return. The block contains a DImode value
1643 followed by the block used by fnsave and frstor. */
1645 #define APPLY_RESULT_SIZE (8+108)
1647 /* 1 if N is a possible register number for function argument passing. */
1648 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1650 /* Define a data type for recording info about an argument list
1651 during the scan of that argument list. This data type should
1652 hold all necessary information about the function itself
1653 and about the args processed so far, enough to enable macros
1654 such as FUNCTION_ARG to determine where the next arg should go. */
1656 typedef struct ix86_args {
1657 int words; /* # words passed so far */
1658 int nregs; /* # registers available for passing */
1659 int regno; /* next available register number */
1660 int sse_words; /* # sse words passed so far */
1661 int sse_nregs; /* # sse registers available for passing */
1662 int sse_regno; /* next available sse register number */
1663 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1666 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1667 for a call to a function whose data type is FNTYPE.
1668 For a library call, FNTYPE is 0. */
1670 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1671 (init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1673 /* Update the data in CUM to advance over an argument
1674 of mode MODE and data type TYPE.
1675 (TYPE is null for libcalls where that information may not be available.) */
1677 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1678 (function_arg_advance (&CUM, MODE, TYPE, NAMED))
1680 /* Define where to put the arguments to a function.
1681 Value is zero to push the argument on the stack,
1682 or a hard register in which to store the argument.
1684 MODE is the argument's machine mode.
1685 TYPE is the data type of the argument (as a tree).
1686 This is null for libcalls where that information may
1688 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1689 the preceding args and about the function being called.
1690 NAMED is nonzero if this argument is a named parameter
1691 (otherwise it is an extra parameter matching an ellipsis). */
1693 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1694 (function_arg (&CUM, MODE, TYPE, NAMED))
1696 /* For an arg passed partly in registers and partly in memory,
1697 this is the number of registers used.
1698 For args passed entirely in registers or entirely in memory, zero. */
1700 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1702 /* If PIC, we cannot make sibling calls to global functions
1703 because the PLT requires %ebx live.
1704 If we are returning floats on the register stack, we cannot make
1705 sibling calls to functions that return floats. (The stack adjust
1706 instruction will wind up after the sibcall jump, and not be executed.) */
1707 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1709 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1710 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1711 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1712 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1714 /* Perform any needed actions needed for a function that is receiving a
1715 variable number of arguments.
1719 MODE and TYPE are the mode and type of the current parameter.
1721 PRETEND_SIZE is a variable that should be set to the amount of stack
1722 that must be pushed by the prolog to pretend that our caller pushed
1725 Normally, this macro will push all remaining incoming registers on the
1726 stack and set PRETEND_SIZE to the length of the registers pushed. */
1728 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1729 ix86_setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1731 /* Define the `__builtin_va_list' type for the ABI. */
1732 #define BUILD_VA_LIST_TYPE(VALIST) \
1733 (VALIST) = ix86_build_va_list ()
1735 /* Implement `va_start' for varargs and stdarg. */
1736 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1737 ix86_va_start (stdarg, valist, nextarg)
1739 /* Implement `va_arg'. */
1740 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1741 ix86_va_arg (valist, type)
1743 /* This macro is invoked at the end of compilation. It is used here to
1744 output code for -fpic that will load the return address into %ebx. */
1747 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1749 /* Output assembler code to FILE to increment profiler label # LABELNO
1750 for profiling a function entry. */
1752 #define FUNCTION_PROFILER(FILE, LABELNO) \
1756 fprintf (FILE, "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1757 LPREFIX, (LABELNO)); \
1758 fprintf (FILE, "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1762 fprintf (FILE, "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1763 fprintf (FILE, "\tcall\t_mcount\n"); \
1767 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1768 the stack pointer does not matter. The value is tested only in
1769 functions that have frame pointers.
1770 No definition is equivalent to always zero. */
1771 /* Note on the 386 it might be more efficient not to define this since
1772 we have to restore it ourselves from the frame pointer, in order to
1775 #define EXIT_IGNORE_STACK 1
1777 /* Output assembler code for a block containing the constant parts
1778 of a trampoline, leaving space for the variable parts. */
1780 /* On the 386, the trampoline contains two instructions:
1783 The trampoline is generated entirely at runtime. The operand of JMP
1784 is the address of FUNCTION relative to the instruction following the
1785 JMP (which is 5 bytes long). */
1787 /* Length in units of the trampoline for entering a nested function. */
1789 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1791 /* Emit RTL insns to initialize the variable parts of a trampoline.
1792 FNADDR is an RTX for the address of the function's pure code.
1793 CXT is an RTX for the static chain value for the function. */
1795 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1796 x86_initialize_trampoline (TRAMP, FNADDR, CXT)
1798 /* Definitions for register eliminations.
1800 This is an array of structures. Each structure initializes one pair
1801 of eliminable registers. The "from" register number is given first,
1802 followed by "to". Eliminations of the same "from" register are listed
1803 in order of preference.
1805 There are two registers that can always be eliminated on the i386.
1806 The frame pointer and the arg pointer can be replaced by either the
1807 hard frame pointer or to the stack pointer, depending upon the
1808 circumstances. The hard frame pointer is not used before reload and
1809 so it is not eligible for elimination. */
1811 #define ELIMINABLE_REGS \
1812 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1813 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1814 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1815 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1817 /* Given FROM and TO register numbers, say whether this elimination is
1818 allowed. Frame pointer elimination is automatically handled.
1820 All other eliminations are valid. */
1822 #define CAN_ELIMINATE(FROM, TO) \
1823 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1825 /* Define the offset between two registers, one to be eliminated, and the other
1826 its replacement, at the start of a routine. */
1828 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1829 (OFFSET) = ix86_initial_elimination_offset (FROM, TO)
1831 /* Addressing modes, and classification of registers for them. */
1833 /* #define HAVE_POST_INCREMENT 0 */
1834 /* #define HAVE_POST_DECREMENT 0 */
1836 /* #define HAVE_PRE_DECREMENT 0 */
1837 /* #define HAVE_PRE_INCREMENT 0 */
1839 /* Macros to check register numbers against specific register classes. */
1841 /* These assume that REGNO is a hard or pseudo reg number.
1842 They give nonzero only if REGNO is a hard reg of the suitable class
1843 or a pseudo reg currently allocated to a suitable hard reg.
1844 Since they use reg_renumber, they are safe only once reg_renumber
1845 has been allocated, which happens in local-alloc.c. */
1847 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1848 ((REGNO) < STACK_POINTER_REGNUM \
1849 || (REGNO >= FIRST_REX_INT_REG \
1850 && (REGNO) <= LAST_REX_INT_REG) \
1851 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1852 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1853 || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM)
1855 #define REGNO_OK_FOR_BASE_P(REGNO) \
1856 ((REGNO) <= STACK_POINTER_REGNUM \
1857 || (REGNO) == ARG_POINTER_REGNUM \
1858 || (REGNO) == FRAME_POINTER_REGNUM \
1859 || (REGNO >= FIRST_REX_INT_REG \
1860 && (REGNO) <= LAST_REX_INT_REG) \
1861 || ((unsigned) reg_renumber[REGNO] >= FIRST_REX_INT_REG \
1862 && (unsigned) reg_renumber[REGNO] <= LAST_REX_INT_REG) \
1863 || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM)
1865 #define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4)
1866 #define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5)
1868 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1869 and check its validity for a certain class.
1870 We have two alternate definitions for each of them.
1871 The usual definition accepts all pseudo regs; the other rejects
1872 them unless they have been allocated suitable hard regs.
1873 The symbol REG_OK_STRICT causes the latter definition to be used.
1875 Most source files want to accept pseudo regs in the hope that
1876 they will get allocated to the class that the insn wants them to be in.
1877 Source files for reload pass need to be strict.
1878 After reload, it makes no difference, since pseudo regs have
1879 been eliminated by then. */
1882 /* Non strict versions, pseudos are ok */
1883 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1884 (REGNO (X) < STACK_POINTER_REGNUM \
1885 || (REGNO (X) >= FIRST_REX_INT_REG \
1886 && REGNO (X) <= LAST_REX_INT_REG) \
1887 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1889 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1890 (REGNO (X) <= STACK_POINTER_REGNUM \
1891 || REGNO (X) == ARG_POINTER_REGNUM \
1892 || REGNO (X) == FRAME_POINTER_REGNUM \
1893 || (REGNO (X) >= FIRST_REX_INT_REG \
1894 && REGNO (X) <= LAST_REX_INT_REG) \
1895 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1897 /* Strict versions, hard registers only */
1898 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1899 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1901 #ifndef REG_OK_STRICT
1902 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X)
1903 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X)
1906 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X)
1907 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X)
1910 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1911 that is a valid memory address for an instruction.
1912 The MODE argument is the machine mode for the MEM expression
1913 that wants to use this address.
1915 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1916 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1918 See legitimize_pic_address in i386.c for details as to what
1919 constitutes a legitimate address when -fpic is used. */
1921 #define MAX_REGS_PER_ADDRESS 2
1923 #define CONSTANT_ADDRESS_P(X) \
1924 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1925 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1926 || GET_CODE (X) == CONST_DOUBLE)
1928 /* Nonzero if the constant value X is a legitimate general operand.
1929 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1931 #define LEGITIMATE_CONSTANT_P(X) 1
1933 #ifdef REG_OK_STRICT
1934 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1936 if (legitimate_address_p (MODE, X, 1)) \
1941 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1943 if (legitimate_address_p (MODE, X, 0)) \
1949 /* If defined, a C expression to determine the base term of address X.
1950 This macro is used in only one place: `find_base_term' in alias.c.
1952 It is always safe for this macro to not be defined. It exists so
1953 that alias analysis can understand machine-dependent addresses.
1955 The typical use of this macro is to handle addresses containing
1956 a label_ref or symbol_ref within an UNSPEC. */
1958 #define FIND_BASE_TERM(X) ix86_find_base_term (x)
1960 /* Try machine-dependent ways of modifying an illegitimate address
1961 to be legitimate. If we find one, return the new, valid address.
1962 This macro is used in only one place: `memory_address' in explow.c.
1964 OLDX is the address as it was before break_out_memory_refs was called.
1965 In some cases it is useful to look at this to decide what needs to be done.
1967 MODE and WIN are passed so that this macro can use
1968 GO_IF_LEGITIMATE_ADDRESS.
1970 It is always safe for this macro to do nothing. It exists to recognize
1971 opportunities to optimize the output.
1973 For the 80386, we handle X+REG by loading X into a register R and
1974 using R+REG. R will go in a general reg and indexing will be used.
1975 However, if REG is a broken-out memory address or multiplication,
1976 nothing needs to be done because REG can certainly go in a general reg.
1978 When -fpic is used, special handling is needed for symbolic references.
1979 See comments by legitimize_pic_address in i386.c for details. */
1981 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1983 (X) = legitimize_address (X, OLDX, MODE); \
1984 if (memory_address_p (MODE, X)) \
1988 #define REWRITE_ADDRESS(x) rewrite_address(x)
1990 /* Nonzero if the constant value X is a legitimate general operand
1991 when generating PIC code. It is given that flag_pic is on and
1992 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1994 #define LEGITIMATE_PIC_OPERAND_P(X) \
1995 (! SYMBOLIC_CONST (X) \
1996 || legitimate_pic_address_disp_p (X))
1998 #define SYMBOLIC_CONST(X) \
1999 (GET_CODE (X) == SYMBOL_REF \
2000 || GET_CODE (X) == LABEL_REF \
2001 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2003 /* Go to LABEL if ADDR (a legitimate address expression)
2004 has an effect that depends on the machine mode it is used for.
2005 On the 80386, only postdecrement and postincrement address depend thus
2006 (the amount of decrement or increment being the length of the operand). */
2007 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2008 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL
2010 /* Codes for all the SSE/MMX builtins. */
2022 IX86_BUILTIN_CMPEQPS,
2023 IX86_BUILTIN_CMPLTPS,
2024 IX86_BUILTIN_CMPLEPS,
2025 IX86_BUILTIN_CMPGTPS,
2026 IX86_BUILTIN_CMPGEPS,
2027 IX86_BUILTIN_CMPNEQPS,
2028 IX86_BUILTIN_CMPNLTPS,
2029 IX86_BUILTIN_CMPNLEPS,
2030 IX86_BUILTIN_CMPNGTPS,
2031 IX86_BUILTIN_CMPNGEPS,
2032 IX86_BUILTIN_CMPORDPS,
2033 IX86_BUILTIN_CMPUNORDPS,
2034 IX86_BUILTIN_CMPNEPS,
2035 IX86_BUILTIN_CMPEQSS,
2036 IX86_BUILTIN_CMPLTSS,
2037 IX86_BUILTIN_CMPLESS,
2038 IX86_BUILTIN_CMPGTSS,
2039 IX86_BUILTIN_CMPGESS,
2040 IX86_BUILTIN_CMPNEQSS,
2041 IX86_BUILTIN_CMPNLTSS,
2042 IX86_BUILTIN_CMPNLESS,
2043 IX86_BUILTIN_CMPNGTSS,
2044 IX86_BUILTIN_CMPNGESS,
2045 IX86_BUILTIN_CMPORDSS,
2046 IX86_BUILTIN_CMPUNORDSS,
2047 IX86_BUILTIN_CMPNESS,
2049 IX86_BUILTIN_COMIEQSS,
2050 IX86_BUILTIN_COMILTSS,
2051 IX86_BUILTIN_COMILESS,
2052 IX86_BUILTIN_COMIGTSS,
2053 IX86_BUILTIN_COMIGESS,
2054 IX86_BUILTIN_COMINEQSS,
2055 IX86_BUILTIN_UCOMIEQSS,
2056 IX86_BUILTIN_UCOMILTSS,
2057 IX86_BUILTIN_UCOMILESS,
2058 IX86_BUILTIN_UCOMIGTSS,
2059 IX86_BUILTIN_UCOMIGESS,
2060 IX86_BUILTIN_UCOMINEQSS,
2062 IX86_BUILTIN_CVTPI2PS,
2063 IX86_BUILTIN_CVTPS2PI,
2064 IX86_BUILTIN_CVTSI2SS,
2065 IX86_BUILTIN_CVTSS2SI,
2066 IX86_BUILTIN_CVTTPS2PI,
2067 IX86_BUILTIN_CVTTSS2SI,
2068 IX86_BUILTIN_M_FROM_INT,
2069 IX86_BUILTIN_M_TO_INT,
2076 IX86_BUILTIN_LOADAPS,
2077 IX86_BUILTIN_LOADUPS,
2078 IX86_BUILTIN_STOREAPS,
2079 IX86_BUILTIN_STOREUPS,
2080 IX86_BUILTIN_LOADSS,
2081 IX86_BUILTIN_STORESS,
2084 IX86_BUILTIN_MOVHLPS,
2085 IX86_BUILTIN_MOVLHPS,
2086 IX86_BUILTIN_LOADHPS,
2087 IX86_BUILTIN_LOADLPS,
2088 IX86_BUILTIN_STOREHPS,
2089 IX86_BUILTIN_STORELPS,
2091 IX86_BUILTIN_MASKMOVQ,
2092 IX86_BUILTIN_MOVMSKPS,
2093 IX86_BUILTIN_PMOVMSKB,
2095 IX86_BUILTIN_MOVNTPS,
2096 IX86_BUILTIN_MOVNTQ,
2098 IX86_BUILTIN_PACKSSWB,
2099 IX86_BUILTIN_PACKSSDW,
2100 IX86_BUILTIN_PACKUSWB,
2105 IX86_BUILTIN_PADDSB,
2106 IX86_BUILTIN_PADDSW,
2107 IX86_BUILTIN_PADDUSB,
2108 IX86_BUILTIN_PADDUSW,
2112 IX86_BUILTIN_PSUBSB,
2113 IX86_BUILTIN_PSUBSW,
2114 IX86_BUILTIN_PSUBUSB,
2115 IX86_BUILTIN_PSUBUSW,
2125 IX86_BUILTIN_PCMPEQB,
2126 IX86_BUILTIN_PCMPEQW,
2127 IX86_BUILTIN_PCMPEQD,
2128 IX86_BUILTIN_PCMPGTB,
2129 IX86_BUILTIN_PCMPGTW,
2130 IX86_BUILTIN_PCMPGTD,
2132 IX86_BUILTIN_PEXTRW,
2133 IX86_BUILTIN_PINSRW,
2135 IX86_BUILTIN_PMADDWD,
2137 IX86_BUILTIN_PMAXSW,
2138 IX86_BUILTIN_PMAXUB,
2139 IX86_BUILTIN_PMINSW,
2140 IX86_BUILTIN_PMINUB,
2142 IX86_BUILTIN_PMULHUW,
2143 IX86_BUILTIN_PMULHW,
2144 IX86_BUILTIN_PMULLW,
2146 IX86_BUILTIN_PSADBW,
2147 IX86_BUILTIN_PSHUFW,
2157 IX86_BUILTIN_PSLLWI,
2158 IX86_BUILTIN_PSLLDI,
2159 IX86_BUILTIN_PSLLQI,
2160 IX86_BUILTIN_PSRAWI,
2161 IX86_BUILTIN_PSRADI,
2162 IX86_BUILTIN_PSRLWI,
2163 IX86_BUILTIN_PSRLDI,
2164 IX86_BUILTIN_PSRLQI,
2166 IX86_BUILTIN_PUNPCKHBW,
2167 IX86_BUILTIN_PUNPCKHWD,
2168 IX86_BUILTIN_PUNPCKHDQ,
2169 IX86_BUILTIN_PUNPCKLBW,
2170 IX86_BUILTIN_PUNPCKLWD,
2171 IX86_BUILTIN_PUNPCKLDQ,
2173 IX86_BUILTIN_SHUFPS,
2177 IX86_BUILTIN_RSQRTPS,
2178 IX86_BUILTIN_RSQRTSS,
2179 IX86_BUILTIN_SQRTPS,
2180 IX86_BUILTIN_SQRTSS,
2182 IX86_BUILTIN_UNPCKHPS,
2183 IX86_BUILTIN_UNPCKLPS,
2186 IX86_BUILTIN_ANDNPS,
2191 IX86_BUILTIN_LDMXCSR,
2192 IX86_BUILTIN_STMXCSR,
2193 IX86_BUILTIN_SFENCE,
2194 IX86_BUILTIN_PREFETCH,
2196 /* 3DNow! Original */
2198 IX86_BUILTIN_PAVGUSB,
2202 IX86_BUILTIN_PFCMPEQ,
2203 IX86_BUILTIN_PFCMPGE,
2204 IX86_BUILTIN_PFCMPGT,
2209 IX86_BUILTIN_PFRCPIT1,
2210 IX86_BUILTIN_PFRCPIT2,
2211 IX86_BUILTIN_PFRSQIT1,
2212 IX86_BUILTIN_PFRSQRT,
2214 IX86_BUILTIN_PFSUBR,
2216 IX86_BUILTIN_PMULHRW,
2217 IX86_BUILTIN_PREFETCH_3DNOW, /* PREFETCH already used */
2218 IX86_BUILTIN_PREFETCHW,
2220 /* 3DNow! Athlon Extensions */
2222 IX86_BUILTIN_PFNACC,
2223 IX86_BUILTIN_PFPNACC,
2225 IX86_BUILTIN_PSWAPDSI,
2226 IX86_BUILTIN_PSWAPDSF,
2228 /* Composite builtins, expand to more than one insn. */
2229 IX86_BUILTIN_SETPS1,
2232 IX86_BUILTIN_SETRPS,
2233 IX86_BUILTIN_LOADPS1,
2234 IX86_BUILTIN_LOADRPS,
2235 IX86_BUILTIN_STOREPS1,
2236 IX86_BUILTIN_STORERPS,
2238 IX86_BUILTIN_MMX_ZERO,
2243 /* Define this macro if references to a symbol must be treated
2244 differently depending on something about the variable or
2245 function named by the symbol (such as what section it is in).
2247 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2248 so that we may access it directly in the GOT. */
2250 #define ENCODE_SECTION_INFO(DECL) \
2255 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2256 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2258 if (GET_CODE (rtl) == MEM) \
2260 if (TARGET_DEBUG_ADDR \
2261 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2263 fprintf (stderr, "Encode %s, public = %d\n", \
2264 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2265 TREE_PUBLIC (DECL)); \
2268 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2269 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2270 || ! TREE_PUBLIC (DECL)); \
2276 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2277 codes once the function is being compiled into assembly code, but
2278 not before. (It is not done before, because in the case of
2279 compiling an inline function, it would lead to multiple PIC
2280 prologues being included in functions which used inline functions
2281 and were compiled to assembly language.) */
2283 #define FINALIZE_PIC \
2286 current_function_uses_pic_offset_table |= profile_flag; \
2291 /* Max number of args passed in registers. If this is more than 3, we will
2292 have problems with ebx (register #4), since it is a caller save register and
2293 is also used as the pic register in ELF. So for now, don't allow more than
2294 3 registers to be passed in registers. */
2296 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2298 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2301 /* Specify the machine mode that this machine uses
2302 for the index in the tablejump instruction. */
2303 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2305 /* Define as C expression which evaluates to nonzero if the tablejump
2306 instruction expects the table to contain offsets from the address of the
2308 Do not define this if the table should contain absolute addresses. */
2309 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2311 /* Specify the tree operation to be used to convert reals to integers.
2312 This should be changed to take advantage of fist --wfs ??
2314 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2316 /* This is the kind of divide that is easiest to do in the general case. */
2317 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2319 /* Define this as 1 if `char' should by default be signed; else as 0. */
2320 #define DEFAULT_SIGNED_CHAR 1
2322 /* Number of bytes moved into a data cache for a single prefetch operation. */
2323 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2325 /* Number of prefetch operations that can be done in parallel. */
2326 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2328 /* Max number of bytes we can move from memory to memory
2329 in one reasonably fast instruction. */
2332 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2333 move efficiently, as opposed to MOVE_MAX which is the maximum
2334 number of bytes we can move with a single instruction. */
2335 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2337 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2338 move-instruction pairs, we will do a movstr or libcall instead.
2339 Increasing the value will always make code faster, but eventually
2340 incurs high cost in increased code size.
2342 If you don't define this, a reasonable default is used. */
2344 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2346 /* Define if shifts truncate the shift count
2347 which implies one can omit a sign-extension or zero-extension
2348 of a shift count. */
2349 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2351 /* #define SHIFT_COUNT_TRUNCATED */
2353 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2354 is done just by pretending it is already truncated. */
2355 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2357 /* We assume that the store-condition-codes instructions store 0 for false
2358 and some other value for true. This is the value stored for true. */
2360 #define STORE_FLAG_VALUE 1
2362 /* When a prototype says `char' or `short', really pass an `int'.
2363 (The 386 can't easily push less than an int.) */
2365 #define PROMOTE_PROTOTYPES 1
2367 /* A macro to update M and UNSIGNEDP when an object whose type is
2368 TYPE and which has the specified mode and signedness is to be
2369 stored in a register. This macro is only called when TYPE is a
2372 On i386 it is sometimes useful to promote HImode and QImode
2373 quantities to SImode. The choice depends on target type. */
2375 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2376 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2377 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2380 /* Specify the machine mode that pointers have.
2381 After generation of rtl, the compiler makes no further distinction
2382 between pointers and any other objects of this machine mode. */
2383 #define Pmode (TARGET_64BIT ? DImode : SImode)
2385 /* A function address in a call instruction
2386 is a byte address (for indexing purposes)
2387 so give the MEM rtx a byte's mode. */
2388 #define FUNCTION_MODE QImode
2390 /* A part of a C `switch' statement that describes the relative costs
2391 of constant RTL expressions. It must contain `case' labels for
2392 expression codes `const_int', `const', `symbol_ref', `label_ref'
2393 and `const_double'. Each case must ultimately reach a `return'
2394 statement to return the relative cost of the use of that kind of
2395 constant value in an expression. The cost may depend on the
2396 precise value of the constant, which is available for examination
2397 in X, and the rtx code of the expression in which it is contained,
2398 found in OUTER_CODE.
2400 CODE is the expression code--redundant, since it can be obtained
2401 with `GET_CODE (X)'. */
2403 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2408 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2410 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2412 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2414 case CONST_DOUBLE: \
2417 if (GET_MODE (RTX) == VOIDmode) \
2420 code = standard_80387_constant_p (RTX); \
2421 return code == 1 ? 1 : \
2426 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2427 #define TOPLEVEL_COSTS_N_INSNS(N) \
2428 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2430 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2431 This can be used, for example, to indicate how costly a multiply
2432 instruction is. In writing this macro, you can use the construct
2433 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2434 instructions. OUTER_CODE is the code of the expression in which X
2437 This macro is optional; do not define it if the default cost
2438 assumptions are adequate for the target machine. */
2440 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2442 /* The zero extensions is often completely free on x86_64, so make \
2443 it as cheap as possible. */ \
2444 if (TARGET_64BIT && GET_MODE (X) == DImode \
2445 && GET_MODE (XEXP (X, 0)) == SImode) \
2447 total = 1; goto egress_rtx_costs; \
2450 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2451 ix86_cost->add : ix86_cost->movzx); \
2454 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2457 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2458 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2460 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2462 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2463 if ((value == 2 || value == 3) \
2464 && !TARGET_DECOMPOSE_LEA \
2465 && ix86_cost->lea <= ix86_cost->shift_const) \
2466 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2468 /* fall through */ \
2474 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2476 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2478 if (INTVAL (XEXP (X, 1)) > 32) \
2479 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2481 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2485 if (GET_CODE (XEXP (X, 1)) == AND) \
2486 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2488 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2493 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2494 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2496 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2501 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2503 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2506 while (value != 0) \
2512 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2513 + nbits * ix86_cost->mult_bit); \
2515 else /* This is arbitrary */ \
2516 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2517 + 7 * ix86_cost->mult_bit); \
2523 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2526 if (!TARGET_DECOMPOSE_LEA \
2527 && INTEGRAL_MODE_P (GET_MODE (X)) \
2528 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2530 if (GET_CODE (XEXP (X, 0)) == PLUS \
2531 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2532 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2533 && CONSTANT_P (XEXP (X, 1))) \
2535 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2536 if (val == 2 || val == 4 || val == 8) \
2538 return (COSTS_N_INSNS (ix86_cost->lea) \
2539 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2540 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), OUTER_CODE) \
2541 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2544 else if (GET_CODE (XEXP (X, 0)) == MULT \
2545 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2547 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2548 if (val == 2 || val == 4 || val == 8) \
2550 return (COSTS_N_INSNS (ix86_cost->lea) \
2551 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2552 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2555 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2557 return (COSTS_N_INSNS (ix86_cost->lea) \
2558 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
2559 + rtx_cost (XEXP (XEXP (X, 0), 1), OUTER_CODE) \
2560 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
2564 /* fall through */ \
2569 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2570 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2571 + (rtx_cost (XEXP (X, 0), OUTER_CODE) \
2572 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2573 + (rtx_cost (XEXP (X, 1), OUTER_CODE) \
2574 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2576 /* fall through */ \
2579 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2580 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2581 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2587 /* An expression giving the cost of an addressing mode that contains
2588 ADDRESS. If not defined, the cost is computed from the ADDRESS
2589 expression and the `CONST_COSTS' values.
2591 For most CISC machines, the default cost is a good approximation
2592 of the true cost of the addressing mode. However, on RISC
2593 machines, all instructions normally have the same length and
2594 execution time. Hence all addresses will have equal costs.
2596 In cases where more than one form of an address is known, the form
2597 with the lowest cost will be used. If multiple forms have the
2598 same, lowest, cost, the one that is the most complex will be used.
2600 For example, suppose an address that is equal to the sum of a
2601 register and a constant is used twice in the same basic block.
2602 When this macro is not defined, the address will be computed in a
2603 register and memory references will be indirect through that
2604 register. On machines where the cost of the addressing mode
2605 containing the sum is no higher than that of a simple indirect
2606 reference, this will produce an additional instruction and
2607 possibly require an additional register. Proper specification of
2608 this macro eliminates this overhead for such machines.
2610 Similar use of this macro is made in strength reduction of loops.
2612 ADDRESS need not be valid as an address. In such a case, the cost
2613 is not relevant and can be any value; invalid addresses need not be
2614 assigned a different cost.
2616 On machines where an address involving more than one register is as
2617 cheap as an address computation involving only one register,
2618 defining `ADDRESS_COST' to reflect this can cause two registers to
2619 be live over a region of code where only one would have been if
2620 `ADDRESS_COST' were not defined in that manner. This effect should
2621 be considered in the definition of this macro. Equivalent costs
2622 should probably only be given to addresses with different numbers
2623 of registers on machines with lots of registers.
2625 This macro will normally either not be defined or be defined as a
2628 For i386, it is better to use a complex address than let gcc copy
2629 the address into a reg and make a new pseudo. But not if the address
2630 requires to two regs - that would mean more pseudos with longer
2633 #define ADDRESS_COST(RTX) \
2634 ix86_address_cost (RTX)
2636 /* A C expression for the cost of moving data from a register in class FROM to
2637 one in class TO. The classes are expressed using the enumeration values
2638 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2639 interpreted relative to that.
2641 It is not required that the cost always equal 2 when FROM is the same as TO;
2642 on some machines it is expensive to move between registers if they are not
2643 general registers. */
2645 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2646 ix86_register_move_cost (MODE, CLASS1, CLASS2)
2648 /* A C expression for the cost of moving data of mode M between a
2649 register and memory. A value of 2 is the default; this cost is
2650 relative to those in `REGISTER_MOVE_COST'.
2652 If moving between registers and memory is more expensive than
2653 between two registers, you should define this macro to express the
2656 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
2657 ix86_memory_move_cost (MODE, CLASS, IN)
2659 /* A C expression for the cost of a branch instruction. A value of 1
2660 is the default; other values are interpreted relative to that. */
2662 #define BRANCH_COST ix86_branch_cost
2664 /* Define this macro as a C expression which is nonzero if accessing
2665 less than a word of memory (i.e. a `char' or a `short') is no
2666 faster than accessing a word of memory, i.e., if such access
2667 require more than one instruction or if there is no difference in
2668 cost between byte and (aligned) word loads.
2670 When this macro is not defined, the compiler will access a field by
2671 finding the smallest containing object; when it is defined, a
2672 fullword load will be used if alignment permits. Unless bytes
2673 accesses are faster than word accesses, using word accesses is
2674 preferable since it may eliminate subsequent memory access if
2675 subsequent accesses occur to other fields in the same word of the
2676 structure, but to different bytes. */
2678 #define SLOW_BYTE_ACCESS 0
2680 /* Nonzero if access to memory by shorts is slow and undesirable. */
2681 #define SLOW_SHORT_ACCESS 0
2683 /* Define this macro if zero-extension (of a `char' or `short' to an
2684 `int') can be done faster if the destination is a register that is
2687 If you define this macro, you must have instruction patterns that
2688 recognize RTL structures like this:
2690 (set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
2692 and likewise for `HImode'. */
2694 /* #define SLOW_ZERO_EXTEND */
2696 /* Define this macro to be the value 1 if unaligned accesses have a
2697 cost many times greater than aligned accesses, for example if they
2698 are emulated in a trap handler.
2700 When this macro is non-zero, the compiler will act as if
2701 `STRICT_ALIGNMENT' were non-zero when generating code for block
2702 moves. This can cause significantly more instructions to be
2703 produced. Therefore, do not set this macro non-zero if unaligned
2704 accesses only add a cycle or two to the time for a memory access.
2706 If the value of this macro is always zero, it need not be defined. */
2708 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2710 /* Define this macro to inhibit strength reduction of memory
2711 addresses. (On some machines, such strength reduction seems to do
2712 harm rather than good.) */
2714 /* #define DONT_REDUCE_ADDR */
2716 /* Define this macro if it is as good or better to call a constant
2717 function address than to call an address kept in a register.
2719 Desirable on the 386 because a CALL with a constant address is
2720 faster than one with a register address. */
2722 #define NO_FUNCTION_CSE
2724 /* Define this macro if it is as good or better for a function to call
2725 itself with an explicit address than to call an address kept in a
2728 #define NO_RECURSIVE_FUNCTION_CSE
2730 /* Add any extra modes needed to represent the condition code.
2732 For the i386, we need separate modes when floating-point
2733 equality comparisons are being done.
2735 Add CCNO to indicate comparisons against zero that requires
2736 Overflow flag to be unset. Sign bit test is used instead and
2737 thus can be used to form "a&b>0" type of tests.
2739 Add CCGC to indicate comparisons agains zero that allows
2740 unspecified garbage in the Carry flag. This mode is used
2741 by inc/dec instructions.
2743 Add CCGOC to indicate comparisons agains zero that allows
2744 unspecified garbage in the Carry and Overflow flag. This
2745 mode is used to simulate comparisons of (a-b) and (a+b)
2746 against zero using sub/cmp/add operations.
2748 Add CCZ to indicate that only the Zero flag is valid. */
2750 #define EXTRA_CC_MODES \
2751 CC(CCGCmode, "CCGC") \
2752 CC(CCGOCmode, "CCGOC") \
2753 CC(CCNOmode, "CCNO") \
2754 CC(CCZmode, "CCZ") \
2755 CC(CCFPmode, "CCFP") \
2756 CC(CCFPUmode, "CCFPU")
2758 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2759 return the mode to be used for the comparison.
2761 For floating-point equality comparisons, CCFPEQmode should be used.
2762 VOIDmode should be used in all other cases.
2764 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2765 possible, to allow for more combinations. */
2767 #define SELECT_CC_MODE(OP,X,Y) ix86_cc_mode (OP, X, Y)
2769 /* Return non-zero if MODE implies a floating point inequality can be
2772 #define REVERSIBLE_CC_MODE(MODE) 1
2774 /* A C expression whose value is reversed condition code of the CODE for
2775 comparison done in CC_MODE mode. */
2776 #define REVERSE_CONDITION(CODE, MODE) \
2777 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2778 : reverse_condition_maybe_unordered (CODE))
2781 /* Control the assembler format that we output, to the extent
2782 this does not vary between assemblers. */
2784 /* How to refer to registers in assembler output.
2785 This sequence is indexed by compiler's hard-register-number (see above). */
2787 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2788 For non floating point regs, the following are the HImode names.
2790 For float regs, the stack top is sometimes referred to as "%st(0)"
2791 instead of just "%st". PRINT_REG handles this with the "y" code. */
2793 #undef HI_REGISTER_NAMES
2794 #define HI_REGISTER_NAMES \
2795 {"ax","dx","cx","bx","si","di","bp","sp", \
2796 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2797 "flags","fpsr", "dirflag", "frame", \
2798 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2799 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2800 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2801 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2803 #define REGISTER_NAMES HI_REGISTER_NAMES
2805 /* Table of additional register names to use in user input. */
2807 #define ADDITIONAL_REGISTER_NAMES \
2808 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2809 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2810 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2811 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2812 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2813 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2814 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2815 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2817 /* Note we are omitting these since currently I don't know how
2818 to get gcc to use these, since they want the same but different
2819 number as al, and ax.
2822 #define QI_REGISTER_NAMES \
2823 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2825 /* These parallel the array above, and can be used to access bits 8:15
2826 of regs 0 through 3. */
2828 #define QI_HIGH_REGISTER_NAMES \
2829 {"ah", "dh", "ch", "bh", }
2831 /* How to renumber registers for dbx and gdb. */
2833 #define DBX_REGISTER_NUMBER(n) \
2834 (TARGET_64BIT ? dbx64_register_map[n] : dbx_register_map[n])
2836 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2837 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2838 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2840 /* Before the prologue, RA is at 0(%esp). */
2841 #define INCOMING_RETURN_ADDR_RTX \
2842 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2844 /* After the prologue, RA is at -4(AP) in the current frame. */
2845 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2847 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2848 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2850 /* PC is dbx register 8; let's use that column for RA. */
2851 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2853 /* Before the prologue, the top of the frame is at 4(%esp). */
2854 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2856 /* Describe how we implement __builtin_eh_return. */
2857 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2858 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2861 /* Select a format to encode pointers in exception handling data. CODE
2862 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2863 true if the symbol may be affected by dynamic relocations.
2865 ??? All x86 object file formats are capable of representing this.
2866 After all, the relocation needed is the same as for the call insn.
2867 Whether or not a particular assembler allows us to enter such, I
2868 guess we'll have to see. */
2869 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2871 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2874 /* This is how to output the definition of a user-level label named NAME,
2875 such as the label on a static function or variable NAME. */
2877 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2878 (assemble_name (FILE, NAME), fputs (":\n", FILE))
2880 /* Store in OUTPUT a string (made with alloca) containing
2881 an assembler-name for a local static variable named NAME.
2882 LABELNO is an integer which is different for each call. */
2884 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2885 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2886 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2888 /* This is how to output an insn to push a register on the stack.
2889 It need not be very fast code. */
2891 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2892 asm_fprintf (FILE, "\tpush{l}\t%%e%s\n", reg_names[REGNO])
2894 /* This is how to output an insn to pop a register from the stack.
2895 It need not be very fast code. */
2897 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2898 asm_fprintf (FILE, "\tpop{l}\t%%e%s\n", reg_names[REGNO])
2900 /* This is how to output an element of a case-vector that is absolute. */
2902 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2903 ix86_output_addr_vec_elt (FILE, VALUE)
2905 /* This is how to output an element of a case-vector that is relative. */
2907 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2908 ix86_output_addr_diff_elt (FILE, VALUE, REL)
2910 /* Under some conditions we need jump tables in the text section, because
2911 the assembler cannot handle label differences between sections. */
2913 #define JUMP_TABLES_IN_TEXT_SECTION \
2914 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2916 /* A C statement that outputs an address constant appropriate to
2917 for DWARF debugging. */
2919 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE,X) \
2920 i386_dwarf_output_addr_const((FILE),(X))
2922 /* Either simplify a location expression, or return the original. */
2924 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2925 i386_simplify_dwarf_addr(X)
2927 /* Print operand X (an rtx) in assembler syntax to file FILE.
2928 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2929 Effect of various CODE letters is described in i386.c near
2930 print_operand function. */
2932 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2933 ((CODE) == '*' || (CODE) == '+')
2935 /* Print the name of a register based on its machine mode and number.
2936 If CODE is 'w', pretend the mode is HImode.
2937 If CODE is 'b', pretend the mode is QImode.
2938 If CODE is 'k', pretend the mode is SImode.
2939 If CODE is 'q', pretend the mode is DImode.
2940 If CODE is 'h', pretend the reg is the `high' byte register.
2941 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2943 #define PRINT_REG(X, CODE, FILE) \
2944 print_reg (X, CODE, FILE)
2946 #define PRINT_OPERAND(FILE, X, CODE) \
2947 print_operand (FILE, X, CODE)
2949 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2950 print_operand_address (FILE, ADDR)
2952 /* Print the name of a register for based on its machine mode and number.
2953 This macro is used to print debugging output.
2954 This macro is different from PRINT_REG in that it may be used in
2955 programs that are not linked with aux-output.o. */
2957 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2958 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2959 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2960 fprintf (FILE, "%d ", REGNO (X)); \
2961 if (REGNO (X) == FLAGS_REG) \
2962 { fputs ("flags", FILE); break; } \
2963 if (REGNO (X) == DIRFLAG_REG) \
2964 { fputs ("dirflag", FILE); break; } \
2965 if (REGNO (X) == FPSR_REG) \
2966 { fputs ("fpsr", FILE); break; } \
2967 if (REGNO (X) == ARG_POINTER_REGNUM) \
2968 { fputs ("argp", FILE); break; } \
2969 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2970 { fputs ("frame", FILE); break; } \
2971 if (STACK_TOP_P (X)) \
2972 { fputs ("st(0)", FILE); break; } \
2974 { fputs (hi_name[REGNO(X)], FILE); break; } \
2975 if (REX_INT_REG_P (X)) \
2977 switch (GET_MODE_SIZE (GET_MODE (X))) \
2981 fprintf (FILE, "r%i", REGNO (X) \
2982 - FIRST_REX_INT_REG + 8); \
2985 fprintf (FILE, "r%id", REGNO (X) \
2986 - FIRST_REX_INT_REG + 8); \
2989 fprintf (FILE, "r%iw", REGNO (X) \
2990 - FIRST_REX_INT_REG + 8); \
2993 fprintf (FILE, "r%ib", REGNO (X) \
2994 - FIRST_REX_INT_REG + 8); \
2999 switch (GET_MODE_SIZE (GET_MODE (X))) \
3002 fputs ("r", FILE); \
3003 fputs (hi_name[REGNO (X)], FILE); \
3006 fputs ("e", FILE); \
3008 fputs (hi_name[REGNO (X)], FILE); \
3011 fputs (qi_name[REGNO (X)], FILE); \
3016 /* a letter which is not needed by the normal asm syntax, which
3017 we can use for operand syntax in the extended asm */
3019 #define ASM_OPERAND_LETTER '#'
3020 #define RET return ""
3021 #define AT_SP(mode) (gen_rtx_MEM ((mode), stack_pointer_rtx))
3023 /* Define the codes that are matched by predicates in i386.c. */
3025 #define PREDICATE_CODES \
3026 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3027 SYMBOL_REF, LABEL_REF, CONST}}, \
3028 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3029 SYMBOL_REF, LABEL_REF, CONST}}, \
3030 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3031 SYMBOL_REF, LABEL_REF, CONST}}, \
3032 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3033 SYMBOL_REF, LABEL_REF, CONST}}, \
3034 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3035 SYMBOL_REF, LABEL_REF, CONST}}, \
3036 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3037 SYMBOL_REF, LABEL_REF, CONST}}, \
3038 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3039 SYMBOL_REF, LABEL_REF}}, \
3040 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3041 {"const_int_1_operand", {CONST_INT}}, \
3042 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3043 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3044 LABEL_REF, SUBREG, REG, MEM}}, \
3045 {"pic_symbolic_operand", {CONST}}, \
3046 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3047 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3048 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3049 {"const1_operand", {CONST_INT}}, \
3050 {"const248_operand", {CONST_INT}}, \
3051 {"incdec_operand", {CONST_INT}}, \
3052 {"mmx_reg_operand", {REG}}, \
3053 {"reg_no_sp_operand", {SUBREG, REG}}, \
3054 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3055 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3056 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3057 {"q_regs_operand", {SUBREG, REG}}, \
3058 {"non_q_regs_operand", {SUBREG, REG}}, \
3059 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3060 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3061 GE, UNGE, LTGT, UNEQ}}, \
3062 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3063 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3065 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3066 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3067 UNGE, UNGT, LTGT, UNEQ }}, \
3068 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3069 {"ext_register_operand", {SUBREG, REG}}, \
3070 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3071 {"mult_operator", {MULT}}, \
3072 {"div_operator", {DIV}}, \
3073 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3074 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3075 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3076 LSHIFTRT, ROTATERT}}, \
3077 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3078 {"memory_displacement_operand", {MEM}}, \
3079 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3080 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3081 {"long_memory_operand", {MEM}},
3083 /* A list of predicates that do special things with modes, and so
3084 should not elicit warnings for VOIDmode match_operand. */
3086 #define SPECIAL_MODE_PREDICATES \
3087 "ext_register_operand",
3089 /* CM_32 is used by 32bit ABI
3090 CM_SMALL is small model assuming that all code and data fits in the first
3091 31bits of address space.
3092 CM_KERNEL is model assuming that all code and data fits in the negative
3093 31bits of address space.
3094 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3095 space. Size of data is unlimited.
3096 CM_LARGE is model making no assumptions about size of particular sections.
3098 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3099 tables first in 31bits of address space.
3110 /* Size of the RED_ZONE area. */
3111 #define RED_ZONE_SIZE 128
3112 /* Reserved area of the red zone for temporaries. */
3113 #define RED_ZONE_RESERVE 8
3114 extern const char *ix86_debug_arg_string, *ix86_debug_addr_string;
3120 extern const char *ix86_asm_string;
3121 extern enum cmodel ix86_asm_dialect;
3122 /* Valud of -mcmodel specified by user. */
3123 extern const char *ix86_cmodel_string;
3124 extern enum cmodel ix86_cmodel;
3126 /* Variables in i386.c */
3127 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3128 extern const char *ix86_arch_string; /* for -march=<xxx> */
3129 extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
3130 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3131 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3132 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3133 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3134 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3135 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3136 extern int ix86_regparm; /* ix86_regparm_string as a number */
3137 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3138 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3139 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */
3140 extern struct rtx_def *ix86_compare_op0; /* operand 0 for comparisons */
3141 extern struct rtx_def *ix86_compare_op1; /* operand 1 for comparisons */
3143 /* To properly truncate FP values into integers, we need to set i387 control
3144 word. We can't emit proper mode switching code before reload, as spills
3145 generated by reload may truncate values incorrectly, but we still can avoid
3146 redundant computation of new control word by the mode switching pass.
3147 The fldcw instructions are still emitted redundantly, but this is probably
3148 not going to be noticeable problem, as most CPUs do have fast path for
3151 The machinery is to emit simple truncation instructions and split them
3152 before reload to instructions having USEs of two memory locations that
3153 are filled by this code to old and new control word.
3155 Post-reload pass may be later used to eliminate the redundant fildcw if
3158 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3160 /* Define this macro if the port needs extra instructions inserted
3161 for mode switching in an optimizing compilation. */
3163 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3165 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3166 initializer for an array of integers. Each initializer element N
3167 refers to an entity that needs mode switching, and specifies the
3168 number of different modes that might need to be set for this
3169 entity. The position of the initializer in the initializer -
3170 starting counting at zero - determines the integer that is used to
3171 refer to the mode-switched entity in question. */
3173 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3175 /* ENTITY is an integer specifying a mode-switched entity. If
3176 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3177 return an integer value not larger than the corresponding element
3178 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3179 must be switched into prior to the execution of INSN. */
3181 #define MODE_NEEDED(ENTITY, I) \
3182 (GET_CODE (I) == CALL_INSN \
3183 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3184 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3185 ? FP_CW_UNINITIALIZED \
3186 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3190 /* This macro specifies the order in which modes for ENTITY are
3191 processed. 0 is the highest priority. */
3193 #define MODE_PRIORITY_TO_MODE(ENTITY, N) N
3195 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3196 is the set of hard registers live at the point where the insn(s)
3197 are to be inserted. */
3199 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3200 (MODE == FP_CW_STORED \
3201 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3202 assign_386_stack_local (HImode, 2)), 0\
3205 /* Avoid renaming of stack registers, as doing so in combination with
3206 scheduling just increases amount of live registers at time and in
3207 the turn amount of fxch instructions needed.
3209 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3211 #define HARD_REGNO_RENAME_OK(src,target) \
3212 ((src) < FIRST_STACK_REG || (src) > LAST_STACK_REG)
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