1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Redefines for option macros. */
39 #define TARGET_64BIT OPTION_ISA_64BIT
40 #define TARGET_MMX OPTION_ISA_MMX
41 #define TARGET_3DNOW OPTION_ISA_3DNOW
42 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A
43 #define TARGET_SSE OPTION_ISA_SSE
44 #define TARGET_SSE2 OPTION_ISA_SSE2
45 #define TARGET_SSE3 OPTION_ISA_SSE3
46 #define TARGET_SSSE3 OPTION_ISA_SSSE3
47 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1
48 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2
49 #define TARGET_SSE4A OPTION_ISA_SSE4A
50 #define TARGET_SSE5 OPTION_ISA_SSE5
51 #define TARGET_ROUND OPTION_ISA_ROUND
53 /* SSE5 and SSE4.1 define the same round instructions */
54 #define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE5)
55 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
57 #include "config/vxworks-dummy.h"
59 /* Algorithm to expand string function with. */
72 #define NAX_STRINGOP_ALGS 4
74 /* Specify what algorithm to use for stringops on known size.
75 When size is unknown, the UNKNOWN_SIZE alg is used. When size is
76 known at compile time or estimated via feedback, the SIZE array
77 is walked in order until MAX is greater then the estimate (or -1
78 means infinity). Corresponding ALG is used then.
79 For example initializer:
80 {{256, loop}, {-1, rep_prefix_4_byte}}
81 will use loop for blocks smaller or equal to 256 bytes, rep prefix will
85 const enum stringop_alg unknown_size;
86 const struct stringop_strategy {
88 const enum stringop_alg alg;
89 } size [NAX_STRINGOP_ALGS];
92 /* Define the specific costs for a given cpu */
94 struct processor_costs {
95 const int add; /* cost of an add instruction */
96 const int lea; /* cost of a lea instruction */
97 const int shift_var; /* variable shift costs */
98 const int shift_const; /* constant shift costs */
99 const int mult_init[5]; /* cost of starting a multiply
100 in QImode, HImode, SImode, DImode, TImode*/
101 const int mult_bit; /* cost of multiply per each bit set */
102 const int divide[5]; /* cost of a divide/mod
103 in QImode, HImode, SImode, DImode, TImode*/
104 int movsx; /* The cost of movsx operation. */
105 int movzx; /* The cost of movzx operation. */
106 const int large_insn; /* insns larger than this cost more */
107 const int move_ratio; /* The threshold of number of scalar
108 memory-to-memory move insns. */
109 const int movzbl_load; /* cost of loading using movzbl */
110 const int int_load[3]; /* cost of loading integer registers
111 in QImode, HImode and SImode relative
112 to reg-reg move (2). */
113 const int int_store[3]; /* cost of storing integer register
114 in QImode, HImode and SImode */
115 const int fp_move; /* cost of reg,reg fld/fst */
116 const int fp_load[3]; /* cost of loading FP register
117 in SFmode, DFmode and XFmode */
118 const int fp_store[3]; /* cost of storing FP register
119 in SFmode, DFmode and XFmode */
120 const int mmx_move; /* cost of moving MMX register. */
121 const int mmx_load[2]; /* cost of loading MMX register
122 in SImode and DImode */
123 const int mmx_store[2]; /* cost of storing MMX register
124 in SImode and DImode */
125 const int sse_move; /* cost of moving SSE register. */
126 const int sse_load[3]; /* cost of loading SSE register
127 in SImode, DImode and TImode*/
128 const int sse_store[3]; /* cost of storing SSE register
129 in SImode, DImode and TImode*/
130 const int mmxsse_to_integer; /* cost of moving mmxsse register to
131 integer and vice versa. */
132 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
133 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
134 const int prefetch_block; /* bytes moved to cache for prefetch. */
135 const int simultaneous_prefetches; /* number of parallel prefetch
137 const int branch_cost; /* Default value for BRANCH_COST. */
138 const int fadd; /* cost of FADD and FSUB instructions. */
139 const int fmul; /* cost of FMUL instruction. */
140 const int fdiv; /* cost of FDIV instruction. */
141 const int fabs; /* cost of FABS instruction. */
142 const int fchs; /* cost of FCHS instruction. */
143 const int fsqrt; /* cost of FSQRT instruction. */
144 /* Specify what algorithm
145 to use for stringops on unknown size. */
146 struct stringop_algs memcpy[2], memset[2];
147 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding
149 const int scalar_load_cost; /* Cost of scalar load. */
150 const int scalar_store_cost; /* Cost of scalar store. */
151 const int vec_stmt_cost; /* Cost of any vector operation, excluding
152 load, store, vector-to-scalar and
153 scalar-to-vector operation. */
154 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */
155 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */
156 const int vec_align_load_cost; /* Cost of aligned vector load. */
157 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */
158 const int vec_store_cost; /* Cost of vector store. */
159 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer
161 const int cond_not_taken_branch_cost;/* Cost of not taken branch for
162 vectorizer cost model. */
165 extern const struct processor_costs *ix86_cost;
167 /* Macros used in the machine description to test the flags. */
169 /* configure can arrange to make this 2, to force a 486. */
171 #ifndef TARGET_CPU_DEFAULT
172 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic
175 #ifndef TARGET_FPMATH_DEFAULT
176 #define TARGET_FPMATH_DEFAULT \
177 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)
180 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS
182 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
183 compile-time constant. */
187 #define TARGET_64BIT 1
189 #define TARGET_64BIT 0
192 #ifndef TARGET_BI_ARCH
194 #if TARGET_64BIT_DEFAULT
195 #define TARGET_64BIT 1
197 #define TARGET_64BIT 0
202 #define HAS_LONG_COND_BRANCH 1
203 #define HAS_LONG_UNCOND_BRANCH 1
205 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
206 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
207 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
208 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
209 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)
210 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
211 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
212 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
213 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
214 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
215 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
216 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
217 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
218 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
219 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
220 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
222 /* Feature tests against the various tunings. */
223 enum ix86_tune_indices {
225 X86_TUNE_PUSH_MEMORY,
226 X86_TUNE_ZERO_EXTEND_WITH_AND,
227 X86_TUNE_USE_BIT_TEST,
228 X86_TUNE_UNROLL_STRLEN,
229 X86_TUNE_DEEP_BRANCH_PREDICTION,
230 X86_TUNE_BRANCH_PREDICTION_HINTS,
231 X86_TUNE_DOUBLE_WITH_ADD,
234 X86_TUNE_PARTIAL_REG_STALL,
235 X86_TUNE_PARTIAL_FLAG_REG_STALL,
236 X86_TUNE_USE_HIMODE_FIOP,
237 X86_TUNE_USE_SIMODE_FIOP,
241 X86_TUNE_SPLIT_LONG_MOVES,
242 X86_TUNE_READ_MODIFY_WRITE,
243 X86_TUNE_READ_MODIFY,
244 X86_TUNE_PROMOTE_QIMODE,
245 X86_TUNE_FAST_PREFIX,
246 X86_TUNE_SINGLE_STRINGOP,
247 X86_TUNE_QIMODE_MATH,
248 X86_TUNE_HIMODE_MATH,
249 X86_TUNE_PROMOTE_QI_REGS,
250 X86_TUNE_PROMOTE_HI_REGS,
255 X86_TUNE_INTEGER_DFMODE_MOVES,
256 X86_TUNE_PARTIAL_REG_DEPENDENCY,
257 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,
258 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,
259 X86_TUNE_SSE_SPLIT_REGS,
260 X86_TUNE_SSE_TYPELESS_STORES,
261 X86_TUNE_SSE_LOAD0_BY_PXOR,
262 X86_TUNE_MEMORY_MISMATCH_STALL,
263 X86_TUNE_PROLOGUE_USING_MOVE,
264 X86_TUNE_EPILOGUE_USING_MOVE,
267 X86_TUNE_INTER_UNIT_MOVES,
268 X86_TUNE_INTER_UNIT_CONVERSIONS,
269 X86_TUNE_FOUR_JUMP_LIMIT,
273 X86_TUNE_PAD_RETURNS,
274 X86_TUNE_EXT_80387_CONSTANTS,
275 X86_TUNE_SHORTEN_X87_SSE,
276 X86_TUNE_AVOID_VECTOR_DECODE,
277 X86_TUNE_PROMOTE_HIMODE_IMUL,
278 X86_TUNE_SLOW_IMUL_IMM32_MEM,
279 X86_TUNE_SLOW_IMUL_IMM8,
280 X86_TUNE_MOVE_M1_VIA_OR,
281 X86_TUNE_NOT_UNPAIRABLE,
282 X86_TUNE_NOT_VECTORMODE,
283 X86_TUNE_USE_VECTOR_CONVERTS,
288 extern unsigned int ix86_tune_features[X86_TUNE_LAST];
290 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE]
291 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY]
292 #define TARGET_ZERO_EXTEND_WITH_AND \
293 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]
294 #define TARGET_USE_BIT_TEST ix86_tune_features[X86_TUNE_USE_BIT_TEST]
295 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN]
296 #define TARGET_DEEP_BRANCH_PREDICTION \
297 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]
298 #define TARGET_BRANCH_PREDICTION_HINTS \
299 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]
300 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]
301 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF]
302 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX]
303 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]
304 #define TARGET_PARTIAL_FLAG_REG_STALL \
305 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]
306 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]
307 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]
308 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0]
309 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD]
310 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB]
311 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]
312 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]
313 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY]
314 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]
315 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX]
316 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]
317 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH]
318 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH]
319 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]
320 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]
321 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4]
322 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8]
323 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4]
324 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8]
325 #define TARGET_INTEGER_DFMODE_MOVES \
326 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]
327 #define TARGET_PARTIAL_REG_DEPENDENCY \
328 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]
329 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
330 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]
331 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \
332 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]
333 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]
334 #define TARGET_SSE_TYPELESS_STORES \
335 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]
336 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]
337 #define TARGET_MEMORY_MISMATCH_STALL \
338 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]
339 #define TARGET_PROLOGUE_USING_MOVE \
340 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]
341 #define TARGET_EPILOGUE_USING_MOVE \
342 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]
343 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1]
344 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP]
345 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]
346 #define TARGET_INTER_UNIT_CONVERSIONS\
347 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]
348 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]
349 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE]
350 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT]
351 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC]
352 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
353 #define TARGET_EXT_80387_CONSTANTS \
354 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
355 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
356 #define TARGET_AVOID_VECTOR_DECODE \
357 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
358 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \
359 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]
360 #define TARGET_SLOW_IMUL_IMM32_MEM \
361 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
362 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
363 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
364 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
365 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
366 #define TARGET_USE_VECTOR_CONVERTS ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
368 /* Feature tests against the various architecture variations. */
369 enum ix86_arch_indices {
370 X86_ARCH_CMOVE, /* || TARGET_SSE */
379 extern unsigned int ix86_arch_features[X86_ARCH_LAST];
381 #define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE]
382 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG]
383 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B]
384 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD]
385 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP]
387 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
389 extern int x86_prefetch_sse;
391 #define TARGET_ABM x86_abm
392 #define TARGET_CMPXCHG16B x86_cmpxchg16b
393 #define TARGET_POPCNT x86_popcnt
394 #define TARGET_PREFETCH_SSE x86_prefetch_sse
395 #define TARGET_SAHF x86_sahf
396 #define TARGET_RECIP x86_recip
397 #define TARGET_FUSED_MADD x86_fused_muladd
398 #define TARGET_AES (TARGET_SSE2 && x86_aes)
399 #define TARGET_PCLMUL (TARGET_SSE2 && x86_pclmul)
401 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
403 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
404 #define TARGET_MIX_SSE_I387 \
405 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))
407 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
408 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2)
409 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS)
410 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
412 extern int ix86_isa_flags;
414 #ifndef TARGET_64BIT_DEFAULT
415 #define TARGET_64BIT_DEFAULT 0
417 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
418 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
421 /* Fence to use after loop using storent. */
423 extern tree x86_mfence;
424 #define FENCE_FOLLOWING_MOVNT x86_mfence
426 /* Once GDB has been enhanced to deal with functions without frame
427 pointers, we can change this to allow for elimination of
428 the frame pointer in leaf functions. */
429 #define TARGET_DEFAULT 0
431 /* Extra bits to force. */
432 #define TARGET_SUBTARGET_DEFAULT 0
433 #define TARGET_SUBTARGET_ISA_DEFAULT 0
435 /* Extra bits to force on w/ 32-bit mode. */
436 #define TARGET_SUBTARGET32_DEFAULT 0
437 #define TARGET_SUBTARGET32_ISA_DEFAULT 0
439 /* Extra bits to force on w/ 64-bit mode. */
440 #define TARGET_SUBTARGET64_DEFAULT 0
441 #define TARGET_SUBTARGET64_ISA_DEFAULT 0
443 /* This is not really a target flag, but is done this way so that
444 it's analogous to similar code for Mach-O on PowerPC. darwin.h
445 redefines this to 1. */
446 #define TARGET_MACHO 0
448 /* Likewise, for the Windows 64-bit ABI. */
449 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
451 /* Available call abi. */
458 /* The default abi form used by target. */
459 #define DEFAULT_ABI SYSV_ABI
461 /* Subtargets may reset this to 1 in order to enable 96-bit long double
462 with the rounding mode forced to 53 bits. */
463 #define TARGET_96_ROUND_53_LONG_DOUBLE 0
465 /* Sometimes certain combinations of command options do not make
466 sense on a particular target machine. You can define a macro
467 `OVERRIDE_OPTIONS' to take account of this. This macro, if
468 defined, is executed once just after all the command options have
471 Don't use this macro to turn on various extra optimizations for
472 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
474 #define OVERRIDE_OPTIONS override_options ()
476 /* Define this to change the optimizations performed by default. */
477 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
478 optimization_options ((LEVEL), (SIZE))
480 /* -march=native handling only makes sense with compiler running on
481 an x86 or x86_64 chip. If changing this condition, also change
482 the condition in driver-i386.c. */
483 #if defined(__i386__) || defined(__x86_64__)
484 /* In driver-i386.c. */
485 extern const char *host_detect_local_cpu (int argc, const char **argv);
486 #define EXTRA_SPEC_FUNCTIONS \
487 { "local_cpu_detect", host_detect_local_cpu },
488 #define HAVE_LOCAL_CPU_DETECT
491 /* Support for configure-time defaults of some command line options.
492 The order here is important so that -march doesn't squash the
493 tune or cpu values. */
494 #define OPTION_DEFAULT_SPECS \
495 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
496 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
497 {"arch", "%{!march=*:-march=%(VALUE)}"}
499 /* Specs for the compiler proper */
502 #define CC1_CPU_SPEC_1 "\
504 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \
506 %{mintel-syntax:-masm=intel \
507 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
508 %{mno-intel-syntax:-masm=att \
509 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
511 #ifndef HAVE_LOCAL_CPU_DETECT
512 #define CC1_CPU_SPEC CC1_CPU_SPEC_1
514 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \
515 "%{march=native:%<march=native %:local_cpu_detect(arch) \
516 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \
517 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
521 /* Target CPU builtins. */
522 #define TARGET_CPU_CPP_BUILTINS() \
525 size_t arch_len = strlen (ix86_arch_string); \
526 size_t tune_len = strlen (ix86_tune_string); \
527 int last_arch_char = ix86_arch_string[arch_len - 1]; \
528 int last_tune_char = ix86_tune_string[tune_len - 1]; \
532 builtin_assert ("cpu=x86_64"); \
533 builtin_assert ("machine=x86_64"); \
534 builtin_define ("__amd64"); \
535 builtin_define ("__amd64__"); \
536 builtin_define ("__x86_64"); \
537 builtin_define ("__x86_64__"); \
541 builtin_assert ("cpu=i386"); \
542 builtin_assert ("machine=i386"); \
543 builtin_define_std ("i386"); \
546 /* Built-ins based on -march=. */ \
549 case PROCESSOR_I386: \
551 case PROCESSOR_I486: \
552 builtin_define ("__i486"); \
553 builtin_define ("__i486__"); \
555 case PROCESSOR_PENTIUM: \
556 builtin_define ("__i586"); \
557 builtin_define ("__i586__"); \
558 builtin_define ("__pentium"); \
559 builtin_define ("__pentium__"); \
560 if (last_arch_char == 'x') \
561 builtin_define ("__pentium_mmx__"); \
563 case PROCESSOR_PENTIUMPRO: \
564 builtin_define ("__i686"); \
565 builtin_define ("__i686__"); \
566 builtin_define ("__pentiumpro"); \
567 builtin_define ("__pentiumpro__"); \
569 case PROCESSOR_GEODE: \
570 builtin_define ("__geode"); \
571 builtin_define ("__geode__"); \
574 builtin_define ("__k6"); \
575 builtin_define ("__k6__"); \
576 if (last_arch_char == '2') \
577 builtin_define ("__k6_2__"); \
578 else if (last_arch_char == '3') \
579 builtin_define ("__k6_3__"); \
581 case PROCESSOR_ATHLON: \
582 builtin_define ("__athlon"); \
583 builtin_define ("__athlon__"); \
584 /* Only plain "athlon" lacks SSE. */ \
585 if (last_arch_char != 'n') \
586 builtin_define ("__athlon_sse__"); \
589 builtin_define ("__k8"); \
590 builtin_define ("__k8__"); \
592 case PROCESSOR_AMDFAM10: \
593 builtin_define ("__amdfam10"); \
594 builtin_define ("__amdfam10__"); \
596 case PROCESSOR_PENTIUM4: \
597 builtin_define ("__pentium4"); \
598 builtin_define ("__pentium4__"); \
600 case PROCESSOR_NOCONA: \
601 builtin_define ("__nocona"); \
602 builtin_define ("__nocona__"); \
604 case PROCESSOR_CORE2: \
605 builtin_define ("__core2"); \
606 builtin_define ("__core2__"); \
608 case PROCESSOR_GENERIC32: \
609 case PROCESSOR_GENERIC64: \
610 case PROCESSOR_max: \
611 gcc_unreachable (); \
614 /* Built-ins based on -mtune=. */ \
617 case PROCESSOR_I386: \
618 builtin_define ("__tune_i386__"); \
620 case PROCESSOR_I486: \
621 builtin_define ("__tune_i486__"); \
623 case PROCESSOR_PENTIUM: \
624 builtin_define ("__tune_i586__"); \
625 builtin_define ("__tune_pentium__"); \
626 if (last_tune_char == 'x') \
627 builtin_define ("__tune_pentium_mmx__"); \
629 case PROCESSOR_PENTIUMPRO: \
630 builtin_define ("__tune_i686__"); \
631 builtin_define ("__tune_pentiumpro__"); \
632 switch (last_tune_char) \
635 builtin_define ("__tune_pentium3__"); \
638 builtin_define ("__tune_pentium2__"); \
642 case PROCESSOR_GEODE: \
643 builtin_define ("__tune_geode__"); \
646 builtin_define ("__tune_k6__"); \
647 if (last_tune_char == '2') \
648 builtin_define ("__tune_k6_2__"); \
649 else if (last_tune_char == '3') \
650 builtin_define ("__tune_k6_3__"); \
652 case PROCESSOR_ATHLON: \
653 builtin_define ("__tune_athlon__"); \
654 /* Only plain "athlon" lacks SSE. */ \
655 if (last_tune_char != 'n') \
656 builtin_define ("__tune_athlon_sse__"); \
659 builtin_define ("__tune_k8__"); \
661 case PROCESSOR_AMDFAM10: \
662 builtin_define ("__tune_amdfam10__"); \
664 case PROCESSOR_PENTIUM4: \
665 builtin_define ("__tune_pentium4__"); \
667 case PROCESSOR_NOCONA: \
668 builtin_define ("__tune_nocona__"); \
670 case PROCESSOR_CORE2: \
671 builtin_define ("__tune_core2__"); \
673 case PROCESSOR_GENERIC32: \
674 case PROCESSOR_GENERIC64: \
676 case PROCESSOR_max: \
677 gcc_unreachable (); \
681 builtin_define ("__MMX__"); \
683 builtin_define ("__3dNOW__"); \
684 if (TARGET_3DNOW_A) \
685 builtin_define ("__3dNOW_A__"); \
687 builtin_define ("__SSE__"); \
689 builtin_define ("__SSE2__"); \
691 builtin_define ("__SSE3__"); \
693 builtin_define ("__SSSE3__"); \
695 builtin_define ("__SSE4_1__"); \
697 builtin_define ("__SSE4_2__"); \
699 builtin_define ("__AES__"); \
701 builtin_define ("__PCLMUL__"); \
703 builtin_define ("__SSE4A__"); \
705 builtin_define ("__SSE5__"); \
706 if (TARGET_SSE_MATH && TARGET_SSE) \
707 builtin_define ("__SSE_MATH__"); \
708 if (TARGET_SSE_MATH && TARGET_SSE2) \
709 builtin_define ("__SSE2_MATH__"); \
713 enum target_cpu_default
715 TARGET_CPU_DEFAULT_generic = 0,
717 TARGET_CPU_DEFAULT_i386,
718 TARGET_CPU_DEFAULT_i486,
719 TARGET_CPU_DEFAULT_pentium,
720 TARGET_CPU_DEFAULT_pentium_mmx,
721 TARGET_CPU_DEFAULT_pentiumpro,
722 TARGET_CPU_DEFAULT_pentium2,
723 TARGET_CPU_DEFAULT_pentium3,
724 TARGET_CPU_DEFAULT_pentium4,
725 TARGET_CPU_DEFAULT_pentium_m,
726 TARGET_CPU_DEFAULT_prescott,
727 TARGET_CPU_DEFAULT_nocona,
728 TARGET_CPU_DEFAULT_core2,
730 TARGET_CPU_DEFAULT_geode,
731 TARGET_CPU_DEFAULT_k6,
732 TARGET_CPU_DEFAULT_k6_2,
733 TARGET_CPU_DEFAULT_k6_3,
734 TARGET_CPU_DEFAULT_athlon,
735 TARGET_CPU_DEFAULT_athlon_sse,
736 TARGET_CPU_DEFAULT_k8,
737 TARGET_CPU_DEFAULT_amdfam10,
739 TARGET_CPU_DEFAULT_max
743 #define CC1_SPEC "%(cc1_cpu) "
746 /* This macro defines names of additional specifications to put in the
747 specs that can be used in various specifications like CC1_SPEC. Its
748 definition is an initializer with a subgrouping for each command option.
750 Each subgrouping contains a string constant, that defines the
751 specification name, and a string constant that used by the GCC driver
754 Do not define this macro if it does not need to do anything. */
756 #ifndef SUBTARGET_EXTRA_SPECS
757 #define SUBTARGET_EXTRA_SPECS
760 #define EXTRA_SPECS \
761 { "cc1_cpu", CC1_CPU_SPEC }, \
762 SUBTARGET_EXTRA_SPECS
765 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
766 FPU, assume that the fpcw is set to extended precision; when using
767 only SSE, rounding is correct; when using both SSE and the FPU,
768 the rounding precision is indeterminate, since either may be chosen
769 apparently at random. */
770 #define TARGET_FLT_EVAL_METHOD \
771 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
773 /* target machine storage layout */
775 #define SHORT_TYPE_SIZE 16
776 #define INT_TYPE_SIZE 32
777 #define FLOAT_TYPE_SIZE 32
778 #define LONG_TYPE_SIZE BITS_PER_WORD
779 #define DOUBLE_TYPE_SIZE 64
780 #define LONG_LONG_TYPE_SIZE 64
781 #define LONG_DOUBLE_TYPE_SIZE 80
783 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE
785 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
786 #define MAX_BITS_PER_WORD 64
788 #define MAX_BITS_PER_WORD 32
791 /* Define this if most significant byte of a word is the lowest numbered. */
792 /* That is true on the 80386. */
794 #define BITS_BIG_ENDIAN 0
796 /* Define this if most significant byte of a word is the lowest numbered. */
797 /* That is not true on the 80386. */
798 #define BYTES_BIG_ENDIAN 0
800 /* Define this if most significant word of a multiword number is the lowest
802 /* Not true for 80386 */
803 #define WORDS_BIG_ENDIAN 0
805 /* Width of a word, in units (bytes). */
806 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
808 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
810 #define MIN_UNITS_PER_WORD 4
813 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
814 #define PARM_BOUNDARY BITS_PER_WORD
816 /* Boundary (in *bits*) on which stack pointer should be aligned. */
817 #define STACK_BOUNDARY (TARGET_64BIT && DEFAULT_ABI == MS_ABI ? 128 \
820 /* Boundary (in *bits*) on which the stack pointer prefers to be
821 aligned; the compiler cannot rely on having this alignment. */
822 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
824 /* As of July 2001, many runtimes do not align the stack properly when
825 entering main. This causes expand_main_function to forcibly align
826 the stack, which results in aligned frames for functions called from
827 main, though it does nothing for the alignment of main itself. */
828 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
829 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
831 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is
832 mandatory for the 64-bit ABI, and may or may not be true for other
833 operating systems. */
834 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT
836 /* Minimum allocation boundary for the code of a function. */
837 #define FUNCTION_BOUNDARY 8
839 /* C++ stores the virtual bit in the lowest bit of function pointers. */
840 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
842 /* Alignment of field after `int : 0' in a structure. */
844 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
846 /* Minimum size in bits of the largest boundary to which any
847 and all fundamental data types supported by the hardware
848 might need to be aligned. No data type wants to be aligned
851 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
852 and Pentium Pro XFmode values at 128 bit boundaries. */
854 #define BIGGEST_ALIGNMENT 128
856 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
857 #define ALIGN_MODE_128(MODE) \
858 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))
860 /* The published ABIs say that doubles should be aligned on word
861 boundaries, so lower the alignment for structure fields unless
862 -malign-double is set. */
864 /* ??? Blah -- this macro is used directly by libobjc. Since it
865 supports no vector modes, cut out the complexity and fall back
866 on BIGGEST_FIELD_ALIGNMENT. */
867 #ifdef IN_TARGET_LIBS
869 #define BIGGEST_FIELD_ALIGNMENT 128
871 #define BIGGEST_FIELD_ALIGNMENT 32
874 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
875 x86_field_alignment (FIELD, COMPUTED)
878 /* If defined, a C expression to compute the alignment given to a
879 constant that is being placed in memory. EXP is the constant
880 and ALIGN is the alignment that the object would ordinarily have.
881 The value of this macro is used instead of that alignment to align
884 If this macro is not defined, then ALIGN is used.
886 The typical use of this macro is to increase alignment for string
887 constants to be word aligned so that `strcpy' calls that copy
888 constants can be done inline. */
890 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
892 /* If defined, a C expression to compute the alignment for a static
893 variable. TYPE is the data type, and ALIGN is the alignment that
894 the object would ordinarily have. The value of this macro is used
895 instead of that alignment to align the object.
897 If this macro is not defined, then ALIGN is used.
899 One use of this macro is to increase alignment of medium-size
900 data to make it all fit in fewer cache lines. Another is to
901 cause character arrays to be word-aligned so that `strcpy' calls
902 that copy constants to character arrays can be done inline. */
904 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
906 /* If defined, a C expression to compute the alignment for a local
907 variable. TYPE is the data type, and ALIGN is the alignment that
908 the object would ordinarily have. The value of this macro is used
909 instead of that alignment to align the object.
911 If this macro is not defined, then ALIGN is used.
913 One use of this macro is to increase alignment of medium-size
914 data to make it all fit in fewer cache lines. */
916 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
917 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))
919 /* If defined, a C expression to compute the alignment for stack slot.
920 TYPE is the data type, MODE is the widest mode available, and ALIGN
921 is the alignment that the slot would ordinarily have. The value of
922 this macro is used instead of that alignment to align the slot.
924 If this macro is not defined, then ALIGN is used when TYPE is NULL,
925 Otherwise, LOCAL_ALIGNMENT will be used.
927 One use of this macro is to set alignment of stack slot to the
928 maximum alignment of all possible modes which the slot may have. */
930 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \
931 ix86_local_alignment ((TYPE), (MODE), (ALIGN))
933 /* If defined, a C expression that gives the alignment boundary, in
934 bits, of an argument with the specified mode and type. If it is
935 not defined, `PARM_BOUNDARY' is used for all arguments. */
937 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
938 ix86_function_arg_boundary ((MODE), (TYPE))
940 /* Set this nonzero if move instructions will actually fail to work
941 when given unaligned data. */
942 #define STRICT_ALIGNMENT 0
944 /* If bit field type is int, don't let it cross an int,
945 and give entire struct the alignment of an int. */
946 /* Required on the 386 since it doesn't have bit-field insns. */
947 #define PCC_BITFIELD_TYPE_MATTERS 1
949 /* Standard register usage. */
951 /* This processor has special stack-like registers. See reg-stack.c
956 #define IS_STACK_MODE(MODE) \
957 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \
958 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \
961 /* Number of actual hardware registers.
962 The hardware registers are assigned numbers for the compiler
963 from 0 to just below FIRST_PSEUDO_REGISTER.
964 All registers that the compiler knows about must be given numbers,
965 even those that are not normally considered general registers.
967 In the 80386 we give the 8 general purpose registers the numbers 0-7.
968 We number the floating point registers 8-15.
969 Note that registers 0-7 can be accessed as a short or int,
970 while only 0-3 may be used with byte `mov' instructions.
972 Reg 16 does not correspond to any hardware register, but instead
973 appears in the RTL as an argument pointer prior to reload, and is
974 eliminated during reloading in favor of either the stack or frame
977 #define FIRST_PSEUDO_REGISTER 53
979 /* Number of hardware registers that go into the DWARF-2 unwind info.
980 If not defined, equals FIRST_PSEUDO_REGISTER. */
982 #define DWARF_FRAME_REGISTERS 17
984 /* 1 for registers that have pervasive standard uses
985 and are not available for the register allocator.
986 On the 80386, the stack pointer is such, as is the arg pointer.
988 The value is zero if the register is not fixed on either 32 or
989 64 bit targets, one if the register if fixed on both 32 and 64
990 bit targets, two if it is only fixed on 32bit targets and three
991 if its only fixed on 64bit targets.
992 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
994 #define FIXED_REGISTERS \
995 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
996 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
997 /*arg,flags,fpsr,fpcr,frame*/ \
999 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
1000 0, 0, 0, 0, 0, 0, 0, 0, \
1001 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
1002 0, 0, 0, 0, 0, 0, 0, 0, \
1003 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1004 2, 2, 2, 2, 2, 2, 2, 2, \
1005 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
1006 2, 2, 2, 2, 2, 2, 2, 2 }
1009 /* 1 for registers not available across function calls.
1010 These must include the FIXED_REGISTERS and also any
1011 registers that can be used without being saved.
1012 The latter must include the registers where values are returned
1013 and the register where structure-value addresses are passed.
1014 Aside from that, you can include as many other registers as you like.
1016 The value is zero if the register is not call used on either 32 or
1017 64 bit targets, one if the register if call used on both 32 and 64
1018 bit targets, two if it is only call used on 32bit targets and three
1019 if its only call used on 64bit targets.
1020 Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
1022 #define CALL_USED_REGISTERS \
1023 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
1024 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1025 /*arg,flags,fpsr,fpcr,frame*/ \
1027 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
1028 1, 1, 1, 1, 1, 1, 1, 1, \
1029 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
1030 1, 1, 1, 1, 1, 1, 1, 1, \
1031 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
1032 1, 1, 1, 1, 2, 2, 2, 2, \
1033 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
1034 1, 1, 1, 1, 1, 1, 1, 1 }
1036 /* Order in which to allocate registers. Each register must be
1037 listed once, even those in FIXED_REGISTERS. List frame pointer
1038 late and fixed registers last. Note that, in general, we prefer
1039 registers listed in CALL_USED_REGISTERS, keeping the others
1040 available for storage of persistent values.
1042 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
1043 so this is just empty initializer for array. */
1045 #define REG_ALLOC_ORDER \
1046 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
1047 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
1048 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1049 48, 49, 50, 51, 52 }
1051 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1052 to be rearranged based on a particular function. When using sse math,
1053 we want to allocate SSE before x87 registers and vice versa. */
1055 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
1058 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)
1060 /* Macro to conditionally modify fixed_regs/call_used_regs. */
1061 #define CONDITIONAL_REGISTER_USAGE \
1065 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1067 if (fixed_regs[i] > 1) \
1068 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
1069 if (call_used_regs[i] > 1) \
1070 call_used_regs[i] = (call_used_regs[i] \
1071 == (TARGET_64BIT ? 3 : 2)); \
1073 j = PIC_OFFSET_TABLE_REGNUM; \
1074 if (j != INVALID_REGNUM) \
1076 fixed_regs[j] = 1; \
1077 call_used_regs[j] = 1; \
1082 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1083 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
1084 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1089 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1090 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
1091 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1093 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
1097 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
1098 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1099 if (TEST_HARD_REG_BIT (x, i)) \
1100 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = ""; \
1102 if (! TARGET_64BIT) \
1105 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++) \
1106 reg_names[i] = ""; \
1107 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++) \
1108 reg_names[i] = ""; \
1110 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI) \
1112 call_used_regs[4 /*RSI*/] = 0; \
1113 call_used_regs[5 /*RDI*/] = 0; \
1117 /* Return number of consecutive hard regs needed starting at reg REGNO
1118 to hold something of mode MODE.
1119 This is ordinarily the length in words of a value of mode MODE
1120 but can be less for certain modes in special long registers.
1122 Actually there are no two word move instructions for consecutive
1123 registers. And only registers 0-3 may have mov byte instructions
1127 #define HARD_REGNO_NREGS(REGNO, MODE) \
1128 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1129 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1130 : ((MODE) == XFmode \
1131 ? (TARGET_64BIT ? 2 : 3) \
1132 : (MODE) == XCmode \
1133 ? (TARGET_64BIT ? 4 : 6) \
1134 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1136 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \
1137 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \
1138 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1140 : ((MODE) == XFmode || (MODE) == XCmode)) \
1143 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)
1145 #define VALID_SSE2_REG_MODE(MODE) \
1146 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1147 || (MODE) == V2DImode || (MODE) == DFmode)
1149 #define VALID_SSE_REG_MODE(MODE) \
1150 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1151 || (MODE) == SFmode || (MODE) == TFmode)
1153 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1154 ((MODE) == V2SFmode || (MODE) == SFmode)
1156 #define VALID_MMX_REG_MODE(MODE) \
1157 ((MODE == V1DImode) || (MODE) == DImode \
1158 || (MODE) == V2SImode || (MODE) == SImode \
1159 || (MODE) == V4HImode || (MODE) == V8QImode)
1161 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
1162 place emms and femms instructions. */
1163 #define UNITS_PER_SIMD_WORD(MODE) (TARGET_SSE ? 16 : UNITS_PER_WORD)
1165 #define VALID_DFP_MODE_P(MODE) \
1166 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)
1168 #define VALID_FP_MODE_P(MODE) \
1169 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1170 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1172 #define VALID_INT_MODE_P(MODE) \
1173 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1174 || (MODE) == DImode \
1175 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1176 || (MODE) == CDImode \
1177 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1178 || (MODE) == TFmode || (MODE) == TCmode)))
1180 /* Return true for modes passed in SSE registers. */
1181 #define SSE_REG_MODE_P(MODE) \
1182 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1183 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1184 || (MODE) == V4SFmode || (MODE) == V4SImode)
1186 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1188 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1189 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1191 /* Value is 1 if it is a good idea to tie two pseudo registers
1192 when one has mode MODE1 and one has mode MODE2.
1193 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1194 for any hard reg, then this must be 0 for correct output. */
1196 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2)
1198 /* It is possible to write patterns to move flags; but until someone
1200 #define AVOID_CCMODE_COPIES
1202 /* Specify the modes required to caller save a given hard regno.
1203 We do this on i386 to prevent flags from being saved at all.
1205 Kill any attempts to combine saving of modes. */
1207 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1208 (CC_REGNO_P (REGNO) ? VOIDmode \
1209 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1210 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \
1211 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1212 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1215 /* Specify the registers used for certain standard purposes.
1216 The values of these macros are register numbers. */
1218 /* on the 386 the pc register is %eip, and is not usable as a general
1219 register. The ordinary mov instructions won't work */
1220 /* #define PC_REGNUM */
1222 /* Register to use for pushing function arguments. */
1223 #define STACK_POINTER_REGNUM 7
1225 /* Base register for access to local variables of the function. */
1226 #define HARD_FRAME_POINTER_REGNUM 6
1228 /* Base register for access to local variables of the function. */
1229 #define FRAME_POINTER_REGNUM 20
1231 /* First floating point reg */
1232 #define FIRST_FLOAT_REG 8
1234 /* First & last stack-like regs */
1235 #define FIRST_STACK_REG FIRST_FLOAT_REG
1236 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1238 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1239 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1241 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1242 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1244 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1245 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1247 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1248 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1250 /* Value should be nonzero if functions must have frame pointers.
1251 Zero means the frame pointer need not be set up (and parms
1252 may be accessed via the stack pointer) in functions that seem suitable.
1253 This is computed in `reload', in reload1.c. */
1254 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1256 /* Override this in other tm.h files to cope with various OS lossage
1257 requiring a frame pointer. */
1258 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1259 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1262 /* Make sure we can access arbitrary call frames. */
1263 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1265 /* Base register for access to arguments of the function. */
1266 #define ARG_POINTER_REGNUM 16
1268 /* Register in which static-chain is passed to a function.
1269 We do use ECX as static chain register for 32 bit ABI. On the
1270 64bit ABI, ECX is an argument register, so we use R10 instead. */
1271 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? R10_REG : CX_REG)
1273 /* Register to hold the addressing base for position independent
1274 code access to data items. We don't use PIC pointer for 64bit
1275 mode. Define the regnum to dummy value to prevent gcc from
1276 pessimizing code dealing with EBX.
1278 To avoid clobbering a call-saved register unnecessarily, we renumber
1279 the pic register when possible. The change is visible after the
1280 prologue has been emitted. */
1282 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1284 #define PIC_OFFSET_TABLE_REGNUM \
1285 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \
1286 || !flag_pic ? INVALID_REGNUM \
1287 : reload_completed ? REGNO (pic_offset_table_rtx) \
1288 : REAL_PIC_OFFSET_TABLE_REGNUM)
1290 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1292 /* This is overridden by <cygwin.h>. */
1293 #define MS_AGGREGATE_RETURN 0
1295 /* This is overridden by <netware.h>. */
1296 #define KEEP_AGGREGATE_RETURN_POINTER 0
1298 /* Define the classes of registers for register constraints in the
1299 machine description. Also define ranges of constants.
1301 One of the classes must always be named ALL_REGS and include all hard regs.
1302 If there is more than one class, another class must be named NO_REGS
1303 and contain no registers.
1305 The name GENERAL_REGS must be the name of a class (or an alias for
1306 another name such as ALL_REGS). This is the class of registers
1307 that is allowed by "g" or "r" in a register constraint.
1308 Also, registers outside this class are allocated only when
1309 instructions express preferences for them.
1311 The classes must be numbered in nondecreasing order; that is,
1312 a larger-numbered class must never be contained completely
1313 in a smaller-numbered class.
1315 For any two classes, it is very desirable that there be another
1316 class that represents their union.
1318 It might seem that class BREG is unnecessary, since no useful 386
1319 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1320 and the "b" register constraint is useful in asms for syscalls.
1322 The flags, fpsr and fpcr registers are in no class. */
1327 AREG, DREG, CREG, BREG, SIREG, DIREG,
1328 AD_REGS, /* %eax/%edx for DImode */
1329 Q_REGS, /* %eax %ebx %ecx %edx */
1330 NON_Q_REGS, /* %esi %edi %ebp %esp */
1331 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1332 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1333 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1334 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1345 ALL_REGS, LIM_REG_CLASSES
1348 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1350 #define INTEGER_CLASS_P(CLASS) \
1351 reg_class_subset_p ((CLASS), GENERAL_REGS)
1352 #define FLOAT_CLASS_P(CLASS) \
1353 reg_class_subset_p ((CLASS), FLOAT_REGS)
1354 #define SSE_CLASS_P(CLASS) \
1355 reg_class_subset_p ((CLASS), SSE_REGS)
1356 #define MMX_CLASS_P(CLASS) \
1357 ((CLASS) == MMX_REGS)
1358 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1359 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1360 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1361 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1362 #define MAYBE_SSE_CLASS_P(CLASS) \
1363 reg_classes_intersect_p (SSE_REGS, (CLASS))
1364 #define MAYBE_MMX_CLASS_P(CLASS) \
1365 reg_classes_intersect_p (MMX_REGS, (CLASS))
1367 #define Q_CLASS_P(CLASS) \
1368 reg_class_subset_p ((CLASS), Q_REGS)
1370 /* Give names of register classes as strings for dump file. */
1372 #define REG_CLASS_NAMES \
1374 "AREG", "DREG", "CREG", "BREG", \
1377 "Q_REGS", "NON_Q_REGS", \
1381 "FP_TOP_REG", "FP_SECOND_REG", \
1386 "FP_TOP_SSE_REGS", \
1387 "FP_SECOND_SSE_REGS", \
1391 "FLOAT_INT_SSE_REGS", \
1394 /* Define which registers fit in which classes.
1395 This is an initializer for a vector of HARD_REG_SET
1396 of length N_REG_CLASSES. */
1398 #define REG_CLASS_CONTENTS \
1400 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1401 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1402 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1403 { 0x03, 0x0 }, /* AD_REGS */ \
1404 { 0x0f, 0x0 }, /* Q_REGS */ \
1405 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1406 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1407 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1408 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1409 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1410 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1411 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \
1412 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1413 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1414 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1415 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1416 { 0x1fe0ff00,0x3fe000 }, /* FLOAT_SSE_REGS */ \
1417 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1418 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1419 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1420 { 0xffffffff,0x1fffff } \
1423 /* The same information, inverted:
1424 Return the class number of the smallest class containing
1425 reg number REGNO. This could be a conditional expression
1426 or could index an array. */
1428 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1430 /* When defined, the compiler allows registers explicitly used in the
1431 rtl to be used as spill registers but prevents the compiler from
1432 extending the lifetime of these registers. */
1434 #define SMALL_REGISTER_CLASSES 1
1436 #define QI_REG_P(X) (REG_P (X) && REGNO (X) < 4)
1438 #define GENERAL_REGNO_P(N) \
1439 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N))
1441 #define GENERAL_REG_P(X) \
1442 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1444 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1446 #define REX_INT_REGNO_P(N) \
1447 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG)
1448 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1450 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1451 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1452 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1453 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1455 #define X87_FLOAT_MODE_P(MODE) \
1456 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode))
1458 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1459 #define SSE_REGNO_P(N) \
1460 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \
1461 || REX_SSE_REGNO_P (N))
1463 #define REX_SSE_REGNO_P(N) \
1464 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG)
1466 #define SSE_REGNO(N) \
1467 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1469 #define SSE_FLOAT_MODE_P(MODE) \
1470 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1472 #define SSE_VEC_FLOAT_MODE_P(MODE) \
1473 ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode))
1475 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1476 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
1478 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP)))
1479 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG)
1481 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1483 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1484 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1486 /* The class value for index registers, and the one for base regs. */
1488 #define INDEX_REG_CLASS INDEX_REGS
1489 #define BASE_REG_CLASS GENERAL_REGS
1491 /* Place additional restrictions on the register class to use when it
1492 is necessary to be able to hold a value of mode MODE in a reload
1493 register for which class CLASS would ordinarily be used. */
1495 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1496 ((MODE) == QImode && !TARGET_64BIT \
1497 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1498 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1501 /* Given an rtx X being reloaded into a reg required to be
1502 in class CLASS, return the class of reg to actually use.
1503 In general this is just CLASS; but on some machines
1504 in some cases it is preferable to use a more restrictive class.
1505 On the 80386 series, we prevent floating constants from being
1506 reloaded into floating registers (since no move-insn can do that)
1507 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1509 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1510 QImode must go into class Q_REGS.
1511 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1512 movdf to do mem-to-mem moves through integer regs. */
1514 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1515 ix86_preferred_reload_class ((X), (CLASS))
1517 /* Discourage putting floating-point values in SSE registers unless
1518 SSE math is being used, and likewise for the 387 registers. */
1520 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
1521 ix86_preferred_output_reload_class ((X), (CLASS))
1523 /* If we are copying between general and FP registers, we need a memory
1524 location. The same is true for SSE and MMX registers. */
1525 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1526 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1528 /* Get_secondary_mem widens integral modes to BITS_PER_WORD.
1529 There is no need to emit full 64 bit move on 64 bit targets
1530 for integral modes that can be moved using 32 bit move. */
1531 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1532 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \
1533 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1536 /* Return the maximum number of consecutive registers
1537 needed to represent mode MODE in a register of class CLASS. */
1538 /* On the 80386, this is the size of MODE in words,
1539 except in the FP regs, where a single reg is always enough. */
1540 #define CLASS_MAX_NREGS(CLASS, MODE) \
1541 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1542 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1543 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1544 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1546 /* A C expression whose value is nonzero if pseudos that have been
1547 assigned to registers of class CLASS would likely be spilled
1548 because registers of CLASS are needed for spill registers.
1550 The default value of this macro returns 1 if CLASS has exactly one
1551 register and zero otherwise. On most machines, this default
1552 should be used. Only define this macro to some other expression
1553 if pseudo allocated by `local-alloc.c' end up in memory because
1554 their hard registers were needed for spill registers. If this
1555 macro returns nonzero for those classes, those pseudos will only
1556 be allocated by `global.c', which knows how to reallocate the
1557 pseudo to another register. If there would not be another
1558 register available for reallocation, you should not change the
1559 definition of this macro since the only effect of such a
1560 definition would be to slow down register allocation. */
1562 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1563 (((CLASS) == AREG) \
1564 || ((CLASS) == DREG) \
1565 || ((CLASS) == CREG) \
1566 || ((CLASS) == BREG) \
1567 || ((CLASS) == AD_REGS) \
1568 || ((CLASS) == SIREG) \
1569 || ((CLASS) == DIREG) \
1570 || ((CLASS) == FP_TOP_REG) \
1571 || ((CLASS) == FP_SECOND_REG))
1573 /* Return a class of registers that cannot change FROM mode to TO mode. */
1575 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1576 ix86_cannot_change_mode_class (FROM, TO, CLASS)
1578 /* Stack layout; function entry, exit and calling. */
1580 /* Define this if pushing a word on the stack
1581 makes the stack pointer a smaller address. */
1582 #define STACK_GROWS_DOWNWARD
1584 /* Define this to nonzero if the nominal address of the stack frame
1585 is at the high-address end of the local variables;
1586 that is, each additional local variable allocated
1587 goes at a more negative offset in the frame. */
1588 #define FRAME_GROWS_DOWNWARD 1
1590 /* Offset within stack frame to start allocating local variables at.
1591 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1592 first local allocated. Otherwise, it is the offset to the BEGINNING
1593 of the first local allocated. */
1594 #define STARTING_FRAME_OFFSET 0
1596 /* If we generate an insn to push BYTES bytes,
1597 this says how many the stack pointer really advances by.
1598 On 386, we have pushw instruction that decrements by exactly 2 no
1599 matter what the position was, there is no pushb.
1600 But as CIE data alignment factor on this arch is -4, we need to make
1601 sure all stack pointer adjustments are in multiple of 4.
1603 For 64bit ABI we round up to 8 bytes.
1606 #define PUSH_ROUNDING(BYTES) \
1608 ? (((BYTES) + 7) & (-8)) \
1609 : (((BYTES) + 3) & (-4)))
1611 /* If defined, the maximum amount of space required for outgoing arguments will
1612 be computed and placed into the variable
1613 `crtl->outgoing_args_size'. No space will be pushed onto the
1614 stack for each call; instead, the function prologue should increase the stack
1615 frame size by this amount. */
1617 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1619 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1620 instructions to pass outgoing arguments. */
1622 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1624 /* We want the stack and args grow in opposite directions, even if
1626 #define PUSH_ARGS_REVERSED 1
1628 /* Offset of first parameter from the argument pointer register value. */
1629 #define FIRST_PARM_OFFSET(FNDECL) 0
1631 /* Define this macro if functions should assume that stack space has been
1632 allocated for arguments even when their values are passed in registers.
1634 The value of this macro is the size, in bytes, of the area reserved for
1635 arguments passed in registers for the function represented by FNDECL.
1637 This space can be allocated by the caller, or be a part of the
1638 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1640 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL)
1642 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) (ix86_function_type_abi (FNTYPE) == MS_ABI ? 1 : 0)
1644 /* Value is the number of bytes of arguments automatically
1645 popped when returning from a subroutine call.
1646 FUNDECL is the declaration node of the function (as a tree),
1647 FUNTYPE is the data type of the function (as a tree),
1648 or for a library call it is an identifier node for the subroutine name.
1649 SIZE is the number of bytes of arguments passed on the stack.
1651 On the 80386, the RTD insn may be used to pop them if the number
1652 of args is fixed, but if the number is variable then the caller
1653 must pop them all. RTD can't be used for library calls now
1654 because the library is compiled with the Unix compiler.
1655 Use of RTD is a selectable option, since it is incompatible with
1656 standard Unix calling sequences. If the option is not selected,
1657 the caller must always pop the args.
1659 The attribute stdcall is equivalent to RTD on a per module basis. */
1661 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1662 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1664 #define FUNCTION_VALUE_REGNO_P(N) \
1665 ix86_function_value_regno_p (N)
1667 /* Define how to find the value returned by a library function
1668 assuming the value has mode MODE. */
1670 #define LIBCALL_VALUE(MODE) \
1671 ix86_libcall_value (MODE)
1673 /* Define the size of the result block used for communication between
1674 untyped_call and untyped_return. The block contains a DImode value
1675 followed by the block used by fnsave and frstor. */
1677 #define APPLY_RESULT_SIZE (8+108)
1679 /* 1 if N is a possible register number for function argument passing. */
1680 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1682 /* Define a data type for recording info about an argument list
1683 during the scan of that argument list. This data type should
1684 hold all necessary information about the function itself
1685 and about the args processed so far, enough to enable macros
1686 such as FUNCTION_ARG to determine where the next arg should go. */
1688 typedef struct ix86_args {
1689 int words; /* # words passed so far */
1690 int nregs; /* # registers available for passing */
1691 int regno; /* next available register number */
1692 int fastcall; /* fastcall calling convention is used */
1693 int sse_words; /* # sse words passed so far */
1694 int sse_nregs; /* # sse registers available for passing */
1695 int warn_sse; /* True when we want to warn about SSE ABI. */
1696 int warn_mmx; /* True when we want to warn about MMX ABI. */
1697 int sse_regno; /* next available sse register number */
1698 int mmx_words; /* # mmx words passed so far */
1699 int mmx_nregs; /* # mmx registers available for passing */
1700 int mmx_regno; /* next available mmx register number */
1701 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1702 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
1703 be passed in SSE registers. Otherwise 0. */
1704 int call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
1705 MS_ABI for ms abi. */
1708 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1709 for a call to a function whose data type is FNTYPE.
1710 For a library call, FNTYPE is 0. */
1712 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1713 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1715 /* Update the data in CUM to advance over an argument
1716 of mode MODE and data type TYPE.
1717 (TYPE is null for libcalls where that information may not be available.) */
1719 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1720 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1722 /* Define where to put the arguments to a function.
1723 Value is zero to push the argument on the stack,
1724 or a hard register in which to store the argument.
1726 MODE is the argument's machine mode.
1727 TYPE is the data type of the argument (as a tree).
1728 This is null for libcalls where that information may
1730 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1731 the preceding args and about the function being called.
1732 NAMED is nonzero if this argument is a named parameter
1733 (otherwise it is an extra parameter matching an ellipsis). */
1735 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1736 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1738 #define TARGET_ASM_FILE_END ix86_file_end
1739 #define NEED_INDICATE_EXEC_STACK 0
1741 /* Output assembler code to FILE to increment profiler label # LABELNO
1742 for profiling a function entry. */
1744 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1746 #define MCOUNT_NAME "_mcount"
1748 #define PROFILE_COUNT_REGISTER "edx"
1750 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1751 the stack pointer does not matter. The value is tested only in
1752 functions that have frame pointers.
1753 No definition is equivalent to always zero. */
1754 /* Note on the 386 it might be more efficient not to define this since
1755 we have to restore it ourselves from the frame pointer, in order to
1758 #define EXIT_IGNORE_STACK 1
1760 /* Output assembler code for a block containing the constant parts
1761 of a trampoline, leaving space for the variable parts. */
1763 /* On the 386, the trampoline contains two instructions:
1766 The trampoline is generated entirely at runtime. The operand of JMP
1767 is the address of FUNCTION relative to the instruction following the
1768 JMP (which is 5 bytes long). */
1770 /* Length in units of the trampoline for entering a nested function. */
1772 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1774 /* Emit RTL insns to initialize the variable parts of a trampoline.
1775 FNADDR is an RTX for the address of the function's pure code.
1776 CXT is an RTX for the static chain value for the function. */
1778 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1779 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1781 /* Definitions for register eliminations.
1783 This is an array of structures. Each structure initializes one pair
1784 of eliminable registers. The "from" register number is given first,
1785 followed by "to". Eliminations of the same "from" register are listed
1786 in order of preference.
1788 There are two registers that can always be eliminated on the i386.
1789 The frame pointer and the arg pointer can be replaced by either the
1790 hard frame pointer or to the stack pointer, depending upon the
1791 circumstances. The hard frame pointer is not used before reload and
1792 so it is not eligible for elimination. */
1794 #define ELIMINABLE_REGS \
1795 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1796 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1797 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1798 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1800 /* Given FROM and TO register numbers, say whether this elimination is
1801 allowed. Frame pointer elimination is automatically handled.
1803 All other eliminations are valid. */
1805 #define CAN_ELIMINATE(FROM, TO) \
1806 ((TO) == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1)
1808 /* Define the offset between two registers, one to be eliminated, and the other
1809 its replacement, at the start of a routine. */
1811 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1812 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1814 /* Addressing modes, and classification of registers for them. */
1816 /* Macros to check register numbers against specific register classes. */
1818 /* These assume that REGNO is a hard or pseudo reg number.
1819 They give nonzero only if REGNO is a hard reg of the suitable class
1820 or a pseudo reg currently allocated to a suitable hard reg.
1821 Since they use reg_renumber, they are safe only once reg_renumber
1822 has been allocated, which happens in local-alloc.c. */
1824 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1825 ((REGNO) < STACK_POINTER_REGNUM \
1826 || REX_INT_REGNO_P (REGNO) \
1827 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \
1828 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1830 #define REGNO_OK_FOR_BASE_P(REGNO) \
1831 (GENERAL_REGNO_P (REGNO) \
1832 || (REGNO) == ARG_POINTER_REGNUM \
1833 || (REGNO) == FRAME_POINTER_REGNUM \
1834 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)]))
1836 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1837 and check its validity for a certain class.
1838 We have two alternate definitions for each of them.
1839 The usual definition accepts all pseudo regs; the other rejects
1840 them unless they have been allocated suitable hard regs.
1841 The symbol REG_OK_STRICT causes the latter definition to be used.
1843 Most source files want to accept pseudo regs in the hope that
1844 they will get allocated to the class that the insn wants them to be in.
1845 Source files for reload pass need to be strict.
1846 After reload, it makes no difference, since pseudo regs have
1847 been eliminated by then. */
1850 /* Non strict versions, pseudos are ok. */
1851 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1852 (REGNO (X) < STACK_POINTER_REGNUM \
1853 || REX_INT_REGNO_P (REGNO (X)) \
1854 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1856 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1857 (GENERAL_REGNO_P (REGNO (X)) \
1858 || REGNO (X) == ARG_POINTER_REGNUM \
1859 || REGNO (X) == FRAME_POINTER_REGNUM \
1860 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1862 /* Strict versions, hard registers only */
1863 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1864 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1866 #ifndef REG_OK_STRICT
1867 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1868 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1871 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1872 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1875 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1876 that is a valid memory address for an instruction.
1877 The MODE argument is the machine mode for the MEM expression
1878 that wants to use this address.
1880 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1881 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1883 See legitimize_pic_address in i386.c for details as to what
1884 constitutes a legitimate address when -fpic is used. */
1886 #define MAX_REGS_PER_ADDRESS 2
1888 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1890 /* Nonzero if the constant value X is a legitimate general operand.
1891 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1893 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1895 #ifdef REG_OK_STRICT
1896 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1898 if (legitimate_address_p ((MODE), (X), 1)) \
1903 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1905 if (legitimate_address_p ((MODE), (X), 0)) \
1911 /* If defined, a C expression to determine the base term of address X.
1912 This macro is used in only one place: `find_base_term' in alias.c.
1914 It is always safe for this macro to not be defined. It exists so
1915 that alias analysis can understand machine-dependent addresses.
1917 The typical use of this macro is to handle addresses containing
1918 a label_ref or symbol_ref within an UNSPEC. */
1920 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1922 /* Try machine-dependent ways of modifying an illegitimate address
1923 to be legitimate. If we find one, return the new, valid address.
1924 This macro is used in only one place: `memory_address' in explow.c.
1926 OLDX is the address as it was before break_out_memory_refs was called.
1927 In some cases it is useful to look at this to decide what needs to be done.
1929 MODE and WIN are passed so that this macro can use
1930 GO_IF_LEGITIMATE_ADDRESS.
1932 It is always safe for this macro to do nothing. It exists to recognize
1933 opportunities to optimize the output.
1935 For the 80386, we handle X+REG by loading X into a register R and
1936 using R+REG. R will go in a general reg and indexing will be used.
1937 However, if REG is a broken-out memory address or multiplication,
1938 nothing needs to be done because REG can certainly go in a general reg.
1940 When -fpic is used, special handling is needed for symbolic references.
1941 See comments by legitimize_pic_address in i386.c for details. */
1943 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1945 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1946 if (memory_address_p ((MODE), (X))) \
1950 /* Nonzero if the constant value X is a legitimate general operand
1951 when generating PIC code. It is given that flag_pic is on and
1952 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1954 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1956 #define SYMBOLIC_CONST(X) \
1957 (GET_CODE (X) == SYMBOL_REF \
1958 || GET_CODE (X) == LABEL_REF \
1959 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1961 /* Go to LABEL if ADDR (a legitimate address expression)
1962 has an effect that depends on the machine mode it is used for.
1963 On the 80386, only postdecrement and postincrement address depend thus
1964 (the amount of decrement or increment being the length of the operand).
1965 These are now caught in recog.c. */
1966 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
1968 /* Max number of args passed in registers. If this is more than 3, we will
1969 have problems with ebx (register #4), since it is a caller save register and
1970 is also used as the pic register in ELF. So for now, don't allow more than
1971 3 registers to be passed in registers. */
1973 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */
1974 #define X86_64_REGPARM_MAX 6
1975 #define X64_REGPARM_MAX 4
1976 #define X86_32_REGPARM_MAX 3
1978 #define X86_64_SSE_REGPARM_MAX 8
1979 #define X64_SSE_REGPARM_MAX 4
1980 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? 3 : 0)
1982 #define REGPARM_MAX (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_REGPARM_MAX \
1983 : X86_64_REGPARM_MAX) \
1984 : X86_32_REGPARM_MAX)
1986 #define SSE_REGPARM_MAX (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X64_SSE_REGPARM_MAX \
1987 : X86_64_SSE_REGPARM_MAX) \
1988 : X86_32_SSE_REGPARM_MAX)
1990 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
1993 /* Specify the machine mode that this machine uses
1994 for the index in the tablejump instruction. */
1995 #define CASE_VECTOR_MODE \
1996 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode)
1998 /* Define this as 1 if `char' should by default be signed; else as 0. */
1999 #define DEFAULT_SIGNED_CHAR 1
2001 /* Max number of bytes we can move from memory to memory
2002 in one reasonably fast instruction. */
2005 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2006 move efficiently, as opposed to MOVE_MAX which is the maximum
2007 number of bytes we can move with a single instruction. */
2008 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2010 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2011 move-instruction pairs, we will do a movmem or libcall instead.
2012 Increasing the value will always make code faster, but eventually
2013 incurs high cost in increased code size.
2015 If you don't define this, a reasonable default is used. */
2017 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2019 /* If a clear memory operation would take CLEAR_RATIO or more simple
2020 move-instruction sequences, we will do a clrmem or libcall instead. */
2022 #define CLEAR_RATIO (optimize_size ? 2 : MIN (6, ix86_cost->move_ratio))
2024 /* Define if shifts truncate the shift count
2025 which implies one can omit a sign-extension or zero-extension
2026 of a shift count. */
2027 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2029 /* #define SHIFT_COUNT_TRUNCATED */
2031 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2032 is done just by pretending it is already truncated. */
2033 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2035 /* A macro to update M and UNSIGNEDP when an object whose type is
2036 TYPE and which has the specified mode and signedness is to be
2037 stored in a register. This macro is only called when TYPE is a
2040 On i386 it is sometimes useful to promote HImode and QImode
2041 quantities to SImode. The choice depends on target type. */
2043 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2045 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2046 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2050 /* Specify the machine mode that pointers have.
2051 After generation of rtl, the compiler makes no further distinction
2052 between pointers and any other objects of this machine mode. */
2053 #define Pmode (TARGET_64BIT ? DImode : SImode)
2055 /* A function address in a call instruction
2056 is a byte address (for indexing purposes)
2057 so give the MEM rtx a byte's mode. */
2058 #define FUNCTION_MODE QImode
2060 /* A C expression for the cost of moving data from a register in class FROM to
2061 one in class TO. The classes are expressed using the enumeration values
2062 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2063 interpreted relative to that.
2065 It is not required that the cost always equal 2 when FROM is the same as TO;
2066 on some machines it is expensive to move between registers if they are not
2067 general registers. */
2069 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2070 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2072 /* A C expression for the cost of moving data of mode M between a
2073 register and memory. A value of 2 is the default; this cost is
2074 relative to those in `REGISTER_MOVE_COST'.
2076 If moving between registers and memory is more expensive than
2077 between two registers, you should define this macro to express the
2080 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2081 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2083 /* A C expression for the cost of a branch instruction. A value of 1
2084 is the default; other values are interpreted relative to that. */
2086 #define BRANCH_COST ix86_branch_cost
2088 /* Define this macro as a C expression which is nonzero if accessing
2089 less than a word of memory (i.e. a `char' or a `short') is no
2090 faster than accessing a word of memory, i.e., if such access
2091 require more than one instruction or if there is no difference in
2092 cost between byte and (aligned) word loads.
2094 When this macro is not defined, the compiler will access a field by
2095 finding the smallest containing object; when it is defined, a
2096 fullword load will be used if alignment permits. Unless bytes
2097 accesses are faster than word accesses, using word accesses is
2098 preferable since it may eliminate subsequent memory access if
2099 subsequent accesses occur to other fields in the same word of the
2100 structure, but to different bytes. */
2102 #define SLOW_BYTE_ACCESS 0
2104 /* Nonzero if access to memory by shorts is slow and undesirable. */
2105 #define SLOW_SHORT_ACCESS 0
2107 /* Define this macro to be the value 1 if unaligned accesses have a
2108 cost many times greater than aligned accesses, for example if they
2109 are emulated in a trap handler.
2111 When this macro is nonzero, the compiler will act as if
2112 `STRICT_ALIGNMENT' were nonzero when generating code for block
2113 moves. This can cause significantly more instructions to be
2114 produced. Therefore, do not set this macro nonzero if unaligned
2115 accesses only add a cycle or two to the time for a memory access.
2117 If the value of this macro is always zero, it need not be defined. */
2119 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2121 /* Define this macro if it is as good or better to call a constant
2122 function address than to call an address kept in a register.
2124 Desirable on the 386 because a CALL with a constant address is
2125 faster than one with a register address. */
2127 #define NO_FUNCTION_CSE
2129 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2130 return the mode to be used for the comparison.
2132 For floating-point equality comparisons, CCFPEQmode should be used.
2133 VOIDmode should be used in all other cases.
2135 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2136 possible, to allow for more combinations. */
2138 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2140 /* Return nonzero if MODE implies a floating point inequality can be
2143 #define REVERSIBLE_CC_MODE(MODE) 1
2145 /* A C expression whose value is reversed condition code of the CODE for
2146 comparison done in CC_MODE mode. */
2147 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2150 /* Control the assembler format that we output, to the extent
2151 this does not vary between assemblers. */
2153 /* How to refer to registers in assembler output.
2154 This sequence is indexed by compiler's hard-register-number (see above). */
2156 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e".
2157 For non floating point regs, the following are the HImode names.
2159 For float regs, the stack top is sometimes referred to as "%st(0)"
2160 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2162 #define HI_REGISTER_NAMES \
2163 {"ax","dx","cx","bx","si","di","bp","sp", \
2164 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2165 "argp", "flags", "fpsr", "fpcr", "frame", \
2166 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2167 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
2168 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2169 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2171 #define REGISTER_NAMES HI_REGISTER_NAMES
2173 /* Table of additional register names to use in user input. */
2175 #define ADDITIONAL_REGISTER_NAMES \
2176 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2177 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2178 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2179 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2180 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2181 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } }
2183 /* Note we are omitting these since currently I don't know how
2184 to get gcc to use these, since they want the same but different
2185 number as al, and ax.
2188 #define QI_REGISTER_NAMES \
2189 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2191 /* These parallel the array above, and can be used to access bits 8:15
2192 of regs 0 through 3. */
2194 #define QI_HIGH_REGISTER_NAMES \
2195 {"ah", "dh", "ch", "bh", }
2197 /* How to renumber registers for dbx and gdb. */
2199 #define DBX_REGISTER_NUMBER(N) \
2200 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2202 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2203 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2204 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2206 /* Before the prologue, RA is at 0(%esp). */
2207 #define INCOMING_RETURN_ADDR_RTX \
2208 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2210 /* After the prologue, RA is at -4(AP) in the current frame. */
2211 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2213 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2214 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2216 /* PC is dbx register 8; let's use that column for RA. */
2217 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2219 /* Before the prologue, the top of the frame is at 4(%esp). */
2220 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2222 /* Describe how we implement __builtin_eh_return. */
2223 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2224 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2227 /* Select a format to encode pointers in exception handling data. CODE
2228 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2229 true if the symbol may be affected by dynamic relocations.
2231 ??? All x86 object file formats are capable of representing this.
2232 After all, the relocation needed is the same as for the call insn.
2233 Whether or not a particular assembler allows us to enter such, I
2234 guess we'll have to see. */
2235 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2236 asm_preferred_eh_data_format ((CODE), (GLOBAL))
2238 /* This is how to output an insn to push a register on the stack.
2239 It need not be very fast code. */
2241 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2244 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2245 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2247 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2250 /* This is how to output an insn to pop a register from the stack.
2251 It need not be very fast code. */
2253 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2256 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2257 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2259 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2262 /* This is how to output an element of a case-vector that is absolute. */
2264 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2265 ix86_output_addr_vec_elt ((FILE), (VALUE))
2267 /* This is how to output an element of a case-vector that is relative. */
2269 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2270 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2272 /* Under some conditions we need jump tables in the text section,
2273 because the assembler cannot handle label differences between
2274 sections. This is the case for x86_64 on Mach-O for example. */
2276 #define JUMP_TABLES_IN_TEXT_SECTION \
2277 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \
2278 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA)))
2280 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2281 and switch back. For x86 we do this only to save a few bytes that
2282 would otherwise be unused in the text section. */
2283 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2284 asm (SECTION_OP "\n\t" \
2285 "call " USER_LABEL_PREFIX #FUNC "\n" \
2286 TEXT_SECTION_ASM_OP);
2288 /* Print operand X (an rtx) in assembler syntax to file FILE.
2289 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2290 Effect of various CODE letters is described in i386.c near
2291 print_operand function. */
2293 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2294 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';')
2296 #define PRINT_OPERAND(FILE, X, CODE) \
2297 print_operand ((FILE), (X), (CODE))
2299 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2300 print_operand_address ((FILE), (ADDR))
2302 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2304 if (! output_addr_const_extra (FILE, (X))) \
2308 /* Which processor to schedule for. The cpu attribute defines a list that
2309 mirrors this list, so changes to i386.md must be made at the same time. */
2313 PROCESSOR_I386 = 0, /* 80386 */
2314 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2316 PROCESSOR_PENTIUMPRO,
2324 PROCESSOR_GENERIC32,
2325 PROCESSOR_GENERIC64,
2330 extern enum processor_type ix86_tune;
2331 extern enum processor_type ix86_arch;
2339 extern enum fpmath_unit ix86_fpmath;
2348 extern enum tls_dialect ix86_tls_dialect;
2351 CM_32, /* The traditional 32-bit ABI. */
2352 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2353 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2354 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2355 CM_LARGE, /* No assumptions. */
2356 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */
2357 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */
2358 CM_LARGE_PIC /* No assumptions. */
2361 extern enum cmodel ix86_cmodel;
2363 /* Size of the RED_ZONE area. */
2364 #define RED_ZONE_SIZE 128
2365 /* Reserved area of the red zone for temporaries. */
2366 #define RED_ZONE_RESERVE 8
2373 extern enum asm_dialect ix86_asm_dialect;
2374 extern unsigned int ix86_preferred_stack_boundary;
2375 extern int ix86_branch_cost, ix86_section_threshold;
2377 /* Smallest class containing REGNO. */
2378 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
2380 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
2381 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
2382 extern rtx ix86_compare_emitted;
2384 /* To properly truncate FP values into integers, we need to set i387 control
2385 word. We can't emit proper mode switching code before reload, as spills
2386 generated by reload may truncate values incorrectly, but we still can avoid
2387 redundant computation of new control word by the mode switching pass.
2388 The fldcw instructions are still emitted redundantly, but this is probably
2389 not going to be noticeable problem, as most CPUs do have fast path for
2392 The machinery is to emit simple truncation instructions and split them
2393 before reload to instructions having USEs of two memory locations that
2394 are filled by this code to old and new control word.
2396 Post-reload pass may be later used to eliminate the redundant fildcw if
2408 enum ix86_stack_slot
2417 MAX_386_STACK_LOCALS
2420 /* Define this macro if the port needs extra instructions inserted
2421 for mode switching in an optimizing compilation. */
2423 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
2424 ix86_optimize_mode_switching[(ENTITY)]
2426 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
2427 initializer for an array of integers. Each initializer element N
2428 refers to an entity that needs mode switching, and specifies the
2429 number of different modes that might need to be set for this
2430 entity. The position of the initializer in the initializer -
2431 starting counting at zero - determines the integer that is used to
2432 refer to the mode-switched entity in question. */
2434 #define NUM_MODES_FOR_MODE_SWITCHING \
2435 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY }
2437 /* ENTITY is an integer specifying a mode-switched entity. If
2438 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
2439 return an integer value not larger than the corresponding element
2440 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
2441 must be switched into prior to the execution of INSN. */
2443 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I))
2445 /* This macro specifies the order in which modes for ENTITY are
2446 processed. 0 is the highest priority. */
2448 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
2450 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
2451 is the set of hard registers live at the point where the insn(s)
2452 are to be inserted. */
2454 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2455 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
2456 ? emit_i387_cw_initialization (MODE), 0 \
2460 /* Avoid renaming of stack registers, as doing so in combination with
2461 scheduling just increases amount of live registers at time and in
2462 the turn amount of fxch instructions needed.
2464 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
2466 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
2467 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG))
2470 #define FASTCALL_PREFIX '@'
2472 struct machine_function GTY(())
2474 struct stack_local_entry *stack_locals;
2475 const char *some_ld_name;
2476 rtx force_align_arg_pointer;
2477 int save_varrargs_registers;
2478 int accesses_prev_frame;
2479 int optimize_mode_switching[MAX_386_ENTITIES];
2481 /* Set by ix86_compute_frame_layout and used by prologue/epilogue
2482 expander to determine the style used. */
2483 int use_fast_prologue_epilogue;
2484 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
2486 int use_fast_prologue_epilogue_nregs;
2487 /* If true, the current function needs the default PIC register, not
2488 an alternate register (on x86) and must not use the red zone (on
2489 x86_64), even if it's a leaf function. We don't want the
2490 function to be regarded as non-leaf because TLS calls need not
2491 affect register allocation. This flag is set when a TLS call
2492 instruction is expanded within a function, and never reset, even
2493 if all such instructions are optimized away. Use the
2494 ix86_current_function_calls_tls_descriptor macro for a better
2496 int tls_descriptor_call_expanded_p;
2497 /* This value is used for amd64 targets and specifies the current abi
2498 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
2502 #define ix86_stack_locals (cfun->machine->stack_locals)
2503 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
2504 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
2505 #define ix86_current_function_needs_cld (cfun->machine->needs_cld)
2506 #define ix86_tls_descriptor_calls_expanded_in_cfun \
2507 (cfun->machine->tls_descriptor_call_expanded_p)
2508 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS
2509 calls are optimized away, we try to detect cases in which it was
2510 optimized away. Since such instructions (use (reg REG_SP)), we can
2511 verify whether there's any such instruction live by testing that
2513 #define ix86_current_function_calls_tls_descriptor \
2514 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG))
2516 /* Control behavior of x86_file_start. */
2517 #define X86_FILE_START_VERSION_DIRECTIVE false
2518 #define X86_FILE_START_FLTUSED false
2520 /* Flag to mark data that is in the large address area. */
2521 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0)
2522 #define SYMBOL_REF_FAR_ADDR_P(X) \
2523 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0)
2525 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to
2526 have defined always, to avoid ifdefing. */
2527 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1)
2528 #define SYMBOL_REF_DLLIMPORT_P(X) \
2529 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0)
2531 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2)
2532 #define SYMBOL_REF_DLLEXPORT_P(X) \
2533 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0)
2535 /* Model costs for vectorizer. */
2537 /* Cost of conditional branch. */
2538 #undef TARG_COND_BRANCH_COST
2539 #define TARG_COND_BRANCH_COST ix86_cost->branch_cost
2541 /* Cost of any scalar operation, excluding load and store. */
2542 #undef TARG_SCALAR_STMT_COST
2543 #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost
2545 /* Cost of scalar load. */
2546 #undef TARG_SCALAR_LOAD_COST
2547 #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost
2549 /* Cost of scalar store. */
2550 #undef TARG_SCALAR_STORE_COST
2551 #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost
2553 /* Cost of any vector operation, excluding load, store or vector to scalar
2555 #undef TARG_VEC_STMT_COST
2556 #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost
2558 /* Cost of vector to scalar operation. */
2559 #undef TARG_VEC_TO_SCALAR_COST
2560 #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost
2562 /* Cost of scalar to vector operation. */
2563 #undef TARG_SCALAR_TO_VEC_COST
2564 #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost
2566 /* Cost of aligned vector load. */
2567 #undef TARG_VEC_LOAD_COST
2568 #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost
2570 /* Cost of misaligned vector load. */
2571 #undef TARG_VEC_UNALIGNED_LOAD_COST
2572 #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost
2574 /* Cost of vector store. */
2575 #undef TARG_VEC_STORE_COST
2576 #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost
2578 /* Cost of conditional taken branch for vectorizer cost model. */
2579 #undef TARG_COND_TAKEN_BRANCH_COST
2580 #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost
2582 /* Cost of conditional not taken branch for vectorizer cost model. */
2583 #undef TARG_COND_NOT_TAKEN_BRANCH_COST
2584 #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost