1 /* Definitions of target machine for GCC for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Define the specific costs for a given cpu */
39 struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init[5]; /* cost of starting a multiply
45 in QImode, HImode, SImode, DImode, TImode*/
46 const int mult_bit; /* cost of multiply per each bit set */
47 const int divide[5]; /* cost of a divide/mod
48 in QImode, HImode, SImode, DImode, TImode*/
49 int movsx; /* The cost of movsx operation. */
50 int movzx; /* The cost of movzx operation. */
51 const int large_insn; /* insns larger than this cost more */
52 const int move_ratio; /* The threshold of number of scalar
53 memory-to-memory move insns. */
54 const int movzbl_load; /* cost of loading using movzbl */
55 const int int_load[3]; /* cost of loading integer registers
56 in QImode, HImode and SImode relative
57 to reg-reg move (2). */
58 const int int_store[3]; /* cost of storing integer register
59 in QImode, HImode and SImode */
60 const int fp_move; /* cost of reg,reg fld/fst */
61 const int fp_load[3]; /* cost of loading FP register
62 in SFmode, DFmode and XFmode */
63 const int fp_store[3]; /* cost of storing FP register
64 in SFmode, DFmode and XFmode */
65 const int mmx_move; /* cost of moving MMX register. */
66 const int mmx_load[2]; /* cost of loading MMX register
67 in SImode and DImode */
68 const int mmx_store[2]; /* cost of storing MMX register
69 in SImode and DImode */
70 const int sse_move; /* cost of moving SSE register. */
71 const int sse_load[3]; /* cost of loading SSE register
72 in SImode, DImode and TImode*/
73 const int sse_store[3]; /* cost of storing SSE register
74 in SImode, DImode and TImode*/
75 const int mmxsse_to_integer; /* cost of moving mmxsse register to
76 integer and vice versa. */
77 const int prefetch_block; /* bytes moved to cache for prefetch. */
78 const int simultaneous_prefetches; /* number of parallel prefetch
80 const int branch_cost; /* Default value for BRANCH_COST. */
81 const int fadd; /* cost of FADD and FSUB instructions. */
82 const int fmul; /* cost of FMUL instruction. */
83 const int fdiv; /* cost of FDIV instruction. */
84 const int fabs; /* cost of FABS instruction. */
85 const int fchs; /* cost of FCHS instruction. */
86 const int fsqrt; /* cost of FSQRT instruction. */
89 extern const struct processor_costs *ix86_cost;
91 /* Run-time compilation parameters selecting different hardware subsets. */
93 extern int target_flags;
95 /* Macros used in the machine description to test the flags. */
97 /* configure can arrange to make this 2, to force a 486. */
99 #ifndef TARGET_CPU_DEFAULT
100 #ifdef TARGET_64BIT_DEFAULT
101 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_k8
103 #define TARGET_CPU_DEFAULT 0
107 /* Masks for the -m switches */
108 #define MASK_80387 0x00000001 /* Hardware floating point */
109 #define MASK_RTD 0x00000002 /* Use ret that pops args */
110 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
111 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
112 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
113 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
114 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
115 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
116 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
117 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
118 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
119 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
120 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
121 #define MASK_MMX 0x00002000 /* Support MMX regs/builtins */
122 #define MASK_SSE 0x00004000 /* Support SSE regs/builtins */
123 #define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */
124 #define MASK_SSE3 0x00010000 /* Support SSE3 regs/builtins */
125 #define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */
126 #define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */
127 #define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
128 #define MASK_64BIT 0x00100000 /* Produce 64bit code */
129 #define MASK_MS_BITFIELD_LAYOUT 0x00200000 /* Use native (MS) bitfield layout */
130 #define MASK_TLS_DIRECT_SEG_REFS 0x00400000 /* Avoid adding %gs:0 */
132 /* Unused: 0x03e0000 */
134 /* ... overlap with subtarget options starts by 0x04000000. */
135 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
137 /* Use the floating point instructions */
138 #define TARGET_80387 (target_flags & MASK_80387)
140 /* Compile using ret insn that pops args.
141 This will not work unless you use prototypes at least
142 for all functions that can take varying numbers of args. */
143 #define TARGET_RTD (target_flags & MASK_RTD)
145 /* Align doubles to a two word boundary. This breaks compatibility with
146 the published ABI's for structures containing doubles, but produces
147 faster code on the pentium. */
148 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
150 /* Use push instructions to save outgoing args. */
151 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
153 /* Accumulate stack adjustments to prologue/epilogue. */
154 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
155 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
157 /* Put uninitialized locals into bss, not data.
158 Meaningful only on svr3. */
159 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
161 /* Use IEEE floating point comparisons. These handle correctly the cases
162 where the result of a comparison is unordered. Normally SIGFPE is
163 generated in such cases, in which case this isn't needed. */
164 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
166 /* Functions that return a floating point value may return that value
167 in the 387 FPU or in 386 integer registers. If set, this flag causes
168 the 387 to be used, which is compatible with most calling conventions. */
169 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
171 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
172 This mode wastes cache, but avoid misaligned data accesses and simplifies
173 address calculations. */
174 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
176 /* Disable generation of FP sin, cos and sqrt operations for 387.
177 This is because FreeBSD lacks these in the math-emulator-code */
178 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
180 /* Don't create frame pointers for leaf functions */
181 #define TARGET_OMIT_LEAF_FRAME_POINTER \
182 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
184 /* Debug GO_IF_LEGITIMATE_ADDRESS */
185 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
187 /* Debug FUNCTION_ARG macros */
188 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
190 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
191 compile-time constant. */
194 #define TARGET_64BIT 1
196 #define TARGET_64BIT 0
199 #ifdef TARGET_BI_ARCH
200 #define TARGET_64BIT (target_flags & MASK_64BIT)
202 #if TARGET_64BIT_DEFAULT
203 #define TARGET_64BIT 1
205 #define TARGET_64BIT 0
210 #define HAS_LONG_COND_BRANCH 1
211 #define HAS_LONG_UNCOND_BRANCH 1
213 /* Avoid adding %gs:0 in TLS references; use %gs:address directly. */
214 #define TARGET_TLS_DIRECT_SEG_REFS (target_flags & MASK_TLS_DIRECT_SEG_REFS)
216 #define TARGET_386 (ix86_tune == PROCESSOR_I386)
217 #define TARGET_486 (ix86_tune == PROCESSOR_I486)
218 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)
219 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)
220 #define TARGET_K6 (ix86_tune == PROCESSOR_K6)
221 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)
222 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
223 #define TARGET_K8 (ix86_tune == PROCESSOR_K8)
224 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
225 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
227 #define TUNEMASK (1 << ix86_tune)
228 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
229 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
230 extern const int x86_branch_hints, x86_unroll_strlen;
231 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
232 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
233 extern const int x86_use_cltd, x86_read_modify_write;
234 extern const int x86_read_modify, x86_split_long_moves;
235 extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
236 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
237 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
238 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
239 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
240 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
241 extern const int x86_epilogue_using_move, x86_decompose_lea;
242 extern const int x86_arch_always_fancy_math_387, x86_shift1;
243 extern const int x86_sse_partial_reg_dependency, x86_sse_partial_regs;
244 extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
245 extern const int x86_use_ffreep, x86_sse_partial_regs_for_cvtsd2ss;
246 extern const int x86_inter_unit_moves;
247 extern int x86_prefetch_sse;
249 #define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
250 #define TARGET_PUSH_MEMORY (x86_push_memory & TUNEMASK)
251 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & TUNEMASK)
252 #define TARGET_USE_BIT_TEST (x86_use_bit_test & TUNEMASK)
253 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & TUNEMASK)
254 /* For sane SSE instruction set generation we need fcomi instruction. It is
255 safe to enable all CMOVE instructions. */
256 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
257 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
258 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
259 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
260 #define TARGET_USE_SAHF ((x86_use_sahf & TUNEMASK) && !TARGET_64BIT)
261 #define TARGET_MOVX (x86_movx & TUNEMASK)
262 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & TUNEMASK)
263 #define TARGET_USE_LOOP (x86_use_loop & TUNEMASK)
264 #define TARGET_USE_FIOP (x86_use_fiop & TUNEMASK)
265 #define TARGET_USE_MOV0 (x86_use_mov0 & TUNEMASK)
266 #define TARGET_USE_CLTD (x86_use_cltd & TUNEMASK)
267 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & TUNEMASK)
268 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & TUNEMASK)
269 #define TARGET_READ_MODIFY (x86_read_modify & TUNEMASK)
270 #define TARGET_PROMOTE_QImode (x86_promote_QImode & TUNEMASK)
271 #define TARGET_FAST_PREFIX (x86_fast_prefix & TUNEMASK)
272 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & TUNEMASK)
273 #define TARGET_QIMODE_MATH (x86_qimode_math & TUNEMASK)
274 #define TARGET_HIMODE_MATH (x86_himode_math & TUNEMASK)
275 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & TUNEMASK)
276 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & TUNEMASK)
277 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & TUNEMASK)
278 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & TUNEMASK)
279 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & TUNEMASK)
280 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & TUNEMASK)
281 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & TUNEMASK)
282 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
283 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
284 (x86_sse_partial_reg_dependency & TUNEMASK)
285 #define TARGET_SSE_PARTIAL_REGS (x86_sse_partial_regs & TUNEMASK)
286 #define TARGET_SSE_PARTIAL_REGS_FOR_CVTSD2SS \
287 (x86_sse_partial_regs_for_cvtsd2ss & TUNEMASK)
288 #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
289 #define TARGET_SSE_TYPELESS_LOAD0 (x86_sse_typeless_load0 & TUNEMASK)
290 #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
291 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
292 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & TUNEMASK)
293 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & TUNEMASK)
294 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & TUNEMASK)
295 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
296 #define TARGET_SHIFT1 (x86_shift1 & TUNEMASK)
297 #define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
298 #define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
299 #define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
300 #define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
302 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
304 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
305 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
307 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
309 #define TARGET_SSE ((target_flags & MASK_SSE) != 0)
310 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
311 #define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0)
312 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
313 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
314 && (ix86_fpmath & FPMATH_387))
315 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
316 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
317 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
319 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
321 #define TARGET_USE_MS_BITFIELD_LAYOUT (target_flags & MASK_MS_BITFIELD_LAYOUT)
323 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
324 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
326 /* WARNING: Do not mark empty strings for translation, as calling
327 gettext on an empty string does NOT return an empty
331 #define TARGET_SWITCHES \
332 { { "80387", MASK_80387, N_("Use hardware fp") }, \
333 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
334 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
335 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
336 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
337 { "386", 0, "" /*Deprecated.*/}, \
338 { "486", 0, "" /*Deprecated.*/}, \
339 { "pentium", 0, "" /*Deprecated.*/}, \
340 { "pentiumpro", 0, "" /*Deprecated.*/}, \
341 { "intel-syntax", 0, "" /*Deprecated.*/}, \
342 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
344 N_("Alternate calling convention") }, \
345 { "no-rtd", -MASK_RTD, \
346 N_("Use normal calling convention") }, \
347 { "align-double", MASK_ALIGN_DOUBLE, \
348 N_("Align some doubles on dword boundary") }, \
349 { "no-align-double", -MASK_ALIGN_DOUBLE, \
350 N_("Align doubles on word boundary") }, \
351 { "svr3-shlib", MASK_SVR3_SHLIB, \
352 N_("Uninitialized locals in .bss") }, \
353 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
354 N_("Uninitialized locals in .data") }, \
355 { "ieee-fp", MASK_IEEE_FP, \
356 N_("Use IEEE math for fp comparisons") }, \
357 { "no-ieee-fp", -MASK_IEEE_FP, \
358 N_("Do not use IEEE math for fp comparisons") }, \
359 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
360 N_("Return values of functions in FPU registers") }, \
361 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
362 N_("Do not return values of functions in FPU registers")}, \
363 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
364 N_("Do not generate sin, cos, sqrt for FPU") }, \
365 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
366 N_("Generate sin, cos, sqrt for FPU")}, \
367 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
368 N_("Omit the frame pointer in leaf functions") }, \
369 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
370 { "stack-arg-probe", MASK_STACK_PROBE, \
371 N_("Enable stack probing") }, \
372 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
373 { "windows", 0, 0 /* undocumented */ }, \
374 { "dll", 0, 0 /* undocumented */ }, \
375 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
376 N_("Align destination of the string operations") }, \
377 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
378 N_("Do not align destination of the string operations") }, \
379 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
380 N_("Inline all known string operations") }, \
381 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
382 N_("Do not inline all known string operations") }, \
383 { "push-args", -MASK_NO_PUSH_ARGS, \
384 N_("Use push instructions to save outgoing arguments") }, \
385 { "no-push-args", MASK_NO_PUSH_ARGS, \
386 N_("Do not use push instructions to save outgoing arguments") }, \
387 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
388 N_("Use push instructions to save outgoing arguments") }, \
389 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
390 N_("Do not use push instructions to save outgoing arguments") }, \
392 N_("Support MMX built-in functions") }, \
393 { "no-mmx", -MASK_MMX, \
394 N_("Do not support MMX built-in functions") }, \
395 { "3dnow", MASK_3DNOW, \
396 N_("Support 3DNow! built-in functions") }, \
397 { "no-3dnow", -MASK_3DNOW, \
398 N_("Do not support 3DNow! built-in functions") }, \
400 N_("Support MMX and SSE built-in functions and code generation") }, \
401 { "no-sse", -MASK_SSE, \
402 N_("Do not support MMX and SSE built-in functions and code generation") },\
403 { "sse2", MASK_SSE2, \
404 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
405 { "no-sse2", -MASK_SSE2, \
406 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
407 { "sse3", MASK_SSE3, \
408 N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
409 { "no-sse3", -MASK_SSE3, \
410 N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
411 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
412 N_("sizeof(long double) is 16") }, \
413 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
414 N_("sizeof(long double) is 12") }, \
415 { "64", MASK_64BIT, \
416 N_("Generate 64bit x86-64 code") }, \
417 { "32", -MASK_64BIT, \
418 N_("Generate 32bit i386 code") }, \
419 { "ms-bitfields", MASK_MS_BITFIELD_LAYOUT, \
420 N_("Use native (MS) bitfield layout") }, \
421 { "no-ms-bitfields", -MASK_MS_BITFIELD_LAYOUT, \
422 N_("Use gcc default bitfield layout") }, \
423 { "red-zone", -MASK_NO_RED_ZONE, \
424 N_("Use red-zone in the x86-64 code") }, \
425 { "no-red-zone", MASK_NO_RED_ZONE, \
426 N_("Do not use red-zone in the x86-64 code") }, \
427 { "tls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS, \
428 N_("Use direct references against %gs when accessing tls data") }, \
429 { "no-tls-direct-seg-refs", -MASK_TLS_DIRECT_SEG_REFS, \
430 N_("Do not use direct references against %gs when accessing tls data") }, \
433 TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT \
434 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT, 0 }}
436 #ifndef TARGET_64BIT_DEFAULT
437 #define TARGET_64BIT_DEFAULT 0
439 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT
440 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0
443 /* Once GDB has been enhanced to deal with functions without frame
444 pointers, we can change this to allow for elimination of
445 the frame pointer in leaf functions. */
446 #define TARGET_DEFAULT 0
448 /* This is not really a target flag, but is done this way so that
449 it's analogous to similar code for Mach-O on PowerPC. darwin.h
450 redefines this to 1. */
451 #define TARGET_MACHO 0
453 /* This macro is similar to `TARGET_SWITCHES' but defines names of
454 command options that have values. Its definition is an
455 initializer with a subgrouping for each command option.
457 Each subgrouping contains a string constant, that defines the
458 fixed part of the option name, and the address of a variable. The
459 variable, type `char *', is set to the variable part of the given
460 option if the fixed part matches. The actual option name is made
461 by appending `-m' to the specified name. */
462 #define TARGET_OPTIONS \
463 { { "tune=", &ix86_tune_string, \
464 N_("Schedule code for given CPU"), 0}, \
465 { "fpmath=", &ix86_fpmath_string, \
466 N_("Generate floating point mathematics using given instruction set"), 0},\
467 { "arch=", &ix86_arch_string, \
468 N_("Generate code for given CPU"), 0}, \
469 { "regparm=", &ix86_regparm_string, \
470 N_("Number of registers used to pass integer arguments"), 0},\
471 { "align-loops=", &ix86_align_loops_string, \
472 N_("Loop code aligned to this power of 2"), 0}, \
473 { "align-jumps=", &ix86_align_jumps_string, \
474 N_("Jump targets are aligned to this power of 2"), 0}, \
475 { "align-functions=", &ix86_align_funcs_string, \
476 N_("Function starts are aligned to this power of 2"), 0}, \
477 { "preferred-stack-boundary=", \
478 &ix86_preferred_stack_boundary_string, \
479 N_("Attempt to keep stack aligned to this power of 2"), 0}, \
480 { "branch-cost=", &ix86_branch_cost_string, \
481 N_("Branches are this expensive (1-5, arbitrary units)"), 0},\
482 { "cmodel=", &ix86_cmodel_string, \
483 N_("Use given x86-64 code model"), 0}, \
484 { "debug-arg", &ix86_debug_arg_string, \
485 "" /* Undocumented. */, 0}, \
486 { "debug-addr", &ix86_debug_addr_string, \
487 "" /* Undocumented. */, 0}, \
488 { "asm=", &ix86_asm_string, \
489 N_("Use given assembler dialect"), 0}, \
490 { "tls-dialect=", &ix86_tls_dialect_string, \
491 N_("Use given thread-local storage dialect"), 0}, \
495 /* Sometimes certain combinations of command options do not make
496 sense on a particular target machine. You can define a macro
497 `OVERRIDE_OPTIONS' to take account of this. This macro, if
498 defined, is executed once just after all the command options have
501 Don't use this macro to turn on various extra optimizations for
502 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
504 #define OVERRIDE_OPTIONS override_options ()
506 /* These are meant to be redefined in the host dependent files */
507 #define SUBTARGET_SWITCHES
508 #define SUBTARGET_OPTIONS
510 /* Define this to change the optimizations performed by default. */
511 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
512 optimization_options ((LEVEL), (SIZE))
514 /* Support for configure-time defaults of some command line options. */
515 #define OPTION_DEFAULT_SPECS \
516 {"arch", "%{!march=*:-march=%(VALUE)}"}, \
517 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \
518 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }
520 /* Specs for the compiler proper */
523 #define CC1_CPU_SPEC "\
526 %n`-m386' is deprecated. Use `-march=i386' or `-mtune=i386' instead.\n} \
528 %n`-m486' is deprecated. Use `-march=i486' or `-mtune=i486' instead.\n} \
529 %{mpentium:-mtune=pentium \
530 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mtune=pentium' instead.\n} \
531 %{mpentiumpro:-mtune=pentiumpro \
532 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mtune=pentiumpro' instead.\n} \
534 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n}} \
536 %{mintel-syntax:-masm=intel \
537 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
538 %{mno-intel-syntax:-masm=att \
539 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
542 /* Target CPU builtins. */
543 #define TARGET_CPU_CPP_BUILTINS() \
546 size_t arch_len = strlen (ix86_arch_string); \
547 size_t tune_len = strlen (ix86_tune_string); \
548 int last_arch_char = ix86_arch_string[arch_len - 1]; \
549 int last_tune_char = ix86_tune_string[tune_len - 1]; \
553 builtin_assert ("cpu=x86_64"); \
554 builtin_assert ("machine=x86_64"); \
555 builtin_define ("__amd64"); \
556 builtin_define ("__amd64__"); \
557 builtin_define ("__x86_64"); \
558 builtin_define ("__x86_64__"); \
562 builtin_assert ("cpu=i386"); \
563 builtin_assert ("machine=i386"); \
564 builtin_define_std ("i386"); \
567 /* Built-ins based on -mtune= (or -march= if no \
570 builtin_define ("__tune_i386__"); \
571 else if (TARGET_486) \
572 builtin_define ("__tune_i486__"); \
573 else if (TARGET_PENTIUM) \
575 builtin_define ("__tune_i586__"); \
576 builtin_define ("__tune_pentium__"); \
577 if (last_tune_char == 'x') \
578 builtin_define ("__tune_pentium_mmx__"); \
580 else if (TARGET_PENTIUMPRO) \
582 builtin_define ("__tune_i686__"); \
583 builtin_define ("__tune_pentiumpro__"); \
584 switch (last_tune_char) \
587 builtin_define ("__tune_pentium3__"); \
590 builtin_define ("__tune_pentium2__"); \
594 else if (TARGET_K6) \
596 builtin_define ("__tune_k6__"); \
597 if (last_tune_char == '2') \
598 builtin_define ("__tune_k6_2__"); \
599 else if (last_tune_char == '3') \
600 builtin_define ("__tune_k6_3__"); \
602 else if (TARGET_ATHLON) \
604 builtin_define ("__tune_athlon__"); \
605 /* Only plain "athlon" lacks SSE. */ \
606 if (last_tune_char != 'n') \
607 builtin_define ("__tune_athlon_sse__"); \
609 else if (TARGET_K8) \
610 builtin_define ("__tune_k8__"); \
611 else if (TARGET_PENTIUM4) \
612 builtin_define ("__tune_pentium4__"); \
613 else if (TARGET_NOCONA) \
614 builtin_define ("__tune_nocona__"); \
617 builtin_define ("__MMX__"); \
619 builtin_define ("__3dNOW__"); \
620 if (TARGET_3DNOW_A) \
621 builtin_define ("__3dNOW_A__"); \
623 builtin_define ("__SSE__"); \
625 builtin_define ("__SSE2__"); \
627 builtin_define ("__SSE3__"); \
628 if (TARGET_SSE_MATH && TARGET_SSE) \
629 builtin_define ("__SSE_MATH__"); \
630 if (TARGET_SSE_MATH && TARGET_SSE2) \
631 builtin_define ("__SSE2_MATH__"); \
633 /* Built-ins based on -march=. */ \
634 if (ix86_arch == PROCESSOR_I486) \
636 builtin_define ("__i486"); \
637 builtin_define ("__i486__"); \
639 else if (ix86_arch == PROCESSOR_PENTIUM) \
641 builtin_define ("__i586"); \
642 builtin_define ("__i586__"); \
643 builtin_define ("__pentium"); \
644 builtin_define ("__pentium__"); \
645 if (last_arch_char == 'x') \
646 builtin_define ("__pentium_mmx__"); \
648 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
650 builtin_define ("__i686"); \
651 builtin_define ("__i686__"); \
652 builtin_define ("__pentiumpro"); \
653 builtin_define ("__pentiumpro__"); \
655 else if (ix86_arch == PROCESSOR_K6) \
658 builtin_define ("__k6"); \
659 builtin_define ("__k6__"); \
660 if (last_arch_char == '2') \
661 builtin_define ("__k6_2__"); \
662 else if (last_arch_char == '3') \
663 builtin_define ("__k6_3__"); \
665 else if (ix86_arch == PROCESSOR_ATHLON) \
667 builtin_define ("__athlon"); \
668 builtin_define ("__athlon__"); \
669 /* Only plain "athlon" lacks SSE. */ \
670 if (last_arch_char != 'n') \
671 builtin_define ("__athlon_sse__"); \
673 else if (ix86_arch == PROCESSOR_K8) \
675 builtin_define ("__k8"); \
676 builtin_define ("__k8__"); \
678 else if (ix86_arch == PROCESSOR_PENTIUM4) \
680 builtin_define ("__pentium4"); \
681 builtin_define ("__pentium4__"); \
683 else if (ix86_arch == PROCESSOR_NOCONA) \
685 builtin_define ("__nocona"); \
686 builtin_define ("__nocona__"); \
691 #define TARGET_CPU_DEFAULT_i386 0
692 #define TARGET_CPU_DEFAULT_i486 1
693 #define TARGET_CPU_DEFAULT_pentium 2
694 #define TARGET_CPU_DEFAULT_pentium_mmx 3
695 #define TARGET_CPU_DEFAULT_pentiumpro 4
696 #define TARGET_CPU_DEFAULT_pentium2 5
697 #define TARGET_CPU_DEFAULT_pentium3 6
698 #define TARGET_CPU_DEFAULT_pentium4 7
699 #define TARGET_CPU_DEFAULT_k6 8
700 #define TARGET_CPU_DEFAULT_k6_2 9
701 #define TARGET_CPU_DEFAULT_k6_3 10
702 #define TARGET_CPU_DEFAULT_athlon 11
703 #define TARGET_CPU_DEFAULT_athlon_sse 12
704 #define TARGET_CPU_DEFAULT_k8 13
705 #define TARGET_CPU_DEFAULT_pentium_m 14
706 #define TARGET_CPU_DEFAULT_prescott 15
707 #define TARGET_CPU_DEFAULT_nocona 16
709 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
710 "pentiumpro", "pentium2", "pentium3", \
711 "pentium4", "k6", "k6-2", "k6-3",\
712 "athlon", "athlon-4", "k8", \
713 "pentium-m", "prescott", "nocona"}
716 #define CC1_SPEC "%(cc1_cpu) "
719 /* This macro defines names of additional specifications to put in the
720 specs that can be used in various specifications like CC1_SPEC. Its
721 definition is an initializer with a subgrouping for each command option.
723 Each subgrouping contains a string constant, that defines the
724 specification name, and a string constant that used by the GCC driver
727 Do not define this macro if it does not need to do anything. */
729 #ifndef SUBTARGET_EXTRA_SPECS
730 #define SUBTARGET_EXTRA_SPECS
733 #define EXTRA_SPECS \
734 { "cc1_cpu", CC1_CPU_SPEC }, \
735 SUBTARGET_EXTRA_SPECS
737 /* target machine storage layout */
739 #define LONG_DOUBLE_TYPE_SIZE 96
741 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
742 FPU, assume that the fpcw is set to extended precision; when using
743 only SSE, rounding is correct; when using both SSE and the FPU,
744 the rounding precision is indeterminate, since either may be chosen
745 apparently at random. */
746 #define TARGET_FLT_EVAL_METHOD \
747 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)
749 #define SHORT_TYPE_SIZE 16
750 #define INT_TYPE_SIZE 32
751 #define FLOAT_TYPE_SIZE 32
752 #define LONG_TYPE_SIZE BITS_PER_WORD
753 #define DOUBLE_TYPE_SIZE 64
754 #define LONG_LONG_TYPE_SIZE 64
756 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
757 #define MAX_BITS_PER_WORD 64
759 #define MAX_BITS_PER_WORD 32
762 /* Define this if most significant byte of a word is the lowest numbered. */
763 /* That is true on the 80386. */
765 #define BITS_BIG_ENDIAN 0
767 /* Define this if most significant byte of a word is the lowest numbered. */
768 /* That is not true on the 80386. */
769 #define BYTES_BIG_ENDIAN 0
771 /* Define this if most significant word of a multiword number is the lowest
773 /* Not true for 80386 */
774 #define WORDS_BIG_ENDIAN 0
776 /* Width of a word, in units (bytes). */
777 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
779 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
781 #define MIN_UNITS_PER_WORD 4
784 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
785 #define PARM_BOUNDARY BITS_PER_WORD
787 /* Boundary (in *bits*) on which stack pointer should be aligned. */
788 #define STACK_BOUNDARY BITS_PER_WORD
790 /* Boundary (in *bits*) on which the stack pointer prefers to be
791 aligned; the compiler cannot rely on having this alignment. */
792 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
794 /* As of July 2001, many runtimes to not align the stack properly when
795 entering main. This causes expand_main_function to forcibly align
796 the stack, which results in aligned frames for functions called from
797 main, though it does nothing for the alignment of main itself. */
798 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
799 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
801 /* Minimum allocation boundary for the code of a function. */
802 #define FUNCTION_BOUNDARY 8
804 /* C++ stores the virtual bit in the lowest bit of function pointers. */
805 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
807 /* Alignment of field after `int : 0' in a structure. */
809 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
811 /* Minimum size in bits of the largest boundary to which any
812 and all fundamental data types supported by the hardware
813 might need to be aligned. No data type wants to be aligned
816 Pentium+ prefers DFmode values to be aligned to 64 bit boundary
817 and Pentium Pro XFmode values at 128 bit boundaries. */
819 #define BIGGEST_ALIGNMENT 128
821 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
822 #define ALIGN_MODE_128(MODE) \
823 ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE))
825 /* The published ABIs say that doubles should be aligned on word
826 boundaries, so lower the alignment for structure fields unless
827 -malign-double is set. */
829 /* ??? Blah -- this macro is used directly by libobjc. Since it
830 supports no vector modes, cut out the complexity and fall back
831 on BIGGEST_FIELD_ALIGNMENT. */
832 #ifdef IN_TARGET_LIBS
834 #define BIGGEST_FIELD_ALIGNMENT 128
836 #define BIGGEST_FIELD_ALIGNMENT 32
839 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
840 x86_field_alignment (FIELD, COMPUTED)
843 /* If defined, a C expression to compute the alignment given to a
844 constant that is being placed in memory. EXP is the constant
845 and ALIGN is the alignment that the object would ordinarily have.
846 The value of this macro is used instead of that alignment to align
849 If this macro is not defined, then ALIGN is used.
851 The typical use of this macro is to increase alignment for string
852 constants to be word aligned so that `strcpy' calls that copy
853 constants can be done inline. */
855 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
857 /* If defined, a C expression to compute the alignment for a static
858 variable. TYPE is the data type, and ALIGN is the alignment that
859 the object would ordinarily have. The value of this macro is used
860 instead of that alignment to align the object.
862 If this macro is not defined, then ALIGN is used.
864 One use of this macro is to increase alignment of medium-size
865 data to make it all fit in fewer cache lines. Another is to
866 cause character arrays to be word-aligned so that `strcpy' calls
867 that copy constants to character arrays can be done inline. */
869 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
871 /* If defined, a C expression to compute the alignment for a local
872 variable. TYPE is the data type, and ALIGN is the alignment that
873 the object would ordinarily have. The value of this macro is used
874 instead of that alignment to align the object.
876 If this macro is not defined, then ALIGN is used.
878 One use of this macro is to increase alignment of medium-size
879 data to make it all fit in fewer cache lines. */
881 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
883 /* If defined, a C expression that gives the alignment boundary, in
884 bits, of an argument with the specified mode and type. If it is
885 not defined, `PARM_BOUNDARY' is used for all arguments. */
887 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
888 ix86_function_arg_boundary ((MODE), (TYPE))
890 /* Set this nonzero if move instructions will actually fail to work
891 when given unaligned data. */
892 #define STRICT_ALIGNMENT 0
894 /* If bit field type is int, don't let it cross an int,
895 and give entire struct the alignment of an int. */
896 /* Required on the 386 since it doesn't have bit-field insns. */
897 #define PCC_BITFIELD_TYPE_MATTERS 1
899 /* Standard register usage. */
901 /* This processor has special stack-like registers. See reg-stack.c
905 #define IS_STACK_MODE(MODE) \
906 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode) \
908 /* Number of actual hardware registers.
909 The hardware registers are assigned numbers for the compiler
910 from 0 to just below FIRST_PSEUDO_REGISTER.
911 All registers that the compiler knows about must be given numbers,
912 even those that are not normally considered general registers.
914 In the 80386 we give the 8 general purpose registers the numbers 0-7.
915 We number the floating point registers 8-15.
916 Note that registers 0-7 can be accessed as a short or int,
917 while only 0-3 may be used with byte `mov' instructions.
919 Reg 16 does not correspond to any hardware register, but instead
920 appears in the RTL as an argument pointer prior to reload, and is
921 eliminated during reloading in favor of either the stack or frame
924 #define FIRST_PSEUDO_REGISTER 53
926 /* Number of hardware registers that go into the DWARF-2 unwind info.
927 If not defined, equals FIRST_PSEUDO_REGISTER. */
929 #define DWARF_FRAME_REGISTERS 17
931 /* 1 for registers that have pervasive standard uses
932 and are not available for the register allocator.
933 On the 80386, the stack pointer is such, as is the arg pointer.
935 The value is a mask - bit 1 is set for fixed registers
936 for 32bit target, while 2 is set for fixed registers for 64bit.
937 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
939 #define FIXED_REGISTERS \
940 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
941 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
942 /*arg,flags,fpsr,dir,frame*/ \
944 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
945 0, 0, 0, 0, 0, 0, 0, 0, \
946 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
947 0, 0, 0, 0, 0, 0, 0, 0, \
948 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
949 1, 1, 1, 1, 1, 1, 1, 1, \
950 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
951 1, 1, 1, 1, 1, 1, 1, 1}
954 /* 1 for registers not available across function calls.
955 These must include the FIXED_REGISTERS and also any
956 registers that can be used without being saved.
957 The latter must include the registers where values are returned
958 and the register where structure-value addresses are passed.
959 Aside from that, you can include as many other registers as you like.
961 The value is a mask - bit 1 is set for call used
962 for 32bit target, while 2 is set for call used for 64bit.
963 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
965 #define CALL_USED_REGISTERS \
966 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
967 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
968 /*arg,flags,fpsr,dir,frame*/ \
970 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
971 3, 3, 3, 3, 3, 3, 3, 3, \
972 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
973 3, 3, 3, 3, 3, 3, 3, 3, \
974 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
975 3, 3, 3, 3, 1, 1, 1, 1, \
976 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
977 3, 3, 3, 3, 3, 3, 3, 3} \
979 /* Order in which to allocate registers. Each register must be
980 listed once, even those in FIXED_REGISTERS. List frame pointer
981 late and fixed registers last. Note that, in general, we prefer
982 registers listed in CALL_USED_REGISTERS, keeping the others
983 available for storage of persistent values.
985 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
986 so this is just empty initializer for array. */
988 #define REG_ALLOC_ORDER \
989 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
990 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
991 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
994 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
995 to be rearranged based on a particular function. When using sse math,
996 we want to allocate SSE before x87 registers and vice vera. */
998 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
1001 /* Macro to conditionally modify fixed_regs/call_used_regs. */
1002 #define CONDITIONAL_REGISTER_USAGE \
1005 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1007 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
1008 call_used_regs[i] = (call_used_regs[i] \
1009 & (TARGET_64BIT ? 2 : 1)) != 0; \
1011 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
1013 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1014 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
1019 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1020 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
1021 fixed_regs[i] = call_used_regs[i] = 1; \
1026 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1027 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
1028 fixed_regs[i] = call_used_regs[i] = 1; \
1030 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
1034 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
1035 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
1036 if (TEST_HARD_REG_BIT (x, i)) \
1037 fixed_regs[i] = call_used_regs[i] = 1; \
1041 /* Return number of consecutive hard regs needed starting at reg REGNO
1042 to hold something of mode MODE.
1043 This is ordinarily the length in words of a value of mode MODE
1044 but can be less for certain modes in special long registers.
1046 Actually there are no two word move instructions for consecutive
1047 registers. And only registers 0-3 may have mov byte instructions
1051 #define HARD_REGNO_NREGS(REGNO, MODE) \
1052 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1053 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1054 : ((MODE) == XFmode \
1055 ? (TARGET_64BIT ? 2 : 3) \
1056 : (MODE) == XCmode \
1057 ? (TARGET_64BIT ? 4 : 6) \
1058 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1060 #define VALID_SSE2_REG_MODE(MODE) \
1061 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
1062 || (MODE) == V2DImode)
1064 #define VALID_SSE_REG_MODE(MODE) \
1065 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1066 || (MODE) == SFmode || (MODE) == TFmode \
1067 /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \
1068 || VALID_SSE2_REG_MODE (MODE) \
1069 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
1071 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1072 ((MODE) == V2SFmode || (MODE) == SFmode)
1074 #define VALID_MMX_REG_MODE(MODE) \
1075 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1076 || (MODE) == V2SImode || (MODE) == SImode)
1078 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1079 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
1080 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
1081 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1083 #define VALID_FP_MODE_P(MODE) \
1084 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
1085 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \
1087 #define VALID_INT_MODE_P(MODE) \
1088 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1089 || (MODE) == DImode \
1090 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1091 || (MODE) == CDImode \
1092 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \
1093 || (MODE) == TFmode || (MODE) == TCmode)))
1095 /* Return true for modes passed in SSE registers. */
1096 #define SSE_REG_MODE_P(MODE) \
1097 ((MODE) == TImode || (MODE) == V16QImode || (MODE) == TFmode \
1098 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1099 || (MODE) == V4SFmode || (MODE) == V4SImode)
1101 /* Return true for modes passed in MMX registers. */
1102 #define MMX_REG_MODE_P(MODE) \
1103 ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \
1104 || (MODE) == V2SFmode)
1106 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1108 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1109 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1111 /* Value is 1 if it is a good idea to tie two pseudo registers
1112 when one has mode MODE1 and one has mode MODE2.
1113 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1114 for any hard reg, then this must be 0 for correct output. */
1116 #define MODES_TIEABLE_P(MODE1, MODE2) \
1117 ((MODE1) == (MODE2) \
1118 || (((MODE1) == HImode || (MODE1) == SImode \
1119 || ((MODE1) == QImode \
1120 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1121 || ((MODE1) == DImode && TARGET_64BIT)) \
1122 && ((MODE2) == HImode || (MODE2) == SImode \
1123 || ((MODE2) == QImode \
1124 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1125 || ((MODE2) == DImode && TARGET_64BIT))))
1127 /* It is possible to write patterns to move flags; but until someone
1129 #define AVOID_CCMODE_COPIES
1131 /* Specify the modes required to caller save a given hard regno.
1132 We do this on i386 to prevent flags from being saved at all.
1134 Kill any attempts to combine saving of modes. */
1136 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1137 (CC_REGNO_P (REGNO) ? VOIDmode \
1138 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1139 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
1140 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1141 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1143 /* Specify the registers used for certain standard purposes.
1144 The values of these macros are register numbers. */
1146 /* on the 386 the pc register is %eip, and is not usable as a general
1147 register. The ordinary mov instructions won't work */
1148 /* #define PC_REGNUM */
1150 /* Register to use for pushing function arguments. */
1151 #define STACK_POINTER_REGNUM 7
1153 /* Base register for access to local variables of the function. */
1154 #define HARD_FRAME_POINTER_REGNUM 6
1156 /* Base register for access to local variables of the function. */
1157 #define FRAME_POINTER_REGNUM 20
1159 /* First floating point reg */
1160 #define FIRST_FLOAT_REG 8
1162 /* First & last stack-like regs */
1163 #define FIRST_STACK_REG FIRST_FLOAT_REG
1164 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1166 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1167 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1169 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1170 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1172 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1173 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1175 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1176 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1178 /* Value should be nonzero if functions must have frame pointers.
1179 Zero means the frame pointer need not be set up (and parms
1180 may be accessed via the stack pointer) in functions that seem suitable.
1181 This is computed in `reload', in reload1.c. */
1182 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1184 /* Override this in other tm.h files to cope with various OS losage
1185 requiring a frame pointer. */
1186 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1187 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1190 /* Make sure we can access arbitrary call frames. */
1191 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1193 /* Base register for access to arguments of the function. */
1194 #define ARG_POINTER_REGNUM 16
1196 /* Register in which static-chain is passed to a function.
1197 We do use ECX as static chain register for 32 bit ABI. On the
1198 64bit ABI, ECX is an argument register, so we use R10 instead. */
1199 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1201 /* Register to hold the addressing base for position independent
1202 code access to data items. We don't use PIC pointer for 64bit
1203 mode. Define the regnum to dummy value to prevent gcc from
1204 pessimizing code dealing with EBX.
1206 To avoid clobbering a call-saved register unnecessarily, we renumber
1207 the pic register when possible. The change is visible after the
1208 prologue has been emitted. */
1210 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1212 #define PIC_OFFSET_TABLE_REGNUM \
1213 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \
1214 : reload_completed ? REGNO (pic_offset_table_rtx) \
1215 : REAL_PIC_OFFSET_TABLE_REGNUM)
1217 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1219 /* A C expression which can inhibit the returning of certain function
1220 values in registers, based on the type of value. A nonzero value
1221 says to return the function value in memory, just as large
1222 structures are always returned. Here TYPE will be a C expression
1223 of type `tree', representing the data type of the value.
1225 Note that values of mode `BLKmode' must be explicitly handled by
1226 this macro. Also, the option `-fpcc-struct-return' takes effect
1227 regardless of this macro. On most systems, it is possible to
1228 leave the macro undefined; this causes a default definition to be
1229 used, whose value is the constant 1 for `BLKmode' values, and 0
1232 Do not use this macro to indicate that structures and unions
1233 should always be returned in memory. You should instead use
1234 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1236 #define RETURN_IN_MEMORY(TYPE) \
1237 ix86_return_in_memory (TYPE)
1239 /* This is overridden by <cygwin.h>. */
1240 #define MS_AGGREGATE_RETURN 0
1243 /* Define the classes of registers for register constraints in the
1244 machine description. Also define ranges of constants.
1246 One of the classes must always be named ALL_REGS and include all hard regs.
1247 If there is more than one class, another class must be named NO_REGS
1248 and contain no registers.
1250 The name GENERAL_REGS must be the name of a class (or an alias for
1251 another name such as ALL_REGS). This is the class of registers
1252 that is allowed by "g" or "r" in a register constraint.
1253 Also, registers outside this class are allocated only when
1254 instructions express preferences for them.
1256 The classes must be numbered in nondecreasing order; that is,
1257 a larger-numbered class must never be contained completely
1258 in a smaller-numbered class.
1260 For any two classes, it is very desirable that there be another
1261 class that represents their union.
1263 It might seem that class BREG is unnecessary, since no useful 386
1264 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1265 and the "b" register constraint is useful in asms for syscalls.
1267 The flags and fpsr registers are in no class. */
1272 AREG, DREG, CREG, BREG, SIREG, DIREG,
1273 AD_REGS, /* %eax/%edx for DImode */
1274 Q_REGS, /* %eax %ebx %ecx %edx */
1275 NON_Q_REGS, /* %esi %edi %ebp %esp */
1276 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1277 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1278 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1279 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1289 ALL_REGS, LIM_REG_CLASSES
1292 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1294 #define INTEGER_CLASS_P(CLASS) \
1295 reg_class_subset_p ((CLASS), GENERAL_REGS)
1296 #define FLOAT_CLASS_P(CLASS) \
1297 reg_class_subset_p ((CLASS), FLOAT_REGS)
1298 #define SSE_CLASS_P(CLASS) \
1299 reg_class_subset_p ((CLASS), SSE_REGS)
1300 #define MMX_CLASS_P(CLASS) \
1301 reg_class_subset_p ((CLASS), MMX_REGS)
1302 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1303 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1304 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1305 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1306 #define MAYBE_SSE_CLASS_P(CLASS) \
1307 reg_classes_intersect_p (SSE_REGS, (CLASS))
1308 #define MAYBE_MMX_CLASS_P(CLASS) \
1309 reg_classes_intersect_p (MMX_REGS, (CLASS))
1311 #define Q_CLASS_P(CLASS) \
1312 reg_class_subset_p ((CLASS), Q_REGS)
1314 /* Give names of register classes as strings for dump file. */
1316 #define REG_CLASS_NAMES \
1318 "AREG", "DREG", "CREG", "BREG", \
1321 "Q_REGS", "NON_Q_REGS", \
1325 "FP_TOP_REG", "FP_SECOND_REG", \
1329 "FP_TOP_SSE_REGS", \
1330 "FP_SECOND_SSE_REGS", \
1334 "FLOAT_INT_SSE_REGS", \
1337 /* Define which registers fit in which classes.
1338 This is an initializer for a vector of HARD_REG_SET
1339 of length N_REG_CLASSES. */
1341 #define REG_CLASS_CONTENTS \
1343 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1344 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1345 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1346 { 0x03, 0x0 }, /* AD_REGS */ \
1347 { 0x0f, 0x0 }, /* Q_REGS */ \
1348 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1349 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1350 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1351 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1352 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1353 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1354 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1355 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1356 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1357 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1358 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1359 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1360 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1361 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1362 { 0xffffffff,0x1fffff } \
1365 /* The same information, inverted:
1366 Return the class number of the smallest class containing
1367 reg number REGNO. This could be a conditional expression
1368 or could index an array. */
1370 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1372 /* When defined, the compiler allows registers explicitly used in the
1373 rtl to be used as spill registers but prevents the compiler from
1374 extending the lifetime of these registers. */
1376 #define SMALL_REGISTER_CLASSES 1
1378 #define QI_REG_P(X) \
1379 (REG_P (X) && REGNO (X) < 4)
1381 #define GENERAL_REGNO_P(N) \
1382 ((N) < 8 || REX_INT_REGNO_P (N))
1384 #define GENERAL_REG_P(X) \
1385 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1387 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1389 #define NON_QI_REG_P(X) \
1390 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1392 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1393 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1395 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1396 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1397 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1398 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1400 #define SSE_REGNO_P(N) \
1401 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1402 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1404 #define REX_SSE_REGNO_P(N) \
1405 ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG)
1407 #define SSE_REGNO(N) \
1408 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1409 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1411 #define SSE_FLOAT_MODE_P(MODE) \
1412 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1414 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1415 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1417 #define STACK_REG_P(XOP) \
1419 REGNO (XOP) >= FIRST_STACK_REG && \
1420 REGNO (XOP) <= LAST_STACK_REG)
1422 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1424 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1426 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1427 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1429 /* The class value for index registers, and the one for base regs. */
1431 #define INDEX_REG_CLASS INDEX_REGS
1432 #define BASE_REG_CLASS GENERAL_REGS
1434 /* Get reg_class from a letter such as appears in the machine description. */
1436 #define REG_CLASS_FROM_LETTER(C) \
1437 ((C) == 'r' ? GENERAL_REGS : \
1438 (C) == 'R' ? LEGACY_REGS : \
1439 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1440 (C) == 'Q' ? Q_REGS : \
1441 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1444 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1447 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1450 (C) == 'a' ? AREG : \
1451 (C) == 'b' ? BREG : \
1452 (C) == 'c' ? CREG : \
1453 (C) == 'd' ? DREG : \
1454 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1455 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1456 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1457 (C) == 'A' ? AD_REGS : \
1458 (C) == 'D' ? DIREG : \
1459 (C) == 'S' ? SIREG : NO_REGS)
1461 /* The letters I, J, K, L and M in a register constraint string
1462 can be used to stand for particular ranges of immediate operands.
1463 This macro defines what the ranges are.
1464 C is the letter, and VALUE is a constant value.
1465 Return 1 if VALUE is in the range specified by C.
1467 I is for non-DImode shifts.
1468 J is for DImode shifts.
1469 K is for signed imm8 operands.
1470 L is for andsi as zero-extending move.
1471 M is for shifts that can be executed by the "lea" opcode.
1472 N is for immediate operands for out/in instructions (0-255)
1475 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1476 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1477 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1478 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1479 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1480 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1481 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1484 /* Similar, but for floating constants, and defining letters G and H.
1485 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1486 TARGET_387 isn't set, because the stack register converter may need to
1487 load 0.0 into the function value register. */
1489 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1490 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1493 /* A C expression that defines the optional machine-dependent
1494 constraint letters that can be used to segregate specific types of
1495 operands, usually memory references, for the target machine. Any
1496 letter that is not elsewhere defined and not matched by
1497 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1500 If it is required for a particular target machine, it should
1501 return 1 if VALUE corresponds to the operand type represented by
1502 the constraint letter C. If C is not defined as an extra
1503 constraint, the value returned should be 0 regardless of VALUE. */
1505 #define EXTRA_CONSTRAINT(VALUE, D) \
1506 ((D) == 'e' ? x86_64_sign_extended_value (VALUE) \
1507 : (D) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1508 : (D) == 'C' ? standard_sse_constant_p (VALUE) \
1511 /* Place additional restrictions on the register class to use when it
1512 is necessary to be able to hold a value of mode MODE in a reload
1513 register for which class CLASS would ordinarily be used. */
1515 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1516 ((MODE) == QImode && !TARGET_64BIT \
1517 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1518 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1521 /* Given an rtx X being reloaded into a reg required to be
1522 in class CLASS, return the class of reg to actually use.
1523 In general this is just CLASS; but on some machines
1524 in some cases it is preferable to use a more restrictive class.
1525 On the 80386 series, we prevent floating constants from being
1526 reloaded into floating registers (since no move-insn can do that)
1527 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1529 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1530 QImode must go into class Q_REGS.
1531 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1532 movdf to do mem-to-mem moves through integer regs. */
1534 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1535 ix86_preferred_reload_class ((X), (CLASS))
1537 /* If we are copying between general and FP registers, we need a memory
1538 location. The same is true for SSE and MMX registers. */
1539 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1540 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1542 /* QImode spills from non-QI registers need a scratch. This does not
1543 happen often -- the only example so far requires an uninitialized
1546 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1547 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1548 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1551 /* Return the maximum number of consecutive registers
1552 needed to represent mode MODE in a register of class CLASS. */
1553 /* On the 80386, this is the size of MODE in words,
1554 except in the FP regs, where a single reg is always enough. */
1555 #define CLASS_MAX_NREGS(CLASS, MODE) \
1556 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1557 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1558 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \
1559 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1561 /* A C expression whose value is nonzero if pseudos that have been
1562 assigned to registers of class CLASS would likely be spilled
1563 because registers of CLASS are needed for spill registers.
1565 The default value of this macro returns 1 if CLASS has exactly one
1566 register and zero otherwise. On most machines, this default
1567 should be used. Only define this macro to some other expression
1568 if pseudo allocated by `local-alloc.c' end up in memory because
1569 their hard registers were needed for spill registers. If this
1570 macro returns nonzero for those classes, those pseudos will only
1571 be allocated by `global.c', which knows how to reallocate the
1572 pseudo to another register. If there would not be another
1573 register available for reallocation, you should not change the
1574 definition of this macro since the only effect of such a
1575 definition would be to slow down register allocation. */
1577 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1578 (((CLASS) == AREG) \
1579 || ((CLASS) == DREG) \
1580 || ((CLASS) == CREG) \
1581 || ((CLASS) == BREG) \
1582 || ((CLASS) == AD_REGS) \
1583 || ((CLASS) == SIREG) \
1584 || ((CLASS) == DIREG) \
1585 || ((CLASS) == FP_TOP_REG) \
1586 || ((CLASS) == FP_SECOND_REG))
1588 /* Return a class of registers that cannot change FROM mode to TO mode.
1590 x87 registers can't do subreg as all values are reformated to extended
1591 precision. XMM registers does not support with nonzero offsets equal
1592 to 4, 8 and 12 otherwise valid for integer registers. Since we can't
1593 determine these, prohibit all nonparadoxical subregs changing size. */
1595 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1596 (GET_MODE_SIZE (TO) < GET_MODE_SIZE (FROM) \
1597 ? reg_classes_intersect_p (FLOAT_SSE_REGS, (CLASS)) \
1598 || MAYBE_MMX_CLASS_P (CLASS) \
1599 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1600 ? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0)
1602 /* Stack layout; function entry, exit and calling. */
1604 /* Define this if pushing a word on the stack
1605 makes the stack pointer a smaller address. */
1606 #define STACK_GROWS_DOWNWARD
1608 /* Define this if the nominal address of the stack frame
1609 is at the high-address end of the local variables;
1610 that is, each additional local variable allocated
1611 goes at a more negative offset in the frame. */
1612 #define FRAME_GROWS_DOWNWARD
1614 /* Offset within stack frame to start allocating local variables at.
1615 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1616 first local allocated. Otherwise, it is the offset to the BEGINNING
1617 of the first local allocated. */
1618 #define STARTING_FRAME_OFFSET 0
1620 /* If we generate an insn to push BYTES bytes,
1621 this says how many the stack pointer really advances by.
1622 On 386 pushw decrements by exactly 2 no matter what the position was.
1623 On the 386 there is no pushb; we use pushw instead, and this
1624 has the effect of rounding up to 2.
1626 For 64bit ABI we round up to 8 bytes.
1629 #define PUSH_ROUNDING(BYTES) \
1631 ? (((BYTES) + 7) & (-8)) \
1632 : (((BYTES) + 1) & (-2)))
1634 /* If defined, the maximum amount of space required for outgoing arguments will
1635 be computed and placed into the variable
1636 `current_function_outgoing_args_size'. No space will be pushed onto the
1637 stack for each call; instead, the function prologue should increase the stack
1638 frame size by this amount. */
1640 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1642 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1643 instructions to pass outgoing arguments. */
1645 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1647 /* We want the stack and args grow in opposite directions, even if
1649 #define PUSH_ARGS_REVERSED 1
1651 /* Offset of first parameter from the argument pointer register value. */
1652 #define FIRST_PARM_OFFSET(FNDECL) 0
1654 /* Define this macro if functions should assume that stack space has been
1655 allocated for arguments even when their values are passed in registers.
1657 The value of this macro is the size, in bytes, of the area reserved for
1658 arguments passed in registers for the function represented by FNDECL.
1660 This space can be allocated by the caller, or be a part of the
1661 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1663 #define REG_PARM_STACK_SPACE(FNDECL) 0
1665 /* Value is the number of bytes of arguments automatically
1666 popped when returning from a subroutine call.
1667 FUNDECL is the declaration node of the function (as a tree),
1668 FUNTYPE is the data type of the function (as a tree),
1669 or for a library call it is an identifier node for the subroutine name.
1670 SIZE is the number of bytes of arguments passed on the stack.
1672 On the 80386, the RTD insn may be used to pop them if the number
1673 of args is fixed, but if the number is variable then the caller
1674 must pop them all. RTD can't be used for library calls now
1675 because the library is compiled with the Unix compiler.
1676 Use of RTD is a selectable option, since it is incompatible with
1677 standard Unix calling sequences. If the option is not selected,
1678 the caller must always pop the args.
1680 The attribute stdcall is equivalent to RTD on a per module basis. */
1682 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1683 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1685 /* Define how to find the value returned by a function.
1686 VALTYPE is the data type of the value (as a tree).
1687 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1688 otherwise, FUNC is 0. */
1689 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1690 ix86_function_value (VALTYPE)
1692 #define FUNCTION_VALUE_REGNO_P(N) \
1693 ix86_function_value_regno_p (N)
1695 /* Define how to find the value returned by a library function
1696 assuming the value has mode MODE. */
1698 #define LIBCALL_VALUE(MODE) \
1699 ix86_libcall_value (MODE)
1701 /* Define the size of the result block used for communication between
1702 untyped_call and untyped_return. The block contains a DImode value
1703 followed by the block used by fnsave and frstor. */
1705 #define APPLY_RESULT_SIZE (8+108)
1707 /* 1 if N is a possible register number for function argument passing. */
1708 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1710 /* Define a data type for recording info about an argument list
1711 during the scan of that argument list. This data type should
1712 hold all necessary information about the function itself
1713 and about the args processed so far, enough to enable macros
1714 such as FUNCTION_ARG to determine where the next arg should go. */
1716 typedef struct ix86_args {
1717 int words; /* # words passed so far */
1718 int nregs; /* # registers available for passing */
1719 int regno; /* next available register number */
1720 int fastcall; /* fastcall calling convention is used */
1721 int sse_words; /* # sse words passed so far */
1722 int sse_nregs; /* # sse registers available for passing */
1723 int warn_sse; /* True when we want to warn about SSE ABI. */
1724 int warn_mmx; /* True when we want to warn about MMX ABI. */
1725 int sse_regno; /* next available sse register number */
1726 int mmx_words; /* # mmx words passed so far */
1727 int mmx_nregs; /* # mmx registers available for passing */
1728 int mmx_regno; /* next available mmx register number */
1729 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1732 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1733 for a call to a function whose data type is FNTYPE.
1734 For a library call, FNTYPE is 0. */
1736 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1737 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
1739 /* Update the data in CUM to advance over an argument
1740 of mode MODE and data type TYPE.
1741 (TYPE is null for libcalls where that information may not be available.) */
1743 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1744 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1746 /* Define where to put the arguments to a function.
1747 Value is zero to push the argument on the stack,
1748 or a hard register in which to store the argument.
1750 MODE is the argument's machine mode.
1751 TYPE is the data type of the argument (as a tree).
1752 This is null for libcalls where that information may
1754 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1755 the preceding args and about the function being called.
1756 NAMED is nonzero if this argument is a named parameter
1757 (otherwise it is an extra parameter matching an ellipsis). */
1759 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1760 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1762 /* For an arg passed partly in registers and partly in memory,
1763 this is the number of registers used.
1764 For args passed entirely in registers or entirely in memory, zero. */
1766 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1768 /* A C expression that indicates when an argument must be passed by
1769 reference. If nonzero for an argument, a copy of that argument is
1770 made in memory and a pointer to the argument is passed instead of
1771 the argument itself. The pointer is passed in whatever way is
1772 appropriate for passing a pointer to that type. */
1774 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1775 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1777 /* Implement `va_start' for varargs and stdarg. */
1778 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1779 ix86_va_start (VALIST, NEXTARG)
1781 /* Implement `va_arg'. */
1782 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) (abort (), NULL_RTX)
1784 #define TARGET_ASM_FILE_END ix86_file_end
1785 #define NEED_INDICATE_EXEC_STACK 0
1787 /* Output assembler code to FILE to increment profiler label # LABELNO
1788 for profiling a function entry. */
1790 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO)
1792 #define MCOUNT_NAME "_mcount"
1794 #define PROFILE_COUNT_REGISTER "edx"
1796 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1797 the stack pointer does not matter. The value is tested only in
1798 functions that have frame pointers.
1799 No definition is equivalent to always zero. */
1800 /* Note on the 386 it might be more efficient not to define this since
1801 we have to restore it ourselves from the frame pointer, in order to
1804 #define EXIT_IGNORE_STACK 1
1806 /* Output assembler code for a block containing the constant parts
1807 of a trampoline, leaving space for the variable parts. */
1809 /* On the 386, the trampoline contains two instructions:
1812 The trampoline is generated entirely at runtime. The operand of JMP
1813 is the address of FUNCTION relative to the instruction following the
1814 JMP (which is 5 bytes long). */
1816 /* Length in units of the trampoline for entering a nested function. */
1818 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1820 /* Emit RTL insns to initialize the variable parts of a trampoline.
1821 FNADDR is an RTX for the address of the function's pure code.
1822 CXT is an RTX for the static chain value for the function. */
1824 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1825 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1827 /* Definitions for register eliminations.
1829 This is an array of structures. Each structure initializes one pair
1830 of eliminable registers. The "from" register number is given first,
1831 followed by "to". Eliminations of the same "from" register are listed
1832 in order of preference.
1834 There are two registers that can always be eliminated on the i386.
1835 The frame pointer and the arg pointer can be replaced by either the
1836 hard frame pointer or to the stack pointer, depending upon the
1837 circumstances. The hard frame pointer is not used before reload and
1838 so it is not eligible for elimination. */
1840 #define ELIMINABLE_REGS \
1841 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1842 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1843 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1844 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1846 /* Given FROM and TO register numbers, say whether this elimination is
1847 allowed. Frame pointer elimination is automatically handled.
1849 All other eliminations are valid. */
1851 #define CAN_ELIMINATE(FROM, TO) \
1852 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1854 /* Define the offset between two registers, one to be eliminated, and the other
1855 its replacement, at the start of a routine. */
1857 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1858 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1860 /* Addressing modes, and classification of registers for them. */
1862 /* Macros to check register numbers against specific register classes. */
1864 /* These assume that REGNO is a hard or pseudo reg number.
1865 They give nonzero only if REGNO is a hard reg of the suitable class
1866 or a pseudo reg currently allocated to a suitable hard reg.
1867 Since they use reg_renumber, they are safe only once reg_renumber
1868 has been allocated, which happens in local-alloc.c. */
1870 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1871 ((REGNO) < STACK_POINTER_REGNUM \
1872 || (REGNO >= FIRST_REX_INT_REG \
1873 && (REGNO) <= LAST_REX_INT_REG) \
1874 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1875 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1876 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1878 #define REGNO_OK_FOR_BASE_P(REGNO) \
1879 ((REGNO) <= STACK_POINTER_REGNUM \
1880 || (REGNO) == ARG_POINTER_REGNUM \
1881 || (REGNO) == FRAME_POINTER_REGNUM \
1882 || (REGNO >= FIRST_REX_INT_REG \
1883 && (REGNO) <= LAST_REX_INT_REG) \
1884 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1885 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1886 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1888 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1889 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1890 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1891 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1893 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1894 and check its validity for a certain class.
1895 We have two alternate definitions for each of them.
1896 The usual definition accepts all pseudo regs; the other rejects
1897 them unless they have been allocated suitable hard regs.
1898 The symbol REG_OK_STRICT causes the latter definition to be used.
1900 Most source files want to accept pseudo regs in the hope that
1901 they will get allocated to the class that the insn wants them to be in.
1902 Source files for reload pass need to be strict.
1903 After reload, it makes no difference, since pseudo regs have
1904 been eliminated by then. */
1907 /* Non strict versions, pseudos are ok. */
1908 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1909 (REGNO (X) < STACK_POINTER_REGNUM \
1910 || (REGNO (X) >= FIRST_REX_INT_REG \
1911 && REGNO (X) <= LAST_REX_INT_REG) \
1912 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1914 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1915 (REGNO (X) <= STACK_POINTER_REGNUM \
1916 || REGNO (X) == ARG_POINTER_REGNUM \
1917 || REGNO (X) == FRAME_POINTER_REGNUM \
1918 || (REGNO (X) >= FIRST_REX_INT_REG \
1919 && REGNO (X) <= LAST_REX_INT_REG) \
1920 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1922 /* Strict versions, hard registers only */
1923 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1924 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1926 #ifndef REG_OK_STRICT
1927 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1928 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1931 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1932 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1935 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1936 that is a valid memory address for an instruction.
1937 The MODE argument is the machine mode for the MEM expression
1938 that wants to use this address.
1940 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1941 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1943 See legitimize_pic_address in i386.c for details as to what
1944 constitutes a legitimate address when -fpic is used. */
1946 #define MAX_REGS_PER_ADDRESS 2
1948 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1950 /* Nonzero if the constant value X is a legitimate general operand.
1951 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1953 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1955 #ifdef REG_OK_STRICT
1956 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1958 if (legitimate_address_p ((MODE), (X), 1)) \
1963 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1965 if (legitimate_address_p ((MODE), (X), 0)) \
1971 /* If defined, a C expression to determine the base term of address X.
1972 This macro is used in only one place: `find_base_term' in alias.c.
1974 It is always safe for this macro to not be defined. It exists so
1975 that alias analysis can understand machine-dependent addresses.
1977 The typical use of this macro is to handle addresses containing
1978 a label_ref or symbol_ref within an UNSPEC. */
1980 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1982 /* Try machine-dependent ways of modifying an illegitimate address
1983 to be legitimate. If we find one, return the new, valid address.
1984 This macro is used in only one place: `memory_address' in explow.c.
1986 OLDX is the address as it was before break_out_memory_refs was called.
1987 In some cases it is useful to look at this to decide what needs to be done.
1989 MODE and WIN are passed so that this macro can use
1990 GO_IF_LEGITIMATE_ADDRESS.
1992 It is always safe for this macro to do nothing. It exists to recognize
1993 opportunities to optimize the output.
1995 For the 80386, we handle X+REG by loading X into a register R and
1996 using R+REG. R will go in a general reg and indexing will be used.
1997 However, if REG is a broken-out memory address or multiplication,
1998 nothing needs to be done because REG can certainly go in a general reg.
2000 When -fpic is used, special handling is needed for symbolic references.
2001 See comments by legitimize_pic_address in i386.c for details. */
2003 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2005 (X) = legitimize_address ((X), (OLDX), (MODE)); \
2006 if (memory_address_p ((MODE), (X))) \
2010 #define REWRITE_ADDRESS(X) rewrite_address (X)
2012 /* Nonzero if the constant value X is a legitimate general operand
2013 when generating PIC code. It is given that flag_pic is on and
2014 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2016 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
2018 #define SYMBOLIC_CONST(X) \
2019 (GET_CODE (X) == SYMBOL_REF \
2020 || GET_CODE (X) == LABEL_REF \
2021 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2023 /* Go to LABEL if ADDR (a legitimate address expression)
2024 has an effect that depends on the machine mode it is used for.
2025 On the 80386, only postdecrement and postincrement address depend thus
2026 (the amount of decrement or increment being the length of the operand). */
2027 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2029 if (GET_CODE (ADDR) == POST_INC \
2030 || GET_CODE (ADDR) == POST_DEC) \
2034 /* Codes for all the SSE/MMX builtins. */
2046 IX86_BUILTIN_CMPEQPS,
2047 IX86_BUILTIN_CMPLTPS,
2048 IX86_BUILTIN_CMPLEPS,
2049 IX86_BUILTIN_CMPGTPS,
2050 IX86_BUILTIN_CMPGEPS,
2051 IX86_BUILTIN_CMPNEQPS,
2052 IX86_BUILTIN_CMPNLTPS,
2053 IX86_BUILTIN_CMPNLEPS,
2054 IX86_BUILTIN_CMPNGTPS,
2055 IX86_BUILTIN_CMPNGEPS,
2056 IX86_BUILTIN_CMPORDPS,
2057 IX86_BUILTIN_CMPUNORDPS,
2058 IX86_BUILTIN_CMPNEPS,
2059 IX86_BUILTIN_CMPEQSS,
2060 IX86_BUILTIN_CMPLTSS,
2061 IX86_BUILTIN_CMPLESS,
2062 IX86_BUILTIN_CMPNEQSS,
2063 IX86_BUILTIN_CMPNLTSS,
2064 IX86_BUILTIN_CMPNLESS,
2065 IX86_BUILTIN_CMPORDSS,
2066 IX86_BUILTIN_CMPUNORDSS,
2067 IX86_BUILTIN_CMPNESS,
2069 IX86_BUILTIN_COMIEQSS,
2070 IX86_BUILTIN_COMILTSS,
2071 IX86_BUILTIN_COMILESS,
2072 IX86_BUILTIN_COMIGTSS,
2073 IX86_BUILTIN_COMIGESS,
2074 IX86_BUILTIN_COMINEQSS,
2075 IX86_BUILTIN_UCOMIEQSS,
2076 IX86_BUILTIN_UCOMILTSS,
2077 IX86_BUILTIN_UCOMILESS,
2078 IX86_BUILTIN_UCOMIGTSS,
2079 IX86_BUILTIN_UCOMIGESS,
2080 IX86_BUILTIN_UCOMINEQSS,
2082 IX86_BUILTIN_CVTPI2PS,
2083 IX86_BUILTIN_CVTPS2PI,
2084 IX86_BUILTIN_CVTSI2SS,
2085 IX86_BUILTIN_CVTSI642SS,
2086 IX86_BUILTIN_CVTSS2SI,
2087 IX86_BUILTIN_CVTSS2SI64,
2088 IX86_BUILTIN_CVTTPS2PI,
2089 IX86_BUILTIN_CVTTSS2SI,
2090 IX86_BUILTIN_CVTTSS2SI64,
2097 IX86_BUILTIN_LOADAPS,
2098 IX86_BUILTIN_LOADUPS,
2099 IX86_BUILTIN_STOREAPS,
2100 IX86_BUILTIN_STOREUPS,
2101 IX86_BUILTIN_LOADSS,
2102 IX86_BUILTIN_STORESS,
2105 IX86_BUILTIN_MOVHLPS,
2106 IX86_BUILTIN_MOVLHPS,
2107 IX86_BUILTIN_LOADHPS,
2108 IX86_BUILTIN_LOADLPS,
2109 IX86_BUILTIN_STOREHPS,
2110 IX86_BUILTIN_STORELPS,
2112 IX86_BUILTIN_MASKMOVQ,
2113 IX86_BUILTIN_MOVMSKPS,
2114 IX86_BUILTIN_PMOVMSKB,
2116 IX86_BUILTIN_MOVNTPS,
2117 IX86_BUILTIN_MOVNTQ,
2119 IX86_BUILTIN_LOADDQA,
2120 IX86_BUILTIN_LOADDQU,
2121 IX86_BUILTIN_STOREDQA,
2122 IX86_BUILTIN_STOREDQU,
2125 IX86_BUILTIN_STORED,
2129 IX86_BUILTIN_PACKSSWB,
2130 IX86_BUILTIN_PACKSSDW,
2131 IX86_BUILTIN_PACKUSWB,
2137 IX86_BUILTIN_PADDSB,
2138 IX86_BUILTIN_PADDSW,
2139 IX86_BUILTIN_PADDUSB,
2140 IX86_BUILTIN_PADDUSW,
2145 IX86_BUILTIN_PSUBSB,
2146 IX86_BUILTIN_PSUBSW,
2147 IX86_BUILTIN_PSUBUSB,
2148 IX86_BUILTIN_PSUBUSW,
2158 IX86_BUILTIN_PCMPEQB,
2159 IX86_BUILTIN_PCMPEQW,
2160 IX86_BUILTIN_PCMPEQD,
2161 IX86_BUILTIN_PCMPGTB,
2162 IX86_BUILTIN_PCMPGTW,
2163 IX86_BUILTIN_PCMPGTD,
2165 IX86_BUILTIN_PEXTRW,
2166 IX86_BUILTIN_PINSRW,
2168 IX86_BUILTIN_PMADDWD,
2170 IX86_BUILTIN_PMAXSW,
2171 IX86_BUILTIN_PMAXUB,
2172 IX86_BUILTIN_PMINSW,
2173 IX86_BUILTIN_PMINUB,
2175 IX86_BUILTIN_PMULHUW,
2176 IX86_BUILTIN_PMULHW,
2177 IX86_BUILTIN_PMULLW,
2179 IX86_BUILTIN_PSADBW,
2180 IX86_BUILTIN_PSHUFW,
2190 IX86_BUILTIN_PSLLWI,
2191 IX86_BUILTIN_PSLLDI,
2192 IX86_BUILTIN_PSLLQI,
2193 IX86_BUILTIN_PSRAWI,
2194 IX86_BUILTIN_PSRADI,
2195 IX86_BUILTIN_PSRLWI,
2196 IX86_BUILTIN_PSRLDI,
2197 IX86_BUILTIN_PSRLQI,
2199 IX86_BUILTIN_PUNPCKHBW,
2200 IX86_BUILTIN_PUNPCKHWD,
2201 IX86_BUILTIN_PUNPCKHDQ,
2202 IX86_BUILTIN_PUNPCKLBW,
2203 IX86_BUILTIN_PUNPCKLWD,
2204 IX86_BUILTIN_PUNPCKLDQ,
2206 IX86_BUILTIN_SHUFPS,
2210 IX86_BUILTIN_RSQRTPS,
2211 IX86_BUILTIN_RSQRTSS,
2212 IX86_BUILTIN_SQRTPS,
2213 IX86_BUILTIN_SQRTSS,
2215 IX86_BUILTIN_UNPCKHPS,
2216 IX86_BUILTIN_UNPCKLPS,
2219 IX86_BUILTIN_ANDNPS,
2224 IX86_BUILTIN_LDMXCSR,
2225 IX86_BUILTIN_STMXCSR,
2226 IX86_BUILTIN_SFENCE,
2228 /* 3DNow! Original */
2230 IX86_BUILTIN_PAVGUSB,
2234 IX86_BUILTIN_PFCMPEQ,
2235 IX86_BUILTIN_PFCMPGE,
2236 IX86_BUILTIN_PFCMPGT,
2241 IX86_BUILTIN_PFRCPIT1,
2242 IX86_BUILTIN_PFRCPIT2,
2243 IX86_BUILTIN_PFRSQIT1,
2244 IX86_BUILTIN_PFRSQRT,
2246 IX86_BUILTIN_PFSUBR,
2248 IX86_BUILTIN_PMULHRW,
2250 /* 3DNow! Athlon Extensions */
2252 IX86_BUILTIN_PFNACC,
2253 IX86_BUILTIN_PFPNACC,
2255 IX86_BUILTIN_PSWAPDSI,
2256 IX86_BUILTIN_PSWAPDSF,
2258 IX86_BUILTIN_SSE_ZERO,
2259 IX86_BUILTIN_MMX_ZERO,
2271 IX86_BUILTIN_CMPEQPD,
2272 IX86_BUILTIN_CMPLTPD,
2273 IX86_BUILTIN_CMPLEPD,
2274 IX86_BUILTIN_CMPGTPD,
2275 IX86_BUILTIN_CMPGEPD,
2276 IX86_BUILTIN_CMPNEQPD,
2277 IX86_BUILTIN_CMPNLTPD,
2278 IX86_BUILTIN_CMPNLEPD,
2279 IX86_BUILTIN_CMPNGTPD,
2280 IX86_BUILTIN_CMPNGEPD,
2281 IX86_BUILTIN_CMPORDPD,
2282 IX86_BUILTIN_CMPUNORDPD,
2283 IX86_BUILTIN_CMPNEPD,
2284 IX86_BUILTIN_CMPEQSD,
2285 IX86_BUILTIN_CMPLTSD,
2286 IX86_BUILTIN_CMPLESD,
2287 IX86_BUILTIN_CMPNEQSD,
2288 IX86_BUILTIN_CMPNLTSD,
2289 IX86_BUILTIN_CMPNLESD,
2290 IX86_BUILTIN_CMPORDSD,
2291 IX86_BUILTIN_CMPUNORDSD,
2292 IX86_BUILTIN_CMPNESD,
2294 IX86_BUILTIN_COMIEQSD,
2295 IX86_BUILTIN_COMILTSD,
2296 IX86_BUILTIN_COMILESD,
2297 IX86_BUILTIN_COMIGTSD,
2298 IX86_BUILTIN_COMIGESD,
2299 IX86_BUILTIN_COMINEQSD,
2300 IX86_BUILTIN_UCOMIEQSD,
2301 IX86_BUILTIN_UCOMILTSD,
2302 IX86_BUILTIN_UCOMILESD,
2303 IX86_BUILTIN_UCOMIGTSD,
2304 IX86_BUILTIN_UCOMIGESD,
2305 IX86_BUILTIN_UCOMINEQSD,
2313 IX86_BUILTIN_ANDNPD,
2317 IX86_BUILTIN_SQRTPD,
2318 IX86_BUILTIN_SQRTSD,
2320 IX86_BUILTIN_UNPCKHPD,
2321 IX86_BUILTIN_UNPCKLPD,
2323 IX86_BUILTIN_SHUFPD,
2325 IX86_BUILTIN_LOADAPD,
2326 IX86_BUILTIN_LOADUPD,
2327 IX86_BUILTIN_STOREAPD,
2328 IX86_BUILTIN_STOREUPD,
2329 IX86_BUILTIN_LOADSD,
2330 IX86_BUILTIN_STORESD,
2333 IX86_BUILTIN_LOADHPD,
2334 IX86_BUILTIN_LOADLPD,
2335 IX86_BUILTIN_STOREHPD,
2336 IX86_BUILTIN_STORELPD,
2338 IX86_BUILTIN_CVTDQ2PD,
2339 IX86_BUILTIN_CVTDQ2PS,
2341 IX86_BUILTIN_CVTPD2DQ,
2342 IX86_BUILTIN_CVTPD2PI,
2343 IX86_BUILTIN_CVTPD2PS,
2344 IX86_BUILTIN_CVTTPD2DQ,
2345 IX86_BUILTIN_CVTTPD2PI,
2347 IX86_BUILTIN_CVTPI2PD,
2348 IX86_BUILTIN_CVTSI2SD,
2349 IX86_BUILTIN_CVTSI642SD,
2351 IX86_BUILTIN_CVTSD2SI,
2352 IX86_BUILTIN_CVTSD2SI64,
2353 IX86_BUILTIN_CVTSD2SS,
2354 IX86_BUILTIN_CVTSS2SD,
2355 IX86_BUILTIN_CVTTSD2SI,
2356 IX86_BUILTIN_CVTTSD2SI64,
2358 IX86_BUILTIN_CVTPS2DQ,
2359 IX86_BUILTIN_CVTPS2PD,
2360 IX86_BUILTIN_CVTTPS2DQ,
2362 IX86_BUILTIN_MOVNTI,
2363 IX86_BUILTIN_MOVNTPD,
2364 IX86_BUILTIN_MOVNTDQ,
2366 IX86_BUILTIN_SETPD1,
2369 IX86_BUILTIN_SETRPD,
2370 IX86_BUILTIN_LOADPD1,
2371 IX86_BUILTIN_LOADRPD,
2372 IX86_BUILTIN_STOREPD1,
2373 IX86_BUILTIN_STORERPD,
2376 IX86_BUILTIN_MASKMOVDQU,
2377 IX86_BUILTIN_MOVMSKPD,
2378 IX86_BUILTIN_PMOVMSKB128,
2379 IX86_BUILTIN_MOVQ2DQ,
2380 IX86_BUILTIN_MOVDQ2Q,
2382 IX86_BUILTIN_PACKSSWB128,
2383 IX86_BUILTIN_PACKSSDW128,
2384 IX86_BUILTIN_PACKUSWB128,
2386 IX86_BUILTIN_PADDB128,
2387 IX86_BUILTIN_PADDW128,
2388 IX86_BUILTIN_PADDD128,
2389 IX86_BUILTIN_PADDQ128,
2390 IX86_BUILTIN_PADDSB128,
2391 IX86_BUILTIN_PADDSW128,
2392 IX86_BUILTIN_PADDUSB128,
2393 IX86_BUILTIN_PADDUSW128,
2394 IX86_BUILTIN_PSUBB128,
2395 IX86_BUILTIN_PSUBW128,
2396 IX86_BUILTIN_PSUBD128,
2397 IX86_BUILTIN_PSUBQ128,
2398 IX86_BUILTIN_PSUBSB128,
2399 IX86_BUILTIN_PSUBSW128,
2400 IX86_BUILTIN_PSUBUSB128,
2401 IX86_BUILTIN_PSUBUSW128,
2403 IX86_BUILTIN_PAND128,
2404 IX86_BUILTIN_PANDN128,
2405 IX86_BUILTIN_POR128,
2406 IX86_BUILTIN_PXOR128,
2408 IX86_BUILTIN_PAVGB128,
2409 IX86_BUILTIN_PAVGW128,
2411 IX86_BUILTIN_PCMPEQB128,
2412 IX86_BUILTIN_PCMPEQW128,
2413 IX86_BUILTIN_PCMPEQD128,
2414 IX86_BUILTIN_PCMPGTB128,
2415 IX86_BUILTIN_PCMPGTW128,
2416 IX86_BUILTIN_PCMPGTD128,
2418 IX86_BUILTIN_PEXTRW128,
2419 IX86_BUILTIN_PINSRW128,
2421 IX86_BUILTIN_PMADDWD128,
2423 IX86_BUILTIN_PMAXSW128,
2424 IX86_BUILTIN_PMAXUB128,
2425 IX86_BUILTIN_PMINSW128,
2426 IX86_BUILTIN_PMINUB128,
2428 IX86_BUILTIN_PMULUDQ,
2429 IX86_BUILTIN_PMULUDQ128,
2430 IX86_BUILTIN_PMULHUW128,
2431 IX86_BUILTIN_PMULHW128,
2432 IX86_BUILTIN_PMULLW128,
2434 IX86_BUILTIN_PSADBW128,
2435 IX86_BUILTIN_PSHUFHW,
2436 IX86_BUILTIN_PSHUFLW,
2437 IX86_BUILTIN_PSHUFD,
2439 IX86_BUILTIN_PSLLW128,
2440 IX86_BUILTIN_PSLLD128,
2441 IX86_BUILTIN_PSLLQ128,
2442 IX86_BUILTIN_PSRAW128,
2443 IX86_BUILTIN_PSRAD128,
2444 IX86_BUILTIN_PSRLW128,
2445 IX86_BUILTIN_PSRLD128,
2446 IX86_BUILTIN_PSRLQ128,
2447 IX86_BUILTIN_PSLLDQI128,
2448 IX86_BUILTIN_PSLLWI128,
2449 IX86_BUILTIN_PSLLDI128,
2450 IX86_BUILTIN_PSLLQI128,
2451 IX86_BUILTIN_PSRAWI128,
2452 IX86_BUILTIN_PSRADI128,
2453 IX86_BUILTIN_PSRLDQI128,
2454 IX86_BUILTIN_PSRLWI128,
2455 IX86_BUILTIN_PSRLDI128,
2456 IX86_BUILTIN_PSRLQI128,
2458 IX86_BUILTIN_PUNPCKHBW128,
2459 IX86_BUILTIN_PUNPCKHWD128,
2460 IX86_BUILTIN_PUNPCKHDQ128,
2461 IX86_BUILTIN_PUNPCKHQDQ128,
2462 IX86_BUILTIN_PUNPCKLBW128,
2463 IX86_BUILTIN_PUNPCKLWD128,
2464 IX86_BUILTIN_PUNPCKLDQ128,
2465 IX86_BUILTIN_PUNPCKLQDQ128,
2467 IX86_BUILTIN_CLFLUSH,
2468 IX86_BUILTIN_MFENCE,
2469 IX86_BUILTIN_LFENCE,
2471 /* Prescott New Instructions. */
2472 IX86_BUILTIN_ADDSUBPS,
2473 IX86_BUILTIN_HADDPS,
2474 IX86_BUILTIN_HSUBPS,
2475 IX86_BUILTIN_MOVSHDUP,
2476 IX86_BUILTIN_MOVSLDUP,
2477 IX86_BUILTIN_ADDSUBPD,
2478 IX86_BUILTIN_HADDPD,
2479 IX86_BUILTIN_HSUBPD,
2480 IX86_BUILTIN_LOADDDUP,
2481 IX86_BUILTIN_MOVDDUP,
2484 IX86_BUILTIN_MONITOR,
2490 /* Max number of args passed in registers. If this is more than 3, we will
2491 have problems with ebx (register #4), since it is a caller save register and
2492 is also used as the pic register in ELF. So for now, don't allow more than
2493 3 registers to be passed in registers. */
2495 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2497 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : (TARGET_SSE ? 3 : 0))
2499 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0))
2502 /* Specify the machine mode that this machine uses
2503 for the index in the tablejump instruction. */
2504 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2506 /* Define this as 1 if `char' should by default be signed; else as 0. */
2507 #define DEFAULT_SIGNED_CHAR 1
2509 /* Number of bytes moved into a data cache for a single prefetch operation. */
2510 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2512 /* Number of prefetch operations that can be done in parallel. */
2513 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2515 /* Max number of bytes we can move from memory to memory
2516 in one reasonably fast instruction. */
2519 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2520 move efficiently, as opposed to MOVE_MAX which is the maximum
2521 number of bytes we can move with a single instruction. */
2522 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2524 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2525 move-instruction pairs, we will do a movmem or libcall instead.
2526 Increasing the value will always make code faster, but eventually
2527 incurs high cost in increased code size.
2529 If you don't define this, a reasonable default is used. */
2531 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2533 /* Define if shifts truncate the shift count
2534 which implies one can omit a sign-extension or zero-extension
2535 of a shift count. */
2536 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2538 /* #define SHIFT_COUNT_TRUNCATED */
2540 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2541 is done just by pretending it is already truncated. */
2542 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2544 /* A macro to update M and UNSIGNEDP when an object whose type is
2545 TYPE and which has the specified mode and signedness is to be
2546 stored in a register. This macro is only called when TYPE is a
2549 On i386 it is sometimes useful to promote HImode and QImode
2550 quantities to SImode. The choice depends on target type. */
2552 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2554 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2555 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2559 /* Specify the machine mode that pointers have.
2560 After generation of rtl, the compiler makes no further distinction
2561 between pointers and any other objects of this machine mode. */
2562 #define Pmode (TARGET_64BIT ? DImode : SImode)
2564 /* A function address in a call instruction
2565 is a byte address (for indexing purposes)
2566 so give the MEM rtx a byte's mode. */
2567 #define FUNCTION_MODE QImode
2569 /* A C expression for the cost of moving data from a register in class FROM to
2570 one in class TO. The classes are expressed using the enumeration values
2571 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2572 interpreted relative to that.
2574 It is not required that the cost always equal 2 when FROM is the same as TO;
2575 on some machines it is expensive to move between registers if they are not
2576 general registers. */
2578 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2579 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2581 /* A C expression for the cost of moving data of mode M between a
2582 register and memory. A value of 2 is the default; this cost is
2583 relative to those in `REGISTER_MOVE_COST'.
2585 If moving between registers and memory is more expensive than
2586 between two registers, you should define this macro to express the
2589 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2590 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2592 /* A C expression for the cost of a branch instruction. A value of 1
2593 is the default; other values are interpreted relative to that. */
2595 #define BRANCH_COST ix86_branch_cost
2597 /* Define this macro as a C expression which is nonzero if accessing
2598 less than a word of memory (i.e. a `char' or a `short') is no
2599 faster than accessing a word of memory, i.e., if such access
2600 require more than one instruction or if there is no difference in
2601 cost between byte and (aligned) word loads.
2603 When this macro is not defined, the compiler will access a field by
2604 finding the smallest containing object; when it is defined, a
2605 fullword load will be used if alignment permits. Unless bytes
2606 accesses are faster than word accesses, using word accesses is
2607 preferable since it may eliminate subsequent memory access if
2608 subsequent accesses occur to other fields in the same word of the
2609 structure, but to different bytes. */
2611 #define SLOW_BYTE_ACCESS 0
2613 /* Nonzero if access to memory by shorts is slow and undesirable. */
2614 #define SLOW_SHORT_ACCESS 0
2616 /* Define this macro to be the value 1 if unaligned accesses have a
2617 cost many times greater than aligned accesses, for example if they
2618 are emulated in a trap handler.
2620 When this macro is nonzero, the compiler will act as if
2621 `STRICT_ALIGNMENT' were nonzero when generating code for block
2622 moves. This can cause significantly more instructions to be
2623 produced. Therefore, do not set this macro nonzero if unaligned
2624 accesses only add a cycle or two to the time for a memory access.
2626 If the value of this macro is always zero, it need not be defined. */
2628 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2630 /* Define this macro if it is as good or better to call a constant
2631 function address than to call an address kept in a register.
2633 Desirable on the 386 because a CALL with a constant address is
2634 faster than one with a register address. */
2636 #define NO_FUNCTION_CSE
2638 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2639 return the mode to be used for the comparison.
2641 For floating-point equality comparisons, CCFPEQmode should be used.
2642 VOIDmode should be used in all other cases.
2644 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2645 possible, to allow for more combinations. */
2647 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2649 /* Return nonzero if MODE implies a floating point inequality can be
2652 #define REVERSIBLE_CC_MODE(MODE) 1
2654 /* A C expression whose value is reversed condition code of the CODE for
2655 comparison done in CC_MODE mode. */
2656 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
2659 /* Control the assembler format that we output, to the extent
2660 this does not vary between assemblers. */
2662 /* How to refer to registers in assembler output.
2663 This sequence is indexed by compiler's hard-register-number (see above). */
2665 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2666 For non floating point regs, the following are the HImode names.
2668 For float regs, the stack top is sometimes referred to as "%st(0)"
2669 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */
2671 #define HI_REGISTER_NAMES \
2672 {"ax","dx","cx","bx","si","di","bp","sp", \
2673 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
2674 "argp", "flags", "fpsr", "dirflag", "frame", \
2675 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2676 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2677 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2678 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2680 #define REGISTER_NAMES HI_REGISTER_NAMES
2682 /* Table of additional register names to use in user input. */
2684 #define ADDITIONAL_REGISTER_NAMES \
2685 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2686 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2687 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2688 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2689 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2690 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2691 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2692 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2694 /* Note we are omitting these since currently I don't know how
2695 to get gcc to use these, since they want the same but different
2696 number as al, and ax.
2699 #define QI_REGISTER_NAMES \
2700 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2702 /* These parallel the array above, and can be used to access bits 8:15
2703 of regs 0 through 3. */
2705 #define QI_HIGH_REGISTER_NAMES \
2706 {"ah", "dh", "ch", "bh", }
2708 /* How to renumber registers for dbx and gdb. */
2710 #define DBX_REGISTER_NUMBER(N) \
2711 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2713 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2714 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2715 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2717 /* Before the prologue, RA is at 0(%esp). */
2718 #define INCOMING_RETURN_ADDR_RTX \
2719 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2721 /* After the prologue, RA is at -4(AP) in the current frame. */
2722 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2724 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2725 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2727 /* PC is dbx register 8; let's use that column for RA. */
2728 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2730 /* Before the prologue, the top of the frame is at 4(%esp). */
2731 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2733 /* Describe how we implement __builtin_eh_return. */
2734 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2735 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2738 /* Select a format to encode pointers in exception handling data. CODE
2739 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2740 true if the symbol may be affected by dynamic relocations.
2742 ??? All x86 object file formats are capable of representing this.
2743 After all, the relocation needed is the same as for the call insn.
2744 Whether or not a particular assembler allows us to enter such, I
2745 guess we'll have to see. */
2746 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2748 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2751 /* This is how to output an insn to push a register on the stack.
2752 It need not be very fast code. */
2754 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2757 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
2758 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2760 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
2763 /* This is how to output an insn to pop a register from the stack.
2764 It need not be very fast code. */
2766 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2769 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
2770 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
2772 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
2775 /* This is how to output an element of a case-vector that is absolute. */
2777 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2778 ix86_output_addr_vec_elt ((FILE), (VALUE))
2780 /* This is how to output an element of a case-vector that is relative. */
2782 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2783 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2785 /* Under some conditions we need jump tables in the text section, because
2786 the assembler cannot handle label differences between sections. */
2788 #define JUMP_TABLES_IN_TEXT_SECTION \
2789 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2791 /* A C statement that outputs an address constant appropriate to
2792 for DWARF debugging. */
2794 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
2795 i386_dwarf_output_addr_const ((FILE), (X))
2797 /* Emit a dtp-relative reference to a TLS variable. */
2800 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
2801 i386_output_dwarf_dtprel (FILE, SIZE, X)
2804 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2805 and switch back. For x86 we do this only to save a few bytes that
2806 would otherwise be unused in the text section. */
2807 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2808 asm (SECTION_OP "\n\t" \
2809 "call " USER_LABEL_PREFIX #FUNC "\n" \
2810 TEXT_SECTION_ASM_OP);
2812 /* Print operand X (an rtx) in assembler syntax to file FILE.
2813 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2814 Effect of various CODE letters is described in i386.c near
2815 print_operand function. */
2817 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2818 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
2820 #define PRINT_OPERAND(FILE, X, CODE) \
2821 print_operand ((FILE), (X), (CODE))
2823 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2824 print_operand_address ((FILE), (ADDR))
2826 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
2828 if (! output_addr_const_extra (FILE, (X))) \
2832 /* a letter which is not needed by the normal asm syntax, which
2833 we can use for operand syntax in the extended asm */
2835 #define ASM_OPERAND_LETTER '#'
2836 #define RET return ""
2837 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
2839 /* Define the codes that are matched by predicates in i386.c. */
2841 #define PREDICATE_CODES \
2842 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
2843 SYMBOL_REF, LABEL_REF, CONST}}, \
2844 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
2845 SYMBOL_REF, LABEL_REF, CONST}}, \
2846 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
2847 SYMBOL_REF, LABEL_REF, CONST}}, \
2848 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
2849 SYMBOL_REF, LABEL_REF, CONST}}, \
2850 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
2851 SYMBOL_REF, LABEL_REF, CONST}}, \
2852 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
2853 SYMBOL_REF, LABEL_REF, CONST}}, \
2854 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
2855 SYMBOL_REF, LABEL_REF}}, \
2856 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
2857 {"const_int_1_31_operand", {CONST_INT}}, \
2858 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2859 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2860 LABEL_REF, SUBREG, REG, MEM}}, \
2861 {"pic_symbolic_operand", {CONST}}, \
2862 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
2863 {"sibcall_insn_operand", {REG, SUBREG, SYMBOL_REF}}, \
2864 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
2865 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
2866 {"const1_operand", {CONST_INT}}, \
2867 {"const248_operand", {CONST_INT}}, \
2868 {"const_0_to_3_operand", {CONST_INT}}, \
2869 {"const_0_to_7_operand", {CONST_INT}}, \
2870 {"const_0_to_15_operand", {CONST_INT}}, \
2871 {"const_0_to_255_operand", {CONST_INT}}, \
2872 {"incdec_operand", {CONST_INT}}, \
2873 {"mmx_reg_operand", {REG}}, \
2874 {"reg_no_sp_operand", {SUBREG, REG}}, \
2875 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
2876 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
2877 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
2878 {"index_register_operand", {SUBREG, REG}}, \
2879 {"flags_reg_operand", {REG}}, \
2880 {"q_regs_operand", {SUBREG, REG}}, \
2881 {"non_q_regs_operand", {SUBREG, REG}}, \
2882 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
2883 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
2884 GE, UNGE, LTGT, UNEQ}}, \
2885 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
2886 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
2888 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
2889 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
2890 UNGE, UNGT, LTGT, UNEQ }}, \
2891 {"ix86_carry_flag_operator", {LTU, LT, UNLT, GT, UNGT, LE, UNLE, \
2892 GE, UNGE, LTGT, UNEQ}}, \
2893 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
2894 {"ext_register_operand", {SUBREG, REG}}, \
2895 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
2896 {"mult_operator", {MULT}}, \
2897 {"div_operator", {DIV}}, \
2898 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
2899 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
2900 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
2901 LSHIFTRT, ROTATERT}}, \
2902 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
2903 {"memory_displacement_operand", {MEM}}, \
2904 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2905 LABEL_REF, SUBREG, REG, MEM, AND}}, \
2906 {"long_memory_operand", {MEM}}, \
2907 {"tls_symbolic_operand", {SYMBOL_REF}}, \
2908 {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \
2909 {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \
2910 {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \
2911 {"local_exec_symbolic_operand", {SYMBOL_REF}}, \
2912 {"any_fp_register_operand", {REG}}, \
2913 {"register_and_not_any_fp_reg_operand", {REG}}, \
2914 {"fp_register_operand", {REG}}, \
2915 {"register_and_not_fp_reg_operand", {REG}}, \
2916 {"zero_extended_scalar_load_operand", {MEM}}, \
2917 {"vector_move_operand", {CONST_VECTOR, SUBREG, REG, MEM}}, \
2918 {"no_seg_address_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2919 LABEL_REF, SUBREG, REG, MEM, PLUS, MULT}},
2921 /* A list of predicates that do special things with modes, and so
2922 should not elicit warnings for VOIDmode match_operand. */
2924 #define SPECIAL_MODE_PREDICATES \
2925 "ext_register_operand",
2927 /* Which processor to schedule for. The cpu attribute defines a list that
2928 mirrors this list, so changes to i386.md must be made at the same time. */
2932 PROCESSOR_I386, /* 80386 */
2933 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
2935 PROCESSOR_PENTIUMPRO,
2944 extern enum processor_type ix86_tune;
2945 extern const char *ix86_tune_string;
2947 extern enum processor_type ix86_arch;
2948 extern const char *ix86_arch_string;
2956 extern enum fpmath_unit ix86_fpmath;
2957 extern const char *ix86_fpmath_string;
2965 extern enum tls_dialect ix86_tls_dialect;
2966 extern const char *ix86_tls_dialect_string;
2969 CM_32, /* The traditional 32-bit ABI. */
2970 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
2971 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
2972 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
2973 CM_LARGE, /* No assumptions. */
2974 CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */
2977 extern enum cmodel ix86_cmodel;
2978 extern const char *ix86_cmodel_string;
2980 /* Size of the RED_ZONE area. */
2981 #define RED_ZONE_SIZE 128
2982 /* Reserved area of the red zone for temporaries. */
2983 #define RED_ZONE_RESERVE 8
2990 extern const char *ix86_asm_string;
2991 extern enum asm_dialect ix86_asm_dialect;
2993 extern int ix86_regparm;
2994 extern const char *ix86_regparm_string;
2996 extern int ix86_preferred_stack_boundary;
2997 extern const char *ix86_preferred_stack_boundary_string;
2999 extern int ix86_branch_cost;
3000 extern const char *ix86_branch_cost_string;
3002 extern const char *ix86_debug_arg_string;
3003 extern const char *ix86_debug_addr_string;
3005 /* Obsoleted by -f options. Remove before 3.2 ships. */
3006 extern const char *ix86_align_loops_string;
3007 extern const char *ix86_align_jumps_string;
3008 extern const char *ix86_align_funcs_string;
3010 /* Smallest class containing REGNO. */
3011 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
3013 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3014 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3016 /* To properly truncate FP values into integers, we need to set i387 control
3017 word. We can't emit proper mode switching code before reload, as spills
3018 generated by reload may truncate values incorrectly, but we still can avoid
3019 redundant computation of new control word by the mode switching pass.
3020 The fldcw instructions are still emitted redundantly, but this is probably
3021 not going to be noticeable problem, as most CPUs do have fast path for
3024 The machinery is to emit simple truncation instructions and split them
3025 before reload to instructions having USEs of two memory locations that
3026 are filled by this code to old and new control word.
3028 Post-reload pass may be later used to eliminate the redundant fildcw if
3031 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3033 /* Define this macro if the port needs extra instructions inserted
3034 for mode switching in an optimizing compilation. */
3036 #define OPTIMIZE_MODE_SWITCHING(ENTITY) ix86_optimize_mode_switching
3038 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3039 initializer for an array of integers. Each initializer element N
3040 refers to an entity that needs mode switching, and specifies the
3041 number of different modes that might need to be set for this
3042 entity. The position of the initializer in the initializer -
3043 starting counting at zero - determines the integer that is used to
3044 refer to the mode-switched entity in question. */
3046 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3048 /* ENTITY is an integer specifying a mode-switched entity. If
3049 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3050 return an integer value not larger than the corresponding element
3051 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3052 must be switched into prior to the execution of INSN. */
3054 #define MODE_NEEDED(ENTITY, I) \
3055 (GET_CODE (I) == CALL_INSN \
3056 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3057 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3058 ? FP_CW_UNINITIALIZED \
3059 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3063 /* This macro specifies the order in which modes for ENTITY are
3064 processed. 0 is the highest priority. */
3066 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3068 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3069 is the set of hard registers live at the point where the insn(s)
3070 are to be inserted. */
3072 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3073 ((MODE) == FP_CW_STORED \
3074 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3075 assign_386_stack_local (HImode, 2)), 0\
3078 /* Avoid renaming of stack registers, as doing so in combination with
3079 scheduling just increases amount of live registers at time and in
3080 the turn amount of fxch instructions needed.
3082 ??? Maybe Pentium chips benefits from renaming, someone can try.... */
3084 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3085 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
3088 #define DLL_IMPORT_EXPORT_PREFIX '#'
3090 #define FASTCALL_PREFIX '@'
3092 struct machine_function GTY(())
3094 struct stack_local_entry *stack_locals;
3095 const char *some_ld_name;
3096 int save_varrargs_registers;
3097 int accesses_prev_frame;
3098 int optimize_mode_switching;
3099 /* Set by ix86_compute_frame_layout and used by prologue/epilogue expander to
3100 determine the style used. */
3101 int use_fast_prologue_epilogue;
3102 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE has been computed
3104 int use_fast_prologue_epilogue_nregs;
3107 #define ix86_stack_locals (cfun->machine->stack_locals)
3108 #define ix86_save_varrargs_registers (cfun->machine->save_varrargs_registers)
3109 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching)
3111 /* Control behavior of x86_file_start. */
3112 #define X86_FILE_START_VERSION_DIRECTIVE false
3113 #define X86_FILE_START_FLTUSED false
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