1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Define the specific costs for a given cpu */
39 struct processor_costs {
40 const int add; /* cost of an add instruction */
41 const int lea; /* cost of a lea instruction */
42 const int shift_var; /* variable shift costs */
43 const int shift_const; /* constant shift costs */
44 const int mult_init; /* cost of starting a multiply */
45 const int mult_bit; /* cost of multiply per each bit set */
46 const int divide; /* cost of a divide/mod */
47 int movsx; /* The cost of movsx operation. */
48 int movzx; /* The cost of movzx operation. */
49 const int large_insn; /* insns larger than this cost more */
50 const int move_ratio; /* The threshold of number of scalar
51 memory-to-memory move insns. */
52 const int movzbl_load; /* cost of loading using movzbl */
53 const int int_load[3]; /* cost of loading integer registers
54 in QImode, HImode and SImode relative
55 to reg-reg move (2). */
56 const int int_store[3]; /* cost of storing integer register
57 in QImode, HImode and SImode */
58 const int fp_move; /* cost of reg,reg fld/fst */
59 const int fp_load[3]; /* cost of loading FP register
60 in SFmode, DFmode and XFmode */
61 const int fp_store[3]; /* cost of storing FP register
62 in SFmode, DFmode and XFmode */
63 const int mmx_move; /* cost of moving MMX register. */
64 const int mmx_load[2]; /* cost of loading MMX register
65 in SImode and DImode */
66 const int mmx_store[2]; /* cost of storing MMX register
67 in SImode and DImode */
68 const int sse_move; /* cost of moving SSE register. */
69 const int sse_load[3]; /* cost of loading SSE register
70 in SImode, DImode and TImode*/
71 const int sse_store[3]; /* cost of storing SSE register
72 in SImode, DImode and TImode*/
73 const int mmxsse_to_integer; /* cost of moving mmxsse register to
74 integer and vice versa. */
75 const int prefetch_block; /* bytes moved to cache for prefetch. */
76 const int simultaneous_prefetches; /* number of parallel prefetch
78 const int fadd; /* cost of FADD and FSUB instructions. */
79 const int fmul; /* cost of FMUL instruction. */
80 const int fdiv; /* cost of FDIV instruction. */
81 const int fabs; /* cost of FABS instruction. */
82 const int fchs; /* cost of FCHS instruction. */
83 const int fsqrt; /* cost of FSQRT instruction. */
86 extern const struct processor_costs *ix86_cost;
88 /* Run-time compilation parameters selecting different hardware subsets. */
90 extern int target_flags;
92 /* Macros used in the machine description to test the flags. */
94 /* configure can arrange to make this 2, to force a 486. */
96 #ifndef TARGET_CPU_DEFAULT
97 #define TARGET_CPU_DEFAULT 0
100 /* Masks for the -m switches */
101 #define MASK_80387 0x00000001 /* Hardware floating point */
102 #define MASK_RTD 0x00000002 /* Use ret that pops args */
103 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
104 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
105 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
106 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
107 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
108 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
109 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
110 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
111 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
112 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
113 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
114 #define MASK_MMX 0x00002000 /* Support MMX regs/builtins */
115 #define MASK_SSE 0x00004000 /* Support SSE regs/builtins */
116 #define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */
117 #define MASK_3DNOW 0x00010000 /* Support 3Dnow builtins */
118 #define MASK_3DNOW_A 0x00020000 /* Support Athlon 3Dnow builtins */
119 #define MASK_128BIT_LONG_DOUBLE 0x00040000 /* long double size is 128bit */
120 #define MASK_64BIT 0x00080000 /* Produce 64bit code */
122 /* Unused: 0x03f0000 */
124 /* ... overlap with subtarget options starts by 0x04000000. */
125 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
127 /* Use the floating point instructions */
128 #define TARGET_80387 (target_flags & MASK_80387)
130 /* Compile using ret insn that pops args.
131 This will not work unless you use prototypes at least
132 for all functions that can take varying numbers of args. */
133 #define TARGET_RTD (target_flags & MASK_RTD)
135 /* Align doubles to a two word boundary. This breaks compatibility with
136 the published ABI's for structures containing doubles, but produces
137 faster code on the pentium. */
138 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
140 /* Use push instructions to save outgoing args. */
141 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
143 /* Accumulate stack adjustments to prologue/epilogue. */
144 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
145 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
147 /* Put uninitialized locals into bss, not data.
148 Meaningful only on svr3. */
149 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
151 /* Use IEEE floating point comparisons. These handle correctly the cases
152 where the result of a comparison is unordered. Normally SIGFPE is
153 generated in such cases, in which case this isn't needed. */
154 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
156 /* Functions that return a floating point value may return that value
157 in the 387 FPU or in 386 integer registers. If set, this flag causes
158 the 387 to be used, which is compatible with most calling conventions. */
159 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
161 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
162 This mode wastes cache, but avoid misaligned data accesses and simplifies
163 address calculations. */
164 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
166 /* Disable generation of FP sin, cos and sqrt operations for 387.
167 This is because FreeBSD lacks these in the math-emulator-code */
168 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
170 /* Don't create frame pointers for leaf functions */
171 #define TARGET_OMIT_LEAF_FRAME_POINTER \
172 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
174 /* Debug GO_IF_LEGITIMATE_ADDRESS */
175 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
177 /* Debug FUNCTION_ARG macros */
178 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
180 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a
181 compile-time constant. */
184 #define TARGET_64BIT 1
186 #define TARGET_64BIT 0
189 #ifdef TARGET_BI_ARCH
190 #define TARGET_64BIT (target_flags & MASK_64BIT)
192 #if TARGET_64BIT_DEFAULT
193 #define TARGET_64BIT 1
195 #define TARGET_64BIT 0
200 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
201 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
202 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
203 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
204 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
205 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
206 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
208 #define CPUMASK (1 << ix86_cpu)
209 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
210 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
211 extern const int x86_branch_hints, x86_unroll_strlen;
212 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
213 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
214 extern const int x86_use_cltd, x86_read_modify_write;
215 extern const int x86_read_modify, x86_split_long_moves;
216 extern const int x86_promote_QImode, x86_single_stringop, x86_fast_prefix;
217 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
218 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
219 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
220 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
221 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
222 extern const int x86_epilogue_using_move, x86_decompose_lea;
223 extern const int x86_arch_always_fancy_math_387, x86_shift1;
224 extern int x86_prefetch_sse;
226 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
227 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
228 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
229 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
230 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
231 /* For sane SSE instruction set generation we need fcomi instruction. It is
232 safe to enable all CMOVE instructions. */
233 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
234 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
235 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
236 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
237 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
238 #define TARGET_MOVX (x86_movx & CPUMASK)
239 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
240 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
241 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
242 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
243 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
244 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
245 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
246 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
247 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
248 #define TARGET_FAST_PREFIX (x86_fast_prefix & CPUMASK)
249 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
250 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
251 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
252 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
253 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
254 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
255 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
256 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
257 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
258 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
259 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
260 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
261 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
262 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
263 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
264 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
265 #define TARGET_SHIFT1 (x86_shift1 & CPUMASK)
267 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
269 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
270 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
272 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
274 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
275 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
276 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
277 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
278 && (ix86_fpmath & FPMATH_387))
279 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
280 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
281 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
283 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
285 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU)
286 #define TARGET_SUN_TLS (ix86_tls_dialect == TLS_DIALECT_SUN)
288 /* WARNING: Do not mark empty strings for translation, as calling
289 gettext on an empty string does NOT return an empty
293 #define TARGET_SWITCHES \
294 { { "80387", MASK_80387, N_("Use hardware fp") }, \
295 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
296 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
297 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
298 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
299 { "386", 0, "" /*Deprecated.*/}, \
300 { "486", 0, "" /*Deprecated.*/}, \
301 { "pentium", 0, "" /*Deprecated.*/}, \
302 { "pentiumpro", 0, "" /*Deprecated.*/}, \
303 { "intel-syntax", 0, "" /*Deprecated.*/}, \
304 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
306 N_("Alternate calling convention") }, \
307 { "no-rtd", -MASK_RTD, \
308 N_("Use normal calling convention") }, \
309 { "align-double", MASK_ALIGN_DOUBLE, \
310 N_("Align some doubles on dword boundary") }, \
311 { "no-align-double", -MASK_ALIGN_DOUBLE, \
312 N_("Align doubles on word boundary") }, \
313 { "svr3-shlib", MASK_SVR3_SHLIB, \
314 N_("Uninitialized locals in .bss") }, \
315 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
316 N_("Uninitialized locals in .data") }, \
317 { "ieee-fp", MASK_IEEE_FP, \
318 N_("Use IEEE math for fp comparisons") }, \
319 { "no-ieee-fp", -MASK_IEEE_FP, \
320 N_("Do not use IEEE math for fp comparisons") }, \
321 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
322 N_("Return values of functions in FPU registers") }, \
323 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
324 N_("Do not return values of functions in FPU registers")}, \
325 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
326 N_("Do not generate sin, cos, sqrt for FPU") }, \
327 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
328 N_("Generate sin, cos, sqrt for FPU")}, \
329 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
330 N_("Omit the frame pointer in leaf functions") }, \
331 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
332 { "stack-arg-probe", MASK_STACK_PROBE, \
333 N_("Enable stack probing") }, \
334 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
335 { "windows", 0, 0 /* undocumented */ }, \
336 { "dll", 0, 0 /* undocumented */ }, \
337 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
338 N_("Align destination of the string operations") }, \
339 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
340 N_("Do not align destination of the string operations") }, \
341 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
342 N_("Inline all known string operations") }, \
343 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
344 N_("Do not inline all known string operations") }, \
345 { "push-args", -MASK_NO_PUSH_ARGS, \
346 N_("Use push instructions to save outgoing arguments") }, \
347 { "no-push-args", MASK_NO_PUSH_ARGS, \
348 N_("Do not use push instructions to save outgoing arguments") }, \
349 { "accumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS, \
350 N_("Use push instructions to save outgoing arguments") }, \
351 { "no-accumulate-outgoing-args",-MASK_ACCUMULATE_OUTGOING_ARGS, \
352 N_("Do not use push instructions to save outgoing arguments") }, \
354 N_("Support MMX built-in functions") }, \
355 { "no-mmx", -MASK_MMX, \
356 N_("Do not support MMX built-in functions") }, \
357 { "3dnow", MASK_3DNOW, \
358 N_("Support 3DNow! built-in functions") }, \
359 { "no-3dnow", -MASK_3DNOW, \
360 N_("Do not support 3DNow! built-in functions") }, \
362 N_("Support MMX and SSE built-in functions and code generation") }, \
363 { "no-sse", -MASK_SSE, \
364 N_("Do not support MMX and SSE built-in functions and code generation") },\
365 { "sse2", MASK_SSE2, \
366 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
367 { "no-sse2", -MASK_SSE2, \
368 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
369 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
370 N_("sizeof(long double) is 16") }, \
371 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
372 N_("sizeof(long double) is 12") }, \
373 { "64", MASK_64BIT, \
374 N_("Generate 64bit x86-64 code") }, \
375 { "32", -MASK_64BIT, \
376 N_("Generate 32bit i386 code") }, \
377 { "red-zone", -MASK_NO_RED_ZONE, \
378 N_("Use red-zone in the x86-64 code") }, \
379 { "no-red-zone", MASK_NO_RED_ZONE, \
380 N_("Do not use red-zone in the x86-64 code") }, \
382 { "", TARGET_DEFAULT | TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_DEFAULT, 0 }}
384 #ifndef TARGET_64BIT_DEFAULT
385 #define TARGET_64BIT_DEFAULT 0
388 /* Once GDB has been enhanced to deal with functions without frame
389 pointers, we can change this to allow for elimination of
390 the frame pointer in leaf functions. */
391 #define TARGET_DEFAULT 0
393 /* This is not really a target flag, but is done this way so that
394 it's analogous to similar code for Mach-O on PowerPC. darwin.h
395 redefines this to 1. */
396 #define TARGET_MACHO 0
398 /* This macro is similar to `TARGET_SWITCHES' but defines names of
399 command options that have values. Its definition is an
400 initializer with a subgrouping for each command option.
402 Each subgrouping contains a string constant, that defines the
403 fixed part of the option name, and the address of a variable. The
404 variable, type `char *', is set to the variable part of the given
405 option if the fixed part matches. The actual option name is made
406 by appending `-m' to the specified name. */
407 #define TARGET_OPTIONS \
408 { { "cpu=", &ix86_cpu_string, \
409 N_("Schedule code for given CPU")}, \
410 { "fpmath=", &ix86_fpmath_string, \
411 N_("Generate floating point mathematics using given instruction set")},\
412 { "arch=", &ix86_arch_string, \
413 N_("Generate code for given CPU")}, \
414 { "regparm=", &ix86_regparm_string, \
415 N_("Number of registers used to pass integer arguments") }, \
416 { "align-loops=", &ix86_align_loops_string, \
417 N_("Loop code aligned to this power of 2") }, \
418 { "align-jumps=", &ix86_align_jumps_string, \
419 N_("Jump targets are aligned to this power of 2") }, \
420 { "align-functions=", &ix86_align_funcs_string, \
421 N_("Function starts are aligned to this power of 2") }, \
422 { "preferred-stack-boundary=", \
423 &ix86_preferred_stack_boundary_string, \
424 N_("Attempt to keep stack aligned to this power of 2") }, \
425 { "branch-cost=", &ix86_branch_cost_string, \
426 N_("Branches are this expensive (1-5, arbitrary units)") }, \
427 { "cmodel=", &ix86_cmodel_string, \
428 N_("Use given x86-64 code model") }, \
429 { "debug-arg", &ix86_debug_arg_string, \
430 "" /* Undocumented. */ }, \
431 { "debug-addr", &ix86_debug_addr_string, \
432 "" /* Undocumented. */ }, \
433 { "asm=", &ix86_asm_string, \
434 N_("Use given assembler dialect") }, \
435 { "tls-dialect=", &ix86_tls_dialect_string, \
436 N_("Use given thread-local storage dialect") }, \
440 /* Sometimes certain combinations of command options do not make
441 sense on a particular target machine. You can define a macro
442 `OVERRIDE_OPTIONS' to take account of this. This macro, if
443 defined, is executed once just after all the command options have
446 Don't use this macro to turn on various extra optimizations for
447 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
449 #define OVERRIDE_OPTIONS override_options ()
451 /* These are meant to be redefined in the host dependent files */
452 #define SUBTARGET_SWITCHES
453 #define SUBTARGET_OPTIONS
455 /* Define this to change the optimizations performed by default. */
456 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
457 optimization_options ((LEVEL), (SIZE))
459 /* Specs for the compiler proper */
462 #define CC1_CPU_SPEC "\
465 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
467 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
468 %{mpentium:-mcpu=pentium \
469 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
470 %{mpentiumpro:-mcpu=pentiumpro \
471 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
472 %{mintel-syntax:-masm=intel \
473 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
474 %{mno-intel-syntax:-masm=att \
475 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
478 /* Target CPU builtins. */
479 #define TARGET_CPU_CPP_BUILTINS() \
482 size_t arch_len = strlen (ix86_arch_string); \
483 size_t cpu_len = strlen (ix86_cpu_string); \
484 int last_arch_char = ix86_arch_string[arch_len - 1]; \
485 int last_cpu_char = ix86_cpu_string[cpu_len - 1]; \
489 builtin_assert ("cpu=x86_64"); \
490 builtin_assert ("machine=x86_64"); \
491 builtin_define ("__x86_64"); \
492 builtin_define ("__x86_64__"); \
496 builtin_assert ("cpu=i386"); \
497 builtin_assert ("machine=i386"); \
498 builtin_define_std ("i386"); \
501 /* Built-ins based on -mcpu= (or -march= if no \
504 builtin_define ("__tune_i386__"); \
505 else if (TARGET_486) \
506 builtin_define ("__tune_i486__"); \
507 else if (TARGET_PENTIUM) \
509 builtin_define ("__tune_i586__"); \
510 builtin_define ("__tune_pentium__"); \
511 if (last_cpu_char == 'x') \
512 builtin_define ("__tune_pentium_mmx__"); \
514 else if (TARGET_PENTIUMPRO) \
516 builtin_define ("__tune_i686__"); \
517 builtin_define ("__tune_pentiumpro__"); \
519 else if (TARGET_K6) \
521 builtin_define ("__tune_k6__"); \
522 if (last_cpu_char == '2') \
523 builtin_define ("__tune_k6_2__"); \
524 else if (last_cpu_char == '3') \
525 builtin_define ("__tune_k6_3__"); \
527 else if (TARGET_ATHLON) \
529 builtin_define ("__tune_athlon__"); \
530 /* Only plain "athlon" lacks SSE. */ \
531 if (last_cpu_char != 'n') \
532 builtin_define ("__tune_athlon_sse__"); \
534 else if (TARGET_PENTIUM4) \
535 builtin_define ("__tune_pentium4__"); \
538 builtin_define ("__MMX__"); \
540 builtin_define ("__3dNOW__"); \
541 if (TARGET_3DNOW_A) \
542 builtin_define ("__3dNOW_A__"); \
544 builtin_define ("__SSE__"); \
546 builtin_define ("__SSE2__"); \
547 if (TARGET_SSE_MATH && TARGET_SSE) \
548 builtin_define ("__SSE_MATH__"); \
549 if (TARGET_SSE_MATH && TARGET_SSE2) \
550 builtin_define ("__SSE2_MATH__"); \
552 /* Built-ins based on -march=. */ \
553 if (ix86_arch == PROCESSOR_I486) \
555 builtin_define ("__i486"); \
556 builtin_define ("__i486__"); \
558 else if (ix86_arch == PROCESSOR_PENTIUM) \
560 builtin_define ("__i586"); \
561 builtin_define ("__i586__"); \
562 builtin_define ("__pentium"); \
563 builtin_define ("__pentium__"); \
564 if (last_arch_char == 'x') \
565 builtin_define ("__pentium_mmx__"); \
567 else if (ix86_arch == PROCESSOR_PENTIUMPRO) \
569 builtin_define ("__i686"); \
570 builtin_define ("__i686__"); \
571 builtin_define ("__pentiumpro"); \
572 builtin_define ("__pentiumpro__"); \
574 else if (ix86_arch == PROCESSOR_K6) \
577 builtin_define ("__k6"); \
578 builtin_define ("__k6__"); \
579 if (last_arch_char == '2') \
580 builtin_define ("__k6_2__"); \
581 else if (last_arch_char == '3') \
582 builtin_define ("__k6_3__"); \
584 else if (ix86_arch == PROCESSOR_ATHLON) \
586 builtin_define ("__athlon"); \
587 builtin_define ("__athlon__"); \
588 /* Only plain "athlon" lacks SSE. */ \
589 if (last_arch_char != 'n') \
590 builtin_define ("__athlon_sse__"); \
592 else if (ix86_arch == PROCESSOR_PENTIUM4) \
594 builtin_define ("__pentium4"); \
595 builtin_define ("__pentium4__"); \
600 #define TARGET_CPU_DEFAULT_i386 0
601 #define TARGET_CPU_DEFAULT_i486 1
602 #define TARGET_CPU_DEFAULT_pentium 2
603 #define TARGET_CPU_DEFAULT_pentium_mmx 3
604 #define TARGET_CPU_DEFAULT_pentiumpro 4
605 #define TARGET_CPU_DEFAULT_pentium2 5
606 #define TARGET_CPU_DEFAULT_pentium3 6
607 #define TARGET_CPU_DEFAULT_pentium4 7
608 #define TARGET_CPU_DEFAULT_k6 8
609 #define TARGET_CPU_DEFAULT_k6_2 9
610 #define TARGET_CPU_DEFAULT_k6_3 10
611 #define TARGET_CPU_DEFAULT_athlon 11
612 #define TARGET_CPU_DEFAULT_athlon_sse 12
614 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
615 "pentiumpro", "pentium2", "pentium3", \
616 "pentium4", "k6", "k6-2", "k6-3",\
617 "athlon", "athlon-4"}
620 #define CC1_SPEC "%(cc1_cpu) "
623 /* This macro defines names of additional specifications to put in the
624 specs that can be used in various specifications like CC1_SPEC. Its
625 definition is an initializer with a subgrouping for each command option.
627 Each subgrouping contains a string constant, that defines the
628 specification name, and a string constant that used by the GNU CC driver
631 Do not define this macro if it does not need to do anything. */
633 #ifndef SUBTARGET_EXTRA_SPECS
634 #define SUBTARGET_EXTRA_SPECS
637 #define EXTRA_SPECS \
638 { "cc1_cpu", CC1_CPU_SPEC }, \
639 SUBTARGET_EXTRA_SPECS
641 /* target machine storage layout */
643 /* Define for XFmode or TFmode extended real floating point support.
644 The XFmode is specified by i386 ABI, while TFmode may be faster
645 due to alignment and simplifications in the address calculations. */
646 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
647 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
649 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
651 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
654 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the
655 FPU, assume that the fpcw is set to extended precision; when using
656 only SSE, rounding is correct; when using both SSE and the FPU,
657 the rounding precision is indeterminate, since either may be chosen
658 apparently at random. */
659 #define TARGET_FLT_EVAL_METHOD \
660 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 1 : 2)
662 #define SHORT_TYPE_SIZE 16
663 #define INT_TYPE_SIZE 32
664 #define FLOAT_TYPE_SIZE 32
665 #define LONG_TYPE_SIZE BITS_PER_WORD
666 #define MAX_WCHAR_TYPE_SIZE 32
667 #define DOUBLE_TYPE_SIZE 64
668 #define LONG_LONG_TYPE_SIZE 64
670 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
671 #define MAX_BITS_PER_WORD 64
672 #define MAX_LONG_TYPE_SIZE 64
674 #define MAX_BITS_PER_WORD 32
675 #define MAX_LONG_TYPE_SIZE 32
678 /* Define this if most significant byte of a word is the lowest numbered. */
679 /* That is true on the 80386. */
681 #define BITS_BIG_ENDIAN 0
683 /* Define this if most significant byte of a word is the lowest numbered. */
684 /* That is not true on the 80386. */
685 #define BYTES_BIG_ENDIAN 0
687 /* Define this if most significant word of a multiword number is the lowest
689 /* Not true for 80386 */
690 #define WORDS_BIG_ENDIAN 0
692 /* Width of a word, in units (bytes). */
693 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
695 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
697 #define MIN_UNITS_PER_WORD 4
700 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
701 #define PARM_BOUNDARY BITS_PER_WORD
703 /* Boundary (in *bits*) on which stack pointer should be aligned. */
704 #define STACK_BOUNDARY BITS_PER_WORD
706 /* Boundary (in *bits*) on which the stack pointer preferrs to be
707 aligned; the compiler cannot rely on having this alignment. */
708 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
710 /* As of July 2001, many runtimes to not align the stack properly when
711 entering main. This causes expand_main_function to forcably align
712 the stack, which results in aligned frames for functions called from
713 main, though it does nothing for the alignment of main itself. */
714 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
715 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
717 /* Minimum allocation boundary for the code of a function. */
718 #define FUNCTION_BOUNDARY 8
720 /* C++ stores the virtual bit in the lowest bit of function pointers. */
721 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn
723 /* Alignment of field after `int : 0' in a structure. */
725 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
727 /* Minimum size in bits of the largest boundary to which any
728 and all fundamental data types supported by the hardware
729 might need to be aligned. No data type wants to be aligned
732 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
733 and Pentium Pro XFmode values at 128 bit boundaries. */
735 #define BIGGEST_ALIGNMENT 128
737 /* Decide whether a variable of mode MODE should be 128 bit aligned. */
738 #define ALIGN_MODE_128(MODE) \
739 ((MODE) == XFmode || (MODE) == TFmode || SSE_REG_MODE_P (MODE))
741 /* The published ABIs say that doubles should be aligned on word
742 boundaries, so lower the aligment for structure fields unless
743 -malign-double is set. */
745 /* ??? Blah -- this macro is used directly by libobjc. Since it
746 supports no vector modes, cut out the complexity and fall back
747 on BIGGEST_FIELD_ALIGNMENT. */
748 #ifdef IN_TARGET_LIBS
750 #define BIGGEST_FIELD_ALIGNMENT 128
752 #define BIGGEST_FIELD_ALIGNMENT 32
755 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
756 x86_field_alignment (FIELD, COMPUTED)
759 /* If defined, a C expression to compute the alignment given to a
760 constant that is being placed in memory. EXP is the constant
761 and ALIGN is the alignment that the object would ordinarily have.
762 The value of this macro is used instead of that alignment to align
765 If this macro is not defined, then ALIGN is used.
767 The typical use of this macro is to increase alignment for string
768 constants to be word aligned so that `strcpy' calls that copy
769 constants can be done inline. */
771 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
773 /* If defined, a C expression to compute the alignment for a static
774 variable. TYPE is the data type, and ALIGN is the alignment that
775 the object would ordinarily have. The value of this macro is used
776 instead of that alignment to align the object.
778 If this macro is not defined, then ALIGN is used.
780 One use of this macro is to increase alignment of medium-size
781 data to make it all fit in fewer cache lines. Another is to
782 cause character arrays to be word-aligned so that `strcpy' calls
783 that copy constants to character arrays can be done inline. */
785 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
787 /* If defined, a C expression to compute the alignment for a local
788 variable. TYPE is the data type, and ALIGN is the alignment that
789 the object would ordinarily have. The value of this macro is used
790 instead of that alignment to align the object.
792 If this macro is not defined, then ALIGN is used.
794 One use of this macro is to increase alignment of medium-size
795 data to make it all fit in fewer cache lines. */
797 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
799 /* If defined, a C expression that gives the alignment boundary, in
800 bits, of an argument with the specified mode and type. If it is
801 not defined, `PARM_BOUNDARY' is used for all arguments. */
803 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
804 ix86_function_arg_boundary ((MODE), (TYPE))
806 /* Set this nonzero if move instructions will actually fail to work
807 when given unaligned data. */
808 #define STRICT_ALIGNMENT 0
810 /* If bit field type is int, don't let it cross an int,
811 and give entire struct the alignment of an int. */
812 /* Required on the 386 since it doesn't have bit-field insns. */
813 #define PCC_BITFIELD_TYPE_MATTERS 1
815 /* Standard register usage. */
817 /* This processor has special stack-like registers. See reg-stack.c
821 #define IS_STACK_MODE(MODE) \
822 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
825 /* Number of actual hardware registers.
826 The hardware registers are assigned numbers for the compiler
827 from 0 to just below FIRST_PSEUDO_REGISTER.
828 All registers that the compiler knows about must be given numbers,
829 even those that are not normally considered general registers.
831 In the 80386 we give the 8 general purpose registers the numbers 0-7.
832 We number the floating point registers 8-15.
833 Note that registers 0-7 can be accessed as a short or int,
834 while only 0-3 may be used with byte `mov' instructions.
836 Reg 16 does not correspond to any hardware register, but instead
837 appears in the RTL as an argument pointer prior to reload, and is
838 eliminated during reloading in favor of either the stack or frame
841 #define FIRST_PSEUDO_REGISTER 53
843 /* Number of hardware registers that go into the DWARF-2 unwind info.
844 If not defined, equals FIRST_PSEUDO_REGISTER. */
846 #define DWARF_FRAME_REGISTERS 17
848 /* 1 for registers that have pervasive standard uses
849 and are not available for the register allocator.
850 On the 80386, the stack pointer is such, as is the arg pointer.
852 The value is an mask - bit 1 is set for fixed registers
853 for 32bit target, while 2 is set for fixed registers for 64bit.
854 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
856 #define FIXED_REGISTERS \
857 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
858 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
859 /*arg,flags,fpsr,dir,frame*/ \
861 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
862 0, 0, 0, 0, 0, 0, 0, 0, \
863 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
864 0, 0, 0, 0, 0, 0, 0, 0, \
865 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
866 1, 1, 1, 1, 1, 1, 1, 1, \
867 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
868 1, 1, 1, 1, 1, 1, 1, 1}
871 /* 1 for registers not available across function calls.
872 These must include the FIXED_REGISTERS and also any
873 registers that can be used without being saved.
874 The latter must include the registers where values are returned
875 and the register where structure-value addresses are passed.
876 Aside from that, you can include as many other registers as you like.
878 The value is an mask - bit 1 is set for call used
879 for 32bit target, while 2 is set for call used for 64bit.
880 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
882 #define CALL_USED_REGISTERS \
883 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
884 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
885 /*arg,flags,fpsr,dir,frame*/ \
887 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
888 3, 3, 3, 3, 3, 3, 3, 3, \
889 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
890 3, 3, 3, 3, 3, 3, 3, 3, \
891 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
892 3, 3, 3, 3, 1, 1, 1, 1, \
893 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
894 3, 3, 3, 3, 3, 3, 3, 3} \
896 /* Order in which to allocate registers. Each register must be
897 listed once, even those in FIXED_REGISTERS. List frame pointer
898 late and fixed registers last. Note that, in general, we prefer
899 registers listed in CALL_USED_REGISTERS, keeping the others
900 available for storage of persistent values.
902 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
903 so this is just empty initializer for array. */
905 #define REG_ALLOC_ORDER \
906 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
907 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
908 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
911 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
912 to be rearranged based on a particular function. When using sse math,
913 we want to allocase SSE before x87 registers and vice vera. */
915 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
918 /* Macro to conditionally modify fixed_regs/call_used_regs. */
919 #define CONDITIONAL_REGISTER_USAGE \
922 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
924 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
925 call_used_regs[i] = (call_used_regs[i] \
926 & (TARGET_64BIT ? 2 : 1)) != 0; \
928 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
930 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
931 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
936 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
937 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
938 fixed_regs[i] = call_used_regs[i] = 1; \
943 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
944 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
945 fixed_regs[i] = call_used_regs[i] = 1; \
947 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
951 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
952 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
953 if (TEST_HARD_REG_BIT (x, i)) \
954 fixed_regs[i] = call_used_regs[i] = 1; \
958 /* Return number of consecutive hard regs needed starting at reg REGNO
959 to hold something of mode MODE.
960 This is ordinarily the length in words of a value of mode MODE
961 but can be less for certain modes in special long registers.
963 Actually there are no two word move instructions for consecutive
964 registers. And only registers 0-3 may have mov byte instructions
968 #define HARD_REGNO_NREGS(REGNO, MODE) \
969 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
970 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
971 : ((MODE) == TFmode \
972 ? (TARGET_64BIT ? 2 : 3) \
974 ? (TARGET_64BIT ? 4 : 6) \
975 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
977 #define VALID_SSE2_REG_MODE(MODE) \
978 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
979 || (MODE) == V2DImode)
981 #define VALID_SSE_REG_MODE(MODE) \
982 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
983 || (MODE) == SFmode \
984 /* Always accept SSE2 modes so that xmmintrin.h compiles. */ \
985 || VALID_SSE2_REG_MODE (MODE) \
986 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
988 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
989 ((MODE) == V2SFmode || (MODE) == SFmode)
991 #define VALID_MMX_REG_MODE(MODE) \
992 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
993 || (MODE) == V2SImode || (MODE) == SImode)
995 #define VECTOR_MODE_SUPPORTED_P(MODE) \
996 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
997 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
998 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1000 #define VALID_FP_MODE_P(MODE) \
1001 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
1002 || (!TARGET_64BIT && (MODE) == XFmode) \
1003 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
1004 || (!TARGET_64BIT && (MODE) == XCmode))
1006 #define VALID_INT_MODE_P(MODE) \
1007 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1008 || (MODE) == DImode \
1009 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1010 || (MODE) == CDImode \
1011 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
1013 /* Return true for modes passed in SSE registers. */
1014 #define SSE_REG_MODE_P(MODE) \
1015 ((MODE) == TImode || (MODE) == V16QImode \
1016 || (MODE) == V8HImode || (MODE) == V2DFmode || (MODE) == V2DImode \
1017 || (MODE) == V4SFmode || (MODE) == V4SImode)
1019 /* Return true for modes passed in MMX registers. */
1020 #define MMX_REG_MODE_P(MODE) \
1021 ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode \
1022 || (MODE) == V2SFmode)
1024 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1026 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1027 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1029 /* Value is 1 if it is a good idea to tie two pseudo registers
1030 when one has mode MODE1 and one has mode MODE2.
1031 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1032 for any hard reg, then this must be 0 for correct output. */
1034 #define MODES_TIEABLE_P(MODE1, MODE2) \
1035 ((MODE1) == (MODE2) \
1036 || (((MODE1) == HImode || (MODE1) == SImode \
1037 || ((MODE1) == QImode \
1038 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1039 || ((MODE1) == DImode && TARGET_64BIT)) \
1040 && ((MODE2) == HImode || (MODE2) == SImode \
1041 || ((MODE1) == QImode \
1042 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1043 || ((MODE2) == DImode && TARGET_64BIT))))
1046 /* Specify the modes required to caller save a given hard regno.
1047 We do this on i386 to prevent flags from being saved at all.
1049 Kill any attempts to combine saving of modes. */
1051 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1052 (CC_REGNO_P (REGNO) ? VOIDmode \
1053 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1054 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1055 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1056 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1058 /* Specify the registers used for certain standard purposes.
1059 The values of these macros are register numbers. */
1061 /* on the 386 the pc register is %eip, and is not usable as a general
1062 register. The ordinary mov instructions won't work */
1063 /* #define PC_REGNUM */
1065 /* Register to use for pushing function arguments. */
1066 #define STACK_POINTER_REGNUM 7
1068 /* Base register for access to local variables of the function. */
1069 #define HARD_FRAME_POINTER_REGNUM 6
1071 /* Base register for access to local variables of the function. */
1072 #define FRAME_POINTER_REGNUM 20
1074 /* First floating point reg */
1075 #define FIRST_FLOAT_REG 8
1077 /* First & last stack-like regs */
1078 #define FIRST_STACK_REG FIRST_FLOAT_REG
1079 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1081 #define FLAGS_REG 17
1083 #define DIRFLAG_REG 19
1085 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1086 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1088 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1089 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1091 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1092 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1094 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1095 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1097 /* Value should be nonzero if functions must have frame pointers.
1098 Zero means the frame pointer need not be set up (and parms
1099 may be accessed via the stack pointer) in functions that seem suitable.
1100 This is computed in `reload', in reload1.c. */
1101 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1103 /* Override this in other tm.h files to cope with various OS losage
1104 requiring a frame pointer. */
1105 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1106 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1109 /* Make sure we can access arbitrary call frames. */
1110 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1112 /* Base register for access to arguments of the function. */
1113 #define ARG_POINTER_REGNUM 16
1115 /* Register in which static-chain is passed to a function.
1116 We do use ECX as static chain register for 32 bit ABI. On the
1117 64bit ABI, ECX is an argument register, so we use R10 instead. */
1118 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1120 /* Register to hold the addressing base for position independent
1121 code access to data items. We don't use PIC pointer for 64bit
1122 mode. Define the regnum to dummy value to prevent gcc from
1123 pessimizing code dealing with EBX.
1125 To avoid clobbering a call-saved register unnecessarily, we renumber
1126 the pic register when possible. The change is visible after the
1127 prologue has been emitted. */
1129 #define REAL_PIC_OFFSET_TABLE_REGNUM 3
1131 #define PIC_OFFSET_TABLE_REGNUM \
1132 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM \
1133 : reload_completed ? REGNO (pic_offset_table_rtx) \
1134 : REAL_PIC_OFFSET_TABLE_REGNUM)
1136 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_"
1138 /* Register in which address to store a structure value
1139 arrives in the function. On the 386, the prologue
1140 copies this from the stack to register %eax. */
1141 #define STRUCT_VALUE_INCOMING 0
1143 /* Place in which caller passes the structure value address.
1144 0 means push the value on the stack like an argument. */
1145 #define STRUCT_VALUE 0
1147 /* A C expression which can inhibit the returning of certain function
1148 values in registers, based on the type of value. A nonzero value
1149 says to return the function value in memory, just as large
1150 structures are always returned. Here TYPE will be a C expression
1151 of type `tree', representing the data type of the value.
1153 Note that values of mode `BLKmode' must be explicitly handled by
1154 this macro. Also, the option `-fpcc-struct-return' takes effect
1155 regardless of this macro. On most systems, it is possible to
1156 leave the macro undefined; this causes a default definition to be
1157 used, whose value is the constant 1 for `BLKmode' values, and 0
1160 Do not use this macro to indicate that structures and unions
1161 should always be returned in memory. You should instead use
1162 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1164 #define RETURN_IN_MEMORY(TYPE) \
1165 ix86_return_in_memory (TYPE)
1168 /* Define the classes of registers for register constraints in the
1169 machine description. Also define ranges of constants.
1171 One of the classes must always be named ALL_REGS and include all hard regs.
1172 If there is more than one class, another class must be named NO_REGS
1173 and contain no registers.
1175 The name GENERAL_REGS must be the name of a class (or an alias for
1176 another name such as ALL_REGS). This is the class of registers
1177 that is allowed by "g" or "r" in a register constraint.
1178 Also, registers outside this class are allocated only when
1179 instructions express preferences for them.
1181 The classes must be numbered in nondecreasing order; that is,
1182 a larger-numbered class must never be contained completely
1183 in a smaller-numbered class.
1185 For any two classes, it is very desirable that there be another
1186 class that represents their union.
1188 It might seem that class BREG is unnecessary, since no useful 386
1189 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1190 and the "b" register constraint is useful in asms for syscalls.
1192 The flags and fpsr registers are in no class. */
1197 AREG, DREG, CREG, BREG, SIREG, DIREG,
1198 AD_REGS, /* %eax/%edx for DImode */
1199 Q_REGS, /* %eax %ebx %ecx %edx */
1200 NON_Q_REGS, /* %esi %edi %ebp %esp */
1201 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1202 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1203 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1204 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1214 ALL_REGS, LIM_REG_CLASSES
1217 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1219 #define INTEGER_CLASS_P(CLASS) \
1220 reg_class_subset_p ((CLASS), GENERAL_REGS)
1221 #define FLOAT_CLASS_P(CLASS) \
1222 reg_class_subset_p ((CLASS), FLOAT_REGS)
1223 #define SSE_CLASS_P(CLASS) \
1224 reg_class_subset_p ((CLASS), SSE_REGS)
1225 #define MMX_CLASS_P(CLASS) \
1226 reg_class_subset_p ((CLASS), MMX_REGS)
1227 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1228 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1229 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1230 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1231 #define MAYBE_SSE_CLASS_P(CLASS) \
1232 reg_classes_intersect_p (SSE_REGS, (CLASS))
1233 #define MAYBE_MMX_CLASS_P(CLASS) \
1234 reg_classes_intersect_p (MMX_REGS, (CLASS))
1236 #define Q_CLASS_P(CLASS) \
1237 reg_class_subset_p ((CLASS), Q_REGS)
1239 /* Give names of register classes as strings for dump file. */
1241 #define REG_CLASS_NAMES \
1243 "AREG", "DREG", "CREG", "BREG", \
1246 "Q_REGS", "NON_Q_REGS", \
1250 "FP_TOP_REG", "FP_SECOND_REG", \
1254 "FP_TOP_SSE_REGS", \
1255 "FP_SECOND_SSE_REGS", \
1259 "FLOAT_INT_SSE_REGS", \
1262 /* Define which registers fit in which classes.
1263 This is an initializer for a vector of HARD_REG_SET
1264 of length N_REG_CLASSES. */
1266 #define REG_CLASS_CONTENTS \
1268 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1269 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1270 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1271 { 0x03, 0x0 }, /* AD_REGS */ \
1272 { 0x0f, 0x0 }, /* Q_REGS */ \
1273 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1274 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1275 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1276 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1277 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1278 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1279 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1280 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1281 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1282 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1283 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1284 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1285 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1286 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1287 { 0xffffffff,0x1fffff } \
1290 /* The same information, inverted:
1291 Return the class number of the smallest class containing
1292 reg number REGNO. This could be a conditional expression
1293 or could index an array. */
1295 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1297 /* When defined, the compiler allows registers explicitly used in the
1298 rtl to be used as spill registers but prevents the compiler from
1299 extending the lifetime of these registers. */
1301 #define SMALL_REGISTER_CLASSES 1
1303 #define QI_REG_P(X) \
1304 (REG_P (X) && REGNO (X) < 4)
1306 #define GENERAL_REGNO_P(N) \
1307 ((N) < 8 || REX_INT_REGNO_P (N))
1309 #define GENERAL_REG_P(X) \
1310 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1312 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1314 #define NON_QI_REG_P(X) \
1315 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1317 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1318 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1320 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1321 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1322 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1323 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1325 #define SSE_REGNO_P(N) \
1326 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1327 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1329 #define SSE_REGNO(N) \
1330 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1331 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1333 #define SSE_FLOAT_MODE_P(MODE) \
1334 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1336 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1337 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1339 #define STACK_REG_P(XOP) \
1341 REGNO (XOP) >= FIRST_STACK_REG && \
1342 REGNO (XOP) <= LAST_STACK_REG)
1344 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1346 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1348 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1349 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1351 /* Indicate whether hard register numbered REG_NO should be converted
1353 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1354 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1356 /* The class value for index registers, and the one for base regs. */
1358 #define INDEX_REG_CLASS INDEX_REGS
1359 #define BASE_REG_CLASS GENERAL_REGS
1361 /* Get reg_class from a letter such as appears in the machine description. */
1363 #define REG_CLASS_FROM_LETTER(C) \
1364 ((C) == 'r' ? GENERAL_REGS : \
1365 (C) == 'R' ? LEGACY_REGS : \
1366 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1367 (C) == 'Q' ? Q_REGS : \
1368 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1371 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1374 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1377 (C) == 'a' ? AREG : \
1378 (C) == 'b' ? BREG : \
1379 (C) == 'c' ? CREG : \
1380 (C) == 'd' ? DREG : \
1381 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1382 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1383 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1384 (C) == 'A' ? AD_REGS : \
1385 (C) == 'D' ? DIREG : \
1386 (C) == 'S' ? SIREG : NO_REGS)
1388 /* The letters I, J, K, L and M in a register constraint string
1389 can be used to stand for particular ranges of immediate operands.
1390 This macro defines what the ranges are.
1391 C is the letter, and VALUE is a constant value.
1392 Return 1 if VALUE is in the range specified by C.
1394 I is for non-DImode shifts.
1395 J is for DImode shifts.
1396 K is for signed imm8 operands.
1397 L is for andsi as zero-extending move.
1398 M is for shifts that can be executed by the "lea" opcode.
1399 N is for immedaite operands for out/in instructions (0-255)
1402 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1403 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1404 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1405 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1406 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1407 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1408 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1411 /* Similar, but for floating constants, and defining letters G and H.
1412 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1413 TARGET_387 isn't set, because the stack register converter may need to
1414 load 0.0 into the function value register. */
1416 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1417 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1420 /* A C expression that defines the optional machine-dependent
1421 constraint letters that can be used to segregate specific types of
1422 operands, usually memory references, for the target machine. Any
1423 letter that is not elsewhere defined and not matched by
1424 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1427 If it is required for a particular target machine, it should
1428 return 1 if VALUE corresponds to the operand type represented by
1429 the constraint letter C. If C is not defined as an extra
1430 constraint, the value returned should be 0 regardless of VALUE. */
1432 #define EXTRA_CONSTRAINT(VALUE, D) \
1433 ((D) == 'e' ? x86_64_sign_extended_value (VALUE, 0) \
1434 : (D) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1435 : (D) == 'C' ? standard_sse_constant_p (VALUE) \
1438 /* Place additional restrictions on the register class to use when it
1439 is necessary to be able to hold a value of mode MODE in a reload
1440 register for which class CLASS would ordinarily be used. */
1442 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1443 ((MODE) == QImode && !TARGET_64BIT \
1444 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1445 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1448 /* Given an rtx X being reloaded into a reg required to be
1449 in class CLASS, return the class of reg to actually use.
1450 In general this is just CLASS; but on some machines
1451 in some cases it is preferable to use a more restrictive class.
1452 On the 80386 series, we prevent floating constants from being
1453 reloaded into floating registers (since no move-insn can do that)
1454 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1456 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1457 QImode must go into class Q_REGS.
1458 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1459 movdf to do mem-to-mem moves through integer regs. */
1461 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1462 ix86_preferred_reload_class ((X), (CLASS))
1464 /* If we are copying between general and FP registers, we need a memory
1465 location. The same is true for SSE and MMX registers. */
1466 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1467 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1469 /* QImode spills from non-QI registers need a scratch. This does not
1470 happen often -- the only example so far requires an uninitialized
1473 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1474 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1475 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1478 /* Return the maximum number of consecutive registers
1479 needed to represent mode MODE in a register of class CLASS. */
1480 /* On the 80386, this is the size of MODE in words,
1481 except in the FP regs, where a single reg is always enough.
1482 The TFmodes are really just 80bit values, so we use only 3 registers
1483 to hold them, instead of 4, as the size would suggest.
1485 #define CLASS_MAX_NREGS(CLASS, MODE) \
1486 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1487 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1488 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1489 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1491 /* A C expression whose value is nonzero if pseudos that have been
1492 assigned to registers of class CLASS would likely be spilled
1493 because registers of CLASS are needed for spill registers.
1495 The default value of this macro returns 1 if CLASS has exactly one
1496 register and zero otherwise. On most machines, this default
1497 should be used. Only define this macro to some other expression
1498 if pseudo allocated by `local-alloc.c' end up in memory because
1499 their hard registers were needed for spill registers. If this
1500 macro returns nonzero for those classes, those pseudos will only
1501 be allocated by `global.c', which knows how to reallocate the
1502 pseudo to another register. If there would not be another
1503 register available for reallocation, you should not change the
1504 definition of this macro since the only effect of such a
1505 definition would be to slow down register allocation. */
1507 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1508 (((CLASS) == AREG) \
1509 || ((CLASS) == DREG) \
1510 || ((CLASS) == CREG) \
1511 || ((CLASS) == BREG) \
1512 || ((CLASS) == AD_REGS) \
1513 || ((CLASS) == SIREG) \
1514 || ((CLASS) == DIREG))
1516 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1517 to automatically clobber for all asms.
1519 We do this in the new i386 backend to maintain source compatibility
1520 with the old cc0-based compiler. */
1522 #define MD_ASM_CLOBBERS(CLOBBERS) \
1524 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1526 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1528 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1532 /* Stack layout; function entry, exit and calling. */
1534 /* Define this if pushing a word on the stack
1535 makes the stack pointer a smaller address. */
1536 #define STACK_GROWS_DOWNWARD
1538 /* Define this if the nominal address of the stack frame
1539 is at the high-address end of the local variables;
1540 that is, each additional local variable allocated
1541 goes at a more negative offset in the frame. */
1542 #define FRAME_GROWS_DOWNWARD
1544 /* Offset within stack frame to start allocating local variables at.
1545 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1546 first local allocated. Otherwise, it is the offset to the BEGINNING
1547 of the first local allocated. */
1548 #define STARTING_FRAME_OFFSET 0
1550 /* If we generate an insn to push BYTES bytes,
1551 this says how many the stack pointer really advances by.
1552 On 386 pushw decrements by exactly 2 no matter what the position was.
1553 On the 386 there is no pushb; we use pushw instead, and this
1554 has the effect of rounding up to 2.
1556 For 64bit ABI we round up to 8 bytes.
1559 #define PUSH_ROUNDING(BYTES) \
1561 ? (((BYTES) + 7) & (-8)) \
1562 : (((BYTES) + 1) & (-2)))
1564 /* If defined, the maximum amount of space required for outgoing arguments will
1565 be computed and placed into the variable
1566 `current_function_outgoing_args_size'. No space will be pushed onto the
1567 stack for each call; instead, the function prologue should increase the stack
1568 frame size by this amount. */
1570 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1572 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1573 instructions to pass outgoing arguments. */
1575 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1577 /* Offset of first parameter from the argument pointer register value. */
1578 #define FIRST_PARM_OFFSET(FNDECL) 0
1580 /* Define this macro if functions should assume that stack space has been
1581 allocated for arguments even when their values are passed in registers.
1583 The value of this macro is the size, in bytes, of the area reserved for
1584 arguments passed in registers for the function represented by FNDECL.
1586 This space can be allocated by the caller, or be a part of the
1587 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1589 #define REG_PARM_STACK_SPACE(FNDECL) 0
1591 /* Define as a C expression that evaluates to nonzero if we do not know how
1592 to pass TYPE solely in registers. The file expr.h defines a
1593 definition that is usually appropriate, refer to expr.h for additional
1594 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1595 computed in the stack and then loaded into a register. */
1596 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1598 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1599 || TREE_ADDRESSABLE (TYPE) \
1600 || ((MODE) == TImode) \
1601 || ((MODE) == BLKmode \
1603 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1604 && 0 == (int_size_in_bytes (TYPE) \
1605 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1606 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1607 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1609 /* Value is the number of bytes of arguments automatically
1610 popped when returning from a subroutine call.
1611 FUNDECL is the declaration node of the function (as a tree),
1612 FUNTYPE is the data type of the function (as a tree),
1613 or for a library call it is an identifier node for the subroutine name.
1614 SIZE is the number of bytes of arguments passed on the stack.
1616 On the 80386, the RTD insn may be used to pop them if the number
1617 of args is fixed, but if the number is variable then the caller
1618 must pop them all. RTD can't be used for library calls now
1619 because the library is compiled with the Unix compiler.
1620 Use of RTD is a selectable option, since it is incompatible with
1621 standard Unix calling sequences. If the option is not selected,
1622 the caller must always pop the args.
1624 The attribute stdcall is equivalent to RTD on a per module basis. */
1626 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1627 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1629 /* Define how to find the value returned by a function.
1630 VALTYPE is the data type of the value (as a tree).
1631 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1632 otherwise, FUNC is 0. */
1633 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1634 ix86_function_value (VALTYPE)
1636 #define FUNCTION_VALUE_REGNO_P(N) \
1637 ix86_function_value_regno_p (N)
1639 /* Define how to find the value returned by a library function
1640 assuming the value has mode MODE. */
1642 #define LIBCALL_VALUE(MODE) \
1643 ix86_libcall_value (MODE)
1645 /* Define the size of the result block used for communication between
1646 untyped_call and untyped_return. The block contains a DImode value
1647 followed by the block used by fnsave and frstor. */
1649 #define APPLY_RESULT_SIZE (8+108)
1651 /* 1 if N is a possible register number for function argument passing. */
1652 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1654 /* Define a data type for recording info about an argument list
1655 during the scan of that argument list. This data type should
1656 hold all necessary information about the function itself
1657 and about the args processed so far, enough to enable macros
1658 such as FUNCTION_ARG to determine where the next arg should go. */
1660 typedef struct ix86_args {
1661 int words; /* # words passed so far */
1662 int nregs; /* # registers available for passing */
1663 int regno; /* next available register number */
1664 int sse_words; /* # sse words passed so far */
1665 int sse_nregs; /* # sse registers available for passing */
1666 int sse_regno; /* next available sse register number */
1667 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1670 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1671 for a call to a function whose data type is FNTYPE.
1672 For a library call, FNTYPE is 0. */
1674 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1675 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
1677 /* Update the data in CUM to advance over an argument
1678 of mode MODE and data type TYPE.
1679 (TYPE is null for libcalls where that information may not be available.) */
1681 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1682 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1684 /* Define where to put the arguments to a function.
1685 Value is zero to push the argument on the stack,
1686 or a hard register in which to store the argument.
1688 MODE is the argument's machine mode.
1689 TYPE is the data type of the argument (as a tree).
1690 This is null for libcalls where that information may
1692 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1693 the preceding args and about the function being called.
1694 NAMED is nonzero if this argument is a named parameter
1695 (otherwise it is an extra parameter matching an ellipsis). */
1697 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1698 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1700 /* For an arg passed partly in registers and partly in memory,
1701 this is the number of registers used.
1702 For args passed entirely in registers or entirely in memory, zero. */
1704 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1706 /* If PIC, we cannot make sibling calls to global functions
1707 because the PLT requires %ebx live.
1708 If we are returning floats on the register stack, we cannot make
1709 sibling calls to functions that return floats. (The stack adjust
1710 instruction will wind up after the sibcall jump, and not be executed.) */
1711 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1713 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1714 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1715 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1716 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1718 /* Perform any needed actions needed for a function that is receiving a
1719 variable number of arguments.
1723 MODE and TYPE are the mode and type of the current parameter.
1725 PRETEND_SIZE is a variable that should be set to the amount of stack
1726 that must be pushed by the prolog to pretend that our caller pushed
1729 Normally, this macro will push all remaining incoming registers on the
1730 stack and set PRETEND_SIZE to the length of the registers pushed. */
1732 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1733 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1736 /* Define the `__builtin_va_list' type for the ABI. */
1737 #define BUILD_VA_LIST_TYPE(VALIST) \
1738 ((VALIST) = ix86_build_va_list ())
1740 /* Implement `va_start' for varargs and stdarg. */
1741 #define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
1742 ix86_va_start (VALIST, NEXTARG)
1744 /* Implement `va_arg'. */
1745 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1746 ix86_va_arg ((VALIST), (TYPE))
1748 /* This macro is invoked at the end of compilation. It is used here to
1749 output code for -fpic that will load the return address into %ebx. */
1752 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1754 /* Output assembler code to FILE to increment profiler label # LABELNO
1755 for profiling a function entry. */
1757 #define FUNCTION_PROFILER(FILE, LABELNO) \
1761 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1762 LPREFIX, (LABELNO)); \
1763 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1767 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1768 fprintf ((FILE), "\tcall\t_mcount\n"); \
1772 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1773 the stack pointer does not matter. The value is tested only in
1774 functions that have frame pointers.
1775 No definition is equivalent to always zero. */
1776 /* Note on the 386 it might be more efficient not to define this since
1777 we have to restore it ourselves from the frame pointer, in order to
1780 #define EXIT_IGNORE_STACK 1
1782 /* Output assembler code for a block containing the constant parts
1783 of a trampoline, leaving space for the variable parts. */
1785 /* On the 386, the trampoline contains two instructions:
1788 The trampoline is generated entirely at runtime. The operand of JMP
1789 is the address of FUNCTION relative to the instruction following the
1790 JMP (which is 5 bytes long). */
1792 /* Length in units of the trampoline for entering a nested function. */
1794 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1796 /* Emit RTL insns to initialize the variable parts of a trampoline.
1797 FNADDR is an RTX for the address of the function's pure code.
1798 CXT is an RTX for the static chain value for the function. */
1800 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1801 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1803 /* Definitions for register eliminations.
1805 This is an array of structures. Each structure initializes one pair
1806 of eliminable registers. The "from" register number is given first,
1807 followed by "to". Eliminations of the same "from" register are listed
1808 in order of preference.
1810 There are two registers that can always be eliminated on the i386.
1811 The frame pointer and the arg pointer can be replaced by either the
1812 hard frame pointer or to the stack pointer, depending upon the
1813 circumstances. The hard frame pointer is not used before reload and
1814 so it is not eligible for elimination. */
1816 #define ELIMINABLE_REGS \
1817 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1818 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1819 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1820 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1822 /* Given FROM and TO register numbers, say whether this elimination is
1823 allowed. Frame pointer elimination is automatically handled.
1825 All other eliminations are valid. */
1827 #define CAN_ELIMINATE(FROM, TO) \
1828 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1830 /* Define the offset between two registers, one to be eliminated, and the other
1831 its replacement, at the start of a routine. */
1833 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1834 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1836 /* Addressing modes, and classification of registers for them. */
1838 /* #define HAVE_POST_INCREMENT 0 */
1839 /* #define HAVE_POST_DECREMENT 0 */
1841 /* #define HAVE_PRE_DECREMENT 0 */
1842 /* #define HAVE_PRE_INCREMENT 0 */
1844 /* Macros to check register numbers against specific register classes. */
1846 /* These assume that REGNO is a hard or pseudo reg number.
1847 They give nonzero only if REGNO is a hard reg of the suitable class
1848 or a pseudo reg currently allocated to a suitable hard reg.
1849 Since they use reg_renumber, they are safe only once reg_renumber
1850 has been allocated, which happens in local-alloc.c. */
1852 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1853 ((REGNO) < STACK_POINTER_REGNUM \
1854 || (REGNO >= FIRST_REX_INT_REG \
1855 && (REGNO) <= LAST_REX_INT_REG) \
1856 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1857 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1858 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1860 #define REGNO_OK_FOR_BASE_P(REGNO) \
1861 ((REGNO) <= STACK_POINTER_REGNUM \
1862 || (REGNO) == ARG_POINTER_REGNUM \
1863 || (REGNO) == FRAME_POINTER_REGNUM \
1864 || (REGNO >= FIRST_REX_INT_REG \
1865 && (REGNO) <= LAST_REX_INT_REG) \
1866 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1867 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1868 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1870 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1871 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1872 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1873 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1875 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1876 and check its validity for a certain class.
1877 We have two alternate definitions for each of them.
1878 The usual definition accepts all pseudo regs; the other rejects
1879 them unless they have been allocated suitable hard regs.
1880 The symbol REG_OK_STRICT causes the latter definition to be used.
1882 Most source files want to accept pseudo regs in the hope that
1883 they will get allocated to the class that the insn wants them to be in.
1884 Source files for reload pass need to be strict.
1885 After reload, it makes no difference, since pseudo regs have
1886 been eliminated by then. */
1889 /* Non strict versions, pseudos are ok */
1890 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1891 (REGNO (X) < STACK_POINTER_REGNUM \
1892 || (REGNO (X) >= FIRST_REX_INT_REG \
1893 && REGNO (X) <= LAST_REX_INT_REG) \
1894 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1896 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1897 (REGNO (X) <= STACK_POINTER_REGNUM \
1898 || REGNO (X) == ARG_POINTER_REGNUM \
1899 || REGNO (X) == FRAME_POINTER_REGNUM \
1900 || (REGNO (X) >= FIRST_REX_INT_REG \
1901 && REGNO (X) <= LAST_REX_INT_REG) \
1902 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1904 /* Strict versions, hard registers only */
1905 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1906 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1908 #ifndef REG_OK_STRICT
1909 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1910 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1913 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1914 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1917 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1918 that is a valid memory address for an instruction.
1919 The MODE argument is the machine mode for the MEM expression
1920 that wants to use this address.
1922 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1923 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1925 See legitimize_pic_address in i386.c for details as to what
1926 constitutes a legitimate address when -fpic is used. */
1928 #define MAX_REGS_PER_ADDRESS 2
1930 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1932 /* Nonzero if the constant value X is a legitimate general operand.
1933 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1935 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1937 #ifdef REG_OK_STRICT
1938 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1940 if (legitimate_address_p ((MODE), (X), 1)) \
1945 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1947 if (legitimate_address_p ((MODE), (X), 0)) \
1953 /* If defined, a C expression to determine the base term of address X.
1954 This macro is used in only one place: `find_base_term' in alias.c.
1956 It is always safe for this macro to not be defined. It exists so
1957 that alias analysis can understand machine-dependent addresses.
1959 The typical use of this macro is to handle addresses containing
1960 a label_ref or symbol_ref within an UNSPEC. */
1962 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1964 /* Try machine-dependent ways of modifying an illegitimate address
1965 to be legitimate. If we find one, return the new, valid address.
1966 This macro is used in only one place: `memory_address' in explow.c.
1968 OLDX is the address as it was before break_out_memory_refs was called.
1969 In some cases it is useful to look at this to decide what needs to be done.
1971 MODE and WIN are passed so that this macro can use
1972 GO_IF_LEGITIMATE_ADDRESS.
1974 It is always safe for this macro to do nothing. It exists to recognize
1975 opportunities to optimize the output.
1977 For the 80386, we handle X+REG by loading X into a register R and
1978 using R+REG. R will go in a general reg and indexing will be used.
1979 However, if REG is a broken-out memory address or multiplication,
1980 nothing needs to be done because REG can certainly go in a general reg.
1982 When -fpic is used, special handling is needed for symbolic references.
1983 See comments by legitimize_pic_address in i386.c for details. */
1985 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1987 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1988 if (memory_address_p ((MODE), (X))) \
1992 #define REWRITE_ADDRESS(X) rewrite_address (X)
1994 /* Nonzero if the constant value X is a legitimate general operand
1995 when generating PIC code. It is given that flag_pic is on and
1996 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1998 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
2000 #define SYMBOLIC_CONST(X) \
2001 (GET_CODE (X) == SYMBOL_REF \
2002 || GET_CODE (X) == LABEL_REF \
2003 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2005 /* Go to LABEL if ADDR (a legitimate address expression)
2006 has an effect that depends on the machine mode it is used for.
2007 On the 80386, only postdecrement and postincrement address depend thus
2008 (the amount of decrement or increment being the length of the operand). */
2009 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2011 if (GET_CODE (ADDR) == POST_INC \
2012 || GET_CODE (ADDR) == POST_DEC) \
2016 /* Codes for all the SSE/MMX builtins. */
2028 IX86_BUILTIN_CMPEQPS,
2029 IX86_BUILTIN_CMPLTPS,
2030 IX86_BUILTIN_CMPLEPS,
2031 IX86_BUILTIN_CMPGTPS,
2032 IX86_BUILTIN_CMPGEPS,
2033 IX86_BUILTIN_CMPNEQPS,
2034 IX86_BUILTIN_CMPNLTPS,
2035 IX86_BUILTIN_CMPNLEPS,
2036 IX86_BUILTIN_CMPNGTPS,
2037 IX86_BUILTIN_CMPNGEPS,
2038 IX86_BUILTIN_CMPORDPS,
2039 IX86_BUILTIN_CMPUNORDPS,
2040 IX86_BUILTIN_CMPNEPS,
2041 IX86_BUILTIN_CMPEQSS,
2042 IX86_BUILTIN_CMPLTSS,
2043 IX86_BUILTIN_CMPLESS,
2044 IX86_BUILTIN_CMPNEQSS,
2045 IX86_BUILTIN_CMPNLTSS,
2046 IX86_BUILTIN_CMPNLESS,
2047 IX86_BUILTIN_CMPORDSS,
2048 IX86_BUILTIN_CMPUNORDSS,
2049 IX86_BUILTIN_CMPNESS,
2051 IX86_BUILTIN_COMIEQSS,
2052 IX86_BUILTIN_COMILTSS,
2053 IX86_BUILTIN_COMILESS,
2054 IX86_BUILTIN_COMIGTSS,
2055 IX86_BUILTIN_COMIGESS,
2056 IX86_BUILTIN_COMINEQSS,
2057 IX86_BUILTIN_UCOMIEQSS,
2058 IX86_BUILTIN_UCOMILTSS,
2059 IX86_BUILTIN_UCOMILESS,
2060 IX86_BUILTIN_UCOMIGTSS,
2061 IX86_BUILTIN_UCOMIGESS,
2062 IX86_BUILTIN_UCOMINEQSS,
2064 IX86_BUILTIN_CVTPI2PS,
2065 IX86_BUILTIN_CVTPS2PI,
2066 IX86_BUILTIN_CVTSI2SS,
2067 IX86_BUILTIN_CVTSS2SI,
2068 IX86_BUILTIN_CVTTPS2PI,
2069 IX86_BUILTIN_CVTTSS2SI,
2076 IX86_BUILTIN_LOADAPS,
2077 IX86_BUILTIN_LOADUPS,
2078 IX86_BUILTIN_STOREAPS,
2079 IX86_BUILTIN_STOREUPS,
2080 IX86_BUILTIN_LOADSS,
2081 IX86_BUILTIN_STORESS,
2084 IX86_BUILTIN_MOVHLPS,
2085 IX86_BUILTIN_MOVLHPS,
2086 IX86_BUILTIN_LOADHPS,
2087 IX86_BUILTIN_LOADLPS,
2088 IX86_BUILTIN_STOREHPS,
2089 IX86_BUILTIN_STORELPS,
2091 IX86_BUILTIN_MASKMOVQ,
2092 IX86_BUILTIN_MOVMSKPS,
2093 IX86_BUILTIN_PMOVMSKB,
2095 IX86_BUILTIN_MOVNTPS,
2096 IX86_BUILTIN_MOVNTQ,
2098 IX86_BUILTIN_LOADDQA,
2099 IX86_BUILTIN_LOADDQU,
2100 IX86_BUILTIN_STOREDQA,
2101 IX86_BUILTIN_STOREDQU,
2104 IX86_BUILTIN_STORED,
2108 IX86_BUILTIN_PACKSSWB,
2109 IX86_BUILTIN_PACKSSDW,
2110 IX86_BUILTIN_PACKUSWB,
2115 IX86_BUILTIN_PADDSB,
2116 IX86_BUILTIN_PADDSW,
2117 IX86_BUILTIN_PADDUSB,
2118 IX86_BUILTIN_PADDUSW,
2122 IX86_BUILTIN_PSUBSB,
2123 IX86_BUILTIN_PSUBSW,
2124 IX86_BUILTIN_PSUBUSB,
2125 IX86_BUILTIN_PSUBUSW,
2135 IX86_BUILTIN_PCMPEQB,
2136 IX86_BUILTIN_PCMPEQW,
2137 IX86_BUILTIN_PCMPEQD,
2138 IX86_BUILTIN_PCMPGTB,
2139 IX86_BUILTIN_PCMPGTW,
2140 IX86_BUILTIN_PCMPGTD,
2142 IX86_BUILTIN_PEXTRW,
2143 IX86_BUILTIN_PINSRW,
2145 IX86_BUILTIN_PMADDWD,
2147 IX86_BUILTIN_PMAXSW,
2148 IX86_BUILTIN_PMAXUB,
2149 IX86_BUILTIN_PMINSW,
2150 IX86_BUILTIN_PMINUB,
2152 IX86_BUILTIN_PMULHUW,
2153 IX86_BUILTIN_PMULHW,
2154 IX86_BUILTIN_PMULLW,
2156 IX86_BUILTIN_PSADBW,
2157 IX86_BUILTIN_PSHUFW,
2167 IX86_BUILTIN_PSLLWI,
2168 IX86_BUILTIN_PSLLDI,
2169 IX86_BUILTIN_PSLLQI,
2170 IX86_BUILTIN_PSRAWI,
2171 IX86_BUILTIN_PSRADI,
2172 IX86_BUILTIN_PSRLWI,
2173 IX86_BUILTIN_PSRLDI,
2174 IX86_BUILTIN_PSRLQI,
2176 IX86_BUILTIN_PUNPCKHBW,
2177 IX86_BUILTIN_PUNPCKHWD,
2178 IX86_BUILTIN_PUNPCKHDQ,
2179 IX86_BUILTIN_PUNPCKLBW,
2180 IX86_BUILTIN_PUNPCKLWD,
2181 IX86_BUILTIN_PUNPCKLDQ,
2183 IX86_BUILTIN_SHUFPS,
2187 IX86_BUILTIN_RSQRTPS,
2188 IX86_BUILTIN_RSQRTSS,
2189 IX86_BUILTIN_SQRTPS,
2190 IX86_BUILTIN_SQRTSS,
2192 IX86_BUILTIN_UNPCKHPS,
2193 IX86_BUILTIN_UNPCKLPS,
2196 IX86_BUILTIN_ANDNPS,
2201 IX86_BUILTIN_LDMXCSR,
2202 IX86_BUILTIN_STMXCSR,
2203 IX86_BUILTIN_SFENCE,
2205 /* 3DNow! Original */
2207 IX86_BUILTIN_PAVGUSB,
2211 IX86_BUILTIN_PFCMPEQ,
2212 IX86_BUILTIN_PFCMPGE,
2213 IX86_BUILTIN_PFCMPGT,
2218 IX86_BUILTIN_PFRCPIT1,
2219 IX86_BUILTIN_PFRCPIT2,
2220 IX86_BUILTIN_PFRSQIT1,
2221 IX86_BUILTIN_PFRSQRT,
2223 IX86_BUILTIN_PFSUBR,
2225 IX86_BUILTIN_PMULHRW,
2227 /* 3DNow! Athlon Extensions */
2229 IX86_BUILTIN_PFNACC,
2230 IX86_BUILTIN_PFPNACC,
2232 IX86_BUILTIN_PSWAPDSI,
2233 IX86_BUILTIN_PSWAPDSF,
2235 IX86_BUILTIN_SSE_ZERO,
2236 IX86_BUILTIN_MMX_ZERO,
2248 IX86_BUILTIN_CMPEQPD,
2249 IX86_BUILTIN_CMPLTPD,
2250 IX86_BUILTIN_CMPLEPD,
2251 IX86_BUILTIN_CMPGTPD,
2252 IX86_BUILTIN_CMPGEPD,
2253 IX86_BUILTIN_CMPNEQPD,
2254 IX86_BUILTIN_CMPNLTPD,
2255 IX86_BUILTIN_CMPNLEPD,
2256 IX86_BUILTIN_CMPNGTPD,
2257 IX86_BUILTIN_CMPNGEPD,
2258 IX86_BUILTIN_CMPORDPD,
2259 IX86_BUILTIN_CMPUNORDPD,
2260 IX86_BUILTIN_CMPNEPD,
2261 IX86_BUILTIN_CMPEQSD,
2262 IX86_BUILTIN_CMPLTSD,
2263 IX86_BUILTIN_CMPLESD,
2264 IX86_BUILTIN_CMPNEQSD,
2265 IX86_BUILTIN_CMPNLTSD,
2266 IX86_BUILTIN_CMPNLESD,
2267 IX86_BUILTIN_CMPORDSD,
2268 IX86_BUILTIN_CMPUNORDSD,
2269 IX86_BUILTIN_CMPNESD,
2271 IX86_BUILTIN_COMIEQSD,
2272 IX86_BUILTIN_COMILTSD,
2273 IX86_BUILTIN_COMILESD,
2274 IX86_BUILTIN_COMIGTSD,
2275 IX86_BUILTIN_COMIGESD,
2276 IX86_BUILTIN_COMINEQSD,
2277 IX86_BUILTIN_UCOMIEQSD,
2278 IX86_BUILTIN_UCOMILTSD,
2279 IX86_BUILTIN_UCOMILESD,
2280 IX86_BUILTIN_UCOMIGTSD,
2281 IX86_BUILTIN_UCOMIGESD,
2282 IX86_BUILTIN_UCOMINEQSD,
2290 IX86_BUILTIN_ANDNPD,
2294 IX86_BUILTIN_SQRTPD,
2295 IX86_BUILTIN_SQRTSD,
2297 IX86_BUILTIN_UNPCKHPD,
2298 IX86_BUILTIN_UNPCKLPD,
2300 IX86_BUILTIN_SHUFPD,
2302 IX86_BUILTIN_LOADAPD,
2303 IX86_BUILTIN_LOADUPD,
2304 IX86_BUILTIN_STOREAPD,
2305 IX86_BUILTIN_STOREUPD,
2306 IX86_BUILTIN_LOADSD,
2307 IX86_BUILTIN_STORESD,
2310 IX86_BUILTIN_LOADHPD,
2311 IX86_BUILTIN_LOADLPD,
2312 IX86_BUILTIN_STOREHPD,
2313 IX86_BUILTIN_STORELPD,
2315 IX86_BUILTIN_CVTDQ2PD,
2316 IX86_BUILTIN_CVTDQ2PS,
2318 IX86_BUILTIN_CVTPD2DQ,
2319 IX86_BUILTIN_CVTPD2PI,
2320 IX86_BUILTIN_CVTPD2PS,
2321 IX86_BUILTIN_CVTTPD2DQ,
2322 IX86_BUILTIN_CVTTPD2PI,
2324 IX86_BUILTIN_CVTPI2PD,
2325 IX86_BUILTIN_CVTSI2SD,
2327 IX86_BUILTIN_CVTSD2SI,
2328 IX86_BUILTIN_CVTSD2SS,
2329 IX86_BUILTIN_CVTSS2SD,
2330 IX86_BUILTIN_CVTTSD2SI,
2332 IX86_BUILTIN_CVTPS2DQ,
2333 IX86_BUILTIN_CVTPS2PD,
2334 IX86_BUILTIN_CVTTPS2DQ,
2336 IX86_BUILTIN_MOVNTI,
2337 IX86_BUILTIN_MOVNTPD,
2338 IX86_BUILTIN_MOVNTDQ,
2340 IX86_BUILTIN_SETPD1,
2343 IX86_BUILTIN_SETRPD,
2344 IX86_BUILTIN_LOADPD1,
2345 IX86_BUILTIN_LOADRPD,
2346 IX86_BUILTIN_STOREPD1,
2347 IX86_BUILTIN_STORERPD,
2350 IX86_BUILTIN_MASKMOVDQU,
2351 IX86_BUILTIN_MOVMSKPD,
2352 IX86_BUILTIN_PMOVMSKB128,
2353 IX86_BUILTIN_MOVQ2DQ,
2354 IX86_BUILTIN_MOVDQ2Q,
2356 IX86_BUILTIN_PACKSSWB128,
2357 IX86_BUILTIN_PACKSSDW128,
2358 IX86_BUILTIN_PACKUSWB128,
2360 IX86_BUILTIN_PADDB128,
2361 IX86_BUILTIN_PADDW128,
2362 IX86_BUILTIN_PADDD128,
2363 IX86_BUILTIN_PADDQ128,
2364 IX86_BUILTIN_PADDSB128,
2365 IX86_BUILTIN_PADDSW128,
2366 IX86_BUILTIN_PADDUSB128,
2367 IX86_BUILTIN_PADDUSW128,
2368 IX86_BUILTIN_PSUBB128,
2369 IX86_BUILTIN_PSUBW128,
2370 IX86_BUILTIN_PSUBD128,
2371 IX86_BUILTIN_PSUBQ128,
2372 IX86_BUILTIN_PSUBSB128,
2373 IX86_BUILTIN_PSUBSW128,
2374 IX86_BUILTIN_PSUBUSB128,
2375 IX86_BUILTIN_PSUBUSW128,
2377 IX86_BUILTIN_PAND128,
2378 IX86_BUILTIN_PANDN128,
2379 IX86_BUILTIN_POR128,
2380 IX86_BUILTIN_PXOR128,
2382 IX86_BUILTIN_PAVGB128,
2383 IX86_BUILTIN_PAVGW128,
2385 IX86_BUILTIN_PCMPEQB128,
2386 IX86_BUILTIN_PCMPEQW128,
2387 IX86_BUILTIN_PCMPEQD128,
2388 IX86_BUILTIN_PCMPGTB128,
2389 IX86_BUILTIN_PCMPGTW128,
2390 IX86_BUILTIN_PCMPGTD128,
2392 IX86_BUILTIN_PEXTRW128,
2393 IX86_BUILTIN_PINSRW128,
2395 IX86_BUILTIN_PMADDWD128,
2397 IX86_BUILTIN_PMAXSW128,
2398 IX86_BUILTIN_PMAXUB128,
2399 IX86_BUILTIN_PMINSW128,
2400 IX86_BUILTIN_PMINUB128,
2402 IX86_BUILTIN_PMULUDQ,
2403 IX86_BUILTIN_PMULUDQ128,
2404 IX86_BUILTIN_PMULHUW128,
2405 IX86_BUILTIN_PMULHW128,
2406 IX86_BUILTIN_PMULLW128,
2408 IX86_BUILTIN_PSADBW128,
2409 IX86_BUILTIN_PSHUFHW,
2410 IX86_BUILTIN_PSHUFLW,
2411 IX86_BUILTIN_PSHUFD,
2413 IX86_BUILTIN_PSLLW128,
2414 IX86_BUILTIN_PSLLD128,
2415 IX86_BUILTIN_PSLLQ128,
2416 IX86_BUILTIN_PSRAW128,
2417 IX86_BUILTIN_PSRAD128,
2418 IX86_BUILTIN_PSRLW128,
2419 IX86_BUILTIN_PSRLD128,
2420 IX86_BUILTIN_PSRLQ128,
2421 IX86_BUILTIN_PSLLDQI128,
2422 IX86_BUILTIN_PSLLWI128,
2423 IX86_BUILTIN_PSLLDI128,
2424 IX86_BUILTIN_PSLLQI128,
2425 IX86_BUILTIN_PSRAWI128,
2426 IX86_BUILTIN_PSRADI128,
2427 IX86_BUILTIN_PSRLDQI128,
2428 IX86_BUILTIN_PSRLWI128,
2429 IX86_BUILTIN_PSRLDI128,
2430 IX86_BUILTIN_PSRLQI128,
2432 IX86_BUILTIN_PUNPCKHBW128,
2433 IX86_BUILTIN_PUNPCKHWD128,
2434 IX86_BUILTIN_PUNPCKHDQ128,
2435 IX86_BUILTIN_PUNPCKHQDQ128,
2436 IX86_BUILTIN_PUNPCKLBW128,
2437 IX86_BUILTIN_PUNPCKLWD128,
2438 IX86_BUILTIN_PUNPCKLDQ128,
2439 IX86_BUILTIN_PUNPCKLQDQ128,
2441 IX86_BUILTIN_CLFLUSH,
2442 IX86_BUILTIN_MFENCE,
2443 IX86_BUILTIN_LFENCE,
2448 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
2449 #define TARGET_STRIP_NAME_ENCODING ix86_strip_name_encoding
2451 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2453 const char *xname = (NAME); \
2454 if (xname[0] == '%') \
2456 if (xname[0] == '*') \
2459 fputs (user_label_prefix, FILE); \
2460 fputs (xname, FILE); \
2463 /* Max number of args passed in registers. If this is more than 3, we will
2464 have problems with ebx (register #4), since it is a caller save register and
2465 is also used as the pic register in ELF. So for now, don't allow more than
2466 3 registers to be passed in registers. */
2468 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2470 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2473 /* Specify the machine mode that this machine uses
2474 for the index in the tablejump instruction. */
2475 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2477 /* Define as C expression which evaluates to nonzero if the tablejump
2478 instruction expects the table to contain offsets from the address of the
2480 Do not define this if the table should contain absolute addresses. */
2481 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2483 /* Define this as 1 if `char' should by default be signed; else as 0. */
2484 #define DEFAULT_SIGNED_CHAR 1
2486 /* Number of bytes moved into a data cache for a single prefetch operation. */
2487 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2489 /* Number of prefetch operations that can be done in parallel. */
2490 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2492 /* Max number of bytes we can move from memory to memory
2493 in one reasonably fast instruction. */
2496 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2497 move efficiently, as opposed to MOVE_MAX which is the maximum
2498 number of bytes we can move with a single instruction. */
2499 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2501 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2502 move-instruction pairs, we will do a movstr or libcall instead.
2503 Increasing the value will always make code faster, but eventually
2504 incurs high cost in increased code size.
2506 If you don't define this, a reasonable default is used. */
2508 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2510 /* Define if shifts truncate the shift count
2511 which implies one can omit a sign-extension or zero-extension
2512 of a shift count. */
2513 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2515 /* #define SHIFT_COUNT_TRUNCATED */
2517 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2518 is done just by pretending it is already truncated. */
2519 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2521 /* We assume that the store-condition-codes instructions store 0 for false
2522 and some other value for true. This is the value stored for true. */
2524 #define STORE_FLAG_VALUE 1
2526 /* When a prototype says `char' or `short', really pass an `int'.
2527 (The 386 can't easily push less than an int.) */
2529 #define PROMOTE_PROTOTYPES 1
2531 /* A macro to update M and UNSIGNEDP when an object whose type is
2532 TYPE and which has the specified mode and signedness is to be
2533 stored in a register. This macro is only called when TYPE is a
2536 On i386 it is sometimes useful to promote HImode and QImode
2537 quantities to SImode. The choice depends on target type. */
2539 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2541 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2542 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2546 /* Specify the machine mode that pointers have.
2547 After generation of rtl, the compiler makes no further distinction
2548 between pointers and any other objects of this machine mode. */
2549 #define Pmode (TARGET_64BIT ? DImode : SImode)
2551 /* A function address in a call instruction
2552 is a byte address (for indexing purposes)
2553 so give the MEM rtx a byte's mode. */
2554 #define FUNCTION_MODE QImode
2556 /* A part of a C `switch' statement that describes the relative costs
2557 of constant RTL expressions. It must contain `case' labels for
2558 expression codes `const_int', `const', `symbol_ref', `label_ref'
2559 and `const_double'. Each case must ultimately reach a `return'
2560 statement to return the relative cost of the use of that kind of
2561 constant value in an expression. The cost may depend on the
2562 precise value of the constant, which is available for examination
2563 in X, and the rtx code of the expression in which it is contained,
2564 found in OUTER_CODE.
2566 CODE is the expression code--redundant, since it can be obtained
2567 with `GET_CODE (X)'. */
2569 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2574 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX, 0)) \
2576 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2578 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2580 case CONST_DOUBLE: \
2581 if (GET_MODE (RTX) == VOIDmode) \
2583 switch (standard_80387_constant_p (RTX)) \
2590 /* Start with (MEM (SYMBOL_REF)), since that's where \
2591 it'll probably end up. Add a penalty for size. */ \
2592 return (COSTS_N_INSNS (1) + (flag_pic != 0) \
2593 + (GET_MODE (RTX) == SFmode ? 0 \
2594 : GET_MODE (RTX) == DFmode ? 1 : 2)); \
2597 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2598 #define TOPLEVEL_COSTS_N_INSNS(N) \
2599 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2601 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2602 This can be used, for example, to indicate how costly a multiply
2603 instruction is. In writing this macro, you can use the construct
2604 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2605 instructions. OUTER_CODE is the code of the expression in which X
2608 This macro is optional; do not define it if the default cost
2609 assumptions are adequate for the target machine. */
2611 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2613 /* The zero extensions is often completely free on x86_64, so make \
2614 it as cheap as possible. */ \
2615 if (TARGET_64BIT && GET_MODE (X) == DImode \
2616 && GET_MODE (XEXP (X, 0)) == SImode) \
2618 total = 1; goto egress_rtx_costs; \
2621 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2622 ix86_cost->add : ix86_cost->movzx); \
2625 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2628 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2629 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2631 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2633 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2634 if ((value == 2 || value == 3) \
2635 && !TARGET_DECOMPOSE_LEA \
2636 && ix86_cost->lea <= ix86_cost->shift_const) \
2637 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2639 /* fall through */ \
2645 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2647 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2649 if (INTVAL (XEXP (X, 1)) > 32) \
2650 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2652 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2656 if (GET_CODE (XEXP (X, 1)) == AND) \
2657 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2659 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2664 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2665 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2667 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2672 if (FLOAT_MODE_P (GET_MODE (X))) \
2673 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fmul); \
2674 else if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2676 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2679 while (value != 0) \
2685 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2686 + nbits * ix86_cost->mult_bit); \
2688 else /* This is arbitrary */ \
2689 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2690 + 7 * ix86_cost->mult_bit); \
2696 if (FLOAT_MODE_P (GET_MODE (X))) \
2697 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fdiv); \
2699 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2703 if (FLOAT_MODE_P (GET_MODE (X))) \
2704 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fadd); \
2705 else if (!TARGET_DECOMPOSE_LEA \
2706 && INTEGRAL_MODE_P (GET_MODE (X)) \
2707 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2709 if (GET_CODE (XEXP (X, 0)) == PLUS \
2710 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2711 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2712 && CONSTANT_P (XEXP (X, 1))) \
2714 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2715 if (val == 2 || val == 4 || val == 8) \
2717 return (COSTS_N_INSNS (ix86_cost->lea) \
2718 + rtx_cost (XEXP (XEXP (X, 0), 1), \
2720 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \
2722 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2725 else if (GET_CODE (XEXP (X, 0)) == MULT \
2726 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2728 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2729 if (val == 2 || val == 4 || val == 8) \
2731 return (COSTS_N_INSNS (ix86_cost->lea) \
2732 + rtx_cost (XEXP (XEXP (X, 0), 0), \
2734 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2737 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2739 return (COSTS_N_INSNS (ix86_cost->lea) \
2740 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \
2741 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \
2742 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2745 /* fall through */ \
2748 if (FLOAT_MODE_P (GET_MODE (X))) \
2749 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fadd); \
2750 /* fall through */ \
2755 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2756 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2757 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \
2758 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2759 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \
2760 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2761 /* fall through */ \
2764 if (FLOAT_MODE_P (GET_MODE (X))) \
2765 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fchs); \
2766 /* fall through */ \
2769 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2770 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2771 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2773 case FLOAT_EXTEND: \
2774 if (!TARGET_SSE_MATH \
2775 || !VALID_SSE_REG_MODE (GET_MODE (X))) \
2776 TOPLEVEL_COSTS_N_INSNS (0); \
2780 if (FLOAT_MODE_P (GET_MODE (X))) \
2781 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fabs); \
2785 if (FLOAT_MODE_P (GET_MODE (X))) \
2786 TOPLEVEL_COSTS_N_INSNS (ix86_cost->fsqrt); \
2793 /* An expression giving the cost of an addressing mode that contains
2794 ADDRESS. If not defined, the cost is computed from the ADDRESS
2795 expression and the `CONST_COSTS' values.
2797 For most CISC machines, the default cost is a good approximation
2798 of the true cost of the addressing mode. However, on RISC
2799 machines, all instructions normally have the same length and
2800 execution time. Hence all addresses will have equal costs.
2802 In cases where more than one form of an address is known, the form
2803 with the lowest cost will be used. If multiple forms have the
2804 same, lowest, cost, the one that is the most complex will be used.
2806 For example, suppose an address that is equal to the sum of a
2807 register and a constant is used twice in the same basic block.
2808 When this macro is not defined, the address will be computed in a
2809 register and memory references will be indirect through that
2810 register. On machines where the cost of the addressing mode
2811 containing the sum is no higher than that of a simple indirect
2812 reference, this will produce an additional instruction and
2813 possibly require an additional register. Proper specification of
2814 this macro eliminates this overhead for such machines.
2816 Similar use of this macro is made in strength reduction of loops.
2818 ADDRESS need not be valid as an address. In such a case, the cost
2819 is not relevant and can be any value; invalid addresses need not be
2820 assigned a different cost.
2822 On machines where an address involving more than one register is as
2823 cheap as an address computation involving only one register,
2824 defining `ADDRESS_COST' to reflect this can cause two registers to
2825 be live over a region of code where only one would have been if
2826 `ADDRESS_COST' were not defined in that manner. This effect should
2827 be considered in the definition of this macro. Equivalent costs
2828 should probably only be given to addresses with different numbers
2829 of registers on machines with lots of registers.
2831 This macro will normally either not be defined or be defined as a
2834 For i386, it is better to use a complex address than let gcc copy
2835 the address into a reg and make a new pseudo. But not if the address
2836 requires to two regs - that would mean more pseudos with longer
2839 #define ADDRESS_COST(RTX) \
2840 ix86_address_cost (RTX)
2842 /* A C expression for the cost of moving data from a register in class FROM to
2843 one in class TO. The classes are expressed using the enumeration values
2844 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2845 interpreted relative to that.
2847 It is not required that the cost always equal 2 when FROM is the same as TO;
2848 on some machines it is expensive to move between registers if they are not
2849 general registers. */
2851 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2852 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2854 /* A C expression for the cost of moving data of mode M between a
2855 register and memory. A value of 2 is the default; this cost is
2856 relative to those in `REGISTER_MOVE_COST'.
2858 If moving between registers and memory is more expensive than
2859 between two registers, you should define this macro to express the
2862 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2863 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2865 /* A C expression for the cost of a branch instruction. A value of 1
2866 is the default; other values are interpreted relative to that. */
2868 #define BRANCH_COST ix86_branch_cost
2870 /* Define this macro as a C expression which is nonzero if accessing
2871 less than a word of memory (i.e. a `char' or a `short') is no
2872 faster than accessing a word of memory, i.e., if such access
2873 require more than one instruction or if there is no difference in
2874 cost between byte and (aligned) word loads.
2876 When this macro is not defined, the compiler will access a field by
2877 finding the smallest containing object; when it is defined, a
2878 fullword load will be used if alignment permits. Unless bytes
2879 accesses are faster than word accesses, using word accesses is
2880 preferable since it may eliminate subsequent memory access if
2881 subsequent accesses occur to other fields in the same word of the
2882 structure, but to different bytes. */
2884 #define SLOW_BYTE_ACCESS 0
2886 /* Nonzero if access to memory by shorts is slow and undesirable. */
2887 #define SLOW_SHORT_ACCESS 0
2889 /* Define this macro to be the value 1 if unaligned accesses have a
2890 cost many times greater than aligned accesses, for example if they
2891 are emulated in a trap handler.
2893 When this macro is nonzero, the compiler will act as if
2894 `STRICT_ALIGNMENT' were nonzero when generating code for block
2895 moves. This can cause significantly more instructions to be
2896 produced. Therefore, do not set this macro nonzero if unaligned
2897 accesses only add a cycle or two to the time for a memory access.
2899 If the value of this macro is always zero, it need not be defined. */
2901 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2903 /* Define this macro to inhibit strength reduction of memory
2904 addresses. (On some machines, such strength reduction seems to do
2905 harm rather than good.) */
2907 /* #define DONT_REDUCE_ADDR */
2909 /* Define this macro if it is as good or better to call a constant
2910 function address than to call an address kept in a register.
2912 Desirable on the 386 because a CALL with a constant address is
2913 faster than one with a register address. */
2915 #define NO_FUNCTION_CSE
2917 /* Define this macro if it is as good or better for a function to call
2918 itself with an explicit address than to call an address kept in a
2921 #define NO_RECURSIVE_FUNCTION_CSE
2923 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2924 return the mode to be used for the comparison.
2926 For floating-point equality comparisons, CCFPEQmode should be used.
2927 VOIDmode should be used in all other cases.
2929 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2930 possible, to allow for more combinations. */
2932 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2934 /* Return nonzero if MODE implies a floating point inequality can be
2937 #define REVERSIBLE_CC_MODE(MODE) 1
2939 /* A C expression whose value is reversed condition code of the CODE for
2940 comparison done in CC_MODE mode. */
2941 #define REVERSE_CONDITION(CODE, MODE) \
2942 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2943 : reverse_condition_maybe_unordered (CODE))
2946 /* Control the assembler format that we output, to the extent
2947 this does not vary between assemblers. */
2949 /* How to refer to registers in assembler output.
2950 This sequence is indexed by compiler's hard-register-number (see above). */
2952 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2953 For non floating point regs, the following are the HImode names.
2955 For float regs, the stack top is sometimes referred to as "%st(0)"
2956 instead of just "%st". PRINT_REG handles this with the "y" code. */
2958 #undef HI_REGISTER_NAMES
2959 #define HI_REGISTER_NAMES \
2960 {"ax","dx","cx","bx","si","di","bp","sp", \
2961 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2962 "flags","fpsr", "dirflag", "frame", \
2963 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2964 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2965 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2966 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2968 #define REGISTER_NAMES HI_REGISTER_NAMES
2970 /* Table of additional register names to use in user input. */
2972 #define ADDITIONAL_REGISTER_NAMES \
2973 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2974 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2975 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2976 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2977 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2978 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2979 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2980 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2982 /* Note we are omitting these since currently I don't know how
2983 to get gcc to use these, since they want the same but different
2984 number as al, and ax.
2987 #define QI_REGISTER_NAMES \
2988 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2990 /* These parallel the array above, and can be used to access bits 8:15
2991 of regs 0 through 3. */
2993 #define QI_HIGH_REGISTER_NAMES \
2994 {"ah", "dh", "ch", "bh", }
2996 /* How to renumber registers for dbx and gdb. */
2998 #define DBX_REGISTER_NUMBER(N) \
2999 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
3001 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
3002 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
3003 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
3005 /* Before the prologue, RA is at 0(%esp). */
3006 #define INCOMING_RETURN_ADDR_RTX \
3007 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
3009 /* After the prologue, RA is at -4(AP) in the current frame. */
3010 #define RETURN_ADDR_RTX(COUNT, FRAME) \
3012 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
3013 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
3015 /* PC is dbx register 8; let's use that column for RA. */
3016 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
3018 /* Before the prologue, the top of the frame is at 4(%esp). */
3019 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
3021 /* Describe how we implement __builtin_eh_return. */
3022 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
3023 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
3026 /* Select a format to encode pointers in exception handling data. CODE
3027 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
3028 true if the symbol may be affected by dynamic relocations.
3030 ??? All x86 object file formats are capable of representing this.
3031 After all, the relocation needed is the same as for the call insn.
3032 Whether or not a particular assembler allows us to enter such, I
3033 guess we'll have to see. */
3034 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3036 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
3039 /* Store in OUTPUT a string (made with alloca) containing
3040 an assembler-name for a local static variable named NAME.
3041 LABELNO is an integer which is different for each call. */
3043 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3044 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3045 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
3047 /* This is how to output an insn to push a register on the stack.
3048 It need not be very fast code. */
3050 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
3053 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \
3054 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
3056 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \
3059 /* This is how to output an insn to pop a register from the stack.
3060 It need not be very fast code. */
3062 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
3065 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \
3066 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \
3068 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \
3071 /* This is how to output an element of a case-vector that is absolute. */
3073 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
3074 ix86_output_addr_vec_elt ((FILE), (VALUE))
3076 /* This is how to output an element of a case-vector that is relative. */
3078 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
3079 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
3081 /* Under some conditions we need jump tables in the text section, because
3082 the assembler cannot handle label differences between sections. */
3084 #define JUMP_TABLES_IN_TEXT_SECTION \
3085 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
3087 /* A C statement that outputs an address constant appropriate to
3088 for DWARF debugging. */
3090 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
3091 i386_dwarf_output_addr_const ((FILE), (X))
3093 /* Either simplify a location expression, or return the original. */
3095 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
3096 i386_simplify_dwarf_addr (X)
3098 /* Emit a dtp-relative reference to a TLS variable. */
3101 #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
3102 i386_output_dwarf_dtprel (FILE, SIZE, X)
3105 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
3106 and switch back. For x86 we do this only to save a few bytes that
3107 would otherwise be unused in the text section. */
3108 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3109 asm (SECTION_OP "\n\t" \
3110 "call " USER_LABEL_PREFIX #FUNC "\n" \
3111 TEXT_SECTION_ASM_OP);
3113 /* Print operand X (an rtx) in assembler syntax to file FILE.
3114 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3115 Effect of various CODE letters is described in i386.c near
3116 print_operand function. */
3118 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
3119 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&')
3121 /* Print the name of a register based on its machine mode and number.
3122 If CODE is 'w', pretend the mode is HImode.
3123 If CODE is 'b', pretend the mode is QImode.
3124 If CODE is 'k', pretend the mode is SImode.
3125 If CODE is 'q', pretend the mode is DImode.
3126 If CODE is 'h', pretend the reg is the `high' byte register.
3127 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
3129 #define PRINT_REG(X, CODE, FILE) \
3130 print_reg ((X), (CODE), (FILE))
3132 #define PRINT_OPERAND(FILE, X, CODE) \
3133 print_operand ((FILE), (X), (CODE))
3135 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
3136 print_operand_address ((FILE), (ADDR))
3138 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \
3140 if (! output_addr_const_extra (FILE, (X))) \
3144 /* Print the name of a register for based on its machine mode and number.
3145 This macro is used to print debugging output.
3146 This macro is different from PRINT_REG in that it may be used in
3147 programs that are not linked with aux-output.o. */
3149 #define DEBUG_PRINT_REG(X, CODE, FILE) \
3150 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
3151 static const char * const qi_name[] = QI_REGISTER_NAMES; \
3152 fprintf ((FILE), "%d ", REGNO (X)); \
3153 if (REGNO (X) == FLAGS_REG) \
3154 { fputs ("flags", (FILE)); break; } \
3155 if (REGNO (X) == DIRFLAG_REG) \
3156 { fputs ("dirflag", (FILE)); break; } \
3157 if (REGNO (X) == FPSR_REG) \
3158 { fputs ("fpsr", (FILE)); break; } \
3159 if (REGNO (X) == ARG_POINTER_REGNUM) \
3160 { fputs ("argp", (FILE)); break; } \
3161 if (REGNO (X) == FRAME_POINTER_REGNUM) \
3162 { fputs ("frame", (FILE)); break; } \
3163 if (STACK_TOP_P (X)) \
3164 { fputs ("st(0)", (FILE)); break; } \
3166 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
3167 if (REX_INT_REG_P (X)) \
3169 switch (GET_MODE_SIZE (GET_MODE (X))) \
3173 fprintf ((FILE), "r%i", REGNO (X) \
3174 - FIRST_REX_INT_REG + 8); \
3177 fprintf ((FILE), "r%id", REGNO (X) \
3178 - FIRST_REX_INT_REG + 8); \
3181 fprintf ((FILE), "r%iw", REGNO (X) \
3182 - FIRST_REX_INT_REG + 8); \
3185 fprintf ((FILE), "r%ib", REGNO (X) \
3186 - FIRST_REX_INT_REG + 8); \
3191 switch (GET_MODE_SIZE (GET_MODE (X))) \
3194 fputs ("r", (FILE)); \
3195 fputs (hi_name[REGNO (X)], (FILE)); \
3198 fputs ("e", (FILE)); \
3200 fputs (hi_name[REGNO (X)], (FILE)); \
3203 fputs (qi_name[REGNO (X)], (FILE)); \
3208 /* a letter which is not needed by the normal asm syntax, which
3209 we can use for operand syntax in the extended asm */
3211 #define ASM_OPERAND_LETTER '#'
3212 #define RET return ""
3213 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
3215 /* Define the codes that are matched by predicates in i386.c. */
3217 #define PREDICATE_CODES \
3218 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3219 SYMBOL_REF, LABEL_REF, CONST}}, \
3220 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3221 SYMBOL_REF, LABEL_REF, CONST}}, \
3222 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3223 SYMBOL_REF, LABEL_REF, CONST}}, \
3224 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3225 SYMBOL_REF, LABEL_REF, CONST}}, \
3226 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3227 SYMBOL_REF, LABEL_REF, CONST}}, \
3228 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3229 SYMBOL_REF, LABEL_REF, CONST}}, \
3230 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3231 SYMBOL_REF, LABEL_REF}}, \
3232 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3233 {"const_int_1_operand", {CONST_INT}}, \
3234 {"const_int_1_31_operand", {CONST_INT}}, \
3235 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3236 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3237 LABEL_REF, SUBREG, REG, MEM}}, \
3238 {"pic_symbolic_operand", {CONST}}, \
3239 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3240 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3241 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3242 {"const1_operand", {CONST_INT}}, \
3243 {"const248_operand", {CONST_INT}}, \
3244 {"incdec_operand", {CONST_INT}}, \
3245 {"mmx_reg_operand", {REG}}, \
3246 {"reg_no_sp_operand", {SUBREG, REG}}, \
3247 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3248 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3249 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3250 {"index_register_operand", {SUBREG, REG}}, \
3251 {"q_regs_operand", {SUBREG, REG}}, \
3252 {"non_q_regs_operand", {SUBREG, REG}}, \
3253 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3254 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3255 GE, UNGE, LTGT, UNEQ}}, \
3256 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3257 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3259 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3260 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3261 UNGE, UNGT, LTGT, UNEQ }}, \
3262 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3263 {"ext_register_operand", {SUBREG, REG}}, \
3264 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3265 {"mult_operator", {MULT}}, \
3266 {"div_operator", {DIV}}, \
3267 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3268 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3269 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3270 LSHIFTRT, ROTATERT}}, \
3271 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3272 {"memory_displacement_operand", {MEM}}, \
3273 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3274 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3275 {"long_memory_operand", {MEM}}, \
3276 {"tls_symbolic_operand", {SYMBOL_REF}}, \
3277 {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3278 {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \
3279 {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \
3280 {"local_exec_symbolic_operand", {SYMBOL_REF}}, \
3281 {"any_fp_register_operand", {REG}}, \
3282 {"register_and_not_any_fp_reg_operand", {REG}}, \
3283 {"fp_register_operand", {REG}}, \
3284 {"register_and_not_fp_reg_operand", {REG}}, \
3286 /* A list of predicates that do special things with modes, and so
3287 should not elicit warnings for VOIDmode match_operand. */
3289 #define SPECIAL_MODE_PREDICATES \
3290 "ext_register_operand",
3292 /* Which processor to schedule for. The cpu attribute defines a list that
3293 mirrors this list, so changes to i386.md must be made at the same time. */
3297 PROCESSOR_I386, /* 80386 */
3298 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
3300 PROCESSOR_PENTIUMPRO,
3307 extern enum processor_type ix86_cpu;
3308 extern const char *ix86_cpu_string;
3310 extern enum processor_type ix86_arch;
3311 extern const char *ix86_arch_string;
3319 extern enum fpmath_unit ix86_fpmath;
3320 extern const char *ix86_fpmath_string;
3328 extern enum tls_dialect ix86_tls_dialect;
3329 extern const char *ix86_tls_dialect_string;
3332 CM_32, /* The traditional 32-bit ABI. */
3333 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */
3334 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */
3335 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */
3336 CM_LARGE, /* No assumptions. */
3337 CM_SMALL_PIC /* Assumes code+data+got/plt fits in a 31 bit region. */
3340 extern enum cmodel ix86_cmodel;
3341 extern const char *ix86_cmodel_string;
3343 /* Size of the RED_ZONE area. */
3344 #define RED_ZONE_SIZE 128
3345 /* Reserved area of the red zone for temporaries. */
3346 #define RED_ZONE_RESERVE 8
3353 extern const char *ix86_asm_string;
3354 extern enum asm_dialect ix86_asm_dialect;
3356 extern int ix86_regparm;
3357 extern const char *ix86_regparm_string;
3359 extern int ix86_preferred_stack_boundary;
3360 extern const char *ix86_preferred_stack_boundary_string;
3362 extern int ix86_branch_cost;
3363 extern const char *ix86_branch_cost_string;
3365 extern const char *ix86_debug_arg_string;
3366 extern const char *ix86_debug_addr_string;
3368 /* Obsoleted by -f options. Remove before 3.2 ships. */
3369 extern const char *ix86_align_loops_string;
3370 extern const char *ix86_align_jumps_string;
3371 extern const char *ix86_align_funcs_string;
3373 /* Smallest class containing REGNO. */
3374 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER];
3376 extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3377 extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3379 /* To properly truncate FP values into integers, we need to set i387 control
3380 word. We can't emit proper mode switching code before reload, as spills
3381 generated by reload may truncate values incorrectly, but we still can avoid
3382 redundant computation of new control word by the mode switching pass.
3383 The fldcw instructions are still emitted redundantly, but this is probably
3384 not going to be noticeable problem, as most CPUs do have fast path for
3387 The machinery is to emit simple truncation instructions and split them
3388 before reload to instructions having USEs of two memory locations that
3389 are filled by this code to old and new control word.
3391 Post-reload pass may be later used to eliminate the redundant fildcw if
3394 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3396 /* Define this macro if the port needs extra instructions inserted
3397 for mode switching in an optimizing compilation. */
3399 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3401 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3402 initializer for an array of integers. Each initializer element N
3403 refers to an entity that needs mode switching, and specifies the
3404 number of different modes that might need to be set for this
3405 entity. The position of the initializer in the initializer -
3406 starting counting at zero - determines the integer that is used to
3407 refer to the mode-switched entity in question. */
3409 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3411 /* ENTITY is an integer specifying a mode-switched entity. If
3412 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3413 return an integer value not larger than the corresponding element
3414 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3415 must be switched into prior to the execution of INSN. */
3417 #define MODE_NEEDED(ENTITY, I) \
3418 (GET_CODE (I) == CALL_INSN \
3419 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3420 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3421 ? FP_CW_UNINITIALIZED \
3422 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3426 /* This macro specifies the order in which modes for ENTITY are
3427 processed. 0 is the highest priority. */
3429 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3431 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3432 is the set of hard registers live at the point where the insn(s)
3433 are to be inserted. */
3435 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3436 ((MODE) == FP_CW_STORED \
3437 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3438 assign_386_stack_local (HImode, 2)), 0\
3441 /* Avoid renaming of stack registers, as doing so in combination with
3442 scheduling just increases amount of live registers at time and in
3443 the turn amount of fxch instructions needed.
3445 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3447 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3448 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
3451 #define MACHINE_DEPENDENT_REORG(X) x86_machine_dependent_reorg(X)
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