1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
51 #include "tree-gimple.h"
54 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs size_cost = { /* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of loading integer registers */
995 2, /* cost of moving MMX register */
996 {6, 6}, /* cost of loading MMX registers
997 in SImode and DImode */
998 {4, 4}, /* cost of storing MMX registers
999 in SImode and DImode */
1000 2, /* cost of moving SSE register */
1001 {6, 6, 6}, /* cost of loading SSE registers
1002 in SImode, DImode and TImode */
1003 {4, 4, 4}, /* cost of storing SSE registers
1004 in SImode, DImode and TImode */
1005 2, /* MMX or SSE register to integer */
1006 32, /* size of l1 cache. */
1007 2048, /* size of l2 cache. */
1008 128, /* size of prefetch block */
1009 8, /* number of parallel prefetches */
1010 3, /* Branch cost */
1011 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1012 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1013 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1014 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1015 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1016 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1017 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1018 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1019 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1020 {{libcall, {{8, loop}, {15, unrolled_loop},
1021 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1022 {libcall, {{24, loop}, {32, unrolled_loop},
1023 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1024 1, /* scalar_stmt_cost. */
1025 1, /* scalar load_cost. */
1026 1, /* scalar_store_cost. */
1027 1, /* vec_stmt_cost. */
1028 1, /* vec_to_scalar_cost. */
1029 1, /* scalar_to_vec_cost. */
1030 1, /* vec_align_load_cost. */
1031 2, /* vec_unalign_load_cost. */
1032 1, /* vec_store_cost. */
1033 3, /* cond_taken_branch_cost. */
1034 1, /* cond_not_taken_branch_cost. */
1037 /* Generic64 should produce code tuned for Nocona and K8. */
1039 struct processor_costs generic64_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 /* On all chips taken into consideration lea is 2 cycles and more. With
1042 this cost however our current implementation of synth_mult results in
1043 use of unnecessary temporary registers causing regression on several
1044 SPECfp benchmarks. */
1045 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1046 COSTS_N_INSNS (1), /* variable shift costs */
1047 COSTS_N_INSNS (1), /* constant shift costs */
1048 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1049 COSTS_N_INSNS (4), /* HI */
1050 COSTS_N_INSNS (3), /* SI */
1051 COSTS_N_INSNS (4), /* DI */
1052 COSTS_N_INSNS (2)}, /* other */
1053 0, /* cost of multiply per each bit set */
1054 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1055 COSTS_N_INSNS (26), /* HI */
1056 COSTS_N_INSNS (42), /* SI */
1057 COSTS_N_INSNS (74), /* DI */
1058 COSTS_N_INSNS (74)}, /* other */
1059 COSTS_N_INSNS (1), /* cost of movsx */
1060 COSTS_N_INSNS (1), /* cost of movzx */
1061 8, /* "large" insn */
1062 17, /* MOVE_RATIO */
1063 4, /* cost for loading QImode using movzbl */
1064 {4, 4, 4}, /* cost of loading integer registers
1065 in QImode, HImode and SImode.
1066 Relative to reg-reg move (2). */
1067 {4, 4, 4}, /* cost of storing integer registers */
1068 4, /* cost of reg,reg fld/fst */
1069 {12, 12, 12}, /* cost of loading fp registers
1070 in SFmode, DFmode and XFmode */
1071 {6, 6, 8}, /* cost of storing fp registers
1072 in SFmode, DFmode and XFmode */
1073 2, /* cost of moving MMX register */
1074 {8, 8}, /* cost of loading MMX registers
1075 in SImode and DImode */
1076 {8, 8}, /* cost of storing MMX registers
1077 in SImode and DImode */
1078 2, /* cost of moving SSE register */
1079 {8, 8, 8}, /* cost of loading SSE registers
1080 in SImode, DImode and TImode */
1081 {8, 8, 8}, /* cost of storing SSE registers
1082 in SImode, DImode and TImode */
1083 5, /* MMX or SSE register to integer */
1084 32, /* size of l1 cache. */
1085 512, /* size of l2 cache. */
1086 64, /* size of prefetch block */
1087 6, /* number of parallel prefetches */
1088 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1089 is increased to perhaps more appropriate value of 5. */
1090 3, /* Branch cost */
1091 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1092 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1093 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1094 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1095 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1096 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1097 {DUMMY_STRINGOP_ALGS,
1098 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 1, /* scalar_stmt_cost. */
1102 1, /* scalar load_cost. */
1103 1, /* scalar_store_cost. */
1104 1, /* vec_stmt_cost. */
1105 1, /* vec_to_scalar_cost. */
1106 1, /* scalar_to_vec_cost. */
1107 1, /* vec_align_load_cost. */
1108 2, /* vec_unalign_load_cost. */
1109 1, /* vec_store_cost. */
1110 3, /* cond_taken_branch_cost. */
1111 1, /* cond_not_taken_branch_cost. */
1114 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1116 struct processor_costs generic32_cost = {
1117 COSTS_N_INSNS (1), /* cost of an add instruction */
1118 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1119 COSTS_N_INSNS (1), /* variable shift costs */
1120 COSTS_N_INSNS (1), /* constant shift costs */
1121 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1122 COSTS_N_INSNS (4), /* HI */
1123 COSTS_N_INSNS (3), /* SI */
1124 COSTS_N_INSNS (4), /* DI */
1125 COSTS_N_INSNS (2)}, /* other */
1126 0, /* cost of multiply per each bit set */
1127 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1128 COSTS_N_INSNS (26), /* HI */
1129 COSTS_N_INSNS (42), /* SI */
1130 COSTS_N_INSNS (74), /* DI */
1131 COSTS_N_INSNS (74)}, /* other */
1132 COSTS_N_INSNS (1), /* cost of movsx */
1133 COSTS_N_INSNS (1), /* cost of movzx */
1134 8, /* "large" insn */
1135 17, /* MOVE_RATIO */
1136 4, /* cost for loading QImode using movzbl */
1137 {4, 4, 4}, /* cost of loading integer registers
1138 in QImode, HImode and SImode.
1139 Relative to reg-reg move (2). */
1140 {4, 4, 4}, /* cost of storing integer registers */
1141 4, /* cost of reg,reg fld/fst */
1142 {12, 12, 12}, /* cost of loading fp registers
1143 in SFmode, DFmode and XFmode */
1144 {6, 6, 8}, /* cost of storing fp registers
1145 in SFmode, DFmode and XFmode */
1146 2, /* cost of moving MMX register */
1147 {8, 8}, /* cost of loading MMX registers
1148 in SImode and DImode */
1149 {8, 8}, /* cost of storing MMX registers
1150 in SImode and DImode */
1151 2, /* cost of moving SSE register */
1152 {8, 8, 8}, /* cost of loading SSE registers
1153 in SImode, DImode and TImode */
1154 {8, 8, 8}, /* cost of storing SSE registers
1155 in SImode, DImode and TImode */
1156 5, /* MMX or SSE register to integer */
1157 32, /* size of l1 cache. */
1158 256, /* size of l2 cache. */
1159 64, /* size of prefetch block */
1160 6, /* number of parallel prefetches */
1161 3, /* Branch cost */
1162 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1163 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1164 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1165 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1166 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1167 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1168 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1169 DUMMY_STRINGOP_ALGS},
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 1, /* scalar_stmt_cost. */
1173 1, /* scalar load_cost. */
1174 1, /* scalar_store_cost. */
1175 1, /* vec_stmt_cost. */
1176 1, /* vec_to_scalar_cost. */
1177 1, /* scalar_to_vec_cost. */
1178 1, /* vec_align_load_cost. */
1179 2, /* vec_unalign_load_cost. */
1180 1, /* vec_store_cost. */
1181 3, /* cond_taken_branch_cost. */
1182 1, /* cond_not_taken_branch_cost. */
1185 const struct processor_costs *ix86_cost = &pentium_cost;
1187 /* Processor feature/optimization bitmasks. */
1188 #define m_386 (1<<PROCESSOR_I386)
1189 #define m_486 (1<<PROCESSOR_I486)
1190 #define m_PENT (1<<PROCESSOR_PENTIUM)
1191 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1192 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1193 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1194 #define m_CORE2 (1<<PROCESSOR_CORE2)
1196 #define m_GEODE (1<<PROCESSOR_GEODE)
1197 #define m_K6 (1<<PROCESSOR_K6)
1198 #define m_K6_GEODE (m_K6 | m_GEODE)
1199 #define m_K8 (1<<PROCESSOR_K8)
1200 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1201 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1202 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1203 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1205 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1206 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1208 /* Generic instruction choice should be common subset of supported CPUs
1209 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1210 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1212 /* Feature tests against the various tunings. */
1213 unsigned int ix86_tune_features[X86_TUNE_LAST] = {
1214 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1215 negatively, so enabling for Generic64 seems like good code size
1216 tradeoff. We can't enable it for 32bit generic because it does not
1217 work well with PPro base chips. */
1218 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1220 /* X86_TUNE_PUSH_MEMORY */
1221 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1222 | m_NOCONA | m_CORE2 | m_GENERIC,
1224 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1227 /* X86_TUNE_USE_BIT_TEST */
1230 /* X86_TUNE_UNROLL_STRLEN */
1231 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1233 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1234 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1236 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1237 on simulation result. But after P4 was made, no performance benefit
1238 was observed with branch hints. It also increases the code size.
1239 As a result, icc never generates branch hints. */
1242 /* X86_TUNE_DOUBLE_WITH_ADD */
1245 /* X86_TUNE_USE_SAHF */
1246 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1247 | m_NOCONA | m_CORE2 | m_GENERIC,
1249 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1250 partial dependencies. */
1251 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1252 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1254 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1255 register stalls on Generic32 compilation setting as well. However
1256 in current implementation the partial register stalls are not eliminated
1257 very well - they can be introduced via subregs synthesized by combine
1258 and can happen in caller/callee saving sequences. Because this option
1259 pays back little on PPro based chips and is in conflict with partial reg
1260 dependencies used by Athlon/P4 based chips, it is better to leave it off
1261 for generic32 for now. */
1264 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1265 m_CORE2 | m_GENERIC,
1267 /* X86_TUNE_USE_HIMODE_FIOP */
1268 m_386 | m_486 | m_K6_GEODE,
1270 /* X86_TUNE_USE_SIMODE_FIOP */
1271 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1273 /* X86_TUNE_USE_MOV0 */
1276 /* X86_TUNE_USE_CLTD */
1277 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1279 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1282 /* X86_TUNE_SPLIT_LONG_MOVES */
1285 /* X86_TUNE_READ_MODIFY_WRITE */
1288 /* X86_TUNE_READ_MODIFY */
1291 /* X86_TUNE_PROMOTE_QIMODE */
1292 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1293 | m_GENERIC /* | m_PENT4 ? */,
1295 /* X86_TUNE_FAST_PREFIX */
1296 ~(m_PENT | m_486 | m_386),
1298 /* X86_TUNE_SINGLE_STRINGOP */
1299 m_386 | m_PENT4 | m_NOCONA,
1301 /* X86_TUNE_QIMODE_MATH */
1304 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1305 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1306 might be considered for Generic32 if our scheme for avoiding partial
1307 stalls was more effective. */
1310 /* X86_TUNE_PROMOTE_QI_REGS */
1313 /* X86_TUNE_PROMOTE_HI_REGS */
1316 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1317 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1319 /* X86_TUNE_ADD_ESP_8 */
1320 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1321 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1323 /* X86_TUNE_SUB_ESP_4 */
1324 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_8 */
1327 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1328 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1330 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1331 for DFmode copies */
1332 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1333 | m_GENERIC | m_GEODE),
1335 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1336 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1338 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1339 conflict here in between PPro/Pentium4 based chips that thread 128bit
1340 SSE registers as single units versus K8 based chips that divide SSE
1341 registers to two 64bit halves. This knob promotes all store destinations
1342 to be 128bit to allow register renaming on 128bit SSE units, but usually
1343 results in one extra microop on 64bit SSE units. Experimental results
1344 shows that disabling this option on P4 brings over 20% SPECfp regression,
1345 while enabling it on K8 brings roughly 2.4% regression that can be partly
1346 masked by careful scheduling of moves. */
1347 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1349 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1352 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1353 are resolved on SSE register parts instead of whole registers, so we may
1354 maintain just lower part of scalar values in proper format leaving the
1355 upper part undefined. */
1358 /* X86_TUNE_SSE_TYPELESS_STORES */
1361 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1362 m_PPRO | m_PENT4 | m_NOCONA,
1364 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1365 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1367 /* X86_TUNE_PROLOGUE_USING_MOVE */
1368 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_EPILOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_SHIFT1 */
1376 /* X86_TUNE_USE_FFREEP */
1379 /* X86_TUNE_INTER_UNIT_MOVES */
1380 ~(m_AMD_MULTIPLE | m_GENERIC),
1382 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1385 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1386 than 4 branch instructions in the 16 byte window. */
1387 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1389 /* X86_TUNE_SCHEDULE */
1390 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_USE_BT */
1395 /* X86_TUNE_USE_INCDEC */
1396 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1398 /* X86_TUNE_PAD_RETURNS */
1399 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_EXT_80387_CONSTANTS */
1402 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_SHORTEN_X87_SSE */
1407 /* X86_TUNE_AVOID_VECTOR_DECODE */
1410 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1411 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1414 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1415 vector path on AMD machines. */
1416 m_K8 | m_GENERIC64 | m_AMDFAM10,
1418 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1420 m_K8 | m_GENERIC64 | m_AMDFAM10,
1422 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1426 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1427 but one byte longer. */
1430 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1431 operand that cannot be represented using a modRM byte. The XOR
1432 replacement is long decoded, so this split helps here as well. */
1435 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1436 from integer to FP. */
1440 /* Feature tests against the various architecture variations. */
1441 unsigned int ix86_arch_features[X86_ARCH_LAST] = {
1442 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1443 ~(m_386 | m_486 | m_PENT | m_K6),
1445 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1448 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1451 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1454 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1458 static const unsigned int x86_accumulate_outgoing_args
1459 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1461 static const unsigned int x86_arch_always_fancy_math_387
1462 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1463 | m_NOCONA | m_CORE2 | m_GENERIC;
1465 static enum stringop_alg stringop_alg = no_stringop;
1467 /* In case the average insn count for single function invocation is
1468 lower than this constant, emit fast (but longer) prologue and
1470 #define FAST_PROLOGUE_INSN_COUNT 20
1472 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1473 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1474 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1475 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1477 /* Array of the smallest class containing reg number REGNO, indexed by
1478 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1480 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1482 /* ax, dx, cx, bx */
1483 AREG, DREG, CREG, BREG,
1484 /* si, di, bp, sp */
1485 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1487 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1488 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1491 /* flags, fpsr, fpcr, frame */
1492 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1494 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1497 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1500 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1501 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1502 /* SSE REX registers */
1503 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1507 /* The "default" register map used in 32bit mode. */
1509 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1511 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1512 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1513 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1514 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1515 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1516 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1517 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1520 static int const x86_64_int_parameter_registers[6] =
1522 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1523 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1526 static int const x86_64_ms_abi_int_parameter_registers[4] =
1528 2 /*RCX*/, 1 /*RDX*/,
1529 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1532 static int const x86_64_int_return_registers[4] =
1534 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1537 /* The "default" register map used in 64bit mode. */
1538 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1540 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1541 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1542 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1543 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1544 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1545 8,9,10,11,12,13,14,15, /* extended integer registers */
1546 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1549 /* Define the register numbers to be used in Dwarf debugging information.
1550 The SVR4 reference port C compiler uses the following register numbers
1551 in its Dwarf output code:
1552 0 for %eax (gcc regno = 0)
1553 1 for %ecx (gcc regno = 2)
1554 2 for %edx (gcc regno = 1)
1555 3 for %ebx (gcc regno = 3)
1556 4 for %esp (gcc regno = 7)
1557 5 for %ebp (gcc regno = 6)
1558 6 for %esi (gcc regno = 4)
1559 7 for %edi (gcc regno = 5)
1560 The following three DWARF register numbers are never generated by
1561 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1562 believes these numbers have these meanings.
1563 8 for %eip (no gcc equivalent)
1564 9 for %eflags (gcc regno = 17)
1565 10 for %trapno (no gcc equivalent)
1566 It is not at all clear how we should number the FP stack registers
1567 for the x86 architecture. If the version of SDB on x86/svr4 were
1568 a bit less brain dead with respect to floating-point then we would
1569 have a precedent to follow with respect to DWARF register numbers
1570 for x86 FP registers, but the SDB on x86/svr4 is so completely
1571 broken with respect to FP registers that it is hardly worth thinking
1572 of it as something to strive for compatibility with.
1573 The version of x86/svr4 SDB I have at the moment does (partially)
1574 seem to believe that DWARF register number 11 is associated with
1575 the x86 register %st(0), but that's about all. Higher DWARF
1576 register numbers don't seem to be associated with anything in
1577 particular, and even for DWARF regno 11, SDB only seems to under-
1578 stand that it should say that a variable lives in %st(0) (when
1579 asked via an `=' command) if we said it was in DWARF regno 11,
1580 but SDB still prints garbage when asked for the value of the
1581 variable in question (via a `/' command).
1582 (Also note that the labels SDB prints for various FP stack regs
1583 when doing an `x' command are all wrong.)
1584 Note that these problems generally don't affect the native SVR4
1585 C compiler because it doesn't allow the use of -O with -g and
1586 because when it is *not* optimizing, it allocates a memory
1587 location for each floating-point variable, and the memory
1588 location is what gets described in the DWARF AT_location
1589 attribute for the variable in question.
1590 Regardless of the severe mental illness of the x86/svr4 SDB, we
1591 do something sensible here and we use the following DWARF
1592 register numbers. Note that these are all stack-top-relative
1594 11 for %st(0) (gcc regno = 8)
1595 12 for %st(1) (gcc regno = 9)
1596 13 for %st(2) (gcc regno = 10)
1597 14 for %st(3) (gcc regno = 11)
1598 15 for %st(4) (gcc regno = 12)
1599 16 for %st(5) (gcc regno = 13)
1600 17 for %st(6) (gcc regno = 14)
1601 18 for %st(7) (gcc regno = 15)
1603 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1605 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1606 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1607 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1608 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1609 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1610 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1611 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1614 /* Test and compare insns in i386.md store the information needed to
1615 generate branch and scc insns here. */
1617 rtx ix86_compare_op0 = NULL_RTX;
1618 rtx ix86_compare_op1 = NULL_RTX;
1619 rtx ix86_compare_emitted = NULL_RTX;
1621 /* Size of the register save area. */
1622 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1624 /* Define the structure for the machine field in struct function. */
1626 struct stack_local_entry GTY(())
1628 unsigned short mode;
1631 struct stack_local_entry *next;
1634 /* Structure describing stack frame layout.
1635 Stack grows downward:
1641 saved frame pointer if frame_pointer_needed
1642 <- HARD_FRAME_POINTER
1647 [va_arg registers] (
1648 > to_allocate <- FRAME_POINTER
1658 HOST_WIDE_INT frame;
1660 int outgoing_arguments_size;
1663 HOST_WIDE_INT to_allocate;
1664 /* The offsets relative to ARG_POINTER. */
1665 HOST_WIDE_INT frame_pointer_offset;
1666 HOST_WIDE_INT hard_frame_pointer_offset;
1667 HOST_WIDE_INT stack_pointer_offset;
1669 /* When save_regs_using_mov is set, emit prologue using
1670 move instead of push instructions. */
1671 bool save_regs_using_mov;
1674 /* Code model option. */
1675 enum cmodel ix86_cmodel;
1677 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1679 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1681 /* Which unit we are generating floating point math for. */
1682 enum fpmath_unit ix86_fpmath;
1684 /* Which cpu are we scheduling for. */
1685 enum processor_type ix86_tune;
1687 /* Which instruction set architecture to use. */
1688 enum processor_type ix86_arch;
1690 /* true if sse prefetch instruction is not NOOP. */
1691 int x86_prefetch_sse;
1693 /* ix86_regparm_string as a number */
1694 static int ix86_regparm;
1696 /* -mstackrealign option */
1697 extern int ix86_force_align_arg_pointer;
1698 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1700 /* Preferred alignment for stack boundary in bits. */
1701 unsigned int ix86_preferred_stack_boundary;
1703 /* Values 1-5: see jump.c */
1704 int ix86_branch_cost;
1706 /* Variables which are this size or smaller are put in the data/bss
1707 or ldata/lbss sections. */
1709 int ix86_section_threshold = 65536;
1711 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1712 char internal_label_prefix[16];
1713 int internal_label_prefix_len;
1715 /* Fence to use after loop using movnt. */
1718 /* Register class used for passing given 64bit part of the argument.
1719 These represent classes as documented by the PS ABI, with the exception
1720 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1721 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1723 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1724 whenever possible (upper half does contain padding). */
1725 enum x86_64_reg_class
1728 X86_64_INTEGER_CLASS,
1729 X86_64_INTEGERSI_CLASS,
1736 X86_64_COMPLEX_X87_CLASS,
1739 static const char * const x86_64_reg_class_name[] =
1741 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1742 "sseup", "x87", "x87up", "cplx87", "no"
1745 #define MAX_CLASSES 4
1747 /* Table of constants used by fldpi, fldln2, etc.... */
1748 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1749 static bool ext_80387_constants_init = 0;
1752 static struct machine_function * ix86_init_machine_status (void);
1753 static rtx ix86_function_value (const_tree, const_tree, bool);
1754 static int ix86_function_regparm (const_tree, const_tree);
1755 static void ix86_compute_frame_layout (struct ix86_frame *);
1756 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1760 /* The svr4 ABI for the i386 says that records and unions are returned
1762 #ifndef DEFAULT_PCC_STRUCT_RETURN
1763 #define DEFAULT_PCC_STRUCT_RETURN 1
1766 /* Bit flags that specify the ISA we are compiling for. */
1767 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1769 /* A mask of ix86_isa_flags that includes bit X if X
1770 was set or cleared on the command line. */
1771 static int ix86_isa_flags_explicit;
1773 /* Define a set of ISAs which are available when a given ISA is
1774 enabled. MMX and SSE ISAs are handled separately. */
1776 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1777 #define OPTION_MASK_ISA_3DNOW_SET \
1778 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1780 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1781 #define OPTION_MASK_ISA_SSE2_SET \
1782 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1783 #define OPTION_MASK_ISA_SSE3_SET \
1784 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1785 #define OPTION_MASK_ISA_SSSE3_SET \
1786 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1787 #define OPTION_MASK_ISA_SSE4_1_SET \
1788 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1789 #define OPTION_MASK_ISA_SSE4_2_SET \
1790 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1792 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1794 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1796 #define OPTION_MASK_ISA_SSE4A_SET \
1797 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1798 #define OPTION_MASK_ISA_SSE5_SET \
1799 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1801 /* Define a set of ISAs which aren't available when a given ISA is
1802 disabled. MMX and SSE ISAs are handled separately. */
1804 #define OPTION_MASK_ISA_MMX_UNSET \
1805 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1806 #define OPTION_MASK_ISA_3DNOW_UNSET \
1807 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1808 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1810 #define OPTION_MASK_ISA_SSE_UNSET \
1811 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1812 #define OPTION_MASK_ISA_SSE2_UNSET \
1813 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1814 #define OPTION_MASK_ISA_SSE3_UNSET \
1815 (OPTION_MASK_ISA_SSE3 \
1816 | OPTION_MASK_ISA_SSSE3_UNSET \
1817 | OPTION_MASK_ISA_SSE4A_UNSET )
1818 #define OPTION_MASK_ISA_SSSE3_UNSET \
1819 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1820 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1821 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1822 #define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4_2
1824 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1826 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1828 #define OPTION_MASK_ISA_SSE4A_UNSET \
1829 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1831 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1833 /* Vectorization library interface and handlers. */
1834 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1835 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1836 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1838 /* Implement TARGET_HANDLE_OPTION. */
1841 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1848 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1849 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1853 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1854 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
1861 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
1862 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
1866 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
1867 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
1877 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
1878 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
1882 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
1883 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
1890 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
1891 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
1895 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
1896 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
1903 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
1904 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
1908 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
1909 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
1916 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
1917 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
1921 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
1922 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
1929 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
1930 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
1934 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
1935 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
1942 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
1943 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
1947 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
1948 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
1953 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
1954 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
1958 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
1959 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
1965 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
1966 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
1970 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
1971 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
1978 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
1979 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
1983 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
1984 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
1993 /* Sometimes certain combinations of command options do not make
1994 sense on a particular target machine. You can define a macro
1995 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1996 defined, is executed once just after all the command options have
1999 Don't use this macro to turn on various extra optimizations for
2000 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2003 override_options (void)
2006 int ix86_tune_defaulted = 0;
2007 int ix86_arch_specified = 0;
2008 unsigned int ix86_arch_mask, ix86_tune_mask;
2010 /* Comes from final.c -- no real reason to change it. */
2011 #define MAX_CODE_ALIGN 16
2015 const struct processor_costs *cost; /* Processor costs */
2016 const int align_loop; /* Default alignments. */
2017 const int align_loop_max_skip;
2018 const int align_jump;
2019 const int align_jump_max_skip;
2020 const int align_func;
2022 const processor_target_table[PROCESSOR_max] =
2024 {&i386_cost, 4, 3, 4, 3, 4},
2025 {&i486_cost, 16, 15, 16, 15, 16},
2026 {&pentium_cost, 16, 7, 16, 7, 16},
2027 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2028 {&geode_cost, 0, 0, 0, 0, 0},
2029 {&k6_cost, 32, 7, 32, 7, 32},
2030 {&athlon_cost, 16, 7, 16, 7, 16},
2031 {&pentium4_cost, 0, 0, 0, 0, 0},
2032 {&k8_cost, 16, 7, 16, 7, 16},
2033 {&nocona_cost, 0, 0, 0, 0, 0},
2034 {&core2_cost, 16, 10, 16, 10, 16},
2035 {&generic32_cost, 16, 7, 16, 7, 16},
2036 {&generic64_cost, 16, 10, 16, 10, 16},
2037 {&amdfam10_cost, 32, 24, 32, 7, 32}
2040 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2071 PTA_PREFETCH_SSE = 1 << 4,
2073 PTA_3DNOW_A = 1 << 6,
2077 PTA_POPCNT = 1 << 10,
2079 PTA_SSE4A = 1 << 12,
2080 PTA_NO_SAHF = 1 << 13,
2081 PTA_SSE4_1 = 1 << 14,
2082 PTA_SSE4_2 = 1 << 15,
2085 PTA_PCLMUL = 1 << 18
2090 const char *const name; /* processor name or nickname. */
2091 const enum processor_type processor;
2092 const unsigned /*enum pta_flags*/ flags;
2094 const processor_alias_table[] =
2096 {"i386", PROCESSOR_I386, 0},
2097 {"i486", PROCESSOR_I486, 0},
2098 {"i586", PROCESSOR_PENTIUM, 0},
2099 {"pentium", PROCESSOR_PENTIUM, 0},
2100 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
2101 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
2102 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2103 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2104 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2105 {"i686", PROCESSOR_PENTIUMPRO, 0},
2106 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
2107 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
2108 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2109 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2110 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
2111 {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
2112 {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
2113 {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2114 {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
2115 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2116 | PTA_CX16 | PTA_NO_SAHF)},
2117 {"core2", PROCESSOR_CORE2, (PTA_64BIT
2118 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2121 {"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2122 |PTA_PREFETCH_SSE)},
2123 {"k6", PROCESSOR_K6, PTA_MMX},
2124 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2125 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2126 {"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2127 | PTA_PREFETCH_SSE)},
2128 {"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2129 | PTA_PREFETCH_SSE)},
2130 {"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2132 {"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2134 {"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2136 {"x86-64", PROCESSOR_K8, (PTA_64BIT
2137 | PTA_MMX | PTA_SSE | PTA_SSE2
2139 {"k8", PROCESSOR_K8, (PTA_64BIT
2140 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2141 | PTA_SSE | PTA_SSE2
2143 {"k8-sse3", PROCESSOR_K8, (PTA_64BIT
2144 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2145 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2147 {"opteron", PROCESSOR_K8, (PTA_64BIT
2148 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2149 | PTA_SSE | PTA_SSE2
2151 {"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
2152 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2153 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2155 {"athlon64", PROCESSOR_K8, (PTA_64BIT
2156 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2157 | PTA_SSE | PTA_SSE2
2159 {"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
2160 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2161 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2163 {"athlon-fx", PROCESSOR_K8, (PTA_64BIT
2164 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2165 | PTA_SSE | PTA_SSE2
2167 {"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
2168 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2169 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2171 | PTA_CX16 | PTA_ABM)},
2172 {"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
2173 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2174 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2176 | PTA_CX16 | PTA_ABM)},
2177 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
2178 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
2181 int const pta_size = ARRAY_SIZE (processor_alias_table);
2183 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2184 SUBTARGET_OVERRIDE_OPTIONS;
2187 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2188 SUBSUBTARGET_OVERRIDE_OPTIONS;
2191 /* -fPIC is the default for x86_64. */
2192 if (TARGET_MACHO && TARGET_64BIT)
2195 /* Set the default values for switches whose default depends on TARGET_64BIT
2196 in case they weren't overwritten by command line options. */
2199 /* Mach-O doesn't support omitting the frame pointer for now. */
2200 if (flag_omit_frame_pointer == 2)
2201 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2202 if (flag_asynchronous_unwind_tables == 2)
2203 flag_asynchronous_unwind_tables = 1;
2204 if (flag_pcc_struct_return == 2)
2205 flag_pcc_struct_return = 0;
2209 if (flag_omit_frame_pointer == 2)
2210 flag_omit_frame_pointer = 0;
2211 if (flag_asynchronous_unwind_tables == 2)
2212 flag_asynchronous_unwind_tables = 0;
2213 if (flag_pcc_struct_return == 2)
2214 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2217 /* Need to check -mtune=generic first. */
2218 if (ix86_tune_string)
2220 if (!strcmp (ix86_tune_string, "generic")
2221 || !strcmp (ix86_tune_string, "i686")
2222 /* As special support for cross compilers we read -mtune=native
2223 as -mtune=generic. With native compilers we won't see the
2224 -mtune=native, as it was changed by the driver. */
2225 || !strcmp (ix86_tune_string, "native"))
2228 ix86_tune_string = "generic64";
2230 ix86_tune_string = "generic32";
2232 else if (!strncmp (ix86_tune_string, "generic", 7))
2233 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2237 if (ix86_arch_string)
2238 ix86_tune_string = ix86_arch_string;
2239 if (!ix86_tune_string)
2241 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2242 ix86_tune_defaulted = 1;
2245 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2246 need to use a sensible tune option. */
2247 if (!strcmp (ix86_tune_string, "generic")
2248 || !strcmp (ix86_tune_string, "x86-64")
2249 || !strcmp (ix86_tune_string, "i686"))
2252 ix86_tune_string = "generic64";
2254 ix86_tune_string = "generic32";
2257 if (ix86_stringop_string)
2259 if (!strcmp (ix86_stringop_string, "rep_byte"))
2260 stringop_alg = rep_prefix_1_byte;
2261 else if (!strcmp (ix86_stringop_string, "libcall"))
2262 stringop_alg = libcall;
2263 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2264 stringop_alg = rep_prefix_4_byte;
2265 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2266 stringop_alg = rep_prefix_8_byte;
2267 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2268 stringop_alg = loop_1_byte;
2269 else if (!strcmp (ix86_stringop_string, "loop"))
2270 stringop_alg = loop;
2271 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2272 stringop_alg = unrolled_loop;
2274 error ("bad value (%s) for -mstringop-strategy= switch", ix86_stringop_string);
2276 if (!strcmp (ix86_tune_string, "x86-64"))
2277 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
2278 "-mtune=generic instead as appropriate.");
2280 if (!ix86_arch_string)
2281 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2283 ix86_arch_specified = 1;
2285 if (!strcmp (ix86_arch_string, "generic"))
2286 error ("generic CPU can be used only for -mtune= switch");
2287 if (!strncmp (ix86_arch_string, "generic", 7))
2288 error ("bad value (%s) for -march= switch", ix86_arch_string);
2290 if (ix86_cmodel_string != 0)
2292 if (!strcmp (ix86_cmodel_string, "small"))
2293 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2294 else if (!strcmp (ix86_cmodel_string, "medium"))
2295 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2296 else if (!strcmp (ix86_cmodel_string, "large"))
2297 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2299 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2300 else if (!strcmp (ix86_cmodel_string, "32"))
2301 ix86_cmodel = CM_32;
2302 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2303 ix86_cmodel = CM_KERNEL;
2305 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
2309 /* For TARGET_64BIT_MS_ABI, force pic on, in order to enable the
2310 use of rip-relative addressing. This eliminates fixups that
2311 would otherwise be needed if this object is to be placed in a
2312 DLL, and is essentially just as efficient as direct addressing. */
2313 if (TARGET_64BIT_MS_ABI)
2314 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2315 else if (TARGET_64BIT)
2316 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2318 ix86_cmodel = CM_32;
2320 if (ix86_asm_string != 0)
2323 && !strcmp (ix86_asm_string, "intel"))
2324 ix86_asm_dialect = ASM_INTEL;
2325 else if (!strcmp (ix86_asm_string, "att"))
2326 ix86_asm_dialect = ASM_ATT;
2328 error ("bad value (%s) for -masm= switch", ix86_asm_string);
2330 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2331 error ("code model %qs not supported in the %s bit mode",
2332 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2333 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2334 sorry ("%i-bit mode not compiled in",
2335 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2337 for (i = 0; i < pta_size; i++)
2338 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2340 ix86_arch = processor_alias_table[i].processor;
2341 /* Default cpu tuning to the architecture. */
2342 ix86_tune = ix86_arch;
2344 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2345 error ("CPU you selected does not support x86-64 "
2348 if (processor_alias_table[i].flags & PTA_MMX
2349 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2350 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2351 if (processor_alias_table[i].flags & PTA_3DNOW
2352 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2353 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2354 if (processor_alias_table[i].flags & PTA_3DNOW_A
2355 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2356 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2357 if (processor_alias_table[i].flags & PTA_SSE
2358 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2359 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2360 if (processor_alias_table[i].flags & PTA_SSE2
2361 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2362 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2363 if (processor_alias_table[i].flags & PTA_SSE3
2364 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2365 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2366 if (processor_alias_table[i].flags & PTA_SSSE3
2367 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2368 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2369 if (processor_alias_table[i].flags & PTA_SSE4_1
2370 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2371 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2372 if (processor_alias_table[i].flags & PTA_SSE4_2
2373 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2374 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2375 if (processor_alias_table[i].flags & PTA_SSE4A
2376 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2377 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2378 if (processor_alias_table[i].flags & PTA_SSE5
2379 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2380 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2382 if (processor_alias_table[i].flags & PTA_ABM)
2384 if (processor_alias_table[i].flags & PTA_CX16)
2385 x86_cmpxchg16b = true;
2386 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM))
2388 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2389 x86_prefetch_sse = true;
2390 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF)))
2392 if (processor_alias_table[i].flags & PTA_AES)
2394 if (processor_alias_table[i].flags & PTA_PCLMUL)
2401 error ("bad value (%s) for -march= switch", ix86_arch_string);
2403 ix86_arch_mask = 1u << ix86_arch;
2404 for (i = 0; i < X86_ARCH_LAST; ++i)
2405 ix86_arch_features[i] &= ix86_arch_mask;
2407 for (i = 0; i < pta_size; i++)
2408 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2410 ix86_tune = processor_alias_table[i].processor;
2411 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2413 if (ix86_tune_defaulted)
2415 ix86_tune_string = "x86-64";
2416 for (i = 0; i < pta_size; i++)
2417 if (! strcmp (ix86_tune_string,
2418 processor_alias_table[i].name))
2420 ix86_tune = processor_alias_table[i].processor;
2423 error ("CPU you selected does not support x86-64 "
2426 /* Intel CPUs have always interpreted SSE prefetch instructions as
2427 NOPs; so, we can enable SSE prefetch instructions even when
2428 -mtune (rather than -march) points us to a processor that has them.
2429 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2430 higher processors. */
2432 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2433 x86_prefetch_sse = true;
2437 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2439 /* Enable SSE2 if AES or PCLMUL is enabled. */
2440 if ((x86_aes || x86_pclmul)
2441 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2443 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2444 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2447 ix86_tune_mask = 1u << ix86_tune;
2448 for (i = 0; i < X86_TUNE_LAST; ++i)
2449 ix86_tune_features[i] &= ix86_tune_mask;
2452 ix86_cost = &size_cost;
2454 ix86_cost = processor_target_table[ix86_tune].cost;
2456 /* Arrange to set up i386_stack_locals for all functions. */
2457 init_machine_status = ix86_init_machine_status;
2459 /* Validate -mregparm= value. */
2460 if (ix86_regparm_string)
2463 warning (0, "-mregparm is ignored in 64-bit mode");
2464 i = atoi (ix86_regparm_string);
2465 if (i < 0 || i > REGPARM_MAX)
2466 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
2471 ix86_regparm = REGPARM_MAX;
2473 /* If the user has provided any of the -malign-* options,
2474 warn and use that value only if -falign-* is not set.
2475 Remove this code in GCC 3.2 or later. */
2476 if (ix86_align_loops_string)
2478 warning (0, "-malign-loops is obsolete, use -falign-loops");
2479 if (align_loops == 0)
2481 i = atoi (ix86_align_loops_string);
2482 if (i < 0 || i > MAX_CODE_ALIGN)
2483 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2485 align_loops = 1 << i;
2489 if (ix86_align_jumps_string)
2491 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
2492 if (align_jumps == 0)
2494 i = atoi (ix86_align_jumps_string);
2495 if (i < 0 || i > MAX_CODE_ALIGN)
2496 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2498 align_jumps = 1 << i;
2502 if (ix86_align_funcs_string)
2504 warning (0, "-malign-functions is obsolete, use -falign-functions");
2505 if (align_functions == 0)
2507 i = atoi (ix86_align_funcs_string);
2508 if (i < 0 || i > MAX_CODE_ALIGN)
2509 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2511 align_functions = 1 << i;
2515 /* Default align_* from the processor table. */
2516 if (align_loops == 0)
2518 align_loops = processor_target_table[ix86_tune].align_loop;
2519 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2521 if (align_jumps == 0)
2523 align_jumps = processor_target_table[ix86_tune].align_jump;
2524 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2526 if (align_functions == 0)
2528 align_functions = processor_target_table[ix86_tune].align_func;
2531 /* Validate -mbranch-cost= value, or provide default. */
2532 ix86_branch_cost = ix86_cost->branch_cost;
2533 if (ix86_branch_cost_string)
2535 i = atoi (ix86_branch_cost_string);
2537 error ("-mbranch-cost=%d is not between 0 and 5", i);
2539 ix86_branch_cost = i;
2541 if (ix86_section_threshold_string)
2543 i = atoi (ix86_section_threshold_string);
2545 error ("-mlarge-data-threshold=%d is negative", i);
2547 ix86_section_threshold = i;
2550 if (ix86_tls_dialect_string)
2552 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2553 ix86_tls_dialect = TLS_DIALECT_GNU;
2554 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2555 ix86_tls_dialect = TLS_DIALECT_GNU2;
2556 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2557 ix86_tls_dialect = TLS_DIALECT_SUN;
2559 error ("bad value (%s) for -mtls-dialect= switch",
2560 ix86_tls_dialect_string);
2563 if (ix87_precision_string)
2565 i = atoi (ix87_precision_string);
2566 if (i != 32 && i != 64 && i != 80)
2567 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
2572 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
2574 /* Enable by default the SSE and MMX builtins. Do allow the user to
2575 explicitly disable any of these. In particular, disabling SSE and
2576 MMX for kernel code is extremely useful. */
2577 if (!ix86_arch_specified)
2579 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
2580 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
2583 warning (0, "-mrtd is ignored in 64bit mode");
2587 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
2589 if (!ix86_arch_specified)
2591 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
2593 /* i386 ABI does not specify red zone. It still makes sense to use it
2594 when programmer takes care to stack from being destroyed. */
2595 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2596 target_flags |= MASK_NO_RED_ZONE;
2599 /* Keep nonleaf frame pointers. */
2600 if (flag_omit_frame_pointer)
2601 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
2602 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
2603 flag_omit_frame_pointer = 1;
2605 /* If we're doing fast math, we don't care about comparison order
2606 wrt NaNs. This lets us use a shorter comparison sequence. */
2607 if (flag_finite_math_only)
2608 target_flags &= ~MASK_IEEE_FP;
2610 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2611 since the insns won't need emulation. */
2612 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
2613 target_flags &= ~MASK_NO_FANCY_MATH_387;
2615 /* Likewise, if the target doesn't have a 387, or we've specified
2616 software floating point, don't use 387 inline intrinsics. */
2618 target_flags |= MASK_NO_FANCY_MATH_387;
2620 /* Turn on MMX builtins for -msse. */
2623 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
2624 x86_prefetch_sse = true;
2627 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
2628 if (TARGET_SSE4_2 || TARGET_ABM)
2631 /* Validate -mpreferred-stack-boundary= value, or provide default.
2632 The default of 128 bits is for Pentium III's SSE __m128. We can't
2633 change it because of optimize_size. Otherwise, we can't mix object
2634 files compiled with -Os and -On. */
2635 ix86_preferred_stack_boundary = 128;
2636 if (ix86_preferred_stack_boundary_string)
2638 i = atoi (ix86_preferred_stack_boundary_string);
2639 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
2640 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
2641 TARGET_64BIT ? 4 : 2);
2643 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
2646 /* Accept -msseregparm only if at least SSE support is enabled. */
2647 if (TARGET_SSEREGPARM
2649 error ("-msseregparm used without SSE enabled");
2651 ix86_fpmath = TARGET_FPMATH_DEFAULT;
2652 if (ix86_fpmath_string != 0)
2654 if (! strcmp (ix86_fpmath_string, "387"))
2655 ix86_fpmath = FPMATH_387;
2656 else if (! strcmp (ix86_fpmath_string, "sse"))
2660 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2661 ix86_fpmath = FPMATH_387;
2664 ix86_fpmath = FPMATH_SSE;
2666 else if (! strcmp (ix86_fpmath_string, "387,sse")
2667 || ! strcmp (ix86_fpmath_string, "sse,387"))
2671 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2672 ix86_fpmath = FPMATH_387;
2674 else if (!TARGET_80387)
2676 warning (0, "387 instruction set disabled, using SSE arithmetics");
2677 ix86_fpmath = FPMATH_SSE;
2680 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
2683 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
2686 /* If the i387 is disabled, then do not return values in it. */
2688 target_flags &= ~MASK_FLOAT_RETURNS;
2690 /* Use external vectorized library in vectorizing intrinsics. */
2691 if (ix86_veclibabi_string)
2693 if (strcmp (ix86_veclibabi_string, "svml") == 0)
2694 ix86_veclib_handler = ix86_veclibabi_svml;
2695 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
2696 ix86_veclib_handler = ix86_veclibabi_acml;
2698 error ("unknown vectorization library ABI type (%s) for "
2699 "-mveclibabi= switch", ix86_veclibabi_string);
2702 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
2703 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2705 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2707 /* ??? Unwind info is not correct around the CFG unless either a frame
2708 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2709 unwind info generation to be aware of the CFG and propagating states
2711 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
2712 || flag_exceptions || flag_non_call_exceptions)
2713 && flag_omit_frame_pointer
2714 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2716 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2717 warning (0, "unwind tables currently require either a frame pointer "
2718 "or -maccumulate-outgoing-args for correctness");
2719 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2722 /* If stack probes are required, the space used for large function
2723 arguments on the stack must also be probed, so enable
2724 -maccumulate-outgoing-args so this happens in the prologue. */
2725 if (TARGET_STACK_PROBE
2726 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2728 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2729 warning (0, "stack probing requires -maccumulate-outgoing-args "
2731 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2734 /* For sane SSE instruction set generation we need fcomi instruction.
2735 It is safe to enable all CMOVE instructions. */
2739 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2742 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
2743 p = strchr (internal_label_prefix, 'X');
2744 internal_label_prefix_len = p - internal_label_prefix;
2748 /* When scheduling description is not available, disable scheduler pass
2749 so it won't slow down the compilation and make x87 code slower. */
2750 if (!TARGET_SCHEDULE)
2751 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
2753 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
2754 set_param_value ("simultaneous-prefetches",
2755 ix86_cost->simultaneous_prefetches);
2756 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
2757 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
2758 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
2759 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
2760 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
2761 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
2763 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
2764 can be optimized to ap = __builtin_next_arg (0). */
2765 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
2766 targetm.expand_builtin_va_start = NULL;
2769 /* Return true if this goes in large data/bss. */
2772 ix86_in_large_data_p (tree exp)
2774 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
2777 /* Functions are never large data. */
2778 if (TREE_CODE (exp) == FUNCTION_DECL)
2781 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
2783 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
2784 if (strcmp (section, ".ldata") == 0
2785 || strcmp (section, ".lbss") == 0)
2791 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
2793 /* If this is an incomplete type with size 0, then we can't put it
2794 in data because it might be too big when completed. */
2795 if (!size || size > ix86_section_threshold)
2802 /* Switch to the appropriate section for output of DECL.
2803 DECL is either a `VAR_DECL' node or a constant of some sort.
2804 RELOC indicates whether forming the initial value of DECL requires
2805 link-time relocations. */
2807 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
2811 x86_64_elf_select_section (tree decl, int reloc,
2812 unsigned HOST_WIDE_INT align)
2814 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2815 && ix86_in_large_data_p (decl))
2817 const char *sname = NULL;
2818 unsigned int flags = SECTION_WRITE;
2819 switch (categorize_decl_for_section (decl, reloc))
2824 case SECCAT_DATA_REL:
2825 sname = ".ldata.rel";
2827 case SECCAT_DATA_REL_LOCAL:
2828 sname = ".ldata.rel.local";
2830 case SECCAT_DATA_REL_RO:
2831 sname = ".ldata.rel.ro";
2833 case SECCAT_DATA_REL_RO_LOCAL:
2834 sname = ".ldata.rel.ro.local";
2838 flags |= SECTION_BSS;
2841 case SECCAT_RODATA_MERGE_STR:
2842 case SECCAT_RODATA_MERGE_STR_INIT:
2843 case SECCAT_RODATA_MERGE_CONST:
2847 case SECCAT_SRODATA:
2854 /* We don't split these for medium model. Place them into
2855 default sections and hope for best. */
2857 case SECCAT_EMUTLS_VAR:
2858 case SECCAT_EMUTLS_TMPL:
2863 /* We might get called with string constants, but get_named_section
2864 doesn't like them as they are not DECLs. Also, we need to set
2865 flags in that case. */
2867 return get_section (sname, flags, NULL);
2868 return get_named_section (decl, sname, reloc);
2871 return default_elf_select_section (decl, reloc, align);
2874 /* Build up a unique section name, expressed as a
2875 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2876 RELOC indicates whether the initial value of EXP requires
2877 link-time relocations. */
2879 static void ATTRIBUTE_UNUSED
2880 x86_64_elf_unique_section (tree decl, int reloc)
2882 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2883 && ix86_in_large_data_p (decl))
2885 const char *prefix = NULL;
2886 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2887 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2889 switch (categorize_decl_for_section (decl, reloc))
2892 case SECCAT_DATA_REL:
2893 case SECCAT_DATA_REL_LOCAL:
2894 case SECCAT_DATA_REL_RO:
2895 case SECCAT_DATA_REL_RO_LOCAL:
2896 prefix = one_only ? ".ld" : ".ldata";
2899 prefix = one_only ? ".lb" : ".lbss";
2902 case SECCAT_RODATA_MERGE_STR:
2903 case SECCAT_RODATA_MERGE_STR_INIT:
2904 case SECCAT_RODATA_MERGE_CONST:
2905 prefix = one_only ? ".lr" : ".lrodata";
2907 case SECCAT_SRODATA:
2914 /* We don't split these for medium model. Place them into
2915 default sections and hope for best. */
2917 case SECCAT_EMUTLS_VAR:
2918 prefix = targetm.emutls.var_section;
2920 case SECCAT_EMUTLS_TMPL:
2921 prefix = targetm.emutls.tmpl_section;
2926 const char *name, *linkonce;
2929 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2930 name = targetm.strip_name_encoding (name);
2932 /* If we're using one_only, then there needs to be a .gnu.linkonce
2933 prefix to the section name. */
2934 linkonce = one_only ? ".gnu.linkonce" : "";
2936 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
2938 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
2942 default_unique_section (decl, reloc);
2945 #ifdef COMMON_ASM_OP
2946 /* This says how to output assembler code to declare an
2947 uninitialized external linkage data object.
2949 For medium model x86-64 we need to use .largecomm opcode for
2952 x86_elf_aligned_common (FILE *file,
2953 const char *name, unsigned HOST_WIDE_INT size,
2956 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2957 && size > (unsigned int)ix86_section_threshold)
2958 fprintf (file, ".largecomm\t");
2960 fprintf (file, "%s", COMMON_ASM_OP);
2961 assemble_name (file, name);
2962 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2963 size, align / BITS_PER_UNIT);
2967 /* Utility function for targets to use in implementing
2968 ASM_OUTPUT_ALIGNED_BSS. */
2971 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2972 const char *name, unsigned HOST_WIDE_INT size,
2975 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2976 && size > (unsigned int)ix86_section_threshold)
2977 switch_to_section (get_named_section (decl, ".lbss", 0));
2979 switch_to_section (bss_section);
2980 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2981 #ifdef ASM_DECLARE_OBJECT_NAME
2982 last_assemble_variable_decl = decl;
2983 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2985 /* Standard thing is just output label for the object. */
2986 ASM_OUTPUT_LABEL (file, name);
2987 #endif /* ASM_DECLARE_OBJECT_NAME */
2988 ASM_OUTPUT_SKIP (file, size ? size : 1);
2992 optimization_options (int level, int size ATTRIBUTE_UNUSED)
2994 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2995 make the problem with not enough registers even worse. */
2996 #ifdef INSN_SCHEDULING
2998 flag_schedule_insns = 0;
3002 /* The Darwin libraries never set errno, so we might as well
3003 avoid calling them when that's the only reason we would. */
3004 flag_errno_math = 0;
3006 /* The default values of these switches depend on the TARGET_64BIT
3007 that is not known at this moment. Mark these values with 2 and
3008 let user the to override these. In case there is no command line option
3009 specifying them, we will set the defaults in override_options. */
3011 flag_omit_frame_pointer = 2;
3012 flag_pcc_struct_return = 2;
3013 flag_asynchronous_unwind_tables = 2;
3014 flag_vect_cost_model = 1;
3015 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
3016 SUBTARGET_OPTIMIZATION_OPTIONS;
3020 /* Decide whether we can make a sibling call to a function. DECL is the
3021 declaration of the function being targeted by the call and EXP is the
3022 CALL_EXPR representing the call. */
3025 ix86_function_ok_for_sibcall (tree decl, tree exp)
3030 /* If we are generating position-independent code, we cannot sibcall
3031 optimize any indirect call, or a direct call to a global function,
3032 as the PLT requires %ebx be live. */
3033 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
3040 func = TREE_TYPE (CALL_EXPR_FN (exp));
3041 if (POINTER_TYPE_P (func))
3042 func = TREE_TYPE (func);
3045 /* Check that the return value locations are the same. Like
3046 if we are returning floats on the 80387 register stack, we cannot
3047 make a sibcall from a function that doesn't return a float to a
3048 function that does or, conversely, from a function that does return
3049 a float to a function that doesn't; the necessary stack adjustment
3050 would not be executed. This is also the place we notice
3051 differences in the return value ABI. Note that it is ok for one
3052 of the functions to have void return type as long as the return
3053 value of the other is passed in a register. */
3054 a = ix86_function_value (TREE_TYPE (exp), func, false);
3055 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
3057 if (STACK_REG_P (a) || STACK_REG_P (b))
3059 if (!rtx_equal_p (a, b))
3062 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
3064 else if (!rtx_equal_p (a, b))
3067 /* If this call is indirect, we'll need to be able to use a call-clobbered
3068 register for the address of the target function. Make sure that all
3069 such registers are not used for passing parameters. */
3070 if (!decl && !TARGET_64BIT)
3074 /* We're looking at the CALL_EXPR, we need the type of the function. */
3075 type = CALL_EXPR_FN (exp); /* pointer expression */
3076 type = TREE_TYPE (type); /* pointer type */
3077 type = TREE_TYPE (type); /* function type */
3079 if (ix86_function_regparm (type, NULL) >= 3)
3081 /* ??? Need to count the actual number of registers to be used,
3082 not the possible number of registers. Fix later. */
3087 /* Dllimport'd functions are also called indirectly. */
3088 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
3089 && decl && DECL_DLLIMPORT_P (decl)
3090 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
3093 /* If we forced aligned the stack, then sibcalling would unalign the
3094 stack, which may break the called function. */
3095 if (cfun->machine->force_align_arg_pointer)
3098 /* Otherwise okay. That also includes certain types of indirect calls. */
3102 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
3103 calling convention attributes;
3104 arguments as in struct attribute_spec.handler. */
3107 ix86_handle_cconv_attribute (tree *node, tree name,
3109 int flags ATTRIBUTE_UNUSED,
3112 if (TREE_CODE (*node) != FUNCTION_TYPE
3113 && TREE_CODE (*node) != METHOD_TYPE
3114 && TREE_CODE (*node) != FIELD_DECL
3115 && TREE_CODE (*node) != TYPE_DECL)
3117 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3118 IDENTIFIER_POINTER (name));
3119 *no_add_attrs = true;
3123 /* Can combine regparm with all attributes but fastcall. */
3124 if (is_attribute_p ("regparm", name))
3128 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3130 error ("fastcall and regparm attributes are not compatible");
3133 cst = TREE_VALUE (args);
3134 if (TREE_CODE (cst) != INTEGER_CST)
3136 warning (OPT_Wattributes,
3137 "%qs attribute requires an integer constant argument",
3138 IDENTIFIER_POINTER (name));
3139 *no_add_attrs = true;
3141 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
3143 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
3144 IDENTIFIER_POINTER (name), REGPARM_MAX);
3145 *no_add_attrs = true;
3149 && lookup_attribute (ix86_force_align_arg_pointer_string,
3150 TYPE_ATTRIBUTES (*node))
3151 && compare_tree_int (cst, REGPARM_MAX-1))
3153 error ("%s functions limited to %d register parameters",
3154 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
3162 /* Do not warn when emulating the MS ABI. */
3163 if (!TARGET_64BIT_MS_ABI)
3164 warning (OPT_Wattributes, "%qs attribute ignored",
3165 IDENTIFIER_POINTER (name));
3166 *no_add_attrs = true;
3170 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
3171 if (is_attribute_p ("fastcall", name))
3173 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3175 error ("fastcall and cdecl attributes are not compatible");
3177 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3179 error ("fastcall and stdcall attributes are not compatible");
3181 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
3183 error ("fastcall and regparm attributes are not compatible");
3187 /* Can combine stdcall with fastcall (redundant), regparm and
3189 else if (is_attribute_p ("stdcall", name))
3191 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
3193 error ("stdcall and cdecl attributes are not compatible");
3195 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3197 error ("stdcall and fastcall attributes are not compatible");
3201 /* Can combine cdecl with regparm and sseregparm. */
3202 else if (is_attribute_p ("cdecl", name))
3204 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
3206 error ("stdcall and cdecl attributes are not compatible");
3208 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
3210 error ("fastcall and cdecl attributes are not compatible");
3214 /* Can combine sseregparm with all attributes. */
3219 /* Return 0 if the attributes for two types are incompatible, 1 if they
3220 are compatible, and 2 if they are nearly compatible (which causes a
3221 warning to be generated). */
3224 ix86_comp_type_attributes (const_tree type1, const_tree type2)
3226 /* Check for mismatch of non-default calling convention. */
3227 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
3229 if (TREE_CODE (type1) != FUNCTION_TYPE
3230 && TREE_CODE (type1) != METHOD_TYPE)
3233 /* Check for mismatched fastcall/regparm types. */
3234 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
3235 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
3236 || (ix86_function_regparm (type1, NULL)
3237 != ix86_function_regparm (type2, NULL)))
3240 /* Check for mismatched sseregparm types. */
3241 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
3242 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
3245 /* Check for mismatched return types (cdecl vs stdcall). */
3246 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
3247 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
3253 /* Return the regparm value for a function with the indicated TYPE and DECL.
3254 DECL may be NULL when calling function indirectly
3255 or considering a libcall. */
3258 ix86_function_regparm (const_tree type, const_tree decl)
3261 int regparm = ix86_regparm;
3263 static bool error_issued;
3268 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
3272 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
3274 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
3276 /* We can't use regparm(3) for nested functions because
3277 these pass static chain pointer in %ecx register. */
3278 if (!error_issued && regparm == 3
3279 && decl_function_context (decl)
3280 && !DECL_NO_STATIC_CHAIN (decl))
3282 error ("nested functions are limited to 2 register parameters");
3283 error_issued = true;
3291 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
3294 /* Use register calling convention for local functions when possible. */
3295 if (decl && TREE_CODE (decl) == FUNCTION_DECL
3296 && flag_unit_at_a_time && !profile_flag)
3298 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3299 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3302 int local_regparm, globals = 0, regno;
3305 /* Make sure no regparm register is taken by a
3306 fixed register variable. */
3307 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
3308 if (fixed_regs[local_regparm])
3311 /* We can't use regparm(3) for nested functions as these use
3312 static chain pointer in third argument. */
3313 if (local_regparm == 3
3314 && (decl_function_context (decl)
3315 || ix86_force_align_arg_pointer)
3316 && !DECL_NO_STATIC_CHAIN (decl))
3319 /* If the function realigns its stackpointer, the prologue will
3320 clobber %ecx. If we've already generated code for the callee,
3321 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
3322 scanning the attributes for the self-realigning property. */
3323 f = DECL_STRUCT_FUNCTION (decl);
3324 if (local_regparm == 3
3325 && (f ? !!f->machine->force_align_arg_pointer
3326 : !!lookup_attribute (ix86_force_align_arg_pointer_string,
3327 TYPE_ATTRIBUTES (TREE_TYPE (decl)))))
3330 /* Each fixed register usage increases register pressure,
3331 so less registers should be used for argument passing.
3332 This functionality can be overriden by an explicit
3334 for (regno = 0; regno <= DI_REG; regno++)
3335 if (fixed_regs[regno])
3339 = globals < local_regparm ? local_regparm - globals : 0;
3341 if (local_regparm > regparm)
3342 regparm = local_regparm;
3349 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
3350 DFmode (2) arguments in SSE registers for a function with the
3351 indicated TYPE and DECL. DECL may be NULL when calling function
3352 indirectly or considering a libcall. Otherwise return 0. */
3355 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
3357 gcc_assert (!TARGET_64BIT);
3359 /* Use SSE registers to pass SFmode and DFmode arguments if requested
3360 by the sseregparm attribute. */
3361 if (TARGET_SSEREGPARM
3362 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
3369 error ("Calling %qD with attribute sseregparm without "
3370 "SSE/SSE2 enabled", decl);
3372 error ("Calling %qT with attribute sseregparm without "
3373 "SSE/SSE2 enabled", type);
3381 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
3382 (and DFmode for SSE2) arguments in SSE registers. */
3383 if (decl && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
3385 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
3386 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
3388 return TARGET_SSE2 ? 2 : 1;
3394 /* Return true if EAX is live at the start of the function. Used by
3395 ix86_expand_prologue to determine if we need special help before
3396 calling allocate_stack_worker. */
3399 ix86_eax_live_at_start_p (void)
3401 /* Cheat. Don't bother working forward from ix86_function_regparm
3402 to the function type to whether an actual argument is located in
3403 eax. Instead just look at cfg info, which is still close enough
3404 to correct at this point. This gives false positives for broken
3405 functions that might use uninitialized data that happens to be
3406 allocated in eax, but who cares? */
3407 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
3410 /* Value is the number of bytes of arguments automatically
3411 popped when returning from a subroutine call.
3412 FUNDECL is the declaration node of the function (as a tree),
3413 FUNTYPE is the data type of the function (as a tree),
3414 or for a library call it is an identifier node for the subroutine name.
3415 SIZE is the number of bytes of arguments passed on the stack.
3417 On the 80386, the RTD insn may be used to pop them if the number
3418 of args is fixed, but if the number is variable then the caller
3419 must pop them all. RTD can't be used for library calls now
3420 because the library is compiled with the Unix compiler.
3421 Use of RTD is a selectable option, since it is incompatible with
3422 standard Unix calling sequences. If the option is not selected,
3423 the caller must always pop the args.
3425 The attribute stdcall is equivalent to RTD on a per module basis. */
3428 ix86_return_pops_args (tree fundecl, tree funtype, int size)
3432 /* None of the 64-bit ABIs pop arguments. */
3436 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
3438 /* Cdecl functions override -mrtd, and never pop the stack. */
3439 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
3441 /* Stdcall and fastcall functions will pop the stack if not
3443 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
3444 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
3447 if (rtd && ! stdarg_p (funtype))
3451 /* Lose any fake structure return argument if it is passed on the stack. */
3452 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
3453 && !KEEP_AGGREGATE_RETURN_POINTER)
3455 int nregs = ix86_function_regparm (funtype, fundecl);
3457 return GET_MODE_SIZE (Pmode);
3463 /* Argument support functions. */
3465 /* Return true when register may be used to pass function parameters. */
3467 ix86_function_arg_regno_p (int regno)
3470 const int *parm_regs;
3475 return (regno < REGPARM_MAX
3476 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
3478 return (regno < REGPARM_MAX
3479 || (TARGET_MMX && MMX_REGNO_P (regno)
3480 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
3481 || (TARGET_SSE && SSE_REGNO_P (regno)
3482 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
3487 if (SSE_REGNO_P (regno) && TARGET_SSE)
3492 if (TARGET_SSE && SSE_REGNO_P (regno)
3493 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
3497 /* RAX is used as hidden argument to va_arg functions. */
3498 if (!TARGET_64BIT_MS_ABI && regno == AX_REG)
3501 if (TARGET_64BIT_MS_ABI)
3502 parm_regs = x86_64_ms_abi_int_parameter_registers;
3504 parm_regs = x86_64_int_parameter_registers;
3505 for (i = 0; i < REGPARM_MAX; i++)
3506 if (regno == parm_regs[i])
3511 /* Return if we do not know how to pass TYPE solely in registers. */
3514 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
3516 if (must_pass_in_stack_var_size_or_pad (mode, type))
3519 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
3520 The layout_type routine is crafty and tries to trick us into passing
3521 currently unsupported vector types on the stack by using TImode. */
3522 return (!TARGET_64BIT && mode == TImode
3523 && type && TREE_CODE (type) != VECTOR_TYPE);
3526 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3527 for a call to a function whose data type is FNTYPE.
3528 For a library call, FNTYPE is 0. */
3531 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
3532 tree fntype, /* tree ptr for function decl */
3533 rtx libname, /* SYMBOL_REF of library name or 0 */
3536 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
3537 memset (cum, 0, sizeof (*cum));
3539 /* Set up the number of registers to use for passing arguments. */
3540 cum->nregs = ix86_regparm;
3542 cum->sse_nregs = SSE_REGPARM_MAX;
3544 cum->mmx_nregs = MMX_REGPARM_MAX;
3545 cum->warn_sse = true;
3546 cum->warn_mmx = true;
3548 /* Because type might mismatch in between caller and callee, we need to
3549 use actual type of function for local calls.
3550 FIXME: cgraph_analyze can be told to actually record if function uses
3551 va_start so for local functions maybe_vaarg can be made aggressive
3553 FIXME: once typesytem is fixed, we won't need this code anymore. */
3555 fntype = TREE_TYPE (fndecl);
3556 cum->maybe_vaarg = (fntype
3557 ? (!prototype_p (fntype) || stdarg_p (fntype))
3562 /* If there are variable arguments, then we won't pass anything
3563 in registers in 32-bit mode. */
3564 if (stdarg_p (fntype))
3574 /* Use ecx and edx registers if function has fastcall attribute,
3575 else look for regparm information. */
3578 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
3584 cum->nregs = ix86_function_regparm (fntype, fndecl);
3587 /* Set up the number of SSE registers used for passing SFmode
3588 and DFmode arguments. Warn for mismatching ABI. */
3589 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
3593 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3594 But in the case of vector types, it is some vector mode.
3596 When we have only some of our vector isa extensions enabled, then there
3597 are some modes for which vector_mode_supported_p is false. For these
3598 modes, the generic vector support in gcc will choose some non-vector mode
3599 in order to implement the type. By computing the natural mode, we'll
3600 select the proper ABI location for the operand and not depend on whatever
3601 the middle-end decides to do with these vector types. */
3603 static enum machine_mode
3604 type_natural_mode (const_tree type)
3606 enum machine_mode mode = TYPE_MODE (type);
3608 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
3610 HOST_WIDE_INT size = int_size_in_bytes (type);
3611 if ((size == 8 || size == 16)
3612 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3613 && TYPE_VECTOR_SUBPARTS (type) > 1)
3615 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
3617 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
3618 mode = MIN_MODE_VECTOR_FLOAT;
3620 mode = MIN_MODE_VECTOR_INT;
3622 /* Get the mode which has this inner mode and number of units. */
3623 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
3624 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
3625 && GET_MODE_INNER (mode) == innermode)
3635 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3636 this may not agree with the mode that the type system has chosen for the
3637 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3638 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3641 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
3646 if (orig_mode != BLKmode)
3647 tmp = gen_rtx_REG (orig_mode, regno);
3650 tmp = gen_rtx_REG (mode, regno);
3651 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
3652 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
3658 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3659 of this code is to classify each 8bytes of incoming argument by the register
3660 class and assign registers accordingly. */
3662 /* Return the union class of CLASS1 and CLASS2.
3663 See the x86-64 PS ABI for details. */
3665 static enum x86_64_reg_class
3666 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
3668 /* Rule #1: If both classes are equal, this is the resulting class. */
3669 if (class1 == class2)
3672 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3674 if (class1 == X86_64_NO_CLASS)
3676 if (class2 == X86_64_NO_CLASS)
3679 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3680 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
3681 return X86_64_MEMORY_CLASS;
3683 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3684 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
3685 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
3686 return X86_64_INTEGERSI_CLASS;
3687 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
3688 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
3689 return X86_64_INTEGER_CLASS;
3691 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3693 if (class1 == X86_64_X87_CLASS
3694 || class1 == X86_64_X87UP_CLASS
3695 || class1 == X86_64_COMPLEX_X87_CLASS
3696 || class2 == X86_64_X87_CLASS
3697 || class2 == X86_64_X87UP_CLASS
3698 || class2 == X86_64_COMPLEX_X87_CLASS)
3699 return X86_64_MEMORY_CLASS;
3701 /* Rule #6: Otherwise class SSE is used. */
3702 return X86_64_SSE_CLASS;
3705 /* Classify the argument of type TYPE and mode MODE.
3706 CLASSES will be filled by the register class used to pass each word
3707 of the operand. The number of words is returned. In case the parameter
3708 should be passed in memory, 0 is returned. As a special case for zero
3709 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3711 BIT_OFFSET is used internally for handling records and specifies offset
3712 of the offset in bits modulo 256 to avoid overflow cases.
3714 See the x86-64 PS ABI for details.
3718 classify_argument (enum machine_mode mode, const_tree type,
3719 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
3721 HOST_WIDE_INT bytes =
3722 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3723 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3725 /* Variable sized entities are always passed/returned in memory. */
3729 if (mode != VOIDmode
3730 && targetm.calls.must_pass_in_stack (mode, type))
3733 if (type && AGGREGATE_TYPE_P (type))
3737 enum x86_64_reg_class subclasses[MAX_CLASSES];
3739 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3743 for (i = 0; i < words; i++)
3744 classes[i] = X86_64_NO_CLASS;
3746 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3747 signalize memory class, so handle it as special case. */
3750 classes[0] = X86_64_NO_CLASS;
3754 /* Classify each field of record and merge classes. */
3755 switch (TREE_CODE (type))
3758 /* And now merge the fields of structure. */
3759 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3761 if (TREE_CODE (field) == FIELD_DECL)
3765 if (TREE_TYPE (field) == error_mark_node)
3768 /* Bitfields are always classified as integer. Handle them
3769 early, since later code would consider them to be
3770 misaligned integers. */
3771 if (DECL_BIT_FIELD (field))
3773 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3774 i < ((int_bit_position (field) + (bit_offset % 64))
3775 + tree_low_cst (DECL_SIZE (field), 0)
3778 merge_classes (X86_64_INTEGER_CLASS,
3783 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3784 TREE_TYPE (field), subclasses,
3785 (int_bit_position (field)
3786 + bit_offset) % 256);
3789 for (i = 0; i < num; i++)
3792 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3794 merge_classes (subclasses[i], classes[i + pos]);
3802 /* Arrays are handled as small records. */
3805 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
3806 TREE_TYPE (type), subclasses, bit_offset);
3810 /* The partial classes are now full classes. */
3811 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
3812 subclasses[0] = X86_64_SSE_CLASS;
3813 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
3814 subclasses[0] = X86_64_INTEGER_CLASS;
3816 for (i = 0; i < words; i++)
3817 classes[i] = subclasses[i % num];
3822 case QUAL_UNION_TYPE:
3823 /* Unions are similar to RECORD_TYPE but offset is always 0.
3825 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3827 if (TREE_CODE (field) == FIELD_DECL)
3831 if (TREE_TYPE (field) == error_mark_node)
3834 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3835 TREE_TYPE (field), subclasses,
3839 for (i = 0; i < num; i++)
3840 classes[i] = merge_classes (subclasses[i], classes[i]);
3849 /* Final merger cleanup. */
3850 for (i = 0; i < words; i++)
3852 /* If one class is MEMORY, everything should be passed in
3854 if (classes[i] == X86_64_MEMORY_CLASS)
3857 /* The X86_64_SSEUP_CLASS should be always preceded by
3858 X86_64_SSE_CLASS. */
3859 if (classes[i] == X86_64_SSEUP_CLASS
3860 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
3861 classes[i] = X86_64_SSE_CLASS;
3863 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3864 if (classes[i] == X86_64_X87UP_CLASS
3865 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
3866 classes[i] = X86_64_SSE_CLASS;
3871 /* Compute alignment needed. We align all types to natural boundaries with
3872 exception of XFmode that is aligned to 64bits. */
3873 if (mode != VOIDmode && mode != BLKmode)
3875 int mode_alignment = GET_MODE_BITSIZE (mode);
3878 mode_alignment = 128;
3879 else if (mode == XCmode)
3880 mode_alignment = 256;
3881 if (COMPLEX_MODE_P (mode))
3882 mode_alignment /= 2;
3883 /* Misaligned fields are always returned in memory. */
3884 if (bit_offset % mode_alignment)
3888 /* for V1xx modes, just use the base mode */
3889 if (VECTOR_MODE_P (mode) && mode != V1DImode
3890 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
3891 mode = GET_MODE_INNER (mode);
3893 /* Classification of atomic types. */
3898 classes[0] = X86_64_SSE_CLASS;
3901 classes[0] = X86_64_SSE_CLASS;
3902 classes[1] = X86_64_SSEUP_CLASS;
3911 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3912 classes[0] = X86_64_INTEGERSI_CLASS;
3914 classes[0] = X86_64_INTEGER_CLASS;
3918 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
3923 if (!(bit_offset % 64))
3924 classes[0] = X86_64_SSESF_CLASS;
3926 classes[0] = X86_64_SSE_CLASS;
3929 classes[0] = X86_64_SSEDF_CLASS;
3932 classes[0] = X86_64_X87_CLASS;
3933 classes[1] = X86_64_X87UP_CLASS;
3936 classes[0] = X86_64_SSE_CLASS;
3937 classes[1] = X86_64_SSEUP_CLASS;
3940 classes[0] = X86_64_SSE_CLASS;
3943 classes[0] = X86_64_SSEDF_CLASS;
3944 classes[1] = X86_64_SSEDF_CLASS;
3947 classes[0] = X86_64_COMPLEX_X87_CLASS;
3950 /* This modes is larger than 16 bytes. */
3958 classes[0] = X86_64_SSE_CLASS;
3959 classes[1] = X86_64_SSEUP_CLASS;
3966 classes[0] = X86_64_SSE_CLASS;
3972 gcc_assert (VECTOR_MODE_P (mode));
3977 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
3979 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3980 classes[0] = X86_64_INTEGERSI_CLASS;
3982 classes[0] = X86_64_INTEGER_CLASS;
3983 classes[1] = X86_64_INTEGER_CLASS;
3984 return 1 + (bytes > 8);
3988 /* Examine the argument and return set number of register required in each
3989 class. Return 0 iff parameter should be passed in memory. */
3991 examine_argument (enum machine_mode mode, const_tree type, int in_return,
3992 int *int_nregs, int *sse_nregs)
3994 enum x86_64_reg_class regclass[MAX_CLASSES];
3995 int n = classify_argument (mode, type, regclass, 0);
4001 for (n--; n >= 0; n--)
4002 switch (regclass[n])
4004 case X86_64_INTEGER_CLASS:
4005 case X86_64_INTEGERSI_CLASS:
4008 case X86_64_SSE_CLASS:
4009 case X86_64_SSESF_CLASS:
4010 case X86_64_SSEDF_CLASS:
4013 case X86_64_NO_CLASS:
4014 case X86_64_SSEUP_CLASS:
4016 case X86_64_X87_CLASS:
4017 case X86_64_X87UP_CLASS:
4021 case X86_64_COMPLEX_X87_CLASS:
4022 return in_return ? 2 : 0;
4023 case X86_64_MEMORY_CLASS:
4029 /* Construct container for the argument used by GCC interface. See
4030 FUNCTION_ARG for the detailed description. */
4033 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
4034 const_tree type, int in_return, int nintregs, int nsseregs,
4035 const int *intreg, int sse_regno)
4037 /* The following variables hold the static issued_error state. */
4038 static bool issued_sse_arg_error;
4039 static bool issued_sse_ret_error;
4040 static bool issued_x87_ret_error;
4042 enum machine_mode tmpmode;
4044 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4045 enum x86_64_reg_class regclass[MAX_CLASSES];
4049 int needed_sseregs, needed_intregs;
4050 rtx exp[MAX_CLASSES];
4053 n = classify_argument (mode, type, regclass, 0);
4056 if (!examine_argument (mode, type, in_return, &needed_intregs,
4059 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
4062 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
4063 some less clueful developer tries to use floating-point anyway. */
4064 if (needed_sseregs && !TARGET_SSE)
4068 if (!issued_sse_ret_error)
4070 error ("SSE register return with SSE disabled");
4071 issued_sse_ret_error = true;
4074 else if (!issued_sse_arg_error)
4076 error ("SSE register argument with SSE disabled");
4077 issued_sse_arg_error = true;
4082 /* Likewise, error if the ABI requires us to return values in the
4083 x87 registers and the user specified -mno-80387. */
4084 if (!TARGET_80387 && in_return)
4085 for (i = 0; i < n; i++)
4086 if (regclass[i] == X86_64_X87_CLASS
4087 || regclass[i] == X86_64_X87UP_CLASS
4088 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
4090 if (!issued_x87_ret_error)
4092 error ("x87 register return with x87 disabled");
4093 issued_x87_ret_error = true;
4098 /* First construct simple cases. Avoid SCmode, since we want to use
4099 single register to pass this type. */
4100 if (n == 1 && mode != SCmode)
4101 switch (regclass[0])
4103 case X86_64_INTEGER_CLASS:
4104 case X86_64_INTEGERSI_CLASS:
4105 return gen_rtx_REG (mode, intreg[0]);
4106 case X86_64_SSE_CLASS:
4107 case X86_64_SSESF_CLASS:
4108 case X86_64_SSEDF_CLASS:
4109 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
4110 case X86_64_X87_CLASS:
4111 case X86_64_COMPLEX_X87_CLASS:
4112 return gen_rtx_REG (mode, FIRST_STACK_REG);
4113 case X86_64_NO_CLASS:
4114 /* Zero sized array, struct or class. */
4119 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
4120 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
4121 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
4124 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
4125 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
4126 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
4127 && regclass[1] == X86_64_INTEGER_CLASS
4128 && (mode == CDImode || mode == TImode || mode == TFmode)
4129 && intreg[0] + 1 == intreg[1])
4130 return gen_rtx_REG (mode, intreg[0]);
4132 /* Otherwise figure out the entries of the PARALLEL. */
4133 for (i = 0; i < n; i++)
4135 switch (regclass[i])
4137 case X86_64_NO_CLASS:
4139 case X86_64_INTEGER_CLASS:
4140 case X86_64_INTEGERSI_CLASS:
4141 /* Merge TImodes on aligned occasions here too. */
4142 if (i * 8 + 8 > bytes)
4143 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
4144 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
4148 /* We've requested 24 bytes we don't have mode for. Use DImode. */
4149 if (tmpmode == BLKmode)
4151 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4152 gen_rtx_REG (tmpmode, *intreg),
4156 case X86_64_SSESF_CLASS:
4157 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4158 gen_rtx_REG (SFmode,
4159 SSE_REGNO (sse_regno)),
4163 case X86_64_SSEDF_CLASS:
4164 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4165 gen_rtx_REG (DFmode,
4166 SSE_REGNO (sse_regno)),
4170 case X86_64_SSE_CLASS:
4171 if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
4175 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
4176 gen_rtx_REG (tmpmode,
4177 SSE_REGNO (sse_regno)),
4179 if (tmpmode == TImode)
4188 /* Empty aligned struct, union or class. */
4192 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
4193 for (i = 0; i < nexps; i++)
4194 XVECEXP (ret, 0, i) = exp [i];
4198 /* Update the data in CUM to advance over an argument of mode MODE
4199 and data type TYPE. (TYPE is null for libcalls where that information
4200 may not be available.) */
4203 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4204 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4220 cum->words += words;
4221 cum->nregs -= words;
4222 cum->regno += words;
4224 if (cum->nregs <= 0)
4232 if (cum->float_in_sse < 2)
4235 if (cum->float_in_sse < 1)
4246 if (!type || !AGGREGATE_TYPE_P (type))
4248 cum->sse_words += words;
4249 cum->sse_nregs -= 1;
4250 cum->sse_regno += 1;
4251 if (cum->sse_nregs <= 0)
4264 if (!type || !AGGREGATE_TYPE_P (type))
4266 cum->mmx_words += words;
4267 cum->mmx_nregs -= 1;
4268 cum->mmx_regno += 1;
4269 if (cum->mmx_nregs <= 0)
4280 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4281 tree type, HOST_WIDE_INT words)
4283 int int_nregs, sse_nregs;
4285 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
4286 cum->words += words;
4287 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
4289 cum->nregs -= int_nregs;
4290 cum->sse_nregs -= sse_nregs;
4291 cum->regno += int_nregs;
4292 cum->sse_regno += sse_nregs;
4295 cum->words += words;
4299 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
4300 HOST_WIDE_INT words)
4302 /* Otherwise, this should be passed indirect. */
4303 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
4305 cum->words += words;
4314 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4315 tree type, int named ATTRIBUTE_UNUSED)
4317 HOST_WIDE_INT bytes, words;
4319 if (mode == BLKmode)
4320 bytes = int_size_in_bytes (type);
4322 bytes = GET_MODE_SIZE (mode);
4323 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4326 mode = type_natural_mode (type);
4328 if (TARGET_64BIT_MS_ABI)
4329 function_arg_advance_ms_64 (cum, bytes, words);
4330 else if (TARGET_64BIT)
4331 function_arg_advance_64 (cum, mode, type, words);
4333 function_arg_advance_32 (cum, mode, type, bytes, words);
4336 /* Define where to put the arguments to a function.
4337 Value is zero to push the argument on the stack,
4338 or a hard register in which to store the argument.
4340 MODE is the argument's machine mode.
4341 TYPE is the data type of the argument (as a tree).
4342 This is null for libcalls where that information may
4344 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4345 the preceding args and about the function being called.
4346 NAMED is nonzero if this argument is a named parameter
4347 (otherwise it is an extra parameter matching an ellipsis). */
4350 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4351 enum machine_mode orig_mode, tree type,
4352 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
4354 static bool warnedsse, warnedmmx;
4356 /* Avoid the AL settings for the Unix64 ABI. */
4357 if (mode == VOIDmode)
4373 if (words <= cum->nregs)
4375 int regno = cum->regno;
4377 /* Fastcall allocates the first two DWORD (SImode) or
4378 smaller arguments to ECX and EDX if it isn't an
4384 || (type && AGGREGATE_TYPE_P (type)))
4387 /* ECX not EAX is the first allocated register. */
4388 if (regno == AX_REG)
4391 return gen_rtx_REG (mode, regno);
4396 if (cum->float_in_sse < 2)
4399 if (cum->float_in_sse < 1)
4409 if (!type || !AGGREGATE_TYPE_P (type))
4411 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
4414 warning (0, "SSE vector argument without SSE enabled "
4418 return gen_reg_or_parallel (mode, orig_mode,
4419 cum->sse_regno + FIRST_SSE_REG);
4428 if (!type || !AGGREGATE_TYPE_P (type))
4430 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
4433 warning (0, "MMX vector argument without MMX enabled "
4437 return gen_reg_or_parallel (mode, orig_mode,
4438 cum->mmx_regno + FIRST_MMX_REG);
4447 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4448 enum machine_mode orig_mode, tree type)
4450 /* Handle a hidden AL argument containing number of registers
4451 for varargs x86-64 functions. */
4452 if (mode == VOIDmode)
4453 return GEN_INT (cum->maybe_vaarg
4454 ? (cum->sse_nregs < 0
4459 return construct_container (mode, orig_mode, type, 0, cum->nregs,
4461 &x86_64_int_parameter_registers [cum->regno],
4466 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4467 enum machine_mode orig_mode, int named,
4468 HOST_WIDE_INT bytes)
4472 /* Avoid the AL settings for the Unix64 ABI. */
4473 if (mode == VOIDmode)
4476 /* If we've run out of registers, it goes on the stack. */
4477 if (cum->nregs == 0)
4480 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
4482 /* Only floating point modes are passed in anything but integer regs. */
4483 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
4486 regno = cum->regno + FIRST_SSE_REG;
4491 /* Unnamed floating parameters are passed in both the
4492 SSE and integer registers. */
4493 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
4494 t2 = gen_rtx_REG (mode, regno);
4495 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
4496 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
4497 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
4500 /* Handle aggregated types passed in register. */
4501 if (orig_mode == BLKmode)
4503 if (bytes > 0 && bytes <= 8)
4504 mode = (bytes > 4 ? DImode : SImode);
4505 if (mode == BLKmode)
4509 return gen_reg_or_parallel (mode, orig_mode, regno);
4513 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
4514 tree type, int named)
4516 enum machine_mode mode = omode;
4517 HOST_WIDE_INT bytes, words;
4519 if (mode == BLKmode)
4520 bytes = int_size_in_bytes (type);
4522 bytes = GET_MODE_SIZE (mode);
4523 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4525 /* To simplify the code below, represent vector types with a vector mode
4526 even if MMX/SSE are not active. */
4527 if (type && TREE_CODE (type) == VECTOR_TYPE)
4528 mode = type_natural_mode (type);
4530 if (TARGET_64BIT_MS_ABI)
4531 return function_arg_ms_64 (cum, mode, omode, named, bytes);
4532 else if (TARGET_64BIT)
4533 return function_arg_64 (cum, mode, omode, type);
4535 return function_arg_32 (cum, mode, omode, type, bytes, words);
4538 /* A C expression that indicates when an argument must be passed by
4539 reference. If nonzero for an argument, a copy of that argument is
4540 made in memory and a pointer to the argument is passed instead of
4541 the argument itself. The pointer is passed in whatever way is
4542 appropriate for passing a pointer to that type. */
4545 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4546 enum machine_mode mode ATTRIBUTE_UNUSED,
4547 const_tree type, bool named ATTRIBUTE_UNUSED)
4549 /* See Windows x64 Software Convention. */
4550 if (TARGET_64BIT_MS_ABI)
4552 int msize = (int) GET_MODE_SIZE (mode);
4555 /* Arrays are passed by reference. */
4556 if (TREE_CODE (type) == ARRAY_TYPE)
4559 if (AGGREGATE_TYPE_P (type))
4561 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
4562 are passed by reference. */
4563 msize = int_size_in_bytes (type);
4567 /* __m128 is passed by reference. */
4569 case 1: case 2: case 4: case 8:
4575 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
4581 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4582 ABI. Only called if TARGET_SSE. */
4584 contains_128bit_aligned_vector_p (tree type)
4586 enum machine_mode mode = TYPE_MODE (type);
4587 if (SSE_REG_MODE_P (mode)
4588 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
4590 if (TYPE_ALIGN (type) < 128)
4593 if (AGGREGATE_TYPE_P (type))
4595 /* Walk the aggregates recursively. */
4596 switch (TREE_CODE (type))
4600 case QUAL_UNION_TYPE:
4604 /* Walk all the structure fields. */
4605 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4607 if (TREE_CODE (field) == FIELD_DECL
4608 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
4615 /* Just for use if some languages passes arrays by value. */
4616 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
4627 /* Gives the alignment boundary, in bits, of an argument with the
4628 specified mode and type. */
4631 ix86_function_arg_boundary (enum machine_mode mode, tree type)
4635 align = TYPE_ALIGN (type);
4637 align = GET_MODE_ALIGNMENT (mode);
4638 if (align < PARM_BOUNDARY)
4639 align = PARM_BOUNDARY;
4640 /* Decimal floating point is aligned to its natural boundary. */
4641 if (!TARGET_64BIT && !VALID_DFP_MODE_P (mode))
4643 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4644 make an exception for SSE modes since these require 128bit
4647 The handling here differs from field_alignment. ICC aligns MMX
4648 arguments to 4 byte boundaries, while structure fields are aligned
4649 to 8 byte boundaries. */
4651 align = PARM_BOUNDARY;
4654 if (!SSE_REG_MODE_P (mode))
4655 align = PARM_BOUNDARY;
4659 if (!contains_128bit_aligned_vector_p (type))
4660 align = PARM_BOUNDARY;
4663 if (align > BIGGEST_ALIGNMENT)
4664 align = BIGGEST_ALIGNMENT;
4668 /* Return true if N is a possible register number of function value. */
4671 ix86_function_value_regno_p (int regno)
4678 case FIRST_FLOAT_REG:
4679 if (TARGET_64BIT_MS_ABI)
4681 return TARGET_FLOAT_RETURNS_IN_80387;
4687 if (TARGET_MACHO || TARGET_64BIT)
4695 /* Define how to find the value returned by a function.
4696 VALTYPE is the data type of the value (as a tree).
4697 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4698 otherwise, FUNC is 0. */
4701 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
4702 const_tree fntype, const_tree fn)
4706 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4707 we normally prevent this case when mmx is not available. However
4708 some ABIs may require the result to be returned like DImode. */
4709 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4710 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
4712 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4713 we prevent this case when sse is not available. However some ABIs
4714 may require the result to be returned like integer TImode. */
4715 else if (mode == TImode
4716 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4717 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
4719 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
4720 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
4721 regno = FIRST_FLOAT_REG;
4723 /* Most things go in %eax. */
4726 /* Override FP return register with %xmm0 for local functions when
4727 SSE math is enabled or for functions with sseregparm attribute. */
4728 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
4730 int sse_level = ix86_function_sseregparm (fntype, fn, false);
4731 if ((sse_level >= 1 && mode == SFmode)
4732 || (sse_level == 2 && mode == DFmode))
4733 regno = FIRST_SSE_REG;
4736 return gen_rtx_REG (orig_mode, regno);
4740 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
4745 /* Handle libcalls, which don't provide a type node. */
4746 if (valtype == NULL)
4758 return gen_rtx_REG (mode, FIRST_SSE_REG);
4761 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
4765 return gen_rtx_REG (mode, AX_REG);
4769 ret = construct_container (mode, orig_mode, valtype, 1,
4770 REGPARM_MAX, SSE_REGPARM_MAX,
4771 x86_64_int_return_registers, 0);
4773 /* For zero sized structures, construct_container returns NULL, but we
4774 need to keep rest of compiler happy by returning meaningful value. */
4776 ret = gen_rtx_REG (orig_mode, AX_REG);
4782 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
4784 unsigned int regno = AX_REG;
4788 switch (GET_MODE_SIZE (mode))
4791 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
4792 && !COMPLEX_MODE_P (mode))
4793 regno = FIRST_SSE_REG;
4797 if (mode == SFmode || mode == DFmode)
4798 regno = FIRST_SSE_REG;
4804 return gen_rtx_REG (orig_mode, regno);
4808 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
4809 enum machine_mode orig_mode, enum machine_mode mode)
4811 const_tree fn, fntype;
4814 if (fntype_or_decl && DECL_P (fntype_or_decl))
4815 fn = fntype_or_decl;
4816 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
4818 if (TARGET_64BIT_MS_ABI)
4819 return function_value_ms_64 (orig_mode, mode);
4820 else if (TARGET_64BIT)
4821 return function_value_64 (orig_mode, mode, valtype);
4823 return function_value_32 (orig_mode, mode, fntype, fn);
4827 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
4828 bool outgoing ATTRIBUTE_UNUSED)
4830 enum machine_mode mode, orig_mode;
4832 orig_mode = TYPE_MODE (valtype);
4833 mode = type_natural_mode (valtype);
4834 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
4838 ix86_libcall_value (enum machine_mode mode)
4840 return ix86_function_value_1 (NULL, NULL, mode, mode);
4843 /* Return true iff type is returned in memory. */
4846 return_in_memory_32 (const_tree type, enum machine_mode mode)
4850 if (mode == BLKmode)
4853 size = int_size_in_bytes (type);
4855 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
4858 if (VECTOR_MODE_P (mode) || mode == TImode)
4860 /* User-created vectors small enough to fit in EAX. */
4864 /* MMX/3dNow values are returned in MM0,
4865 except when it doesn't exits. */
4867 return (TARGET_MMX ? 0 : 1);
4869 /* SSE values are returned in XMM0, except when it doesn't exist. */
4871 return (TARGET_SSE ? 0 : 1);
4886 return_in_memory_64 (const_tree type, enum machine_mode mode)
4888 int needed_intregs, needed_sseregs;
4889 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
4893 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
4895 HOST_WIDE_INT size = int_size_in_bytes (type);
4897 /* __m128 is returned in xmm0. */
4898 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
4899 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
4902 /* Otherwise, the size must be exactly in [1248]. */
4903 return (size != 1 && size != 2 && size != 4 && size != 8);
4907 ix86_return_in_memory (const_tree type)
4909 const enum machine_mode mode = type_natural_mode (type);
4911 if (TARGET_64BIT_MS_ABI)
4912 return return_in_memory_ms_64 (type, mode);
4913 else if (TARGET_64BIT)
4914 return return_in_memory_64 (type, mode);
4916 return return_in_memory_32 (type, mode);
4919 /* Return false iff TYPE is returned in memory. This version is used
4920 on Solaris 10. It is similar to the generic ix86_return_in_memory,
4921 but differs notably in that when MMX is available, 8-byte vectors
4922 are returned in memory, rather than in MMX registers. */
4925 ix86_sol10_return_in_memory (const_tree type)
4928 enum machine_mode mode = type_natural_mode (type);
4931 return return_in_memory_64 (type, mode);
4933 if (mode == BLKmode)
4936 size = int_size_in_bytes (type);
4938 if (VECTOR_MODE_P (mode))
4940 /* Return in memory only if MMX registers *are* available. This
4941 seems backwards, but it is consistent with the existing
4948 else if (mode == TImode)
4950 else if (mode == XFmode)
4956 /* When returning SSE vector types, we have a choice of either
4957 (1) being abi incompatible with a -march switch, or
4958 (2) generating an error.
4959 Given no good solution, I think the safest thing is one warning.
4960 The user won't be able to use -Werror, but....
4962 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
4963 called in response to actually generating a caller or callee that
4964 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
4965 via aggregate_value_p for general type probing from tree-ssa. */
4968 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
4970 static bool warnedsse, warnedmmx;
4972 if (!TARGET_64BIT && type)
4974 /* Look at the return type of the function, not the function type. */
4975 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
4977 if (!TARGET_SSE && !warnedsse)
4980 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4983 warning (0, "SSE vector return without SSE enabled "
4988 if (!TARGET_MMX && !warnedmmx)
4990 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4993 warning (0, "MMX vector return without MMX enabled "
5003 /* Create the va_list data type. */
5006 ix86_build_builtin_va_list (void)
5008 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
5010 /* For i386 we use plain pointer to argument area. */
5011 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5012 return build_pointer_type (char_type_node);
5014 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5015 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5017 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
5018 unsigned_type_node);
5019 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
5020 unsigned_type_node);
5021 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5023 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5026 va_list_gpr_counter_field = f_gpr;
5027 va_list_fpr_counter_field = f_fpr;
5029 DECL_FIELD_CONTEXT (f_gpr) = record;
5030 DECL_FIELD_CONTEXT (f_fpr) = record;
5031 DECL_FIELD_CONTEXT (f_ovf) = record;
5032 DECL_FIELD_CONTEXT (f_sav) = record;
5034 TREE_CHAIN (record) = type_decl;
5035 TYPE_NAME (record) = type_decl;
5036 TYPE_FIELDS (record) = f_gpr;
5037 TREE_CHAIN (f_gpr) = f_fpr;
5038 TREE_CHAIN (f_fpr) = f_ovf;
5039 TREE_CHAIN (f_ovf) = f_sav;
5041 layout_type (record);
5043 /* The correct type is an array type of one element. */
5044 return build_array_type (record, build_index_type (size_zero_node));
5047 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
5050 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
5060 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
5063 /* Indicate to allocate space on the stack for varargs save area. */
5064 ix86_save_varrargs_registers = 1;
5065 /* We need 16-byte stack alignment to save SSE registers. If user
5066 asked for lower preferred_stack_boundary, lets just hope that he knows
5067 what he is doing and won't varargs SSE values.
5069 We also may end up assuming that only 64bit values are stored in SSE
5070 register let some floating point program work. */
5071 if (ix86_preferred_stack_boundary >= BIGGEST_ALIGNMENT)
5072 crtl->stack_alignment_needed = BIGGEST_ALIGNMENT;
5074 save_area = frame_pointer_rtx;
5075 set = get_varargs_alias_set ();
5077 for (i = cum->regno;
5079 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
5082 mem = gen_rtx_MEM (Pmode,
5083 plus_constant (save_area, i * UNITS_PER_WORD));
5084 MEM_NOTRAP_P (mem) = 1;
5085 set_mem_alias_set (mem, set);
5086 emit_move_insn (mem, gen_rtx_REG (Pmode,
5087 x86_64_int_parameter_registers[i]));
5090 if (cum->sse_nregs && cfun->va_list_fpr_size)
5092 /* Now emit code to save SSE registers. The AX parameter contains number
5093 of SSE parameter registers used to call this function. We use
5094 sse_prologue_save insn template that produces computed jump across
5095 SSE saves. We need some preparation work to get this working. */
5097 label = gen_label_rtx ();
5098 label_ref = gen_rtx_LABEL_REF (Pmode, label);
5100 /* Compute address to jump to :
5101 label - 5*eax + nnamed_sse_arguments*5 */
5102 tmp_reg = gen_reg_rtx (Pmode);
5103 nsse_reg = gen_reg_rtx (Pmode);
5104 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
5105 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5106 gen_rtx_MULT (Pmode, nsse_reg,
5111 gen_rtx_CONST (DImode,
5112 gen_rtx_PLUS (DImode,
5114 GEN_INT (cum->sse_regno * 4))));
5116 emit_move_insn (nsse_reg, label_ref);
5117 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
5119 /* Compute address of memory block we save into. We always use pointer
5120 pointing 127 bytes after first byte to store - this is needed to keep
5121 instruction size limited by 4 bytes. */
5122 tmp_reg = gen_reg_rtx (Pmode);
5123 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
5124 plus_constant (save_area,
5125 8 * REGPARM_MAX + 127)));
5126 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
5127 MEM_NOTRAP_P (mem) = 1;
5128 set_mem_alias_set (mem, set);
5129 set_mem_align (mem, BITS_PER_WORD);
5131 /* And finally do the dirty job! */
5132 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
5133 GEN_INT (cum->sse_regno), label));
5138 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
5140 alias_set_type set = get_varargs_alias_set ();
5143 for (i = cum->regno; i < REGPARM_MAX; i++)
5147 mem = gen_rtx_MEM (Pmode,
5148 plus_constant (virtual_incoming_args_rtx,
5149 i * UNITS_PER_WORD));
5150 MEM_NOTRAP_P (mem) = 1;
5151 set_mem_alias_set (mem, set);
5153 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
5154 emit_move_insn (mem, reg);
5159 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5160 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5163 CUMULATIVE_ARGS next_cum;
5166 /* This argument doesn't appear to be used anymore. Which is good,
5167 because the old code here didn't suppress rtl generation. */
5168 gcc_assert (!no_rtl);
5173 fntype = TREE_TYPE (current_function_decl);
5175 /* For varargs, we do not want to skip the dummy va_dcl argument.
5176 For stdargs, we do want to skip the last named argument. */
5178 if (stdarg_p (fntype))
5179 function_arg_advance (&next_cum, mode, type, 1);
5181 if (TARGET_64BIT_MS_ABI)
5182 setup_incoming_varargs_ms_64 (&next_cum);
5184 setup_incoming_varargs_64 (&next_cum);
5187 /* Implement va_start. */
5190 ix86_va_start (tree valist, rtx nextarg)
5192 HOST_WIDE_INT words, n_gpr, n_fpr;
5193 tree f_gpr, f_fpr, f_ovf, f_sav;
5194 tree gpr, fpr, ovf, sav, t;
5197 /* Only 64bit target needs something special. */
5198 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5200 std_expand_builtin_va_start (valist, nextarg);
5204 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5205 f_fpr = TREE_CHAIN (f_gpr);
5206 f_ovf = TREE_CHAIN (f_fpr);
5207 f_sav = TREE_CHAIN (f_ovf);
5209 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
5210 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5211 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5212 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5213 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5215 /* Count number of gp and fp argument registers used. */
5216 words = crtl->args.info.words;
5217 n_gpr = crtl->args.info.regno;
5218 n_fpr = crtl->args.info.sse_regno;
5220 if (cfun->va_list_gpr_size)
5222 type = TREE_TYPE (gpr);
5223 t = build2 (GIMPLE_MODIFY_STMT, type, gpr,
5224 build_int_cst (type, n_gpr * 8));
5225 TREE_SIDE_EFFECTS (t) = 1;
5226 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5229 if (cfun->va_list_fpr_size)
5231 type = TREE_TYPE (fpr);
5232 t = build2 (GIMPLE_MODIFY_STMT, type, fpr,
5233 build_int_cst (type, n_fpr * 16 + 8*REGPARM_MAX));
5234 TREE_SIDE_EFFECTS (t) = 1;
5235 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5238 /* Find the overflow area. */
5239 type = TREE_TYPE (ovf);
5240 t = make_tree (type, virtual_incoming_args_rtx);
5242 t = build2 (POINTER_PLUS_EXPR, type, t,
5243 size_int (words * UNITS_PER_WORD));
5244 t = build2 (GIMPLE_MODIFY_STMT, type, ovf, t);
5245 TREE_SIDE_EFFECTS (t) = 1;
5246 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5248 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
5250 /* Find the register save area.
5251 Prologue of the function save it right above stack frame. */
5252 type = TREE_TYPE (sav);
5253 t = make_tree (type, frame_pointer_rtx);
5254 t = build2 (GIMPLE_MODIFY_STMT, type, sav, t);
5255 TREE_SIDE_EFFECTS (t) = 1;
5256 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5260 /* Implement va_arg. */
5263 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5265 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
5266 tree f_gpr, f_fpr, f_ovf, f_sav;
5267 tree gpr, fpr, ovf, sav, t;
5269 tree lab_false, lab_over = NULL_TREE;
5274 enum machine_mode nat_mode;
5276 /* Only 64bit target needs something special. */
5277 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
5278 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5280 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5281 f_fpr = TREE_CHAIN (f_gpr);
5282 f_ovf = TREE_CHAIN (f_fpr);
5283 f_sav = TREE_CHAIN (f_ovf);
5285 valist = build_va_arg_indirect_ref (valist);
5286 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5287 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5288 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5289 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5291 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5293 type = build_pointer_type (type);
5294 size = int_size_in_bytes (type);
5295 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5297 nat_mode = type_natural_mode (type);
5298 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
5299 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
5301 /* Pull the value out of the saved registers. */
5303 addr = create_tmp_var (ptr_type_node, "addr");
5304 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5308 int needed_intregs, needed_sseregs;
5310 tree int_addr, sse_addr;
5312 lab_false = create_artificial_label ();
5313 lab_over = create_artificial_label ();
5315 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
5317 need_temp = (!REG_P (container)
5318 && ((needed_intregs && TYPE_ALIGN (type) > 64)
5319 || TYPE_ALIGN (type) > 128));
5321 /* In case we are passing structure, verify that it is consecutive block
5322 on the register save area. If not we need to do moves. */
5323 if (!need_temp && !REG_P (container))
5325 /* Verify that all registers are strictly consecutive */
5326 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
5330 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5332 rtx slot = XVECEXP (container, 0, i);
5333 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
5334 || INTVAL (XEXP (slot, 1)) != i * 16)
5342 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
5344 rtx slot = XVECEXP (container, 0, i);
5345 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
5346 || INTVAL (XEXP (slot, 1)) != i * 8)
5358 int_addr = create_tmp_var (ptr_type_node, "int_addr");
5359 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
5360 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
5361 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
5364 /* First ensure that we fit completely in registers. */
5367 t = build_int_cst (TREE_TYPE (gpr),
5368 (REGPARM_MAX - needed_intregs + 1) * 8);
5369 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
5370 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5371 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5372 gimplify_and_add (t, pre_p);
5376 t = build_int_cst (TREE_TYPE (fpr),
5377 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
5379 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
5380 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
5381 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
5382 gimplify_and_add (t, pre_p);
5385 /* Compute index to start of area used for integer regs. */
5388 /* int_addr = gpr + sav; */
5389 t = fold_convert (sizetype, gpr);
5390 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5391 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, int_addr, t);
5392 gimplify_and_add (t, pre_p);
5396 /* sse_addr = fpr + sav; */
5397 t = fold_convert (sizetype, fpr);
5398 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
5399 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, sse_addr, t);
5400 gimplify_and_add (t, pre_p);
5405 tree temp = create_tmp_var (type, "va_arg_tmp");
5408 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
5409 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5410 gimplify_and_add (t, pre_p);
5412 for (i = 0; i < XVECLEN (container, 0); i++)
5414 rtx slot = XVECEXP (container, 0, i);
5415 rtx reg = XEXP (slot, 0);
5416 enum machine_mode mode = GET_MODE (reg);
5417 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
5418 tree addr_type = build_pointer_type (piece_type);
5421 tree dest_addr, dest;
5423 if (SSE_REGNO_P (REGNO (reg)))
5425 src_addr = sse_addr;
5426 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
5430 src_addr = int_addr;
5431 src_offset = REGNO (reg) * 8;
5433 src_addr = fold_convert (addr_type, src_addr);
5434 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
5435 size_int (src_offset));
5436 src = build_va_arg_indirect_ref (src_addr);
5438 dest_addr = fold_convert (addr_type, addr);
5439 dest_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, dest_addr,
5440 size_int (INTVAL (XEXP (slot, 1))));
5441 dest = build_va_arg_indirect_ref (dest_addr);
5443 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, dest, src);
5444 gimplify_and_add (t, pre_p);
5450 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
5451 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
5452 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr, t);
5453 gimplify_and_add (t, pre_p);
5457 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
5458 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
5459 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr, t);
5460 gimplify_and_add (t, pre_p);
5463 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5464 gimplify_and_add (t, pre_p);
5466 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5467 append_to_statement_list (t, pre_p);
5470 /* ... otherwise out of the overflow area. */
5472 /* Care for on-stack alignment if needed. */
5473 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
5474 || integer_zerop (TYPE_SIZE (type)))
5478 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
5479 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
5480 size_int (align - 1));
5481 t = fold_convert (sizetype, t);
5482 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5484 t = fold_convert (TREE_TYPE (ovf), t);
5486 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5488 t2 = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
5489 gimplify_and_add (t2, pre_p);
5491 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
5492 size_int (rsize * UNITS_PER_WORD));
5493 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
5494 gimplify_and_add (t, pre_p);
5498 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5499 append_to_statement_list (t, pre_p);
5502 ptrtype = build_pointer_type (type);
5503 addr = fold_convert (ptrtype, addr);
5506 addr = build_va_arg_indirect_ref (addr);
5507 return build_va_arg_indirect_ref (addr);
5510 /* Return nonzero if OPNUM's MEM should be matched
5511 in movabs* patterns. */
5514 ix86_check_movabs (rtx insn, int opnum)
5518 set = PATTERN (insn);
5519 if (GET_CODE (set) == PARALLEL)
5520 set = XVECEXP (set, 0, 0);
5521 gcc_assert (GET_CODE (set) == SET);
5522 mem = XEXP (set, opnum);
5523 while (GET_CODE (mem) == SUBREG)
5524 mem = SUBREG_REG (mem);
5525 gcc_assert (MEM_P (mem));
5526 return (volatile_ok || !MEM_VOLATILE_P (mem));
5529 /* Initialize the table of extra 80387 mathematical constants. */
5532 init_ext_80387_constants (void)
5534 static const char * cst[5] =
5536 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
5537 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
5538 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
5539 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
5540 "3.1415926535897932385128089594061862044", /* 4: fldpi */
5544 for (i = 0; i < 5; i++)
5546 real_from_string (&ext_80387_constants_table[i], cst[i]);
5547 /* Ensure each constant is rounded to XFmode precision. */
5548 real_convert (&ext_80387_constants_table[i],
5549 XFmode, &ext_80387_constants_table[i]);
5552 ext_80387_constants_init = 1;
5555 /* Return true if the constant is something that can be loaded with
5556 a special instruction. */
5559 standard_80387_constant_p (rtx x)
5561 enum machine_mode mode = GET_MODE (x);
5565 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
5568 if (x == CONST0_RTX (mode))
5570 if (x == CONST1_RTX (mode))
5573 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5575 /* For XFmode constants, try to find a special 80387 instruction when
5576 optimizing for size or on those CPUs that benefit from them. */
5578 && (optimize_size || TARGET_EXT_80387_CONSTANTS))
5582 if (! ext_80387_constants_init)
5583 init_ext_80387_constants ();
5585 for (i = 0; i < 5; i++)
5586 if (real_identical (&r, &ext_80387_constants_table[i]))
5590 /* Load of the constant -0.0 or -1.0 will be split as
5591 fldz;fchs or fld1;fchs sequence. */
5592 if (real_isnegzero (&r))
5594 if (real_identical (&r, &dconstm1))
5600 /* Return the opcode of the special instruction to be used to load
5604 standard_80387_constant_opcode (rtx x)
5606 switch (standard_80387_constant_p (x))
5630 /* Return the CONST_DOUBLE representing the 80387 constant that is
5631 loaded by the specified special instruction. The argument IDX
5632 matches the return value from standard_80387_constant_p. */
5635 standard_80387_constant_rtx (int idx)
5639 if (! ext_80387_constants_init)
5640 init_ext_80387_constants ();
5656 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
5660 /* Return 1 if mode is a valid mode for sse. */
5662 standard_sse_mode_p (enum machine_mode mode)
5679 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
5682 standard_sse_constant_p (rtx x)
5684 enum machine_mode mode = GET_MODE (x);
5686 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
5688 if (vector_all_ones_operand (x, mode)
5689 && standard_sse_mode_p (mode))
5690 return TARGET_SSE2 ? 2 : -1;
5695 /* Return the opcode of the special instruction to be used to load
5699 standard_sse_constant_opcode (rtx insn, rtx x)
5701 switch (standard_sse_constant_p (x))
5704 if (get_attr_mode (insn) == MODE_V4SF)
5705 return "xorps\t%0, %0";
5706 else if (get_attr_mode (insn) == MODE_V2DF)
5707 return "xorpd\t%0, %0";
5709 return "pxor\t%0, %0";
5711 return "pcmpeqd\t%0, %0";
5716 /* Returns 1 if OP contains a symbol reference */
5719 symbolic_reference_mentioned_p (rtx op)
5724 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
5727 fmt = GET_RTX_FORMAT (GET_CODE (op));
5728 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
5734 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
5735 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
5739 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
5746 /* Return 1 if it is appropriate to emit `ret' instructions in the
5747 body of a function. Do this only if the epilogue is simple, needing a
5748 couple of insns. Prior to reloading, we can't tell how many registers
5749 must be saved, so return 0 then. Return 0 if there is no frame
5750 marker to de-allocate. */
5753 ix86_can_use_return_insn_p (void)
5755 struct ix86_frame frame;
5757 if (! reload_completed || frame_pointer_needed)
5760 /* Don't allow more than 32 pop, since that's all we can do
5761 with one instruction. */
5762 if (crtl->args.pops_args
5763 && crtl->args.size >= 32768)
5766 ix86_compute_frame_layout (&frame);
5767 return frame.to_allocate == 0 && frame.nregs == 0;
5770 /* Value should be nonzero if functions must have frame pointers.
5771 Zero means the frame pointer need not be set up (and parms may
5772 be accessed via the stack pointer) in functions that seem suitable. */
5775 ix86_frame_pointer_required (void)
5777 /* If we accessed previous frames, then the generated code expects
5778 to be able to access the saved ebp value in our frame. */
5779 if (cfun->machine->accesses_prev_frame)
5782 /* Several x86 os'es need a frame pointer for other reasons,
5783 usually pertaining to setjmp. */
5784 if (SUBTARGET_FRAME_POINTER_REQUIRED)
5787 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5788 the frame pointer by default. Turn it back on now if we've not
5789 got a leaf function. */
5790 if (TARGET_OMIT_LEAF_FRAME_POINTER
5791 && (!current_function_is_leaf
5792 || ix86_current_function_calls_tls_descriptor))
5801 /* Record that the current function accesses previous call frames. */
5804 ix86_setup_frame_addresses (void)
5806 cfun->machine->accesses_prev_frame = 1;
5809 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5810 # define USE_HIDDEN_LINKONCE 1
5812 # define USE_HIDDEN_LINKONCE 0
5815 static int pic_labels_used;
5817 /* Fills in the label name that should be used for a pc thunk for
5818 the given register. */
5821 get_pc_thunk_name (char name[32], unsigned int regno)
5823 gcc_assert (!TARGET_64BIT);
5825 if (USE_HIDDEN_LINKONCE)
5826 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
5828 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
5832 /* This function generates code for -fpic that loads %ebx with
5833 the return address of the caller and then returns. */
5836 ix86_file_end (void)
5841 for (regno = 0; regno < 8; ++regno)
5845 if (! ((pic_labels_used >> regno) & 1))
5848 get_pc_thunk_name (name, regno);
5853 switch_to_section (darwin_sections[text_coal_section]);
5854 fputs ("\t.weak_definition\t", asm_out_file);
5855 assemble_name (asm_out_file, name);
5856 fputs ("\n\t.private_extern\t", asm_out_file);
5857 assemble_name (asm_out_file, name);
5858 fputs ("\n", asm_out_file);
5859 ASM_OUTPUT_LABEL (asm_out_file, name);
5863 if (USE_HIDDEN_LINKONCE)
5867 decl = build_decl (FUNCTION_DECL, get_identifier (name),
5869 TREE_PUBLIC (decl) = 1;
5870 TREE_STATIC (decl) = 1;
5871 DECL_ONE_ONLY (decl) = 1;
5873 (*targetm.asm_out.unique_section) (decl, 0);
5874 switch_to_section (get_named_section (decl, NULL, 0));
5876 (*targetm.asm_out.globalize_label) (asm_out_file, name);
5877 fputs ("\t.hidden\t", asm_out_file);
5878 assemble_name (asm_out_file, name);
5879 fputc ('\n', asm_out_file);
5880 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
5884 switch_to_section (text_section);
5885 ASM_OUTPUT_LABEL (asm_out_file, name);
5887 if (TARGET_64BIT_MS_ABI)
5889 xops[0] = gen_rtx_REG (Pmode, regno);
5890 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
5891 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
5892 output_asm_insn ("ret", xops);
5896 xops[0] = gen_rtx_REG (SImode, regno);
5897 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
5898 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
5899 output_asm_insn ("ret", xops);
5903 if (NEED_INDICATE_EXEC_STACK)
5904 file_end_indicate_exec_stack ();
5907 /* Emit code for the SET_GOT patterns. */
5910 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
5916 if (TARGET_VXWORKS_RTP && flag_pic)
5918 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
5919 xops[2] = gen_rtx_MEM (Pmode,
5920 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
5921 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5923 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
5924 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
5925 an unadorned address. */
5926 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
5927 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
5928 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
5932 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
5934 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
5936 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
5939 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5941 output_asm_insn ("call\t%a2", xops);
5944 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5945 is what will be referenced by the Mach-O PIC subsystem. */
5947 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5950 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5951 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
5954 output_asm_insn ("pop{l}\t%0", xops);
5959 get_pc_thunk_name (name, REGNO (dest));
5960 pic_labels_used |= 1 << REGNO (dest);
5962 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5963 xops[2] = gen_rtx_MEM (QImode, xops[2]);
5964 output_asm_insn ("call\t%X2", xops);
5965 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5966 is what will be referenced by the Mach-O PIC subsystem. */
5969 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5971 targetm.asm_out.internal_label (asm_out_file, "L",
5972 CODE_LABEL_NUMBER (label));
5979 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
5980 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
5982 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
5987 /* Generate an "push" pattern for input ARG. */
5992 return gen_rtx_SET (VOIDmode,
5994 gen_rtx_PRE_DEC (Pmode,
5995 stack_pointer_rtx)),
5999 /* Return >= 0 if there is an unused call-clobbered register available
6000 for the entire function. */
6003 ix86_select_alt_pic_regnum (void)
6005 if (current_function_is_leaf && !crtl->profile
6006 && !ix86_current_function_calls_tls_descriptor)
6009 for (i = 2; i >= 0; --i)
6010 if (!df_regs_ever_live_p (i))
6014 return INVALID_REGNUM;
6017 /* Return 1 if we need to save REGNO. */
6019 ix86_save_reg (unsigned int regno, int maybe_eh_return)
6021 if (pic_offset_table_rtx
6022 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
6023 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
6025 || crtl->calls_eh_return
6026 || crtl->uses_const_pool))
6028 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
6033 if (crtl->calls_eh_return && maybe_eh_return)
6038 unsigned test = EH_RETURN_DATA_REGNO (i);
6039 if (test == INVALID_REGNUM)
6046 if (cfun->machine->force_align_arg_pointer
6047 && regno == REGNO (cfun->machine->force_align_arg_pointer))
6050 return (df_regs_ever_live_p (regno)
6051 && !call_used_regs[regno]
6052 && !fixed_regs[regno]
6053 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
6056 /* Return number of registers to be saved on the stack. */
6059 ix86_nsaved_regs (void)
6064 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
6065 if (ix86_save_reg (regno, true))
6070 /* Return the offset between two registers, one to be eliminated, and the other
6071 its replacement, at the start of a routine. */
6074 ix86_initial_elimination_offset (int from, int to)
6076 struct ix86_frame frame;
6077 ix86_compute_frame_layout (&frame);
6079 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
6080 return frame.hard_frame_pointer_offset;
6081 else if (from == FRAME_POINTER_REGNUM
6082 && to == HARD_FRAME_POINTER_REGNUM)
6083 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
6086 gcc_assert (to == STACK_POINTER_REGNUM);
6088 if (from == ARG_POINTER_REGNUM)
6089 return frame.stack_pointer_offset;
6091 gcc_assert (from == FRAME_POINTER_REGNUM);
6092 return frame.stack_pointer_offset - frame.frame_pointer_offset;
6096 /* Fill structure ix86_frame about frame of currently computed function. */
6099 ix86_compute_frame_layout (struct ix86_frame *frame)
6101 HOST_WIDE_INT total_size;
6102 unsigned int stack_alignment_needed;
6103 HOST_WIDE_INT offset;
6104 unsigned int preferred_alignment;
6105 HOST_WIDE_INT size = get_frame_size ();
6107 frame->nregs = ix86_nsaved_regs ();
6110 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
6111 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
6113 /* During reload iteration the amount of registers saved can change.
6114 Recompute the value as needed. Do not recompute when amount of registers
6115 didn't change as reload does multiple calls to the function and does not
6116 expect the decision to change within single iteration. */
6118 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
6120 int count = frame->nregs;
6122 cfun->machine->use_fast_prologue_epilogue_nregs = count;
6123 /* The fast prologue uses move instead of push to save registers. This
6124 is significantly longer, but also executes faster as modern hardware
6125 can execute the moves in parallel, but can't do that for push/pop.
6127 Be careful about choosing what prologue to emit: When function takes
6128 many instructions to execute we may use slow version as well as in
6129 case function is known to be outside hot spot (this is known with
6130 feedback only). Weight the size of function by number of registers
6131 to save as it is cheap to use one or two push instructions but very
6132 slow to use many of them. */
6134 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
6135 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
6136 || (flag_branch_probabilities
6137 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
6138 cfun->machine->use_fast_prologue_epilogue = false;
6140 cfun->machine->use_fast_prologue_epilogue
6141 = !expensive_function_p (count);
6143 if (TARGET_PROLOGUE_USING_MOVE
6144 && cfun->machine->use_fast_prologue_epilogue)
6145 frame->save_regs_using_mov = true;
6147 frame->save_regs_using_mov = false;
6150 /* Skip return address and saved base pointer. */
6151 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
6153 frame->hard_frame_pointer_offset = offset;
6155 /* Do some sanity checking of stack_alignment_needed and
6156 preferred_alignment, since i386 port is the only using those features
6157 that may break easily. */
6159 gcc_assert (!size || stack_alignment_needed);
6160 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
6161 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6162 gcc_assert (stack_alignment_needed
6163 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
6165 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
6166 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
6168 /* Register save area */
6169 offset += frame->nregs * UNITS_PER_WORD;
6172 if (ix86_save_varrargs_registers)
6174 offset += X86_64_VARARGS_SIZE;
6175 frame->va_arg_size = X86_64_VARARGS_SIZE;
6178 frame->va_arg_size = 0;
6180 /* Align start of frame for local function. */
6181 frame->padding1 = ((offset + stack_alignment_needed - 1)
6182 & -stack_alignment_needed) - offset;
6184 offset += frame->padding1;
6186 /* Frame pointer points here. */
6187 frame->frame_pointer_offset = offset;
6191 /* Add outgoing arguments area. Can be skipped if we eliminated
6192 all the function calls as dead code.
6193 Skipping is however impossible when function calls alloca. Alloca
6194 expander assumes that last crtl->outgoing_args_size
6195 of stack frame are unused. */
6196 if (ACCUMULATE_OUTGOING_ARGS
6197 && (!current_function_is_leaf || cfun->calls_alloca
6198 || ix86_current_function_calls_tls_descriptor))
6200 offset += crtl->outgoing_args_size;
6201 frame->outgoing_arguments_size = crtl->outgoing_args_size;
6204 frame->outgoing_arguments_size = 0;
6206 /* Align stack boundary. Only needed if we're calling another function
6208 if (!current_function_is_leaf || cfun->calls_alloca
6209 || ix86_current_function_calls_tls_descriptor)
6210 frame->padding2 = ((offset + preferred_alignment - 1)
6211 & -preferred_alignment) - offset;
6213 frame->padding2 = 0;
6215 offset += frame->padding2;
6217 /* We've reached end of stack frame. */
6218 frame->stack_pointer_offset = offset;
6220 /* Size prologue needs to allocate. */
6221 frame->to_allocate =
6222 (size + frame->padding1 + frame->padding2
6223 + frame->outgoing_arguments_size + frame->va_arg_size);
6225 if ((!frame->to_allocate && frame->nregs <= 1)
6226 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
6227 frame->save_regs_using_mov = false;
6229 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
6230 && current_function_is_leaf
6231 && !ix86_current_function_calls_tls_descriptor)
6233 frame->red_zone_size = frame->to_allocate;
6234 if (frame->save_regs_using_mov)
6235 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
6236 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
6237 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
6240 frame->red_zone_size = 0;
6241 frame->to_allocate -= frame->red_zone_size;
6242 frame->stack_pointer_offset -= frame->red_zone_size;
6244 fprintf (stderr, "\n");
6245 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
6246 fprintf (stderr, "size: %ld\n", (long)size);
6247 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
6248 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
6249 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
6250 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
6251 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
6252 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
6253 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
6254 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
6255 (long)frame->hard_frame_pointer_offset);
6256 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
6257 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
6258 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
6259 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
6263 /* Emit code to save registers in the prologue. */
6266 ix86_emit_save_regs (void)
6271 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
6272 if (ix86_save_reg (regno, true))
6274 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
6275 RTX_FRAME_RELATED_P (insn) = 1;
6279 /* Emit code to save registers using MOV insns. First register
6280 is restored from POINTER + OFFSET. */
6282 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
6287 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6288 if (ix86_save_reg (regno, true))
6290 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
6292 gen_rtx_REG (Pmode, regno));
6293 RTX_FRAME_RELATED_P (insn) = 1;
6294 offset += UNITS_PER_WORD;
6298 /* Expand prologue or epilogue stack adjustment.
6299 The pattern exist to put a dependency on all ebp-based memory accesses.
6300 STYLE should be negative if instructions should be marked as frame related,
6301 zero if %r11 register is live and cannot be freely used and positive
6305 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
6310 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
6311 else if (x86_64_immediate_operand (offset, DImode))
6312 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
6316 /* r11 is used by indirect sibcall return as well, set before the
6317 epilogue and used after the epilogue. ATM indirect sibcall
6318 shouldn't be used together with huge frame sizes in one
6319 function because of the frame_size check in sibcall.c. */
6321 r11 = gen_rtx_REG (DImode, R11_REG);
6322 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
6324 RTX_FRAME_RELATED_P (insn) = 1;
6325 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
6329 RTX_FRAME_RELATED_P (insn) = 1;
6332 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
6335 ix86_internal_arg_pointer (void)
6337 bool has_force_align_arg_pointer =
6338 (0 != lookup_attribute (ix86_force_align_arg_pointer_string,
6339 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))));
6340 if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
6341 && DECL_NAME (current_function_decl)
6342 && MAIN_NAME_P (DECL_NAME (current_function_decl))
6343 && DECL_FILE_SCOPE_P (current_function_decl))
6344 || ix86_force_align_arg_pointer
6345 || has_force_align_arg_pointer)
6347 /* Nested functions can't realign the stack due to a register
6349 if (DECL_CONTEXT (current_function_decl)
6350 && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL)
6352 if (ix86_force_align_arg_pointer)
6353 warning (0, "-mstackrealign ignored for nested functions");
6354 if (has_force_align_arg_pointer)
6355 error ("%s not supported for nested functions",
6356 ix86_force_align_arg_pointer_string);
6357 return virtual_incoming_args_rtx;
6359 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, CX_REG);
6360 return copy_to_reg (cfun->machine->force_align_arg_pointer);
6363 return virtual_incoming_args_rtx;
6366 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
6367 This is called from dwarf2out.c to emit call frame instructions
6368 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
6370 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
6372 rtx unspec = SET_SRC (pattern);
6373 gcc_assert (GET_CODE (unspec) == UNSPEC);
6377 case UNSPEC_REG_SAVE:
6378 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
6379 SET_DEST (pattern));
6381 case UNSPEC_DEF_CFA:
6382 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
6383 INTVAL (XVECEXP (unspec, 0, 0)));
6390 /* Expand the prologue into a bunch of separate insns. */
6393 ix86_expand_prologue (void)
6397 struct ix86_frame frame;
6398 HOST_WIDE_INT allocate;
6400 ix86_compute_frame_layout (&frame);
6402 if (cfun->machine->force_align_arg_pointer)
6406 /* Grab the argument pointer. */
6407 x = plus_constant (stack_pointer_rtx, 4);
6408 y = cfun->machine->force_align_arg_pointer;
6409 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
6410 RTX_FRAME_RELATED_P (insn) = 1;
6412 /* The unwind info consists of two parts: install the fafp as the cfa,
6413 and record the fafp as the "save register" of the stack pointer.
6414 The later is there in order that the unwinder can see where it
6415 should restore the stack pointer across the and insn. */
6416 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
6417 x = gen_rtx_SET (VOIDmode, y, x);
6418 RTX_FRAME_RELATED_P (x) = 1;
6419 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
6421 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
6422 RTX_FRAME_RELATED_P (y) = 1;
6423 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
6424 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6425 REG_NOTES (insn) = x;
6427 /* Align the stack. */
6428 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
6431 /* And here we cheat like madmen with the unwind info. We force the
6432 cfa register back to sp+4, which is exactly what it was at the
6433 start of the function. Re-pushing the return address results in
6434 the return at the same spot relative to the cfa, and thus is
6435 correct wrt the unwind info. */
6436 x = cfun->machine->force_align_arg_pointer;
6437 x = gen_frame_mem (Pmode, plus_constant (x, -4));
6438 insn = emit_insn (gen_push (x));
6439 RTX_FRAME_RELATED_P (insn) = 1;
6442 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
6443 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
6444 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
6445 REG_NOTES (insn) = x;
6448 /* Note: AT&T enter does NOT have reversed args. Enter is probably
6449 slower on all targets. Also sdb doesn't like it. */
6451 if (frame_pointer_needed)
6453 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
6454 RTX_FRAME_RELATED_P (insn) = 1;
6456 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6457 RTX_FRAME_RELATED_P (insn) = 1;
6460 allocate = frame.to_allocate;
6462 if (!frame.save_regs_using_mov)
6463 ix86_emit_save_regs ();
6465 allocate += frame.nregs * UNITS_PER_WORD;
6467 /* When using red zone we may start register saving before allocating
6468 the stack frame saving one cycle of the prologue. However I will
6469 avoid doing this if I am going to have to probe the stack since
6470 at least on x86_64 the stack probe can turn into a call that clobbers
6471 a red zone location */
6472 if (TARGET_RED_ZONE && frame.save_regs_using_mov
6473 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
6474 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
6475 : stack_pointer_rtx,
6476 -frame.nregs * UNITS_PER_WORD);
6480 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
6481 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6482 GEN_INT (-allocate), -1);
6485 /* Only valid for Win32. */
6486 rtx eax = gen_rtx_REG (Pmode, AX_REG);
6490 gcc_assert (!TARGET_64BIT || TARGET_64BIT_MS_ABI);
6492 if (TARGET_64BIT_MS_ABI)
6495 eax_live = ix86_eax_live_at_start_p ();
6499 emit_insn (gen_push (eax));
6500 allocate -= UNITS_PER_WORD;
6503 emit_move_insn (eax, GEN_INT (allocate));
6506 insn = gen_allocate_stack_worker_64 (eax);
6508 insn = gen_allocate_stack_worker_32 (eax);
6509 insn = emit_insn (insn);
6510 RTX_FRAME_RELATED_P (insn) = 1;
6511 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
6512 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
6513 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6514 t, REG_NOTES (insn));
6518 if (frame_pointer_needed)
6519 t = plus_constant (hard_frame_pointer_rtx,
6522 - frame.nregs * UNITS_PER_WORD);
6524 t = plus_constant (stack_pointer_rtx, allocate);
6525 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
6529 if (frame.save_regs_using_mov
6530 && !(TARGET_RED_ZONE
6531 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
6533 if (!frame_pointer_needed || !frame.to_allocate)
6534 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
6536 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
6537 -frame.nregs * UNITS_PER_WORD);
6540 pic_reg_used = false;
6541 if (pic_offset_table_rtx
6542 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
6545 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
6547 if (alt_pic_reg_used != INVALID_REGNUM)
6548 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
6550 pic_reg_used = true;
6557 if (ix86_cmodel == CM_LARGE_PIC)
6559 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
6560 rtx label = gen_label_rtx ();
6562 LABEL_PRESERVE_P (label) = 1;
6563 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
6564 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
6565 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
6566 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
6567 pic_offset_table_rtx, tmp_reg));
6570 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
6573 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
6576 /* Prevent function calls from being scheduled before the call to mcount.
6577 In the pic_reg_used case, make sure that the got load isn't deleted. */
6581 emit_insn (gen_prologue_use (pic_offset_table_rtx));
6582 emit_insn (gen_blockage ());
6586 /* Emit code to restore saved registers using MOV insns. First register
6587 is restored from POINTER + OFFSET. */
6589 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
6590 int maybe_eh_return)
6593 rtx base_address = gen_rtx_MEM (Pmode, pointer);
6595 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6596 if (ix86_save_reg (regno, maybe_eh_return))
6598 /* Ensure that adjust_address won't be forced to produce pointer
6599 out of range allowed by x86-64 instruction set. */
6600 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
6604 r11 = gen_rtx_REG (DImode, R11_REG);
6605 emit_move_insn (r11, GEN_INT (offset));
6606 emit_insn (gen_adddi3 (r11, r11, pointer));
6607 base_address = gen_rtx_MEM (Pmode, r11);
6610 emit_move_insn (gen_rtx_REG (Pmode, regno),
6611 adjust_address (base_address, Pmode, offset));
6612 offset += UNITS_PER_WORD;
6616 /* Restore function stack, frame, and registers. */
6619 ix86_expand_epilogue (int style)
6622 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
6623 struct ix86_frame frame;
6624 HOST_WIDE_INT offset;
6626 ix86_compute_frame_layout (&frame);
6628 /* Calculate start of saved registers relative to ebp. Special care
6629 must be taken for the normal return case of a function using
6630 eh_return: the eax and edx registers are marked as saved, but not
6631 restored along this path. */
6632 offset = frame.nregs;
6633 if (crtl->calls_eh_return && style != 2)
6635 offset *= -UNITS_PER_WORD;
6637 /* If we're only restoring one register and sp is not valid then
6638 using a move instruction to restore the register since it's
6639 less work than reloading sp and popping the register.
6641 The default code result in stack adjustment using add/lea instruction,
6642 while this code results in LEAVE instruction (or discrete equivalent),
6643 so it is profitable in some other cases as well. Especially when there
6644 are no registers to restore. We also use this code when TARGET_USE_LEAVE
6645 and there is exactly one register to pop. This heuristic may need some
6646 tuning in future. */
6647 if ((!sp_valid && frame.nregs <= 1)
6648 || (TARGET_EPILOGUE_USING_MOVE
6649 && cfun->machine->use_fast_prologue_epilogue
6650 && (frame.nregs > 1 || frame.to_allocate))
6651 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
6652 || (frame_pointer_needed && TARGET_USE_LEAVE
6653 && cfun->machine->use_fast_prologue_epilogue
6654 && frame.nregs == 1)
6655 || crtl->calls_eh_return)
6657 /* Restore registers. We can use ebp or esp to address the memory
6658 locations. If both are available, default to ebp, since offsets
6659 are known to be small. Only exception is esp pointing directly to the
6660 end of block of saved registers, where we may simplify addressing
6663 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
6664 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
6665 frame.to_allocate, style == 2);
6667 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
6668 offset, style == 2);
6670 /* eh_return epilogues need %ecx added to the stack pointer. */
6673 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
6675 if (frame_pointer_needed)
6677 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
6678 tmp = plus_constant (tmp, UNITS_PER_WORD);
6679 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
6681 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
6682 emit_move_insn (hard_frame_pointer_rtx, tmp);
6684 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
6689 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
6690 tmp = plus_constant (tmp, (frame.to_allocate
6691 + frame.nregs * UNITS_PER_WORD));
6692 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
6695 else if (!frame_pointer_needed)
6696 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6697 GEN_INT (frame.to_allocate
6698 + frame.nregs * UNITS_PER_WORD),
6700 /* If not an i386, mov & pop is faster than "leave". */
6701 else if (TARGET_USE_LEAVE || optimize_size
6702 || !cfun->machine->use_fast_prologue_epilogue)
6703 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6706 pro_epilogue_adjust_stack (stack_pointer_rtx,
6707 hard_frame_pointer_rtx,
6710 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6712 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6717 /* First step is to deallocate the stack frame so that we can
6718 pop the registers. */
6721 gcc_assert (frame_pointer_needed);
6722 pro_epilogue_adjust_stack (stack_pointer_rtx,
6723 hard_frame_pointer_rtx,
6724 GEN_INT (offset), style);
6726 else if (frame.to_allocate)
6727 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6728 GEN_INT (frame.to_allocate), style);
6730 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6731 if (ix86_save_reg (regno, false))
6734 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
6736 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
6738 if (frame_pointer_needed)
6740 /* Leave results in shorter dependency chains on CPUs that are
6741 able to grok it fast. */
6742 if (TARGET_USE_LEAVE)
6743 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6744 else if (TARGET_64BIT)
6745 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6747 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6751 if (cfun->machine->force_align_arg_pointer)
6753 emit_insn (gen_addsi3 (stack_pointer_rtx,
6754 cfun->machine->force_align_arg_pointer,
6758 /* Sibcall epilogues don't want a return instruction. */
6762 if (crtl->args.pops_args && crtl->args.size)
6764 rtx popc = GEN_INT (crtl->args.pops_args);
6766 /* i386 can only pop 64K bytes. If asked to pop more, pop
6767 return address, do explicit add, and jump indirectly to the
6770 if (crtl->args.pops_args >= 65536)
6772 rtx ecx = gen_rtx_REG (SImode, CX_REG);
6774 /* There is no "pascal" calling convention in any 64bit ABI. */
6775 gcc_assert (!TARGET_64BIT);
6777 emit_insn (gen_popsi1 (ecx));
6778 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
6779 emit_jump_insn (gen_return_indirect_internal (ecx));
6782 emit_jump_insn (gen_return_pop_internal (popc));
6785 emit_jump_insn (gen_return_internal ());
6788 /* Reset from the function's potential modifications. */
6791 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6792 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6794 if (pic_offset_table_rtx)
6795 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
6797 /* Mach-O doesn't support labels at the end of objects, so if
6798 it looks like we might want one, insert a NOP. */
6800 rtx insn = get_last_insn ();
6803 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
6804 insn = PREV_INSN (insn);
6808 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
6809 fputs ("\tnop\n", file);
6815 /* Extract the parts of an RTL expression that is a valid memory address
6816 for an instruction. Return 0 if the structure of the address is
6817 grossly off. Return -1 if the address contains ASHIFT, so it is not
6818 strictly valid, but still used for computing length of lea instruction. */
6821 ix86_decompose_address (rtx addr, struct ix86_address *out)
6823 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
6824 rtx base_reg, index_reg;
6825 HOST_WIDE_INT scale = 1;
6826 rtx scale_rtx = NULL_RTX;
6828 enum ix86_address_seg seg = SEG_DEFAULT;
6830 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
6832 else if (GET_CODE (addr) == PLUS)
6842 addends[n++] = XEXP (op, 1);
6845 while (GET_CODE (op) == PLUS);
6850 for (i = n; i >= 0; --i)
6853 switch (GET_CODE (op))
6858 index = XEXP (op, 0);
6859 scale_rtx = XEXP (op, 1);
6863 if (XINT (op, 1) == UNSPEC_TP
6864 && TARGET_TLS_DIRECT_SEG_REFS
6865 && seg == SEG_DEFAULT)
6866 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
6895 else if (GET_CODE (addr) == MULT)
6897 index = XEXP (addr, 0); /* index*scale */
6898 scale_rtx = XEXP (addr, 1);
6900 else if (GET_CODE (addr) == ASHIFT)
6904 /* We're called for lea too, which implements ashift on occasion. */
6905 index = XEXP (addr, 0);
6906 tmp = XEXP (addr, 1);
6907 if (!CONST_INT_P (tmp))
6909 scale = INTVAL (tmp);
6910 if ((unsigned HOST_WIDE_INT) scale > 3)
6916 disp = addr; /* displacement */
6918 /* Extract the integral value of scale. */
6921 if (!CONST_INT_P (scale_rtx))
6923 scale = INTVAL (scale_rtx);
6926 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
6927 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
6929 /* Allow arg pointer and stack pointer as index if there is not scaling. */
6930 if (base_reg && index_reg && scale == 1
6931 && (index_reg == arg_pointer_rtx
6932 || index_reg == frame_pointer_rtx
6933 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
6936 tmp = base, base = index, index = tmp;
6937 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
6940 /* Special case: %ebp cannot be encoded as a base without a displacement. */
6941 if ((base_reg == hard_frame_pointer_rtx
6942 || base_reg == frame_pointer_rtx
6943 || base_reg == arg_pointer_rtx) && !disp)
6946 /* Special case: on K6, [%esi] makes the instruction vector decoded.
6947 Avoid this by transforming to [%esi+0]. */
6948 if (TARGET_K6 && !optimize_size
6949 && base_reg && !index_reg && !disp
6951 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
6954 /* Special case: encode reg+reg instead of reg*2. */
6955 if (!base && index && scale && scale == 2)
6956 base = index, base_reg = index_reg, scale = 1;
6958 /* Special case: scaling cannot be encoded without base or displacement. */
6959 if (!base && !disp && index && scale != 1)
6971 /* Return cost of the memory address x.
6972 For i386, it is better to use a complex address than let gcc copy
6973 the address into a reg and make a new pseudo. But not if the address
6974 requires to two regs - that would mean more pseudos with longer
6977 ix86_address_cost (rtx x)
6979 struct ix86_address parts;
6981 int ok = ix86_decompose_address (x, &parts);
6985 if (parts.base && GET_CODE (parts.base) == SUBREG)
6986 parts.base = SUBREG_REG (parts.base);
6987 if (parts.index && GET_CODE (parts.index) == SUBREG)
6988 parts.index = SUBREG_REG (parts.index);
6990 /* Attempt to minimize number of registers in the address. */
6992 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
6994 && (!REG_P (parts.index)
6995 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
6999 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
7001 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
7002 && parts.base != parts.index)
7005 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
7006 since it's predecode logic can't detect the length of instructions
7007 and it degenerates to vector decoded. Increase cost of such
7008 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
7009 to split such addresses or even refuse such addresses at all.
7011 Following addressing modes are affected:
7016 The first and last case may be avoidable by explicitly coding the zero in
7017 memory address, but I don't have AMD-K6 machine handy to check this
7021 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
7022 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
7023 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
7029 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
7030 this is used for to form addresses to local data when -fPIC is in
7034 darwin_local_data_pic (rtx disp)
7036 if (GET_CODE (disp) == MINUS)
7038 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
7039 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
7040 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
7042 const char *sym_name = XSTR (XEXP (disp, 1), 0);
7043 if (! strcmp (sym_name, "<pic base>"))
7051 /* Determine if a given RTX is a valid constant. We already know this
7052 satisfies CONSTANT_P. */
7055 legitimate_constant_p (rtx x)
7057 switch (GET_CODE (x))
7062 if (GET_CODE (x) == PLUS)
7064 if (!CONST_INT_P (XEXP (x, 1)))
7069 if (TARGET_MACHO && darwin_local_data_pic (x))
7072 /* Only some unspecs are valid as "constants". */
7073 if (GET_CODE (x) == UNSPEC)
7074 switch (XINT (x, 1))
7079 return TARGET_64BIT;
7082 x = XVECEXP (x, 0, 0);
7083 return (GET_CODE (x) == SYMBOL_REF
7084 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7086 x = XVECEXP (x, 0, 0);
7087 return (GET_CODE (x) == SYMBOL_REF
7088 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
7093 /* We must have drilled down to a symbol. */
7094 if (GET_CODE (x) == LABEL_REF)
7096 if (GET_CODE (x) != SYMBOL_REF)
7101 /* TLS symbols are never valid. */
7102 if (SYMBOL_REF_TLS_MODEL (x))
7105 /* DLLIMPORT symbols are never valid. */
7106 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
7107 && SYMBOL_REF_DLLIMPORT_P (x))
7112 if (GET_MODE (x) == TImode
7113 && x != CONST0_RTX (TImode)
7119 if (x == CONST0_RTX (GET_MODE (x)))
7127 /* Otherwise we handle everything else in the move patterns. */
7131 /* Determine if it's legal to put X into the constant pool. This
7132 is not possible for the address of thread-local symbols, which
7133 is checked above. */
7136 ix86_cannot_force_const_mem (rtx x)
7138 /* We can always put integral constants and vectors in memory. */
7139 switch (GET_CODE (x))
7149 return !legitimate_constant_p (x);
7152 /* Determine if a given RTX is a valid constant address. */
7155 constant_address_p (rtx x)
7157 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
7160 /* Nonzero if the constant value X is a legitimate general operand
7161 when generating PIC code. It is given that flag_pic is on and
7162 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
7165 legitimate_pic_operand_p (rtx x)
7169 switch (GET_CODE (x))
7172 inner = XEXP (x, 0);
7173 if (GET_CODE (inner) == PLUS
7174 && CONST_INT_P (XEXP (inner, 1)))
7175 inner = XEXP (inner, 0);
7177 /* Only some unspecs are valid as "constants". */
7178 if (GET_CODE (inner) == UNSPEC)
7179 switch (XINT (inner, 1))
7184 return TARGET_64BIT;
7186 x = XVECEXP (inner, 0, 0);
7187 return (GET_CODE (x) == SYMBOL_REF
7188 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
7196 return legitimate_pic_address_disp_p (x);
7203 /* Determine if a given CONST RTX is a valid memory displacement
7207 legitimate_pic_address_disp_p (rtx disp)
7211 /* In 64bit mode we can allow direct addresses of symbols and labels
7212 when they are not dynamic symbols. */
7215 rtx op0 = disp, op1;
7217 switch (GET_CODE (disp))
7223 if (GET_CODE (XEXP (disp, 0)) != PLUS)
7225 op0 = XEXP (XEXP (disp, 0), 0);
7226 op1 = XEXP (XEXP (disp, 0), 1);
7227 if (!CONST_INT_P (op1)
7228 || INTVAL (op1) >= 16*1024*1024
7229 || INTVAL (op1) < -16*1024*1024)
7231 if (GET_CODE (op0) == LABEL_REF)
7233 if (GET_CODE (op0) != SYMBOL_REF)
7238 /* TLS references should always be enclosed in UNSPEC. */
7239 if (SYMBOL_REF_TLS_MODEL (op0))
7241 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
7242 && ix86_cmodel != CM_LARGE_PIC)
7250 if (GET_CODE (disp) != CONST)
7252 disp = XEXP (disp, 0);
7256 /* We are unsafe to allow PLUS expressions. This limit allowed distance
7257 of GOT tables. We should not need these anyway. */
7258 if (GET_CODE (disp) != UNSPEC
7259 || (XINT (disp, 1) != UNSPEC_GOTPCREL
7260 && XINT (disp, 1) != UNSPEC_GOTOFF
7261 && XINT (disp, 1) != UNSPEC_PLTOFF))
7264 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
7265 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
7271 if (GET_CODE (disp) == PLUS)
7273 if (!CONST_INT_P (XEXP (disp, 1)))
7275 disp = XEXP (disp, 0);
7279 if (TARGET_MACHO && darwin_local_data_pic (disp))
7282 if (GET_CODE (disp) != UNSPEC)
7285 switch (XINT (disp, 1))
7290 /* We need to check for both symbols and labels because VxWorks loads
7291 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
7293 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7294 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
7296 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
7297 While ABI specify also 32bit relocation but we don't produce it in
7298 small PIC model at all. */
7299 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
7300 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
7302 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
7304 case UNSPEC_GOTTPOFF:
7305 case UNSPEC_GOTNTPOFF:
7306 case UNSPEC_INDNTPOFF:
7309 disp = XVECEXP (disp, 0, 0);
7310 return (GET_CODE (disp) == SYMBOL_REF
7311 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
7313 disp = XVECEXP (disp, 0, 0);
7314 return (GET_CODE (disp) == SYMBOL_REF
7315 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
7317 disp = XVECEXP (disp, 0, 0);
7318 return (GET_CODE (disp) == SYMBOL_REF
7319 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
7325 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
7326 memory address for an instruction. The MODE argument is the machine mode
7327 for the MEM expression that wants to use this address.
7329 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
7330 convert common non-canonical forms to canonical form so that they will
7334 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
7335 rtx addr, int strict)
7337 struct ix86_address parts;
7338 rtx base, index, disp;
7339 HOST_WIDE_INT scale;
7340 const char *reason = NULL;
7341 rtx reason_rtx = NULL_RTX;
7343 if (ix86_decompose_address (addr, &parts) <= 0)
7345 reason = "decomposition failed";
7350 index = parts.index;
7352 scale = parts.scale;
7354 /* Validate base register.
7356 Don't allow SUBREG's that span more than a word here. It can lead to spill
7357 failures when the base is one word out of a two word structure, which is
7358 represented internally as a DImode int. */
7367 else if (GET_CODE (base) == SUBREG
7368 && REG_P (SUBREG_REG (base))
7369 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
7371 reg = SUBREG_REG (base);
7374 reason = "base is not a register";
7378 if (GET_MODE (base) != Pmode)
7380 reason = "base is not in Pmode";
7384 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
7385 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
7387 reason = "base is not valid";
7392 /* Validate index register.
7394 Don't allow SUBREG's that span more than a word here -- same as above. */
7403 else if (GET_CODE (index) == SUBREG
7404 && REG_P (SUBREG_REG (index))
7405 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
7407 reg = SUBREG_REG (index);
7410 reason = "index is not a register";
7414 if (GET_MODE (index) != Pmode)
7416 reason = "index is not in Pmode";
7420 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
7421 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
7423 reason = "index is not valid";
7428 /* Validate scale factor. */
7431 reason_rtx = GEN_INT (scale);
7434 reason = "scale without index";
7438 if (scale != 2 && scale != 4 && scale != 8)
7440 reason = "scale is not a valid multiplier";
7445 /* Validate displacement. */
7450 if (GET_CODE (disp) == CONST
7451 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
7452 switch (XINT (XEXP (disp, 0), 1))
7454 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
7455 used. While ABI specify also 32bit relocations, we don't produce
7456 them at all and use IP relative instead. */
7459 gcc_assert (flag_pic);
7461 goto is_legitimate_pic;
7462 reason = "64bit address unspec";
7465 case UNSPEC_GOTPCREL:
7466 gcc_assert (flag_pic);
7467 goto is_legitimate_pic;
7469 case UNSPEC_GOTTPOFF:
7470 case UNSPEC_GOTNTPOFF:
7471 case UNSPEC_INDNTPOFF:
7477 reason = "invalid address unspec";
7481 else if (SYMBOLIC_CONST (disp)
7485 && MACHOPIC_INDIRECT
7486 && !machopic_operand_p (disp)
7492 if (TARGET_64BIT && (index || base))
7494 /* foo@dtpoff(%rX) is ok. */
7495 if (GET_CODE (disp) != CONST
7496 || GET_CODE (XEXP (disp, 0)) != PLUS
7497 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
7498 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
7499 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
7500 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
7502 reason = "non-constant pic memory reference";
7506 else if (! legitimate_pic_address_disp_p (disp))
7508 reason = "displacement is an invalid pic construct";
7512 /* This code used to verify that a symbolic pic displacement
7513 includes the pic_offset_table_rtx register.
7515 While this is good idea, unfortunately these constructs may
7516 be created by "adds using lea" optimization for incorrect
7525 This code is nonsensical, but results in addressing
7526 GOT table with pic_offset_table_rtx base. We can't
7527 just refuse it easily, since it gets matched by
7528 "addsi3" pattern, that later gets split to lea in the
7529 case output register differs from input. While this
7530 can be handled by separate addsi pattern for this case
7531 that never results in lea, this seems to be easier and
7532 correct fix for crash to disable this test. */
7534 else if (GET_CODE (disp) != LABEL_REF
7535 && !CONST_INT_P (disp)
7536 && (GET_CODE (disp) != CONST
7537 || !legitimate_constant_p (disp))
7538 && (GET_CODE (disp) != SYMBOL_REF
7539 || !legitimate_constant_p (disp)))
7541 reason = "displacement is not constant";
7544 else if (TARGET_64BIT
7545 && !x86_64_immediate_operand (disp, VOIDmode))
7547 reason = "displacement is out of range";
7552 /* Everything looks valid. */
7559 /* Return a unique alias set for the GOT. */
7561 static alias_set_type
7562 ix86_GOT_alias_set (void)
7564 static alias_set_type set = -1;
7566 set = new_alias_set ();
7570 /* Return a legitimate reference for ORIG (an address) using the
7571 register REG. If REG is 0, a new pseudo is generated.
7573 There are two types of references that must be handled:
7575 1. Global data references must load the address from the GOT, via
7576 the PIC reg. An insn is emitted to do this load, and the reg is
7579 2. Static data references, constant pool addresses, and code labels
7580 compute the address as an offset from the GOT, whose base is in
7581 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
7582 differentiate them from global data objects. The returned
7583 address is the PIC reg + an unspec constant.
7585 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
7586 reg also appears in the address. */
7589 legitimize_pic_address (rtx orig, rtx reg)
7596 if (TARGET_MACHO && !TARGET_64BIT)
7599 reg = gen_reg_rtx (Pmode);
7600 /* Use the generic Mach-O PIC machinery. */
7601 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
7605 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
7607 else if (TARGET_64BIT
7608 && ix86_cmodel != CM_SMALL_PIC
7609 && gotoff_operand (addr, Pmode))
7612 /* This symbol may be referenced via a displacement from the PIC
7613 base address (@GOTOFF). */
7615 if (reload_in_progress)
7616 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7617 if (GET_CODE (addr) == CONST)
7618 addr = XEXP (addr, 0);
7619 if (GET_CODE (addr) == PLUS)
7621 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7623 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7626 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7627 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7629 tmpreg = gen_reg_rtx (Pmode);
7632 emit_move_insn (tmpreg, new_rtx);
7636 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
7637 tmpreg, 1, OPTAB_DIRECT);
7640 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
7642 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
7644 /* This symbol may be referenced via a displacement from the PIC
7645 base address (@GOTOFF). */
7647 if (reload_in_progress)
7648 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7649 if (GET_CODE (addr) == CONST)
7650 addr = XEXP (addr, 0);
7651 if (GET_CODE (addr) == PLUS)
7653 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7655 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
7658 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7659 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7660 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7664 emit_move_insn (reg, new_rtx);
7668 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
7669 /* We can't use @GOTOFF for text labels on VxWorks;
7670 see gotoff_operand. */
7671 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
7673 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
7675 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
7676 return legitimize_dllimport_symbol (addr, true);
7677 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
7678 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
7679 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
7681 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
7682 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
7686 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
7688 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
7689 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7690 new_rtx = gen_const_mem (Pmode, new_rtx);
7691 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7694 reg = gen_reg_rtx (Pmode);
7695 /* Use directly gen_movsi, otherwise the address is loaded
7696 into register for CSE. We don't want to CSE this addresses,
7697 instead we CSE addresses from the GOT table, so skip this. */
7698 emit_insn (gen_movsi (reg, new_rtx));
7703 /* This symbol must be referenced via a load from the
7704 Global Offset Table (@GOT). */
7706 if (reload_in_progress)
7707 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7708 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
7709 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7711 new_rtx = force_reg (Pmode, new_rtx);
7712 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7713 new_rtx = gen_const_mem (Pmode, new_rtx);
7714 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
7717 reg = gen_reg_rtx (Pmode);
7718 emit_move_insn (reg, new_rtx);
7724 if (CONST_INT_P (addr)
7725 && !x86_64_immediate_operand (addr, VOIDmode))
7729 emit_move_insn (reg, addr);
7733 new_rtx = force_reg (Pmode, addr);
7735 else if (GET_CODE (addr) == CONST)
7737 addr = XEXP (addr, 0);
7739 /* We must match stuff we generate before. Assume the only
7740 unspecs that can get here are ours. Not that we could do
7741 anything with them anyway.... */
7742 if (GET_CODE (addr) == UNSPEC
7743 || (GET_CODE (addr) == PLUS
7744 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
7746 gcc_assert (GET_CODE (addr) == PLUS);
7748 if (GET_CODE (addr) == PLUS)
7750 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
7752 /* Check first to see if this is a constant offset from a @GOTOFF
7753 symbol reference. */
7754 if (gotoff_operand (op0, Pmode)
7755 && CONST_INT_P (op1))
7759 if (reload_in_progress)
7760 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7761 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
7763 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
7764 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
7765 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
7769 emit_move_insn (reg, new_rtx);
7775 if (INTVAL (op1) < -16*1024*1024
7776 || INTVAL (op1) >= 16*1024*1024)
7778 if (!x86_64_immediate_operand (op1, Pmode))
7779 op1 = force_reg (Pmode, op1);
7780 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
7786 base = legitimize_pic_address (XEXP (addr, 0), reg);
7787 new_rtx = legitimize_pic_address (XEXP (addr, 1),
7788 base == reg ? NULL_RTX : reg);
7790 if (CONST_INT_P (new_rtx))
7791 new_rtx = plus_constant (base, INTVAL (new_rtx));
7794 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
7796 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
7797 new_rtx = XEXP (new_rtx, 1);
7799 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
7807 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7810 get_thread_pointer (int to_reg)
7814 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
7818 reg = gen_reg_rtx (Pmode);
7819 insn = gen_rtx_SET (VOIDmode, reg, tp);
7820 insn = emit_insn (insn);
7825 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7826 false if we expect this to be used for a memory address and true if
7827 we expect to load the address into a register. */
7830 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
7832 rtx dest, base, off, pic, tp;
7837 case TLS_MODEL_GLOBAL_DYNAMIC:
7838 dest = gen_reg_rtx (Pmode);
7839 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7841 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7843 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
7846 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
7847 insns = get_insns ();
7850 CONST_OR_PURE_CALL_P (insns) = 1;
7851 emit_libcall_block (insns, dest, rax, x);
7853 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7854 emit_insn (gen_tls_global_dynamic_64 (dest, x));
7856 emit_insn (gen_tls_global_dynamic_32 (dest, x));
7858 if (TARGET_GNU2_TLS)
7860 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
7862 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7866 case TLS_MODEL_LOCAL_DYNAMIC:
7867 base = gen_reg_rtx (Pmode);
7868 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7870 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7872 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
7875 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
7876 insns = get_insns ();
7879 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
7880 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
7881 CONST_OR_PURE_CALL_P (insns) = 1;
7882 emit_libcall_block (insns, base, rax, note);
7884 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7885 emit_insn (gen_tls_local_dynamic_base_64 (base));
7887 emit_insn (gen_tls_local_dynamic_base_32 (base));
7889 if (TARGET_GNU2_TLS)
7891 rtx x = ix86_tls_module_base ();
7893 set_unique_reg_note (get_last_insn (), REG_EQUIV,
7894 gen_rtx_MINUS (Pmode, x, tp));
7897 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
7898 off = gen_rtx_CONST (Pmode, off);
7900 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
7902 if (TARGET_GNU2_TLS)
7904 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
7906 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7911 case TLS_MODEL_INITIAL_EXEC:
7915 type = UNSPEC_GOTNTPOFF;
7919 if (reload_in_progress)
7920 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
7921 pic = pic_offset_table_rtx;
7922 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
7924 else if (!TARGET_ANY_GNU_TLS)
7926 pic = gen_reg_rtx (Pmode);
7927 emit_insn (gen_set_got (pic));
7928 type = UNSPEC_GOTTPOFF;
7933 type = UNSPEC_INDNTPOFF;
7936 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
7937 off = gen_rtx_CONST (Pmode, off);
7939 off = gen_rtx_PLUS (Pmode, pic, off);
7940 off = gen_const_mem (Pmode, off);
7941 set_mem_alias_set (off, ix86_GOT_alias_set ());
7943 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7945 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7946 off = force_reg (Pmode, off);
7947 return gen_rtx_PLUS (Pmode, base, off);
7951 base = get_thread_pointer (true);
7952 dest = gen_reg_rtx (Pmode);
7953 emit_insn (gen_subsi3 (dest, base, off));
7957 case TLS_MODEL_LOCAL_EXEC:
7958 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
7959 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7960 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
7961 off = gen_rtx_CONST (Pmode, off);
7963 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7965 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7966 return gen_rtx_PLUS (Pmode, base, off);
7970 base = get_thread_pointer (true);
7971 dest = gen_reg_rtx (Pmode);
7972 emit_insn (gen_subsi3 (dest, base, off));
7983 /* Create or return the unique __imp_DECL dllimport symbol corresponding
7986 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
7987 htab_t dllimport_map;
7990 get_dllimport_decl (tree decl)
7992 struct tree_map *h, in;
7996 size_t namelen, prefixlen;
8002 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
8004 in.hash = htab_hash_pointer (decl);
8005 in.base.from = decl;
8006 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
8007 h = (struct tree_map *) *loc;
8011 *loc = h = GGC_NEW (struct tree_map);
8013 h->base.from = decl;
8014 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
8015 DECL_ARTIFICIAL (to) = 1;
8016 DECL_IGNORED_P (to) = 1;
8017 DECL_EXTERNAL (to) = 1;
8018 TREE_READONLY (to) = 1;
8020 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
8021 name = targetm.strip_name_encoding (name);
8022 prefix = name[0] == FASTCALL_PREFIX ? "*__imp_": "*__imp__";
8023 namelen = strlen (name);
8024 prefixlen = strlen (prefix);
8025 imp_name = (char *) alloca (namelen + prefixlen + 1);
8026 memcpy (imp_name, prefix, prefixlen);
8027 memcpy (imp_name + prefixlen, name, namelen + 1);
8029 name = ggc_alloc_string (imp_name, namelen + prefixlen);
8030 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
8031 SET_SYMBOL_REF_DECL (rtl, to);
8032 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
8034 rtl = gen_const_mem (Pmode, rtl);
8035 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
8037 SET_DECL_RTL (to, rtl);
8038 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
8043 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
8044 true if we require the result be a register. */
8047 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
8052 gcc_assert (SYMBOL_REF_DECL (symbol));
8053 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
8055 x = DECL_RTL (imp_decl);
8057 x = force_reg (Pmode, x);
8061 /* Try machine-dependent ways of modifying an illegitimate address
8062 to be legitimate. If we find one, return the new, valid address.
8063 This macro is used in only one place: `memory_address' in explow.c.
8065 OLDX is the address as it was before break_out_memory_refs was called.
8066 In some cases it is useful to look at this to decide what needs to be done.
8068 MODE and WIN are passed so that this macro can use
8069 GO_IF_LEGITIMATE_ADDRESS.
8071 It is always safe for this macro to do nothing. It exists to recognize
8072 opportunities to optimize the output.
8074 For the 80386, we handle X+REG by loading X into a register R and
8075 using R+REG. R will go in a general reg and indexing will be used.
8076 However, if REG is a broken-out memory address or multiplication,
8077 nothing needs to be done because REG can certainly go in a general reg.
8079 When -fpic is used, special handling is needed for symbolic references.
8080 See comments by legitimize_pic_address in i386.c for details. */
8083 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
8088 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
8090 return legitimize_tls_address (x, (enum tls_model) log, false);
8091 if (GET_CODE (x) == CONST
8092 && GET_CODE (XEXP (x, 0)) == PLUS
8093 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8094 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
8096 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
8097 (enum tls_model) log, false);
8098 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8101 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
8103 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
8104 return legitimize_dllimport_symbol (x, true);
8105 if (GET_CODE (x) == CONST
8106 && GET_CODE (XEXP (x, 0)) == PLUS
8107 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
8108 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
8110 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
8111 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
8115 if (flag_pic && SYMBOLIC_CONST (x))
8116 return legitimize_pic_address (x, 0);
8118 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
8119 if (GET_CODE (x) == ASHIFT
8120 && CONST_INT_P (XEXP (x, 1))
8121 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
8124 log = INTVAL (XEXP (x, 1));
8125 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
8126 GEN_INT (1 << log));
8129 if (GET_CODE (x) == PLUS)
8131 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
8133 if (GET_CODE (XEXP (x, 0)) == ASHIFT
8134 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8135 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
8138 log = INTVAL (XEXP (XEXP (x, 0), 1));
8139 XEXP (x, 0) = gen_rtx_MULT (Pmode,
8140 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
8141 GEN_INT (1 << log));
8144 if (GET_CODE (XEXP (x, 1)) == ASHIFT
8145 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
8146 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
8149 log = INTVAL (XEXP (XEXP (x, 1), 1));
8150 XEXP (x, 1) = gen_rtx_MULT (Pmode,
8151 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
8152 GEN_INT (1 << log));
8155 /* Put multiply first if it isn't already. */
8156 if (GET_CODE (XEXP (x, 1)) == MULT)
8158 rtx tmp = XEXP (x, 0);
8159 XEXP (x, 0) = XEXP (x, 1);
8164 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
8165 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
8166 created by virtual register instantiation, register elimination, and
8167 similar optimizations. */
8168 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
8171 x = gen_rtx_PLUS (Pmode,
8172 gen_rtx_PLUS (Pmode, XEXP (x, 0),
8173 XEXP (XEXP (x, 1), 0)),
8174 XEXP (XEXP (x, 1), 1));
8178 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
8179 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
8180 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
8181 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
8182 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
8183 && CONSTANT_P (XEXP (x, 1)))
8186 rtx other = NULL_RTX;
8188 if (CONST_INT_P (XEXP (x, 1)))
8190 constant = XEXP (x, 1);
8191 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
8193 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
8195 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
8196 other = XEXP (x, 1);
8204 x = gen_rtx_PLUS (Pmode,
8205 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
8206 XEXP (XEXP (XEXP (x, 0), 1), 0)),
8207 plus_constant (other, INTVAL (constant)));
8211 if (changed && legitimate_address_p (mode, x, FALSE))
8214 if (GET_CODE (XEXP (x, 0)) == MULT)
8217 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
8220 if (GET_CODE (XEXP (x, 1)) == MULT)
8223 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
8227 && REG_P (XEXP (x, 1))
8228 && REG_P (XEXP (x, 0)))
8231 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
8234 x = legitimize_pic_address (x, 0);
8237 if (changed && legitimate_address_p (mode, x, FALSE))
8240 if (REG_P (XEXP (x, 0)))
8242 rtx temp = gen_reg_rtx (Pmode);
8243 rtx val = force_operand (XEXP (x, 1), temp);
8245 emit_move_insn (temp, val);
8251 else if (REG_P (XEXP (x, 1)))
8253 rtx temp = gen_reg_rtx (Pmode);
8254 rtx val = force_operand (XEXP (x, 0), temp);
8256 emit_move_insn (temp, val);
8266 /* Print an integer constant expression in assembler syntax. Addition
8267 and subtraction are the only arithmetic that may appear in these
8268 expressions. FILE is the stdio stream to write to, X is the rtx, and
8269 CODE is the operand print code from the output string. */
8272 output_pic_addr_const (FILE *file, rtx x, int code)
8276 switch (GET_CODE (x))
8279 gcc_assert (flag_pic);
8284 if (! TARGET_MACHO || TARGET_64BIT)
8285 output_addr_const (file, x);
8288 const char *name = XSTR (x, 0);
8290 /* Mark the decl as referenced so that cgraph will
8291 output the function. */
8292 if (SYMBOL_REF_DECL (x))
8293 mark_decl_referenced (SYMBOL_REF_DECL (x));
8296 if (MACHOPIC_INDIRECT
8297 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
8298 name = machopic_indirection_name (x, /*stub_p=*/true);
8300 assemble_name (file, name);
8302 if (!TARGET_MACHO && !TARGET_64BIT_MS_ABI
8303 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
8304 fputs ("@PLT", file);
8311 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
8312 assemble_name (asm_out_file, buf);
8316 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
8320 /* This used to output parentheses around the expression,
8321 but that does not work on the 386 (either ATT or BSD assembler). */
8322 output_pic_addr_const (file, XEXP (x, 0), code);
8326 if (GET_MODE (x) == VOIDmode)
8328 /* We can use %d if the number is <32 bits and positive. */
8329 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
8330 fprintf (file, "0x%lx%08lx",
8331 (unsigned long) CONST_DOUBLE_HIGH (x),
8332 (unsigned long) CONST_DOUBLE_LOW (x));
8334 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
8337 /* We can't handle floating point constants;
8338 PRINT_OPERAND must handle them. */
8339 output_operand_lossage ("floating constant misused");
8343 /* Some assemblers need integer constants to appear first. */
8344 if (CONST_INT_P (XEXP (x, 0)))
8346 output_pic_addr_const (file, XEXP (x, 0), code);
8348 output_pic_addr_const (file, XEXP (x, 1), code);
8352 gcc_assert (CONST_INT_P (XEXP (x, 1)));
8353 output_pic_addr_const (file, XEXP (x, 1), code);
8355 output_pic_addr_const (file, XEXP (x, 0), code);
8361 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
8362 output_pic_addr_const (file, XEXP (x, 0), code);
8364 output_pic_addr_const (file, XEXP (x, 1), code);
8366 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
8370 gcc_assert (XVECLEN (x, 0) == 1);
8371 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
8372 switch (XINT (x, 1))
8375 fputs ("@GOT", file);
8378 fputs ("@GOTOFF", file);
8381 fputs ("@PLTOFF", file);
8383 case UNSPEC_GOTPCREL:
8384 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8385 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
8387 case UNSPEC_GOTTPOFF:
8388 /* FIXME: This might be @TPOFF in Sun ld too. */
8389 fputs ("@GOTTPOFF", file);
8392 fputs ("@TPOFF", file);
8396 fputs ("@TPOFF", file);
8398 fputs ("@NTPOFF", file);
8401 fputs ("@DTPOFF", file);
8403 case UNSPEC_GOTNTPOFF:
8405 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
8406 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
8408 fputs ("@GOTNTPOFF", file);
8410 case UNSPEC_INDNTPOFF:
8411 fputs ("@INDNTPOFF", file);
8414 output_operand_lossage ("invalid UNSPEC as operand");
8420 output_operand_lossage ("invalid expression as operand");
8424 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8425 We need to emit DTP-relative relocations. */
8427 static void ATTRIBUTE_UNUSED
8428 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
8430 fputs (ASM_LONG, file);
8431 output_addr_const (file, x);
8432 fputs ("@DTPOFF", file);
8438 fputs (", 0", file);
8445 /* In the name of slightly smaller debug output, and to cater to
8446 general assembler lossage, recognize PIC+GOTOFF and turn it back
8447 into a direct symbol reference.
8449 On Darwin, this is necessary to avoid a crash, because Darwin
8450 has a different PIC label for each routine but the DWARF debugging
8451 information is not associated with any particular routine, so it's
8452 necessary to remove references to the PIC label from RTL stored by
8453 the DWARF output code. */
8456 ix86_delegitimize_address (rtx orig_x)
8459 /* reg_addend is NULL or a multiple of some register. */
8460 rtx reg_addend = NULL_RTX;
8461 /* const_addend is NULL or a const_int. */
8462 rtx const_addend = NULL_RTX;
8463 /* This is the result, or NULL. */
8464 rtx result = NULL_RTX;
8471 if (GET_CODE (x) != CONST
8472 || GET_CODE (XEXP (x, 0)) != UNSPEC
8473 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
8476 return XVECEXP (XEXP (x, 0), 0, 0);
8479 if (GET_CODE (x) != PLUS
8480 || GET_CODE (XEXP (x, 1)) != CONST)
8483 if (REG_P (XEXP (x, 0))
8484 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
8485 /* %ebx + GOT/GOTOFF */
8487 else if (GET_CODE (XEXP (x, 0)) == PLUS)
8489 /* %ebx + %reg * scale + GOT/GOTOFF */
8490 reg_addend = XEXP (x, 0);
8491 if (REG_P (XEXP (reg_addend, 0))
8492 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
8493 reg_addend = XEXP (reg_addend, 1);
8494 else if (REG_P (XEXP (reg_addend, 1))
8495 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
8496 reg_addend = XEXP (reg_addend, 0);
8499 if (!REG_P (reg_addend)
8500 && GET_CODE (reg_addend) != MULT
8501 && GET_CODE (reg_addend) != ASHIFT)
8507 x = XEXP (XEXP (x, 1), 0);
8508 if (GET_CODE (x) == PLUS
8509 && CONST_INT_P (XEXP (x, 1)))
8511 const_addend = XEXP (x, 1);
8515 if (GET_CODE (x) == UNSPEC
8516 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
8517 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
8518 result = XVECEXP (x, 0, 0);
8520 if (TARGET_MACHO && darwin_local_data_pic (x)
8522 result = XEXP (x, 0);
8528 result = gen_rtx_PLUS (Pmode, result, const_addend);
8530 result = gen_rtx_PLUS (Pmode, reg_addend, result);
8534 /* If X is a machine specific address (i.e. a symbol or label being
8535 referenced as a displacement from the GOT implemented using an
8536 UNSPEC), then return the base term. Otherwise return X. */
8539 ix86_find_base_term (rtx x)
8545 if (GET_CODE (x) != CONST)
8548 if (GET_CODE (term) == PLUS
8549 && (CONST_INT_P (XEXP (term, 1))
8550 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
8551 term = XEXP (term, 0);
8552 if (GET_CODE (term) != UNSPEC
8553 || XINT (term, 1) != UNSPEC_GOTPCREL)
8556 term = XVECEXP (term, 0, 0);
8558 if (GET_CODE (term) != SYMBOL_REF
8559 && GET_CODE (term) != LABEL_REF)
8565 term = ix86_delegitimize_address (x);
8567 if (GET_CODE (term) != SYMBOL_REF
8568 && GET_CODE (term) != LABEL_REF)
8575 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
8580 if (mode == CCFPmode || mode == CCFPUmode)
8582 enum rtx_code second_code, bypass_code;
8583 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
8584 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
8585 code = ix86_fp_compare_code_to_integer (code);
8589 code = reverse_condition (code);
8640 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
8644 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
8645 Those same assemblers have the same but opposite lossage on cmov. */
8647 suffix = fp ? "nbe" : "a";
8648 else if (mode == CCCmode)
8671 gcc_assert (mode == CCmode || mode == CCCmode);
8693 gcc_assert (mode == CCmode || mode == CCCmode);
8694 suffix = fp ? "nb" : "ae";
8697 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
8704 else if (mode == CCCmode)
8705 suffix = fp ? "nb" : "ae";
8710 suffix = fp ? "u" : "p";
8713 suffix = fp ? "nu" : "np";
8718 fputs (suffix, file);
8721 /* Print the name of register X to FILE based on its machine mode and number.
8722 If CODE is 'w', pretend the mode is HImode.
8723 If CODE is 'b', pretend the mode is QImode.
8724 If CODE is 'k', pretend the mode is SImode.
8725 If CODE is 'q', pretend the mode is DImode.
8726 If CODE is 'h', pretend the reg is the 'high' byte register.
8727 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
8730 print_reg (rtx x, int code, FILE *file)
8732 gcc_assert (x == pc_rtx
8733 || (REGNO (x) != ARG_POINTER_REGNUM
8734 && REGNO (x) != FRAME_POINTER_REGNUM
8735 && REGNO (x) != FLAGS_REG
8736 && REGNO (x) != FPSR_REG
8737 && REGNO (x) != FPCR_REG));
8739 if (ASSEMBLER_DIALECT == ASM_ATT)
8744 gcc_assert (TARGET_64BIT);
8745 fputs ("rip", file);
8749 if (code == 'w' || MMX_REG_P (x))
8751 else if (code == 'b')
8753 else if (code == 'k')
8755 else if (code == 'q')
8757 else if (code == 'y')
8759 else if (code == 'h')
8762 code = GET_MODE_SIZE (GET_MODE (x));
8764 /* Irritatingly, AMD extended registers use different naming convention
8765 from the normal registers. */
8766 if (REX_INT_REG_P (x))
8768 gcc_assert (TARGET_64BIT);
8772 error ("extended registers have no high halves");
8775 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
8778 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
8781 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
8784 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
8787 error ("unsupported operand size for extended register");
8795 if (STACK_TOP_P (x))
8797 fputs ("st(0)", file);
8804 if (! ANY_FP_REG_P (x))
8805 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
8810 fputs (hi_reg_name[REGNO (x)], file);
8813 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
8815 fputs (qi_reg_name[REGNO (x)], file);
8818 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
8820 fputs (qi_high_reg_name[REGNO (x)], file);
8827 /* Locate some local-dynamic symbol still in use by this function
8828 so that we can print its name in some tls_local_dynamic_base
8832 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8836 if (GET_CODE (x) == SYMBOL_REF
8837 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8839 cfun->machine->some_ld_name = XSTR (x, 0);
8847 get_some_local_dynamic_name (void)
8851 if (cfun->machine->some_ld_name)
8852 return cfun->machine->some_ld_name;
8854 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8856 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8857 return cfun->machine->some_ld_name;
8863 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
8864 C -- print opcode suffix for set/cmov insn.
8865 c -- like C, but print reversed condition
8866 F,f -- likewise, but for floating-point.
8867 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
8869 R -- print the prefix for register names.
8870 z -- print the opcode suffix for the size of the current operand.
8871 * -- print a star (in certain assembler syntax)
8872 A -- print an absolute memory reference.
8873 w -- print the operand as if it's a "word" (HImode) even if it isn't.
8874 s -- print a shift double count, followed by the assemblers argument
8876 b -- print the QImode name of the register for the indicated operand.
8877 %b0 would print %al if operands[0] is reg 0.
8878 w -- likewise, print the HImode name of the register.
8879 k -- likewise, print the SImode name of the register.
8880 q -- likewise, print the DImode name of the register.
8881 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
8882 y -- print "st(0)" instead of "st" as a register.
8883 D -- print condition for SSE cmp instruction.
8884 P -- if PIC, print an @PLT suffix.
8885 X -- don't print any sort of PIC '@' suffix for a symbol.
8886 & -- print some in-use local-dynamic symbol name.
8887 H -- print a memory address offset by 8; used for sse high-parts
8888 Y -- print condition for SSE5 com* instruction.
8889 + -- print a branch hint as 'cs' or 'ds' prefix
8890 ; -- print a semicolon (after prefixes due to bug in older gas).
8894 print_operand (FILE *file, rtx x, int code)
8901 if (ASSEMBLER_DIALECT == ASM_ATT)
8906 assemble_name (file, get_some_local_dynamic_name ());
8910 switch (ASSEMBLER_DIALECT)
8917 /* Intel syntax. For absolute addresses, registers should not
8918 be surrounded by braces. */
8922 PRINT_OPERAND (file, x, 0);
8932 PRINT_OPERAND (file, x, 0);
8937 if (ASSEMBLER_DIALECT == ASM_ATT)
8942 if (ASSEMBLER_DIALECT == ASM_ATT)
8947 if (ASSEMBLER_DIALECT == ASM_ATT)
8952 if (ASSEMBLER_DIALECT == ASM_ATT)
8957 if (ASSEMBLER_DIALECT == ASM_ATT)
8962 if (ASSEMBLER_DIALECT == ASM_ATT)
8967 /* 387 opcodes don't get size suffixes if the operands are
8969 if (STACK_REG_P (x))
8972 /* Likewise if using Intel opcodes. */
8973 if (ASSEMBLER_DIALECT == ASM_INTEL)
8976 /* This is the size of op from size of operand. */
8977 switch (GET_MODE_SIZE (GET_MODE (x)))
8986 #ifdef HAVE_GAS_FILDS_FISTS
8996 if (GET_MODE (x) == SFmode)
9011 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
9013 #ifdef GAS_MNEMONICS
9039 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
9041 PRINT_OPERAND (file, x, 0);
9047 /* Little bit of braindamage here. The SSE compare instructions
9048 does use completely different names for the comparisons that the
9049 fp conditional moves. */
9050 switch (GET_CODE (x))
9065 fputs ("unord", file);
9069 fputs ("neq", file);
9073 fputs ("nlt", file);
9077 fputs ("nle", file);
9080 fputs ("ord", file);
9087 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9088 if (ASSEMBLER_DIALECT == ASM_ATT)
9090 switch (GET_MODE (x))
9092 case HImode: putc ('w', file); break;
9094 case SFmode: putc ('l', file); break;
9096 case DFmode: putc ('q', file); break;
9097 default: gcc_unreachable ();
9104 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
9107 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9108 if (ASSEMBLER_DIALECT == ASM_ATT)
9111 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
9114 /* Like above, but reverse condition */
9116 /* Check to see if argument to %c is really a constant
9117 and not a condition code which needs to be reversed. */
9118 if (!COMPARISON_P (x))
9120 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
9123 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
9126 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
9127 if (ASSEMBLER_DIALECT == ASM_ATT)
9130 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
9134 /* It doesn't actually matter what mode we use here, as we're
9135 only going to use this for printing. */
9136 x = adjust_address_nv (x, DImode, 8);
9143 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
9146 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
9149 int pred_val = INTVAL (XEXP (x, 0));
9151 if (pred_val < REG_BR_PROB_BASE * 45 / 100
9152 || pred_val > REG_BR_PROB_BASE * 55 / 100)
9154 int taken = pred_val > REG_BR_PROB_BASE / 2;
9155 int cputaken = final_forward_branch_p (current_output_insn) == 0;
9157 /* Emit hints only in the case default branch prediction
9158 heuristics would fail. */
9159 if (taken != cputaken)
9161 /* We use 3e (DS) prefix for taken branches and
9162 2e (CS) prefix for not taken branches. */
9164 fputs ("ds ; ", file);
9166 fputs ("cs ; ", file);
9174 switch (GET_CODE (x))
9177 fputs ("neq", file);
9184 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
9188 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
9199 fputs ("unord", file);
9202 fputs ("ord", file);
9205 fputs ("ueq", file);
9208 fputs ("nlt", file);
9211 fputs ("nle", file);
9214 fputs ("ule", file);
9217 fputs ("ult", file);
9220 fputs ("une", file);
9229 fputs (" ; ", file);
9236 output_operand_lossage ("invalid operand code '%c'", code);
9241 print_reg (x, code, file);
9245 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
9246 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
9247 && GET_MODE (x) != BLKmode)
9250 switch (GET_MODE_SIZE (GET_MODE (x)))
9252 case 1: size = "BYTE"; break;
9253 case 2: size = "WORD"; break;
9254 case 4: size = "DWORD"; break;
9255 case 8: size = "QWORD"; break;
9256 case 12: size = "XWORD"; break;
9258 if (GET_MODE (x) == XFmode)
9267 /* Check for explicit size override (codes 'b', 'w' and 'k') */
9270 else if (code == 'w')
9272 else if (code == 'k')
9276 fputs (" PTR ", file);
9280 /* Avoid (%rip) for call operands. */
9281 if (CONSTANT_ADDRESS_P (x) && code == 'P'
9282 && !CONST_INT_P (x))
9283 output_addr_const (file, x);
9284 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
9285 output_operand_lossage ("invalid constraints for operand");
9290 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
9295 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9296 REAL_VALUE_TO_TARGET_SINGLE (r, l);
9298 if (ASSEMBLER_DIALECT == ASM_ATT)
9300 fprintf (file, "0x%08lx", (long unsigned int) l);
9303 /* These float cases don't actually occur as immediate operands. */
9304 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
9308 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9309 fprintf (file, "%s", dstr);
9312 else if (GET_CODE (x) == CONST_DOUBLE
9313 && GET_MODE (x) == XFmode)
9317 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
9318 fprintf (file, "%s", dstr);
9323 /* We have patterns that allow zero sets of memory, for instance.
9324 In 64-bit mode, we should probably support all 8-byte vectors,
9325 since we can in fact encode that into an immediate. */
9326 if (GET_CODE (x) == CONST_VECTOR)
9328 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
9334 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
9336 if (ASSEMBLER_DIALECT == ASM_ATT)
9339 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
9340 || GET_CODE (x) == LABEL_REF)
9342 if (ASSEMBLER_DIALECT == ASM_ATT)
9345 fputs ("OFFSET FLAT:", file);
9348 if (CONST_INT_P (x))
9349 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
9351 output_pic_addr_const (file, x, code);
9353 output_addr_const (file, x);
9357 /* Print a memory operand whose address is ADDR. */
9360 print_operand_address (FILE *file, rtx addr)
9362 struct ix86_address parts;
9363 rtx base, index, disp;
9365 int ok = ix86_decompose_address (addr, &parts);
9370 index = parts.index;
9372 scale = parts.scale;
9380 if (ASSEMBLER_DIALECT == ASM_ATT)
9382 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
9388 /* Use one byte shorter RIP relative addressing for 64bit mode. */
9389 if (TARGET_64BIT && !base && !index)
9393 if (GET_CODE (disp) == CONST
9394 && GET_CODE (XEXP (disp, 0)) == PLUS
9395 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9396 symbol = XEXP (XEXP (disp, 0), 0);
9398 if (GET_CODE (symbol) == LABEL_REF
9399 || (GET_CODE (symbol) == SYMBOL_REF
9400 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
9403 if (!base && !index)
9405 /* Displacement only requires special attention. */
9407 if (CONST_INT_P (disp))
9409 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
9410 fputs ("ds:", file);
9411 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
9414 output_pic_addr_const (file, disp, 0);
9416 output_addr_const (file, disp);
9420 if (ASSEMBLER_DIALECT == ASM_ATT)
9425 output_pic_addr_const (file, disp, 0);
9426 else if (GET_CODE (disp) == LABEL_REF)
9427 output_asm_label (disp);
9429 output_addr_const (file, disp);
9434 print_reg (base, 0, file);
9438 print_reg (index, 0, file);
9440 fprintf (file, ",%d", scale);
9446 rtx offset = NULL_RTX;
9450 /* Pull out the offset of a symbol; print any symbol itself. */
9451 if (GET_CODE (disp) == CONST
9452 && GET_CODE (XEXP (disp, 0)) == PLUS
9453 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
9455 offset = XEXP (XEXP (disp, 0), 1);
9456 disp = gen_rtx_CONST (VOIDmode,
9457 XEXP (XEXP (disp, 0), 0));
9461 output_pic_addr_const (file, disp, 0);
9462 else if (GET_CODE (disp) == LABEL_REF)
9463 output_asm_label (disp);
9464 else if (CONST_INT_P (disp))
9467 output_addr_const (file, disp);
9473 print_reg (base, 0, file);
9476 if (INTVAL (offset) >= 0)
9478 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9482 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
9489 print_reg (index, 0, file);
9491 fprintf (file, "*%d", scale);
9499 output_addr_const_extra (FILE *file, rtx x)
9503 if (GET_CODE (x) != UNSPEC)
9506 op = XVECEXP (x, 0, 0);
9507 switch (XINT (x, 1))
9509 case UNSPEC_GOTTPOFF:
9510 output_addr_const (file, op);
9511 /* FIXME: This might be @TPOFF in Sun ld. */
9512 fputs ("@GOTTPOFF", file);
9515 output_addr_const (file, op);
9516 fputs ("@TPOFF", file);
9519 output_addr_const (file, op);
9521 fputs ("@TPOFF", file);
9523 fputs ("@NTPOFF", file);
9526 output_addr_const (file, op);
9527 fputs ("@DTPOFF", file);
9529 case UNSPEC_GOTNTPOFF:
9530 output_addr_const (file, op);
9532 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
9533 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
9535 fputs ("@GOTNTPOFF", file);
9537 case UNSPEC_INDNTPOFF:
9538 output_addr_const (file, op);
9539 fputs ("@INDNTPOFF", file);
9549 /* Split one or more DImode RTL references into pairs of SImode
9550 references. The RTL can be REG, offsettable MEM, integer constant, or
9551 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9552 split and "num" is its length. lo_half and hi_half are output arrays
9553 that parallel "operands". */
9556 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9560 rtx op = operands[num];
9562 /* simplify_subreg refuse to split volatile memory addresses,
9563 but we still have to handle it. */
9566 lo_half[num] = adjust_address (op, SImode, 0);
9567 hi_half[num] = adjust_address (op, SImode, 4);
9571 lo_half[num] = simplify_gen_subreg (SImode, op,
9572 GET_MODE (op) == VOIDmode
9573 ? DImode : GET_MODE (op), 0);
9574 hi_half[num] = simplify_gen_subreg (SImode, op,
9575 GET_MODE (op) == VOIDmode
9576 ? DImode : GET_MODE (op), 4);
9580 /* Split one or more TImode RTL references into pairs of DImode
9581 references. The RTL can be REG, offsettable MEM, integer constant, or
9582 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
9583 split and "num" is its length. lo_half and hi_half are output arrays
9584 that parallel "operands". */
9587 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
9591 rtx op = operands[num];
9593 /* simplify_subreg refuse to split volatile memory addresses, but we
9594 still have to handle it. */
9597 lo_half[num] = adjust_address (op, DImode, 0);
9598 hi_half[num] = adjust_address (op, DImode, 8);
9602 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
9603 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
9608 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
9609 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
9610 is the expression of the binary operation. The output may either be
9611 emitted here, or returned to the caller, like all output_* functions.
9613 There is no guarantee that the operands are the same mode, as they
9614 might be within FLOAT or FLOAT_EXTEND expressions. */
9616 #ifndef SYSV386_COMPAT
9617 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
9618 wants to fix the assemblers because that causes incompatibility
9619 with gcc. No-one wants to fix gcc because that causes
9620 incompatibility with assemblers... You can use the option of
9621 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
9622 #define SYSV386_COMPAT 1
9626 output_387_binary_op (rtx insn, rtx *operands)
9628 static char buf[30];
9631 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
9633 #ifdef ENABLE_CHECKING
9634 /* Even if we do not want to check the inputs, this documents input
9635 constraints. Which helps in understanding the following code. */
9636 if (STACK_REG_P (operands[0])
9637 && ((REG_P (operands[1])
9638 && REGNO (operands[0]) == REGNO (operands[1])
9639 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
9640 || (REG_P (operands[2])
9641 && REGNO (operands[0]) == REGNO (operands[2])
9642 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
9643 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
9646 gcc_assert (is_sse);
9649 switch (GET_CODE (operands[3]))
9652 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9653 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9661 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9662 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9670 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9671 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9679 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9680 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9694 if (GET_MODE (operands[0]) == SFmode)
9695 strcat (buf, "ss\t{%2, %0|%0, %2}");
9697 strcat (buf, "sd\t{%2, %0|%0, %2}");
9702 switch (GET_CODE (operands[3]))
9706 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
9708 rtx temp = operands[2];
9709 operands[2] = operands[1];
9713 /* know operands[0] == operands[1]. */
9715 if (MEM_P (operands[2]))
9721 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9723 if (STACK_TOP_P (operands[0]))
9724 /* How is it that we are storing to a dead operand[2]?
9725 Well, presumably operands[1] is dead too. We can't
9726 store the result to st(0) as st(0) gets popped on this
9727 instruction. Instead store to operands[2] (which I
9728 think has to be st(1)). st(1) will be popped later.
9729 gcc <= 2.8.1 didn't have this check and generated
9730 assembly code that the Unixware assembler rejected. */
9731 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9733 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9737 if (STACK_TOP_P (operands[0]))
9738 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9740 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9745 if (MEM_P (operands[1]))
9751 if (MEM_P (operands[2]))
9757 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9760 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
9761 derived assemblers, confusingly reverse the direction of
9762 the operation for fsub{r} and fdiv{r} when the
9763 destination register is not st(0). The Intel assembler
9764 doesn't have this brain damage. Read !SYSV386_COMPAT to
9765 figure out what the hardware really does. */
9766 if (STACK_TOP_P (operands[0]))
9767 p = "{p\t%0, %2|rp\t%2, %0}";
9769 p = "{rp\t%2, %0|p\t%0, %2}";
9771 if (STACK_TOP_P (operands[0]))
9772 /* As above for fmul/fadd, we can't store to st(0). */
9773 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9775 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9780 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
9783 if (STACK_TOP_P (operands[0]))
9784 p = "{rp\t%0, %1|p\t%1, %0}";
9786 p = "{p\t%1, %0|rp\t%0, %1}";
9788 if (STACK_TOP_P (operands[0]))
9789 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
9791 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
9796 if (STACK_TOP_P (operands[0]))
9798 if (STACK_TOP_P (operands[1]))
9799 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9801 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
9804 else if (STACK_TOP_P (operands[1]))
9807 p = "{\t%1, %0|r\t%0, %1}";
9809 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
9815 p = "{r\t%2, %0|\t%0, %2}";
9817 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9830 /* Return needed mode for entity in optimize_mode_switching pass. */
9833 ix86_mode_needed (int entity, rtx insn)
9835 enum attr_i387_cw mode;
9837 /* The mode UNINITIALIZED is used to store control word after a
9838 function call or ASM pattern. The mode ANY specify that function
9839 has no requirements on the control word and make no changes in the
9840 bits we are interested in. */
9843 || (NONJUMP_INSN_P (insn)
9844 && (asm_noperands (PATTERN (insn)) >= 0
9845 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
9846 return I387_CW_UNINITIALIZED;
9848 if (recog_memoized (insn) < 0)
9851 mode = get_attr_i387_cw (insn);
9856 if (mode == I387_CW_TRUNC)
9861 if (mode == I387_CW_FLOOR)
9866 if (mode == I387_CW_CEIL)
9871 if (mode == I387_CW_MASK_PM)
9882 /* Output code to initialize control word copies used by trunc?f?i and
9883 rounding patterns. CURRENT_MODE is set to current control word,
9884 while NEW_MODE is set to new control word. */
9887 emit_i387_cw_initialization (int mode)
9889 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
9892 enum ix86_stack_slot slot;
9894 rtx reg = gen_reg_rtx (HImode);
9896 emit_insn (gen_x86_fnstcw_1 (stored_mode));
9897 emit_move_insn (reg, copy_rtx (stored_mode));
9899 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
9904 /* round toward zero (truncate) */
9905 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
9906 slot = SLOT_CW_TRUNC;
9910 /* round down toward -oo */
9911 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9912 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
9913 slot = SLOT_CW_FLOOR;
9917 /* round up toward +oo */
9918 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9919 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
9920 slot = SLOT_CW_CEIL;
9923 case I387_CW_MASK_PM:
9924 /* mask precision exception for nearbyint() */
9925 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9926 slot = SLOT_CW_MASK_PM;
9938 /* round toward zero (truncate) */
9939 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
9940 slot = SLOT_CW_TRUNC;
9944 /* round down toward -oo */
9945 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
9946 slot = SLOT_CW_FLOOR;
9950 /* round up toward +oo */
9951 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
9952 slot = SLOT_CW_CEIL;
9955 case I387_CW_MASK_PM:
9956 /* mask precision exception for nearbyint() */
9957 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9958 slot = SLOT_CW_MASK_PM;
9966 gcc_assert (slot < MAX_386_STACK_LOCALS);
9968 new_mode = assign_386_stack_local (HImode, slot);
9969 emit_move_insn (new_mode, reg);
9972 /* Output code for INSN to convert a float to a signed int. OPERANDS
9973 are the insn operands. The output may be [HSD]Imode and the input
9974 operand may be [SDX]Fmode. */
9977 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
9979 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9980 int dimode_p = GET_MODE (operands[0]) == DImode;
9981 int round_mode = get_attr_i387_cw (insn);
9983 /* Jump through a hoop or two for DImode, since the hardware has no
9984 non-popping instruction. We used to do this a different way, but
9985 that was somewhat fragile and broke with post-reload splitters. */
9986 if ((dimode_p || fisttp) && !stack_top_dies)
9987 output_asm_insn ("fld\t%y1", operands);
9989 gcc_assert (STACK_TOP_P (operands[1]));
9990 gcc_assert (MEM_P (operands[0]));
9991 gcc_assert (GET_MODE (operands[1]) != TFmode);
9994 output_asm_insn ("fisttp%z0\t%0", operands);
9997 if (round_mode != I387_CW_ANY)
9998 output_asm_insn ("fldcw\t%3", operands);
9999 if (stack_top_dies || dimode_p)
10000 output_asm_insn ("fistp%z0\t%0", operands);
10002 output_asm_insn ("fist%z0\t%0", operands);
10003 if (round_mode != I387_CW_ANY)
10004 output_asm_insn ("fldcw\t%2", operands);
10010 /* Output code for x87 ffreep insn. The OPNO argument, which may only
10011 have the values zero or one, indicates the ffreep insn's operand
10012 from the OPERANDS array. */
10014 static const char *
10015 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
10017 if (TARGET_USE_FFREEP)
10018 #if HAVE_AS_IX86_FFREEP
10019 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
10022 static char retval[] = ".word\t0xc_df";
10023 int regno = REGNO (operands[opno]);
10025 gcc_assert (FP_REGNO_P (regno));
10027 retval[9] = '0' + (regno - FIRST_STACK_REG);
10032 return opno ? "fstp\t%y1" : "fstp\t%y0";
10036 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
10037 should be used. UNORDERED_P is true when fucom should be used. */
10040 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
10042 int stack_top_dies;
10043 rtx cmp_op0, cmp_op1;
10044 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
10048 cmp_op0 = operands[0];
10049 cmp_op1 = operands[1];
10053 cmp_op0 = operands[1];
10054 cmp_op1 = operands[2];
10059 if (GET_MODE (operands[0]) == SFmode)
10061 return "ucomiss\t{%1, %0|%0, %1}";
10063 return "comiss\t{%1, %0|%0, %1}";
10066 return "ucomisd\t{%1, %0|%0, %1}";
10068 return "comisd\t{%1, %0|%0, %1}";
10071 gcc_assert (STACK_TOP_P (cmp_op0));
10073 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
10075 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
10077 if (stack_top_dies)
10079 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
10080 return output_387_ffreep (operands, 1);
10083 return "ftst\n\tfnstsw\t%0";
10086 if (STACK_REG_P (cmp_op1)
10088 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
10089 && REGNO (cmp_op1) != FIRST_STACK_REG)
10091 /* If both the top of the 387 stack dies, and the other operand
10092 is also a stack register that dies, then this must be a
10093 `fcompp' float compare */
10097 /* There is no double popping fcomi variant. Fortunately,
10098 eflags is immune from the fstp's cc clobbering. */
10100 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
10102 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
10103 return output_387_ffreep (operands, 0);
10108 return "fucompp\n\tfnstsw\t%0";
10110 return "fcompp\n\tfnstsw\t%0";
10115 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
10117 static const char * const alt[16] =
10119 "fcom%z2\t%y2\n\tfnstsw\t%0",
10120 "fcomp%z2\t%y2\n\tfnstsw\t%0",
10121 "fucom%z2\t%y2\n\tfnstsw\t%0",
10122 "fucomp%z2\t%y2\n\tfnstsw\t%0",
10124 "ficom%z2\t%y2\n\tfnstsw\t%0",
10125 "ficomp%z2\t%y2\n\tfnstsw\t%0",
10129 "fcomi\t{%y1, %0|%0, %y1}",
10130 "fcomip\t{%y1, %0|%0, %y1}",
10131 "fucomi\t{%y1, %0|%0, %y1}",
10132 "fucomip\t{%y1, %0|%0, %y1}",
10143 mask = eflags_p << 3;
10144 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
10145 mask |= unordered_p << 1;
10146 mask |= stack_top_dies;
10148 gcc_assert (mask < 16);
10157 ix86_output_addr_vec_elt (FILE *file, int value)
10159 const char *directive = ASM_LONG;
10163 directive = ASM_QUAD;
10165 gcc_assert (!TARGET_64BIT);
10168 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
10172 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
10174 const char *directive = ASM_LONG;
10177 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
10178 directive = ASM_QUAD;
10180 gcc_assert (!TARGET_64BIT);
10182 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
10183 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
10184 fprintf (file, "%s%s%d-%s%d\n",
10185 directive, LPREFIX, value, LPREFIX, rel);
10186 else if (HAVE_AS_GOTOFF_IN_DATA)
10187 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
10189 else if (TARGET_MACHO)
10191 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
10192 machopic_output_function_base_name (file);
10193 fprintf(file, "\n");
10197 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
10198 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
10201 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
10205 ix86_expand_clear (rtx dest)
10209 /* We play register width games, which are only valid after reload. */
10210 gcc_assert (reload_completed);
10212 /* Avoid HImode and its attendant prefix byte. */
10213 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
10214 dest = gen_rtx_REG (SImode, REGNO (dest));
10215 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
10217 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
10218 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
10220 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10221 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
10227 /* X is an unchanging MEM. If it is a constant pool reference, return
10228 the constant pool rtx, else NULL. */
10231 maybe_get_pool_constant (rtx x)
10233 x = ix86_delegitimize_address (XEXP (x, 0));
10235 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
10236 return get_pool_constant (x);
10242 ix86_expand_move (enum machine_mode mode, rtx operands[])
10245 enum tls_model model;
10250 if (GET_CODE (op1) == SYMBOL_REF)
10252 model = SYMBOL_REF_TLS_MODEL (op1);
10255 op1 = legitimize_tls_address (op1, model, true);
10256 op1 = force_operand (op1, op0);
10260 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10261 && SYMBOL_REF_DLLIMPORT_P (op1))
10262 op1 = legitimize_dllimport_symbol (op1, false);
10264 else if (GET_CODE (op1) == CONST
10265 && GET_CODE (XEXP (op1, 0)) == PLUS
10266 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
10268 rtx addend = XEXP (XEXP (op1, 0), 1);
10269 rtx symbol = XEXP (XEXP (op1, 0), 0);
10272 model = SYMBOL_REF_TLS_MODEL (symbol);
10274 tmp = legitimize_tls_address (symbol, model, true);
10275 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
10276 && SYMBOL_REF_DLLIMPORT_P (symbol))
10277 tmp = legitimize_dllimport_symbol (symbol, true);
10281 tmp = force_operand (tmp, NULL);
10282 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
10283 op0, 1, OPTAB_DIRECT);
10289 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
10291 if (TARGET_MACHO && !TARGET_64BIT)
10296 rtx temp = ((reload_in_progress
10297 || ((op0 && REG_P (op0))
10299 ? op0 : gen_reg_rtx (Pmode));
10300 op1 = machopic_indirect_data_reference (op1, temp);
10301 op1 = machopic_legitimize_pic_address (op1, mode,
10302 temp == op1 ? 0 : temp);
10304 else if (MACHOPIC_INDIRECT)
10305 op1 = machopic_indirect_data_reference (op1, 0);
10313 op1 = force_reg (Pmode, op1);
10314 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
10316 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
10317 op1 = legitimize_pic_address (op1, reg);
10326 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
10327 || !push_operand (op0, mode))
10329 op1 = force_reg (mode, op1);
10331 if (push_operand (op0, mode)
10332 && ! general_no_elim_operand (op1, mode))
10333 op1 = copy_to_mode_reg (mode, op1);
10335 /* Force large constants in 64bit compilation into register
10336 to get them CSEed. */
10337 if (can_create_pseudo_p ()
10338 && (mode == DImode) && TARGET_64BIT
10339 && immediate_operand (op1, mode)
10340 && !x86_64_zext_immediate_operand (op1, VOIDmode)
10341 && !register_operand (op0, mode)
10343 op1 = copy_to_mode_reg (mode, op1);
10345 if (can_create_pseudo_p ()
10346 && FLOAT_MODE_P (mode)
10347 && GET_CODE (op1) == CONST_DOUBLE)
10349 /* If we are loading a floating point constant to a register,
10350 force the value to memory now, since we'll get better code
10351 out the back end. */
10353 op1 = validize_mem (force_const_mem (mode, op1));
10354 if (!register_operand (op0, mode))
10356 rtx temp = gen_reg_rtx (mode);
10357 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
10358 emit_move_insn (op0, temp);
10364 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10368 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
10370 rtx op0 = operands[0], op1 = operands[1];
10371 unsigned int align = GET_MODE_ALIGNMENT (mode);
10373 /* Force constants other than zero into memory. We do not know how
10374 the instructions used to build constants modify the upper 64 bits
10375 of the register, once we have that information we may be able
10376 to handle some of them more efficiently. */
10377 if (can_create_pseudo_p ()
10378 && register_operand (op0, mode)
10379 && (CONSTANT_P (op1)
10380 || (GET_CODE (op1) == SUBREG
10381 && CONSTANT_P (SUBREG_REG (op1))))
10382 && standard_sse_constant_p (op1) <= 0)
10383 op1 = validize_mem (force_const_mem (mode, op1));
10385 /* TDmode values are passed as TImode on the stack. TImode values
10386 are moved via xmm registers, and moving them to stack can result in
10387 unaligned memory access. Use ix86_expand_vector_move_misalign()
10388 if memory operand is not aligned correctly. */
10389 if (can_create_pseudo_p ()
10390 && (mode == TImode) && !TARGET_64BIT
10391 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
10392 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
10396 /* ix86_expand_vector_move_misalign() does not like constants ... */
10397 if (CONSTANT_P (op1)
10398 || (GET_CODE (op1) == SUBREG
10399 && CONSTANT_P (SUBREG_REG (op1))))
10400 op1 = validize_mem (force_const_mem (mode, op1));
10402 /* ... nor both arguments in memory. */
10403 if (!register_operand (op0, mode)
10404 && !register_operand (op1, mode))
10405 op1 = force_reg (mode, op1);
10407 tmp[0] = op0; tmp[1] = op1;
10408 ix86_expand_vector_move_misalign (mode, tmp);
10412 /* Make operand1 a register if it isn't already. */
10413 if (can_create_pseudo_p ()
10414 && !register_operand (op0, mode)
10415 && !register_operand (op1, mode))
10417 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
10421 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
10424 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
10425 straight to ix86_expand_vector_move. */
10426 /* Code generation for scalar reg-reg moves of single and double precision data:
10427 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
10431 if (x86_sse_partial_reg_dependency == true)
10436 Code generation for scalar loads of double precision data:
10437 if (x86_sse_split_regs == true)
10438 movlpd mem, reg (gas syntax)
10442 Code generation for unaligned packed loads of single precision data
10443 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
10444 if (x86_sse_unaligned_move_optimal)
10447 if (x86_sse_partial_reg_dependency == true)
10459 Code generation for unaligned packed loads of double precision data
10460 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
10461 if (x86_sse_unaligned_move_optimal)
10464 if (x86_sse_split_regs == true)
10477 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
10486 /* If we're optimizing for size, movups is the smallest. */
10489 op0 = gen_lowpart (V4SFmode, op0);
10490 op1 = gen_lowpart (V4SFmode, op1);
10491 emit_insn (gen_sse_movups (op0, op1));
10495 /* ??? If we have typed data, then it would appear that using
10496 movdqu is the only way to get unaligned data loaded with
10498 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10500 op0 = gen_lowpart (V16QImode, op0);
10501 op1 = gen_lowpart (V16QImode, op1);
10502 emit_insn (gen_sse2_movdqu (op0, op1));
10506 if (TARGET_SSE2 && mode == V2DFmode)
10510 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10512 op0 = gen_lowpart (V2DFmode, op0);
10513 op1 = gen_lowpart (V2DFmode, op1);
10514 emit_insn (gen_sse2_movupd (op0, op1));
10518 /* When SSE registers are split into halves, we can avoid
10519 writing to the top half twice. */
10520 if (TARGET_SSE_SPLIT_REGS)
10522 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10527 /* ??? Not sure about the best option for the Intel chips.
10528 The following would seem to satisfy; the register is
10529 entirely cleared, breaking the dependency chain. We
10530 then store to the upper half, with a dependency depth
10531 of one. A rumor has it that Intel recommends two movsd
10532 followed by an unpacklpd, but this is unconfirmed. And
10533 given that the dependency depth of the unpacklpd would
10534 still be one, I'm not sure why this would be better. */
10535 zero = CONST0_RTX (V2DFmode);
10538 m = adjust_address (op1, DFmode, 0);
10539 emit_insn (gen_sse2_loadlpd (op0, zero, m));
10540 m = adjust_address (op1, DFmode, 8);
10541 emit_insn (gen_sse2_loadhpd (op0, op0, m));
10545 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
10547 op0 = gen_lowpart (V4SFmode, op0);
10548 op1 = gen_lowpart (V4SFmode, op1);
10549 emit_insn (gen_sse_movups (op0, op1));
10553 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
10554 emit_move_insn (op0, CONST0_RTX (mode));
10556 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
10558 if (mode != V4SFmode)
10559 op0 = gen_lowpart (V4SFmode, op0);
10560 m = adjust_address (op1, V2SFmode, 0);
10561 emit_insn (gen_sse_loadlps (op0, op0, m));
10562 m = adjust_address (op1, V2SFmode, 8);
10563 emit_insn (gen_sse_loadhps (op0, op0, m));
10566 else if (MEM_P (op0))
10568 /* If we're optimizing for size, movups is the smallest. */
10571 op0 = gen_lowpart (V4SFmode, op0);
10572 op1 = gen_lowpart (V4SFmode, op1);
10573 emit_insn (gen_sse_movups (op0, op1));
10577 /* ??? Similar to above, only less clear because of quote
10578 typeless stores unquote. */
10579 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
10580 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
10582 op0 = gen_lowpart (V16QImode, op0);
10583 op1 = gen_lowpart (V16QImode, op1);
10584 emit_insn (gen_sse2_movdqu (op0, op1));
10588 if (TARGET_SSE2 && mode == V2DFmode)
10590 m = adjust_address (op0, DFmode, 0);
10591 emit_insn (gen_sse2_storelpd (m, op1));
10592 m = adjust_address (op0, DFmode, 8);
10593 emit_insn (gen_sse2_storehpd (m, op1));
10597 if (mode != V4SFmode)
10598 op1 = gen_lowpart (V4SFmode, op1);
10599 m = adjust_address (op0, V2SFmode, 0);
10600 emit_insn (gen_sse_storelps (m, op1));
10601 m = adjust_address (op0, V2SFmode, 8);
10602 emit_insn (gen_sse_storehps (m, op1));
10606 gcc_unreachable ();
10609 /* Expand a push in MODE. This is some mode for which we do not support
10610 proper push instructions, at least from the registers that we expect
10611 the value to live in. */
10614 ix86_expand_push (enum machine_mode mode, rtx x)
10618 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
10619 GEN_INT (-GET_MODE_SIZE (mode)),
10620 stack_pointer_rtx, 1, OPTAB_DIRECT);
10621 if (tmp != stack_pointer_rtx)
10622 emit_move_insn (stack_pointer_rtx, tmp);
10624 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
10625 emit_move_insn (tmp, x);
10628 /* Helper function of ix86_fixup_binary_operands to canonicalize
10629 operand order. Returns true if the operands should be swapped. */
10632 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
10635 rtx dst = operands[0];
10636 rtx src1 = operands[1];
10637 rtx src2 = operands[2];
10639 /* If the operation is not commutative, we can't do anything. */
10640 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
10643 /* Highest priority is that src1 should match dst. */
10644 if (rtx_equal_p (dst, src1))
10646 if (rtx_equal_p (dst, src2))
10649 /* Next highest priority is that immediate constants come second. */
10650 if (immediate_operand (src2, mode))
10652 if (immediate_operand (src1, mode))
10655 /* Lowest priority is that memory references should come second. */
10665 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
10666 destination to use for the operation. If different from the true
10667 destination in operands[0], a copy operation will be required. */
10670 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
10673 rtx dst = operands[0];
10674 rtx src1 = operands[1];
10675 rtx src2 = operands[2];
10677 /* Canonicalize operand order. */
10678 if (ix86_swap_binary_operands_p (code, mode, operands))
10685 /* Both source operands cannot be in memory. */
10686 if (MEM_P (src1) && MEM_P (src2))
10688 /* Optimization: Only read from memory once. */
10689 if (rtx_equal_p (src1, src2))
10691 src2 = force_reg (mode, src2);
10695 src2 = force_reg (mode, src2);
10698 /* If the destination is memory, and we do not have matching source
10699 operands, do things in registers. */
10700 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10701 dst = gen_reg_rtx (mode);
10703 /* Source 1 cannot be a constant. */
10704 if (CONSTANT_P (src1))
10705 src1 = force_reg (mode, src1);
10707 /* Source 1 cannot be a non-matching memory. */
10708 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10709 src1 = force_reg (mode, src1);
10711 operands[1] = src1;
10712 operands[2] = src2;
10716 /* Similarly, but assume that the destination has already been
10717 set up properly. */
10720 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
10721 enum machine_mode mode, rtx operands[])
10723 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
10724 gcc_assert (dst == operands[0]);
10727 /* Attempt to expand a binary operator. Make the expansion closer to the
10728 actual machine, then just general_operand, which will allow 3 separate
10729 memory references (one output, two input) in a single insn. */
10732 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
10735 rtx src1, src2, dst, op, clob;
10737 dst = ix86_fixup_binary_operands (code, mode, operands);
10738 src1 = operands[1];
10739 src2 = operands[2];
10741 /* Emit the instruction. */
10743 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
10744 if (reload_in_progress)
10746 /* Reload doesn't know about the flags register, and doesn't know that
10747 it doesn't want to clobber it. We can only do this with PLUS. */
10748 gcc_assert (code == PLUS);
10753 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10754 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10757 /* Fix up the destination if needed. */
10758 if (dst != operands[0])
10759 emit_move_insn (operands[0], dst);
10762 /* Return TRUE or FALSE depending on whether the binary operator meets the
10763 appropriate constraints. */
10766 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
10769 rtx dst = operands[0];
10770 rtx src1 = operands[1];
10771 rtx src2 = operands[2];
10773 /* Both source operands cannot be in memory. */
10774 if (MEM_P (src1) && MEM_P (src2))
10777 /* Canonicalize operand order for commutative operators. */
10778 if (ix86_swap_binary_operands_p (code, mode, operands))
10785 /* If the destination is memory, we must have a matching source operand. */
10786 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10789 /* Source 1 cannot be a constant. */
10790 if (CONSTANT_P (src1))
10793 /* Source 1 cannot be a non-matching memory. */
10794 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10800 /* Attempt to expand a unary operator. Make the expansion closer to the
10801 actual machine, then just general_operand, which will allow 2 separate
10802 memory references (one output, one input) in a single insn. */
10805 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
10808 int matching_memory;
10809 rtx src, dst, op, clob;
10814 /* If the destination is memory, and we do not have matching source
10815 operands, do things in registers. */
10816 matching_memory = 0;
10819 if (rtx_equal_p (dst, src))
10820 matching_memory = 1;
10822 dst = gen_reg_rtx (mode);
10825 /* When source operand is memory, destination must match. */
10826 if (MEM_P (src) && !matching_memory)
10827 src = force_reg (mode, src);
10829 /* Emit the instruction. */
10831 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
10832 if (reload_in_progress || code == NOT)
10834 /* Reload doesn't know about the flags register, and doesn't know that
10835 it doesn't want to clobber it. */
10836 gcc_assert (code == NOT);
10841 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10842 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10845 /* Fix up the destination if needed. */
10846 if (dst != operands[0])
10847 emit_move_insn (operands[0], dst);
10850 /* Return TRUE or FALSE depending on whether the unary operator meets the
10851 appropriate constraints. */
10854 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
10855 enum machine_mode mode ATTRIBUTE_UNUSED,
10856 rtx operands[2] ATTRIBUTE_UNUSED)
10858 /* If one of operands is memory, source and destination must match. */
10859 if ((MEM_P (operands[0])
10860 || MEM_P (operands[1]))
10861 && ! rtx_equal_p (operands[0], operands[1]))
10866 /* Post-reload splitter for converting an SF or DFmode value in an
10867 SSE register into an unsigned SImode. */
10870 ix86_split_convert_uns_si_sse (rtx operands[])
10872 enum machine_mode vecmode;
10873 rtx value, large, zero_or_two31, input, two31, x;
10875 large = operands[1];
10876 zero_or_two31 = operands[2];
10877 input = operands[3];
10878 two31 = operands[4];
10879 vecmode = GET_MODE (large);
10880 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
10882 /* Load up the value into the low element. We must ensure that the other
10883 elements are valid floats -- zero is the easiest such value. */
10886 if (vecmode == V4SFmode)
10887 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
10889 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
10893 input = gen_rtx_REG (vecmode, REGNO (input));
10894 emit_move_insn (value, CONST0_RTX (vecmode));
10895 if (vecmode == V4SFmode)
10896 emit_insn (gen_sse_movss (value, value, input));
10898 emit_insn (gen_sse2_movsd (value, value, input));
10901 emit_move_insn (large, two31);
10902 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
10904 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
10905 emit_insn (gen_rtx_SET (VOIDmode, large, x));
10907 x = gen_rtx_AND (vecmode, zero_or_two31, large);
10908 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
10910 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
10911 emit_insn (gen_rtx_SET (VOIDmode, value, x));
10913 large = gen_rtx_REG (V4SImode, REGNO (large));
10914 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
10916 x = gen_rtx_REG (V4SImode, REGNO (value));
10917 if (vecmode == V4SFmode)
10918 emit_insn (gen_sse2_cvttps2dq (x, value));
10920 emit_insn (gen_sse2_cvttpd2dq (x, value));
10923 emit_insn (gen_xorv4si3 (value, value, large));
10926 /* Convert an unsigned DImode value into a DFmode, using only SSE.
10927 Expects the 64-bit DImode to be supplied in a pair of integral
10928 registers. Requires SSE2; will use SSE3 if available. For x86_32,
10929 -mfpmath=sse, !optimize_size only. */
10932 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
10934 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
10935 rtx int_xmm, fp_xmm;
10936 rtx biases, exponents;
10939 int_xmm = gen_reg_rtx (V4SImode);
10940 if (TARGET_INTER_UNIT_MOVES)
10941 emit_insn (gen_movdi_to_sse (int_xmm, input));
10942 else if (TARGET_SSE_SPLIT_REGS)
10944 emit_insn (gen_rtx_CLOBBER (VOIDmode, int_xmm));
10945 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
10949 x = gen_reg_rtx (V2DImode);
10950 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
10951 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
10954 x = gen_rtx_CONST_VECTOR (V4SImode,
10955 gen_rtvec (4, GEN_INT (0x43300000UL),
10956 GEN_INT (0x45300000UL),
10957 const0_rtx, const0_rtx));
10958 exponents = validize_mem (force_const_mem (V4SImode, x));
10960 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
10961 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
10963 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
10964 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
10965 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
10966 (0x1.0p84 + double(fp_value_hi_xmm)).
10967 Note these exponents differ by 32. */
10969 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
10971 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
10972 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
10973 real_ldexp (&bias_lo_rvt, &dconst1, 52);
10974 real_ldexp (&bias_hi_rvt, &dconst1, 84);
10975 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
10976 x = const_double_from_real_value (bias_hi_rvt, DFmode);
10977 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
10978 biases = validize_mem (force_const_mem (V2DFmode, biases));
10979 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
10981 /* Add the upper and lower DFmode values together. */
10983 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
10986 x = copy_to_mode_reg (V2DFmode, fp_xmm);
10987 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
10988 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
10991 ix86_expand_vector_extract (false, target, fp_xmm, 0);
10994 /* Not used, but eases macroization of patterns. */
10996 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
10997 rtx input ATTRIBUTE_UNUSED)
10999 gcc_unreachable ();
11002 /* Convert an unsigned SImode value into a DFmode. Only currently used
11003 for SSE, but applicable anywhere. */
11006 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
11008 REAL_VALUE_TYPE TWO31r;
11011 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
11012 NULL, 1, OPTAB_DIRECT);
11014 fp = gen_reg_rtx (DFmode);
11015 emit_insn (gen_floatsidf2 (fp, x));
11017 real_ldexp (&TWO31r, &dconst1, 31);
11018 x = const_double_from_real_value (TWO31r, DFmode);
11020 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
11022 emit_move_insn (target, x);
11025 /* Convert a signed DImode value into a DFmode. Only used for SSE in
11026 32-bit mode; otherwise we have a direct convert instruction. */
11029 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
11031 REAL_VALUE_TYPE TWO32r;
11032 rtx fp_lo, fp_hi, x;
11034 fp_lo = gen_reg_rtx (DFmode);
11035 fp_hi = gen_reg_rtx (DFmode);
11037 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
11039 real_ldexp (&TWO32r, &dconst1, 32);
11040 x = const_double_from_real_value (TWO32r, DFmode);
11041 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
11043 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
11045 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
11048 emit_move_insn (target, x);
11051 /* Convert an unsigned SImode value into a SFmode, using only SSE.
11052 For x86_32, -mfpmath=sse, !optimize_size only. */
11054 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
11056 REAL_VALUE_TYPE ONE16r;
11057 rtx fp_hi, fp_lo, int_hi, int_lo, x;
11059 real_ldexp (&ONE16r, &dconst1, 16);
11060 x = const_double_from_real_value (ONE16r, SFmode);
11061 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
11062 NULL, 0, OPTAB_DIRECT);
11063 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
11064 NULL, 0, OPTAB_DIRECT);
11065 fp_hi = gen_reg_rtx (SFmode);
11066 fp_lo = gen_reg_rtx (SFmode);
11067 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
11068 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
11069 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
11071 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
11073 if (!rtx_equal_p (target, fp_hi))
11074 emit_move_insn (target, fp_hi);
11077 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
11078 then replicate the value for all elements of the vector
11082 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
11089 v = gen_rtvec (4, value, value, value, value);
11090 return gen_rtx_CONST_VECTOR (V4SImode, v);
11094 v = gen_rtvec (2, value, value);
11095 return gen_rtx_CONST_VECTOR (V2DImode, v);
11099 v = gen_rtvec (4, value, value, value, value);
11101 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
11102 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11103 return gen_rtx_CONST_VECTOR (V4SFmode, v);
11107 v = gen_rtvec (2, value, value);
11109 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
11110 return gen_rtx_CONST_VECTOR (V2DFmode, v);
11113 gcc_unreachable ();
11117 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
11118 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
11119 for an SSE register. If VECT is true, then replicate the mask for
11120 all elements of the vector register. If INVERT is true, then create
11121 a mask excluding the sign bit. */
11124 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
11126 enum machine_mode vec_mode, imode;
11127 HOST_WIDE_INT hi, lo;
11132 /* Find the sign bit, sign extended to 2*HWI. */
11138 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
11139 lo = 0x80000000, hi = lo < 0;
11145 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
11146 if (HOST_BITS_PER_WIDE_INT >= 64)
11147 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
11149 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
11155 vec_mode = VOIDmode;
11156 gcc_assert (HOST_BITS_PER_WIDE_INT >= 64);
11157 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
11161 gcc_unreachable ();
11165 lo = ~lo, hi = ~hi;
11167 /* Force this value into the low part of a fp vector constant. */
11168 mask = immed_double_const (lo, hi, imode);
11169 mask = gen_lowpart (mode, mask);
11171 if (vec_mode == VOIDmode)
11172 return force_reg (mode, mask);
11174 v = ix86_build_const_vector (mode, vect, mask);
11175 return force_reg (vec_mode, v);
11178 /* Generate code for floating point ABS or NEG. */
11181 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
11184 rtx mask, set, use, clob, dst, src;
11185 bool use_sse = false;
11186 bool vector_mode = VECTOR_MODE_P (mode);
11187 enum machine_mode elt_mode = mode;
11191 elt_mode = GET_MODE_INNER (mode);
11194 else if (mode == TFmode)
11196 else if (TARGET_SSE_MATH)
11197 use_sse = SSE_FLOAT_MODE_P (mode);
11199 /* NEG and ABS performed with SSE use bitwise mask operations.
11200 Create the appropriate mask now. */
11202 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
11211 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
11212 set = gen_rtx_SET (VOIDmode, dst, set);
11217 set = gen_rtx_fmt_e (code, mode, src);
11218 set = gen_rtx_SET (VOIDmode, dst, set);
11221 use = gen_rtx_USE (VOIDmode, mask);
11222 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11223 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11224 gen_rtvec (3, set, use, clob)));
11231 /* Expand a copysign operation. Special case operand 0 being a constant. */
11234 ix86_expand_copysign (rtx operands[])
11236 enum machine_mode mode, vmode;
11237 rtx dest, op0, op1, mask, nmask;
11239 dest = operands[0];
11243 mode = GET_MODE (dest);
11244 vmode = mode == SFmode ? V4SFmode : V2DFmode;
11246 if (GET_CODE (op0) == CONST_DOUBLE)
11248 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
11250 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
11251 op0 = simplify_unary_operation (ABS, mode, op0, mode);
11253 if (mode == SFmode || mode == DFmode)
11255 if (op0 == CONST0_RTX (mode))
11256 op0 = CONST0_RTX (vmode);
11261 if (mode == SFmode)
11262 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
11263 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
11265 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
11266 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
11270 mask = ix86_build_signbit_mask (mode, 0, 0);
11272 if (mode == SFmode)
11273 copysign_insn = gen_copysignsf3_const;
11274 else if (mode == DFmode)
11275 copysign_insn = gen_copysigndf3_const;
11277 copysign_insn = gen_copysigntf3_const;
11279 emit_insn (copysign_insn (dest, op0, op1, mask));
11283 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
11285 nmask = ix86_build_signbit_mask (mode, 0, 1);
11286 mask = ix86_build_signbit_mask (mode, 0, 0);
11288 if (mode == SFmode)
11289 copysign_insn = gen_copysignsf3_var;
11290 else if (mode == DFmode)
11291 copysign_insn = gen_copysigndf3_var;
11293 copysign_insn = gen_copysigntf3_var;
11295 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
11299 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
11300 be a constant, and so has already been expanded into a vector constant. */
11303 ix86_split_copysign_const (rtx operands[])
11305 enum machine_mode mode, vmode;
11306 rtx dest, op0, op1, mask, x;
11308 dest = operands[0];
11311 mask = operands[3];
11313 mode = GET_MODE (dest);
11314 vmode = GET_MODE (mask);
11316 dest = simplify_gen_subreg (vmode, dest, mode, 0);
11317 x = gen_rtx_AND (vmode, dest, mask);
11318 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11320 if (op0 != CONST0_RTX (vmode))
11322 x = gen_rtx_IOR (vmode, dest, op0);
11323 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11327 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
11328 so we have to do two masks. */
11331 ix86_split_copysign_var (rtx operands[])
11333 enum machine_mode mode, vmode;
11334 rtx dest, scratch, op0, op1, mask, nmask, x;
11336 dest = operands[0];
11337 scratch = operands[1];
11340 nmask = operands[4];
11341 mask = operands[5];
11343 mode = GET_MODE (dest);
11344 vmode = GET_MODE (mask);
11346 if (rtx_equal_p (op0, op1))
11348 /* Shouldn't happen often (it's useless, obviously), but when it does
11349 we'd generate incorrect code if we continue below. */
11350 emit_move_insn (dest, op0);
11354 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
11356 gcc_assert (REGNO (op1) == REGNO (scratch));
11358 x = gen_rtx_AND (vmode, scratch, mask);
11359 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11362 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11363 x = gen_rtx_NOT (vmode, dest);
11364 x = gen_rtx_AND (vmode, x, op0);
11365 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11369 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
11371 x = gen_rtx_AND (vmode, scratch, mask);
11373 else /* alternative 2,4 */
11375 gcc_assert (REGNO (mask) == REGNO (scratch));
11376 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
11377 x = gen_rtx_AND (vmode, scratch, op1);
11379 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
11381 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
11383 dest = simplify_gen_subreg (vmode, op0, mode, 0);
11384 x = gen_rtx_AND (vmode, dest, nmask);
11386 else /* alternative 3,4 */
11388 gcc_assert (REGNO (nmask) == REGNO (dest));
11390 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
11391 x = gen_rtx_AND (vmode, dest, op0);
11393 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11396 x = gen_rtx_IOR (vmode, dest, scratch);
11397 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
11400 /* Return TRUE or FALSE depending on whether the first SET in INSN
11401 has source and destination with matching CC modes, and that the
11402 CC mode is at least as constrained as REQ_MODE. */
11405 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
11408 enum machine_mode set_mode;
11410 set = PATTERN (insn);
11411 if (GET_CODE (set) == PARALLEL)
11412 set = XVECEXP (set, 0, 0);
11413 gcc_assert (GET_CODE (set) == SET);
11414 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
11416 set_mode = GET_MODE (SET_DEST (set));
11420 if (req_mode != CCNOmode
11421 && (req_mode != CCmode
11422 || XEXP (SET_SRC (set), 1) != const0_rtx))
11426 if (req_mode == CCGCmode)
11430 if (req_mode == CCGOCmode || req_mode == CCNOmode)
11434 if (req_mode == CCZmode)
11441 gcc_unreachable ();
11444 return (GET_MODE (SET_SRC (set)) == set_mode);
11447 /* Generate insn patterns to do an integer compare of OPERANDS. */
11450 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
11452 enum machine_mode cmpmode;
11455 cmpmode = SELECT_CC_MODE (code, op0, op1);
11456 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
11458 /* This is very simple, but making the interface the same as in the
11459 FP case makes the rest of the code easier. */
11460 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
11461 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
11463 /* Return the test that should be put into the flags user, i.e.
11464 the bcc, scc, or cmov instruction. */
11465 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
11468 /* Figure out whether to use ordered or unordered fp comparisons.
11469 Return the appropriate mode to use. */
11472 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
11474 /* ??? In order to make all comparisons reversible, we do all comparisons
11475 non-trapping when compiling for IEEE. Once gcc is able to distinguish
11476 all forms trapping and nontrapping comparisons, we can make inequality
11477 comparisons trapping again, since it results in better code when using
11478 FCOM based compares. */
11479 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
11483 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
11485 enum machine_mode mode = GET_MODE (op0);
11487 if (SCALAR_FLOAT_MODE_P (mode))
11489 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
11490 return ix86_fp_compare_mode (code);
11495 /* Only zero flag is needed. */
11496 case EQ: /* ZF=0 */
11497 case NE: /* ZF!=0 */
11499 /* Codes needing carry flag. */
11500 case GEU: /* CF=0 */
11501 case LTU: /* CF=1 */
11502 /* Detect overflow checks. They need just the carry flag. */
11503 if (GET_CODE (op0) == PLUS
11504 && rtx_equal_p (op1, XEXP (op0, 0)))
11508 case GTU: /* CF=0 & ZF=0 */
11509 case LEU: /* CF=1 | ZF=1 */
11510 /* Detect overflow checks. They need just the carry flag. */
11511 if (GET_CODE (op0) == MINUS
11512 && rtx_equal_p (op1, XEXP (op0, 0)))
11516 /* Codes possibly doable only with sign flag when
11517 comparing against zero. */
11518 case GE: /* SF=OF or SF=0 */
11519 case LT: /* SF<>OF or SF=1 */
11520 if (op1 == const0_rtx)
11523 /* For other cases Carry flag is not required. */
11525 /* Codes doable only with sign flag when comparing
11526 against zero, but we miss jump instruction for it
11527 so we need to use relational tests against overflow
11528 that thus needs to be zero. */
11529 case GT: /* ZF=0 & SF=OF */
11530 case LE: /* ZF=1 | SF<>OF */
11531 if (op1 == const0_rtx)
11535 /* strcmp pattern do (use flags) and combine may ask us for proper
11540 gcc_unreachable ();
11544 /* Return the fixed registers used for condition codes. */
11547 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
11554 /* If two condition code modes are compatible, return a condition code
11555 mode which is compatible with both. Otherwise, return
11558 static enum machine_mode
11559 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
11564 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
11567 if ((m1 == CCGCmode && m2 == CCGOCmode)
11568 || (m1 == CCGOCmode && m2 == CCGCmode))
11574 gcc_unreachable ();
11604 /* These are only compatible with themselves, which we already
11610 /* Split comparison code CODE into comparisons we can do using branch
11611 instructions. BYPASS_CODE is comparison code for branch that will
11612 branch around FIRST_CODE and SECOND_CODE. If some of branches
11613 is not required, set value to UNKNOWN.
11614 We never require more than two branches. */
11617 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
11618 enum rtx_code *first_code,
11619 enum rtx_code *second_code)
11621 *first_code = code;
11622 *bypass_code = UNKNOWN;
11623 *second_code = UNKNOWN;
11625 /* The fcomi comparison sets flags as follows:
11635 case GT: /* GTU - CF=0 & ZF=0 */
11636 case GE: /* GEU - CF=0 */
11637 case ORDERED: /* PF=0 */
11638 case UNORDERED: /* PF=1 */
11639 case UNEQ: /* EQ - ZF=1 */
11640 case UNLT: /* LTU - CF=1 */
11641 case UNLE: /* LEU - CF=1 | ZF=1 */
11642 case LTGT: /* EQ - ZF=0 */
11644 case LT: /* LTU - CF=1 - fails on unordered */
11645 *first_code = UNLT;
11646 *bypass_code = UNORDERED;
11648 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
11649 *first_code = UNLE;
11650 *bypass_code = UNORDERED;
11652 case EQ: /* EQ - ZF=1 - fails on unordered */
11653 *first_code = UNEQ;
11654 *bypass_code = UNORDERED;
11656 case NE: /* NE - ZF=0 - fails on unordered */
11657 *first_code = LTGT;
11658 *second_code = UNORDERED;
11660 case UNGE: /* GEU - CF=0 - fails on unordered */
11662 *second_code = UNORDERED;
11664 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
11666 *second_code = UNORDERED;
11669 gcc_unreachable ();
11671 if (!TARGET_IEEE_FP)
11673 *second_code = UNKNOWN;
11674 *bypass_code = UNKNOWN;
11678 /* Return cost of comparison done fcom + arithmetics operations on AX.
11679 All following functions do use number of instructions as a cost metrics.
11680 In future this should be tweaked to compute bytes for optimize_size and
11681 take into account performance of various instructions on various CPUs. */
11683 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
11685 if (!TARGET_IEEE_FP)
11687 /* The cost of code output by ix86_expand_fp_compare. */
11711 gcc_unreachable ();
11715 /* Return cost of comparison done using fcomi operation.
11716 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11718 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
11720 enum rtx_code bypass_code, first_code, second_code;
11721 /* Return arbitrarily high cost when instruction is not supported - this
11722 prevents gcc from using it. */
11725 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11726 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
11729 /* Return cost of comparison done using sahf operation.
11730 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11732 ix86_fp_comparison_sahf_cost (enum rtx_code code)
11734 enum rtx_code bypass_code, first_code, second_code;
11735 /* Return arbitrarily high cost when instruction is not preferred - this
11736 avoids gcc from using it. */
11737 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_size)))
11739 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11740 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
11743 /* Compute cost of the comparison done using any method.
11744 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11746 ix86_fp_comparison_cost (enum rtx_code code)
11748 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
11751 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
11752 sahf_cost = ix86_fp_comparison_sahf_cost (code);
11754 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
11755 if (min > sahf_cost)
11757 if (min > fcomi_cost)
11762 /* Return true if we should use an FCOMI instruction for this
11766 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
11768 enum rtx_code swapped_code = swap_condition (code);
11770 return ((ix86_fp_comparison_cost (code)
11771 == ix86_fp_comparison_fcomi_cost (code))
11772 || (ix86_fp_comparison_cost (swapped_code)
11773 == ix86_fp_comparison_fcomi_cost (swapped_code)));
11776 /* Swap, force into registers, or otherwise massage the two operands
11777 to a fp comparison. The operands are updated in place; the new
11778 comparison code is returned. */
11780 static enum rtx_code
11781 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
11783 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
11784 rtx op0 = *pop0, op1 = *pop1;
11785 enum machine_mode op_mode = GET_MODE (op0);
11786 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
11788 /* All of the unordered compare instructions only work on registers.
11789 The same is true of the fcomi compare instructions. The XFmode
11790 compare instructions require registers except when comparing
11791 against zero or when converting operand 1 from fixed point to
11795 && (fpcmp_mode == CCFPUmode
11796 || (op_mode == XFmode
11797 && ! (standard_80387_constant_p (op0) == 1
11798 || standard_80387_constant_p (op1) == 1)
11799 && GET_CODE (op1) != FLOAT)
11800 || ix86_use_fcomi_compare (code)))
11802 op0 = force_reg (op_mode, op0);
11803 op1 = force_reg (op_mode, op1);
11807 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
11808 things around if they appear profitable, otherwise force op0
11809 into a register. */
11811 if (standard_80387_constant_p (op0) == 0
11813 && ! (standard_80387_constant_p (op1) == 0
11817 tmp = op0, op0 = op1, op1 = tmp;
11818 code = swap_condition (code);
11822 op0 = force_reg (op_mode, op0);
11824 if (CONSTANT_P (op1))
11826 int tmp = standard_80387_constant_p (op1);
11828 op1 = validize_mem (force_const_mem (op_mode, op1));
11832 op1 = force_reg (op_mode, op1);
11835 op1 = force_reg (op_mode, op1);
11839 /* Try to rearrange the comparison to make it cheaper. */
11840 if (ix86_fp_comparison_cost (code)
11841 > ix86_fp_comparison_cost (swap_condition (code))
11842 && (REG_P (op1) || can_create_pseudo_p ()))
11845 tmp = op0, op0 = op1, op1 = tmp;
11846 code = swap_condition (code);
11848 op0 = force_reg (op_mode, op0);
11856 /* Convert comparison codes we use to represent FP comparison to integer
11857 code that will result in proper branch. Return UNKNOWN if no such code
11861 ix86_fp_compare_code_to_integer (enum rtx_code code)
11890 /* Generate insn patterns to do a floating point compare of OPERANDS. */
11893 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
11894 rtx *second_test, rtx *bypass_test)
11896 enum machine_mode fpcmp_mode, intcmp_mode;
11898 int cost = ix86_fp_comparison_cost (code);
11899 enum rtx_code bypass_code, first_code, second_code;
11901 fpcmp_mode = ix86_fp_compare_mode (code);
11902 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
11905 *second_test = NULL_RTX;
11907 *bypass_test = NULL_RTX;
11909 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11911 /* Do fcomi/sahf based test when profitable. */
11912 if (ix86_fp_comparison_arithmetics_cost (code) > cost
11913 && (bypass_code == UNKNOWN || bypass_test)
11914 && (second_code == UNKNOWN || second_test))
11916 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11917 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
11923 gcc_assert (TARGET_SAHF);
11926 scratch = gen_reg_rtx (HImode);
11927 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
11929 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
11932 /* The FP codes work out to act like unsigned. */
11933 intcmp_mode = fpcmp_mode;
11935 if (bypass_code != UNKNOWN)
11936 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
11937 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11939 if (second_code != UNKNOWN)
11940 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
11941 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11946 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
11947 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11948 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
11950 scratch = gen_reg_rtx (HImode);
11951 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
11953 /* In the unordered case, we have to check C2 for NaN's, which
11954 doesn't happen to work out to anything nice combination-wise.
11955 So do some bit twiddling on the value we've got in AH to come
11956 up with an appropriate set of condition codes. */
11958 intcmp_mode = CCNOmode;
11963 if (code == GT || !TARGET_IEEE_FP)
11965 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11970 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11971 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11972 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
11973 intcmp_mode = CCmode;
11979 if (code == LT && TARGET_IEEE_FP)
11981 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11982 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
11983 intcmp_mode = CCmode;
11988 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
11994 if (code == GE || !TARGET_IEEE_FP)
11996 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
12001 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12002 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
12009 if (code == LE && TARGET_IEEE_FP)
12011 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12012 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
12013 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
12014 intcmp_mode = CCmode;
12019 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
12025 if (code == EQ && TARGET_IEEE_FP)
12027 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12028 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
12029 intcmp_mode = CCmode;
12034 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
12041 if (code == NE && TARGET_IEEE_FP)
12043 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
12044 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
12050 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
12056 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
12060 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
12065 gcc_unreachable ();
12069 /* Return the test that should be put into the flags user, i.e.
12070 the bcc, scc, or cmov instruction. */
12071 return gen_rtx_fmt_ee (code, VOIDmode,
12072 gen_rtx_REG (intcmp_mode, FLAGS_REG),
12077 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
12080 op0 = ix86_compare_op0;
12081 op1 = ix86_compare_op1;
12084 *second_test = NULL_RTX;
12086 *bypass_test = NULL_RTX;
12088 if (ix86_compare_emitted)
12090 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
12091 ix86_compare_emitted = NULL_RTX;
12093 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
12095 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
12096 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12097 second_test, bypass_test);
12100 ret = ix86_expand_int_compare (code, op0, op1);
12105 /* Return true if the CODE will result in nontrivial jump sequence. */
12107 ix86_fp_jump_nontrivial_p (enum rtx_code code)
12109 enum rtx_code bypass_code, first_code, second_code;
12112 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12113 return bypass_code != UNKNOWN || second_code != UNKNOWN;
12117 ix86_expand_branch (enum rtx_code code, rtx label)
12121 /* If we have emitted a compare insn, go straight to simple.
12122 ix86_expand_compare won't emit anything if ix86_compare_emitted
12124 if (ix86_compare_emitted)
12127 switch (GET_MODE (ix86_compare_op0))
12133 tmp = ix86_expand_compare (code, NULL, NULL);
12134 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12135 gen_rtx_LABEL_REF (VOIDmode, label),
12137 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
12146 enum rtx_code bypass_code, first_code, second_code;
12148 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
12149 &ix86_compare_op1);
12151 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
12153 /* Check whether we will use the natural sequence with one jump. If
12154 so, we can expand jump early. Otherwise delay expansion by
12155 creating compound insn to not confuse optimizers. */
12156 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
12158 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
12159 gen_rtx_LABEL_REF (VOIDmode, label),
12160 pc_rtx, NULL_RTX, NULL_RTX);
12164 tmp = gen_rtx_fmt_ee (code, VOIDmode,
12165 ix86_compare_op0, ix86_compare_op1);
12166 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
12167 gen_rtx_LABEL_REF (VOIDmode, label),
12169 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
12171 use_fcomi = ix86_use_fcomi_compare (code);
12172 vec = rtvec_alloc (3 + !use_fcomi);
12173 RTVEC_ELT (vec, 0) = tmp;
12175 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
12177 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
12180 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
12182 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12191 /* Expand DImode branch into multiple compare+branch. */
12193 rtx lo[2], hi[2], label2;
12194 enum rtx_code code1, code2, code3;
12195 enum machine_mode submode;
12197 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
12199 tmp = ix86_compare_op0;
12200 ix86_compare_op0 = ix86_compare_op1;
12201 ix86_compare_op1 = tmp;
12202 code = swap_condition (code);
12204 if (GET_MODE (ix86_compare_op0) == DImode)
12206 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
12207 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
12212 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
12213 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
12217 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
12218 avoid two branches. This costs one extra insn, so disable when
12219 optimizing for size. */
12221 if ((code == EQ || code == NE)
12223 || hi[1] == const0_rtx || lo[1] == const0_rtx))
12228 if (hi[1] != const0_rtx)
12229 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
12230 NULL_RTX, 0, OPTAB_WIDEN);
12233 if (lo[1] != const0_rtx)
12234 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
12235 NULL_RTX, 0, OPTAB_WIDEN);
12237 tmp = expand_binop (submode, ior_optab, xor1, xor0,
12238 NULL_RTX, 0, OPTAB_WIDEN);
12240 ix86_compare_op0 = tmp;
12241 ix86_compare_op1 = const0_rtx;
12242 ix86_expand_branch (code, label);
12246 /* Otherwise, if we are doing less-than or greater-or-equal-than,
12247 op1 is a constant and the low word is zero, then we can just
12248 examine the high word. Similarly for low word -1 and
12249 less-or-equal-than or greater-than. */
12251 if (CONST_INT_P (hi[1]))
12254 case LT: case LTU: case GE: case GEU:
12255 if (lo[1] == const0_rtx)
12257 ix86_compare_op0 = hi[0];
12258 ix86_compare_op1 = hi[1];
12259 ix86_expand_branch (code, label);
12263 case LE: case LEU: case GT: case GTU:
12264 if (lo[1] == constm1_rtx)
12266 ix86_compare_op0 = hi[0];
12267 ix86_compare_op1 = hi[1];
12268 ix86_expand_branch (code, label);
12276 /* Otherwise, we need two or three jumps. */
12278 label2 = gen_label_rtx ();
12281 code2 = swap_condition (code);
12282 code3 = unsigned_condition (code);
12286 case LT: case GT: case LTU: case GTU:
12289 case LE: code1 = LT; code2 = GT; break;
12290 case GE: code1 = GT; code2 = LT; break;
12291 case LEU: code1 = LTU; code2 = GTU; break;
12292 case GEU: code1 = GTU; code2 = LTU; break;
12294 case EQ: code1 = UNKNOWN; code2 = NE; break;
12295 case NE: code2 = UNKNOWN; break;
12298 gcc_unreachable ();
12303 * if (hi(a) < hi(b)) goto true;
12304 * if (hi(a) > hi(b)) goto false;
12305 * if (lo(a) < lo(b)) goto true;
12309 ix86_compare_op0 = hi[0];
12310 ix86_compare_op1 = hi[1];
12312 if (code1 != UNKNOWN)
12313 ix86_expand_branch (code1, label);
12314 if (code2 != UNKNOWN)
12315 ix86_expand_branch (code2, label2);
12317 ix86_compare_op0 = lo[0];
12318 ix86_compare_op1 = lo[1];
12319 ix86_expand_branch (code3, label);
12321 if (code2 != UNKNOWN)
12322 emit_label (label2);
12327 gcc_unreachable ();
12331 /* Split branch based on floating point condition. */
12333 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
12334 rtx target1, rtx target2, rtx tmp, rtx pushed)
12336 rtx second, bypass;
12337 rtx label = NULL_RTX;
12339 int bypass_probability = -1, second_probability = -1, probability = -1;
12342 if (target2 != pc_rtx)
12345 code = reverse_condition_maybe_unordered (code);
12350 condition = ix86_expand_fp_compare (code, op1, op2,
12351 tmp, &second, &bypass);
12353 /* Remove pushed operand from stack. */
12355 ix86_free_from_memory (GET_MODE (pushed));
12357 if (split_branch_probability >= 0)
12359 /* Distribute the probabilities across the jumps.
12360 Assume the BYPASS and SECOND to be always test
12362 probability = split_branch_probability;
12364 /* Value of 1 is low enough to make no need for probability
12365 to be updated. Later we may run some experiments and see
12366 if unordered values are more frequent in practice. */
12368 bypass_probability = 1;
12370 second_probability = 1;
12372 if (bypass != NULL_RTX)
12374 label = gen_label_rtx ();
12375 i = emit_jump_insn (gen_rtx_SET
12377 gen_rtx_IF_THEN_ELSE (VOIDmode,
12379 gen_rtx_LABEL_REF (VOIDmode,
12382 if (bypass_probability >= 0)
12384 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12385 GEN_INT (bypass_probability),
12388 i = emit_jump_insn (gen_rtx_SET
12390 gen_rtx_IF_THEN_ELSE (VOIDmode,
12391 condition, target1, target2)));
12392 if (probability >= 0)
12394 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12395 GEN_INT (probability),
12397 if (second != NULL_RTX)
12399 i = emit_jump_insn (gen_rtx_SET
12401 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
12403 if (second_probability >= 0)
12405 = gen_rtx_EXPR_LIST (REG_BR_PROB,
12406 GEN_INT (second_probability),
12409 if (label != NULL_RTX)
12410 emit_label (label);
12414 ix86_expand_setcc (enum rtx_code code, rtx dest)
12416 rtx ret, tmp, tmpreg, equiv;
12417 rtx second_test, bypass_test;
12419 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
12420 return 0; /* FAIL */
12422 gcc_assert (GET_MODE (dest) == QImode);
12424 ret = ix86_expand_compare (code, &second_test, &bypass_test);
12425 PUT_MODE (ret, QImode);
12430 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
12431 if (bypass_test || second_test)
12433 rtx test = second_test;
12435 rtx tmp2 = gen_reg_rtx (QImode);
12438 gcc_assert (!second_test);
12439 test = bypass_test;
12441 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
12443 PUT_MODE (test, QImode);
12444 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
12447 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
12449 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
12452 /* Attach a REG_EQUAL note describing the comparison result. */
12453 if (ix86_compare_op0 && ix86_compare_op1)
12455 equiv = simplify_gen_relational (code, QImode,
12456 GET_MODE (ix86_compare_op0),
12457 ix86_compare_op0, ix86_compare_op1);
12458 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
12461 return 1; /* DONE */
12464 /* Expand comparison setting or clearing carry flag. Return true when
12465 successful and set pop for the operation. */
12467 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
12469 enum machine_mode mode =
12470 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
12472 /* Do not handle DImode compares that go through special path. */
12473 if (mode == (TARGET_64BIT ? TImode : DImode))
12476 if (SCALAR_FLOAT_MODE_P (mode))
12478 rtx second_test = NULL, bypass_test = NULL;
12479 rtx compare_op, compare_seq;
12481 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
12483 /* Shortcut: following common codes never translate
12484 into carry flag compares. */
12485 if (code == EQ || code == NE || code == UNEQ || code == LTGT
12486 || code == ORDERED || code == UNORDERED)
12489 /* These comparisons require zero flag; swap operands so they won't. */
12490 if ((code == GT || code == UNLE || code == LE || code == UNGT)
12491 && !TARGET_IEEE_FP)
12496 code = swap_condition (code);
12499 /* Try to expand the comparison and verify that we end up with
12500 carry flag based comparison. This fails to be true only when
12501 we decide to expand comparison using arithmetic that is not
12502 too common scenario. */
12504 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
12505 &second_test, &bypass_test);
12506 compare_seq = get_insns ();
12509 if (second_test || bypass_test)
12512 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12513 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12514 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
12516 code = GET_CODE (compare_op);
12518 if (code != LTU && code != GEU)
12521 emit_insn (compare_seq);
12526 if (!INTEGRAL_MODE_P (mode))
12535 /* Convert a==0 into (unsigned)a<1. */
12538 if (op1 != const0_rtx)
12541 code = (code == EQ ? LTU : GEU);
12544 /* Convert a>b into b<a or a>=b-1. */
12547 if (CONST_INT_P (op1))
12549 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
12550 /* Bail out on overflow. We still can swap operands but that
12551 would force loading of the constant into register. */
12552 if (op1 == const0_rtx
12553 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
12555 code = (code == GTU ? GEU : LTU);
12562 code = (code == GTU ? LTU : GEU);
12566 /* Convert a>=0 into (unsigned)a<0x80000000. */
12569 if (mode == DImode || op1 != const0_rtx)
12571 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12572 code = (code == LT ? GEU : LTU);
12576 if (mode == DImode || op1 != constm1_rtx)
12578 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
12579 code = (code == LE ? GEU : LTU);
12585 /* Swapping operands may cause constant to appear as first operand. */
12586 if (!nonimmediate_operand (op0, VOIDmode))
12588 if (!can_create_pseudo_p ())
12590 op0 = force_reg (mode, op0);
12592 ix86_compare_op0 = op0;
12593 ix86_compare_op1 = op1;
12594 *pop = ix86_expand_compare (code, NULL, NULL);
12595 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
12600 ix86_expand_int_movcc (rtx operands[])
12602 enum rtx_code code = GET_CODE (operands[1]), compare_code;
12603 rtx compare_seq, compare_op;
12604 rtx second_test, bypass_test;
12605 enum machine_mode mode = GET_MODE (operands[0]);
12606 bool sign_bit_compare_p = false;;
12609 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12610 compare_seq = get_insns ();
12613 compare_code = GET_CODE (compare_op);
12615 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
12616 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
12617 sign_bit_compare_p = true;
12619 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
12620 HImode insns, we'd be swallowed in word prefix ops. */
12622 if ((mode != HImode || TARGET_FAST_PREFIX)
12623 && (mode != (TARGET_64BIT ? TImode : DImode))
12624 && CONST_INT_P (operands[2])
12625 && CONST_INT_P (operands[3]))
12627 rtx out = operands[0];
12628 HOST_WIDE_INT ct = INTVAL (operands[2]);
12629 HOST_WIDE_INT cf = INTVAL (operands[3]);
12630 HOST_WIDE_INT diff;
12633 /* Sign bit compares are better done using shifts than we do by using
12635 if (sign_bit_compare_p
12636 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
12637 ix86_compare_op1, &compare_op))
12639 /* Detect overlap between destination and compare sources. */
12642 if (!sign_bit_compare_p)
12644 bool fpcmp = false;
12646 compare_code = GET_CODE (compare_op);
12648 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12649 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12652 compare_code = ix86_fp_compare_code_to_integer (compare_code);
12655 /* To simplify rest of code, restrict to the GEU case. */
12656 if (compare_code == LTU)
12658 HOST_WIDE_INT tmp = ct;
12661 compare_code = reverse_condition (compare_code);
12662 code = reverse_condition (code);
12667 PUT_CODE (compare_op,
12668 reverse_condition_maybe_unordered
12669 (GET_CODE (compare_op)));
12671 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
12675 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
12676 || reg_overlap_mentioned_p (out, ix86_compare_op1))
12677 tmp = gen_reg_rtx (mode);
12679 if (mode == DImode)
12680 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
12682 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
12686 if (code == GT || code == GE)
12687 code = reverse_condition (code);
12690 HOST_WIDE_INT tmp = ct;
12695 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
12696 ix86_compare_op1, VOIDmode, 0, -1);
12709 tmp = expand_simple_binop (mode, PLUS,
12711 copy_rtx (tmp), 1, OPTAB_DIRECT);
12722 tmp = expand_simple_binop (mode, IOR,
12724 copy_rtx (tmp), 1, OPTAB_DIRECT);
12726 else if (diff == -1 && ct)
12736 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12738 tmp = expand_simple_binop (mode, PLUS,
12739 copy_rtx (tmp), GEN_INT (cf),
12740 copy_rtx (tmp), 1, OPTAB_DIRECT);
12748 * andl cf - ct, dest
12758 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12761 tmp = expand_simple_binop (mode, AND,
12763 gen_int_mode (cf - ct, mode),
12764 copy_rtx (tmp), 1, OPTAB_DIRECT);
12766 tmp = expand_simple_binop (mode, PLUS,
12767 copy_rtx (tmp), GEN_INT (ct),
12768 copy_rtx (tmp), 1, OPTAB_DIRECT);
12771 if (!rtx_equal_p (tmp, out))
12772 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
12774 return 1; /* DONE */
12779 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12782 tmp = ct, ct = cf, cf = tmp;
12785 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12787 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12789 /* We may be reversing unordered compare to normal compare, that
12790 is not valid in general (we may convert non-trapping condition
12791 to trapping one), however on i386 we currently emit all
12792 comparisons unordered. */
12793 compare_code = reverse_condition_maybe_unordered (compare_code);
12794 code = reverse_condition_maybe_unordered (code);
12798 compare_code = reverse_condition (compare_code);
12799 code = reverse_condition (code);
12803 compare_code = UNKNOWN;
12804 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
12805 && CONST_INT_P (ix86_compare_op1))
12807 if (ix86_compare_op1 == const0_rtx
12808 && (code == LT || code == GE))
12809 compare_code = code;
12810 else if (ix86_compare_op1 == constm1_rtx)
12814 else if (code == GT)
12819 /* Optimize dest = (op0 < 0) ? -1 : cf. */
12820 if (compare_code != UNKNOWN
12821 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
12822 && (cf == -1 || ct == -1))
12824 /* If lea code below could be used, only optimize
12825 if it results in a 2 insn sequence. */
12827 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
12828 || diff == 3 || diff == 5 || diff == 9)
12829 || (compare_code == LT && ct == -1)
12830 || (compare_code == GE && cf == -1))
12833 * notl op1 (if necessary)
12841 code = reverse_condition (code);
12844 out = emit_store_flag (out, code, ix86_compare_op0,
12845 ix86_compare_op1, VOIDmode, 0, -1);
12847 out = expand_simple_binop (mode, IOR,
12849 out, 1, OPTAB_DIRECT);
12850 if (out != operands[0])
12851 emit_move_insn (operands[0], out);
12853 return 1; /* DONE */
12858 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
12859 || diff == 3 || diff == 5 || diff == 9)
12860 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
12862 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
12868 * lea cf(dest*(ct-cf)),dest
12872 * This also catches the degenerate setcc-only case.
12878 out = emit_store_flag (out, code, ix86_compare_op0,
12879 ix86_compare_op1, VOIDmode, 0, 1);
12882 /* On x86_64 the lea instruction operates on Pmode, so we need
12883 to get arithmetics done in proper mode to match. */
12885 tmp = copy_rtx (out);
12889 out1 = copy_rtx (out);
12890 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
12894 tmp = gen_rtx_PLUS (mode, tmp, out1);
12900 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
12903 if (!rtx_equal_p (tmp, out))
12906 out = force_operand (tmp, copy_rtx (out));
12908 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
12910 if (!rtx_equal_p (out, operands[0]))
12911 emit_move_insn (operands[0], copy_rtx (out));
12913 return 1; /* DONE */
12917 * General case: Jumpful:
12918 * xorl dest,dest cmpl op1, op2
12919 * cmpl op1, op2 movl ct, dest
12920 * setcc dest jcc 1f
12921 * decl dest movl cf, dest
12922 * andl (cf-ct),dest 1:
12925 * Size 20. Size 14.
12927 * This is reasonably steep, but branch mispredict costs are
12928 * high on modern cpus, so consider failing only if optimizing
12932 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12933 && BRANCH_COST >= 2)
12937 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12942 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12944 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12946 /* We may be reversing unordered compare to normal compare,
12947 that is not valid in general (we may convert non-trapping
12948 condition to trapping one), however on i386 we currently
12949 emit all comparisons unordered. */
12950 code = reverse_condition_maybe_unordered (code);
12954 code = reverse_condition (code);
12955 if (compare_code != UNKNOWN)
12956 compare_code = reverse_condition (compare_code);
12960 if (compare_code != UNKNOWN)
12962 /* notl op1 (if needed)
12967 For x < 0 (resp. x <= -1) there will be no notl,
12968 so if possible swap the constants to get rid of the
12970 True/false will be -1/0 while code below (store flag
12971 followed by decrement) is 0/-1, so the constants need
12972 to be exchanged once more. */
12974 if (compare_code == GE || !cf)
12976 code = reverse_condition (code);
12981 HOST_WIDE_INT tmp = cf;
12986 out = emit_store_flag (out, code, ix86_compare_op0,
12987 ix86_compare_op1, VOIDmode, 0, -1);
12991 out = emit_store_flag (out, code, ix86_compare_op0,
12992 ix86_compare_op1, VOIDmode, 0, 1);
12994 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
12995 copy_rtx (out), 1, OPTAB_DIRECT);
12998 out = expand_simple_binop (mode, AND, copy_rtx (out),
12999 gen_int_mode (cf - ct, mode),
13000 copy_rtx (out), 1, OPTAB_DIRECT);
13002 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
13003 copy_rtx (out), 1, OPTAB_DIRECT);
13004 if (!rtx_equal_p (out, operands[0]))
13005 emit_move_insn (operands[0], copy_rtx (out));
13007 return 1; /* DONE */
13011 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
13013 /* Try a few things more with specific constants and a variable. */
13016 rtx var, orig_out, out, tmp;
13018 if (BRANCH_COST <= 2)
13019 return 0; /* FAIL */
13021 /* If one of the two operands is an interesting constant, load a
13022 constant with the above and mask it in with a logical operation. */
13024 if (CONST_INT_P (operands[2]))
13027 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
13028 operands[3] = constm1_rtx, op = and_optab;
13029 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
13030 operands[3] = const0_rtx, op = ior_optab;
13032 return 0; /* FAIL */
13034 else if (CONST_INT_P (operands[3]))
13037 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
13038 operands[2] = constm1_rtx, op = and_optab;
13039 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
13040 operands[2] = const0_rtx, op = ior_optab;
13042 return 0; /* FAIL */
13045 return 0; /* FAIL */
13047 orig_out = operands[0];
13048 tmp = gen_reg_rtx (mode);
13051 /* Recurse to get the constant loaded. */
13052 if (ix86_expand_int_movcc (operands) == 0)
13053 return 0; /* FAIL */
13055 /* Mask in the interesting variable. */
13056 out = expand_binop (mode, op, var, tmp, orig_out, 0,
13058 if (!rtx_equal_p (out, orig_out))
13059 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
13061 return 1; /* DONE */
13065 * For comparison with above,
13075 if (! nonimmediate_operand (operands[2], mode))
13076 operands[2] = force_reg (mode, operands[2]);
13077 if (! nonimmediate_operand (operands[3], mode))
13078 operands[3] = force_reg (mode, operands[3]);
13080 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
13082 rtx tmp = gen_reg_rtx (mode);
13083 emit_move_insn (tmp, operands[3]);
13086 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13088 rtx tmp = gen_reg_rtx (mode);
13089 emit_move_insn (tmp, operands[2]);
13093 if (! register_operand (operands[2], VOIDmode)
13095 || ! register_operand (operands[3], VOIDmode)))
13096 operands[2] = force_reg (mode, operands[2]);
13099 && ! register_operand (operands[3], VOIDmode))
13100 operands[3] = force_reg (mode, operands[3]);
13102 emit_insn (compare_seq);
13103 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13104 gen_rtx_IF_THEN_ELSE (mode,
13105 compare_op, operands[2],
13108 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13109 gen_rtx_IF_THEN_ELSE (mode,
13111 copy_rtx (operands[3]),
13112 copy_rtx (operands[0]))));
13114 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
13115 gen_rtx_IF_THEN_ELSE (mode,
13117 copy_rtx (operands[2]),
13118 copy_rtx (operands[0]))));
13120 return 1; /* DONE */
13123 /* Swap, force into registers, or otherwise massage the two operands
13124 to an sse comparison with a mask result. Thus we differ a bit from
13125 ix86_prepare_fp_compare_args which expects to produce a flags result.
13127 The DEST operand exists to help determine whether to commute commutative
13128 operators. The POP0/POP1 operands are updated in place. The new
13129 comparison code is returned, or UNKNOWN if not implementable. */
13131 static enum rtx_code
13132 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
13133 rtx *pop0, rtx *pop1)
13141 /* We have no LTGT as an operator. We could implement it with
13142 NE & ORDERED, but this requires an extra temporary. It's
13143 not clear that it's worth it. */
13150 /* These are supported directly. */
13157 /* For commutative operators, try to canonicalize the destination
13158 operand to be first in the comparison - this helps reload to
13159 avoid extra moves. */
13160 if (!dest || !rtx_equal_p (dest, *pop1))
13168 /* These are not supported directly. Swap the comparison operands
13169 to transform into something that is supported. */
13173 code = swap_condition (code);
13177 gcc_unreachable ();
13183 /* Detect conditional moves that exactly match min/max operational
13184 semantics. Note that this is IEEE safe, as long as we don't
13185 interchange the operands.
13187 Returns FALSE if this conditional move doesn't match a MIN/MAX,
13188 and TRUE if the operation is successful and instructions are emitted. */
13191 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
13192 rtx cmp_op1, rtx if_true, rtx if_false)
13194 enum machine_mode mode;
13200 else if (code == UNGE)
13203 if_true = if_false;
13209 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
13211 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
13216 mode = GET_MODE (dest);
13218 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
13219 but MODE may be a vector mode and thus not appropriate. */
13220 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
13222 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
13225 if_true = force_reg (mode, if_true);
13226 v = gen_rtvec (2, if_true, if_false);
13227 tmp = gen_rtx_UNSPEC (mode, v, u);
13231 code = is_min ? SMIN : SMAX;
13232 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
13235 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
13239 /* Expand an sse vector comparison. Return the register with the result. */
13242 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
13243 rtx op_true, rtx op_false)
13245 enum machine_mode mode = GET_MODE (dest);
13248 cmp_op0 = force_reg (mode, cmp_op0);
13249 if (!nonimmediate_operand (cmp_op1, mode))
13250 cmp_op1 = force_reg (mode, cmp_op1);
13253 || reg_overlap_mentioned_p (dest, op_true)
13254 || reg_overlap_mentioned_p (dest, op_false))
13255 dest = gen_reg_rtx (mode);
13257 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
13258 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13263 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
13264 operations. This is used for both scalar and vector conditional moves. */
13267 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
13269 enum machine_mode mode = GET_MODE (dest);
13274 rtx pcmov = gen_rtx_SET (mode, dest,
13275 gen_rtx_IF_THEN_ELSE (mode, cmp,
13280 else if (op_false == CONST0_RTX (mode))
13282 op_true = force_reg (mode, op_true);
13283 x = gen_rtx_AND (mode, cmp, op_true);
13284 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13286 else if (op_true == CONST0_RTX (mode))
13288 op_false = force_reg (mode, op_false);
13289 x = gen_rtx_NOT (mode, cmp);
13290 x = gen_rtx_AND (mode, x, op_false);
13291 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13295 op_true = force_reg (mode, op_true);
13296 op_false = force_reg (mode, op_false);
13298 t2 = gen_reg_rtx (mode);
13300 t3 = gen_reg_rtx (mode);
13304 x = gen_rtx_AND (mode, op_true, cmp);
13305 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
13307 x = gen_rtx_NOT (mode, cmp);
13308 x = gen_rtx_AND (mode, x, op_false);
13309 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
13311 x = gen_rtx_IOR (mode, t3, t2);
13312 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13316 /* Expand a floating-point conditional move. Return true if successful. */
13319 ix86_expand_fp_movcc (rtx operands[])
13321 enum machine_mode mode = GET_MODE (operands[0]);
13322 enum rtx_code code = GET_CODE (operands[1]);
13323 rtx tmp, compare_op, second_test, bypass_test;
13325 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
13327 enum machine_mode cmode;
13329 /* Since we've no cmove for sse registers, don't force bad register
13330 allocation just to gain access to it. Deny movcc when the
13331 comparison mode doesn't match the move mode. */
13332 cmode = GET_MODE (ix86_compare_op0);
13333 if (cmode == VOIDmode)
13334 cmode = GET_MODE (ix86_compare_op1);
13338 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13340 &ix86_compare_op1);
13341 if (code == UNKNOWN)
13344 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
13345 ix86_compare_op1, operands[2],
13349 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
13350 ix86_compare_op1, operands[2], operands[3]);
13351 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
13355 /* The floating point conditional move instructions don't directly
13356 support conditions resulting from a signed integer comparison. */
13358 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13360 /* The floating point conditional move instructions don't directly
13361 support signed integer comparisons. */
13363 if (!fcmov_comparison_operator (compare_op, VOIDmode))
13365 gcc_assert (!second_test && !bypass_test);
13366 tmp = gen_reg_rtx (QImode);
13367 ix86_expand_setcc (code, tmp);
13369 ix86_compare_op0 = tmp;
13370 ix86_compare_op1 = const0_rtx;
13371 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13373 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
13375 tmp = gen_reg_rtx (mode);
13376 emit_move_insn (tmp, operands[3]);
13379 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
13381 tmp = gen_reg_rtx (mode);
13382 emit_move_insn (tmp, operands[2]);
13386 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13387 gen_rtx_IF_THEN_ELSE (mode, compare_op,
13388 operands[2], operands[3])));
13390 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13391 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
13392 operands[3], operands[0])));
13394 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
13395 gen_rtx_IF_THEN_ELSE (mode, second_test,
13396 operands[2], operands[0])));
13401 /* Expand a floating-point vector conditional move; a vcond operation
13402 rather than a movcc operation. */
13405 ix86_expand_fp_vcond (rtx operands[])
13407 enum rtx_code code = GET_CODE (operands[3]);
13410 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
13411 &operands[4], &operands[5]);
13412 if (code == UNKNOWN)
13415 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
13416 operands[5], operands[1], operands[2]))
13419 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
13420 operands[1], operands[2]);
13421 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
13425 /* Expand a signed/unsigned integral vector conditional move. */
13428 ix86_expand_int_vcond (rtx operands[])
13430 enum machine_mode mode = GET_MODE (operands[0]);
13431 enum rtx_code code = GET_CODE (operands[3]);
13432 bool negate = false;
13435 cop0 = operands[4];
13436 cop1 = operands[5];
13438 /* Canonicalize the comparison to EQ, GT, GTU. */
13449 code = reverse_condition (code);
13455 code = reverse_condition (code);
13461 code = swap_condition (code);
13462 x = cop0, cop0 = cop1, cop1 = x;
13466 gcc_unreachable ();
13469 /* Only SSE4.1/SSE4.2 supports V2DImode. */
13470 if (mode == V2DImode)
13475 /* SSE4.1 supports EQ. */
13476 if (!TARGET_SSE4_1)
13482 /* SSE4.2 supports GT/GTU. */
13483 if (!TARGET_SSE4_2)
13488 gcc_unreachable ();
13492 /* Unsigned parallel compare is not supported by the hardware. Play some
13493 tricks to turn this into a signed comparison against 0. */
13496 cop0 = force_reg (mode, cop0);
13505 /* Perform a parallel modulo subtraction. */
13506 t1 = gen_reg_rtx (mode);
13507 emit_insn ((mode == V4SImode
13509 : gen_subv2di3) (t1, cop0, cop1));
13511 /* Extract the original sign bit of op0. */
13512 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
13514 t2 = gen_reg_rtx (mode);
13515 emit_insn ((mode == V4SImode
13517 : gen_andv2di3) (t2, cop0, mask));
13519 /* XOR it back into the result of the subtraction. This results
13520 in the sign bit set iff we saw unsigned underflow. */
13521 x = gen_reg_rtx (mode);
13522 emit_insn ((mode == V4SImode
13524 : gen_xorv2di3) (x, t1, t2));
13532 /* Perform a parallel unsigned saturating subtraction. */
13533 x = gen_reg_rtx (mode);
13534 emit_insn (gen_rtx_SET (VOIDmode, x,
13535 gen_rtx_US_MINUS (mode, cop0, cop1)));
13542 gcc_unreachable ();
13546 cop1 = CONST0_RTX (mode);
13549 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
13550 operands[1+negate], operands[2-negate]);
13552 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
13553 operands[2-negate]);
13557 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
13558 true if we should do zero extension, else sign extension. HIGH_P is
13559 true if we want the N/2 high elements, else the low elements. */
13562 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13564 enum machine_mode imode = GET_MODE (operands[1]);
13565 rtx (*unpack)(rtx, rtx, rtx);
13572 unpack = gen_vec_interleave_highv16qi;
13574 unpack = gen_vec_interleave_lowv16qi;
13578 unpack = gen_vec_interleave_highv8hi;
13580 unpack = gen_vec_interleave_lowv8hi;
13584 unpack = gen_vec_interleave_highv4si;
13586 unpack = gen_vec_interleave_lowv4si;
13589 gcc_unreachable ();
13592 dest = gen_lowpart (imode, operands[0]);
13595 se = force_reg (imode, CONST0_RTX (imode));
13597 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
13598 operands[1], pc_rtx, pc_rtx);
13600 emit_insn (unpack (dest, operands[1], se));
13603 /* This function performs the same task as ix86_expand_sse_unpack,
13604 but with SSE4.1 instructions. */
13607 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13609 enum machine_mode imode = GET_MODE (operands[1]);
13610 rtx (*unpack)(rtx, rtx);
13617 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
13619 unpack = gen_sse4_1_extendv8qiv8hi2;
13623 unpack = gen_sse4_1_zero_extendv4hiv4si2;
13625 unpack = gen_sse4_1_extendv4hiv4si2;
13629 unpack = gen_sse4_1_zero_extendv2siv2di2;
13631 unpack = gen_sse4_1_extendv2siv2di2;
13634 gcc_unreachable ();
13637 dest = operands[0];
13640 /* Shift higher 8 bytes to lower 8 bytes. */
13641 src = gen_reg_rtx (imode);
13642 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
13643 gen_lowpart (TImode, operands[1]),
13649 emit_insn (unpack (dest, src));
13652 /* This function performs the same task as ix86_expand_sse_unpack,
13653 but with amdfam15 instructions. */
13655 #define PPERM_SRC 0x00 /* copy source */
13656 #define PPERM_INVERT 0x20 /* invert source */
13657 #define PPERM_REVERSE 0x40 /* bit reverse source */
13658 #define PPERM_REV_INV 0x60 /* bit reverse & invert src */
13659 #define PPERM_ZERO 0x80 /* all 0's */
13660 #define PPERM_ONES 0xa0 /* all 1's */
13661 #define PPERM_SIGN 0xc0 /* propagate sign bit */
13662 #define PPERM_INV_SIGN 0xe0 /* invert & propagate sign */
13664 #define PPERM_SRC1 0x00 /* use first source byte */
13665 #define PPERM_SRC2 0x10 /* use second source byte */
13668 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
13670 enum machine_mode imode = GET_MODE (operands[1]);
13671 int pperm_bytes[16];
13673 int h = (high_p) ? 8 : 0;
13676 rtvec v = rtvec_alloc (16);
13679 rtx op0 = operands[0], op1 = operands[1];
13684 vs = rtvec_alloc (8);
13685 h2 = (high_p) ? 8 : 0;
13686 for (i = 0; i < 8; i++)
13688 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
13689 pperm_bytes[2*i+1] = ((unsigned_p)
13691 : PPERM_SIGN | PPERM_SRC2 | i | h);
13694 for (i = 0; i < 16; i++)
13695 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13697 for (i = 0; i < 8; i++)
13698 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13700 p = gen_rtx_PARALLEL (VOIDmode, vs);
13701 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13703 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
13705 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
13709 vs = rtvec_alloc (4);
13710 h2 = (high_p) ? 4 : 0;
13711 for (i = 0; i < 4; i++)
13713 sign_extend = ((unsigned_p)
13715 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
13716 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
13717 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
13718 pperm_bytes[4*i+2] = sign_extend;
13719 pperm_bytes[4*i+3] = sign_extend;
13722 for (i = 0; i < 16; i++)
13723 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13725 for (i = 0; i < 4; i++)
13726 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13728 p = gen_rtx_PARALLEL (VOIDmode, vs);
13729 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13731 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
13733 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
13737 vs = rtvec_alloc (2);
13738 h2 = (high_p) ? 2 : 0;
13739 for (i = 0; i < 2; i++)
13741 sign_extend = ((unsigned_p)
13743 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
13744 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
13745 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
13746 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
13747 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
13748 pperm_bytes[8*i+4] = sign_extend;
13749 pperm_bytes[8*i+5] = sign_extend;
13750 pperm_bytes[8*i+6] = sign_extend;
13751 pperm_bytes[8*i+7] = sign_extend;
13754 for (i = 0; i < 16; i++)
13755 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13757 for (i = 0; i < 2; i++)
13758 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
13760 p = gen_rtx_PARALLEL (VOIDmode, vs);
13761 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13763 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
13765 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
13769 gcc_unreachable ();
13775 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
13776 next narrower integer vector type */
13778 ix86_expand_sse5_pack (rtx operands[3])
13780 enum machine_mode imode = GET_MODE (operands[0]);
13781 int pperm_bytes[16];
13783 rtvec v = rtvec_alloc (16);
13785 rtx op0 = operands[0];
13786 rtx op1 = operands[1];
13787 rtx op2 = operands[2];
13792 for (i = 0; i < 8; i++)
13794 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
13795 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
13798 for (i = 0; i < 16; i++)
13799 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13801 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13802 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
13806 for (i = 0; i < 4; i++)
13808 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
13809 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
13810 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
13811 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
13814 for (i = 0; i < 16; i++)
13815 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13817 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13818 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
13822 for (i = 0; i < 2; i++)
13824 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
13825 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
13826 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
13827 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
13828 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
13829 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
13830 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
13831 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
13834 for (i = 0; i < 16; i++)
13835 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
13837 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
13838 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
13842 gcc_unreachable ();
13848 /* Expand conditional increment or decrement using adb/sbb instructions.
13849 The default case using setcc followed by the conditional move can be
13850 done by generic code. */
13852 ix86_expand_int_addcc (rtx operands[])
13854 enum rtx_code code = GET_CODE (operands[1]);
13856 rtx val = const0_rtx;
13857 bool fpcmp = false;
13858 enum machine_mode mode = GET_MODE (operands[0]);
13860 if (operands[3] != const1_rtx
13861 && operands[3] != constm1_rtx)
13863 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
13864 ix86_compare_op1, &compare_op))
13866 code = GET_CODE (compare_op);
13868 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
13869 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
13872 code = ix86_fp_compare_code_to_integer (code);
13879 PUT_CODE (compare_op,
13880 reverse_condition_maybe_unordered
13881 (GET_CODE (compare_op)));
13883 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
13885 PUT_MODE (compare_op, mode);
13887 /* Construct either adc or sbb insn. */
13888 if ((code == LTU) == (operands[3] == constm1_rtx))
13890 switch (GET_MODE (operands[0]))
13893 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
13896 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
13899 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
13902 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13905 gcc_unreachable ();
13910 switch (GET_MODE (operands[0]))
13913 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
13916 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
13919 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
13922 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
13925 gcc_unreachable ();
13928 return 1; /* DONE */
13932 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
13933 works for floating pointer parameters and nonoffsetable memories.
13934 For pushes, it returns just stack offsets; the values will be saved
13935 in the right order. Maximally three parts are generated. */
13938 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
13943 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
13945 size = (GET_MODE_SIZE (mode) + 4) / 8;
13947 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
13948 gcc_assert (size >= 2 && size <= 3);
13950 /* Optimize constant pool reference to immediates. This is used by fp
13951 moves, that force all constants to memory to allow combining. */
13952 if (MEM_P (operand) && MEM_READONLY_P (operand))
13954 rtx tmp = maybe_get_pool_constant (operand);
13959 if (MEM_P (operand) && !offsettable_memref_p (operand))
13961 /* The only non-offsetable memories we handle are pushes. */
13962 int ok = push_operand (operand, VOIDmode);
13966 operand = copy_rtx (operand);
13967 PUT_MODE (operand, Pmode);
13968 parts[0] = parts[1] = parts[2] = operand;
13972 if (GET_CODE (operand) == CONST_VECTOR)
13974 enum machine_mode imode = int_mode_for_mode (mode);
13975 /* Caution: if we looked through a constant pool memory above,
13976 the operand may actually have a different mode now. That's
13977 ok, since we want to pun this all the way back to an integer. */
13978 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
13979 gcc_assert (operand != NULL);
13985 if (mode == DImode)
13986 split_di (&operand, 1, &parts[0], &parts[1]);
13989 if (REG_P (operand))
13991 gcc_assert (reload_completed);
13992 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
13993 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
13995 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
13997 else if (offsettable_memref_p (operand))
13999 operand = adjust_address (operand, SImode, 0);
14000 parts[0] = operand;
14001 parts[1] = adjust_address (operand, SImode, 4);
14003 parts[2] = adjust_address (operand, SImode, 8);
14005 else if (GET_CODE (operand) == CONST_DOUBLE)
14010 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
14014 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
14015 parts[2] = gen_int_mode (l[2], SImode);
14018 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
14021 gcc_unreachable ();
14023 parts[1] = gen_int_mode (l[1], SImode);
14024 parts[0] = gen_int_mode (l[0], SImode);
14027 gcc_unreachable ();
14032 if (mode == TImode)
14033 split_ti (&operand, 1, &parts[0], &parts[1]);
14034 if (mode == XFmode || mode == TFmode)
14036 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
14037 if (REG_P (operand))
14039 gcc_assert (reload_completed);
14040 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
14041 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
14043 else if (offsettable_memref_p (operand))
14045 operand = adjust_address (operand, DImode, 0);
14046 parts[0] = operand;
14047 parts[1] = adjust_address (operand, upper_mode, 8);
14049 else if (GET_CODE (operand) == CONST_DOUBLE)
14054 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
14055 real_to_target (l, &r, mode);
14057 /* Do not use shift by 32 to avoid warning on 32bit systems. */
14058 if (HOST_BITS_PER_WIDE_INT >= 64)
14061 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
14062 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
14065 parts[0] = immed_double_const (l[0], l[1], DImode);
14067 if (upper_mode == SImode)
14068 parts[1] = gen_int_mode (l[2], SImode);
14069 else if (HOST_BITS_PER_WIDE_INT >= 64)
14072 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
14073 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
14076 parts[1] = immed_double_const (l[2], l[3], DImode);
14079 gcc_unreachable ();
14086 /* Emit insns to perform a move or push of DI, DF, and XF values.
14087 Return false when normal moves are needed; true when all required
14088 insns have been emitted. Operands 2-4 contain the input values
14089 int the correct order; operands 5-7 contain the output values. */
14092 ix86_split_long_move (rtx operands[])
14097 int collisions = 0;
14098 enum machine_mode mode = GET_MODE (operands[0]);
14100 /* The DFmode expanders may ask us to move double.
14101 For 64bit target this is single move. By hiding the fact
14102 here we simplify i386.md splitters. */
14103 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
14105 /* Optimize constant pool reference to immediates. This is used by
14106 fp moves, that force all constants to memory to allow combining. */
14108 if (MEM_P (operands[1])
14109 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
14110 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
14111 operands[1] = get_pool_constant (XEXP (operands[1], 0));
14112 if (push_operand (operands[0], VOIDmode))
14114 operands[0] = copy_rtx (operands[0]);
14115 PUT_MODE (operands[0], Pmode);
14118 operands[0] = gen_lowpart (DImode, operands[0]);
14119 operands[1] = gen_lowpart (DImode, operands[1]);
14120 emit_move_insn (operands[0], operands[1]);
14124 /* The only non-offsettable memory we handle is push. */
14125 if (push_operand (operands[0], VOIDmode))
14128 gcc_assert (!MEM_P (operands[0])
14129 || offsettable_memref_p (operands[0]));
14131 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
14132 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
14134 /* When emitting push, take care for source operands on the stack. */
14135 if (push && MEM_P (operands[1])
14136 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
14139 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
14140 XEXP (part[1][2], 0));
14141 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
14142 XEXP (part[1][1], 0));
14145 /* We need to do copy in the right order in case an address register
14146 of the source overlaps the destination. */
14147 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
14149 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
14151 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14154 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
14157 /* Collision in the middle part can be handled by reordering. */
14158 if (collisions == 1 && nparts == 3
14159 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
14162 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
14163 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
14166 /* If there are more collisions, we can't handle it by reordering.
14167 Do an lea to the last part and use only one colliding move. */
14168 else if (collisions > 1)
14174 base = part[0][nparts - 1];
14176 /* Handle the case when the last part isn't valid for lea.
14177 Happens in 64-bit mode storing the 12-byte XFmode. */
14178 if (GET_MODE (base) != Pmode)
14179 base = gen_rtx_REG (Pmode, REGNO (base));
14181 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
14182 part[1][0] = replace_equiv_address (part[1][0], base);
14183 part[1][1] = replace_equiv_address (part[1][1],
14184 plus_constant (base, UNITS_PER_WORD));
14186 part[1][2] = replace_equiv_address (part[1][2],
14187 plus_constant (base, 8));
14197 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
14198 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
14199 emit_move_insn (part[0][2], part[1][2]);
14204 /* In 64bit mode we don't have 32bit push available. In case this is
14205 register, it is OK - we will just use larger counterpart. We also
14206 retype memory - these comes from attempt to avoid REX prefix on
14207 moving of second half of TFmode value. */
14208 if (GET_MODE (part[1][1]) == SImode)
14210 switch (GET_CODE (part[1][1]))
14213 part[1][1] = adjust_address (part[1][1], DImode, 0);
14217 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
14221 gcc_unreachable ();
14224 if (GET_MODE (part[1][0]) == SImode)
14225 part[1][0] = part[1][1];
14228 emit_move_insn (part[0][1], part[1][1]);
14229 emit_move_insn (part[0][0], part[1][0]);
14233 /* Choose correct order to not overwrite the source before it is copied. */
14234 if ((REG_P (part[0][0])
14235 && REG_P (part[1][1])
14236 && (REGNO (part[0][0]) == REGNO (part[1][1])
14238 && REGNO (part[0][0]) == REGNO (part[1][2]))))
14240 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
14244 operands[2] = part[0][2];
14245 operands[3] = part[0][1];
14246 operands[4] = part[0][0];
14247 operands[5] = part[1][2];
14248 operands[6] = part[1][1];
14249 operands[7] = part[1][0];
14253 operands[2] = part[0][1];
14254 operands[3] = part[0][0];
14255 operands[5] = part[1][1];
14256 operands[6] = part[1][0];
14263 operands[2] = part[0][0];
14264 operands[3] = part[0][1];
14265 operands[4] = part[0][2];
14266 operands[5] = part[1][0];
14267 operands[6] = part[1][1];
14268 operands[7] = part[1][2];
14272 operands[2] = part[0][0];
14273 operands[3] = part[0][1];
14274 operands[5] = part[1][0];
14275 operands[6] = part[1][1];
14279 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
14282 if (CONST_INT_P (operands[5])
14283 && operands[5] != const0_rtx
14284 && REG_P (operands[2]))
14286 if (CONST_INT_P (operands[6])
14287 && INTVAL (operands[6]) == INTVAL (operands[5]))
14288 operands[6] = operands[2];
14291 && CONST_INT_P (operands[7])
14292 && INTVAL (operands[7]) == INTVAL (operands[5]))
14293 operands[7] = operands[2];
14297 && CONST_INT_P (operands[6])
14298 && operands[6] != const0_rtx
14299 && REG_P (operands[3])
14300 && CONST_INT_P (operands[7])
14301 && INTVAL (operands[7]) == INTVAL (operands[6]))
14302 operands[7] = operands[3];
14305 emit_move_insn (operands[2], operands[5]);
14306 emit_move_insn (operands[3], operands[6]);
14308 emit_move_insn (operands[4], operands[7]);
14313 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
14314 left shift by a constant, either using a single shift or
14315 a sequence of add instructions. */
14318 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
14322 emit_insn ((mode == DImode
14324 : gen_adddi3) (operand, operand, operand));
14326 else if (!optimize_size
14327 && count * ix86_cost->add <= ix86_cost->shift_const)
14330 for (i=0; i<count; i++)
14332 emit_insn ((mode == DImode
14334 : gen_adddi3) (operand, operand, operand));
14338 emit_insn ((mode == DImode
14340 : gen_ashldi3) (operand, operand, GEN_INT (count)));
14344 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
14346 rtx low[2], high[2];
14348 const int single_width = mode == DImode ? 32 : 64;
14350 if (CONST_INT_P (operands[2]))
14352 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14353 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14355 if (count >= single_width)
14357 emit_move_insn (high[0], low[1]);
14358 emit_move_insn (low[0], const0_rtx);
14360 if (count > single_width)
14361 ix86_expand_ashl_const (high[0], count - single_width, mode);
14365 if (!rtx_equal_p (operands[0], operands[1]))
14366 emit_move_insn (operands[0], operands[1]);
14367 emit_insn ((mode == DImode
14369 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
14370 ix86_expand_ashl_const (low[0], count, mode);
14375 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14377 if (operands[1] == const1_rtx)
14379 /* Assuming we've chosen a QImode capable registers, then 1 << N
14380 can be done with two 32/64-bit shifts, no branches, no cmoves. */
14381 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
14383 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
14385 ix86_expand_clear (low[0]);
14386 ix86_expand_clear (high[0]);
14387 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
14389 d = gen_lowpart (QImode, low[0]);
14390 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14391 s = gen_rtx_EQ (QImode, flags, const0_rtx);
14392 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14394 d = gen_lowpart (QImode, high[0]);
14395 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
14396 s = gen_rtx_NE (QImode, flags, const0_rtx);
14397 emit_insn (gen_rtx_SET (VOIDmode, d, s));
14400 /* Otherwise, we can get the same results by manually performing
14401 a bit extract operation on bit 5/6, and then performing the two
14402 shifts. The two methods of getting 0/1 into low/high are exactly
14403 the same size. Avoiding the shift in the bit extract case helps
14404 pentium4 a bit; no one else seems to care much either way. */
14409 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
14410 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
14412 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
14413 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
14415 emit_insn ((mode == DImode
14417 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
14418 emit_insn ((mode == DImode
14420 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
14421 emit_move_insn (low[0], high[0]);
14422 emit_insn ((mode == DImode
14424 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
14427 emit_insn ((mode == DImode
14429 : gen_ashldi3) (low[0], low[0], operands[2]));
14430 emit_insn ((mode == DImode
14432 : gen_ashldi3) (high[0], high[0], operands[2]));
14436 if (operands[1] == constm1_rtx)
14438 /* For -1 << N, we can avoid the shld instruction, because we
14439 know that we're shifting 0...31/63 ones into a -1. */
14440 emit_move_insn (low[0], constm1_rtx);
14442 emit_move_insn (high[0], low[0]);
14444 emit_move_insn (high[0], constm1_rtx);
14448 if (!rtx_equal_p (operands[0], operands[1]))
14449 emit_move_insn (operands[0], operands[1]);
14451 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14452 emit_insn ((mode == DImode
14454 : gen_x86_64_shld) (high[0], low[0], operands[2]));
14457 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
14459 if (TARGET_CMOVE && scratch)
14461 ix86_expand_clear (scratch);
14462 emit_insn ((mode == DImode
14463 ? gen_x86_shift_adj_1
14464 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
14467 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
14471 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
14473 rtx low[2], high[2];
14475 const int single_width = mode == DImode ? 32 : 64;
14477 if (CONST_INT_P (operands[2]))
14479 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14480 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14482 if (count == single_width * 2 - 1)
14484 emit_move_insn (high[0], high[1]);
14485 emit_insn ((mode == DImode
14487 : gen_ashrdi3) (high[0], high[0],
14488 GEN_INT (single_width - 1)));
14489 emit_move_insn (low[0], high[0]);
14492 else if (count >= single_width)
14494 emit_move_insn (low[0], high[1]);
14495 emit_move_insn (high[0], low[0]);
14496 emit_insn ((mode == DImode
14498 : gen_ashrdi3) (high[0], high[0],
14499 GEN_INT (single_width - 1)));
14500 if (count > single_width)
14501 emit_insn ((mode == DImode
14503 : gen_ashrdi3) (low[0], low[0],
14504 GEN_INT (count - single_width)));
14508 if (!rtx_equal_p (operands[0], operands[1]))
14509 emit_move_insn (operands[0], operands[1]);
14510 emit_insn ((mode == DImode
14512 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14513 emit_insn ((mode == DImode
14515 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
14520 if (!rtx_equal_p (operands[0], operands[1]))
14521 emit_move_insn (operands[0], operands[1]);
14523 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14525 emit_insn ((mode == DImode
14527 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14528 emit_insn ((mode == DImode
14530 : gen_ashrdi3) (high[0], high[0], operands[2]));
14532 if (TARGET_CMOVE && scratch)
14534 emit_move_insn (scratch, high[0]);
14535 emit_insn ((mode == DImode
14537 : gen_ashrdi3) (scratch, scratch,
14538 GEN_INT (single_width - 1)));
14539 emit_insn ((mode == DImode
14540 ? gen_x86_shift_adj_1
14541 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14545 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
14550 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
14552 rtx low[2], high[2];
14554 const int single_width = mode == DImode ? 32 : 64;
14556 if (CONST_INT_P (operands[2]))
14558 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
14559 count = INTVAL (operands[2]) & (single_width * 2 - 1);
14561 if (count >= single_width)
14563 emit_move_insn (low[0], high[1]);
14564 ix86_expand_clear (high[0]);
14566 if (count > single_width)
14567 emit_insn ((mode == DImode
14569 : gen_lshrdi3) (low[0], low[0],
14570 GEN_INT (count - single_width)));
14574 if (!rtx_equal_p (operands[0], operands[1]))
14575 emit_move_insn (operands[0], operands[1]);
14576 emit_insn ((mode == DImode
14578 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
14579 emit_insn ((mode == DImode
14581 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
14586 if (!rtx_equal_p (operands[0], operands[1]))
14587 emit_move_insn (operands[0], operands[1]);
14589 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
14591 emit_insn ((mode == DImode
14593 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
14594 emit_insn ((mode == DImode
14596 : gen_lshrdi3) (high[0], high[0], operands[2]));
14598 /* Heh. By reversing the arguments, we can reuse this pattern. */
14599 if (TARGET_CMOVE && scratch)
14601 ix86_expand_clear (scratch);
14602 emit_insn ((mode == DImode
14603 ? gen_x86_shift_adj_1
14604 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
14608 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
14612 /* Predict just emitted jump instruction to be taken with probability PROB. */
14614 predict_jump (int prob)
14616 rtx insn = get_last_insn ();
14617 gcc_assert (JUMP_P (insn));
14619 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14624 /* Helper function for the string operations below. Dest VARIABLE whether
14625 it is aligned to VALUE bytes. If true, jump to the label. */
14627 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
14629 rtx label = gen_label_rtx ();
14630 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
14631 if (GET_MODE (variable) == DImode)
14632 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
14634 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
14635 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
14638 predict_jump (REG_BR_PROB_BASE * 50 / 100);
14640 predict_jump (REG_BR_PROB_BASE * 90 / 100);
14644 /* Adjust COUNTER by the VALUE. */
14646 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
14648 if (GET_MODE (countreg) == DImode)
14649 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
14651 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
14654 /* Zero extend possibly SImode EXP to Pmode register. */
14656 ix86_zero_extend_to_Pmode (rtx exp)
14659 if (GET_MODE (exp) == VOIDmode)
14660 return force_reg (Pmode, exp);
14661 if (GET_MODE (exp) == Pmode)
14662 return copy_to_mode_reg (Pmode, exp);
14663 r = gen_reg_rtx (Pmode);
14664 emit_insn (gen_zero_extendsidi2 (r, exp));
14668 /* Divide COUNTREG by SCALE. */
14670 scale_counter (rtx countreg, int scale)
14673 rtx piece_size_mask;
14677 if (CONST_INT_P (countreg))
14678 return GEN_INT (INTVAL (countreg) / scale);
14679 gcc_assert (REG_P (countreg));
14681 piece_size_mask = GEN_INT (scale - 1);
14682 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
14683 GEN_INT (exact_log2 (scale)),
14684 NULL, 1, OPTAB_DIRECT);
14688 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
14689 DImode for constant loop counts. */
14691 static enum machine_mode
14692 counter_mode (rtx count_exp)
14694 if (GET_MODE (count_exp) != VOIDmode)
14695 return GET_MODE (count_exp);
14696 if (GET_CODE (count_exp) != CONST_INT)
14698 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
14703 /* When SRCPTR is non-NULL, output simple loop to move memory
14704 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
14705 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
14706 equivalent loop to set memory by VALUE (supposed to be in MODE).
14708 The size is rounded down to whole number of chunk size moved at once.
14709 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
14713 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
14714 rtx destptr, rtx srcptr, rtx value,
14715 rtx count, enum machine_mode mode, int unroll,
14718 rtx out_label, top_label, iter, tmp;
14719 enum machine_mode iter_mode = counter_mode (count);
14720 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
14721 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
14727 top_label = gen_label_rtx ();
14728 out_label = gen_label_rtx ();
14729 iter = gen_reg_rtx (iter_mode);
14731 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
14732 NULL, 1, OPTAB_DIRECT);
14733 /* Those two should combine. */
14734 if (piece_size == const1_rtx)
14736 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
14738 predict_jump (REG_BR_PROB_BASE * 10 / 100);
14740 emit_move_insn (iter, const0_rtx);
14742 emit_label (top_label);
14744 tmp = convert_modes (Pmode, iter_mode, iter, true);
14745 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
14746 destmem = change_address (destmem, mode, x_addr);
14750 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
14751 srcmem = change_address (srcmem, mode, y_addr);
14753 /* When unrolling for chips that reorder memory reads and writes,
14754 we can save registers by using single temporary.
14755 Also using 4 temporaries is overkill in 32bit mode. */
14756 if (!TARGET_64BIT && 0)
14758 for (i = 0; i < unroll; i++)
14763 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14765 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14767 emit_move_insn (destmem, srcmem);
14773 gcc_assert (unroll <= 4);
14774 for (i = 0; i < unroll; i++)
14776 tmpreg[i] = gen_reg_rtx (mode);
14780 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
14782 emit_move_insn (tmpreg[i], srcmem);
14784 for (i = 0; i < unroll; i++)
14789 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14791 emit_move_insn (destmem, tmpreg[i]);
14796 for (i = 0; i < unroll; i++)
14800 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
14801 emit_move_insn (destmem, value);
14804 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
14805 true, OPTAB_LIB_WIDEN);
14807 emit_move_insn (iter, tmp);
14809 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
14811 if (expected_size != -1)
14813 expected_size /= GET_MODE_SIZE (mode) * unroll;
14814 if (expected_size == 0)
14816 else if (expected_size > REG_BR_PROB_BASE)
14817 predict_jump (REG_BR_PROB_BASE - 1);
14819 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
14822 predict_jump (REG_BR_PROB_BASE * 80 / 100);
14823 iter = ix86_zero_extend_to_Pmode (iter);
14824 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
14825 true, OPTAB_LIB_WIDEN);
14826 if (tmp != destptr)
14827 emit_move_insn (destptr, tmp);
14830 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
14831 true, OPTAB_LIB_WIDEN);
14833 emit_move_insn (srcptr, tmp);
14835 emit_label (out_label);
14838 /* Output "rep; mov" instruction.
14839 Arguments have same meaning as for previous function */
14841 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
14842 rtx destptr, rtx srcptr,
14844 enum machine_mode mode)
14850 /* If the size is known, it is shorter to use rep movs. */
14851 if (mode == QImode && CONST_INT_P (count)
14852 && !(INTVAL (count) & 3))
14855 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14856 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14857 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
14858 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
14859 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14860 if (mode != QImode)
14862 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14863 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14864 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14865 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
14866 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14867 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
14871 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14872 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
14874 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
14878 /* Output "rep; stos" instruction.
14879 Arguments have same meaning as for previous function */
14881 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
14883 enum machine_mode mode)
14888 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
14889 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
14890 value = force_reg (mode, gen_lowpart (mode, value));
14891 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
14892 if (mode != QImode)
14894 destexp = gen_rtx_ASHIFT (Pmode, countreg,
14895 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
14896 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
14899 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
14900 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
14904 emit_strmov (rtx destmem, rtx srcmem,
14905 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
14907 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
14908 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
14909 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14912 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
14914 expand_movmem_epilogue (rtx destmem, rtx srcmem,
14915 rtx destptr, rtx srcptr, rtx count, int max_size)
14918 if (CONST_INT_P (count))
14920 HOST_WIDE_INT countval = INTVAL (count);
14923 if ((countval & 0x10) && max_size > 16)
14927 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14928 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
14931 gcc_unreachable ();
14934 if ((countval & 0x08) && max_size > 8)
14937 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
14940 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14941 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
14945 if ((countval & 0x04) && max_size > 4)
14947 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
14950 if ((countval & 0x02) && max_size > 2)
14952 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
14955 if ((countval & 0x01) && max_size > 1)
14957 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
14964 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
14965 count, 1, OPTAB_DIRECT);
14966 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
14967 count, QImode, 1, 4);
14971 /* When there are stringops, we can cheaply increase dest and src pointers.
14972 Otherwise we save code size by maintaining offset (zero is readily
14973 available from preceding rep operation) and using x86 addressing modes.
14975 if (TARGET_SINGLE_STRINGOP)
14979 rtx label = ix86_expand_aligntest (count, 4, true);
14980 src = change_address (srcmem, SImode, srcptr);
14981 dest = change_address (destmem, SImode, destptr);
14982 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14983 emit_label (label);
14984 LABEL_NUSES (label) = 1;
14988 rtx label = ix86_expand_aligntest (count, 2, true);
14989 src = change_address (srcmem, HImode, srcptr);
14990 dest = change_address (destmem, HImode, destptr);
14991 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14992 emit_label (label);
14993 LABEL_NUSES (label) = 1;
14997 rtx label = ix86_expand_aligntest (count, 1, true);
14998 src = change_address (srcmem, QImode, srcptr);
14999 dest = change_address (destmem, QImode, destptr);
15000 emit_insn (gen_strmov (destptr, dest, srcptr, src));
15001 emit_label (label);
15002 LABEL_NUSES (label) = 1;
15007 rtx offset = force_reg (Pmode, const0_rtx);
15012 rtx label = ix86_expand_aligntest (count, 4, true);
15013 src = change_address (srcmem, SImode, srcptr);
15014 dest = change_address (destmem, SImode, destptr);
15015 emit_move_insn (dest, src);
15016 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
15017 true, OPTAB_LIB_WIDEN);
15019 emit_move_insn (offset, tmp);
15020 emit_label (label);
15021 LABEL_NUSES (label) = 1;
15025 rtx label = ix86_expand_aligntest (count, 2, true);
15026 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
15027 src = change_address (srcmem, HImode, tmp);
15028 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
15029 dest = change_address (destmem, HImode, tmp);
15030 emit_move_insn (dest, src);
15031 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
15032 true, OPTAB_LIB_WIDEN);
15034 emit_move_insn (offset, tmp);
15035 emit_label (label);
15036 LABEL_NUSES (label) = 1;
15040 rtx label = ix86_expand_aligntest (count, 1, true);
15041 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
15042 src = change_address (srcmem, QImode, tmp);
15043 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
15044 dest = change_address (destmem, QImode, tmp);
15045 emit_move_insn (dest, src);
15046 emit_label (label);
15047 LABEL_NUSES (label) = 1;
15052 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
15054 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
15055 rtx count, int max_size)
15058 expand_simple_binop (counter_mode (count), AND, count,
15059 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
15060 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
15061 gen_lowpart (QImode, value), count, QImode,
15065 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
15067 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
15071 if (CONST_INT_P (count))
15073 HOST_WIDE_INT countval = INTVAL (count);
15076 if ((countval & 0x10) && max_size > 16)
15080 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
15081 emit_insn (gen_strset (destptr, dest, value));
15082 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
15083 emit_insn (gen_strset (destptr, dest, value));
15086 gcc_unreachable ();
15089 if ((countval & 0x08) && max_size > 8)
15093 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
15094 emit_insn (gen_strset (destptr, dest, value));
15098 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15099 emit_insn (gen_strset (destptr, dest, value));
15100 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
15101 emit_insn (gen_strset (destptr, dest, value));
15105 if ((countval & 0x04) && max_size > 4)
15107 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
15108 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15111 if ((countval & 0x02) && max_size > 2)
15113 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
15114 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15117 if ((countval & 0x01) && max_size > 1)
15119 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
15120 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15127 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
15132 rtx label = ix86_expand_aligntest (count, 16, true);
15135 dest = change_address (destmem, DImode, destptr);
15136 emit_insn (gen_strset (destptr, dest, value));
15137 emit_insn (gen_strset (destptr, dest, value));
15141 dest = change_address (destmem, SImode, destptr);
15142 emit_insn (gen_strset (destptr, dest, value));
15143 emit_insn (gen_strset (destptr, dest, value));
15144 emit_insn (gen_strset (destptr, dest, value));
15145 emit_insn (gen_strset (destptr, dest, value));
15147 emit_label (label);
15148 LABEL_NUSES (label) = 1;
15152 rtx label = ix86_expand_aligntest (count, 8, true);
15155 dest = change_address (destmem, DImode, destptr);
15156 emit_insn (gen_strset (destptr, dest, value));
15160 dest = change_address (destmem, SImode, destptr);
15161 emit_insn (gen_strset (destptr, dest, value));
15162 emit_insn (gen_strset (destptr, dest, value));
15164 emit_label (label);
15165 LABEL_NUSES (label) = 1;
15169 rtx label = ix86_expand_aligntest (count, 4, true);
15170 dest = change_address (destmem, SImode, destptr);
15171 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
15172 emit_label (label);
15173 LABEL_NUSES (label) = 1;
15177 rtx label = ix86_expand_aligntest (count, 2, true);
15178 dest = change_address (destmem, HImode, destptr);
15179 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
15180 emit_label (label);
15181 LABEL_NUSES (label) = 1;
15185 rtx label = ix86_expand_aligntest (count, 1, true);
15186 dest = change_address (destmem, QImode, destptr);
15187 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
15188 emit_label (label);
15189 LABEL_NUSES (label) = 1;
15193 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
15194 DESIRED_ALIGNMENT. */
15196 expand_movmem_prologue (rtx destmem, rtx srcmem,
15197 rtx destptr, rtx srcptr, rtx count,
15198 int align, int desired_alignment)
15200 if (align <= 1 && desired_alignment > 1)
15202 rtx label = ix86_expand_aligntest (destptr, 1, false);
15203 srcmem = change_address (srcmem, QImode, srcptr);
15204 destmem = change_address (destmem, QImode, destptr);
15205 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15206 ix86_adjust_counter (count, 1);
15207 emit_label (label);
15208 LABEL_NUSES (label) = 1;
15210 if (align <= 2 && desired_alignment > 2)
15212 rtx label = ix86_expand_aligntest (destptr, 2, false);
15213 srcmem = change_address (srcmem, HImode, srcptr);
15214 destmem = change_address (destmem, HImode, destptr);
15215 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15216 ix86_adjust_counter (count, 2);
15217 emit_label (label);
15218 LABEL_NUSES (label) = 1;
15220 if (align <= 4 && desired_alignment > 4)
15222 rtx label = ix86_expand_aligntest (destptr, 4, false);
15223 srcmem = change_address (srcmem, SImode, srcptr);
15224 destmem = change_address (destmem, SImode, destptr);
15225 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
15226 ix86_adjust_counter (count, 4);
15227 emit_label (label);
15228 LABEL_NUSES (label) = 1;
15230 gcc_assert (desired_alignment <= 8);
15233 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
15234 DESIRED_ALIGNMENT. */
15236 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
15237 int align, int desired_alignment)
15239 if (align <= 1 && desired_alignment > 1)
15241 rtx label = ix86_expand_aligntest (destptr, 1, false);
15242 destmem = change_address (destmem, QImode, destptr);
15243 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
15244 ix86_adjust_counter (count, 1);
15245 emit_label (label);
15246 LABEL_NUSES (label) = 1;
15248 if (align <= 2 && desired_alignment > 2)
15250 rtx label = ix86_expand_aligntest (destptr, 2, false);
15251 destmem = change_address (destmem, HImode, destptr);
15252 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
15253 ix86_adjust_counter (count, 2);
15254 emit_label (label);
15255 LABEL_NUSES (label) = 1;
15257 if (align <= 4 && desired_alignment > 4)
15259 rtx label = ix86_expand_aligntest (destptr, 4, false);
15260 destmem = change_address (destmem, SImode, destptr);
15261 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
15262 ix86_adjust_counter (count, 4);
15263 emit_label (label);
15264 LABEL_NUSES (label) = 1;
15266 gcc_assert (desired_alignment <= 8);
15269 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
15270 static enum stringop_alg
15271 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
15272 int *dynamic_check)
15274 const struct stringop_algs * algs;
15275 /* Algorithms using the rep prefix want at least edi and ecx;
15276 additionally, memset wants eax and memcpy wants esi. Don't
15277 consider such algorithms if the user has appropriated those
15278 registers for their own purposes. */
15279 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
15281 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
15283 #define ALG_USABLE_P(alg) (rep_prefix_usable \
15284 || (alg != rep_prefix_1_byte \
15285 && alg != rep_prefix_4_byte \
15286 && alg != rep_prefix_8_byte))
15288 *dynamic_check = -1;
15290 algs = &ix86_cost->memset[TARGET_64BIT != 0];
15292 algs = &ix86_cost->memcpy[TARGET_64BIT != 0];
15293 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
15294 return stringop_alg;
15295 /* rep; movq or rep; movl is the smallest variant. */
15296 else if (optimize_size)
15298 if (!count || (count & 3))
15299 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
15301 return rep_prefix_usable ? rep_prefix_4_byte : loop;
15303 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
15305 else if (expected_size != -1 && expected_size < 4)
15306 return loop_1_byte;
15307 else if (expected_size != -1)
15310 enum stringop_alg alg = libcall;
15311 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15313 /* We get here if the algorithms that were not libcall-based
15314 were rep-prefix based and we are unable to use rep prefixes
15315 based on global register usage. Break out of the loop and
15316 use the heuristic below. */
15317 if (algs->size[i].max == 0)
15319 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
15321 enum stringop_alg candidate = algs->size[i].alg;
15323 if (candidate != libcall && ALG_USABLE_P (candidate))
15325 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
15326 last non-libcall inline algorithm. */
15327 if (TARGET_INLINE_ALL_STRINGOPS)
15329 /* When the current size is best to be copied by a libcall,
15330 but we are still forced to inline, run the heuristic below
15331 that will pick code for medium sized blocks. */
15332 if (alg != libcall)
15336 else if (ALG_USABLE_P (candidate))
15340 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
15342 /* When asked to inline the call anyway, try to pick meaningful choice.
15343 We look for maximal size of block that is faster to copy by hand and
15344 take blocks of at most of that size guessing that average size will
15345 be roughly half of the block.
15347 If this turns out to be bad, we might simply specify the preferred
15348 choice in ix86_costs. */
15349 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15350 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
15353 enum stringop_alg alg;
15355 bool any_alg_usable_p = true;
15357 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
15359 enum stringop_alg candidate = algs->size[i].alg;
15360 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
15362 if (candidate != libcall && candidate
15363 && ALG_USABLE_P (candidate))
15364 max = algs->size[i].max;
15366 /* If there aren't any usable algorithms, then recursing on
15367 smaller sizes isn't going to find anything. Just return the
15368 simple byte-at-a-time copy loop. */
15369 if (!any_alg_usable_p)
15371 /* Pick something reasonable. */
15372 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15373 *dynamic_check = 128;
15374 return loop_1_byte;
15378 alg = decide_alg (count, max / 2, memset, dynamic_check);
15379 gcc_assert (*dynamic_check == -1);
15380 gcc_assert (alg != libcall);
15381 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
15382 *dynamic_check = max;
15385 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
15386 #undef ALG_USABLE_P
15389 /* Decide on alignment. We know that the operand is already aligned to ALIGN
15390 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
15392 decide_alignment (int align,
15393 enum stringop_alg alg,
15396 int desired_align = 0;
15400 gcc_unreachable ();
15402 case unrolled_loop:
15403 desired_align = GET_MODE_SIZE (Pmode);
15405 case rep_prefix_8_byte:
15408 case rep_prefix_4_byte:
15409 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15410 copying whole cacheline at once. */
15411 if (TARGET_PENTIUMPRO)
15416 case rep_prefix_1_byte:
15417 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
15418 copying whole cacheline at once. */
15419 if (TARGET_PENTIUMPRO)
15433 if (desired_align < align)
15434 desired_align = align;
15435 if (expected_size != -1 && expected_size < 4)
15436 desired_align = align;
15437 return desired_align;
15440 /* Return the smallest power of 2 greater than VAL. */
15442 smallest_pow2_greater_than (int val)
15450 /* Expand string move (memcpy) operation. Use i386 string operations when
15451 profitable. expand_setmem contains similar code. The code depends upon
15452 architecture, block size and alignment, but always has the same
15455 1) Prologue guard: Conditional that jumps up to epilogues for small
15456 blocks that can be handled by epilogue alone. This is faster but
15457 also needed for correctness, since prologue assume the block is larger
15458 than the desired alignment.
15460 Optional dynamic check for size and libcall for large
15461 blocks is emitted here too, with -minline-stringops-dynamically.
15463 2) Prologue: copy first few bytes in order to get destination aligned
15464 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
15465 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
15466 We emit either a jump tree on power of two sized blocks, or a byte loop.
15468 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
15469 with specified algorithm.
15471 4) Epilogue: code copying tail of the block that is too small to be
15472 handled by main body (or up to size guarded by prologue guard). */
15475 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
15476 rtx expected_align_exp, rtx expected_size_exp)
15482 rtx jump_around_label = NULL;
15483 HOST_WIDE_INT align = 1;
15484 unsigned HOST_WIDE_INT count = 0;
15485 HOST_WIDE_INT expected_size = -1;
15486 int size_needed = 0, epilogue_size_needed;
15487 int desired_align = 0;
15488 enum stringop_alg alg;
15491 if (CONST_INT_P (align_exp))
15492 align = INTVAL (align_exp);
15493 /* i386 can do misaligned access on reasonably increased cost. */
15494 if (CONST_INT_P (expected_align_exp)
15495 && INTVAL (expected_align_exp) > align)
15496 align = INTVAL (expected_align_exp);
15497 if (CONST_INT_P (count_exp))
15498 count = expected_size = INTVAL (count_exp);
15499 if (CONST_INT_P (expected_size_exp) && count == 0)
15500 expected_size = INTVAL (expected_size_exp);
15502 /* Make sure we don't need to care about overflow later on. */
15503 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15506 /* Step 0: Decide on preferred algorithm, desired alignment and
15507 size of chunks to be copied by main loop. */
15509 alg = decide_alg (count, expected_size, false, &dynamic_check);
15510 desired_align = decide_alignment (align, alg, expected_size);
15512 if (!TARGET_ALIGN_STRINGOPS)
15513 align = desired_align;
15515 if (alg == libcall)
15517 gcc_assert (alg != no_stringop);
15519 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
15520 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15521 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
15526 gcc_unreachable ();
15528 size_needed = GET_MODE_SIZE (Pmode);
15530 case unrolled_loop:
15531 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
15533 case rep_prefix_8_byte:
15536 case rep_prefix_4_byte:
15539 case rep_prefix_1_byte:
15545 epilogue_size_needed = size_needed;
15547 /* Step 1: Prologue guard. */
15549 /* Alignment code needs count to be in register. */
15550 if (CONST_INT_P (count_exp) && desired_align > align)
15551 count_exp = force_reg (counter_mode (count_exp), count_exp);
15552 gcc_assert (desired_align >= 1 && align >= 1);
15554 /* Ensure that alignment prologue won't copy past end of block. */
15555 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15557 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15558 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15559 Make sure it is power of 2. */
15560 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15562 if (CONST_INT_P (count_exp))
15564 if (UINTVAL (count_exp) < (unsigned HOST_WIDE_INT)epilogue_size_needed)
15569 label = gen_label_rtx ();
15570 emit_cmp_and_jump_insns (count_exp,
15571 GEN_INT (epilogue_size_needed),
15572 LTU, 0, counter_mode (count_exp), 1, label);
15573 if (expected_size == -1 || expected_size < epilogue_size_needed)
15574 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15576 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15580 /* Emit code to decide on runtime whether library call or inline should be
15582 if (dynamic_check != -1)
15584 if (CONST_INT_P (count_exp))
15586 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
15588 emit_block_move_via_libcall (dst, src, count_exp, false);
15589 count_exp = const0_rtx;
15595 rtx hot_label = gen_label_rtx ();
15596 jump_around_label = gen_label_rtx ();
15597 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15598 LEU, 0, GET_MODE (count_exp), 1, hot_label);
15599 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15600 emit_block_move_via_libcall (dst, src, count_exp, false);
15601 emit_jump (jump_around_label);
15602 emit_label (hot_label);
15606 /* Step 2: Alignment prologue. */
15608 if (desired_align > align)
15610 /* Except for the first move in epilogue, we no longer know
15611 constant offset in aliasing info. It don't seems to worth
15612 the pain to maintain it for the first move, so throw away
15614 src = change_address (src, BLKmode, srcreg);
15615 dst = change_address (dst, BLKmode, destreg);
15616 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
15619 if (label && size_needed == 1)
15621 emit_label (label);
15622 LABEL_NUSES (label) = 1;
15626 /* Step 3: Main loop. */
15632 gcc_unreachable ();
15634 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15635 count_exp, QImode, 1, expected_size);
15638 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15639 count_exp, Pmode, 1, expected_size);
15641 case unrolled_loop:
15642 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
15643 registers for 4 temporaries anyway. */
15644 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
15645 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
15648 case rep_prefix_8_byte:
15649 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15652 case rep_prefix_4_byte:
15653 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15656 case rep_prefix_1_byte:
15657 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
15661 /* Adjust properly the offset of src and dest memory for aliasing. */
15662 if (CONST_INT_P (count_exp))
15664 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
15665 (count / size_needed) * size_needed);
15666 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15667 (count / size_needed) * size_needed);
15671 src = change_address (src, BLKmode, srcreg);
15672 dst = change_address (dst, BLKmode, destreg);
15675 /* Step 4: Epilogue to copy the remaining bytes. */
15679 /* When the main loop is done, COUNT_EXP might hold original count,
15680 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15681 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15682 bytes. Compensate if needed. */
15684 if (size_needed < epilogue_size_needed)
15687 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
15688 GEN_INT (size_needed - 1), count_exp, 1,
15690 if (tmp != count_exp)
15691 emit_move_insn (count_exp, tmp);
15693 emit_label (label);
15694 LABEL_NUSES (label) = 1;
15697 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15698 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
15699 epilogue_size_needed);
15700 if (jump_around_label)
15701 emit_label (jump_around_label);
15705 /* Helper function for memcpy. For QImode value 0xXY produce
15706 0xXYXYXYXY of wide specified by MODE. This is essentially
15707 a * 0x10101010, but we can do slightly better than
15708 synth_mult by unwinding the sequence by hand on CPUs with
15711 promote_duplicated_reg (enum machine_mode mode, rtx val)
15713 enum machine_mode valmode = GET_MODE (val);
15715 int nops = mode == DImode ? 3 : 2;
15717 gcc_assert (mode == SImode || mode == DImode);
15718 if (val == const0_rtx)
15719 return copy_to_mode_reg (mode, const0_rtx);
15720 if (CONST_INT_P (val))
15722 HOST_WIDE_INT v = INTVAL (val) & 255;
15726 if (mode == DImode)
15727 v |= (v << 16) << 16;
15728 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
15731 if (valmode == VOIDmode)
15733 if (valmode != QImode)
15734 val = gen_lowpart (QImode, val);
15735 if (mode == QImode)
15737 if (!TARGET_PARTIAL_REG_STALL)
15739 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
15740 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
15741 <= (ix86_cost->shift_const + ix86_cost->add) * nops
15742 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
15744 rtx reg = convert_modes (mode, QImode, val, true);
15745 tmp = promote_duplicated_reg (mode, const1_rtx);
15746 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
15751 rtx reg = convert_modes (mode, QImode, val, true);
15753 if (!TARGET_PARTIAL_REG_STALL)
15754 if (mode == SImode)
15755 emit_insn (gen_movsi_insv_1 (reg, reg));
15757 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
15760 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
15761 NULL, 1, OPTAB_DIRECT);
15763 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15765 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
15766 NULL, 1, OPTAB_DIRECT);
15767 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15768 if (mode == SImode)
15770 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
15771 NULL, 1, OPTAB_DIRECT);
15772 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
15777 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
15778 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
15779 alignment from ALIGN to DESIRED_ALIGN. */
15781 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
15786 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
15787 promoted_val = promote_duplicated_reg (DImode, val);
15788 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
15789 promoted_val = promote_duplicated_reg (SImode, val);
15790 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
15791 promoted_val = promote_duplicated_reg (HImode, val);
15793 promoted_val = val;
15795 return promoted_val;
15798 /* Expand string clear operation (bzero). Use i386 string operations when
15799 profitable. See expand_movmem comment for explanation of individual
15800 steps performed. */
15802 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
15803 rtx expected_align_exp, rtx expected_size_exp)
15808 rtx jump_around_label = NULL;
15809 HOST_WIDE_INT align = 1;
15810 unsigned HOST_WIDE_INT count = 0;
15811 HOST_WIDE_INT expected_size = -1;
15812 int size_needed = 0, epilogue_size_needed;
15813 int desired_align = 0;
15814 enum stringop_alg alg;
15815 rtx promoted_val = NULL;
15816 bool force_loopy_epilogue = false;
15819 if (CONST_INT_P (align_exp))
15820 align = INTVAL (align_exp);
15821 /* i386 can do misaligned access on reasonably increased cost. */
15822 if (CONST_INT_P (expected_align_exp)
15823 && INTVAL (expected_align_exp) > align)
15824 align = INTVAL (expected_align_exp);
15825 if (CONST_INT_P (count_exp))
15826 count = expected_size = INTVAL (count_exp);
15827 if (CONST_INT_P (expected_size_exp) && count == 0)
15828 expected_size = INTVAL (expected_size_exp);
15830 /* Make sure we don't need to care about overflow later on. */
15831 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
15834 /* Step 0: Decide on preferred algorithm, desired alignment and
15835 size of chunks to be copied by main loop. */
15837 alg = decide_alg (count, expected_size, true, &dynamic_check);
15838 desired_align = decide_alignment (align, alg, expected_size);
15840 if (!TARGET_ALIGN_STRINGOPS)
15841 align = desired_align;
15843 if (alg == libcall)
15845 gcc_assert (alg != no_stringop);
15847 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
15848 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
15853 gcc_unreachable ();
15855 size_needed = GET_MODE_SIZE (Pmode);
15857 case unrolled_loop:
15858 size_needed = GET_MODE_SIZE (Pmode) * 4;
15860 case rep_prefix_8_byte:
15863 case rep_prefix_4_byte:
15866 case rep_prefix_1_byte:
15871 epilogue_size_needed = size_needed;
15873 /* Step 1: Prologue guard. */
15875 /* Alignment code needs count to be in register. */
15876 if (CONST_INT_P (count_exp) && desired_align > align)
15878 enum machine_mode mode = SImode;
15879 if (TARGET_64BIT && (count & ~0xffffffff))
15881 count_exp = force_reg (mode, count_exp);
15883 /* Do the cheap promotion to allow better CSE across the
15884 main loop and epilogue (ie one load of the big constant in the
15885 front of all code. */
15886 if (CONST_INT_P (val_exp))
15887 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15888 desired_align, align);
15889 /* Ensure that alignment prologue won't copy past end of block. */
15890 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
15892 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
15893 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
15894 Make sure it is power of 2. */
15895 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
15897 /* To improve performance of small blocks, we jump around the VAL
15898 promoting mode. This mean that if the promoted VAL is not constant,
15899 we might not use it in the epilogue and have to use byte
15901 if (epilogue_size_needed > 2 && !promoted_val)
15902 force_loopy_epilogue = true;
15903 label = gen_label_rtx ();
15904 emit_cmp_and_jump_insns (count_exp,
15905 GEN_INT (epilogue_size_needed),
15906 LTU, 0, counter_mode (count_exp), 1, label);
15907 if (GET_CODE (count_exp) == CONST_INT)
15909 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
15910 predict_jump (REG_BR_PROB_BASE * 60 / 100);
15912 predict_jump (REG_BR_PROB_BASE * 20 / 100);
15914 if (dynamic_check != -1)
15916 rtx hot_label = gen_label_rtx ();
15917 jump_around_label = gen_label_rtx ();
15918 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
15919 LEU, 0, counter_mode (count_exp), 1, hot_label);
15920 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15921 set_storage_via_libcall (dst, count_exp, val_exp, false);
15922 emit_jump (jump_around_label);
15923 emit_label (hot_label);
15926 /* Step 2: Alignment prologue. */
15928 /* Do the expensive promotion once we branched off the small blocks. */
15930 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
15931 desired_align, align);
15932 gcc_assert (desired_align >= 1 && align >= 1);
15934 if (desired_align > align)
15936 /* Except for the first move in epilogue, we no longer know
15937 constant offset in aliasing info. It don't seems to worth
15938 the pain to maintain it for the first move, so throw away
15940 dst = change_address (dst, BLKmode, destreg);
15941 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
15944 if (label && size_needed == 1)
15946 emit_label (label);
15947 LABEL_NUSES (label) = 1;
15951 /* Step 3: Main loop. */
15957 gcc_unreachable ();
15959 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15960 count_exp, QImode, 1, expected_size);
15963 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15964 count_exp, Pmode, 1, expected_size);
15966 case unrolled_loop:
15967 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
15968 count_exp, Pmode, 4, expected_size);
15970 case rep_prefix_8_byte:
15971 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15974 case rep_prefix_4_byte:
15975 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15978 case rep_prefix_1_byte:
15979 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
15983 /* Adjust properly the offset of src and dest memory for aliasing. */
15984 if (CONST_INT_P (count_exp))
15985 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
15986 (count / size_needed) * size_needed);
15988 dst = change_address (dst, BLKmode, destreg);
15990 /* Step 4: Epilogue to copy the remaining bytes. */
15994 /* When the main loop is done, COUNT_EXP might hold original count,
15995 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
15996 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
15997 bytes. Compensate if needed. */
15999 if (size_needed < desired_align - align)
16002 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
16003 GEN_INT (size_needed - 1), count_exp, 1,
16005 size_needed = desired_align - align + 1;
16006 if (tmp != count_exp)
16007 emit_move_insn (count_exp, tmp);
16009 emit_label (label);
16010 LABEL_NUSES (label) = 1;
16012 if (count_exp != const0_rtx && epilogue_size_needed > 1)
16014 if (force_loopy_epilogue)
16015 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
16018 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
16021 if (jump_around_label)
16022 emit_label (jump_around_label);
16026 /* Expand the appropriate insns for doing strlen if not just doing
16029 out = result, initialized with the start address
16030 align_rtx = alignment of the address.
16031 scratch = scratch register, initialized with the startaddress when
16032 not aligned, otherwise undefined
16034 This is just the body. It needs the initializations mentioned above and
16035 some address computing at the end. These things are done in i386.md. */
16038 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
16042 rtx align_2_label = NULL_RTX;
16043 rtx align_3_label = NULL_RTX;
16044 rtx align_4_label = gen_label_rtx ();
16045 rtx end_0_label = gen_label_rtx ();
16047 rtx tmpreg = gen_reg_rtx (SImode);
16048 rtx scratch = gen_reg_rtx (SImode);
16052 if (CONST_INT_P (align_rtx))
16053 align = INTVAL (align_rtx);
16055 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
16057 /* Is there a known alignment and is it less than 4? */
16060 rtx scratch1 = gen_reg_rtx (Pmode);
16061 emit_move_insn (scratch1, out);
16062 /* Is there a known alignment and is it not 2? */
16065 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
16066 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
16068 /* Leave just the 3 lower bits. */
16069 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
16070 NULL_RTX, 0, OPTAB_WIDEN);
16072 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
16073 Pmode, 1, align_4_label);
16074 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
16075 Pmode, 1, align_2_label);
16076 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
16077 Pmode, 1, align_3_label);
16081 /* Since the alignment is 2, we have to check 2 or 0 bytes;
16082 check if is aligned to 4 - byte. */
16084 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
16085 NULL_RTX, 0, OPTAB_WIDEN);
16087 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
16088 Pmode, 1, align_4_label);
16091 mem = change_address (src, QImode, out);
16093 /* Now compare the bytes. */
16095 /* Compare the first n unaligned byte on a byte per byte basis. */
16096 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
16097 QImode, 1, end_0_label);
16099 /* Increment the address. */
16101 emit_insn (gen_adddi3 (out, out, const1_rtx));
16103 emit_insn (gen_addsi3 (out, out, const1_rtx));
16105 /* Not needed with an alignment of 2 */
16108 emit_label (align_2_label);
16110 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16114 emit_insn (gen_adddi3 (out, out, const1_rtx));
16116 emit_insn (gen_addsi3 (out, out, const1_rtx));
16118 emit_label (align_3_label);
16121 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
16125 emit_insn (gen_adddi3 (out, out, const1_rtx));
16127 emit_insn (gen_addsi3 (out, out, const1_rtx));
16130 /* Generate loop to check 4 bytes at a time. It is not a good idea to
16131 align this loop. It gives only huge programs, but does not help to
16133 emit_label (align_4_label);
16135 mem = change_address (src, SImode, out);
16136 emit_move_insn (scratch, mem);
16138 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
16140 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
16142 /* This formula yields a nonzero result iff one of the bytes is zero.
16143 This saves three branches inside loop and many cycles. */
16145 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
16146 emit_insn (gen_one_cmplsi2 (scratch, scratch));
16147 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
16148 emit_insn (gen_andsi3 (tmpreg, tmpreg,
16149 gen_int_mode (0x80808080, SImode)));
16150 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
16155 rtx reg = gen_reg_rtx (SImode);
16156 rtx reg2 = gen_reg_rtx (Pmode);
16157 emit_move_insn (reg, tmpreg);
16158 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
16160 /* If zero is not in the first two bytes, move two bytes forward. */
16161 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16162 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16163 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16164 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
16165 gen_rtx_IF_THEN_ELSE (SImode, tmp,
16168 /* Emit lea manually to avoid clobbering of flags. */
16169 emit_insn (gen_rtx_SET (SImode, reg2,
16170 gen_rtx_PLUS (Pmode, out, const2_rtx)));
16172 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16173 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
16174 emit_insn (gen_rtx_SET (VOIDmode, out,
16175 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
16182 rtx end_2_label = gen_label_rtx ();
16183 /* Is zero in the first two bytes? */
16185 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
16186 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
16187 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
16188 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
16189 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
16191 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
16192 JUMP_LABEL (tmp) = end_2_label;
16194 /* Not in the first two. Move two bytes forward. */
16195 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
16197 emit_insn (gen_adddi3 (out, out, const2_rtx));
16199 emit_insn (gen_addsi3 (out, out, const2_rtx));
16201 emit_label (end_2_label);
16205 /* Avoid branch in fixing the byte. */
16206 tmpreg = gen_lowpart (QImode, tmpreg);
16207 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
16208 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
16210 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
16212 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
16214 emit_label (end_0_label);
16217 /* Expand strlen. */
16220 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
16222 rtx addr, scratch1, scratch2, scratch3, scratch4;
16224 /* The generic case of strlen expander is long. Avoid it's
16225 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
16227 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16228 && !TARGET_INLINE_ALL_STRINGOPS
16230 && (!CONST_INT_P (align) || INTVAL (align) < 4))
16233 addr = force_reg (Pmode, XEXP (src, 0));
16234 scratch1 = gen_reg_rtx (Pmode);
16236 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
16239 /* Well it seems that some optimizer does not combine a call like
16240 foo(strlen(bar), strlen(bar));
16241 when the move and the subtraction is done here. It does calculate
16242 the length just once when these instructions are done inside of
16243 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
16244 often used and I use one fewer register for the lifetime of
16245 output_strlen_unroll() this is better. */
16247 emit_move_insn (out, addr);
16249 ix86_expand_strlensi_unroll_1 (out, src, align);
16251 /* strlensi_unroll_1 returns the address of the zero at the end of
16252 the string, like memchr(), so compute the length by subtracting
16253 the start address. */
16255 emit_insn (gen_subdi3 (out, out, addr));
16257 emit_insn (gen_subsi3 (out, out, addr));
16263 /* Can't use this if the user has appropriated eax, ecx, or edi. */
16264 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
16267 scratch2 = gen_reg_rtx (Pmode);
16268 scratch3 = gen_reg_rtx (Pmode);
16269 scratch4 = force_reg (Pmode, constm1_rtx);
16271 emit_move_insn (scratch3, addr);
16272 eoschar = force_reg (QImode, eoschar);
16274 src = replace_equiv_address_nv (src, scratch3);
16276 /* If .md starts supporting :P, this can be done in .md. */
16277 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
16278 scratch4), UNSPEC_SCAS);
16279 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
16282 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
16283 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
16287 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
16288 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
16294 /* For given symbol (function) construct code to compute address of it's PLT
16295 entry in large x86-64 PIC model. */
16297 construct_plt_address (rtx symbol)
16299 rtx tmp = gen_reg_rtx (Pmode);
16300 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
16302 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
16303 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
16305 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
16306 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
16311 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
16312 rtx callarg2 ATTRIBUTE_UNUSED,
16313 rtx pop, int sibcall)
16315 rtx use = NULL, call;
16317 if (pop == const0_rtx)
16319 gcc_assert (!TARGET_64BIT || !pop);
16321 if (TARGET_MACHO && !TARGET_64BIT)
16324 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
16325 fnaddr = machopic_indirect_call_target (fnaddr);
16330 /* Static functions and indirect calls don't need the pic register. */
16331 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
16332 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16333 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
16334 use_reg (&use, pic_offset_table_rtx);
16337 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
16339 rtx al = gen_rtx_REG (QImode, AX_REG);
16340 emit_move_insn (al, callarg2);
16341 use_reg (&use, al);
16344 if (ix86_cmodel == CM_LARGE_PIC
16345 && GET_CODE (fnaddr) == MEM
16346 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
16347 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
16348 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
16349 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
16351 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16352 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16354 if (sibcall && TARGET_64BIT
16355 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
16358 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
16359 fnaddr = gen_rtx_REG (Pmode, R11_REG);
16360 emit_move_insn (fnaddr, addr);
16361 fnaddr = gen_rtx_MEM (QImode, fnaddr);
16364 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
16366 call = gen_rtx_SET (VOIDmode, retval, call);
16369 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
16370 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
16371 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
16374 call = emit_call_insn (call);
16376 CALL_INSN_FUNCTION_USAGE (call) = use;
16380 /* Clear stack slot assignments remembered from previous functions.
16381 This is called from INIT_EXPANDERS once before RTL is emitted for each
16384 static struct machine_function *
16385 ix86_init_machine_status (void)
16387 struct machine_function *f;
16389 f = GGC_CNEW (struct machine_function);
16390 f->use_fast_prologue_epilogue_nregs = -1;
16391 f->tls_descriptor_call_expanded_p = 0;
16396 /* Return a MEM corresponding to a stack slot with mode MODE.
16397 Allocate a new slot if necessary.
16399 The RTL for a function can have several slots available: N is
16400 which slot to use. */
16403 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
16405 struct stack_local_entry *s;
16407 gcc_assert (n < MAX_386_STACK_LOCALS);
16409 /* Virtual slot is valid only before vregs are instantiated. */
16410 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
16412 for (s = ix86_stack_locals; s; s = s->next)
16413 if (s->mode == mode && s->n == n)
16414 return copy_rtx (s->rtl);
16416 s = (struct stack_local_entry *)
16417 ggc_alloc (sizeof (struct stack_local_entry));
16420 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
16422 s->next = ix86_stack_locals;
16423 ix86_stack_locals = s;
16427 /* Construct the SYMBOL_REF for the tls_get_addr function. */
16429 static GTY(()) rtx ix86_tls_symbol;
16431 ix86_tls_get_addr (void)
16434 if (!ix86_tls_symbol)
16436 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
16437 (TARGET_ANY_GNU_TLS
16439 ? "___tls_get_addr"
16440 : "__tls_get_addr");
16443 return ix86_tls_symbol;
16446 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
16448 static GTY(()) rtx ix86_tls_module_base_symbol;
16450 ix86_tls_module_base (void)
16453 if (!ix86_tls_module_base_symbol)
16455 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
16456 "_TLS_MODULE_BASE_");
16457 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
16458 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
16461 return ix86_tls_module_base_symbol;
16464 /* Calculate the length of the memory address in the instruction
16465 encoding. Does not include the one-byte modrm, opcode, or prefix. */
16468 memory_address_length (rtx addr)
16470 struct ix86_address parts;
16471 rtx base, index, disp;
16475 if (GET_CODE (addr) == PRE_DEC
16476 || GET_CODE (addr) == POST_INC
16477 || GET_CODE (addr) == PRE_MODIFY
16478 || GET_CODE (addr) == POST_MODIFY)
16481 ok = ix86_decompose_address (addr, &parts);
16484 if (parts.base && GET_CODE (parts.base) == SUBREG)
16485 parts.base = SUBREG_REG (parts.base);
16486 if (parts.index && GET_CODE (parts.index) == SUBREG)
16487 parts.index = SUBREG_REG (parts.index);
16490 index = parts.index;
16495 - esp as the base always wants an index,
16496 - ebp as the base always wants a displacement. */
16498 /* Register Indirect. */
16499 if (base && !index && !disp)
16501 /* esp (for its index) and ebp (for its displacement) need
16502 the two-byte modrm form. */
16503 if (addr == stack_pointer_rtx
16504 || addr == arg_pointer_rtx
16505 || addr == frame_pointer_rtx
16506 || addr == hard_frame_pointer_rtx)
16510 /* Direct Addressing. */
16511 else if (disp && !base && !index)
16516 /* Find the length of the displacement constant. */
16519 if (base && satisfies_constraint_K (disp))
16524 /* ebp always wants a displacement. */
16525 else if (base == hard_frame_pointer_rtx)
16528 /* An index requires the two-byte modrm form.... */
16530 /* ...like esp, which always wants an index. */
16531 || base == stack_pointer_rtx
16532 || base == arg_pointer_rtx
16533 || base == frame_pointer_rtx)
16540 /* Compute default value for "length_immediate" attribute. When SHORTFORM
16541 is set, expect that insn have 8bit immediate alternative. */
16543 ix86_attr_length_immediate_default (rtx insn, int shortform)
16547 extract_insn_cached (insn);
16548 for (i = recog_data.n_operands - 1; i >= 0; --i)
16549 if (CONSTANT_P (recog_data.operand[i]))
16552 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
16556 switch (get_attr_mode (insn))
16567 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
16572 fatal_insn ("unknown insn mode", insn);
16578 /* Compute default value for "length_address" attribute. */
16580 ix86_attr_length_address_default (rtx insn)
16584 if (get_attr_type (insn) == TYPE_LEA)
16586 rtx set = PATTERN (insn);
16588 if (GET_CODE (set) == PARALLEL)
16589 set = XVECEXP (set, 0, 0);
16591 gcc_assert (GET_CODE (set) == SET);
16593 return memory_address_length (SET_SRC (set));
16596 extract_insn_cached (insn);
16597 for (i = recog_data.n_operands - 1; i >= 0; --i)
16598 if (MEM_P (recog_data.operand[i]))
16600 return memory_address_length (XEXP (recog_data.operand[i], 0));
16606 /* Return the maximum number of instructions a cpu can issue. */
16609 ix86_issue_rate (void)
16613 case PROCESSOR_PENTIUM:
16617 case PROCESSOR_PENTIUMPRO:
16618 case PROCESSOR_PENTIUM4:
16619 case PROCESSOR_ATHLON:
16621 case PROCESSOR_AMDFAM10:
16622 case PROCESSOR_NOCONA:
16623 case PROCESSOR_GENERIC32:
16624 case PROCESSOR_GENERIC64:
16627 case PROCESSOR_CORE2:
16635 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
16636 by DEP_INSN and nothing set by DEP_INSN. */
16639 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16643 /* Simplify the test for uninteresting insns. */
16644 if (insn_type != TYPE_SETCC
16645 && insn_type != TYPE_ICMOV
16646 && insn_type != TYPE_FCMOV
16647 && insn_type != TYPE_IBR)
16650 if ((set = single_set (dep_insn)) != 0)
16652 set = SET_DEST (set);
16655 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
16656 && XVECLEN (PATTERN (dep_insn), 0) == 2
16657 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
16658 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
16660 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16661 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
16666 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
16669 /* This test is true if the dependent insn reads the flags but
16670 not any other potentially set register. */
16671 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
16674 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
16680 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
16681 address with operands set by DEP_INSN. */
16684 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
16688 if (insn_type == TYPE_LEA
16691 addr = PATTERN (insn);
16693 if (GET_CODE (addr) == PARALLEL)
16694 addr = XVECEXP (addr, 0, 0);
16696 gcc_assert (GET_CODE (addr) == SET);
16698 addr = SET_SRC (addr);
16703 extract_insn_cached (insn);
16704 for (i = recog_data.n_operands - 1; i >= 0; --i)
16705 if (MEM_P (recog_data.operand[i]))
16707 addr = XEXP (recog_data.operand[i], 0);
16714 return modified_in_p (addr, dep_insn);
16718 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16720 enum attr_type insn_type, dep_insn_type;
16721 enum attr_memory memory;
16723 int dep_insn_code_number;
16725 /* Anti and output dependencies have zero cost on all CPUs. */
16726 if (REG_NOTE_KIND (link) != 0)
16729 dep_insn_code_number = recog_memoized (dep_insn);
16731 /* If we can't recognize the insns, we can't really do anything. */
16732 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
16735 insn_type = get_attr_type (insn);
16736 dep_insn_type = get_attr_type (dep_insn);
16740 case PROCESSOR_PENTIUM:
16741 /* Address Generation Interlock adds a cycle of latency. */
16742 if (ix86_agi_dependent (insn, dep_insn, insn_type))
16745 /* ??? Compares pair with jump/setcc. */
16746 if (ix86_flags_dependent (insn, dep_insn, insn_type))
16749 /* Floating point stores require value to be ready one cycle earlier. */
16750 if (insn_type == TYPE_FMOV
16751 && get_attr_memory (insn) == MEMORY_STORE
16752 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16756 case PROCESSOR_PENTIUMPRO:
16757 memory = get_attr_memory (insn);
16759 /* INT->FP conversion is expensive. */
16760 if (get_attr_fp_int_src (dep_insn))
16763 /* There is one cycle extra latency between an FP op and a store. */
16764 if (insn_type == TYPE_FMOV
16765 && (set = single_set (dep_insn)) != NULL_RTX
16766 && (set2 = single_set (insn)) != NULL_RTX
16767 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
16768 && MEM_P (SET_DEST (set2)))
16771 /* Show ability of reorder buffer to hide latency of load by executing
16772 in parallel with previous instruction in case
16773 previous instruction is not needed to compute the address. */
16774 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16775 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16777 /* Claim moves to take one cycle, as core can issue one load
16778 at time and the next load can start cycle later. */
16779 if (dep_insn_type == TYPE_IMOV
16780 || dep_insn_type == TYPE_FMOV)
16788 memory = get_attr_memory (insn);
16790 /* The esp dependency is resolved before the instruction is really
16792 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
16793 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
16796 /* INT->FP conversion is expensive. */
16797 if (get_attr_fp_int_src (dep_insn))
16800 /* Show ability of reorder buffer to hide latency of load by executing
16801 in parallel with previous instruction in case
16802 previous instruction is not needed to compute the address. */
16803 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16804 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16806 /* Claim moves to take one cycle, as core can issue one load
16807 at time and the next load can start cycle later. */
16808 if (dep_insn_type == TYPE_IMOV
16809 || dep_insn_type == TYPE_FMOV)
16818 case PROCESSOR_ATHLON:
16820 case PROCESSOR_AMDFAM10:
16821 case PROCESSOR_GENERIC32:
16822 case PROCESSOR_GENERIC64:
16823 memory = get_attr_memory (insn);
16825 /* Show ability of reorder buffer to hide latency of load by executing
16826 in parallel with previous instruction in case
16827 previous instruction is not needed to compute the address. */
16828 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
16829 && !ix86_agi_dependent (insn, dep_insn, insn_type))
16831 enum attr_unit unit = get_attr_unit (insn);
16834 /* Because of the difference between the length of integer and
16835 floating unit pipeline preparation stages, the memory operands
16836 for floating point are cheaper.
16838 ??? For Athlon it the difference is most probably 2. */
16839 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
16842 loadcost = TARGET_ATHLON ? 2 : 0;
16844 if (cost >= loadcost)
16857 /* How many alternative schedules to try. This should be as wide as the
16858 scheduling freedom in the DFA, but no wider. Making this value too
16859 large results extra work for the scheduler. */
16862 ia32_multipass_dfa_lookahead (void)
16866 case PROCESSOR_PENTIUM:
16869 case PROCESSOR_PENTIUMPRO:
16879 /* Compute the alignment given to a constant that is being placed in memory.
16880 EXP is the constant and ALIGN is the alignment that the object would
16882 The value of this function is used instead of that alignment to align
16886 ix86_constant_alignment (tree exp, int align)
16888 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
16889 || TREE_CODE (exp) == INTEGER_CST)
16891 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
16893 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
16896 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
16897 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
16898 return BITS_PER_WORD;
16903 /* Compute the alignment for a static variable.
16904 TYPE is the data type, and ALIGN is the alignment that
16905 the object would ordinarily have. The value of this function is used
16906 instead of that alignment to align the object. */
16909 ix86_data_alignment (tree type, int align)
16911 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
16913 if (AGGREGATE_TYPE_P (type)
16914 && TYPE_SIZE (type)
16915 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16916 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
16917 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
16918 && align < max_align)
16921 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16922 to 16byte boundary. */
16925 if (AGGREGATE_TYPE_P (type)
16926 && TYPE_SIZE (type)
16927 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16928 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
16929 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16933 if (TREE_CODE (type) == ARRAY_TYPE)
16935 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16937 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16940 else if (TREE_CODE (type) == COMPLEX_TYPE)
16943 if (TYPE_MODE (type) == DCmode && align < 64)
16945 if (TYPE_MODE (type) == XCmode && align < 128)
16948 else if ((TREE_CODE (type) == RECORD_TYPE
16949 || TREE_CODE (type) == UNION_TYPE
16950 || TREE_CODE (type) == QUAL_UNION_TYPE)
16951 && TYPE_FIELDS (type))
16953 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
16955 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
16958 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
16959 || TREE_CODE (type) == INTEGER_TYPE)
16961 if (TYPE_MODE (type) == DFmode && align < 64)
16963 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16970 /* Compute the alignment for a local variable.
16971 TYPE is the data type, and ALIGN is the alignment that
16972 the object would ordinarily have. The value of this macro is used
16973 instead of that alignment to align the object. */
16976 ix86_local_alignment (tree type, int align)
16978 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
16979 to 16byte boundary. */
16982 if (AGGREGATE_TYPE_P (type)
16983 && TYPE_SIZE (type)
16984 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
16985 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
16986 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
16989 if (TREE_CODE (type) == ARRAY_TYPE)
16991 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
16993 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
16996 else if (TREE_CODE (type) == COMPLEX_TYPE)
16998 if (TYPE_MODE (type) == DCmode && align < 64)
17000 if (TYPE_MODE (type) == XCmode && align < 128)
17003 else if ((TREE_CODE (type) == RECORD_TYPE
17004 || TREE_CODE (type) == UNION_TYPE
17005 || TREE_CODE (type) == QUAL_UNION_TYPE)
17006 && TYPE_FIELDS (type))
17008 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
17010 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
17013 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
17014 || TREE_CODE (type) == INTEGER_TYPE)
17017 if (TYPE_MODE (type) == DFmode && align < 64)
17019 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
17025 /* Emit RTL insns to initialize the variable parts of a trampoline.
17026 FNADDR is an RTX for the address of the function's pure code.
17027 CXT is an RTX for the static chain value for the function. */
17029 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
17033 /* Compute offset from the end of the jmp to the target function. */
17034 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
17035 plus_constant (tramp, 10),
17036 NULL_RTX, 1, OPTAB_DIRECT);
17037 emit_move_insn (gen_rtx_MEM (QImode, tramp),
17038 gen_int_mode (0xb9, QImode));
17039 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
17040 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
17041 gen_int_mode (0xe9, QImode));
17042 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
17047 /* Try to load address using shorter movl instead of movabs.
17048 We may want to support movq for kernel mode, but kernel does not use
17049 trampolines at the moment. */
17050 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
17052 fnaddr = copy_to_mode_reg (DImode, fnaddr);
17053 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17054 gen_int_mode (0xbb41, HImode));
17055 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
17056 gen_lowpart (SImode, fnaddr));
17061 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17062 gen_int_mode (0xbb49, HImode));
17063 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
17067 /* Load static chain using movabs to r10. */
17068 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17069 gen_int_mode (0xba49, HImode));
17070 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
17073 /* Jump to the r11 */
17074 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
17075 gen_int_mode (0xff49, HImode));
17076 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
17077 gen_int_mode (0xe3, QImode));
17079 gcc_assert (offset <= TRAMPOLINE_SIZE);
17082 #ifdef ENABLE_EXECUTE_STACK
17083 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
17084 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
17088 /* Codes for all the SSE/MMX builtins. */
17091 IX86_BUILTIN_ADDPS,
17092 IX86_BUILTIN_ADDSS,
17093 IX86_BUILTIN_DIVPS,
17094 IX86_BUILTIN_DIVSS,
17095 IX86_BUILTIN_MULPS,
17096 IX86_BUILTIN_MULSS,
17097 IX86_BUILTIN_SUBPS,
17098 IX86_BUILTIN_SUBSS,
17100 IX86_BUILTIN_CMPEQPS,
17101 IX86_BUILTIN_CMPLTPS,
17102 IX86_BUILTIN_CMPLEPS,
17103 IX86_BUILTIN_CMPGTPS,
17104 IX86_BUILTIN_CMPGEPS,
17105 IX86_BUILTIN_CMPNEQPS,
17106 IX86_BUILTIN_CMPNLTPS,
17107 IX86_BUILTIN_CMPNLEPS,
17108 IX86_BUILTIN_CMPNGTPS,
17109 IX86_BUILTIN_CMPNGEPS,
17110 IX86_BUILTIN_CMPORDPS,
17111 IX86_BUILTIN_CMPUNORDPS,
17112 IX86_BUILTIN_CMPEQSS,
17113 IX86_BUILTIN_CMPLTSS,
17114 IX86_BUILTIN_CMPLESS,
17115 IX86_BUILTIN_CMPNEQSS,
17116 IX86_BUILTIN_CMPNLTSS,
17117 IX86_BUILTIN_CMPNLESS,
17118 IX86_BUILTIN_CMPNGTSS,
17119 IX86_BUILTIN_CMPNGESS,
17120 IX86_BUILTIN_CMPORDSS,
17121 IX86_BUILTIN_CMPUNORDSS,
17123 IX86_BUILTIN_COMIEQSS,
17124 IX86_BUILTIN_COMILTSS,
17125 IX86_BUILTIN_COMILESS,
17126 IX86_BUILTIN_COMIGTSS,
17127 IX86_BUILTIN_COMIGESS,
17128 IX86_BUILTIN_COMINEQSS,
17129 IX86_BUILTIN_UCOMIEQSS,
17130 IX86_BUILTIN_UCOMILTSS,
17131 IX86_BUILTIN_UCOMILESS,
17132 IX86_BUILTIN_UCOMIGTSS,
17133 IX86_BUILTIN_UCOMIGESS,
17134 IX86_BUILTIN_UCOMINEQSS,
17136 IX86_BUILTIN_CVTPI2PS,
17137 IX86_BUILTIN_CVTPS2PI,
17138 IX86_BUILTIN_CVTSI2SS,
17139 IX86_BUILTIN_CVTSI642SS,
17140 IX86_BUILTIN_CVTSS2SI,
17141 IX86_BUILTIN_CVTSS2SI64,
17142 IX86_BUILTIN_CVTTPS2PI,
17143 IX86_BUILTIN_CVTTSS2SI,
17144 IX86_BUILTIN_CVTTSS2SI64,
17146 IX86_BUILTIN_MAXPS,
17147 IX86_BUILTIN_MAXSS,
17148 IX86_BUILTIN_MINPS,
17149 IX86_BUILTIN_MINSS,
17151 IX86_BUILTIN_LOADUPS,
17152 IX86_BUILTIN_STOREUPS,
17153 IX86_BUILTIN_MOVSS,
17155 IX86_BUILTIN_MOVHLPS,
17156 IX86_BUILTIN_MOVLHPS,
17157 IX86_BUILTIN_LOADHPS,
17158 IX86_BUILTIN_LOADLPS,
17159 IX86_BUILTIN_STOREHPS,
17160 IX86_BUILTIN_STORELPS,
17162 IX86_BUILTIN_MASKMOVQ,
17163 IX86_BUILTIN_MOVMSKPS,
17164 IX86_BUILTIN_PMOVMSKB,
17166 IX86_BUILTIN_MOVNTPS,
17167 IX86_BUILTIN_MOVNTQ,
17169 IX86_BUILTIN_LOADDQU,
17170 IX86_BUILTIN_STOREDQU,
17172 IX86_BUILTIN_PACKSSWB,
17173 IX86_BUILTIN_PACKSSDW,
17174 IX86_BUILTIN_PACKUSWB,
17176 IX86_BUILTIN_PADDB,
17177 IX86_BUILTIN_PADDW,
17178 IX86_BUILTIN_PADDD,
17179 IX86_BUILTIN_PADDQ,
17180 IX86_BUILTIN_PADDSB,
17181 IX86_BUILTIN_PADDSW,
17182 IX86_BUILTIN_PADDUSB,
17183 IX86_BUILTIN_PADDUSW,
17184 IX86_BUILTIN_PSUBB,
17185 IX86_BUILTIN_PSUBW,
17186 IX86_BUILTIN_PSUBD,
17187 IX86_BUILTIN_PSUBQ,
17188 IX86_BUILTIN_PSUBSB,
17189 IX86_BUILTIN_PSUBSW,
17190 IX86_BUILTIN_PSUBUSB,
17191 IX86_BUILTIN_PSUBUSW,
17194 IX86_BUILTIN_PANDN,
17198 IX86_BUILTIN_PAVGB,
17199 IX86_BUILTIN_PAVGW,
17201 IX86_BUILTIN_PCMPEQB,
17202 IX86_BUILTIN_PCMPEQW,
17203 IX86_BUILTIN_PCMPEQD,
17204 IX86_BUILTIN_PCMPGTB,
17205 IX86_BUILTIN_PCMPGTW,
17206 IX86_BUILTIN_PCMPGTD,
17208 IX86_BUILTIN_PMADDWD,
17210 IX86_BUILTIN_PMAXSW,
17211 IX86_BUILTIN_PMAXUB,
17212 IX86_BUILTIN_PMINSW,
17213 IX86_BUILTIN_PMINUB,
17215 IX86_BUILTIN_PMULHUW,
17216 IX86_BUILTIN_PMULHW,
17217 IX86_BUILTIN_PMULLW,
17219 IX86_BUILTIN_PSADBW,
17220 IX86_BUILTIN_PSHUFW,
17222 IX86_BUILTIN_PSLLW,
17223 IX86_BUILTIN_PSLLD,
17224 IX86_BUILTIN_PSLLQ,
17225 IX86_BUILTIN_PSRAW,
17226 IX86_BUILTIN_PSRAD,
17227 IX86_BUILTIN_PSRLW,
17228 IX86_BUILTIN_PSRLD,
17229 IX86_BUILTIN_PSRLQ,
17230 IX86_BUILTIN_PSLLWI,
17231 IX86_BUILTIN_PSLLDI,
17232 IX86_BUILTIN_PSLLQI,
17233 IX86_BUILTIN_PSRAWI,
17234 IX86_BUILTIN_PSRADI,
17235 IX86_BUILTIN_PSRLWI,
17236 IX86_BUILTIN_PSRLDI,
17237 IX86_BUILTIN_PSRLQI,
17239 IX86_BUILTIN_PUNPCKHBW,
17240 IX86_BUILTIN_PUNPCKHWD,
17241 IX86_BUILTIN_PUNPCKHDQ,
17242 IX86_BUILTIN_PUNPCKLBW,
17243 IX86_BUILTIN_PUNPCKLWD,
17244 IX86_BUILTIN_PUNPCKLDQ,
17246 IX86_BUILTIN_SHUFPS,
17248 IX86_BUILTIN_RCPPS,
17249 IX86_BUILTIN_RCPSS,
17250 IX86_BUILTIN_RSQRTPS,
17251 IX86_BUILTIN_RSQRTPS_NR,
17252 IX86_BUILTIN_RSQRTSS,
17253 IX86_BUILTIN_RSQRTF,
17254 IX86_BUILTIN_SQRTPS,
17255 IX86_BUILTIN_SQRTPS_NR,
17256 IX86_BUILTIN_SQRTSS,
17258 IX86_BUILTIN_UNPCKHPS,
17259 IX86_BUILTIN_UNPCKLPS,
17261 IX86_BUILTIN_ANDPS,
17262 IX86_BUILTIN_ANDNPS,
17264 IX86_BUILTIN_XORPS,
17267 IX86_BUILTIN_LDMXCSR,
17268 IX86_BUILTIN_STMXCSR,
17269 IX86_BUILTIN_SFENCE,
17271 /* 3DNow! Original */
17272 IX86_BUILTIN_FEMMS,
17273 IX86_BUILTIN_PAVGUSB,
17274 IX86_BUILTIN_PF2ID,
17275 IX86_BUILTIN_PFACC,
17276 IX86_BUILTIN_PFADD,
17277 IX86_BUILTIN_PFCMPEQ,
17278 IX86_BUILTIN_PFCMPGE,
17279 IX86_BUILTIN_PFCMPGT,
17280 IX86_BUILTIN_PFMAX,
17281 IX86_BUILTIN_PFMIN,
17282 IX86_BUILTIN_PFMUL,
17283 IX86_BUILTIN_PFRCP,
17284 IX86_BUILTIN_PFRCPIT1,
17285 IX86_BUILTIN_PFRCPIT2,
17286 IX86_BUILTIN_PFRSQIT1,
17287 IX86_BUILTIN_PFRSQRT,
17288 IX86_BUILTIN_PFSUB,
17289 IX86_BUILTIN_PFSUBR,
17290 IX86_BUILTIN_PI2FD,
17291 IX86_BUILTIN_PMULHRW,
17293 /* 3DNow! Athlon Extensions */
17294 IX86_BUILTIN_PF2IW,
17295 IX86_BUILTIN_PFNACC,
17296 IX86_BUILTIN_PFPNACC,
17297 IX86_BUILTIN_PI2FW,
17298 IX86_BUILTIN_PSWAPDSI,
17299 IX86_BUILTIN_PSWAPDSF,
17302 IX86_BUILTIN_ADDPD,
17303 IX86_BUILTIN_ADDSD,
17304 IX86_BUILTIN_DIVPD,
17305 IX86_BUILTIN_DIVSD,
17306 IX86_BUILTIN_MULPD,
17307 IX86_BUILTIN_MULSD,
17308 IX86_BUILTIN_SUBPD,
17309 IX86_BUILTIN_SUBSD,
17311 IX86_BUILTIN_CMPEQPD,
17312 IX86_BUILTIN_CMPLTPD,
17313 IX86_BUILTIN_CMPLEPD,
17314 IX86_BUILTIN_CMPGTPD,
17315 IX86_BUILTIN_CMPGEPD,
17316 IX86_BUILTIN_CMPNEQPD,
17317 IX86_BUILTIN_CMPNLTPD,
17318 IX86_BUILTIN_CMPNLEPD,
17319 IX86_BUILTIN_CMPNGTPD,
17320 IX86_BUILTIN_CMPNGEPD,
17321 IX86_BUILTIN_CMPORDPD,
17322 IX86_BUILTIN_CMPUNORDPD,
17323 IX86_BUILTIN_CMPEQSD,
17324 IX86_BUILTIN_CMPLTSD,
17325 IX86_BUILTIN_CMPLESD,
17326 IX86_BUILTIN_CMPNEQSD,
17327 IX86_BUILTIN_CMPNLTSD,
17328 IX86_BUILTIN_CMPNLESD,
17329 IX86_BUILTIN_CMPORDSD,
17330 IX86_BUILTIN_CMPUNORDSD,
17332 IX86_BUILTIN_COMIEQSD,
17333 IX86_BUILTIN_COMILTSD,
17334 IX86_BUILTIN_COMILESD,
17335 IX86_BUILTIN_COMIGTSD,
17336 IX86_BUILTIN_COMIGESD,
17337 IX86_BUILTIN_COMINEQSD,
17338 IX86_BUILTIN_UCOMIEQSD,
17339 IX86_BUILTIN_UCOMILTSD,
17340 IX86_BUILTIN_UCOMILESD,
17341 IX86_BUILTIN_UCOMIGTSD,
17342 IX86_BUILTIN_UCOMIGESD,
17343 IX86_BUILTIN_UCOMINEQSD,
17345 IX86_BUILTIN_MAXPD,
17346 IX86_BUILTIN_MAXSD,
17347 IX86_BUILTIN_MINPD,
17348 IX86_BUILTIN_MINSD,
17350 IX86_BUILTIN_ANDPD,
17351 IX86_BUILTIN_ANDNPD,
17353 IX86_BUILTIN_XORPD,
17355 IX86_BUILTIN_SQRTPD,
17356 IX86_BUILTIN_SQRTSD,
17358 IX86_BUILTIN_UNPCKHPD,
17359 IX86_BUILTIN_UNPCKLPD,
17361 IX86_BUILTIN_SHUFPD,
17363 IX86_BUILTIN_LOADUPD,
17364 IX86_BUILTIN_STOREUPD,
17365 IX86_BUILTIN_MOVSD,
17367 IX86_BUILTIN_LOADHPD,
17368 IX86_BUILTIN_LOADLPD,
17370 IX86_BUILTIN_CVTDQ2PD,
17371 IX86_BUILTIN_CVTDQ2PS,
17373 IX86_BUILTIN_CVTPD2DQ,
17374 IX86_BUILTIN_CVTPD2PI,
17375 IX86_BUILTIN_CVTPD2PS,
17376 IX86_BUILTIN_CVTTPD2DQ,
17377 IX86_BUILTIN_CVTTPD2PI,
17379 IX86_BUILTIN_CVTPI2PD,
17380 IX86_BUILTIN_CVTSI2SD,
17381 IX86_BUILTIN_CVTSI642SD,
17383 IX86_BUILTIN_CVTSD2SI,
17384 IX86_BUILTIN_CVTSD2SI64,
17385 IX86_BUILTIN_CVTSD2SS,
17386 IX86_BUILTIN_CVTSS2SD,
17387 IX86_BUILTIN_CVTTSD2SI,
17388 IX86_BUILTIN_CVTTSD2SI64,
17390 IX86_BUILTIN_CVTPS2DQ,
17391 IX86_BUILTIN_CVTPS2PD,
17392 IX86_BUILTIN_CVTTPS2DQ,
17394 IX86_BUILTIN_MOVNTI,
17395 IX86_BUILTIN_MOVNTPD,
17396 IX86_BUILTIN_MOVNTDQ,
17399 IX86_BUILTIN_MASKMOVDQU,
17400 IX86_BUILTIN_MOVMSKPD,
17401 IX86_BUILTIN_PMOVMSKB128,
17403 IX86_BUILTIN_PACKSSWB128,
17404 IX86_BUILTIN_PACKSSDW128,
17405 IX86_BUILTIN_PACKUSWB128,
17407 IX86_BUILTIN_PADDB128,
17408 IX86_BUILTIN_PADDW128,
17409 IX86_BUILTIN_PADDD128,
17410 IX86_BUILTIN_PADDQ128,
17411 IX86_BUILTIN_PADDSB128,
17412 IX86_BUILTIN_PADDSW128,
17413 IX86_BUILTIN_PADDUSB128,
17414 IX86_BUILTIN_PADDUSW128,
17415 IX86_BUILTIN_PSUBB128,
17416 IX86_BUILTIN_PSUBW128,
17417 IX86_BUILTIN_PSUBD128,
17418 IX86_BUILTIN_PSUBQ128,
17419 IX86_BUILTIN_PSUBSB128,
17420 IX86_BUILTIN_PSUBSW128,
17421 IX86_BUILTIN_PSUBUSB128,
17422 IX86_BUILTIN_PSUBUSW128,
17424 IX86_BUILTIN_PAND128,
17425 IX86_BUILTIN_PANDN128,
17426 IX86_BUILTIN_POR128,
17427 IX86_BUILTIN_PXOR128,
17429 IX86_BUILTIN_PAVGB128,
17430 IX86_BUILTIN_PAVGW128,
17432 IX86_BUILTIN_PCMPEQB128,
17433 IX86_BUILTIN_PCMPEQW128,
17434 IX86_BUILTIN_PCMPEQD128,
17435 IX86_BUILTIN_PCMPGTB128,
17436 IX86_BUILTIN_PCMPGTW128,
17437 IX86_BUILTIN_PCMPGTD128,
17439 IX86_BUILTIN_PMADDWD128,
17441 IX86_BUILTIN_PMAXSW128,
17442 IX86_BUILTIN_PMAXUB128,
17443 IX86_BUILTIN_PMINSW128,
17444 IX86_BUILTIN_PMINUB128,
17446 IX86_BUILTIN_PMULUDQ,
17447 IX86_BUILTIN_PMULUDQ128,
17448 IX86_BUILTIN_PMULHUW128,
17449 IX86_BUILTIN_PMULHW128,
17450 IX86_BUILTIN_PMULLW128,
17452 IX86_BUILTIN_PSADBW128,
17453 IX86_BUILTIN_PSHUFHW,
17454 IX86_BUILTIN_PSHUFLW,
17455 IX86_BUILTIN_PSHUFD,
17457 IX86_BUILTIN_PSLLDQI128,
17458 IX86_BUILTIN_PSLLWI128,
17459 IX86_BUILTIN_PSLLDI128,
17460 IX86_BUILTIN_PSLLQI128,
17461 IX86_BUILTIN_PSRAWI128,
17462 IX86_BUILTIN_PSRADI128,
17463 IX86_BUILTIN_PSRLDQI128,
17464 IX86_BUILTIN_PSRLWI128,
17465 IX86_BUILTIN_PSRLDI128,
17466 IX86_BUILTIN_PSRLQI128,
17468 IX86_BUILTIN_PSLLDQ128,
17469 IX86_BUILTIN_PSLLW128,
17470 IX86_BUILTIN_PSLLD128,
17471 IX86_BUILTIN_PSLLQ128,
17472 IX86_BUILTIN_PSRAW128,
17473 IX86_BUILTIN_PSRAD128,
17474 IX86_BUILTIN_PSRLW128,
17475 IX86_BUILTIN_PSRLD128,
17476 IX86_BUILTIN_PSRLQ128,
17478 IX86_BUILTIN_PUNPCKHBW128,
17479 IX86_BUILTIN_PUNPCKHWD128,
17480 IX86_BUILTIN_PUNPCKHDQ128,
17481 IX86_BUILTIN_PUNPCKHQDQ128,
17482 IX86_BUILTIN_PUNPCKLBW128,
17483 IX86_BUILTIN_PUNPCKLWD128,
17484 IX86_BUILTIN_PUNPCKLDQ128,
17485 IX86_BUILTIN_PUNPCKLQDQ128,
17487 IX86_BUILTIN_CLFLUSH,
17488 IX86_BUILTIN_MFENCE,
17489 IX86_BUILTIN_LFENCE,
17492 IX86_BUILTIN_ADDSUBPS,
17493 IX86_BUILTIN_HADDPS,
17494 IX86_BUILTIN_HSUBPS,
17495 IX86_BUILTIN_MOVSHDUP,
17496 IX86_BUILTIN_MOVSLDUP,
17497 IX86_BUILTIN_ADDSUBPD,
17498 IX86_BUILTIN_HADDPD,
17499 IX86_BUILTIN_HSUBPD,
17500 IX86_BUILTIN_LDDQU,
17502 IX86_BUILTIN_MONITOR,
17503 IX86_BUILTIN_MWAIT,
17506 IX86_BUILTIN_PHADDW,
17507 IX86_BUILTIN_PHADDD,
17508 IX86_BUILTIN_PHADDSW,
17509 IX86_BUILTIN_PHSUBW,
17510 IX86_BUILTIN_PHSUBD,
17511 IX86_BUILTIN_PHSUBSW,
17512 IX86_BUILTIN_PMADDUBSW,
17513 IX86_BUILTIN_PMULHRSW,
17514 IX86_BUILTIN_PSHUFB,
17515 IX86_BUILTIN_PSIGNB,
17516 IX86_BUILTIN_PSIGNW,
17517 IX86_BUILTIN_PSIGND,
17518 IX86_BUILTIN_PALIGNR,
17519 IX86_BUILTIN_PABSB,
17520 IX86_BUILTIN_PABSW,
17521 IX86_BUILTIN_PABSD,
17523 IX86_BUILTIN_PHADDW128,
17524 IX86_BUILTIN_PHADDD128,
17525 IX86_BUILTIN_PHADDSW128,
17526 IX86_BUILTIN_PHSUBW128,
17527 IX86_BUILTIN_PHSUBD128,
17528 IX86_BUILTIN_PHSUBSW128,
17529 IX86_BUILTIN_PMADDUBSW128,
17530 IX86_BUILTIN_PMULHRSW128,
17531 IX86_BUILTIN_PSHUFB128,
17532 IX86_BUILTIN_PSIGNB128,
17533 IX86_BUILTIN_PSIGNW128,
17534 IX86_BUILTIN_PSIGND128,
17535 IX86_BUILTIN_PALIGNR128,
17536 IX86_BUILTIN_PABSB128,
17537 IX86_BUILTIN_PABSW128,
17538 IX86_BUILTIN_PABSD128,
17540 /* AMDFAM10 - SSE4A New Instructions. */
17541 IX86_BUILTIN_MOVNTSD,
17542 IX86_BUILTIN_MOVNTSS,
17543 IX86_BUILTIN_EXTRQI,
17544 IX86_BUILTIN_EXTRQ,
17545 IX86_BUILTIN_INSERTQI,
17546 IX86_BUILTIN_INSERTQ,
17549 IX86_BUILTIN_BLENDPD,
17550 IX86_BUILTIN_BLENDPS,
17551 IX86_BUILTIN_BLENDVPD,
17552 IX86_BUILTIN_BLENDVPS,
17553 IX86_BUILTIN_PBLENDVB128,
17554 IX86_BUILTIN_PBLENDW128,
17559 IX86_BUILTIN_INSERTPS128,
17561 IX86_BUILTIN_MOVNTDQA,
17562 IX86_BUILTIN_MPSADBW128,
17563 IX86_BUILTIN_PACKUSDW128,
17564 IX86_BUILTIN_PCMPEQQ,
17565 IX86_BUILTIN_PHMINPOSUW128,
17567 IX86_BUILTIN_PMAXSB128,
17568 IX86_BUILTIN_PMAXSD128,
17569 IX86_BUILTIN_PMAXUD128,
17570 IX86_BUILTIN_PMAXUW128,
17572 IX86_BUILTIN_PMINSB128,
17573 IX86_BUILTIN_PMINSD128,
17574 IX86_BUILTIN_PMINUD128,
17575 IX86_BUILTIN_PMINUW128,
17577 IX86_BUILTIN_PMOVSXBW128,
17578 IX86_BUILTIN_PMOVSXBD128,
17579 IX86_BUILTIN_PMOVSXBQ128,
17580 IX86_BUILTIN_PMOVSXWD128,
17581 IX86_BUILTIN_PMOVSXWQ128,
17582 IX86_BUILTIN_PMOVSXDQ128,
17584 IX86_BUILTIN_PMOVZXBW128,
17585 IX86_BUILTIN_PMOVZXBD128,
17586 IX86_BUILTIN_PMOVZXBQ128,
17587 IX86_BUILTIN_PMOVZXWD128,
17588 IX86_BUILTIN_PMOVZXWQ128,
17589 IX86_BUILTIN_PMOVZXDQ128,
17591 IX86_BUILTIN_PMULDQ128,
17592 IX86_BUILTIN_PMULLD128,
17594 IX86_BUILTIN_ROUNDPD,
17595 IX86_BUILTIN_ROUNDPS,
17596 IX86_BUILTIN_ROUNDSD,
17597 IX86_BUILTIN_ROUNDSS,
17599 IX86_BUILTIN_PTESTZ,
17600 IX86_BUILTIN_PTESTC,
17601 IX86_BUILTIN_PTESTNZC,
17603 IX86_BUILTIN_VEC_INIT_V2SI,
17604 IX86_BUILTIN_VEC_INIT_V4HI,
17605 IX86_BUILTIN_VEC_INIT_V8QI,
17606 IX86_BUILTIN_VEC_EXT_V2DF,
17607 IX86_BUILTIN_VEC_EXT_V2DI,
17608 IX86_BUILTIN_VEC_EXT_V4SF,
17609 IX86_BUILTIN_VEC_EXT_V4SI,
17610 IX86_BUILTIN_VEC_EXT_V8HI,
17611 IX86_BUILTIN_VEC_EXT_V2SI,
17612 IX86_BUILTIN_VEC_EXT_V4HI,
17613 IX86_BUILTIN_VEC_EXT_V16QI,
17614 IX86_BUILTIN_VEC_SET_V2DI,
17615 IX86_BUILTIN_VEC_SET_V4SF,
17616 IX86_BUILTIN_VEC_SET_V4SI,
17617 IX86_BUILTIN_VEC_SET_V8HI,
17618 IX86_BUILTIN_VEC_SET_V4HI,
17619 IX86_BUILTIN_VEC_SET_V16QI,
17621 IX86_BUILTIN_VEC_PACK_SFIX,
17624 IX86_BUILTIN_CRC32QI,
17625 IX86_BUILTIN_CRC32HI,
17626 IX86_BUILTIN_CRC32SI,
17627 IX86_BUILTIN_CRC32DI,
17629 IX86_BUILTIN_PCMPESTRI128,
17630 IX86_BUILTIN_PCMPESTRM128,
17631 IX86_BUILTIN_PCMPESTRA128,
17632 IX86_BUILTIN_PCMPESTRC128,
17633 IX86_BUILTIN_PCMPESTRO128,
17634 IX86_BUILTIN_PCMPESTRS128,
17635 IX86_BUILTIN_PCMPESTRZ128,
17636 IX86_BUILTIN_PCMPISTRI128,
17637 IX86_BUILTIN_PCMPISTRM128,
17638 IX86_BUILTIN_PCMPISTRA128,
17639 IX86_BUILTIN_PCMPISTRC128,
17640 IX86_BUILTIN_PCMPISTRO128,
17641 IX86_BUILTIN_PCMPISTRS128,
17642 IX86_BUILTIN_PCMPISTRZ128,
17644 IX86_BUILTIN_PCMPGTQ,
17646 /* AES instructions */
17647 IX86_BUILTIN_AESENC128,
17648 IX86_BUILTIN_AESENCLAST128,
17649 IX86_BUILTIN_AESDEC128,
17650 IX86_BUILTIN_AESDECLAST128,
17651 IX86_BUILTIN_AESIMC128,
17652 IX86_BUILTIN_AESKEYGENASSIST128,
17654 /* PCLMUL instruction */
17655 IX86_BUILTIN_PCLMULQDQ128,
17657 /* TFmode support builtins. */
17659 IX86_BUILTIN_FABSQ,
17660 IX86_BUILTIN_COPYSIGNQ,
17662 /* SSE5 instructions */
17663 IX86_BUILTIN_FMADDSS,
17664 IX86_BUILTIN_FMADDSD,
17665 IX86_BUILTIN_FMADDPS,
17666 IX86_BUILTIN_FMADDPD,
17667 IX86_BUILTIN_FMSUBSS,
17668 IX86_BUILTIN_FMSUBSD,
17669 IX86_BUILTIN_FMSUBPS,
17670 IX86_BUILTIN_FMSUBPD,
17671 IX86_BUILTIN_FNMADDSS,
17672 IX86_BUILTIN_FNMADDSD,
17673 IX86_BUILTIN_FNMADDPS,
17674 IX86_BUILTIN_FNMADDPD,
17675 IX86_BUILTIN_FNMSUBSS,
17676 IX86_BUILTIN_FNMSUBSD,
17677 IX86_BUILTIN_FNMSUBPS,
17678 IX86_BUILTIN_FNMSUBPD,
17679 IX86_BUILTIN_PCMOV_V2DI,
17680 IX86_BUILTIN_PCMOV_V4SI,
17681 IX86_BUILTIN_PCMOV_V8HI,
17682 IX86_BUILTIN_PCMOV_V16QI,
17683 IX86_BUILTIN_PCMOV_V4SF,
17684 IX86_BUILTIN_PCMOV_V2DF,
17685 IX86_BUILTIN_PPERM,
17686 IX86_BUILTIN_PERMPS,
17687 IX86_BUILTIN_PERMPD,
17688 IX86_BUILTIN_PMACSSWW,
17689 IX86_BUILTIN_PMACSWW,
17690 IX86_BUILTIN_PMACSSWD,
17691 IX86_BUILTIN_PMACSWD,
17692 IX86_BUILTIN_PMACSSDD,
17693 IX86_BUILTIN_PMACSDD,
17694 IX86_BUILTIN_PMACSSDQL,
17695 IX86_BUILTIN_PMACSSDQH,
17696 IX86_BUILTIN_PMACSDQL,
17697 IX86_BUILTIN_PMACSDQH,
17698 IX86_BUILTIN_PMADCSSWD,
17699 IX86_BUILTIN_PMADCSWD,
17700 IX86_BUILTIN_PHADDBW,
17701 IX86_BUILTIN_PHADDBD,
17702 IX86_BUILTIN_PHADDBQ,
17703 IX86_BUILTIN_PHADDWD,
17704 IX86_BUILTIN_PHADDWQ,
17705 IX86_BUILTIN_PHADDDQ,
17706 IX86_BUILTIN_PHADDUBW,
17707 IX86_BUILTIN_PHADDUBD,
17708 IX86_BUILTIN_PHADDUBQ,
17709 IX86_BUILTIN_PHADDUWD,
17710 IX86_BUILTIN_PHADDUWQ,
17711 IX86_BUILTIN_PHADDUDQ,
17712 IX86_BUILTIN_PHSUBBW,
17713 IX86_BUILTIN_PHSUBWD,
17714 IX86_BUILTIN_PHSUBDQ,
17715 IX86_BUILTIN_PROTB,
17716 IX86_BUILTIN_PROTW,
17717 IX86_BUILTIN_PROTD,
17718 IX86_BUILTIN_PROTQ,
17719 IX86_BUILTIN_PROTB_IMM,
17720 IX86_BUILTIN_PROTW_IMM,
17721 IX86_BUILTIN_PROTD_IMM,
17722 IX86_BUILTIN_PROTQ_IMM,
17723 IX86_BUILTIN_PSHLB,
17724 IX86_BUILTIN_PSHLW,
17725 IX86_BUILTIN_PSHLD,
17726 IX86_BUILTIN_PSHLQ,
17727 IX86_BUILTIN_PSHAB,
17728 IX86_BUILTIN_PSHAW,
17729 IX86_BUILTIN_PSHAD,
17730 IX86_BUILTIN_PSHAQ,
17731 IX86_BUILTIN_FRCZSS,
17732 IX86_BUILTIN_FRCZSD,
17733 IX86_BUILTIN_FRCZPS,
17734 IX86_BUILTIN_FRCZPD,
17735 IX86_BUILTIN_CVTPH2PS,
17736 IX86_BUILTIN_CVTPS2PH,
17738 IX86_BUILTIN_COMEQSS,
17739 IX86_BUILTIN_COMNESS,
17740 IX86_BUILTIN_COMLTSS,
17741 IX86_BUILTIN_COMLESS,
17742 IX86_BUILTIN_COMGTSS,
17743 IX86_BUILTIN_COMGESS,
17744 IX86_BUILTIN_COMUEQSS,
17745 IX86_BUILTIN_COMUNESS,
17746 IX86_BUILTIN_COMULTSS,
17747 IX86_BUILTIN_COMULESS,
17748 IX86_BUILTIN_COMUGTSS,
17749 IX86_BUILTIN_COMUGESS,
17750 IX86_BUILTIN_COMORDSS,
17751 IX86_BUILTIN_COMUNORDSS,
17752 IX86_BUILTIN_COMFALSESS,
17753 IX86_BUILTIN_COMTRUESS,
17755 IX86_BUILTIN_COMEQSD,
17756 IX86_BUILTIN_COMNESD,
17757 IX86_BUILTIN_COMLTSD,
17758 IX86_BUILTIN_COMLESD,
17759 IX86_BUILTIN_COMGTSD,
17760 IX86_BUILTIN_COMGESD,
17761 IX86_BUILTIN_COMUEQSD,
17762 IX86_BUILTIN_COMUNESD,
17763 IX86_BUILTIN_COMULTSD,
17764 IX86_BUILTIN_COMULESD,
17765 IX86_BUILTIN_COMUGTSD,
17766 IX86_BUILTIN_COMUGESD,
17767 IX86_BUILTIN_COMORDSD,
17768 IX86_BUILTIN_COMUNORDSD,
17769 IX86_BUILTIN_COMFALSESD,
17770 IX86_BUILTIN_COMTRUESD,
17772 IX86_BUILTIN_COMEQPS,
17773 IX86_BUILTIN_COMNEPS,
17774 IX86_BUILTIN_COMLTPS,
17775 IX86_BUILTIN_COMLEPS,
17776 IX86_BUILTIN_COMGTPS,
17777 IX86_BUILTIN_COMGEPS,
17778 IX86_BUILTIN_COMUEQPS,
17779 IX86_BUILTIN_COMUNEPS,
17780 IX86_BUILTIN_COMULTPS,
17781 IX86_BUILTIN_COMULEPS,
17782 IX86_BUILTIN_COMUGTPS,
17783 IX86_BUILTIN_COMUGEPS,
17784 IX86_BUILTIN_COMORDPS,
17785 IX86_BUILTIN_COMUNORDPS,
17786 IX86_BUILTIN_COMFALSEPS,
17787 IX86_BUILTIN_COMTRUEPS,
17789 IX86_BUILTIN_COMEQPD,
17790 IX86_BUILTIN_COMNEPD,
17791 IX86_BUILTIN_COMLTPD,
17792 IX86_BUILTIN_COMLEPD,
17793 IX86_BUILTIN_COMGTPD,
17794 IX86_BUILTIN_COMGEPD,
17795 IX86_BUILTIN_COMUEQPD,
17796 IX86_BUILTIN_COMUNEPD,
17797 IX86_BUILTIN_COMULTPD,
17798 IX86_BUILTIN_COMULEPD,
17799 IX86_BUILTIN_COMUGTPD,
17800 IX86_BUILTIN_COMUGEPD,
17801 IX86_BUILTIN_COMORDPD,
17802 IX86_BUILTIN_COMUNORDPD,
17803 IX86_BUILTIN_COMFALSEPD,
17804 IX86_BUILTIN_COMTRUEPD,
17806 IX86_BUILTIN_PCOMEQUB,
17807 IX86_BUILTIN_PCOMNEUB,
17808 IX86_BUILTIN_PCOMLTUB,
17809 IX86_BUILTIN_PCOMLEUB,
17810 IX86_BUILTIN_PCOMGTUB,
17811 IX86_BUILTIN_PCOMGEUB,
17812 IX86_BUILTIN_PCOMFALSEUB,
17813 IX86_BUILTIN_PCOMTRUEUB,
17814 IX86_BUILTIN_PCOMEQUW,
17815 IX86_BUILTIN_PCOMNEUW,
17816 IX86_BUILTIN_PCOMLTUW,
17817 IX86_BUILTIN_PCOMLEUW,
17818 IX86_BUILTIN_PCOMGTUW,
17819 IX86_BUILTIN_PCOMGEUW,
17820 IX86_BUILTIN_PCOMFALSEUW,
17821 IX86_BUILTIN_PCOMTRUEUW,
17822 IX86_BUILTIN_PCOMEQUD,
17823 IX86_BUILTIN_PCOMNEUD,
17824 IX86_BUILTIN_PCOMLTUD,
17825 IX86_BUILTIN_PCOMLEUD,
17826 IX86_BUILTIN_PCOMGTUD,
17827 IX86_BUILTIN_PCOMGEUD,
17828 IX86_BUILTIN_PCOMFALSEUD,
17829 IX86_BUILTIN_PCOMTRUEUD,
17830 IX86_BUILTIN_PCOMEQUQ,
17831 IX86_BUILTIN_PCOMNEUQ,
17832 IX86_BUILTIN_PCOMLTUQ,
17833 IX86_BUILTIN_PCOMLEUQ,
17834 IX86_BUILTIN_PCOMGTUQ,
17835 IX86_BUILTIN_PCOMGEUQ,
17836 IX86_BUILTIN_PCOMFALSEUQ,
17837 IX86_BUILTIN_PCOMTRUEUQ,
17839 IX86_BUILTIN_PCOMEQB,
17840 IX86_BUILTIN_PCOMNEB,
17841 IX86_BUILTIN_PCOMLTB,
17842 IX86_BUILTIN_PCOMLEB,
17843 IX86_BUILTIN_PCOMGTB,
17844 IX86_BUILTIN_PCOMGEB,
17845 IX86_BUILTIN_PCOMFALSEB,
17846 IX86_BUILTIN_PCOMTRUEB,
17847 IX86_BUILTIN_PCOMEQW,
17848 IX86_BUILTIN_PCOMNEW,
17849 IX86_BUILTIN_PCOMLTW,
17850 IX86_BUILTIN_PCOMLEW,
17851 IX86_BUILTIN_PCOMGTW,
17852 IX86_BUILTIN_PCOMGEW,
17853 IX86_BUILTIN_PCOMFALSEW,
17854 IX86_BUILTIN_PCOMTRUEW,
17855 IX86_BUILTIN_PCOMEQD,
17856 IX86_BUILTIN_PCOMNED,
17857 IX86_BUILTIN_PCOMLTD,
17858 IX86_BUILTIN_PCOMLED,
17859 IX86_BUILTIN_PCOMGTD,
17860 IX86_BUILTIN_PCOMGED,
17861 IX86_BUILTIN_PCOMFALSED,
17862 IX86_BUILTIN_PCOMTRUED,
17863 IX86_BUILTIN_PCOMEQQ,
17864 IX86_BUILTIN_PCOMNEQ,
17865 IX86_BUILTIN_PCOMLTQ,
17866 IX86_BUILTIN_PCOMLEQ,
17867 IX86_BUILTIN_PCOMGTQ,
17868 IX86_BUILTIN_PCOMGEQ,
17869 IX86_BUILTIN_PCOMFALSEQ,
17870 IX86_BUILTIN_PCOMTRUEQ,
17875 /* Table for the ix86 builtin decls. */
17876 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
17878 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Do so,
17879 * if the target_flags include one of MASK. Stores the function decl
17880 * in the ix86_builtins array.
17881 * Returns the function decl or NULL_TREE, if the builtin was not added. */
17884 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
17886 tree decl = NULL_TREE;
17888 if (mask & ix86_isa_flags
17889 && (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT))
17891 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
17893 ix86_builtins[(int) code] = decl;
17899 /* Like def_builtin, but also marks the function decl "const". */
17902 def_builtin_const (int mask, const char *name, tree type,
17903 enum ix86_builtins code)
17905 tree decl = def_builtin (mask, name, type, code);
17907 TREE_READONLY (decl) = 1;
17911 /* Bits for builtin_description.flag. */
17913 /* Set when we don't support the comparison natively, and should
17914 swap_comparison in order to support it. */
17915 #define BUILTIN_DESC_SWAP_OPERANDS 1
17917 struct builtin_description
17919 const unsigned int mask;
17920 const enum insn_code icode;
17921 const char *const name;
17922 const enum ix86_builtins code;
17923 const enum rtx_code comparison;
17927 static const struct builtin_description bdesc_comi[] =
17929 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
17930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
17931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
17932 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
17933 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
17934 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
17935 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
17936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
17937 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
17938 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
17939 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
17940 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
17941 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
17942 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
17943 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
17944 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
17945 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
17946 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
17947 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
17948 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
17949 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
17950 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
17951 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
17952 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
17955 static const struct builtin_description bdesc_ptest[] =
17958 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, 0 },
17959 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, 0 },
17960 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, 0 },
17963 static const struct builtin_description bdesc_pcmpestr[] =
17966 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
17967 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
17968 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
17969 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
17970 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
17971 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
17972 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
17975 static const struct builtin_description bdesc_pcmpistr[] =
17978 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
17979 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
17980 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
17981 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
17982 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
17983 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
17984 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
17987 static const struct builtin_description bdesc_crc32[] =
17990 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32qi, 0, IX86_BUILTIN_CRC32QI, UNKNOWN, 0 },
17991 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, 0, IX86_BUILTIN_CRC32HI, UNKNOWN, 0 },
17992 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, 0, IX86_BUILTIN_CRC32SI, UNKNOWN, 0 },
17993 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32di, 0, IX86_BUILTIN_CRC32DI, UNKNOWN, 0 },
17996 /* Builtin types */
17997 enum ix86_builtin_type
18000 FLOAT128_FTYPE_FLOAT128,
18034 V4SF_FTYPE_V4SF_INT,
18035 V2DI_FTYPE_V2DI_INT,
18036 V2DF_FTYPE_V2DF_INT,
18037 V16QI_FTYPE_V16QI_V16QI_V16QI,
18038 V4SF_FTYPE_V4SF_V4SF_V4SF,
18039 V2DF_FTYPE_V2DF_V2DF_V2DF,
18040 V16QI_FTYPE_V16QI_V16QI_INT,
18041 V8HI_FTYPE_V8HI_V8HI_INT,
18042 V4SI_FTYPE_V4SI_V4SI_INT,
18043 V4SF_FTYPE_V4SF_V4SF_INT,
18044 V2DI_FTYPE_V2DI_V2DI_INT,
18045 V2DF_FTYPE_V2DF_V2DF_INT
18048 /* Builtins with variable number of arguments. */
18049 static const struct builtin_description bdesc_args[] =
18052 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
18053 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
18054 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
18055 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
18058 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
18059 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
18060 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
18061 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
18064 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
18065 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18066 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18067 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18068 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18069 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18070 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
18071 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
18072 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
18073 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
18074 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
18075 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
18077 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18079 /* SSE and 3DNow!A */
18080 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
18083 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18085 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
18086 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
18087 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
18088 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
18089 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
18091 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
18092 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
18093 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
18094 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
18095 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
18097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
18099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
18100 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
18101 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
18102 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
18104 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
18105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
18106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
18109 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
18110 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
18113 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
18114 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
18115 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
18116 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
18117 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
18118 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
18121 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18122 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18123 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
18124 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
18125 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18126 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18127 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18128 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
18129 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
18130 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
18132 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
18133 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
18134 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
18135 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
18136 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
18137 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
18138 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
18139 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
18140 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
18141 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
18142 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
18143 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
18144 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
18146 /* SSE4.1 and SSE5 */
18147 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
18148 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
18149 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
18150 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
18153 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
18154 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
18157 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
18160 { OPTION_MASK_ISA_64BIT, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
18163 static const struct builtin_description bdesc_2arg[] =
18166 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, 0 },
18167 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, 0 },
18168 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, 0 },
18169 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, 0 },
18170 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, 0 },
18171 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, 0 },
18172 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, 0 },
18173 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, 0 },
18175 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
18176 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
18177 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
18178 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, BUILTIN_DESC_SWAP_OPERANDS },
18179 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, BUILTIN_DESC_SWAP_OPERANDS },
18180 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
18181 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
18182 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
18183 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
18184 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
18185 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
18186 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
18187 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
18188 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
18189 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
18190 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
18191 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
18192 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
18193 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
18194 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
18195 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
18196 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, 0 },
18198 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, 0 },
18199 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, 0 },
18200 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, 0 },
18201 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, 0 },
18203 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, 0 },
18204 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, 0 },
18205 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, 0 },
18206 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, 0 },
18208 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, 0 },
18209 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, 0 },
18210 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, 0 },
18211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, 0 },
18212 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, 0 },
18215 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, 0 },
18216 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, 0 },
18217 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, 0 },
18218 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, 0 },
18219 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, 0 },
18220 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, 0 },
18221 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, 0 },
18222 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, 0 },
18224 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, 0 },
18225 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, 0 },
18226 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, 0 },
18227 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, 0 },
18228 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, 0 },
18229 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, 0 },
18230 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, 0 },
18231 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, 0 },
18233 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, 0 },
18234 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, 0 },
18235 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, 0 },
18237 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, 0 },
18238 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, 0 },
18239 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, 0 },
18240 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, 0 },
18242 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, 0 },
18243 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, 0 },
18245 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, 0 },
18246 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, 0 },
18247 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, 0 },
18248 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, 0 },
18249 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, 0 },
18250 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, 0 },
18252 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, 0 },
18253 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, 0 },
18254 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, 0 },
18255 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, 0 },
18257 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, 0 },
18258 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, 0 },
18259 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, 0 },
18260 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, 0 },
18261 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, 0 },
18262 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, 0 },
18265 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, UNKNOWN, 0 },
18266 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, UNKNOWN, 0 },
18267 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, UNKNOWN, 0 },
18269 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, UNKNOWN, 0 },
18270 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, UNKNOWN, 0 },
18271 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, UNKNOWN, 0 },
18273 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, UNKNOWN, 0 },
18274 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, UNKNOWN, 0 },
18277 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, 0 },
18278 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, 0 },
18279 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, 0 },
18280 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, 0 },
18281 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, 0 },
18282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, 0 },
18283 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, 0 },
18284 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, 0 },
18286 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
18287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
18288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
18289 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, BUILTIN_DESC_SWAP_OPERANDS },
18290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, BUILTIN_DESC_SWAP_OPERANDS },
18291 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
18292 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
18293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
18294 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
18295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, BUILTIN_DESC_SWAP_OPERANDS },
18296 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, BUILTIN_DESC_SWAP_OPERANDS },
18297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
18298 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
18299 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
18300 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
18301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
18302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
18303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
18304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
18305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
18307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, 0 },
18308 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, 0 },
18309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, 0 },
18310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, 0 },
18312 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, 0 },
18313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, 0 },
18314 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, 0 },
18315 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, 0 },
18317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, 0 },
18318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, 0 },
18319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, 0 },
18321 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, 0 },
18324 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, 0 },
18325 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, 0 },
18326 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, 0 },
18327 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, 0 },
18328 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, 0 },
18329 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, 0 },
18330 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, 0 },
18331 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, 0 },
18333 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, 0 },
18334 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, 0 },
18335 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, 0 },
18336 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, 0 },
18337 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, 0 },
18338 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, 0 },
18339 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, 0 },
18340 { OPTION_MASK_ISA_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, 0 },
18342 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, 0 },
18343 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN, 0 },
18345 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, 0 },
18346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, 0 },
18347 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, 0 },
18348 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, 0 },
18350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, 0 },
18351 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, 0 },
18353 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, 0 },
18354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, 0 },
18355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, 0 },
18356 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, 0 },
18357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, 0 },
18358 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, 0 },
18360 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, 0 },
18361 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, 0 },
18362 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, 0 },
18363 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, 0 },
18365 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, 0 },
18366 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, 0 },
18367 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, 0 },
18368 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, 0 },
18369 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, 0 },
18370 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, 0 },
18371 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, 0 },
18372 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, 0 },
18374 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, 0 },
18375 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, 0 },
18376 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, 0 },
18378 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, 0 },
18379 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, UNKNOWN, 0 },
18381 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, 0, IX86_BUILTIN_PMULUDQ, UNKNOWN, 0 },
18382 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, UNKNOWN, 0 },
18384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, UNKNOWN, 0 },
18386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, UNKNOWN, 0 },
18387 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, UNKNOWN, 0 },
18388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, UNKNOWN, 0 },
18389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, UNKNOWN, 0 },
18392 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, 0 },
18393 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, 0 },
18394 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, 0 },
18395 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, 0 },
18396 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, 0 },
18397 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, 0 },
18400 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, 0 },
18401 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, 0 },
18402 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, 0 },
18403 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, 0 },
18404 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, 0 },
18405 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, 0 },
18406 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, 0 },
18407 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, 0 },
18408 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, 0 },
18409 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, 0 },
18410 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, 0 },
18411 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, 0 },
18412 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, 0 },
18413 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, 0 },
18414 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, 0 },
18415 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, 0 },
18416 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, 0 },
18417 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, 0 },
18418 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, 0 },
18419 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, 0 },
18420 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, 0 },
18421 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, 0 },
18422 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, 0 },
18423 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, 0 },
18426 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, 0 },
18427 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, 0 },
18428 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, 0 },
18429 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, 0 },
18430 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, 0 },
18431 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, 0 },
18432 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, 0 },
18433 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, 0 },
18434 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, 0 },
18435 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, 0 },
18436 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, 0, IX86_BUILTIN_PMULDQ128, UNKNOWN, 0 },
18437 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, 0 },
18440 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, 0 },
18443 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, 0 },
18444 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, 0 },
18445 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, 0 },
18446 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, 0 },
18450 enum multi_arg_type {
18460 MULTI_ARG_3_PERMPS,
18461 MULTI_ARG_3_PERMPD,
18468 MULTI_ARG_2_DI_IMM,
18469 MULTI_ARG_2_SI_IMM,
18470 MULTI_ARG_2_HI_IMM,
18471 MULTI_ARG_2_QI_IMM,
18472 MULTI_ARG_2_SF_CMP,
18473 MULTI_ARG_2_DF_CMP,
18474 MULTI_ARG_2_DI_CMP,
18475 MULTI_ARG_2_SI_CMP,
18476 MULTI_ARG_2_HI_CMP,
18477 MULTI_ARG_2_QI_CMP,
18500 static const struct builtin_description bdesc_multi_arg[] =
18502 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
18503 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
18504 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
18505 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
18506 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
18507 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
18508 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
18509 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
18510 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
18511 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
18512 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
18513 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
18514 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
18515 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
18516 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
18517 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
18518 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18519 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
18520 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
18521 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
18522 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
18523 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
18524 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
18525 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
18526 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
18527 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
18528 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
18529 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
18530 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18531 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
18532 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
18533 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
18534 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18535 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18536 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
18537 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
18538 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
18539 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
18540 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
18541 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
18542 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
18543 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
18544 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
18545 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
18546 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
18547 { OPTION_MASK_ISA_SSE5, CODE_FOR_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
18548 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
18549 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
18550 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
18551 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
18552 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
18553 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
18554 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
18555 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
18556 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
18557 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
18558 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
18559 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
18560 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
18561 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
18562 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
18563 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
18564 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
18565 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
18566 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
18567 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
18568 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
18569 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
18570 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
18571 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
18572 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
18573 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
18574 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
18575 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
18576 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
18578 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
18579 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18580 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
18581 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
18582 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
18583 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
18584 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
18585 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18586 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18587 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18588 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18589 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18590 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18591 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18592 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18593 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18595 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
18596 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18597 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
18598 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
18599 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
18600 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
18601 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
18602 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18603 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18604 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18605 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18606 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18607 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18608 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18609 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18610 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18612 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
18613 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18614 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
18615 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
18616 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
18617 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
18618 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
18619 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
18620 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18621 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
18622 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
18623 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
18624 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
18625 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
18626 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
18627 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
18629 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
18630 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18631 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
18632 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
18633 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
18634 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
18635 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
18636 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
18637 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18638 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
18639 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
18640 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
18641 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
18642 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
18643 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
18644 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
18646 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
18647 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18648 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
18649 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
18650 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
18651 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
18652 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
18654 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
18655 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18656 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
18657 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
18658 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
18659 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
18660 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
18662 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
18663 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18664 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
18665 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
18666 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
18667 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
18668 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
18670 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18671 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18672 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
18673 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
18674 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
18675 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
18676 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
18678 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
18679 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18680 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
18681 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
18682 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
18683 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
18684 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
18686 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
18687 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18688 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
18689 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
18690 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
18691 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
18692 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
18694 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
18695 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18696 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
18697 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
18698 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
18699 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
18700 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
18702 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
18703 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18704 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
18705 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
18706 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
18707 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
18708 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
18710 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
18711 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
18712 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
18713 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
18714 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
18715 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
18716 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
18717 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
18719 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18720 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18721 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18722 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18723 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
18724 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
18725 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
18726 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
18728 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18729 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18730 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18731 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18732 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
18733 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
18734 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
18735 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
18738 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
18739 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
18742 ix86_init_mmx_sse_builtins (void)
18744 const struct builtin_description * d;
18747 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
18748 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
18749 tree V1DI_type_node
18750 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
18751 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
18752 tree V2DI_type_node
18753 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
18754 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
18755 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
18756 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
18757 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
18758 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
18759 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
18761 tree pchar_type_node = build_pointer_type (char_type_node);
18762 tree pcchar_type_node = build_pointer_type (
18763 build_type_variant (char_type_node, 1, 0));
18764 tree pfloat_type_node = build_pointer_type (float_type_node);
18765 tree pcfloat_type_node = build_pointer_type (
18766 build_type_variant (float_type_node, 1, 0));
18767 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
18768 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
18769 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
18772 tree int_ftype_v4sf_v4sf
18773 = build_function_type_list (integer_type_node,
18774 V4SF_type_node, V4SF_type_node, NULL_TREE);
18775 tree v4si_ftype_v4sf_v4sf
18776 = build_function_type_list (V4SI_type_node,
18777 V4SF_type_node, V4SF_type_node, NULL_TREE);
18778 /* MMX/SSE/integer conversions. */
18779 tree int_ftype_v4sf
18780 = build_function_type_list (integer_type_node,
18781 V4SF_type_node, NULL_TREE);
18782 tree int64_ftype_v4sf
18783 = build_function_type_list (long_long_integer_type_node,
18784 V4SF_type_node, NULL_TREE);
18785 tree int_ftype_v8qi
18786 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
18787 tree v4sf_ftype_v4sf_int
18788 = build_function_type_list (V4SF_type_node,
18789 V4SF_type_node, integer_type_node, NULL_TREE);
18790 tree v4sf_ftype_v4sf_int64
18791 = build_function_type_list (V4SF_type_node,
18792 V4SF_type_node, long_long_integer_type_node,
18794 tree v4sf_ftype_v4sf_v2si
18795 = build_function_type_list (V4SF_type_node,
18796 V4SF_type_node, V2SI_type_node, NULL_TREE);
18798 /* Miscellaneous. */
18799 tree v8qi_ftype_v4hi_v4hi
18800 = build_function_type_list (V8QI_type_node,
18801 V4HI_type_node, V4HI_type_node, NULL_TREE);
18802 tree v4hi_ftype_v2si_v2si
18803 = build_function_type_list (V4HI_type_node,
18804 V2SI_type_node, V2SI_type_node, NULL_TREE);
18805 tree v4sf_ftype_v4sf_v4sf_int
18806 = build_function_type_list (V4SF_type_node,
18807 V4SF_type_node, V4SF_type_node,
18808 integer_type_node, NULL_TREE);
18809 tree v2si_ftype_v4hi_v4hi
18810 = build_function_type_list (V2SI_type_node,
18811 V4HI_type_node, V4HI_type_node, NULL_TREE);
18812 tree v4hi_ftype_v4hi_int
18813 = build_function_type_list (V4HI_type_node,
18814 V4HI_type_node, integer_type_node, NULL_TREE);
18815 tree v2si_ftype_v2si_int
18816 = build_function_type_list (V2SI_type_node,
18817 V2SI_type_node, integer_type_node, NULL_TREE);
18818 tree v1di_ftype_v1di_int
18819 = build_function_type_list (V1DI_type_node,
18820 V1DI_type_node, integer_type_node, NULL_TREE);
18822 tree void_ftype_void
18823 = build_function_type (void_type_node, void_list_node);
18824 tree void_ftype_unsigned
18825 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
18826 tree void_ftype_unsigned_unsigned
18827 = build_function_type_list (void_type_node, unsigned_type_node,
18828 unsigned_type_node, NULL_TREE);
18829 tree void_ftype_pcvoid_unsigned_unsigned
18830 = build_function_type_list (void_type_node, const_ptr_type_node,
18831 unsigned_type_node, unsigned_type_node,
18833 tree unsigned_ftype_void
18834 = build_function_type (unsigned_type_node, void_list_node);
18835 tree v2si_ftype_v4sf
18836 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
18837 /* Loads/stores. */
18838 tree void_ftype_v8qi_v8qi_pchar
18839 = build_function_type_list (void_type_node,
18840 V8QI_type_node, V8QI_type_node,
18841 pchar_type_node, NULL_TREE);
18842 tree v4sf_ftype_pcfloat
18843 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
18844 /* @@@ the type is bogus */
18845 tree v4sf_ftype_v4sf_pv2si
18846 = build_function_type_list (V4SF_type_node,
18847 V4SF_type_node, pv2si_type_node, NULL_TREE);
18848 tree void_ftype_pv2si_v4sf
18849 = build_function_type_list (void_type_node,
18850 pv2si_type_node, V4SF_type_node, NULL_TREE);
18851 tree void_ftype_pfloat_v4sf
18852 = build_function_type_list (void_type_node,
18853 pfloat_type_node, V4SF_type_node, NULL_TREE);
18854 tree void_ftype_pdi_di
18855 = build_function_type_list (void_type_node,
18856 pdi_type_node, long_long_unsigned_type_node,
18858 tree void_ftype_pv2di_v2di
18859 = build_function_type_list (void_type_node,
18860 pv2di_type_node, V2DI_type_node, NULL_TREE);
18861 /* Normal vector unops. */
18862 tree v4sf_ftype_v4sf
18863 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
18864 tree v16qi_ftype_v16qi
18865 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
18866 tree v8hi_ftype_v8hi
18867 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
18868 tree v4si_ftype_v4si
18869 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
18870 tree v8qi_ftype_v8qi
18871 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
18872 tree v4hi_ftype_v4hi
18873 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
18875 /* Normal vector binops. */
18876 tree v4sf_ftype_v4sf_v4sf
18877 = build_function_type_list (V4SF_type_node,
18878 V4SF_type_node, V4SF_type_node, NULL_TREE);
18879 tree v8qi_ftype_v8qi_v8qi
18880 = build_function_type_list (V8QI_type_node,
18881 V8QI_type_node, V8QI_type_node, NULL_TREE);
18882 tree v4hi_ftype_v4hi_v4hi
18883 = build_function_type_list (V4HI_type_node,
18884 V4HI_type_node, V4HI_type_node, NULL_TREE);
18885 tree v2si_ftype_v2si_v2si
18886 = build_function_type_list (V2SI_type_node,
18887 V2SI_type_node, V2SI_type_node, NULL_TREE);
18888 tree v1di_ftype_v1di_v1di
18889 = build_function_type_list (V1DI_type_node,
18890 V1DI_type_node, V1DI_type_node, NULL_TREE);
18892 tree di_ftype_di_di_int
18893 = build_function_type_list (long_long_unsigned_type_node,
18894 long_long_unsigned_type_node,
18895 long_long_unsigned_type_node,
18896 integer_type_node, NULL_TREE);
18898 tree v2si_ftype_v2sf
18899 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
18900 tree v2sf_ftype_v2si
18901 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
18902 tree v2si_ftype_v2si
18903 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
18904 tree v2sf_ftype_v2sf
18905 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
18906 tree v2sf_ftype_v2sf_v2sf
18907 = build_function_type_list (V2SF_type_node,
18908 V2SF_type_node, V2SF_type_node, NULL_TREE);
18909 tree v2si_ftype_v2sf_v2sf
18910 = build_function_type_list (V2SI_type_node,
18911 V2SF_type_node, V2SF_type_node, NULL_TREE);
18912 tree pint_type_node = build_pointer_type (integer_type_node);
18913 tree pdouble_type_node = build_pointer_type (double_type_node);
18914 tree pcdouble_type_node = build_pointer_type (
18915 build_type_variant (double_type_node, 1, 0));
18916 tree int_ftype_v2df_v2df
18917 = build_function_type_list (integer_type_node,
18918 V2DF_type_node, V2DF_type_node, NULL_TREE);
18920 tree void_ftype_pcvoid
18921 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
18922 tree v4sf_ftype_v4si
18923 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
18924 tree v4si_ftype_v4sf
18925 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
18926 tree v2df_ftype_v4si
18927 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
18928 tree v4si_ftype_v2df
18929 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
18930 tree v4si_ftype_v2df_v2df
18931 = build_function_type_list (V4SI_type_node,
18932 V2DF_type_node, V2DF_type_node, NULL_TREE);
18933 tree v2si_ftype_v2df
18934 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
18935 tree v4sf_ftype_v2df
18936 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
18937 tree v2df_ftype_v2si
18938 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
18939 tree v2df_ftype_v4sf
18940 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
18941 tree int_ftype_v2df
18942 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
18943 tree int64_ftype_v2df
18944 = build_function_type_list (long_long_integer_type_node,
18945 V2DF_type_node, NULL_TREE);
18946 tree v2df_ftype_v2df_int
18947 = build_function_type_list (V2DF_type_node,
18948 V2DF_type_node, integer_type_node, NULL_TREE);
18949 tree v2df_ftype_v2df_int64
18950 = build_function_type_list (V2DF_type_node,
18951 V2DF_type_node, long_long_integer_type_node,
18953 tree v4sf_ftype_v4sf_v2df
18954 = build_function_type_list (V4SF_type_node,
18955 V4SF_type_node, V2DF_type_node, NULL_TREE);
18956 tree v2df_ftype_v2df_v4sf
18957 = build_function_type_list (V2DF_type_node,
18958 V2DF_type_node, V4SF_type_node, NULL_TREE);
18959 tree v2df_ftype_v2df_v2df_int
18960 = build_function_type_list (V2DF_type_node,
18961 V2DF_type_node, V2DF_type_node,
18964 tree v2df_ftype_v2df_pcdouble
18965 = build_function_type_list (V2DF_type_node,
18966 V2DF_type_node, pcdouble_type_node, NULL_TREE);
18967 tree void_ftype_pdouble_v2df
18968 = build_function_type_list (void_type_node,
18969 pdouble_type_node, V2DF_type_node, NULL_TREE);
18970 tree void_ftype_pint_int
18971 = build_function_type_list (void_type_node,
18972 pint_type_node, integer_type_node, NULL_TREE);
18973 tree void_ftype_v16qi_v16qi_pchar
18974 = build_function_type_list (void_type_node,
18975 V16QI_type_node, V16QI_type_node,
18976 pchar_type_node, NULL_TREE);
18977 tree v2df_ftype_pcdouble
18978 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
18979 tree v2df_ftype_v2df_v2df
18980 = build_function_type_list (V2DF_type_node,
18981 V2DF_type_node, V2DF_type_node, NULL_TREE);
18982 tree v16qi_ftype_v16qi_v16qi
18983 = build_function_type_list (V16QI_type_node,
18984 V16QI_type_node, V16QI_type_node, NULL_TREE);
18985 tree v8hi_ftype_v8hi_v8hi
18986 = build_function_type_list (V8HI_type_node,
18987 V8HI_type_node, V8HI_type_node, NULL_TREE);
18988 tree v4si_ftype_v4si_v4si
18989 = build_function_type_list (V4SI_type_node,
18990 V4SI_type_node, V4SI_type_node, NULL_TREE);
18991 tree v2di_ftype_v2di_v2di
18992 = build_function_type_list (V2DI_type_node,
18993 V2DI_type_node, V2DI_type_node, NULL_TREE);
18994 tree v2di_ftype_v2df_v2df
18995 = build_function_type_list (V2DI_type_node,
18996 V2DF_type_node, V2DF_type_node, NULL_TREE);
18997 tree v2df_ftype_v2df
18998 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
18999 tree v2di_ftype_v2di_int
19000 = build_function_type_list (V2DI_type_node,
19001 V2DI_type_node, integer_type_node, NULL_TREE);
19002 tree v2di_ftype_v2di_v2di_int
19003 = build_function_type_list (V2DI_type_node, V2DI_type_node,
19004 V2DI_type_node, integer_type_node, NULL_TREE);
19005 tree v4si_ftype_v4si_int
19006 = build_function_type_list (V4SI_type_node,
19007 V4SI_type_node, integer_type_node, NULL_TREE);
19008 tree v8hi_ftype_v8hi_int
19009 = build_function_type_list (V8HI_type_node,
19010 V8HI_type_node, integer_type_node, NULL_TREE);
19011 tree v4si_ftype_v8hi_v8hi
19012 = build_function_type_list (V4SI_type_node,
19013 V8HI_type_node, V8HI_type_node, NULL_TREE);
19014 tree v1di_ftype_v8qi_v8qi
19015 = build_function_type_list (V1DI_type_node,
19016 V8QI_type_node, V8QI_type_node, NULL_TREE);
19017 tree v1di_ftype_v2si_v2si
19018 = build_function_type_list (V1DI_type_node,
19019 V2SI_type_node, V2SI_type_node, NULL_TREE);
19020 tree v2di_ftype_v16qi_v16qi
19021 = build_function_type_list (V2DI_type_node,
19022 V16QI_type_node, V16QI_type_node, NULL_TREE);
19023 tree v2di_ftype_v4si_v4si
19024 = build_function_type_list (V2DI_type_node,
19025 V4SI_type_node, V4SI_type_node, NULL_TREE);
19026 tree int_ftype_v16qi
19027 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
19028 tree v16qi_ftype_pcchar
19029 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
19030 tree void_ftype_pchar_v16qi
19031 = build_function_type_list (void_type_node,
19032 pchar_type_node, V16QI_type_node, NULL_TREE);
19034 tree v2di_ftype_v2di_unsigned_unsigned
19035 = build_function_type_list (V2DI_type_node, V2DI_type_node,
19036 unsigned_type_node, unsigned_type_node,
19038 tree v2di_ftype_v2di_v2di_unsigned_unsigned
19039 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
19040 unsigned_type_node, unsigned_type_node,
19042 tree v2di_ftype_v2di_v16qi
19043 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
19045 tree v2df_ftype_v2df_v2df_v2df
19046 = build_function_type_list (V2DF_type_node,
19047 V2DF_type_node, V2DF_type_node,
19048 V2DF_type_node, NULL_TREE);
19049 tree v4sf_ftype_v4sf_v4sf_v4sf
19050 = build_function_type_list (V4SF_type_node,
19051 V4SF_type_node, V4SF_type_node,
19052 V4SF_type_node, NULL_TREE);
19053 tree v8hi_ftype_v16qi
19054 = build_function_type_list (V8HI_type_node, V16QI_type_node,
19056 tree v4si_ftype_v16qi
19057 = build_function_type_list (V4SI_type_node, V16QI_type_node,
19059 tree v2di_ftype_v16qi
19060 = build_function_type_list (V2DI_type_node, V16QI_type_node,
19062 tree v4si_ftype_v8hi
19063 = build_function_type_list (V4SI_type_node, V8HI_type_node,
19065 tree v2di_ftype_v8hi
19066 = build_function_type_list (V2DI_type_node, V8HI_type_node,
19068 tree v2di_ftype_v4si
19069 = build_function_type_list (V2DI_type_node, V4SI_type_node,
19071 tree v2di_ftype_pv2di
19072 = build_function_type_list (V2DI_type_node, pv2di_type_node,
19074 tree v16qi_ftype_v16qi_v16qi_int
19075 = build_function_type_list (V16QI_type_node, V16QI_type_node,
19076 V16QI_type_node, integer_type_node,
19078 tree v16qi_ftype_v16qi_v16qi_v16qi
19079 = build_function_type_list (V16QI_type_node, V16QI_type_node,
19080 V16QI_type_node, V16QI_type_node,
19082 tree v8hi_ftype_v8hi_v8hi_int
19083 = build_function_type_list (V8HI_type_node, V8HI_type_node,
19084 V8HI_type_node, integer_type_node,
19086 tree v4si_ftype_v4si_v4si_int
19087 = build_function_type_list (V4SI_type_node, V4SI_type_node,
19088 V4SI_type_node, integer_type_node,
19090 tree int_ftype_v2di_v2di
19091 = build_function_type_list (integer_type_node,
19092 V2DI_type_node, V2DI_type_node,
19094 tree int_ftype_v16qi_int_v16qi_int_int
19095 = build_function_type_list (integer_type_node,
19102 tree v16qi_ftype_v16qi_int_v16qi_int_int
19103 = build_function_type_list (V16QI_type_node,
19110 tree int_ftype_v16qi_v16qi_int
19111 = build_function_type_list (integer_type_node,
19117 /* SSE5 instructions */
19118 tree v2di_ftype_v2di_v2di_v2di
19119 = build_function_type_list (V2DI_type_node,
19125 tree v4si_ftype_v4si_v4si_v4si
19126 = build_function_type_list (V4SI_type_node,
19132 tree v4si_ftype_v4si_v4si_v2di
19133 = build_function_type_list (V4SI_type_node,
19139 tree v8hi_ftype_v8hi_v8hi_v8hi
19140 = build_function_type_list (V8HI_type_node,
19146 tree v8hi_ftype_v8hi_v8hi_v4si
19147 = build_function_type_list (V8HI_type_node,
19153 tree v2df_ftype_v2df_v2df_v16qi
19154 = build_function_type_list (V2DF_type_node,
19160 tree v4sf_ftype_v4sf_v4sf_v16qi
19161 = build_function_type_list (V4SF_type_node,
19167 tree v2di_ftype_v2di_si
19168 = build_function_type_list (V2DI_type_node,
19173 tree v4si_ftype_v4si_si
19174 = build_function_type_list (V4SI_type_node,
19179 tree v8hi_ftype_v8hi_si
19180 = build_function_type_list (V8HI_type_node,
19185 tree v16qi_ftype_v16qi_si
19186 = build_function_type_list (V16QI_type_node,
19190 tree v4sf_ftype_v4hi
19191 = build_function_type_list (V4SF_type_node,
19195 tree v4hi_ftype_v4sf
19196 = build_function_type_list (V4HI_type_node,
19200 tree v2di_ftype_v2di
19201 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
19205 /* The __float80 type. */
19206 if (TYPE_MODE (long_double_type_node) == XFmode)
19207 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
19211 /* The __float80 type. */
19212 tree float80_type_node = make_node (REAL_TYPE);
19214 TYPE_PRECISION (float80_type_node) = 80;
19215 layout_type (float80_type_node);
19216 (*lang_hooks.types.register_builtin_type) (float80_type_node,
19222 tree float128_type_node = make_node (REAL_TYPE);
19224 TYPE_PRECISION (float128_type_node) = 128;
19225 layout_type (float128_type_node);
19226 (*lang_hooks.types.register_builtin_type) (float128_type_node,
19229 /* TFmode support builtins. */
19230 ftype = build_function_type (float128_type_node,
19232 def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_infq", ftype, IX86_BUILTIN_INFQ);
19234 ftype = build_function_type_list (float128_type_node,
19235 float128_type_node,
19237 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_fabsq", ftype, IX86_BUILTIN_FABSQ);
19239 ftype = build_function_type_list (float128_type_node,
19240 float128_type_node,
19241 float128_type_node,
19243 def_builtin_const (OPTION_MASK_ISA_64BIT, "__builtin_copysignq", ftype, IX86_BUILTIN_COPYSIGNQ);
19246 /* Add all builtins with variable number of operands. */
19247 for (i = 0, d = bdesc_args;
19248 i < ARRAY_SIZE (bdesc_args);
19256 switch ((enum ix86_builtin_type) d->flag)
19258 case INT64_FTYPE_V4SF:
19259 type = int64_ftype_v4sf;
19261 case INT64_FTYPE_V2DF:
19262 type = int64_ftype_v2df;
19264 case INT_FTYPE_V16QI:
19265 type = int_ftype_v16qi;
19267 case INT_FTYPE_V8QI:
19268 type = int_ftype_v8qi;
19270 case INT_FTYPE_V4SF:
19271 type = int_ftype_v4sf;
19273 case INT_FTYPE_V2DF:
19274 type = int_ftype_v2df;
19276 case V16QI_FTYPE_V16QI:
19277 type = v16qi_ftype_v16qi;
19279 case V8HI_FTYPE_V8HI:
19280 type = v8hi_ftype_v8hi;
19282 case V8HI_FTYPE_V16QI:
19283 type = v8hi_ftype_v16qi;
19285 case V8QI_FTYPE_V8QI:
19286 type = v8qi_ftype_v8qi;
19288 case V4SI_FTYPE_V4SI:
19289 type = v4si_ftype_v4si;
19291 case V4SI_FTYPE_V16QI:
19292 type = v4si_ftype_v16qi;
19294 case V4SI_FTYPE_V8HI:
19295 type = v4si_ftype_v8hi;
19297 case V4HI_FTYPE_V4HI:
19298 type = v4hi_ftype_v4hi;
19300 case V4SI_FTYPE_V4SF:
19301 type = v4si_ftype_v4sf;
19303 case V4SI_FTYPE_V2DF:
19304 type = v4si_ftype_v2df;
19306 case V4SF_FTYPE_V4SF:
19307 type = v4sf_ftype_v4sf;
19309 case V4SF_FTYPE_V4SI:
19310 type = v4sf_ftype_v4si;
19312 case V4SF_FTYPE_V2DF:
19313 type = v4sf_ftype_v2df;
19315 case V2DI_FTYPE_V2DI:
19316 type = v2di_ftype_v2di;
19318 case V2DI_FTYPE_V16QI:
19319 type = v2di_ftype_v16qi;
19321 case V2DI_FTYPE_V8HI:
19322 type = v2di_ftype_v8hi;
19324 case V2DI_FTYPE_V4SI:
19325 type = v2di_ftype_v4si;
19327 case V2SI_FTYPE_V2SI:
19328 type = v2si_ftype_v2si;
19330 case V2SI_FTYPE_V4SF:
19331 type = v2si_ftype_v4sf;
19333 case V2SI_FTYPE_V2DF:
19334 type = v2si_ftype_v2df;
19336 case V2SI_FTYPE_V2SF:
19337 type = v2si_ftype_v2sf;
19339 case V2DF_FTYPE_V4SF:
19340 type = v2df_ftype_v4sf;
19342 case V2DF_FTYPE_V2DF:
19343 type = v2df_ftype_v2df;
19345 case V2DF_FTYPE_V2SI:
19346 type = v2df_ftype_v2si;
19348 case V2DF_FTYPE_V4SI:
19349 type = v2df_ftype_v4si;
19351 case V2SF_FTYPE_V2SF:
19352 type = v2sf_ftype_v2sf;
19354 case V2SF_FTYPE_V2SI:
19355 type = v2sf_ftype_v2si;
19357 case V4SF_FTYPE_V4SF_INT:
19358 type = v4sf_ftype_v4sf_int;
19360 case V2DI_FTYPE_V2DI_INT:
19361 type = v2di_ftype_v2di_int;
19363 case V2DF_FTYPE_V2DF_INT:
19364 type = v2df_ftype_v2df_int;
19366 case V16QI_FTYPE_V16QI_V16QI_V16QI:
19367 type = v16qi_ftype_v16qi_v16qi_v16qi;
19369 case V4SF_FTYPE_V4SF_V4SF_V4SF:
19370 type = v4sf_ftype_v4sf_v4sf_v4sf;
19372 case V2DF_FTYPE_V2DF_V2DF_V2DF:
19373 type = v2df_ftype_v2df_v2df_v2df;
19375 case V16QI_FTYPE_V16QI_V16QI_INT:
19376 type = v16qi_ftype_v16qi_v16qi_int;
19378 case V8HI_FTYPE_V8HI_V8HI_INT:
19379 type = v8hi_ftype_v8hi_v8hi_int;
19381 case V4SI_FTYPE_V4SI_V4SI_INT:
19382 type = v4si_ftype_v4si_v4si_int;
19384 case V4SF_FTYPE_V4SF_V4SF_INT:
19385 type = v4sf_ftype_v4sf_v4sf_int;
19387 case V2DI_FTYPE_V2DI_V2DI_INT:
19388 type = v2di_ftype_v2di_v2di_int;
19390 case V2DF_FTYPE_V2DF_V2DF_INT:
19391 type = v2df_ftype_v2df_v2df_int;
19394 gcc_unreachable ();
19397 def_builtin_const (d->mask, d->name, type, d->code);
19400 /* Add all builtins that are more or less simple operations on two
19402 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
19404 /* Use one of the operands; the target can have a different mode for
19405 mask-generating compares. */
19406 enum machine_mode mode;
19411 mode = insn_data[d->icode].operand[1].mode;
19416 type = v16qi_ftype_v16qi_v16qi;
19419 type = v8hi_ftype_v8hi_v8hi;
19422 type = v4si_ftype_v4si_v4si;
19425 type = v2di_ftype_v2di_v2di;
19428 type = v2df_ftype_v2df_v2df;
19431 type = v4sf_ftype_v4sf_v4sf;
19434 type = v8qi_ftype_v8qi_v8qi;
19437 type = v4hi_ftype_v4hi_v4hi;
19440 type = v2si_ftype_v2si_v2si;
19443 type = v1di_ftype_v1di_v1di;
19447 gcc_unreachable ();
19450 /* Override for comparisons. */
19451 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
19452 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
19453 type = v4si_ftype_v4sf_v4sf;
19455 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
19456 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
19457 type = v2di_ftype_v2df_v2df;
19459 if (d->icode == CODE_FOR_vec_pack_sfix_v2df)
19460 type = v4si_ftype_v2df_v2df;
19462 def_builtin_const (d->mask, d->name, type, d->code);
19465 /* pcmpestr[im] insns. */
19466 for (i = 0, d = bdesc_pcmpestr;
19467 i < ARRAY_SIZE (bdesc_pcmpestr);
19470 if (d->code == IX86_BUILTIN_PCMPESTRM128)
19471 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
19473 ftype = int_ftype_v16qi_int_v16qi_int_int;
19474 def_builtin_const (d->mask, d->name, ftype, d->code);
19477 /* pcmpistr[im] insns. */
19478 for (i = 0, d = bdesc_pcmpistr;
19479 i < ARRAY_SIZE (bdesc_pcmpistr);
19482 if (d->code == IX86_BUILTIN_PCMPISTRM128)
19483 ftype = v16qi_ftype_v16qi_v16qi_int;
19485 ftype = int_ftype_v16qi_v16qi_int;
19486 def_builtin_const (d->mask, d->name, ftype, d->code);
19489 /* Add the remaining MMX insns with somewhat more complicated types. */
19490 def_builtin (OPTION_MASK_ISA_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
19492 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllwi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSLLWI);
19493 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pslldi", v2si_ftype_v2si_int, IX86_BUILTIN_PSLLDI);
19494 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllqi", v1di_ftype_v1di_int, IX86_BUILTIN_PSLLQI);
19495 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSLLW);
19496 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSLLD);
19497 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psllq", v1di_ftype_v1di_v1di, IX86_BUILTIN_PSLLQ);
19499 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlwi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSRLWI);
19500 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrldi", v2si_ftype_v2si_int, IX86_BUILTIN_PSRLDI);
19501 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlqi", v1di_ftype_v1di_int, IX86_BUILTIN_PSRLQI);
19502 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSRLW);
19503 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSRLD);
19504 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrlq", v1di_ftype_v1di_v1di, IX86_BUILTIN_PSRLQ);
19506 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrawi", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSRAWI);
19507 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psradi", v2si_ftype_v2si_int, IX86_BUILTIN_PSRADI);
19508 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PSRAW);
19509 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_v2si, IX86_BUILTIN_PSRAD);
19511 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
19512 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
19514 /* comi/ucomi insns. */
19515 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
19516 if (d->mask == OPTION_MASK_ISA_SSE2)
19517 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
19519 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
19522 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
19523 def_builtin_const (d->mask, d->name, int_ftype_v2di_v2di, d->code);
19525 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
19526 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
19527 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
19529 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
19530 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
19531 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
19532 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
19533 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
19535 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
19537 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
19538 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
19540 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
19541 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
19542 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
19543 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
19545 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
19546 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
19547 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
19549 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_psadbw", v1di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
19551 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
19552 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
19553 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
19555 ftype = build_function_type_list (float_type_node,
19558 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_rsqrtf", ftype, IX86_BUILTIN_RSQRTF);
19560 /* Original 3DNow! */
19561 def_builtin (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
19562 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
19563 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
19564 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
19565 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
19566 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
19567 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
19568 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
19569 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
19570 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
19571 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
19572 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
19573 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
19574 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
19575 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
19576 def_builtin_const (OPTION_MASK_ISA_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
19578 /* 3DNow! extension as used in the Athlon CPU. */
19579 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
19580 def_builtin_const (OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
19583 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
19585 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
19586 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
19588 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
19589 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
19591 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
19592 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
19593 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
19595 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
19596 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
19597 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
19598 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
19600 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
19602 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
19603 def_builtin_const (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
19604 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
19605 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
19607 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
19608 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
19609 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
19611 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
19612 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
19614 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq", v1di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
19615 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
19617 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
19618 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
19619 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
19620 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
19621 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSLLW128);
19622 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSLLD128);
19623 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
19625 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
19626 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
19627 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
19628 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
19629 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRLW128);
19630 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRLD128);
19631 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
19633 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
19634 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
19635 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRAW128);
19636 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRAD128);
19638 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
19641 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
19642 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
19643 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_lddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
19646 def_builtin_const (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
19647 def_builtin_const (OPTION_MASK_ISA_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int, IX86_BUILTIN_PALIGNR);
19650 def_builtin (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_movntdqa", v2di_ftype_pv2di, IX86_BUILTIN_MOVNTDQA);
19651 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_pmuldq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULDQ128);
19654 ftype = build_function_type_list (unsigned_type_node,
19655 unsigned_type_node,
19656 unsigned_char_type_node,
19658 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32qi", ftype, IX86_BUILTIN_CRC32QI);
19659 ftype = build_function_type_list (unsigned_type_node,
19660 unsigned_type_node,
19661 short_unsigned_type_node,
19663 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32hi", ftype, IX86_BUILTIN_CRC32HI);
19664 ftype = build_function_type_list (unsigned_type_node,
19665 unsigned_type_node,
19666 unsigned_type_node,
19668 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32si", ftype, IX86_BUILTIN_CRC32SI);
19669 ftype = build_function_type_list (long_long_unsigned_type_node,
19670 long_long_unsigned_type_node,
19671 long_long_unsigned_type_node,
19673 def_builtin_const (OPTION_MASK_ISA_SSE4_2, "__builtin_ia32_crc32di", ftype, IX86_BUILTIN_CRC32DI);
19678 /* Define AES built-in functions only if AES is enabled. */
19679 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
19680 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
19681 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
19682 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
19683 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
19684 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
19690 /* Define PCLMUL built-in function only if PCLMUL is enabled. */
19691 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
19694 /* AMDFAM10 SSE4A New built-ins */
19695 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntsd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTSD);
19696 def_builtin (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_movntss", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTSS);
19697 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrqi", v2di_ftype_v2di_unsigned_unsigned, IX86_BUILTIN_EXTRQI);
19698 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_extrq", v2di_ftype_v2di_v16qi, IX86_BUILTIN_EXTRQ);
19699 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertqi", v2di_ftype_v2di_v2di_unsigned_unsigned, IX86_BUILTIN_INSERTQI);
19700 def_builtin_const (OPTION_MASK_ISA_SSE4A, "__builtin_ia32_insertq", v2di_ftype_v2di_v2di, IX86_BUILTIN_INSERTQ);
19702 /* Access to the vec_init patterns. */
19703 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
19704 integer_type_node, NULL_TREE);
19705 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
19707 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
19708 short_integer_type_node,
19709 short_integer_type_node,
19710 short_integer_type_node, NULL_TREE);
19711 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
19713 ftype = build_function_type_list (V8QI_type_node, char_type_node,
19714 char_type_node, char_type_node,
19715 char_type_node, char_type_node,
19716 char_type_node, char_type_node,
19717 char_type_node, NULL_TREE);
19718 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
19720 /* Access to the vec_extract patterns. */
19721 ftype = build_function_type_list (double_type_node, V2DF_type_node,
19722 integer_type_node, NULL_TREE);
19723 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
19725 ftype = build_function_type_list (long_long_integer_type_node,
19726 V2DI_type_node, integer_type_node,
19728 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
19730 ftype = build_function_type_list (float_type_node, V4SF_type_node,
19731 integer_type_node, NULL_TREE);
19732 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
19734 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
19735 integer_type_node, NULL_TREE);
19736 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
19738 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
19739 integer_type_node, NULL_TREE);
19740 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
19742 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
19743 integer_type_node, NULL_TREE);
19744 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
19746 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
19747 integer_type_node, NULL_TREE);
19748 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
19750 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
19751 integer_type_node, NULL_TREE);
19752 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
19754 /* Access to the vec_set patterns. */
19755 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
19757 integer_type_node, NULL_TREE);
19758 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
19760 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
19762 integer_type_node, NULL_TREE);
19763 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
19765 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
19767 integer_type_node, NULL_TREE);
19768 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
19770 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
19772 integer_type_node, NULL_TREE);
19773 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
19775 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
19777 integer_type_node, NULL_TREE);
19778 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
19780 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
19782 integer_type_node, NULL_TREE);
19783 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
19785 /* Add SSE5 multi-arg argument instructions */
19786 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
19788 tree mtype = NULL_TREE;
19793 switch ((enum multi_arg_type)d->flag)
19795 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
19796 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
19797 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
19798 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
19799 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
19800 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
19801 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
19802 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
19803 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
19804 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
19805 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
19806 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
19807 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
19808 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
19809 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
19810 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
19811 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
19812 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
19813 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
19814 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
19815 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
19816 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
19817 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
19818 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
19819 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
19820 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
19821 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
19822 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
19823 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
19824 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
19825 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
19826 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
19827 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
19828 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
19829 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
19830 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
19831 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
19832 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
19833 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
19834 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
19835 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
19836 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
19837 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
19838 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
19839 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
19840 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
19841 case MULTI_ARG_UNKNOWN:
19843 gcc_unreachable ();
19847 def_builtin_const (d->mask, d->name, mtype, d->code);
19852 ix86_init_builtins (void)
19855 ix86_init_mmx_sse_builtins ();
19858 /* Errors in the source file can cause expand_expr to return const0_rtx
19859 where we expect a vector. To avoid crashing, use one of the vector
19860 clear instructions. */
19862 safe_vector_operand (rtx x, enum machine_mode mode)
19864 if (x == const0_rtx)
19865 x = CONST0_RTX (mode);
19869 /* Subroutine of ix86_expand_builtin to take care of SSE insns with
19870 variable number of operands. */
19873 ix86_expand_args_builtin (enum insn_code icode, tree exp,
19874 enum ix86_builtin_type type, rtx target)
19877 unsigned int i, nargs;
19878 int num_memory = 0;
19882 enum machine_mode mode;
19884 bool last_arg_constant = false;
19885 const struct insn_data *insn_p = &insn_data[icode];
19886 enum machine_mode tmode = insn_p->operand[0].mode;
19890 case FLOAT128_FTYPE_FLOAT128:
19891 case INT64_FTYPE_V4SF:
19892 case INT64_FTYPE_V2DF:
19893 case INT_FTYPE_V16QI:
19894 case INT_FTYPE_V8QI:
19895 case INT_FTYPE_V4SF:
19896 case INT_FTYPE_V2DF:
19897 case V16QI_FTYPE_V16QI:
19898 case V8HI_FTYPE_V8HI:
19899 case V8HI_FTYPE_V16QI:
19900 case V8QI_FTYPE_V8QI:
19901 case V4SI_FTYPE_V4SI:
19902 case V4SI_FTYPE_V16QI:
19903 case V4SI_FTYPE_V4SF:
19904 case V4SI_FTYPE_V8HI:
19905 case V4SI_FTYPE_V2DF:
19906 case V4HI_FTYPE_V4HI:
19907 case V4SF_FTYPE_V4SF:
19908 case V4SF_FTYPE_V4SI:
19909 case V4SF_FTYPE_V2DF:
19910 case V2DI_FTYPE_V2DI:
19911 case V2DI_FTYPE_V16QI:
19912 case V2DI_FTYPE_V8HI:
19913 case V2DI_FTYPE_V4SI:
19914 case V2DF_FTYPE_V2DF:
19915 case V2DF_FTYPE_V4SI:
19916 case V2DF_FTYPE_V4SF:
19917 case V2DF_FTYPE_V2SI:
19918 case V2SI_FTYPE_V2SI:
19919 case V2SI_FTYPE_V4SF:
19920 case V2SI_FTYPE_V2SF:
19921 case V2SI_FTYPE_V2DF:
19922 case V2SF_FTYPE_V2SF:
19923 case V2SF_FTYPE_V2SI:
19926 case V4SF_FTYPE_V4SF_INT:
19927 case V2DI_FTYPE_V2DI_INT:
19928 case V2DF_FTYPE_V2DF_INT:
19930 last_arg_constant = true;
19932 case V16QI_FTYPE_V16QI_V16QI_V16QI:
19933 case V4SF_FTYPE_V4SF_V4SF_V4SF:
19934 case V2DF_FTYPE_V2DF_V2DF_V2DF:
19937 case V16QI_FTYPE_V16QI_V16QI_INT:
19938 case V8HI_FTYPE_V8HI_V8HI_INT:
19939 case V4SI_FTYPE_V4SI_V4SI_INT:
19940 case V4SF_FTYPE_V4SF_V4SF_INT:
19941 case V2DI_FTYPE_V2DI_V2DI_INT:
19942 case V2DF_FTYPE_V2DF_V2DF_INT:
19944 last_arg_constant = true;
19947 gcc_unreachable ();
19950 gcc_assert (nargs <= ARRAY_SIZE (args));
19954 || GET_MODE (target) != tmode
19955 || ! (*insn_p->operand[0].predicate) (target, tmode))
19956 target = gen_reg_rtx (tmode);
19958 for (i = 0; i < nargs; i++)
19960 tree arg = CALL_EXPR_ARG (exp, i);
19961 rtx op = expand_normal (arg);
19962 enum machine_mode mode = insn_p->operand[i + 1].mode;
19963 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
19965 if (last_arg_constant && (i + 1) == nargs)
19970 case CODE_FOR_sse4_1_roundpd:
19971 case CODE_FOR_sse4_1_roundps:
19972 case CODE_FOR_sse4_1_roundsd:
19973 case CODE_FOR_sse4_1_roundss:
19974 case CODE_FOR_sse4_1_blendps:
19975 error ("the last argument must be a 4-bit immediate");
19978 case CODE_FOR_sse4_1_blendpd:
19979 error ("the last argument must be a 2-bit immediate");
19983 error ("the last argument must be an 8-bit immediate");
19989 if (VECTOR_MODE_P (mode))
19990 op = safe_vector_operand (op, mode);
19992 /* If we aren't optimizing, only allow one memory operand to
19994 if (memory_operand (op, mode))
19997 gcc_assert (GET_MODE (op) == mode
19998 || GET_MODE (op) == VOIDmode);
20000 if (optimize || !match || num_memory > 1)
20001 op = copy_to_mode_reg (mode, op);
20005 args[i].mode = mode;
20011 pat = GEN_FCN (icode) (target, args[0].op);
20014 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
20017 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
20021 gcc_unreachable ();
20031 /* Subroutine of ix86_expand_builtin to take care of crc32 insns. */
20034 ix86_expand_crc32 (enum insn_code icode, tree exp, rtx target)
20037 tree arg0 = CALL_EXPR_ARG (exp, 0);
20038 tree arg1 = CALL_EXPR_ARG (exp, 1);
20039 rtx op0 = expand_normal (arg0);
20040 rtx op1 = expand_normal (arg1);
20041 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20042 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20043 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
20047 || GET_MODE (target) != tmode
20048 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20049 target = gen_reg_rtx (tmode);
20051 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
20052 op0 = copy_to_mode_reg (mode0, op0);
20053 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
20055 op1 = copy_to_reg (op1);
20056 op1 = simplify_gen_subreg (mode1, op1, GET_MODE (op1), 0);
20059 pat = GEN_FCN (icode) (target, op0, op1);
20066 /* Subroutine of ix86_expand_builtin to take care of binop insns
20067 with an immediate. */
20070 ix86_expand_binop_imm_builtin (enum insn_code icode, tree exp,
20074 tree arg0 = CALL_EXPR_ARG (exp, 0);
20075 tree arg1 = CALL_EXPR_ARG (exp, 1);
20076 rtx op0 = expand_normal (arg0);
20077 rtx op1 = expand_normal (arg1);
20078 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20079 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20080 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
20082 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
20084 op0 = copy_to_reg (op0);
20085 op0 = simplify_gen_subreg (mode0, op0, GET_MODE (op0), 0);
20088 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
20090 error ("the last operand must be an immediate");
20094 target = gen_reg_rtx (V2DImode);
20095 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target,
20104 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
20107 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
20110 tree arg0 = CALL_EXPR_ARG (exp, 0);
20111 tree arg1 = CALL_EXPR_ARG (exp, 1);
20112 rtx op0 = expand_normal (arg0);
20113 rtx op1 = expand_normal (arg1);
20114 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20115 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20116 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
20118 if (VECTOR_MODE_P (mode0))
20119 op0 = safe_vector_operand (op0, mode0);
20120 if (VECTOR_MODE_P (mode1))
20121 op1 = safe_vector_operand (op1, mode1);
20123 if (optimize || !target
20124 || GET_MODE (target) != tmode
20125 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20126 target = gen_reg_rtx (tmode);
20128 if (GET_MODE (op1) == SImode && mode1 == TImode)
20130 rtx x = gen_reg_rtx (V4SImode);
20131 emit_insn (gen_sse2_loadd (x, op1));
20132 op1 = gen_lowpart (TImode, x);
20135 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
20136 op0 = copy_to_mode_reg (mode0, op0);
20137 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
20138 op1 = copy_to_mode_reg (mode1, op1);
20140 /* ??? Using ix86_fixup_binary_operands is problematic when
20141 we've got mismatched modes. Fake it. */
20147 if (tmode == mode0 && tmode == mode1)
20149 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
20153 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
20155 op0 = force_reg (mode0, op0);
20156 op1 = force_reg (mode1, op1);
20157 target = gen_reg_rtx (tmode);
20160 pat = GEN_FCN (icode) (target, op0, op1);
20167 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
20170 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
20171 enum multi_arg_type m_type,
20172 enum insn_code sub_code)
20177 bool comparison_p = false;
20179 bool last_arg_constant = false;
20180 int num_memory = 0;
20183 enum machine_mode mode;
20186 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20190 case MULTI_ARG_3_SF:
20191 case MULTI_ARG_3_DF:
20192 case MULTI_ARG_3_DI:
20193 case MULTI_ARG_3_SI:
20194 case MULTI_ARG_3_SI_DI:
20195 case MULTI_ARG_3_HI:
20196 case MULTI_ARG_3_HI_SI:
20197 case MULTI_ARG_3_QI:
20198 case MULTI_ARG_3_PERMPS:
20199 case MULTI_ARG_3_PERMPD:
20203 case MULTI_ARG_2_SF:
20204 case MULTI_ARG_2_DF:
20205 case MULTI_ARG_2_DI:
20206 case MULTI_ARG_2_SI:
20207 case MULTI_ARG_2_HI:
20208 case MULTI_ARG_2_QI:
20212 case MULTI_ARG_2_DI_IMM:
20213 case MULTI_ARG_2_SI_IMM:
20214 case MULTI_ARG_2_HI_IMM:
20215 case MULTI_ARG_2_QI_IMM:
20217 last_arg_constant = true;
20220 case MULTI_ARG_1_SF:
20221 case MULTI_ARG_1_DF:
20222 case MULTI_ARG_1_DI:
20223 case MULTI_ARG_1_SI:
20224 case MULTI_ARG_1_HI:
20225 case MULTI_ARG_1_QI:
20226 case MULTI_ARG_1_SI_DI:
20227 case MULTI_ARG_1_HI_DI:
20228 case MULTI_ARG_1_HI_SI:
20229 case MULTI_ARG_1_QI_DI:
20230 case MULTI_ARG_1_QI_SI:
20231 case MULTI_ARG_1_QI_HI:
20232 case MULTI_ARG_1_PH2PS:
20233 case MULTI_ARG_1_PS2PH:
20237 case MULTI_ARG_2_SF_CMP:
20238 case MULTI_ARG_2_DF_CMP:
20239 case MULTI_ARG_2_DI_CMP:
20240 case MULTI_ARG_2_SI_CMP:
20241 case MULTI_ARG_2_HI_CMP:
20242 case MULTI_ARG_2_QI_CMP:
20244 comparison_p = true;
20247 case MULTI_ARG_2_SF_TF:
20248 case MULTI_ARG_2_DF_TF:
20249 case MULTI_ARG_2_DI_TF:
20250 case MULTI_ARG_2_SI_TF:
20251 case MULTI_ARG_2_HI_TF:
20252 case MULTI_ARG_2_QI_TF:
20257 case MULTI_ARG_UNKNOWN:
20259 gcc_unreachable ();
20262 if (optimize || !target
20263 || GET_MODE (target) != tmode
20264 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20265 target = gen_reg_rtx (tmode);
20267 gcc_assert (nargs <= 4);
20269 for (i = 0; i < nargs; i++)
20271 tree arg = CALL_EXPR_ARG (exp, i);
20272 rtx op = expand_normal (arg);
20273 int adjust = (comparison_p) ? 1 : 0;
20274 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
20276 if (last_arg_constant && i == nargs-1)
20278 if (GET_CODE (op) != CONST_INT)
20280 error ("last argument must be an immediate");
20281 return gen_reg_rtx (tmode);
20286 if (VECTOR_MODE_P (mode))
20287 op = safe_vector_operand (op, mode);
20289 /* If we aren't optimizing, only allow one memory operand to be
20291 if (memory_operand (op, mode))
20294 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
20297 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
20299 op = force_reg (mode, op);
20303 args[i].mode = mode;
20309 pat = GEN_FCN (icode) (target, args[0].op);
20314 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
20315 GEN_INT ((int)sub_code));
20316 else if (! comparison_p)
20317 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
20320 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
20324 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
20329 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
20333 gcc_unreachable ();
20343 /* Subroutine of ix86_expand_builtin to take care of stores. */
20346 ix86_expand_store_builtin (enum insn_code icode, tree exp)
20349 tree arg0 = CALL_EXPR_ARG (exp, 0);
20350 tree arg1 = CALL_EXPR_ARG (exp, 1);
20351 rtx op0 = expand_normal (arg0);
20352 rtx op1 = expand_normal (arg1);
20353 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
20354 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
20356 if (VECTOR_MODE_P (mode1))
20357 op1 = safe_vector_operand (op1, mode1);
20359 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20360 op1 = copy_to_mode_reg (mode1, op1);
20362 pat = GEN_FCN (icode) (op0, op1);
20368 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
20371 ix86_expand_unop_builtin (enum insn_code icode, tree exp,
20372 rtx target, int do_load)
20375 tree arg0 = CALL_EXPR_ARG (exp, 0);
20376 rtx op0 = expand_normal (arg0);
20377 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20378 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20380 if (optimize || !target
20381 || GET_MODE (target) != tmode
20382 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20383 target = gen_reg_rtx (tmode);
20385 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
20388 if (VECTOR_MODE_P (mode0))
20389 op0 = safe_vector_operand (op0, mode0);
20391 if ((optimize && !register_operand (op0, mode0))
20392 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20393 op0 = copy_to_mode_reg (mode0, op0);
20396 pat = GEN_FCN (icode) (target, op0);
20403 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
20404 sqrtss, sqrtsd, rsqrtss, rsqrtsf, rcpss. */
20407 ix86_expand_unop1_builtin (enum insn_code icode, tree exp, rtx target)
20410 tree arg0 = CALL_EXPR_ARG (exp, 0);
20411 rtx op1, op0 = expand_normal (arg0);
20412 enum machine_mode tmode = insn_data[icode].operand[0].mode;
20413 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
20415 if (optimize || !target
20416 || GET_MODE (target) != tmode
20417 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
20418 target = gen_reg_rtx (tmode);
20420 if (VECTOR_MODE_P (mode0))
20421 op0 = safe_vector_operand (op0, mode0);
20423 if ((optimize && !register_operand (op0, mode0))
20424 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
20425 op0 = copy_to_mode_reg (mode0, op0);
20428 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
20429 op1 = copy_to_mode_reg (mode0, op1);
20431 pat = GEN_FCN (icode) (target, op0, op1);
20438 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
20441 ix86_expand_sse_compare (const struct builtin_description *d, tree exp,
20445 tree arg0 = CALL_EXPR_ARG (exp, 0);
20446 tree arg1 = CALL_EXPR_ARG (exp, 1);
20447 rtx op0 = expand_normal (arg0);
20448 rtx op1 = expand_normal (arg1);
20450 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
20451 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
20452 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
20453 enum rtx_code comparison = d->comparison;
20455 if (VECTOR_MODE_P (mode0))
20456 op0 = safe_vector_operand (op0, mode0);
20457 if (VECTOR_MODE_P (mode1))
20458 op1 = safe_vector_operand (op1, mode1);
20460 /* Swap operands if we have a comparison that isn't available in
20462 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20464 rtx tmp = gen_reg_rtx (mode1);
20465 emit_move_insn (tmp, op1);
20470 if (optimize || !target
20471 || GET_MODE (target) != tmode
20472 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
20473 target = gen_reg_rtx (tmode);
20475 if ((optimize && !register_operand (op0, mode0))
20476 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
20477 op0 = copy_to_mode_reg (mode0, op0);
20478 if ((optimize && !register_operand (op1, mode1))
20479 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
20480 op1 = copy_to_mode_reg (mode1, op1);
20482 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
20483 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
20490 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
20493 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
20497 tree arg0 = CALL_EXPR_ARG (exp, 0);
20498 tree arg1 = CALL_EXPR_ARG (exp, 1);
20499 rtx op0 = expand_normal (arg0);
20500 rtx op1 = expand_normal (arg1);
20501 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20502 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20503 enum rtx_code comparison = d->comparison;
20505 if (VECTOR_MODE_P (mode0))
20506 op0 = safe_vector_operand (op0, mode0);
20507 if (VECTOR_MODE_P (mode1))
20508 op1 = safe_vector_operand (op1, mode1);
20510 /* Swap operands if we have a comparison that isn't available in
20512 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
20519 target = gen_reg_rtx (SImode);
20520 emit_move_insn (target, const0_rtx);
20521 target = gen_rtx_SUBREG (QImode, target, 0);
20523 if ((optimize && !register_operand (op0, mode0))
20524 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20525 op0 = copy_to_mode_reg (mode0, op0);
20526 if ((optimize && !register_operand (op1, mode1))
20527 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20528 op1 = copy_to_mode_reg (mode1, op1);
20530 pat = GEN_FCN (d->icode) (op0, op1);
20534 emit_insn (gen_rtx_SET (VOIDmode,
20535 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20536 gen_rtx_fmt_ee (comparison, QImode,
20540 return SUBREG_REG (target);
20543 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
20546 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
20550 tree arg0 = CALL_EXPR_ARG (exp, 0);
20551 tree arg1 = CALL_EXPR_ARG (exp, 1);
20552 rtx op0 = expand_normal (arg0);
20553 rtx op1 = expand_normal (arg1);
20554 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
20555 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
20556 enum rtx_code comparison = d->comparison;
20558 if (VECTOR_MODE_P (mode0))
20559 op0 = safe_vector_operand (op0, mode0);
20560 if (VECTOR_MODE_P (mode1))
20561 op1 = safe_vector_operand (op1, mode1);
20563 target = gen_reg_rtx (SImode);
20564 emit_move_insn (target, const0_rtx);
20565 target = gen_rtx_SUBREG (QImode, target, 0);
20567 if ((optimize && !register_operand (op0, mode0))
20568 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
20569 op0 = copy_to_mode_reg (mode0, op0);
20570 if ((optimize && !register_operand (op1, mode1))
20571 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
20572 op1 = copy_to_mode_reg (mode1, op1);
20574 pat = GEN_FCN (d->icode) (op0, op1);
20578 emit_insn (gen_rtx_SET (VOIDmode,
20579 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20580 gen_rtx_fmt_ee (comparison, QImode,
20584 return SUBREG_REG (target);
20587 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
20590 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
20591 tree exp, rtx target)
20594 tree arg0 = CALL_EXPR_ARG (exp, 0);
20595 tree arg1 = CALL_EXPR_ARG (exp, 1);
20596 tree arg2 = CALL_EXPR_ARG (exp, 2);
20597 tree arg3 = CALL_EXPR_ARG (exp, 3);
20598 tree arg4 = CALL_EXPR_ARG (exp, 4);
20599 rtx scratch0, scratch1;
20600 rtx op0 = expand_normal (arg0);
20601 rtx op1 = expand_normal (arg1);
20602 rtx op2 = expand_normal (arg2);
20603 rtx op3 = expand_normal (arg3);
20604 rtx op4 = expand_normal (arg4);
20605 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
20607 tmode0 = insn_data[d->icode].operand[0].mode;
20608 tmode1 = insn_data[d->icode].operand[1].mode;
20609 modev2 = insn_data[d->icode].operand[2].mode;
20610 modei3 = insn_data[d->icode].operand[3].mode;
20611 modev4 = insn_data[d->icode].operand[4].mode;
20612 modei5 = insn_data[d->icode].operand[5].mode;
20613 modeimm = insn_data[d->icode].operand[6].mode;
20615 if (VECTOR_MODE_P (modev2))
20616 op0 = safe_vector_operand (op0, modev2);
20617 if (VECTOR_MODE_P (modev4))
20618 op2 = safe_vector_operand (op2, modev4);
20620 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20621 op0 = copy_to_mode_reg (modev2, op0);
20622 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
20623 op1 = copy_to_mode_reg (modei3, op1);
20624 if ((optimize && !register_operand (op2, modev4))
20625 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
20626 op2 = copy_to_mode_reg (modev4, op2);
20627 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
20628 op3 = copy_to_mode_reg (modei5, op3);
20630 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
20632 error ("the fifth argument must be a 8-bit immediate");
20636 if (d->code == IX86_BUILTIN_PCMPESTRI128)
20638 if (optimize || !target
20639 || GET_MODE (target) != tmode0
20640 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20641 target = gen_reg_rtx (tmode0);
20643 scratch1 = gen_reg_rtx (tmode1);
20645 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
20647 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
20649 if (optimize || !target
20650 || GET_MODE (target) != tmode1
20651 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20652 target = gen_reg_rtx (tmode1);
20654 scratch0 = gen_reg_rtx (tmode0);
20656 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
20660 gcc_assert (d->flag);
20662 scratch0 = gen_reg_rtx (tmode0);
20663 scratch1 = gen_reg_rtx (tmode1);
20665 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
20675 target = gen_reg_rtx (SImode);
20676 emit_move_insn (target, const0_rtx);
20677 target = gen_rtx_SUBREG (QImode, target, 0);
20680 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20681 gen_rtx_fmt_ee (EQ, QImode,
20682 gen_rtx_REG ((enum machine_mode) d->flag,
20685 return SUBREG_REG (target);
20692 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
20695 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
20696 tree exp, rtx target)
20699 tree arg0 = CALL_EXPR_ARG (exp, 0);
20700 tree arg1 = CALL_EXPR_ARG (exp, 1);
20701 tree arg2 = CALL_EXPR_ARG (exp, 2);
20702 rtx scratch0, scratch1;
20703 rtx op0 = expand_normal (arg0);
20704 rtx op1 = expand_normal (arg1);
20705 rtx op2 = expand_normal (arg2);
20706 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
20708 tmode0 = insn_data[d->icode].operand[0].mode;
20709 tmode1 = insn_data[d->icode].operand[1].mode;
20710 modev2 = insn_data[d->icode].operand[2].mode;
20711 modev3 = insn_data[d->icode].operand[3].mode;
20712 modeimm = insn_data[d->icode].operand[4].mode;
20714 if (VECTOR_MODE_P (modev2))
20715 op0 = safe_vector_operand (op0, modev2);
20716 if (VECTOR_MODE_P (modev3))
20717 op1 = safe_vector_operand (op1, modev3);
20719 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
20720 op0 = copy_to_mode_reg (modev2, op0);
20721 if ((optimize && !register_operand (op1, modev3))
20722 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
20723 op1 = copy_to_mode_reg (modev3, op1);
20725 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
20727 error ("the third argument must be a 8-bit immediate");
20731 if (d->code == IX86_BUILTIN_PCMPISTRI128)
20733 if (optimize || !target
20734 || GET_MODE (target) != tmode0
20735 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
20736 target = gen_reg_rtx (tmode0);
20738 scratch1 = gen_reg_rtx (tmode1);
20740 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
20742 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
20744 if (optimize || !target
20745 || GET_MODE (target) != tmode1
20746 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
20747 target = gen_reg_rtx (tmode1);
20749 scratch0 = gen_reg_rtx (tmode0);
20751 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
20755 gcc_assert (d->flag);
20757 scratch0 = gen_reg_rtx (tmode0);
20758 scratch1 = gen_reg_rtx (tmode1);
20760 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
20770 target = gen_reg_rtx (SImode);
20771 emit_move_insn (target, const0_rtx);
20772 target = gen_rtx_SUBREG (QImode, target, 0);
20775 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
20776 gen_rtx_fmt_ee (EQ, QImode,
20777 gen_rtx_REG ((enum machine_mode) d->flag,
20780 return SUBREG_REG (target);
20786 /* Return the integer constant in ARG. Constrain it to be in the range
20787 of the subparts of VEC_TYPE; issue an error if not. */
20790 get_element_number (tree vec_type, tree arg)
20792 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
20794 if (!host_integerp (arg, 1)
20795 || (elt = tree_low_cst (arg, 1), elt > max))
20797 error ("selector must be an integer constant in the range 0..%wi", max);
20804 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20805 ix86_expand_vector_init. We DO have language-level syntax for this, in
20806 the form of (type){ init-list }. Except that since we can't place emms
20807 instructions from inside the compiler, we can't allow the use of MMX
20808 registers unless the user explicitly asks for it. So we do *not* define
20809 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
20810 we have builtins invoked by mmintrin.h that gives us license to emit
20811 these sorts of instructions. */
20814 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
20816 enum machine_mode tmode = TYPE_MODE (type);
20817 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
20818 int i, n_elt = GET_MODE_NUNITS (tmode);
20819 rtvec v = rtvec_alloc (n_elt);
20821 gcc_assert (VECTOR_MODE_P (tmode));
20822 gcc_assert (call_expr_nargs (exp) == n_elt);
20824 for (i = 0; i < n_elt; ++i)
20826 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
20827 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
20830 if (!target || !register_operand (target, tmode))
20831 target = gen_reg_rtx (tmode);
20833 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
20837 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20838 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
20839 had a language-level syntax for referencing vector elements. */
20842 ix86_expand_vec_ext_builtin (tree exp, rtx target)
20844 enum machine_mode tmode, mode0;
20849 arg0 = CALL_EXPR_ARG (exp, 0);
20850 arg1 = CALL_EXPR_ARG (exp, 1);
20852 op0 = expand_normal (arg0);
20853 elt = get_element_number (TREE_TYPE (arg0), arg1);
20855 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
20856 mode0 = TYPE_MODE (TREE_TYPE (arg0));
20857 gcc_assert (VECTOR_MODE_P (mode0));
20859 op0 = force_reg (mode0, op0);
20861 if (optimize || !target || !register_operand (target, tmode))
20862 target = gen_reg_rtx (tmode);
20864 ix86_expand_vector_extract (true, target, op0, elt);
20869 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
20870 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
20871 a language-level syntax for referencing vector elements. */
20874 ix86_expand_vec_set_builtin (tree exp)
20876 enum machine_mode tmode, mode1;
20877 tree arg0, arg1, arg2;
20879 rtx op0, op1, target;
20881 arg0 = CALL_EXPR_ARG (exp, 0);
20882 arg1 = CALL_EXPR_ARG (exp, 1);
20883 arg2 = CALL_EXPR_ARG (exp, 2);
20885 tmode = TYPE_MODE (TREE_TYPE (arg0));
20886 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
20887 gcc_assert (VECTOR_MODE_P (tmode));
20889 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
20890 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
20891 elt = get_element_number (TREE_TYPE (arg0), arg2);
20893 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
20894 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
20896 op0 = force_reg (tmode, op0);
20897 op1 = force_reg (mode1, op1);
20899 /* OP0 is the source of these builtin functions and shouldn't be
20900 modified. Create a copy, use it and return it as target. */
20901 target = gen_reg_rtx (tmode);
20902 emit_move_insn (target, op0);
20903 ix86_expand_vector_set (true, target, op1, elt);
20908 /* Expand an expression EXP that calls a built-in function,
20909 with result going to TARGET if that's convenient
20910 (and in mode MODE if that's convenient).
20911 SUBTARGET may be used as the target for computing one of EXP's operands.
20912 IGNORE is nonzero if the value is to be ignored. */
20915 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
20916 enum machine_mode mode ATTRIBUTE_UNUSED,
20917 int ignore ATTRIBUTE_UNUSED)
20919 const struct builtin_description *d;
20921 enum insn_code icode;
20922 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
20923 tree arg0, arg1, arg2, arg3;
20924 rtx op0, op1, op2, op3, pat;
20925 enum machine_mode tmode, mode0, mode1, mode2, mode3, mode4;
20926 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
20930 case IX86_BUILTIN_EMMS:
20931 emit_insn (gen_mmx_emms ());
20934 case IX86_BUILTIN_SFENCE:
20935 emit_insn (gen_sse_sfence ());
20938 case IX86_BUILTIN_MASKMOVQ:
20939 case IX86_BUILTIN_MASKMOVDQU:
20940 icode = (fcode == IX86_BUILTIN_MASKMOVQ
20941 ? CODE_FOR_mmx_maskmovq
20942 : CODE_FOR_sse2_maskmovdqu);
20943 /* Note the arg order is different from the operand order. */
20944 arg1 = CALL_EXPR_ARG (exp, 0);
20945 arg2 = CALL_EXPR_ARG (exp, 1);
20946 arg0 = CALL_EXPR_ARG (exp, 2);
20947 op0 = expand_normal (arg0);
20948 op1 = expand_normal (arg1);
20949 op2 = expand_normal (arg2);
20950 mode0 = insn_data[icode].operand[0].mode;
20951 mode1 = insn_data[icode].operand[1].mode;
20952 mode2 = insn_data[icode].operand[2].mode;
20954 op0 = force_reg (Pmode, op0);
20955 op0 = gen_rtx_MEM (mode1, op0);
20957 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
20958 op0 = copy_to_mode_reg (mode0, op0);
20959 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
20960 op1 = copy_to_mode_reg (mode1, op1);
20961 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
20962 op2 = copy_to_mode_reg (mode2, op2);
20963 pat = GEN_FCN (icode) (op0, op1, op2);
20969 case IX86_BUILTIN_RSQRTF:
20970 return ix86_expand_unop1_builtin (CODE_FOR_rsqrtsf2, exp, target);
20972 case IX86_BUILTIN_SQRTSS:
20973 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, exp, target);
20974 case IX86_BUILTIN_RSQRTSS:
20975 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, exp, target);
20976 case IX86_BUILTIN_RCPSS:
20977 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, exp, target);
20979 case IX86_BUILTIN_LOADUPS:
20980 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, exp, target, 1);
20982 case IX86_BUILTIN_STOREUPS:
20983 return ix86_expand_store_builtin (CODE_FOR_sse_movups, exp);
20985 case IX86_BUILTIN_LOADHPS:
20986 case IX86_BUILTIN_LOADLPS:
20987 case IX86_BUILTIN_LOADHPD:
20988 case IX86_BUILTIN_LOADLPD:
20989 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
20990 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
20991 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
20992 : CODE_FOR_sse2_loadlpd);
20993 arg0 = CALL_EXPR_ARG (exp, 0);
20994 arg1 = CALL_EXPR_ARG (exp, 1);
20995 op0 = expand_normal (arg0);
20996 op1 = expand_normal (arg1);
20997 tmode = insn_data[icode].operand[0].mode;
20998 mode0 = insn_data[icode].operand[1].mode;
20999 mode1 = insn_data[icode].operand[2].mode;
21001 op0 = force_reg (mode0, op0);
21002 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
21003 if (optimize || target == 0
21004 || GET_MODE (target) != tmode
21005 || !register_operand (target, tmode))
21006 target = gen_reg_rtx (tmode);
21007 pat = GEN_FCN (icode) (target, op0, op1);
21013 case IX86_BUILTIN_STOREHPS:
21014 case IX86_BUILTIN_STORELPS:
21015 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
21016 : CODE_FOR_sse_storelps);
21017 arg0 = CALL_EXPR_ARG (exp, 0);
21018 arg1 = CALL_EXPR_ARG (exp, 1);
21019 op0 = expand_normal (arg0);
21020 op1 = expand_normal (arg1);
21021 mode0 = insn_data[icode].operand[0].mode;
21022 mode1 = insn_data[icode].operand[1].mode;
21024 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
21025 op1 = force_reg (mode1, op1);
21027 pat = GEN_FCN (icode) (op0, op1);
21033 case IX86_BUILTIN_MOVNTPS:
21034 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, exp);
21035 case IX86_BUILTIN_MOVNTQ:
21036 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, exp);
21038 case IX86_BUILTIN_LDMXCSR:
21039 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
21040 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
21041 emit_move_insn (target, op0);
21042 emit_insn (gen_sse_ldmxcsr (target));
21045 case IX86_BUILTIN_STMXCSR:
21046 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
21047 emit_insn (gen_sse_stmxcsr (target));
21048 return copy_to_mode_reg (SImode, target);
21050 case IX86_BUILTIN_PSHUFW:
21051 case IX86_BUILTIN_PSHUFD:
21052 case IX86_BUILTIN_PSHUFHW:
21053 case IX86_BUILTIN_PSHUFLW:
21054 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
21055 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
21056 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
21057 : CODE_FOR_mmx_pshufw);
21058 arg0 = CALL_EXPR_ARG (exp, 0);
21059 arg1 = CALL_EXPR_ARG (exp, 1);
21060 op0 = expand_normal (arg0);
21061 op1 = expand_normal (arg1);
21062 tmode = insn_data[icode].operand[0].mode;
21063 mode1 = insn_data[icode].operand[1].mode;
21064 mode2 = insn_data[icode].operand[2].mode;
21066 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21067 op0 = copy_to_mode_reg (mode1, op0);
21068 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21070 /* @@@ better error message */
21071 error ("mask must be an immediate");
21075 || GET_MODE (target) != tmode
21076 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21077 target = gen_reg_rtx (tmode);
21078 pat = GEN_FCN (icode) (target, op0, op1);
21084 case IX86_BUILTIN_PSLLW:
21085 case IX86_BUILTIN_PSLLWI:
21086 icode = CODE_FOR_mmx_ashlv4hi3;
21088 case IX86_BUILTIN_PSLLD:
21089 case IX86_BUILTIN_PSLLDI:
21090 icode = CODE_FOR_mmx_ashlv2si3;
21092 case IX86_BUILTIN_PSLLQ:
21093 case IX86_BUILTIN_PSLLQI:
21094 icode = CODE_FOR_mmx_ashlv1di3;
21096 case IX86_BUILTIN_PSRAW:
21097 case IX86_BUILTIN_PSRAWI:
21098 icode = CODE_FOR_mmx_ashrv4hi3;
21100 case IX86_BUILTIN_PSRAD:
21101 case IX86_BUILTIN_PSRADI:
21102 icode = CODE_FOR_mmx_ashrv2si3;
21104 case IX86_BUILTIN_PSRLW:
21105 case IX86_BUILTIN_PSRLWI:
21106 icode = CODE_FOR_mmx_lshrv4hi3;
21108 case IX86_BUILTIN_PSRLD:
21109 case IX86_BUILTIN_PSRLDI:
21110 icode = CODE_FOR_mmx_lshrv2si3;
21112 case IX86_BUILTIN_PSRLQ:
21113 case IX86_BUILTIN_PSRLQI:
21114 icode = CODE_FOR_mmx_lshrv1di3;
21117 case IX86_BUILTIN_PSLLW128:
21118 case IX86_BUILTIN_PSLLWI128:
21119 icode = CODE_FOR_ashlv8hi3;
21121 case IX86_BUILTIN_PSLLD128:
21122 case IX86_BUILTIN_PSLLDI128:
21123 icode = CODE_FOR_ashlv4si3;
21125 case IX86_BUILTIN_PSLLQ128:
21126 case IX86_BUILTIN_PSLLQI128:
21127 icode = CODE_FOR_ashlv2di3;
21129 case IX86_BUILTIN_PSRAW128:
21130 case IX86_BUILTIN_PSRAWI128:
21131 icode = CODE_FOR_ashrv8hi3;
21133 case IX86_BUILTIN_PSRAD128:
21134 case IX86_BUILTIN_PSRADI128:
21135 icode = CODE_FOR_ashrv4si3;
21137 case IX86_BUILTIN_PSRLW128:
21138 case IX86_BUILTIN_PSRLWI128:
21139 icode = CODE_FOR_lshrv8hi3;
21141 case IX86_BUILTIN_PSRLD128:
21142 case IX86_BUILTIN_PSRLDI128:
21143 icode = CODE_FOR_lshrv4si3;
21145 case IX86_BUILTIN_PSRLQ128:
21146 case IX86_BUILTIN_PSRLQI128:
21147 icode = CODE_FOR_lshrv2di3;
21150 arg0 = CALL_EXPR_ARG (exp, 0);
21151 arg1 = CALL_EXPR_ARG (exp, 1);
21152 op0 = expand_normal (arg0);
21153 op1 = expand_normal (arg1);
21155 tmode = insn_data[icode].operand[0].mode;
21156 mode1 = insn_data[icode].operand[1].mode;
21158 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21159 op0 = copy_to_reg (op0);
21161 if (!CONST_INT_P (op1))
21162 op1 = simplify_gen_subreg (SImode, op1, GET_MODE (op1), 0);
21164 if (! (*insn_data[icode].operand[2].predicate) (op1, SImode))
21165 op1 = copy_to_reg (op1);
21167 target = gen_reg_rtx (tmode);
21168 pat = GEN_FCN (icode) (target, op0, op1);
21174 case IX86_BUILTIN_PSLLDQI128:
21175 return ix86_expand_binop_imm_builtin (CODE_FOR_sse2_ashlti3,
21179 case IX86_BUILTIN_PSRLDQI128:
21180 return ix86_expand_binop_imm_builtin (CODE_FOR_sse2_lshrti3,
21184 case IX86_BUILTIN_FEMMS:
21185 emit_insn (gen_mmx_femms ());
21188 case IX86_BUILTIN_PAVGUSB:
21189 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, exp, target);
21191 case IX86_BUILTIN_PFACC:
21192 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, exp, target);
21194 case IX86_BUILTIN_PFADD:
21195 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, exp, target);
21197 case IX86_BUILTIN_PFCMPEQ:
21198 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, exp, target);
21200 case IX86_BUILTIN_PFCMPGE:
21201 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, exp, target);
21203 case IX86_BUILTIN_PFCMPGT:
21204 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, exp, target);
21206 case IX86_BUILTIN_PFMAX:
21207 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, exp, target);
21209 case IX86_BUILTIN_PFMIN:
21210 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, exp, target);
21212 case IX86_BUILTIN_PFMUL:
21213 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, exp, target);
21215 case IX86_BUILTIN_PFRCPIT1:
21216 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, exp, target);
21218 case IX86_BUILTIN_PFRCPIT2:
21219 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, exp, target);
21221 case IX86_BUILTIN_PFRSQIT1:
21222 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, exp, target);
21224 case IX86_BUILTIN_PFSUB:
21225 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, exp, target);
21227 case IX86_BUILTIN_PFSUBR:
21228 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, exp, target);
21230 case IX86_BUILTIN_PMULHRW:
21231 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, exp, target);
21233 case IX86_BUILTIN_PFNACC:
21234 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, exp, target);
21236 case IX86_BUILTIN_PFPNACC:
21237 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, exp, target);
21239 case IX86_BUILTIN_SQRTSD:
21240 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, exp, target);
21241 case IX86_BUILTIN_LOADUPD:
21242 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, exp, target, 1);
21243 case IX86_BUILTIN_STOREUPD:
21244 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, exp);
21246 case IX86_BUILTIN_MFENCE:
21247 emit_insn (gen_sse2_mfence ());
21249 case IX86_BUILTIN_LFENCE:
21250 emit_insn (gen_sse2_lfence ());
21253 case IX86_BUILTIN_CLFLUSH:
21254 arg0 = CALL_EXPR_ARG (exp, 0);
21255 op0 = expand_normal (arg0);
21256 icode = CODE_FOR_sse2_clflush;
21257 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
21258 op0 = copy_to_mode_reg (Pmode, op0);
21260 emit_insn (gen_sse2_clflush (op0));
21263 case IX86_BUILTIN_MOVNTPD:
21264 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, exp);
21265 case IX86_BUILTIN_MOVNTDQ:
21266 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, exp);
21267 case IX86_BUILTIN_MOVNTI:
21268 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, exp);
21270 case IX86_BUILTIN_LOADDQU:
21271 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, exp, target, 1);
21272 case IX86_BUILTIN_STOREDQU:
21273 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, exp);
21275 case IX86_BUILTIN_MONITOR:
21276 arg0 = CALL_EXPR_ARG (exp, 0);
21277 arg1 = CALL_EXPR_ARG (exp, 1);
21278 arg2 = CALL_EXPR_ARG (exp, 2);
21279 op0 = expand_normal (arg0);
21280 op1 = expand_normal (arg1);
21281 op2 = expand_normal (arg2);
21283 op0 = copy_to_mode_reg (Pmode, op0);
21285 op1 = copy_to_mode_reg (SImode, op1);
21287 op2 = copy_to_mode_reg (SImode, op2);
21289 emit_insn (gen_sse3_monitor (op0, op1, op2));
21291 emit_insn (gen_sse3_monitor64 (op0, op1, op2));
21294 case IX86_BUILTIN_MWAIT:
21295 arg0 = CALL_EXPR_ARG (exp, 0);
21296 arg1 = CALL_EXPR_ARG (exp, 1);
21297 op0 = expand_normal (arg0);
21298 op1 = expand_normal (arg1);
21300 op0 = copy_to_mode_reg (SImode, op0);
21302 op1 = copy_to_mode_reg (SImode, op1);
21303 emit_insn (gen_sse3_mwait (op0, op1));
21306 case IX86_BUILTIN_LDDQU:
21307 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, exp,
21310 case IX86_BUILTIN_PALIGNR:
21311 case IX86_BUILTIN_PALIGNR128:
21312 if (fcode == IX86_BUILTIN_PALIGNR)
21314 icode = CODE_FOR_ssse3_palignrdi;
21319 icode = CODE_FOR_ssse3_palignrti;
21322 arg0 = CALL_EXPR_ARG (exp, 0);
21323 arg1 = CALL_EXPR_ARG (exp, 1);
21324 arg2 = CALL_EXPR_ARG (exp, 2);
21325 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21326 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21327 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
21328 tmode = insn_data[icode].operand[0].mode;
21329 mode1 = insn_data[icode].operand[1].mode;
21330 mode2 = insn_data[icode].operand[2].mode;
21331 mode3 = insn_data[icode].operand[3].mode;
21333 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21335 op0 = copy_to_reg (op0);
21336 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
21338 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21340 op1 = copy_to_reg (op1);
21341 op1 = simplify_gen_subreg (mode2, op1, GET_MODE (op1), 0);
21343 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21345 error ("shift must be an immediate");
21348 target = gen_reg_rtx (mode);
21349 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
21356 case IX86_BUILTIN_MOVNTDQA:
21357 return ix86_expand_unop_builtin (CODE_FOR_sse4_1_movntdqa, exp,
21360 case IX86_BUILTIN_MOVNTSD:
21361 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv2df, exp);
21363 case IX86_BUILTIN_MOVNTSS:
21364 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv4sf, exp);
21366 case IX86_BUILTIN_INSERTQ:
21367 case IX86_BUILTIN_EXTRQ:
21368 icode = (fcode == IX86_BUILTIN_EXTRQ
21369 ? CODE_FOR_sse4a_extrq
21370 : CODE_FOR_sse4a_insertq);
21371 arg0 = CALL_EXPR_ARG (exp, 0);
21372 arg1 = CALL_EXPR_ARG (exp, 1);
21373 op0 = expand_normal (arg0);
21374 op1 = expand_normal (arg1);
21375 tmode = insn_data[icode].operand[0].mode;
21376 mode1 = insn_data[icode].operand[1].mode;
21377 mode2 = insn_data[icode].operand[2].mode;
21378 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21379 op0 = copy_to_mode_reg (mode1, op0);
21380 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21381 op1 = copy_to_mode_reg (mode2, op1);
21382 if (optimize || target == 0
21383 || GET_MODE (target) != tmode
21384 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21385 target = gen_reg_rtx (tmode);
21386 pat = GEN_FCN (icode) (target, op0, op1);
21392 case IX86_BUILTIN_EXTRQI:
21393 icode = CODE_FOR_sse4a_extrqi;
21394 arg0 = CALL_EXPR_ARG (exp, 0);
21395 arg1 = CALL_EXPR_ARG (exp, 1);
21396 arg2 = CALL_EXPR_ARG (exp, 2);
21397 op0 = expand_normal (arg0);
21398 op1 = expand_normal (arg1);
21399 op2 = expand_normal (arg2);
21400 tmode = insn_data[icode].operand[0].mode;
21401 mode1 = insn_data[icode].operand[1].mode;
21402 mode2 = insn_data[icode].operand[2].mode;
21403 mode3 = insn_data[icode].operand[3].mode;
21404 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21405 op0 = copy_to_mode_reg (mode1, op0);
21406 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21408 error ("index mask must be an immediate");
21409 return gen_reg_rtx (tmode);
21411 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21413 error ("length mask must be an immediate");
21414 return gen_reg_rtx (tmode);
21416 if (optimize || target == 0
21417 || GET_MODE (target) != tmode
21418 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21419 target = gen_reg_rtx (tmode);
21420 pat = GEN_FCN (icode) (target, op0, op1, op2);
21426 case IX86_BUILTIN_INSERTQI:
21427 icode = CODE_FOR_sse4a_insertqi;
21428 arg0 = CALL_EXPR_ARG (exp, 0);
21429 arg1 = CALL_EXPR_ARG (exp, 1);
21430 arg2 = CALL_EXPR_ARG (exp, 2);
21431 arg3 = CALL_EXPR_ARG (exp, 3);
21432 op0 = expand_normal (arg0);
21433 op1 = expand_normal (arg1);
21434 op2 = expand_normal (arg2);
21435 op3 = expand_normal (arg3);
21436 tmode = insn_data[icode].operand[0].mode;
21437 mode1 = insn_data[icode].operand[1].mode;
21438 mode2 = insn_data[icode].operand[2].mode;
21439 mode3 = insn_data[icode].operand[3].mode;
21440 mode4 = insn_data[icode].operand[4].mode;
21442 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
21443 op0 = copy_to_mode_reg (mode1, op0);
21445 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
21446 op1 = copy_to_mode_reg (mode2, op1);
21448 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
21450 error ("index mask must be an immediate");
21451 return gen_reg_rtx (tmode);
21453 if (! (*insn_data[icode].operand[4].predicate) (op3, mode4))
21455 error ("length mask must be an immediate");
21456 return gen_reg_rtx (tmode);
21458 if (optimize || target == 0
21459 || GET_MODE (target) != tmode
21460 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21461 target = gen_reg_rtx (tmode);
21462 pat = GEN_FCN (icode) (target, op0, op1, op2, op3);
21468 case IX86_BUILTIN_VEC_INIT_V2SI:
21469 case IX86_BUILTIN_VEC_INIT_V4HI:
21470 case IX86_BUILTIN_VEC_INIT_V8QI:
21471 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
21473 case IX86_BUILTIN_VEC_EXT_V2DF:
21474 case IX86_BUILTIN_VEC_EXT_V2DI:
21475 case IX86_BUILTIN_VEC_EXT_V4SF:
21476 case IX86_BUILTIN_VEC_EXT_V4SI:
21477 case IX86_BUILTIN_VEC_EXT_V8HI:
21478 case IX86_BUILTIN_VEC_EXT_V2SI:
21479 case IX86_BUILTIN_VEC_EXT_V4HI:
21480 case IX86_BUILTIN_VEC_EXT_V16QI:
21481 return ix86_expand_vec_ext_builtin (exp, target);
21483 case IX86_BUILTIN_VEC_SET_V2DI:
21484 case IX86_BUILTIN_VEC_SET_V4SF:
21485 case IX86_BUILTIN_VEC_SET_V4SI:
21486 case IX86_BUILTIN_VEC_SET_V8HI:
21487 case IX86_BUILTIN_VEC_SET_V4HI:
21488 case IX86_BUILTIN_VEC_SET_V16QI:
21489 return ix86_expand_vec_set_builtin (exp);
21491 case IX86_BUILTIN_INFQ:
21493 REAL_VALUE_TYPE inf;
21497 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
21499 tmp = validize_mem (force_const_mem (mode, tmp));
21502 target = gen_reg_rtx (mode);
21504 emit_move_insn (target, tmp);
21508 case IX86_BUILTIN_COPYSIGNQ:
21509 return ix86_expand_binop_builtin (CODE_FOR_copysigntf3, exp, target);
21515 for (i = 0, d = bdesc_args;
21516 i < ARRAY_SIZE (bdesc_args);
21518 if (d->code == fcode)
21520 enum ix86_builtin_type type = (enum ix86_builtin_type) d->flag;
21521 return ix86_expand_args_builtin (d->icode, exp, type, target);
21524 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
21525 if (d->code == fcode)
21527 /* Compares are treated specially. */
21528 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
21529 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
21530 || d->icode == CODE_FOR_sse2_maskcmpv2df3
21531 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
21532 return ix86_expand_sse_compare (d, exp, target);
21534 return ix86_expand_binop_builtin (d->icode, exp, target);
21537 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
21538 if (d->code == fcode)
21539 return ix86_expand_sse_comi (d, exp, target);
21541 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
21542 if (d->code == fcode)
21543 return ix86_expand_sse_ptest (d, exp, target);
21545 for (i = 0, d = bdesc_crc32; i < ARRAY_SIZE (bdesc_crc32); i++, d++)
21546 if (d->code == fcode)
21547 return ix86_expand_crc32 (d->icode, exp, target);
21549 for (i = 0, d = bdesc_pcmpestr;
21550 i < ARRAY_SIZE (bdesc_pcmpestr);
21552 if (d->code == fcode)
21553 return ix86_expand_sse_pcmpestr (d, exp, target);
21555 for (i = 0, d = bdesc_pcmpistr;
21556 i < ARRAY_SIZE (bdesc_pcmpistr);
21558 if (d->code == fcode)
21559 return ix86_expand_sse_pcmpistr (d, exp, target);
21561 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
21562 if (d->code == fcode)
21563 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
21564 (enum multi_arg_type)d->flag,
21567 gcc_unreachable ();
21570 /* Returns a function decl for a vectorized version of the builtin function
21571 with builtin function code FN and the result vector type TYPE, or NULL_TREE
21572 if it is not available. */
21575 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
21578 enum machine_mode in_mode, out_mode;
21581 if (TREE_CODE (type_out) != VECTOR_TYPE
21582 || TREE_CODE (type_in) != VECTOR_TYPE)
21585 out_mode = TYPE_MODE (TREE_TYPE (type_out));
21586 out_n = TYPE_VECTOR_SUBPARTS (type_out);
21587 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21588 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21592 case BUILT_IN_SQRT:
21593 if (out_mode == DFmode && out_n == 2
21594 && in_mode == DFmode && in_n == 2)
21595 return ix86_builtins[IX86_BUILTIN_SQRTPD];
21598 case BUILT_IN_SQRTF:
21599 if (out_mode == SFmode && out_n == 4
21600 && in_mode == SFmode && in_n == 4)
21601 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
21604 case BUILT_IN_LRINT:
21605 if (out_mode == SImode && out_n == 4
21606 && in_mode == DFmode && in_n == 2)
21607 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
21610 case BUILT_IN_LRINTF:
21611 if (out_mode == SImode && out_n == 4
21612 && in_mode == SFmode && in_n == 4)
21613 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
21620 /* Dispatch to a handler for a vectorization library. */
21621 if (ix86_veclib_handler)
21622 return (*ix86_veclib_handler)(fn, type_out, type_in);
21627 /* Handler for an SVML-style interface to
21628 a library with vectorized intrinsics. */
21631 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
21634 tree fntype, new_fndecl, args;
21637 enum machine_mode el_mode, in_mode;
21640 /* The SVML is suitable for unsafe math only. */
21641 if (!flag_unsafe_math_optimizations)
21644 el_mode = TYPE_MODE (TREE_TYPE (type_out));
21645 n = TYPE_VECTOR_SUBPARTS (type_out);
21646 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21647 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21648 if (el_mode != in_mode
21656 case BUILT_IN_LOG10:
21658 case BUILT_IN_TANH:
21660 case BUILT_IN_ATAN:
21661 case BUILT_IN_ATAN2:
21662 case BUILT_IN_ATANH:
21663 case BUILT_IN_CBRT:
21664 case BUILT_IN_SINH:
21666 case BUILT_IN_ASINH:
21667 case BUILT_IN_ASIN:
21668 case BUILT_IN_COSH:
21670 case BUILT_IN_ACOSH:
21671 case BUILT_IN_ACOS:
21672 if (el_mode != DFmode || n != 2)
21676 case BUILT_IN_EXPF:
21677 case BUILT_IN_LOGF:
21678 case BUILT_IN_LOG10F:
21679 case BUILT_IN_POWF:
21680 case BUILT_IN_TANHF:
21681 case BUILT_IN_TANF:
21682 case BUILT_IN_ATANF:
21683 case BUILT_IN_ATAN2F:
21684 case BUILT_IN_ATANHF:
21685 case BUILT_IN_CBRTF:
21686 case BUILT_IN_SINHF:
21687 case BUILT_IN_SINF:
21688 case BUILT_IN_ASINHF:
21689 case BUILT_IN_ASINF:
21690 case BUILT_IN_COSHF:
21691 case BUILT_IN_COSF:
21692 case BUILT_IN_ACOSHF:
21693 case BUILT_IN_ACOSF:
21694 if (el_mode != SFmode || n != 4)
21702 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
21704 if (fn == BUILT_IN_LOGF)
21705 strcpy (name, "vmlsLn4");
21706 else if (fn == BUILT_IN_LOG)
21707 strcpy (name, "vmldLn2");
21710 sprintf (name, "vmls%s", bname+10);
21711 name[strlen (name)-1] = '4';
21714 sprintf (name, "vmld%s2", bname+10);
21716 /* Convert to uppercase. */
21720 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
21721 args = TREE_CHAIN (args))
21725 fntype = build_function_type_list (type_out, type_in, NULL);
21727 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
21729 /* Build a function declaration for the vectorized function. */
21730 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
21731 TREE_PUBLIC (new_fndecl) = 1;
21732 DECL_EXTERNAL (new_fndecl) = 1;
21733 DECL_IS_NOVOPS (new_fndecl) = 1;
21734 TREE_READONLY (new_fndecl) = 1;
21739 /* Handler for an ACML-style interface to
21740 a library with vectorized intrinsics. */
21743 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
21745 char name[20] = "__vr.._";
21746 tree fntype, new_fndecl, args;
21749 enum machine_mode el_mode, in_mode;
21752 /* The ACML is 64bits only and suitable for unsafe math only as
21753 it does not correctly support parts of IEEE with the required
21754 precision such as denormals. */
21756 || !flag_unsafe_math_optimizations)
21759 el_mode = TYPE_MODE (TREE_TYPE (type_out));
21760 n = TYPE_VECTOR_SUBPARTS (type_out);
21761 in_mode = TYPE_MODE (TREE_TYPE (type_in));
21762 in_n = TYPE_VECTOR_SUBPARTS (type_in);
21763 if (el_mode != in_mode
21773 case BUILT_IN_LOG2:
21774 case BUILT_IN_LOG10:
21777 if (el_mode != DFmode
21782 case BUILT_IN_SINF:
21783 case BUILT_IN_COSF:
21784 case BUILT_IN_EXPF:
21785 case BUILT_IN_POWF:
21786 case BUILT_IN_LOGF:
21787 case BUILT_IN_LOG2F:
21788 case BUILT_IN_LOG10F:
21791 if (el_mode != SFmode
21800 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
21801 sprintf (name + 7, "%s", bname+10);
21804 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
21805 args = TREE_CHAIN (args))
21809 fntype = build_function_type_list (type_out, type_in, NULL);
21811 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
21813 /* Build a function declaration for the vectorized function. */
21814 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
21815 TREE_PUBLIC (new_fndecl) = 1;
21816 DECL_EXTERNAL (new_fndecl) = 1;
21817 DECL_IS_NOVOPS (new_fndecl) = 1;
21818 TREE_READONLY (new_fndecl) = 1;
21824 /* Returns a decl of a function that implements conversion of the
21825 input vector of type TYPE, or NULL_TREE if it is not available. */
21828 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
21830 if (TREE_CODE (type) != VECTOR_TYPE)
21836 switch (TYPE_MODE (type))
21839 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
21844 case FIX_TRUNC_EXPR:
21845 switch (TYPE_MODE (type))
21848 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
21858 /* Returns a code for a target-specific builtin that implements
21859 reciprocal of the function, or NULL_TREE if not available. */
21862 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
21863 bool sqrt ATTRIBUTE_UNUSED)
21865 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
21866 && flag_finite_math_only && !flag_trapping_math
21867 && flag_unsafe_math_optimizations))
21871 /* Machine dependent builtins. */
21874 /* Vectorized version of sqrt to rsqrt conversion. */
21875 case IX86_BUILTIN_SQRTPS_NR:
21876 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
21882 /* Normal builtins. */
21885 /* Sqrt to rsqrt conversion. */
21886 case BUILT_IN_SQRTF:
21887 return ix86_builtins[IX86_BUILTIN_RSQRTF];
21894 /* Store OPERAND to the memory after reload is completed. This means
21895 that we can't easily use assign_stack_local. */
21897 ix86_force_to_memory (enum machine_mode mode, rtx operand)
21901 gcc_assert (reload_completed);
21902 if (TARGET_RED_ZONE)
21904 result = gen_rtx_MEM (mode,
21905 gen_rtx_PLUS (Pmode,
21907 GEN_INT (-RED_ZONE_SIZE)));
21908 emit_move_insn (result, operand);
21910 else if (!TARGET_RED_ZONE && TARGET_64BIT)
21916 operand = gen_lowpart (DImode, operand);
21920 gen_rtx_SET (VOIDmode,
21921 gen_rtx_MEM (DImode,
21922 gen_rtx_PRE_DEC (DImode,
21923 stack_pointer_rtx)),
21927 gcc_unreachable ();
21929 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21938 split_di (&operand, 1, operands, operands + 1);
21940 gen_rtx_SET (VOIDmode,
21941 gen_rtx_MEM (SImode,
21942 gen_rtx_PRE_DEC (Pmode,
21943 stack_pointer_rtx)),
21946 gen_rtx_SET (VOIDmode,
21947 gen_rtx_MEM (SImode,
21948 gen_rtx_PRE_DEC (Pmode,
21949 stack_pointer_rtx)),
21954 /* Store HImodes as SImodes. */
21955 operand = gen_lowpart (SImode, operand);
21959 gen_rtx_SET (VOIDmode,
21960 gen_rtx_MEM (GET_MODE (operand),
21961 gen_rtx_PRE_DEC (SImode,
21962 stack_pointer_rtx)),
21966 gcc_unreachable ();
21968 result = gen_rtx_MEM (mode, stack_pointer_rtx);
21973 /* Free operand from the memory. */
21975 ix86_free_from_memory (enum machine_mode mode)
21977 if (!TARGET_RED_ZONE)
21981 if (mode == DImode || TARGET_64BIT)
21985 /* Use LEA to deallocate stack space. In peephole2 it will be converted
21986 to pop or add instruction if registers are available. */
21987 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
21988 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
21993 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
21994 QImode must go into class Q_REGS.
21995 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
21996 movdf to do mem-to-mem moves through integer regs. */
21998 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
22000 enum machine_mode mode = GET_MODE (x);
22002 /* We're only allowed to return a subclass of CLASS. Many of the
22003 following checks fail for NO_REGS, so eliminate that early. */
22004 if (regclass == NO_REGS)
22007 /* All classes can load zeros. */
22008 if (x == CONST0_RTX (mode))
22011 /* Force constants into memory if we are loading a (nonzero) constant into
22012 an MMX or SSE register. This is because there are no MMX/SSE instructions
22013 to load from a constant. */
22015 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
22018 /* Prefer SSE regs only, if we can use them for math. */
22019 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
22020 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
22022 /* Floating-point constants need more complex checks. */
22023 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
22025 /* General regs can load everything. */
22026 if (reg_class_subset_p (regclass, GENERAL_REGS))
22029 /* Floats can load 0 and 1 plus some others. Note that we eliminated
22030 zero above. We only want to wind up preferring 80387 registers if
22031 we plan on doing computation with them. */
22033 && standard_80387_constant_p (x))
22035 /* Limit class to non-sse. */
22036 if (regclass == FLOAT_SSE_REGS)
22038 if (regclass == FP_TOP_SSE_REGS)
22040 if (regclass == FP_SECOND_SSE_REGS)
22041 return FP_SECOND_REG;
22042 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
22049 /* Generally when we see PLUS here, it's the function invariant
22050 (plus soft-fp const_int). Which can only be computed into general
22052 if (GET_CODE (x) == PLUS)
22053 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
22055 /* QImode constants are easy to load, but non-constant QImode data
22056 must go into Q_REGS. */
22057 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
22059 if (reg_class_subset_p (regclass, Q_REGS))
22061 if (reg_class_subset_p (Q_REGS, regclass))
22069 /* Discourage putting floating-point values in SSE registers unless
22070 SSE math is being used, and likewise for the 387 registers. */
22072 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
22074 enum machine_mode mode = GET_MODE (x);
22076 /* Restrict the output reload class to the register bank that we are doing
22077 math on. If we would like not to return a subset of CLASS, reject this
22078 alternative: if reload cannot do this, it will still use its choice. */
22079 mode = GET_MODE (x);
22080 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
22081 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
22083 if (X87_FLOAT_MODE_P (mode))
22085 if (regclass == FP_TOP_SSE_REGS)
22087 else if (regclass == FP_SECOND_SSE_REGS)
22088 return FP_SECOND_REG;
22090 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
22096 /* If we are copying between general and FP registers, we need a memory
22097 location. The same is true for SSE and MMX registers.
22099 To optimize register_move_cost performance, allow inline variant.
22101 The macro can't work reliably when one of the CLASSES is class containing
22102 registers from multiple units (SSE, MMX, integer). We avoid this by never
22103 combining those units in single alternative in the machine description.
22104 Ensure that this constraint holds to avoid unexpected surprises.
22106 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
22107 enforce these sanity checks. */
22110 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
22111 enum machine_mode mode, int strict)
22113 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
22114 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
22115 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
22116 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
22117 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
22118 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
22120 gcc_assert (!strict);
22124 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
22127 /* ??? This is a lie. We do have moves between mmx/general, and for
22128 mmx/sse2. But by saying we need secondary memory we discourage the
22129 register allocator from using the mmx registers unless needed. */
22130 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
22133 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
22135 /* SSE1 doesn't have any direct moves from other classes. */
22139 /* If the target says that inter-unit moves are more expensive
22140 than moving through memory, then don't generate them. */
22141 if (!TARGET_INTER_UNIT_MOVES)
22144 /* Between SSE and general, we have moves no larger than word size. */
22145 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
22153 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
22154 enum machine_mode mode, int strict)
22156 return inline_secondary_memory_needed (class1, class2, mode, strict);
22159 /* Return true if the registers in CLASS cannot represent the change from
22160 modes FROM to TO. */
22163 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
22164 enum reg_class regclass)
22169 /* x87 registers can't do subreg at all, as all values are reformatted
22170 to extended precision. */
22171 if (MAYBE_FLOAT_CLASS_P (regclass))
22174 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
22176 /* Vector registers do not support QI or HImode loads. If we don't
22177 disallow a change to these modes, reload will assume it's ok to
22178 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
22179 the vec_dupv4hi pattern. */
22180 if (GET_MODE_SIZE (from) < 4)
22183 /* Vector registers do not support subreg with nonzero offsets, which
22184 are otherwise valid for integer registers. Since we can't see
22185 whether we have a nonzero offset from here, prohibit all
22186 nonparadoxical subregs changing size. */
22187 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
22194 /* Return the cost of moving data of mode M between a
22195 register and memory. A value of 2 is the default; this cost is
22196 relative to those in `REGISTER_MOVE_COST'.
22198 This function is used extensively by register_move_cost that is used to
22199 build tables at startup. Make it inline in this case.
22200 When IN is 2, return maximum of in and out move cost.
22202 If moving between registers and memory is more expensive than
22203 between two registers, you should define this macro to express the
22206 Model also increased moving costs of QImode registers in non
22210 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
22214 if (FLOAT_CLASS_P (regclass))
22232 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
22233 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
22235 if (SSE_CLASS_P (regclass))
22238 switch (GET_MODE_SIZE (mode))
22253 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
22254 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
22256 if (MMX_CLASS_P (regclass))
22259 switch (GET_MODE_SIZE (mode))
22271 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
22272 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
22274 switch (GET_MODE_SIZE (mode))
22277 if (Q_CLASS_P (regclass) || TARGET_64BIT)
22280 return ix86_cost->int_store[0];
22281 if (TARGET_PARTIAL_REG_DEPENDENCY && !optimize_size)
22282 cost = ix86_cost->movzbl_load;
22284 cost = ix86_cost->int_load[0];
22286 return MAX (cost, ix86_cost->int_store[0]);
22292 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
22294 return ix86_cost->movzbl_load;
22296 return ix86_cost->int_store[0] + 4;
22301 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
22302 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
22304 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
22305 if (mode == TFmode)
22308 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
22310 cost = ix86_cost->int_load[2];
22312 cost = ix86_cost->int_store[2];
22313 return (cost * (((int) GET_MODE_SIZE (mode)
22314 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
22319 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
22321 return inline_memory_move_cost (mode, regclass, in);
22325 /* Return the cost of moving data from a register in class CLASS1 to
22326 one in class CLASS2.
22328 It is not required that the cost always equal 2 when FROM is the same as TO;
22329 on some machines it is expensive to move between registers if they are not
22330 general registers. */
22333 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
22334 enum reg_class class2)
22336 /* In case we require secondary memory, compute cost of the store followed
22337 by load. In order to avoid bad register allocation choices, we need
22338 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
22340 if (inline_secondary_memory_needed (class1, class2, mode, 0))
22344 cost += inline_memory_move_cost (mode, class1, 2);
22345 cost += inline_memory_move_cost (mode, class2, 2);
22347 /* In case of copying from general_purpose_register we may emit multiple
22348 stores followed by single load causing memory size mismatch stall.
22349 Count this as arbitrarily high cost of 20. */
22350 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
22353 /* In the case of FP/MMX moves, the registers actually overlap, and we
22354 have to switch modes in order to treat them differently. */
22355 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
22356 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
22362 /* Moves between SSE/MMX and integer unit are expensive. */
22363 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
22364 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
22366 /* ??? By keeping returned value relatively high, we limit the number
22367 of moves between integer and MMX/SSE registers for all targets.
22368 Additionally, high value prevents problem with x86_modes_tieable_p(),
22369 where integer modes in MMX/SSE registers are not tieable
22370 because of missing QImode and HImode moves to, from or between
22371 MMX/SSE registers. */
22372 return MAX (8, ix86_cost->mmxsse_to_integer);
22374 if (MAYBE_FLOAT_CLASS_P (class1))
22375 return ix86_cost->fp_move;
22376 if (MAYBE_SSE_CLASS_P (class1))
22377 return ix86_cost->sse_move;
22378 if (MAYBE_MMX_CLASS_P (class1))
22379 return ix86_cost->mmx_move;
22383 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
22386 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
22388 /* Flags and only flags can only hold CCmode values. */
22389 if (CC_REGNO_P (regno))
22390 return GET_MODE_CLASS (mode) == MODE_CC;
22391 if (GET_MODE_CLASS (mode) == MODE_CC
22392 || GET_MODE_CLASS (mode) == MODE_RANDOM
22393 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
22395 if (FP_REGNO_P (regno))
22396 return VALID_FP_MODE_P (mode);
22397 if (SSE_REGNO_P (regno))
22399 /* We implement the move patterns for all vector modes into and
22400 out of SSE registers, even when no operation instructions
22402 return (VALID_SSE_REG_MODE (mode)
22403 || VALID_SSE2_REG_MODE (mode)
22404 || VALID_MMX_REG_MODE (mode)
22405 || VALID_MMX_REG_MODE_3DNOW (mode));
22407 if (MMX_REGNO_P (regno))
22409 /* We implement the move patterns for 3DNOW modes even in MMX mode,
22410 so if the register is available at all, then we can move data of
22411 the given mode into or out of it. */
22412 return (VALID_MMX_REG_MODE (mode)
22413 || VALID_MMX_REG_MODE_3DNOW (mode));
22416 if (mode == QImode)
22418 /* Take care for QImode values - they can be in non-QI regs,
22419 but then they do cause partial register stalls. */
22420 if (regno < 4 || TARGET_64BIT)
22422 if (!TARGET_PARTIAL_REG_STALL)
22424 return reload_in_progress || reload_completed;
22426 /* We handle both integer and floats in the general purpose registers. */
22427 else if (VALID_INT_MODE_P (mode))
22429 else if (VALID_FP_MODE_P (mode))
22431 else if (VALID_DFP_MODE_P (mode))
22433 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
22434 on to use that value in smaller contexts, this can easily force a
22435 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
22436 supporting DImode, allow it. */
22437 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
22443 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
22444 tieable integer mode. */
22447 ix86_tieable_integer_mode_p (enum machine_mode mode)
22456 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
22459 return TARGET_64BIT;
22466 /* Return true if MODE1 is accessible in a register that can hold MODE2
22467 without copying. That is, all register classes that can hold MODE2
22468 can also hold MODE1. */
22471 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
22473 if (mode1 == mode2)
22476 if (ix86_tieable_integer_mode_p (mode1)
22477 && ix86_tieable_integer_mode_p (mode2))
22480 /* MODE2 being XFmode implies fp stack or general regs, which means we
22481 can tie any smaller floating point modes to it. Note that we do not
22482 tie this with TFmode. */
22483 if (mode2 == XFmode)
22484 return mode1 == SFmode || mode1 == DFmode;
22486 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
22487 that we can tie it with SFmode. */
22488 if (mode2 == DFmode)
22489 return mode1 == SFmode;
22491 /* If MODE2 is only appropriate for an SSE register, then tie with
22492 any other mode acceptable to SSE registers. */
22493 if (GET_MODE_SIZE (mode2) == 16
22494 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
22495 return (GET_MODE_SIZE (mode1) == 16
22496 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
22498 /* If MODE2 is appropriate for an MMX register, then tie
22499 with any other mode acceptable to MMX registers. */
22500 if (GET_MODE_SIZE (mode2) == 8
22501 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
22502 return (GET_MODE_SIZE (mode1) == 8
22503 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
22508 /* Compute a (partial) cost for rtx X. Return true if the complete
22509 cost has been computed, and false if subexpressions should be
22510 scanned. In either case, *TOTAL contains the cost result. */
22513 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total)
22515 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
22516 enum machine_mode mode = GET_MODE (x);
22524 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
22526 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
22528 else if (flag_pic && SYMBOLIC_CONST (x)
22530 || (!GET_CODE (x) != LABEL_REF
22531 && (GET_CODE (x) != SYMBOL_REF
22532 || !SYMBOL_REF_LOCAL_P (x)))))
22539 if (mode == VOIDmode)
22542 switch (standard_80387_constant_p (x))
22547 default: /* Other constants */
22552 /* Start with (MEM (SYMBOL_REF)), since that's where
22553 it'll probably end up. Add a penalty for size. */
22554 *total = (COSTS_N_INSNS (1)
22555 + (flag_pic != 0 && !TARGET_64BIT)
22556 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
22562 /* The zero extensions is often completely free on x86_64, so make
22563 it as cheap as possible. */
22564 if (TARGET_64BIT && mode == DImode
22565 && GET_MODE (XEXP (x, 0)) == SImode)
22567 else if (TARGET_ZERO_EXTEND_WITH_AND)
22568 *total = ix86_cost->add;
22570 *total = ix86_cost->movzx;
22574 *total = ix86_cost->movsx;
22578 if (CONST_INT_P (XEXP (x, 1))
22579 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
22581 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22584 *total = ix86_cost->add;
22587 if ((value == 2 || value == 3)
22588 && ix86_cost->lea <= ix86_cost->shift_const)
22590 *total = ix86_cost->lea;
22600 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
22602 if (CONST_INT_P (XEXP (x, 1)))
22604 if (INTVAL (XEXP (x, 1)) > 32)
22605 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
22607 *total = ix86_cost->shift_const * 2;
22611 if (GET_CODE (XEXP (x, 1)) == AND)
22612 *total = ix86_cost->shift_var * 2;
22614 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
22619 if (CONST_INT_P (XEXP (x, 1)))
22620 *total = ix86_cost->shift_const;
22622 *total = ix86_cost->shift_var;
22627 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22629 /* ??? SSE scalar cost should be used here. */
22630 *total = ix86_cost->fmul;
22633 else if (X87_FLOAT_MODE_P (mode))
22635 *total = ix86_cost->fmul;
22638 else if (FLOAT_MODE_P (mode))
22640 /* ??? SSE vector cost should be used here. */
22641 *total = ix86_cost->fmul;
22646 rtx op0 = XEXP (x, 0);
22647 rtx op1 = XEXP (x, 1);
22649 if (CONST_INT_P (XEXP (x, 1)))
22651 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
22652 for (nbits = 0; value != 0; value &= value - 1)
22656 /* This is arbitrary. */
22659 /* Compute costs correctly for widening multiplication. */
22660 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
22661 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
22662 == GET_MODE_SIZE (mode))
22664 int is_mulwiden = 0;
22665 enum machine_mode inner_mode = GET_MODE (op0);
22667 if (GET_CODE (op0) == GET_CODE (op1))
22668 is_mulwiden = 1, op1 = XEXP (op1, 0);
22669 else if (CONST_INT_P (op1))
22671 if (GET_CODE (op0) == SIGN_EXTEND)
22672 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
22675 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
22679 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
22682 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
22683 + nbits * ix86_cost->mult_bit
22684 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
22693 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22694 /* ??? SSE cost should be used here. */
22695 *total = ix86_cost->fdiv;
22696 else if (X87_FLOAT_MODE_P (mode))
22697 *total = ix86_cost->fdiv;
22698 else if (FLOAT_MODE_P (mode))
22699 /* ??? SSE vector cost should be used here. */
22700 *total = ix86_cost->fdiv;
22702 *total = ix86_cost->divide[MODE_INDEX (mode)];
22706 if (GET_MODE_CLASS (mode) == MODE_INT
22707 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
22709 if (GET_CODE (XEXP (x, 0)) == PLUS
22710 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
22711 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
22712 && CONSTANT_P (XEXP (x, 1)))
22714 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
22715 if (val == 2 || val == 4 || val == 8)
22717 *total = ix86_cost->lea;
22718 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22719 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
22721 *total += rtx_cost (XEXP (x, 1), outer_code);
22725 else if (GET_CODE (XEXP (x, 0)) == MULT
22726 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
22728 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
22729 if (val == 2 || val == 4 || val == 8)
22731 *total = ix86_cost->lea;
22732 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22733 *total += rtx_cost (XEXP (x, 1), outer_code);
22737 else if (GET_CODE (XEXP (x, 0)) == PLUS)
22739 *total = ix86_cost->lea;
22740 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
22741 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
22742 *total += rtx_cost (XEXP (x, 1), outer_code);
22749 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22751 /* ??? SSE cost should be used here. */
22752 *total = ix86_cost->fadd;
22755 else if (X87_FLOAT_MODE_P (mode))
22757 *total = ix86_cost->fadd;
22760 else if (FLOAT_MODE_P (mode))
22762 /* ??? SSE vector cost should be used here. */
22763 *total = ix86_cost->fadd;
22771 if (!TARGET_64BIT && mode == DImode)
22773 *total = (ix86_cost->add * 2
22774 + (rtx_cost (XEXP (x, 0), outer_code)
22775 << (GET_MODE (XEXP (x, 0)) != DImode))
22776 + (rtx_cost (XEXP (x, 1), outer_code)
22777 << (GET_MODE (XEXP (x, 1)) != DImode)));
22783 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22785 /* ??? SSE cost should be used here. */
22786 *total = ix86_cost->fchs;
22789 else if (X87_FLOAT_MODE_P (mode))
22791 *total = ix86_cost->fchs;
22794 else if (FLOAT_MODE_P (mode))
22796 /* ??? SSE vector cost should be used here. */
22797 *total = ix86_cost->fchs;
22803 if (!TARGET_64BIT && mode == DImode)
22804 *total = ix86_cost->add * 2;
22806 *total = ix86_cost->add;
22810 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
22811 && XEXP (XEXP (x, 0), 1) == const1_rtx
22812 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
22813 && XEXP (x, 1) == const0_rtx)
22815 /* This kind of construct is implemented using test[bwl].
22816 Treat it as if we had an AND. */
22817 *total = (ix86_cost->add
22818 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
22819 + rtx_cost (const1_rtx, outer_code));
22825 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
22830 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22831 /* ??? SSE cost should be used here. */
22832 *total = ix86_cost->fabs;
22833 else if (X87_FLOAT_MODE_P (mode))
22834 *total = ix86_cost->fabs;
22835 else if (FLOAT_MODE_P (mode))
22836 /* ??? SSE vector cost should be used here. */
22837 *total = ix86_cost->fabs;
22841 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
22842 /* ??? SSE cost should be used here. */
22843 *total = ix86_cost->fsqrt;
22844 else if (X87_FLOAT_MODE_P (mode))
22845 *total = ix86_cost->fsqrt;
22846 else if (FLOAT_MODE_P (mode))
22847 /* ??? SSE vector cost should be used here. */
22848 *total = ix86_cost->fsqrt;
22852 if (XINT (x, 1) == UNSPEC_TP)
22863 static int current_machopic_label_num;
22865 /* Given a symbol name and its associated stub, write out the
22866 definition of the stub. */
22869 machopic_output_stub (FILE *file, const char *symb, const char *stub)
22871 unsigned int length;
22872 char *binder_name, *symbol_name, lazy_ptr_name[32];
22873 int label = ++current_machopic_label_num;
22875 /* For 64-bit we shouldn't get here. */
22876 gcc_assert (!TARGET_64BIT);
22878 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
22879 symb = (*targetm.strip_name_encoding) (symb);
22881 length = strlen (stub);
22882 binder_name = alloca (length + 32);
22883 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
22885 length = strlen (symb);
22886 symbol_name = alloca (length + 32);
22887 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
22889 sprintf (lazy_ptr_name, "L%d$lz", label);
22892 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
22894 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
22896 fprintf (file, "%s:\n", stub);
22897 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22901 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
22902 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
22903 fprintf (file, "\tjmp\t*%%edx\n");
22906 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
22908 fprintf (file, "%s:\n", binder_name);
22912 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
22913 fprintf (file, "\tpushl\t%%eax\n");
22916 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
22918 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
22920 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
22921 fprintf (file, "%s:\n", lazy_ptr_name);
22922 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
22923 fprintf (file, "\t.long %s\n", binder_name);
22927 darwin_x86_file_end (void)
22929 darwin_file_end ();
22932 #endif /* TARGET_MACHO */
22934 /* Order the registers for register allocator. */
22937 x86_order_regs_for_local_alloc (void)
22942 /* First allocate the local general purpose registers. */
22943 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22944 if (GENERAL_REGNO_P (i) && call_used_regs[i])
22945 reg_alloc_order [pos++] = i;
22947 /* Global general purpose registers. */
22948 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
22949 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
22950 reg_alloc_order [pos++] = i;
22952 /* x87 registers come first in case we are doing FP math
22954 if (!TARGET_SSE_MATH)
22955 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22956 reg_alloc_order [pos++] = i;
22958 /* SSE registers. */
22959 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
22960 reg_alloc_order [pos++] = i;
22961 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
22962 reg_alloc_order [pos++] = i;
22964 /* x87 registers. */
22965 if (TARGET_SSE_MATH)
22966 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
22967 reg_alloc_order [pos++] = i;
22969 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
22970 reg_alloc_order [pos++] = i;
22972 /* Initialize the rest of array as we do not allocate some registers
22974 while (pos < FIRST_PSEUDO_REGISTER)
22975 reg_alloc_order [pos++] = 0;
22978 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
22979 struct attribute_spec.handler. */
22981 ix86_handle_struct_attribute (tree *node, tree name,
22982 tree args ATTRIBUTE_UNUSED,
22983 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
22986 if (DECL_P (*node))
22988 if (TREE_CODE (*node) == TYPE_DECL)
22989 type = &TREE_TYPE (*node);
22994 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
22995 || TREE_CODE (*type) == UNION_TYPE)))
22997 warning (OPT_Wattributes, "%qs attribute ignored",
22998 IDENTIFIER_POINTER (name));
22999 *no_add_attrs = true;
23002 else if ((is_attribute_p ("ms_struct", name)
23003 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
23004 || ((is_attribute_p ("gcc_struct", name)
23005 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
23007 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
23008 IDENTIFIER_POINTER (name));
23009 *no_add_attrs = true;
23016 ix86_ms_bitfield_layout_p (const_tree record_type)
23018 return (TARGET_MS_BITFIELD_LAYOUT &&
23019 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
23020 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
23023 /* Returns an expression indicating where the this parameter is
23024 located on entry to the FUNCTION. */
23027 x86_this_parameter (tree function)
23029 tree type = TREE_TYPE (function);
23030 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
23035 const int *parm_regs;
23037 if (TARGET_64BIT_MS_ABI)
23038 parm_regs = x86_64_ms_abi_int_parameter_registers;
23040 parm_regs = x86_64_int_parameter_registers;
23041 return gen_rtx_REG (DImode, parm_regs[aggr]);
23044 nregs = ix86_function_regparm (type, function);
23046 if (nregs > 0 && !stdarg_p (type))
23050 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
23051 regno = aggr ? DX_REG : CX_REG;
23059 return gen_rtx_MEM (SImode,
23060 plus_constant (stack_pointer_rtx, 4));
23063 return gen_rtx_REG (SImode, regno);
23066 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
23069 /* Determine whether x86_output_mi_thunk can succeed. */
23072 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
23073 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
23074 HOST_WIDE_INT vcall_offset, const_tree function)
23076 /* 64-bit can handle anything. */
23080 /* For 32-bit, everything's fine if we have one free register. */
23081 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
23084 /* Need a free register for vcall_offset. */
23088 /* Need a free register for GOT references. */
23089 if (flag_pic && !(*targetm.binds_local_p) (function))
23092 /* Otherwise ok. */
23096 /* Output the assembler code for a thunk function. THUNK_DECL is the
23097 declaration for the thunk function itself, FUNCTION is the decl for
23098 the target function. DELTA is an immediate constant offset to be
23099 added to THIS. If VCALL_OFFSET is nonzero, the word at
23100 *(*this + vcall_offset) should be added to THIS. */
23103 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
23104 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
23105 HOST_WIDE_INT vcall_offset, tree function)
23108 rtx this_param = x86_this_parameter (function);
23111 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
23112 pull it in now and let DELTA benefit. */
23113 if (REG_P (this_param))
23114 this_reg = this_param;
23115 else if (vcall_offset)
23117 /* Put the this parameter into %eax. */
23118 xops[0] = this_param;
23119 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
23120 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
23123 this_reg = NULL_RTX;
23125 /* Adjust the this parameter by a fixed constant. */
23128 xops[0] = GEN_INT (delta);
23129 xops[1] = this_reg ? this_reg : this_param;
23132 if (!x86_64_general_operand (xops[0], DImode))
23134 tmp = gen_rtx_REG (DImode, R10_REG);
23136 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
23138 xops[1] = this_param;
23140 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
23143 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
23146 /* Adjust the this parameter by a value stored in the vtable. */
23150 tmp = gen_rtx_REG (DImode, R10_REG);
23153 int tmp_regno = CX_REG;
23154 if (lookup_attribute ("fastcall",
23155 TYPE_ATTRIBUTES (TREE_TYPE (function))))
23156 tmp_regno = AX_REG;
23157 tmp = gen_rtx_REG (SImode, tmp_regno);
23160 xops[0] = gen_rtx_MEM (Pmode, this_reg);
23163 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
23165 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
23167 /* Adjust the this parameter. */
23168 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
23169 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
23171 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
23172 xops[0] = GEN_INT (vcall_offset);
23174 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
23175 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
23177 xops[1] = this_reg;
23179 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
23181 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
23184 /* If necessary, drop THIS back to its stack slot. */
23185 if (this_reg && this_reg != this_param)
23187 xops[0] = this_reg;
23188 xops[1] = this_param;
23189 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
23192 xops[0] = XEXP (DECL_RTL (function), 0);
23195 if (!flag_pic || (*targetm.binds_local_p) (function))
23196 output_asm_insn ("jmp\t%P0", xops);
23197 /* All thunks should be in the same object as their target,
23198 and thus binds_local_p should be true. */
23199 else if (TARGET_64BIT_MS_ABI)
23200 gcc_unreachable ();
23203 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
23204 tmp = gen_rtx_CONST (Pmode, tmp);
23205 tmp = gen_rtx_MEM (QImode, tmp);
23207 output_asm_insn ("jmp\t%A0", xops);
23212 if (!flag_pic || (*targetm.binds_local_p) (function))
23213 output_asm_insn ("jmp\t%P0", xops);
23218 rtx sym_ref = XEXP (DECL_RTL (function), 0);
23219 tmp = (gen_rtx_SYMBOL_REF
23221 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
23222 tmp = gen_rtx_MEM (QImode, tmp);
23224 output_asm_insn ("jmp\t%0", xops);
23227 #endif /* TARGET_MACHO */
23229 tmp = gen_rtx_REG (SImode, CX_REG);
23230 output_set_got (tmp, NULL_RTX);
23233 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
23234 output_asm_insn ("jmp\t{*}%1", xops);
23240 x86_file_start (void)
23242 default_file_start ();
23244 darwin_file_start ();
23246 if (X86_FILE_START_VERSION_DIRECTIVE)
23247 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
23248 if (X86_FILE_START_FLTUSED)
23249 fputs ("\t.global\t__fltused\n", asm_out_file);
23250 if (ix86_asm_dialect == ASM_INTEL)
23251 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
23255 x86_field_alignment (tree field, int computed)
23257 enum machine_mode mode;
23258 tree type = TREE_TYPE (field);
23260 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
23262 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
23263 ? get_inner_array_type (type) : type);
23264 if (mode == DFmode || mode == DCmode
23265 || GET_MODE_CLASS (mode) == MODE_INT
23266 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
23267 return MIN (32, computed);
23271 /* Output assembler code to FILE to increment profiler label # LABELNO
23272 for profiling a function entry. */
23274 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
23278 #ifndef NO_PROFILE_COUNTERS
23279 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
23282 if (!TARGET_64BIT_MS_ABI && flag_pic)
23283 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
23285 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
23289 #ifndef NO_PROFILE_COUNTERS
23290 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
23291 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
23293 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
23297 #ifndef NO_PROFILE_COUNTERS
23298 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
23299 PROFILE_COUNT_REGISTER);
23301 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
23305 /* We don't have exact information about the insn sizes, but we may assume
23306 quite safely that we are informed about all 1 byte insns and memory
23307 address sizes. This is enough to eliminate unnecessary padding in
23311 min_insn_size (rtx insn)
23315 if (!INSN_P (insn) || !active_insn_p (insn))
23318 /* Discard alignments we've emit and jump instructions. */
23319 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
23320 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
23323 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
23324 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
23327 /* Important case - calls are always 5 bytes.
23328 It is common to have many calls in the row. */
23330 && symbolic_reference_mentioned_p (PATTERN (insn))
23331 && !SIBLING_CALL_P (insn))
23333 if (get_attr_length (insn) <= 1)
23336 /* For normal instructions we may rely on the sizes of addresses
23337 and the presence of symbol to require 4 bytes of encoding.
23338 This is not the case for jumps where references are PC relative. */
23339 if (!JUMP_P (insn))
23341 l = get_attr_length_address (insn);
23342 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
23351 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
23355 ix86_avoid_jump_misspredicts (void)
23357 rtx insn, start = get_insns ();
23358 int nbytes = 0, njumps = 0;
23361 /* Look for all minimal intervals of instructions containing 4 jumps.
23362 The intervals are bounded by START and INSN. NBYTES is the total
23363 size of instructions in the interval including INSN and not including
23364 START. When the NBYTES is smaller than 16 bytes, it is possible
23365 that the end of START and INSN ends up in the same 16byte page.
23367 The smallest offset in the page INSN can start is the case where START
23368 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
23369 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
23371 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
23374 nbytes += min_insn_size (insn);
23376 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
23377 INSN_UID (insn), min_insn_size (insn));
23379 && GET_CODE (PATTERN (insn)) != ADDR_VEC
23380 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
23388 start = NEXT_INSN (start);
23389 if ((JUMP_P (start)
23390 && GET_CODE (PATTERN (start)) != ADDR_VEC
23391 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
23393 njumps--, isjump = 1;
23396 nbytes -= min_insn_size (start);
23398 gcc_assert (njumps >= 0);
23400 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
23401 INSN_UID (start), INSN_UID (insn), nbytes);
23403 if (njumps == 3 && isjump && nbytes < 16)
23405 int padsize = 15 - nbytes + min_insn_size (insn);
23408 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
23409 INSN_UID (insn), padsize);
23410 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
23415 /* AMD Athlon works faster
23416 when RET is not destination of conditional jump or directly preceded
23417 by other jump instruction. We avoid the penalty by inserting NOP just
23418 before the RET instructions in such cases. */
23420 ix86_pad_returns (void)
23425 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
23427 basic_block bb = e->src;
23428 rtx ret = BB_END (bb);
23430 bool replace = false;
23432 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
23433 || !maybe_hot_bb_p (bb))
23435 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
23436 if (active_insn_p (prev) || LABEL_P (prev))
23438 if (prev && LABEL_P (prev))
23443 FOR_EACH_EDGE (e, ei, bb->preds)
23444 if (EDGE_FREQUENCY (e) && e->src->index >= 0
23445 && !(e->flags & EDGE_FALLTHRU))
23450 prev = prev_active_insn (ret);
23452 && ((JUMP_P (prev) && any_condjump_p (prev))
23455 /* Empty functions get branch mispredict even when the jump destination
23456 is not visible to us. */
23457 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
23462 emit_insn_before (gen_return_internal_long (), ret);
23468 /* Implement machine specific optimizations. We implement padding of returns
23469 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
23473 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
23474 ix86_pad_returns ();
23475 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
23476 ix86_avoid_jump_misspredicts ();
23479 /* Return nonzero when QImode register that must be represented via REX prefix
23482 x86_extended_QIreg_mentioned_p (rtx insn)
23485 extract_insn_cached (insn);
23486 for (i = 0; i < recog_data.n_operands; i++)
23487 if (REG_P (recog_data.operand[i])
23488 && REGNO (recog_data.operand[i]) >= 4)
23493 /* Return nonzero when P points to register encoded via REX prefix.
23494 Called via for_each_rtx. */
23496 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
23498 unsigned int regno;
23501 regno = REGNO (*p);
23502 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
23505 /* Return true when INSN mentions register that must be encoded using REX
23508 x86_extended_reg_mentioned_p (rtx insn)
23510 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
23513 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
23514 optabs would emit if we didn't have TFmode patterns. */
23517 x86_emit_floatuns (rtx operands[2])
23519 rtx neglab, donelab, i0, i1, f0, in, out;
23520 enum machine_mode mode, inmode;
23522 inmode = GET_MODE (operands[1]);
23523 gcc_assert (inmode == SImode || inmode == DImode);
23526 in = force_reg (inmode, operands[1]);
23527 mode = GET_MODE (out);
23528 neglab = gen_label_rtx ();
23529 donelab = gen_label_rtx ();
23530 f0 = gen_reg_rtx (mode);
23532 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
23534 expand_float (out, in, 0);
23536 emit_jump_insn (gen_jump (donelab));
23539 emit_label (neglab);
23541 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
23543 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
23545 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
23547 expand_float (f0, i0, 0);
23549 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
23551 emit_label (donelab);
23554 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23555 with all elements equal to VAR. Return true if successful. */
23558 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
23559 rtx target, rtx val)
23561 enum machine_mode smode, wsmode, wvmode;
23576 val = force_reg (GET_MODE_INNER (mode), val);
23577 x = gen_rtx_VEC_DUPLICATE (mode, val);
23578 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23584 if (TARGET_SSE || TARGET_3DNOW_A)
23586 val = gen_lowpart (SImode, val);
23587 x = gen_rtx_TRUNCATE (HImode, val);
23588 x = gen_rtx_VEC_DUPLICATE (mode, x);
23589 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23611 /* Extend HImode to SImode using a paradoxical SUBREG. */
23612 tmp1 = gen_reg_rtx (SImode);
23613 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23614 /* Insert the SImode value as low element of V4SImode vector. */
23615 tmp2 = gen_reg_rtx (V4SImode);
23616 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23617 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23618 CONST0_RTX (V4SImode),
23620 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23621 /* Cast the V4SImode vector back to a V8HImode vector. */
23622 tmp1 = gen_reg_rtx (V8HImode);
23623 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
23624 /* Duplicate the low short through the whole low SImode word. */
23625 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
23626 /* Cast the V8HImode vector back to a V4SImode vector. */
23627 tmp2 = gen_reg_rtx (V4SImode);
23628 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23629 /* Replicate the low element of the V4SImode vector. */
23630 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23631 /* Cast the V2SImode back to V8HImode, and store in target. */
23632 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
23643 /* Extend QImode to SImode using a paradoxical SUBREG. */
23644 tmp1 = gen_reg_rtx (SImode);
23645 emit_move_insn (tmp1, gen_lowpart (SImode, val));
23646 /* Insert the SImode value as low element of V4SImode vector. */
23647 tmp2 = gen_reg_rtx (V4SImode);
23648 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
23649 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
23650 CONST0_RTX (V4SImode),
23652 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
23653 /* Cast the V4SImode vector back to a V16QImode vector. */
23654 tmp1 = gen_reg_rtx (V16QImode);
23655 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
23656 /* Duplicate the low byte through the whole low SImode word. */
23657 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23658 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
23659 /* Cast the V16QImode vector back to a V4SImode vector. */
23660 tmp2 = gen_reg_rtx (V4SImode);
23661 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
23662 /* Replicate the low element of the V4SImode vector. */
23663 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
23664 /* Cast the V2SImode back to V16QImode, and store in target. */
23665 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
23673 /* Replicate the value once into the next wider mode and recurse. */
23674 val = convert_modes (wsmode, smode, val, true);
23675 x = expand_simple_binop (wsmode, ASHIFT, val,
23676 GEN_INT (GET_MODE_BITSIZE (smode)),
23677 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23678 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
23680 x = gen_reg_rtx (wvmode);
23681 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
23682 gcc_unreachable ();
23683 emit_move_insn (target, gen_lowpart (mode, x));
23691 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23692 whose ONE_VAR element is VAR, and other elements are zero. Return true
23696 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
23697 rtx target, rtx var, int one_var)
23699 enum machine_mode vsimode;
23715 var = force_reg (GET_MODE_INNER (mode), var);
23716 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
23717 emit_insn (gen_rtx_SET (VOIDmode, target, x));
23722 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
23723 new_target = gen_reg_rtx (mode);
23725 new_target = target;
23726 var = force_reg (GET_MODE_INNER (mode), var);
23727 x = gen_rtx_VEC_DUPLICATE (mode, var);
23728 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
23729 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
23732 /* We need to shuffle the value to the correct position, so
23733 create a new pseudo to store the intermediate result. */
23735 /* With SSE2, we can use the integer shuffle insns. */
23736 if (mode != V4SFmode && TARGET_SSE2)
23738 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
23740 GEN_INT (one_var == 1 ? 0 : 1),
23741 GEN_INT (one_var == 2 ? 0 : 1),
23742 GEN_INT (one_var == 3 ? 0 : 1)));
23743 if (target != new_target)
23744 emit_move_insn (target, new_target);
23748 /* Otherwise convert the intermediate result to V4SFmode and
23749 use the SSE1 shuffle instructions. */
23750 if (mode != V4SFmode)
23752 tmp = gen_reg_rtx (V4SFmode);
23753 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
23758 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
23760 GEN_INT (one_var == 1 ? 0 : 1),
23761 GEN_INT (one_var == 2 ? 0+4 : 1+4),
23762 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
23764 if (mode != V4SFmode)
23765 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
23766 else if (tmp != target)
23767 emit_move_insn (target, tmp);
23769 else if (target != new_target)
23770 emit_move_insn (target, new_target);
23775 vsimode = V4SImode;
23781 vsimode = V2SImode;
23787 /* Zero extend the variable element to SImode and recurse. */
23788 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
23790 x = gen_reg_rtx (vsimode);
23791 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
23793 gcc_unreachable ();
23795 emit_move_insn (target, gen_lowpart (mode, x));
23803 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
23804 consisting of the values in VALS. It is known that all elements
23805 except ONE_VAR are constants. Return true if successful. */
23808 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
23809 rtx target, rtx vals, int one_var)
23811 rtx var = XVECEXP (vals, 0, one_var);
23812 enum machine_mode wmode;
23815 const_vec = copy_rtx (vals);
23816 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
23817 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
23825 /* For the two element vectors, it's just as easy to use
23826 the general case. */
23842 /* There's no way to set one QImode entry easily. Combine
23843 the variable value with its adjacent constant value, and
23844 promote to an HImode set. */
23845 x = XVECEXP (vals, 0, one_var ^ 1);
23848 var = convert_modes (HImode, QImode, var, true);
23849 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
23850 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23851 x = GEN_INT (INTVAL (x) & 0xff);
23855 var = convert_modes (HImode, QImode, var, true);
23856 x = gen_int_mode (INTVAL (x) << 8, HImode);
23858 if (x != const0_rtx)
23859 var = expand_simple_binop (HImode, IOR, var, x, var,
23860 1, OPTAB_LIB_WIDEN);
23862 x = gen_reg_rtx (wmode);
23863 emit_move_insn (x, gen_lowpart (wmode, const_vec));
23864 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
23866 emit_move_insn (target, gen_lowpart (mode, x));
23873 emit_move_insn (target, const_vec);
23874 ix86_expand_vector_set (mmx_ok, target, var, one_var);
23878 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
23879 all values variable, and none identical. */
23882 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
23883 rtx target, rtx vals)
23885 enum machine_mode half_mode = GET_MODE_INNER (mode);
23886 rtx op0 = NULL, op1 = NULL;
23887 bool use_vec_concat = false;
23893 if (!mmx_ok && !TARGET_SSE)
23899 /* For the two element vectors, we always implement VEC_CONCAT. */
23900 op0 = XVECEXP (vals, 0, 0);
23901 op1 = XVECEXP (vals, 0, 1);
23902 use_vec_concat = true;
23906 half_mode = V2SFmode;
23909 half_mode = V2SImode;
23915 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
23916 Recurse to load the two halves. */
23918 op0 = gen_reg_rtx (half_mode);
23919 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
23920 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
23922 op1 = gen_reg_rtx (half_mode);
23923 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
23924 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
23926 use_vec_concat = true;
23937 gcc_unreachable ();
23940 if (use_vec_concat)
23942 if (!register_operand (op0, half_mode))
23943 op0 = force_reg (half_mode, op0);
23944 if (!register_operand (op1, half_mode))
23945 op1 = force_reg (half_mode, op1);
23947 emit_insn (gen_rtx_SET (VOIDmode, target,
23948 gen_rtx_VEC_CONCAT (mode, op0, op1)));
23952 int i, j, n_elts, n_words, n_elt_per_word;
23953 enum machine_mode inner_mode;
23954 rtx words[4], shift;
23956 inner_mode = GET_MODE_INNER (mode);
23957 n_elts = GET_MODE_NUNITS (mode);
23958 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
23959 n_elt_per_word = n_elts / n_words;
23960 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
23962 for (i = 0; i < n_words; ++i)
23964 rtx word = NULL_RTX;
23966 for (j = 0; j < n_elt_per_word; ++j)
23968 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
23969 elt = convert_modes (word_mode, inner_mode, elt, true);
23975 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
23976 word, 1, OPTAB_LIB_WIDEN);
23977 word = expand_simple_binop (word_mode, IOR, word, elt,
23978 word, 1, OPTAB_LIB_WIDEN);
23986 emit_move_insn (target, gen_lowpart (mode, words[0]));
23987 else if (n_words == 2)
23989 rtx tmp = gen_reg_rtx (mode);
23990 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
23991 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
23992 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
23993 emit_move_insn (target, tmp);
23995 else if (n_words == 4)
23997 rtx tmp = gen_reg_rtx (V4SImode);
23998 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
23999 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
24000 emit_move_insn (target, gen_lowpart (mode, tmp));
24003 gcc_unreachable ();
24007 /* Initialize vector TARGET via VALS. Suppress the use of MMX
24008 instructions unless MMX_OK is true. */
24011 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
24013 enum machine_mode mode = GET_MODE (target);
24014 enum machine_mode inner_mode = GET_MODE_INNER (mode);
24015 int n_elts = GET_MODE_NUNITS (mode);
24016 int n_var = 0, one_var = -1;
24017 bool all_same = true, all_const_zero = true;
24021 for (i = 0; i < n_elts; ++i)
24023 x = XVECEXP (vals, 0, i);
24024 if (!(CONST_INT_P (x)
24025 || GET_CODE (x) == CONST_DOUBLE
24026 || GET_CODE (x) == CONST_FIXED))
24027 n_var++, one_var = i;
24028 else if (x != CONST0_RTX (inner_mode))
24029 all_const_zero = false;
24030 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
24034 /* Constants are best loaded from the constant pool. */
24037 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
24041 /* If all values are identical, broadcast the value. */
24043 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
24044 XVECEXP (vals, 0, 0)))
24047 /* Values where only one field is non-constant are best loaded from
24048 the pool and overwritten via move later. */
24052 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
24053 XVECEXP (vals, 0, one_var),
24057 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
24061 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
24065 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
24067 enum machine_mode mode = GET_MODE (target);
24068 enum machine_mode inner_mode = GET_MODE_INNER (mode);
24069 bool use_vec_merge = false;
24078 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
24079 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
24081 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
24083 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
24084 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24090 use_vec_merge = TARGET_SSE4_1;
24098 /* For the two element vectors, we implement a VEC_CONCAT with
24099 the extraction of the other element. */
24101 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
24102 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
24105 op0 = val, op1 = tmp;
24107 op0 = tmp, op1 = val;
24109 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
24110 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24115 use_vec_merge = TARGET_SSE4_1;
24122 use_vec_merge = true;
24126 /* tmp = target = A B C D */
24127 tmp = copy_to_reg (target);
24128 /* target = A A B B */
24129 emit_insn (gen_sse_unpcklps (target, target, target));
24130 /* target = X A B B */
24131 ix86_expand_vector_set (false, target, val, 0);
24132 /* target = A X C D */
24133 emit_insn (gen_sse_shufps_1 (target, target, tmp,
24134 GEN_INT (1), GEN_INT (0),
24135 GEN_INT (2+4), GEN_INT (3+4)));
24139 /* tmp = target = A B C D */
24140 tmp = copy_to_reg (target);
24141 /* tmp = X B C D */
24142 ix86_expand_vector_set (false, tmp, val, 0);
24143 /* target = A B X D */
24144 emit_insn (gen_sse_shufps_1 (target, target, tmp,
24145 GEN_INT (0), GEN_INT (1),
24146 GEN_INT (0+4), GEN_INT (3+4)));
24150 /* tmp = target = A B C D */
24151 tmp = copy_to_reg (target);
24152 /* tmp = X B C D */
24153 ix86_expand_vector_set (false, tmp, val, 0);
24154 /* target = A B X D */
24155 emit_insn (gen_sse_shufps_1 (target, target, tmp,
24156 GEN_INT (0), GEN_INT (1),
24157 GEN_INT (2+4), GEN_INT (0+4)));
24161 gcc_unreachable ();
24166 use_vec_merge = TARGET_SSE4_1;
24170 /* Element 0 handled by vec_merge below. */
24173 use_vec_merge = true;
24179 /* With SSE2, use integer shuffles to swap element 0 and ELT,
24180 store into element 0, then shuffle them back. */
24184 order[0] = GEN_INT (elt);
24185 order[1] = const1_rtx;
24186 order[2] = const2_rtx;
24187 order[3] = GEN_INT (3);
24188 order[elt] = const0_rtx;
24190 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
24191 order[1], order[2], order[3]));
24193 ix86_expand_vector_set (false, target, val, 0);
24195 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
24196 order[1], order[2], order[3]));
24200 /* For SSE1, we have to reuse the V4SF code. */
24201 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
24202 gen_lowpart (SFmode, val), elt);
24207 use_vec_merge = TARGET_SSE2;
24210 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
24214 use_vec_merge = TARGET_SSE4_1;
24224 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
24225 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
24226 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24230 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
24232 emit_move_insn (mem, target);
24234 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
24235 emit_move_insn (tmp, val);
24237 emit_move_insn (target, mem);
24242 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
24244 enum machine_mode mode = GET_MODE (vec);
24245 enum machine_mode inner_mode = GET_MODE_INNER (mode);
24246 bool use_vec_extr = false;
24259 use_vec_extr = true;
24263 use_vec_extr = TARGET_SSE4_1;
24275 tmp = gen_reg_rtx (mode);
24276 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
24277 GEN_INT (elt), GEN_INT (elt),
24278 GEN_INT (elt+4), GEN_INT (elt+4)));
24282 tmp = gen_reg_rtx (mode);
24283 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
24287 gcc_unreachable ();
24290 use_vec_extr = true;
24295 use_vec_extr = TARGET_SSE4_1;
24309 tmp = gen_reg_rtx (mode);
24310 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
24311 GEN_INT (elt), GEN_INT (elt),
24312 GEN_INT (elt), GEN_INT (elt)));
24316 tmp = gen_reg_rtx (mode);
24317 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
24321 gcc_unreachable ();
24324 use_vec_extr = true;
24329 /* For SSE1, we have to reuse the V4SF code. */
24330 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
24331 gen_lowpart (V4SFmode, vec), elt);
24337 use_vec_extr = TARGET_SSE2;
24340 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
24344 use_vec_extr = TARGET_SSE4_1;
24348 /* ??? Could extract the appropriate HImode element and shift. */
24355 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
24356 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
24358 /* Let the rtl optimizers know about the zero extension performed. */
24359 if (inner_mode == QImode || inner_mode == HImode)
24361 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
24362 target = gen_lowpart (SImode, target);
24365 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
24369 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
24371 emit_move_insn (mem, vec);
24373 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
24374 emit_move_insn (target, tmp);
24378 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
24379 pattern to reduce; DEST is the destination; IN is the input vector. */
24382 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
24384 rtx tmp1, tmp2, tmp3;
24386 tmp1 = gen_reg_rtx (V4SFmode);
24387 tmp2 = gen_reg_rtx (V4SFmode);
24388 tmp3 = gen_reg_rtx (V4SFmode);
24390 emit_insn (gen_sse_movhlps (tmp1, in, in));
24391 emit_insn (fn (tmp2, tmp1, in));
24393 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
24394 GEN_INT (1), GEN_INT (1),
24395 GEN_INT (1+4), GEN_INT (1+4)));
24396 emit_insn (fn (dest, tmp2, tmp3));
24399 /* Target hook for scalar_mode_supported_p. */
24401 ix86_scalar_mode_supported_p (enum machine_mode mode)
24403 if (DECIMAL_FLOAT_MODE_P (mode))
24405 else if (mode == TFmode)
24406 return TARGET_64BIT;
24408 return default_scalar_mode_supported_p (mode);
24411 /* Implements target hook vector_mode_supported_p. */
24413 ix86_vector_mode_supported_p (enum machine_mode mode)
24415 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
24417 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
24419 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
24421 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
24426 /* Target hook for c_mode_for_suffix. */
24427 static enum machine_mode
24428 ix86_c_mode_for_suffix (char suffix)
24430 if (TARGET_64BIT && suffix == 'q')
24432 if (TARGET_MMX && suffix == 'w')
24438 /* Worker function for TARGET_MD_ASM_CLOBBERS.
24440 We do this in the new i386 backend to maintain source compatibility
24441 with the old cc0-based compiler. */
24444 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
24445 tree inputs ATTRIBUTE_UNUSED,
24448 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
24450 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
24455 /* Implements target vector targetm.asm.encode_section_info. This
24456 is not used by netware. */
24458 static void ATTRIBUTE_UNUSED
24459 ix86_encode_section_info (tree decl, rtx rtl, int first)
24461 default_encode_section_info (decl, rtl, first);
24463 if (TREE_CODE (decl) == VAR_DECL
24464 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
24465 && ix86_in_large_data_p (decl))
24466 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
24469 /* Worker function for REVERSE_CONDITION. */
24472 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
24474 return (mode != CCFPmode && mode != CCFPUmode
24475 ? reverse_condition (code)
24476 : reverse_condition_maybe_unordered (code));
24479 /* Output code to perform an x87 FP register move, from OPERANDS[1]
24483 output_387_reg_move (rtx insn, rtx *operands)
24485 if (REG_P (operands[0]))
24487 if (REG_P (operands[1])
24488 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24490 if (REGNO (operands[0]) == FIRST_STACK_REG)
24491 return output_387_ffreep (operands, 0);
24492 return "fstp\t%y0";
24494 if (STACK_TOP_P (operands[0]))
24495 return "fld%z1\t%y1";
24498 else if (MEM_P (operands[0]))
24500 gcc_assert (REG_P (operands[1]));
24501 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
24502 return "fstp%z0\t%y0";
24505 /* There is no non-popping store to memory for XFmode.
24506 So if we need one, follow the store with a load. */
24507 if (GET_MODE (operands[0]) == XFmode)
24508 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
24510 return "fst%z0\t%y0";
24517 /* Output code to perform a conditional jump to LABEL, if C2 flag in
24518 FP status register is set. */
24521 ix86_emit_fp_unordered_jump (rtx label)
24523 rtx reg = gen_reg_rtx (HImode);
24526 emit_insn (gen_x86_fnstsw_1 (reg));
24528 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_size))
24530 emit_insn (gen_x86_sahf_1 (reg));
24532 temp = gen_rtx_REG (CCmode, FLAGS_REG);
24533 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
24537 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
24539 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
24540 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
24543 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
24544 gen_rtx_LABEL_REF (VOIDmode, label),
24546 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
24548 emit_jump_insn (temp);
24549 predict_jump (REG_BR_PROB_BASE * 10 / 100);
24552 /* Output code to perform a log1p XFmode calculation. */
24554 void ix86_emit_i387_log1p (rtx op0, rtx op1)
24556 rtx label1 = gen_label_rtx ();
24557 rtx label2 = gen_label_rtx ();
24559 rtx tmp = gen_reg_rtx (XFmode);
24560 rtx tmp2 = gen_reg_rtx (XFmode);
24562 emit_insn (gen_absxf2 (tmp, op1));
24563 emit_insn (gen_cmpxf (tmp,
24564 CONST_DOUBLE_FROM_REAL_VALUE (
24565 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
24567 emit_jump_insn (gen_bge (label1));
24569 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24570 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
24571 emit_jump (label2);
24573 emit_label (label1);
24574 emit_move_insn (tmp, CONST1_RTX (XFmode));
24575 emit_insn (gen_addxf3 (tmp, op1, tmp));
24576 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
24577 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
24579 emit_label (label2);
24582 /* Output code to perform a Newton-Rhapson approximation of a single precision
24583 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
24585 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
24587 rtx x0, x1, e0, e1, two;
24589 x0 = gen_reg_rtx (mode);
24590 e0 = gen_reg_rtx (mode);
24591 e1 = gen_reg_rtx (mode);
24592 x1 = gen_reg_rtx (mode);
24594 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
24596 if (VECTOR_MODE_P (mode))
24597 two = ix86_build_const_vector (SFmode, true, two);
24599 two = force_reg (mode, two);
24601 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
24603 /* x0 = rcp(b) estimate */
24604 emit_insn (gen_rtx_SET (VOIDmode, x0,
24605 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
24608 emit_insn (gen_rtx_SET (VOIDmode, e0,
24609 gen_rtx_MULT (mode, x0, b)));
24611 emit_insn (gen_rtx_SET (VOIDmode, e1,
24612 gen_rtx_MINUS (mode, two, e0)));
24614 emit_insn (gen_rtx_SET (VOIDmode, x1,
24615 gen_rtx_MULT (mode, x0, e1)));
24617 emit_insn (gen_rtx_SET (VOIDmode, res,
24618 gen_rtx_MULT (mode, a, x1)));
24621 /* Output code to perform a Newton-Rhapson approximation of a
24622 single precision floating point [reciprocal] square root. */
24624 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
24627 rtx x0, e0, e1, e2, e3, mthree, mhalf;
24630 x0 = gen_reg_rtx (mode);
24631 e0 = gen_reg_rtx (mode);
24632 e1 = gen_reg_rtx (mode);
24633 e2 = gen_reg_rtx (mode);
24634 e3 = gen_reg_rtx (mode);
24636 real_from_integer (&r, VOIDmode, -3, -1, 0);
24637 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24639 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
24640 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
24642 if (VECTOR_MODE_P (mode))
24644 mthree = ix86_build_const_vector (SFmode, true, mthree);
24645 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
24648 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
24649 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
24651 /* x0 = rsqrt(a) estimate */
24652 emit_insn (gen_rtx_SET (VOIDmode, x0,
24653 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
24656 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
24661 zero = gen_reg_rtx (mode);
24662 mask = gen_reg_rtx (mode);
24664 zero = force_reg (mode, CONST0_RTX(mode));
24665 emit_insn (gen_rtx_SET (VOIDmode, mask,
24666 gen_rtx_NE (mode, zero, a)));
24668 emit_insn (gen_rtx_SET (VOIDmode, x0,
24669 gen_rtx_AND (mode, x0, mask)));
24673 emit_insn (gen_rtx_SET (VOIDmode, e0,
24674 gen_rtx_MULT (mode, x0, a)));
24676 emit_insn (gen_rtx_SET (VOIDmode, e1,
24677 gen_rtx_MULT (mode, e0, x0)));
24680 mthree = force_reg (mode, mthree);
24681 emit_insn (gen_rtx_SET (VOIDmode, e2,
24682 gen_rtx_PLUS (mode, e1, mthree)));
24684 mhalf = force_reg (mode, mhalf);
24686 /* e3 = -.5 * x0 */
24687 emit_insn (gen_rtx_SET (VOIDmode, e3,
24688 gen_rtx_MULT (mode, x0, mhalf)));
24690 /* e3 = -.5 * e0 */
24691 emit_insn (gen_rtx_SET (VOIDmode, e3,
24692 gen_rtx_MULT (mode, e0, mhalf)));
24693 /* ret = e2 * e3 */
24694 emit_insn (gen_rtx_SET (VOIDmode, res,
24695 gen_rtx_MULT (mode, e2, e3)));
24698 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
24700 static void ATTRIBUTE_UNUSED
24701 i386_solaris_elf_named_section (const char *name, unsigned int flags,
24704 /* With Binutils 2.15, the "@unwind" marker must be specified on
24705 every occurrence of the ".eh_frame" section, not just the first
24708 && strcmp (name, ".eh_frame") == 0)
24710 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
24711 flags & SECTION_WRITE ? "aw" : "a");
24714 default_elf_asm_named_section (name, flags, decl);
24717 /* Return the mangling of TYPE if it is an extended fundamental type. */
24719 static const char *
24720 ix86_mangle_type (const_tree type)
24722 type = TYPE_MAIN_VARIANT (type);
24724 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24725 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24728 switch (TYPE_MODE (type))
24731 /* __float128 is "g". */
24734 /* "long double" or __float80 is "e". */
24741 /* For 32-bit code we can save PIC register setup by using
24742 __stack_chk_fail_local hidden function instead of calling
24743 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
24744 register, so it is better to call __stack_chk_fail directly. */
24747 ix86_stack_protect_fail (void)
24749 return TARGET_64BIT
24750 ? default_external_stack_protect_fail ()
24751 : default_hidden_stack_protect_fail ();
24754 /* Select a format to encode pointers in exception handling data. CODE
24755 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
24756 true if the symbol may be affected by dynamic relocations.
24758 ??? All x86 object file formats are capable of representing this.
24759 After all, the relocation needed is the same as for the call insn.
24760 Whether or not a particular assembler allows us to enter such, I
24761 guess we'll have to see. */
24763 asm_preferred_eh_data_format (int code, int global)
24767 int type = DW_EH_PE_sdata8;
24769 || ix86_cmodel == CM_SMALL_PIC
24770 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
24771 type = DW_EH_PE_sdata4;
24772 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
24774 if (ix86_cmodel == CM_SMALL
24775 || (ix86_cmodel == CM_MEDIUM && code))
24776 return DW_EH_PE_udata4;
24777 return DW_EH_PE_absptr;
24780 /* Expand copysign from SIGN to the positive value ABS_VALUE
24781 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
24784 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
24786 enum machine_mode mode = GET_MODE (sign);
24787 rtx sgn = gen_reg_rtx (mode);
24788 if (mask == NULL_RTX)
24790 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
24791 if (!VECTOR_MODE_P (mode))
24793 /* We need to generate a scalar mode mask in this case. */
24794 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
24795 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
24796 mask = gen_reg_rtx (mode);
24797 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
24801 mask = gen_rtx_NOT (mode, mask);
24802 emit_insn (gen_rtx_SET (VOIDmode, sgn,
24803 gen_rtx_AND (mode, mask, sign)));
24804 emit_insn (gen_rtx_SET (VOIDmode, result,
24805 gen_rtx_IOR (mode, abs_value, sgn)));
24808 /* Expand fabs (OP0) and return a new rtx that holds the result. The
24809 mask for masking out the sign-bit is stored in *SMASK, if that is
24812 ix86_expand_sse_fabs (rtx op0, rtx *smask)
24814 enum machine_mode mode = GET_MODE (op0);
24817 xa = gen_reg_rtx (mode);
24818 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
24819 if (!VECTOR_MODE_P (mode))
24821 /* We need to generate a scalar mode mask in this case. */
24822 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
24823 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
24824 mask = gen_reg_rtx (mode);
24825 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
24827 emit_insn (gen_rtx_SET (VOIDmode, xa,
24828 gen_rtx_AND (mode, op0, mask)));
24836 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
24837 swapping the operands if SWAP_OPERANDS is true. The expanded
24838 code is a forward jump to a newly created label in case the
24839 comparison is true. The generated label rtx is returned. */
24841 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
24842 bool swap_operands)
24853 label = gen_label_rtx ();
24854 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
24855 emit_insn (gen_rtx_SET (VOIDmode, tmp,
24856 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
24857 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
24858 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
24859 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
24860 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
24861 JUMP_LABEL (tmp) = label;
24866 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
24867 using comparison code CODE. Operands are swapped for the comparison if
24868 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
24870 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
24871 bool swap_operands)
24873 enum machine_mode mode = GET_MODE (op0);
24874 rtx mask = gen_reg_rtx (mode);
24883 if (mode == DFmode)
24884 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
24885 gen_rtx_fmt_ee (code, mode, op0, op1)));
24887 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
24888 gen_rtx_fmt_ee (code, mode, op0, op1)));
24893 /* Generate and return a rtx of mode MODE for 2**n where n is the number
24894 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
24896 ix86_gen_TWO52 (enum machine_mode mode)
24898 REAL_VALUE_TYPE TWO52r;
24901 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
24902 TWO52 = const_double_from_real_value (TWO52r, mode);
24903 TWO52 = force_reg (mode, TWO52);
24908 /* Expand SSE sequence for computing lround from OP1 storing
24911 ix86_expand_lround (rtx op0, rtx op1)
24913 /* C code for the stuff we're doing below:
24914 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
24917 enum machine_mode mode = GET_MODE (op1);
24918 const struct real_format *fmt;
24919 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
24922 /* load nextafter (0.5, 0.0) */
24923 fmt = REAL_MODE_FORMAT (mode);
24924 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
24925 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
24927 /* adj = copysign (0.5, op1) */
24928 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
24929 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
24931 /* adj = op1 + adj */
24932 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
24934 /* op0 = (imode)adj */
24935 expand_fix (op0, adj, 0);
24938 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
24941 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
24943 /* C code for the stuff we're doing below (for do_floor):
24945 xi -= (double)xi > op1 ? 1 : 0;
24948 enum machine_mode fmode = GET_MODE (op1);
24949 enum machine_mode imode = GET_MODE (op0);
24950 rtx ireg, freg, label, tmp;
24952 /* reg = (long)op1 */
24953 ireg = gen_reg_rtx (imode);
24954 expand_fix (ireg, op1, 0);
24956 /* freg = (double)reg */
24957 freg = gen_reg_rtx (fmode);
24958 expand_float (freg, ireg, 0);
24960 /* ireg = (freg > op1) ? ireg - 1 : ireg */
24961 label = ix86_expand_sse_compare_and_jump (UNLE,
24962 freg, op1, !do_floor);
24963 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
24964 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
24965 emit_move_insn (ireg, tmp);
24967 emit_label (label);
24968 LABEL_NUSES (label) = 1;
24970 emit_move_insn (op0, ireg);
24973 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
24974 result in OPERAND0. */
24976 ix86_expand_rint (rtx operand0, rtx operand1)
24978 /* C code for the stuff we're doing below:
24979 xa = fabs (operand1);
24980 if (!isless (xa, 2**52))
24982 xa = xa + 2**52 - 2**52;
24983 return copysign (xa, operand1);
24985 enum machine_mode mode = GET_MODE (operand0);
24986 rtx res, xa, label, TWO52, mask;
24988 res = gen_reg_rtx (mode);
24989 emit_move_insn (res, operand1);
24991 /* xa = abs (operand1) */
24992 xa = ix86_expand_sse_fabs (res, &mask);
24994 /* if (!isless (xa, TWO52)) goto label; */
24995 TWO52 = ix86_gen_TWO52 (mode);
24996 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
24998 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
24999 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
25001 ix86_sse_copysign_to_positive (res, xa, res, mask);
25003 emit_label (label);
25004 LABEL_NUSES (label) = 1;
25006 emit_move_insn (operand0, res);
25009 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
25012 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
25014 /* C code for the stuff we expand below.
25015 double xa = fabs (x), x2;
25016 if (!isless (xa, TWO52))
25018 xa = xa + TWO52 - TWO52;
25019 x2 = copysign (xa, x);
25028 enum machine_mode mode = GET_MODE (operand0);
25029 rtx xa, TWO52, tmp, label, one, res, mask;
25031 TWO52 = ix86_gen_TWO52 (mode);
25033 /* Temporary for holding the result, initialized to the input
25034 operand to ease control flow. */
25035 res = gen_reg_rtx (mode);
25036 emit_move_insn (res, operand1);
25038 /* xa = abs (operand1) */
25039 xa = ix86_expand_sse_fabs (res, &mask);
25041 /* if (!isless (xa, TWO52)) goto label; */
25042 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25044 /* xa = xa + TWO52 - TWO52; */
25045 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25046 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
25048 /* xa = copysign (xa, operand1) */
25049 ix86_sse_copysign_to_positive (xa, xa, res, mask);
25051 /* generate 1.0 or -1.0 */
25052 one = force_reg (mode,
25053 const_double_from_real_value (do_floor
25054 ? dconst1 : dconstm1, mode));
25056 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
25057 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
25058 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25059 gen_rtx_AND (mode, one, tmp)));
25060 /* We always need to subtract here to preserve signed zero. */
25061 tmp = expand_simple_binop (mode, MINUS,
25062 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25063 emit_move_insn (res, tmp);
25065 emit_label (label);
25066 LABEL_NUSES (label) = 1;
25068 emit_move_insn (operand0, res);
25071 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
25074 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
25076 /* C code for the stuff we expand below.
25077 double xa = fabs (x), x2;
25078 if (!isless (xa, TWO52))
25080 x2 = (double)(long)x;
25087 if (HONOR_SIGNED_ZEROS (mode))
25088 return copysign (x2, x);
25091 enum machine_mode mode = GET_MODE (operand0);
25092 rtx xa, xi, TWO52, tmp, label, one, res, mask;
25094 TWO52 = ix86_gen_TWO52 (mode);
25096 /* Temporary for holding the result, initialized to the input
25097 operand to ease control flow. */
25098 res = gen_reg_rtx (mode);
25099 emit_move_insn (res, operand1);
25101 /* xa = abs (operand1) */
25102 xa = ix86_expand_sse_fabs (res, &mask);
25104 /* if (!isless (xa, TWO52)) goto label; */
25105 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25107 /* xa = (double)(long)x */
25108 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25109 expand_fix (xi, res, 0);
25110 expand_float (xa, xi, 0);
25113 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
25115 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
25116 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
25117 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25118 gen_rtx_AND (mode, one, tmp)));
25119 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
25120 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25121 emit_move_insn (res, tmp);
25123 if (HONOR_SIGNED_ZEROS (mode))
25124 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
25126 emit_label (label);
25127 LABEL_NUSES (label) = 1;
25129 emit_move_insn (operand0, res);
25132 /* Expand SSE sequence for computing round from OPERAND1 storing
25133 into OPERAND0. Sequence that works without relying on DImode truncation
25134 via cvttsd2siq that is only available on 64bit targets. */
25136 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
25138 /* C code for the stuff we expand below.
25139 double xa = fabs (x), xa2, x2;
25140 if (!isless (xa, TWO52))
25142 Using the absolute value and copying back sign makes
25143 -0.0 -> -0.0 correct.
25144 xa2 = xa + TWO52 - TWO52;
25149 else if (dxa > 0.5)
25151 x2 = copysign (xa2, x);
25154 enum machine_mode mode = GET_MODE (operand0);
25155 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
25157 TWO52 = ix86_gen_TWO52 (mode);
25159 /* Temporary for holding the result, initialized to the input
25160 operand to ease control flow. */
25161 res = gen_reg_rtx (mode);
25162 emit_move_insn (res, operand1);
25164 /* xa = abs (operand1) */
25165 xa = ix86_expand_sse_fabs (res, &mask);
25167 /* if (!isless (xa, TWO52)) goto label; */
25168 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25170 /* xa2 = xa + TWO52 - TWO52; */
25171 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25172 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
25174 /* dxa = xa2 - xa; */
25175 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
25177 /* generate 0.5, 1.0 and -0.5 */
25178 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
25179 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
25180 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
25184 tmp = gen_reg_rtx (mode);
25185 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
25186 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
25187 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25188 gen_rtx_AND (mode, one, tmp)));
25189 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25190 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
25191 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
25192 emit_insn (gen_rtx_SET (VOIDmode, tmp,
25193 gen_rtx_AND (mode, one, tmp)));
25194 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
25196 /* res = copysign (xa2, operand1) */
25197 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
25199 emit_label (label);
25200 LABEL_NUSES (label) = 1;
25202 emit_move_insn (operand0, res);
25205 /* Expand SSE sequence for computing trunc from OPERAND1 storing
25208 ix86_expand_trunc (rtx operand0, rtx operand1)
25210 /* C code for SSE variant we expand below.
25211 double xa = fabs (x), x2;
25212 if (!isless (xa, TWO52))
25214 x2 = (double)(long)x;
25215 if (HONOR_SIGNED_ZEROS (mode))
25216 return copysign (x2, x);
25219 enum machine_mode mode = GET_MODE (operand0);
25220 rtx xa, xi, TWO52, label, res, mask;
25222 TWO52 = ix86_gen_TWO52 (mode);
25224 /* Temporary for holding the result, initialized to the input
25225 operand to ease control flow. */
25226 res = gen_reg_rtx (mode);
25227 emit_move_insn (res, operand1);
25229 /* xa = abs (operand1) */
25230 xa = ix86_expand_sse_fabs (res, &mask);
25232 /* if (!isless (xa, TWO52)) goto label; */
25233 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25235 /* x = (double)(long)x */
25236 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25237 expand_fix (xi, res, 0);
25238 expand_float (res, xi, 0);
25240 if (HONOR_SIGNED_ZEROS (mode))
25241 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
25243 emit_label (label);
25244 LABEL_NUSES (label) = 1;
25246 emit_move_insn (operand0, res);
25249 /* Expand SSE sequence for computing trunc from OPERAND1 storing
25252 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
25254 enum machine_mode mode = GET_MODE (operand0);
25255 rtx xa, mask, TWO52, label, one, res, smask, tmp;
25257 /* C code for SSE variant we expand below.
25258 double xa = fabs (x), x2;
25259 if (!isless (xa, TWO52))
25261 xa2 = xa + TWO52 - TWO52;
25265 x2 = copysign (xa2, x);
25269 TWO52 = ix86_gen_TWO52 (mode);
25271 /* Temporary for holding the result, initialized to the input
25272 operand to ease control flow. */
25273 res = gen_reg_rtx (mode);
25274 emit_move_insn (res, operand1);
25276 /* xa = abs (operand1) */
25277 xa = ix86_expand_sse_fabs (res, &smask);
25279 /* if (!isless (xa, TWO52)) goto label; */
25280 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25282 /* res = xa + TWO52 - TWO52; */
25283 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
25284 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
25285 emit_move_insn (res, tmp);
25288 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
25290 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
25291 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
25292 emit_insn (gen_rtx_SET (VOIDmode, mask,
25293 gen_rtx_AND (mode, mask, one)));
25294 tmp = expand_simple_binop (mode, MINUS,
25295 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
25296 emit_move_insn (res, tmp);
25298 /* res = copysign (res, operand1) */
25299 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
25301 emit_label (label);
25302 LABEL_NUSES (label) = 1;
25304 emit_move_insn (operand0, res);
25307 /* Expand SSE sequence for computing round from OPERAND1 storing
25310 ix86_expand_round (rtx operand0, rtx operand1)
25312 /* C code for the stuff we're doing below:
25313 double xa = fabs (x);
25314 if (!isless (xa, TWO52))
25316 xa = (double)(long)(xa + nextafter (0.5, 0.0));
25317 return copysign (xa, x);
25319 enum machine_mode mode = GET_MODE (operand0);
25320 rtx res, TWO52, xa, label, xi, half, mask;
25321 const struct real_format *fmt;
25322 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
25324 /* Temporary for holding the result, initialized to the input
25325 operand to ease control flow. */
25326 res = gen_reg_rtx (mode);
25327 emit_move_insn (res, operand1);
25329 TWO52 = ix86_gen_TWO52 (mode);
25330 xa = ix86_expand_sse_fabs (res, &mask);
25331 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
25333 /* load nextafter (0.5, 0.0) */
25334 fmt = REAL_MODE_FORMAT (mode);
25335 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
25336 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
25338 /* xa = xa + 0.5 */
25339 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
25340 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
25342 /* xa = (double)(int64_t)xa */
25343 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
25344 expand_fix (xi, xa, 0);
25345 expand_float (xa, xi, 0);
25347 /* res = copysign (xa, operand1) */
25348 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
25350 emit_label (label);
25351 LABEL_NUSES (label) = 1;
25353 emit_move_insn (operand0, res);
25357 /* Validate whether a SSE5 instruction is valid or not.
25358 OPERANDS is the array of operands.
25359 NUM is the number of operands.
25360 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
25361 NUM_MEMORY is the maximum number of memory operands to accept. */
25363 ix86_sse5_valid_op_p (rtx operands[], rtx insn, int num, bool uses_oc0, int num_memory)
25369 /* Count the number of memory arguments */
25372 for (i = 0; i < num; i++)
25374 enum machine_mode mode = GET_MODE (operands[i]);
25375 if (register_operand (operands[i], mode))
25378 else if (memory_operand (operands[i], mode))
25380 mem_mask |= (1 << i);
25386 rtx pattern = PATTERN (insn);
25388 /* allow 0 for pcmov */
25389 if (GET_CODE (pattern) != SET
25390 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
25392 || operands[i] != CONST0_RTX (mode))
25397 /* If there were no memory operations, allow the insn */
25401 /* Do not allow the destination register to be a memory operand. */
25402 else if (mem_mask & (1 << 0))
25405 /* If there are too many memory operations, disallow the instruction. While
25406 the hardware only allows 1 memory reference, before register allocation
25407 for some insns, we allow two memory operations sometimes in order to allow
25408 code like the following to be optimized:
25410 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
25412 or similar cases that are vectorized into using the fmaddss
25414 else if (mem_count > num_memory)
25417 /* Don't allow more than one memory operation if not optimizing. */
25418 else if (mem_count > 1 && !optimize)
25421 else if (num == 4 && mem_count == 1)
25423 /* formats (destination is the first argument), example fmaddss:
25424 xmm1, xmm1, xmm2, xmm3/mem
25425 xmm1, xmm1, xmm2/mem, xmm3
25426 xmm1, xmm2, xmm3/mem, xmm1
25427 xmm1, xmm2/mem, xmm3, xmm1 */
25429 return ((mem_mask == (1 << 1))
25430 || (mem_mask == (1 << 2))
25431 || (mem_mask == (1 << 3)));
25433 /* format, example pmacsdd:
25434 xmm1, xmm2, xmm3/mem, xmm1 */
25436 return (mem_mask == (1 << 2));
25439 else if (num == 4 && num_memory == 2)
25441 /* If there are two memory operations, we can load one of the memory ops
25442 into the destination register. This is for optimizing the
25443 multiply/add ops, which the combiner has optimized both the multiply
25444 and the add insns to have a memory operation. We have to be careful
25445 that the destination doesn't overlap with the inputs. */
25446 rtx op0 = operands[0];
25448 if (reg_mentioned_p (op0, operands[1])
25449 || reg_mentioned_p (op0, operands[2])
25450 || reg_mentioned_p (op0, operands[3]))
25453 /* formats (destination is the first argument), example fmaddss:
25454 xmm1, xmm1, xmm2, xmm3/mem
25455 xmm1, xmm1, xmm2/mem, xmm3
25456 xmm1, xmm2, xmm3/mem, xmm1
25457 xmm1, xmm2/mem, xmm3, xmm1
25459 For the oc0 case, we will load either operands[1] or operands[3] into
25460 operands[0], so any combination of 2 memory operands is ok. */
25464 /* format, example pmacsdd:
25465 xmm1, xmm2, xmm3/mem, xmm1
25467 For the integer multiply/add instructions be more restrictive and
25468 require operands[2] and operands[3] to be the memory operands. */
25470 return (mem_mask == ((1 << 2) | (1 << 3)));
25473 else if (num == 3 && num_memory == 1)
25475 /* formats, example protb:
25476 xmm1, xmm2, xmm3/mem
25477 xmm1, xmm2/mem, xmm3 */
25479 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
25481 /* format, example comeq:
25482 xmm1, xmm2, xmm3/mem */
25484 return (mem_mask == (1 << 2));
25488 gcc_unreachable ();
25494 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
25495 hardware will allow by using the destination register to load one of the
25496 memory operations. Presently this is used by the multiply/add routines to
25497 allow 2 memory references. */
25500 ix86_expand_sse5_multiple_memory (rtx operands[],
25502 enum machine_mode mode)
25504 rtx op0 = operands[0];
25506 || memory_operand (op0, mode)
25507 || reg_mentioned_p (op0, operands[1])
25508 || reg_mentioned_p (op0, operands[2])
25509 || reg_mentioned_p (op0, operands[3]))
25510 gcc_unreachable ();
25512 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
25513 the destination register. */
25514 if (memory_operand (operands[1], mode))
25516 emit_move_insn (op0, operands[1]);
25519 else if (memory_operand (operands[3], mode))
25521 emit_move_insn (op0, operands[3]);
25525 gcc_unreachable ();
25531 /* Table of valid machine attributes. */
25532 static const struct attribute_spec ix86_attribute_table[] =
25534 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
25535 /* Stdcall attribute says callee is responsible for popping arguments
25536 if they are not variable. */
25537 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25538 /* Fastcall attribute says callee is responsible for popping arguments
25539 if they are not variable. */
25540 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25541 /* Cdecl attribute says the callee is a normal C declaration */
25542 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25543 /* Regparm attribute specifies how many integer arguments are to be
25544 passed in registers. */
25545 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
25546 /* Sseregparm attribute says we are using x86_64 calling conventions
25547 for FP arguments. */
25548 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
25549 /* force_align_arg_pointer says this function realigns the stack at entry. */
25550 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
25551 false, true, true, ix86_handle_cconv_attribute },
25552 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25553 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
25554 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
25555 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
25557 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25558 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
25559 #ifdef SUBTARGET_ATTRIBUTE_TABLE
25560 SUBTARGET_ATTRIBUTE_TABLE,
25562 { NULL, 0, 0, false, false, false, NULL }
25565 /* Implement targetm.vectorize.builtin_vectorization_cost. */
25567 x86_builtin_vectorization_cost (bool runtime_test)
25569 /* If the branch of the runtime test is taken - i.e. - the vectorized
25570 version is skipped - this incurs a misprediction cost (because the
25571 vectorized version is expected to be the fall-through). So we subtract
25572 the latency of a mispredicted branch from the costs that are incured
25573 when the vectorized version is executed.
25575 TODO: The values in individual target tables have to be tuned or new
25576 fields may be needed. For eg. on K8, the default branch path is the
25577 not-taken path. If the taken path is predicted correctly, the minimum
25578 penalty of going down the taken-path is 1 cycle. If the taken-path is
25579 not predicted correctly, then the minimum penalty is 10 cycles. */
25583 return (-(ix86_cost->cond_taken_branch_cost));
25589 /* Initialize the GCC target structure. */
25590 #undef TARGET_ATTRIBUTE_TABLE
25591 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
25592 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25593 # undef TARGET_MERGE_DECL_ATTRIBUTES
25594 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
25597 #undef TARGET_COMP_TYPE_ATTRIBUTES
25598 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
25600 #undef TARGET_INIT_BUILTINS
25601 #define TARGET_INIT_BUILTINS ix86_init_builtins
25602 #undef TARGET_EXPAND_BUILTIN
25603 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
25605 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
25606 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
25607 ix86_builtin_vectorized_function
25609 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
25610 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
25612 #undef TARGET_BUILTIN_RECIPROCAL
25613 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
25615 #undef TARGET_ASM_FUNCTION_EPILOGUE
25616 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
25618 #undef TARGET_ENCODE_SECTION_INFO
25619 #ifndef SUBTARGET_ENCODE_SECTION_INFO
25620 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
25622 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
25625 #undef TARGET_ASM_OPEN_PAREN
25626 #define TARGET_ASM_OPEN_PAREN ""
25627 #undef TARGET_ASM_CLOSE_PAREN
25628 #define TARGET_ASM_CLOSE_PAREN ""
25630 #undef TARGET_ASM_ALIGNED_HI_OP
25631 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
25632 #undef TARGET_ASM_ALIGNED_SI_OP
25633 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
25635 #undef TARGET_ASM_ALIGNED_DI_OP
25636 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
25639 #undef TARGET_ASM_UNALIGNED_HI_OP
25640 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
25641 #undef TARGET_ASM_UNALIGNED_SI_OP
25642 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
25643 #undef TARGET_ASM_UNALIGNED_DI_OP
25644 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
25646 #undef TARGET_SCHED_ADJUST_COST
25647 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
25648 #undef TARGET_SCHED_ISSUE_RATE
25649 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
25650 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
25651 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
25652 ia32_multipass_dfa_lookahead
25654 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
25655 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
25658 #undef TARGET_HAVE_TLS
25659 #define TARGET_HAVE_TLS true
25661 #undef TARGET_CANNOT_FORCE_CONST_MEM
25662 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
25663 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
25664 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
25666 #undef TARGET_DELEGITIMIZE_ADDRESS
25667 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
25669 #undef TARGET_MS_BITFIELD_LAYOUT_P
25670 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
25673 #undef TARGET_BINDS_LOCAL_P
25674 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
25676 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
25677 #undef TARGET_BINDS_LOCAL_P
25678 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
25681 #undef TARGET_ASM_OUTPUT_MI_THUNK
25682 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
25683 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
25684 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
25686 #undef TARGET_ASM_FILE_START
25687 #define TARGET_ASM_FILE_START x86_file_start
25689 #undef TARGET_DEFAULT_TARGET_FLAGS
25690 #define TARGET_DEFAULT_TARGET_FLAGS \
25692 | TARGET_SUBTARGET_DEFAULT \
25693 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
25695 #undef TARGET_HANDLE_OPTION
25696 #define TARGET_HANDLE_OPTION ix86_handle_option
25698 #undef TARGET_RTX_COSTS
25699 #define TARGET_RTX_COSTS ix86_rtx_costs
25700 #undef TARGET_ADDRESS_COST
25701 #define TARGET_ADDRESS_COST ix86_address_cost
25703 #undef TARGET_FIXED_CONDITION_CODE_REGS
25704 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
25705 #undef TARGET_CC_MODES_COMPATIBLE
25706 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
25708 #undef TARGET_MACHINE_DEPENDENT_REORG
25709 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
25711 #undef TARGET_BUILD_BUILTIN_VA_LIST
25712 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
25714 #undef TARGET_EXPAND_BUILTIN_VA_START
25715 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
25717 #undef TARGET_MD_ASM_CLOBBERS
25718 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
25720 #undef TARGET_PROMOTE_PROTOTYPES
25721 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
25722 #undef TARGET_STRUCT_VALUE_RTX
25723 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
25724 #undef TARGET_SETUP_INCOMING_VARARGS
25725 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
25726 #undef TARGET_MUST_PASS_IN_STACK
25727 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
25728 #undef TARGET_PASS_BY_REFERENCE
25729 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
25730 #undef TARGET_INTERNAL_ARG_POINTER
25731 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
25732 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
25733 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
25734 #undef TARGET_STRICT_ARGUMENT_NAMING
25735 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
25737 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
25738 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
25740 #undef TARGET_SCALAR_MODE_SUPPORTED_P
25741 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
25743 #undef TARGET_VECTOR_MODE_SUPPORTED_P
25744 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
25746 #undef TARGET_C_MODE_FOR_SUFFIX
25747 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
25750 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
25751 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
25754 #ifdef SUBTARGET_INSERT_ATTRIBUTES
25755 #undef TARGET_INSERT_ATTRIBUTES
25756 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
25759 #undef TARGET_MANGLE_TYPE
25760 #define TARGET_MANGLE_TYPE ix86_mangle_type
25762 #undef TARGET_STACK_PROTECT_FAIL
25763 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
25765 #undef TARGET_FUNCTION_VALUE
25766 #define TARGET_FUNCTION_VALUE ix86_function_value
25768 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
25769 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
25771 struct gcc_target targetm = TARGET_INITIALIZER;
25773 #include "gt-i386.h"
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