1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs size_cost = { /* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of loading integer registers */
995 2, /* cost of moving MMX register */
996 {6, 6}, /* cost of loading MMX registers
997 in SImode and DImode */
998 {4, 4}, /* cost of storing MMX registers
999 in SImode and DImode */
1000 2, /* cost of moving SSE register */
1001 {6, 6, 6}, /* cost of loading SSE registers
1002 in SImode, DImode and TImode */
1003 {4, 4, 4}, /* cost of storing SSE registers
1004 in SImode, DImode and TImode */
1005 2, /* MMX or SSE register to integer */
1006 32, /* size of l1 cache. */
1007 2048, /* size of l2 cache. */
1008 128, /* size of prefetch block */
1009 8, /* number of parallel prefetches */
1010 3, /* Branch cost */
1011 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1012 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1013 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1014 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1015 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1016 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1017 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1018 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1019 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1020 {{libcall, {{8, loop}, {15, unrolled_loop},
1021 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1022 {libcall, {{24, loop}, {32, unrolled_loop},
1023 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1024 1, /* scalar_stmt_cost. */
1025 1, /* scalar load_cost. */
1026 1, /* scalar_store_cost. */
1027 1, /* vec_stmt_cost. */
1028 1, /* vec_to_scalar_cost. */
1029 1, /* scalar_to_vec_cost. */
1030 1, /* vec_align_load_cost. */
1031 2, /* vec_unalign_load_cost. */
1032 1, /* vec_store_cost. */
1033 3, /* cond_taken_branch_cost. */
1034 1, /* cond_not_taken_branch_cost. */
1037 /* Generic64 should produce code tuned for Nocona and K8. */
1039 struct processor_costs generic64_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 /* On all chips taken into consideration lea is 2 cycles and more. With
1042 this cost however our current implementation of synth_mult results in
1043 use of unnecessary temporary registers causing regression on several
1044 SPECfp benchmarks. */
1045 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1046 COSTS_N_INSNS (1), /* variable shift costs */
1047 COSTS_N_INSNS (1), /* constant shift costs */
1048 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1049 COSTS_N_INSNS (4), /* HI */
1050 COSTS_N_INSNS (3), /* SI */
1051 COSTS_N_INSNS (4), /* DI */
1052 COSTS_N_INSNS (2)}, /* other */
1053 0, /* cost of multiply per each bit set */
1054 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1055 COSTS_N_INSNS (26), /* HI */
1056 COSTS_N_INSNS (42), /* SI */
1057 COSTS_N_INSNS (74), /* DI */
1058 COSTS_N_INSNS (74)}, /* other */
1059 COSTS_N_INSNS (1), /* cost of movsx */
1060 COSTS_N_INSNS (1), /* cost of movzx */
1061 8, /* "large" insn */
1062 17, /* MOVE_RATIO */
1063 4, /* cost for loading QImode using movzbl */
1064 {4, 4, 4}, /* cost of loading integer registers
1065 in QImode, HImode and SImode.
1066 Relative to reg-reg move (2). */
1067 {4, 4, 4}, /* cost of storing integer registers */
1068 4, /* cost of reg,reg fld/fst */
1069 {12, 12, 12}, /* cost of loading fp registers
1070 in SFmode, DFmode and XFmode */
1071 {6, 6, 8}, /* cost of storing fp registers
1072 in SFmode, DFmode and XFmode */
1073 2, /* cost of moving MMX register */
1074 {8, 8}, /* cost of loading MMX registers
1075 in SImode and DImode */
1076 {8, 8}, /* cost of storing MMX registers
1077 in SImode and DImode */
1078 2, /* cost of moving SSE register */
1079 {8, 8, 8}, /* cost of loading SSE registers
1080 in SImode, DImode and TImode */
1081 {8, 8, 8}, /* cost of storing SSE registers
1082 in SImode, DImode and TImode */
1083 5, /* MMX or SSE register to integer */
1084 32, /* size of l1 cache. */
1085 512, /* size of l2 cache. */
1086 64, /* size of prefetch block */
1087 6, /* number of parallel prefetches */
1088 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1089 is increased to perhaps more appropriate value of 5. */
1090 3, /* Branch cost */
1091 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1092 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1093 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1094 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1095 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1096 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1097 {DUMMY_STRINGOP_ALGS,
1098 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 1, /* scalar_stmt_cost. */
1102 1, /* scalar load_cost. */
1103 1, /* scalar_store_cost. */
1104 1, /* vec_stmt_cost. */
1105 1, /* vec_to_scalar_cost. */
1106 1, /* scalar_to_vec_cost. */
1107 1, /* vec_align_load_cost. */
1108 2, /* vec_unalign_load_cost. */
1109 1, /* vec_store_cost. */
1110 3, /* cond_taken_branch_cost. */
1111 1, /* cond_not_taken_branch_cost. */
1114 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1116 struct processor_costs generic32_cost = {
1117 COSTS_N_INSNS (1), /* cost of an add instruction */
1118 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1119 COSTS_N_INSNS (1), /* variable shift costs */
1120 COSTS_N_INSNS (1), /* constant shift costs */
1121 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1122 COSTS_N_INSNS (4), /* HI */
1123 COSTS_N_INSNS (3), /* SI */
1124 COSTS_N_INSNS (4), /* DI */
1125 COSTS_N_INSNS (2)}, /* other */
1126 0, /* cost of multiply per each bit set */
1127 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1128 COSTS_N_INSNS (26), /* HI */
1129 COSTS_N_INSNS (42), /* SI */
1130 COSTS_N_INSNS (74), /* DI */
1131 COSTS_N_INSNS (74)}, /* other */
1132 COSTS_N_INSNS (1), /* cost of movsx */
1133 COSTS_N_INSNS (1), /* cost of movzx */
1134 8, /* "large" insn */
1135 17, /* MOVE_RATIO */
1136 4, /* cost for loading QImode using movzbl */
1137 {4, 4, 4}, /* cost of loading integer registers
1138 in QImode, HImode and SImode.
1139 Relative to reg-reg move (2). */
1140 {4, 4, 4}, /* cost of storing integer registers */
1141 4, /* cost of reg,reg fld/fst */
1142 {12, 12, 12}, /* cost of loading fp registers
1143 in SFmode, DFmode and XFmode */
1144 {6, 6, 8}, /* cost of storing fp registers
1145 in SFmode, DFmode and XFmode */
1146 2, /* cost of moving MMX register */
1147 {8, 8}, /* cost of loading MMX registers
1148 in SImode and DImode */
1149 {8, 8}, /* cost of storing MMX registers
1150 in SImode and DImode */
1151 2, /* cost of moving SSE register */
1152 {8, 8, 8}, /* cost of loading SSE registers
1153 in SImode, DImode and TImode */
1154 {8, 8, 8}, /* cost of storing SSE registers
1155 in SImode, DImode and TImode */
1156 5, /* MMX or SSE register to integer */
1157 32, /* size of l1 cache. */
1158 256, /* size of l2 cache. */
1159 64, /* size of prefetch block */
1160 6, /* number of parallel prefetches */
1161 3, /* Branch cost */
1162 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1163 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1164 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1165 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1166 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1167 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1168 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1169 DUMMY_STRINGOP_ALGS},
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 1, /* scalar_stmt_cost. */
1173 1, /* scalar load_cost. */
1174 1, /* scalar_store_cost. */
1175 1, /* vec_stmt_cost. */
1176 1, /* vec_to_scalar_cost. */
1177 1, /* scalar_to_vec_cost. */
1178 1, /* vec_align_load_cost. */
1179 2, /* vec_unalign_load_cost. */
1180 1, /* vec_store_cost. */
1181 3, /* cond_taken_branch_cost. */
1182 1, /* cond_not_taken_branch_cost. */
1185 const struct processor_costs *ix86_cost = &pentium_cost;
1187 /* Processor feature/optimization bitmasks. */
1188 #define m_386 (1<<PROCESSOR_I386)
1189 #define m_486 (1<<PROCESSOR_I486)
1190 #define m_PENT (1<<PROCESSOR_PENTIUM)
1191 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1192 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1193 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1194 #define m_CORE2 (1<<PROCESSOR_CORE2)
1196 #define m_GEODE (1<<PROCESSOR_GEODE)
1197 #define m_K6 (1<<PROCESSOR_K6)
1198 #define m_K6_GEODE (m_K6 | m_GEODE)
1199 #define m_K8 (1<<PROCESSOR_K8)
1200 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1201 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1202 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1203 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1205 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1206 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1208 /* Generic instruction choice should be common subset of supported CPUs
1209 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1210 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1212 /* Feature tests against the various tunings. */
1213 unsigned char ix86_tune_features[X86_TUNE_LAST];
1215 /* Feature tests against the various tunings used to create ix86_tune_features
1216 based on the processor mask. */
1217 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1218 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1219 negatively, so enabling for Generic64 seems like good code size
1220 tradeoff. We can't enable it for 32bit generic because it does not
1221 work well with PPro base chips. */
1222 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1224 /* X86_TUNE_PUSH_MEMORY */
1225 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1226 | m_NOCONA | m_CORE2 | m_GENERIC,
1228 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1231 /* X86_TUNE_USE_BIT_TEST */
1234 /* X86_TUNE_UNROLL_STRLEN */
1235 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1237 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1238 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1240 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1241 on simulation result. But after P4 was made, no performance benefit
1242 was observed with branch hints. It also increases the code size.
1243 As a result, icc never generates branch hints. */
1246 /* X86_TUNE_DOUBLE_WITH_ADD */
1249 /* X86_TUNE_USE_SAHF */
1250 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1251 | m_NOCONA | m_CORE2 | m_GENERIC,
1253 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1254 partial dependencies. */
1255 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1256 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1258 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1259 register stalls on Generic32 compilation setting as well. However
1260 in current implementation the partial register stalls are not eliminated
1261 very well - they can be introduced via subregs synthesized by combine
1262 and can happen in caller/callee saving sequences. Because this option
1263 pays back little on PPro based chips and is in conflict with partial reg
1264 dependencies used by Athlon/P4 based chips, it is better to leave it off
1265 for generic32 for now. */
1268 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1269 m_CORE2 | m_GENERIC,
1271 /* X86_TUNE_USE_HIMODE_FIOP */
1272 m_386 | m_486 | m_K6_GEODE,
1274 /* X86_TUNE_USE_SIMODE_FIOP */
1275 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1277 /* X86_TUNE_USE_MOV0 */
1280 /* X86_TUNE_USE_CLTD */
1281 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1283 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1286 /* X86_TUNE_SPLIT_LONG_MOVES */
1289 /* X86_TUNE_READ_MODIFY_WRITE */
1292 /* X86_TUNE_READ_MODIFY */
1295 /* X86_TUNE_PROMOTE_QIMODE */
1296 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1297 | m_GENERIC /* | m_PENT4 ? */,
1299 /* X86_TUNE_FAST_PREFIX */
1300 ~(m_PENT | m_486 | m_386),
1302 /* X86_TUNE_SINGLE_STRINGOP */
1303 m_386 | m_PENT4 | m_NOCONA,
1305 /* X86_TUNE_QIMODE_MATH */
1308 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1309 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1310 might be considered for Generic32 if our scheme for avoiding partial
1311 stalls was more effective. */
1314 /* X86_TUNE_PROMOTE_QI_REGS */
1317 /* X86_TUNE_PROMOTE_HI_REGS */
1320 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1321 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1323 /* X86_TUNE_ADD_ESP_8 */
1324 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1325 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1327 /* X86_TUNE_SUB_ESP_4 */
1328 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1330 /* X86_TUNE_SUB_ESP_8 */
1331 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1332 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1334 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1335 for DFmode copies */
1336 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1337 | m_GENERIC | m_GEODE),
1339 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1340 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1342 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1343 conflict here in between PPro/Pentium4 based chips that thread 128bit
1344 SSE registers as single units versus K8 based chips that divide SSE
1345 registers to two 64bit halves. This knob promotes all store destinations
1346 to be 128bit to allow register renaming on 128bit SSE units, but usually
1347 results in one extra microop on 64bit SSE units. Experimental results
1348 shows that disabling this option on P4 brings over 20% SPECfp regression,
1349 while enabling it on K8 brings roughly 2.4% regression that can be partly
1350 masked by careful scheduling of moves. */
1351 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1353 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1356 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1357 are resolved on SSE register parts instead of whole registers, so we may
1358 maintain just lower part of scalar values in proper format leaving the
1359 upper part undefined. */
1362 /* X86_TUNE_SSE_TYPELESS_STORES */
1365 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1366 m_PPRO | m_PENT4 | m_NOCONA,
1368 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1369 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1371 /* X86_TUNE_PROLOGUE_USING_MOVE */
1372 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1374 /* X86_TUNE_EPILOGUE_USING_MOVE */
1375 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1377 /* X86_TUNE_SHIFT1 */
1380 /* X86_TUNE_USE_FFREEP */
1383 /* X86_TUNE_INTER_UNIT_MOVES */
1384 ~(m_AMD_MULTIPLE | m_GENERIC),
1386 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1389 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1390 than 4 branch instructions in the 16 byte window. */
1391 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1393 /* X86_TUNE_SCHEDULE */
1394 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1396 /* X86_TUNE_USE_BT */
1397 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1399 /* X86_TUNE_USE_INCDEC */
1400 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1402 /* X86_TUNE_PAD_RETURNS */
1403 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1405 /* X86_TUNE_EXT_80387_CONSTANTS */
1406 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1408 /* X86_TUNE_SHORTEN_X87_SSE */
1411 /* X86_TUNE_AVOID_VECTOR_DECODE */
1414 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1415 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1418 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1419 vector path on AMD machines. */
1420 m_K8 | m_GENERIC64 | m_AMDFAM10,
1422 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1424 m_K8 | m_GENERIC64 | m_AMDFAM10,
1426 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1430 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1431 but one byte longer. */
1434 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1435 operand that cannot be represented using a modRM byte. The XOR
1436 replacement is long decoded, so this split helps here as well. */
1439 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1440 from integer to FP. */
1443 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1444 with a subsequent conditional jump instruction into a single
1445 compare-and-branch uop. */
1449 /* Feature tests against the various architecture variations. */
1450 unsigned char ix86_arch_features[X86_ARCH_LAST];
1452 /* Feature tests against the various architecture variations, used to create
1453 ix86_arch_features based on the processor mask. */
1454 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1455 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1456 ~(m_386 | m_486 | m_PENT | m_K6),
1458 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1461 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1464 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1467 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1471 static const unsigned int x86_accumulate_outgoing_args
1472 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1474 static const unsigned int x86_arch_always_fancy_math_387
1475 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1476 | m_NOCONA | m_CORE2 | m_GENERIC;
1478 static enum stringop_alg stringop_alg = no_stringop;
1480 /* In case the average insn count for single function invocation is
1481 lower than this constant, emit fast (but longer) prologue and
1483 #define FAST_PROLOGUE_INSN_COUNT 20
1485 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1486 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1487 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1488 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1490 /* Array of the smallest class containing reg number REGNO, indexed by
1491 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1493 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1495 /* ax, dx, cx, bx */
1496 AREG, DREG, CREG, BREG,
1497 /* si, di, bp, sp */
1498 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1500 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1501 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1504 /* flags, fpsr, fpcr, frame */
1505 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1507 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1510 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1513 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1514 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1515 /* SSE REX registers */
1516 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1520 /* The "default" register map used in 32bit mode. */
1522 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1524 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1525 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1526 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1527 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1528 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1529 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1530 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1533 static int const x86_64_int_parameter_registers[6] =
1535 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1536 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1539 static int const x86_64_ms_abi_int_parameter_registers[4] =
1541 2 /*RCX*/, 1 /*RDX*/,
1542 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1545 static int const x86_64_int_return_registers[4] =
1547 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1550 /* The "default" register map used in 64bit mode. */
1551 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1553 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1554 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1555 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1556 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1557 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1558 8,9,10,11,12,13,14,15, /* extended integer registers */
1559 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1562 /* Define the register numbers to be used in Dwarf debugging information.
1563 The SVR4 reference port C compiler uses the following register numbers
1564 in its Dwarf output code:
1565 0 for %eax (gcc regno = 0)
1566 1 for %ecx (gcc regno = 2)
1567 2 for %edx (gcc regno = 1)
1568 3 for %ebx (gcc regno = 3)
1569 4 for %esp (gcc regno = 7)
1570 5 for %ebp (gcc regno = 6)
1571 6 for %esi (gcc regno = 4)
1572 7 for %edi (gcc regno = 5)
1573 The following three DWARF register numbers are never generated by
1574 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1575 believes these numbers have these meanings.
1576 8 for %eip (no gcc equivalent)
1577 9 for %eflags (gcc regno = 17)
1578 10 for %trapno (no gcc equivalent)
1579 It is not at all clear how we should number the FP stack registers
1580 for the x86 architecture. If the version of SDB on x86/svr4 were
1581 a bit less brain dead with respect to floating-point then we would
1582 have a precedent to follow with respect to DWARF register numbers
1583 for x86 FP registers, but the SDB on x86/svr4 is so completely
1584 broken with respect to FP registers that it is hardly worth thinking
1585 of it as something to strive for compatibility with.
1586 The version of x86/svr4 SDB I have at the moment does (partially)
1587 seem to believe that DWARF register number 11 is associated with
1588 the x86 register %st(0), but that's about all. Higher DWARF
1589 register numbers don't seem to be associated with anything in
1590 particular, and even for DWARF regno 11, SDB only seems to under-
1591 stand that it should say that a variable lives in %st(0) (when
1592 asked via an `=' command) if we said it was in DWARF regno 11,
1593 but SDB still prints garbage when asked for the value of the
1594 variable in question (via a `/' command).
1595 (Also note that the labels SDB prints for various FP stack regs
1596 when doing an `x' command are all wrong.)
1597 Note that these problems generally don't affect the native SVR4
1598 C compiler because it doesn't allow the use of -O with -g and
1599 because when it is *not* optimizing, it allocates a memory
1600 location for each floating-point variable, and the memory
1601 location is what gets described in the DWARF AT_location
1602 attribute for the variable in question.
1603 Regardless of the severe mental illness of the x86/svr4 SDB, we
1604 do something sensible here and we use the following DWARF
1605 register numbers. Note that these are all stack-top-relative
1607 11 for %st(0) (gcc regno = 8)
1608 12 for %st(1) (gcc regno = 9)
1609 13 for %st(2) (gcc regno = 10)
1610 14 for %st(3) (gcc regno = 11)
1611 15 for %st(4) (gcc regno = 12)
1612 16 for %st(5) (gcc regno = 13)
1613 17 for %st(6) (gcc regno = 14)
1614 18 for %st(7) (gcc regno = 15)
1616 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1618 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1619 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1620 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1621 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1622 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1623 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1624 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1627 /* Test and compare insns in i386.md store the information needed to
1628 generate branch and scc insns here. */
1630 rtx ix86_compare_op0 = NULL_RTX;
1631 rtx ix86_compare_op1 = NULL_RTX;
1632 rtx ix86_compare_emitted = NULL_RTX;
1634 /* Size of the register save area. */
1635 #define X86_64_VARARGS_SIZE (X86_64_REGPARM_MAX * UNITS_PER_WORD + X86_64_SSE_REGPARM_MAX * 16)
1637 /* Define the structure for the machine field in struct function. */
1639 struct stack_local_entry GTY(())
1641 unsigned short mode;
1644 struct stack_local_entry *next;
1647 /* Structure describing stack frame layout.
1648 Stack grows downward:
1654 saved frame pointer if frame_pointer_needed
1655 <- HARD_FRAME_POINTER
1660 [va_arg registers] (
1661 > to_allocate <- FRAME_POINTER
1671 HOST_WIDE_INT frame;
1673 int outgoing_arguments_size;
1676 HOST_WIDE_INT to_allocate;
1677 /* The offsets relative to ARG_POINTER. */
1678 HOST_WIDE_INT frame_pointer_offset;
1679 HOST_WIDE_INT hard_frame_pointer_offset;
1680 HOST_WIDE_INT stack_pointer_offset;
1682 /* When save_regs_using_mov is set, emit prologue using
1683 move instead of push instructions. */
1684 bool save_regs_using_mov;
1687 /* Code model option. */
1688 enum cmodel ix86_cmodel;
1690 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1692 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1694 /* Which unit we are generating floating point math for. */
1695 enum fpmath_unit ix86_fpmath;
1697 /* Which cpu are we scheduling for. */
1698 enum processor_type ix86_tune;
1700 /* Which instruction set architecture to use. */
1701 enum processor_type ix86_arch;
1703 /* true if sse prefetch instruction is not NOOP. */
1704 int x86_prefetch_sse;
1706 /* ix86_regparm_string as a number */
1707 static int ix86_regparm;
1709 /* -mstackrealign option */
1710 extern int ix86_force_align_arg_pointer;
1711 static const char ix86_force_align_arg_pointer_string[]
1712 = "force_align_arg_pointer";
1714 static rtx (*ix86_gen_leave) (void);
1715 static rtx (*ix86_gen_pop1) (rtx);
1716 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1717 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1718 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1719 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1720 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1721 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1723 /* Preferred alignment for stack boundary in bits. */
1724 unsigned int ix86_preferred_stack_boundary;
1726 /* Alignment for incoming stack boundary in bits specified at
1728 static unsigned int ix86_user_incoming_stack_boundary;
1730 /* Default alignment for incoming stack boundary in bits. */
1731 static unsigned int ix86_default_incoming_stack_boundary;
1733 /* Alignment for incoming stack boundary in bits. */
1734 unsigned int ix86_incoming_stack_boundary;
1736 /* Values 1-5: see jump.c */
1737 int ix86_branch_cost;
1739 /* Calling abi specific va_list type nodes. */
1740 static GTY(()) tree sysv_va_list_type_node;
1741 static GTY(()) tree ms_va_list_type_node;
1743 /* Variables which are this size or smaller are put in the data/bss
1744 or ldata/lbss sections. */
1746 int ix86_section_threshold = 65536;
1748 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1749 char internal_label_prefix[16];
1750 int internal_label_prefix_len;
1752 /* Fence to use after loop using movnt. */
1755 /* Register class used for passing given 64bit part of the argument.
1756 These represent classes as documented by the PS ABI, with the exception
1757 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1758 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1760 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1761 whenever possible (upper half does contain padding). */
1762 enum x86_64_reg_class
1765 X86_64_INTEGER_CLASS,
1766 X86_64_INTEGERSI_CLASS,
1773 X86_64_COMPLEX_X87_CLASS,
1776 static const char * const x86_64_reg_class_name[] =
1778 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1779 "sseup", "x87", "x87up", "cplx87", "no"
1782 #define MAX_CLASSES 4
1784 /* Table of constants used by fldpi, fldln2, etc.... */
1785 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1786 static bool ext_80387_constants_init = 0;
1789 static struct machine_function * ix86_init_machine_status (void);
1790 static rtx ix86_function_value (const_tree, const_tree, bool);
1791 static int ix86_function_regparm (const_tree, const_tree);
1792 static void ix86_compute_frame_layout (struct ix86_frame *);
1793 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1796 enum ix86_function_specific_strings
1798 IX86_FUNCTION_SPECIFIC_ARCH,
1799 IX86_FUNCTION_SPECIFIC_TUNE,
1800 IX86_FUNCTION_SPECIFIC_FPMATH,
1801 IX86_FUNCTION_SPECIFIC_MAX
1804 static char *ix86_target_string (int, int, const char *, const char *,
1805 const char *, bool);
1806 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1807 static void ix86_function_specific_save (struct cl_target_option *);
1808 static void ix86_function_specific_restore (struct cl_target_option *);
1809 static void ix86_function_specific_print (FILE *, int,
1810 struct cl_target_option *);
1811 static bool ix86_valid_option_attribute_p (tree, tree, tree, int);
1812 static bool ix86_valid_option_attribute_inner_p (tree, char *[]);
1813 static bool ix86_can_inline_p (tree, tree);
1814 static void ix86_set_current_function (tree);
1817 /* The svr4 ABI for the i386 says that records and unions are returned
1819 #ifndef DEFAULT_PCC_STRUCT_RETURN
1820 #define DEFAULT_PCC_STRUCT_RETURN 1
1823 /* Whether -mtune= or -march= were specified */
1824 static int ix86_tune_defaulted;
1825 static int ix86_arch_specified;
1827 /* Bit flags that specify the ISA we are compiling for. */
1828 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1830 /* A mask of ix86_isa_flags that includes bit X if X
1831 was set or cleared on the command line. */
1832 static int ix86_isa_flags_explicit;
1834 /* Define a set of ISAs which are available when a given ISA is
1835 enabled. MMX and SSE ISAs are handled separately. */
1837 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1838 #define OPTION_MASK_ISA_3DNOW_SET \
1839 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1841 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1842 #define OPTION_MASK_ISA_SSE2_SET \
1843 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1844 #define OPTION_MASK_ISA_SSE3_SET \
1845 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1846 #define OPTION_MASK_ISA_SSSE3_SET \
1847 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1848 #define OPTION_MASK_ISA_SSE4_1_SET \
1849 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1850 #define OPTION_MASK_ISA_SSE4_2_SET \
1851 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1853 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1855 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1857 #define OPTION_MASK_ISA_SSE4A_SET \
1858 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1859 #define OPTION_MASK_ISA_SSE5_SET \
1860 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1862 /* AES and PCLMUL need SSE2 because they use xmm registers */
1863 #define OPTION_MASK_ISA_AES_SET \
1864 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1865 #define OPTION_MASK_ISA_PCLMUL_SET \
1866 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1868 #define OPTION_MASK_ISA_ABM_SET \
1869 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1870 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1871 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1872 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1874 /* Define a set of ISAs which aren't available when a given ISA is
1875 disabled. MMX and SSE ISAs are handled separately. */
1877 #define OPTION_MASK_ISA_MMX_UNSET \
1878 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1879 #define OPTION_MASK_ISA_3DNOW_UNSET \
1880 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1881 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1883 #define OPTION_MASK_ISA_SSE_UNSET \
1884 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1885 #define OPTION_MASK_ISA_SSE2_UNSET \
1886 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1887 #define OPTION_MASK_ISA_SSE3_UNSET \
1888 (OPTION_MASK_ISA_SSE3 \
1889 | OPTION_MASK_ISA_SSSE3_UNSET \
1890 | OPTION_MASK_ISA_SSE4A_UNSET )
1891 #define OPTION_MASK_ISA_SSSE3_UNSET \
1892 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1893 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1894 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1895 #define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4_2
1897 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1899 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1901 #define OPTION_MASK_ISA_SSE4A_UNSET \
1902 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1903 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1904 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1905 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1906 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1907 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1908 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1909 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1911 /* Vectorization library interface and handlers. */
1912 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1913 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1914 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1916 /* Processor target table, indexed by processor number */
1919 const struct processor_costs *cost; /* Processor costs */
1920 const int align_loop; /* Default alignments. */
1921 const int align_loop_max_skip;
1922 const int align_jump;
1923 const int align_jump_max_skip;
1924 const int align_func;
1927 static const struct ptt processor_target_table[PROCESSOR_max] =
1929 {&i386_cost, 4, 3, 4, 3, 4},
1930 {&i486_cost, 16, 15, 16, 15, 16},
1931 {&pentium_cost, 16, 7, 16, 7, 16},
1932 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1933 {&geode_cost, 0, 0, 0, 0, 0},
1934 {&k6_cost, 32, 7, 32, 7, 32},
1935 {&athlon_cost, 16, 7, 16, 7, 16},
1936 {&pentium4_cost, 0, 0, 0, 0, 0},
1937 {&k8_cost, 16, 7, 16, 7, 16},
1938 {&nocona_cost, 0, 0, 0, 0, 0},
1939 {&core2_cost, 16, 10, 16, 10, 16},
1940 {&generic32_cost, 16, 7, 16, 7, 16},
1941 {&generic64_cost, 16, 10, 16, 10, 16},
1942 {&amdfam10_cost, 32, 24, 32, 7, 32}
1945 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1970 /* Implement TARGET_HANDLE_OPTION. */
1973 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1980 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1981 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1985 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
1986 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
1993 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
1994 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
1998 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
1999 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2009 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2010 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2014 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2015 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2022 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2023 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2027 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2028 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2035 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2036 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2040 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2041 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2048 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2049 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2053 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2054 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2061 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2062 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2066 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2067 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2074 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2075 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2079 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2080 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2085 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2086 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2090 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2091 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2097 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2098 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2102 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2103 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2110 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2111 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2115 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2116 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2123 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2124 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2128 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2129 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2136 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2137 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2141 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2142 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2149 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2150 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2154 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2155 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2162 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2163 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2167 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2168 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2175 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2176 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2180 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2181 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2188 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2189 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2193 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2194 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2203 /* Return a string the documents the current -m options. The caller is
2204 responsible for freeing the string. */
2207 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2208 const char *fpmath, bool add_nl_p)
2210 struct ix86_target_opts
2212 const char *option; /* option string */
2213 int mask; /* isa mask options */
2216 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2217 preceding options while match those first. */
2218 static struct ix86_target_opts isa_opts[] =
2220 { "-m64", OPTION_MASK_ISA_64BIT },
2221 { "-msse5", OPTION_MASK_ISA_SSE5 },
2222 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2223 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2224 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2225 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2226 { "-msse3", OPTION_MASK_ISA_SSE3 },
2227 { "-msse2", OPTION_MASK_ISA_SSE2 },
2228 { "-msse", OPTION_MASK_ISA_SSE },
2229 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2230 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2231 { "-mmmx", OPTION_MASK_ISA_MMX },
2232 { "-mabm", OPTION_MASK_ISA_ABM },
2233 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2234 { "-maes", OPTION_MASK_ISA_AES },
2235 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2239 static struct ix86_target_opts flag_opts[] =
2241 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2242 { "-m80387", MASK_80387 },
2243 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2244 { "-malign-double", MASK_ALIGN_DOUBLE },
2245 { "-mcld", MASK_CLD },
2246 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2247 { "-mieee-fp", MASK_IEEE_FP },
2248 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2249 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2250 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2251 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2252 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2253 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2254 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2255 { "-mno-red-zone", MASK_NO_RED_ZONE },
2256 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2257 { "-mrecip", MASK_RECIP },
2258 { "-mrtd", MASK_RTD },
2259 { "-msseregparm", MASK_SSEREGPARM },
2260 { "-mstack-arg-probe", MASK_STACK_PROBE },
2261 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2264 const char *opts[ (sizeof (isa_opts) / sizeof (isa_opts[0])
2265 + sizeof (flag_opts) / sizeof (flag_opts[0])
2269 char target_other[40];
2278 memset (opts, '\0', sizeof (opts));
2280 /* Add -march= option. */
2283 opts[num][0] = "-march=";
2284 opts[num++][1] = arch;
2287 /* Add -mtune= option. */
2290 opts[num][0] = "-mtune=";
2291 opts[num++][1] = tune;
2294 /* Pick out the options in isa options. */
2295 for (i = 0; i < sizeof (isa_opts) / sizeof (isa_opts[0]); i++)
2297 if ((isa & isa_opts[i].mask) != 0)
2299 opts[num++][0] = isa_opts[i].option;
2300 isa &= ~ isa_opts[i].mask;
2304 if (isa && add_nl_p)
2306 opts[num++][0] = isa_other;
2307 sprintf (isa_other, "(other isa: 0x%x)", isa);
2310 /* Add flag options. */
2311 for (i = 0; i < sizeof (flag_opts) / sizeof (flag_opts[0]); i++)
2313 if ((flags & flag_opts[i].mask) != 0)
2315 opts[num++][0] = flag_opts[i].option;
2316 flags &= ~ flag_opts[i].mask;
2320 if (flags && add_nl_p)
2322 opts[num++][0] = target_other;
2323 sprintf (target_other, "(other flags: 0x%x)", isa);
2326 /* Add -fpmath= option. */
2329 opts[num][0] = "-mfpmath=";
2330 opts[num++][1] = fpmath;
2337 gcc_assert (num < sizeof (opts) / sizeof (opts[0]));
2339 /* Size the string. */
2341 sep_len = (add_nl_p) ? 3 : 1;
2342 for (i = 0; i < num; i++)
2345 for (j = 0; j < 2; j++)
2347 len += strlen (opts[i][j]);
2350 /* Build the string. */
2351 ret = ptr = (char *) xmalloc (len);
2354 for (i = 0; i < num; i++)
2358 for (j = 0; j < 2; j++)
2359 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2366 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2374 for (j = 0; j < 2; j++)
2377 memcpy (ptr, opts[i][j], len2[j]);
2379 line_len += len2[j];
2384 gcc_assert (ret + len >= ptr);
2389 /* Function that is callable from the debugger to print the current
2392 ix86_debug_options (void)
2394 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2395 ix86_arch_string, ix86_tune_string,
2396 ix86_fpmath_string, true);
2400 fprintf (stderr, "%s\n\n", opts);
2404 fprintf (stderr, "<no options>\n\n");
2409 /* Sometimes certain combinations of command options do not make
2410 sense on a particular target machine. You can define a macro
2411 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2412 defined, is executed once just after all the command options have
2415 Don't use this macro to turn on various extra optimizations for
2416 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2419 override_options (bool main_args_p)
2422 unsigned int ix86_arch_mask, ix86_tune_mask;
2427 /* Comes from final.c -- no real reason to change it. */
2428 #define MAX_CODE_ALIGN 16
2436 PTA_PREFETCH_SSE = 1 << 4,
2438 PTA_3DNOW_A = 1 << 6,
2442 PTA_POPCNT = 1 << 10,
2444 PTA_SSE4A = 1 << 12,
2445 PTA_NO_SAHF = 1 << 13,
2446 PTA_SSE4_1 = 1 << 14,
2447 PTA_SSE4_2 = 1 << 15,
2450 PTA_PCLMUL = 1 << 18
2455 const char *const name; /* processor name or nickname. */
2456 const enum processor_type processor;
2457 const unsigned /*enum pta_flags*/ flags;
2459 const processor_alias_table[] =
2461 {"i386", PROCESSOR_I386, 0},
2462 {"i486", PROCESSOR_I486, 0},
2463 {"i586", PROCESSOR_PENTIUM, 0},
2464 {"pentium", PROCESSOR_PENTIUM, 0},
2465 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
2466 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
2467 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2468 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
2469 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2470 {"i686", PROCESSOR_PENTIUMPRO, 0},
2471 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
2472 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
2473 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2474 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE},
2475 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_SSE2},
2476 {"pentium4", PROCESSOR_PENTIUM4, PTA_MMX |PTA_SSE | PTA_SSE2},
2477 {"pentium4m", PROCESSOR_PENTIUM4, PTA_MMX | PTA_SSE | PTA_SSE2},
2478 {"prescott", PROCESSOR_NOCONA, PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2479 {"nocona", PROCESSOR_NOCONA, (PTA_64BIT
2480 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2481 | PTA_CX16 | PTA_NO_SAHF)},
2482 {"core2", PROCESSOR_CORE2, (PTA_64BIT
2483 | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2486 {"geode", PROCESSOR_GEODE, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2487 |PTA_PREFETCH_SSE)},
2488 {"k6", PROCESSOR_K6, PTA_MMX},
2489 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2490 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
2491 {"athlon", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2492 | PTA_PREFETCH_SSE)},
2493 {"athlon-tbird", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2494 | PTA_PREFETCH_SSE)},
2495 {"athlon-4", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2497 {"athlon-xp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2499 {"athlon-mp", PROCESSOR_ATHLON, (PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2501 {"x86-64", PROCESSOR_K8, (PTA_64BIT
2502 | PTA_MMX | PTA_SSE | PTA_SSE2
2504 {"k8", PROCESSOR_K8, (PTA_64BIT
2505 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2506 | PTA_SSE | PTA_SSE2
2508 {"k8-sse3", PROCESSOR_K8, (PTA_64BIT
2509 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2510 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2512 {"opteron", PROCESSOR_K8, (PTA_64BIT
2513 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2514 | PTA_SSE | PTA_SSE2
2516 {"opteron-sse3", PROCESSOR_K8, (PTA_64BIT
2517 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2518 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2520 {"athlon64", PROCESSOR_K8, (PTA_64BIT
2521 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2522 | PTA_SSE | PTA_SSE2
2524 {"athlon64-sse3", PROCESSOR_K8, (PTA_64BIT
2525 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2526 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2528 {"athlon-fx", PROCESSOR_K8, (PTA_64BIT
2529 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2530 | PTA_SSE | PTA_SSE2
2532 {"amdfam10", PROCESSOR_AMDFAM10, (PTA_64BIT
2533 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2534 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2536 | PTA_CX16 | PTA_ABM)},
2537 {"barcelona", PROCESSOR_AMDFAM10, (PTA_64BIT
2538 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A
2539 | PTA_SSE | PTA_SSE2 | PTA_SSE3
2541 | PTA_CX16 | PTA_ABM)},
2542 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
2543 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
2546 int const pta_size = ARRAY_SIZE (processor_alias_table);
2548 /* Set up prefix/suffix so the error messages refer to either the command
2549 line argument, or the attribute(option). */
2558 prefix = "option(\"";
2563 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2564 SUBTARGET_OVERRIDE_OPTIONS;
2567 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2568 SUBSUBTARGET_OVERRIDE_OPTIONS;
2571 /* -fPIC is the default for x86_64. */
2572 if (TARGET_MACHO && TARGET_64BIT)
2575 /* Set the default values for switches whose default depends on TARGET_64BIT
2576 in case they weren't overwritten by command line options. */
2579 /* Mach-O doesn't support omitting the frame pointer for now. */
2580 if (flag_omit_frame_pointer == 2)
2581 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2582 if (flag_asynchronous_unwind_tables == 2)
2583 flag_asynchronous_unwind_tables = 1;
2584 if (flag_pcc_struct_return == 2)
2585 flag_pcc_struct_return = 0;
2589 if (flag_omit_frame_pointer == 2)
2590 flag_omit_frame_pointer = 0;
2591 if (flag_asynchronous_unwind_tables == 2)
2592 flag_asynchronous_unwind_tables = 0;
2593 if (flag_pcc_struct_return == 2)
2594 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2597 /* Need to check -mtune=generic first. */
2598 if (ix86_tune_string)
2600 if (!strcmp (ix86_tune_string, "generic")
2601 || !strcmp (ix86_tune_string, "i686")
2602 /* As special support for cross compilers we read -mtune=native
2603 as -mtune=generic. With native compilers we won't see the
2604 -mtune=native, as it was changed by the driver. */
2605 || !strcmp (ix86_tune_string, "native"))
2608 ix86_tune_string = "generic64";
2610 ix86_tune_string = "generic32";
2612 /* If this call is for setting the option attribute, allow the
2613 generic32/generic64 that was previously set. */
2614 else if (!main_args_p
2615 && (!strcmp (ix86_tune_string, "generic32")
2616 || !strcmp (ix86_tune_string, "generic64")))
2618 else if (!strncmp (ix86_tune_string, "generic", 7))
2619 error ("bad value (%s) for %stune=%s %s",
2620 ix86_tune_string, prefix, suffix, sw);
2624 if (ix86_arch_string)
2625 ix86_tune_string = ix86_arch_string;
2626 if (!ix86_tune_string)
2628 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2629 ix86_tune_defaulted = 1;
2632 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2633 need to use a sensible tune option. */
2634 if (!strcmp (ix86_tune_string, "generic")
2635 || !strcmp (ix86_tune_string, "x86-64")
2636 || !strcmp (ix86_tune_string, "i686"))
2639 ix86_tune_string = "generic64";
2641 ix86_tune_string = "generic32";
2644 if (ix86_stringop_string)
2646 if (!strcmp (ix86_stringop_string, "rep_byte"))
2647 stringop_alg = rep_prefix_1_byte;
2648 else if (!strcmp (ix86_stringop_string, "libcall"))
2649 stringop_alg = libcall;
2650 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2651 stringop_alg = rep_prefix_4_byte;
2652 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
2653 stringop_alg = rep_prefix_8_byte;
2654 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2655 stringop_alg = loop_1_byte;
2656 else if (!strcmp (ix86_stringop_string, "loop"))
2657 stringop_alg = loop;
2658 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2659 stringop_alg = unrolled_loop;
2661 error ("bad value (%s) for %sstringop-strategy=%s %s",
2662 ix86_stringop_string, prefix, suffix, sw);
2664 if (!strcmp (ix86_tune_string, "x86-64"))
2665 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2666 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2667 prefix, suffix, prefix, suffix, prefix, suffix);
2669 if (!ix86_arch_string)
2670 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2672 ix86_arch_specified = 1;
2674 if (!strcmp (ix86_arch_string, "generic"))
2675 error ("generic CPU can be used only for %stune=%s %s",
2676 prefix, suffix, sw);
2677 if (!strncmp (ix86_arch_string, "generic", 7))
2678 error ("bad value (%s) for %sarch=%s %s",
2679 ix86_arch_string, prefix, suffix, sw);
2681 if (ix86_cmodel_string != 0)
2683 if (!strcmp (ix86_cmodel_string, "small"))
2684 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2685 else if (!strcmp (ix86_cmodel_string, "medium"))
2686 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2687 else if (!strcmp (ix86_cmodel_string, "large"))
2688 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2690 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2691 else if (!strcmp (ix86_cmodel_string, "32"))
2692 ix86_cmodel = CM_32;
2693 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2694 ix86_cmodel = CM_KERNEL;
2696 error ("bad value (%s) for %scmodel=%s %s",
2697 ix86_cmodel_string, prefix, suffix, sw);
2701 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2702 use of rip-relative addressing. This eliminates fixups that
2703 would otherwise be needed if this object is to be placed in a
2704 DLL, and is essentially just as efficient as direct addressing. */
2705 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2706 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2707 else if (TARGET_64BIT)
2708 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2710 ix86_cmodel = CM_32;
2712 if (ix86_asm_string != 0)
2715 && !strcmp (ix86_asm_string, "intel"))
2716 ix86_asm_dialect = ASM_INTEL;
2717 else if (!strcmp (ix86_asm_string, "att"))
2718 ix86_asm_dialect = ASM_ATT;
2720 error ("bad value (%s) for %sasm=%s %s",
2721 ix86_asm_string, prefix, suffix, sw);
2723 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2724 error ("code model %qs not supported in the %s bit mode",
2725 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2726 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2727 sorry ("%i-bit mode not compiled in",
2728 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2730 for (i = 0; i < pta_size; i++)
2731 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2733 ix86_arch = processor_alias_table[i].processor;
2734 /* Default cpu tuning to the architecture. */
2735 ix86_tune = ix86_arch;
2737 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2738 error ("CPU you selected does not support x86-64 "
2741 if (processor_alias_table[i].flags & PTA_MMX
2742 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2743 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2744 if (processor_alias_table[i].flags & PTA_3DNOW
2745 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2746 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2747 if (processor_alias_table[i].flags & PTA_3DNOW_A
2748 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2749 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2750 if (processor_alias_table[i].flags & PTA_SSE
2751 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2752 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2753 if (processor_alias_table[i].flags & PTA_SSE2
2754 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2755 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2756 if (processor_alias_table[i].flags & PTA_SSE3
2757 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2758 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2759 if (processor_alias_table[i].flags & PTA_SSSE3
2760 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2761 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2762 if (processor_alias_table[i].flags & PTA_SSE4_1
2763 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2764 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2765 if (processor_alias_table[i].flags & PTA_SSE4_2
2766 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2767 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2768 if (processor_alias_table[i].flags & PTA_SSE4A
2769 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2770 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2771 if (processor_alias_table[i].flags & PTA_SSE5
2772 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2773 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2774 if (processor_alias_table[i].flags & PTA_ABM
2775 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2776 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2777 if (processor_alias_table[i].flags & PTA_CX16
2778 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2779 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2780 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2781 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2782 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2783 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2784 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2785 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2786 if (processor_alias_table[i].flags & PTA_AES
2787 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2788 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2789 if (processor_alias_table[i].flags & PTA_PCLMUL
2790 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2791 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2792 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2793 x86_prefetch_sse = true;
2799 error ("bad value (%s) for %sarch=%s %s",
2800 ix86_arch_string, prefix, suffix, sw);
2802 ix86_arch_mask = 1u << ix86_arch;
2803 for (i = 0; i < X86_ARCH_LAST; ++i)
2804 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2806 for (i = 0; i < pta_size; i++)
2807 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2809 ix86_tune = processor_alias_table[i].processor;
2810 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2812 if (ix86_tune_defaulted)
2814 ix86_tune_string = "x86-64";
2815 for (i = 0; i < pta_size; i++)
2816 if (! strcmp (ix86_tune_string,
2817 processor_alias_table[i].name))
2819 ix86_tune = processor_alias_table[i].processor;
2822 error ("CPU you selected does not support x86-64 "
2825 /* Intel CPUs have always interpreted SSE prefetch instructions as
2826 NOPs; so, we can enable SSE prefetch instructions even when
2827 -mtune (rather than -march) points us to a processor that has them.
2828 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2829 higher processors. */
2831 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2832 x86_prefetch_sse = true;
2836 error ("bad value (%s) for %stune=%s %s",
2837 ix86_tune_string, prefix, suffix, sw);
2839 ix86_tune_mask = 1u << ix86_tune;
2840 for (i = 0; i < X86_TUNE_LAST; ++i)
2841 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
2844 ix86_cost = &size_cost;
2846 ix86_cost = processor_target_table[ix86_tune].cost;
2848 /* Arrange to set up i386_stack_locals for all functions. */
2849 init_machine_status = ix86_init_machine_status;
2851 /* Validate -mregparm= value. */
2852 if (ix86_regparm_string)
2855 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
2856 i = atoi (ix86_regparm_string);
2857 if (i < 0 || i > REGPARM_MAX)
2858 error ("%sregparm=%d%s is not between 0 and %d",
2859 prefix, i, suffix, REGPARM_MAX);
2864 ix86_regparm = REGPARM_MAX;
2866 /* If the user has provided any of the -malign-* options,
2867 warn and use that value only if -falign-* is not set.
2868 Remove this code in GCC 3.2 or later. */
2869 if (ix86_align_loops_string)
2871 warning (0, "%salign-loops%s is obsolete, use %salign-loops%s",
2872 prefix, suffix, prefix, suffix);
2873 if (align_loops == 0)
2875 i = atoi (ix86_align_loops_string);
2876 if (i < 0 || i > MAX_CODE_ALIGN)
2877 error ("%salign-loops=%d%s is not between 0 and %d",
2878 prefix, i, suffix, MAX_CODE_ALIGN);
2880 align_loops = 1 << i;
2884 if (ix86_align_jumps_string)
2886 warning (0, "%salign-jumps%s is obsolete, use %salign-jumps%s",
2887 prefix, suffix, prefix, suffix);
2888 if (align_jumps == 0)
2890 i = atoi (ix86_align_jumps_string);
2891 if (i < 0 || i > MAX_CODE_ALIGN)
2892 error ("%salign-loops=%d%s is not between 0 and %d",
2893 prefix, i, suffix, MAX_CODE_ALIGN);
2895 align_jumps = 1 << i;
2899 if (ix86_align_funcs_string)
2901 warning (0, "%salign-functions%s is obsolete, use %salign-functions%s",
2902 prefix, suffix, prefix, suffix);
2903 if (align_functions == 0)
2905 i = atoi (ix86_align_funcs_string);
2906 if (i < 0 || i > MAX_CODE_ALIGN)
2907 error ("%salign-loops=%d%s is not between 0 and %d",
2908 prefix, i, suffix, MAX_CODE_ALIGN);
2910 align_functions = 1 << i;
2914 /* Default align_* from the processor table. */
2915 if (align_loops == 0)
2917 align_loops = processor_target_table[ix86_tune].align_loop;
2918 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2920 if (align_jumps == 0)
2922 align_jumps = processor_target_table[ix86_tune].align_jump;
2923 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2925 if (align_functions == 0)
2927 align_functions = processor_target_table[ix86_tune].align_func;
2930 /* Validate -mbranch-cost= value, or provide default. */
2931 ix86_branch_cost = ix86_cost->branch_cost;
2932 if (ix86_branch_cost_string)
2934 i = atoi (ix86_branch_cost_string);
2936 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
2938 ix86_branch_cost = i;
2940 if (ix86_section_threshold_string)
2942 i = atoi (ix86_section_threshold_string);
2944 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
2946 ix86_section_threshold = i;
2949 if (ix86_tls_dialect_string)
2951 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2952 ix86_tls_dialect = TLS_DIALECT_GNU;
2953 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2954 ix86_tls_dialect = TLS_DIALECT_GNU2;
2955 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2956 ix86_tls_dialect = TLS_DIALECT_SUN;
2958 error ("bad value (%s) for %stls-dialect=%s %s",
2959 ix86_tls_dialect_string, prefix, suffix, sw);
2962 if (ix87_precision_string)
2964 i = atoi (ix87_precision_string);
2965 if (i != 32 && i != 64 && i != 80)
2966 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
2971 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
2973 /* Enable by default the SSE and MMX builtins. Do allow the user to
2974 explicitly disable any of these. In particular, disabling SSE and
2975 MMX for kernel code is extremely useful. */
2976 if (!ix86_arch_specified)
2978 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
2979 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
2982 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
2986 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
2988 if (!ix86_arch_specified)
2990 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
2992 /* i386 ABI does not specify red zone. It still makes sense to use it
2993 when programmer takes care to stack from being destroyed. */
2994 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2995 target_flags |= MASK_NO_RED_ZONE;
2998 /* Keep nonleaf frame pointers. */
2999 if (flag_omit_frame_pointer)
3000 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3001 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3002 flag_omit_frame_pointer = 1;
3004 /* If we're doing fast math, we don't care about comparison order
3005 wrt NaNs. This lets us use a shorter comparison sequence. */
3006 if (flag_finite_math_only)
3007 target_flags &= ~MASK_IEEE_FP;
3009 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3010 since the insns won't need emulation. */
3011 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3012 target_flags &= ~MASK_NO_FANCY_MATH_387;
3014 /* Likewise, if the target doesn't have a 387, or we've specified
3015 software floating point, don't use 387 inline intrinsics. */
3017 target_flags |= MASK_NO_FANCY_MATH_387;
3019 /* Turn on MMX builtins for -msse. */
3022 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3023 x86_prefetch_sse = true;
3026 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3027 if (TARGET_SSE4_2 || TARGET_ABM)
3028 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3030 /* Validate -mpreferred-stack-boundary= value or default it to
3031 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3032 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3033 if (ix86_preferred_stack_boundary_string)
3035 i = atoi (ix86_preferred_stack_boundary_string);
3036 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3037 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3038 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3040 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3043 /* Set the default value for -mstackrealign. */
3044 if (ix86_force_align_arg_pointer == -1)
3045 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3047 /* Validate -mincoming-stack-boundary= value or default it to
3048 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3049 if (ix86_force_align_arg_pointer)
3050 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3052 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3053 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3054 if (ix86_incoming_stack_boundary_string)
3056 i = atoi (ix86_incoming_stack_boundary_string);
3057 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3058 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3059 i, TARGET_64BIT ? 4 : 2);
3062 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3063 ix86_incoming_stack_boundary
3064 = ix86_user_incoming_stack_boundary;
3068 /* Accept -msseregparm only if at least SSE support is enabled. */
3069 if (TARGET_SSEREGPARM
3071 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3073 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3074 if (ix86_fpmath_string != 0)
3076 if (! strcmp (ix86_fpmath_string, "387"))
3077 ix86_fpmath = FPMATH_387;
3078 else if (! strcmp (ix86_fpmath_string, "sse"))
3082 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3083 ix86_fpmath = FPMATH_387;
3086 ix86_fpmath = FPMATH_SSE;
3088 else if (! strcmp (ix86_fpmath_string, "387,sse")
3089 || ! strcmp (ix86_fpmath_string, "387+sse")
3090 || ! strcmp (ix86_fpmath_string, "sse,387")
3091 || ! strcmp (ix86_fpmath_string, "sse+387")
3092 || ! strcmp (ix86_fpmath_string, "both"))
3096 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3097 ix86_fpmath = FPMATH_387;
3099 else if (!TARGET_80387)
3101 warning (0, "387 instruction set disabled, using SSE arithmetics");
3102 ix86_fpmath = FPMATH_SSE;
3105 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3108 error ("bad value (%s) for %sfpmath=%s %s",
3109 ix86_fpmath_string, prefix, suffix, sw);
3112 /* If the i387 is disabled, then do not return values in it. */
3114 target_flags &= ~MASK_FLOAT_RETURNS;
3116 /* Use external vectorized library in vectorizing intrinsics. */
3117 if (ix86_veclibabi_string)
3119 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3120 ix86_veclib_handler = ix86_veclibabi_svml;
3121 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3122 ix86_veclib_handler = ix86_veclibabi_acml;
3124 error ("unknown vectorization library ABI type (%s) for "
3125 "%sveclibabi=%s %s", ix86_veclibabi_string,
3126 prefix, suffix, sw);
3129 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3130 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3132 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3134 /* ??? Unwind info is not correct around the CFG unless either a frame
3135 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3136 unwind info generation to be aware of the CFG and propagating states
3138 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3139 || flag_exceptions || flag_non_call_exceptions)
3140 && flag_omit_frame_pointer
3141 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3143 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3144 warning (0, "unwind tables currently require either a frame pointer "
3145 "or %saccumulate-outgoing-args%s for correctness",
3147 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3150 /* If stack probes are required, the space used for large function
3151 arguments on the stack must also be probed, so enable
3152 -maccumulate-outgoing-args so this happens in the prologue. */
3153 if (TARGET_STACK_PROBE
3154 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3156 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3157 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3158 "for correctness", prefix, suffix);
3159 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3162 /* For sane SSE instruction set generation we need fcomi instruction.
3163 It is safe to enable all CMOVE instructions. */
3167 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3170 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3171 p = strchr (internal_label_prefix, 'X');
3172 internal_label_prefix_len = p - internal_label_prefix;
3176 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3177 set_param_value ("simultaneous-prefetches",
3178 ix86_cost->simultaneous_prefetches);
3179 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3180 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3181 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3182 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3183 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3184 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3186 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3187 can be optimized to ap = __builtin_next_arg (0). */
3189 targetm.expand_builtin_va_start = NULL;
3193 ix86_gen_leave = gen_leave_rex64;
3194 ix86_gen_pop1 = gen_popdi1;
3195 ix86_gen_add3 = gen_adddi3;
3196 ix86_gen_sub3 = gen_subdi3;
3197 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3198 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3199 ix86_gen_monitor = gen_sse3_monitor64;
3200 ix86_gen_andsp = gen_anddi3;
3204 ix86_gen_leave = gen_leave;
3205 ix86_gen_pop1 = gen_popsi1;
3206 ix86_gen_add3 = gen_addsi3;
3207 ix86_gen_sub3 = gen_subsi3;
3208 ix86_gen_sub3_carry = gen_subsi3_carry;
3209 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3210 ix86_gen_monitor = gen_sse3_monitor;
3211 ix86_gen_andsp = gen_andsi3;
3215 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3217 target_flags |= MASK_CLD & ~target_flags_explicit;
3220 /* Save the initial options in case the user does function specific options */
3222 target_option_default_node = target_option_current_node
3223 = build_target_option_node ();
3226 /* Save the current options */
3229 ix86_function_specific_save (struct cl_target_option *ptr)
3231 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3232 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3233 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3234 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3236 ptr->arch = ix86_arch;
3237 ptr->tune = ix86_tune;
3238 ptr->fpmath = ix86_fpmath;
3239 ptr->branch_cost = ix86_branch_cost;
3240 ptr->tune_defaulted = ix86_tune_defaulted;
3241 ptr->arch_specified = ix86_arch_specified;
3242 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3243 ptr->target_flags_explicit = target_flags_explicit;
3246 /* Restore the current options */
3249 ix86_function_specific_restore (struct cl_target_option *ptr)
3251 enum processor_type old_tune = ix86_tune;
3252 enum processor_type old_arch = ix86_arch;
3253 unsigned int ix86_arch_mask, ix86_tune_mask;
3256 ix86_arch = ptr->arch;
3257 ix86_tune = ptr->tune;
3258 ix86_fpmath = ptr->fpmath;
3259 ix86_branch_cost = ptr->branch_cost;
3260 ix86_tune_defaulted = ptr->tune_defaulted;
3261 ix86_arch_specified = ptr->arch_specified;
3262 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3263 target_flags_explicit = ptr->target_flags_explicit;
3265 /* Recreate the arch feature tests if the arch changed */
3266 if (old_arch != ix86_arch)
3268 ix86_arch_mask = 1u << ix86_arch;
3269 for (i = 0; i < X86_ARCH_LAST; ++i)
3270 ix86_arch_features[i]
3271 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3274 /* Recreate the tune optimization tests */
3275 if (old_tune != ix86_tune)
3277 ix86_tune_mask = 1u << ix86_tune;
3278 for (i = 0; i < X86_TUNE_LAST; ++i)
3279 ix86_tune_features[i]
3280 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3284 /* Print the current options */
3287 ix86_function_specific_print (FILE *file, int indent,
3288 struct cl_target_option *ptr)
3291 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3292 NULL, NULL, NULL, false);
3294 fprintf (file, "%*sarch = %d (%s)\n",
3297 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3298 ? cpu_names[ptr->arch]
3301 fprintf (file, "%*stune = %d (%s)\n",
3304 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3305 ? cpu_names[ptr->tune]
3308 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3309 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3310 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3311 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3315 fprintf (file, "%*s%s\n", indent, "", target_string);
3316 free (target_string);
3321 /* Inner function to process the attribute((option(...))), take an argument and
3322 set the current options from the argument. If we have a list, recursively go
3326 ix86_valid_option_attribute_inner_p (tree args, char *p_strings[])
3331 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3332 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3333 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3334 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3349 enum ix86_opt_type type;
3354 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3355 IX86_ATTR_ISA ("abm", OPT_mabm),
3356 IX86_ATTR_ISA ("aes", OPT_maes),
3357 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3358 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3359 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3360 IX86_ATTR_ISA ("sse", OPT_msse),
3361 IX86_ATTR_ISA ("sse2", OPT_msse2),
3362 IX86_ATTR_ISA ("sse3", OPT_msse3),
3363 IX86_ATTR_ISA ("sse4", OPT_msse4),
3364 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3365 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3366 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3367 IX86_ATTR_ISA ("sse5", OPT_msse5),
3368 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3370 /* string options */
3371 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3372 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3373 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3376 IX86_ATTR_YES ("cld",
3380 IX86_ATTR_NO ("fancy-math-387",
3381 OPT_mfancy_math_387,
3382 MASK_NO_FANCY_MATH_387),
3384 IX86_ATTR_NO ("fused-madd",
3386 MASK_NO_FUSED_MADD),
3388 IX86_ATTR_YES ("ieee-fp",
3392 IX86_ATTR_YES ("inline-all-stringops",
3393 OPT_minline_all_stringops,
3394 MASK_INLINE_ALL_STRINGOPS),
3396 IX86_ATTR_YES ("inline-stringops-dynamically",
3397 OPT_minline_stringops_dynamically,
3398 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3400 IX86_ATTR_NO ("align-stringops",
3401 OPT_mno_align_stringops,
3402 MASK_NO_ALIGN_STRINGOPS),
3404 IX86_ATTR_YES ("recip",
3410 /* If this is a list, recurse to get the options. */
3411 if (TREE_CODE (args) == TREE_LIST)
3415 for (; args; args = TREE_CHAIN (args))
3416 if (TREE_VALUE (args)
3417 && !ix86_valid_option_attribute_inner_p (TREE_VALUE (args), p_strings))
3423 else if (TREE_CODE (args) != STRING_CST)
3426 /* Handle multiple arguments separated by commas. */
3427 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3429 while (next_optstr && *next_optstr != '\0')
3431 char *p = next_optstr;
3433 char *comma = strchr (next_optstr, ',');
3434 const char *opt_string;
3435 size_t len, opt_len;
3440 enum ix86_opt_type type = ix86_opt_unknown;
3446 len = comma - next_optstr;
3447 next_optstr = comma + 1;
3455 /* Recognize no-xxx. */
3456 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3465 /* Find the option. */
3468 for (i = 0; i < sizeof (attrs) / sizeof (attrs[0]); i++)
3470 type = attrs[i].type;
3471 opt_len = attrs[i].len;
3472 if (ch == attrs[i].string[0]
3473 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3474 && memcmp (p, attrs[i].string, opt_len) == 0)
3477 mask = attrs[i].mask;
3478 opt_string = attrs[i].string;
3483 /* Process the option. */
3486 error ("attribute(option(\"%s\")) is unknown", orig_p);
3490 else if (type == ix86_opt_isa)
3491 ix86_handle_option (opt, p, opt_set_p);
3493 else if (type == ix86_opt_yes || type == ix86_opt_no)
3495 if (type == ix86_opt_no)
3496 opt_set_p = !opt_set_p;
3499 target_flags |= mask;
3501 target_flags &= ~mask;
3504 else if (type == ix86_opt_str)
3508 error ("option(\"%s\") was already specified", opt_string);
3512 p_strings[opt] = xstrdup (p + opt_len);
3522 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3525 ix86_valid_option_attribute_tree (tree args)
3527 const char *orig_arch_string = ix86_arch_string;
3528 const char *orig_tune_string = ix86_tune_string;
3529 const char *orig_fpmath_string = ix86_fpmath_string;
3530 int orig_tune_defaulted = ix86_tune_defaulted;
3531 int orig_arch_specified = ix86_arch_specified;
3532 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3535 struct cl_target_option *def
3536 = TREE_TARGET_OPTION (target_option_default_node);
3538 /* Process each of the options on the chain. */
3539 if (! ix86_valid_option_attribute_inner_p (args, option_strings))
3542 /* If the changed options are different from the default, rerun override_options,
3543 and then save the options away. The string options are are attribute options,
3544 and will be undone when we copy the save structure. */
3545 if (ix86_isa_flags != def->ix86_isa_flags
3546 || target_flags != def->target_flags
3547 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3548 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3549 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3551 /* If we are using the default tune= or arch=, undo the string assigned,
3552 and use the default. */
3553 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3554 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3555 else if (!orig_arch_specified)
3556 ix86_arch_string = NULL;
3558 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3559 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3560 else if (orig_tune_defaulted)
3561 ix86_tune_string = NULL;
3563 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3564 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3565 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3566 else if (!TARGET_64BIT && TARGET_SSE)
3567 ix86_fpmath_string = "sse,387";
3569 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3570 override_options (false);
3572 /* Save the current options unless we are validating options for
3574 t = build_target_option_node ();
3576 ix86_arch_string = orig_arch_string;
3577 ix86_tune_string = orig_tune_string;
3578 ix86_fpmath_string = orig_fpmath_string;
3580 /* Free up memory allocated to hold the strings */
3581 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3582 if (option_strings[i])
3583 free (option_strings[i]);
3589 /* Hook to validate attribute((option("string"))). */
3592 ix86_valid_option_attribute_p (tree fndecl,
3593 tree ARG_UNUSED (name),
3595 int ARG_UNUSED (flags))
3597 struct cl_target_option cur_opts;
3601 cl_target_option_save (&cur_opts);
3602 new_opts = ix86_valid_option_attribute_tree (args);
3607 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_opts;
3609 cl_target_option_restore (&cur_opts);
3614 /* Hook to determine if one function can safely inline another. */
3617 ix86_can_inline_p (tree caller, tree callee)
3620 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3621 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3623 /* If callee has no option attributes, then it is ok to inline. */
3627 /* If caller has no option attributes, but callee does then it is not ok to
3629 else if (!caller_tree)
3634 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3635 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3637 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3638 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3640 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3641 != callee_opts->ix86_isa_flags)
3644 /* See if we have the same non-isa options. */
3645 else if (caller_opts->target_flags != callee_opts->target_flags)
3648 /* See if arch, tune, etc. are the same. */
3649 else if (caller_opts->arch != callee_opts->arch)
3652 else if (caller_opts->tune != callee_opts->tune)
3655 else if (caller_opts->fpmath != callee_opts->fpmath)
3658 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3669 /* Remember the last target of ix86_set_current_function. */
3670 static GTY(()) tree ix86_previous_fndecl;
3672 /* Establish appropriate back-end context for processing the function
3673 FNDECL. The argument might be NULL to indicate processing at top
3674 level, outside of any function scope. */
3676 ix86_set_current_function (tree fndecl)
3678 /* Only change the context if the function changes. This hook is called
3679 several times in the course of compiling a function, and we don't want to
3680 slow things down too much or call target_reinit when it isn't safe. */
3681 if (fndecl && fndecl != ix86_previous_fndecl)
3683 tree old_tree = (ix86_previous_fndecl
3684 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3687 tree new_tree = (fndecl
3688 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3691 ix86_previous_fndecl = fndecl;
3692 if (old_tree == new_tree)
3697 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3703 struct cl_target_option *def
3704 = TREE_TARGET_OPTION (target_option_current_node);
3706 cl_target_option_restore (def);
3713 /* Return true if this goes in large data/bss. */
3716 ix86_in_large_data_p (tree exp)
3718 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3721 /* Functions are never large data. */
3722 if (TREE_CODE (exp) == FUNCTION_DECL)
3725 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3727 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3728 if (strcmp (section, ".ldata") == 0
3729 || strcmp (section, ".lbss") == 0)
3735 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3737 /* If this is an incomplete type with size 0, then we can't put it
3738 in data because it might be too big when completed. */
3739 if (!size || size > ix86_section_threshold)
3746 /* Switch to the appropriate section for output of DECL.
3747 DECL is either a `VAR_DECL' node or a constant of some sort.
3748 RELOC indicates whether forming the initial value of DECL requires
3749 link-time relocations. */
3751 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3755 x86_64_elf_select_section (tree decl, int reloc,
3756 unsigned HOST_WIDE_INT align)
3758 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3759 && ix86_in_large_data_p (decl))
3761 const char *sname = NULL;
3762 unsigned int flags = SECTION_WRITE;
3763 switch (categorize_decl_for_section (decl, reloc))
3768 case SECCAT_DATA_REL:
3769 sname = ".ldata.rel";
3771 case SECCAT_DATA_REL_LOCAL:
3772 sname = ".ldata.rel.local";
3774 case SECCAT_DATA_REL_RO:
3775 sname = ".ldata.rel.ro";
3777 case SECCAT_DATA_REL_RO_LOCAL:
3778 sname = ".ldata.rel.ro.local";
3782 flags |= SECTION_BSS;
3785 case SECCAT_RODATA_MERGE_STR:
3786 case SECCAT_RODATA_MERGE_STR_INIT:
3787 case SECCAT_RODATA_MERGE_CONST:
3791 case SECCAT_SRODATA:
3798 /* We don't split these for medium model. Place them into
3799 default sections and hope for best. */
3801 case SECCAT_EMUTLS_VAR:
3802 case SECCAT_EMUTLS_TMPL:
3807 /* We might get called with string constants, but get_named_section
3808 doesn't like them as they are not DECLs. Also, we need to set
3809 flags in that case. */
3811 return get_section (sname, flags, NULL);
3812 return get_named_section (decl, sname, reloc);
3815 return default_elf_select_section (decl, reloc, align);
3818 /* Build up a unique section name, expressed as a
3819 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3820 RELOC indicates whether the initial value of EXP requires
3821 link-time relocations. */
3823 static void ATTRIBUTE_UNUSED
3824 x86_64_elf_unique_section (tree decl, int reloc)
3826 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3827 && ix86_in_large_data_p (decl))
3829 const char *prefix = NULL;
3830 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3831 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3833 switch (categorize_decl_for_section (decl, reloc))
3836 case SECCAT_DATA_REL:
3837 case SECCAT_DATA_REL_LOCAL:
3838 case SECCAT_DATA_REL_RO:
3839 case SECCAT_DATA_REL_RO_LOCAL:
3840 prefix = one_only ? ".ld" : ".ldata";
3843 prefix = one_only ? ".lb" : ".lbss";
3846 case SECCAT_RODATA_MERGE_STR:
3847 case SECCAT_RODATA_MERGE_STR_INIT:
3848 case SECCAT_RODATA_MERGE_CONST:
3849 prefix = one_only ? ".lr" : ".lrodata";
3851 case SECCAT_SRODATA:
3858 /* We don't split these for medium model. Place them into
3859 default sections and hope for best. */
3861 case SECCAT_EMUTLS_VAR:
3862 prefix = targetm.emutls.var_section;
3864 case SECCAT_EMUTLS_TMPL:
3865 prefix = targetm.emutls.tmpl_section;
3870 const char *name, *linkonce;
3873 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3874 name = targetm.strip_name_encoding (name);
3876 /* If we're using one_only, then there needs to be a .gnu.linkonce
3877 prefix to the section name. */
3878 linkonce = one_only ? ".gnu.linkonce" : "";
3880 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
3882 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
3886 default_unique_section (decl, reloc);
3889 #ifdef COMMON_ASM_OP
3890 /* This says how to output assembler code to declare an
3891 uninitialized external linkage data object.
3893 For medium model x86-64 we need to use .largecomm opcode for
3896 x86_elf_aligned_common (FILE *file,
3897 const char *name, unsigned HOST_WIDE_INT size,
3900 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3901 && size > (unsigned int)ix86_section_threshold)
3902 fprintf (file, ".largecomm\t");
3904 fprintf (file, "%s", COMMON_ASM_OP);
3905 assemble_name (file, name);
3906 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
3907 size, align / BITS_PER_UNIT);
3911 /* Utility function for targets to use in implementing
3912 ASM_OUTPUT_ALIGNED_BSS. */
3915 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
3916 const char *name, unsigned HOST_WIDE_INT size,
3919 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3920 && size > (unsigned int)ix86_section_threshold)
3921 switch_to_section (get_named_section (decl, ".lbss", 0));
3923 switch_to_section (bss_section);
3924 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
3925 #ifdef ASM_DECLARE_OBJECT_NAME
3926 last_assemble_variable_decl = decl;
3927 ASM_DECLARE_OBJECT_NAME (file, name, decl);
3929 /* Standard thing is just output label for the object. */
3930 ASM_OUTPUT_LABEL (file, name);
3931 #endif /* ASM_DECLARE_OBJECT_NAME */
3932 ASM_OUTPUT_SKIP (file, size ? size : 1);
3936 optimization_options (int level, int size ATTRIBUTE_UNUSED)
3938 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
3939 make the problem with not enough registers even worse. */
3940 #ifdef INSN_SCHEDULING
3942 flag_schedule_insns = 0;
3945 /* When scheduling description is not available, disable scheduler pass
3946 so it won't slow down the compilation and make x87 code slower. */
3947 if (!TARGET_SCHEDULE)
3948 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3951 /* The Darwin libraries never set errno, so we might as well
3952 avoid calling them when that's the only reason we would. */
3953 flag_errno_math = 0;
3955 /* The default values of these switches depend on the TARGET_64BIT
3956 that is not known at this moment. Mark these values with 2 and
3957 let user the to override these. In case there is no command line option
3958 specifying them, we will set the defaults in override_options. */
3960 flag_omit_frame_pointer = 2;
3961 flag_pcc_struct_return = 2;
3962 flag_asynchronous_unwind_tables = 2;
3963 flag_vect_cost_model = 1;
3964 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
3965 SUBTARGET_OPTIMIZATION_OPTIONS;
3969 /* Decide whether we can make a sibling call to a function. DECL is the
3970 declaration of the function being targeted by the call and EXP is the
3971 CALL_EXPR representing the call. */
3974 ix86_function_ok_for_sibcall (tree decl, tree exp)
3979 /* If we are generating position-independent code, we cannot sibcall
3980 optimize any indirect call, or a direct call to a global function,
3981 as the PLT requires %ebx be live. */
3982 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
3989 func = TREE_TYPE (CALL_EXPR_FN (exp));
3990 if (POINTER_TYPE_P (func))
3991 func = TREE_TYPE (func);
3994 /* Check that the return value locations are the same. Like
3995 if we are returning floats on the 80387 register stack, we cannot
3996 make a sibcall from a function that doesn't return a float to a
3997 function that does or, conversely, from a function that does return
3998 a float to a function that doesn't; the necessary stack adjustment
3999 would not be executed. This is also the place we notice
4000 differences in the return value ABI. Note that it is ok for one
4001 of the functions to have void return type as long as the return
4002 value of the other is passed in a register. */
4003 a = ix86_function_value (TREE_TYPE (exp), func, false);
4004 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4006 if (STACK_REG_P (a) || STACK_REG_P (b))
4008 if (!rtx_equal_p (a, b))
4011 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4013 else if (!rtx_equal_p (a, b))
4016 /* If this call is indirect, we'll need to be able to use a call-clobbered
4017 register for the address of the target function. Make sure that all
4018 such registers are not used for passing parameters. */
4019 if (!decl && !TARGET_64BIT)
4023 /* We're looking at the CALL_EXPR, we need the type of the function. */
4024 type = CALL_EXPR_FN (exp); /* pointer expression */
4025 type = TREE_TYPE (type); /* pointer type */
4026 type = TREE_TYPE (type); /* function type */
4028 if (ix86_function_regparm (type, NULL) >= 3)
4030 /* ??? Need to count the actual number of registers to be used,
4031 not the possible number of registers. Fix later. */
4036 /* Dllimport'd functions are also called indirectly. */
4037 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
4038 && decl && DECL_DLLIMPORT_P (decl)
4039 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
4042 /* Otherwise okay. That also includes certain types of indirect calls. */
4046 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4047 calling convention attributes;
4048 arguments as in struct attribute_spec.handler. */
4051 ix86_handle_cconv_attribute (tree *node, tree name,
4053 int flags ATTRIBUTE_UNUSED,
4056 if (TREE_CODE (*node) != FUNCTION_TYPE
4057 && TREE_CODE (*node) != METHOD_TYPE
4058 && TREE_CODE (*node) != FIELD_DECL
4059 && TREE_CODE (*node) != TYPE_DECL)
4061 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4062 IDENTIFIER_POINTER (name));
4063 *no_add_attrs = true;
4067 /* Can combine regparm with all attributes but fastcall. */
4068 if (is_attribute_p ("regparm", name))
4072 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4074 error ("fastcall and regparm attributes are not compatible");
4077 cst = TREE_VALUE (args);
4078 if (TREE_CODE (cst) != INTEGER_CST)
4080 warning (OPT_Wattributes,
4081 "%qs attribute requires an integer constant argument",
4082 IDENTIFIER_POINTER (name));
4083 *no_add_attrs = true;
4085 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4087 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
4088 IDENTIFIER_POINTER (name), REGPARM_MAX);
4089 *no_add_attrs = true;
4097 /* Do not warn when emulating the MS ABI. */
4098 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4099 warning (OPT_Wattributes, "%qs attribute ignored",
4100 IDENTIFIER_POINTER (name));
4101 *no_add_attrs = true;
4105 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4106 if (is_attribute_p ("fastcall", name))
4108 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4110 error ("fastcall and cdecl attributes are not compatible");
4112 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4114 error ("fastcall and stdcall attributes are not compatible");
4116 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4118 error ("fastcall and regparm attributes are not compatible");
4122 /* Can combine stdcall with fastcall (redundant), regparm and
4124 else if (is_attribute_p ("stdcall", name))
4126 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4128 error ("stdcall and cdecl attributes are not compatible");
4130 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4132 error ("stdcall and fastcall attributes are not compatible");
4136 /* Can combine cdecl with regparm and sseregparm. */
4137 else if (is_attribute_p ("cdecl", name))
4139 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4141 error ("stdcall and cdecl attributes are not compatible");
4143 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4145 error ("fastcall and cdecl attributes are not compatible");
4149 /* Can combine sseregparm with all attributes. */
4154 /* Return 0 if the attributes for two types are incompatible, 1 if they
4155 are compatible, and 2 if they are nearly compatible (which causes a
4156 warning to be generated). */
4159 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4161 /* Check for mismatch of non-default calling convention. */
4162 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4164 if (TREE_CODE (type1) != FUNCTION_TYPE
4165 && TREE_CODE (type1) != METHOD_TYPE)
4168 /* Check for mismatched fastcall/regparm types. */
4169 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4170 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4171 || (ix86_function_regparm (type1, NULL)
4172 != ix86_function_regparm (type2, NULL)))
4175 /* Check for mismatched sseregparm types. */
4176 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4177 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4180 /* Check for mismatched return types (cdecl vs stdcall). */
4181 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4182 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4188 /* Return the regparm value for a function with the indicated TYPE and DECL.
4189 DECL may be NULL when calling function indirectly
4190 or considering a libcall. */
4193 ix86_function_regparm (const_tree type, const_tree decl)
4196 int regparm = ix86_regparm;
4198 static bool error_issued;
4202 if (ix86_function_type_abi (type) == DEFAULT_ABI)
4204 return DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
4207 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4211 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4213 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4215 /* We can't use regparm(3) for nested functions because
4216 these pass static chain pointer in %ecx register. */
4217 if (!error_issued && regparm == 3
4218 && decl_function_context (decl)
4219 && !DECL_NO_STATIC_CHAIN (decl))
4221 error ("nested functions are limited to 2 register parameters");
4222 error_issued = true;
4230 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4233 /* Use register calling convention for local functions when possible. */
4234 if (decl && TREE_CODE (decl) == FUNCTION_DECL
4237 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4238 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4241 int local_regparm, globals = 0, regno;
4244 /* Make sure no regparm register is taken by a
4245 fixed register variable. */
4246 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4247 if (fixed_regs[local_regparm])
4250 /* We can't use regparm(3) for nested functions as these use
4251 static chain pointer in third argument. */
4252 if (local_regparm == 3
4253 && decl_function_context (decl)
4254 && !DECL_NO_STATIC_CHAIN (decl))
4257 /* If the function realigns its stackpointer, the prologue will
4258 clobber %ecx. If we've already generated code for the callee,
4259 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4260 scanning the attributes for the self-realigning property. */
4261 f = DECL_STRUCT_FUNCTION (decl);
4262 /* Since current internal arg pointer won't conflict with
4263 parameter passing regs, so no need to change stack
4264 realignment and adjust regparm number.
4266 Each fixed register usage increases register pressure,
4267 so less registers should be used for argument passing.
4268 This functionality can be overriden by an explicit
4270 for (regno = 0; regno <= DI_REG; regno++)
4271 if (fixed_regs[regno])
4275 = globals < local_regparm ? local_regparm - globals : 0;
4277 if (local_regparm > regparm)
4278 regparm = local_regparm;
4285 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4286 DFmode (2) arguments in SSE registers for a function with the
4287 indicated TYPE and DECL. DECL may be NULL when calling function
4288 indirectly or considering a libcall. Otherwise return 0. */
4291 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4293 gcc_assert (!TARGET_64BIT);
4295 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4296 by the sseregparm attribute. */
4297 if (TARGET_SSEREGPARM
4298 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4305 error ("Calling %qD with attribute sseregparm without "
4306 "SSE/SSE2 enabled", decl);
4308 error ("Calling %qT with attribute sseregparm without "
4309 "SSE/SSE2 enabled", type);
4317 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4318 (and DFmode for SSE2) arguments in SSE registers. */
4319 if (decl && TARGET_SSE_MATH && !profile_flag)
4321 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4322 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4324 return TARGET_SSE2 ? 2 : 1;
4330 /* Return true if EAX is live at the start of the function. Used by
4331 ix86_expand_prologue to determine if we need special help before
4332 calling allocate_stack_worker. */
4335 ix86_eax_live_at_start_p (void)
4337 /* Cheat. Don't bother working forward from ix86_function_regparm
4338 to the function type to whether an actual argument is located in
4339 eax. Instead just look at cfg info, which is still close enough
4340 to correct at this point. This gives false positives for broken
4341 functions that might use uninitialized data that happens to be
4342 allocated in eax, but who cares? */
4343 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4346 /* Value is the number of bytes of arguments automatically
4347 popped when returning from a subroutine call.
4348 FUNDECL is the declaration node of the function (as a tree),
4349 FUNTYPE is the data type of the function (as a tree),
4350 or for a library call it is an identifier node for the subroutine name.
4351 SIZE is the number of bytes of arguments passed on the stack.
4353 On the 80386, the RTD insn may be used to pop them if the number
4354 of args is fixed, but if the number is variable then the caller
4355 must pop them all. RTD can't be used for library calls now
4356 because the library is compiled with the Unix compiler.
4357 Use of RTD is a selectable option, since it is incompatible with
4358 standard Unix calling sequences. If the option is not selected,
4359 the caller must always pop the args.
4361 The attribute stdcall is equivalent to RTD on a per module basis. */
4364 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4368 /* None of the 64-bit ABIs pop arguments. */
4372 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4374 /* Cdecl functions override -mrtd, and never pop the stack. */
4375 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4377 /* Stdcall and fastcall functions will pop the stack if not
4379 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4380 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4383 if (rtd && ! stdarg_p (funtype))
4387 /* Lose any fake structure return argument if it is passed on the stack. */
4388 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4389 && !KEEP_AGGREGATE_RETURN_POINTER)
4391 int nregs = ix86_function_regparm (funtype, fundecl);
4393 return GET_MODE_SIZE (Pmode);
4399 /* Argument support functions. */
4401 /* Return true when register may be used to pass function parameters. */
4403 ix86_function_arg_regno_p (int regno)
4406 const int *parm_regs;
4411 return (regno < REGPARM_MAX
4412 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4414 return (regno < REGPARM_MAX
4415 || (TARGET_MMX && MMX_REGNO_P (regno)
4416 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4417 || (TARGET_SSE && SSE_REGNO_P (regno)
4418 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4423 if (SSE_REGNO_P (regno) && TARGET_SSE)
4428 if (TARGET_SSE && SSE_REGNO_P (regno)
4429 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4433 /* TODO: The function should depend on current function ABI but
4434 builtins.c would need updating then. Therefore we use the
4437 /* RAX is used as hidden argument to va_arg functions. */
4438 if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
4441 if (DEFAULT_ABI == MS_ABI)
4442 parm_regs = x86_64_ms_abi_int_parameter_registers;
4444 parm_regs = x86_64_int_parameter_registers;
4445 for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
4446 : X86_64_REGPARM_MAX); i++)
4447 if (regno == parm_regs[i])
4452 /* Return if we do not know how to pass TYPE solely in registers. */
4455 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4457 if (must_pass_in_stack_var_size_or_pad (mode, type))
4460 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4461 The layout_type routine is crafty and tries to trick us into passing
4462 currently unsupported vector types on the stack by using TImode. */
4463 return (!TARGET_64BIT && mode == TImode
4464 && type && TREE_CODE (type) != VECTOR_TYPE);
4467 /* It returns the size, in bytes, of the area reserved for arguments passed
4468 in registers for the function represented by fndecl dependent to the used
4471 ix86_reg_parm_stack_space (const_tree fndecl)
4474 /* For libcalls it is possible that there is no fndecl at hand.
4475 Therefore assume for this case the default abi of the target. */
4477 call_abi = DEFAULT_ABI;
4479 call_abi = ix86_function_abi (fndecl);
4485 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4488 ix86_function_type_abi (const_tree fntype)
4490 if (TARGET_64BIT && fntype != NULL)
4493 if (DEFAULT_ABI == SYSV_ABI)
4494 abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
4496 abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
4504 ix86_function_abi (const_tree fndecl)
4508 return ix86_function_type_abi (TREE_TYPE (fndecl));
4511 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4514 ix86_cfun_abi (void)
4516 if (! cfun || ! TARGET_64BIT)
4518 return cfun->machine->call_abi;
4522 extern void init_regs (void);
4524 /* Implementation of call abi switching target hook. Specific to FNDECL
4525 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4527 To prevent redudant calls of costy function init_regs (), it checks not to
4528 reset register usage for default abi. */
4530 ix86_call_abi_override (const_tree fndecl)
4532 if (fndecl == NULL_TREE)
4533 cfun->machine->call_abi = DEFAULT_ABI;
4535 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4536 if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
4538 if (call_used_regs[4 /*RSI*/] != 0 || call_used_regs[5 /*RDI*/] != 0)
4540 call_used_regs[4 /*RSI*/] = 0;
4541 call_used_regs[5 /*RDI*/] = 0;
4545 else if (TARGET_64BIT)
4547 if (call_used_regs[4 /*RSI*/] != 1 || call_used_regs[5 /*RDI*/] != 1)
4549 call_used_regs[4 /*RSI*/] = 1;
4550 call_used_regs[5 /*RDI*/] = 1;
4556 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4557 for a call to a function whose data type is FNTYPE.
4558 For a library call, FNTYPE is 0. */
4561 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4562 tree fntype, /* tree ptr for function decl */
4563 rtx libname, /* SYMBOL_REF of library name or 0 */
4566 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4567 memset (cum, 0, sizeof (*cum));
4569 cum->call_abi = ix86_function_type_abi (fntype);
4570 /* Set up the number of registers to use for passing arguments. */
4571 cum->nregs = ix86_regparm;
4574 if (cum->call_abi != DEFAULT_ABI)
4575 cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
4580 cum->sse_nregs = SSE_REGPARM_MAX;
4583 if (cum->call_abi != DEFAULT_ABI)
4584 cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4585 : X64_SSE_REGPARM_MAX;
4589 cum->mmx_nregs = MMX_REGPARM_MAX;
4590 cum->warn_sse = true;
4591 cum->warn_mmx = true;
4593 /* Because type might mismatch in between caller and callee, we need to
4594 use actual type of function for local calls.
4595 FIXME: cgraph_analyze can be told to actually record if function uses
4596 va_start so for local functions maybe_vaarg can be made aggressive
4598 FIXME: once typesytem is fixed, we won't need this code anymore. */
4600 fntype = TREE_TYPE (fndecl);
4601 cum->maybe_vaarg = (fntype
4602 ? (!prototype_p (fntype) || stdarg_p (fntype))
4607 /* If there are variable arguments, then we won't pass anything
4608 in registers in 32-bit mode. */
4609 if (stdarg_p (fntype))
4619 /* Use ecx and edx registers if function has fastcall attribute,
4620 else look for regparm information. */
4623 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4629 cum->nregs = ix86_function_regparm (fntype, fndecl);
4632 /* Set up the number of SSE registers used for passing SFmode
4633 and DFmode arguments. Warn for mismatching ABI. */
4634 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4638 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4639 But in the case of vector types, it is some vector mode.
4641 When we have only some of our vector isa extensions enabled, then there
4642 are some modes for which vector_mode_supported_p is false. For these
4643 modes, the generic vector support in gcc will choose some non-vector mode
4644 in order to implement the type. By computing the natural mode, we'll
4645 select the proper ABI location for the operand and not depend on whatever
4646 the middle-end decides to do with these vector types. */
4648 static enum machine_mode
4649 type_natural_mode (const_tree type)
4651 enum machine_mode mode = TYPE_MODE (type);
4653 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4655 HOST_WIDE_INT size = int_size_in_bytes (type);
4656 if ((size == 8 || size == 16)
4657 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4658 && TYPE_VECTOR_SUBPARTS (type) > 1)
4660 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4662 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4663 mode = MIN_MODE_VECTOR_FLOAT;
4665 mode = MIN_MODE_VECTOR_INT;
4667 /* Get the mode which has this inner mode and number of units. */
4668 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4669 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4670 && GET_MODE_INNER (mode) == innermode)
4680 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4681 this may not agree with the mode that the type system has chosen for the
4682 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4683 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4686 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4691 if (orig_mode != BLKmode)
4692 tmp = gen_rtx_REG (orig_mode, regno);
4695 tmp = gen_rtx_REG (mode, regno);
4696 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4697 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4703 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4704 of this code is to classify each 8bytes of incoming argument by the register
4705 class and assign registers accordingly. */
4707 /* Return the union class of CLASS1 and CLASS2.
4708 See the x86-64 PS ABI for details. */
4710 static enum x86_64_reg_class
4711 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4713 /* Rule #1: If both classes are equal, this is the resulting class. */
4714 if (class1 == class2)
4717 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4719 if (class1 == X86_64_NO_CLASS)
4721 if (class2 == X86_64_NO_CLASS)
4724 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4725 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4726 return X86_64_MEMORY_CLASS;
4728 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4729 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4730 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4731 return X86_64_INTEGERSI_CLASS;
4732 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4733 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4734 return X86_64_INTEGER_CLASS;
4736 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4738 if (class1 == X86_64_X87_CLASS
4739 || class1 == X86_64_X87UP_CLASS
4740 || class1 == X86_64_COMPLEX_X87_CLASS
4741 || class2 == X86_64_X87_CLASS
4742 || class2 == X86_64_X87UP_CLASS
4743 || class2 == X86_64_COMPLEX_X87_CLASS)
4744 return X86_64_MEMORY_CLASS;
4746 /* Rule #6: Otherwise class SSE is used. */
4747 return X86_64_SSE_CLASS;
4750 /* Classify the argument of type TYPE and mode MODE.
4751 CLASSES will be filled by the register class used to pass each word
4752 of the operand. The number of words is returned. In case the parameter
4753 should be passed in memory, 0 is returned. As a special case for zero
4754 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4756 BIT_OFFSET is used internally for handling records and specifies offset
4757 of the offset in bits modulo 256 to avoid overflow cases.
4759 See the x86-64 PS ABI for details.
4763 classify_argument (enum machine_mode mode, const_tree type,
4764 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4766 HOST_WIDE_INT bytes =
4767 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4768 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4770 /* Variable sized entities are always passed/returned in memory. */
4774 if (mode != VOIDmode
4775 && targetm.calls.must_pass_in_stack (mode, type))
4778 if (type && AGGREGATE_TYPE_P (type))
4782 enum x86_64_reg_class subclasses[MAX_CLASSES];
4784 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
4788 for (i = 0; i < words; i++)
4789 classes[i] = X86_64_NO_CLASS;
4791 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4792 signalize memory class, so handle it as special case. */
4795 classes[0] = X86_64_NO_CLASS;
4799 /* Classify each field of record and merge classes. */
4800 switch (TREE_CODE (type))
4803 /* And now merge the fields of structure. */
4804 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4806 if (TREE_CODE (field) == FIELD_DECL)
4810 if (TREE_TYPE (field) == error_mark_node)
4813 /* Bitfields are always classified as integer. Handle them
4814 early, since later code would consider them to be
4815 misaligned integers. */
4816 if (DECL_BIT_FIELD (field))
4818 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4819 i < ((int_bit_position (field) + (bit_offset % 64))
4820 + tree_low_cst (DECL_SIZE (field), 0)
4823 merge_classes (X86_64_INTEGER_CLASS,
4828 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4829 TREE_TYPE (field), subclasses,
4830 (int_bit_position (field)
4831 + bit_offset) % 256);
4834 for (i = 0; i < num; i++)
4837 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4839 merge_classes (subclasses[i], classes[i + pos]);
4847 /* Arrays are handled as small records. */
4850 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
4851 TREE_TYPE (type), subclasses, bit_offset);
4855 /* The partial classes are now full classes. */
4856 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
4857 subclasses[0] = X86_64_SSE_CLASS;
4858 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
4859 subclasses[0] = X86_64_INTEGER_CLASS;
4861 for (i = 0; i < words; i++)
4862 classes[i] = subclasses[i % num];
4867 case QUAL_UNION_TYPE:
4868 /* Unions are similar to RECORD_TYPE but offset is always 0.
4870 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4872 if (TREE_CODE (field) == FIELD_DECL)
4876 if (TREE_TYPE (field) == error_mark_node)
4879 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4880 TREE_TYPE (field), subclasses,
4884 for (i = 0; i < num; i++)
4885 classes[i] = merge_classes (subclasses[i], classes[i]);
4894 /* Final merger cleanup. */
4895 for (i = 0; i < words; i++)
4897 /* If one class is MEMORY, everything should be passed in
4899 if (classes[i] == X86_64_MEMORY_CLASS)
4902 /* The X86_64_SSEUP_CLASS should be always preceded by
4903 X86_64_SSE_CLASS. */
4904 if (classes[i] == X86_64_SSEUP_CLASS
4905 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
4906 classes[i] = X86_64_SSE_CLASS;
4908 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
4909 if (classes[i] == X86_64_X87UP_CLASS
4910 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
4911 classes[i] = X86_64_SSE_CLASS;
4916 /* Compute alignment needed. We align all types to natural boundaries with
4917 exception of XFmode that is aligned to 64bits. */
4918 if (mode != VOIDmode && mode != BLKmode)
4920 int mode_alignment = GET_MODE_BITSIZE (mode);
4923 mode_alignment = 128;
4924 else if (mode == XCmode)
4925 mode_alignment = 256;
4926 if (COMPLEX_MODE_P (mode))
4927 mode_alignment /= 2;
4928 /* Misaligned fields are always returned in memory. */
4929 if (bit_offset % mode_alignment)
4933 /* for V1xx modes, just use the base mode */
4934 if (VECTOR_MODE_P (mode) && mode != V1DImode
4935 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
4936 mode = GET_MODE_INNER (mode);
4938 /* Classification of atomic types. */
4943 classes[0] = X86_64_SSE_CLASS;
4946 classes[0] = X86_64_SSE_CLASS;
4947 classes[1] = X86_64_SSEUP_CLASS;
4956 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
4957 classes[0] = X86_64_INTEGERSI_CLASS;
4959 classes[0] = X86_64_INTEGER_CLASS;
4963 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
4968 if (!(bit_offset % 64))
4969 classes[0] = X86_64_SSESF_CLASS;
4971 classes[0] = X86_64_SSE_CLASS;
4974 classes[0] = X86_64_SSEDF_CLASS;
4977 classes[0] = X86_64_X87_CLASS;
4978 classes[1] = X86_64_X87UP_CLASS;
4981 classes[0] = X86_64_SSE_CLASS;
4982 classes[1] = X86_64_SSEUP_CLASS;
4985 classes[0] = X86_64_SSE_CLASS;
4988 classes[0] = X86_64_SSEDF_CLASS;
4989 classes[1] = X86_64_SSEDF_CLASS;
4992 classes[0] = X86_64_COMPLEX_X87_CLASS;
4995 /* This modes is larger than 16 bytes. */
5003 classes[0] = X86_64_SSE_CLASS;
5004 classes[1] = X86_64_SSEUP_CLASS;
5011 classes[0] = X86_64_SSE_CLASS;
5017 gcc_assert (VECTOR_MODE_P (mode));
5022 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5024 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5025 classes[0] = X86_64_INTEGERSI_CLASS;
5027 classes[0] = X86_64_INTEGER_CLASS;
5028 classes[1] = X86_64_INTEGER_CLASS;
5029 return 1 + (bytes > 8);
5033 /* Examine the argument and return set number of register required in each
5034 class. Return 0 iff parameter should be passed in memory. */
5036 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5037 int *int_nregs, int *sse_nregs)
5039 enum x86_64_reg_class regclass[MAX_CLASSES];
5040 int n = classify_argument (mode, type, regclass, 0);
5046 for (n--; n >= 0; n--)
5047 switch (regclass[n])
5049 case X86_64_INTEGER_CLASS:
5050 case X86_64_INTEGERSI_CLASS:
5053 case X86_64_SSE_CLASS:
5054 case X86_64_SSESF_CLASS:
5055 case X86_64_SSEDF_CLASS:
5058 case X86_64_NO_CLASS:
5059 case X86_64_SSEUP_CLASS:
5061 case X86_64_X87_CLASS:
5062 case X86_64_X87UP_CLASS:
5066 case X86_64_COMPLEX_X87_CLASS:
5067 return in_return ? 2 : 0;
5068 case X86_64_MEMORY_CLASS:
5074 /* Construct container for the argument used by GCC interface. See
5075 FUNCTION_ARG for the detailed description. */
5078 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5079 const_tree type, int in_return, int nintregs, int nsseregs,
5080 const int *intreg, int sse_regno)
5082 /* The following variables hold the static issued_error state. */
5083 static bool issued_sse_arg_error;
5084 static bool issued_sse_ret_error;
5085 static bool issued_x87_ret_error;
5087 enum machine_mode tmpmode;
5089 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5090 enum x86_64_reg_class regclass[MAX_CLASSES];
5094 int needed_sseregs, needed_intregs;
5095 rtx exp[MAX_CLASSES];
5098 n = classify_argument (mode, type, regclass, 0);
5101 if (!examine_argument (mode, type, in_return, &needed_intregs,
5104 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5107 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5108 some less clueful developer tries to use floating-point anyway. */
5109 if (needed_sseregs && !TARGET_SSE)
5113 if (!issued_sse_ret_error)
5115 error ("SSE register return with SSE disabled");
5116 issued_sse_ret_error = true;
5119 else if (!issued_sse_arg_error)
5121 error ("SSE register argument with SSE disabled");
5122 issued_sse_arg_error = true;
5127 /* Likewise, error if the ABI requires us to return values in the
5128 x87 registers and the user specified -mno-80387. */
5129 if (!TARGET_80387 && in_return)
5130 for (i = 0; i < n; i++)
5131 if (regclass[i] == X86_64_X87_CLASS
5132 || regclass[i] == X86_64_X87UP_CLASS
5133 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5135 if (!issued_x87_ret_error)
5137 error ("x87 register return with x87 disabled");
5138 issued_x87_ret_error = true;
5143 /* First construct simple cases. Avoid SCmode, since we want to use
5144 single register to pass this type. */
5145 if (n == 1 && mode != SCmode)
5146 switch (regclass[0])
5148 case X86_64_INTEGER_CLASS:
5149 case X86_64_INTEGERSI_CLASS:
5150 return gen_rtx_REG (mode, intreg[0]);
5151 case X86_64_SSE_CLASS:
5152 case X86_64_SSESF_CLASS:
5153 case X86_64_SSEDF_CLASS:
5154 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
5155 case X86_64_X87_CLASS:
5156 case X86_64_COMPLEX_X87_CLASS:
5157 return gen_rtx_REG (mode, FIRST_STACK_REG);
5158 case X86_64_NO_CLASS:
5159 /* Zero sized array, struct or class. */
5164 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5165 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5166 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5169 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5170 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5171 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5172 && regclass[1] == X86_64_INTEGER_CLASS
5173 && (mode == CDImode || mode == TImode || mode == TFmode)
5174 && intreg[0] + 1 == intreg[1])
5175 return gen_rtx_REG (mode, intreg[0]);
5177 /* Otherwise figure out the entries of the PARALLEL. */
5178 for (i = 0; i < n; i++)
5180 switch (regclass[i])
5182 case X86_64_NO_CLASS:
5184 case X86_64_INTEGER_CLASS:
5185 case X86_64_INTEGERSI_CLASS:
5186 /* Merge TImodes on aligned occasions here too. */
5187 if (i * 8 + 8 > bytes)
5188 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5189 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5193 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5194 if (tmpmode == BLKmode)
5196 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5197 gen_rtx_REG (tmpmode, *intreg),
5201 case X86_64_SSESF_CLASS:
5202 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5203 gen_rtx_REG (SFmode,
5204 SSE_REGNO (sse_regno)),
5208 case X86_64_SSEDF_CLASS:
5209 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5210 gen_rtx_REG (DFmode,
5211 SSE_REGNO (sse_regno)),
5215 case X86_64_SSE_CLASS:
5216 if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
5220 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5221 gen_rtx_REG (tmpmode,
5222 SSE_REGNO (sse_regno)),
5224 if (tmpmode == TImode)
5233 /* Empty aligned struct, union or class. */
5237 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5238 for (i = 0; i < nexps; i++)
5239 XVECEXP (ret, 0, i) = exp [i];
5243 /* Update the data in CUM to advance over an argument of mode MODE
5244 and data type TYPE. (TYPE is null for libcalls where that information
5245 may not be available.) */
5248 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5249 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5265 cum->words += words;
5266 cum->nregs -= words;
5267 cum->regno += words;
5269 if (cum->nregs <= 0)
5277 if (cum->float_in_sse < 2)
5280 if (cum->float_in_sse < 1)
5291 if (!type || !AGGREGATE_TYPE_P (type))
5293 cum->sse_words += words;
5294 cum->sse_nregs -= 1;
5295 cum->sse_regno += 1;
5296 if (cum->sse_nregs <= 0)
5309 if (!type || !AGGREGATE_TYPE_P (type))
5311 cum->mmx_words += words;
5312 cum->mmx_nregs -= 1;
5313 cum->mmx_regno += 1;
5314 if (cum->mmx_nregs <= 0)
5325 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5326 tree type, HOST_WIDE_INT words)
5328 int int_nregs, sse_nregs;
5330 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5331 cum->words += words;
5332 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5334 cum->nregs -= int_nregs;
5335 cum->sse_nregs -= sse_nregs;
5336 cum->regno += int_nregs;
5337 cum->sse_regno += sse_nregs;
5340 cum->words += words;
5344 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5345 HOST_WIDE_INT words)
5347 /* Otherwise, this should be passed indirect. */
5348 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5350 cum->words += words;
5359 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5360 tree type, int named ATTRIBUTE_UNUSED)
5362 HOST_WIDE_INT bytes, words;
5364 if (mode == BLKmode)
5365 bytes = int_size_in_bytes (type);
5367 bytes = GET_MODE_SIZE (mode);
5368 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5371 mode = type_natural_mode (type);
5373 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5374 function_arg_advance_ms_64 (cum, bytes, words);
5375 else if (TARGET_64BIT)
5376 function_arg_advance_64 (cum, mode, type, words);
5378 function_arg_advance_32 (cum, mode, type, bytes, words);
5381 /* Define where to put the arguments to a function.
5382 Value is zero to push the argument on the stack,
5383 or a hard register in which to store the argument.
5385 MODE is the argument's machine mode.
5386 TYPE is the data type of the argument (as a tree).
5387 This is null for libcalls where that information may
5389 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5390 the preceding args and about the function being called.
5391 NAMED is nonzero if this argument is a named parameter
5392 (otherwise it is an extra parameter matching an ellipsis). */
5395 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5396 enum machine_mode orig_mode, tree type,
5397 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5399 static bool warnedsse, warnedmmx;
5401 /* Avoid the AL settings for the Unix64 ABI. */
5402 if (mode == VOIDmode)
5418 if (words <= cum->nregs)
5420 int regno = cum->regno;
5422 /* Fastcall allocates the first two DWORD (SImode) or
5423 smaller arguments to ECX and EDX if it isn't an
5429 || (type && AGGREGATE_TYPE_P (type)))
5432 /* ECX not EAX is the first allocated register. */
5433 if (regno == AX_REG)
5436 return gen_rtx_REG (mode, regno);
5441 if (cum->float_in_sse < 2)
5444 if (cum->float_in_sse < 1)
5454 if (!type || !AGGREGATE_TYPE_P (type))
5456 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5459 warning (0, "SSE vector argument without SSE enabled "
5463 return gen_reg_or_parallel (mode, orig_mode,
5464 cum->sse_regno + FIRST_SSE_REG);
5473 if (!type || !AGGREGATE_TYPE_P (type))
5475 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5478 warning (0, "MMX vector argument without MMX enabled "
5482 return gen_reg_or_parallel (mode, orig_mode,
5483 cum->mmx_regno + FIRST_MMX_REG);
5492 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5493 enum machine_mode orig_mode, tree type)
5495 /* Handle a hidden AL argument containing number of registers
5496 for varargs x86-64 functions. */
5497 if (mode == VOIDmode)
5498 return GEN_INT (cum->maybe_vaarg
5499 ? (cum->sse_nregs < 0
5500 ? (cum->call_abi == DEFAULT_ABI
5502 : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5503 : X64_SSE_REGPARM_MAX))
5507 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5509 &x86_64_int_parameter_registers [cum->regno],
5514 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5515 enum machine_mode orig_mode, int named,
5516 HOST_WIDE_INT bytes)
5520 /* Avoid the AL settings for the Unix64 ABI. */
5521 if (mode == VOIDmode)
5524 /* If we've run out of registers, it goes on the stack. */
5525 if (cum->nregs == 0)
5528 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5530 /* Only floating point modes are passed in anything but integer regs. */
5531 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5534 regno = cum->regno + FIRST_SSE_REG;
5539 /* Unnamed floating parameters are passed in both the
5540 SSE and integer registers. */
5541 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5542 t2 = gen_rtx_REG (mode, regno);
5543 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5544 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5545 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5548 /* Handle aggregated types passed in register. */
5549 if (orig_mode == BLKmode)
5551 if (bytes > 0 && bytes <= 8)
5552 mode = (bytes > 4 ? DImode : SImode);
5553 if (mode == BLKmode)
5557 return gen_reg_or_parallel (mode, orig_mode, regno);
5561 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5562 tree type, int named)
5564 enum machine_mode mode = omode;
5565 HOST_WIDE_INT bytes, words;
5567 if (mode == BLKmode)
5568 bytes = int_size_in_bytes (type);
5570 bytes = GET_MODE_SIZE (mode);
5571 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5573 /* To simplify the code below, represent vector types with a vector mode
5574 even if MMX/SSE are not active. */
5575 if (type && TREE_CODE (type) == VECTOR_TYPE)
5576 mode = type_natural_mode (type);
5578 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5579 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5580 else if (TARGET_64BIT)
5581 return function_arg_64 (cum, mode, omode, type);
5583 return function_arg_32 (cum, mode, omode, type, bytes, words);
5586 /* A C expression that indicates when an argument must be passed by
5587 reference. If nonzero for an argument, a copy of that argument is
5588 made in memory and a pointer to the argument is passed instead of
5589 the argument itself. The pointer is passed in whatever way is
5590 appropriate for passing a pointer to that type. */
5593 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5594 enum machine_mode mode ATTRIBUTE_UNUSED,
5595 const_tree type, bool named ATTRIBUTE_UNUSED)
5597 /* See Windows x64 Software Convention. */
5598 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5600 int msize = (int) GET_MODE_SIZE (mode);
5603 /* Arrays are passed by reference. */
5604 if (TREE_CODE (type) == ARRAY_TYPE)
5607 if (AGGREGATE_TYPE_P (type))
5609 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5610 are passed by reference. */
5611 msize = int_size_in_bytes (type);
5615 /* __m128 is passed by reference. */
5617 case 1: case 2: case 4: case 8:
5623 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
5629 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5632 contains_aligned_value_p (tree type)
5634 enum machine_mode mode = TYPE_MODE (type);
5635 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
5639 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
5641 if (TYPE_ALIGN (type) < 128)
5644 if (AGGREGATE_TYPE_P (type))
5646 /* Walk the aggregates recursively. */
5647 switch (TREE_CODE (type))
5651 case QUAL_UNION_TYPE:
5655 /* Walk all the structure fields. */
5656 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5658 if (TREE_CODE (field) == FIELD_DECL
5659 && contains_aligned_value_p (TREE_TYPE (field)))
5666 /* Just for use if some languages passes arrays by value. */
5667 if (contains_aligned_value_p (TREE_TYPE (type)))
5678 /* Gives the alignment boundary, in bits, of an argument with the
5679 specified mode and type. */
5682 ix86_function_arg_boundary (enum machine_mode mode, tree type)
5687 /* Since canonical type is used for call, we convert it to
5688 canonical type if needed. */
5689 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
5690 type = TYPE_CANONICAL (type);
5691 align = TYPE_ALIGN (type);
5694 align = GET_MODE_ALIGNMENT (mode);
5695 if (align < PARM_BOUNDARY)
5696 align = PARM_BOUNDARY;
5697 /* In 32bit, only _Decimal128 and __float128 are aligned to their
5698 natural boundaries. */
5699 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
5701 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
5702 make an exception for SSE modes since these require 128bit
5705 The handling here differs from field_alignment. ICC aligns MMX
5706 arguments to 4 byte boundaries, while structure fields are aligned
5707 to 8 byte boundaries. */
5710 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
5711 align = PARM_BOUNDARY;
5715 if (!contains_aligned_value_p (type))
5716 align = PARM_BOUNDARY;
5719 if (align > BIGGEST_ALIGNMENT)
5720 align = BIGGEST_ALIGNMENT;
5724 /* Return true if N is a possible register number of function value. */
5727 ix86_function_value_regno_p (int regno)
5734 case FIRST_FLOAT_REG:
5735 /* TODO: The function should depend on current function ABI but
5736 builtins.c would need updating then. Therefore we use the
5738 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
5740 return TARGET_FLOAT_RETURNS_IN_80387;
5746 if (TARGET_MACHO || TARGET_64BIT)
5754 /* Define how to find the value returned by a function.
5755 VALTYPE is the data type of the value (as a tree).
5756 If the precise function being called is known, FUNC is its FUNCTION_DECL;
5757 otherwise, FUNC is 0. */
5760 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
5761 const_tree fntype, const_tree fn)
5765 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
5766 we normally prevent this case when mmx is not available. However
5767 some ABIs may require the result to be returned like DImode. */
5768 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
5769 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
5771 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
5772 we prevent this case when sse is not available. However some ABIs
5773 may require the result to be returned like integer TImode. */
5774 else if (mode == TImode
5775 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
5776 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
5778 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
5779 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
5780 regno = FIRST_FLOAT_REG;
5782 /* Most things go in %eax. */
5785 /* Override FP return register with %xmm0 for local functions when
5786 SSE math is enabled or for functions with sseregparm attribute. */
5787 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
5789 int sse_level = ix86_function_sseregparm (fntype, fn, false);
5790 if ((sse_level >= 1 && mode == SFmode)
5791 || (sse_level == 2 && mode == DFmode))
5792 regno = FIRST_SSE_REG;
5795 return gen_rtx_REG (orig_mode, regno);
5799 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
5804 /* Handle libcalls, which don't provide a type node. */
5805 if (valtype == NULL)
5817 return gen_rtx_REG (mode, FIRST_SSE_REG);
5820 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
5824 return gen_rtx_REG (mode, AX_REG);
5828 ret = construct_container (mode, orig_mode, valtype, 1,
5829 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
5830 x86_64_int_return_registers, 0);
5832 /* For zero sized structures, construct_container returns NULL, but we
5833 need to keep rest of compiler happy by returning meaningful value. */
5835 ret = gen_rtx_REG (orig_mode, AX_REG);
5841 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
5843 unsigned int regno = AX_REG;
5847 switch (GET_MODE_SIZE (mode))
5850 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
5851 && !COMPLEX_MODE_P (mode))
5852 regno = FIRST_SSE_REG;
5856 if (mode == SFmode || mode == DFmode)
5857 regno = FIRST_SSE_REG;
5863 return gen_rtx_REG (orig_mode, regno);
5867 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
5868 enum machine_mode orig_mode, enum machine_mode mode)
5870 const_tree fn, fntype;
5873 if (fntype_or_decl && DECL_P (fntype_or_decl))
5874 fn = fntype_or_decl;
5875 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
5877 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
5878 return function_value_ms_64 (orig_mode, mode);
5879 else if (TARGET_64BIT)
5880 return function_value_64 (orig_mode, mode, valtype);
5882 return function_value_32 (orig_mode, mode, fntype, fn);
5886 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
5887 bool outgoing ATTRIBUTE_UNUSED)
5889 enum machine_mode mode, orig_mode;
5891 orig_mode = TYPE_MODE (valtype);
5892 mode = type_natural_mode (valtype);
5893 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
5897 ix86_libcall_value (enum machine_mode mode)
5899 return ix86_function_value_1 (NULL, NULL, mode, mode);
5902 /* Return true iff type is returned in memory. */
5904 static int ATTRIBUTE_UNUSED
5905 return_in_memory_32 (const_tree type, enum machine_mode mode)
5909 if (mode == BLKmode)
5912 size = int_size_in_bytes (type);
5914 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
5917 if (VECTOR_MODE_P (mode) || mode == TImode)
5919 /* User-created vectors small enough to fit in EAX. */
5923 /* MMX/3dNow values are returned in MM0,
5924 except when it doesn't exits. */
5926 return (TARGET_MMX ? 0 : 1);
5928 /* SSE values are returned in XMM0, except when it doesn't exist. */
5930 return (TARGET_SSE ? 0 : 1);
5941 static int ATTRIBUTE_UNUSED
5942 return_in_memory_64 (const_tree type, enum machine_mode mode)
5944 int needed_intregs, needed_sseregs;
5945 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
5948 static int ATTRIBUTE_UNUSED
5949 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
5951 HOST_WIDE_INT size = int_size_in_bytes (type);
5953 /* __m128 is returned in xmm0. */
5954 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
5955 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
5958 /* Otherwise, the size must be exactly in [1248]. */
5959 return (size != 1 && size != 2 && size != 4 && size != 8);
5963 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5965 #ifdef SUBTARGET_RETURN_IN_MEMORY
5966 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
5968 const enum machine_mode mode = type_natural_mode (type);
5970 if (TARGET_64BIT_MS_ABI)
5971 return return_in_memory_ms_64 (type, mode);
5972 else if (TARGET_64BIT)
5973 return return_in_memory_64 (type, mode);
5975 return return_in_memory_32 (type, mode);
5979 /* Return false iff TYPE is returned in memory. This version is used
5980 on Solaris 10. It is similar to the generic ix86_return_in_memory,
5981 but differs notably in that when MMX is available, 8-byte vectors
5982 are returned in memory, rather than in MMX registers. */
5985 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5988 enum machine_mode mode = type_natural_mode (type);
5991 return return_in_memory_64 (type, mode);
5993 if (mode == BLKmode)
5996 size = int_size_in_bytes (type);
5998 if (VECTOR_MODE_P (mode))
6000 /* Return in memory only if MMX registers *are* available. This
6001 seems backwards, but it is consistent with the existing
6008 else if (mode == TImode)
6010 else if (mode == XFmode)
6016 /* When returning SSE vector types, we have a choice of either
6017 (1) being abi incompatible with a -march switch, or
6018 (2) generating an error.
6019 Given no good solution, I think the safest thing is one warning.
6020 The user won't be able to use -Werror, but....
6022 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6023 called in response to actually generating a caller or callee that
6024 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6025 via aggregate_value_p for general type probing from tree-ssa. */
6028 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6030 static bool warnedsse, warnedmmx;
6032 if (!TARGET_64BIT && type)
6034 /* Look at the return type of the function, not the function type. */
6035 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6037 if (!TARGET_SSE && !warnedsse)
6040 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6043 warning (0, "SSE vector return without SSE enabled "
6048 if (!TARGET_MMX && !warnedmmx)
6050 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6053 warning (0, "MMX vector return without MMX enabled "
6063 /* Create the va_list data type. */
6065 /* Returns the calling convention specific va_list date type.
6066 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6069 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6071 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6073 /* For i386 we use plain pointer to argument area. */
6074 if (!TARGET_64BIT || abi == MS_ABI)
6075 return build_pointer_type (char_type_node);
6077 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6078 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6080 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6081 unsigned_type_node);
6082 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6083 unsigned_type_node);
6084 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6086 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6089 va_list_gpr_counter_field = f_gpr;
6090 va_list_fpr_counter_field = f_fpr;
6092 DECL_FIELD_CONTEXT (f_gpr) = record;
6093 DECL_FIELD_CONTEXT (f_fpr) = record;
6094 DECL_FIELD_CONTEXT (f_ovf) = record;
6095 DECL_FIELD_CONTEXT (f_sav) = record;
6097 TREE_CHAIN (record) = type_decl;
6098 TYPE_NAME (record) = type_decl;
6099 TYPE_FIELDS (record) = f_gpr;
6100 TREE_CHAIN (f_gpr) = f_fpr;
6101 TREE_CHAIN (f_fpr) = f_ovf;
6102 TREE_CHAIN (f_ovf) = f_sav;
6104 layout_type (record);
6106 /* The correct type is an array type of one element. */
6107 return build_array_type (record, build_index_type (size_zero_node));
6110 /* Setup the builtin va_list data type and for 64-bit the additional
6111 calling convention specific va_list data types. */
6114 ix86_build_builtin_va_list (void)
6116 tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI);
6118 /* Initialize abi specific va_list builtin types. */
6122 if (DEFAULT_ABI == MS_ABI)
6124 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6125 if (TREE_CODE (t) != RECORD_TYPE)
6126 t = build_variant_type_copy (t);
6127 sysv_va_list_type_node = t;
6132 if (TREE_CODE (t) != RECORD_TYPE)
6133 t = build_variant_type_copy (t);
6134 sysv_va_list_type_node = t;
6136 if (DEFAULT_ABI != MS_ABI)
6138 t = ix86_build_builtin_va_list_abi (MS_ABI);
6139 if (TREE_CODE (t) != RECORD_TYPE)
6140 t = build_variant_type_copy (t);
6141 ms_va_list_type_node = t;
6146 if (TREE_CODE (t) != RECORD_TYPE)
6147 t = build_variant_type_copy (t);
6148 ms_va_list_type_node = t;
6155 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6158 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6167 int regparm = ix86_regparm;
6169 if((cum ? cum->call_abi : ix86_cfun_abi ()) != DEFAULT_ABI)
6170 regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6172 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
6175 /* Indicate to allocate space on the stack for varargs save area. */
6176 ix86_save_varrargs_registers = 1;
6178 save_area = frame_pointer_rtx;
6179 set = get_varargs_alias_set ();
6181 for (i = cum->regno;
6183 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6186 mem = gen_rtx_MEM (Pmode,
6187 plus_constant (save_area, i * UNITS_PER_WORD));
6188 MEM_NOTRAP_P (mem) = 1;
6189 set_mem_alias_set (mem, set);
6190 emit_move_insn (mem, gen_rtx_REG (Pmode,
6191 x86_64_int_parameter_registers[i]));
6194 if (cum->sse_nregs && cfun->va_list_fpr_size)
6196 /* Now emit code to save SSE registers. The AX parameter contains number
6197 of SSE parameter registers used to call this function. We use
6198 sse_prologue_save insn template that produces computed jump across
6199 SSE saves. We need some preparation work to get this working. */
6201 label = gen_label_rtx ();
6202 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6204 /* Compute address to jump to :
6205 label - eax*4 + nnamed_sse_arguments*4 */
6206 tmp_reg = gen_reg_rtx (Pmode);
6207 nsse_reg = gen_reg_rtx (Pmode);
6208 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6209 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6210 gen_rtx_MULT (Pmode, nsse_reg,
6215 gen_rtx_CONST (DImode,
6216 gen_rtx_PLUS (DImode,
6218 GEN_INT (cum->sse_regno * 4))));
6220 emit_move_insn (nsse_reg, label_ref);
6221 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6223 /* Compute address of memory block we save into. We always use pointer
6224 pointing 127 bytes after first byte to store - this is needed to keep
6225 instruction size limited by 4 bytes. */
6226 tmp_reg = gen_reg_rtx (Pmode);
6227 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6228 plus_constant (save_area,
6229 8 * X86_64_REGPARM_MAX + 127)));
6230 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6231 MEM_NOTRAP_P (mem) = 1;
6232 set_mem_alias_set (mem, set);
6233 set_mem_align (mem, BITS_PER_WORD);
6235 /* And finally do the dirty job! */
6236 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6237 GEN_INT (cum->sse_regno), label));
6242 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6244 alias_set_type set = get_varargs_alias_set ();
6247 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6251 mem = gen_rtx_MEM (Pmode,
6252 plus_constant (virtual_incoming_args_rtx,
6253 i * UNITS_PER_WORD));
6254 MEM_NOTRAP_P (mem) = 1;
6255 set_mem_alias_set (mem, set);
6257 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6258 emit_move_insn (mem, reg);
6263 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6264 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6267 CUMULATIVE_ARGS next_cum;
6270 /* This argument doesn't appear to be used anymore. Which is good,
6271 because the old code here didn't suppress rtl generation. */
6272 gcc_assert (!no_rtl);
6277 fntype = TREE_TYPE (current_function_decl);
6279 /* For varargs, we do not want to skip the dummy va_dcl argument.
6280 For stdargs, we do want to skip the last named argument. */
6282 if (stdarg_p (fntype))
6283 function_arg_advance (&next_cum, mode, type, 1);
6285 if ((cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
6286 setup_incoming_varargs_ms_64 (&next_cum);
6288 setup_incoming_varargs_64 (&next_cum);
6291 /* Checks if TYPE is of kind va_list char *. */
6294 is_va_list_char_pointer (tree type)
6298 /* For 32-bit it is always true. */
6301 canonic = ix86_canonical_va_list_type (type);
6302 return (canonic == ms_va_list_type_node
6303 || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node));
6306 /* Implement va_start. */
6309 ix86_va_start (tree valist, rtx nextarg)
6311 HOST_WIDE_INT words, n_gpr, n_fpr;
6312 tree f_gpr, f_fpr, f_ovf, f_sav;
6313 tree gpr, fpr, ovf, sav, t;
6316 /* Only 64bit target needs something special. */
6317 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6319 std_expand_builtin_va_start (valist, nextarg);
6323 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6324 f_fpr = TREE_CHAIN (f_gpr);
6325 f_ovf = TREE_CHAIN (f_fpr);
6326 f_sav = TREE_CHAIN (f_ovf);
6328 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6329 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6330 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6331 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6332 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6334 /* Count number of gp and fp argument registers used. */
6335 words = crtl->args.info.words;
6336 n_gpr = crtl->args.info.regno;
6337 n_fpr = crtl->args.info.sse_regno;
6339 if (cfun->va_list_gpr_size)
6341 type = TREE_TYPE (gpr);
6342 t = build2 (MODIFY_EXPR, type,
6343 gpr, build_int_cst (type, n_gpr * 8));
6344 TREE_SIDE_EFFECTS (t) = 1;
6345 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6348 if (cfun->va_list_fpr_size)
6350 type = TREE_TYPE (fpr);
6351 t = build2 (MODIFY_EXPR, type, fpr,
6352 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6353 TREE_SIDE_EFFECTS (t) = 1;
6354 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6357 /* Find the overflow area. */
6358 type = TREE_TYPE (ovf);
6359 t = make_tree (type, crtl->args.internal_arg_pointer);
6361 t = build2 (POINTER_PLUS_EXPR, type, t,
6362 size_int (words * UNITS_PER_WORD));
6363 t = build2 (MODIFY_EXPR, type, ovf, t);
6364 TREE_SIDE_EFFECTS (t) = 1;
6365 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6367 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
6369 /* Find the register save area.
6370 Prologue of the function save it right above stack frame. */
6371 type = TREE_TYPE (sav);
6372 t = make_tree (type, frame_pointer_rtx);
6373 t = build2 (MODIFY_EXPR, type, sav, t);
6374 TREE_SIDE_EFFECTS (t) = 1;
6375 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6379 /* Implement va_arg. */
6382 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6385 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6386 tree f_gpr, f_fpr, f_ovf, f_sav;
6387 tree gpr, fpr, ovf, sav, t;
6389 tree lab_false, lab_over = NULL_TREE;
6394 enum machine_mode nat_mode;
6397 /* Only 64bit target needs something special. */
6398 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6399 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6401 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6402 f_fpr = TREE_CHAIN (f_gpr);
6403 f_ovf = TREE_CHAIN (f_fpr);
6404 f_sav = TREE_CHAIN (f_ovf);
6406 valist = build_va_arg_indirect_ref (valist);
6407 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6408 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6409 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6410 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6412 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6414 type = build_pointer_type (type);
6415 size = int_size_in_bytes (type);
6416 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6418 nat_mode = type_natural_mode (type);
6419 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
6420 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6423 /* Pull the value out of the saved registers. */
6425 addr = create_tmp_var (ptr_type_node, "addr");
6426 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6430 int needed_intregs, needed_sseregs;
6432 tree int_addr, sse_addr;
6434 lab_false = create_artificial_label ();
6435 lab_over = create_artificial_label ();
6437 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6439 need_temp = (!REG_P (container)
6440 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6441 || TYPE_ALIGN (type) > 128));
6443 /* In case we are passing structure, verify that it is consecutive block
6444 on the register save area. If not we need to do moves. */
6445 if (!need_temp && !REG_P (container))
6447 /* Verify that all registers are strictly consecutive */
6448 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6452 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6454 rtx slot = XVECEXP (container, 0, i);
6455 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6456 || INTVAL (XEXP (slot, 1)) != i * 16)
6464 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6466 rtx slot = XVECEXP (container, 0, i);
6467 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6468 || INTVAL (XEXP (slot, 1)) != i * 8)
6480 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6481 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6482 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6483 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6486 /* First ensure that we fit completely in registers. */
6489 t = build_int_cst (TREE_TYPE (gpr),
6490 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6491 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6492 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6493 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6494 gimplify_and_add (t, pre_p);
6498 t = build_int_cst (TREE_TYPE (fpr),
6499 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6500 + X86_64_REGPARM_MAX * 8);
6501 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6502 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6503 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6504 gimplify_and_add (t, pre_p);
6507 /* Compute index to start of area used for integer regs. */
6510 /* int_addr = gpr + sav; */
6511 t = fold_convert (sizetype, gpr);
6512 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6513 gimplify_assign (int_addr, t, pre_p);
6517 /* sse_addr = fpr + sav; */
6518 t = fold_convert (sizetype, fpr);
6519 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6520 gimplify_assign (sse_addr, t, pre_p);
6525 tree temp = create_tmp_var (type, "va_arg_tmp");
6528 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
6529 gimplify_assign (addr, t, pre_p);
6531 for (i = 0; i < XVECLEN (container, 0); i++)
6533 rtx slot = XVECEXP (container, 0, i);
6534 rtx reg = XEXP (slot, 0);
6535 enum machine_mode mode = GET_MODE (reg);
6536 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
6537 tree addr_type = build_pointer_type (piece_type);
6540 tree dest_addr, dest;
6542 if (SSE_REGNO_P (REGNO (reg)))
6544 src_addr = sse_addr;
6545 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
6549 src_addr = int_addr;
6550 src_offset = REGNO (reg) * 8;
6552 src_addr = fold_convert (addr_type, src_addr);
6553 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
6554 size_int (src_offset));
6555 src = build_va_arg_indirect_ref (src_addr);
6557 dest_addr = fold_convert (addr_type, addr);
6558 dest_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, dest_addr,
6559 size_int (INTVAL (XEXP (slot, 1))));
6560 dest = build_va_arg_indirect_ref (dest_addr);
6562 gimplify_assign (dest, src, pre_p);
6568 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
6569 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
6570 gimplify_assign (gpr, t, pre_p);
6575 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
6576 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
6577 gimplify_assign (fpr, t, pre_p);
6580 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
6582 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
6585 /* ... otherwise out of the overflow area. */
6587 /* When we align parameter on stack for caller, if the parameter
6588 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6589 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6590 here with caller. */
6591 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
6592 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6593 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6595 /* Care for on-stack alignment if needed. */
6596 if (arg_boundary <= 64
6597 || integer_zerop (TYPE_SIZE (type)))
6601 HOST_WIDE_INT align = arg_boundary / 8;
6602 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
6603 size_int (align - 1));
6604 t = fold_convert (sizetype, t);
6605 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6607 t = fold_convert (TREE_TYPE (ovf), t);
6609 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6610 gimplify_assign (addr, t, pre_p);
6612 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
6613 size_int (rsize * UNITS_PER_WORD));
6614 gimplify_assign (unshare_expr (ovf), t, pre_p);
6617 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
6619 ptrtype = build_pointer_type (type);
6620 addr = fold_convert (ptrtype, addr);
6623 addr = build_va_arg_indirect_ref (addr);
6624 return build_va_arg_indirect_ref (addr);
6627 /* Return nonzero if OPNUM's MEM should be matched
6628 in movabs* patterns. */
6631 ix86_check_movabs (rtx insn, int opnum)
6635 set = PATTERN (insn);
6636 if (GET_CODE (set) == PARALLEL)
6637 set = XVECEXP (set, 0, 0);
6638 gcc_assert (GET_CODE (set) == SET);
6639 mem = XEXP (set, opnum);
6640 while (GET_CODE (mem) == SUBREG)
6641 mem = SUBREG_REG (mem);
6642 gcc_assert (MEM_P (mem));
6643 return (volatile_ok || !MEM_VOLATILE_P (mem));
6646 /* Initialize the table of extra 80387 mathematical constants. */
6649 init_ext_80387_constants (void)
6651 static const char * cst[5] =
6653 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
6654 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
6655 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
6656 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
6657 "3.1415926535897932385128089594061862044", /* 4: fldpi */
6661 for (i = 0; i < 5; i++)
6663 real_from_string (&ext_80387_constants_table[i], cst[i]);
6664 /* Ensure each constant is rounded to XFmode precision. */
6665 real_convert (&ext_80387_constants_table[i],
6666 XFmode, &ext_80387_constants_table[i]);
6669 ext_80387_constants_init = 1;
6672 /* Return true if the constant is something that can be loaded with
6673 a special instruction. */
6676 standard_80387_constant_p (rtx x)
6678 enum machine_mode mode = GET_MODE (x);
6682 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
6685 if (x == CONST0_RTX (mode))
6687 if (x == CONST1_RTX (mode))
6690 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6692 /* For XFmode constants, try to find a special 80387 instruction when
6693 optimizing for size or on those CPUs that benefit from them. */
6695 && (optimize_insn_for_size_p () || TARGET_EXT_80387_CONSTANTS))
6699 if (! ext_80387_constants_init)
6700 init_ext_80387_constants ();
6702 for (i = 0; i < 5; i++)
6703 if (real_identical (&r, &ext_80387_constants_table[i]))
6707 /* Load of the constant -0.0 or -1.0 will be split as
6708 fldz;fchs or fld1;fchs sequence. */
6709 if (real_isnegzero (&r))
6711 if (real_identical (&r, &dconstm1))
6717 /* Return the opcode of the special instruction to be used to load
6721 standard_80387_constant_opcode (rtx x)
6723 switch (standard_80387_constant_p (x))
6747 /* Return the CONST_DOUBLE representing the 80387 constant that is
6748 loaded by the specified special instruction. The argument IDX
6749 matches the return value from standard_80387_constant_p. */
6752 standard_80387_constant_rtx (int idx)
6756 if (! ext_80387_constants_init)
6757 init_ext_80387_constants ();
6773 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
6777 /* Return 1 if mode is a valid mode for sse. */
6779 standard_sse_mode_p (enum machine_mode mode)
6796 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
6799 standard_sse_constant_p (rtx x)
6801 enum machine_mode mode = GET_MODE (x);
6803 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
6805 if (vector_all_ones_operand (x, mode)
6806 && standard_sse_mode_p (mode))
6807 return TARGET_SSE2 ? 2 : -1;
6812 /* Return the opcode of the special instruction to be used to load
6816 standard_sse_constant_opcode (rtx insn, rtx x)
6818 switch (standard_sse_constant_p (x))
6821 if (get_attr_mode (insn) == MODE_V4SF)
6822 return "xorps\t%0, %0";
6823 else if (get_attr_mode (insn) == MODE_V2DF)
6824 return "xorpd\t%0, %0";
6826 return "pxor\t%0, %0";
6828 return "pcmpeqd\t%0, %0";
6833 /* Returns 1 if OP contains a symbol reference */
6836 symbolic_reference_mentioned_p (rtx op)
6841 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
6844 fmt = GET_RTX_FORMAT (GET_CODE (op));
6845 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
6851 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
6852 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
6856 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
6863 /* Return 1 if it is appropriate to emit `ret' instructions in the
6864 body of a function. Do this only if the epilogue is simple, needing a
6865 couple of insns. Prior to reloading, we can't tell how many registers
6866 must be saved, so return 0 then. Return 0 if there is no frame
6867 marker to de-allocate. */
6870 ix86_can_use_return_insn_p (void)
6872 struct ix86_frame frame;
6874 if (! reload_completed || frame_pointer_needed)
6877 /* Don't allow more than 32 pop, since that's all we can do
6878 with one instruction. */
6879 if (crtl->args.pops_args
6880 && crtl->args.size >= 32768)
6883 ix86_compute_frame_layout (&frame);
6884 return frame.to_allocate == 0 && frame.nregs == 0;
6887 /* Value should be nonzero if functions must have frame pointers.
6888 Zero means the frame pointer need not be set up (and parms may
6889 be accessed via the stack pointer) in functions that seem suitable. */
6892 ix86_frame_pointer_required (void)
6894 /* If we accessed previous frames, then the generated code expects
6895 to be able to access the saved ebp value in our frame. */
6896 if (cfun->machine->accesses_prev_frame)
6899 /* Several x86 os'es need a frame pointer for other reasons,
6900 usually pertaining to setjmp. */
6901 if (SUBTARGET_FRAME_POINTER_REQUIRED)
6904 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
6905 the frame pointer by default. Turn it back on now if we've not
6906 got a leaf function. */
6907 if (TARGET_OMIT_LEAF_FRAME_POINTER
6908 && (!current_function_is_leaf
6909 || ix86_current_function_calls_tls_descriptor))
6918 /* Record that the current function accesses previous call frames. */
6921 ix86_setup_frame_addresses (void)
6923 cfun->machine->accesses_prev_frame = 1;
6926 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
6927 # define USE_HIDDEN_LINKONCE 1
6929 # define USE_HIDDEN_LINKONCE 0
6932 static int pic_labels_used;
6934 /* Fills in the label name that should be used for a pc thunk for
6935 the given register. */
6938 get_pc_thunk_name (char name[32], unsigned int regno)
6940 gcc_assert (!TARGET_64BIT);
6942 if (USE_HIDDEN_LINKONCE)
6943 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
6945 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
6949 /* This function generates code for -fpic that loads %ebx with
6950 the return address of the caller and then returns. */
6953 ix86_file_end (void)
6958 for (regno = 0; regno < 8; ++regno)
6962 if (! ((pic_labels_used >> regno) & 1))
6965 get_pc_thunk_name (name, regno);
6970 switch_to_section (darwin_sections[text_coal_section]);
6971 fputs ("\t.weak_definition\t", asm_out_file);
6972 assemble_name (asm_out_file, name);
6973 fputs ("\n\t.private_extern\t", asm_out_file);
6974 assemble_name (asm_out_file, name);
6975 fputs ("\n", asm_out_file);
6976 ASM_OUTPUT_LABEL (asm_out_file, name);
6980 if (USE_HIDDEN_LINKONCE)
6984 decl = build_decl (FUNCTION_DECL, get_identifier (name),
6986 TREE_PUBLIC (decl) = 1;
6987 TREE_STATIC (decl) = 1;
6988 DECL_ONE_ONLY (decl) = 1;
6990 (*targetm.asm_out.unique_section) (decl, 0);
6991 switch_to_section (get_named_section (decl, NULL, 0));
6993 (*targetm.asm_out.globalize_label) (asm_out_file, name);
6994 fputs ("\t.hidden\t", asm_out_file);
6995 assemble_name (asm_out_file, name);
6996 fputc ('\n', asm_out_file);
6997 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7001 switch_to_section (text_section);
7002 ASM_OUTPUT_LABEL (asm_out_file, name);
7005 xops[0] = gen_rtx_REG (Pmode, regno);
7006 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7007 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7008 output_asm_insn ("ret", xops);
7011 if (NEED_INDICATE_EXEC_STACK)
7012 file_end_indicate_exec_stack ();
7015 /* Emit code for the SET_GOT patterns. */
7018 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7024 if (TARGET_VXWORKS_RTP && flag_pic)
7026 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7027 xops[2] = gen_rtx_MEM (Pmode,
7028 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7029 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7031 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7032 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7033 an unadorned address. */
7034 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7035 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7036 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7040 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7042 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7044 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7047 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7049 output_asm_insn ("call\t%a2", xops);
7052 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7053 is what will be referenced by the Mach-O PIC subsystem. */
7055 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
7058 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7059 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7062 output_asm_insn ("pop%z0\t%0", xops);
7067 get_pc_thunk_name (name, REGNO (dest));
7068 pic_labels_used |= 1 << REGNO (dest);
7070 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7071 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7072 output_asm_insn ("call\t%X2", xops);
7073 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7074 is what will be referenced by the Mach-O PIC subsystem. */
7077 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
7079 targetm.asm_out.internal_label (asm_out_file, "L",
7080 CODE_LABEL_NUMBER (label));
7087 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7088 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7090 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7095 /* Generate an "push" pattern for input ARG. */
7100 return gen_rtx_SET (VOIDmode,
7102 gen_rtx_PRE_DEC (Pmode,
7103 stack_pointer_rtx)),
7107 /* Return >= 0 if there is an unused call-clobbered register available
7108 for the entire function. */
7111 ix86_select_alt_pic_regnum (void)
7113 if (current_function_is_leaf && !crtl->profile
7114 && !ix86_current_function_calls_tls_descriptor)
7117 /* Can't use the same register for both PIC and DRAP. */
7119 drap = REGNO (crtl->drap_reg);
7122 for (i = 2; i >= 0; --i)
7123 if (i != drap && !df_regs_ever_live_p (i))
7127 return INVALID_REGNUM;
7130 /* Return 1 if we need to save REGNO. */
7132 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7134 if (pic_offset_table_rtx
7135 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7136 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7138 || crtl->calls_eh_return
7139 || crtl->uses_const_pool))
7141 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7146 if (crtl->calls_eh_return && maybe_eh_return)
7151 unsigned test = EH_RETURN_DATA_REGNO (i);
7152 if (test == INVALID_REGNUM)
7160 && regno == REGNO (crtl->drap_reg))
7163 return (df_regs_ever_live_p (regno)
7164 && !call_used_regs[regno]
7165 && !fixed_regs[regno]
7166 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7169 /* Return number of registers to be saved on the stack. */
7172 ix86_nsaved_regs (void)
7177 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
7178 if (ix86_save_reg (regno, true))
7183 /* Given FROM and TO register numbers, say whether this elimination is
7184 allowed. If stack alignment is needed, we can only replace argument
7185 pointer with hard frame pointer, or replace frame pointer with stack
7186 pointer. Otherwise, frame pointer elimination is automatically
7187 handled and all other eliminations are valid. */
7190 ix86_can_eliminate (int from, int to)
7192 if (stack_realign_fp)
7193 return ((from == ARG_POINTER_REGNUM
7194 && to == HARD_FRAME_POINTER_REGNUM)
7195 || (from == FRAME_POINTER_REGNUM
7196 && to == STACK_POINTER_REGNUM));
7198 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7201 /* Return the offset between two registers, one to be eliminated, and the other
7202 its replacement, at the start of a routine. */
7205 ix86_initial_elimination_offset (int from, int to)
7207 struct ix86_frame frame;
7208 ix86_compute_frame_layout (&frame);
7210 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7211 return frame.hard_frame_pointer_offset;
7212 else if (from == FRAME_POINTER_REGNUM
7213 && to == HARD_FRAME_POINTER_REGNUM)
7214 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7217 gcc_assert (to == STACK_POINTER_REGNUM);
7219 if (from == ARG_POINTER_REGNUM)
7220 return frame.stack_pointer_offset;
7222 gcc_assert (from == FRAME_POINTER_REGNUM);
7223 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7227 /* Fill structure ix86_frame about frame of currently computed function. */
7230 ix86_compute_frame_layout (struct ix86_frame *frame)
7232 HOST_WIDE_INT total_size;
7233 unsigned int stack_alignment_needed;
7234 HOST_WIDE_INT offset;
7235 unsigned int preferred_alignment;
7236 HOST_WIDE_INT size = get_frame_size ();
7238 frame->nregs = ix86_nsaved_regs ();
7241 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7242 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7244 gcc_assert (!size || stack_alignment_needed);
7245 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7246 gcc_assert (preferred_alignment <= stack_alignment_needed);
7248 /* During reload iteration the amount of registers saved can change.
7249 Recompute the value as needed. Do not recompute when amount of registers
7250 didn't change as reload does multiple calls to the function and does not
7251 expect the decision to change within single iteration. */
7253 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7255 int count = frame->nregs;
7257 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7258 /* The fast prologue uses move instead of push to save registers. This
7259 is significantly longer, but also executes faster as modern hardware
7260 can execute the moves in parallel, but can't do that for push/pop.
7262 Be careful about choosing what prologue to emit: When function takes
7263 many instructions to execute we may use slow version as well as in
7264 case function is known to be outside hot spot (this is known with
7265 feedback only). Weight the size of function by number of registers
7266 to save as it is cheap to use one or two push instructions but very
7267 slow to use many of them. */
7269 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7270 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7271 || (flag_branch_probabilities
7272 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7273 cfun->machine->use_fast_prologue_epilogue = false;
7275 cfun->machine->use_fast_prologue_epilogue
7276 = !expensive_function_p (count);
7278 if (TARGET_PROLOGUE_USING_MOVE
7279 && cfun->machine->use_fast_prologue_epilogue)
7280 frame->save_regs_using_mov = true;
7282 frame->save_regs_using_mov = false;
7285 /* Skip return address and saved base pointer. */
7286 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7288 frame->hard_frame_pointer_offset = offset;
7290 /* Set offset to aligned because the realigned frame starts from
7292 if (stack_realign_fp)
7293 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7295 /* Register save area */
7296 offset += frame->nregs * UNITS_PER_WORD;
7299 if (ix86_save_varrargs_registers)
7301 offset += X86_64_VARARGS_SIZE;
7302 frame->va_arg_size = X86_64_VARARGS_SIZE;
7305 frame->va_arg_size = 0;
7307 /* Align start of frame for local function. */
7308 frame->padding1 = ((offset + stack_alignment_needed - 1)
7309 & -stack_alignment_needed) - offset;
7311 offset += frame->padding1;
7313 /* Frame pointer points here. */
7314 frame->frame_pointer_offset = offset;
7318 /* Add outgoing arguments area. Can be skipped if we eliminated
7319 all the function calls as dead code.
7320 Skipping is however impossible when function calls alloca. Alloca
7321 expander assumes that last crtl->outgoing_args_size
7322 of stack frame are unused. */
7323 if (ACCUMULATE_OUTGOING_ARGS
7324 && (!current_function_is_leaf || cfun->calls_alloca
7325 || ix86_current_function_calls_tls_descriptor))
7327 offset += crtl->outgoing_args_size;
7328 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7331 frame->outgoing_arguments_size = 0;
7333 /* Align stack boundary. Only needed if we're calling another function
7335 if (!current_function_is_leaf || cfun->calls_alloca
7336 || ix86_current_function_calls_tls_descriptor)
7337 frame->padding2 = ((offset + preferred_alignment - 1)
7338 & -preferred_alignment) - offset;
7340 frame->padding2 = 0;
7342 offset += frame->padding2;
7344 /* We've reached end of stack frame. */
7345 frame->stack_pointer_offset = offset;
7347 /* Size prologue needs to allocate. */
7348 frame->to_allocate =
7349 (size + frame->padding1 + frame->padding2
7350 + frame->outgoing_arguments_size + frame->va_arg_size);
7352 if ((!frame->to_allocate && frame->nregs <= 1)
7353 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7354 frame->save_regs_using_mov = false;
7356 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && current_function_sp_is_unchanging
7357 && current_function_is_leaf
7358 && !ix86_current_function_calls_tls_descriptor)
7360 frame->red_zone_size = frame->to_allocate;
7361 if (frame->save_regs_using_mov)
7362 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7363 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7364 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7367 frame->red_zone_size = 0;
7368 frame->to_allocate -= frame->red_zone_size;
7369 frame->stack_pointer_offset -= frame->red_zone_size;
7371 fprintf (stderr, "\n");
7372 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7373 fprintf (stderr, "size: %ld\n", (long)size);
7374 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7375 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7376 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7377 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7378 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7379 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7380 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7381 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7382 (long)frame->hard_frame_pointer_offset);
7383 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7384 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7385 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7386 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7390 /* Emit code to save registers in the prologue. */
7393 ix86_emit_save_regs (void)
7398 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
7399 if (ix86_save_reg (regno, true))
7401 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7402 RTX_FRAME_RELATED_P (insn) = 1;
7406 /* Emit code to save registers using MOV insns. First register
7407 is restored from POINTER + OFFSET. */
7409 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7414 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7415 if (ix86_save_reg (regno, true))
7417 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7419 gen_rtx_REG (Pmode, regno));
7420 RTX_FRAME_RELATED_P (insn) = 1;
7421 offset += UNITS_PER_WORD;
7425 /* Expand prologue or epilogue stack adjustment.
7426 The pattern exist to put a dependency on all ebp-based memory accesses.
7427 STYLE should be negative if instructions should be marked as frame related,
7428 zero if %r11 register is live and cannot be freely used and positive
7432 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
7437 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
7438 else if (x86_64_immediate_operand (offset, DImode))
7439 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
7443 /* r11 is used by indirect sibcall return as well, set before the
7444 epilogue and used after the epilogue. ATM indirect sibcall
7445 shouldn't be used together with huge frame sizes in one
7446 function because of the frame_size check in sibcall.c. */
7448 r11 = gen_rtx_REG (DImode, R11_REG);
7449 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
7451 RTX_FRAME_RELATED_P (insn) = 1;
7452 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
7456 RTX_FRAME_RELATED_P (insn) = 1;
7459 /* Find an available register to be used as dynamic realign argument
7460 pointer regsiter. Such a register will be written in prologue and
7461 used in begin of body, so it must not be
7462 1. parameter passing register.
7464 We reuse static-chain register if it is available. Otherwise, we
7465 use DI for i386 and R13 for x86-64. We chose R13 since it has
7468 Return: the regno of chosen register. */
7471 find_drap_reg (void)
7473 tree decl = cfun->decl;
7477 /* Use R13 for nested function or function need static chain.
7478 Since function with tail call may use any caller-saved
7479 registers in epilogue, DRAP must not use caller-saved
7480 register in such case. */
7481 if ((decl_function_context (decl)
7482 && !DECL_NO_STATIC_CHAIN (decl))
7483 || crtl->tail_call_emit)
7490 /* Use DI for nested function or function need static chain.
7491 Since function with tail call may use any caller-saved
7492 registers in epilogue, DRAP must not use caller-saved
7493 register in such case. */
7494 if ((decl_function_context (decl)
7495 && !DECL_NO_STATIC_CHAIN (decl))
7496 || crtl->tail_call_emit)
7499 /* Reuse static chain register if it isn't used for parameter
7501 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
7502 && !lookup_attribute ("fastcall",
7503 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
7510 /* Update incoming stack boundary and estimated stack alignment. */
7513 ix86_update_stack_boundary (void)
7515 /* Prefer the one specified at command line. */
7516 ix86_incoming_stack_boundary
7517 = (ix86_user_incoming_stack_boundary
7518 ? ix86_user_incoming_stack_boundary
7519 : ix86_default_incoming_stack_boundary);
7521 /* Incoming stack alignment can be changed on individual functions
7522 via force_align_arg_pointer attribute. We use the smallest
7523 incoming stack boundary. */
7524 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
7525 && lookup_attribute (ix86_force_align_arg_pointer_string,
7526 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
7527 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
7529 /* Stack at entrance of main is aligned by runtime. We use the
7530 smallest incoming stack boundary. */
7531 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
7532 && DECL_NAME (current_function_decl)
7533 && MAIN_NAME_P (DECL_NAME (current_function_decl))
7534 && DECL_FILE_SCOPE_P (current_function_decl))
7535 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
7537 /* x86_64 vararg needs 16byte stack alignment for register save
7541 && crtl->stack_alignment_estimated < 128)
7542 crtl->stack_alignment_estimated = 128;
7545 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
7546 needed or an rtx for DRAP otherwise. */
7549 ix86_get_drap_rtx (void)
7551 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
7552 crtl->need_drap = true;
7554 if (stack_realign_drap)
7556 /* Assign DRAP to vDRAP and returns vDRAP */
7557 unsigned int regno = find_drap_reg ();
7562 arg_ptr = gen_rtx_REG (Pmode, regno);
7563 crtl->drap_reg = arg_ptr;
7566 drap_vreg = copy_to_reg (arg_ptr);
7570 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
7571 RTX_FRAME_RELATED_P (insn) = 1;
7578 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
7581 ix86_internal_arg_pointer (void)
7583 return virtual_incoming_args_rtx;
7586 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
7587 This is called from dwarf2out.c to emit call frame instructions
7588 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
7590 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
7592 rtx unspec = SET_SRC (pattern);
7593 gcc_assert (GET_CODE (unspec) == UNSPEC);
7597 case UNSPEC_REG_SAVE:
7598 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
7599 SET_DEST (pattern));
7601 case UNSPEC_DEF_CFA:
7602 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
7603 INTVAL (XVECEXP (unspec, 0, 0)));
7610 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
7611 to be generated in correct form. */
7613 ix86_finalize_stack_realign_flags (void)
7615 /* Check if stack realign is really needed after reload, and
7616 stores result in cfun */
7617 unsigned int incoming_stack_boundary
7618 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
7619 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
7620 unsigned int stack_realign = (incoming_stack_boundary
7621 < (current_function_is_leaf
7622 ? crtl->max_used_stack_slot_alignment
7623 : crtl->stack_alignment_needed));
7625 if (crtl->stack_realign_finalized)
7627 /* After stack_realign_needed is finalized, we can't no longer
7629 gcc_assert (crtl->stack_realign_needed == stack_realign);
7633 crtl->stack_realign_needed = stack_realign;
7634 crtl->stack_realign_finalized = true;
7638 /* Expand the prologue into a bunch of separate insns. */
7641 ix86_expand_prologue (void)
7645 struct ix86_frame frame;
7646 HOST_WIDE_INT allocate;
7648 ix86_finalize_stack_realign_flags ();
7650 /* DRAP should not coexist with stack_realign_fp */
7651 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
7653 ix86_compute_frame_layout (&frame);
7655 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
7656 of DRAP is needed and stack realignment is really needed after reload */
7657 if (crtl->drap_reg && crtl->stack_realign_needed)
7660 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
7661 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
7662 ? 0 : UNITS_PER_WORD);
7664 gcc_assert (stack_realign_drap);
7666 /* Grab the argument pointer. */
7667 x = plus_constant (stack_pointer_rtx,
7668 (UNITS_PER_WORD + param_ptr_offset));
7671 /* Only need to push parameter pointer reg if it is caller
7673 if (!call_used_regs[REGNO (crtl->drap_reg)])
7675 /* Push arg pointer reg */
7676 insn = emit_insn (gen_push (y));
7677 RTX_FRAME_RELATED_P (insn) = 1;
7680 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
7681 RTX_FRAME_RELATED_P (insn) = 1;
7683 /* Align the stack. */
7684 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
7686 GEN_INT (-align_bytes)));
7687 RTX_FRAME_RELATED_P (insn) = 1;
7689 /* Replicate the return address on the stack so that return
7690 address can be reached via (argp - 1) slot. This is needed
7691 to implement macro RETURN_ADDR_RTX and intrinsic function
7692 expand_builtin_return_addr etc. */
7694 x = gen_frame_mem (Pmode,
7695 plus_constant (x, -UNITS_PER_WORD));
7696 insn = emit_insn (gen_push (x));
7697 RTX_FRAME_RELATED_P (insn) = 1;
7700 /* Note: AT&T enter does NOT have reversed args. Enter is probably
7701 slower on all targets. Also sdb doesn't like it. */
7703 if (frame_pointer_needed)
7705 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
7706 RTX_FRAME_RELATED_P (insn) = 1;
7708 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7709 RTX_FRAME_RELATED_P (insn) = 1;
7712 if (stack_realign_fp)
7714 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
7715 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
7717 /* Align the stack. */
7718 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
7720 GEN_INT (-align_bytes)));
7721 RTX_FRAME_RELATED_P (insn) = 1;
7724 allocate = frame.to_allocate;
7726 if (!frame.save_regs_using_mov)
7727 ix86_emit_save_regs ();
7729 allocate += frame.nregs * UNITS_PER_WORD;
7731 /* When using red zone we may start register saving before allocating
7732 the stack frame saving one cycle of the prologue. However I will
7733 avoid doing this if I am going to have to probe the stack since
7734 at least on x86_64 the stack probe can turn into a call that clobbers
7735 a red zone location */
7736 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
7737 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
7738 ix86_emit_save_regs_using_mov ((frame_pointer_needed
7739 && !crtl->stack_realign_needed)
7740 ? hard_frame_pointer_rtx
7741 : stack_pointer_rtx,
7742 -frame.nregs * UNITS_PER_WORD);
7746 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
7747 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
7748 GEN_INT (-allocate), -1);
7751 /* Only valid for Win32. */
7752 rtx eax = gen_rtx_REG (Pmode, AX_REG);
7756 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
7758 if (cfun->machine->call_abi == MS_ABI)
7761 eax_live = ix86_eax_live_at_start_p ();
7765 emit_insn (gen_push (eax));
7766 allocate -= UNITS_PER_WORD;
7769 emit_move_insn (eax, GEN_INT (allocate));
7772 insn = gen_allocate_stack_worker_64 (eax);
7774 insn = gen_allocate_stack_worker_32 (eax);
7775 insn = emit_insn (insn);
7776 RTX_FRAME_RELATED_P (insn) = 1;
7777 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
7778 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
7779 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7780 t, REG_NOTES (insn));
7784 if (frame_pointer_needed)
7785 t = plus_constant (hard_frame_pointer_rtx,
7788 - frame.nregs * UNITS_PER_WORD);
7790 t = plus_constant (stack_pointer_rtx, allocate);
7791 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
7795 if (frame.save_regs_using_mov
7796 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
7797 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
7799 if (!frame_pointer_needed
7800 || !frame.to_allocate
7801 || crtl->stack_realign_needed)
7802 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
7805 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
7806 -frame.nregs * UNITS_PER_WORD);
7809 pic_reg_used = false;
7810 if (pic_offset_table_rtx
7811 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7814 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
7816 if (alt_pic_reg_used != INVALID_REGNUM)
7817 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
7819 pic_reg_used = true;
7826 if (ix86_cmodel == CM_LARGE_PIC)
7828 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
7829 rtx label = gen_label_rtx ();
7831 LABEL_PRESERVE_P (label) = 1;
7832 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
7833 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
7834 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
7835 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
7836 pic_offset_table_rtx, tmp_reg));
7839 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
7842 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
7845 /* Prevent function calls from being scheduled before the call to mcount.
7846 In the pic_reg_used case, make sure that the got load isn't deleted. */
7850 emit_insn (gen_prologue_use (pic_offset_table_rtx));
7851 emit_insn (gen_blockage ());
7854 if (crtl->drap_reg && !crtl->stack_realign_needed)
7856 /* vDRAP is setup but after reload it turns out stack realign
7857 isn't necessary, here we will emit prologue to setup DRAP
7858 without stack realign adjustment */
7859 int drap_bp_offset = UNITS_PER_WORD * 2;
7860 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
7861 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
7864 /* Emit cld instruction if stringops are used in the function. */
7865 if (TARGET_CLD && ix86_current_function_needs_cld)
7866 emit_insn (gen_cld ());
7869 /* Emit code to restore saved registers using MOV insns. First register
7870 is restored from POINTER + OFFSET. */
7872 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
7873 int maybe_eh_return)
7876 rtx base_address = gen_rtx_MEM (Pmode, pointer);
7878 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7879 if (ix86_save_reg (regno, maybe_eh_return))
7881 /* Ensure that adjust_address won't be forced to produce pointer
7882 out of range allowed by x86-64 instruction set. */
7883 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
7887 r11 = gen_rtx_REG (DImode, R11_REG);
7888 emit_move_insn (r11, GEN_INT (offset));
7889 emit_insn (gen_adddi3 (r11, r11, pointer));
7890 base_address = gen_rtx_MEM (Pmode, r11);
7893 emit_move_insn (gen_rtx_REG (Pmode, regno),
7894 adjust_address (base_address, Pmode, offset));
7895 offset += UNITS_PER_WORD;
7899 /* Restore function stack, frame, and registers. */
7902 ix86_expand_epilogue (int style)
7906 struct ix86_frame frame;
7907 HOST_WIDE_INT offset;
7909 ix86_finalize_stack_realign_flags ();
7911 /* When stack is realigned, SP must be valid. */
7912 sp_valid = (!frame_pointer_needed
7913 || current_function_sp_is_unchanging
7914 || stack_realign_fp);
7916 ix86_compute_frame_layout (&frame);
7918 /* Calculate start of saved registers relative to ebp. Special care
7919 must be taken for the normal return case of a function using
7920 eh_return: the eax and edx registers are marked as saved, but not
7921 restored along this path. */
7922 offset = frame.nregs;
7923 if (crtl->calls_eh_return && style != 2)
7925 offset *= -UNITS_PER_WORD;
7927 /* If we're only restoring one register and sp is not valid then
7928 using a move instruction to restore the register since it's
7929 less work than reloading sp and popping the register.
7931 The default code result in stack adjustment using add/lea instruction,
7932 while this code results in LEAVE instruction (or discrete equivalent),
7933 so it is profitable in some other cases as well. Especially when there
7934 are no registers to restore. We also use this code when TARGET_USE_LEAVE
7935 and there is exactly one register to pop. This heuristic may need some
7936 tuning in future. */
7937 if ((!sp_valid && frame.nregs <= 1)
7938 || (TARGET_EPILOGUE_USING_MOVE
7939 && cfun->machine->use_fast_prologue_epilogue
7940 && (frame.nregs > 1 || frame.to_allocate))
7941 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
7942 || (frame_pointer_needed && TARGET_USE_LEAVE
7943 && cfun->machine->use_fast_prologue_epilogue
7944 && frame.nregs == 1)
7945 || crtl->calls_eh_return)
7947 /* Restore registers. We can use ebp or esp to address the memory
7948 locations. If both are available, default to ebp, since offsets
7949 are known to be small. Only exception is esp pointing directly
7950 to the end of block of saved registers, where we may simplify
7953 If we are realigning stack with bp and sp, regs restore can't
7954 be addressed by bp. sp must be used instead. */
7956 if (!frame_pointer_needed
7957 || (sp_valid && !frame.to_allocate)
7958 || stack_realign_fp)
7959 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
7960 frame.to_allocate, style == 2);
7962 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
7963 offset, style == 2);
7965 /* eh_return epilogues need %ecx added to the stack pointer. */
7968 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
7970 /* Stack align doesn't work with eh_return. */
7971 gcc_assert (!crtl->stack_realign_needed);
7973 if (frame_pointer_needed)
7975 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
7976 tmp = plus_constant (tmp, UNITS_PER_WORD);
7977 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
7979 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
7980 emit_move_insn (hard_frame_pointer_rtx, tmp);
7982 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
7987 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
7988 tmp = plus_constant (tmp, (frame.to_allocate
7989 + frame.nregs * UNITS_PER_WORD));
7990 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
7993 else if (!frame_pointer_needed)
7994 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
7995 GEN_INT (frame.to_allocate
7996 + frame.nregs * UNITS_PER_WORD),
7998 /* If not an i386, mov & pop is faster than "leave". */
7999 else if (TARGET_USE_LEAVE || optimize_size
8000 || !cfun->machine->use_fast_prologue_epilogue)
8001 emit_insn ((*ix86_gen_leave) ());
8004 pro_epilogue_adjust_stack (stack_pointer_rtx,
8005 hard_frame_pointer_rtx,
8008 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8013 /* First step is to deallocate the stack frame so that we can
8016 If we realign stack with frame pointer, then stack pointer
8017 won't be able to recover via lea $offset(%bp), %sp, because
8018 there is a padding area between bp and sp for realign.
8019 "add $to_allocate, %sp" must be used instead. */
8022 gcc_assert (frame_pointer_needed);
8023 gcc_assert (!stack_realign_fp);
8024 pro_epilogue_adjust_stack (stack_pointer_rtx,
8025 hard_frame_pointer_rtx,
8026 GEN_INT (offset), style);
8028 else if (frame.to_allocate)
8029 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8030 GEN_INT (frame.to_allocate), style);
8032 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8033 if (ix86_save_reg (regno, false))
8034 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8035 if (frame_pointer_needed)
8037 /* Leave results in shorter dependency chains on CPUs that are
8038 able to grok it fast. */
8039 if (TARGET_USE_LEAVE)
8040 emit_insn ((*ix86_gen_leave) ());
8043 /* For stack realigned really happens, recover stack
8044 pointer to hard frame pointer is a must, if not using
8046 if (stack_realign_fp)
8047 pro_epilogue_adjust_stack (stack_pointer_rtx,
8048 hard_frame_pointer_rtx,
8050 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8055 if (crtl->drap_reg && crtl->stack_realign_needed)
8057 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8058 ? 0 : UNITS_PER_WORD);
8059 gcc_assert (stack_realign_drap);
8060 emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8062 GEN_INT (-(UNITS_PER_WORD
8063 + param_ptr_offset))));
8064 if (!call_used_regs[REGNO (crtl->drap_reg)])
8065 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8069 /* Sibcall epilogues don't want a return instruction. */
8073 if (crtl->args.pops_args && crtl->args.size)
8075 rtx popc = GEN_INT (crtl->args.pops_args);
8077 /* i386 can only pop 64K bytes. If asked to pop more, pop
8078 return address, do explicit add, and jump indirectly to the
8081 if (crtl->args.pops_args >= 65536)
8083 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8085 /* There is no "pascal" calling convention in any 64bit ABI. */
8086 gcc_assert (!TARGET_64BIT);
8088 emit_insn (gen_popsi1 (ecx));
8089 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8090 emit_jump_insn (gen_return_indirect_internal (ecx));
8093 emit_jump_insn (gen_return_pop_internal (popc));
8096 emit_jump_insn (gen_return_internal ());
8099 /* Reset from the function's potential modifications. */
8102 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8103 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8105 if (pic_offset_table_rtx)
8106 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8108 /* Mach-O doesn't support labels at the end of objects, so if
8109 it looks like we might want one, insert a NOP. */
8111 rtx insn = get_last_insn ();
8114 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8115 insn = PREV_INSN (insn);
8119 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8120 fputs ("\tnop\n", file);
8126 /* Extract the parts of an RTL expression that is a valid memory address
8127 for an instruction. Return 0 if the structure of the address is
8128 grossly off. Return -1 if the address contains ASHIFT, so it is not
8129 strictly valid, but still used for computing length of lea instruction. */
8132 ix86_decompose_address (rtx addr, struct ix86_address *out)
8134 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8135 rtx base_reg, index_reg;
8136 HOST_WIDE_INT scale = 1;
8137 rtx scale_rtx = NULL_RTX;
8139 enum ix86_address_seg seg = SEG_DEFAULT;
8141 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8143 else if (GET_CODE (addr) == PLUS)
8153 addends[n++] = XEXP (op, 1);
8156 while (GET_CODE (op) == PLUS);
8161 for (i = n; i >= 0; --i)
8164 switch (GET_CODE (op))
8169 index = XEXP (op, 0);
8170 scale_rtx = XEXP (op, 1);
8174 if (XINT (op, 1) == UNSPEC_TP
8175 && TARGET_TLS_DIRECT_SEG_REFS
8176 && seg == SEG_DEFAULT)
8177 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8206 else if (GET_CODE (addr) == MULT)
8208 index = XEXP (addr, 0); /* index*scale */
8209 scale_rtx = XEXP (addr, 1);
8211 else if (GET_CODE (addr) == ASHIFT)
8215 /* We're called for lea too, which implements ashift on occasion. */
8216 index = XEXP (addr, 0);
8217 tmp = XEXP (addr, 1);
8218 if (!CONST_INT_P (tmp))
8220 scale = INTVAL (tmp);
8221 if ((unsigned HOST_WIDE_INT) scale > 3)
8227 disp = addr; /* displacement */
8229 /* Extract the integral value of scale. */
8232 if (!CONST_INT_P (scale_rtx))
8234 scale = INTVAL (scale_rtx);
8237 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8238 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8240 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8241 if (base_reg && index_reg && scale == 1
8242 && (index_reg == arg_pointer_rtx
8243 || index_reg == frame_pointer_rtx
8244 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8247 tmp = base, base = index, index = tmp;
8248 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8251 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8252 if ((base_reg == hard_frame_pointer_rtx
8253 || base_reg == frame_pointer_rtx
8254 || base_reg == arg_pointer_rtx) && !disp)
8257 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8258 Avoid this by transforming to [%esi+0]. */
8259 if (TARGET_K6 && !optimize_size
8260 && base_reg && !index_reg && !disp
8262 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
8265 /* Special case: encode reg+reg instead of reg*2. */
8266 if (!base && index && scale && scale == 2)
8267 base = index, base_reg = index_reg, scale = 1;
8269 /* Special case: scaling cannot be encoded without base or displacement. */
8270 if (!base && !disp && index && scale != 1)
8282 /* Return cost of the memory address x.
8283 For i386, it is better to use a complex address than let gcc copy
8284 the address into a reg and make a new pseudo. But not if the address
8285 requires to two regs - that would mean more pseudos with longer
8288 ix86_address_cost (rtx x)
8290 struct ix86_address parts;
8292 int ok = ix86_decompose_address (x, &parts);
8296 if (parts.base && GET_CODE (parts.base) == SUBREG)
8297 parts.base = SUBREG_REG (parts.base);
8298 if (parts.index && GET_CODE (parts.index) == SUBREG)
8299 parts.index = SUBREG_REG (parts.index);
8301 /* Attempt to minimize number of registers in the address. */
8303 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8305 && (!REG_P (parts.index)
8306 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8310 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8312 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8313 && parts.base != parts.index)
8316 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8317 since it's predecode logic can't detect the length of instructions
8318 and it degenerates to vector decoded. Increase cost of such
8319 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8320 to split such addresses or even refuse such addresses at all.
8322 Following addressing modes are affected:
8327 The first and last case may be avoidable by explicitly coding the zero in
8328 memory address, but I don't have AMD-K6 machine handy to check this
8332 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8333 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8334 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
8340 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8341 this is used for to form addresses to local data when -fPIC is in
8345 darwin_local_data_pic (rtx disp)
8347 if (GET_CODE (disp) == MINUS)
8349 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
8350 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
8351 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
8353 const char *sym_name = XSTR (XEXP (disp, 1), 0);
8354 if (! strcmp (sym_name, "<pic base>"))
8362 /* Determine if a given RTX is a valid constant. We already know this
8363 satisfies CONSTANT_P. */
8366 legitimate_constant_p (rtx x)
8368 switch (GET_CODE (x))
8373 if (GET_CODE (x) == PLUS)
8375 if (!CONST_INT_P (XEXP (x, 1)))
8380 if (TARGET_MACHO && darwin_local_data_pic (x))
8383 /* Only some unspecs are valid as "constants". */
8384 if (GET_CODE (x) == UNSPEC)
8385 switch (XINT (x, 1))
8390 return TARGET_64BIT;
8393 x = XVECEXP (x, 0, 0);
8394 return (GET_CODE (x) == SYMBOL_REF
8395 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8397 x = XVECEXP (x, 0, 0);
8398 return (GET_CODE (x) == SYMBOL_REF
8399 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
8404 /* We must have drilled down to a symbol. */
8405 if (GET_CODE (x) == LABEL_REF)
8407 if (GET_CODE (x) != SYMBOL_REF)
8412 /* TLS symbols are never valid. */
8413 if (SYMBOL_REF_TLS_MODEL (x))
8416 /* DLLIMPORT symbols are never valid. */
8417 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
8418 && SYMBOL_REF_DLLIMPORT_P (x))
8423 if (GET_MODE (x) == TImode
8424 && x != CONST0_RTX (TImode)
8430 if (x == CONST0_RTX (GET_MODE (x)))
8438 /* Otherwise we handle everything else in the move patterns. */
8442 /* Determine if it's legal to put X into the constant pool. This
8443 is not possible for the address of thread-local symbols, which
8444 is checked above. */
8447 ix86_cannot_force_const_mem (rtx x)
8449 /* We can always put integral constants and vectors in memory. */
8450 switch (GET_CODE (x))
8460 return !legitimate_constant_p (x);
8463 /* Determine if a given RTX is a valid constant address. */
8466 constant_address_p (rtx x)
8468 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
8471 /* Nonzero if the constant value X is a legitimate general operand
8472 when generating PIC code. It is given that flag_pic is on and
8473 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
8476 legitimate_pic_operand_p (rtx x)
8480 switch (GET_CODE (x))
8483 inner = XEXP (x, 0);
8484 if (GET_CODE (inner) == PLUS
8485 && CONST_INT_P (XEXP (inner, 1)))
8486 inner = XEXP (inner, 0);
8488 /* Only some unspecs are valid as "constants". */
8489 if (GET_CODE (inner) == UNSPEC)
8490 switch (XINT (inner, 1))
8495 return TARGET_64BIT;
8497 x = XVECEXP (inner, 0, 0);
8498 return (GET_CODE (x) == SYMBOL_REF
8499 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8507 return legitimate_pic_address_disp_p (x);
8514 /* Determine if a given CONST RTX is a valid memory displacement
8518 legitimate_pic_address_disp_p (rtx disp)
8522 /* In 64bit mode we can allow direct addresses of symbols and labels
8523 when they are not dynamic symbols. */
8526 rtx op0 = disp, op1;
8528 switch (GET_CODE (disp))
8534 if (GET_CODE (XEXP (disp, 0)) != PLUS)
8536 op0 = XEXP (XEXP (disp, 0), 0);
8537 op1 = XEXP (XEXP (disp, 0), 1);
8538 if (!CONST_INT_P (op1)
8539 || INTVAL (op1) >= 16*1024*1024
8540 || INTVAL (op1) < -16*1024*1024)
8542 if (GET_CODE (op0) == LABEL_REF)
8544 if (GET_CODE (op0) != SYMBOL_REF)
8549 /* TLS references should always be enclosed in UNSPEC. */
8550 if (SYMBOL_REF_TLS_MODEL (op0))
8552 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
8553 && ix86_cmodel != CM_LARGE_PIC)
8561 if (GET_CODE (disp) != CONST)
8563 disp = XEXP (disp, 0);
8567 /* We are unsafe to allow PLUS expressions. This limit allowed distance
8568 of GOT tables. We should not need these anyway. */
8569 if (GET_CODE (disp) != UNSPEC
8570 || (XINT (disp, 1) != UNSPEC_GOTPCREL
8571 && XINT (disp, 1) != UNSPEC_GOTOFF
8572 && XINT (disp, 1) != UNSPEC_PLTOFF))
8575 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
8576 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
8582 if (GET_CODE (disp) == PLUS)
8584 if (!CONST_INT_P (XEXP (disp, 1)))
8586 disp = XEXP (disp, 0);
8590 if (TARGET_MACHO && darwin_local_data_pic (disp))
8593 if (GET_CODE (disp) != UNSPEC)
8596 switch (XINT (disp, 1))
8601 /* We need to check for both symbols and labels because VxWorks loads
8602 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
8604 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
8605 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
8607 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
8608 While ABI specify also 32bit relocation but we don't produce it in
8609 small PIC model at all. */
8610 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
8611 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
8613 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
8615 case UNSPEC_GOTTPOFF:
8616 case UNSPEC_GOTNTPOFF:
8617 case UNSPEC_INDNTPOFF:
8620 disp = XVECEXP (disp, 0, 0);
8621 return (GET_CODE (disp) == SYMBOL_REF
8622 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
8624 disp = XVECEXP (disp, 0, 0);
8625 return (GET_CODE (disp) == SYMBOL_REF
8626 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
8628 disp = XVECEXP (disp, 0, 0);
8629 return (GET_CODE (disp) == SYMBOL_REF
8630 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
8636 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
8637 memory address for an instruction. The MODE argument is the machine mode
8638 for the MEM expression that wants to use this address.
8640 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
8641 convert common non-canonical forms to canonical form so that they will
8645 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
8646 rtx addr, int strict)
8648 struct ix86_address parts;
8649 rtx base, index, disp;
8650 HOST_WIDE_INT scale;
8651 const char *reason = NULL;
8652 rtx reason_rtx = NULL_RTX;
8654 if (ix86_decompose_address (addr, &parts) <= 0)
8656 reason = "decomposition failed";
8661 index = parts.index;
8663 scale = parts.scale;
8665 /* Validate base register.
8667 Don't allow SUBREG's that span more than a word here. It can lead to spill
8668 failures when the base is one word out of a two word structure, which is
8669 represented internally as a DImode int. */
8678 else if (GET_CODE (base) == SUBREG
8679 && REG_P (SUBREG_REG (base))
8680 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
8682 reg = SUBREG_REG (base);
8685 reason = "base is not a register";
8689 if (GET_MODE (base) != Pmode)
8691 reason = "base is not in Pmode";
8695 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
8696 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
8698 reason = "base is not valid";
8703 /* Validate index register.
8705 Don't allow SUBREG's that span more than a word here -- same as above. */
8714 else if (GET_CODE (index) == SUBREG
8715 && REG_P (SUBREG_REG (index))
8716 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
8718 reg = SUBREG_REG (index);
8721 reason = "index is not a register";
8725 if (GET_MODE (index) != Pmode)
8727 reason = "index is not in Pmode";
8731 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
8732 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
8734 reason = "index is not valid";
8739 /* Validate scale factor. */
8742 reason_rtx = GEN_INT (scale);
8745 reason = "scale without index";
8749 if (scale != 2 && scale != 4 && scale != 8)
8751 reason = "scale is not a valid multiplier";
8756 /* Validate displacement. */
8761 if (GET_CODE (disp) == CONST
8762 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
8763 switch (XINT (XEXP (disp, 0), 1))
8765 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
8766 used. While ABI specify also 32bit relocations, we don't produce
8767 them at all and use IP relative instead. */
8770 gcc_assert (flag_pic);
8772 goto is_legitimate_pic;
8773 reason = "64bit address unspec";
8776 case UNSPEC_GOTPCREL:
8777 gcc_assert (flag_pic);
8778 goto is_legitimate_pic;
8780 case UNSPEC_GOTTPOFF:
8781 case UNSPEC_GOTNTPOFF:
8782 case UNSPEC_INDNTPOFF:
8788 reason = "invalid address unspec";
8792 else if (SYMBOLIC_CONST (disp)
8796 && MACHOPIC_INDIRECT
8797 && !machopic_operand_p (disp)
8803 if (TARGET_64BIT && (index || base))
8805 /* foo@dtpoff(%rX) is ok. */
8806 if (GET_CODE (disp) != CONST
8807 || GET_CODE (XEXP (disp, 0)) != PLUS
8808 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
8809 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
8810 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
8811 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
8813 reason = "non-constant pic memory reference";
8817 else if (! legitimate_pic_address_disp_p (disp))
8819 reason = "displacement is an invalid pic construct";
8823 /* This code used to verify that a symbolic pic displacement
8824 includes the pic_offset_table_rtx register.
8826 While this is good idea, unfortunately these constructs may
8827 be created by "adds using lea" optimization for incorrect
8836 This code is nonsensical, but results in addressing
8837 GOT table with pic_offset_table_rtx base. We can't
8838 just refuse it easily, since it gets matched by
8839 "addsi3" pattern, that later gets split to lea in the
8840 case output register differs from input. While this
8841 can be handled by separate addsi pattern for this case
8842 that never results in lea, this seems to be easier and
8843 correct fix for crash to disable this test. */
8845 else if (GET_CODE (disp) != LABEL_REF
8846 && !CONST_INT_P (disp)
8847 && (GET_CODE (disp) != CONST
8848 || !legitimate_constant_p (disp))
8849 && (GET_CODE (disp) != SYMBOL_REF
8850 || !legitimate_constant_p (disp)))
8852 reason = "displacement is not constant";
8855 else if (TARGET_64BIT
8856 && !x86_64_immediate_operand (disp, VOIDmode))
8858 reason = "displacement is out of range";
8863 /* Everything looks valid. */
8870 /* Return a unique alias set for the GOT. */
8872 static alias_set_type
8873 ix86_GOT_alias_set (void)
8875 static alias_set_type set = -1;
8877 set = new_alias_set ();
8881 /* Return a legitimate reference for ORIG (an address) using the
8882 register REG. If REG is 0, a new pseudo is generated.
8884 There are two types of references that must be handled:
8886 1. Global data references must load the address from the GOT, via
8887 the PIC reg. An insn is emitted to do this load, and the reg is
8890 2. Static data references, constant pool addresses, and code labels
8891 compute the address as an offset from the GOT, whose base is in
8892 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
8893 differentiate them from global data objects. The returned
8894 address is the PIC reg + an unspec constant.
8896 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
8897 reg also appears in the address. */
8900 legitimize_pic_address (rtx orig, rtx reg)
8907 if (TARGET_MACHO && !TARGET_64BIT)
8910 reg = gen_reg_rtx (Pmode);
8911 /* Use the generic Mach-O PIC machinery. */
8912 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
8916 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
8918 else if (TARGET_64BIT
8919 && ix86_cmodel != CM_SMALL_PIC
8920 && gotoff_operand (addr, Pmode))
8923 /* This symbol may be referenced via a displacement from the PIC
8924 base address (@GOTOFF). */
8926 if (reload_in_progress)
8927 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
8928 if (GET_CODE (addr) == CONST)
8929 addr = XEXP (addr, 0);
8930 if (GET_CODE (addr) == PLUS)
8932 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
8934 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
8937 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
8938 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
8940 tmpreg = gen_reg_rtx (Pmode);
8943 emit_move_insn (tmpreg, new_rtx);
8947 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
8948 tmpreg, 1, OPTAB_DIRECT);
8951 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
8953 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
8955 /* This symbol may be referenced via a displacement from the PIC
8956 base address (@GOTOFF). */
8958 if (reload_in_progress)
8959 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
8960 if (GET_CODE (addr) == CONST)
8961 addr = XEXP (addr, 0);
8962 if (GET_CODE (addr) == PLUS)
8964 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
8966 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
8969 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
8970 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
8971 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
8975 emit_move_insn (reg, new_rtx);
8979 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
8980 /* We can't use @GOTOFF for text labels on VxWorks;
8981 see gotoff_operand. */
8982 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
8984 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
8986 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
8987 return legitimize_dllimport_symbol (addr, true);
8988 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
8989 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
8990 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
8992 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
8993 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
8997 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
8999 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9000 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9001 new_rtx = gen_const_mem (Pmode, new_rtx);
9002 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9005 reg = gen_reg_rtx (Pmode);
9006 /* Use directly gen_movsi, otherwise the address is loaded
9007 into register for CSE. We don't want to CSE this addresses,
9008 instead we CSE addresses from the GOT table, so skip this. */
9009 emit_insn (gen_movsi (reg, new_rtx));
9014 /* This symbol must be referenced via a load from the
9015 Global Offset Table (@GOT). */
9017 if (reload_in_progress)
9018 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9019 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9020 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9022 new_rtx = force_reg (Pmode, new_rtx);
9023 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9024 new_rtx = gen_const_mem (Pmode, new_rtx);
9025 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9028 reg = gen_reg_rtx (Pmode);
9029 emit_move_insn (reg, new_rtx);
9035 if (CONST_INT_P (addr)
9036 && !x86_64_immediate_operand (addr, VOIDmode))
9040 emit_move_insn (reg, addr);
9044 new_rtx = force_reg (Pmode, addr);
9046 else if (GET_CODE (addr) == CONST)
9048 addr = XEXP (addr, 0);
9050 /* We must match stuff we generate before. Assume the only
9051 unspecs that can get here are ours. Not that we could do
9052 anything with them anyway.... */
9053 if (GET_CODE (addr) == UNSPEC
9054 || (GET_CODE (addr) == PLUS
9055 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9057 gcc_assert (GET_CODE (addr) == PLUS);
9059 if (GET_CODE (addr) == PLUS)
9061 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9063 /* Check first to see if this is a constant offset from a @GOTOFF
9064 symbol reference. */
9065 if (gotoff_operand (op0, Pmode)
9066 && CONST_INT_P (op1))
9070 if (reload_in_progress)
9071 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9072 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9074 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9075 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9076 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9080 emit_move_insn (reg, new_rtx);
9086 if (INTVAL (op1) < -16*1024*1024
9087 || INTVAL (op1) >= 16*1024*1024)
9089 if (!x86_64_immediate_operand (op1, Pmode))
9090 op1 = force_reg (Pmode, op1);
9091 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9097 base = legitimize_pic_address (XEXP (addr, 0), reg);
9098 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9099 base == reg ? NULL_RTX : reg);
9101 if (CONST_INT_P (new_rtx))
9102 new_rtx = plus_constant (base, INTVAL (new_rtx));
9105 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9107 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9108 new_rtx = XEXP (new_rtx, 1);
9110 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9118 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9121 get_thread_pointer (int to_reg)
9125 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9129 reg = gen_reg_rtx (Pmode);
9130 insn = gen_rtx_SET (VOIDmode, reg, tp);
9131 insn = emit_insn (insn);
9136 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9137 false if we expect this to be used for a memory address and true if
9138 we expect to load the address into a register. */
9141 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9143 rtx dest, base, off, pic, tp;
9148 case TLS_MODEL_GLOBAL_DYNAMIC:
9149 dest = gen_reg_rtx (Pmode);
9150 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9152 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9154 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9157 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9158 insns = get_insns ();
9161 RTL_CONST_CALL_P (insns) = 1;
9162 emit_libcall_block (insns, dest, rax, x);
9164 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9165 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9167 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9169 if (TARGET_GNU2_TLS)
9171 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9173 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9177 case TLS_MODEL_LOCAL_DYNAMIC:
9178 base = gen_reg_rtx (Pmode);
9179 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9181 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9183 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9186 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9187 insns = get_insns ();
9190 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9191 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9192 RTL_CONST_CALL_P (insns) = 1;
9193 emit_libcall_block (insns, base, rax, note);
9195 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9196 emit_insn (gen_tls_local_dynamic_base_64 (base));
9198 emit_insn (gen_tls_local_dynamic_base_32 (base));
9200 if (TARGET_GNU2_TLS)
9202 rtx x = ix86_tls_module_base ();
9204 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9205 gen_rtx_MINUS (Pmode, x, tp));
9208 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9209 off = gen_rtx_CONST (Pmode, off);
9211 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9213 if (TARGET_GNU2_TLS)
9215 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9217 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9222 case TLS_MODEL_INITIAL_EXEC:
9226 type = UNSPEC_GOTNTPOFF;
9230 if (reload_in_progress)
9231 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9232 pic = pic_offset_table_rtx;
9233 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9235 else if (!TARGET_ANY_GNU_TLS)
9237 pic = gen_reg_rtx (Pmode);
9238 emit_insn (gen_set_got (pic));
9239 type = UNSPEC_GOTTPOFF;
9244 type = UNSPEC_INDNTPOFF;
9247 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9248 off = gen_rtx_CONST (Pmode, off);
9250 off = gen_rtx_PLUS (Pmode, pic, off);
9251 off = gen_const_mem (Pmode, off);
9252 set_mem_alias_set (off, ix86_GOT_alias_set ());
9254 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9256 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9257 off = force_reg (Pmode, off);
9258 return gen_rtx_PLUS (Pmode, base, off);
9262 base = get_thread_pointer (true);
9263 dest = gen_reg_rtx (Pmode);
9264 emit_insn (gen_subsi3 (dest, base, off));
9268 case TLS_MODEL_LOCAL_EXEC:
9269 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9270 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9271 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9272 off = gen_rtx_CONST (Pmode, off);
9274 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9276 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9277 return gen_rtx_PLUS (Pmode, base, off);
9281 base = get_thread_pointer (true);
9282 dest = gen_reg_rtx (Pmode);
9283 emit_insn (gen_subsi3 (dest, base, off));
9294 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9297 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9298 htab_t dllimport_map;
9301 get_dllimport_decl (tree decl)
9303 struct tree_map *h, in;
9307 size_t namelen, prefixlen;
9313 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9315 in.hash = htab_hash_pointer (decl);
9316 in.base.from = decl;
9317 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9318 h = (struct tree_map *) *loc;
9322 *loc = h = GGC_NEW (struct tree_map);
9324 h->base.from = decl;
9325 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9326 DECL_ARTIFICIAL (to) = 1;
9327 DECL_IGNORED_P (to) = 1;
9328 DECL_EXTERNAL (to) = 1;
9329 TREE_READONLY (to) = 1;
9331 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9332 name = targetm.strip_name_encoding (name);
9333 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9334 ? "*__imp_" : "*__imp__";
9335 namelen = strlen (name);
9336 prefixlen = strlen (prefix);
9337 imp_name = (char *) alloca (namelen + prefixlen + 1);
9338 memcpy (imp_name, prefix, prefixlen);
9339 memcpy (imp_name + prefixlen, name, namelen + 1);
9341 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9342 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9343 SET_SYMBOL_REF_DECL (rtl, to);
9344 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
9346 rtl = gen_const_mem (Pmode, rtl);
9347 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
9349 SET_DECL_RTL (to, rtl);
9350 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
9355 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9356 true if we require the result be a register. */
9359 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
9364 gcc_assert (SYMBOL_REF_DECL (symbol));
9365 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
9367 x = DECL_RTL (imp_decl);
9369 x = force_reg (Pmode, x);
9373 /* Try machine-dependent ways of modifying an illegitimate address
9374 to be legitimate. If we find one, return the new, valid address.
9375 This macro is used in only one place: `memory_address' in explow.c.
9377 OLDX is the address as it was before break_out_memory_refs was called.
9378 In some cases it is useful to look at this to decide what needs to be done.
9380 MODE and WIN are passed so that this macro can use
9381 GO_IF_LEGITIMATE_ADDRESS.
9383 It is always safe for this macro to do nothing. It exists to recognize
9384 opportunities to optimize the output.
9386 For the 80386, we handle X+REG by loading X into a register R and
9387 using R+REG. R will go in a general reg and indexing will be used.
9388 However, if REG is a broken-out memory address or multiplication,
9389 nothing needs to be done because REG can certainly go in a general reg.
9391 When -fpic is used, special handling is needed for symbolic references.
9392 See comments by legitimize_pic_address in i386.c for details. */
9395 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
9400 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
9402 return legitimize_tls_address (x, (enum tls_model) log, false);
9403 if (GET_CODE (x) == CONST
9404 && GET_CODE (XEXP (x, 0)) == PLUS
9405 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9406 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
9408 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
9409 (enum tls_model) log, false);
9410 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9413 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9415 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
9416 return legitimize_dllimport_symbol (x, true);
9417 if (GET_CODE (x) == CONST
9418 && GET_CODE (XEXP (x, 0)) == PLUS
9419 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9420 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
9422 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
9423 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9427 if (flag_pic && SYMBOLIC_CONST (x))
9428 return legitimize_pic_address (x, 0);
9430 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
9431 if (GET_CODE (x) == ASHIFT
9432 && CONST_INT_P (XEXP (x, 1))
9433 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
9436 log = INTVAL (XEXP (x, 1));
9437 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
9438 GEN_INT (1 << log));
9441 if (GET_CODE (x) == PLUS)
9443 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
9445 if (GET_CODE (XEXP (x, 0)) == ASHIFT
9446 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9447 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
9450 log = INTVAL (XEXP (XEXP (x, 0), 1));
9451 XEXP (x, 0) = gen_rtx_MULT (Pmode,
9452 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
9453 GEN_INT (1 << log));
9456 if (GET_CODE (XEXP (x, 1)) == ASHIFT
9457 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
9458 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
9461 log = INTVAL (XEXP (XEXP (x, 1), 1));
9462 XEXP (x, 1) = gen_rtx_MULT (Pmode,
9463 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
9464 GEN_INT (1 << log));
9467 /* Put multiply first if it isn't already. */
9468 if (GET_CODE (XEXP (x, 1)) == MULT)
9470 rtx tmp = XEXP (x, 0);
9471 XEXP (x, 0) = XEXP (x, 1);
9476 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
9477 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
9478 created by virtual register instantiation, register elimination, and
9479 similar optimizations. */
9480 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
9483 x = gen_rtx_PLUS (Pmode,
9484 gen_rtx_PLUS (Pmode, XEXP (x, 0),
9485 XEXP (XEXP (x, 1), 0)),
9486 XEXP (XEXP (x, 1), 1));
9490 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
9491 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
9492 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
9493 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
9494 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
9495 && CONSTANT_P (XEXP (x, 1)))
9498 rtx other = NULL_RTX;
9500 if (CONST_INT_P (XEXP (x, 1)))
9502 constant = XEXP (x, 1);
9503 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
9505 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
9507 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
9508 other = XEXP (x, 1);
9516 x = gen_rtx_PLUS (Pmode,
9517 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
9518 XEXP (XEXP (XEXP (x, 0), 1), 0)),
9519 plus_constant (other, INTVAL (constant)));
9523 if (changed && legitimate_address_p (mode, x, FALSE))
9526 if (GET_CODE (XEXP (x, 0)) == MULT)
9529 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
9532 if (GET_CODE (XEXP (x, 1)) == MULT)
9535 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
9539 && REG_P (XEXP (x, 1))
9540 && REG_P (XEXP (x, 0)))
9543 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
9546 x = legitimize_pic_address (x, 0);
9549 if (changed && legitimate_address_p (mode, x, FALSE))
9552 if (REG_P (XEXP (x, 0)))
9554 rtx temp = gen_reg_rtx (Pmode);
9555 rtx val = force_operand (XEXP (x, 1), temp);
9557 emit_move_insn (temp, val);
9563 else if (REG_P (XEXP (x, 1)))
9565 rtx temp = gen_reg_rtx (Pmode);
9566 rtx val = force_operand (XEXP (x, 0), temp);
9568 emit_move_insn (temp, val);
9578 /* Print an integer constant expression in assembler syntax. Addition
9579 and subtraction are the only arithmetic that may appear in these
9580 expressions. FILE is the stdio stream to write to, X is the rtx, and
9581 CODE is the operand print code from the output string. */
9584 output_pic_addr_const (FILE *file, rtx x, int code)
9588 switch (GET_CODE (x))
9591 gcc_assert (flag_pic);
9596 if (! TARGET_MACHO || TARGET_64BIT)
9597 output_addr_const (file, x);
9600 const char *name = XSTR (x, 0);
9602 /* Mark the decl as referenced so that cgraph will
9603 output the function. */
9604 if (SYMBOL_REF_DECL (x))
9605 mark_decl_referenced (SYMBOL_REF_DECL (x));
9608 if (MACHOPIC_INDIRECT
9609 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
9610 name = machopic_indirection_name (x, /*stub_p=*/true);
9612 assemble_name (file, name);
9614 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
9615 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
9616 fputs ("@PLT", file);
9623 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
9624 assemble_name (asm_out_file, buf);
9628 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
9632 /* This used to output parentheses around the expression,
9633 but that does not work on the 386 (either ATT or BSD assembler). */
9634 output_pic_addr_const (file, XEXP (x, 0), code);
9638 if (GET_MODE (x) == VOIDmode)
9640 /* We can use %d if the number is <32 bits and positive. */
9641 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
9642 fprintf (file, "0x%lx%08lx",
9643 (unsigned long) CONST_DOUBLE_HIGH (x),
9644 (unsigned long) CONST_DOUBLE_LOW (x));
9646 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
9649 /* We can't handle floating point constants;
9650 PRINT_OPERAND must handle them. */
9651 output_operand_lossage ("floating constant misused");
9655 /* Some assemblers need integer constants to appear first. */
9656 if (CONST_INT_P (XEXP (x, 0)))
9658 output_pic_addr_const (file, XEXP (x, 0), code);
9660 output_pic_addr_const (file, XEXP (x, 1), code);
9664 gcc_assert (CONST_INT_P (XEXP (x, 1)));
9665 output_pic_addr_const (file, XEXP (x, 1), code);
9667 output_pic_addr_const (file, XEXP (x, 0), code);
9673 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
9674 output_pic_addr_const (file, XEXP (x, 0), code);
9676 output_pic_addr_const (file, XEXP (x, 1), code);
9678 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
9682 gcc_assert (XVECLEN (x, 0) == 1);
9683 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
9684 switch (XINT (x, 1))
9687 fputs ("@GOT", file);
9690 fputs ("@GOTOFF", file);
9693 fputs ("@PLTOFF", file);
9695 case UNSPEC_GOTPCREL:
9696 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
9697 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
9699 case UNSPEC_GOTTPOFF:
9700 /* FIXME: This might be @TPOFF in Sun ld too. */
9701 fputs ("@GOTTPOFF", file);
9704 fputs ("@TPOFF", file);
9708 fputs ("@TPOFF", file);
9710 fputs ("@NTPOFF", file);
9713 fputs ("@DTPOFF", file);
9715 case UNSPEC_GOTNTPOFF:
9717 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
9718 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
9720 fputs ("@GOTNTPOFF", file);
9722 case UNSPEC_INDNTPOFF:
9723 fputs ("@INDNTPOFF", file);
9726 output_operand_lossage ("invalid UNSPEC as operand");
9732 output_operand_lossage ("invalid expression as operand");
9736 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9737 We need to emit DTP-relative relocations. */
9739 static void ATTRIBUTE_UNUSED
9740 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
9742 fputs (ASM_LONG, file);
9743 output_addr_const (file, x);
9744 fputs ("@DTPOFF", file);
9750 fputs (", 0", file);
9757 /* In the name of slightly smaller debug output, and to cater to
9758 general assembler lossage, recognize PIC+GOTOFF and turn it back
9759 into a direct symbol reference.
9761 On Darwin, this is necessary to avoid a crash, because Darwin
9762 has a different PIC label for each routine but the DWARF debugging
9763 information is not associated with any particular routine, so it's
9764 necessary to remove references to the PIC label from RTL stored by
9765 the DWARF output code. */
9768 ix86_delegitimize_address (rtx orig_x)
9771 /* reg_addend is NULL or a multiple of some register. */
9772 rtx reg_addend = NULL_RTX;
9773 /* const_addend is NULL or a const_int. */
9774 rtx const_addend = NULL_RTX;
9775 /* This is the result, or NULL. */
9776 rtx result = NULL_RTX;
9783 if (GET_CODE (x) != CONST
9784 || GET_CODE (XEXP (x, 0)) != UNSPEC
9785 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
9788 return XVECEXP (XEXP (x, 0), 0, 0);
9791 if (GET_CODE (x) != PLUS
9792 || GET_CODE (XEXP (x, 1)) != CONST)
9795 if (REG_P (XEXP (x, 0))
9796 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
9797 /* %ebx + GOT/GOTOFF */
9799 else if (GET_CODE (XEXP (x, 0)) == PLUS)
9801 /* %ebx + %reg * scale + GOT/GOTOFF */
9802 reg_addend = XEXP (x, 0);
9803 if (REG_P (XEXP (reg_addend, 0))
9804 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
9805 reg_addend = XEXP (reg_addend, 1);
9806 else if (REG_P (XEXP (reg_addend, 1))
9807 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
9808 reg_addend = XEXP (reg_addend, 0);
9811 if (!REG_P (reg_addend)
9812 && GET_CODE (reg_addend) != MULT
9813 && GET_CODE (reg_addend) != ASHIFT)
9819 x = XEXP (XEXP (x, 1), 0);
9820 if (GET_CODE (x) == PLUS
9821 && CONST_INT_P (XEXP (x, 1)))
9823 const_addend = XEXP (x, 1);
9827 if (GET_CODE (x) == UNSPEC
9828 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
9829 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
9830 result = XVECEXP (x, 0, 0);
9832 if (TARGET_MACHO && darwin_local_data_pic (x)
9834 result = XEXP (x, 0);
9840 result = gen_rtx_PLUS (Pmode, result, const_addend);
9842 result = gen_rtx_PLUS (Pmode, reg_addend, result);
9846 /* If X is a machine specific address (i.e. a symbol or label being
9847 referenced as a displacement from the GOT implemented using an
9848 UNSPEC), then return the base term. Otherwise return X. */
9851 ix86_find_base_term (rtx x)
9857 if (GET_CODE (x) != CONST)
9860 if (GET_CODE (term) == PLUS
9861 && (CONST_INT_P (XEXP (term, 1))
9862 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
9863 term = XEXP (term, 0);
9864 if (GET_CODE (term) != UNSPEC
9865 || XINT (term, 1) != UNSPEC_GOTPCREL)
9868 term = XVECEXP (term, 0, 0);
9870 if (GET_CODE (term) != SYMBOL_REF
9871 && GET_CODE (term) != LABEL_REF)
9877 term = ix86_delegitimize_address (x);
9879 if (GET_CODE (term) != SYMBOL_REF
9880 && GET_CODE (term) != LABEL_REF)
9887 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
9892 if (mode == CCFPmode || mode == CCFPUmode)
9894 enum rtx_code second_code, bypass_code;
9895 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
9896 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
9897 code = ix86_fp_compare_code_to_integer (code);
9901 code = reverse_condition (code);
9952 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
9956 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
9957 Those same assemblers have the same but opposite lossage on cmov. */
9959 suffix = fp ? "nbe" : "a";
9960 else if (mode == CCCmode)
9983 gcc_assert (mode == CCmode || mode == CCCmode);
10000 gcc_unreachable ();
10004 /* ??? As above. */
10005 gcc_assert (mode == CCmode || mode == CCCmode);
10006 suffix = fp ? "nb" : "ae";
10009 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10013 /* ??? As above. */
10014 if (mode == CCmode)
10016 else if (mode == CCCmode)
10017 suffix = fp ? "nb" : "ae";
10019 gcc_unreachable ();
10022 suffix = fp ? "u" : "p";
10025 suffix = fp ? "nu" : "np";
10028 gcc_unreachable ();
10030 fputs (suffix, file);
10033 /* Print the name of register X to FILE based on its machine mode and number.
10034 If CODE is 'w', pretend the mode is HImode.
10035 If CODE is 'b', pretend the mode is QImode.
10036 If CODE is 'k', pretend the mode is SImode.
10037 If CODE is 'q', pretend the mode is DImode.
10038 If CODE is 'h', pretend the reg is the 'high' byte register.
10039 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
10042 print_reg (rtx x, int code, FILE *file)
10044 gcc_assert (x == pc_rtx
10045 || (REGNO (x) != ARG_POINTER_REGNUM
10046 && REGNO (x) != FRAME_POINTER_REGNUM
10047 && REGNO (x) != FLAGS_REG
10048 && REGNO (x) != FPSR_REG
10049 && REGNO (x) != FPCR_REG));
10051 if (ASSEMBLER_DIALECT == ASM_ATT)
10056 gcc_assert (TARGET_64BIT);
10057 fputs ("rip", file);
10061 if (code == 'w' || MMX_REG_P (x))
10063 else if (code == 'b')
10065 else if (code == 'k')
10067 else if (code == 'q')
10069 else if (code == 'y')
10071 else if (code == 'h')
10074 code = GET_MODE_SIZE (GET_MODE (x));
10076 /* Irritatingly, AMD extended registers use different naming convention
10077 from the normal registers. */
10078 if (REX_INT_REG_P (x))
10080 gcc_assert (TARGET_64BIT);
10084 error ("extended registers have no high halves");
10087 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10090 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10093 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10096 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10099 error ("unsupported operand size for extended register");
10107 if (STACK_TOP_P (x))
10109 fputs ("st(0)", file);
10116 if (! ANY_FP_REG_P (x))
10117 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10122 fputs (hi_reg_name[REGNO (x)], file);
10125 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10127 fputs (qi_reg_name[REGNO (x)], file);
10130 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10132 fputs (qi_high_reg_name[REGNO (x)], file);
10135 gcc_unreachable ();
10139 /* Locate some local-dynamic symbol still in use by this function
10140 so that we can print its name in some tls_local_dynamic_base
10144 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10148 if (GET_CODE (x) == SYMBOL_REF
10149 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10151 cfun->machine->some_ld_name = XSTR (x, 0);
10158 static const char *
10159 get_some_local_dynamic_name (void)
10163 if (cfun->machine->some_ld_name)
10164 return cfun->machine->some_ld_name;
10166 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10168 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10169 return cfun->machine->some_ld_name;
10171 gcc_unreachable ();
10174 /* Meaning of CODE:
10175 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10176 C -- print opcode suffix for set/cmov insn.
10177 c -- like C, but print reversed condition
10178 E,e -- likewise, but for compare-and-branch fused insn.
10179 F,f -- likewise, but for floating-point.
10180 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10182 R -- print the prefix for register names.
10183 z -- print the opcode suffix for the size of the current operand.
10184 * -- print a star (in certain assembler syntax)
10185 A -- print an absolute memory reference.
10186 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10187 s -- print a shift double count, followed by the assemblers argument
10189 b -- print the QImode name of the register for the indicated operand.
10190 %b0 would print %al if operands[0] is reg 0.
10191 w -- likewise, print the HImode name of the register.
10192 k -- likewise, print the SImode name of the register.
10193 q -- likewise, print the DImode name of the register.
10194 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10195 y -- print "st(0)" instead of "st" as a register.
10196 D -- print condition for SSE cmp instruction.
10197 P -- if PIC, print an @PLT suffix.
10198 X -- don't print any sort of PIC '@' suffix for a symbol.
10199 & -- print some in-use local-dynamic symbol name.
10200 H -- print a memory address offset by 8; used for sse high-parts
10201 Y -- print condition for SSE5 com* instruction.
10202 + -- print a branch hint as 'cs' or 'ds' prefix
10203 ; -- print a semicolon (after prefixes due to bug in older gas).
10207 print_operand (FILE *file, rtx x, int code)
10214 if (ASSEMBLER_DIALECT == ASM_ATT)
10219 assemble_name (file, get_some_local_dynamic_name ());
10223 switch (ASSEMBLER_DIALECT)
10230 /* Intel syntax. For absolute addresses, registers should not
10231 be surrounded by braces. */
10235 PRINT_OPERAND (file, x, 0);
10242 gcc_unreachable ();
10245 PRINT_OPERAND (file, x, 0);
10250 if (ASSEMBLER_DIALECT == ASM_ATT)
10255 if (ASSEMBLER_DIALECT == ASM_ATT)
10260 if (ASSEMBLER_DIALECT == ASM_ATT)
10265 if (ASSEMBLER_DIALECT == ASM_ATT)
10270 if (ASSEMBLER_DIALECT == ASM_ATT)
10275 if (ASSEMBLER_DIALECT == ASM_ATT)
10280 /* 387 opcodes don't get size suffixes if the operands are
10282 if (STACK_REG_P (x))
10285 /* Likewise if using Intel opcodes. */
10286 if (ASSEMBLER_DIALECT == ASM_INTEL)
10289 /* This is the size of op from size of operand. */
10290 switch (GET_MODE_SIZE (GET_MODE (x)))
10299 #ifdef HAVE_GAS_FILDS_FISTS
10309 if (GET_MODE (x) == SFmode)
10324 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10328 #ifdef GAS_MNEMONICS
10343 gcc_unreachable ();
10357 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
10359 PRINT_OPERAND (file, x, 0);
10360 fputs (", ", file);
10365 /* Little bit of braindamage here. The SSE compare instructions
10366 does use completely different names for the comparisons that the
10367 fp conditional moves. */
10368 switch (GET_CODE (x))
10372 fputs ("eq", file);
10376 fputs ("lt", file);
10380 fputs ("le", file);
10383 fputs ("unord", file);
10387 fputs ("neq", file);
10391 fputs ("nlt", file);
10395 fputs ("nle", file);
10398 fputs ("ord", file);
10401 gcc_unreachable ();
10405 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10406 if (ASSEMBLER_DIALECT == ASM_ATT)
10408 switch (GET_MODE (x))
10410 case HImode: putc ('w', file); break;
10412 case SFmode: putc ('l', file); break;
10414 case DFmode: putc ('q', file); break;
10415 default: gcc_unreachable ();
10422 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
10425 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10426 if (ASSEMBLER_DIALECT == ASM_ATT)
10429 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
10432 /* Like above, but reverse condition */
10434 /* Check to see if argument to %c is really a constant
10435 and not a condition code which needs to be reversed. */
10436 if (!COMPARISON_P (x))
10438 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
10441 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
10444 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10445 if (ASSEMBLER_DIALECT == ASM_ATT)
10448 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
10452 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
10456 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
10460 /* It doesn't actually matter what mode we use here, as we're
10461 only going to use this for printing. */
10462 x = adjust_address_nv (x, DImode, 8);
10469 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
10472 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
10475 int pred_val = INTVAL (XEXP (x, 0));
10477 if (pred_val < REG_BR_PROB_BASE * 45 / 100
10478 || pred_val > REG_BR_PROB_BASE * 55 / 100)
10480 int taken = pred_val > REG_BR_PROB_BASE / 2;
10481 int cputaken = final_forward_branch_p (current_output_insn) == 0;
10483 /* Emit hints only in the case default branch prediction
10484 heuristics would fail. */
10485 if (taken != cputaken)
10487 /* We use 3e (DS) prefix for taken branches and
10488 2e (CS) prefix for not taken branches. */
10490 fputs ("ds ; ", file);
10492 fputs ("cs ; ", file);
10500 switch (GET_CODE (x))
10503 fputs ("neq", file);
10506 fputs ("eq", file);
10510 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
10514 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
10518 fputs ("le", file);
10522 fputs ("lt", file);
10525 fputs ("unord", file);
10528 fputs ("ord", file);
10531 fputs ("ueq", file);
10534 fputs ("nlt", file);
10537 fputs ("nle", file);
10540 fputs ("ule", file);
10543 fputs ("ult", file);
10546 fputs ("une", file);
10549 gcc_unreachable ();
10555 fputs (" ; ", file);
10562 output_operand_lossage ("invalid operand code '%c'", code);
10567 print_reg (x, code, file);
10569 else if (MEM_P (x))
10571 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
10572 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
10573 && GET_MODE (x) != BLKmode)
10576 switch (GET_MODE_SIZE (GET_MODE (x)))
10578 case 1: size = "BYTE"; break;
10579 case 2: size = "WORD"; break;
10580 case 4: size = "DWORD"; break;
10581 case 8: size = "QWORD"; break;
10582 case 12: size = "XWORD"; break;
10584 if (GET_MODE (x) == XFmode)
10590 gcc_unreachable ();
10593 /* Check for explicit size override (codes 'b', 'w' and 'k') */
10596 else if (code == 'w')
10598 else if (code == 'k')
10601 fputs (size, file);
10602 fputs (" PTR ", file);
10606 /* Avoid (%rip) for call operands. */
10607 if (CONSTANT_ADDRESS_P (x) && code == 'P'
10608 && !CONST_INT_P (x))
10609 output_addr_const (file, x);
10610 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
10611 output_operand_lossage ("invalid constraints for operand");
10613 output_address (x);
10616 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
10621 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10622 REAL_VALUE_TO_TARGET_SINGLE (r, l);
10624 if (ASSEMBLER_DIALECT == ASM_ATT)
10626 fprintf (file, "0x%08lx", (long unsigned int) l);
10629 /* These float cases don't actually occur as immediate operands. */
10630 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
10634 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
10635 fprintf (file, "%s", dstr);
10638 else if (GET_CODE (x) == CONST_DOUBLE
10639 && GET_MODE (x) == XFmode)
10643 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
10644 fprintf (file, "%s", dstr);
10649 /* We have patterns that allow zero sets of memory, for instance.
10650 In 64-bit mode, we should probably support all 8-byte vectors,
10651 since we can in fact encode that into an immediate. */
10652 if (GET_CODE (x) == CONST_VECTOR)
10654 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
10660 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
10662 if (ASSEMBLER_DIALECT == ASM_ATT)
10665 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
10666 || GET_CODE (x) == LABEL_REF)
10668 if (ASSEMBLER_DIALECT == ASM_ATT)
10671 fputs ("OFFSET FLAT:", file);
10674 if (CONST_INT_P (x))
10675 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10677 output_pic_addr_const (file, x, code);
10679 output_addr_const (file, x);
10683 /* Print a memory operand whose address is ADDR. */
10686 print_operand_address (FILE *file, rtx addr)
10688 struct ix86_address parts;
10689 rtx base, index, disp;
10691 int ok = ix86_decompose_address (addr, &parts);
10696 index = parts.index;
10698 scale = parts.scale;
10706 if (ASSEMBLER_DIALECT == ASM_ATT)
10708 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
10711 gcc_unreachable ();
10714 /* Use one byte shorter RIP relative addressing for 64bit mode. */
10715 if (TARGET_64BIT && !base && !index)
10719 if (GET_CODE (disp) == CONST
10720 && GET_CODE (XEXP (disp, 0)) == PLUS
10721 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
10722 symbol = XEXP (XEXP (disp, 0), 0);
10724 if (GET_CODE (symbol) == LABEL_REF
10725 || (GET_CODE (symbol) == SYMBOL_REF
10726 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
10729 if (!base && !index)
10731 /* Displacement only requires special attention. */
10733 if (CONST_INT_P (disp))
10735 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
10736 fputs ("ds:", file);
10737 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
10740 output_pic_addr_const (file, disp, 0);
10742 output_addr_const (file, disp);
10746 if (ASSEMBLER_DIALECT == ASM_ATT)
10751 output_pic_addr_const (file, disp, 0);
10752 else if (GET_CODE (disp) == LABEL_REF)
10753 output_asm_label (disp);
10755 output_addr_const (file, disp);
10760 print_reg (base, 0, file);
10764 print_reg (index, 0, file);
10766 fprintf (file, ",%d", scale);
10772 rtx offset = NULL_RTX;
10776 /* Pull out the offset of a symbol; print any symbol itself. */
10777 if (GET_CODE (disp) == CONST
10778 && GET_CODE (XEXP (disp, 0)) == PLUS
10779 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
10781 offset = XEXP (XEXP (disp, 0), 1);
10782 disp = gen_rtx_CONST (VOIDmode,
10783 XEXP (XEXP (disp, 0), 0));
10787 output_pic_addr_const (file, disp, 0);
10788 else if (GET_CODE (disp) == LABEL_REF)
10789 output_asm_label (disp);
10790 else if (CONST_INT_P (disp))
10793 output_addr_const (file, disp);
10799 print_reg (base, 0, file);
10802 if (INTVAL (offset) >= 0)
10804 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
10808 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
10815 print_reg (index, 0, file);
10817 fprintf (file, "*%d", scale);
10825 output_addr_const_extra (FILE *file, rtx x)
10829 if (GET_CODE (x) != UNSPEC)
10832 op = XVECEXP (x, 0, 0);
10833 switch (XINT (x, 1))
10835 case UNSPEC_GOTTPOFF:
10836 output_addr_const (file, op);
10837 /* FIXME: This might be @TPOFF in Sun ld. */
10838 fputs ("@GOTTPOFF", file);
10841 output_addr_const (file, op);
10842 fputs ("@TPOFF", file);
10844 case UNSPEC_NTPOFF:
10845 output_addr_const (file, op);
10847 fputs ("@TPOFF", file);
10849 fputs ("@NTPOFF", file);
10851 case UNSPEC_DTPOFF:
10852 output_addr_const (file, op);
10853 fputs ("@DTPOFF", file);
10855 case UNSPEC_GOTNTPOFF:
10856 output_addr_const (file, op);
10858 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10859 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
10861 fputs ("@GOTNTPOFF", file);
10863 case UNSPEC_INDNTPOFF:
10864 output_addr_const (file, op);
10865 fputs ("@INDNTPOFF", file);
10875 /* Split one or more DImode RTL references into pairs of SImode
10876 references. The RTL can be REG, offsettable MEM, integer constant, or
10877 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
10878 split and "num" is its length. lo_half and hi_half are output arrays
10879 that parallel "operands". */
10882 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
10886 rtx op = operands[num];
10888 /* simplify_subreg refuse to split volatile memory addresses,
10889 but we still have to handle it. */
10892 lo_half[num] = adjust_address (op, SImode, 0);
10893 hi_half[num] = adjust_address (op, SImode, 4);
10897 lo_half[num] = simplify_gen_subreg (SImode, op,
10898 GET_MODE (op) == VOIDmode
10899 ? DImode : GET_MODE (op), 0);
10900 hi_half[num] = simplify_gen_subreg (SImode, op,
10901 GET_MODE (op) == VOIDmode
10902 ? DImode : GET_MODE (op), 4);
10906 /* Split one or more TImode RTL references into pairs of DImode
10907 references. The RTL can be REG, offsettable MEM, integer constant, or
10908 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
10909 split and "num" is its length. lo_half and hi_half are output arrays
10910 that parallel "operands". */
10913 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
10917 rtx op = operands[num];
10919 /* simplify_subreg refuse to split volatile memory addresses, but we
10920 still have to handle it. */
10923 lo_half[num] = adjust_address (op, DImode, 0);
10924 hi_half[num] = adjust_address (op, DImode, 8);
10928 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
10929 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
10934 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
10935 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
10936 is the expression of the binary operation. The output may either be
10937 emitted here, or returned to the caller, like all output_* functions.
10939 There is no guarantee that the operands are the same mode, as they
10940 might be within FLOAT or FLOAT_EXTEND expressions. */
10942 #ifndef SYSV386_COMPAT
10943 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
10944 wants to fix the assemblers because that causes incompatibility
10945 with gcc. No-one wants to fix gcc because that causes
10946 incompatibility with assemblers... You can use the option of
10947 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
10948 #define SYSV386_COMPAT 1
10952 output_387_binary_op (rtx insn, rtx *operands)
10954 static char buf[30];
10957 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
10959 #ifdef ENABLE_CHECKING
10960 /* Even if we do not want to check the inputs, this documents input
10961 constraints. Which helps in understanding the following code. */
10962 if (STACK_REG_P (operands[0])
10963 && ((REG_P (operands[1])
10964 && REGNO (operands[0]) == REGNO (operands[1])
10965 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
10966 || (REG_P (operands[2])
10967 && REGNO (operands[0]) == REGNO (operands[2])
10968 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
10969 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
10972 gcc_assert (is_sse);
10975 switch (GET_CODE (operands[3]))
10978 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
10979 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
10987 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
10988 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
10996 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
10997 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11005 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11006 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11014 gcc_unreachable ();
11019 strcpy (buf, ssep);
11020 if (GET_MODE (operands[0]) == SFmode)
11021 strcat (buf, "ss\t{%2, %0|%0, %2}");
11023 strcat (buf, "sd\t{%2, %0|%0, %2}");
11028 switch (GET_CODE (operands[3]))
11032 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11034 rtx temp = operands[2];
11035 operands[2] = operands[1];
11036 operands[1] = temp;
11039 /* know operands[0] == operands[1]. */
11041 if (MEM_P (operands[2]))
11047 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11049 if (STACK_TOP_P (operands[0]))
11050 /* How is it that we are storing to a dead operand[2]?
11051 Well, presumably operands[1] is dead too. We can't
11052 store the result to st(0) as st(0) gets popped on this
11053 instruction. Instead store to operands[2] (which I
11054 think has to be st(1)). st(1) will be popped later.
11055 gcc <= 2.8.1 didn't have this check and generated
11056 assembly code that the Unixware assembler rejected. */
11057 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11059 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11063 if (STACK_TOP_P (operands[0]))
11064 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11066 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11071 if (MEM_P (operands[1]))
11077 if (MEM_P (operands[2]))
11083 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11086 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11087 derived assemblers, confusingly reverse the direction of
11088 the operation for fsub{r} and fdiv{r} when the
11089 destination register is not st(0). The Intel assembler
11090 doesn't have this brain damage. Read !SYSV386_COMPAT to
11091 figure out what the hardware really does. */
11092 if (STACK_TOP_P (operands[0]))
11093 p = "{p\t%0, %2|rp\t%2, %0}";
11095 p = "{rp\t%2, %0|p\t%0, %2}";
11097 if (STACK_TOP_P (operands[0]))
11098 /* As above for fmul/fadd, we can't store to st(0). */
11099 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11101 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11106 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11109 if (STACK_TOP_P (operands[0]))
11110 p = "{rp\t%0, %1|p\t%1, %0}";
11112 p = "{p\t%1, %0|rp\t%0, %1}";
11114 if (STACK_TOP_P (operands[0]))
11115 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11117 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11122 if (STACK_TOP_P (operands[0]))
11124 if (STACK_TOP_P (operands[1]))
11125 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11127 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11130 else if (STACK_TOP_P (operands[1]))
11133 p = "{\t%1, %0|r\t%0, %1}";
11135 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11141 p = "{r\t%2, %0|\t%0, %2}";
11143 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11149 gcc_unreachable ();
11156 /* Return needed mode for entity in optimize_mode_switching pass. */
11159 ix86_mode_needed (int entity, rtx insn)
11161 enum attr_i387_cw mode;
11163 /* The mode UNINITIALIZED is used to store control word after a
11164 function call or ASM pattern. The mode ANY specify that function
11165 has no requirements on the control word and make no changes in the
11166 bits we are interested in. */
11169 || (NONJUMP_INSN_P (insn)
11170 && (asm_noperands (PATTERN (insn)) >= 0
11171 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
11172 return I387_CW_UNINITIALIZED;
11174 if (recog_memoized (insn) < 0)
11175 return I387_CW_ANY;
11177 mode = get_attr_i387_cw (insn);
11182 if (mode == I387_CW_TRUNC)
11187 if (mode == I387_CW_FLOOR)
11192 if (mode == I387_CW_CEIL)
11197 if (mode == I387_CW_MASK_PM)
11202 gcc_unreachable ();
11205 return I387_CW_ANY;
11208 /* Output code to initialize control word copies used by trunc?f?i and
11209 rounding patterns. CURRENT_MODE is set to current control word,
11210 while NEW_MODE is set to new control word. */
11213 emit_i387_cw_initialization (int mode)
11215 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
11218 enum ix86_stack_slot slot;
11220 rtx reg = gen_reg_rtx (HImode);
11222 emit_insn (gen_x86_fnstcw_1 (stored_mode));
11223 emit_move_insn (reg, copy_rtx (stored_mode));
11225 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
11229 case I387_CW_TRUNC:
11230 /* round toward zero (truncate) */
11231 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
11232 slot = SLOT_CW_TRUNC;
11235 case I387_CW_FLOOR:
11236 /* round down toward -oo */
11237 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11238 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
11239 slot = SLOT_CW_FLOOR;
11243 /* round up toward +oo */
11244 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11245 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
11246 slot = SLOT_CW_CEIL;
11249 case I387_CW_MASK_PM:
11250 /* mask precision exception for nearbyint() */
11251 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11252 slot = SLOT_CW_MASK_PM;
11256 gcc_unreachable ();
11263 case I387_CW_TRUNC:
11264 /* round toward zero (truncate) */
11265 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
11266 slot = SLOT_CW_TRUNC;
11269 case I387_CW_FLOOR:
11270 /* round down toward -oo */
11271 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
11272 slot = SLOT_CW_FLOOR;
11276 /* round up toward +oo */
11277 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
11278 slot = SLOT_CW_CEIL;
11281 case I387_CW_MASK_PM:
11282 /* mask precision exception for nearbyint() */
11283 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11284 slot = SLOT_CW_MASK_PM;
11288 gcc_unreachable ();
11292 gcc_assert (slot < MAX_386_STACK_LOCALS);
11294 new_mode = assign_386_stack_local (HImode, slot);
11295 emit_move_insn (new_mode, reg);
11298 /* Output code for INSN to convert a float to a signed int. OPERANDS
11299 are the insn operands. The output may be [HSD]Imode and the input
11300 operand may be [SDX]Fmode. */
11303 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
11305 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
11306 int dimode_p = GET_MODE (operands[0]) == DImode;
11307 int round_mode = get_attr_i387_cw (insn);
11309 /* Jump through a hoop or two for DImode, since the hardware has no
11310 non-popping instruction. We used to do this a different way, but
11311 that was somewhat fragile and broke with post-reload splitters. */
11312 if ((dimode_p || fisttp) && !stack_top_dies)
11313 output_asm_insn ("fld\t%y1", operands);
11315 gcc_assert (STACK_TOP_P (operands[1]));
11316 gcc_assert (MEM_P (operands[0]));
11317 gcc_assert (GET_MODE (operands[1]) != TFmode);
11320 output_asm_insn ("fisttp%z0\t%0", operands);
11323 if (round_mode != I387_CW_ANY)
11324 output_asm_insn ("fldcw\t%3", operands);
11325 if (stack_top_dies || dimode_p)
11326 output_asm_insn ("fistp%z0\t%0", operands);
11328 output_asm_insn ("fist%z0\t%0", operands);
11329 if (round_mode != I387_CW_ANY)
11330 output_asm_insn ("fldcw\t%2", operands);
11336 /* Output code for x87 ffreep insn. The OPNO argument, which may only
11337 have the values zero or one, indicates the ffreep insn's operand
11338 from the OPERANDS array. */
11340 static const char *
11341 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
11343 if (TARGET_USE_FFREEP)
11344 #if HAVE_AS_IX86_FFREEP
11345 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
11348 static char retval[] = ".word\t0xc_df";
11349 int regno = REGNO (operands[opno]);
11351 gcc_assert (FP_REGNO_P (regno));
11353 retval[9] = '0' + (regno - FIRST_STACK_REG);
11358 return opno ? "fstp\t%y1" : "fstp\t%y0";
11362 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
11363 should be used. UNORDERED_P is true when fucom should be used. */
11366 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
11368 int stack_top_dies;
11369 rtx cmp_op0, cmp_op1;
11370 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
11374 cmp_op0 = operands[0];
11375 cmp_op1 = operands[1];
11379 cmp_op0 = operands[1];
11380 cmp_op1 = operands[2];
11385 if (GET_MODE (operands[0]) == SFmode)
11387 return "ucomiss\t{%1, %0|%0, %1}";
11389 return "comiss\t{%1, %0|%0, %1}";
11392 return "ucomisd\t{%1, %0|%0, %1}";
11394 return "comisd\t{%1, %0|%0, %1}";
11397 gcc_assert (STACK_TOP_P (cmp_op0));
11399 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
11401 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
11403 if (stack_top_dies)
11405 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
11406 return output_387_ffreep (operands, 1);
11409 return "ftst\n\tfnstsw\t%0";
11412 if (STACK_REG_P (cmp_op1)
11414 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
11415 && REGNO (cmp_op1) != FIRST_STACK_REG)
11417 /* If both the top of the 387 stack dies, and the other operand
11418 is also a stack register that dies, then this must be a
11419 `fcompp' float compare */
11423 /* There is no double popping fcomi variant. Fortunately,
11424 eflags is immune from the fstp's cc clobbering. */
11426 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
11428 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
11429 return output_387_ffreep (operands, 0);
11434 return "fucompp\n\tfnstsw\t%0";
11436 return "fcompp\n\tfnstsw\t%0";
11441 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
11443 static const char * const alt[16] =
11445 "fcom%z2\t%y2\n\tfnstsw\t%0",
11446 "fcomp%z2\t%y2\n\tfnstsw\t%0",
11447 "fucom%z2\t%y2\n\tfnstsw\t%0",
11448 "fucomp%z2\t%y2\n\tfnstsw\t%0",
11450 "ficom%z2\t%y2\n\tfnstsw\t%0",
11451 "ficomp%z2\t%y2\n\tfnstsw\t%0",
11455 "fcomi\t{%y1, %0|%0, %y1}",
11456 "fcomip\t{%y1, %0|%0, %y1}",
11457 "fucomi\t{%y1, %0|%0, %y1}",
11458 "fucomip\t{%y1, %0|%0, %y1}",
11469 mask = eflags_p << 3;
11470 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
11471 mask |= unordered_p << 1;
11472 mask |= stack_top_dies;
11474 gcc_assert (mask < 16);
11483 ix86_output_addr_vec_elt (FILE *file, int value)
11485 const char *directive = ASM_LONG;
11489 directive = ASM_QUAD;
11491 gcc_assert (!TARGET_64BIT);
11494 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
11498 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
11500 const char *directive = ASM_LONG;
11503 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
11504 directive = ASM_QUAD;
11506 gcc_assert (!TARGET_64BIT);
11508 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
11509 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
11510 fprintf (file, "%s%s%d-%s%d\n",
11511 directive, LPREFIX, value, LPREFIX, rel);
11512 else if (HAVE_AS_GOTOFF_IN_DATA)
11513 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
11515 else if (TARGET_MACHO)
11517 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
11518 machopic_output_function_base_name (file);
11519 fprintf(file, "\n");
11523 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
11524 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
11527 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
11531 ix86_expand_clear (rtx dest)
11535 /* We play register width games, which are only valid after reload. */
11536 gcc_assert (reload_completed);
11538 /* Avoid HImode and its attendant prefix byte. */
11539 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
11540 dest = gen_rtx_REG (SImode, REGNO (dest));
11541 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
11543 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
11544 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
11546 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
11547 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
11553 /* X is an unchanging MEM. If it is a constant pool reference, return
11554 the constant pool rtx, else NULL. */
11557 maybe_get_pool_constant (rtx x)
11559 x = ix86_delegitimize_address (XEXP (x, 0));
11561 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
11562 return get_pool_constant (x);
11568 ix86_expand_move (enum machine_mode mode, rtx operands[])
11571 enum tls_model model;
11576 if (GET_CODE (op1) == SYMBOL_REF)
11578 model = SYMBOL_REF_TLS_MODEL (op1);
11581 op1 = legitimize_tls_address (op1, model, true);
11582 op1 = force_operand (op1, op0);
11586 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
11587 && SYMBOL_REF_DLLIMPORT_P (op1))
11588 op1 = legitimize_dllimport_symbol (op1, false);
11590 else if (GET_CODE (op1) == CONST
11591 && GET_CODE (XEXP (op1, 0)) == PLUS
11592 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
11594 rtx addend = XEXP (XEXP (op1, 0), 1);
11595 rtx symbol = XEXP (XEXP (op1, 0), 0);
11598 model = SYMBOL_REF_TLS_MODEL (symbol);
11600 tmp = legitimize_tls_address (symbol, model, true);
11601 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
11602 && SYMBOL_REF_DLLIMPORT_P (symbol))
11603 tmp = legitimize_dllimport_symbol (symbol, true);
11607 tmp = force_operand (tmp, NULL);
11608 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
11609 op0, 1, OPTAB_DIRECT);
11615 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
11617 if (TARGET_MACHO && !TARGET_64BIT)
11622 rtx temp = ((reload_in_progress
11623 || ((op0 && REG_P (op0))
11625 ? op0 : gen_reg_rtx (Pmode));
11626 op1 = machopic_indirect_data_reference (op1, temp);
11627 op1 = machopic_legitimize_pic_address (op1, mode,
11628 temp == op1 ? 0 : temp);
11630 else if (MACHOPIC_INDIRECT)
11631 op1 = machopic_indirect_data_reference (op1, 0);
11639 op1 = force_reg (Pmode, op1);
11640 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
11642 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
11643 op1 = legitimize_pic_address (op1, reg);
11652 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
11653 || !push_operand (op0, mode))
11655 op1 = force_reg (mode, op1);
11657 if (push_operand (op0, mode)
11658 && ! general_no_elim_operand (op1, mode))
11659 op1 = copy_to_mode_reg (mode, op1);
11661 /* Force large constants in 64bit compilation into register
11662 to get them CSEed. */
11663 if (can_create_pseudo_p ()
11664 && (mode == DImode) && TARGET_64BIT
11665 && immediate_operand (op1, mode)
11666 && !x86_64_zext_immediate_operand (op1, VOIDmode)
11667 && !register_operand (op0, mode)
11669 op1 = copy_to_mode_reg (mode, op1);
11671 if (can_create_pseudo_p ()
11672 && FLOAT_MODE_P (mode)
11673 && GET_CODE (op1) == CONST_DOUBLE)
11675 /* If we are loading a floating point constant to a register,
11676 force the value to memory now, since we'll get better code
11677 out the back end. */
11679 op1 = validize_mem (force_const_mem (mode, op1));
11680 if (!register_operand (op0, mode))
11682 rtx temp = gen_reg_rtx (mode);
11683 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
11684 emit_move_insn (op0, temp);
11690 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
11694 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
11696 rtx op0 = operands[0], op1 = operands[1];
11697 unsigned int align = GET_MODE_ALIGNMENT (mode);
11699 /* Force constants other than zero into memory. We do not know how
11700 the instructions used to build constants modify the upper 64 bits
11701 of the register, once we have that information we may be able
11702 to handle some of them more efficiently. */
11703 if (can_create_pseudo_p ()
11704 && register_operand (op0, mode)
11705 && (CONSTANT_P (op1)
11706 || (GET_CODE (op1) == SUBREG
11707 && CONSTANT_P (SUBREG_REG (op1))))
11708 && standard_sse_constant_p (op1) <= 0)
11709 op1 = validize_mem (force_const_mem (mode, op1));
11711 /* We need to check memory alignment for SSE mode since attribute
11712 can make operands unaligned. */
11713 if (can_create_pseudo_p ()
11714 && SSE_REG_MODE_P (mode)
11715 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
11716 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
11720 /* ix86_expand_vector_move_misalign() does not like constants ... */
11721 if (CONSTANT_P (op1)
11722 || (GET_CODE (op1) == SUBREG
11723 && CONSTANT_P (SUBREG_REG (op1))))
11724 op1 = validize_mem (force_const_mem (mode, op1));
11726 /* ... nor both arguments in memory. */
11727 if (!register_operand (op0, mode)
11728 && !register_operand (op1, mode))
11729 op1 = force_reg (mode, op1);
11731 tmp[0] = op0; tmp[1] = op1;
11732 ix86_expand_vector_move_misalign (mode, tmp);
11736 /* Make operand1 a register if it isn't already. */
11737 if (can_create_pseudo_p ()
11738 && !register_operand (op0, mode)
11739 && !register_operand (op1, mode))
11741 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
11745 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
11748 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
11749 straight to ix86_expand_vector_move. */
11750 /* Code generation for scalar reg-reg moves of single and double precision data:
11751 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
11755 if (x86_sse_partial_reg_dependency == true)
11760 Code generation for scalar loads of double precision data:
11761 if (x86_sse_split_regs == true)
11762 movlpd mem, reg (gas syntax)
11766 Code generation for unaligned packed loads of single precision data
11767 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
11768 if (x86_sse_unaligned_move_optimal)
11771 if (x86_sse_partial_reg_dependency == true)
11783 Code generation for unaligned packed loads of double precision data
11784 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
11785 if (x86_sse_unaligned_move_optimal)
11788 if (x86_sse_split_regs == true)
11801 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
11810 /* If we're optimizing for size, movups is the smallest. */
11811 if (optimize_insn_for_size_p ())
11813 op0 = gen_lowpart (V4SFmode, op0);
11814 op1 = gen_lowpart (V4SFmode, op1);
11815 emit_insn (gen_sse_movups (op0, op1));
11819 /* ??? If we have typed data, then it would appear that using
11820 movdqu is the only way to get unaligned data loaded with
11822 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
11824 op0 = gen_lowpart (V16QImode, op0);
11825 op1 = gen_lowpart (V16QImode, op1);
11826 emit_insn (gen_sse2_movdqu (op0, op1));
11830 if (TARGET_SSE2 && mode == V2DFmode)
11834 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
11836 op0 = gen_lowpart (V2DFmode, op0);
11837 op1 = gen_lowpart (V2DFmode, op1);
11838 emit_insn (gen_sse2_movupd (op0, op1));
11842 /* When SSE registers are split into halves, we can avoid
11843 writing to the top half twice. */
11844 if (TARGET_SSE_SPLIT_REGS)
11846 emit_clobber (op0);
11851 /* ??? Not sure about the best option for the Intel chips.
11852 The following would seem to satisfy; the register is
11853 entirely cleared, breaking the dependency chain. We
11854 then store to the upper half, with a dependency depth
11855 of one. A rumor has it that Intel recommends two movsd
11856 followed by an unpacklpd, but this is unconfirmed. And
11857 given that the dependency depth of the unpacklpd would
11858 still be one, I'm not sure why this would be better. */
11859 zero = CONST0_RTX (V2DFmode);
11862 m = adjust_address (op1, DFmode, 0);
11863 emit_insn (gen_sse2_loadlpd (op0, zero, m));
11864 m = adjust_address (op1, DFmode, 8);
11865 emit_insn (gen_sse2_loadhpd (op0, op0, m));
11869 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
11871 op0 = gen_lowpart (V4SFmode, op0);
11872 op1 = gen_lowpart (V4SFmode, op1);
11873 emit_insn (gen_sse_movups (op0, op1));
11877 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
11878 emit_move_insn (op0, CONST0_RTX (mode));
11880 emit_clobber (op0);
11882 if (mode != V4SFmode)
11883 op0 = gen_lowpart (V4SFmode, op0);
11884 m = adjust_address (op1, V2SFmode, 0);
11885 emit_insn (gen_sse_loadlps (op0, op0, m));
11886 m = adjust_address (op1, V2SFmode, 8);
11887 emit_insn (gen_sse_loadhps (op0, op0, m));
11890 else if (MEM_P (op0))
11892 /* If we're optimizing for size, movups is the smallest. */
11893 if (optimize_insn_for_size_p ())
11895 op0 = gen_lowpart (V4SFmode, op0);
11896 op1 = gen_lowpart (V4SFmode, op1);
11897 emit_insn (gen_sse_movups (op0, op1));
11901 /* ??? Similar to above, only less clear because of quote
11902 typeless stores unquote. */
11903 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
11904 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
11906 op0 = gen_lowpart (V16QImode, op0);
11907 op1 = gen_lowpart (V16QImode, op1);
11908 emit_insn (gen_sse2_movdqu (op0, op1));
11912 if (TARGET_SSE2 && mode == V2DFmode)
11914 m = adjust_address (op0, DFmode, 0);
11915 emit_insn (gen_sse2_storelpd (m, op1));
11916 m = adjust_address (op0, DFmode, 8);
11917 emit_insn (gen_sse2_storehpd (m, op1));
11921 if (mode != V4SFmode)
11922 op1 = gen_lowpart (V4SFmode, op1);
11923 m = adjust_address (op0, V2SFmode, 0);
11924 emit_insn (gen_sse_storelps (m, op1));
11925 m = adjust_address (op0, V2SFmode, 8);
11926 emit_insn (gen_sse_storehps (m, op1));
11930 gcc_unreachable ();
11933 /* Expand a push in MODE. This is some mode for which we do not support
11934 proper push instructions, at least from the registers that we expect
11935 the value to live in. */
11938 ix86_expand_push (enum machine_mode mode, rtx x)
11942 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
11943 GEN_INT (-GET_MODE_SIZE (mode)),
11944 stack_pointer_rtx, 1, OPTAB_DIRECT);
11945 if (tmp != stack_pointer_rtx)
11946 emit_move_insn (stack_pointer_rtx, tmp);
11948 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
11949 emit_move_insn (tmp, x);
11952 /* Helper function of ix86_fixup_binary_operands to canonicalize
11953 operand order. Returns true if the operands should be swapped. */
11956 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
11959 rtx dst = operands[0];
11960 rtx src1 = operands[1];
11961 rtx src2 = operands[2];
11963 /* If the operation is not commutative, we can't do anything. */
11964 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
11967 /* Highest priority is that src1 should match dst. */
11968 if (rtx_equal_p (dst, src1))
11970 if (rtx_equal_p (dst, src2))
11973 /* Next highest priority is that immediate constants come second. */
11974 if (immediate_operand (src2, mode))
11976 if (immediate_operand (src1, mode))
11979 /* Lowest priority is that memory references should come second. */
11989 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
11990 destination to use for the operation. If different from the true
11991 destination in operands[0], a copy operation will be required. */
11994 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
11997 rtx dst = operands[0];
11998 rtx src1 = operands[1];
11999 rtx src2 = operands[2];
12001 /* Canonicalize operand order. */
12002 if (ix86_swap_binary_operands_p (code, mode, operands))
12006 /* It is invalid to swap operands of different modes. */
12007 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12014 /* Both source operands cannot be in memory. */
12015 if (MEM_P (src1) && MEM_P (src2))
12017 /* Optimization: Only read from memory once. */
12018 if (rtx_equal_p (src1, src2))
12020 src2 = force_reg (mode, src2);
12024 src2 = force_reg (mode, src2);
12027 /* If the destination is memory, and we do not have matching source
12028 operands, do things in registers. */
12029 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12030 dst = gen_reg_rtx (mode);
12032 /* Source 1 cannot be a constant. */
12033 if (CONSTANT_P (src1))
12034 src1 = force_reg (mode, src1);
12036 /* Source 1 cannot be a non-matching memory. */
12037 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12038 src1 = force_reg (mode, src1);
12040 operands[1] = src1;
12041 operands[2] = src2;
12045 /* Similarly, but assume that the destination has already been
12046 set up properly. */
12049 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12050 enum machine_mode mode, rtx operands[])
12052 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12053 gcc_assert (dst == operands[0]);
12056 /* Attempt to expand a binary operator. Make the expansion closer to the
12057 actual machine, then just general_operand, which will allow 3 separate
12058 memory references (one output, two input) in a single insn. */
12061 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12064 rtx src1, src2, dst, op, clob;
12066 dst = ix86_fixup_binary_operands (code, mode, operands);
12067 src1 = operands[1];
12068 src2 = operands[2];
12070 /* Emit the instruction. */
12072 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12073 if (reload_in_progress)
12075 /* Reload doesn't know about the flags register, and doesn't know that
12076 it doesn't want to clobber it. We can only do this with PLUS. */
12077 gcc_assert (code == PLUS);
12082 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12083 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12086 /* Fix up the destination if needed. */
12087 if (dst != operands[0])
12088 emit_move_insn (operands[0], dst);
12091 /* Return TRUE or FALSE depending on whether the binary operator meets the
12092 appropriate constraints. */
12095 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12098 rtx dst = operands[0];
12099 rtx src1 = operands[1];
12100 rtx src2 = operands[2];
12102 /* Both source operands cannot be in memory. */
12103 if (MEM_P (src1) && MEM_P (src2))
12106 /* Canonicalize operand order for commutative operators. */
12107 if (ix86_swap_binary_operands_p (code, mode, operands))
12114 /* If the destination is memory, we must have a matching source operand. */
12115 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12118 /* Source 1 cannot be a constant. */
12119 if (CONSTANT_P (src1))
12122 /* Source 1 cannot be a non-matching memory. */
12123 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12129 /* Attempt to expand a unary operator. Make the expansion closer to the
12130 actual machine, then just general_operand, which will allow 2 separate
12131 memory references (one output, one input) in a single insn. */
12134 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
12137 int matching_memory;
12138 rtx src, dst, op, clob;
12143 /* If the destination is memory, and we do not have matching source
12144 operands, do things in registers. */
12145 matching_memory = 0;
12148 if (rtx_equal_p (dst, src))
12149 matching_memory = 1;
12151 dst = gen_reg_rtx (mode);
12154 /* When source operand is memory, destination must match. */
12155 if (MEM_P (src) && !matching_memory)
12156 src = force_reg (mode, src);
12158 /* Emit the instruction. */
12160 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
12161 if (reload_in_progress || code == NOT)
12163 /* Reload doesn't know about the flags register, and doesn't know that
12164 it doesn't want to clobber it. */
12165 gcc_assert (code == NOT);
12170 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12171 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12174 /* Fix up the destination if needed. */
12175 if (dst != operands[0])
12176 emit_move_insn (operands[0], dst);
12179 /* Return TRUE or FALSE depending on whether the unary operator meets the
12180 appropriate constraints. */
12183 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
12184 enum machine_mode mode ATTRIBUTE_UNUSED,
12185 rtx operands[2] ATTRIBUTE_UNUSED)
12187 /* If one of operands is memory, source and destination must match. */
12188 if ((MEM_P (operands[0])
12189 || MEM_P (operands[1]))
12190 && ! rtx_equal_p (operands[0], operands[1]))
12195 /* Post-reload splitter for converting an SF or DFmode value in an
12196 SSE register into an unsigned SImode. */
12199 ix86_split_convert_uns_si_sse (rtx operands[])
12201 enum machine_mode vecmode;
12202 rtx value, large, zero_or_two31, input, two31, x;
12204 large = operands[1];
12205 zero_or_two31 = operands[2];
12206 input = operands[3];
12207 two31 = operands[4];
12208 vecmode = GET_MODE (large);
12209 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
12211 /* Load up the value into the low element. We must ensure that the other
12212 elements are valid floats -- zero is the easiest such value. */
12215 if (vecmode == V4SFmode)
12216 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
12218 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
12222 input = gen_rtx_REG (vecmode, REGNO (input));
12223 emit_move_insn (value, CONST0_RTX (vecmode));
12224 if (vecmode == V4SFmode)
12225 emit_insn (gen_sse_movss (value, value, input));
12227 emit_insn (gen_sse2_movsd (value, value, input));
12230 emit_move_insn (large, two31);
12231 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
12233 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
12234 emit_insn (gen_rtx_SET (VOIDmode, large, x));
12236 x = gen_rtx_AND (vecmode, zero_or_two31, large);
12237 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
12239 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
12240 emit_insn (gen_rtx_SET (VOIDmode, value, x));
12242 large = gen_rtx_REG (V4SImode, REGNO (large));
12243 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
12245 x = gen_rtx_REG (V4SImode, REGNO (value));
12246 if (vecmode == V4SFmode)
12247 emit_insn (gen_sse2_cvttps2dq (x, value));
12249 emit_insn (gen_sse2_cvttpd2dq (x, value));
12252 emit_insn (gen_xorv4si3 (value, value, large));
12255 /* Convert an unsigned DImode value into a DFmode, using only SSE.
12256 Expects the 64-bit DImode to be supplied in a pair of integral
12257 registers. Requires SSE2; will use SSE3 if available. For x86_32,
12258 -mfpmath=sse, !optimize_size only. */
12261 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
12263 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
12264 rtx int_xmm, fp_xmm;
12265 rtx biases, exponents;
12268 int_xmm = gen_reg_rtx (V4SImode);
12269 if (TARGET_INTER_UNIT_MOVES)
12270 emit_insn (gen_movdi_to_sse (int_xmm, input));
12271 else if (TARGET_SSE_SPLIT_REGS)
12273 emit_clobber (int_xmm);
12274 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
12278 x = gen_reg_rtx (V2DImode);
12279 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
12280 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
12283 x = gen_rtx_CONST_VECTOR (V4SImode,
12284 gen_rtvec (4, GEN_INT (0x43300000UL),
12285 GEN_INT (0x45300000UL),
12286 const0_rtx, const0_rtx));
12287 exponents = validize_mem (force_const_mem (V4SImode, x));
12289 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
12290 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
12292 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
12293 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
12294 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
12295 (0x1.0p84 + double(fp_value_hi_xmm)).
12296 Note these exponents differ by 32. */
12298 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
12300 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
12301 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
12302 real_ldexp (&bias_lo_rvt, &dconst1, 52);
12303 real_ldexp (&bias_hi_rvt, &dconst1, 84);
12304 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
12305 x = const_double_from_real_value (bias_hi_rvt, DFmode);
12306 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
12307 biases = validize_mem (force_const_mem (V2DFmode, biases));
12308 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
12310 /* Add the upper and lower DFmode values together. */
12312 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
12315 x = copy_to_mode_reg (V2DFmode, fp_xmm);
12316 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
12317 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
12320 ix86_expand_vector_extract (false, target, fp_xmm, 0);
12323 /* Not used, but eases macroization of patterns. */
12325 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
12326 rtx input ATTRIBUTE_UNUSED)
12328 gcc_unreachable ();
12331 /* Convert an unsigned SImode value into a DFmode. Only currently used
12332 for SSE, but applicable anywhere. */
12335 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
12337 REAL_VALUE_TYPE TWO31r;
12340 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
12341 NULL, 1, OPTAB_DIRECT);
12343 fp = gen_reg_rtx (DFmode);
12344 emit_insn (gen_floatsidf2 (fp, x));
12346 real_ldexp (&TWO31r, &dconst1, 31);
12347 x = const_double_from_real_value (TWO31r, DFmode);
12349 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
12351 emit_move_insn (target, x);
12354 /* Convert a signed DImode value into a DFmode. Only used for SSE in
12355 32-bit mode; otherwise we have a direct convert instruction. */
12358 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
12360 REAL_VALUE_TYPE TWO32r;
12361 rtx fp_lo, fp_hi, x;
12363 fp_lo = gen_reg_rtx (DFmode);
12364 fp_hi = gen_reg_rtx (DFmode);
12366 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
12368 real_ldexp (&TWO32r, &dconst1, 32);
12369 x = const_double_from_real_value (TWO32r, DFmode);
12370 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
12372 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
12374 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
12377 emit_move_insn (target, x);
12380 /* Convert an unsigned SImode value into a SFmode, using only SSE.
12381 For x86_32, -mfpmath=sse, !optimize_size only. */
12383 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
12385 REAL_VALUE_TYPE ONE16r;
12386 rtx fp_hi, fp_lo, int_hi, int_lo, x;
12388 real_ldexp (&ONE16r, &dconst1, 16);
12389 x = const_double_from_real_value (ONE16r, SFmode);
12390 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
12391 NULL, 0, OPTAB_DIRECT);
12392 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
12393 NULL, 0, OPTAB_DIRECT);
12394 fp_hi = gen_reg_rtx (SFmode);
12395 fp_lo = gen_reg_rtx (SFmode);
12396 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
12397 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
12398 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
12400 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
12402 if (!rtx_equal_p (target, fp_hi))
12403 emit_move_insn (target, fp_hi);
12406 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
12407 then replicate the value for all elements of the vector
12411 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
12418 v = gen_rtvec (4, value, value, value, value);
12419 return gen_rtx_CONST_VECTOR (V4SImode, v);
12423 v = gen_rtvec (2, value, value);
12424 return gen_rtx_CONST_VECTOR (V2DImode, v);
12428 v = gen_rtvec (4, value, value, value, value);
12430 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
12431 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
12432 return gen_rtx_CONST_VECTOR (V4SFmode, v);
12436 v = gen_rtvec (2, value, value);
12438 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
12439 return gen_rtx_CONST_VECTOR (V2DFmode, v);
12442 gcc_unreachable ();
12446 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
12447 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
12448 for an SSE register. If VECT is true, then replicate the mask for
12449 all elements of the vector register. If INVERT is true, then create
12450 a mask excluding the sign bit. */
12453 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
12455 enum machine_mode vec_mode, imode;
12456 HOST_WIDE_INT hi, lo;
12461 /* Find the sign bit, sign extended to 2*HWI. */
12467 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
12468 lo = 0x80000000, hi = lo < 0;
12474 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
12475 if (HOST_BITS_PER_WIDE_INT >= 64)
12476 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
12478 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
12483 vec_mode = VOIDmode;
12484 if (HOST_BITS_PER_WIDE_INT >= 64)
12487 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
12494 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
12498 lo = ~lo, hi = ~hi;
12504 mask = immed_double_const (lo, hi, imode);
12506 vec = gen_rtvec (2, v, mask);
12507 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
12508 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
12515 gcc_unreachable ();
12519 lo = ~lo, hi = ~hi;
12521 /* Force this value into the low part of a fp vector constant. */
12522 mask = immed_double_const (lo, hi, imode);
12523 mask = gen_lowpart (mode, mask);
12525 if (vec_mode == VOIDmode)
12526 return force_reg (mode, mask);
12528 v = ix86_build_const_vector (mode, vect, mask);
12529 return force_reg (vec_mode, v);
12532 /* Generate code for floating point ABS or NEG. */
12535 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
12538 rtx mask, set, use, clob, dst, src;
12539 bool use_sse = false;
12540 bool vector_mode = VECTOR_MODE_P (mode);
12541 enum machine_mode elt_mode = mode;
12545 elt_mode = GET_MODE_INNER (mode);
12548 else if (mode == TFmode)
12550 else if (TARGET_SSE_MATH)
12551 use_sse = SSE_FLOAT_MODE_P (mode);
12553 /* NEG and ABS performed with SSE use bitwise mask operations.
12554 Create the appropriate mask now. */
12556 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
12565 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
12566 set = gen_rtx_SET (VOIDmode, dst, set);
12571 set = gen_rtx_fmt_e (code, mode, src);
12572 set = gen_rtx_SET (VOIDmode, dst, set);
12575 use = gen_rtx_USE (VOIDmode, mask);
12576 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12577 emit_insn (gen_rtx_PARALLEL (VOIDmode,
12578 gen_rtvec (3, set, use, clob)));
12585 /* Expand a copysign operation. Special case operand 0 being a constant. */
12588 ix86_expand_copysign (rtx operands[])
12590 enum machine_mode mode;
12591 rtx dest, op0, op1, mask, nmask;
12593 dest = operands[0];
12597 mode = GET_MODE (dest);
12599 if (GET_CODE (op0) == CONST_DOUBLE)
12601 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
12603 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
12604 op0 = simplify_unary_operation (ABS, mode, op0, mode);
12606 if (mode == SFmode || mode == DFmode)
12608 enum machine_mode vmode;
12610 vmode = mode == SFmode ? V4SFmode : V2DFmode;
12612 if (op0 == CONST0_RTX (mode))
12613 op0 = CONST0_RTX (vmode);
12618 if (mode == SFmode)
12619 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
12620 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
12622 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
12624 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
12627 else if (op0 != CONST0_RTX (mode))
12628 op0 = force_reg (mode, op0);
12630 mask = ix86_build_signbit_mask (mode, 0, 0);
12632 if (mode == SFmode)
12633 copysign_insn = gen_copysignsf3_const;
12634 else if (mode == DFmode)
12635 copysign_insn = gen_copysigndf3_const;
12637 copysign_insn = gen_copysigntf3_const;
12639 emit_insn (copysign_insn (dest, op0, op1, mask));
12643 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
12645 nmask = ix86_build_signbit_mask (mode, 0, 1);
12646 mask = ix86_build_signbit_mask (mode, 0, 0);
12648 if (mode == SFmode)
12649 copysign_insn = gen_copysignsf3_var;
12650 else if (mode == DFmode)
12651 copysign_insn = gen_copysigndf3_var;
12653 copysign_insn = gen_copysigntf3_var;
12655 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
12659 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
12660 be a constant, and so has already been expanded into a vector constant. */
12663 ix86_split_copysign_const (rtx operands[])
12665 enum machine_mode mode, vmode;
12666 rtx dest, op0, op1, mask, x;
12668 dest = operands[0];
12671 mask = operands[3];
12673 mode = GET_MODE (dest);
12674 vmode = GET_MODE (mask);
12676 dest = simplify_gen_subreg (vmode, dest, mode, 0);
12677 x = gen_rtx_AND (vmode, dest, mask);
12678 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12680 if (op0 != CONST0_RTX (vmode))
12682 x = gen_rtx_IOR (vmode, dest, op0);
12683 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12687 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
12688 so we have to do two masks. */
12691 ix86_split_copysign_var (rtx operands[])
12693 enum machine_mode mode, vmode;
12694 rtx dest, scratch, op0, op1, mask, nmask, x;
12696 dest = operands[0];
12697 scratch = operands[1];
12700 nmask = operands[4];
12701 mask = operands[5];
12703 mode = GET_MODE (dest);
12704 vmode = GET_MODE (mask);
12706 if (rtx_equal_p (op0, op1))
12708 /* Shouldn't happen often (it's useless, obviously), but when it does
12709 we'd generate incorrect code if we continue below. */
12710 emit_move_insn (dest, op0);
12714 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
12716 gcc_assert (REGNO (op1) == REGNO (scratch));
12718 x = gen_rtx_AND (vmode, scratch, mask);
12719 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12722 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
12723 x = gen_rtx_NOT (vmode, dest);
12724 x = gen_rtx_AND (vmode, x, op0);
12725 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12729 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
12731 x = gen_rtx_AND (vmode, scratch, mask);
12733 else /* alternative 2,4 */
12735 gcc_assert (REGNO (mask) == REGNO (scratch));
12736 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
12737 x = gen_rtx_AND (vmode, scratch, op1);
12739 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12741 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
12743 dest = simplify_gen_subreg (vmode, op0, mode, 0);
12744 x = gen_rtx_AND (vmode, dest, nmask);
12746 else /* alternative 3,4 */
12748 gcc_assert (REGNO (nmask) == REGNO (dest));
12750 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
12751 x = gen_rtx_AND (vmode, dest, op0);
12753 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12756 x = gen_rtx_IOR (vmode, dest, scratch);
12757 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12760 /* Return TRUE or FALSE depending on whether the first SET in INSN
12761 has source and destination with matching CC modes, and that the
12762 CC mode is at least as constrained as REQ_MODE. */
12765 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
12768 enum machine_mode set_mode;
12770 set = PATTERN (insn);
12771 if (GET_CODE (set) == PARALLEL)
12772 set = XVECEXP (set, 0, 0);
12773 gcc_assert (GET_CODE (set) == SET);
12774 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
12776 set_mode = GET_MODE (SET_DEST (set));
12780 if (req_mode != CCNOmode
12781 && (req_mode != CCmode
12782 || XEXP (SET_SRC (set), 1) != const0_rtx))
12786 if (req_mode == CCGCmode)
12790 if (req_mode == CCGOCmode || req_mode == CCNOmode)
12794 if (req_mode == CCZmode)
12801 gcc_unreachable ();
12804 return (GET_MODE (SET_SRC (set)) == set_mode);
12807 /* Generate insn patterns to do an integer compare of OPERANDS. */
12810 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
12812 enum machine_mode cmpmode;
12815 cmpmode = SELECT_CC_MODE (code, op0, op1);
12816 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
12818 /* This is very simple, but making the interface the same as in the
12819 FP case makes the rest of the code easier. */
12820 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
12821 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
12823 /* Return the test that should be put into the flags user, i.e.
12824 the bcc, scc, or cmov instruction. */
12825 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
12828 /* Figure out whether to use ordered or unordered fp comparisons.
12829 Return the appropriate mode to use. */
12832 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
12834 /* ??? In order to make all comparisons reversible, we do all comparisons
12835 non-trapping when compiling for IEEE. Once gcc is able to distinguish
12836 all forms trapping and nontrapping comparisons, we can make inequality
12837 comparisons trapping again, since it results in better code when using
12838 FCOM based compares. */
12839 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
12843 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
12845 enum machine_mode mode = GET_MODE (op0);
12847 if (SCALAR_FLOAT_MODE_P (mode))
12849 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
12850 return ix86_fp_compare_mode (code);
12855 /* Only zero flag is needed. */
12856 case EQ: /* ZF=0 */
12857 case NE: /* ZF!=0 */
12859 /* Codes needing carry flag. */
12860 case GEU: /* CF=0 */
12861 case LTU: /* CF=1 */
12862 /* Detect overflow checks. They need just the carry flag. */
12863 if (GET_CODE (op0) == PLUS
12864 && rtx_equal_p (op1, XEXP (op0, 0)))
12868 case GTU: /* CF=0 & ZF=0 */
12869 case LEU: /* CF=1 | ZF=1 */
12870 /* Detect overflow checks. They need just the carry flag. */
12871 if (GET_CODE (op0) == MINUS
12872 && rtx_equal_p (op1, XEXP (op0, 0)))
12876 /* Codes possibly doable only with sign flag when
12877 comparing against zero. */
12878 case GE: /* SF=OF or SF=0 */
12879 case LT: /* SF<>OF or SF=1 */
12880 if (op1 == const0_rtx)
12883 /* For other cases Carry flag is not required. */
12885 /* Codes doable only with sign flag when comparing
12886 against zero, but we miss jump instruction for it
12887 so we need to use relational tests against overflow
12888 that thus needs to be zero. */
12889 case GT: /* ZF=0 & SF=OF */
12890 case LE: /* ZF=1 | SF<>OF */
12891 if (op1 == const0_rtx)
12895 /* strcmp pattern do (use flags) and combine may ask us for proper
12900 gcc_unreachable ();
12904 /* Return the fixed registers used for condition codes. */
12907 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
12914 /* If two condition code modes are compatible, return a condition code
12915 mode which is compatible with both. Otherwise, return
12918 static enum machine_mode
12919 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
12924 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
12927 if ((m1 == CCGCmode && m2 == CCGOCmode)
12928 || (m1 == CCGOCmode && m2 == CCGCmode))
12934 gcc_unreachable ();
12964 /* These are only compatible with themselves, which we already
12970 /* Split comparison code CODE into comparisons we can do using branch
12971 instructions. BYPASS_CODE is comparison code for branch that will
12972 branch around FIRST_CODE and SECOND_CODE. If some of branches
12973 is not required, set value to UNKNOWN.
12974 We never require more than two branches. */
12977 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
12978 enum rtx_code *first_code,
12979 enum rtx_code *second_code)
12981 *first_code = code;
12982 *bypass_code = UNKNOWN;
12983 *second_code = UNKNOWN;
12985 /* The fcomi comparison sets flags as follows:
12995 case GT: /* GTU - CF=0 & ZF=0 */
12996 case GE: /* GEU - CF=0 */
12997 case ORDERED: /* PF=0 */
12998 case UNORDERED: /* PF=1 */
12999 case UNEQ: /* EQ - ZF=1 */
13000 case UNLT: /* LTU - CF=1 */
13001 case UNLE: /* LEU - CF=1 | ZF=1 */
13002 case LTGT: /* EQ - ZF=0 */
13004 case LT: /* LTU - CF=1 - fails on unordered */
13005 *first_code = UNLT;
13006 *bypass_code = UNORDERED;
13008 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
13009 *first_code = UNLE;
13010 *bypass_code = UNORDERED;
13012 case EQ: /* EQ - ZF=1 - fails on unordered */
13013 *first_code = UNEQ;
13014 *bypass_code = UNORDERED;
13016 case NE: /* NE - ZF=0 - fails on unordered */
13017 *first_code = LTGT;
13018 *second_code = UNORDERED;
13020 case UNGE: /* GEU - CF=0 - fails on unordered */
13022 *second_code = UNORDERED;
13024 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
13026 *second_code = UNORDERED;
13029 gcc_unreachable ();
13031 if (!TARGET_IEEE_FP)
13033 *second_code = UNKNOWN;
13034 *bypass_code = UNKNOWN;
13038 /* Return cost of comparison done fcom + arithmetics operations on AX.
13039 All following functions do use number of instructions as a cost metrics.
13040 In future this should be tweaked to compute bytes for optimize_size and
13041 take into account performance of various instructions on various CPUs. */
13043 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
13045 if (!TARGET_IEEE_FP)
13047 /* The cost of code output by ix86_expand_fp_compare. */
13071 gcc_unreachable ();
13075 /* Return cost of comparison done using fcomi operation.
13076 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13078 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
13080 enum rtx_code bypass_code, first_code, second_code;
13081 /* Return arbitrarily high cost when instruction is not supported - this
13082 prevents gcc from using it. */
13085 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13086 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
13089 /* Return cost of comparison done using sahf operation.
13090 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13092 ix86_fp_comparison_sahf_cost (enum rtx_code code)
13094 enum rtx_code bypass_code, first_code, second_code;
13095 /* Return arbitrarily high cost when instruction is not preferred - this
13096 avoids gcc from using it. */
13097 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
13099 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13100 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
13103 /* Compute cost of the comparison done using any method.
13104 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13106 ix86_fp_comparison_cost (enum rtx_code code)
13108 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
13111 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
13112 sahf_cost = ix86_fp_comparison_sahf_cost (code);
13114 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
13115 if (min > sahf_cost)
13117 if (min > fcomi_cost)
13122 /* Return true if we should use an FCOMI instruction for this
13126 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
13128 enum rtx_code swapped_code = swap_condition (code);
13130 return ((ix86_fp_comparison_cost (code)
13131 == ix86_fp_comparison_fcomi_cost (code))
13132 || (ix86_fp_comparison_cost (swapped_code)
13133 == ix86_fp_comparison_fcomi_cost (swapped_code)));
13136 /* Swap, force into registers, or otherwise massage the two operands
13137 to a fp comparison. The operands are updated in place; the new
13138 comparison code is returned. */
13140 static enum rtx_code
13141 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
13143 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
13144 rtx op0 = *pop0, op1 = *pop1;
13145 enum machine_mode op_mode = GET_MODE (op0);
13146 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
13148 /* All of the unordered compare instructions only work on registers.
13149 The same is true of the fcomi compare instructions. The XFmode
13150 compare instructions require registers except when comparing
13151 against zero or when converting operand 1 from fixed point to
13155 && (fpcmp_mode == CCFPUmode
13156 || (op_mode == XFmode
13157 && ! (standard_80387_constant_p (op0) == 1
13158 || standard_80387_constant_p (op1) == 1)
13159 && GET_CODE (op1) != FLOAT)
13160 || ix86_use_fcomi_compare (code)))
13162 op0 = force_reg (op_mode, op0);
13163 op1 = force_reg (op_mode, op1);
13167 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13168 things around if they appear profitable, otherwise force op0
13169 into a register. */
13171 if (standard_80387_constant_p (op0) == 0
13173 && ! (standard_80387_constant_p (op1) == 0
13177 tmp = op0, op0 = op1, op1 = tmp;
13178 code = swap_condition (code);
13182 op0 = force_reg (op_mode, op0);
13184 if (CONSTANT_P (op1))
13186 int tmp = standard_80387_constant_p (op1);
13188 op1 = validize_mem (force_const_mem (op_mode, op1));
13192 op1 = force_reg (op_mode, op1);
13195 op1 = force_reg (op_mode, op1);
13199 /* Try to rearrange the comparison to make it cheaper. */
13200 if (ix86_fp_comparison_cost (code)
13201 > ix86_fp_comparison_cost (swap_condition (code))
13202 && (REG_P (op1) || can_create_pseudo_p ()))
13205 tmp = op0, op0 = op1, op1 = tmp;
13206 code = swap_condition (code);
13208 op0 = force_reg (op_mode, op0);
13216 /* Convert comparison codes we use to represent FP comparison to integer
13217 code that will result in proper branch. Return UNKNOWN if no such code
13221 ix86_fp_compare_code_to_integer (enum rtx_code code)
13250 /* Generate insn patterns to do a floating point compare of OPERANDS. */
13253 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
13254 rtx *second_test, rtx *bypass_test)
13256 enum machine_mode fpcmp_mode, intcmp_mode;
13258 int cost = ix86_fp_comparison_cost (code);
13259 enum rtx_code bypass_code, first_code, second_code;
13261 fpcmp_mode = ix86_fp_compare_mode (code);
13262 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
13265 *second_test = NULL_RTX;
13267 *bypass_test = NULL_RTX;
13269 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13271 /* Do fcomi/sahf based test when profitable. */
13272 if (ix86_fp_comparison_arithmetics_cost (code) > cost
13273 && (bypass_code == UNKNOWN || bypass_test)
13274 && (second_code == UNKNOWN || second_test))
13276 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13277 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
13283 gcc_assert (TARGET_SAHF);
13286 scratch = gen_reg_rtx (HImode);
13287 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
13289 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
13292 /* The FP codes work out to act like unsigned. */
13293 intcmp_mode = fpcmp_mode;
13295 if (bypass_code != UNKNOWN)
13296 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
13297 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13299 if (second_code != UNKNOWN)
13300 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
13301 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13306 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
13307 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13308 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
13310 scratch = gen_reg_rtx (HImode);
13311 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
13313 /* In the unordered case, we have to check C2 for NaN's, which
13314 doesn't happen to work out to anything nice combination-wise.
13315 So do some bit twiddling on the value we've got in AH to come
13316 up with an appropriate set of condition codes. */
13318 intcmp_mode = CCNOmode;
13323 if (code == GT || !TARGET_IEEE_FP)
13325 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
13330 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13331 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
13332 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
13333 intcmp_mode = CCmode;
13339 if (code == LT && TARGET_IEEE_FP)
13341 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13342 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
13343 intcmp_mode = CCmode;
13348 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
13354 if (code == GE || !TARGET_IEEE_FP)
13356 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
13361 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13362 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
13369 if (code == LE && TARGET_IEEE_FP)
13371 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13372 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
13373 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
13374 intcmp_mode = CCmode;
13379 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
13385 if (code == EQ && TARGET_IEEE_FP)
13387 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13388 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
13389 intcmp_mode = CCmode;
13394 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
13401 if (code == NE && TARGET_IEEE_FP)
13403 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
13404 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
13410 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
13416 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
13420 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
13425 gcc_unreachable ();
13429 /* Return the test that should be put into the flags user, i.e.
13430 the bcc, scc, or cmov instruction. */
13431 return gen_rtx_fmt_ee (code, VOIDmode,
13432 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13437 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
13440 op0 = ix86_compare_op0;
13441 op1 = ix86_compare_op1;
13444 *second_test = NULL_RTX;
13446 *bypass_test = NULL_RTX;
13448 if (ix86_compare_emitted)
13450 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
13451 ix86_compare_emitted = NULL_RTX;
13453 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
13455 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
13456 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
13457 second_test, bypass_test);
13460 ret = ix86_expand_int_compare (code, op0, op1);
13465 /* Return true if the CODE will result in nontrivial jump sequence. */
13467 ix86_fp_jump_nontrivial_p (enum rtx_code code)
13469 enum rtx_code bypass_code, first_code, second_code;
13472 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13473 return bypass_code != UNKNOWN || second_code != UNKNOWN;
13477 ix86_expand_branch (enum rtx_code code, rtx label)
13481 /* If we have emitted a compare insn, go straight to simple.
13482 ix86_expand_compare won't emit anything if ix86_compare_emitted
13484 if (ix86_compare_emitted)
13487 switch (GET_MODE (ix86_compare_op0))
13493 tmp = ix86_expand_compare (code, NULL, NULL);
13494 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
13495 gen_rtx_LABEL_REF (VOIDmode, label),
13497 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
13506 enum rtx_code bypass_code, first_code, second_code;
13508 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
13509 &ix86_compare_op1);
13511 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13513 /* Check whether we will use the natural sequence with one jump. If
13514 so, we can expand jump early. Otherwise delay expansion by
13515 creating compound insn to not confuse optimizers. */
13516 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
13518 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
13519 gen_rtx_LABEL_REF (VOIDmode, label),
13520 pc_rtx, NULL_RTX, NULL_RTX);
13524 tmp = gen_rtx_fmt_ee (code, VOIDmode,
13525 ix86_compare_op0, ix86_compare_op1);
13526 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
13527 gen_rtx_LABEL_REF (VOIDmode, label),
13529 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
13531 use_fcomi = ix86_use_fcomi_compare (code);
13532 vec = rtvec_alloc (3 + !use_fcomi);
13533 RTVEC_ELT (vec, 0) = tmp;
13535 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
13537 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
13540 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
13542 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
13551 /* Expand DImode branch into multiple compare+branch. */
13553 rtx lo[2], hi[2], label2;
13554 enum rtx_code code1, code2, code3;
13555 enum machine_mode submode;
13557 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
13559 tmp = ix86_compare_op0;
13560 ix86_compare_op0 = ix86_compare_op1;
13561 ix86_compare_op1 = tmp;
13562 code = swap_condition (code);
13564 if (GET_MODE (ix86_compare_op0) == DImode)
13566 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
13567 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
13572 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
13573 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
13577 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
13578 avoid two branches. This costs one extra insn, so disable when
13579 optimizing for size. */
13581 if ((code == EQ || code == NE)
13582 && (!optimize_insn_for_size_p ()
13583 || hi[1] == const0_rtx || lo[1] == const0_rtx))
13588 if (hi[1] != const0_rtx)
13589 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
13590 NULL_RTX, 0, OPTAB_WIDEN);
13593 if (lo[1] != const0_rtx)
13594 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
13595 NULL_RTX, 0, OPTAB_WIDEN);
13597 tmp = expand_binop (submode, ior_optab, xor1, xor0,
13598 NULL_RTX, 0, OPTAB_WIDEN);
13600 ix86_compare_op0 = tmp;
13601 ix86_compare_op1 = const0_rtx;
13602 ix86_expand_branch (code, label);
13606 /* Otherwise, if we are doing less-than or greater-or-equal-than,
13607 op1 is a constant and the low word is zero, then we can just
13608 examine the high word. Similarly for low word -1 and
13609 less-or-equal-than or greater-than. */
13611 if (CONST_INT_P (hi[1]))
13614 case LT: case LTU: case GE: case GEU:
13615 if (lo[1] == const0_rtx)
13617 ix86_compare_op0 = hi[0];
13618 ix86_compare_op1 = hi[1];
13619 ix86_expand_branch (code, label);
13623 case LE: case LEU: case GT: case GTU:
13624 if (lo[1] == constm1_rtx)
13626 ix86_compare_op0 = hi[0];
13627 ix86_compare_op1 = hi[1];
13628 ix86_expand_branch (code, label);
13636 /* Otherwise, we need two or three jumps. */
13638 label2 = gen_label_rtx ();
13641 code2 = swap_condition (code);
13642 code3 = unsigned_condition (code);
13646 case LT: case GT: case LTU: case GTU:
13649 case LE: code1 = LT; code2 = GT; break;
13650 case GE: code1 = GT; code2 = LT; break;
13651 case LEU: code1 = LTU; code2 = GTU; break;
13652 case GEU: code1 = GTU; code2 = LTU; break;
13654 case EQ: code1 = UNKNOWN; code2 = NE; break;
13655 case NE: code2 = UNKNOWN; break;
13658 gcc_unreachable ();
13663 * if (hi(a) < hi(b)) goto true;
13664 * if (hi(a) > hi(b)) goto false;
13665 * if (lo(a) < lo(b)) goto true;
13669 ix86_compare_op0 = hi[0];
13670 ix86_compare_op1 = hi[1];
13672 if (code1 != UNKNOWN)
13673 ix86_expand_branch (code1, label);
13674 if (code2 != UNKNOWN)
13675 ix86_expand_branch (code2, label2);
13677 ix86_compare_op0 = lo[0];
13678 ix86_compare_op1 = lo[1];
13679 ix86_expand_branch (code3, label);
13681 if (code2 != UNKNOWN)
13682 emit_label (label2);
13687 gcc_unreachable ();
13691 /* Split branch based on floating point condition. */
13693 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
13694 rtx target1, rtx target2, rtx tmp, rtx pushed)
13696 rtx second, bypass;
13697 rtx label = NULL_RTX;
13699 int bypass_probability = -1, second_probability = -1, probability = -1;
13702 if (target2 != pc_rtx)
13705 code = reverse_condition_maybe_unordered (code);
13710 condition = ix86_expand_fp_compare (code, op1, op2,
13711 tmp, &second, &bypass);
13713 /* Remove pushed operand from stack. */
13715 ix86_free_from_memory (GET_MODE (pushed));
13717 if (split_branch_probability >= 0)
13719 /* Distribute the probabilities across the jumps.
13720 Assume the BYPASS and SECOND to be always test
13722 probability = split_branch_probability;
13724 /* Value of 1 is low enough to make no need for probability
13725 to be updated. Later we may run some experiments and see
13726 if unordered values are more frequent in practice. */
13728 bypass_probability = 1;
13730 second_probability = 1;
13732 if (bypass != NULL_RTX)
13734 label = gen_label_rtx ();
13735 i = emit_jump_insn (gen_rtx_SET
13737 gen_rtx_IF_THEN_ELSE (VOIDmode,
13739 gen_rtx_LABEL_REF (VOIDmode,
13742 if (bypass_probability >= 0)
13744 = gen_rtx_EXPR_LIST (REG_BR_PROB,
13745 GEN_INT (bypass_probability),
13748 i = emit_jump_insn (gen_rtx_SET
13750 gen_rtx_IF_THEN_ELSE (VOIDmode,
13751 condition, target1, target2)));
13752 if (probability >= 0)
13754 = gen_rtx_EXPR_LIST (REG_BR_PROB,
13755 GEN_INT (probability),
13757 if (second != NULL_RTX)
13759 i = emit_jump_insn (gen_rtx_SET
13761 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
13763 if (second_probability >= 0)
13765 = gen_rtx_EXPR_LIST (REG_BR_PROB,
13766 GEN_INT (second_probability),
13769 if (label != NULL_RTX)
13770 emit_label (label);
13774 ix86_expand_setcc (enum rtx_code code, rtx dest)
13776 rtx ret, tmp, tmpreg, equiv;
13777 rtx second_test, bypass_test;
13779 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
13780 return 0; /* FAIL */
13782 gcc_assert (GET_MODE (dest) == QImode);
13784 ret = ix86_expand_compare (code, &second_test, &bypass_test);
13785 PUT_MODE (ret, QImode);
13790 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
13791 if (bypass_test || second_test)
13793 rtx test = second_test;
13795 rtx tmp2 = gen_reg_rtx (QImode);
13798 gcc_assert (!second_test);
13799 test = bypass_test;
13801 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
13803 PUT_MODE (test, QImode);
13804 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
13807 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
13809 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
13812 /* Attach a REG_EQUAL note describing the comparison result. */
13813 if (ix86_compare_op0 && ix86_compare_op1)
13815 equiv = simplify_gen_relational (code, QImode,
13816 GET_MODE (ix86_compare_op0),
13817 ix86_compare_op0, ix86_compare_op1);
13818 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
13821 return 1; /* DONE */
13824 /* Expand comparison setting or clearing carry flag. Return true when
13825 successful and set pop for the operation. */
13827 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
13829 enum machine_mode mode =
13830 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
13832 /* Do not handle DImode compares that go through special path. */
13833 if (mode == (TARGET_64BIT ? TImode : DImode))
13836 if (SCALAR_FLOAT_MODE_P (mode))
13838 rtx second_test = NULL, bypass_test = NULL;
13839 rtx compare_op, compare_seq;
13841 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
13843 /* Shortcut: following common codes never translate
13844 into carry flag compares. */
13845 if (code == EQ || code == NE || code == UNEQ || code == LTGT
13846 || code == ORDERED || code == UNORDERED)
13849 /* These comparisons require zero flag; swap operands so they won't. */
13850 if ((code == GT || code == UNLE || code == LE || code == UNGT)
13851 && !TARGET_IEEE_FP)
13856 code = swap_condition (code);
13859 /* Try to expand the comparison and verify that we end up with
13860 carry flag based comparison. This fails to be true only when
13861 we decide to expand comparison using arithmetic that is not
13862 too common scenario. */
13864 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
13865 &second_test, &bypass_test);
13866 compare_seq = get_insns ();
13869 if (second_test || bypass_test)
13872 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
13873 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
13874 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
13876 code = GET_CODE (compare_op);
13878 if (code != LTU && code != GEU)
13881 emit_insn (compare_seq);
13886 if (!INTEGRAL_MODE_P (mode))
13895 /* Convert a==0 into (unsigned)a<1. */
13898 if (op1 != const0_rtx)
13901 code = (code == EQ ? LTU : GEU);
13904 /* Convert a>b into b<a or a>=b-1. */
13907 if (CONST_INT_P (op1))
13909 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
13910 /* Bail out on overflow. We still can swap operands but that
13911 would force loading of the constant into register. */
13912 if (op1 == const0_rtx
13913 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
13915 code = (code == GTU ? GEU : LTU);
13922 code = (code == GTU ? LTU : GEU);
13926 /* Convert a>=0 into (unsigned)a<0x80000000. */
13929 if (mode == DImode || op1 != const0_rtx)
13931 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
13932 code = (code == LT ? GEU : LTU);
13936 if (mode == DImode || op1 != constm1_rtx)
13938 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
13939 code = (code == LE ? GEU : LTU);
13945 /* Swapping operands may cause constant to appear as first operand. */
13946 if (!nonimmediate_operand (op0, VOIDmode))
13948 if (!can_create_pseudo_p ())
13950 op0 = force_reg (mode, op0);
13952 ix86_compare_op0 = op0;
13953 ix86_compare_op1 = op1;
13954 *pop = ix86_expand_compare (code, NULL, NULL);
13955 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
13960 ix86_expand_int_movcc (rtx operands[])
13962 enum rtx_code code = GET_CODE (operands[1]), compare_code;
13963 rtx compare_seq, compare_op;
13964 rtx second_test, bypass_test;
13965 enum machine_mode mode = GET_MODE (operands[0]);
13966 bool sign_bit_compare_p = false;;
13969 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
13970 compare_seq = get_insns ();
13973 compare_code = GET_CODE (compare_op);
13975 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
13976 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
13977 sign_bit_compare_p = true;
13979 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
13980 HImode insns, we'd be swallowed in word prefix ops. */
13982 if ((mode != HImode || TARGET_FAST_PREFIX)
13983 && (mode != (TARGET_64BIT ? TImode : DImode))
13984 && CONST_INT_P (operands[2])
13985 && CONST_INT_P (operands[3]))
13987 rtx out = operands[0];
13988 HOST_WIDE_INT ct = INTVAL (operands[2]);
13989 HOST_WIDE_INT cf = INTVAL (operands[3]);
13990 HOST_WIDE_INT diff;
13993 /* Sign bit compares are better done using shifts than we do by using
13995 if (sign_bit_compare_p
13996 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
13997 ix86_compare_op1, &compare_op))
13999 /* Detect overlap between destination and compare sources. */
14002 if (!sign_bit_compare_p)
14004 bool fpcmp = false;
14006 compare_code = GET_CODE (compare_op);
14008 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14009 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14012 compare_code = ix86_fp_compare_code_to_integer (compare_code);
14015 /* To simplify rest of code, restrict to the GEU case. */
14016 if (compare_code == LTU)
14018 HOST_WIDE_INT tmp = ct;
14021 compare_code = reverse_condition (compare_code);
14022 code = reverse_condition (code);
14027 PUT_CODE (compare_op,
14028 reverse_condition_maybe_unordered
14029 (GET_CODE (compare_op)));
14031 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14035 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
14036 || reg_overlap_mentioned_p (out, ix86_compare_op1))
14037 tmp = gen_reg_rtx (mode);
14039 if (mode == DImode)
14040 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
14042 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
14046 if (code == GT || code == GE)
14047 code = reverse_condition (code);
14050 HOST_WIDE_INT tmp = ct;
14055 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
14056 ix86_compare_op1, VOIDmode, 0, -1);
14069 tmp = expand_simple_binop (mode, PLUS,
14071 copy_rtx (tmp), 1, OPTAB_DIRECT);
14082 tmp = expand_simple_binop (mode, IOR,
14084 copy_rtx (tmp), 1, OPTAB_DIRECT);
14086 else if (diff == -1 && ct)
14096 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14098 tmp = expand_simple_binop (mode, PLUS,
14099 copy_rtx (tmp), GEN_INT (cf),
14100 copy_rtx (tmp), 1, OPTAB_DIRECT);
14108 * andl cf - ct, dest
14118 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14121 tmp = expand_simple_binop (mode, AND,
14123 gen_int_mode (cf - ct, mode),
14124 copy_rtx (tmp), 1, OPTAB_DIRECT);
14126 tmp = expand_simple_binop (mode, PLUS,
14127 copy_rtx (tmp), GEN_INT (ct),
14128 copy_rtx (tmp), 1, OPTAB_DIRECT);
14131 if (!rtx_equal_p (tmp, out))
14132 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
14134 return 1; /* DONE */
14139 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14142 tmp = ct, ct = cf, cf = tmp;
14145 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14147 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14149 /* We may be reversing unordered compare to normal compare, that
14150 is not valid in general (we may convert non-trapping condition
14151 to trapping one), however on i386 we currently emit all
14152 comparisons unordered. */
14153 compare_code = reverse_condition_maybe_unordered (compare_code);
14154 code = reverse_condition_maybe_unordered (code);
14158 compare_code = reverse_condition (compare_code);
14159 code = reverse_condition (code);
14163 compare_code = UNKNOWN;
14164 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
14165 && CONST_INT_P (ix86_compare_op1))
14167 if (ix86_compare_op1 == const0_rtx
14168 && (code == LT || code == GE))
14169 compare_code = code;
14170 else if (ix86_compare_op1 == constm1_rtx)
14174 else if (code == GT)
14179 /* Optimize dest = (op0 < 0) ? -1 : cf. */
14180 if (compare_code != UNKNOWN
14181 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
14182 && (cf == -1 || ct == -1))
14184 /* If lea code below could be used, only optimize
14185 if it results in a 2 insn sequence. */
14187 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
14188 || diff == 3 || diff == 5 || diff == 9)
14189 || (compare_code == LT && ct == -1)
14190 || (compare_code == GE && cf == -1))
14193 * notl op1 (if necessary)
14201 code = reverse_condition (code);
14204 out = emit_store_flag (out, code, ix86_compare_op0,
14205 ix86_compare_op1, VOIDmode, 0, -1);
14207 out = expand_simple_binop (mode, IOR,
14209 out, 1, OPTAB_DIRECT);
14210 if (out != operands[0])
14211 emit_move_insn (operands[0], out);
14213 return 1; /* DONE */
14218 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
14219 || diff == 3 || diff == 5 || diff == 9)
14220 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
14222 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
14228 * lea cf(dest*(ct-cf)),dest
14232 * This also catches the degenerate setcc-only case.
14238 out = emit_store_flag (out, code, ix86_compare_op0,
14239 ix86_compare_op1, VOIDmode, 0, 1);
14242 /* On x86_64 the lea instruction operates on Pmode, so we need
14243 to get arithmetics done in proper mode to match. */
14245 tmp = copy_rtx (out);
14249 out1 = copy_rtx (out);
14250 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
14254 tmp = gen_rtx_PLUS (mode, tmp, out1);
14260 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
14263 if (!rtx_equal_p (tmp, out))
14266 out = force_operand (tmp, copy_rtx (out));
14268 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
14270 if (!rtx_equal_p (out, operands[0]))
14271 emit_move_insn (operands[0], copy_rtx (out));
14273 return 1; /* DONE */
14277 * General case: Jumpful:
14278 * xorl dest,dest cmpl op1, op2
14279 * cmpl op1, op2 movl ct, dest
14280 * setcc dest jcc 1f
14281 * decl dest movl cf, dest
14282 * andl (cf-ct),dest 1:
14285 * Size 20. Size 14.
14287 * This is reasonably steep, but branch mispredict costs are
14288 * high on modern cpus, so consider failing only if optimizing
14292 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
14293 && BRANCH_COST >= 2)
14297 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14302 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14304 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14306 /* We may be reversing unordered compare to normal compare,
14307 that is not valid in general (we may convert non-trapping
14308 condition to trapping one), however on i386 we currently
14309 emit all comparisons unordered. */
14310 code = reverse_condition_maybe_unordered (code);
14314 code = reverse_condition (code);
14315 if (compare_code != UNKNOWN)
14316 compare_code = reverse_condition (compare_code);
14320 if (compare_code != UNKNOWN)
14322 /* notl op1 (if needed)
14327 For x < 0 (resp. x <= -1) there will be no notl,
14328 so if possible swap the constants to get rid of the
14330 True/false will be -1/0 while code below (store flag
14331 followed by decrement) is 0/-1, so the constants need
14332 to be exchanged once more. */
14334 if (compare_code == GE || !cf)
14336 code = reverse_condition (code);
14341 HOST_WIDE_INT tmp = cf;
14346 out = emit_store_flag (out, code, ix86_compare_op0,
14347 ix86_compare_op1, VOIDmode, 0, -1);
14351 out = emit_store_flag (out, code, ix86_compare_op0,
14352 ix86_compare_op1, VOIDmode, 0, 1);
14354 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
14355 copy_rtx (out), 1, OPTAB_DIRECT);
14358 out = expand_simple_binop (mode, AND, copy_rtx (out),
14359 gen_int_mode (cf - ct, mode),
14360 copy_rtx (out), 1, OPTAB_DIRECT);
14362 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
14363 copy_rtx (out), 1, OPTAB_DIRECT);
14364 if (!rtx_equal_p (out, operands[0]))
14365 emit_move_insn (operands[0], copy_rtx (out));
14367 return 1; /* DONE */
14371 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
14373 /* Try a few things more with specific constants and a variable. */
14376 rtx var, orig_out, out, tmp;
14378 if (BRANCH_COST <= 2)
14379 return 0; /* FAIL */
14381 /* If one of the two operands is an interesting constant, load a
14382 constant with the above and mask it in with a logical operation. */
14384 if (CONST_INT_P (operands[2]))
14387 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
14388 operands[3] = constm1_rtx, op = and_optab;
14389 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
14390 operands[3] = const0_rtx, op = ior_optab;
14392 return 0; /* FAIL */
14394 else if (CONST_INT_P (operands[3]))
14397 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
14398 operands[2] = constm1_rtx, op = and_optab;
14399 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
14400 operands[2] = const0_rtx, op = ior_optab;
14402 return 0; /* FAIL */
14405 return 0; /* FAIL */
14407 orig_out = operands[0];
14408 tmp = gen_reg_rtx (mode);
14411 /* Recurse to get the constant loaded. */
14412 if (ix86_expand_int_movcc (operands) == 0)
14413 return 0; /* FAIL */
14415 /* Mask in the interesting variable. */
14416 out = expand_binop (mode, op, var, tmp, orig_out, 0,
14418 if (!rtx_equal_p (out, orig_out))
14419 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
14421 return 1; /* DONE */
14425 * For comparison with above,
14435 if (! nonimmediate_operand (operands[2], mode))
14436 operands[2] = force_reg (mode, operands[2]);
14437 if (! nonimmediate_operand (operands[3], mode))
14438 operands[3] = force_reg (mode, operands[3]);
14440 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
14442 rtx tmp = gen_reg_rtx (mode);
14443 emit_move_insn (tmp, operands[3]);
14446 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
14448 rtx tmp = gen_reg_rtx (mode);
14449 emit_move_insn (tmp, operands[2]);
14453 if (! register_operand (operands[2], VOIDmode)
14455 || ! register_operand (operands[3], VOIDmode)))
14456 operands[2] = force_reg (mode, operands[2]);
14459 && ! register_operand (operands[3], VOIDmode))
14460 operands[3] = force_reg (mode, operands[3]);
14462 emit_insn (compare_seq);
14463 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14464 gen_rtx_IF_THEN_ELSE (mode,
14465 compare_op, operands[2],
14468 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
14469 gen_rtx_IF_THEN_ELSE (mode,
14471 copy_rtx (operands[3]),
14472 copy_rtx (operands[0]))));
14474 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
14475 gen_rtx_IF_THEN_ELSE (mode,
14477 copy_rtx (operands[2]),
14478 copy_rtx (operands[0]))));
14480 return 1; /* DONE */
14483 /* Swap, force into registers, or otherwise massage the two operands
14484 to an sse comparison with a mask result. Thus we differ a bit from
14485 ix86_prepare_fp_compare_args which expects to produce a flags result.
14487 The DEST operand exists to help determine whether to commute commutative
14488 operators. The POP0/POP1 operands are updated in place. The new
14489 comparison code is returned, or UNKNOWN if not implementable. */
14491 static enum rtx_code
14492 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
14493 rtx *pop0, rtx *pop1)
14501 /* We have no LTGT as an operator. We could implement it with
14502 NE & ORDERED, but this requires an extra temporary. It's
14503 not clear that it's worth it. */
14510 /* These are supported directly. */
14517 /* For commutative operators, try to canonicalize the destination
14518 operand to be first in the comparison - this helps reload to
14519 avoid extra moves. */
14520 if (!dest || !rtx_equal_p (dest, *pop1))
14528 /* These are not supported directly. Swap the comparison operands
14529 to transform into something that is supported. */
14533 code = swap_condition (code);
14537 gcc_unreachable ();
14543 /* Detect conditional moves that exactly match min/max operational
14544 semantics. Note that this is IEEE safe, as long as we don't
14545 interchange the operands.
14547 Returns FALSE if this conditional move doesn't match a MIN/MAX,
14548 and TRUE if the operation is successful and instructions are emitted. */
14551 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
14552 rtx cmp_op1, rtx if_true, rtx if_false)
14554 enum machine_mode mode;
14560 else if (code == UNGE)
14563 if_true = if_false;
14569 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
14571 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
14576 mode = GET_MODE (dest);
14578 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
14579 but MODE may be a vector mode and thus not appropriate. */
14580 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
14582 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
14585 if_true = force_reg (mode, if_true);
14586 v = gen_rtvec (2, if_true, if_false);
14587 tmp = gen_rtx_UNSPEC (mode, v, u);
14591 code = is_min ? SMIN : SMAX;
14592 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
14595 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
14599 /* Expand an sse vector comparison. Return the register with the result. */
14602 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
14603 rtx op_true, rtx op_false)
14605 enum machine_mode mode = GET_MODE (dest);
14608 cmp_op0 = force_reg (mode, cmp_op0);
14609 if (!nonimmediate_operand (cmp_op1, mode))
14610 cmp_op1 = force_reg (mode, cmp_op1);
14613 || reg_overlap_mentioned_p (dest, op_true)
14614 || reg_overlap_mentioned_p (dest, op_false))
14615 dest = gen_reg_rtx (mode);
14617 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
14618 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14623 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
14624 operations. This is used for both scalar and vector conditional moves. */
14627 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
14629 enum machine_mode mode = GET_MODE (dest);
14632 if (op_false == CONST0_RTX (mode))
14634 op_true = force_reg (mode, op_true);
14635 x = gen_rtx_AND (mode, cmp, op_true);
14636 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14638 else if (op_true == CONST0_RTX (mode))
14640 op_false = force_reg (mode, op_false);
14641 x = gen_rtx_NOT (mode, cmp);
14642 x = gen_rtx_AND (mode, x, op_false);
14643 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14645 else if (TARGET_SSE5)
14647 rtx pcmov = gen_rtx_SET (mode, dest,
14648 gen_rtx_IF_THEN_ELSE (mode, cmp,
14655 op_true = force_reg (mode, op_true);
14656 op_false = force_reg (mode, op_false);
14658 t2 = gen_reg_rtx (mode);
14660 t3 = gen_reg_rtx (mode);
14664 x = gen_rtx_AND (mode, op_true, cmp);
14665 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
14667 x = gen_rtx_NOT (mode, cmp);
14668 x = gen_rtx_AND (mode, x, op_false);
14669 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
14671 x = gen_rtx_IOR (mode, t3, t2);
14672 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14676 /* Expand a floating-point conditional move. Return true if successful. */
14679 ix86_expand_fp_movcc (rtx operands[])
14681 enum machine_mode mode = GET_MODE (operands[0]);
14682 enum rtx_code code = GET_CODE (operands[1]);
14683 rtx tmp, compare_op, second_test, bypass_test;
14685 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
14687 enum machine_mode cmode;
14689 /* Since we've no cmove for sse registers, don't force bad register
14690 allocation just to gain access to it. Deny movcc when the
14691 comparison mode doesn't match the move mode. */
14692 cmode = GET_MODE (ix86_compare_op0);
14693 if (cmode == VOIDmode)
14694 cmode = GET_MODE (ix86_compare_op1);
14698 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
14700 &ix86_compare_op1);
14701 if (code == UNKNOWN)
14704 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
14705 ix86_compare_op1, operands[2],
14709 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
14710 ix86_compare_op1, operands[2], operands[3]);
14711 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
14715 /* The floating point conditional move instructions don't directly
14716 support conditions resulting from a signed integer comparison. */
14718 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14720 /* The floating point conditional move instructions don't directly
14721 support signed integer comparisons. */
14723 if (!fcmov_comparison_operator (compare_op, VOIDmode))
14725 gcc_assert (!second_test && !bypass_test);
14726 tmp = gen_reg_rtx (QImode);
14727 ix86_expand_setcc (code, tmp);
14729 ix86_compare_op0 = tmp;
14730 ix86_compare_op1 = const0_rtx;
14731 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14733 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
14735 tmp = gen_reg_rtx (mode);
14736 emit_move_insn (tmp, operands[3]);
14739 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
14741 tmp = gen_reg_rtx (mode);
14742 emit_move_insn (tmp, operands[2]);
14746 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14747 gen_rtx_IF_THEN_ELSE (mode, compare_op,
14748 operands[2], operands[3])));
14750 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14751 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
14752 operands[3], operands[0])));
14754 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
14755 gen_rtx_IF_THEN_ELSE (mode, second_test,
14756 operands[2], operands[0])));
14761 /* Expand a floating-point vector conditional move; a vcond operation
14762 rather than a movcc operation. */
14765 ix86_expand_fp_vcond (rtx operands[])
14767 enum rtx_code code = GET_CODE (operands[3]);
14770 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
14771 &operands[4], &operands[5]);
14772 if (code == UNKNOWN)
14775 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
14776 operands[5], operands[1], operands[2]))
14779 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
14780 operands[1], operands[2]);
14781 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
14785 /* Expand a signed/unsigned integral vector conditional move. */
14788 ix86_expand_int_vcond (rtx operands[])
14790 enum machine_mode mode = GET_MODE (operands[0]);
14791 enum rtx_code code = GET_CODE (operands[3]);
14792 bool negate = false;
14795 cop0 = operands[4];
14796 cop1 = operands[5];
14798 /* SSE5 supports all of the comparisons on all vector int types. */
14801 /* Canonicalize the comparison to EQ, GT, GTU. */
14812 code = reverse_condition (code);
14818 code = reverse_condition (code);
14824 code = swap_condition (code);
14825 x = cop0, cop0 = cop1, cop1 = x;
14829 gcc_unreachable ();
14832 /* Only SSE4.1/SSE4.2 supports V2DImode. */
14833 if (mode == V2DImode)
14838 /* SSE4.1 supports EQ. */
14839 if (!TARGET_SSE4_1)
14845 /* SSE4.2 supports GT/GTU. */
14846 if (!TARGET_SSE4_2)
14851 gcc_unreachable ();
14855 /* Unsigned parallel compare is not supported by the hardware. Play some
14856 tricks to turn this into a signed comparison against 0. */
14859 cop0 = force_reg (mode, cop0);
14868 /* Perform a parallel modulo subtraction. */
14869 t1 = gen_reg_rtx (mode);
14870 emit_insn ((mode == V4SImode
14872 : gen_subv2di3) (t1, cop0, cop1));
14874 /* Extract the original sign bit of op0. */
14875 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
14877 t2 = gen_reg_rtx (mode);
14878 emit_insn ((mode == V4SImode
14880 : gen_andv2di3) (t2, cop0, mask));
14882 /* XOR it back into the result of the subtraction. This results
14883 in the sign bit set iff we saw unsigned underflow. */
14884 x = gen_reg_rtx (mode);
14885 emit_insn ((mode == V4SImode
14887 : gen_xorv2di3) (x, t1, t2));
14895 /* Perform a parallel unsigned saturating subtraction. */
14896 x = gen_reg_rtx (mode);
14897 emit_insn (gen_rtx_SET (VOIDmode, x,
14898 gen_rtx_US_MINUS (mode, cop0, cop1)));
14905 gcc_unreachable ();
14909 cop1 = CONST0_RTX (mode);
14913 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
14914 operands[1+negate], operands[2-negate]);
14916 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
14917 operands[2-negate]);
14921 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
14922 true if we should do zero extension, else sign extension. HIGH_P is
14923 true if we want the N/2 high elements, else the low elements. */
14926 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
14928 enum machine_mode imode = GET_MODE (operands[1]);
14929 rtx (*unpack)(rtx, rtx, rtx);
14936 unpack = gen_vec_interleave_highv16qi;
14938 unpack = gen_vec_interleave_lowv16qi;
14942 unpack = gen_vec_interleave_highv8hi;
14944 unpack = gen_vec_interleave_lowv8hi;
14948 unpack = gen_vec_interleave_highv4si;
14950 unpack = gen_vec_interleave_lowv4si;
14953 gcc_unreachable ();
14956 dest = gen_lowpart (imode, operands[0]);
14959 se = force_reg (imode, CONST0_RTX (imode));
14961 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
14962 operands[1], pc_rtx, pc_rtx);
14964 emit_insn (unpack (dest, operands[1], se));
14967 /* This function performs the same task as ix86_expand_sse_unpack,
14968 but with SSE4.1 instructions. */
14971 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
14973 enum machine_mode imode = GET_MODE (operands[1]);
14974 rtx (*unpack)(rtx, rtx);
14981 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
14983 unpack = gen_sse4_1_extendv8qiv8hi2;
14987 unpack = gen_sse4_1_zero_extendv4hiv4si2;
14989 unpack = gen_sse4_1_extendv4hiv4si2;
14993 unpack = gen_sse4_1_zero_extendv2siv2di2;
14995 unpack = gen_sse4_1_extendv2siv2di2;
14998 gcc_unreachable ();
15001 dest = operands[0];
15004 /* Shift higher 8 bytes to lower 8 bytes. */
15005 src = gen_reg_rtx (imode);
15006 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
15007 gen_lowpart (TImode, operands[1]),
15013 emit_insn (unpack (dest, src));
15016 /* This function performs the same task as ix86_expand_sse_unpack,
15017 but with sse5 instructions. */
15020 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15022 enum machine_mode imode = GET_MODE (operands[1]);
15023 int pperm_bytes[16];
15025 int h = (high_p) ? 8 : 0;
15028 rtvec v = rtvec_alloc (16);
15031 rtx op0 = operands[0], op1 = operands[1];
15036 vs = rtvec_alloc (8);
15037 h2 = (high_p) ? 8 : 0;
15038 for (i = 0; i < 8; i++)
15040 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
15041 pperm_bytes[2*i+1] = ((unsigned_p)
15043 : PPERM_SIGN | PPERM_SRC2 | i | h);
15046 for (i = 0; i < 16; i++)
15047 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15049 for (i = 0; i < 8; i++)
15050 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15052 p = gen_rtx_PARALLEL (VOIDmode, vs);
15053 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15055 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
15057 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
15061 vs = rtvec_alloc (4);
15062 h2 = (high_p) ? 4 : 0;
15063 for (i = 0; i < 4; i++)
15065 sign_extend = ((unsigned_p)
15067 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
15068 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
15069 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
15070 pperm_bytes[4*i+2] = sign_extend;
15071 pperm_bytes[4*i+3] = sign_extend;
15074 for (i = 0; i < 16; i++)
15075 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15077 for (i = 0; i < 4; i++)
15078 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15080 p = gen_rtx_PARALLEL (VOIDmode, vs);
15081 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15083 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
15085 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
15089 vs = rtvec_alloc (2);
15090 h2 = (high_p) ? 2 : 0;
15091 for (i = 0; i < 2; i++)
15093 sign_extend = ((unsigned_p)
15095 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
15096 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
15097 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
15098 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
15099 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
15100 pperm_bytes[8*i+4] = sign_extend;
15101 pperm_bytes[8*i+5] = sign_extend;
15102 pperm_bytes[8*i+6] = sign_extend;
15103 pperm_bytes[8*i+7] = sign_extend;
15106 for (i = 0; i < 16; i++)
15107 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15109 for (i = 0; i < 2; i++)
15110 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15112 p = gen_rtx_PARALLEL (VOIDmode, vs);
15113 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15115 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
15117 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
15121 gcc_unreachable ();
15127 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15128 next narrower integer vector type */
15130 ix86_expand_sse5_pack (rtx operands[3])
15132 enum machine_mode imode = GET_MODE (operands[0]);
15133 int pperm_bytes[16];
15135 rtvec v = rtvec_alloc (16);
15137 rtx op0 = operands[0];
15138 rtx op1 = operands[1];
15139 rtx op2 = operands[2];
15144 for (i = 0; i < 8; i++)
15146 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
15147 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
15150 for (i = 0; i < 16; i++)
15151 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15153 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15154 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
15158 for (i = 0; i < 4; i++)
15160 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
15161 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
15162 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
15163 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
15166 for (i = 0; i < 16; i++)
15167 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15169 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15170 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
15174 for (i = 0; i < 2; i++)
15176 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
15177 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
15178 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
15179 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
15180 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
15181 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
15182 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
15183 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
15186 for (i = 0; i < 16; i++)
15187 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15189 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15190 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
15194 gcc_unreachable ();
15200 /* Expand conditional increment or decrement using adb/sbb instructions.
15201 The default case using setcc followed by the conditional move can be
15202 done by generic code. */
15204 ix86_expand_int_addcc (rtx operands[])
15206 enum rtx_code code = GET_CODE (operands[1]);
15208 rtx val = const0_rtx;
15209 bool fpcmp = false;
15210 enum machine_mode mode = GET_MODE (operands[0]);
15212 if (operands[3] != const1_rtx
15213 && operands[3] != constm1_rtx)
15215 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15216 ix86_compare_op1, &compare_op))
15218 code = GET_CODE (compare_op);
15220 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15221 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15224 code = ix86_fp_compare_code_to_integer (code);
15231 PUT_CODE (compare_op,
15232 reverse_condition_maybe_unordered
15233 (GET_CODE (compare_op)));
15235 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15237 PUT_MODE (compare_op, mode);
15239 /* Construct either adc or sbb insn. */
15240 if ((code == LTU) == (operands[3] == constm1_rtx))
15242 switch (GET_MODE (operands[0]))
15245 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
15248 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
15251 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
15254 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15257 gcc_unreachable ();
15262 switch (GET_MODE (operands[0]))
15265 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
15268 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
15271 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
15274 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15277 gcc_unreachable ();
15280 return 1; /* DONE */
15284 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
15285 works for floating pointer parameters and nonoffsetable memories.
15286 For pushes, it returns just stack offsets; the values will be saved
15287 in the right order. Maximally three parts are generated. */
15290 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
15295 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
15297 size = (GET_MODE_SIZE (mode) + 4) / 8;
15299 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
15300 gcc_assert (size >= 2 && size <= 4);
15302 /* Optimize constant pool reference to immediates. This is used by fp
15303 moves, that force all constants to memory to allow combining. */
15304 if (MEM_P (operand) && MEM_READONLY_P (operand))
15306 rtx tmp = maybe_get_pool_constant (operand);
15311 if (MEM_P (operand) && !offsettable_memref_p (operand))
15313 /* The only non-offsetable memories we handle are pushes. */
15314 int ok = push_operand (operand, VOIDmode);
15318 operand = copy_rtx (operand);
15319 PUT_MODE (operand, Pmode);
15320 parts[0] = parts[1] = parts[2] = parts[3] = operand;
15324 if (GET_CODE (operand) == CONST_VECTOR)
15326 enum machine_mode imode = int_mode_for_mode (mode);
15327 /* Caution: if we looked through a constant pool memory above,
15328 the operand may actually have a different mode now. That's
15329 ok, since we want to pun this all the way back to an integer. */
15330 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
15331 gcc_assert (operand != NULL);
15337 if (mode == DImode)
15338 split_di (&operand, 1, &parts[0], &parts[1]);
15343 if (REG_P (operand))
15345 gcc_assert (reload_completed);
15346 for (i = 0; i < size; i++)
15347 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
15349 else if (offsettable_memref_p (operand))
15351 operand = adjust_address (operand, SImode, 0);
15352 parts[0] = operand;
15353 for (i = 1; i < size; i++)
15354 parts[i] = adjust_address (operand, SImode, 4 * i);
15356 else if (GET_CODE (operand) == CONST_DOUBLE)
15361 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
15365 real_to_target (l, &r, mode);
15366 parts[3] = gen_int_mode (l[3], SImode);
15367 parts[2] = gen_int_mode (l[2], SImode);
15370 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
15371 parts[2] = gen_int_mode (l[2], SImode);
15374 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
15377 gcc_unreachable ();
15379 parts[1] = gen_int_mode (l[1], SImode);
15380 parts[0] = gen_int_mode (l[0], SImode);
15383 gcc_unreachable ();
15388 if (mode == TImode)
15389 split_ti (&operand, 1, &parts[0], &parts[1]);
15390 if (mode == XFmode || mode == TFmode)
15392 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
15393 if (REG_P (operand))
15395 gcc_assert (reload_completed);
15396 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
15397 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
15399 else if (offsettable_memref_p (operand))
15401 operand = adjust_address (operand, DImode, 0);
15402 parts[0] = operand;
15403 parts[1] = adjust_address (operand, upper_mode, 8);
15405 else if (GET_CODE (operand) == CONST_DOUBLE)
15410 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
15411 real_to_target (l, &r, mode);
15413 /* Do not use shift by 32 to avoid warning on 32bit systems. */
15414 if (HOST_BITS_PER_WIDE_INT >= 64)
15417 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
15418 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
15421 parts[0] = immed_double_const (l[0], l[1], DImode);
15423 if (upper_mode == SImode)
15424 parts[1] = gen_int_mode (l[2], SImode);
15425 else if (HOST_BITS_PER_WIDE_INT >= 64)
15428 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
15429 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
15432 parts[1] = immed_double_const (l[2], l[3], DImode);
15435 gcc_unreachable ();
15442 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
15443 Return false when normal moves are needed; true when all required
15444 insns have been emitted. Operands 2-4 contain the input values
15445 int the correct order; operands 5-7 contain the output values. */
15448 ix86_split_long_move (rtx operands[])
15453 int collisions = 0;
15454 enum machine_mode mode = GET_MODE (operands[0]);
15455 bool collisionparts[4];
15457 /* The DFmode expanders may ask us to move double.
15458 For 64bit target this is single move. By hiding the fact
15459 here we simplify i386.md splitters. */
15460 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
15462 /* Optimize constant pool reference to immediates. This is used by
15463 fp moves, that force all constants to memory to allow combining. */
15465 if (MEM_P (operands[1])
15466 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
15467 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
15468 operands[1] = get_pool_constant (XEXP (operands[1], 0));
15469 if (push_operand (operands[0], VOIDmode))
15471 operands[0] = copy_rtx (operands[0]);
15472 PUT_MODE (operands[0], Pmode);
15475 operands[0] = gen_lowpart (DImode, operands[0]);
15476 operands[1] = gen_lowpart (DImode, operands[1]);
15477 emit_move_insn (operands[0], operands[1]);
15481 /* The only non-offsettable memory we handle is push. */
15482 if (push_operand (operands[0], VOIDmode))
15485 gcc_assert (!MEM_P (operands[0])
15486 || offsettable_memref_p (operands[0]));
15488 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
15489 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
15491 /* When emitting push, take care for source operands on the stack. */
15492 if (push && MEM_P (operands[1])
15493 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
15494 for (i = 0; i < nparts - 1; i++)
15495 part[1][i] = change_address (part[1][i],
15496 GET_MODE (part[1][i]),
15497 XEXP (part[1][i + 1], 0));
15499 /* We need to do copy in the right order in case an address register
15500 of the source overlaps the destination. */
15501 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
15505 for (i = 0; i < nparts; i++)
15508 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
15509 if (collisionparts[i])
15513 /* Collision in the middle part can be handled by reordering. */
15514 if (collisions == 1 && nparts == 3 && collisionparts [1])
15516 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
15517 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
15519 else if (collisions == 1
15521 && (collisionparts [1] || collisionparts [2]))
15523 if (collisionparts [1])
15525 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
15526 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
15530 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
15531 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
15535 /* If there are more collisions, we can't handle it by reordering.
15536 Do an lea to the last part and use only one colliding move. */
15537 else if (collisions > 1)
15543 base = part[0][nparts - 1];
15545 /* Handle the case when the last part isn't valid for lea.
15546 Happens in 64-bit mode storing the 12-byte XFmode. */
15547 if (GET_MODE (base) != Pmode)
15548 base = gen_rtx_REG (Pmode, REGNO (base));
15550 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
15551 part[1][0] = replace_equiv_address (part[1][0], base);
15552 for (i = 1; i < nparts; i++)
15554 tmp = plus_constant (base, UNITS_PER_WORD * i);
15555 part[1][i] = replace_equiv_address (part[1][i], tmp);
15566 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
15567 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
15568 emit_move_insn (part[0][2], part[1][2]);
15570 else if (nparts == 4)
15572 emit_move_insn (part[0][3], part[1][3]);
15573 emit_move_insn (part[0][2], part[1][2]);
15578 /* In 64bit mode we don't have 32bit push available. In case this is
15579 register, it is OK - we will just use larger counterpart. We also
15580 retype memory - these comes from attempt to avoid REX prefix on
15581 moving of second half of TFmode value. */
15582 if (GET_MODE (part[1][1]) == SImode)
15584 switch (GET_CODE (part[1][1]))
15587 part[1][1] = adjust_address (part[1][1], DImode, 0);
15591 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
15595 gcc_unreachable ();
15598 if (GET_MODE (part[1][0]) == SImode)
15599 part[1][0] = part[1][1];
15602 emit_move_insn (part[0][1], part[1][1]);
15603 emit_move_insn (part[0][0], part[1][0]);
15607 /* Choose correct order to not overwrite the source before it is copied. */
15608 if ((REG_P (part[0][0])
15609 && REG_P (part[1][1])
15610 && (REGNO (part[0][0]) == REGNO (part[1][1])
15612 && REGNO (part[0][0]) == REGNO (part[1][2]))
15614 && REGNO (part[0][0]) == REGNO (part[1][3]))))
15616 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
15618 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
15620 operands[2 + i] = part[0][j];
15621 operands[6 + i] = part[1][j];
15626 for (i = 0; i < nparts; i++)
15628 operands[2 + i] = part[0][i];
15629 operands[6 + i] = part[1][i];
15633 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
15634 if (optimize_insn_for_size_p ())
15636 for (j = 0; j < nparts - 1; j++)
15637 if (CONST_INT_P (operands[6 + j])
15638 && operands[6 + j] != const0_rtx
15639 && REG_P (operands[2 + j]))
15640 for (i = j; i < nparts - 1; i++)
15641 if (CONST_INT_P (operands[7 + i])
15642 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
15643 operands[7 + i] = operands[2 + j];
15646 for (i = 0; i < nparts; i++)
15647 emit_move_insn (operands[2 + i], operands[6 + i]);
15652 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
15653 left shift by a constant, either using a single shift or
15654 a sequence of add instructions. */
15657 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
15661 emit_insn ((mode == DImode
15663 : gen_adddi3) (operand, operand, operand));
15665 else if (!optimize_insn_for_size_p ()
15666 && count * ix86_cost->add <= ix86_cost->shift_const)
15669 for (i=0; i<count; i++)
15671 emit_insn ((mode == DImode
15673 : gen_adddi3) (operand, operand, operand));
15677 emit_insn ((mode == DImode
15679 : gen_ashldi3) (operand, operand, GEN_INT (count)));
15683 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
15685 rtx low[2], high[2];
15687 const int single_width = mode == DImode ? 32 : 64;
15689 if (CONST_INT_P (operands[2]))
15691 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
15692 count = INTVAL (operands[2]) & (single_width * 2 - 1);
15694 if (count >= single_width)
15696 emit_move_insn (high[0], low[1]);
15697 emit_move_insn (low[0], const0_rtx);
15699 if (count > single_width)
15700 ix86_expand_ashl_const (high[0], count - single_width, mode);
15704 if (!rtx_equal_p (operands[0], operands[1]))
15705 emit_move_insn (operands[0], operands[1]);
15706 emit_insn ((mode == DImode
15708 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
15709 ix86_expand_ashl_const (low[0], count, mode);
15714 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
15716 if (operands[1] == const1_rtx)
15718 /* Assuming we've chosen a QImode capable registers, then 1 << N
15719 can be done with two 32/64-bit shifts, no branches, no cmoves. */
15720 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
15722 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
15724 ix86_expand_clear (low[0]);
15725 ix86_expand_clear (high[0]);
15726 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
15728 d = gen_lowpart (QImode, low[0]);
15729 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
15730 s = gen_rtx_EQ (QImode, flags, const0_rtx);
15731 emit_insn (gen_rtx_SET (VOIDmode, d, s));
15733 d = gen_lowpart (QImode, high[0]);
15734 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
15735 s = gen_rtx_NE (QImode, flags, const0_rtx);
15736 emit_insn (gen_rtx_SET (VOIDmode, d, s));
15739 /* Otherwise, we can get the same results by manually performing
15740 a bit extract operation on bit 5/6, and then performing the two
15741 shifts. The two methods of getting 0/1 into low/high are exactly
15742 the same size. Avoiding the shift in the bit extract case helps
15743 pentium4 a bit; no one else seems to care much either way. */
15748 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
15749 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
15751 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
15752 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
15754 emit_insn ((mode == DImode
15756 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
15757 emit_insn ((mode == DImode
15759 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
15760 emit_move_insn (low[0], high[0]);
15761 emit_insn ((mode == DImode
15763 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
15766 emit_insn ((mode == DImode
15768 : gen_ashldi3) (low[0], low[0], operands[2]));
15769 emit_insn ((mode == DImode
15771 : gen_ashldi3) (high[0], high[0], operands[2]));
15775 if (operands[1] == constm1_rtx)
15777 /* For -1 << N, we can avoid the shld instruction, because we
15778 know that we're shifting 0...31/63 ones into a -1. */
15779 emit_move_insn (low[0], constm1_rtx);
15780 if (optimize_insn_for_size_p ())
15781 emit_move_insn (high[0], low[0]);
15783 emit_move_insn (high[0], constm1_rtx);
15787 if (!rtx_equal_p (operands[0], operands[1]))
15788 emit_move_insn (operands[0], operands[1]);
15790 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
15791 emit_insn ((mode == DImode
15793 : gen_x86_64_shld) (high[0], low[0], operands[2]));
15796 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
15798 if (TARGET_CMOVE && scratch)
15800 ix86_expand_clear (scratch);
15801 emit_insn ((mode == DImode
15802 ? gen_x86_shift_adj_1
15803 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
15807 emit_insn ((mode == DImode
15808 ? gen_x86_shift_adj_2
15809 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
15813 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
15815 rtx low[2], high[2];
15817 const int single_width = mode == DImode ? 32 : 64;
15819 if (CONST_INT_P (operands[2]))
15821 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
15822 count = INTVAL (operands[2]) & (single_width * 2 - 1);
15824 if (count == single_width * 2 - 1)
15826 emit_move_insn (high[0], high[1]);
15827 emit_insn ((mode == DImode
15829 : gen_ashrdi3) (high[0], high[0],
15830 GEN_INT (single_width - 1)));
15831 emit_move_insn (low[0], high[0]);
15834 else if (count >= single_width)
15836 emit_move_insn (low[0], high[1]);
15837 emit_move_insn (high[0], low[0]);
15838 emit_insn ((mode == DImode
15840 : gen_ashrdi3) (high[0], high[0],
15841 GEN_INT (single_width - 1)));
15842 if (count > single_width)
15843 emit_insn ((mode == DImode
15845 : gen_ashrdi3) (low[0], low[0],
15846 GEN_INT (count - single_width)));
15850 if (!rtx_equal_p (operands[0], operands[1]))
15851 emit_move_insn (operands[0], operands[1]);
15852 emit_insn ((mode == DImode
15854 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
15855 emit_insn ((mode == DImode
15857 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
15862 if (!rtx_equal_p (operands[0], operands[1]))
15863 emit_move_insn (operands[0], operands[1]);
15865 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
15867 emit_insn ((mode == DImode
15869 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
15870 emit_insn ((mode == DImode
15872 : gen_ashrdi3) (high[0], high[0], operands[2]));
15874 if (TARGET_CMOVE && scratch)
15876 emit_move_insn (scratch, high[0]);
15877 emit_insn ((mode == DImode
15879 : gen_ashrdi3) (scratch, scratch,
15880 GEN_INT (single_width - 1)));
15881 emit_insn ((mode == DImode
15882 ? gen_x86_shift_adj_1
15883 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
15887 emit_insn ((mode == DImode
15888 ? gen_x86_shift_adj_3
15889 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
15894 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
15896 rtx low[2], high[2];
15898 const int single_width = mode == DImode ? 32 : 64;
15900 if (CONST_INT_P (operands[2]))
15902 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
15903 count = INTVAL (operands[2]) & (single_width * 2 - 1);
15905 if (count >= single_width)
15907 emit_move_insn (low[0], high[1]);
15908 ix86_expand_clear (high[0]);
15910 if (count > single_width)
15911 emit_insn ((mode == DImode
15913 : gen_lshrdi3) (low[0], low[0],
15914 GEN_INT (count - single_width)));
15918 if (!rtx_equal_p (operands[0], operands[1]))
15919 emit_move_insn (operands[0], operands[1]);
15920 emit_insn ((mode == DImode
15922 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
15923 emit_insn ((mode == DImode
15925 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
15930 if (!rtx_equal_p (operands[0], operands[1]))
15931 emit_move_insn (operands[0], operands[1]);
15933 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
15935 emit_insn ((mode == DImode
15937 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
15938 emit_insn ((mode == DImode
15940 : gen_lshrdi3) (high[0], high[0], operands[2]));
15942 /* Heh. By reversing the arguments, we can reuse this pattern. */
15943 if (TARGET_CMOVE && scratch)
15945 ix86_expand_clear (scratch);
15946 emit_insn ((mode == DImode
15947 ? gen_x86_shift_adj_1
15948 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
15952 emit_insn ((mode == DImode
15953 ? gen_x86_shift_adj_2
15954 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
15958 /* Predict just emitted jump instruction to be taken with probability PROB. */
15960 predict_jump (int prob)
15962 rtx insn = get_last_insn ();
15963 gcc_assert (JUMP_P (insn));
15965 = gen_rtx_EXPR_LIST (REG_BR_PROB,
15970 /* Helper function for the string operations below. Dest VARIABLE whether
15971 it is aligned to VALUE bytes. If true, jump to the label. */
15973 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
15975 rtx label = gen_label_rtx ();
15976 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
15977 if (GET_MODE (variable) == DImode)
15978 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
15980 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
15981 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
15984 predict_jump (REG_BR_PROB_BASE * 50 / 100);
15986 predict_jump (REG_BR_PROB_BASE * 90 / 100);
15990 /* Adjust COUNTER by the VALUE. */
15992 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
15994 if (GET_MODE (countreg) == DImode)
15995 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
15997 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16000 /* Zero extend possibly SImode EXP to Pmode register. */
16002 ix86_zero_extend_to_Pmode (rtx exp)
16005 if (GET_MODE (exp) == VOIDmode)
16006 return force_reg (Pmode, exp);
16007 if (GET_MODE (exp) == Pmode)
16008 return copy_to_mode_reg (Pmode, exp);
16009 r = gen_reg_rtx (Pmode);
16010 emit_insn (gen_zero_extendsidi2 (r, exp));
16014 /* Divide COUNTREG by SCALE. */
16016 scale_counter (rtx countreg, int scale)
16019 rtx piece_size_mask;
16023 if (CONST_INT_P (countreg))
16024 return GEN_INT (INTVAL (countreg) / scale);
16025 gcc_assert (REG_P (countreg));
16027 piece_size_mask = GEN_INT (scale - 1);
16028 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16029 GEN_INT (exact_log2 (scale)),
16030 NULL, 1, OPTAB_DIRECT);
16034 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16035 DImode for constant loop counts. */
16037 static enum machine_mode
16038 counter_mode (rtx count_exp)
16040 if (GET_MODE (count_exp) != VOIDmode)
16041 return GET_MODE (count_exp);
16042 if (GET_CODE (count_exp) != CONST_INT)
16044 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
16049 /* When SRCPTR is non-NULL, output simple loop to move memory
16050 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16051 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16052 equivalent loop to set memory by VALUE (supposed to be in MODE).
16054 The size is rounded down to whole number of chunk size moved at once.
16055 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16059 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
16060 rtx destptr, rtx srcptr, rtx value,
16061 rtx count, enum machine_mode mode, int unroll,
16064 rtx out_label, top_label, iter, tmp;
16065 enum machine_mode iter_mode = counter_mode (count);
16066 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
16067 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
16073 top_label = gen_label_rtx ();
16074 out_label = gen_label_rtx ();
16075 iter = gen_reg_rtx (iter_mode);
16077 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
16078 NULL, 1, OPTAB_DIRECT);
16079 /* Those two should combine. */
16080 if (piece_size == const1_rtx)
16082 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
16084 predict_jump (REG_BR_PROB_BASE * 10 / 100);
16086 emit_move_insn (iter, const0_rtx);
16088 emit_label (top_label);
16090 tmp = convert_modes (Pmode, iter_mode, iter, true);
16091 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
16092 destmem = change_address (destmem, mode, x_addr);
16096 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
16097 srcmem = change_address (srcmem, mode, y_addr);
16099 /* When unrolling for chips that reorder memory reads and writes,
16100 we can save registers by using single temporary.
16101 Also using 4 temporaries is overkill in 32bit mode. */
16102 if (!TARGET_64BIT && 0)
16104 for (i = 0; i < unroll; i++)
16109 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16111 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16113 emit_move_insn (destmem, srcmem);
16119 gcc_assert (unroll <= 4);
16120 for (i = 0; i < unroll; i++)
16122 tmpreg[i] = gen_reg_rtx (mode);
16126 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16128 emit_move_insn (tmpreg[i], srcmem);
16130 for (i = 0; i < unroll; i++)
16135 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16137 emit_move_insn (destmem, tmpreg[i]);
16142 for (i = 0; i < unroll; i++)
16146 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16147 emit_move_insn (destmem, value);
16150 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
16151 true, OPTAB_LIB_WIDEN);
16153 emit_move_insn (iter, tmp);
16155 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
16157 if (expected_size != -1)
16159 expected_size /= GET_MODE_SIZE (mode) * unroll;
16160 if (expected_size == 0)
16162 else if (expected_size > REG_BR_PROB_BASE)
16163 predict_jump (REG_BR_PROB_BASE - 1);
16165 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
16168 predict_jump (REG_BR_PROB_BASE * 80 / 100);
16169 iter = ix86_zero_extend_to_Pmode (iter);
16170 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
16171 true, OPTAB_LIB_WIDEN);
16172 if (tmp != destptr)
16173 emit_move_insn (destptr, tmp);
16176 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
16177 true, OPTAB_LIB_WIDEN);
16179 emit_move_insn (srcptr, tmp);
16181 emit_label (out_label);
16184 /* Output "rep; mov" instruction.
16185 Arguments have same meaning as for previous function */
16187 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
16188 rtx destptr, rtx srcptr,
16190 enum machine_mode mode)
16196 /* If the size is known, it is shorter to use rep movs. */
16197 if (mode == QImode && CONST_INT_P (count)
16198 && !(INTVAL (count) & 3))
16201 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16202 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16203 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
16204 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
16205 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16206 if (mode != QImode)
16208 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16209 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16210 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16211 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
16212 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16213 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
16217 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16218 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
16220 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
16224 /* Output "rep; stos" instruction.
16225 Arguments have same meaning as for previous function */
16227 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
16229 enum machine_mode mode)
16234 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16235 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16236 value = force_reg (mode, gen_lowpart (mode, value));
16237 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16238 if (mode != QImode)
16240 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16241 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16242 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16245 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16246 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
16250 emit_strmov (rtx destmem, rtx srcmem,
16251 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
16253 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
16254 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
16255 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16258 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
16260 expand_movmem_epilogue (rtx destmem, rtx srcmem,
16261 rtx destptr, rtx srcptr, rtx count, int max_size)
16264 if (CONST_INT_P (count))
16266 HOST_WIDE_INT countval = INTVAL (count);
16269 if ((countval & 0x10) && max_size > 16)
16273 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
16274 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
16277 gcc_unreachable ();
16280 if ((countval & 0x08) && max_size > 8)
16283 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
16286 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
16287 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
16291 if ((countval & 0x04) && max_size > 4)
16293 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
16296 if ((countval & 0x02) && max_size > 2)
16298 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
16301 if ((countval & 0x01) && max_size > 1)
16303 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
16310 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
16311 count, 1, OPTAB_DIRECT);
16312 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
16313 count, QImode, 1, 4);
16317 /* When there are stringops, we can cheaply increase dest and src pointers.
16318 Otherwise we save code size by maintaining offset (zero is readily
16319 available from preceding rep operation) and using x86 addressing modes.
16321 if (TARGET_SINGLE_STRINGOP)
16325 rtx label = ix86_expand_aligntest (count, 4, true);
16326 src = change_address (srcmem, SImode, srcptr);
16327 dest = change_address (destmem, SImode, destptr);
16328 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16329 emit_label (label);
16330 LABEL_NUSES (label) = 1;
16334 rtx label = ix86_expand_aligntest (count, 2, true);
16335 src = change_address (srcmem, HImode, srcptr);
16336 dest = change_address (destmem, HImode, destptr);
16337 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16338 emit_label (label);
16339 LABEL_NUSES (label) = 1;
16343 rtx label = ix86_expand_aligntest (count, 1, true);
16344 src = change_address (srcmem, QImode, srcptr);
16345 dest = change_address (destmem, QImode, destptr);
16346 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16347 emit_label (label);
16348 LABEL_NUSES (label) = 1;
16353 rtx offset = force_reg (Pmode, const0_rtx);
16358 rtx label = ix86_expand_aligntest (count, 4, true);
16359 src = change_address (srcmem, SImode, srcptr);
16360 dest = change_address (destmem, SImode, destptr);
16361 emit_move_insn (dest, src);
16362 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
16363 true, OPTAB_LIB_WIDEN);
16365 emit_move_insn (offset, tmp);
16366 emit_label (label);
16367 LABEL_NUSES (label) = 1;
16371 rtx label = ix86_expand_aligntest (count, 2, true);
16372 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
16373 src = change_address (srcmem, HImode, tmp);
16374 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
16375 dest = change_address (destmem, HImode, tmp);
16376 emit_move_insn (dest, src);
16377 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
16378 true, OPTAB_LIB_WIDEN);
16380 emit_move_insn (offset, tmp);
16381 emit_label (label);
16382 LABEL_NUSES (label) = 1;
16386 rtx label = ix86_expand_aligntest (count, 1, true);
16387 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
16388 src = change_address (srcmem, QImode, tmp);
16389 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
16390 dest = change_address (destmem, QImode, tmp);
16391 emit_move_insn (dest, src);
16392 emit_label (label);
16393 LABEL_NUSES (label) = 1;
16398 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16400 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
16401 rtx count, int max_size)
16404 expand_simple_binop (counter_mode (count), AND, count,
16405 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
16406 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
16407 gen_lowpart (QImode, value), count, QImode,
16411 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
16413 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
16417 if (CONST_INT_P (count))
16419 HOST_WIDE_INT countval = INTVAL (count);
16422 if ((countval & 0x10) && max_size > 16)
16426 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
16427 emit_insn (gen_strset (destptr, dest, value));
16428 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
16429 emit_insn (gen_strset (destptr, dest, value));
16432 gcc_unreachable ();
16435 if ((countval & 0x08) && max_size > 8)
16439 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
16440 emit_insn (gen_strset (destptr, dest, value));
16444 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
16445 emit_insn (gen_strset (destptr, dest, value));
16446 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
16447 emit_insn (gen_strset (destptr, dest, value));
16451 if ((countval & 0x04) && max_size > 4)
16453 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
16454 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
16457 if ((countval & 0x02) && max_size > 2)
16459 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
16460 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
16463 if ((countval & 0x01) && max_size > 1)
16465 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
16466 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
16473 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
16478 rtx label = ix86_expand_aligntest (count, 16, true);
16481 dest = change_address (destmem, DImode, destptr);
16482 emit_insn (gen_strset (destptr, dest, value));
16483 emit_insn (gen_strset (destptr, dest, value));
16487 dest = change_address (destmem, SImode, destptr);
16488 emit_insn (gen_strset (destptr, dest, value));
16489 emit_insn (gen_strset (destptr, dest, value));
16490 emit_insn (gen_strset (destptr, dest, value));
16491 emit_insn (gen_strset (destptr, dest, value));
16493 emit_label (label);
16494 LABEL_NUSES (label) = 1;
16498 rtx label = ix86_expand_aligntest (count, 8, true);
16501 dest = change_address (destmem, DImode, destptr);
16502 emit_insn (gen_strset (destptr, dest, value));
16506 dest = change_address (destmem, SImode, destptr);
16507 emit_insn (gen_strset (destptr, dest, value));
16508 emit_insn (gen_strset (destptr, dest, value));
16510 emit_label (label);
16511 LABEL_NUSES (label) = 1;
16515 rtx label = ix86_expand_aligntest (count, 4, true);
16516 dest = change_address (destmem, SImode, destptr);
16517 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
16518 emit_label (label);
16519 LABEL_NUSES (label) = 1;
16523 rtx label = ix86_expand_aligntest (count, 2, true);
16524 dest = change_address (destmem, HImode, destptr);
16525 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
16526 emit_label (label);
16527 LABEL_NUSES (label) = 1;
16531 rtx label = ix86_expand_aligntest (count, 1, true);
16532 dest = change_address (destmem, QImode, destptr);
16533 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
16534 emit_label (label);
16535 LABEL_NUSES (label) = 1;
16539 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
16540 DESIRED_ALIGNMENT. */
16542 expand_movmem_prologue (rtx destmem, rtx srcmem,
16543 rtx destptr, rtx srcptr, rtx count,
16544 int align, int desired_alignment)
16546 if (align <= 1 && desired_alignment > 1)
16548 rtx label = ix86_expand_aligntest (destptr, 1, false);
16549 srcmem = change_address (srcmem, QImode, srcptr);
16550 destmem = change_address (destmem, QImode, destptr);
16551 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
16552 ix86_adjust_counter (count, 1);
16553 emit_label (label);
16554 LABEL_NUSES (label) = 1;
16556 if (align <= 2 && desired_alignment > 2)
16558 rtx label = ix86_expand_aligntest (destptr, 2, false);
16559 srcmem = change_address (srcmem, HImode, srcptr);
16560 destmem = change_address (destmem, HImode, destptr);
16561 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
16562 ix86_adjust_counter (count, 2);
16563 emit_label (label);
16564 LABEL_NUSES (label) = 1;
16566 if (align <= 4 && desired_alignment > 4)
16568 rtx label = ix86_expand_aligntest (destptr, 4, false);
16569 srcmem = change_address (srcmem, SImode, srcptr);
16570 destmem = change_address (destmem, SImode, destptr);
16571 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
16572 ix86_adjust_counter (count, 4);
16573 emit_label (label);
16574 LABEL_NUSES (label) = 1;
16576 gcc_assert (desired_alignment <= 8);
16579 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
16580 DESIRED_ALIGNMENT. */
16582 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
16583 int align, int desired_alignment)
16585 if (align <= 1 && desired_alignment > 1)
16587 rtx label = ix86_expand_aligntest (destptr, 1, false);
16588 destmem = change_address (destmem, QImode, destptr);
16589 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
16590 ix86_adjust_counter (count, 1);
16591 emit_label (label);
16592 LABEL_NUSES (label) = 1;
16594 if (align <= 2 && desired_alignment > 2)
16596 rtx label = ix86_expand_aligntest (destptr, 2, false);
16597 destmem = change_address (destmem, HImode, destptr);
16598 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
16599 ix86_adjust_counter (count, 2);
16600 emit_label (label);
16601 LABEL_NUSES (label) = 1;
16603 if (align <= 4 && desired_alignment > 4)
16605 rtx label = ix86_expand_aligntest (destptr, 4, false);
16606 destmem = change_address (destmem, SImode, destptr);
16607 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
16608 ix86_adjust_counter (count, 4);
16609 emit_label (label);
16610 LABEL_NUSES (label) = 1;
16612 gcc_assert (desired_alignment <= 8);
16615 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
16616 static enum stringop_alg
16617 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
16618 int *dynamic_check)
16620 const struct stringop_algs * algs;
16621 /* Algorithms using the rep prefix want at least edi and ecx;
16622 additionally, memset wants eax and memcpy wants esi. Don't
16623 consider such algorithms if the user has appropriated those
16624 registers for their own purposes. */
16625 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
16627 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
16629 #define ALG_USABLE_P(alg) (rep_prefix_usable \
16630 || (alg != rep_prefix_1_byte \
16631 && alg != rep_prefix_4_byte \
16632 && alg != rep_prefix_8_byte))
16633 const struct processor_costs *cost;
16635 cost = optimize_insn_for_size_p () ? &size_cost : ix86_cost;
16637 *dynamic_check = -1;
16639 algs = &cost->memset[TARGET_64BIT != 0];
16641 algs = &cost->memcpy[TARGET_64BIT != 0];
16642 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
16643 return stringop_alg;
16644 /* rep; movq or rep; movl is the smallest variant. */
16645 else if (optimize_insn_for_size_p ())
16647 if (!count || (count & 3))
16648 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
16650 return rep_prefix_usable ? rep_prefix_4_byte : loop;
16652 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
16654 else if (expected_size != -1 && expected_size < 4)
16655 return loop_1_byte;
16656 else if (expected_size != -1)
16659 enum stringop_alg alg = libcall;
16660 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
16662 /* We get here if the algorithms that were not libcall-based
16663 were rep-prefix based and we are unable to use rep prefixes
16664 based on global register usage. Break out of the loop and
16665 use the heuristic below. */
16666 if (algs->size[i].max == 0)
16668 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
16670 enum stringop_alg candidate = algs->size[i].alg;
16672 if (candidate != libcall && ALG_USABLE_P (candidate))
16674 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
16675 last non-libcall inline algorithm. */
16676 if (TARGET_INLINE_ALL_STRINGOPS)
16678 /* When the current size is best to be copied by a libcall,
16679 but we are still forced to inline, run the heuristic below
16680 that will pick code for medium sized blocks. */
16681 if (alg != libcall)
16685 else if (ALG_USABLE_P (candidate))
16689 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
16691 /* When asked to inline the call anyway, try to pick meaningful choice.
16692 We look for maximal size of block that is faster to copy by hand and
16693 take blocks of at most of that size guessing that average size will
16694 be roughly half of the block.
16696 If this turns out to be bad, we might simply specify the preferred
16697 choice in ix86_costs. */
16698 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
16699 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
16702 enum stringop_alg alg;
16704 bool any_alg_usable_p = true;
16706 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
16708 enum stringop_alg candidate = algs->size[i].alg;
16709 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
16711 if (candidate != libcall && candidate
16712 && ALG_USABLE_P (candidate))
16713 max = algs->size[i].max;
16715 /* If there aren't any usable algorithms, then recursing on
16716 smaller sizes isn't going to find anything. Just return the
16717 simple byte-at-a-time copy loop. */
16718 if (!any_alg_usable_p)
16720 /* Pick something reasonable. */
16721 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
16722 *dynamic_check = 128;
16723 return loop_1_byte;
16727 alg = decide_alg (count, max / 2, memset, dynamic_check);
16728 gcc_assert (*dynamic_check == -1);
16729 gcc_assert (alg != libcall);
16730 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
16731 *dynamic_check = max;
16734 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
16735 #undef ALG_USABLE_P
16738 /* Decide on alignment. We know that the operand is already aligned to ALIGN
16739 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
16741 decide_alignment (int align,
16742 enum stringop_alg alg,
16745 int desired_align = 0;
16749 gcc_unreachable ();
16751 case unrolled_loop:
16752 desired_align = GET_MODE_SIZE (Pmode);
16754 case rep_prefix_8_byte:
16757 case rep_prefix_4_byte:
16758 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
16759 copying whole cacheline at once. */
16760 if (TARGET_PENTIUMPRO)
16765 case rep_prefix_1_byte:
16766 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
16767 copying whole cacheline at once. */
16768 if (TARGET_PENTIUMPRO)
16782 if (desired_align < align)
16783 desired_align = align;
16784 if (expected_size != -1 && expected_size < 4)
16785 desired_align = align;
16786 return desired_align;
16789 /* Return the smallest power of 2 greater than VAL. */
16791 smallest_pow2_greater_than (int val)
16799 /* Expand string move (memcpy) operation. Use i386 string operations when
16800 profitable. expand_setmem contains similar code. The code depends upon
16801 architecture, block size and alignment, but always has the same
16804 1) Prologue guard: Conditional that jumps up to epilogues for small
16805 blocks that can be handled by epilogue alone. This is faster but
16806 also needed for correctness, since prologue assume the block is larger
16807 than the desired alignment.
16809 Optional dynamic check for size and libcall for large
16810 blocks is emitted here too, with -minline-stringops-dynamically.
16812 2) Prologue: copy first few bytes in order to get destination aligned
16813 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
16814 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
16815 We emit either a jump tree on power of two sized blocks, or a byte loop.
16817 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
16818 with specified algorithm.
16820 4) Epilogue: code copying tail of the block that is too small to be
16821 handled by main body (or up to size guarded by prologue guard). */
16824 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
16825 rtx expected_align_exp, rtx expected_size_exp)
16831 rtx jump_around_label = NULL;
16832 HOST_WIDE_INT align = 1;
16833 unsigned HOST_WIDE_INT count = 0;
16834 HOST_WIDE_INT expected_size = -1;
16835 int size_needed = 0, epilogue_size_needed;
16836 int desired_align = 0;
16837 enum stringop_alg alg;
16840 if (CONST_INT_P (align_exp))
16841 align = INTVAL (align_exp);
16842 /* i386 can do misaligned access on reasonably increased cost. */
16843 if (CONST_INT_P (expected_align_exp)
16844 && INTVAL (expected_align_exp) > align)
16845 align = INTVAL (expected_align_exp);
16846 if (CONST_INT_P (count_exp))
16847 count = expected_size = INTVAL (count_exp);
16848 if (CONST_INT_P (expected_size_exp) && count == 0)
16849 expected_size = INTVAL (expected_size_exp);
16851 /* Make sure we don't need to care about overflow later on. */
16852 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
16855 /* Step 0: Decide on preferred algorithm, desired alignment and
16856 size of chunks to be copied by main loop. */
16858 alg = decide_alg (count, expected_size, false, &dynamic_check);
16859 desired_align = decide_alignment (align, alg, expected_size);
16861 if (!TARGET_ALIGN_STRINGOPS)
16862 align = desired_align;
16864 if (alg == libcall)
16866 gcc_assert (alg != no_stringop);
16868 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
16869 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
16870 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
16875 gcc_unreachable ();
16877 size_needed = GET_MODE_SIZE (Pmode);
16879 case unrolled_loop:
16880 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
16882 case rep_prefix_8_byte:
16885 case rep_prefix_4_byte:
16888 case rep_prefix_1_byte:
16894 epilogue_size_needed = size_needed;
16896 /* Step 1: Prologue guard. */
16898 /* Alignment code needs count to be in register. */
16899 if (CONST_INT_P (count_exp) && desired_align > align)
16900 count_exp = force_reg (counter_mode (count_exp), count_exp);
16901 gcc_assert (desired_align >= 1 && align >= 1);
16903 /* Ensure that alignment prologue won't copy past end of block. */
16904 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
16906 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
16907 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
16908 Make sure it is power of 2. */
16909 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
16911 if (CONST_INT_P (count_exp))
16913 if (UINTVAL (count_exp) < (unsigned HOST_WIDE_INT)epilogue_size_needed)
16918 label = gen_label_rtx ();
16919 emit_cmp_and_jump_insns (count_exp,
16920 GEN_INT (epilogue_size_needed),
16921 LTU, 0, counter_mode (count_exp), 1, label);
16922 if (expected_size == -1 || expected_size < epilogue_size_needed)
16923 predict_jump (REG_BR_PROB_BASE * 60 / 100);
16925 predict_jump (REG_BR_PROB_BASE * 20 / 100);
16929 /* Emit code to decide on runtime whether library call or inline should be
16931 if (dynamic_check != -1)
16933 if (CONST_INT_P (count_exp))
16935 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
16937 emit_block_move_via_libcall (dst, src, count_exp, false);
16938 count_exp = const0_rtx;
16944 rtx hot_label = gen_label_rtx ();
16945 jump_around_label = gen_label_rtx ();
16946 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
16947 LEU, 0, GET_MODE (count_exp), 1, hot_label);
16948 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16949 emit_block_move_via_libcall (dst, src, count_exp, false);
16950 emit_jump (jump_around_label);
16951 emit_label (hot_label);
16955 /* Step 2: Alignment prologue. */
16957 if (desired_align > align)
16959 /* Except for the first move in epilogue, we no longer know
16960 constant offset in aliasing info. It don't seems to worth
16961 the pain to maintain it for the first move, so throw away
16963 src = change_address (src, BLKmode, srcreg);
16964 dst = change_address (dst, BLKmode, destreg);
16965 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
16968 if (label && size_needed == 1)
16970 emit_label (label);
16971 LABEL_NUSES (label) = 1;
16975 /* Step 3: Main loop. */
16981 gcc_unreachable ();
16983 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
16984 count_exp, QImode, 1, expected_size);
16987 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
16988 count_exp, Pmode, 1, expected_size);
16990 case unrolled_loop:
16991 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
16992 registers for 4 temporaries anyway. */
16993 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
16994 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
16997 case rep_prefix_8_byte:
16998 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17001 case rep_prefix_4_byte:
17002 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17005 case rep_prefix_1_byte:
17006 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17010 /* Adjust properly the offset of src and dest memory for aliasing. */
17011 if (CONST_INT_P (count_exp))
17013 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
17014 (count / size_needed) * size_needed);
17015 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
17016 (count / size_needed) * size_needed);
17020 src = change_address (src, BLKmode, srcreg);
17021 dst = change_address (dst, BLKmode, destreg);
17024 /* Step 4: Epilogue to copy the remaining bytes. */
17028 /* When the main loop is done, COUNT_EXP might hold original count,
17029 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17030 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17031 bytes. Compensate if needed. */
17033 if (size_needed < epilogue_size_needed)
17036 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
17037 GEN_INT (size_needed - 1), count_exp, 1,
17039 if (tmp != count_exp)
17040 emit_move_insn (count_exp, tmp);
17042 emit_label (label);
17043 LABEL_NUSES (label) = 1;
17046 if (count_exp != const0_rtx && epilogue_size_needed > 1)
17047 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
17048 epilogue_size_needed);
17049 if (jump_around_label)
17050 emit_label (jump_around_label);
17054 /* Helper function for memcpy. For QImode value 0xXY produce
17055 0xXYXYXYXY of wide specified by MODE. This is essentially
17056 a * 0x10101010, but we can do slightly better than
17057 synth_mult by unwinding the sequence by hand on CPUs with
17060 promote_duplicated_reg (enum machine_mode mode, rtx val)
17062 enum machine_mode valmode = GET_MODE (val);
17064 int nops = mode == DImode ? 3 : 2;
17066 gcc_assert (mode == SImode || mode == DImode);
17067 if (val == const0_rtx)
17068 return copy_to_mode_reg (mode, const0_rtx);
17069 if (CONST_INT_P (val))
17071 HOST_WIDE_INT v = INTVAL (val) & 255;
17075 if (mode == DImode)
17076 v |= (v << 16) << 16;
17077 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
17080 if (valmode == VOIDmode)
17082 if (valmode != QImode)
17083 val = gen_lowpart (QImode, val);
17084 if (mode == QImode)
17086 if (!TARGET_PARTIAL_REG_STALL)
17088 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
17089 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
17090 <= (ix86_cost->shift_const + ix86_cost->add) * nops
17091 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
17093 rtx reg = convert_modes (mode, QImode, val, true);
17094 tmp = promote_duplicated_reg (mode, const1_rtx);
17095 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
17100 rtx reg = convert_modes (mode, QImode, val, true);
17102 if (!TARGET_PARTIAL_REG_STALL)
17103 if (mode == SImode)
17104 emit_insn (gen_movsi_insv_1 (reg, reg));
17106 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
17109 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
17110 NULL, 1, OPTAB_DIRECT);
17112 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
17114 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
17115 NULL, 1, OPTAB_DIRECT);
17116 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
17117 if (mode == SImode)
17119 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
17120 NULL, 1, OPTAB_DIRECT);
17121 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
17126 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
17127 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
17128 alignment from ALIGN to DESIRED_ALIGN. */
17130 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
17135 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
17136 promoted_val = promote_duplicated_reg (DImode, val);
17137 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
17138 promoted_val = promote_duplicated_reg (SImode, val);
17139 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
17140 promoted_val = promote_duplicated_reg (HImode, val);
17142 promoted_val = val;
17144 return promoted_val;
17147 /* Expand string clear operation (bzero). Use i386 string operations when
17148 profitable. See expand_movmem comment for explanation of individual
17149 steps performed. */
17151 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
17152 rtx expected_align_exp, rtx expected_size_exp)
17157 rtx jump_around_label = NULL;
17158 HOST_WIDE_INT align = 1;
17159 unsigned HOST_WIDE_INT count = 0;
17160 HOST_WIDE_INT expected_size = -1;
17161 int size_needed = 0, epilogue_size_needed;
17162 int desired_align = 0;
17163 enum stringop_alg alg;
17164 rtx promoted_val = NULL;
17165 bool force_loopy_epilogue = false;
17168 if (CONST_INT_P (align_exp))
17169 align = INTVAL (align_exp);
17170 /* i386 can do misaligned access on reasonably increased cost. */
17171 if (CONST_INT_P (expected_align_exp)
17172 && INTVAL (expected_align_exp) > align)
17173 align = INTVAL (expected_align_exp);
17174 if (CONST_INT_P (count_exp))
17175 count = expected_size = INTVAL (count_exp);
17176 if (CONST_INT_P (expected_size_exp) && count == 0)
17177 expected_size = INTVAL (expected_size_exp);
17179 /* Make sure we don't need to care about overflow later on. */
17180 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17183 /* Step 0: Decide on preferred algorithm, desired alignment and
17184 size of chunks to be copied by main loop. */
17186 alg = decide_alg (count, expected_size, true, &dynamic_check);
17187 desired_align = decide_alignment (align, alg, expected_size);
17189 if (!TARGET_ALIGN_STRINGOPS)
17190 align = desired_align;
17192 if (alg == libcall)
17194 gcc_assert (alg != no_stringop);
17196 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
17197 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17202 gcc_unreachable ();
17204 size_needed = GET_MODE_SIZE (Pmode);
17206 case unrolled_loop:
17207 size_needed = GET_MODE_SIZE (Pmode) * 4;
17209 case rep_prefix_8_byte:
17212 case rep_prefix_4_byte:
17215 case rep_prefix_1_byte:
17220 epilogue_size_needed = size_needed;
17222 /* Step 1: Prologue guard. */
17224 /* Alignment code needs count to be in register. */
17225 if (CONST_INT_P (count_exp) && desired_align > align)
17227 enum machine_mode mode = SImode;
17228 if (TARGET_64BIT && (count & ~0xffffffff))
17230 count_exp = force_reg (mode, count_exp);
17232 /* Do the cheap promotion to allow better CSE across the
17233 main loop and epilogue (ie one load of the big constant in the
17234 front of all code. */
17235 if (CONST_INT_P (val_exp))
17236 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
17237 desired_align, align);
17238 /* Ensure that alignment prologue won't copy past end of block. */
17239 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17241 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17242 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17243 Make sure it is power of 2. */
17244 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17246 /* To improve performance of small blocks, we jump around the VAL
17247 promoting mode. This mean that if the promoted VAL is not constant,
17248 we might not use it in the epilogue and have to use byte
17250 if (epilogue_size_needed > 2 && !promoted_val)
17251 force_loopy_epilogue = true;
17252 label = gen_label_rtx ();
17253 emit_cmp_and_jump_insns (count_exp,
17254 GEN_INT (epilogue_size_needed),
17255 LTU, 0, counter_mode (count_exp), 1, label);
17256 if (GET_CODE (count_exp) == CONST_INT)
17258 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
17259 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17261 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17263 if (dynamic_check != -1)
17265 rtx hot_label = gen_label_rtx ();
17266 jump_around_label = gen_label_rtx ();
17267 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17268 LEU, 0, counter_mode (count_exp), 1, hot_label);
17269 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17270 set_storage_via_libcall (dst, count_exp, val_exp, false);
17271 emit_jump (jump_around_label);
17272 emit_label (hot_label);
17275 /* Step 2: Alignment prologue. */
17277 /* Do the expensive promotion once we branched off the small blocks. */
17279 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
17280 desired_align, align);
17281 gcc_assert (desired_align >= 1 && align >= 1);
17283 if (desired_align > align)
17285 /* Except for the first move in epilogue, we no longer know
17286 constant offset in aliasing info. It don't seems to worth
17287 the pain to maintain it for the first move, so throw away
17289 dst = change_address (dst, BLKmode, destreg);
17290 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
17293 if (label && size_needed == 1)
17295 emit_label (label);
17296 LABEL_NUSES (label) = 1;
17300 /* Step 3: Main loop. */
17306 gcc_unreachable ();
17308 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
17309 count_exp, QImode, 1, expected_size);
17312 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
17313 count_exp, Pmode, 1, expected_size);
17315 case unrolled_loop:
17316 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
17317 count_exp, Pmode, 4, expected_size);
17319 case rep_prefix_8_byte:
17320 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
17323 case rep_prefix_4_byte:
17324 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
17327 case rep_prefix_1_byte:
17328 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
17332 /* Adjust properly the offset of src and dest memory for aliasing. */
17333 if (CONST_INT_P (count_exp))
17334 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
17335 (count / size_needed) * size_needed);
17337 dst = change_address (dst, BLKmode, destreg);
17339 /* Step 4: Epilogue to copy the remaining bytes. */
17343 /* When the main loop is done, COUNT_EXP might hold original count,
17344 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17345 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17346 bytes. Compensate if needed. */
17348 if (size_needed < desired_align - align)
17351 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
17352 GEN_INT (size_needed - 1), count_exp, 1,
17354 size_needed = desired_align - align + 1;
17355 if (tmp != count_exp)
17356 emit_move_insn (count_exp, tmp);
17358 emit_label (label);
17359 LABEL_NUSES (label) = 1;
17361 if (count_exp != const0_rtx && epilogue_size_needed > 1)
17363 if (force_loopy_epilogue)
17364 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
17367 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
17370 if (jump_around_label)
17371 emit_label (jump_around_label);
17375 /* Expand the appropriate insns for doing strlen if not just doing
17378 out = result, initialized with the start address
17379 align_rtx = alignment of the address.
17380 scratch = scratch register, initialized with the startaddress when
17381 not aligned, otherwise undefined
17383 This is just the body. It needs the initializations mentioned above and
17384 some address computing at the end. These things are done in i386.md. */
17387 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
17391 rtx align_2_label = NULL_RTX;
17392 rtx align_3_label = NULL_RTX;
17393 rtx align_4_label = gen_label_rtx ();
17394 rtx end_0_label = gen_label_rtx ();
17396 rtx tmpreg = gen_reg_rtx (SImode);
17397 rtx scratch = gen_reg_rtx (SImode);
17401 if (CONST_INT_P (align_rtx))
17402 align = INTVAL (align_rtx);
17404 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
17406 /* Is there a known alignment and is it less than 4? */
17409 rtx scratch1 = gen_reg_rtx (Pmode);
17410 emit_move_insn (scratch1, out);
17411 /* Is there a known alignment and is it not 2? */
17414 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
17415 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
17417 /* Leave just the 3 lower bits. */
17418 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
17419 NULL_RTX, 0, OPTAB_WIDEN);
17421 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
17422 Pmode, 1, align_4_label);
17423 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
17424 Pmode, 1, align_2_label);
17425 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
17426 Pmode, 1, align_3_label);
17430 /* Since the alignment is 2, we have to check 2 or 0 bytes;
17431 check if is aligned to 4 - byte. */
17433 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
17434 NULL_RTX, 0, OPTAB_WIDEN);
17436 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
17437 Pmode, 1, align_4_label);
17440 mem = change_address (src, QImode, out);
17442 /* Now compare the bytes. */
17444 /* Compare the first n unaligned byte on a byte per byte basis. */
17445 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
17446 QImode, 1, end_0_label);
17448 /* Increment the address. */
17449 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
17451 /* Not needed with an alignment of 2 */
17454 emit_label (align_2_label);
17456 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
17459 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
17461 emit_label (align_3_label);
17464 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
17467 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
17470 /* Generate loop to check 4 bytes at a time. It is not a good idea to
17471 align this loop. It gives only huge programs, but does not help to
17473 emit_label (align_4_label);
17475 mem = change_address (src, SImode, out);
17476 emit_move_insn (scratch, mem);
17477 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
17479 /* This formula yields a nonzero result iff one of the bytes is zero.
17480 This saves three branches inside loop and many cycles. */
17482 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
17483 emit_insn (gen_one_cmplsi2 (scratch, scratch));
17484 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
17485 emit_insn (gen_andsi3 (tmpreg, tmpreg,
17486 gen_int_mode (0x80808080, SImode)));
17487 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
17492 rtx reg = gen_reg_rtx (SImode);
17493 rtx reg2 = gen_reg_rtx (Pmode);
17494 emit_move_insn (reg, tmpreg);
17495 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
17497 /* If zero is not in the first two bytes, move two bytes forward. */
17498 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
17499 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
17500 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
17501 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
17502 gen_rtx_IF_THEN_ELSE (SImode, tmp,
17505 /* Emit lea manually to avoid clobbering of flags. */
17506 emit_insn (gen_rtx_SET (SImode, reg2,
17507 gen_rtx_PLUS (Pmode, out, const2_rtx)));
17509 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
17510 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
17511 emit_insn (gen_rtx_SET (VOIDmode, out,
17512 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
17519 rtx end_2_label = gen_label_rtx ();
17520 /* Is zero in the first two bytes? */
17522 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
17523 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
17524 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
17525 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
17526 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
17528 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
17529 JUMP_LABEL (tmp) = end_2_label;
17531 /* Not in the first two. Move two bytes forward. */
17532 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
17533 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
17535 emit_label (end_2_label);
17539 /* Avoid branch in fixing the byte. */
17540 tmpreg = gen_lowpart (QImode, tmpreg);
17541 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
17542 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
17543 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
17545 emit_label (end_0_label);
17548 /* Expand strlen. */
17551 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
17553 rtx addr, scratch1, scratch2, scratch3, scratch4;
17555 /* The generic case of strlen expander is long. Avoid it's
17556 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
17558 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
17559 && !TARGET_INLINE_ALL_STRINGOPS
17560 && !optimize_insn_for_size_p ()
17561 && (!CONST_INT_P (align) || INTVAL (align) < 4))
17564 addr = force_reg (Pmode, XEXP (src, 0));
17565 scratch1 = gen_reg_rtx (Pmode);
17567 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
17568 && !optimize_insn_for_size_p ())
17570 /* Well it seems that some optimizer does not combine a call like
17571 foo(strlen(bar), strlen(bar));
17572 when the move and the subtraction is done here. It does calculate
17573 the length just once when these instructions are done inside of
17574 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
17575 often used and I use one fewer register for the lifetime of
17576 output_strlen_unroll() this is better. */
17578 emit_move_insn (out, addr);
17580 ix86_expand_strlensi_unroll_1 (out, src, align);
17582 /* strlensi_unroll_1 returns the address of the zero at the end of
17583 the string, like memchr(), so compute the length by subtracting
17584 the start address. */
17585 emit_insn ((*ix86_gen_sub3) (out, out, addr));
17591 /* Can't use this if the user has appropriated eax, ecx, or edi. */
17592 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
17595 scratch2 = gen_reg_rtx (Pmode);
17596 scratch3 = gen_reg_rtx (Pmode);
17597 scratch4 = force_reg (Pmode, constm1_rtx);
17599 emit_move_insn (scratch3, addr);
17600 eoschar = force_reg (QImode, eoschar);
17602 src = replace_equiv_address_nv (src, scratch3);
17604 /* If .md starts supporting :P, this can be done in .md. */
17605 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
17606 scratch4), UNSPEC_SCAS);
17607 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
17608 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
17609 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
17614 /* For given symbol (function) construct code to compute address of it's PLT
17615 entry in large x86-64 PIC model. */
17617 construct_plt_address (rtx symbol)
17619 rtx tmp = gen_reg_rtx (Pmode);
17620 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
17622 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
17623 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
17625 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
17626 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
17631 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
17632 rtx callarg2 ATTRIBUTE_UNUSED,
17633 rtx pop, int sibcall)
17635 rtx use = NULL, call;
17637 if (pop == const0_rtx)
17639 gcc_assert (!TARGET_64BIT || !pop);
17641 if (TARGET_MACHO && !TARGET_64BIT)
17644 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
17645 fnaddr = machopic_indirect_call_target (fnaddr);
17650 /* Static functions and indirect calls don't need the pic register. */
17651 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
17652 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
17653 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
17654 use_reg (&use, pic_offset_table_rtx);
17657 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
17659 rtx al = gen_rtx_REG (QImode, AX_REG);
17660 emit_move_insn (al, callarg2);
17661 use_reg (&use, al);
17664 if (ix86_cmodel == CM_LARGE_PIC
17665 && GET_CODE (fnaddr) == MEM
17666 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
17667 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
17668 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
17669 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
17671 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
17672 fnaddr = gen_rtx_MEM (QImode, fnaddr);
17674 if (sibcall && TARGET_64BIT
17675 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
17678 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
17679 fnaddr = gen_rtx_REG (Pmode, R11_REG);
17680 emit_move_insn (fnaddr, addr);
17681 fnaddr = gen_rtx_MEM (QImode, fnaddr);
17684 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
17686 call = gen_rtx_SET (VOIDmode, retval, call);
17689 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
17690 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
17691 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
17694 call = emit_call_insn (call);
17696 CALL_INSN_FUNCTION_USAGE (call) = use;
17700 /* Clear stack slot assignments remembered from previous functions.
17701 This is called from INIT_EXPANDERS once before RTL is emitted for each
17704 static struct machine_function *
17705 ix86_init_machine_status (void)
17707 struct machine_function *f;
17709 f = GGC_CNEW (struct machine_function);
17710 f->use_fast_prologue_epilogue_nregs = -1;
17711 f->tls_descriptor_call_expanded_p = 0;
17712 f->call_abi = DEFAULT_ABI;
17717 /* Return a MEM corresponding to a stack slot with mode MODE.
17718 Allocate a new slot if necessary.
17720 The RTL for a function can have several slots available: N is
17721 which slot to use. */
17724 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
17726 struct stack_local_entry *s;
17728 gcc_assert (n < MAX_386_STACK_LOCALS);
17730 /* Virtual slot is valid only before vregs are instantiated. */
17731 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
17733 for (s = ix86_stack_locals; s; s = s->next)
17734 if (s->mode == mode && s->n == n)
17735 return copy_rtx (s->rtl);
17737 s = (struct stack_local_entry *)
17738 ggc_alloc (sizeof (struct stack_local_entry));
17741 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
17743 s->next = ix86_stack_locals;
17744 ix86_stack_locals = s;
17748 /* Construct the SYMBOL_REF for the tls_get_addr function. */
17750 static GTY(()) rtx ix86_tls_symbol;
17752 ix86_tls_get_addr (void)
17755 if (!ix86_tls_symbol)
17757 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
17758 (TARGET_ANY_GNU_TLS
17760 ? "___tls_get_addr"
17761 : "__tls_get_addr");
17764 return ix86_tls_symbol;
17767 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
17769 static GTY(()) rtx ix86_tls_module_base_symbol;
17771 ix86_tls_module_base (void)
17774 if (!ix86_tls_module_base_symbol)
17776 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
17777 "_TLS_MODULE_BASE_");
17778 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
17779 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
17782 return ix86_tls_module_base_symbol;
17785 /* Calculate the length of the memory address in the instruction
17786 encoding. Does not include the one-byte modrm, opcode, or prefix. */
17789 memory_address_length (rtx addr)
17791 struct ix86_address parts;
17792 rtx base, index, disp;
17796 if (GET_CODE (addr) == PRE_DEC
17797 || GET_CODE (addr) == POST_INC
17798 || GET_CODE (addr) == PRE_MODIFY
17799 || GET_CODE (addr) == POST_MODIFY)
17802 ok = ix86_decompose_address (addr, &parts);
17805 if (parts.base && GET_CODE (parts.base) == SUBREG)
17806 parts.base = SUBREG_REG (parts.base);
17807 if (parts.index && GET_CODE (parts.index) == SUBREG)
17808 parts.index = SUBREG_REG (parts.index);
17811 index = parts.index;
17816 - esp as the base always wants an index,
17817 - ebp as the base always wants a displacement. */
17819 /* Register Indirect. */
17820 if (base && !index && !disp)
17822 /* esp (for its index) and ebp (for its displacement) need
17823 the two-byte modrm form. */
17824 if (addr == stack_pointer_rtx
17825 || addr == arg_pointer_rtx
17826 || addr == frame_pointer_rtx
17827 || addr == hard_frame_pointer_rtx)
17831 /* Direct Addressing. */
17832 else if (disp && !base && !index)
17837 /* Find the length of the displacement constant. */
17840 if (base && satisfies_constraint_K (disp))
17845 /* ebp always wants a displacement. */
17846 else if (base == hard_frame_pointer_rtx)
17849 /* An index requires the two-byte modrm form.... */
17851 /* ...like esp, which always wants an index. */
17852 || base == stack_pointer_rtx
17853 || base == arg_pointer_rtx
17854 || base == frame_pointer_rtx)
17861 /* Compute default value for "length_immediate" attribute. When SHORTFORM
17862 is set, expect that insn have 8bit immediate alternative. */
17864 ix86_attr_length_immediate_default (rtx insn, int shortform)
17868 extract_insn_cached (insn);
17869 for (i = recog_data.n_operands - 1; i >= 0; --i)
17870 if (CONSTANT_P (recog_data.operand[i]))
17873 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
17877 switch (get_attr_mode (insn))
17888 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
17893 fatal_insn ("unknown insn mode", insn);
17899 /* Compute default value for "length_address" attribute. */
17901 ix86_attr_length_address_default (rtx insn)
17905 if (get_attr_type (insn) == TYPE_LEA)
17907 rtx set = PATTERN (insn);
17909 if (GET_CODE (set) == PARALLEL)
17910 set = XVECEXP (set, 0, 0);
17912 gcc_assert (GET_CODE (set) == SET);
17914 return memory_address_length (SET_SRC (set));
17917 extract_insn_cached (insn);
17918 for (i = recog_data.n_operands - 1; i >= 0; --i)
17919 if (MEM_P (recog_data.operand[i]))
17921 return memory_address_length (XEXP (recog_data.operand[i], 0));
17927 /* Return the maximum number of instructions a cpu can issue. */
17930 ix86_issue_rate (void)
17934 case PROCESSOR_PENTIUM:
17938 case PROCESSOR_PENTIUMPRO:
17939 case PROCESSOR_PENTIUM4:
17940 case PROCESSOR_ATHLON:
17942 case PROCESSOR_AMDFAM10:
17943 case PROCESSOR_NOCONA:
17944 case PROCESSOR_GENERIC32:
17945 case PROCESSOR_GENERIC64:
17948 case PROCESSOR_CORE2:
17956 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
17957 by DEP_INSN and nothing set by DEP_INSN. */
17960 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
17964 /* Simplify the test for uninteresting insns. */
17965 if (insn_type != TYPE_SETCC
17966 && insn_type != TYPE_ICMOV
17967 && insn_type != TYPE_FCMOV
17968 && insn_type != TYPE_IBR)
17971 if ((set = single_set (dep_insn)) != 0)
17973 set = SET_DEST (set);
17976 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
17977 && XVECLEN (PATTERN (dep_insn), 0) == 2
17978 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
17979 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
17981 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
17982 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
17987 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
17990 /* This test is true if the dependent insn reads the flags but
17991 not any other potentially set register. */
17992 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
17995 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
18001 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
18002 address with operands set by DEP_INSN. */
18005 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
18009 if (insn_type == TYPE_LEA
18012 addr = PATTERN (insn);
18014 if (GET_CODE (addr) == PARALLEL)
18015 addr = XVECEXP (addr, 0, 0);
18017 gcc_assert (GET_CODE (addr) == SET);
18019 addr = SET_SRC (addr);
18024 extract_insn_cached (insn);
18025 for (i = recog_data.n_operands - 1; i >= 0; --i)
18026 if (MEM_P (recog_data.operand[i]))
18028 addr = XEXP (recog_data.operand[i], 0);
18035 return modified_in_p (addr, dep_insn);
18039 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
18041 enum attr_type insn_type, dep_insn_type;
18042 enum attr_memory memory;
18044 int dep_insn_code_number;
18046 /* Anti and output dependencies have zero cost on all CPUs. */
18047 if (REG_NOTE_KIND (link) != 0)
18050 dep_insn_code_number = recog_memoized (dep_insn);
18052 /* If we can't recognize the insns, we can't really do anything. */
18053 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
18056 insn_type = get_attr_type (insn);
18057 dep_insn_type = get_attr_type (dep_insn);
18061 case PROCESSOR_PENTIUM:
18062 /* Address Generation Interlock adds a cycle of latency. */
18063 if (ix86_agi_dependent (insn, dep_insn, insn_type))
18066 /* ??? Compares pair with jump/setcc. */
18067 if (ix86_flags_dependent (insn, dep_insn, insn_type))
18070 /* Floating point stores require value to be ready one cycle earlier. */
18071 if (insn_type == TYPE_FMOV
18072 && get_attr_memory (insn) == MEMORY_STORE
18073 && !ix86_agi_dependent (insn, dep_insn, insn_type))
18077 case PROCESSOR_PENTIUMPRO:
18078 memory = get_attr_memory (insn);
18080 /* INT->FP conversion is expensive. */
18081 if (get_attr_fp_int_src (dep_insn))
18084 /* There is one cycle extra latency between an FP op and a store. */
18085 if (insn_type == TYPE_FMOV
18086 && (set = single_set (dep_insn)) != NULL_RTX
18087 && (set2 = single_set (insn)) != NULL_RTX
18088 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
18089 && MEM_P (SET_DEST (set2)))
18092 /* Show ability of reorder buffer to hide latency of load by executing
18093 in parallel with previous instruction in case
18094 previous instruction is not needed to compute the address. */
18095 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
18096 && !ix86_agi_dependent (insn, dep_insn, insn_type))
18098 /* Claim moves to take one cycle, as core can issue one load
18099 at time and the next load can start cycle later. */
18100 if (dep_insn_type == TYPE_IMOV
18101 || dep_insn_type == TYPE_FMOV)
18109 memory = get_attr_memory (insn);
18111 /* The esp dependency is resolved before the instruction is really
18113 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
18114 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
18117 /* INT->FP conversion is expensive. */
18118 if (get_attr_fp_int_src (dep_insn))
18121 /* Show ability of reorder buffer to hide latency of load by executing
18122 in parallel with previous instruction in case
18123 previous instruction is not needed to compute the address. */
18124 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
18125 && !ix86_agi_dependent (insn, dep_insn, insn_type))
18127 /* Claim moves to take one cycle, as core can issue one load
18128 at time and the next load can start cycle later. */
18129 if (dep_insn_type == TYPE_IMOV
18130 || dep_insn_type == TYPE_FMOV)
18139 case PROCESSOR_ATHLON:
18141 case PROCESSOR_AMDFAM10:
18142 case PROCESSOR_GENERIC32:
18143 case PROCESSOR_GENERIC64:
18144 memory = get_attr_memory (insn);
18146 /* Show ability of reorder buffer to hide latency of load by executing
18147 in parallel with previous instruction in case
18148 previous instruction is not needed to compute the address. */
18149 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
18150 && !ix86_agi_dependent (insn, dep_insn, insn_type))
18152 enum attr_unit unit = get_attr_unit (insn);
18155 /* Because of the difference between the length of integer and
18156 floating unit pipeline preparation stages, the memory operands
18157 for floating point are cheaper.
18159 ??? For Athlon it the difference is most probably 2. */
18160 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
18163 loadcost = TARGET_ATHLON ? 2 : 0;
18165 if (cost >= loadcost)
18178 /* How many alternative schedules to try. This should be as wide as the
18179 scheduling freedom in the DFA, but no wider. Making this value too
18180 large results extra work for the scheduler. */
18183 ia32_multipass_dfa_lookahead (void)
18187 case PROCESSOR_PENTIUM:
18190 case PROCESSOR_PENTIUMPRO:
18200 /* Compute the alignment given to a constant that is being placed in memory.
18201 EXP is the constant and ALIGN is the alignment that the object would
18203 The value of this function is used instead of that alignment to align
18207 ix86_constant_alignment (tree exp, int align)
18209 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
18210 || TREE_CODE (exp) == INTEGER_CST)
18212 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
18214 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
18217 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
18218 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
18219 return BITS_PER_WORD;
18224 /* Compute the alignment for a static variable.
18225 TYPE is the data type, and ALIGN is the alignment that
18226 the object would ordinarily have. The value of this function is used
18227 instead of that alignment to align the object. */
18230 ix86_data_alignment (tree type, int align)
18232 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
18234 if (AGGREGATE_TYPE_P (type)
18235 && TYPE_SIZE (type)
18236 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
18237 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
18238 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
18239 && align < max_align)
18242 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
18243 to 16byte boundary. */
18246 if (AGGREGATE_TYPE_P (type)
18247 && TYPE_SIZE (type)
18248 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
18249 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
18250 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
18254 if (TREE_CODE (type) == ARRAY_TYPE)
18256 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
18258 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
18261 else if (TREE_CODE (type) == COMPLEX_TYPE)
18264 if (TYPE_MODE (type) == DCmode && align < 64)
18266 if ((TYPE_MODE (type) == XCmode
18267 || TYPE_MODE (type) == TCmode) && align < 128)
18270 else if ((TREE_CODE (type) == RECORD_TYPE
18271 || TREE_CODE (type) == UNION_TYPE
18272 || TREE_CODE (type) == QUAL_UNION_TYPE)
18273 && TYPE_FIELDS (type))
18275 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
18277 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
18280 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
18281 || TREE_CODE (type) == INTEGER_TYPE)
18283 if (TYPE_MODE (type) == DFmode && align < 64)
18285 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
18292 /* Compute the alignment for a local variable or a stack slot. TYPE is
18293 the data type, MODE is the widest mode available and ALIGN is the
18294 alignment that the object would ordinarily have. The value of this
18295 macro is used instead of that alignment to align the object. */
18298 ix86_local_alignment (tree type, enum machine_mode mode,
18299 unsigned int align)
18301 /* If TYPE is NULL, we are allocating a stack slot for caller-save
18302 register in MODE. We will return the largest alignment of XF
18306 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
18307 align = GET_MODE_ALIGNMENT (DFmode);
18311 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
18312 to 16byte boundary. */
18315 if (AGGREGATE_TYPE_P (type)
18316 && TYPE_SIZE (type)
18317 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
18318 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
18319 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
18322 if (TREE_CODE (type) == ARRAY_TYPE)
18324 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
18326 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
18329 else if (TREE_CODE (type) == COMPLEX_TYPE)
18331 if (TYPE_MODE (type) == DCmode && align < 64)
18333 if ((TYPE_MODE (type) == XCmode
18334 || TYPE_MODE (type) == TCmode) && align < 128)
18337 else if ((TREE_CODE (type) == RECORD_TYPE
18338 || TREE_CODE (type) == UNION_TYPE
18339 || TREE_CODE (type) == QUAL_UNION_TYPE)
18340 && TYPE_FIELDS (type))
18342 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
18344 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
18347 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
18348 || TREE_CODE (type) == INTEGER_TYPE)
18351 if (TYPE_MODE (type) == DFmode && align < 64)
18353 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
18359 /* Emit RTL insns to initialize the variable parts of a trampoline.
18360 FNADDR is an RTX for the address of the function's pure code.
18361 CXT is an RTX for the static chain value for the function. */
18363 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
18367 /* Compute offset from the end of the jmp to the target function. */
18368 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
18369 plus_constant (tramp, 10),
18370 NULL_RTX, 1, OPTAB_DIRECT);
18371 emit_move_insn (gen_rtx_MEM (QImode, tramp),
18372 gen_int_mode (0xb9, QImode));
18373 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
18374 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
18375 gen_int_mode (0xe9, QImode));
18376 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
18381 /* Try to load address using shorter movl instead of movabs.
18382 We may want to support movq for kernel mode, but kernel does not use
18383 trampolines at the moment. */
18384 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
18386 fnaddr = copy_to_mode_reg (DImode, fnaddr);
18387 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
18388 gen_int_mode (0xbb41, HImode));
18389 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
18390 gen_lowpart (SImode, fnaddr));
18395 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
18396 gen_int_mode (0xbb49, HImode));
18397 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
18401 /* Load static chain using movabs to r10. */
18402 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
18403 gen_int_mode (0xba49, HImode));
18404 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
18407 /* Jump to the r11 */
18408 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
18409 gen_int_mode (0xff49, HImode));
18410 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
18411 gen_int_mode (0xe3, QImode));
18413 gcc_assert (offset <= TRAMPOLINE_SIZE);
18416 #ifdef ENABLE_EXECUTE_STACK
18417 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
18418 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
18422 /* Codes for all the SSE/MMX builtins. */
18425 IX86_BUILTIN_ADDPS,
18426 IX86_BUILTIN_ADDSS,
18427 IX86_BUILTIN_DIVPS,
18428 IX86_BUILTIN_DIVSS,
18429 IX86_BUILTIN_MULPS,
18430 IX86_BUILTIN_MULSS,
18431 IX86_BUILTIN_SUBPS,
18432 IX86_BUILTIN_SUBSS,
18434 IX86_BUILTIN_CMPEQPS,
18435 IX86_BUILTIN_CMPLTPS,
18436 IX86_BUILTIN_CMPLEPS,
18437 IX86_BUILTIN_CMPGTPS,
18438 IX86_BUILTIN_CMPGEPS,
18439 IX86_BUILTIN_CMPNEQPS,
18440 IX86_BUILTIN_CMPNLTPS,
18441 IX86_BUILTIN_CMPNLEPS,
18442 IX86_BUILTIN_CMPNGTPS,
18443 IX86_BUILTIN_CMPNGEPS,
18444 IX86_BUILTIN_CMPORDPS,
18445 IX86_BUILTIN_CMPUNORDPS,
18446 IX86_BUILTIN_CMPEQSS,
18447 IX86_BUILTIN_CMPLTSS,
18448 IX86_BUILTIN_CMPLESS,
18449 IX86_BUILTIN_CMPNEQSS,
18450 IX86_BUILTIN_CMPNLTSS,
18451 IX86_BUILTIN_CMPNLESS,
18452 IX86_BUILTIN_CMPNGTSS,
18453 IX86_BUILTIN_CMPNGESS,
18454 IX86_BUILTIN_CMPORDSS,
18455 IX86_BUILTIN_CMPUNORDSS,
18457 IX86_BUILTIN_COMIEQSS,
18458 IX86_BUILTIN_COMILTSS,
18459 IX86_BUILTIN_COMILESS,
18460 IX86_BUILTIN_COMIGTSS,
18461 IX86_BUILTIN_COMIGESS,
18462 IX86_BUILTIN_COMINEQSS,
18463 IX86_BUILTIN_UCOMIEQSS,
18464 IX86_BUILTIN_UCOMILTSS,
18465 IX86_BUILTIN_UCOMILESS,
18466 IX86_BUILTIN_UCOMIGTSS,
18467 IX86_BUILTIN_UCOMIGESS,
18468 IX86_BUILTIN_UCOMINEQSS,
18470 IX86_BUILTIN_CVTPI2PS,
18471 IX86_BUILTIN_CVTPS2PI,
18472 IX86_BUILTIN_CVTSI2SS,
18473 IX86_BUILTIN_CVTSI642SS,
18474 IX86_BUILTIN_CVTSS2SI,
18475 IX86_BUILTIN_CVTSS2SI64,
18476 IX86_BUILTIN_CVTTPS2PI,
18477 IX86_BUILTIN_CVTTSS2SI,
18478 IX86_BUILTIN_CVTTSS2SI64,
18480 IX86_BUILTIN_MAXPS,
18481 IX86_BUILTIN_MAXSS,
18482 IX86_BUILTIN_MINPS,
18483 IX86_BUILTIN_MINSS,
18485 IX86_BUILTIN_LOADUPS,
18486 IX86_BUILTIN_STOREUPS,
18487 IX86_BUILTIN_MOVSS,
18489 IX86_BUILTIN_MOVHLPS,
18490 IX86_BUILTIN_MOVLHPS,
18491 IX86_BUILTIN_LOADHPS,
18492 IX86_BUILTIN_LOADLPS,
18493 IX86_BUILTIN_STOREHPS,
18494 IX86_BUILTIN_STORELPS,
18496 IX86_BUILTIN_MASKMOVQ,
18497 IX86_BUILTIN_MOVMSKPS,
18498 IX86_BUILTIN_PMOVMSKB,
18500 IX86_BUILTIN_MOVNTPS,
18501 IX86_BUILTIN_MOVNTQ,
18503 IX86_BUILTIN_LOADDQU,
18504 IX86_BUILTIN_STOREDQU,
18506 IX86_BUILTIN_PACKSSWB,
18507 IX86_BUILTIN_PACKSSDW,
18508 IX86_BUILTIN_PACKUSWB,
18510 IX86_BUILTIN_PADDB,
18511 IX86_BUILTIN_PADDW,
18512 IX86_BUILTIN_PADDD,
18513 IX86_BUILTIN_PADDQ,
18514 IX86_BUILTIN_PADDSB,
18515 IX86_BUILTIN_PADDSW,
18516 IX86_BUILTIN_PADDUSB,
18517 IX86_BUILTIN_PADDUSW,
18518 IX86_BUILTIN_PSUBB,
18519 IX86_BUILTIN_PSUBW,
18520 IX86_BUILTIN_PSUBD,
18521 IX86_BUILTIN_PSUBQ,
18522 IX86_BUILTIN_PSUBSB,
18523 IX86_BUILTIN_PSUBSW,
18524 IX86_BUILTIN_PSUBUSB,
18525 IX86_BUILTIN_PSUBUSW,
18528 IX86_BUILTIN_PANDN,
18532 IX86_BUILTIN_PAVGB,
18533 IX86_BUILTIN_PAVGW,
18535 IX86_BUILTIN_PCMPEQB,
18536 IX86_BUILTIN_PCMPEQW,
18537 IX86_BUILTIN_PCMPEQD,
18538 IX86_BUILTIN_PCMPGTB,
18539 IX86_BUILTIN_PCMPGTW,
18540 IX86_BUILTIN_PCMPGTD,
18542 IX86_BUILTIN_PMADDWD,
18544 IX86_BUILTIN_PMAXSW,
18545 IX86_BUILTIN_PMAXUB,
18546 IX86_BUILTIN_PMINSW,
18547 IX86_BUILTIN_PMINUB,
18549 IX86_BUILTIN_PMULHUW,
18550 IX86_BUILTIN_PMULHW,
18551 IX86_BUILTIN_PMULLW,
18553 IX86_BUILTIN_PSADBW,
18554 IX86_BUILTIN_PSHUFW,
18556 IX86_BUILTIN_PSLLW,
18557 IX86_BUILTIN_PSLLD,
18558 IX86_BUILTIN_PSLLQ,
18559 IX86_BUILTIN_PSRAW,
18560 IX86_BUILTIN_PSRAD,
18561 IX86_BUILTIN_PSRLW,
18562 IX86_BUILTIN_PSRLD,
18563 IX86_BUILTIN_PSRLQ,
18564 IX86_BUILTIN_PSLLWI,
18565 IX86_BUILTIN_PSLLDI,
18566 IX86_BUILTIN_PSLLQI,
18567 IX86_BUILTIN_PSRAWI,
18568 IX86_BUILTIN_PSRADI,
18569 IX86_BUILTIN_PSRLWI,
18570 IX86_BUILTIN_PSRLDI,
18571 IX86_BUILTIN_PSRLQI,
18573 IX86_BUILTIN_PUNPCKHBW,
18574 IX86_BUILTIN_PUNPCKHWD,
18575 IX86_BUILTIN_PUNPCKHDQ,
18576 IX86_BUILTIN_PUNPCKLBW,
18577 IX86_BUILTIN_PUNPCKLWD,
18578 IX86_BUILTIN_PUNPCKLDQ,
18580 IX86_BUILTIN_SHUFPS,
18582 IX86_BUILTIN_RCPPS,
18583 IX86_BUILTIN_RCPSS,
18584 IX86_BUILTIN_RSQRTPS,
18585 IX86_BUILTIN_RSQRTPS_NR,
18586 IX86_BUILTIN_RSQRTSS,
18587 IX86_BUILTIN_RSQRTF,
18588 IX86_BUILTIN_SQRTPS,
18589 IX86_BUILTIN_SQRTPS_NR,
18590 IX86_BUILTIN_SQRTSS,
18592 IX86_BUILTIN_UNPCKHPS,
18593 IX86_BUILTIN_UNPCKLPS,
18595 IX86_BUILTIN_ANDPS,
18596 IX86_BUILTIN_ANDNPS,
18598 IX86_BUILTIN_XORPS,
18601 IX86_BUILTIN_LDMXCSR,
18602 IX86_BUILTIN_STMXCSR,
18603 IX86_BUILTIN_SFENCE,
18605 /* 3DNow! Original */
18606 IX86_BUILTIN_FEMMS,
18607 IX86_BUILTIN_PAVGUSB,
18608 IX86_BUILTIN_PF2ID,
18609 IX86_BUILTIN_PFACC,
18610 IX86_BUILTIN_PFADD,
18611 IX86_BUILTIN_PFCMPEQ,
18612 IX86_BUILTIN_PFCMPGE,
18613 IX86_BUILTIN_PFCMPGT,
18614 IX86_BUILTIN_PFMAX,
18615 IX86_BUILTIN_PFMIN,
18616 IX86_BUILTIN_PFMUL,
18617 IX86_BUILTIN_PFRCP,
18618 IX86_BUILTIN_PFRCPIT1,
18619 IX86_BUILTIN_PFRCPIT2,
18620 IX86_BUILTIN_PFRSQIT1,
18621 IX86_BUILTIN_PFRSQRT,
18622 IX86_BUILTIN_PFSUB,
18623 IX86_BUILTIN_PFSUBR,
18624 IX86_BUILTIN_PI2FD,
18625 IX86_BUILTIN_PMULHRW,
18627 /* 3DNow! Athlon Extensions */
18628 IX86_BUILTIN_PF2IW,
18629 IX86_BUILTIN_PFNACC,
18630 IX86_BUILTIN_PFPNACC,
18631 IX86_BUILTIN_PI2FW,
18632 IX86_BUILTIN_PSWAPDSI,
18633 IX86_BUILTIN_PSWAPDSF,
18636 IX86_BUILTIN_ADDPD,
18637 IX86_BUILTIN_ADDSD,
18638 IX86_BUILTIN_DIVPD,
18639 IX86_BUILTIN_DIVSD,
18640 IX86_BUILTIN_MULPD,
18641 IX86_BUILTIN_MULSD,
18642 IX86_BUILTIN_SUBPD,
18643 IX86_BUILTIN_SUBSD,
18645 IX86_BUILTIN_CMPEQPD,
18646 IX86_BUILTIN_CMPLTPD,
18647 IX86_BUILTIN_CMPLEPD,
18648 IX86_BUILTIN_CMPGTPD,
18649 IX86_BUILTIN_CMPGEPD,
18650 IX86_BUILTIN_CMPNEQPD,
18651 IX86_BUILTIN_CMPNLTPD,
18652 IX86_BUILTIN_CMPNLEPD,
18653 IX86_BUILTIN_CMPNGTPD,
18654 IX86_BUILTIN_CMPNGEPD,
18655 IX86_BUILTIN_CMPORDPD,
18656 IX86_BUILTIN_CMPUNORDPD,
18657 IX86_BUILTIN_CMPEQSD,
18658 IX86_BUILTIN_CMPLTSD,
18659 IX86_BUILTIN_CMPLESD,
18660 IX86_BUILTIN_CMPNEQSD,
18661 IX86_BUILTIN_CMPNLTSD,
18662 IX86_BUILTIN_CMPNLESD,
18663 IX86_BUILTIN_CMPORDSD,
18664 IX86_BUILTIN_CMPUNORDSD,
18666 IX86_BUILTIN_COMIEQSD,
18667 IX86_BUILTIN_COMILTSD,
18668 IX86_BUILTIN_COMILESD,
18669 IX86_BUILTIN_COMIGTSD,
18670 IX86_BUILTIN_COMIGESD,
18671 IX86_BUILTIN_COMINEQSD,
18672 IX86_BUILTIN_UCOMIEQSD,
18673 IX86_BUILTIN_UCOMILTSD,
18674 IX86_BUILTIN_UCOMILESD,
18675 IX86_BUILTIN_UCOMIGTSD,
18676 IX86_BUILTIN_UCOMIGESD,
18677 IX86_BUILTIN_UCOMINEQSD,
18679 IX86_BUILTIN_MAXPD,
18680 IX86_BUILTIN_MAXSD,
18681 IX86_BUILTIN_MINPD,
18682 IX86_BUILTIN_MINSD,
18684 IX86_BUILTIN_ANDPD,
18685 IX86_BUILTIN_ANDNPD,
18687 IX86_BUILTIN_XORPD,
18689 IX86_BUILTIN_SQRTPD,
18690 IX86_BUILTIN_SQRTSD,
18692 IX86_BUILTIN_UNPCKHPD,
18693 IX86_BUILTIN_UNPCKLPD,
18695 IX86_BUILTIN_SHUFPD,
18697 IX86_BUILTIN_LOADUPD,
18698 IX86_BUILTIN_STOREUPD,
18699 IX86_BUILTIN_MOVSD,
18701 IX86_BUILTIN_LOADHPD,
18702 IX86_BUILTIN_LOADLPD,
18704 IX86_BUILTIN_CVTDQ2PD,
18705 IX86_BUILTIN_CVTDQ2PS,
18707 IX86_BUILTIN_CVTPD2DQ,
18708 IX86_BUILTIN_CVTPD2PI,
18709 IX86_BUILTIN_CVTPD2PS,
18710 IX86_BUILTIN_CVTTPD2DQ,
18711 IX86_BUILTIN_CVTTPD2PI,
18713 IX86_BUILTIN_CVTPI2PD,
18714 IX86_BUILTIN_CVTSI2SD,
18715 IX86_BUILTIN_CVTSI642SD,
18717 IX86_BUILTIN_CVTSD2SI,
18718 IX86_BUILTIN_CVTSD2SI64,
18719 IX86_BUILTIN_CVTSD2SS,
18720 IX86_BUILTIN_CVTSS2SD,
18721 IX86_BUILTIN_CVTTSD2SI,
18722 IX86_BUILTIN_CVTTSD2SI64,
18724 IX86_BUILTIN_CVTPS2DQ,
18725 IX86_BUILTIN_CVTPS2PD,
18726 IX86_BUILTIN_CVTTPS2DQ,
18728 IX86_BUILTIN_MOVNTI,
18729 IX86_BUILTIN_MOVNTPD,
18730 IX86_BUILTIN_MOVNTDQ,
18733 IX86_BUILTIN_MASKMOVDQU,
18734 IX86_BUILTIN_MOVMSKPD,
18735 IX86_BUILTIN_PMOVMSKB128,
18737 IX86_BUILTIN_PACKSSWB128,
18738 IX86_BUILTIN_PACKSSDW128,
18739 IX86_BUILTIN_PACKUSWB128,
18741 IX86_BUILTIN_PADDB128,
18742 IX86_BUILTIN_PADDW128,
18743 IX86_BUILTIN_PADDD128,
18744 IX86_BUILTIN_PADDQ128,
18745 IX86_BUILTIN_PADDSB128,
18746 IX86_BUILTIN_PADDSW128,
18747 IX86_BUILTIN_PADDUSB128,
18748 IX86_BUILTIN_PADDUSW128,
18749 IX86_BUILTIN_PSUBB128,
18750 IX86_BUILTIN_PSUBW128,
18751 IX86_BUILTIN_PSUBD128,
18752 IX86_BUILTIN_PSUBQ128,
18753 IX86_BUILTIN_PSUBSB128,
18754 IX86_BUILTIN_PSUBSW128,
18755 IX86_BUILTIN_PSUBUSB128,
18756 IX86_BUILTIN_PSUBUSW128,
18758 IX86_BUILTIN_PAND128,
18759 IX86_BUILTIN_PANDN128,
18760 IX86_BUILTIN_POR128,
18761 IX86_BUILTIN_PXOR128,
18763 IX86_BUILTIN_PAVGB128,
18764 IX86_BUILTIN_PAVGW128,
18766 IX86_BUILTIN_PCMPEQB128,
18767 IX86_BUILTIN_PCMPEQW128,
18768 IX86_BUILTIN_PCMPEQD128,
18769 IX86_BUILTIN_PCMPGTB128,
18770 IX86_BUILTIN_PCMPGTW128,
18771 IX86_BUILTIN_PCMPGTD128,
18773 IX86_BUILTIN_PMADDWD128,
18775 IX86_BUILTIN_PMAXSW128,
18776 IX86_BUILTIN_PMAXUB128,
18777 IX86_BUILTIN_PMINSW128,
18778 IX86_BUILTIN_PMINUB128,
18780 IX86_BUILTIN_PMULUDQ,
18781 IX86_BUILTIN_PMULUDQ128,
18782 IX86_BUILTIN_PMULHUW128,
18783 IX86_BUILTIN_PMULHW128,
18784 IX86_BUILTIN_PMULLW128,
18786 IX86_BUILTIN_PSADBW128,
18787 IX86_BUILTIN_PSHUFHW,
18788 IX86_BUILTIN_PSHUFLW,
18789 IX86_BUILTIN_PSHUFD,
18791 IX86_BUILTIN_PSLLDQI128,
18792 IX86_BUILTIN_PSLLWI128,
18793 IX86_BUILTIN_PSLLDI128,
18794 IX86_BUILTIN_PSLLQI128,
18795 IX86_BUILTIN_PSRAWI128,
18796 IX86_BUILTIN_PSRADI128,
18797 IX86_BUILTIN_PSRLDQI128,
18798 IX86_BUILTIN_PSRLWI128,
18799 IX86_BUILTIN_PSRLDI128,
18800 IX86_BUILTIN_PSRLQI128,
18802 IX86_BUILTIN_PSLLDQ128,
18803 IX86_BUILTIN_PSLLW128,
18804 IX86_BUILTIN_PSLLD128,
18805 IX86_BUILTIN_PSLLQ128,
18806 IX86_BUILTIN_PSRAW128,
18807 IX86_BUILTIN_PSRAD128,
18808 IX86_BUILTIN_PSRLW128,
18809 IX86_BUILTIN_PSRLD128,
18810 IX86_BUILTIN_PSRLQ128,
18812 IX86_BUILTIN_PUNPCKHBW128,
18813 IX86_BUILTIN_PUNPCKHWD128,
18814 IX86_BUILTIN_PUNPCKHDQ128,
18815 IX86_BUILTIN_PUNPCKHQDQ128,
18816 IX86_BUILTIN_PUNPCKLBW128,
18817 IX86_BUILTIN_PUNPCKLWD128,
18818 IX86_BUILTIN_PUNPCKLDQ128,
18819 IX86_BUILTIN_PUNPCKLQDQ128,
18821 IX86_BUILTIN_CLFLUSH,
18822 IX86_BUILTIN_MFENCE,
18823 IX86_BUILTIN_LFENCE,
18826 IX86_BUILTIN_ADDSUBPS,
18827 IX86_BUILTIN_HADDPS,
18828 IX86_BUILTIN_HSUBPS,
18829 IX86_BUILTIN_MOVSHDUP,
18830 IX86_BUILTIN_MOVSLDUP,
18831 IX86_BUILTIN_ADDSUBPD,
18832 IX86_BUILTIN_HADDPD,
18833 IX86_BUILTIN_HSUBPD,
18834 IX86_BUILTIN_LDDQU,
18836 IX86_BUILTIN_MONITOR,
18837 IX86_BUILTIN_MWAIT,
18840 IX86_BUILTIN_PHADDW,
18841 IX86_BUILTIN_PHADDD,
18842 IX86_BUILTIN_PHADDSW,
18843 IX86_BUILTIN_PHSUBW,
18844 IX86_BUILTIN_PHSUBD,
18845 IX86_BUILTIN_PHSUBSW,
18846 IX86_BUILTIN_PMADDUBSW,
18847 IX86_BUILTIN_PMULHRSW,
18848 IX86_BUILTIN_PSHUFB,
18849 IX86_BUILTIN_PSIGNB,
18850 IX86_BUILTIN_PSIGNW,
18851 IX86_BUILTIN_PSIGND,
18852 IX86_BUILTIN_PALIGNR,
18853 IX86_BUILTIN_PABSB,
18854 IX86_BUILTIN_PABSW,
18855 IX86_BUILTIN_PABSD,
18857 IX86_BUILTIN_PHADDW128,
18858 IX86_BUILTIN_PHADDD128,
18859 IX86_BUILTIN_PHADDSW128,
18860 IX86_BUILTIN_PHSUBW128,
18861 IX86_BUILTIN_PHSUBD128,
18862 IX86_BUILTIN_PHSUBSW128,
18863 IX86_BUILTIN_PMADDUBSW128,
18864 IX86_BUILTIN_PMULHRSW128,
18865 IX86_BUILTIN_PSHUFB128,
18866 IX86_BUILTIN_PSIGNB128,
18867 IX86_BUILTIN_PSIGNW128,
18868 IX86_BUILTIN_PSIGND128,
18869 IX86_BUILTIN_PALIGNR128,
18870 IX86_BUILTIN_PABSB128,
18871 IX86_BUILTIN_PABSW128,
18872 IX86_BUILTIN_PABSD128,
18874 /* AMDFAM10 - SSE4A New Instructions. */
18875 IX86_BUILTIN_MOVNTSD,
18876 IX86_BUILTIN_MOVNTSS,
18877 IX86_BUILTIN_EXTRQI,
18878 IX86_BUILTIN_EXTRQ,
18879 IX86_BUILTIN_INSERTQI,
18880 IX86_BUILTIN_INSERTQ,
18883 IX86_BUILTIN_BLENDPD,
18884 IX86_BUILTIN_BLENDPS,
18885 IX86_BUILTIN_BLENDVPD,
18886 IX86_BUILTIN_BLENDVPS,
18887 IX86_BUILTIN_PBLENDVB128,
18888 IX86_BUILTIN_PBLENDW128,
18893 IX86_BUILTIN_INSERTPS128,
18895 IX86_BUILTIN_MOVNTDQA,
18896 IX86_BUILTIN_MPSADBW128,
18897 IX86_BUILTIN_PACKUSDW128,
18898 IX86_BUILTIN_PCMPEQQ,
18899 IX86_BUILTIN_PHMINPOSUW128,
18901 IX86_BUILTIN_PMAXSB128,
18902 IX86_BUILTIN_PMAXSD128,
18903 IX86_BUILTIN_PMAXUD128,
18904 IX86_BUILTIN_PMAXUW128,
18906 IX86_BUILTIN_PMINSB128,
18907 IX86_BUILTIN_PMINSD128,
18908 IX86_BUILTIN_PMINUD128,
18909 IX86_BUILTIN_PMINUW128,
18911 IX86_BUILTIN_PMOVSXBW128,
18912 IX86_BUILTIN_PMOVSXBD128,
18913 IX86_BUILTIN_PMOVSXBQ128,
18914 IX86_BUILTIN_PMOVSXWD128,
18915 IX86_BUILTIN_PMOVSXWQ128,
18916 IX86_BUILTIN_PMOVSXDQ128,
18918 IX86_BUILTIN_PMOVZXBW128,
18919 IX86_BUILTIN_PMOVZXBD128,
18920 IX86_BUILTIN_PMOVZXBQ128,
18921 IX86_BUILTIN_PMOVZXWD128,
18922 IX86_BUILTIN_PMOVZXWQ128,
18923 IX86_BUILTIN_PMOVZXDQ128,
18925 IX86_BUILTIN_PMULDQ128,
18926 IX86_BUILTIN_PMULLD128,
18928 IX86_BUILTIN_ROUNDPD,
18929 IX86_BUILTIN_ROUNDPS,
18930 IX86_BUILTIN_ROUNDSD,
18931 IX86_BUILTIN_ROUNDSS,
18933 IX86_BUILTIN_PTESTZ,
18934 IX86_BUILTIN_PTESTC,
18935 IX86_BUILTIN_PTESTNZC,
18937 IX86_BUILTIN_VEC_INIT_V2SI,
18938 IX86_BUILTIN_VEC_INIT_V4HI,
18939 IX86_BUILTIN_VEC_INIT_V8QI,
18940 IX86_BUILTIN_VEC_EXT_V2DF,
18941 IX86_BUILTIN_VEC_EXT_V2DI,
18942 IX86_BUILTIN_VEC_EXT_V4SF,
18943 IX86_BUILTIN_VEC_EXT_V4SI,
18944 IX86_BUILTIN_VEC_EXT_V8HI,
18945 IX86_BUILTIN_VEC_EXT_V2SI,
18946 IX86_BUILTIN_VEC_EXT_V4HI,
18947 IX86_BUILTIN_VEC_EXT_V16QI,
18948 IX86_BUILTIN_VEC_SET_V2DI,
18949 IX86_BUILTIN_VEC_SET_V4SF,
18950 IX86_BUILTIN_VEC_SET_V4SI,
18951 IX86_BUILTIN_VEC_SET_V8HI,
18952 IX86_BUILTIN_VEC_SET_V4HI,
18953 IX86_BUILTIN_VEC_SET_V16QI,
18955 IX86_BUILTIN_VEC_PACK_SFIX,
18958 IX86_BUILTIN_CRC32QI,
18959 IX86_BUILTIN_CRC32HI,
18960 IX86_BUILTIN_CRC32SI,
18961 IX86_BUILTIN_CRC32DI,
18963 IX86_BUILTIN_PCMPESTRI128,
18964 IX86_BUILTIN_PCMPESTRM128,
18965 IX86_BUILTIN_PCMPESTRA128,
18966 IX86_BUILTIN_PCMPESTRC128,
18967 IX86_BUILTIN_PCMPESTRO128,
18968 IX86_BUILTIN_PCMPESTRS128,
18969 IX86_BUILTIN_PCMPESTRZ128,
18970 IX86_BUILTIN_PCMPISTRI128,
18971 IX86_BUILTIN_PCMPISTRM128,
18972 IX86_BUILTIN_PCMPISTRA128,
18973 IX86_BUILTIN_PCMPISTRC128,
18974 IX86_BUILTIN_PCMPISTRO128,
18975 IX86_BUILTIN_PCMPISTRS128,
18976 IX86_BUILTIN_PCMPISTRZ128,
18978 IX86_BUILTIN_PCMPGTQ,
18980 /* AES instructions */
18981 IX86_BUILTIN_AESENC128,
18982 IX86_BUILTIN_AESENCLAST128,
18983 IX86_BUILTIN_AESDEC128,
18984 IX86_BUILTIN_AESDECLAST128,
18985 IX86_BUILTIN_AESIMC128,
18986 IX86_BUILTIN_AESKEYGENASSIST128,
18988 /* PCLMUL instruction */
18989 IX86_BUILTIN_PCLMULQDQ128,
18991 /* TFmode support builtins. */
18993 IX86_BUILTIN_FABSQ,
18994 IX86_BUILTIN_COPYSIGNQ,
18996 /* SSE5 instructions */
18997 IX86_BUILTIN_FMADDSS,
18998 IX86_BUILTIN_FMADDSD,
18999 IX86_BUILTIN_FMADDPS,
19000 IX86_BUILTIN_FMADDPD,
19001 IX86_BUILTIN_FMSUBSS,
19002 IX86_BUILTIN_FMSUBSD,
19003 IX86_BUILTIN_FMSUBPS,
19004 IX86_BUILTIN_FMSUBPD,
19005 IX86_BUILTIN_FNMADDSS,
19006 IX86_BUILTIN_FNMADDSD,
19007 IX86_BUILTIN_FNMADDPS,
19008 IX86_BUILTIN_FNMADDPD,
19009 IX86_BUILTIN_FNMSUBSS,
19010 IX86_BUILTIN_FNMSUBSD,
19011 IX86_BUILTIN_FNMSUBPS,
19012 IX86_BUILTIN_FNMSUBPD,
19013 IX86_BUILTIN_PCMOV_V2DI,
19014 IX86_BUILTIN_PCMOV_V4SI,
19015 IX86_BUILTIN_PCMOV_V8HI,
19016 IX86_BUILTIN_PCMOV_V16QI,
19017 IX86_BUILTIN_PCMOV_V4SF,
19018 IX86_BUILTIN_PCMOV_V2DF,
19019 IX86_BUILTIN_PPERM,
19020 IX86_BUILTIN_PERMPS,
19021 IX86_BUILTIN_PERMPD,
19022 IX86_BUILTIN_PMACSSWW,
19023 IX86_BUILTIN_PMACSWW,
19024 IX86_BUILTIN_PMACSSWD,
19025 IX86_BUILTIN_PMACSWD,
19026 IX86_BUILTIN_PMACSSDD,
19027 IX86_BUILTIN_PMACSDD,
19028 IX86_BUILTIN_PMACSSDQL,
19029 IX86_BUILTIN_PMACSSDQH,
19030 IX86_BUILTIN_PMACSDQL,
19031 IX86_BUILTIN_PMACSDQH,
19032 IX86_BUILTIN_PMADCSSWD,
19033 IX86_BUILTIN_PMADCSWD,
19034 IX86_BUILTIN_PHADDBW,
19035 IX86_BUILTIN_PHADDBD,
19036 IX86_BUILTIN_PHADDBQ,
19037 IX86_BUILTIN_PHADDWD,
19038 IX86_BUILTIN_PHADDWQ,
19039 IX86_BUILTIN_PHADDDQ,
19040 IX86_BUILTIN_PHADDUBW,
19041 IX86_BUILTIN_PHADDUBD,
19042 IX86_BUILTIN_PHADDUBQ,
19043 IX86_BUILTIN_PHADDUWD,
19044 IX86_BUILTIN_PHADDUWQ,
19045 IX86_BUILTIN_PHADDUDQ,
19046 IX86_BUILTIN_PHSUBBW,
19047 IX86_BUILTIN_PHSUBWD,
19048 IX86_BUILTIN_PHSUBDQ,
19049 IX86_BUILTIN_PROTB,
19050 IX86_BUILTIN_PROTW,
19051 IX86_BUILTIN_PROTD,
19052 IX86_BUILTIN_PROTQ,
19053 IX86_BUILTIN_PROTB_IMM,
19054 IX86_BUILTIN_PROTW_IMM,
19055 IX86_BUILTIN_PROTD_IMM,
19056 IX86_BUILTIN_PROTQ_IMM,
19057 IX86_BUILTIN_PSHLB,
19058 IX86_BUILTIN_PSHLW,
19059 IX86_BUILTIN_PSHLD,
19060 IX86_BUILTIN_PSHLQ,
19061 IX86_BUILTIN_PSHAB,
19062 IX86_BUILTIN_PSHAW,
19063 IX86_BUILTIN_PSHAD,
19064 IX86_BUILTIN_PSHAQ,
19065 IX86_BUILTIN_FRCZSS,
19066 IX86_BUILTIN_FRCZSD,
19067 IX86_BUILTIN_FRCZPS,
19068 IX86_BUILTIN_FRCZPD,
19069 IX86_BUILTIN_CVTPH2PS,
19070 IX86_BUILTIN_CVTPS2PH,
19072 IX86_BUILTIN_COMEQSS,
19073 IX86_BUILTIN_COMNESS,
19074 IX86_BUILTIN_COMLTSS,
19075 IX86_BUILTIN_COMLESS,
19076 IX86_BUILTIN_COMGTSS,
19077 IX86_BUILTIN_COMGESS,
19078 IX86_BUILTIN_COMUEQSS,
19079 IX86_BUILTIN_COMUNESS,
19080 IX86_BUILTIN_COMULTSS,
19081 IX86_BUILTIN_COMULESS,
19082 IX86_BUILTIN_COMUGTSS,
19083 IX86_BUILTIN_COMUGESS,
19084 IX86_BUILTIN_COMORDSS,
19085 IX86_BUILTIN_COMUNORDSS,
19086 IX86_BUILTIN_COMFALSESS,
19087 IX86_BUILTIN_COMTRUESS,
19089 IX86_BUILTIN_COMEQSD,
19090 IX86_BUILTIN_COMNESD,
19091 IX86_BUILTIN_COMLTSD,
19092 IX86_BUILTIN_COMLESD,
19093 IX86_BUILTIN_COMGTSD,
19094 IX86_BUILTIN_COMGESD,
19095 IX86_BUILTIN_COMUEQSD,
19096 IX86_BUILTIN_COMUNESD,
19097 IX86_BUILTIN_COMULTSD,
19098 IX86_BUILTIN_COMULESD,
19099 IX86_BUILTIN_COMUGTSD,
19100 IX86_BUILTIN_COMUGESD,
19101 IX86_BUILTIN_COMORDSD,
19102 IX86_BUILTIN_COMUNORDSD,
19103 IX86_BUILTIN_COMFALSESD,
19104 IX86_BUILTIN_COMTRUESD,
19106 IX86_BUILTIN_COMEQPS,
19107 IX86_BUILTIN_COMNEPS,
19108 IX86_BUILTIN_COMLTPS,
19109 IX86_BUILTIN_COMLEPS,
19110 IX86_BUILTIN_COMGTPS,
19111 IX86_BUILTIN_COMGEPS,
19112 IX86_BUILTIN_COMUEQPS,
19113 IX86_BUILTIN_COMUNEPS,
19114 IX86_BUILTIN_COMULTPS,
19115 IX86_BUILTIN_COMULEPS,
19116 IX86_BUILTIN_COMUGTPS,
19117 IX86_BUILTIN_COMUGEPS,
19118 IX86_BUILTIN_COMORDPS,
19119 IX86_BUILTIN_COMUNORDPS,
19120 IX86_BUILTIN_COMFALSEPS,
19121 IX86_BUILTIN_COMTRUEPS,
19123 IX86_BUILTIN_COMEQPD,
19124 IX86_BUILTIN_COMNEPD,
19125 IX86_BUILTIN_COMLTPD,
19126 IX86_BUILTIN_COMLEPD,
19127 IX86_BUILTIN_COMGTPD,
19128 IX86_BUILTIN_COMGEPD,
19129 IX86_BUILTIN_COMUEQPD,
19130 IX86_BUILTIN_COMUNEPD,
19131 IX86_BUILTIN_COMULTPD,
19132 IX86_BUILTIN_COMULEPD,
19133 IX86_BUILTIN_COMUGTPD,
19134 IX86_BUILTIN_COMUGEPD,
19135 IX86_BUILTIN_COMORDPD,
19136 IX86_BUILTIN_COMUNORDPD,
19137 IX86_BUILTIN_COMFALSEPD,
19138 IX86_BUILTIN_COMTRUEPD,
19140 IX86_BUILTIN_PCOMEQUB,
19141 IX86_BUILTIN_PCOMNEUB,
19142 IX86_BUILTIN_PCOMLTUB,
19143 IX86_BUILTIN_PCOMLEUB,
19144 IX86_BUILTIN_PCOMGTUB,
19145 IX86_BUILTIN_PCOMGEUB,
19146 IX86_BUILTIN_PCOMFALSEUB,
19147 IX86_BUILTIN_PCOMTRUEUB,
19148 IX86_BUILTIN_PCOMEQUW,
19149 IX86_BUILTIN_PCOMNEUW,
19150 IX86_BUILTIN_PCOMLTUW,
19151 IX86_BUILTIN_PCOMLEUW,
19152 IX86_BUILTIN_PCOMGTUW,
19153 IX86_BUILTIN_PCOMGEUW,
19154 IX86_BUILTIN_PCOMFALSEUW,
19155 IX86_BUILTIN_PCOMTRUEUW,
19156 IX86_BUILTIN_PCOMEQUD,
19157 IX86_BUILTIN_PCOMNEUD,
19158 IX86_BUILTIN_PCOMLTUD,
19159 IX86_BUILTIN_PCOMLEUD,
19160 IX86_BUILTIN_PCOMGTUD,
19161 IX86_BUILTIN_PCOMGEUD,
19162 IX86_BUILTIN_PCOMFALSEUD,
19163 IX86_BUILTIN_PCOMTRUEUD,
19164 IX86_BUILTIN_PCOMEQUQ,
19165 IX86_BUILTIN_PCOMNEUQ,
19166 IX86_BUILTIN_PCOMLTUQ,
19167 IX86_BUILTIN_PCOMLEUQ,
19168 IX86_BUILTIN_PCOMGTUQ,
19169 IX86_BUILTIN_PCOMGEUQ,
19170 IX86_BUILTIN_PCOMFALSEUQ,
19171 IX86_BUILTIN_PCOMTRUEUQ,
19173 IX86_BUILTIN_PCOMEQB,
19174 IX86_BUILTIN_PCOMNEB,
19175 IX86_BUILTIN_PCOMLTB,
19176 IX86_BUILTIN_PCOMLEB,
19177 IX86_BUILTIN_PCOMGTB,
19178 IX86_BUILTIN_PCOMGEB,
19179 IX86_BUILTIN_PCOMFALSEB,
19180 IX86_BUILTIN_PCOMTRUEB,
19181 IX86_BUILTIN_PCOMEQW,
19182 IX86_BUILTIN_PCOMNEW,
19183 IX86_BUILTIN_PCOMLTW,
19184 IX86_BUILTIN_PCOMLEW,
19185 IX86_BUILTIN_PCOMGTW,
19186 IX86_BUILTIN_PCOMGEW,
19187 IX86_BUILTIN_PCOMFALSEW,
19188 IX86_BUILTIN_PCOMTRUEW,
19189 IX86_BUILTIN_PCOMEQD,
19190 IX86_BUILTIN_PCOMNED,
19191 IX86_BUILTIN_PCOMLTD,
19192 IX86_BUILTIN_PCOMLED,
19193 IX86_BUILTIN_PCOMGTD,
19194 IX86_BUILTIN_PCOMGED,
19195 IX86_BUILTIN_PCOMFALSED,
19196 IX86_BUILTIN_PCOMTRUED,
19197 IX86_BUILTIN_PCOMEQQ,
19198 IX86_BUILTIN_PCOMNEQ,
19199 IX86_BUILTIN_PCOMLTQ,
19200 IX86_BUILTIN_PCOMLEQ,
19201 IX86_BUILTIN_PCOMGTQ,
19202 IX86_BUILTIN_PCOMGEQ,
19203 IX86_BUILTIN_PCOMFALSEQ,
19204 IX86_BUILTIN_PCOMTRUEQ,
19209 /* Table for the ix86 builtin decls. */
19210 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
19212 /* Table to record which ISA options the builtin needs. */
19213 static int ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
19215 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
19216 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
19217 * function decl in the ix86_builtins array. Returns the function decl or
19218 * NULL_TREE, if the builtin was not added.
19220 * Record all builtins, even if it isn't an instruction set in the current ISA
19221 * in case the user uses function specific options for a different ISA. When
19222 * the builtin is expanded, check at that time whether it is valid. */
19225 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
19227 tree decl = NULL_TREE;
19229 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
19231 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
19233 ix86_builtins[(int) code] = decl;
19234 ix86_builtins_isa[(int) code] = mask;
19240 /* Like def_builtin, but also marks the function decl "const". */
19243 def_builtin_const (int mask, const char *name, tree type,
19244 enum ix86_builtins code)
19246 tree decl = def_builtin (mask, name, type, code);
19248 TREE_READONLY (decl) = 1;
19252 /* Bits for builtin_description.flag. */
19254 /* Set when we don't support the comparison natively, and should
19255 swap_comparison in order to support it. */
19256 #define BUILTIN_DESC_SWAP_OPERANDS 1
19258 struct builtin_description
19260 const unsigned int mask;
19261 const enum insn_code icode;
19262 const char *const name;
19263 const enum ix86_builtins code;
19264 const enum rtx_code comparison;
19268 static const struct builtin_description bdesc_comi[] =
19270 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
19271 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
19272 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
19273 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
19274 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
19275 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
19276 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
19277 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
19278 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
19279 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
19280 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
19281 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
19282 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
19283 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
19284 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
19285 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
19286 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
19287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
19288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
19289 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
19290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
19291 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
19292 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
19293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
19296 static const struct builtin_description bdesc_pcmpestr[] =
19299 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
19300 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
19301 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
19302 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
19303 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
19304 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
19305 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
19308 static const struct builtin_description bdesc_pcmpistr[] =
19311 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
19312 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
19313 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
19314 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
19315 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
19316 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
19317 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
19320 /* Special builtin types */
19321 enum ix86_special_builtin_type
19323 SPECIAL_FTYPE_UNKNOWN,
19325 V16QI_FTYPE_PCCHAR,
19326 V4SF_FTYPE_PCFLOAT,
19327 V2DF_FTYPE_PCDOUBLE,
19328 V4SF_FTYPE_V4SF_PCV2SF,
19329 V2DF_FTYPE_V2DF_PCDOUBLE,
19331 VOID_FTYPE_PV2SF_V4SF,
19332 VOID_FTYPE_PV2DI_V2DI,
19333 VOID_FTYPE_PCHAR_V16QI,
19334 VOID_FTYPE_PFLOAT_V4SF,
19335 VOID_FTYPE_PDOUBLE_V2DF,
19337 VOID_FTYPE_PINT_INT
19340 /* Builtin types */
19341 enum ix86_builtin_type
19344 FLOAT128_FTYPE_FLOAT128,
19346 FLOAT128_FTYPE_FLOAT128_FLOAT128,
19347 INT_FTYPE_V2DI_V2DI_PTEST,
19365 V4SF_FTYPE_V4SF_VEC_MERGE,
19373 V2DF_FTYPE_V2DF_VEC_MERGE,
19383 V16QI_FTYPE_V16QI_V16QI,
19384 V16QI_FTYPE_V8HI_V8HI,
19385 V8QI_FTYPE_V8QI_V8QI,
19386 V8QI_FTYPE_V4HI_V4HI,
19387 V8HI_FTYPE_V8HI_V8HI,
19388 V8HI_FTYPE_V8HI_V8HI_COUNT,
19389 V8HI_FTYPE_V16QI_V16QI,
19390 V8HI_FTYPE_V4SI_V4SI,
19391 V8HI_FTYPE_V8HI_SI_COUNT,
19392 V4SI_FTYPE_V4SI_V4SI,
19393 V4SI_FTYPE_V4SI_V4SI_COUNT,
19394 V4SI_FTYPE_V8HI_V8HI,
19395 V4SI_FTYPE_V4SF_V4SF,
19396 V4SI_FTYPE_V2DF_V2DF,
19397 V4SI_FTYPE_V4SI_SI_COUNT,
19398 V4HI_FTYPE_V4HI_V4HI,
19399 V4HI_FTYPE_V4HI_V4HI_COUNT,
19400 V4HI_FTYPE_V8QI_V8QI,
19401 V4HI_FTYPE_V2SI_V2SI,
19402 V4HI_FTYPE_V4HI_SI_COUNT,
19403 V4SF_FTYPE_V4SF_V4SF,
19404 V4SF_FTYPE_V4SF_V4SF_SWAP,
19405 V4SF_FTYPE_V4SF_V2SI,
19406 V4SF_FTYPE_V4SF_V2DF,
19407 V4SF_FTYPE_V4SF_DI,
19408 V4SF_FTYPE_V4SF_SI,
19409 V2DI_FTYPE_V2DI_V2DI,
19410 V2DI_FTYPE_V2DI_V2DI_COUNT,
19411 V2DI_FTYPE_V16QI_V16QI,
19412 V2DI_FTYPE_V4SI_V4SI,
19413 V2DI_FTYPE_V2DI_V16QI,
19414 V2DI_FTYPE_V2DF_V2DF,
19415 V2DI_FTYPE_V2DI_SI_COUNT,
19416 V2SI_FTYPE_V2SI_V2SI,
19417 V2SI_FTYPE_V2SI_V2SI_COUNT,
19418 V2SI_FTYPE_V4HI_V4HI,
19419 V2SI_FTYPE_V2SF_V2SF,
19420 V2SI_FTYPE_V2SI_SI_COUNT,
19421 V2DF_FTYPE_V2DF_V2DF,
19422 V2DF_FTYPE_V2DF_V2DF_SWAP,
19423 V2DF_FTYPE_V2DF_V4SF,
19424 V2DF_FTYPE_V2DF_DI,
19425 V2DF_FTYPE_V2DF_SI,
19426 V2SF_FTYPE_V2SF_V2SF,
19427 V1DI_FTYPE_V1DI_V1DI,
19428 V1DI_FTYPE_V1DI_V1DI_COUNT,
19429 V1DI_FTYPE_V8QI_V8QI,
19430 V1DI_FTYPE_V2SI_V2SI,
19431 V1DI_FTYPE_V1DI_SI_COUNT,
19432 UINT64_FTYPE_UINT64_UINT64,
19433 UINT_FTYPE_UINT_UINT,
19434 UINT_FTYPE_UINT_USHORT,
19435 UINT_FTYPE_UINT_UCHAR,
19436 V8HI_FTYPE_V8HI_INT,
19437 V4SI_FTYPE_V4SI_INT,
19438 V4HI_FTYPE_V4HI_INT,
19439 V4SF_FTYPE_V4SF_INT,
19440 V2DI_FTYPE_V2DI_INT,
19441 V2DI2TI_FTYPE_V2DI_INT,
19442 V2DF_FTYPE_V2DF_INT,
19443 V16QI_FTYPE_V16QI_V16QI_V16QI,
19444 V4SF_FTYPE_V4SF_V4SF_V4SF,
19445 V2DF_FTYPE_V2DF_V2DF_V2DF,
19446 V16QI_FTYPE_V16QI_V16QI_INT,
19447 V8HI_FTYPE_V8HI_V8HI_INT,
19448 V4SI_FTYPE_V4SI_V4SI_INT,
19449 V4SF_FTYPE_V4SF_V4SF_INT,
19450 V2DI_FTYPE_V2DI_V2DI_INT,
19451 V2DI2TI_FTYPE_V2DI_V2DI_INT,
19452 V1DI2DI_FTYPE_V1DI_V1DI_INT,
19453 V2DF_FTYPE_V2DF_V2DF_INT,
19454 V2DI_FTYPE_V2DI_UINT_UINT,
19455 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
19458 /* Special builtins with variable number of arguments. */
19459 static const struct builtin_description bdesc_special_args[] =
19462 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
19465 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
19468 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
19469 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
19470 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
19472 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
19473 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
19474 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
19475 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
19477 /* SSE or 3DNow!A */
19478 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
19479 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
19482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
19483 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
19484 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
19485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
19486 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
19487 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
19488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
19489 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
19490 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
19492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
19493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
19496 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
19499 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
19502 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
19503 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
19506 /* Builtins with variable number of arguments. */
19507 static const struct builtin_description bdesc_args[] =
19510 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19511 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19512 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19513 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19514 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19515 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19517 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19518 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19519 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19520 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19521 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19522 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19523 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19524 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19526 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19527 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19529 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19530 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19531 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19532 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19534 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19535 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19536 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19537 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19538 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19539 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19541 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19542 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19543 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19544 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19545 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
19546 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
19548 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
19549 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
19550 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
19552 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
19554 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
19555 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
19556 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
19557 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
19558 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
19559 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
19561 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
19562 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
19563 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
19564 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
19565 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
19566 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
19568 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
19569 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
19570 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
19571 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
19574 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
19575 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
19576 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
19577 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
19579 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19580 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19581 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19582 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
19583 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
19584 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
19585 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19586 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19587 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19588 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19589 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19590 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19591 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19592 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19593 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19596 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
19597 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
19598 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
19599 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
19600 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19601 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
19604 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
19605 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19606 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19607 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19608 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19609 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19610 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
19611 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
19612 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
19613 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
19614 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
19615 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
19617 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
19619 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19620 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19621 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19622 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19623 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19624 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19625 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19626 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19628 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
19629 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
19630 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
19631 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
19632 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
19633 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
19634 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
19635 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
19636 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
19637 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
19638 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
19639 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
19640 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
19641 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
19642 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
19643 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
19644 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
19645 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
19646 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
19647 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
19648 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
19649 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
19651 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19652 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19653 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19654 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19656 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19657 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19658 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19659 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19661 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19662 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19663 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19664 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19665 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19667 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
19668 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
19669 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
19671 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
19673 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
19674 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
19675 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
19677 /* SSE MMX or 3Dnow!A */
19678 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19679 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19680 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19682 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19683 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19684 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19685 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19687 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
19688 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
19690 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
19693 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
19695 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
19696 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
19697 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
19698 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
19699 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
19701 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
19702 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
19703 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
19704 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
19705 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
19707 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
19709 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
19710 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
19711 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
19712 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
19714 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
19715 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
19716 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
19718 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19719 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19720 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19721 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19722 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19723 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19724 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19725 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19727 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
19728 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
19729 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
19730 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
19731 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
19732 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
19733 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
19734 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
19735 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
19736 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
19737 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
19738 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
19739 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
19740 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
19741 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
19742 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
19743 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
19744 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
19745 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
19746 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
19748 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19749 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19750 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19751 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19753 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19754 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19755 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19756 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19758 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19759 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19760 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19762 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
19764 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19765 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19766 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19767 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19768 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19769 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19770 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19771 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19773 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19774 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19775 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19776 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19777 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19778 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19779 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19780 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19782 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19783 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
19785 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19786 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19787 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19788 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19790 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19791 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19793 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19794 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19795 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19796 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19797 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19798 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19800 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19801 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19802 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19803 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19805 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19806 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19807 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19808 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19809 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19810 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19811 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19812 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19814 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
19815 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
19816 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
19818 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19819 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
19821 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
19822 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
19824 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
19826 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
19827 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
19828 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
19829 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
19831 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
19832 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
19833 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
19834 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
19835 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
19836 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
19837 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
19839 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
19840 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
19841 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
19842 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
19843 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
19844 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
19845 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
19847 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
19848 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
19849 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
19850 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
19852 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
19853 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
19854 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
19856 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
19858 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
19859 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
19862 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
19863 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
19866 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
19867 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
19869 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19870 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19871 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19872 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19873 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
19874 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
19877 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
19878 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
19879 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
19880 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
19881 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
19882 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
19884 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19885 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19886 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19887 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19888 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19889 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19890 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19891 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19892 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19893 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19894 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19895 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19896 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
19897 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
19898 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19899 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19900 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19901 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19902 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19903 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
19904 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19905 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
19906 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19907 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
19910 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
19911 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
19914 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
19915 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
19916 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
19917 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
19918 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
19919 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
19920 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
19921 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
19922 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
19923 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
19925 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
19926 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
19927 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
19928 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
19929 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
19930 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
19931 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
19932 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
19933 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
19934 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
19935 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
19936 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
19937 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
19939 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
19940 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19941 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19942 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19943 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19944 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19945 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
19946 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19947 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19948 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
19949 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
19950 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
19952 /* SSE4.1 and SSE5 */
19953 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
19954 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
19955 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
19956 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
19958 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
19959 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
19960 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
19963 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19964 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
19965 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
19966 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
19967 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
19970 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
19971 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
19972 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
19973 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19976 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
19977 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
19979 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19980 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19981 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19982 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
19985 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
19989 enum multi_arg_type {
19999 MULTI_ARG_3_PERMPS,
20000 MULTI_ARG_3_PERMPD,
20007 MULTI_ARG_2_DI_IMM,
20008 MULTI_ARG_2_SI_IMM,
20009 MULTI_ARG_2_HI_IMM,
20010 MULTI_ARG_2_QI_IMM,
20011 MULTI_ARG_2_SF_CMP,
20012 MULTI_ARG_2_DF_CMP,
20013 MULTI_ARG_2_DI_CMP,
20014 MULTI_ARG_2_SI_CMP,
20015 MULTI_ARG_2_HI_CMP,
20016 MULTI_ARG_2_QI_CMP,
20039 static const struct builtin_description bdesc_multi_arg[] =
20041 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
20042 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
20043 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
20044 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
20045 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
20046 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
20047 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
20048 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
20049 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
20050 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
20051 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
20052 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
20053 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
20054 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
20055 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
20056 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
20057 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
20058 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
20059 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
20060 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
20061 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
20062 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
20063 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
20064 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
20065 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
20066 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
20067 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
20068 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
20069 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
20070 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
20071 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
20072 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
20073 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
20074 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
20075 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
20076 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
20077 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
20078 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
20079 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
20080 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
20081 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
20082 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
20083 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
20084 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
20085 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
20086 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
20087 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
20088 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
20089 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
20090 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
20091 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
20092 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
20093 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
20094 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
20095 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
20096 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
20097 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
20098 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
20099 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
20100 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
20101 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
20102 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
20103 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
20104 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
20105 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
20106 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
20107 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
20108 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
20109 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
20110 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
20111 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
20112 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
20113 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
20114 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
20115 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
20117 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
20118 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
20119 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
20120 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
20121 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
20122 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
20123 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
20124 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
20125 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
20126 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
20127 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
20128 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
20129 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
20130 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
20131 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
20132 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
20134 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
20135 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
20136 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
20137 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
20138 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
20139 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
20140 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
20141 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
20142 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
20143 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
20144 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
20145 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
20146 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
20147 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
20148 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
20149 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
20151 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
20152 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
20153 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
20154 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
20155 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
20156 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
20157 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
20158 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
20159 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
20160 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
20161 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
20162 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
20163 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
20164 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
20165 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
20166 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
20168 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
20169 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
20170 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
20171 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
20172 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
20173 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
20174 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
20175 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
20176 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
20177 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
20178 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
20179 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
20180 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
20181 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
20182 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
20183 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
20185 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
20186 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
20187 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
20188 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
20189 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
20190 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
20191 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
20193 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
20194 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
20195 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
20196 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
20197 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
20198 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
20199 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
20201 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
20202 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
20203 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
20204 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
20205 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
20206 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
20207 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
20209 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
20210 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
20211 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
20212 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
20213 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
20214 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
20215 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
20217 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
20218 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
20219 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
20220 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
20221 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
20222 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
20223 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
20225 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
20226 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
20227 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
20228 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
20229 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
20230 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
20231 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
20233 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
20234 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
20235 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
20236 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
20237 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
20238 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
20239 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
20241 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
20242 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
20243 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
20244 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
20245 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
20246 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
20247 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
20249 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
20250 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
20251 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
20252 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
20253 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
20254 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
20255 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
20256 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
20258 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
20259 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
20260 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
20261 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
20262 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
20263 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
20264 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
20265 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
20267 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
20268 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
20269 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
20270 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
20271 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
20272 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
20273 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
20274 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
20277 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
20278 in the current target ISA to allow the user to compile particular modules
20279 with different target specific options that differ from the command line
20282 ix86_init_mmx_sse_builtins (void)
20284 const struct builtin_description * d;
20287 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
20288 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
20289 tree V1DI_type_node
20290 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
20291 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
20292 tree V2DI_type_node
20293 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
20294 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
20295 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
20296 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
20297 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
20298 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
20299 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
20301 tree pchar_type_node = build_pointer_type (char_type_node);
20302 tree pcchar_type_node
20303 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
20304 tree pfloat_type_node = build_pointer_type (float_type_node);
20305 tree pcfloat_type_node
20306 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
20307 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
20308 tree pcv2sf_type_node
20309 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
20310 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
20311 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
20314 tree int_ftype_v4sf_v4sf
20315 = build_function_type_list (integer_type_node,
20316 V4SF_type_node, V4SF_type_node, NULL_TREE);
20317 tree v4si_ftype_v4sf_v4sf
20318 = build_function_type_list (V4SI_type_node,
20319 V4SF_type_node, V4SF_type_node, NULL_TREE);
20320 /* MMX/SSE/integer conversions. */
20321 tree int_ftype_v4sf
20322 = build_function_type_list (integer_type_node,
20323 V4SF_type_node, NULL_TREE);
20324 tree int64_ftype_v4sf
20325 = build_function_type_list (long_long_integer_type_node,
20326 V4SF_type_node, NULL_TREE);
20327 tree int_ftype_v8qi
20328 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
20329 tree v4sf_ftype_v4sf_int
20330 = build_function_type_list (V4SF_type_node,
20331 V4SF_type_node, integer_type_node, NULL_TREE);
20332 tree v4sf_ftype_v4sf_int64
20333 = build_function_type_list (V4SF_type_node,
20334 V4SF_type_node, long_long_integer_type_node,
20336 tree v4sf_ftype_v4sf_v2si
20337 = build_function_type_list (V4SF_type_node,
20338 V4SF_type_node, V2SI_type_node, NULL_TREE);
20340 /* Miscellaneous. */
20341 tree v8qi_ftype_v4hi_v4hi
20342 = build_function_type_list (V8QI_type_node,
20343 V4HI_type_node, V4HI_type_node, NULL_TREE);
20344 tree v4hi_ftype_v2si_v2si
20345 = build_function_type_list (V4HI_type_node,
20346 V2SI_type_node, V2SI_type_node, NULL_TREE);
20347 tree v4sf_ftype_v4sf_v4sf_int
20348 = build_function_type_list (V4SF_type_node,
20349 V4SF_type_node, V4SF_type_node,
20350 integer_type_node, NULL_TREE);
20351 tree v2si_ftype_v4hi_v4hi
20352 = build_function_type_list (V2SI_type_node,
20353 V4HI_type_node, V4HI_type_node, NULL_TREE);
20354 tree v4hi_ftype_v4hi_int
20355 = build_function_type_list (V4HI_type_node,
20356 V4HI_type_node, integer_type_node, NULL_TREE);
20357 tree v2si_ftype_v2si_int
20358 = build_function_type_list (V2SI_type_node,
20359 V2SI_type_node, integer_type_node, NULL_TREE);
20360 tree v1di_ftype_v1di_int
20361 = build_function_type_list (V1DI_type_node,
20362 V1DI_type_node, integer_type_node, NULL_TREE);
20364 tree void_ftype_void
20365 = build_function_type (void_type_node, void_list_node);
20366 tree void_ftype_unsigned
20367 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
20368 tree void_ftype_unsigned_unsigned
20369 = build_function_type_list (void_type_node, unsigned_type_node,
20370 unsigned_type_node, NULL_TREE);
20371 tree void_ftype_pcvoid_unsigned_unsigned
20372 = build_function_type_list (void_type_node, const_ptr_type_node,
20373 unsigned_type_node, unsigned_type_node,
20375 tree unsigned_ftype_void
20376 = build_function_type (unsigned_type_node, void_list_node);
20377 tree v2si_ftype_v4sf
20378 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
20379 /* Loads/stores. */
20380 tree void_ftype_v8qi_v8qi_pchar
20381 = build_function_type_list (void_type_node,
20382 V8QI_type_node, V8QI_type_node,
20383 pchar_type_node, NULL_TREE);
20384 tree v4sf_ftype_pcfloat
20385 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
20386 tree v4sf_ftype_v4sf_pcv2sf
20387 = build_function_type_list (V4SF_type_node,
20388 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
20389 tree void_ftype_pv2sf_v4sf
20390 = build_function_type_list (void_type_node,
20391 pv2sf_type_node, V4SF_type_node, NULL_TREE);
20392 tree void_ftype_pfloat_v4sf
20393 = build_function_type_list (void_type_node,
20394 pfloat_type_node, V4SF_type_node, NULL_TREE);
20395 tree void_ftype_pdi_di
20396 = build_function_type_list (void_type_node,
20397 pdi_type_node, long_long_unsigned_type_node,
20399 tree void_ftype_pv2di_v2di
20400 = build_function_type_list (void_type_node,
20401 pv2di_type_node, V2DI_type_node, NULL_TREE);
20402 /* Normal vector unops. */
20403 tree v4sf_ftype_v4sf
20404 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
20405 tree v16qi_ftype_v16qi
20406 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
20407 tree v8hi_ftype_v8hi
20408 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
20409 tree v4si_ftype_v4si
20410 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
20411 tree v8qi_ftype_v8qi
20412 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
20413 tree v4hi_ftype_v4hi
20414 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
20416 /* Normal vector binops. */
20417 tree v4sf_ftype_v4sf_v4sf
20418 = build_function_type_list (V4SF_type_node,
20419 V4SF_type_node, V4SF_type_node, NULL_TREE);
20420 tree v8qi_ftype_v8qi_v8qi
20421 = build_function_type_list (V8QI_type_node,
20422 V8QI_type_node, V8QI_type_node, NULL_TREE);
20423 tree v4hi_ftype_v4hi_v4hi
20424 = build_function_type_list (V4HI_type_node,
20425 V4HI_type_node, V4HI_type_node, NULL_TREE);
20426 tree v2si_ftype_v2si_v2si
20427 = build_function_type_list (V2SI_type_node,
20428 V2SI_type_node, V2SI_type_node, NULL_TREE);
20429 tree v1di_ftype_v1di_v1di
20430 = build_function_type_list (V1DI_type_node,
20431 V1DI_type_node, V1DI_type_node, NULL_TREE);
20432 tree v1di_ftype_v1di_v1di_int
20433 = build_function_type_list (V1DI_type_node,
20434 V1DI_type_node, V1DI_type_node,
20435 integer_type_node, NULL_TREE);
20436 tree v2si_ftype_v2sf
20437 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
20438 tree v2sf_ftype_v2si
20439 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
20440 tree v2si_ftype_v2si
20441 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
20442 tree v2sf_ftype_v2sf
20443 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
20444 tree v2sf_ftype_v2sf_v2sf
20445 = build_function_type_list (V2SF_type_node,
20446 V2SF_type_node, V2SF_type_node, NULL_TREE);
20447 tree v2si_ftype_v2sf_v2sf
20448 = build_function_type_list (V2SI_type_node,
20449 V2SF_type_node, V2SF_type_node, NULL_TREE);
20450 tree pint_type_node = build_pointer_type (integer_type_node);
20451 tree pdouble_type_node = build_pointer_type (double_type_node);
20452 tree pcdouble_type_node = build_pointer_type (
20453 build_type_variant (double_type_node, 1, 0));
20454 tree int_ftype_v2df_v2df
20455 = build_function_type_list (integer_type_node,
20456 V2DF_type_node, V2DF_type_node, NULL_TREE);
20458 tree void_ftype_pcvoid
20459 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
20460 tree v4sf_ftype_v4si
20461 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
20462 tree v4si_ftype_v4sf
20463 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
20464 tree v2df_ftype_v4si
20465 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
20466 tree v4si_ftype_v2df
20467 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
20468 tree v4si_ftype_v2df_v2df
20469 = build_function_type_list (V4SI_type_node,
20470 V2DF_type_node, V2DF_type_node, NULL_TREE);
20471 tree v2si_ftype_v2df
20472 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
20473 tree v4sf_ftype_v2df
20474 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
20475 tree v2df_ftype_v2si
20476 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
20477 tree v2df_ftype_v4sf
20478 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
20479 tree int_ftype_v2df
20480 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
20481 tree int64_ftype_v2df
20482 = build_function_type_list (long_long_integer_type_node,
20483 V2DF_type_node, NULL_TREE);
20484 tree v2df_ftype_v2df_int
20485 = build_function_type_list (V2DF_type_node,
20486 V2DF_type_node, integer_type_node, NULL_TREE);
20487 tree v2df_ftype_v2df_int64
20488 = build_function_type_list (V2DF_type_node,
20489 V2DF_type_node, long_long_integer_type_node,
20491 tree v4sf_ftype_v4sf_v2df
20492 = build_function_type_list (V4SF_type_node,
20493 V4SF_type_node, V2DF_type_node, NULL_TREE);
20494 tree v2df_ftype_v2df_v4sf
20495 = build_function_type_list (V2DF_type_node,
20496 V2DF_type_node, V4SF_type_node, NULL_TREE);
20497 tree v2df_ftype_v2df_v2df_int
20498 = build_function_type_list (V2DF_type_node,
20499 V2DF_type_node, V2DF_type_node,
20502 tree v2df_ftype_v2df_pcdouble
20503 = build_function_type_list (V2DF_type_node,
20504 V2DF_type_node, pcdouble_type_node, NULL_TREE);
20505 tree void_ftype_pdouble_v2df
20506 = build_function_type_list (void_type_node,
20507 pdouble_type_node, V2DF_type_node, NULL_TREE);
20508 tree void_ftype_pint_int
20509 = build_function_type_list (void_type_node,
20510 pint_type_node, integer_type_node, NULL_TREE);
20511 tree void_ftype_v16qi_v16qi_pchar
20512 = build_function_type_list (void_type_node,
20513 V16QI_type_node, V16QI_type_node,
20514 pchar_type_node, NULL_TREE);
20515 tree v2df_ftype_pcdouble
20516 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
20517 tree v2df_ftype_v2df_v2df
20518 = build_function_type_list (V2DF_type_node,
20519 V2DF_type_node, V2DF_type_node, NULL_TREE);
20520 tree v16qi_ftype_v16qi_v16qi
20521 = build_function_type_list (V16QI_type_node,
20522 V16QI_type_node, V16QI_type_node, NULL_TREE);
20523 tree v8hi_ftype_v8hi_v8hi
20524 = build_function_type_list (V8HI_type_node,
20525 V8HI_type_node, V8HI_type_node, NULL_TREE);
20526 tree v4si_ftype_v4si_v4si
20527 = build_function_type_list (V4SI_type_node,
20528 V4SI_type_node, V4SI_type_node, NULL_TREE);
20529 tree v2di_ftype_v2di_v2di
20530 = build_function_type_list (V2DI_type_node,
20531 V2DI_type_node, V2DI_type_node, NULL_TREE);
20532 tree v2di_ftype_v2df_v2df
20533 = build_function_type_list (V2DI_type_node,
20534 V2DF_type_node, V2DF_type_node, NULL_TREE);
20535 tree v2df_ftype_v2df
20536 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
20537 tree v2di_ftype_v2di_int
20538 = build_function_type_list (V2DI_type_node,
20539 V2DI_type_node, integer_type_node, NULL_TREE);
20540 tree v2di_ftype_v2di_v2di_int
20541 = build_function_type_list (V2DI_type_node, V2DI_type_node,
20542 V2DI_type_node, integer_type_node, NULL_TREE);
20543 tree v4si_ftype_v4si_int
20544 = build_function_type_list (V4SI_type_node,
20545 V4SI_type_node, integer_type_node, NULL_TREE);
20546 tree v8hi_ftype_v8hi_int
20547 = build_function_type_list (V8HI_type_node,
20548 V8HI_type_node, integer_type_node, NULL_TREE);
20549 tree v4si_ftype_v8hi_v8hi
20550 = build_function_type_list (V4SI_type_node,
20551 V8HI_type_node, V8HI_type_node, NULL_TREE);
20552 tree v1di_ftype_v8qi_v8qi
20553 = build_function_type_list (V1DI_type_node,
20554 V8QI_type_node, V8QI_type_node, NULL_TREE);
20555 tree v1di_ftype_v2si_v2si
20556 = build_function_type_list (V1DI_type_node,
20557 V2SI_type_node, V2SI_type_node, NULL_TREE);
20558 tree v2di_ftype_v16qi_v16qi
20559 = build_function_type_list (V2DI_type_node,
20560 V16QI_type_node, V16QI_type_node, NULL_TREE);
20561 tree v2di_ftype_v4si_v4si
20562 = build_function_type_list (V2DI_type_node,
20563 V4SI_type_node, V4SI_type_node, NULL_TREE);
20564 tree int_ftype_v16qi
20565 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
20566 tree v16qi_ftype_pcchar
20567 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
20568 tree void_ftype_pchar_v16qi
20569 = build_function_type_list (void_type_node,
20570 pchar_type_node, V16QI_type_node, NULL_TREE);
20572 tree v2di_ftype_v2di_unsigned_unsigned
20573 = build_function_type_list (V2DI_type_node, V2DI_type_node,
20574 unsigned_type_node, unsigned_type_node,
20576 tree v2di_ftype_v2di_v2di_unsigned_unsigned
20577 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
20578 unsigned_type_node, unsigned_type_node,
20580 tree v2di_ftype_v2di_v16qi
20581 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
20583 tree v2df_ftype_v2df_v2df_v2df
20584 = build_function_type_list (V2DF_type_node,
20585 V2DF_type_node, V2DF_type_node,
20586 V2DF_type_node, NULL_TREE);
20587 tree v4sf_ftype_v4sf_v4sf_v4sf
20588 = build_function_type_list (V4SF_type_node,
20589 V4SF_type_node, V4SF_type_node,
20590 V4SF_type_node, NULL_TREE);
20591 tree v8hi_ftype_v16qi
20592 = build_function_type_list (V8HI_type_node, V16QI_type_node,
20594 tree v4si_ftype_v16qi
20595 = build_function_type_list (V4SI_type_node, V16QI_type_node,
20597 tree v2di_ftype_v16qi
20598 = build_function_type_list (V2DI_type_node, V16QI_type_node,
20600 tree v4si_ftype_v8hi
20601 = build_function_type_list (V4SI_type_node, V8HI_type_node,
20603 tree v2di_ftype_v8hi
20604 = build_function_type_list (V2DI_type_node, V8HI_type_node,
20606 tree v2di_ftype_v4si
20607 = build_function_type_list (V2DI_type_node, V4SI_type_node,
20609 tree v2di_ftype_pv2di
20610 = build_function_type_list (V2DI_type_node, pv2di_type_node,
20612 tree v16qi_ftype_v16qi_v16qi_int
20613 = build_function_type_list (V16QI_type_node, V16QI_type_node,
20614 V16QI_type_node, integer_type_node,
20616 tree v16qi_ftype_v16qi_v16qi_v16qi
20617 = build_function_type_list (V16QI_type_node, V16QI_type_node,
20618 V16QI_type_node, V16QI_type_node,
20620 tree v8hi_ftype_v8hi_v8hi_int
20621 = build_function_type_list (V8HI_type_node, V8HI_type_node,
20622 V8HI_type_node, integer_type_node,
20624 tree v4si_ftype_v4si_v4si_int
20625 = build_function_type_list (V4SI_type_node, V4SI_type_node,
20626 V4SI_type_node, integer_type_node,
20628 tree int_ftype_v2di_v2di
20629 = build_function_type_list (integer_type_node,
20630 V2DI_type_node, V2DI_type_node,
20632 tree int_ftype_v16qi_int_v16qi_int_int
20633 = build_function_type_list (integer_type_node,
20640 tree v16qi_ftype_v16qi_int_v16qi_int_int
20641 = build_function_type_list (V16QI_type_node,
20648 tree int_ftype_v16qi_v16qi_int
20649 = build_function_type_list (integer_type_node,
20655 /* SSE5 instructions */
20656 tree v2di_ftype_v2di_v2di_v2di
20657 = build_function_type_list (V2DI_type_node,
20663 tree v4si_ftype_v4si_v4si_v4si
20664 = build_function_type_list (V4SI_type_node,
20670 tree v4si_ftype_v4si_v4si_v2di
20671 = build_function_type_list (V4SI_type_node,
20677 tree v8hi_ftype_v8hi_v8hi_v8hi
20678 = build_function_type_list (V8HI_type_node,
20684 tree v8hi_ftype_v8hi_v8hi_v4si
20685 = build_function_type_list (V8HI_type_node,
20691 tree v2df_ftype_v2df_v2df_v16qi
20692 = build_function_type_list (V2DF_type_node,
20698 tree v4sf_ftype_v4sf_v4sf_v16qi
20699 = build_function_type_list (V4SF_type_node,
20705 tree v2di_ftype_v2di_si
20706 = build_function_type_list (V2DI_type_node,
20711 tree v4si_ftype_v4si_si
20712 = build_function_type_list (V4SI_type_node,
20717 tree v8hi_ftype_v8hi_si
20718 = build_function_type_list (V8HI_type_node,
20723 tree v16qi_ftype_v16qi_si
20724 = build_function_type_list (V16QI_type_node,
20728 tree v4sf_ftype_v4hi
20729 = build_function_type_list (V4SF_type_node,
20733 tree v4hi_ftype_v4sf
20734 = build_function_type_list (V4HI_type_node,
20738 tree v2di_ftype_v2di
20739 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
20741 tree v16qi_ftype_v8hi_v8hi
20742 = build_function_type_list (V16QI_type_node,
20743 V8HI_type_node, V8HI_type_node,
20745 tree v8hi_ftype_v4si_v4si
20746 = build_function_type_list (V8HI_type_node,
20747 V4SI_type_node, V4SI_type_node,
20749 tree v8hi_ftype_v16qi_v16qi
20750 = build_function_type_list (V8HI_type_node,
20751 V16QI_type_node, V16QI_type_node,
20753 tree v4hi_ftype_v8qi_v8qi
20754 = build_function_type_list (V4HI_type_node,
20755 V8QI_type_node, V8QI_type_node,
20757 tree unsigned_ftype_unsigned_uchar
20758 = build_function_type_list (unsigned_type_node,
20759 unsigned_type_node,
20760 unsigned_char_type_node,
20762 tree unsigned_ftype_unsigned_ushort
20763 = build_function_type_list (unsigned_type_node,
20764 unsigned_type_node,
20765 short_unsigned_type_node,
20767 tree unsigned_ftype_unsigned_unsigned
20768 = build_function_type_list (unsigned_type_node,
20769 unsigned_type_node,
20770 unsigned_type_node,
20772 tree uint64_ftype_uint64_uint64
20773 = build_function_type_list (long_long_unsigned_type_node,
20774 long_long_unsigned_type_node,
20775 long_long_unsigned_type_node,
20777 tree float_ftype_float
20778 = build_function_type_list (float_type_node,
20784 /* Add all special builtins with variable number of operands. */
20785 for (i = 0, d = bdesc_special_args;
20786 i < ARRAY_SIZE (bdesc_special_args);
20794 switch ((enum ix86_special_builtin_type) d->flag)
20796 case VOID_FTYPE_VOID:
20797 type = void_ftype_void;
20799 case V16QI_FTYPE_PCCHAR:
20800 type = v16qi_ftype_pcchar;
20802 case V4SF_FTYPE_PCFLOAT:
20803 type = v4sf_ftype_pcfloat;
20805 case V2DI_FTYPE_PV2DI:
20806 type = v2di_ftype_pv2di;
20808 case V2DF_FTYPE_PCDOUBLE:
20809 type = v2df_ftype_pcdouble;
20811 case V4SF_FTYPE_V4SF_PCV2SF:
20812 type = v4sf_ftype_v4sf_pcv2sf;
20814 case V2DF_FTYPE_V2DF_PCDOUBLE:
20815 type = v2df_ftype_v2df_pcdouble;
20817 case VOID_FTYPE_PV2SF_V4SF:
20818 type = void_ftype_pv2sf_v4sf;
20820 case VOID_FTYPE_PV2DI_V2DI:
20821 type = void_ftype_pv2di_v2di;
20823 case VOID_FTYPE_PCHAR_V16QI:
20824 type = void_ftype_pchar_v16qi;
20826 case VOID_FTYPE_PFLOAT_V4SF:
20827 type = void_ftype_pfloat_v4sf;
20829 case VOID_FTYPE_PDOUBLE_V2DF:
20830 type = void_ftype_pdouble_v2df;
20832 case VOID_FTYPE_PDI_DI:
20833 type = void_ftype_pdi_di;
20835 case VOID_FTYPE_PINT_INT:
20836 type = void_ftype_pint_int;
20839 gcc_unreachable ();
20842 def_builtin (d->mask, d->name, type, d->code);
20845 /* Add all builtins with variable number of operands. */
20846 for (i = 0, d = bdesc_args;
20847 i < ARRAY_SIZE (bdesc_args);
20855 switch ((enum ix86_builtin_type) d->flag)
20857 case FLOAT_FTYPE_FLOAT:
20858 type = float_ftype_float;
20860 case INT_FTYPE_V2DI_V2DI_PTEST:
20861 type = int_ftype_v2di_v2di;
20863 case INT64_FTYPE_V4SF:
20864 type = int64_ftype_v4sf;
20866 case INT64_FTYPE_V2DF:
20867 type = int64_ftype_v2df;
20869 case INT_FTYPE_V16QI:
20870 type = int_ftype_v16qi;
20872 case INT_FTYPE_V8QI:
20873 type = int_ftype_v8qi;
20875 case INT_FTYPE_V4SF:
20876 type = int_ftype_v4sf;
20878 case INT_FTYPE_V2DF:
20879 type = int_ftype_v2df;
20881 case V16QI_FTYPE_V16QI:
20882 type = v16qi_ftype_v16qi;
20884 case V8HI_FTYPE_V8HI:
20885 type = v8hi_ftype_v8hi;
20887 case V8HI_FTYPE_V16QI:
20888 type = v8hi_ftype_v16qi;
20890 case V8QI_FTYPE_V8QI:
20891 type = v8qi_ftype_v8qi;
20893 case V4SI_FTYPE_V4SI:
20894 type = v4si_ftype_v4si;
20896 case V4SI_FTYPE_V16QI:
20897 type = v4si_ftype_v16qi;
20899 case V4SI_FTYPE_V8HI:
20900 type = v4si_ftype_v8hi;
20902 case V4SI_FTYPE_V4SF:
20903 type = v4si_ftype_v4sf;
20905 case V4SI_FTYPE_V2DF:
20906 type = v4si_ftype_v2df;
20908 case V4HI_FTYPE_V4HI:
20909 type = v4hi_ftype_v4hi;
20911 case V4SF_FTYPE_V4SF:
20912 case V4SF_FTYPE_V4SF_VEC_MERGE:
20913 type = v4sf_ftype_v4sf;
20915 case V4SF_FTYPE_V4SI:
20916 type = v4sf_ftype_v4si;
20918 case V4SF_FTYPE_V2DF:
20919 type = v4sf_ftype_v2df;
20921 case V2DI_FTYPE_V2DI:
20922 type = v2di_ftype_v2di;
20924 case V2DI_FTYPE_V16QI:
20925 type = v2di_ftype_v16qi;
20927 case V2DI_FTYPE_V8HI:
20928 type = v2di_ftype_v8hi;
20930 case V2DI_FTYPE_V4SI:
20931 type = v2di_ftype_v4si;
20933 case V2SI_FTYPE_V2SI:
20934 type = v2si_ftype_v2si;
20936 case V2SI_FTYPE_V4SF:
20937 type = v2si_ftype_v4sf;
20939 case V2SI_FTYPE_V2DF:
20940 type = v2si_ftype_v2df;
20942 case V2SI_FTYPE_V2SF:
20943 type = v2si_ftype_v2sf;
20945 case V2DF_FTYPE_V4SF:
20946 type = v2df_ftype_v4sf;
20948 case V2DF_FTYPE_V2DF:
20949 case V2DF_FTYPE_V2DF_VEC_MERGE:
20950 type = v2df_ftype_v2df;
20952 case V2DF_FTYPE_V2SI:
20953 type = v2df_ftype_v2si;
20955 case V2DF_FTYPE_V4SI:
20956 type = v2df_ftype_v4si;
20958 case V2SF_FTYPE_V2SF:
20959 type = v2sf_ftype_v2sf;
20961 case V2SF_FTYPE_V2SI:
20962 type = v2sf_ftype_v2si;
20964 case V16QI_FTYPE_V16QI_V16QI:
20965 type = v16qi_ftype_v16qi_v16qi;
20967 case V16QI_FTYPE_V8HI_V8HI:
20968 type = v16qi_ftype_v8hi_v8hi;
20970 case V8QI_FTYPE_V8QI_V8QI:
20971 type = v8qi_ftype_v8qi_v8qi;
20973 case V8QI_FTYPE_V4HI_V4HI:
20974 type = v8qi_ftype_v4hi_v4hi;
20976 case V8HI_FTYPE_V8HI_V8HI:
20977 case V8HI_FTYPE_V8HI_V8HI_COUNT:
20978 type = v8hi_ftype_v8hi_v8hi;
20980 case V8HI_FTYPE_V16QI_V16QI:
20981 type = v8hi_ftype_v16qi_v16qi;
20983 case V8HI_FTYPE_V4SI_V4SI:
20984 type = v8hi_ftype_v4si_v4si;
20986 case V8HI_FTYPE_V8HI_SI_COUNT:
20987 type = v8hi_ftype_v8hi_int;
20989 case V4SI_FTYPE_V4SI_V4SI:
20990 case V4SI_FTYPE_V4SI_V4SI_COUNT:
20991 type = v4si_ftype_v4si_v4si;
20993 case V4SI_FTYPE_V8HI_V8HI:
20994 type = v4si_ftype_v8hi_v8hi;
20996 case V4SI_FTYPE_V4SF_V4SF:
20997 type = v4si_ftype_v4sf_v4sf;
20999 case V4SI_FTYPE_V2DF_V2DF:
21000 type = v4si_ftype_v2df_v2df;
21002 case V4SI_FTYPE_V4SI_SI_COUNT:
21003 type = v4si_ftype_v4si_int;
21005 case V4HI_FTYPE_V4HI_V4HI:
21006 case V4HI_FTYPE_V4HI_V4HI_COUNT:
21007 type = v4hi_ftype_v4hi_v4hi;
21009 case V4HI_FTYPE_V8QI_V8QI:
21010 type = v4hi_ftype_v8qi_v8qi;
21012 case V4HI_FTYPE_V2SI_V2SI:
21013 type = v4hi_ftype_v2si_v2si;
21015 case V4HI_FTYPE_V4HI_SI_COUNT:
21016 type = v4hi_ftype_v4hi_int;
21018 case V4SF_FTYPE_V4SF_V4SF:
21019 case V4SF_FTYPE_V4SF_V4SF_SWAP:
21020 type = v4sf_ftype_v4sf_v4sf;
21022 case V4SF_FTYPE_V4SF_V2SI:
21023 type = v4sf_ftype_v4sf_v2si;
21025 case V4SF_FTYPE_V4SF_V2DF:
21026 type = v4sf_ftype_v4sf_v2df;
21028 case V4SF_FTYPE_V4SF_DI:
21029 type = v4sf_ftype_v4sf_int64;
21031 case V4SF_FTYPE_V4SF_SI:
21032 type = v4sf_ftype_v4sf_int;
21034 case V2DI_FTYPE_V2DI_V2DI:
21035 case V2DI_FTYPE_V2DI_V2DI_COUNT:
21036 type = v2di_ftype_v2di_v2di;
21038 case V2DI_FTYPE_V16QI_V16QI:
21039 type = v2di_ftype_v16qi_v16qi;
21041 case V2DI_FTYPE_V4SI_V4SI:
21042 type = v2di_ftype_v4si_v4si;
21044 case V2DI_FTYPE_V2DI_V16QI:
21045 type = v2di_ftype_v2di_v16qi;
21047 case V2DI_FTYPE_V2DF_V2DF:
21048 type = v2di_ftype_v2df_v2df;
21050 case V2DI_FTYPE_V2DI_SI_COUNT:
21051 type = v2di_ftype_v2di_int;
21053 case V2SI_FTYPE_V2SI_V2SI:
21054 case V2SI_FTYPE_V2SI_V2SI_COUNT:
21055 type = v2si_ftype_v2si_v2si;
21057 case V2SI_FTYPE_V4HI_V4HI:
21058 type = v2si_ftype_v4hi_v4hi;
21060 case V2SI_FTYPE_V2SF_V2SF:
21061 type = v2si_ftype_v2sf_v2sf;
21063 case V2SI_FTYPE_V2SI_SI_COUNT:
21064 type = v2si_ftype_v2si_int;
21066 case V2DF_FTYPE_V2DF_V2DF:
21067 case V2DF_FTYPE_V2DF_V2DF_SWAP:
21068 type = v2df_ftype_v2df_v2df;
21070 case V2DF_FTYPE_V2DF_V4SF:
21071 type = v2df_ftype_v2df_v4sf;
21073 case V2DF_FTYPE_V2DF_DI:
21074 type = v2df_ftype_v2df_int64;
21076 case V2DF_FTYPE_V2DF_SI:
21077 type = v2df_ftype_v2df_int;
21079 case V2SF_FTYPE_V2SF_V2SF:
21080 type = v2sf_ftype_v2sf_v2sf;
21082 case V1DI_FTYPE_V1DI_V1DI:
21083 case V1DI_FTYPE_V1DI_V1DI_COUNT:
21084 type = v1di_ftype_v1di_v1di;
21086 case V1DI_FTYPE_V8QI_V8QI:
21087 type = v1di_ftype_v8qi_v8qi;
21089 case V1DI_FTYPE_V2SI_V2SI:
21090 type = v1di_ftype_v2si_v2si;
21092 case V1DI_FTYPE_V1DI_SI_COUNT:
21093 type = v1di_ftype_v1di_int;
21095 case UINT64_FTYPE_UINT64_UINT64:
21096 type = uint64_ftype_uint64_uint64;
21098 case UINT_FTYPE_UINT_UINT:
21099 type = unsigned_ftype_unsigned_unsigned;
21101 case UINT_FTYPE_UINT_USHORT:
21102 type = unsigned_ftype_unsigned_ushort;
21104 case UINT_FTYPE_UINT_UCHAR:
21105 type = unsigned_ftype_unsigned_uchar;
21107 case V8HI_FTYPE_V8HI_INT:
21108 type = v8hi_ftype_v8hi_int;
21110 case V4SI_FTYPE_V4SI_INT:
21111 type = v4si_ftype_v4si_int;
21113 case V4HI_FTYPE_V4HI_INT:
21114 type = v4hi_ftype_v4hi_int;
21116 case V4SF_FTYPE_V4SF_INT:
21117 type = v4sf_ftype_v4sf_int;
21119 case V2DI_FTYPE_V2DI_INT:
21120 case V2DI2TI_FTYPE_V2DI_INT:
21121 type = v2di_ftype_v2di_int;
21123 case V2DF_FTYPE_V2DF_INT:
21124 type = v2df_ftype_v2df_int;
21126 case V16QI_FTYPE_V16QI_V16QI_V16QI:
21127 type = v16qi_ftype_v16qi_v16qi_v16qi;
21129 case V4SF_FTYPE_V4SF_V4SF_V4SF:
21130 type = v4sf_ftype_v4sf_v4sf_v4sf;
21132 case V2DF_FTYPE_V2DF_V2DF_V2DF:
21133 type = v2df_ftype_v2df_v2df_v2df;
21135 case V16QI_FTYPE_V16QI_V16QI_INT:
21136 type = v16qi_ftype_v16qi_v16qi_int;
21138 case V8HI_FTYPE_V8HI_V8HI_INT:
21139 type = v8hi_ftype_v8hi_v8hi_int;
21141 case V4SI_FTYPE_V4SI_V4SI_INT:
21142 type = v4si_ftype_v4si_v4si_int;
21144 case V4SF_FTYPE_V4SF_V4SF_INT:
21145 type = v4sf_ftype_v4sf_v4sf_int;
21147 case V2DI_FTYPE_V2DI_V2DI_INT:
21148 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
21149 type = v2di_ftype_v2di_v2di_int;
21151 case V2DF_FTYPE_V2DF_V2DF_INT:
21152 type = v2df_ftype_v2df_v2df_int;
21154 case V2DI_FTYPE_V2DI_UINT_UINT:
21155 type = v2di_ftype_v2di_unsigned_unsigned;
21157 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
21158 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
21160 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
21161 type = v1di_ftype_v1di_v1di_int;
21164 gcc_unreachable ();
21167 def_builtin_const (d->mask, d->name, type, d->code);
21170 /* pcmpestr[im] insns. */
21171 for (i = 0, d = bdesc_pcmpestr;
21172 i < ARRAY_SIZE (bdesc_pcmpestr);
21175 if (d->code == IX86_BUILTIN_PCMPESTRM128)
21176 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
21178 ftype = int_ftype_v16qi_int_v16qi_int_int;
21179 def_builtin_const (d->mask, d->name, ftype, d->code);
21182 /* pcmpistr[im] insns. */
21183 for (i = 0, d = bdesc_pcmpistr;
21184 i < ARRAY_SIZE (bdesc_pcmpistr);
21187 if (d->code == IX86_BUILTIN_PCMPISTRM128)
21188 ftype = v16qi_ftype_v16qi_v16qi_int;
21190 ftype = int_ftype_v16qi_v16qi_int;
21191 def_builtin_const (d->mask, d->name, ftype, d->code);
21194 /* comi/ucomi insns. */
21195 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
21196 if (d->mask == OPTION_MASK_ISA_SSE2)
21197 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
21199 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
21202 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
21203 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
21205 /* SSE or 3DNow!A */
21206 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
21209 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
21211 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
21212 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
21215 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
21216 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
21219 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
21220 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
21221 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
21222 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
21223 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
21224 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
21227 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
21229 /* Access to the vec_init patterns. */
21230 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
21231 integer_type_node, NULL_TREE);
21232 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
21234 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
21235 short_integer_type_node,
21236 short_integer_type_node,
21237 short_integer_type_node, NULL_TREE);
21238 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
21240 ftype = build_function_type_list (V8QI_type_node, char_type_node,
21241 char_type_node, char_type_node,
21242 char_type_node, char_type_node,
21243 char_type_node, char_type_node,
21244 char_type_node, NULL_TREE);
21245 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
21247 /* Access to the vec_extract patterns. */
21248 ftype = build_function_type_list (double_type_node, V2DF_type_node,
21249 integer_type_node, NULL_TREE);
21250 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
21252 ftype = build_function_type_list (long_long_integer_type_node,
21253 V2DI_type_node, integer_type_node,
21255 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
21257 ftype = build_function_type_list (float_type_node, V4SF_type_node,
21258 integer_type_node, NULL_TREE);
21259 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
21261 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
21262 integer_type_node, NULL_TREE);
21263 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
21265 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
21266 integer_type_node, NULL_TREE);
21267 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
21269 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
21270 integer_type_node, NULL_TREE);
21271 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
21273 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
21274 integer_type_node, NULL_TREE);
21275 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
21277 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
21278 integer_type_node, NULL_TREE);
21279 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
21281 /* Access to the vec_set patterns. */
21282 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
21284 integer_type_node, NULL_TREE);
21285 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
21287 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
21289 integer_type_node, NULL_TREE);
21290 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
21292 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
21294 integer_type_node, NULL_TREE);
21295 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
21297 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
21299 integer_type_node, NULL_TREE);
21300 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
21302 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
21304 integer_type_node, NULL_TREE);
21305 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
21307 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
21309 integer_type_node, NULL_TREE);
21310 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
21312 /* Add SSE5 multi-arg argument instructions */
21313 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
21315 tree mtype = NULL_TREE;
21320 switch ((enum multi_arg_type)d->flag)
21322 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
21323 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
21324 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
21325 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
21326 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
21327 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
21328 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
21329 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
21330 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
21331 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
21332 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
21333 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
21334 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
21335 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
21336 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
21337 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
21338 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
21339 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
21340 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
21341 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
21342 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
21343 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
21344 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
21345 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
21346 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
21347 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
21348 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
21349 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
21350 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
21351 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
21352 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
21353 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
21354 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
21355 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
21356 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
21357 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
21358 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
21359 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
21360 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
21361 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
21362 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
21363 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
21364 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
21365 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
21366 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
21367 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
21368 case MULTI_ARG_UNKNOWN:
21370 gcc_unreachable ();
21374 def_builtin_const (d->mask, d->name, mtype, d->code);
21378 /* Internal method for ix86_init_builtins. */
21381 ix86_init_builtins_va_builtins_abi (void)
21383 tree ms_va_ref, sysv_va_ref;
21384 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
21385 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
21386 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
21387 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
21391 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
21392 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
21393 ms_va_ref = build_reference_type (ms_va_list_type_node);
21395 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
21398 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
21399 fnvoid_va_start_ms =
21400 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
21401 fnvoid_va_end_sysv =
21402 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
21403 fnvoid_va_start_sysv =
21404 build_varargs_function_type_list (void_type_node, sysv_va_ref,
21406 fnvoid_va_copy_ms =
21407 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
21409 fnvoid_va_copy_sysv =
21410 build_function_type_list (void_type_node, sysv_va_ref,
21411 sysv_va_ref, NULL_TREE);
21413 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
21414 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
21415 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
21416 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
21417 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
21418 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
21419 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
21420 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
21421 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
21422 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
21423 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
21424 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
21428 ix86_init_builtins (void)
21430 tree float128_type_node = make_node (REAL_TYPE);
21433 /* The __float80 type. */
21434 if (TYPE_MODE (long_double_type_node) == XFmode)
21435 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
21439 /* The __float80 type. */
21440 tree float80_type_node = make_node (REAL_TYPE);
21442 TYPE_PRECISION (float80_type_node) = 80;
21443 layout_type (float80_type_node);
21444 (*lang_hooks.types.register_builtin_type) (float80_type_node,
21448 /* The __float128 type. */
21449 TYPE_PRECISION (float128_type_node) = 128;
21450 layout_type (float128_type_node);
21451 (*lang_hooks.types.register_builtin_type) (float128_type_node,
21454 /* TFmode support builtins. */
21455 ftype = build_function_type (float128_type_node, void_list_node);
21456 decl = add_builtin_function ("__builtin_infq", ftype,
21457 IX86_BUILTIN_INFQ, BUILT_IN_MD,
21459 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
21461 /* We will expand them to normal call if SSE2 isn't available since
21462 they are used by libgcc. */
21463 ftype = build_function_type_list (float128_type_node,
21464 float128_type_node,
21466 decl = add_builtin_function ("__builtin_fabsq", ftype,
21467 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
21468 "__fabstf2", NULL_TREE);
21469 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
21470 TREE_READONLY (decl) = 1;
21472 ftype = build_function_type_list (float128_type_node,
21473 float128_type_node,
21474 float128_type_node,
21476 decl = add_builtin_function ("__builtin_copysignq", ftype,
21477 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
21478 "__copysigntf3", NULL_TREE);
21479 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
21480 TREE_READONLY (decl) = 1;
21482 ix86_init_mmx_sse_builtins ();
21484 ix86_init_builtins_va_builtins_abi ();
21487 /* Errors in the source file can cause expand_expr to return const0_rtx
21488 where we expect a vector. To avoid crashing, use one of the vector
21489 clear instructions. */
21491 safe_vector_operand (rtx x, enum machine_mode mode)
21493 if (x == const0_rtx)
21494 x = CONST0_RTX (mode);
21498 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
21501 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
21504 tree arg0 = CALL_EXPR_ARG (exp, 0);
21505 tree arg1 = CALL_EXPR_ARG (exp, 1);
21506 rtx op0 = expand_normal (arg0);
21507 rtx op1 = expand_normal (arg1);
21508 enum machine_mode tmode = insn_data[icode].operand[0].mode;
21509 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
21510 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
21512 if (VECTOR_MODE_P (mode0))
21513 op0 = safe_vector_operand (op0, mode0);
21514 if (VECTOR_MODE_P (mode1))
21515 op1 = safe_vector_operand (op1, mode1);
21517 if (optimize || !target
21518 || GET_MODE (target) != tmode
21519 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21520 target = gen_reg_rtx (tmode);
21522 if (GET_MODE (op1) == SImode && mode1 == TImode)
21524 rtx x = gen_reg_rtx (V4SImode);
21525 emit_insn (gen_sse2_loadd (x, op1));
21526 op1 = gen_lowpart (TImode, x);
21529 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
21530 op0 = copy_to_mode_reg (mode0, op0);
21531 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
21532 op1 = copy_to_mode_reg (mode1, op1);
21534 pat = GEN_FCN (icode) (target, op0, op1);
21543 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
21546 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
21547 enum multi_arg_type m_type,
21548 enum insn_code sub_code)
21553 bool comparison_p = false;
21555 bool last_arg_constant = false;
21556 int num_memory = 0;
21559 enum machine_mode mode;
21562 enum machine_mode tmode = insn_data[icode].operand[0].mode;
21566 case MULTI_ARG_3_SF:
21567 case MULTI_ARG_3_DF:
21568 case MULTI_ARG_3_DI:
21569 case MULTI_ARG_3_SI:
21570 case MULTI_ARG_3_SI_DI:
21571 case MULTI_ARG_3_HI:
21572 case MULTI_ARG_3_HI_SI:
21573 case MULTI_ARG_3_QI:
21574 case MULTI_ARG_3_PERMPS:
21575 case MULTI_ARG_3_PERMPD:
21579 case MULTI_ARG_2_SF:
21580 case MULTI_ARG_2_DF:
21581 case MULTI_ARG_2_DI:
21582 case MULTI_ARG_2_SI:
21583 case MULTI_ARG_2_HI:
21584 case MULTI_ARG_2_QI:
21588 case MULTI_ARG_2_DI_IMM:
21589 case MULTI_ARG_2_SI_IMM:
21590 case MULTI_ARG_2_HI_IMM:
21591 case MULTI_ARG_2_QI_IMM:
21593 last_arg_constant = true;
21596 case MULTI_ARG_1_SF:
21597 case MULTI_ARG_1_DF:
21598 case MULTI_ARG_1_DI:
21599 case MULTI_ARG_1_SI:
21600 case MULTI_ARG_1_HI:
21601 case MULTI_ARG_1_QI:
21602 case MULTI_ARG_1_SI_DI:
21603 case MULTI_ARG_1_HI_DI:
21604 case MULTI_ARG_1_HI_SI:
21605 case MULTI_ARG_1_QI_DI:
21606 case MULTI_ARG_1_QI_SI:
21607 case MULTI_ARG_1_QI_HI:
21608 case MULTI_ARG_1_PH2PS:
21609 case MULTI_ARG_1_PS2PH:
21613 case MULTI_ARG_2_SF_CMP:
21614 case MULTI_ARG_2_DF_CMP:
21615 case MULTI_ARG_2_DI_CMP:
21616 case MULTI_ARG_2_SI_CMP:
21617 case MULTI_ARG_2_HI_CMP:
21618 case MULTI_ARG_2_QI_CMP:
21620 comparison_p = true;
21623 case MULTI_ARG_2_SF_TF:
21624 case MULTI_ARG_2_DF_TF:
21625 case MULTI_ARG_2_DI_TF:
21626 case MULTI_ARG_2_SI_TF:
21627 case MULTI_ARG_2_HI_TF:
21628 case MULTI_ARG_2_QI_TF:
21633 case MULTI_ARG_UNKNOWN:
21635 gcc_unreachable ();
21638 if (optimize || !target
21639 || GET_MODE (target) != tmode
21640 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21641 target = gen_reg_rtx (tmode);
21643 gcc_assert (nargs <= 4);
21645 for (i = 0; i < nargs; i++)
21647 tree arg = CALL_EXPR_ARG (exp, i);
21648 rtx op = expand_normal (arg);
21649 int adjust = (comparison_p) ? 1 : 0;
21650 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
21652 if (last_arg_constant && i == nargs-1)
21654 if (GET_CODE (op) != CONST_INT)
21656 error ("last argument must be an immediate");
21657 return gen_reg_rtx (tmode);
21662 if (VECTOR_MODE_P (mode))
21663 op = safe_vector_operand (op, mode);
21665 /* If we aren't optimizing, only allow one memory operand to be
21667 if (memory_operand (op, mode))
21670 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
21673 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
21675 op = force_reg (mode, op);
21679 args[i].mode = mode;
21685 pat = GEN_FCN (icode) (target, args[0].op);
21690 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
21691 GEN_INT ((int)sub_code));
21692 else if (! comparison_p)
21693 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
21696 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
21700 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
21705 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
21709 gcc_unreachable ();
21719 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
21720 insns with vec_merge. */
21723 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
21727 tree arg0 = CALL_EXPR_ARG (exp, 0);
21728 rtx op1, op0 = expand_normal (arg0);
21729 enum machine_mode tmode = insn_data[icode].operand[0].mode;
21730 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
21732 if (optimize || !target
21733 || GET_MODE (target) != tmode
21734 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
21735 target = gen_reg_rtx (tmode);
21737 if (VECTOR_MODE_P (mode0))
21738 op0 = safe_vector_operand (op0, mode0);
21740 if ((optimize && !register_operand (op0, mode0))
21741 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
21742 op0 = copy_to_mode_reg (mode0, op0);
21745 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
21746 op1 = copy_to_mode_reg (mode0, op1);
21748 pat = GEN_FCN (icode) (target, op0, op1);
21755 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
21758 ix86_expand_sse_compare (const struct builtin_description *d,
21759 tree exp, rtx target, bool swap)
21762 tree arg0 = CALL_EXPR_ARG (exp, 0);
21763 tree arg1 = CALL_EXPR_ARG (exp, 1);
21764 rtx op0 = expand_normal (arg0);
21765 rtx op1 = expand_normal (arg1);
21767 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
21768 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
21769 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
21770 enum rtx_code comparison = d->comparison;
21772 if (VECTOR_MODE_P (mode0))
21773 op0 = safe_vector_operand (op0, mode0);
21774 if (VECTOR_MODE_P (mode1))
21775 op1 = safe_vector_operand (op1, mode1);
21777 /* Swap operands if we have a comparison that isn't available in
21781 rtx tmp = gen_reg_rtx (mode1);
21782 emit_move_insn (tmp, op1);
21787 if (optimize || !target
21788 || GET_MODE (target) != tmode
21789 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
21790 target = gen_reg_rtx (tmode);
21792 if ((optimize && !register_operand (op0, mode0))
21793 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
21794 op0 = copy_to_mode_reg (mode0, op0);
21795 if ((optimize && !register_operand (op1, mode1))
21796 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
21797 op1 = copy_to_mode_reg (mode1, op1);
21799 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
21800 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
21807 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
21810 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
21814 tree arg0 = CALL_EXPR_ARG (exp, 0);
21815 tree arg1 = CALL_EXPR_ARG (exp, 1);
21816 rtx op0 = expand_normal (arg0);
21817 rtx op1 = expand_normal (arg1);
21818 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
21819 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
21820 enum rtx_code comparison = d->comparison;
21822 if (VECTOR_MODE_P (mode0))
21823 op0 = safe_vector_operand (op0, mode0);
21824 if (VECTOR_MODE_P (mode1))
21825 op1 = safe_vector_operand (op1, mode1);
21827 /* Swap operands if we have a comparison that isn't available in
21829 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
21836 target = gen_reg_rtx (SImode);
21837 emit_move_insn (target, const0_rtx);
21838 target = gen_rtx_SUBREG (QImode, target, 0);
21840 if ((optimize && !register_operand (op0, mode0))
21841 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
21842 op0 = copy_to_mode_reg (mode0, op0);
21843 if ((optimize && !register_operand (op1, mode1))
21844 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
21845 op1 = copy_to_mode_reg (mode1, op1);
21847 pat = GEN_FCN (d->icode) (op0, op1);
21851 emit_insn (gen_rtx_SET (VOIDmode,
21852 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
21853 gen_rtx_fmt_ee (comparison, QImode,
21857 return SUBREG_REG (target);
21860 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
21863 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
21867 tree arg0 = CALL_EXPR_ARG (exp, 0);
21868 tree arg1 = CALL_EXPR_ARG (exp, 1);
21869 rtx op0 = expand_normal (arg0);
21870 rtx op1 = expand_normal (arg1);
21871 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
21872 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
21873 enum rtx_code comparison = d->comparison;
21875 if (VECTOR_MODE_P (mode0))
21876 op0 = safe_vector_operand (op0, mode0);
21877 if (VECTOR_MODE_P (mode1))
21878 op1 = safe_vector_operand (op1, mode1);
21880 target = gen_reg_rtx (SImode);
21881 emit_move_insn (target, const0_rtx);
21882 target = gen_rtx_SUBREG (QImode, target, 0);
21884 if ((optimize && !register_operand (op0, mode0))
21885 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
21886 op0 = copy_to_mode_reg (mode0, op0);
21887 if ((optimize && !register_operand (op1, mode1))
21888 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
21889 op1 = copy_to_mode_reg (mode1, op1);
21891 pat = GEN_FCN (d->icode) (op0, op1);
21895 emit_insn (gen_rtx_SET (VOIDmode,
21896 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
21897 gen_rtx_fmt_ee (comparison, QImode,
21901 return SUBREG_REG (target);
21904 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
21907 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
21908 tree exp, rtx target)
21911 tree arg0 = CALL_EXPR_ARG (exp, 0);
21912 tree arg1 = CALL_EXPR_ARG (exp, 1);
21913 tree arg2 = CALL_EXPR_ARG (exp, 2);
21914 tree arg3 = CALL_EXPR_ARG (exp, 3);
21915 tree arg4 = CALL_EXPR_ARG (exp, 4);
21916 rtx scratch0, scratch1;
21917 rtx op0 = expand_normal (arg0);
21918 rtx op1 = expand_normal (arg1);
21919 rtx op2 = expand_normal (arg2);
21920 rtx op3 = expand_normal (arg3);
21921 rtx op4 = expand_normal (arg4);
21922 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
21924 tmode0 = insn_data[d->icode].operand[0].mode;
21925 tmode1 = insn_data[d->icode].operand[1].mode;
21926 modev2 = insn_data[d->icode].operand[2].mode;
21927 modei3 = insn_data[d->icode].operand[3].mode;
21928 modev4 = insn_data[d->icode].operand[4].mode;
21929 modei5 = insn_data[d->icode].operand[5].mode;
21930 modeimm = insn_data[d->icode].operand[6].mode;
21932 if (VECTOR_MODE_P (modev2))
21933 op0 = safe_vector_operand (op0, modev2);
21934 if (VECTOR_MODE_P (modev4))
21935 op2 = safe_vector_operand (op2, modev4);
21937 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
21938 op0 = copy_to_mode_reg (modev2, op0);
21939 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
21940 op1 = copy_to_mode_reg (modei3, op1);
21941 if ((optimize && !register_operand (op2, modev4))
21942 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
21943 op2 = copy_to_mode_reg (modev4, op2);
21944 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
21945 op3 = copy_to_mode_reg (modei5, op3);
21947 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
21949 error ("the fifth argument must be a 8-bit immediate");
21953 if (d->code == IX86_BUILTIN_PCMPESTRI128)
21955 if (optimize || !target
21956 || GET_MODE (target) != tmode0
21957 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
21958 target = gen_reg_rtx (tmode0);
21960 scratch1 = gen_reg_rtx (tmode1);
21962 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
21964 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
21966 if (optimize || !target
21967 || GET_MODE (target) != tmode1
21968 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
21969 target = gen_reg_rtx (tmode1);
21971 scratch0 = gen_reg_rtx (tmode0);
21973 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
21977 gcc_assert (d->flag);
21979 scratch0 = gen_reg_rtx (tmode0);
21980 scratch1 = gen_reg_rtx (tmode1);
21982 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
21992 target = gen_reg_rtx (SImode);
21993 emit_move_insn (target, const0_rtx);
21994 target = gen_rtx_SUBREG (QImode, target, 0);
21997 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
21998 gen_rtx_fmt_ee (EQ, QImode,
21999 gen_rtx_REG ((enum machine_mode) d->flag,
22002 return SUBREG_REG (target);
22009 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
22012 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
22013 tree exp, rtx target)
22016 tree arg0 = CALL_EXPR_ARG (exp, 0);
22017 tree arg1 = CALL_EXPR_ARG (exp, 1);
22018 tree arg2 = CALL_EXPR_ARG (exp, 2);
22019 rtx scratch0, scratch1;
22020 rtx op0 = expand_normal (arg0);
22021 rtx op1 = expand_normal (arg1);
22022 rtx op2 = expand_normal (arg2);
22023 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
22025 tmode0 = insn_data[d->icode].operand[0].mode;
22026 tmode1 = insn_data[d->icode].operand[1].mode;
22027 modev2 = insn_data[d->icode].operand[2].mode;
22028 modev3 = insn_data[d->icode].operand[3].mode;
22029 modeimm = insn_data[d->icode].operand[4].mode;
22031 if (VECTOR_MODE_P (modev2))
22032 op0 = safe_vector_operand (op0, modev2);
22033 if (VECTOR_MODE_P (modev3))
22034 op1 = safe_vector_operand (op1, modev3);
22036 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
22037 op0 = copy_to_mode_reg (modev2, op0);
22038 if ((optimize && !register_operand (op1, modev3))
22039 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
22040 op1 = copy_to_mode_reg (modev3, op1);
22042 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
22044 error ("the third argument must be a 8-bit immediate");
22048 if (d->code == IX86_BUILTIN_PCMPISTRI128)
22050 if (optimize || !target
22051 || GET_MODE (target) != tmode0
22052 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
22053 target = gen_reg_rtx (tmode0);
22055 scratch1 = gen_reg_rtx (tmode1);
22057 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
22059 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
22061 if (optimize || !target
22062 || GET_MODE (target) != tmode1
22063 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
22064 target = gen_reg_rtx (tmode1);
22066 scratch0 = gen_reg_rtx (tmode0);
22068 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
22072 gcc_assert (d->flag);
22074 scratch0 = gen_reg_rtx (tmode0);
22075 scratch1 = gen_reg_rtx (tmode1);
22077 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
22087 target = gen_reg_rtx (SImode);
22088 emit_move_insn (target, const0_rtx);
22089 target = gen_rtx_SUBREG (QImode, target, 0);
22092 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
22093 gen_rtx_fmt_ee (EQ, QImode,
22094 gen_rtx_REG ((enum machine_mode) d->flag,
22097 return SUBREG_REG (target);
22103 /* Subroutine of ix86_expand_builtin to take care of insns with
22104 variable number of operands. */
22107 ix86_expand_args_builtin (const struct builtin_description *d,
22108 tree exp, rtx target)
22110 rtx pat, real_target;
22111 unsigned int i, nargs;
22112 unsigned int nargs_constant = 0;
22113 int num_memory = 0;
22117 enum machine_mode mode;
22119 bool last_arg_count = false;
22120 enum insn_code icode = d->icode;
22121 const struct insn_data *insn_p = &insn_data[icode];
22122 enum machine_mode tmode = insn_p->operand[0].mode;
22123 enum machine_mode rmode = VOIDmode;
22125 enum rtx_code comparison = d->comparison;
22127 switch ((enum ix86_builtin_type) d->flag)
22129 case INT_FTYPE_V2DI_V2DI_PTEST:
22130 return ix86_expand_sse_ptest (d, exp, target);
22131 case FLOAT128_FTYPE_FLOAT128:
22132 case FLOAT_FTYPE_FLOAT:
22133 case INT64_FTYPE_V4SF:
22134 case INT64_FTYPE_V2DF:
22135 case INT_FTYPE_V16QI:
22136 case INT_FTYPE_V8QI:
22137 case INT_FTYPE_V4SF:
22138 case INT_FTYPE_V2DF:
22139 case V16QI_FTYPE_V16QI:
22140 case V8HI_FTYPE_V8HI:
22141 case V8HI_FTYPE_V16QI:
22142 case V8QI_FTYPE_V8QI:
22143 case V4SI_FTYPE_V4SI:
22144 case V4SI_FTYPE_V16QI:
22145 case V4SI_FTYPE_V4SF:
22146 case V4SI_FTYPE_V8HI:
22147 case V4SI_FTYPE_V2DF:
22148 case V4HI_FTYPE_V4HI:
22149 case V4SF_FTYPE_V4SF:
22150 case V4SF_FTYPE_V4SI:
22151 case V4SF_FTYPE_V2DF:
22152 case V2DI_FTYPE_V2DI:
22153 case V2DI_FTYPE_V16QI:
22154 case V2DI_FTYPE_V8HI:
22155 case V2DI_FTYPE_V4SI:
22156 case V2DF_FTYPE_V2DF:
22157 case V2DF_FTYPE_V4SI:
22158 case V2DF_FTYPE_V4SF:
22159 case V2DF_FTYPE_V2SI:
22160 case V2SI_FTYPE_V2SI:
22161 case V2SI_FTYPE_V4SF:
22162 case V2SI_FTYPE_V2SF:
22163 case V2SI_FTYPE_V2DF:
22164 case V2SF_FTYPE_V2SF:
22165 case V2SF_FTYPE_V2SI:
22168 case V4SF_FTYPE_V4SF_VEC_MERGE:
22169 case V2DF_FTYPE_V2DF_VEC_MERGE:
22170 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
22171 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
22172 case V16QI_FTYPE_V16QI_V16QI:
22173 case V16QI_FTYPE_V8HI_V8HI:
22174 case V8QI_FTYPE_V8QI_V8QI:
22175 case V8QI_FTYPE_V4HI_V4HI:
22176 case V8HI_FTYPE_V8HI_V8HI:
22177 case V8HI_FTYPE_V16QI_V16QI:
22178 case V8HI_FTYPE_V4SI_V4SI:
22179 case V4SI_FTYPE_V4SI_V4SI:
22180 case V4SI_FTYPE_V8HI_V8HI:
22181 case V4SI_FTYPE_V4SF_V4SF:
22182 case V4SI_FTYPE_V2DF_V2DF:
22183 case V4HI_FTYPE_V4HI_V4HI:
22184 case V4HI_FTYPE_V8QI_V8QI:
22185 case V4HI_FTYPE_V2SI_V2SI:
22186 case V4SF_FTYPE_V4SF_V4SF:
22187 case V4SF_FTYPE_V4SF_V2SI:
22188 case V4SF_FTYPE_V4SF_V2DF:
22189 case V4SF_FTYPE_V4SF_DI:
22190 case V4SF_FTYPE_V4SF_SI:
22191 case V2DI_FTYPE_V2DI_V2DI:
22192 case V2DI_FTYPE_V16QI_V16QI:
22193 case V2DI_FTYPE_V4SI_V4SI:
22194 case V2DI_FTYPE_V2DI_V16QI:
22195 case V2DI_FTYPE_V2DF_V2DF:
22196 case V2SI_FTYPE_V2SI_V2SI:
22197 case V2SI_FTYPE_V4HI_V4HI:
22198 case V2SI_FTYPE_V2SF_V2SF:
22199 case V2DF_FTYPE_V2DF_V2DF:
22200 case V2DF_FTYPE_V2DF_V4SF:
22201 case V2DF_FTYPE_V2DF_DI:
22202 case V2DF_FTYPE_V2DF_SI:
22203 case V2SF_FTYPE_V2SF_V2SF:
22204 case V1DI_FTYPE_V1DI_V1DI:
22205 case V1DI_FTYPE_V8QI_V8QI:
22206 case V1DI_FTYPE_V2SI_V2SI:
22207 if (comparison == UNKNOWN)
22208 return ix86_expand_binop_builtin (icode, exp, target);
22211 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22212 case V2DF_FTYPE_V2DF_V2DF_SWAP:
22213 gcc_assert (comparison != UNKNOWN);
22217 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22218 case V8HI_FTYPE_V8HI_SI_COUNT:
22219 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22220 case V4SI_FTYPE_V4SI_SI_COUNT:
22221 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22222 case V4HI_FTYPE_V4HI_SI_COUNT:
22223 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22224 case V2DI_FTYPE_V2DI_SI_COUNT:
22225 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22226 case V2SI_FTYPE_V2SI_SI_COUNT:
22227 case V1DI_FTYPE_V1DI_V1DI_COUNT:
22228 case V1DI_FTYPE_V1DI_SI_COUNT:
22230 last_arg_count = true;
22232 case UINT64_FTYPE_UINT64_UINT64:
22233 case UINT_FTYPE_UINT_UINT:
22234 case UINT_FTYPE_UINT_USHORT:
22235 case UINT_FTYPE_UINT_UCHAR:
22238 case V2DI2TI_FTYPE_V2DI_INT:
22241 nargs_constant = 1;
22243 case V8HI_FTYPE_V8HI_INT:
22244 case V4SI_FTYPE_V4SI_INT:
22245 case V4HI_FTYPE_V4HI_INT:
22246 case V4SF_FTYPE_V4SF_INT:
22247 case V2DI_FTYPE_V2DI_INT:
22248 case V2DF_FTYPE_V2DF_INT:
22250 nargs_constant = 1;
22252 case V16QI_FTYPE_V16QI_V16QI_V16QI:
22253 case V4SF_FTYPE_V4SF_V4SF_V4SF:
22254 case V2DF_FTYPE_V2DF_V2DF_V2DF:
22257 case V16QI_FTYPE_V16QI_V16QI_INT:
22258 case V8HI_FTYPE_V8HI_V8HI_INT:
22259 case V4SI_FTYPE_V4SI_V4SI_INT:
22260 case V4SF_FTYPE_V4SF_V4SF_INT:
22261 case V2DI_FTYPE_V2DI_V2DI_INT:
22262 case V2DF_FTYPE_V2DF_V2DF_INT:
22264 nargs_constant = 1;
22266 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
22269 nargs_constant = 1;
22271 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
22274 nargs_constant = 1;
22276 case V2DI_FTYPE_V2DI_UINT_UINT:
22278 nargs_constant = 2;
22280 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
22282 nargs_constant = 2;
22285 gcc_unreachable ();
22288 gcc_assert (nargs <= ARRAY_SIZE (args));
22290 if (comparison != UNKNOWN)
22292 gcc_assert (nargs == 2);
22293 return ix86_expand_sse_compare (d, exp, target, swap);
22296 if (rmode == VOIDmode || rmode == tmode)
22300 || GET_MODE (target) != tmode
22301 || ! (*insn_p->operand[0].predicate) (target, tmode))
22302 target = gen_reg_rtx (tmode);
22303 real_target = target;
22307 target = gen_reg_rtx (rmode);
22308 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
22311 for (i = 0; i < nargs; i++)
22313 tree arg = CALL_EXPR_ARG (exp, i);
22314 rtx op = expand_normal (arg);
22315 enum machine_mode mode = insn_p->operand[i + 1].mode;
22316 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
22318 if (last_arg_count && (i + 1) == nargs)
22320 /* SIMD shift insns take either an 8-bit immediate or
22321 register as count. But builtin functions take int as
22322 count. If count doesn't match, we put it in register. */
22325 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
22326 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
22327 op = copy_to_reg (op);
22330 else if ((nargs - i) <= nargs_constant)
22335 case CODE_FOR_sse4_1_roundpd:
22336 case CODE_FOR_sse4_1_roundps:
22337 case CODE_FOR_sse4_1_roundsd:
22338 case CODE_FOR_sse4_1_roundss:
22339 case CODE_FOR_sse4_1_blendps:
22340 error ("the last argument must be a 4-bit immediate");
22343 case CODE_FOR_sse4_1_blendpd:
22344 error ("the last argument must be a 2-bit immediate");
22348 switch (nargs_constant)
22351 if ((nargs - i) == nargs_constant)
22353 error ("the next to last argument must be an 8-bit immediate");
22357 error ("the last argument must be an 8-bit immediate");
22360 gcc_unreachable ();
22367 if (VECTOR_MODE_P (mode))
22368 op = safe_vector_operand (op, mode);
22370 /* If we aren't optimizing, only allow one memory operand to
22372 if (memory_operand (op, mode))
22375 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
22377 if (optimize || !match || num_memory > 1)
22378 op = copy_to_mode_reg (mode, op);
22382 op = copy_to_reg (op);
22383 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
22388 args[i].mode = mode;
22394 pat = GEN_FCN (icode) (real_target, args[0].op);
22397 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
22400 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
22404 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
22405 args[2].op, args[3].op);
22408 gcc_unreachable ();
22418 /* Subroutine of ix86_expand_builtin to take care of special insns
22419 with variable number of operands. */
22422 ix86_expand_special_args_builtin (const struct builtin_description *d,
22423 tree exp, rtx target)
22427 unsigned int i, nargs, arg_adjust, memory;
22431 enum machine_mode mode;
22433 enum insn_code icode = d->icode;
22434 bool last_arg_constant = false;
22435 const struct insn_data *insn_p = &insn_data[icode];
22436 enum machine_mode tmode = insn_p->operand[0].mode;
22437 enum { load, store } klass;
22439 switch ((enum ix86_special_builtin_type) d->flag)
22441 case VOID_FTYPE_VOID:
22442 emit_insn (GEN_FCN (icode) (target));
22444 case V2DI_FTYPE_PV2DI:
22445 case V16QI_FTYPE_PCCHAR:
22446 case V4SF_FTYPE_PCFLOAT:
22447 case V2DF_FTYPE_PCDOUBLE:
22452 case VOID_FTYPE_PV2SF_V4SF:
22453 case VOID_FTYPE_PV2DI_V2DI:
22454 case VOID_FTYPE_PCHAR_V16QI:
22455 case VOID_FTYPE_PFLOAT_V4SF:
22456 case VOID_FTYPE_PDOUBLE_V2DF:
22457 case VOID_FTYPE_PDI_DI:
22458 case VOID_FTYPE_PINT_INT:
22461 /* Reserve memory operand for target. */
22462 memory = ARRAY_SIZE (args);
22464 case V4SF_FTYPE_V4SF_PCV2SF:
22465 case V2DF_FTYPE_V2DF_PCDOUBLE:
22471 gcc_unreachable ();
22474 gcc_assert (nargs <= ARRAY_SIZE (args));
22476 if (klass == store)
22478 arg = CALL_EXPR_ARG (exp, 0);
22479 op = expand_normal (arg);
22480 gcc_assert (target == 0);
22481 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
22489 || GET_MODE (target) != tmode
22490 || ! (*insn_p->operand[0].predicate) (target, tmode))
22491 target = gen_reg_rtx (tmode);
22494 for (i = 0; i < nargs; i++)
22496 enum machine_mode mode = insn_p->operand[i + 1].mode;
22499 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
22500 op = expand_normal (arg);
22501 match = (*insn_p->operand[i + 1].predicate) (op, mode);
22503 if (last_arg_constant && (i + 1) == nargs)
22509 error ("the last argument must be an 8-bit immediate");
22517 /* This must be the memory operand. */
22518 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
22519 gcc_assert (GET_MODE (op) == mode
22520 || GET_MODE (op) == VOIDmode);
22524 /* This must be register. */
22525 if (VECTOR_MODE_P (mode))
22526 op = safe_vector_operand (op, mode);
22528 gcc_assert (GET_MODE (op) == mode
22529 || GET_MODE (op) == VOIDmode);
22530 op = copy_to_mode_reg (mode, op);
22535 args[i].mode = mode;
22541 pat = GEN_FCN (icode) (target, args[0].op);
22544 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
22547 gcc_unreachable ();
22553 return klass == store ? 0 : target;
22556 /* Return the integer constant in ARG. Constrain it to be in the range
22557 of the subparts of VEC_TYPE; issue an error if not. */
22560 get_element_number (tree vec_type, tree arg)
22562 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
22564 if (!host_integerp (arg, 1)
22565 || (elt = tree_low_cst (arg, 1), elt > max))
22567 error ("selector must be an integer constant in the range 0..%wi", max);
22574 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
22575 ix86_expand_vector_init. We DO have language-level syntax for this, in
22576 the form of (type){ init-list }. Except that since we can't place emms
22577 instructions from inside the compiler, we can't allow the use of MMX
22578 registers unless the user explicitly asks for it. So we do *not* define
22579 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
22580 we have builtins invoked by mmintrin.h that gives us license to emit
22581 these sorts of instructions. */
22584 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
22586 enum machine_mode tmode = TYPE_MODE (type);
22587 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
22588 int i, n_elt = GET_MODE_NUNITS (tmode);
22589 rtvec v = rtvec_alloc (n_elt);
22591 gcc_assert (VECTOR_MODE_P (tmode));
22592 gcc_assert (call_expr_nargs (exp) == n_elt);
22594 for (i = 0; i < n_elt; ++i)
22596 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
22597 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
22600 if (!target || !register_operand (target, tmode))
22601 target = gen_reg_rtx (tmode);
22603 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
22607 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
22608 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
22609 had a language-level syntax for referencing vector elements. */
22612 ix86_expand_vec_ext_builtin (tree exp, rtx target)
22614 enum machine_mode tmode, mode0;
22619 arg0 = CALL_EXPR_ARG (exp, 0);
22620 arg1 = CALL_EXPR_ARG (exp, 1);
22622 op0 = expand_normal (arg0);
22623 elt = get_element_number (TREE_TYPE (arg0), arg1);
22625 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
22626 mode0 = TYPE_MODE (TREE_TYPE (arg0));
22627 gcc_assert (VECTOR_MODE_P (mode0));
22629 op0 = force_reg (mode0, op0);
22631 if (optimize || !target || !register_operand (target, tmode))
22632 target = gen_reg_rtx (tmode);
22634 ix86_expand_vector_extract (true, target, op0, elt);
22639 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
22640 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
22641 a language-level syntax for referencing vector elements. */
22644 ix86_expand_vec_set_builtin (tree exp)
22646 enum machine_mode tmode, mode1;
22647 tree arg0, arg1, arg2;
22649 rtx op0, op1, target;
22651 arg0 = CALL_EXPR_ARG (exp, 0);
22652 arg1 = CALL_EXPR_ARG (exp, 1);
22653 arg2 = CALL_EXPR_ARG (exp, 2);
22655 tmode = TYPE_MODE (TREE_TYPE (arg0));
22656 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
22657 gcc_assert (VECTOR_MODE_P (tmode));
22659 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
22660 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
22661 elt = get_element_number (TREE_TYPE (arg0), arg2);
22663 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
22664 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
22666 op0 = force_reg (tmode, op0);
22667 op1 = force_reg (mode1, op1);
22669 /* OP0 is the source of these builtin functions and shouldn't be
22670 modified. Create a copy, use it and return it as target. */
22671 target = gen_reg_rtx (tmode);
22672 emit_move_insn (target, op0);
22673 ix86_expand_vector_set (true, target, op1, elt);
22678 /* Expand an expression EXP that calls a built-in function,
22679 with result going to TARGET if that's convenient
22680 (and in mode MODE if that's convenient).
22681 SUBTARGET may be used as the target for computing one of EXP's operands.
22682 IGNORE is nonzero if the value is to be ignored. */
22685 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
22686 enum machine_mode mode ATTRIBUTE_UNUSED,
22687 int ignore ATTRIBUTE_UNUSED)
22689 const struct builtin_description *d;
22691 enum insn_code icode;
22692 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
22693 tree arg0, arg1, arg2;
22694 rtx op0, op1, op2, pat;
22695 enum machine_mode mode0, mode1, mode2;
22696 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
22698 /* Determine whether the builtin function is available under the current ISA.
22699 Originally the builtin was not created if it wasn't applicable to the
22700 current ISA based on the command line switches. With function specific
22701 options, we need to check in the context of the function making the call
22702 whether it is supported. */
22703 if (ix86_builtins_isa[fcode]
22704 && !(ix86_builtins_isa[fcode] & ix86_isa_flags))
22706 char *opts = ix86_target_string (ix86_builtins_isa[fcode], 0, NULL,
22707 NULL, NULL, false);
22710 error ("%qE needs unknown isa option", fndecl);
22713 gcc_assert (opts != NULL);
22714 error ("%qE needs isa option %s", fndecl, opts);
22722 case IX86_BUILTIN_MASKMOVQ:
22723 case IX86_BUILTIN_MASKMOVDQU:
22724 icode = (fcode == IX86_BUILTIN_MASKMOVQ
22725 ? CODE_FOR_mmx_maskmovq
22726 : CODE_FOR_sse2_maskmovdqu);
22727 /* Note the arg order is different from the operand order. */
22728 arg1 = CALL_EXPR_ARG (exp, 0);
22729 arg2 = CALL_EXPR_ARG (exp, 1);
22730 arg0 = CALL_EXPR_ARG (exp, 2);
22731 op0 = expand_normal (arg0);
22732 op1 = expand_normal (arg1);
22733 op2 = expand_normal (arg2);
22734 mode0 = insn_data[icode].operand[0].mode;
22735 mode1 = insn_data[icode].operand[1].mode;
22736 mode2 = insn_data[icode].operand[2].mode;
22738 op0 = force_reg (Pmode, op0);
22739 op0 = gen_rtx_MEM (mode1, op0);
22741 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
22742 op0 = copy_to_mode_reg (mode0, op0);
22743 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
22744 op1 = copy_to_mode_reg (mode1, op1);
22745 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
22746 op2 = copy_to_mode_reg (mode2, op2);
22747 pat = GEN_FCN (icode) (op0, op1, op2);
22753 case IX86_BUILTIN_LDMXCSR:
22754 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
22755 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
22756 emit_move_insn (target, op0);
22757 emit_insn (gen_sse_ldmxcsr (target));
22760 case IX86_BUILTIN_STMXCSR:
22761 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
22762 emit_insn (gen_sse_stmxcsr (target));
22763 return copy_to_mode_reg (SImode, target);
22765 case IX86_BUILTIN_CLFLUSH:
22766 arg0 = CALL_EXPR_ARG (exp, 0);
22767 op0 = expand_normal (arg0);
22768 icode = CODE_FOR_sse2_clflush;
22769 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
22770 op0 = copy_to_mode_reg (Pmode, op0);
22772 emit_insn (gen_sse2_clflush (op0));
22775 case IX86_BUILTIN_MONITOR:
22776 arg0 = CALL_EXPR_ARG (exp, 0);
22777 arg1 = CALL_EXPR_ARG (exp, 1);
22778 arg2 = CALL_EXPR_ARG (exp, 2);
22779 op0 = expand_normal (arg0);
22780 op1 = expand_normal (arg1);
22781 op2 = expand_normal (arg2);
22783 op0 = copy_to_mode_reg (Pmode, op0);
22785 op1 = copy_to_mode_reg (SImode, op1);
22787 op2 = copy_to_mode_reg (SImode, op2);
22788 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
22791 case IX86_BUILTIN_MWAIT:
22792 arg0 = CALL_EXPR_ARG (exp, 0);
22793 arg1 = CALL_EXPR_ARG (exp, 1);
22794 op0 = expand_normal (arg0);
22795 op1 = expand_normal (arg1);
22797 op0 = copy_to_mode_reg (SImode, op0);
22799 op1 = copy_to_mode_reg (SImode, op1);
22800 emit_insn (gen_sse3_mwait (op0, op1));
22803 case IX86_BUILTIN_VEC_INIT_V2SI:
22804 case IX86_BUILTIN_VEC_INIT_V4HI:
22805 case IX86_BUILTIN_VEC_INIT_V8QI:
22806 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
22808 case IX86_BUILTIN_VEC_EXT_V2DF:
22809 case IX86_BUILTIN_VEC_EXT_V2DI:
22810 case IX86_BUILTIN_VEC_EXT_V4SF:
22811 case IX86_BUILTIN_VEC_EXT_V4SI:
22812 case IX86_BUILTIN_VEC_EXT_V8HI:
22813 case IX86_BUILTIN_VEC_EXT_V2SI:
22814 case IX86_BUILTIN_VEC_EXT_V4HI:
22815 case IX86_BUILTIN_VEC_EXT_V16QI:
22816 return ix86_expand_vec_ext_builtin (exp, target);
22818 case IX86_BUILTIN_VEC_SET_V2DI:
22819 case IX86_BUILTIN_VEC_SET_V4SF:
22820 case IX86_BUILTIN_VEC_SET_V4SI:
22821 case IX86_BUILTIN_VEC_SET_V8HI:
22822 case IX86_BUILTIN_VEC_SET_V4HI:
22823 case IX86_BUILTIN_VEC_SET_V16QI:
22824 return ix86_expand_vec_set_builtin (exp);
22826 case IX86_BUILTIN_INFQ:
22828 REAL_VALUE_TYPE inf;
22832 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
22834 tmp = validize_mem (force_const_mem (mode, tmp));
22837 target = gen_reg_rtx (mode);
22839 emit_move_insn (target, tmp);
22847 for (i = 0, d = bdesc_special_args;
22848 i < ARRAY_SIZE (bdesc_special_args);
22850 if (d->code == fcode)
22851 return ix86_expand_special_args_builtin (d, exp, target);
22853 for (i = 0, d = bdesc_args;
22854 i < ARRAY_SIZE (bdesc_args);
22856 if (d->code == fcode)
22859 case IX86_BUILTIN_FABSQ:
22860 case IX86_BUILTIN_COPYSIGNQ:
22862 /* Emit a normal call if SSE2 isn't available. */
22863 return expand_call (exp, target, ignore);
22865 return ix86_expand_args_builtin (d, exp, target);
22868 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
22869 if (d->code == fcode)
22870 return ix86_expand_sse_comi (d, exp, target);
22872 for (i = 0, d = bdesc_pcmpestr;
22873 i < ARRAY_SIZE (bdesc_pcmpestr);
22875 if (d->code == fcode)
22876 return ix86_expand_sse_pcmpestr (d, exp, target);
22878 for (i = 0, d = bdesc_pcmpistr;
22879 i < ARRAY_SIZE (bdesc_pcmpistr);
22881 if (d->code == fcode)
22882 return ix86_expand_sse_pcmpistr (d, exp, target);
22884 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
22885 if (d->code == fcode)
22886 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
22887 (enum multi_arg_type)d->flag,
22890 gcc_unreachable ();
22893 /* Returns a function decl for a vectorized version of the builtin function
22894 with builtin function code FN and the result vector type TYPE, or NULL_TREE
22895 if it is not available. */
22898 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
22901 enum machine_mode in_mode, out_mode;
22904 if (TREE_CODE (type_out) != VECTOR_TYPE
22905 || TREE_CODE (type_in) != VECTOR_TYPE)
22908 out_mode = TYPE_MODE (TREE_TYPE (type_out));
22909 out_n = TYPE_VECTOR_SUBPARTS (type_out);
22910 in_mode = TYPE_MODE (TREE_TYPE (type_in));
22911 in_n = TYPE_VECTOR_SUBPARTS (type_in);
22915 case BUILT_IN_SQRT:
22916 if (out_mode == DFmode && out_n == 2
22917 && in_mode == DFmode && in_n == 2)
22918 return ix86_builtins[IX86_BUILTIN_SQRTPD];
22921 case BUILT_IN_SQRTF:
22922 if (out_mode == SFmode && out_n == 4
22923 && in_mode == SFmode && in_n == 4)
22924 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
22927 case BUILT_IN_LRINT:
22928 if (out_mode == SImode && out_n == 4
22929 && in_mode == DFmode && in_n == 2)
22930 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
22933 case BUILT_IN_LRINTF:
22934 if (out_mode == SImode && out_n == 4
22935 && in_mode == SFmode && in_n == 4)
22936 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
22943 /* Dispatch to a handler for a vectorization library. */
22944 if (ix86_veclib_handler)
22945 return (*ix86_veclib_handler)(fn, type_out, type_in);
22950 /* Handler for an SVML-style interface to
22951 a library with vectorized intrinsics. */
22954 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
22957 tree fntype, new_fndecl, args;
22960 enum machine_mode el_mode, in_mode;
22963 /* The SVML is suitable for unsafe math only. */
22964 if (!flag_unsafe_math_optimizations)
22967 el_mode = TYPE_MODE (TREE_TYPE (type_out));
22968 n = TYPE_VECTOR_SUBPARTS (type_out);
22969 in_mode = TYPE_MODE (TREE_TYPE (type_in));
22970 in_n = TYPE_VECTOR_SUBPARTS (type_in);
22971 if (el_mode != in_mode
22979 case BUILT_IN_LOG10:
22981 case BUILT_IN_TANH:
22983 case BUILT_IN_ATAN:
22984 case BUILT_IN_ATAN2:
22985 case BUILT_IN_ATANH:
22986 case BUILT_IN_CBRT:
22987 case BUILT_IN_SINH:
22989 case BUILT_IN_ASINH:
22990 case BUILT_IN_ASIN:
22991 case BUILT_IN_COSH:
22993 case BUILT_IN_ACOSH:
22994 case BUILT_IN_ACOS:
22995 if (el_mode != DFmode || n != 2)
22999 case BUILT_IN_EXPF:
23000 case BUILT_IN_LOGF:
23001 case BUILT_IN_LOG10F:
23002 case BUILT_IN_POWF:
23003 case BUILT_IN_TANHF:
23004 case BUILT_IN_TANF:
23005 case BUILT_IN_ATANF:
23006 case BUILT_IN_ATAN2F:
23007 case BUILT_IN_ATANHF:
23008 case BUILT_IN_CBRTF:
23009 case BUILT_IN_SINHF:
23010 case BUILT_IN_SINF:
23011 case BUILT_IN_ASINHF:
23012 case BUILT_IN_ASINF:
23013 case BUILT_IN_COSHF:
23014 case BUILT_IN_COSF:
23015 case BUILT_IN_ACOSHF:
23016 case BUILT_IN_ACOSF:
23017 if (el_mode != SFmode || n != 4)
23025 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
23027 if (fn == BUILT_IN_LOGF)
23028 strcpy (name, "vmlsLn4");
23029 else if (fn == BUILT_IN_LOG)
23030 strcpy (name, "vmldLn2");
23033 sprintf (name, "vmls%s", bname+10);
23034 name[strlen (name)-1] = '4';
23037 sprintf (name, "vmld%s2", bname+10);
23039 /* Convert to uppercase. */
23043 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
23044 args = TREE_CHAIN (args))
23048 fntype = build_function_type_list (type_out, type_in, NULL);
23050 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
23052 /* Build a function declaration for the vectorized function. */
23053 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
23054 TREE_PUBLIC (new_fndecl) = 1;
23055 DECL_EXTERNAL (new_fndecl) = 1;
23056 DECL_IS_NOVOPS (new_fndecl) = 1;
23057 TREE_READONLY (new_fndecl) = 1;
23062 /* Handler for an ACML-style interface to
23063 a library with vectorized intrinsics. */
23066 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
23068 char name[20] = "__vr.._";
23069 tree fntype, new_fndecl, args;
23072 enum machine_mode el_mode, in_mode;
23075 /* The ACML is 64bits only and suitable for unsafe math only as
23076 it does not correctly support parts of IEEE with the required
23077 precision such as denormals. */
23079 || !flag_unsafe_math_optimizations)
23082 el_mode = TYPE_MODE (TREE_TYPE (type_out));
23083 n = TYPE_VECTOR_SUBPARTS (type_out);
23084 in_mode = TYPE_MODE (TREE_TYPE (type_in));
23085 in_n = TYPE_VECTOR_SUBPARTS (type_in);
23086 if (el_mode != in_mode
23096 case BUILT_IN_LOG2:
23097 case BUILT_IN_LOG10:
23100 if (el_mode != DFmode
23105 case BUILT_IN_SINF:
23106 case BUILT_IN_COSF:
23107 case BUILT_IN_EXPF:
23108 case BUILT_IN_POWF:
23109 case BUILT_IN_LOGF:
23110 case BUILT_IN_LOG2F:
23111 case BUILT_IN_LOG10F:
23114 if (el_mode != SFmode
23123 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
23124 sprintf (name + 7, "%s", bname+10);
23127 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
23128 args = TREE_CHAIN (args))
23132 fntype = build_function_type_list (type_out, type_in, NULL);
23134 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
23136 /* Build a function declaration for the vectorized function. */
23137 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
23138 TREE_PUBLIC (new_fndecl) = 1;
23139 DECL_EXTERNAL (new_fndecl) = 1;
23140 DECL_IS_NOVOPS (new_fndecl) = 1;
23141 TREE_READONLY (new_fndecl) = 1;
23147 /* Returns a decl of a function that implements conversion of the
23148 input vector of type TYPE, or NULL_TREE if it is not available. */
23151 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
23153 if (TREE_CODE (type) != VECTOR_TYPE)
23159 switch (TYPE_MODE (type))
23162 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
23167 case FIX_TRUNC_EXPR:
23168 switch (TYPE_MODE (type))
23171 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
23181 /* Returns a code for a target-specific builtin that implements
23182 reciprocal of the function, or NULL_TREE if not available. */
23185 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
23186 bool sqrt ATTRIBUTE_UNUSED)
23188 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
23189 && flag_finite_math_only && !flag_trapping_math
23190 && flag_unsafe_math_optimizations))
23194 /* Machine dependent builtins. */
23197 /* Vectorized version of sqrt to rsqrt conversion. */
23198 case IX86_BUILTIN_SQRTPS_NR:
23199 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
23205 /* Normal builtins. */
23208 /* Sqrt to rsqrt conversion. */
23209 case BUILT_IN_SQRTF:
23210 return ix86_builtins[IX86_BUILTIN_RSQRTF];
23217 /* Store OPERAND to the memory after reload is completed. This means
23218 that we can't easily use assign_stack_local. */
23220 ix86_force_to_memory (enum machine_mode mode, rtx operand)
23224 gcc_assert (reload_completed);
23225 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
23227 result = gen_rtx_MEM (mode,
23228 gen_rtx_PLUS (Pmode,
23230 GEN_INT (-RED_ZONE_SIZE)));
23231 emit_move_insn (result, operand);
23233 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
23239 operand = gen_lowpart (DImode, operand);
23243 gen_rtx_SET (VOIDmode,
23244 gen_rtx_MEM (DImode,
23245 gen_rtx_PRE_DEC (DImode,
23246 stack_pointer_rtx)),
23250 gcc_unreachable ();
23252 result = gen_rtx_MEM (mode, stack_pointer_rtx);
23261 split_di (&operand, 1, operands, operands + 1);
23263 gen_rtx_SET (VOIDmode,
23264 gen_rtx_MEM (SImode,
23265 gen_rtx_PRE_DEC (Pmode,
23266 stack_pointer_rtx)),
23269 gen_rtx_SET (VOIDmode,
23270 gen_rtx_MEM (SImode,
23271 gen_rtx_PRE_DEC (Pmode,
23272 stack_pointer_rtx)),
23277 /* Store HImodes as SImodes. */
23278 operand = gen_lowpart (SImode, operand);
23282 gen_rtx_SET (VOIDmode,
23283 gen_rtx_MEM (GET_MODE (operand),
23284 gen_rtx_PRE_DEC (SImode,
23285 stack_pointer_rtx)),
23289 gcc_unreachable ();
23291 result = gen_rtx_MEM (mode, stack_pointer_rtx);
23296 /* Free operand from the memory. */
23298 ix86_free_from_memory (enum machine_mode mode)
23300 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
23304 if (mode == DImode || TARGET_64BIT)
23308 /* Use LEA to deallocate stack space. In peephole2 it will be converted
23309 to pop or add instruction if registers are available. */
23310 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
23311 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
23316 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
23317 QImode must go into class Q_REGS.
23318 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
23319 movdf to do mem-to-mem moves through integer regs. */
23321 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
23323 enum machine_mode mode = GET_MODE (x);
23325 /* We're only allowed to return a subclass of CLASS. Many of the
23326 following checks fail for NO_REGS, so eliminate that early. */
23327 if (regclass == NO_REGS)
23330 /* All classes can load zeros. */
23331 if (x == CONST0_RTX (mode))
23334 /* Force constants into memory if we are loading a (nonzero) constant into
23335 an MMX or SSE register. This is because there are no MMX/SSE instructions
23336 to load from a constant. */
23338 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
23341 /* Prefer SSE regs only, if we can use them for math. */
23342 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
23343 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
23345 /* Floating-point constants need more complex checks. */
23346 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
23348 /* General regs can load everything. */
23349 if (reg_class_subset_p (regclass, GENERAL_REGS))
23352 /* Floats can load 0 and 1 plus some others. Note that we eliminated
23353 zero above. We only want to wind up preferring 80387 registers if
23354 we plan on doing computation with them. */
23356 && standard_80387_constant_p (x))
23358 /* Limit class to non-sse. */
23359 if (regclass == FLOAT_SSE_REGS)
23361 if (regclass == FP_TOP_SSE_REGS)
23363 if (regclass == FP_SECOND_SSE_REGS)
23364 return FP_SECOND_REG;
23365 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
23372 /* Generally when we see PLUS here, it's the function invariant
23373 (plus soft-fp const_int). Which can only be computed into general
23375 if (GET_CODE (x) == PLUS)
23376 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
23378 /* QImode constants are easy to load, but non-constant QImode data
23379 must go into Q_REGS. */
23380 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
23382 if (reg_class_subset_p (regclass, Q_REGS))
23384 if (reg_class_subset_p (Q_REGS, regclass))
23392 /* Discourage putting floating-point values in SSE registers unless
23393 SSE math is being used, and likewise for the 387 registers. */
23395 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
23397 enum machine_mode mode = GET_MODE (x);
23399 /* Restrict the output reload class to the register bank that we are doing
23400 math on. If we would like not to return a subset of CLASS, reject this
23401 alternative: if reload cannot do this, it will still use its choice. */
23402 mode = GET_MODE (x);
23403 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
23404 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
23406 if (X87_FLOAT_MODE_P (mode))
23408 if (regclass == FP_TOP_SSE_REGS)
23410 else if (regclass == FP_SECOND_SSE_REGS)
23411 return FP_SECOND_REG;
23413 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
23419 static enum reg_class
23420 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
23421 enum machine_mode mode,
23422 secondary_reload_info *sri ATTRIBUTE_UNUSED)
23424 /* QImode spills from non-QI registers require
23425 intermediate register on 32bit targets. */
23426 if (!in_p && mode == QImode && !TARGET_64BIT
23427 && (rclass == GENERAL_REGS
23428 || rclass == LEGACY_REGS
23429 || rclass == INDEX_REGS))
23438 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
23439 regno = true_regnum (x);
23441 /* Return Q_REGS if the operand is in memory. */
23449 /* If we are copying between general and FP registers, we need a memory
23450 location. The same is true for SSE and MMX registers.
23452 To optimize register_move_cost performance, allow inline variant.
23454 The macro can't work reliably when one of the CLASSES is class containing
23455 registers from multiple units (SSE, MMX, integer). We avoid this by never
23456 combining those units in single alternative in the machine description.
23457 Ensure that this constraint holds to avoid unexpected surprises.
23459 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
23460 enforce these sanity checks. */
23463 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
23464 enum machine_mode mode, int strict)
23466 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
23467 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
23468 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
23469 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
23470 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
23471 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
23473 gcc_assert (!strict);
23477 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
23480 /* ??? This is a lie. We do have moves between mmx/general, and for
23481 mmx/sse2. But by saying we need secondary memory we discourage the
23482 register allocator from using the mmx registers unless needed. */
23483 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
23486 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
23488 /* SSE1 doesn't have any direct moves from other classes. */
23492 /* If the target says that inter-unit moves are more expensive
23493 than moving through memory, then don't generate them. */
23494 if (!TARGET_INTER_UNIT_MOVES)
23497 /* Between SSE and general, we have moves no larger than word size. */
23498 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
23506 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
23507 enum machine_mode mode, int strict)
23509 return inline_secondary_memory_needed (class1, class2, mode, strict);
23512 /* Return true if the registers in CLASS cannot represent the change from
23513 modes FROM to TO. */
23516 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
23517 enum reg_class regclass)
23522 /* x87 registers can't do subreg at all, as all values are reformatted
23523 to extended precision. */
23524 if (MAYBE_FLOAT_CLASS_P (regclass))
23527 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
23529 /* Vector registers do not support QI or HImode loads. If we don't
23530 disallow a change to these modes, reload will assume it's ok to
23531 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
23532 the vec_dupv4hi pattern. */
23533 if (GET_MODE_SIZE (from) < 4)
23536 /* Vector registers do not support subreg with nonzero offsets, which
23537 are otherwise valid for integer registers. Since we can't see
23538 whether we have a nonzero offset from here, prohibit all
23539 nonparadoxical subregs changing size. */
23540 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
23547 /* Return the cost of moving data of mode M between a
23548 register and memory. A value of 2 is the default; this cost is
23549 relative to those in `REGISTER_MOVE_COST'.
23551 This function is used extensively by register_move_cost that is used to
23552 build tables at startup. Make it inline in this case.
23553 When IN is 2, return maximum of in and out move cost.
23555 If moving between registers and memory is more expensive than
23556 between two registers, you should define this macro to express the
23559 Model also increased moving costs of QImode registers in non
23563 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
23567 if (FLOAT_CLASS_P (regclass))
23585 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
23586 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
23588 if (SSE_CLASS_P (regclass))
23591 switch (GET_MODE_SIZE (mode))
23606 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
23607 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
23609 if (MMX_CLASS_P (regclass))
23612 switch (GET_MODE_SIZE (mode))
23624 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
23625 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
23627 switch (GET_MODE_SIZE (mode))
23630 if (Q_CLASS_P (regclass) || TARGET_64BIT)
23633 return ix86_cost->int_store[0];
23634 if (TARGET_PARTIAL_REG_DEPENDENCY && !optimize_size)
23635 cost = ix86_cost->movzbl_load;
23637 cost = ix86_cost->int_load[0];
23639 return MAX (cost, ix86_cost->int_store[0]);
23645 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
23647 return ix86_cost->movzbl_load;
23649 return ix86_cost->int_store[0] + 4;
23654 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
23655 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
23657 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
23658 if (mode == TFmode)
23661 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
23663 cost = ix86_cost->int_load[2];
23665 cost = ix86_cost->int_store[2];
23666 return (cost * (((int) GET_MODE_SIZE (mode)
23667 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
23672 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
23674 return inline_memory_move_cost (mode, regclass, in);
23678 /* Return the cost of moving data from a register in class CLASS1 to
23679 one in class CLASS2.
23681 It is not required that the cost always equal 2 when FROM is the same as TO;
23682 on some machines it is expensive to move between registers if they are not
23683 general registers. */
23686 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
23687 enum reg_class class2)
23689 /* In case we require secondary memory, compute cost of the store followed
23690 by load. In order to avoid bad register allocation choices, we need
23691 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
23693 if (inline_secondary_memory_needed (class1, class2, mode, 0))
23697 cost += inline_memory_move_cost (mode, class1, 2);
23698 cost += inline_memory_move_cost (mode, class2, 2);
23700 /* In case of copying from general_purpose_register we may emit multiple
23701 stores followed by single load causing memory size mismatch stall.
23702 Count this as arbitrarily high cost of 20. */
23703 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
23706 /* In the case of FP/MMX moves, the registers actually overlap, and we
23707 have to switch modes in order to treat them differently. */
23708 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
23709 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
23715 /* Moves between SSE/MMX and integer unit are expensive. */
23716 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
23717 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
23719 /* ??? By keeping returned value relatively high, we limit the number
23720 of moves between integer and MMX/SSE registers for all targets.
23721 Additionally, high value prevents problem with x86_modes_tieable_p(),
23722 where integer modes in MMX/SSE registers are not tieable
23723 because of missing QImode and HImode moves to, from or between
23724 MMX/SSE registers. */
23725 return MAX (8, ix86_cost->mmxsse_to_integer);
23727 if (MAYBE_FLOAT_CLASS_P (class1))
23728 return ix86_cost->fp_move;
23729 if (MAYBE_SSE_CLASS_P (class1))
23730 return ix86_cost->sse_move;
23731 if (MAYBE_MMX_CLASS_P (class1))
23732 return ix86_cost->mmx_move;
23736 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
23739 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
23741 /* Flags and only flags can only hold CCmode values. */
23742 if (CC_REGNO_P (regno))
23743 return GET_MODE_CLASS (mode) == MODE_CC;
23744 if (GET_MODE_CLASS (mode) == MODE_CC
23745 || GET_MODE_CLASS (mode) == MODE_RANDOM
23746 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
23748 if (FP_REGNO_P (regno))
23749 return VALID_FP_MODE_P (mode);
23750 if (SSE_REGNO_P (regno))
23752 /* We implement the move patterns for all vector modes into and
23753 out of SSE registers, even when no operation instructions
23755 return (VALID_SSE_REG_MODE (mode)
23756 || VALID_SSE2_REG_MODE (mode)
23757 || VALID_MMX_REG_MODE (mode)
23758 || VALID_MMX_REG_MODE_3DNOW (mode));
23760 if (MMX_REGNO_P (regno))
23762 /* We implement the move patterns for 3DNOW modes even in MMX mode,
23763 so if the register is available at all, then we can move data of
23764 the given mode into or out of it. */
23765 return (VALID_MMX_REG_MODE (mode)
23766 || VALID_MMX_REG_MODE_3DNOW (mode));
23769 if (mode == QImode)
23771 /* Take care for QImode values - they can be in non-QI regs,
23772 but then they do cause partial register stalls. */
23773 if (regno < 4 || TARGET_64BIT)
23775 if (!TARGET_PARTIAL_REG_STALL)
23777 return reload_in_progress || reload_completed;
23779 /* We handle both integer and floats in the general purpose registers. */
23780 else if (VALID_INT_MODE_P (mode))
23782 else if (VALID_FP_MODE_P (mode))
23784 else if (VALID_DFP_MODE_P (mode))
23786 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
23787 on to use that value in smaller contexts, this can easily force a
23788 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
23789 supporting DImode, allow it. */
23790 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
23796 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
23797 tieable integer mode. */
23800 ix86_tieable_integer_mode_p (enum machine_mode mode)
23809 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
23812 return TARGET_64BIT;
23819 /* Return true if MODE1 is accessible in a register that can hold MODE2
23820 without copying. That is, all register classes that can hold MODE2
23821 can also hold MODE1. */
23824 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
23826 if (mode1 == mode2)
23829 if (ix86_tieable_integer_mode_p (mode1)
23830 && ix86_tieable_integer_mode_p (mode2))
23833 /* MODE2 being XFmode implies fp stack or general regs, which means we
23834 can tie any smaller floating point modes to it. Note that we do not
23835 tie this with TFmode. */
23836 if (mode2 == XFmode)
23837 return mode1 == SFmode || mode1 == DFmode;
23839 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
23840 that we can tie it with SFmode. */
23841 if (mode2 == DFmode)
23842 return mode1 == SFmode;
23844 /* If MODE2 is only appropriate for an SSE register, then tie with
23845 any other mode acceptable to SSE registers. */
23846 if (GET_MODE_SIZE (mode2) == 16
23847 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
23848 return (GET_MODE_SIZE (mode1) == 16
23849 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
23851 /* If MODE2 is appropriate for an MMX register, then tie
23852 with any other mode acceptable to MMX registers. */
23853 if (GET_MODE_SIZE (mode2) == 8
23854 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
23855 return (GET_MODE_SIZE (mode1) == 8
23856 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
23861 /* Compute a (partial) cost for rtx X. Return true if the complete
23862 cost has been computed, and false if subexpressions should be
23863 scanned. In either case, *TOTAL contains the cost result. */
23866 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total)
23868 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
23869 enum machine_mode mode = GET_MODE (x);
23877 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
23879 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
23881 else if (flag_pic && SYMBOLIC_CONST (x)
23883 || (!GET_CODE (x) != LABEL_REF
23884 && (GET_CODE (x) != SYMBOL_REF
23885 || !SYMBOL_REF_LOCAL_P (x)))))
23892 if (mode == VOIDmode)
23895 switch (standard_80387_constant_p (x))
23900 default: /* Other constants */
23905 /* Start with (MEM (SYMBOL_REF)), since that's where
23906 it'll probably end up. Add a penalty for size. */
23907 *total = (COSTS_N_INSNS (1)
23908 + (flag_pic != 0 && !TARGET_64BIT)
23909 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
23915 /* The zero extensions is often completely free on x86_64, so make
23916 it as cheap as possible. */
23917 if (TARGET_64BIT && mode == DImode
23918 && GET_MODE (XEXP (x, 0)) == SImode)
23920 else if (TARGET_ZERO_EXTEND_WITH_AND)
23921 *total = ix86_cost->add;
23923 *total = ix86_cost->movzx;
23927 *total = ix86_cost->movsx;
23931 if (CONST_INT_P (XEXP (x, 1))
23932 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
23934 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
23937 *total = ix86_cost->add;
23940 if ((value == 2 || value == 3)
23941 && ix86_cost->lea <= ix86_cost->shift_const)
23943 *total = ix86_cost->lea;
23953 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
23955 if (CONST_INT_P (XEXP (x, 1)))
23957 if (INTVAL (XEXP (x, 1)) > 32)
23958 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
23960 *total = ix86_cost->shift_const * 2;
23964 if (GET_CODE (XEXP (x, 1)) == AND)
23965 *total = ix86_cost->shift_var * 2;
23967 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
23972 if (CONST_INT_P (XEXP (x, 1)))
23973 *total = ix86_cost->shift_const;
23975 *total = ix86_cost->shift_var;
23980 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
23982 /* ??? SSE scalar cost should be used here. */
23983 *total = ix86_cost->fmul;
23986 else if (X87_FLOAT_MODE_P (mode))
23988 *total = ix86_cost->fmul;
23991 else if (FLOAT_MODE_P (mode))
23993 /* ??? SSE vector cost should be used here. */
23994 *total = ix86_cost->fmul;
23999 rtx op0 = XEXP (x, 0);
24000 rtx op1 = XEXP (x, 1);
24002 if (CONST_INT_P (XEXP (x, 1)))
24004 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
24005 for (nbits = 0; value != 0; value &= value - 1)
24009 /* This is arbitrary. */
24012 /* Compute costs correctly for widening multiplication. */
24013 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
24014 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
24015 == GET_MODE_SIZE (mode))
24017 int is_mulwiden = 0;
24018 enum machine_mode inner_mode = GET_MODE (op0);
24020 if (GET_CODE (op0) == GET_CODE (op1))
24021 is_mulwiden = 1, op1 = XEXP (op1, 0);
24022 else if (CONST_INT_P (op1))
24024 if (GET_CODE (op0) == SIGN_EXTEND)
24025 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
24028 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
24032 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
24035 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
24036 + nbits * ix86_cost->mult_bit
24037 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
24046 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
24047 /* ??? SSE cost should be used here. */
24048 *total = ix86_cost->fdiv;
24049 else if (X87_FLOAT_MODE_P (mode))
24050 *total = ix86_cost->fdiv;
24051 else if (FLOAT_MODE_P (mode))
24052 /* ??? SSE vector cost should be used here. */
24053 *total = ix86_cost->fdiv;
24055 *total = ix86_cost->divide[MODE_INDEX (mode)];
24059 if (GET_MODE_CLASS (mode) == MODE_INT
24060 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
24062 if (GET_CODE (XEXP (x, 0)) == PLUS
24063 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
24064 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
24065 && CONSTANT_P (XEXP (x, 1)))
24067 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
24068 if (val == 2 || val == 4 || val == 8)
24070 *total = ix86_cost->lea;
24071 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
24072 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
24074 *total += rtx_cost (XEXP (x, 1), outer_code);
24078 else if (GET_CODE (XEXP (x, 0)) == MULT
24079 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
24081 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
24082 if (val == 2 || val == 4 || val == 8)
24084 *total = ix86_cost->lea;
24085 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
24086 *total += rtx_cost (XEXP (x, 1), outer_code);
24090 else if (GET_CODE (XEXP (x, 0)) == PLUS)
24092 *total = ix86_cost->lea;
24093 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
24094 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
24095 *total += rtx_cost (XEXP (x, 1), outer_code);
24102 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
24104 /* ??? SSE cost should be used here. */
24105 *total = ix86_cost->fadd;
24108 else if (X87_FLOAT_MODE_P (mode))
24110 *total = ix86_cost->fadd;
24113 else if (FLOAT_MODE_P (mode))
24115 /* ??? SSE vector cost should be used here. */
24116 *total = ix86_cost->fadd;
24124 if (!TARGET_64BIT && mode == DImode)
24126 *total = (ix86_cost->add * 2
24127 + (rtx_cost (XEXP (x, 0), outer_code)
24128 << (GET_MODE (XEXP (x, 0)) != DImode))
24129 + (rtx_cost (XEXP (x, 1), outer_code)
24130 << (GET_MODE (XEXP (x, 1)) != DImode)));
24136 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
24138 /* ??? SSE cost should be used here. */
24139 *total = ix86_cost->fchs;
24142 else if (X87_FLOAT_MODE_P (mode))
24144 *total = ix86_cost->fchs;
24147 else if (FLOAT_MODE_P (mode))
24149 /* ??? SSE vector cost should be used here. */
24150 *total = ix86_cost->fchs;
24156 if (!TARGET_64BIT && mode == DImode)
24157 *total = ix86_cost->add * 2;
24159 *total = ix86_cost->add;
24163 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
24164 && XEXP (XEXP (x, 0), 1) == const1_rtx
24165 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
24166 && XEXP (x, 1) == const0_rtx)
24168 /* This kind of construct is implemented using test[bwl].
24169 Treat it as if we had an AND. */
24170 *total = (ix86_cost->add
24171 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
24172 + rtx_cost (const1_rtx, outer_code));
24178 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
24183 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
24184 /* ??? SSE cost should be used here. */
24185 *total = ix86_cost->fabs;
24186 else if (X87_FLOAT_MODE_P (mode))
24187 *total = ix86_cost->fabs;
24188 else if (FLOAT_MODE_P (mode))
24189 /* ??? SSE vector cost should be used here. */
24190 *total = ix86_cost->fabs;
24194 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
24195 /* ??? SSE cost should be used here. */
24196 *total = ix86_cost->fsqrt;
24197 else if (X87_FLOAT_MODE_P (mode))
24198 *total = ix86_cost->fsqrt;
24199 else if (FLOAT_MODE_P (mode))
24200 /* ??? SSE vector cost should be used here. */
24201 *total = ix86_cost->fsqrt;
24205 if (XINT (x, 1) == UNSPEC_TP)
24216 static int current_machopic_label_num;
24218 /* Given a symbol name and its associated stub, write out the
24219 definition of the stub. */
24222 machopic_output_stub (FILE *file, const char *symb, const char *stub)
24224 unsigned int length;
24225 char *binder_name, *symbol_name, lazy_ptr_name[32];
24226 int label = ++current_machopic_label_num;
24228 /* For 64-bit we shouldn't get here. */
24229 gcc_assert (!TARGET_64BIT);
24231 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
24232 symb = (*targetm.strip_name_encoding) (symb);
24234 length = strlen (stub);
24235 binder_name = XALLOCAVEC (char, length + 32);
24236 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
24238 length = strlen (symb);
24239 symbol_name = XALLOCAVEC (char, length + 32);
24240 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
24242 sprintf (lazy_ptr_name, "L%d$lz", label);
24245 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
24247 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
24249 fprintf (file, "%s:\n", stub);
24250 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24254 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
24255 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
24256 fprintf (file, "\tjmp\t*%%edx\n");
24259 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
24261 fprintf (file, "%s:\n", binder_name);
24265 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
24266 fprintf (file, "\tpushl\t%%eax\n");
24269 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
24271 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
24273 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
24274 fprintf (file, "%s:\n", lazy_ptr_name);
24275 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24276 fprintf (file, "\t.long %s\n", binder_name);
24280 darwin_x86_file_end (void)
24282 darwin_file_end ();
24285 #endif /* TARGET_MACHO */
24287 /* Order the registers for register allocator. */
24290 x86_order_regs_for_local_alloc (void)
24295 /* First allocate the local general purpose registers. */
24296 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
24297 if (GENERAL_REGNO_P (i) && call_used_regs[i])
24298 reg_alloc_order [pos++] = i;
24300 /* Global general purpose registers. */
24301 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
24302 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
24303 reg_alloc_order [pos++] = i;
24305 /* x87 registers come first in case we are doing FP math
24307 if (!TARGET_SSE_MATH)
24308 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
24309 reg_alloc_order [pos++] = i;
24311 /* SSE registers. */
24312 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
24313 reg_alloc_order [pos++] = i;
24314 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
24315 reg_alloc_order [pos++] = i;
24317 /* x87 registers. */
24318 if (TARGET_SSE_MATH)
24319 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
24320 reg_alloc_order [pos++] = i;
24322 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
24323 reg_alloc_order [pos++] = i;
24325 /* Initialize the rest of array as we do not allocate some registers
24327 while (pos < FIRST_PSEUDO_REGISTER)
24328 reg_alloc_order [pos++] = 0;
24331 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
24332 struct attribute_spec.handler. */
24334 ix86_handle_abi_attribute (tree *node, tree name,
24335 tree args ATTRIBUTE_UNUSED,
24336 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
24338 if (TREE_CODE (*node) != FUNCTION_TYPE
24339 && TREE_CODE (*node) != METHOD_TYPE
24340 && TREE_CODE (*node) != FIELD_DECL
24341 && TREE_CODE (*node) != TYPE_DECL)
24343 warning (OPT_Wattributes, "%qs attribute only applies to functions",
24344 IDENTIFIER_POINTER (name));
24345 *no_add_attrs = true;
24350 warning (OPT_Wattributes, "%qs attribute only available for 64-bit",
24351 IDENTIFIER_POINTER (name));
24352 *no_add_attrs = true;
24356 /* Can combine regparm with all attributes but fastcall. */
24357 if (is_attribute_p ("ms_abi", name))
24359 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
24361 error ("ms_abi and sysv_abi attributes are not compatible");
24366 else if (is_attribute_p ("sysv_abi", name))
24368 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
24370 error ("ms_abi and sysv_abi attributes are not compatible");
24379 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24380 struct attribute_spec.handler. */
24382 ix86_handle_struct_attribute (tree *node, tree name,
24383 tree args ATTRIBUTE_UNUSED,
24384 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
24387 if (DECL_P (*node))
24389 if (TREE_CODE (*node) == TYPE_DECL)
24390 type = &TREE_TYPE (*node);
24395 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
24396 || TREE_CODE (*type) == UNION_TYPE)))
24398 warning (OPT_Wattributes, "%qs attribute ignored",
24399 IDENTIFIER_POINTER (name));
24400 *no_add_attrs = true;
24403 else if ((is_attribute_p ("ms_struct", name)
24404 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
24405 || ((is_attribute_p ("gcc_struct", name)
24406 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
24408 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
24409 IDENTIFIER_POINTER (name));
24410 *no_add_attrs = true;
24417 ix86_ms_bitfield_layout_p (const_tree record_type)
24419 return (TARGET_MS_BITFIELD_LAYOUT &&
24420 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
24421 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
24424 /* Returns an expression indicating where the this parameter is
24425 located on entry to the FUNCTION. */
24428 x86_this_parameter (tree function)
24430 tree type = TREE_TYPE (function);
24431 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
24436 const int *parm_regs;
24438 if (ix86_function_type_abi (type) == MS_ABI)
24439 parm_regs = x86_64_ms_abi_int_parameter_registers;
24441 parm_regs = x86_64_int_parameter_registers;
24442 return gen_rtx_REG (DImode, parm_regs[aggr]);
24445 nregs = ix86_function_regparm (type, function);
24447 if (nregs > 0 && !stdarg_p (type))
24451 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
24452 regno = aggr ? DX_REG : CX_REG;
24460 return gen_rtx_MEM (SImode,
24461 plus_constant (stack_pointer_rtx, 4));
24464 return gen_rtx_REG (SImode, regno);
24467 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
24470 /* Determine whether x86_output_mi_thunk can succeed. */
24473 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
24474 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
24475 HOST_WIDE_INT vcall_offset, const_tree function)
24477 /* 64-bit can handle anything. */
24481 /* For 32-bit, everything's fine if we have one free register. */
24482 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
24485 /* Need a free register for vcall_offset. */
24489 /* Need a free register for GOT references. */
24490 if (flag_pic && !(*targetm.binds_local_p) (function))
24493 /* Otherwise ok. */
24497 /* Output the assembler code for a thunk function. THUNK_DECL is the
24498 declaration for the thunk function itself, FUNCTION is the decl for
24499 the target function. DELTA is an immediate constant offset to be
24500 added to THIS. If VCALL_OFFSET is nonzero, the word at
24501 *(*this + vcall_offset) should be added to THIS. */
24504 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
24505 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
24506 HOST_WIDE_INT vcall_offset, tree function)
24509 rtx this_param = x86_this_parameter (function);
24512 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
24513 pull it in now and let DELTA benefit. */
24514 if (REG_P (this_param))
24515 this_reg = this_param;
24516 else if (vcall_offset)
24518 /* Put the this parameter into %eax. */
24519 xops[0] = this_param;
24520 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
24521 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
24524 this_reg = NULL_RTX;
24526 /* Adjust the this parameter by a fixed constant. */
24529 xops[0] = GEN_INT (delta);
24530 xops[1] = this_reg ? this_reg : this_param;
24533 if (!x86_64_general_operand (xops[0], DImode))
24535 tmp = gen_rtx_REG (DImode, R10_REG);
24537 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
24539 xops[1] = this_param;
24541 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
24544 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
24547 /* Adjust the this parameter by a value stored in the vtable. */
24551 tmp = gen_rtx_REG (DImode, R10_REG);
24554 int tmp_regno = CX_REG;
24555 if (lookup_attribute ("fastcall",
24556 TYPE_ATTRIBUTES (TREE_TYPE (function))))
24557 tmp_regno = AX_REG;
24558 tmp = gen_rtx_REG (SImode, tmp_regno);
24561 xops[0] = gen_rtx_MEM (Pmode, this_reg);
24563 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
24565 /* Adjust the this parameter. */
24566 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
24567 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
24569 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
24570 xops[0] = GEN_INT (vcall_offset);
24572 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
24573 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
24575 xops[1] = this_reg;
24576 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
24579 /* If necessary, drop THIS back to its stack slot. */
24580 if (this_reg && this_reg != this_param)
24582 xops[0] = this_reg;
24583 xops[1] = this_param;
24584 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
24587 xops[0] = XEXP (DECL_RTL (function), 0);
24590 if (!flag_pic || (*targetm.binds_local_p) (function))
24591 output_asm_insn ("jmp\t%P0", xops);
24592 /* All thunks should be in the same object as their target,
24593 and thus binds_local_p should be true. */
24594 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
24595 gcc_unreachable ();
24598 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
24599 tmp = gen_rtx_CONST (Pmode, tmp);
24600 tmp = gen_rtx_MEM (QImode, tmp);
24602 output_asm_insn ("jmp\t%A0", xops);
24607 if (!flag_pic || (*targetm.binds_local_p) (function))
24608 output_asm_insn ("jmp\t%P0", xops);
24613 rtx sym_ref = XEXP (DECL_RTL (function), 0);
24614 tmp = (gen_rtx_SYMBOL_REF
24616 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
24617 tmp = gen_rtx_MEM (QImode, tmp);
24619 output_asm_insn ("jmp\t%0", xops);
24622 #endif /* TARGET_MACHO */
24624 tmp = gen_rtx_REG (SImode, CX_REG);
24625 output_set_got (tmp, NULL_RTX);
24628 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
24629 output_asm_insn ("jmp\t{*}%1", xops);
24635 x86_file_start (void)
24637 default_file_start ();
24639 darwin_file_start ();
24641 if (X86_FILE_START_VERSION_DIRECTIVE)
24642 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
24643 if (X86_FILE_START_FLTUSED)
24644 fputs ("\t.global\t__fltused\n", asm_out_file);
24645 if (ix86_asm_dialect == ASM_INTEL)
24646 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
24650 x86_field_alignment (tree field, int computed)
24652 enum machine_mode mode;
24653 tree type = TREE_TYPE (field);
24655 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
24657 mode = TYPE_MODE (strip_array_types (type));
24658 if (mode == DFmode || mode == DCmode
24659 || GET_MODE_CLASS (mode) == MODE_INT
24660 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
24661 return MIN (32, computed);
24665 /* Output assembler code to FILE to increment profiler label # LABELNO
24666 for profiling a function entry. */
24668 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
24672 #ifndef NO_PROFILE_COUNTERS
24673 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
24676 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
24677 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
24679 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
24683 #ifndef NO_PROFILE_COUNTERS
24684 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
24685 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
24687 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
24691 #ifndef NO_PROFILE_COUNTERS
24692 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
24693 PROFILE_COUNT_REGISTER);
24695 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
24699 /* We don't have exact information about the insn sizes, but we may assume
24700 quite safely that we are informed about all 1 byte insns and memory
24701 address sizes. This is enough to eliminate unnecessary padding in
24705 min_insn_size (rtx insn)
24709 if (!INSN_P (insn) || !active_insn_p (insn))
24712 /* Discard alignments we've emit and jump instructions. */
24713 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
24714 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
24717 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
24718 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
24721 /* Important case - calls are always 5 bytes.
24722 It is common to have many calls in the row. */
24724 && symbolic_reference_mentioned_p (PATTERN (insn))
24725 && !SIBLING_CALL_P (insn))
24727 if (get_attr_length (insn) <= 1)
24730 /* For normal instructions we may rely on the sizes of addresses
24731 and the presence of symbol to require 4 bytes of encoding.
24732 This is not the case for jumps where references are PC relative. */
24733 if (!JUMP_P (insn))
24735 l = get_attr_length_address (insn);
24736 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
24745 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
24749 ix86_avoid_jump_misspredicts (void)
24751 rtx insn, start = get_insns ();
24752 int nbytes = 0, njumps = 0;
24755 /* Look for all minimal intervals of instructions containing 4 jumps.
24756 The intervals are bounded by START and INSN. NBYTES is the total
24757 size of instructions in the interval including INSN and not including
24758 START. When the NBYTES is smaller than 16 bytes, it is possible
24759 that the end of START and INSN ends up in the same 16byte page.
24761 The smallest offset in the page INSN can start is the case where START
24762 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
24763 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
24765 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
24768 nbytes += min_insn_size (insn);
24770 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
24771 INSN_UID (insn), min_insn_size (insn));
24773 && GET_CODE (PATTERN (insn)) != ADDR_VEC
24774 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
24782 start = NEXT_INSN (start);
24783 if ((JUMP_P (start)
24784 && GET_CODE (PATTERN (start)) != ADDR_VEC
24785 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
24787 njumps--, isjump = 1;
24790 nbytes -= min_insn_size (start);
24792 gcc_assert (njumps >= 0);
24794 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
24795 INSN_UID (start), INSN_UID (insn), nbytes);
24797 if (njumps == 3 && isjump && nbytes < 16)
24799 int padsize = 15 - nbytes + min_insn_size (insn);
24802 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
24803 INSN_UID (insn), padsize);
24804 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
24809 /* AMD Athlon works faster
24810 when RET is not destination of conditional jump or directly preceded
24811 by other jump instruction. We avoid the penalty by inserting NOP just
24812 before the RET instructions in such cases. */
24814 ix86_pad_returns (void)
24819 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
24821 basic_block bb = e->src;
24822 rtx ret = BB_END (bb);
24824 bool replace = false;
24826 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
24827 || !maybe_hot_bb_p (bb))
24829 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
24830 if (active_insn_p (prev) || LABEL_P (prev))
24832 if (prev && LABEL_P (prev))
24837 FOR_EACH_EDGE (e, ei, bb->preds)
24838 if (EDGE_FREQUENCY (e) && e->src->index >= 0
24839 && !(e->flags & EDGE_FALLTHRU))
24844 prev = prev_active_insn (ret);
24846 && ((JUMP_P (prev) && any_condjump_p (prev))
24849 /* Empty functions get branch mispredict even when the jump destination
24850 is not visible to us. */
24851 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
24856 emit_insn_before (gen_return_internal_long (), ret);
24862 /* Implement machine specific optimizations. We implement padding of returns
24863 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
24867 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
24868 ix86_pad_returns ();
24869 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
24870 ix86_avoid_jump_misspredicts ();
24873 /* Return nonzero when QImode register that must be represented via REX prefix
24876 x86_extended_QIreg_mentioned_p (rtx insn)
24879 extract_insn_cached (insn);
24880 for (i = 0; i < recog_data.n_operands; i++)
24881 if (REG_P (recog_data.operand[i])
24882 && REGNO (recog_data.operand[i]) >= 4)
24887 /* Return nonzero when P points to register encoded via REX prefix.
24888 Called via for_each_rtx. */
24890 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
24892 unsigned int regno;
24895 regno = REGNO (*p);
24896 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
24899 /* Return true when INSN mentions register that must be encoded using REX
24902 x86_extended_reg_mentioned_p (rtx insn)
24904 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
24907 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
24908 optabs would emit if we didn't have TFmode patterns. */
24911 x86_emit_floatuns (rtx operands[2])
24913 rtx neglab, donelab, i0, i1, f0, in, out;
24914 enum machine_mode mode, inmode;
24916 inmode = GET_MODE (operands[1]);
24917 gcc_assert (inmode == SImode || inmode == DImode);
24920 in = force_reg (inmode, operands[1]);
24921 mode = GET_MODE (out);
24922 neglab = gen_label_rtx ();
24923 donelab = gen_label_rtx ();
24924 f0 = gen_reg_rtx (mode);
24926 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
24928 expand_float (out, in, 0);
24930 emit_jump_insn (gen_jump (donelab));
24933 emit_label (neglab);
24935 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
24937 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
24939 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
24941 expand_float (f0, i0, 0);
24943 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
24945 emit_label (donelab);
24948 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
24949 with all elements equal to VAR. Return true if successful. */
24952 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
24953 rtx target, rtx val)
24955 enum machine_mode smode, wsmode, wvmode;
24970 val = force_reg (GET_MODE_INNER (mode), val);
24971 x = gen_rtx_VEC_DUPLICATE (mode, val);
24972 emit_insn (gen_rtx_SET (VOIDmode, target, x));
24978 if (TARGET_SSE || TARGET_3DNOW_A)
24980 val = gen_lowpart (SImode, val);
24981 x = gen_rtx_TRUNCATE (HImode, val);
24982 x = gen_rtx_VEC_DUPLICATE (mode, x);
24983 emit_insn (gen_rtx_SET (VOIDmode, target, x));
25005 /* Extend HImode to SImode using a paradoxical SUBREG. */
25006 tmp1 = gen_reg_rtx (SImode);
25007 emit_move_insn (tmp1, gen_lowpart (SImode, val));
25008 /* Insert the SImode value as low element of V4SImode vector. */
25009 tmp2 = gen_reg_rtx (V4SImode);
25010 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
25011 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
25012 CONST0_RTX (V4SImode),
25014 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
25015 /* Cast the V4SImode vector back to a V8HImode vector. */
25016 tmp1 = gen_reg_rtx (V8HImode);
25017 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
25018 /* Duplicate the low short through the whole low SImode word. */
25019 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
25020 /* Cast the V8HImode vector back to a V4SImode vector. */
25021 tmp2 = gen_reg_rtx (V4SImode);
25022 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
25023 /* Replicate the low element of the V4SImode vector. */
25024 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
25025 /* Cast the V2SImode back to V8HImode, and store in target. */
25026 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
25037 /* Extend QImode to SImode using a paradoxical SUBREG. */
25038 tmp1 = gen_reg_rtx (SImode);
25039 emit_move_insn (tmp1, gen_lowpart (SImode, val));
25040 /* Insert the SImode value as low element of V4SImode vector. */
25041 tmp2 = gen_reg_rtx (V4SImode);
25042 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
25043 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
25044 CONST0_RTX (V4SImode),
25046 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
25047 /* Cast the V4SImode vector back to a V16QImode vector. */
25048 tmp1 = gen_reg_rtx (V16QImode);
25049 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
25050 /* Duplicate the low byte through the whole low SImode word. */
25051 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
25052 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
25053 /* Cast the V16QImode vector back to a V4SImode vector. */
25054 tmp2 = gen_reg_rtx (V4SImode);
25055 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
25056 /* Replicate the low element of the V4SImode vector. */
25057 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
25058 /* Cast the V2SImode back to V16QImode, and store in target. */
25059 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
25067 /* Replicate the value once into the next wider mode and recurse. */
25068 val = convert_modes (wsmode, smode, val, true);
25069 x = expand_simple_binop (wsmode, ASHIFT, val,
25070 GEN_INT (GET_MODE_BITSIZE (smode)),
25071 NULL_RTX, 1, OPTAB_LIB_WIDEN);
25072 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
25074 x = gen_reg_rtx (wvmode);
25075 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
25076 gcc_unreachable ();
25077 emit_move_insn (target, gen_lowpart (mode, x));
25085 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
25086 whose ONE_VAR element is VAR, and other elements are zero. Return true
25090 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
25091 rtx target, rtx var, int one_var)
25093 enum machine_mode vsimode;
25096 bool use_vector_set = false;
25101 use_vector_set = TARGET_64BIT && TARGET_SSE4_1;
25106 use_vector_set = TARGET_SSE4_1;
25109 use_vector_set = TARGET_SSE2;
25112 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
25118 if (use_vector_set)
25120 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
25121 var = force_reg (GET_MODE_INNER (mode), var);
25122 ix86_expand_vector_set (mmx_ok, target, var, one_var);
25138 var = force_reg (GET_MODE_INNER (mode), var);
25139 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
25140 emit_insn (gen_rtx_SET (VOIDmode, target, x));
25145 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
25146 new_target = gen_reg_rtx (mode);
25148 new_target = target;
25149 var = force_reg (GET_MODE_INNER (mode), var);
25150 x = gen_rtx_VEC_DUPLICATE (mode, var);
25151 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
25152 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
25155 /* We need to shuffle the value to the correct position, so
25156 create a new pseudo to store the intermediate result. */
25158 /* With SSE2, we can use the integer shuffle insns. */
25159 if (mode != V4SFmode && TARGET_SSE2)
25161 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
25163 GEN_INT (one_var == 1 ? 0 : 1),
25164 GEN_INT (one_var == 2 ? 0 : 1),
25165 GEN_INT (one_var == 3 ? 0 : 1)));
25166 if (target != new_target)
25167 emit_move_insn (target, new_target);
25171 /* Otherwise convert the intermediate result to V4SFmode and
25172 use the SSE1 shuffle instructions. */
25173 if (mode != V4SFmode)
25175 tmp = gen_reg_rtx (V4SFmode);
25176 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
25181 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
25183 GEN_INT (one_var == 1 ? 0 : 1),
25184 GEN_INT (one_var == 2 ? 0+4 : 1+4),
25185 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
25187 if (mode != V4SFmode)
25188 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
25189 else if (tmp != target)
25190 emit_move_insn (target, tmp);
25192 else if (target != new_target)
25193 emit_move_insn (target, new_target);
25198 vsimode = V4SImode;
25204 vsimode = V2SImode;
25210 /* Zero extend the variable element to SImode and recurse. */
25211 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
25213 x = gen_reg_rtx (vsimode);
25214 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
25216 gcc_unreachable ();
25218 emit_move_insn (target, gen_lowpart (mode, x));
25226 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
25227 consisting of the values in VALS. It is known that all elements
25228 except ONE_VAR are constants. Return true if successful. */
25231 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
25232 rtx target, rtx vals, int one_var)
25234 rtx var = XVECEXP (vals, 0, one_var);
25235 enum machine_mode wmode;
25238 const_vec = copy_rtx (vals);
25239 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
25240 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
25248 /* For the two element vectors, it's just as easy to use
25249 the general case. */
25267 /* There's no way to set one QImode entry easily. Combine
25268 the variable value with its adjacent constant value, and
25269 promote to an HImode set. */
25270 x = XVECEXP (vals, 0, one_var ^ 1);
25273 var = convert_modes (HImode, QImode, var, true);
25274 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
25275 NULL_RTX, 1, OPTAB_LIB_WIDEN);
25276 x = GEN_INT (INTVAL (x) & 0xff);
25280 var = convert_modes (HImode, QImode, var, true);
25281 x = gen_int_mode (INTVAL (x) << 8, HImode);
25283 if (x != const0_rtx)
25284 var = expand_simple_binop (HImode, IOR, var, x, var,
25285 1, OPTAB_LIB_WIDEN);
25287 x = gen_reg_rtx (wmode);
25288 emit_move_insn (x, gen_lowpart (wmode, const_vec));
25289 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
25291 emit_move_insn (target, gen_lowpart (mode, x));
25298 emit_move_insn (target, const_vec);
25299 ix86_expand_vector_set (mmx_ok, target, var, one_var);
25303 /* A subroutine of ix86_expand_vector_init_general. Use vector
25304 concatenate to handle the most general case: all values variable,
25305 and none identical. */
25308 ix86_expand_vector_init_concat (enum machine_mode mode,
25309 rtx target, rtx *ops, int n)
25311 enum machine_mode cmode, hmode = VOIDmode;
25312 rtx first[4], second[2];
25340 gcc_unreachable ();
25343 if (!register_operand (ops[1], cmode))
25344 ops[1] = force_reg (cmode, ops[1]);
25345 if (!register_operand (ops[0], cmode))
25346 ops[0] = force_reg (cmode, ops[0]);
25347 emit_insn (gen_rtx_SET (VOIDmode, target,
25348 gen_rtx_VEC_CONCAT (mode, ops[0],
25362 gcc_unreachable ();
25367 /* FIXME: We process inputs backward to help RA. PR 36222. */
25370 for (; i > 0; i -= 2, j--)
25372 first[j] = gen_reg_rtx (cmode);
25373 v = gen_rtvec (2, ops[i - 1], ops[i]);
25374 ix86_expand_vector_init (false, first[j],
25375 gen_rtx_PARALLEL (cmode, v));
25381 gcc_assert (hmode != VOIDmode);
25382 for (i = j = 0; i < n; i += 2, j++)
25384 second[j] = gen_reg_rtx (hmode);
25385 ix86_expand_vector_init_concat (hmode, second [j],
25389 ix86_expand_vector_init_concat (mode, target, second, n);
25392 ix86_expand_vector_init_concat (mode, target, first, n);
25396 gcc_unreachable ();
25400 /* A subroutine of ix86_expand_vector_init_general. Use vector
25401 interleave to handle the most general case: all values variable,
25402 and none identical. */
25405 ix86_expand_vector_init_interleave (enum machine_mode mode,
25406 rtx target, rtx *ops, int n)
25408 enum machine_mode first_imode, second_imode, third_imode;
25411 rtx (*gen_load_even) (rtx, rtx, rtx);
25412 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
25413 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
25418 gen_load_even = gen_vec_setv8hi;
25419 gen_interleave_first_low = gen_vec_interleave_lowv4si;
25420 gen_interleave_second_low = gen_vec_interleave_lowv2di;
25421 first_imode = V4SImode;
25422 second_imode = V2DImode;
25423 third_imode = VOIDmode;
25426 gen_load_even = gen_vec_setv16qi;
25427 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
25428 gen_interleave_second_low = gen_vec_interleave_lowv4si;
25429 first_imode = V8HImode;
25430 second_imode = V4SImode;
25431 third_imode = V2DImode;
25434 gcc_unreachable ();
25437 for (i = 0; i < n; i++)
25439 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
25440 op0 = gen_reg_rtx (SImode);
25441 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
25443 /* Insert the SImode value as low element of V4SImode vector. */
25444 op1 = gen_reg_rtx (V4SImode);
25445 op0 = gen_rtx_VEC_MERGE (V4SImode,
25446 gen_rtx_VEC_DUPLICATE (V4SImode,
25448 CONST0_RTX (V4SImode),
25450 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
25452 /* Cast the V4SImode vector back to a vector in orignal mode. */
25453 op0 = gen_reg_rtx (mode);
25454 emit_move_insn (op0, gen_lowpart (mode, op1));
25456 /* Load even elements into the second positon. */
25457 emit_insn ((*gen_load_even) (op0, ops [i + i + 1],
25460 /* Cast vector to FIRST_IMODE vector. */
25461 ops[i] = gen_reg_rtx (first_imode);
25462 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
25465 /* Interleave low FIRST_IMODE vectors. */
25466 for (i = j = 0; i < n; i += 2, j++)
25468 op0 = gen_reg_rtx (first_imode);
25469 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
25471 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
25472 ops[j] = gen_reg_rtx (second_imode);
25473 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
25476 /* Interleave low SECOND_IMODE vectors. */
25477 switch (second_imode)
25480 for (i = j = 0; i < n / 2; i += 2, j++)
25482 op0 = gen_reg_rtx (second_imode);
25483 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
25486 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
25488 ops[j] = gen_reg_rtx (third_imode);
25489 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
25491 second_imode = V2DImode;
25492 gen_interleave_second_low = gen_vec_interleave_lowv2di;
25496 op0 = gen_reg_rtx (second_imode);
25497 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
25500 /* Cast the SECOND_IMODE vector back to a vector on original
25502 emit_insn (gen_rtx_SET (VOIDmode, target,
25503 gen_lowpart (mode, op0)));
25507 gcc_unreachable ();
25511 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
25512 all values variable, and none identical. */
25515 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
25516 rtx target, rtx vals)
25525 if (!mmx_ok && !TARGET_SSE)
25533 n = GET_MODE_NUNITS (mode);
25534 for (i = 0; i < n; i++)
25535 ops[i] = XVECEXP (vals, 0, i);
25536 ix86_expand_vector_init_concat (mode, target, ops, n);
25540 if (!TARGET_SSE4_1)
25548 n = GET_MODE_NUNITS (mode);
25549 for (i = 0; i < n; i++)
25550 ops[i] = XVECEXP (vals, 0, i);
25551 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
25559 gcc_unreachable ();
25563 int i, j, n_elts, n_words, n_elt_per_word;
25564 enum machine_mode inner_mode;
25565 rtx words[4], shift;
25567 inner_mode = GET_MODE_INNER (mode);
25568 n_elts = GET_MODE_NUNITS (mode);
25569 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
25570 n_elt_per_word = n_elts / n_words;
25571 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
25573 for (i = 0; i < n_words; ++i)
25575 rtx word = NULL_RTX;
25577 for (j = 0; j < n_elt_per_word; ++j)
25579 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
25580 elt = convert_modes (word_mode, inner_mode, elt, true);
25586 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
25587 word, 1, OPTAB_LIB_WIDEN);
25588 word = expand_simple_binop (word_mode, IOR, word, elt,
25589 word, 1, OPTAB_LIB_WIDEN);
25597 emit_move_insn (target, gen_lowpart (mode, words[0]));
25598 else if (n_words == 2)
25600 rtx tmp = gen_reg_rtx (mode);
25601 emit_clobber (tmp);
25602 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
25603 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
25604 emit_move_insn (target, tmp);
25606 else if (n_words == 4)
25608 rtx tmp = gen_reg_rtx (V4SImode);
25609 gcc_assert (word_mode == SImode);
25610 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
25611 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
25612 emit_move_insn (target, gen_lowpart (mode, tmp));
25615 gcc_unreachable ();
25619 /* Initialize vector TARGET via VALS. Suppress the use of MMX
25620 instructions unless MMX_OK is true. */
25623 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
25625 enum machine_mode mode = GET_MODE (target);
25626 enum machine_mode inner_mode = GET_MODE_INNER (mode);
25627 int n_elts = GET_MODE_NUNITS (mode);
25628 int n_var = 0, one_var = -1;
25629 bool all_same = true, all_const_zero = true;
25633 for (i = 0; i < n_elts; ++i)
25635 x = XVECEXP (vals, 0, i);
25636 if (!(CONST_INT_P (x)
25637 || GET_CODE (x) == CONST_DOUBLE
25638 || GET_CODE (x) == CONST_FIXED))
25639 n_var++, one_var = i;
25640 else if (x != CONST0_RTX (inner_mode))
25641 all_const_zero = false;
25642 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
25646 /* Constants are best loaded from the constant pool. */
25649 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
25653 /* If all values are identical, broadcast the value. */
25655 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
25656 XVECEXP (vals, 0, 0)))
25659 /* Values where only one field is non-constant are best loaded from
25660 the pool and overwritten via move later. */
25664 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
25665 XVECEXP (vals, 0, one_var),
25669 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
25673 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
25677 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
25679 enum machine_mode mode = GET_MODE (target);
25680 enum machine_mode inner_mode = GET_MODE_INNER (mode);
25681 bool use_vec_merge = false;
25690 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
25691 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
25693 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
25695 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
25696 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
25702 use_vec_merge = TARGET_SSE4_1;
25710 /* For the two element vectors, we implement a VEC_CONCAT with
25711 the extraction of the other element. */
25713 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
25714 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
25717 op0 = val, op1 = tmp;
25719 op0 = tmp, op1 = val;
25721 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
25722 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
25727 use_vec_merge = TARGET_SSE4_1;
25734 use_vec_merge = true;
25738 /* tmp = target = A B C D */
25739 tmp = copy_to_reg (target);
25740 /* target = A A B B */
25741 emit_insn (gen_sse_unpcklps (target, target, target));
25742 /* target = X A B B */
25743 ix86_expand_vector_set (false, target, val, 0);
25744 /* target = A X C D */
25745 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
25746 GEN_INT (1), GEN_INT (0),
25747 GEN_INT (2+4), GEN_INT (3+4)));
25751 /* tmp = target = A B C D */
25752 tmp = copy_to_reg (target);
25753 /* tmp = X B C D */
25754 ix86_expand_vector_set (false, tmp, val, 0);
25755 /* target = A B X D */
25756 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
25757 GEN_INT (0), GEN_INT (1),
25758 GEN_INT (0+4), GEN_INT (3+4)));
25762 /* tmp = target = A B C D */
25763 tmp = copy_to_reg (target);
25764 /* tmp = X B C D */
25765 ix86_expand_vector_set (false, tmp, val, 0);
25766 /* target = A B X D */
25767 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
25768 GEN_INT (0), GEN_INT (1),
25769 GEN_INT (2+4), GEN_INT (0+4)));
25773 gcc_unreachable ();
25778 use_vec_merge = TARGET_SSE4_1;
25782 /* Element 0 handled by vec_merge below. */
25785 use_vec_merge = true;
25791 /* With SSE2, use integer shuffles to swap element 0 and ELT,
25792 store into element 0, then shuffle them back. */
25796 order[0] = GEN_INT (elt);
25797 order[1] = const1_rtx;
25798 order[2] = const2_rtx;
25799 order[3] = GEN_INT (3);
25800 order[elt] = const0_rtx;
25802 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
25803 order[1], order[2], order[3]));
25805 ix86_expand_vector_set (false, target, val, 0);
25807 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
25808 order[1], order[2], order[3]));
25812 /* For SSE1, we have to reuse the V4SF code. */
25813 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
25814 gen_lowpart (SFmode, val), elt);
25819 use_vec_merge = TARGET_SSE2;
25822 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
25826 use_vec_merge = TARGET_SSE4_1;
25836 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
25837 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
25838 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
25842 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
25844 emit_move_insn (mem, target);
25846 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
25847 emit_move_insn (tmp, val);
25849 emit_move_insn (target, mem);
25854 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
25856 enum machine_mode mode = GET_MODE (vec);
25857 enum machine_mode inner_mode = GET_MODE_INNER (mode);
25858 bool use_vec_extr = false;
25871 use_vec_extr = true;
25875 use_vec_extr = TARGET_SSE4_1;
25887 tmp = gen_reg_rtx (mode);
25888 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
25889 GEN_INT (elt), GEN_INT (elt),
25890 GEN_INT (elt+4), GEN_INT (elt+4)));
25894 tmp = gen_reg_rtx (mode);
25895 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
25899 gcc_unreachable ();
25902 use_vec_extr = true;
25907 use_vec_extr = TARGET_SSE4_1;
25921 tmp = gen_reg_rtx (mode);
25922 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
25923 GEN_INT (elt), GEN_INT (elt),
25924 GEN_INT (elt), GEN_INT (elt)));
25928 tmp = gen_reg_rtx (mode);
25929 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
25933 gcc_unreachable ();
25936 use_vec_extr = true;
25941 /* For SSE1, we have to reuse the V4SF code. */
25942 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
25943 gen_lowpart (V4SFmode, vec), elt);
25949 use_vec_extr = TARGET_SSE2;
25952 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
25956 use_vec_extr = TARGET_SSE4_1;
25960 /* ??? Could extract the appropriate HImode element and shift. */
25967 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
25968 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
25970 /* Let the rtl optimizers know about the zero extension performed. */
25971 if (inner_mode == QImode || inner_mode == HImode)
25973 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
25974 target = gen_lowpart (SImode, target);
25977 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
25981 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
25983 emit_move_insn (mem, vec);
25985 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
25986 emit_move_insn (target, tmp);
25990 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
25991 pattern to reduce; DEST is the destination; IN is the input vector. */
25994 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
25996 rtx tmp1, tmp2, tmp3;
25998 tmp1 = gen_reg_rtx (V4SFmode);
25999 tmp2 = gen_reg_rtx (V4SFmode);
26000 tmp3 = gen_reg_rtx (V4SFmode);
26002 emit_insn (gen_sse_movhlps (tmp1, in, in));
26003 emit_insn (fn (tmp2, tmp1, in));
26005 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
26006 GEN_INT (1), GEN_INT (1),
26007 GEN_INT (1+4), GEN_INT (1+4)));
26008 emit_insn (fn (dest, tmp2, tmp3));
26011 /* Target hook for scalar_mode_supported_p. */
26013 ix86_scalar_mode_supported_p (enum machine_mode mode)
26015 if (DECIMAL_FLOAT_MODE_P (mode))
26017 else if (mode == TFmode)
26020 return default_scalar_mode_supported_p (mode);
26023 /* Implements target hook vector_mode_supported_p. */
26025 ix86_vector_mode_supported_p (enum machine_mode mode)
26027 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
26029 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
26031 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
26033 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
26038 /* Target hook for c_mode_for_suffix. */
26039 static enum machine_mode
26040 ix86_c_mode_for_suffix (char suffix)
26050 /* Worker function for TARGET_MD_ASM_CLOBBERS.
26052 We do this in the new i386 backend to maintain source compatibility
26053 with the old cc0-based compiler. */
26056 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
26057 tree inputs ATTRIBUTE_UNUSED,
26060 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
26062 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
26067 /* Implements target vector targetm.asm.encode_section_info. This
26068 is not used by netware. */
26070 static void ATTRIBUTE_UNUSED
26071 ix86_encode_section_info (tree decl, rtx rtl, int first)
26073 default_encode_section_info (decl, rtl, first);
26075 if (TREE_CODE (decl) == VAR_DECL
26076 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
26077 && ix86_in_large_data_p (decl))
26078 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
26081 /* Worker function for REVERSE_CONDITION. */
26084 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
26086 return (mode != CCFPmode && mode != CCFPUmode
26087 ? reverse_condition (code)
26088 : reverse_condition_maybe_unordered (code));
26091 /* Output code to perform an x87 FP register move, from OPERANDS[1]
26095 output_387_reg_move (rtx insn, rtx *operands)
26097 if (REG_P (operands[0]))
26099 if (REG_P (operands[1])
26100 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
26102 if (REGNO (operands[0]) == FIRST_STACK_REG)
26103 return output_387_ffreep (operands, 0);
26104 return "fstp\t%y0";
26106 if (STACK_TOP_P (operands[0]))
26107 return "fld%z1\t%y1";
26110 else if (MEM_P (operands[0]))
26112 gcc_assert (REG_P (operands[1]));
26113 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
26114 return "fstp%z0\t%y0";
26117 /* There is no non-popping store to memory for XFmode.
26118 So if we need one, follow the store with a load. */
26119 if (GET_MODE (operands[0]) == XFmode)
26120 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
26122 return "fst%z0\t%y0";
26129 /* Output code to perform a conditional jump to LABEL, if C2 flag in
26130 FP status register is set. */
26133 ix86_emit_fp_unordered_jump (rtx label)
26135 rtx reg = gen_reg_rtx (HImode);
26138 emit_insn (gen_x86_fnstsw_1 (reg));
26140 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
26142 emit_insn (gen_x86_sahf_1 (reg));
26144 temp = gen_rtx_REG (CCmode, FLAGS_REG);
26145 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
26149 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
26151 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
26152 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
26155 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
26156 gen_rtx_LABEL_REF (VOIDmode, label),
26158 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
26160 emit_jump_insn (temp);
26161 predict_jump (REG_BR_PROB_BASE * 10 / 100);
26164 /* Output code to perform a log1p XFmode calculation. */
26166 void ix86_emit_i387_log1p (rtx op0, rtx op1)
26168 rtx label1 = gen_label_rtx ();
26169 rtx label2 = gen_label_rtx ();
26171 rtx tmp = gen_reg_rtx (XFmode);
26172 rtx tmp2 = gen_reg_rtx (XFmode);
26174 emit_insn (gen_absxf2 (tmp, op1));
26175 emit_insn (gen_cmpxf (tmp,
26176 CONST_DOUBLE_FROM_REAL_VALUE (
26177 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
26179 emit_jump_insn (gen_bge (label1));
26181 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
26182 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
26183 emit_jump (label2);
26185 emit_label (label1);
26186 emit_move_insn (tmp, CONST1_RTX (XFmode));
26187 emit_insn (gen_addxf3 (tmp, op1, tmp));
26188 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
26189 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
26191 emit_label (label2);
26194 /* Output code to perform a Newton-Rhapson approximation of a single precision
26195 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
26197 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
26199 rtx x0, x1, e0, e1, two;
26201 x0 = gen_reg_rtx (mode);
26202 e0 = gen_reg_rtx (mode);
26203 e1 = gen_reg_rtx (mode);
26204 x1 = gen_reg_rtx (mode);
26206 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
26208 if (VECTOR_MODE_P (mode))
26209 two = ix86_build_const_vector (SFmode, true, two);
26211 two = force_reg (mode, two);
26213 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
26215 /* x0 = rcp(b) estimate */
26216 emit_insn (gen_rtx_SET (VOIDmode, x0,
26217 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
26220 emit_insn (gen_rtx_SET (VOIDmode, e0,
26221 gen_rtx_MULT (mode, x0, b)));
26223 emit_insn (gen_rtx_SET (VOIDmode, e1,
26224 gen_rtx_MINUS (mode, two, e0)));
26226 emit_insn (gen_rtx_SET (VOIDmode, x1,
26227 gen_rtx_MULT (mode, x0, e1)));
26229 emit_insn (gen_rtx_SET (VOIDmode, res,
26230 gen_rtx_MULT (mode, a, x1)));
26233 /* Output code to perform a Newton-Rhapson approximation of a
26234 single precision floating point [reciprocal] square root. */
26236 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
26239 rtx x0, e0, e1, e2, e3, mthree, mhalf;
26242 x0 = gen_reg_rtx (mode);
26243 e0 = gen_reg_rtx (mode);
26244 e1 = gen_reg_rtx (mode);
26245 e2 = gen_reg_rtx (mode);
26246 e3 = gen_reg_rtx (mode);
26248 real_from_integer (&r, VOIDmode, -3, -1, 0);
26249 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
26251 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
26252 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
26254 if (VECTOR_MODE_P (mode))
26256 mthree = ix86_build_const_vector (SFmode, true, mthree);
26257 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
26260 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
26261 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
26263 /* x0 = rsqrt(a) estimate */
26264 emit_insn (gen_rtx_SET (VOIDmode, x0,
26265 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
26268 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
26273 zero = gen_reg_rtx (mode);
26274 mask = gen_reg_rtx (mode);
26276 zero = force_reg (mode, CONST0_RTX(mode));
26277 emit_insn (gen_rtx_SET (VOIDmode, mask,
26278 gen_rtx_NE (mode, zero, a)));
26280 emit_insn (gen_rtx_SET (VOIDmode, x0,
26281 gen_rtx_AND (mode, x0, mask)));
26285 emit_insn (gen_rtx_SET (VOIDmode, e0,
26286 gen_rtx_MULT (mode, x0, a)));
26288 emit_insn (gen_rtx_SET (VOIDmode, e1,
26289 gen_rtx_MULT (mode, e0, x0)));
26292 mthree = force_reg (mode, mthree);
26293 emit_insn (gen_rtx_SET (VOIDmode, e2,
26294 gen_rtx_PLUS (mode, e1, mthree)));
26296 mhalf = force_reg (mode, mhalf);
26298 /* e3 = -.5 * x0 */
26299 emit_insn (gen_rtx_SET (VOIDmode, e3,
26300 gen_rtx_MULT (mode, x0, mhalf)));
26302 /* e3 = -.5 * e0 */
26303 emit_insn (gen_rtx_SET (VOIDmode, e3,
26304 gen_rtx_MULT (mode, e0, mhalf)));
26305 /* ret = e2 * e3 */
26306 emit_insn (gen_rtx_SET (VOIDmode, res,
26307 gen_rtx_MULT (mode, e2, e3)));
26310 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
26312 static void ATTRIBUTE_UNUSED
26313 i386_solaris_elf_named_section (const char *name, unsigned int flags,
26316 /* With Binutils 2.15, the "@unwind" marker must be specified on
26317 every occurrence of the ".eh_frame" section, not just the first
26320 && strcmp (name, ".eh_frame") == 0)
26322 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
26323 flags & SECTION_WRITE ? "aw" : "a");
26326 default_elf_asm_named_section (name, flags, decl);
26329 /* Return the mangling of TYPE if it is an extended fundamental type. */
26331 static const char *
26332 ix86_mangle_type (const_tree type)
26334 type = TYPE_MAIN_VARIANT (type);
26336 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
26337 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
26340 switch (TYPE_MODE (type))
26343 /* __float128 is "g". */
26346 /* "long double" or __float80 is "e". */
26353 /* For 32-bit code we can save PIC register setup by using
26354 __stack_chk_fail_local hidden function instead of calling
26355 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
26356 register, so it is better to call __stack_chk_fail directly. */
26359 ix86_stack_protect_fail (void)
26361 return TARGET_64BIT
26362 ? default_external_stack_protect_fail ()
26363 : default_hidden_stack_protect_fail ();
26366 /* Select a format to encode pointers in exception handling data. CODE
26367 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
26368 true if the symbol may be affected by dynamic relocations.
26370 ??? All x86 object file formats are capable of representing this.
26371 After all, the relocation needed is the same as for the call insn.
26372 Whether or not a particular assembler allows us to enter such, I
26373 guess we'll have to see. */
26375 asm_preferred_eh_data_format (int code, int global)
26379 int type = DW_EH_PE_sdata8;
26381 || ix86_cmodel == CM_SMALL_PIC
26382 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
26383 type = DW_EH_PE_sdata4;
26384 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
26386 if (ix86_cmodel == CM_SMALL
26387 || (ix86_cmodel == CM_MEDIUM && code))
26388 return DW_EH_PE_udata4;
26389 return DW_EH_PE_absptr;
26392 /* Expand copysign from SIGN to the positive value ABS_VALUE
26393 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
26396 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
26398 enum machine_mode mode = GET_MODE (sign);
26399 rtx sgn = gen_reg_rtx (mode);
26400 if (mask == NULL_RTX)
26402 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
26403 if (!VECTOR_MODE_P (mode))
26405 /* We need to generate a scalar mode mask in this case. */
26406 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
26407 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
26408 mask = gen_reg_rtx (mode);
26409 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
26413 mask = gen_rtx_NOT (mode, mask);
26414 emit_insn (gen_rtx_SET (VOIDmode, sgn,
26415 gen_rtx_AND (mode, mask, sign)));
26416 emit_insn (gen_rtx_SET (VOIDmode, result,
26417 gen_rtx_IOR (mode, abs_value, sgn)));
26420 /* Expand fabs (OP0) and return a new rtx that holds the result. The
26421 mask for masking out the sign-bit is stored in *SMASK, if that is
26424 ix86_expand_sse_fabs (rtx op0, rtx *smask)
26426 enum machine_mode mode = GET_MODE (op0);
26429 xa = gen_reg_rtx (mode);
26430 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
26431 if (!VECTOR_MODE_P (mode))
26433 /* We need to generate a scalar mode mask in this case. */
26434 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
26435 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
26436 mask = gen_reg_rtx (mode);
26437 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
26439 emit_insn (gen_rtx_SET (VOIDmode, xa,
26440 gen_rtx_AND (mode, op0, mask)));
26448 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
26449 swapping the operands if SWAP_OPERANDS is true. The expanded
26450 code is a forward jump to a newly created label in case the
26451 comparison is true. The generated label rtx is returned. */
26453 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
26454 bool swap_operands)
26465 label = gen_label_rtx ();
26466 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
26467 emit_insn (gen_rtx_SET (VOIDmode, tmp,
26468 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
26469 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
26470 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
26471 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
26472 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
26473 JUMP_LABEL (tmp) = label;
26478 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
26479 using comparison code CODE. Operands are swapped for the comparison if
26480 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
26482 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
26483 bool swap_operands)
26485 enum machine_mode mode = GET_MODE (op0);
26486 rtx mask = gen_reg_rtx (mode);
26495 if (mode == DFmode)
26496 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
26497 gen_rtx_fmt_ee (code, mode, op0, op1)));
26499 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
26500 gen_rtx_fmt_ee (code, mode, op0, op1)));
26505 /* Generate and return a rtx of mode MODE for 2**n where n is the number
26506 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
26508 ix86_gen_TWO52 (enum machine_mode mode)
26510 REAL_VALUE_TYPE TWO52r;
26513 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
26514 TWO52 = const_double_from_real_value (TWO52r, mode);
26515 TWO52 = force_reg (mode, TWO52);
26520 /* Expand SSE sequence for computing lround from OP1 storing
26523 ix86_expand_lround (rtx op0, rtx op1)
26525 /* C code for the stuff we're doing below:
26526 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
26529 enum machine_mode mode = GET_MODE (op1);
26530 const struct real_format *fmt;
26531 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
26534 /* load nextafter (0.5, 0.0) */
26535 fmt = REAL_MODE_FORMAT (mode);
26536 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
26537 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
26539 /* adj = copysign (0.5, op1) */
26540 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
26541 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
26543 /* adj = op1 + adj */
26544 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
26546 /* op0 = (imode)adj */
26547 expand_fix (op0, adj, 0);
26550 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
26553 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
26555 /* C code for the stuff we're doing below (for do_floor):
26557 xi -= (double)xi > op1 ? 1 : 0;
26560 enum machine_mode fmode = GET_MODE (op1);
26561 enum machine_mode imode = GET_MODE (op0);
26562 rtx ireg, freg, label, tmp;
26564 /* reg = (long)op1 */
26565 ireg = gen_reg_rtx (imode);
26566 expand_fix (ireg, op1, 0);
26568 /* freg = (double)reg */
26569 freg = gen_reg_rtx (fmode);
26570 expand_float (freg, ireg, 0);
26572 /* ireg = (freg > op1) ? ireg - 1 : ireg */
26573 label = ix86_expand_sse_compare_and_jump (UNLE,
26574 freg, op1, !do_floor);
26575 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
26576 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
26577 emit_move_insn (ireg, tmp);
26579 emit_label (label);
26580 LABEL_NUSES (label) = 1;
26582 emit_move_insn (op0, ireg);
26585 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
26586 result in OPERAND0. */
26588 ix86_expand_rint (rtx operand0, rtx operand1)
26590 /* C code for the stuff we're doing below:
26591 xa = fabs (operand1);
26592 if (!isless (xa, 2**52))
26594 xa = xa + 2**52 - 2**52;
26595 return copysign (xa, operand1);
26597 enum machine_mode mode = GET_MODE (operand0);
26598 rtx res, xa, label, TWO52, mask;
26600 res = gen_reg_rtx (mode);
26601 emit_move_insn (res, operand1);
26603 /* xa = abs (operand1) */
26604 xa = ix86_expand_sse_fabs (res, &mask);
26606 /* if (!isless (xa, TWO52)) goto label; */
26607 TWO52 = ix86_gen_TWO52 (mode);
26608 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
26610 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
26611 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
26613 ix86_sse_copysign_to_positive (res, xa, res, mask);
26615 emit_label (label);
26616 LABEL_NUSES (label) = 1;
26618 emit_move_insn (operand0, res);
26621 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
26624 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
26626 /* C code for the stuff we expand below.
26627 double xa = fabs (x), x2;
26628 if (!isless (xa, TWO52))
26630 xa = xa + TWO52 - TWO52;
26631 x2 = copysign (xa, x);
26640 enum machine_mode mode = GET_MODE (operand0);
26641 rtx xa, TWO52, tmp, label, one, res, mask;
26643 TWO52 = ix86_gen_TWO52 (mode);
26645 /* Temporary for holding the result, initialized to the input
26646 operand to ease control flow. */
26647 res = gen_reg_rtx (mode);
26648 emit_move_insn (res, operand1);
26650 /* xa = abs (operand1) */
26651 xa = ix86_expand_sse_fabs (res, &mask);
26653 /* if (!isless (xa, TWO52)) goto label; */
26654 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
26656 /* xa = xa + TWO52 - TWO52; */
26657 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
26658 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
26660 /* xa = copysign (xa, operand1) */
26661 ix86_sse_copysign_to_positive (xa, xa, res, mask);
26663 /* generate 1.0 or -1.0 */
26664 one = force_reg (mode,
26665 const_double_from_real_value (do_floor
26666 ? dconst1 : dconstm1, mode));
26668 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
26669 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
26670 emit_insn (gen_rtx_SET (VOIDmode, tmp,
26671 gen_rtx_AND (mode, one, tmp)));
26672 /* We always need to subtract here to preserve signed zero. */
26673 tmp = expand_simple_binop (mode, MINUS,
26674 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
26675 emit_move_insn (res, tmp);
26677 emit_label (label);
26678 LABEL_NUSES (label) = 1;
26680 emit_move_insn (operand0, res);
26683 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
26686 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
26688 /* C code for the stuff we expand below.
26689 double xa = fabs (x), x2;
26690 if (!isless (xa, TWO52))
26692 x2 = (double)(long)x;
26699 if (HONOR_SIGNED_ZEROS (mode))
26700 return copysign (x2, x);
26703 enum machine_mode mode = GET_MODE (operand0);
26704 rtx xa, xi, TWO52, tmp, label, one, res, mask;
26706 TWO52 = ix86_gen_TWO52 (mode);
26708 /* Temporary for holding the result, initialized to the input
26709 operand to ease control flow. */
26710 res = gen_reg_rtx (mode);
26711 emit_move_insn (res, operand1);
26713 /* xa = abs (operand1) */
26714 xa = ix86_expand_sse_fabs (res, &mask);
26716 /* if (!isless (xa, TWO52)) goto label; */
26717 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
26719 /* xa = (double)(long)x */
26720 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
26721 expand_fix (xi, res, 0);
26722 expand_float (xa, xi, 0);
26725 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
26727 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
26728 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
26729 emit_insn (gen_rtx_SET (VOIDmode, tmp,
26730 gen_rtx_AND (mode, one, tmp)));
26731 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
26732 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
26733 emit_move_insn (res, tmp);
26735 if (HONOR_SIGNED_ZEROS (mode))
26736 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
26738 emit_label (label);
26739 LABEL_NUSES (label) = 1;
26741 emit_move_insn (operand0, res);
26744 /* Expand SSE sequence for computing round from OPERAND1 storing
26745 into OPERAND0. Sequence that works without relying on DImode truncation
26746 via cvttsd2siq that is only available on 64bit targets. */
26748 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
26750 /* C code for the stuff we expand below.
26751 double xa = fabs (x), xa2, x2;
26752 if (!isless (xa, TWO52))
26754 Using the absolute value and copying back sign makes
26755 -0.0 -> -0.0 correct.
26756 xa2 = xa + TWO52 - TWO52;
26761 else if (dxa > 0.5)
26763 x2 = copysign (xa2, x);
26766 enum machine_mode mode = GET_MODE (operand0);
26767 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
26769 TWO52 = ix86_gen_TWO52 (mode);
26771 /* Temporary for holding the result, initialized to the input
26772 operand to ease control flow. */
26773 res = gen_reg_rtx (mode);
26774 emit_move_insn (res, operand1);
26776 /* xa = abs (operand1) */
26777 xa = ix86_expand_sse_fabs (res, &mask);
26779 /* if (!isless (xa, TWO52)) goto label; */
26780 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
26782 /* xa2 = xa + TWO52 - TWO52; */
26783 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
26784 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
26786 /* dxa = xa2 - xa; */
26787 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
26789 /* generate 0.5, 1.0 and -0.5 */
26790 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
26791 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
26792 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
26796 tmp = gen_reg_rtx (mode);
26797 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
26798 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
26799 emit_insn (gen_rtx_SET (VOIDmode, tmp,
26800 gen_rtx_AND (mode, one, tmp)));
26801 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
26802 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
26803 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
26804 emit_insn (gen_rtx_SET (VOIDmode, tmp,
26805 gen_rtx_AND (mode, one, tmp)));
26806 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
26808 /* res = copysign (xa2, operand1) */
26809 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
26811 emit_label (label);
26812 LABEL_NUSES (label) = 1;
26814 emit_move_insn (operand0, res);
26817 /* Expand SSE sequence for computing trunc from OPERAND1 storing
26820 ix86_expand_trunc (rtx operand0, rtx operand1)
26822 /* C code for SSE variant we expand below.
26823 double xa = fabs (x), x2;
26824 if (!isless (xa, TWO52))
26826 x2 = (double)(long)x;
26827 if (HONOR_SIGNED_ZEROS (mode))
26828 return copysign (x2, x);
26831 enum machine_mode mode = GET_MODE (operand0);
26832 rtx xa, xi, TWO52, label, res, mask;
26834 TWO52 = ix86_gen_TWO52 (mode);
26836 /* Temporary for holding the result, initialized to the input
26837 operand to ease control flow. */
26838 res = gen_reg_rtx (mode);
26839 emit_move_insn (res, operand1);
26841 /* xa = abs (operand1) */
26842 xa = ix86_expand_sse_fabs (res, &mask);
26844 /* if (!isless (xa, TWO52)) goto label; */
26845 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
26847 /* x = (double)(long)x */
26848 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
26849 expand_fix (xi, res, 0);
26850 expand_float (res, xi, 0);
26852 if (HONOR_SIGNED_ZEROS (mode))
26853 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
26855 emit_label (label);
26856 LABEL_NUSES (label) = 1;
26858 emit_move_insn (operand0, res);
26861 /* Expand SSE sequence for computing trunc from OPERAND1 storing
26864 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
26866 enum machine_mode mode = GET_MODE (operand0);
26867 rtx xa, mask, TWO52, label, one, res, smask, tmp;
26869 /* C code for SSE variant we expand below.
26870 double xa = fabs (x), x2;
26871 if (!isless (xa, TWO52))
26873 xa2 = xa + TWO52 - TWO52;
26877 x2 = copysign (xa2, x);
26881 TWO52 = ix86_gen_TWO52 (mode);
26883 /* Temporary for holding the result, initialized to the input
26884 operand to ease control flow. */
26885 res = gen_reg_rtx (mode);
26886 emit_move_insn (res, operand1);
26888 /* xa = abs (operand1) */
26889 xa = ix86_expand_sse_fabs (res, &smask);
26891 /* if (!isless (xa, TWO52)) goto label; */
26892 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
26894 /* res = xa + TWO52 - TWO52; */
26895 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
26896 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
26897 emit_move_insn (res, tmp);
26900 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
26902 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
26903 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
26904 emit_insn (gen_rtx_SET (VOIDmode, mask,
26905 gen_rtx_AND (mode, mask, one)));
26906 tmp = expand_simple_binop (mode, MINUS,
26907 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
26908 emit_move_insn (res, tmp);
26910 /* res = copysign (res, operand1) */
26911 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
26913 emit_label (label);
26914 LABEL_NUSES (label) = 1;
26916 emit_move_insn (operand0, res);
26919 /* Expand SSE sequence for computing round from OPERAND1 storing
26922 ix86_expand_round (rtx operand0, rtx operand1)
26924 /* C code for the stuff we're doing below:
26925 double xa = fabs (x);
26926 if (!isless (xa, TWO52))
26928 xa = (double)(long)(xa + nextafter (0.5, 0.0));
26929 return copysign (xa, x);
26931 enum machine_mode mode = GET_MODE (operand0);
26932 rtx res, TWO52, xa, label, xi, half, mask;
26933 const struct real_format *fmt;
26934 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
26936 /* Temporary for holding the result, initialized to the input
26937 operand to ease control flow. */
26938 res = gen_reg_rtx (mode);
26939 emit_move_insn (res, operand1);
26941 TWO52 = ix86_gen_TWO52 (mode);
26942 xa = ix86_expand_sse_fabs (res, &mask);
26943 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
26945 /* load nextafter (0.5, 0.0) */
26946 fmt = REAL_MODE_FORMAT (mode);
26947 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
26948 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
26950 /* xa = xa + 0.5 */
26951 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
26952 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
26954 /* xa = (double)(int64_t)xa */
26955 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
26956 expand_fix (xi, xa, 0);
26957 expand_float (xa, xi, 0);
26959 /* res = copysign (xa, operand1) */
26960 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
26962 emit_label (label);
26963 LABEL_NUSES (label) = 1;
26965 emit_move_insn (operand0, res);
26969 /* Validate whether a SSE5 instruction is valid or not.
26970 OPERANDS is the array of operands.
26971 NUM is the number of operands.
26972 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
26973 NUM_MEMORY is the maximum number of memory operands to accept.
26974 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
26977 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
26978 bool uses_oc0, int num_memory, bool commutative)
26984 /* Count the number of memory arguments */
26987 for (i = 0; i < num; i++)
26989 enum machine_mode mode = GET_MODE (operands[i]);
26990 if (register_operand (operands[i], mode))
26993 else if (memory_operand (operands[i], mode))
26995 mem_mask |= (1 << i);
27001 rtx pattern = PATTERN (insn);
27003 /* allow 0 for pcmov */
27004 if (GET_CODE (pattern) != SET
27005 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
27007 || operands[i] != CONST0_RTX (mode))
27012 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
27013 a memory operation. */
27014 if (num_memory < 0)
27016 num_memory = -num_memory;
27017 if ((mem_mask & (1 << (num-1))) != 0)
27019 mem_mask &= ~(1 << (num-1));
27024 /* If there were no memory operations, allow the insn */
27028 /* Do not allow the destination register to be a memory operand. */
27029 else if (mem_mask & (1 << 0))
27032 /* If there are too many memory operations, disallow the instruction. While
27033 the hardware only allows 1 memory reference, before register allocation
27034 for some insns, we allow two memory operations sometimes in order to allow
27035 code like the following to be optimized:
27037 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
27039 or similar cases that are vectorized into using the fmaddss
27041 else if (mem_count > num_memory)
27044 /* Don't allow more than one memory operation if not optimizing. */
27045 else if (mem_count > 1 && !optimize)
27048 else if (num == 4 && mem_count == 1)
27050 /* formats (destination is the first argument), example fmaddss:
27051 xmm1, xmm1, xmm2, xmm3/mem
27052 xmm1, xmm1, xmm2/mem, xmm3
27053 xmm1, xmm2, xmm3/mem, xmm1
27054 xmm1, xmm2/mem, xmm3, xmm1 */
27056 return ((mem_mask == (1 << 1))
27057 || (mem_mask == (1 << 2))
27058 || (mem_mask == (1 << 3)));
27060 /* format, example pmacsdd:
27061 xmm1, xmm2, xmm3/mem, xmm1 */
27063 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
27065 return (mem_mask == (1 << 2));
27068 else if (num == 4 && num_memory == 2)
27070 /* If there are two memory operations, we can load one of the memory ops
27071 into the destination register. This is for optimizing the
27072 multiply/add ops, which the combiner has optimized both the multiply
27073 and the add insns to have a memory operation. We have to be careful
27074 that the destination doesn't overlap with the inputs. */
27075 rtx op0 = operands[0];
27077 if (reg_mentioned_p (op0, operands[1])
27078 || reg_mentioned_p (op0, operands[2])
27079 || reg_mentioned_p (op0, operands[3]))
27082 /* formats (destination is the first argument), example fmaddss:
27083 xmm1, xmm1, xmm2, xmm3/mem
27084 xmm1, xmm1, xmm2/mem, xmm3
27085 xmm1, xmm2, xmm3/mem, xmm1
27086 xmm1, xmm2/mem, xmm3, xmm1
27088 For the oc0 case, we will load either operands[1] or operands[3] into
27089 operands[0], so any combination of 2 memory operands is ok. */
27093 /* format, example pmacsdd:
27094 xmm1, xmm2, xmm3/mem, xmm1
27096 For the integer multiply/add instructions be more restrictive and
27097 require operands[2] and operands[3] to be the memory operands. */
27099 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
27101 return (mem_mask == ((1 << 2) | (1 << 3)));
27104 else if (num == 3 && num_memory == 1)
27106 /* formats, example protb:
27107 xmm1, xmm2, xmm3/mem
27108 xmm1, xmm2/mem, xmm3 */
27110 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
27112 /* format, example comeq:
27113 xmm1, xmm2, xmm3/mem */
27115 return (mem_mask == (1 << 2));
27119 gcc_unreachable ();
27125 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
27126 hardware will allow by using the destination register to load one of the
27127 memory operations. Presently this is used by the multiply/add routines to
27128 allow 2 memory references. */
27131 ix86_expand_sse5_multiple_memory (rtx operands[],
27133 enum machine_mode mode)
27135 rtx op0 = operands[0];
27137 || memory_operand (op0, mode)
27138 || reg_mentioned_p (op0, operands[1])
27139 || reg_mentioned_p (op0, operands[2])
27140 || reg_mentioned_p (op0, operands[3]))
27141 gcc_unreachable ();
27143 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
27144 the destination register. */
27145 if (memory_operand (operands[1], mode))
27147 emit_move_insn (op0, operands[1]);
27150 else if (memory_operand (operands[3], mode))
27152 emit_move_insn (op0, operands[3]);
27156 gcc_unreachable ();
27162 /* Table of valid machine attributes. */
27163 static const struct attribute_spec ix86_attribute_table[] =
27165 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
27166 /* Stdcall attribute says callee is responsible for popping arguments
27167 if they are not variable. */
27168 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
27169 /* Fastcall attribute says callee is responsible for popping arguments
27170 if they are not variable. */
27171 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
27172 /* Cdecl attribute says the callee is a normal C declaration */
27173 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
27174 /* Regparm attribute specifies how many integer arguments are to be
27175 passed in registers. */
27176 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
27177 /* Sseregparm attribute says we are using x86_64 calling conventions
27178 for FP arguments. */
27179 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
27180 /* force_align_arg_pointer says this function realigns the stack at entry. */
27181 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
27182 false, true, true, ix86_handle_cconv_attribute },
27183 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
27184 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
27185 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
27186 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
27188 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
27189 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
27190 #ifdef SUBTARGET_ATTRIBUTE_TABLE
27191 SUBTARGET_ATTRIBUTE_TABLE,
27193 /* ms_abi and sysv_abi calling convention function attributes. */
27194 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
27195 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
27197 { NULL, 0, 0, false, false, false, NULL }
27200 /* Implement targetm.vectorize.builtin_vectorization_cost. */
27202 x86_builtin_vectorization_cost (bool runtime_test)
27204 /* If the branch of the runtime test is taken - i.e. - the vectorized
27205 version is skipped - this incurs a misprediction cost (because the
27206 vectorized version is expected to be the fall-through). So we subtract
27207 the latency of a mispredicted branch from the costs that are incured
27208 when the vectorized version is executed.
27210 TODO: The values in individual target tables have to be tuned or new
27211 fields may be needed. For eg. on K8, the default branch path is the
27212 not-taken path. If the taken path is predicted correctly, the minimum
27213 penalty of going down the taken-path is 1 cycle. If the taken-path is
27214 not predicted correctly, then the minimum penalty is 10 cycles. */
27218 return (-(ix86_cost->cond_taken_branch_cost));
27224 /* This function returns the calling abi specific va_list type node.
27225 It returns the FNDECL specific va_list type. */
27228 ix86_fn_abi_va_list (tree fndecl)
27233 return va_list_type_node;
27234 gcc_assert (fndecl != NULL_TREE);
27235 abi = ix86_function_abi ((const_tree) fndecl);
27238 return ms_va_list_type_node;
27240 return sysv_va_list_type_node;
27243 /* Returns the canonical va_list type specified by TYPE. If there
27244 is no valid TYPE provided, it return NULL_TREE. */
27247 ix86_canonical_va_list_type (tree type)
27251 /* Resolve references and pointers to va_list type. */
27252 if (INDIRECT_REF_P (type))
27253 type = TREE_TYPE (type);
27254 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
27255 type = TREE_TYPE (type);
27259 wtype = va_list_type_node;
27260 gcc_assert (wtype != NULL_TREE);
27262 if (TREE_CODE (wtype) == ARRAY_TYPE)
27264 /* If va_list is an array type, the argument may have decayed
27265 to a pointer type, e.g. by being passed to another function.
27266 In that case, unwrap both types so that we can compare the
27267 underlying records. */
27268 if (TREE_CODE (htype) == ARRAY_TYPE
27269 || POINTER_TYPE_P (htype))
27271 wtype = TREE_TYPE (wtype);
27272 htype = TREE_TYPE (htype);
27275 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
27276 return va_list_type_node;
27277 wtype = sysv_va_list_type_node;
27278 gcc_assert (wtype != NULL_TREE);
27280 if (TREE_CODE (wtype) == ARRAY_TYPE)
27282 /* If va_list is an array type, the argument may have decayed
27283 to a pointer type, e.g. by being passed to another function.
27284 In that case, unwrap both types so that we can compare the
27285 underlying records. */
27286 if (TREE_CODE (htype) == ARRAY_TYPE
27287 || POINTER_TYPE_P (htype))
27289 wtype = TREE_TYPE (wtype);
27290 htype = TREE_TYPE (htype);
27293 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
27294 return sysv_va_list_type_node;
27295 wtype = ms_va_list_type_node;
27296 gcc_assert (wtype != NULL_TREE);
27298 if (TREE_CODE (wtype) == ARRAY_TYPE)
27300 /* If va_list is an array type, the argument may have decayed
27301 to a pointer type, e.g. by being passed to another function.
27302 In that case, unwrap both types so that we can compare the
27303 underlying records. */
27304 if (TREE_CODE (htype) == ARRAY_TYPE
27305 || POINTER_TYPE_P (htype))
27307 wtype = TREE_TYPE (wtype);
27308 htype = TREE_TYPE (htype);
27311 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
27312 return ms_va_list_type_node;
27315 return std_canonical_va_list_type (type);
27318 /* Iterate through the target-specific builtin types for va_list.
27319 IDX denotes the iterator, *PTREE is set to the result type of
27320 the va_list builtin, and *PNAME to its internal type.
27321 Returns zero if there is no element for this index, otherwise
27322 IDX should be increased upon the next call.
27323 Note, do not iterate a base builtin's name like __builtin_va_list.
27324 Used from c_common_nodes_and_builtins. */
27327 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
27333 *ptree = ms_va_list_type_node;
27334 *pname = "__builtin_ms_va_list";
27337 *ptree = sysv_va_list_type_node;
27338 *pname = "__builtin_sysv_va_list";
27346 /* Initialize the GCC target structure. */
27347 #undef TARGET_RETURN_IN_MEMORY
27348 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
27350 #undef TARGET_ATTRIBUTE_TABLE
27351 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
27352 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
27353 # undef TARGET_MERGE_DECL_ATTRIBUTES
27354 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
27357 #undef TARGET_COMP_TYPE_ATTRIBUTES
27358 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
27360 #undef TARGET_INIT_BUILTINS
27361 #define TARGET_INIT_BUILTINS ix86_init_builtins
27362 #undef TARGET_EXPAND_BUILTIN
27363 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
27365 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
27366 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
27367 ix86_builtin_vectorized_function
27369 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
27370 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
27372 #undef TARGET_BUILTIN_RECIPROCAL
27373 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
27375 #undef TARGET_ASM_FUNCTION_EPILOGUE
27376 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
27378 #undef TARGET_ENCODE_SECTION_INFO
27379 #ifndef SUBTARGET_ENCODE_SECTION_INFO
27380 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
27382 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
27385 #undef TARGET_ASM_OPEN_PAREN
27386 #define TARGET_ASM_OPEN_PAREN ""
27387 #undef TARGET_ASM_CLOSE_PAREN
27388 #define TARGET_ASM_CLOSE_PAREN ""
27390 #undef TARGET_ASM_ALIGNED_HI_OP
27391 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
27392 #undef TARGET_ASM_ALIGNED_SI_OP
27393 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
27395 #undef TARGET_ASM_ALIGNED_DI_OP
27396 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
27399 #undef TARGET_ASM_UNALIGNED_HI_OP
27400 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
27401 #undef TARGET_ASM_UNALIGNED_SI_OP
27402 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
27403 #undef TARGET_ASM_UNALIGNED_DI_OP
27404 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
27406 #undef TARGET_SCHED_ADJUST_COST
27407 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
27408 #undef TARGET_SCHED_ISSUE_RATE
27409 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
27410 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
27411 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
27412 ia32_multipass_dfa_lookahead
27414 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
27415 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
27418 #undef TARGET_HAVE_TLS
27419 #define TARGET_HAVE_TLS true
27421 #undef TARGET_CANNOT_FORCE_CONST_MEM
27422 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
27423 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
27424 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
27426 #undef TARGET_DELEGITIMIZE_ADDRESS
27427 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
27429 #undef TARGET_MS_BITFIELD_LAYOUT_P
27430 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
27433 #undef TARGET_BINDS_LOCAL_P
27434 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
27436 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
27437 #undef TARGET_BINDS_LOCAL_P
27438 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
27441 #undef TARGET_ASM_OUTPUT_MI_THUNK
27442 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
27443 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
27444 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
27446 #undef TARGET_ASM_FILE_START
27447 #define TARGET_ASM_FILE_START x86_file_start
27449 #undef TARGET_DEFAULT_TARGET_FLAGS
27450 #define TARGET_DEFAULT_TARGET_FLAGS \
27452 | TARGET_SUBTARGET_DEFAULT \
27453 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
27455 #undef TARGET_HANDLE_OPTION
27456 #define TARGET_HANDLE_OPTION ix86_handle_option
27458 #undef TARGET_RTX_COSTS
27459 #define TARGET_RTX_COSTS ix86_rtx_costs
27460 #undef TARGET_ADDRESS_COST
27461 #define TARGET_ADDRESS_COST ix86_address_cost
27463 #undef TARGET_FIXED_CONDITION_CODE_REGS
27464 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
27465 #undef TARGET_CC_MODES_COMPATIBLE
27466 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
27468 #undef TARGET_MACHINE_DEPENDENT_REORG
27469 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
27471 #undef TARGET_BUILD_BUILTIN_VA_LIST
27472 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
27474 #undef TARGET_FN_ABI_VA_LIST
27475 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
27477 #undef TARGET_CANONICAL_VA_LIST_TYPE
27478 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
27480 #undef TARGET_EXPAND_BUILTIN_VA_START
27481 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
27483 #undef TARGET_MD_ASM_CLOBBERS
27484 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
27486 #undef TARGET_PROMOTE_PROTOTYPES
27487 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
27488 #undef TARGET_STRUCT_VALUE_RTX
27489 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
27490 #undef TARGET_SETUP_INCOMING_VARARGS
27491 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
27492 #undef TARGET_MUST_PASS_IN_STACK
27493 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
27494 #undef TARGET_PASS_BY_REFERENCE
27495 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
27496 #undef TARGET_INTERNAL_ARG_POINTER
27497 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
27498 #undef TARGET_UPDATE_STACK_BOUNDARY
27499 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
27500 #undef TARGET_GET_DRAP_RTX
27501 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
27502 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
27503 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
27504 #undef TARGET_STRICT_ARGUMENT_NAMING
27505 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
27507 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
27508 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
27510 #undef TARGET_SCALAR_MODE_SUPPORTED_P
27511 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
27513 #undef TARGET_VECTOR_MODE_SUPPORTED_P
27514 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
27516 #undef TARGET_C_MODE_FOR_SUFFIX
27517 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
27520 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
27521 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
27524 #ifdef SUBTARGET_INSERT_ATTRIBUTES
27525 #undef TARGET_INSERT_ATTRIBUTES
27526 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
27529 #undef TARGET_MANGLE_TYPE
27530 #define TARGET_MANGLE_TYPE ix86_mangle_type
27532 #undef TARGET_STACK_PROTECT_FAIL
27533 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
27535 #undef TARGET_FUNCTION_VALUE
27536 #define TARGET_FUNCTION_VALUE ix86_function_value
27538 #undef TARGET_SECONDARY_RELOAD
27539 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
27541 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
27542 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
27544 #undef TARGET_SET_CURRENT_FUNCTION
27545 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
27547 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
27548 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_option_attribute_p
27550 #undef TARGET_OPTION_SAVE
27551 #define TARGET_OPTION_SAVE ix86_function_specific_save
27553 #undef TARGET_OPTION_RESTORE
27554 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
27556 #undef TARGET_OPTION_PRINT
27557 #define TARGET_OPTION_PRINT ix86_function_specific_print
27559 #undef TARGET_OPTION_CAN_INLINE_P
27560 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
27562 #undef TARGET_OPTION_COLD_ATTRIBUTE_SETS_OPTIMIZATION
27563 #define TARGET_OPTION_COLD_ATTRIBUTE_SETS_OPTIMIZATION true
27565 #undef TARGET_OPTION_HOT_ATTRIBUTE_SETS_OPTIMIZATION
27566 #define TARGET_OPTION_HOT_ATTRIBUTE_SETS_OPTIMIZATION true
27568 struct gcc_target targetm = TARGET_INITIALIZER;
27570 #include "gt-i386.h"
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