1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
53 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of storing fp registers
995 in SFmode, DFmode and XFmode */
996 2, /* cost of moving MMX register */
997 {6, 6}, /* cost of loading MMX registers
998 in SImode and DImode */
999 {4, 4}, /* cost of storing MMX registers
1000 in SImode and DImode */
1001 2, /* cost of moving SSE register */
1002 {6, 6, 6}, /* cost of loading SSE registers
1003 in SImode, DImode and TImode */
1004 {4, 4, 4}, /* cost of storing SSE registers
1005 in SImode, DImode and TImode */
1006 2, /* MMX or SSE register to integer */
1007 32, /* size of l1 cache. */
1008 2048, /* size of l2 cache. */
1009 128, /* size of prefetch block */
1010 8, /* number of parallel prefetches */
1011 3, /* Branch cost */
1012 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1013 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1014 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1015 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1016 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1017 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1018 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1019 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 {{libcall, {{8, loop}, {15, unrolled_loop},
1022 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1023 {libcall, {{24, loop}, {32, unrolled_loop},
1024 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1025 1, /* scalar_stmt_cost. */
1026 1, /* scalar load_cost. */
1027 1, /* scalar_store_cost. */
1028 1, /* vec_stmt_cost. */
1029 1, /* vec_to_scalar_cost. */
1030 1, /* scalar_to_vec_cost. */
1031 1, /* vec_align_load_cost. */
1032 2, /* vec_unalign_load_cost. */
1033 1, /* vec_store_cost. */
1034 3, /* cond_taken_branch_cost. */
1035 1, /* cond_not_taken_branch_cost. */
1039 struct processor_costs atom_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1042 COSTS_N_INSNS (1), /* variable shift costs */
1043 COSTS_N_INSNS (1), /* constant shift costs */
1044 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1045 COSTS_N_INSNS (4), /* HI */
1046 COSTS_N_INSNS (3), /* SI */
1047 COSTS_N_INSNS (4), /* DI */
1048 COSTS_N_INSNS (2)}, /* other */
1049 0, /* cost of multiply per each bit set */
1050 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1051 COSTS_N_INSNS (26), /* HI */
1052 COSTS_N_INSNS (42), /* SI */
1053 COSTS_N_INSNS (74), /* DI */
1054 COSTS_N_INSNS (74)}, /* other */
1055 COSTS_N_INSNS (1), /* cost of movsx */
1056 COSTS_N_INSNS (1), /* cost of movzx */
1057 8, /* "large" insn */
1058 17, /* MOVE_RATIO */
1059 2, /* cost for loading QImode using movzbl */
1060 {4, 4, 4}, /* cost of loading integer registers
1061 in QImode, HImode and SImode.
1062 Relative to reg-reg move (2). */
1063 {4, 4, 4}, /* cost of storing integer registers */
1064 4, /* cost of reg,reg fld/fst */
1065 {12, 12, 12}, /* cost of loading fp registers
1066 in SFmode, DFmode and XFmode */
1067 {6, 6, 8}, /* cost of storing fp registers
1068 in SFmode, DFmode and XFmode */
1069 2, /* cost of moving MMX register */
1070 {8, 8}, /* cost of loading MMX registers
1071 in SImode and DImode */
1072 {8, 8}, /* cost of storing MMX registers
1073 in SImode and DImode */
1074 2, /* cost of moving SSE register */
1075 {8, 8, 8}, /* cost of loading SSE registers
1076 in SImode, DImode and TImode */
1077 {8, 8, 8}, /* cost of storing SSE registers
1078 in SImode, DImode and TImode */
1079 5, /* MMX or SSE register to integer */
1080 32, /* size of l1 cache. */
1081 256, /* size of l2 cache. */
1082 64, /* size of prefetch block */
1083 6, /* number of parallel prefetches */
1084 3, /* Branch cost */
1085 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1086 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1087 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1088 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1089 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1090 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1091 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1092 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1093 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1094 {{libcall, {{8, loop}, {15, unrolled_loop},
1095 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1096 {libcall, {{24, loop}, {32, unrolled_loop},
1097 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1098 1, /* scalar_stmt_cost. */
1099 1, /* scalar load_cost. */
1100 1, /* scalar_store_cost. */
1101 1, /* vec_stmt_cost. */
1102 1, /* vec_to_scalar_cost. */
1103 1, /* scalar_to_vec_cost. */
1104 1, /* vec_align_load_cost. */
1105 2, /* vec_unalign_load_cost. */
1106 1, /* vec_store_cost. */
1107 3, /* cond_taken_branch_cost. */
1108 1, /* cond_not_taken_branch_cost. */
1111 /* Generic64 should produce code tuned for Nocona and K8. */
1113 struct processor_costs generic64_cost = {
1114 COSTS_N_INSNS (1), /* cost of an add instruction */
1115 /* On all chips taken into consideration lea is 2 cycles and more. With
1116 this cost however our current implementation of synth_mult results in
1117 use of unnecessary temporary registers causing regression on several
1118 SPECfp benchmarks. */
1119 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1120 COSTS_N_INSNS (1), /* variable shift costs */
1121 COSTS_N_INSNS (1), /* constant shift costs */
1122 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1123 COSTS_N_INSNS (4), /* HI */
1124 COSTS_N_INSNS (3), /* SI */
1125 COSTS_N_INSNS (4), /* DI */
1126 COSTS_N_INSNS (2)}, /* other */
1127 0, /* cost of multiply per each bit set */
1128 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1129 COSTS_N_INSNS (26), /* HI */
1130 COSTS_N_INSNS (42), /* SI */
1131 COSTS_N_INSNS (74), /* DI */
1132 COSTS_N_INSNS (74)}, /* other */
1133 COSTS_N_INSNS (1), /* cost of movsx */
1134 COSTS_N_INSNS (1), /* cost of movzx */
1135 8, /* "large" insn */
1136 17, /* MOVE_RATIO */
1137 4, /* cost for loading QImode using movzbl */
1138 {4, 4, 4}, /* cost of loading integer registers
1139 in QImode, HImode and SImode.
1140 Relative to reg-reg move (2). */
1141 {4, 4, 4}, /* cost of storing integer registers */
1142 4, /* cost of reg,reg fld/fst */
1143 {12, 12, 12}, /* cost of loading fp registers
1144 in SFmode, DFmode and XFmode */
1145 {6, 6, 8}, /* cost of storing fp registers
1146 in SFmode, DFmode and XFmode */
1147 2, /* cost of moving MMX register */
1148 {8, 8}, /* cost of loading MMX registers
1149 in SImode and DImode */
1150 {8, 8}, /* cost of storing MMX registers
1151 in SImode and DImode */
1152 2, /* cost of moving SSE register */
1153 {8, 8, 8}, /* cost of loading SSE registers
1154 in SImode, DImode and TImode */
1155 {8, 8, 8}, /* cost of storing SSE registers
1156 in SImode, DImode and TImode */
1157 5, /* MMX or SSE register to integer */
1158 32, /* size of l1 cache. */
1159 512, /* size of l2 cache. */
1160 64, /* size of prefetch block */
1161 6, /* number of parallel prefetches */
1162 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1163 is increased to perhaps more appropriate value of 5. */
1164 3, /* Branch cost */
1165 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1166 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1167 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1168 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1169 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1170 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1171 {DUMMY_STRINGOP_ALGS,
1172 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1173 {DUMMY_STRINGOP_ALGS,
1174 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1175 1, /* scalar_stmt_cost. */
1176 1, /* scalar load_cost. */
1177 1, /* scalar_store_cost. */
1178 1, /* vec_stmt_cost. */
1179 1, /* vec_to_scalar_cost. */
1180 1, /* scalar_to_vec_cost. */
1181 1, /* vec_align_load_cost. */
1182 2, /* vec_unalign_load_cost. */
1183 1, /* vec_store_cost. */
1184 3, /* cond_taken_branch_cost. */
1185 1, /* cond_not_taken_branch_cost. */
1188 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1190 struct processor_costs generic32_cost = {
1191 COSTS_N_INSNS (1), /* cost of an add instruction */
1192 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1193 COSTS_N_INSNS (1), /* variable shift costs */
1194 COSTS_N_INSNS (1), /* constant shift costs */
1195 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1196 COSTS_N_INSNS (4), /* HI */
1197 COSTS_N_INSNS (3), /* SI */
1198 COSTS_N_INSNS (4), /* DI */
1199 COSTS_N_INSNS (2)}, /* other */
1200 0, /* cost of multiply per each bit set */
1201 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1202 COSTS_N_INSNS (26), /* HI */
1203 COSTS_N_INSNS (42), /* SI */
1204 COSTS_N_INSNS (74), /* DI */
1205 COSTS_N_INSNS (74)}, /* other */
1206 COSTS_N_INSNS (1), /* cost of movsx */
1207 COSTS_N_INSNS (1), /* cost of movzx */
1208 8, /* "large" insn */
1209 17, /* MOVE_RATIO */
1210 4, /* cost for loading QImode using movzbl */
1211 {4, 4, 4}, /* cost of loading integer registers
1212 in QImode, HImode and SImode.
1213 Relative to reg-reg move (2). */
1214 {4, 4, 4}, /* cost of storing integer registers */
1215 4, /* cost of reg,reg fld/fst */
1216 {12, 12, 12}, /* cost of loading fp registers
1217 in SFmode, DFmode and XFmode */
1218 {6, 6, 8}, /* cost of storing fp registers
1219 in SFmode, DFmode and XFmode */
1220 2, /* cost of moving MMX register */
1221 {8, 8}, /* cost of loading MMX registers
1222 in SImode and DImode */
1223 {8, 8}, /* cost of storing MMX registers
1224 in SImode and DImode */
1225 2, /* cost of moving SSE register */
1226 {8, 8, 8}, /* cost of loading SSE registers
1227 in SImode, DImode and TImode */
1228 {8, 8, 8}, /* cost of storing SSE registers
1229 in SImode, DImode and TImode */
1230 5, /* MMX or SSE register to integer */
1231 32, /* size of l1 cache. */
1232 256, /* size of l2 cache. */
1233 64, /* size of prefetch block */
1234 6, /* number of parallel prefetches */
1235 3, /* Branch cost */
1236 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1237 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1238 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1239 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1240 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1241 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1242 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1243 DUMMY_STRINGOP_ALGS},
1244 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1245 DUMMY_STRINGOP_ALGS},
1246 1, /* scalar_stmt_cost. */
1247 1, /* scalar load_cost. */
1248 1, /* scalar_store_cost. */
1249 1, /* vec_stmt_cost. */
1250 1, /* vec_to_scalar_cost. */
1251 1, /* scalar_to_vec_cost. */
1252 1, /* vec_align_load_cost. */
1253 2, /* vec_unalign_load_cost. */
1254 1, /* vec_store_cost. */
1255 3, /* cond_taken_branch_cost. */
1256 1, /* cond_not_taken_branch_cost. */
1259 const struct processor_costs *ix86_cost = &pentium_cost;
1261 /* Processor feature/optimization bitmasks. */
1262 #define m_386 (1<<PROCESSOR_I386)
1263 #define m_486 (1<<PROCESSOR_I486)
1264 #define m_PENT (1<<PROCESSOR_PENTIUM)
1265 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1266 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1267 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1268 #define m_CORE2 (1<<PROCESSOR_CORE2)
1269 #define m_ATOM (1<<PROCESSOR_ATOM)
1271 #define m_GEODE (1<<PROCESSOR_GEODE)
1272 #define m_K6 (1<<PROCESSOR_K6)
1273 #define m_K6_GEODE (m_K6 | m_GEODE)
1274 #define m_K8 (1<<PROCESSOR_K8)
1275 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1276 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1277 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1278 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1280 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1281 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1283 /* Generic instruction choice should be common subset of supported CPUs
1284 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1285 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1287 /* Feature tests against the various tunings. */
1288 unsigned char ix86_tune_features[X86_TUNE_LAST];
1290 /* Feature tests against the various tunings used to create ix86_tune_features
1291 based on the processor mask. */
1292 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1293 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1294 negatively, so enabling for Generic64 seems like good code size
1295 tradeoff. We can't enable it for 32bit generic because it does not
1296 work well with PPro base chips. */
1297 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1299 /* X86_TUNE_PUSH_MEMORY */
1300 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1301 | m_NOCONA | m_CORE2 | m_GENERIC,
1303 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1306 /* X86_TUNE_UNROLL_STRLEN */
1307 m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
1308 | m_CORE2 | m_GENERIC,
1310 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1311 m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1313 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1314 on simulation result. But after P4 was made, no performance benefit
1315 was observed with branch hints. It also increases the code size.
1316 As a result, icc never generates branch hints. */
1319 /* X86_TUNE_DOUBLE_WITH_ADD */
1322 /* X86_TUNE_USE_SAHF */
1323 m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1324 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1327 partial dependencies. */
1328 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
1329 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1331 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1332 register stalls on Generic32 compilation setting as well. However
1333 in current implementation the partial register stalls are not eliminated
1334 very well - they can be introduced via subregs synthesized by combine
1335 and can happen in caller/callee saving sequences. Because this option
1336 pays back little on PPro based chips and is in conflict with partial reg
1337 dependencies used by Athlon/P4 based chips, it is better to leave it off
1338 for generic32 for now. */
1341 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1342 m_CORE2 | m_GENERIC,
1344 /* X86_TUNE_USE_HIMODE_FIOP */
1345 m_386 | m_486 | m_K6_GEODE,
1347 /* X86_TUNE_USE_SIMODE_FIOP */
1348 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),
1350 /* X86_TUNE_USE_MOV0 */
1353 /* X86_TUNE_USE_CLTD */
1354 ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),
1356 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1359 /* X86_TUNE_SPLIT_LONG_MOVES */
1362 /* X86_TUNE_READ_MODIFY_WRITE */
1365 /* X86_TUNE_READ_MODIFY */
1368 /* X86_TUNE_PROMOTE_QIMODE */
1369 m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
1370 | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,
1372 /* X86_TUNE_FAST_PREFIX */
1373 ~(m_PENT | m_486 | m_386),
1375 /* X86_TUNE_SINGLE_STRINGOP */
1376 m_386 | m_PENT4 | m_NOCONA,
1378 /* X86_TUNE_QIMODE_MATH */
1381 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1382 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1383 might be considered for Generic32 if our scheme for avoiding partial
1384 stalls was more effective. */
1387 /* X86_TUNE_PROMOTE_QI_REGS */
1390 /* X86_TUNE_PROMOTE_HI_REGS */
1393 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1394 m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
1395 | m_CORE2 | m_GENERIC,
1397 /* X86_TUNE_ADD_ESP_8 */
1398 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
1399 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_SUB_ESP_4 */
1402 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
1405 /* X86_TUNE_SUB_ESP_8 */
1406 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
1407 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1409 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1410 for DFmode copies */
1411 ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1412 | m_GENERIC | m_GEODE),
1414 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1415 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1417 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1418 conflict here in between PPro/Pentium4 based chips that thread 128bit
1419 SSE registers as single units versus K8 based chips that divide SSE
1420 registers to two 64bit halves. This knob promotes all store destinations
1421 to be 128bit to allow register renaming on 128bit SSE units, but usually
1422 results in one extra microop on 64bit SSE units. Experimental results
1423 shows that disabling this option on P4 brings over 20% SPECfp regression,
1424 while enabling it on K8 brings roughly 2.4% regression that can be partly
1425 masked by careful scheduling of moves. */
1426 m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
1429 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1432 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1433 are resolved on SSE register parts instead of whole registers, so we may
1434 maintain just lower part of scalar values in proper format leaving the
1435 upper part undefined. */
1438 /* X86_TUNE_SSE_TYPELESS_STORES */
1441 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1442 m_PPRO | m_PENT4 | m_NOCONA,
1444 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1445 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1447 /* X86_TUNE_PROLOGUE_USING_MOVE */
1448 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1450 /* X86_TUNE_EPILOGUE_USING_MOVE */
1451 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1453 /* X86_TUNE_SHIFT1 */
1456 /* X86_TUNE_USE_FFREEP */
1459 /* X86_TUNE_INTER_UNIT_MOVES */
1460 ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
1462 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1465 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1466 than 4 branch instructions in the 16 byte window. */
1467 m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
1470 /* X86_TUNE_SCHEDULE */
1471 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
1474 /* X86_TUNE_USE_BT */
1475 m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,
1477 /* X86_TUNE_USE_INCDEC */
1478 ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),
1480 /* X86_TUNE_PAD_RETURNS */
1481 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1483 /* X86_TUNE_EXT_80387_CONSTANTS */
1484 m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
1485 | m_CORE2 | m_GENERIC,
1487 /* X86_TUNE_SHORTEN_X87_SSE */
1490 /* X86_TUNE_AVOID_VECTOR_DECODE */
1493 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1494 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1497 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1498 vector path on AMD machines. */
1499 m_K8 | m_GENERIC64 | m_AMDFAM10,
1501 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1503 m_K8 | m_GENERIC64 | m_AMDFAM10,
1505 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1509 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1510 but one byte longer. */
1513 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1514 operand that cannot be represented using a modRM byte. The XOR
1515 replacement is long decoded, so this split helps here as well. */
1518 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1520 m_AMDFAM10 | m_GENERIC,
1522 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1523 from integer to FP. */
1526 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1527 with a subsequent conditional jump instruction into a single
1528 compare-and-branch uop. */
1531 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1532 will impact LEA instruction selection. */
1536 /* Feature tests against the various architecture variations. */
1537 unsigned char ix86_arch_features[X86_ARCH_LAST];
1539 /* Feature tests against the various architecture variations, used to create
1540 ix86_arch_features based on the processor mask. */
1541 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1542 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1543 ~(m_386 | m_486 | m_PENT | m_K6),
1545 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1548 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1551 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1554 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1558 static const unsigned int x86_accumulate_outgoing_args
1559 = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1562 static const unsigned int x86_arch_always_fancy_math_387
1563 = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1564 | m_NOCONA | m_CORE2 | m_GENERIC;
1566 static enum stringop_alg stringop_alg = no_stringop;
1568 /* In case the average insn count for single function invocation is
1569 lower than this constant, emit fast (but longer) prologue and
1571 #define FAST_PROLOGUE_INSN_COUNT 20
1573 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1574 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1575 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1576 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1578 /* Array of the smallest class containing reg number REGNO, indexed by
1579 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1581 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1583 /* ax, dx, cx, bx */
1584 AREG, DREG, CREG, BREG,
1585 /* si, di, bp, sp */
1586 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1588 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1589 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1592 /* flags, fpsr, fpcr, frame */
1593 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1595 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1598 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1601 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1602 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1603 /* SSE REX registers */
1604 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1608 /* The "default" register map used in 32bit mode. */
1610 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1612 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1613 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1614 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1615 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1616 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1617 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1618 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1621 /* The "default" register map used in 64bit mode. */
1623 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1625 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1626 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1627 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1628 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1629 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1630 8,9,10,11,12,13,14,15, /* extended integer registers */
1631 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1634 /* Define the register numbers to be used in Dwarf debugging information.
1635 The SVR4 reference port C compiler uses the following register numbers
1636 in its Dwarf output code:
1637 0 for %eax (gcc regno = 0)
1638 1 for %ecx (gcc regno = 2)
1639 2 for %edx (gcc regno = 1)
1640 3 for %ebx (gcc regno = 3)
1641 4 for %esp (gcc regno = 7)
1642 5 for %ebp (gcc regno = 6)
1643 6 for %esi (gcc regno = 4)
1644 7 for %edi (gcc regno = 5)
1645 The following three DWARF register numbers are never generated by
1646 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1647 believes these numbers have these meanings.
1648 8 for %eip (no gcc equivalent)
1649 9 for %eflags (gcc regno = 17)
1650 10 for %trapno (no gcc equivalent)
1651 It is not at all clear how we should number the FP stack registers
1652 for the x86 architecture. If the version of SDB on x86/svr4 were
1653 a bit less brain dead with respect to floating-point then we would
1654 have a precedent to follow with respect to DWARF register numbers
1655 for x86 FP registers, but the SDB on x86/svr4 is so completely
1656 broken with respect to FP registers that it is hardly worth thinking
1657 of it as something to strive for compatibility with.
1658 The version of x86/svr4 SDB I have at the moment does (partially)
1659 seem to believe that DWARF register number 11 is associated with
1660 the x86 register %st(0), but that's about all. Higher DWARF
1661 register numbers don't seem to be associated with anything in
1662 particular, and even for DWARF regno 11, SDB only seems to under-
1663 stand that it should say that a variable lives in %st(0) (when
1664 asked via an `=' command) if we said it was in DWARF regno 11,
1665 but SDB still prints garbage when asked for the value of the
1666 variable in question (via a `/' command).
1667 (Also note that the labels SDB prints for various FP stack regs
1668 when doing an `x' command are all wrong.)
1669 Note that these problems generally don't affect the native SVR4
1670 C compiler because it doesn't allow the use of -O with -g and
1671 because when it is *not* optimizing, it allocates a memory
1672 location for each floating-point variable, and the memory
1673 location is what gets described in the DWARF AT_location
1674 attribute for the variable in question.
1675 Regardless of the severe mental illness of the x86/svr4 SDB, we
1676 do something sensible here and we use the following DWARF
1677 register numbers. Note that these are all stack-top-relative
1679 11 for %st(0) (gcc regno = 8)
1680 12 for %st(1) (gcc regno = 9)
1681 13 for %st(2) (gcc regno = 10)
1682 14 for %st(3) (gcc regno = 11)
1683 15 for %st(4) (gcc regno = 12)
1684 16 for %st(5) (gcc regno = 13)
1685 17 for %st(6) (gcc regno = 14)
1686 18 for %st(7) (gcc regno = 15)
1688 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1690 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1691 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1692 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1693 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1694 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1695 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1696 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1699 /* Test and compare insns in i386.md store the information needed to
1700 generate branch and scc insns here. */
1702 rtx ix86_compare_op0 = NULL_RTX;
1703 rtx ix86_compare_op1 = NULL_RTX;
1705 /* Define parameter passing and return registers. */
1707 static int const x86_64_int_parameter_registers[6] =
1709 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1712 static int const x86_64_ms_abi_int_parameter_registers[4] =
1714 CX_REG, DX_REG, R8_REG, R9_REG
1717 static int const x86_64_int_return_registers[4] =
1719 AX_REG, DX_REG, DI_REG, SI_REG
1722 /* Define the structure for the machine field in struct function. */
1724 struct GTY(()) stack_local_entry {
1725 unsigned short mode;
1728 struct stack_local_entry *next;
1731 /* Structure describing stack frame layout.
1732 Stack grows downward:
1738 saved frame pointer if frame_pointer_needed
1739 <- HARD_FRAME_POINTER
1748 [va_arg registers] (
1749 > to_allocate <- FRAME_POINTER
1761 HOST_WIDE_INT frame;
1763 int outgoing_arguments_size;
1766 HOST_WIDE_INT to_allocate;
1767 /* The offsets relative to ARG_POINTER. */
1768 HOST_WIDE_INT frame_pointer_offset;
1769 HOST_WIDE_INT hard_frame_pointer_offset;
1770 HOST_WIDE_INT stack_pointer_offset;
1772 /* When save_regs_using_mov is set, emit prologue using
1773 move instead of push instructions. */
1774 bool save_regs_using_mov;
1777 /* Code model option. */
1778 enum cmodel ix86_cmodel;
1780 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1782 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1784 /* Which unit we are generating floating point math for. */
1785 enum fpmath_unit ix86_fpmath;
1787 /* Which cpu are we scheduling for. */
1788 enum attr_cpu ix86_schedule;
1790 /* Which cpu are we optimizing for. */
1791 enum processor_type ix86_tune;
1793 /* Which instruction set architecture to use. */
1794 enum processor_type ix86_arch;
1796 /* true if sse prefetch instruction is not NOOP. */
1797 int x86_prefetch_sse;
1799 /* ix86_regparm_string as a number */
1800 static int ix86_regparm;
1802 /* -mstackrealign option */
1803 extern int ix86_force_align_arg_pointer;
1804 static const char ix86_force_align_arg_pointer_string[]
1805 = "force_align_arg_pointer";
1807 static rtx (*ix86_gen_leave) (void);
1808 static rtx (*ix86_gen_pop1) (rtx);
1809 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1810 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1811 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1812 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1813 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1814 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1816 /* Preferred alignment for stack boundary in bits. */
1817 unsigned int ix86_preferred_stack_boundary;
1819 /* Alignment for incoming stack boundary in bits specified at
1821 static unsigned int ix86_user_incoming_stack_boundary;
1823 /* Default alignment for incoming stack boundary in bits. */
1824 static unsigned int ix86_default_incoming_stack_boundary;
1826 /* Alignment for incoming stack boundary in bits. */
1827 unsigned int ix86_incoming_stack_boundary;
1829 /* The abi used by target. */
1830 enum calling_abi ix86_abi;
1832 /* Values 1-5: see jump.c */
1833 int ix86_branch_cost;
1835 /* Calling abi specific va_list type nodes. */
1836 static GTY(()) tree sysv_va_list_type_node;
1837 static GTY(()) tree ms_va_list_type_node;
1839 /* Variables which are this size or smaller are put in the data/bss
1840 or ldata/lbss sections. */
1842 int ix86_section_threshold = 65536;
1844 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1845 char internal_label_prefix[16];
1846 int internal_label_prefix_len;
1848 /* Fence to use after loop using movnt. */
1851 /* Register class used for passing given 64bit part of the argument.
1852 These represent classes as documented by the PS ABI, with the exception
1853 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1854 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1856 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1857 whenever possible (upper half does contain padding). */
1858 enum x86_64_reg_class
1861 X86_64_INTEGER_CLASS,
1862 X86_64_INTEGERSI_CLASS,
1869 X86_64_COMPLEX_X87_CLASS,
1873 #define MAX_CLASSES 4
1875 /* Table of constants used by fldpi, fldln2, etc.... */
1876 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1877 static bool ext_80387_constants_init = 0;
1880 static struct machine_function * ix86_init_machine_status (void);
1881 static rtx ix86_function_value (const_tree, const_tree, bool);
1882 static rtx ix86_static_chain (const_tree, bool);
1883 static int ix86_function_regparm (const_tree, const_tree);
1884 static void ix86_compute_frame_layout (struct ix86_frame *);
1885 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1887 static void ix86_add_new_builtins (int);
1889 enum ix86_function_specific_strings
1891 IX86_FUNCTION_SPECIFIC_ARCH,
1892 IX86_FUNCTION_SPECIFIC_TUNE,
1893 IX86_FUNCTION_SPECIFIC_FPMATH,
1894 IX86_FUNCTION_SPECIFIC_MAX
1897 static char *ix86_target_string (int, int, const char *, const char *,
1898 const char *, bool);
1899 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1900 static void ix86_function_specific_save (struct cl_target_option *);
1901 static void ix86_function_specific_restore (struct cl_target_option *);
1902 static void ix86_function_specific_print (FILE *, int,
1903 struct cl_target_option *);
1904 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1905 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1906 static bool ix86_can_inline_p (tree, tree);
1907 static void ix86_set_current_function (tree);
1909 static enum calling_abi ix86_function_abi (const_tree);
1912 /* The svr4 ABI for the i386 says that records and unions are returned
1914 #ifndef DEFAULT_PCC_STRUCT_RETURN
1915 #define DEFAULT_PCC_STRUCT_RETURN 1
1918 /* Whether -mtune= or -march= were specified */
1919 static int ix86_tune_defaulted;
1920 static int ix86_arch_specified;
1922 /* Bit flags that specify the ISA we are compiling for. */
1923 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1925 /* A mask of ix86_isa_flags that includes bit X if X
1926 was set or cleared on the command line. */
1927 static int ix86_isa_flags_explicit;
1929 /* Define a set of ISAs which are available when a given ISA is
1930 enabled. MMX and SSE ISAs are handled separately. */
1932 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1933 #define OPTION_MASK_ISA_3DNOW_SET \
1934 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1936 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1937 #define OPTION_MASK_ISA_SSE2_SET \
1938 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1939 #define OPTION_MASK_ISA_SSE3_SET \
1940 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1941 #define OPTION_MASK_ISA_SSSE3_SET \
1942 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1943 #define OPTION_MASK_ISA_SSE4_1_SET \
1944 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1945 #define OPTION_MASK_ISA_SSE4_2_SET \
1946 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1947 #define OPTION_MASK_ISA_AVX_SET \
1948 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1949 #define OPTION_MASK_ISA_FMA_SET \
1950 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1952 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1954 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1956 #define OPTION_MASK_ISA_SSE4A_SET \
1957 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1958 #define OPTION_MASK_ISA_FMA4_SET \
1959 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
1960 | OPTION_MASK_ISA_AVX_SET)
1962 /* AES and PCLMUL need SSE2 because they use xmm registers */
1963 #define OPTION_MASK_ISA_AES_SET \
1964 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1965 #define OPTION_MASK_ISA_PCLMUL_SET \
1966 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1968 #define OPTION_MASK_ISA_ABM_SET \
1969 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1971 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1972 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1973 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1974 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1975 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
1977 /* Define a set of ISAs which aren't available when a given ISA is
1978 disabled. MMX and SSE ISAs are handled separately. */
1980 #define OPTION_MASK_ISA_MMX_UNSET \
1981 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1982 #define OPTION_MASK_ISA_3DNOW_UNSET \
1983 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1984 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1986 #define OPTION_MASK_ISA_SSE_UNSET \
1987 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1988 #define OPTION_MASK_ISA_SSE2_UNSET \
1989 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1990 #define OPTION_MASK_ISA_SSE3_UNSET \
1991 (OPTION_MASK_ISA_SSE3 \
1992 | OPTION_MASK_ISA_SSSE3_UNSET \
1993 | OPTION_MASK_ISA_SSE4A_UNSET )
1994 #define OPTION_MASK_ISA_SSSE3_UNSET \
1995 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1996 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1997 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1998 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1999 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
2000 #define OPTION_MASK_ISA_AVX_UNSET \
2001 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
2002 | OPTION_MASK_ISA_FMA4_UNSET)
2003 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2005 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2007 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2009 #define OPTION_MASK_ISA_SSE4A_UNSET \
2010 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
2012 #define OPTION_MASK_ISA_FMA4_UNSET OPTION_MASK_ISA_FMA4
2014 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2015 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2016 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2017 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2018 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2019 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2020 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2021 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2023 /* Vectorization library interface and handlers. */
2024 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
2025 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
2026 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
2028 /* Processor target table, indexed by processor number */
2031 const struct processor_costs *cost; /* Processor costs */
2032 const int align_loop; /* Default alignments. */
2033 const int align_loop_max_skip;
2034 const int align_jump;
2035 const int align_jump_max_skip;
2036 const int align_func;
2039 static const struct ptt processor_target_table[PROCESSOR_max] =
2041 {&i386_cost, 4, 3, 4, 3, 4},
2042 {&i486_cost, 16, 15, 16, 15, 16},
2043 {&pentium_cost, 16, 7, 16, 7, 16},
2044 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2045 {&geode_cost, 0, 0, 0, 0, 0},
2046 {&k6_cost, 32, 7, 32, 7, 32},
2047 {&athlon_cost, 16, 7, 16, 7, 16},
2048 {&pentium4_cost, 0, 0, 0, 0, 0},
2049 {&k8_cost, 16, 7, 16, 7, 16},
2050 {&nocona_cost, 0, 0, 0, 0, 0},
2051 {&core2_cost, 16, 10, 16, 10, 16},
2052 {&generic32_cost, 16, 7, 16, 7, 16},
2053 {&generic64_cost, 16, 10, 16, 10, 16},
2054 {&amdfam10_cost, 32, 24, 32, 7, 32},
2055 {&atom_cost, 16, 7, 16, 7, 16}
2058 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2084 /* Implement TARGET_HANDLE_OPTION. */
2087 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
2094 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2095 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2099 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2100 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2107 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2108 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2112 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2113 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2123 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2124 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2128 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2129 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2136 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2137 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2141 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2142 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2149 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2150 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2154 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2155 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2162 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2163 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2167 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2168 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2175 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2176 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2180 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2181 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2188 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2189 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2193 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2194 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2201 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2202 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2206 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2207 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2214 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2215 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2219 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2220 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2225 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2226 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2230 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2231 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2237 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2238 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2242 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2243 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2250 ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
2251 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
2255 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
2256 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
2263 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2264 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2268 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2269 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2276 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2277 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2281 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2282 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2289 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2290 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2294 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2295 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2302 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2303 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2307 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2308 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2315 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
2316 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
2320 ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
2321 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
2328 ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
2329 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
2333 ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
2334 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
2341 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2342 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2346 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2347 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2354 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2355 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2359 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2360 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2369 /* Return a string the documents the current -m options. The caller is
2370 responsible for freeing the string. */
2373 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2374 const char *fpmath, bool add_nl_p)
2376 struct ix86_target_opts
2378 const char *option; /* option string */
2379 int mask; /* isa mask options */
2382 /* This table is ordered so that options like -msse4.2 that imply
2383 preceding options while match those first. */
2384 static struct ix86_target_opts isa_opts[] =
2386 { "-m64", OPTION_MASK_ISA_64BIT },
2387 { "-mfma4", OPTION_MASK_ISA_FMA4 },
2388 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2389 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2390 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2391 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2392 { "-msse3", OPTION_MASK_ISA_SSE3 },
2393 { "-msse2", OPTION_MASK_ISA_SSE2 },
2394 { "-msse", OPTION_MASK_ISA_SSE },
2395 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2396 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2397 { "-mmmx", OPTION_MASK_ISA_MMX },
2398 { "-mabm", OPTION_MASK_ISA_ABM },
2399 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2400 { "-mmovbe", OPTION_MASK_ISA_MOVBE },
2401 { "-mcrc32", OPTION_MASK_ISA_CRC32 },
2402 { "-maes", OPTION_MASK_ISA_AES },
2403 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2407 static struct ix86_target_opts flag_opts[] =
2409 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2410 { "-m80387", MASK_80387 },
2411 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2412 { "-malign-double", MASK_ALIGN_DOUBLE },
2413 { "-mcld", MASK_CLD },
2414 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2415 { "-mieee-fp", MASK_IEEE_FP },
2416 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2417 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2418 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2419 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2420 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2421 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2422 { "-mno-red-zone", MASK_NO_RED_ZONE },
2423 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2424 { "-mrecip", MASK_RECIP },
2425 { "-mrtd", MASK_RTD },
2426 { "-msseregparm", MASK_SSEREGPARM },
2427 { "-mstack-arg-probe", MASK_STACK_PROBE },
2428 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2431 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2434 char target_other[40];
2443 memset (opts, '\0', sizeof (opts));
2445 /* Add -march= option. */
2448 opts[num][0] = "-march=";
2449 opts[num++][1] = arch;
2452 /* Add -mtune= option. */
2455 opts[num][0] = "-mtune=";
2456 opts[num++][1] = tune;
2459 /* Pick out the options in isa options. */
2460 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2462 if ((isa & isa_opts[i].mask) != 0)
2464 opts[num++][0] = isa_opts[i].option;
2465 isa &= ~ isa_opts[i].mask;
2469 if (isa && add_nl_p)
2471 opts[num++][0] = isa_other;
2472 sprintf (isa_other, "(other isa: 0x%x)", isa);
2475 /* Add flag options. */
2476 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2478 if ((flags & flag_opts[i].mask) != 0)
2480 opts[num++][0] = flag_opts[i].option;
2481 flags &= ~ flag_opts[i].mask;
2485 if (flags && add_nl_p)
2487 opts[num++][0] = target_other;
2488 sprintf (target_other, "(other flags: 0x%x)", isa);
2491 /* Add -fpmath= option. */
2494 opts[num][0] = "-mfpmath=";
2495 opts[num++][1] = fpmath;
2502 gcc_assert (num < ARRAY_SIZE (opts));
2504 /* Size the string. */
2506 sep_len = (add_nl_p) ? 3 : 1;
2507 for (i = 0; i < num; i++)
2510 for (j = 0; j < 2; j++)
2512 len += strlen (opts[i][j]);
2515 /* Build the string. */
2516 ret = ptr = (char *) xmalloc (len);
2519 for (i = 0; i < num; i++)
2523 for (j = 0; j < 2; j++)
2524 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2531 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2539 for (j = 0; j < 2; j++)
2542 memcpy (ptr, opts[i][j], len2[j]);
2544 line_len += len2[j];
2549 gcc_assert (ret + len >= ptr);
2554 /* Function that is callable from the debugger to print the current
2557 ix86_debug_options (void)
2559 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2560 ix86_arch_string, ix86_tune_string,
2561 ix86_fpmath_string, true);
2565 fprintf (stderr, "%s\n\n", opts);
2569 fputs ("<no options>\n\n", stderr);
2574 /* Sometimes certain combinations of command options do not make
2575 sense on a particular target machine. You can define a macro
2576 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2577 defined, is executed once just after all the command options have
2580 Don't use this macro to turn on various extra optimizations for
2581 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2584 override_options (bool main_args_p)
2587 unsigned int ix86_arch_mask, ix86_tune_mask;
2592 /* Comes from final.c -- no real reason to change it. */
2593 #define MAX_CODE_ALIGN 16
2601 PTA_PREFETCH_SSE = 1 << 4,
2603 PTA_3DNOW_A = 1 << 6,
2607 PTA_POPCNT = 1 << 10,
2609 PTA_SSE4A = 1 << 12,
2610 PTA_NO_SAHF = 1 << 13,
2611 PTA_SSE4_1 = 1 << 14,
2612 PTA_SSE4_2 = 1 << 15,
2614 PTA_PCLMUL = 1 << 17,
2617 PTA_MOVBE = 1 << 20,
2623 const char *const name; /* processor name or nickname. */
2624 const enum processor_type processor;
2625 const enum attr_cpu schedule;
2626 const unsigned /*enum pta_flags*/ flags;
2628 const processor_alias_table[] =
2630 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2631 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2632 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2633 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2634 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2635 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2636 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2637 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2638 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2639 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2640 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2641 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2642 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2644 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2646 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2647 PTA_MMX | PTA_SSE | PTA_SSE2},
2648 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2649 PTA_MMX |PTA_SSE | PTA_SSE2},
2650 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2651 PTA_MMX | PTA_SSE | PTA_SSE2},
2652 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2653 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2654 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2655 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2656 | PTA_CX16 | PTA_NO_SAHF},
2657 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2658 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2659 | PTA_SSSE3 | PTA_CX16},
2660 {"atom", PROCESSOR_ATOM, CPU_ATOM,
2661 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2662 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
2663 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2664 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2665 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2666 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2667 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2668 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2669 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2670 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2671 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2672 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2673 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2674 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2675 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2676 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2677 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2678 {"x86-64", PROCESSOR_K8, CPU_K8,
2679 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2680 {"k8", PROCESSOR_K8, CPU_K8,
2681 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2682 | PTA_SSE2 | PTA_NO_SAHF},
2683 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2684 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2685 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2686 {"opteron", PROCESSOR_K8, CPU_K8,
2687 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2688 | PTA_SSE2 | PTA_NO_SAHF},
2689 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2690 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2691 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2692 {"athlon64", PROCESSOR_K8, CPU_K8,
2693 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2694 | PTA_SSE2 | PTA_NO_SAHF},
2695 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2696 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2697 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2698 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2699 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2700 | PTA_SSE2 | PTA_NO_SAHF},
2701 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2702 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2703 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2704 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2705 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2706 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2707 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2708 0 /* flags are only used for -march switch. */ },
2709 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2710 PTA_64BIT /* flags are only used for -march switch. */ },
2713 int const pta_size = ARRAY_SIZE (processor_alias_table);
2715 /* Set up prefix/suffix so the error messages refer to either the command
2716 line argument, or the attribute(target). */
2725 prefix = "option(\"";
2730 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2731 SUBTARGET_OVERRIDE_OPTIONS;
2734 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2735 SUBSUBTARGET_OVERRIDE_OPTIONS;
2738 /* -fPIC is the default for x86_64. */
2739 if (TARGET_MACHO && TARGET_64BIT)
2742 /* Set the default values for switches whose default depends on TARGET_64BIT
2743 in case they weren't overwritten by command line options. */
2746 /* Mach-O doesn't support omitting the frame pointer for now. */
2747 if (flag_omit_frame_pointer == 2)
2748 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2749 if (flag_asynchronous_unwind_tables == 2)
2750 flag_asynchronous_unwind_tables = 1;
2751 if (flag_pcc_struct_return == 2)
2752 flag_pcc_struct_return = 0;
2756 if (flag_omit_frame_pointer == 2)
2757 flag_omit_frame_pointer = 0;
2758 if (flag_asynchronous_unwind_tables == 2)
2759 flag_asynchronous_unwind_tables = 0;
2760 if (flag_pcc_struct_return == 2)
2761 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2764 /* Need to check -mtune=generic first. */
2765 if (ix86_tune_string)
2767 if (!strcmp (ix86_tune_string, "generic")
2768 || !strcmp (ix86_tune_string, "i686")
2769 /* As special support for cross compilers we read -mtune=native
2770 as -mtune=generic. With native compilers we won't see the
2771 -mtune=native, as it was changed by the driver. */
2772 || !strcmp (ix86_tune_string, "native"))
2775 ix86_tune_string = "generic64";
2777 ix86_tune_string = "generic32";
2779 /* If this call is for setting the option attribute, allow the
2780 generic32/generic64 that was previously set. */
2781 else if (!main_args_p
2782 && (!strcmp (ix86_tune_string, "generic32")
2783 || !strcmp (ix86_tune_string, "generic64")))
2785 else if (!strncmp (ix86_tune_string, "generic", 7))
2786 error ("bad value (%s) for %stune=%s %s",
2787 ix86_tune_string, prefix, suffix, sw);
2791 if (ix86_arch_string)
2792 ix86_tune_string = ix86_arch_string;
2793 if (!ix86_tune_string)
2795 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2796 ix86_tune_defaulted = 1;
2799 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2800 need to use a sensible tune option. */
2801 if (!strcmp (ix86_tune_string, "generic")
2802 || !strcmp (ix86_tune_string, "x86-64")
2803 || !strcmp (ix86_tune_string, "i686"))
2806 ix86_tune_string = "generic64";
2808 ix86_tune_string = "generic32";
2811 if (ix86_stringop_string)
2813 if (!strcmp (ix86_stringop_string, "rep_byte"))
2814 stringop_alg = rep_prefix_1_byte;
2815 else if (!strcmp (ix86_stringop_string, "libcall"))
2816 stringop_alg = libcall;
2817 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2818 stringop_alg = rep_prefix_4_byte;
2819 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2821 /* rep; movq isn't available in 32-bit code. */
2822 stringop_alg = rep_prefix_8_byte;
2823 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2824 stringop_alg = loop_1_byte;
2825 else if (!strcmp (ix86_stringop_string, "loop"))
2826 stringop_alg = loop;
2827 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2828 stringop_alg = unrolled_loop;
2830 error ("bad value (%s) for %sstringop-strategy=%s %s",
2831 ix86_stringop_string, prefix, suffix, sw);
2833 if (!strcmp (ix86_tune_string, "x86-64"))
2834 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2835 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2836 prefix, suffix, prefix, suffix, prefix, suffix);
2838 if (!ix86_arch_string)
2839 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2841 ix86_arch_specified = 1;
2843 if (!strcmp (ix86_arch_string, "generic"))
2844 error ("generic CPU can be used only for %stune=%s %s",
2845 prefix, suffix, sw);
2846 if (!strncmp (ix86_arch_string, "generic", 7))
2847 error ("bad value (%s) for %sarch=%s %s",
2848 ix86_arch_string, prefix, suffix, sw);
2850 /* Validate -mabi= value. */
2851 if (ix86_abi_string)
2853 if (strcmp (ix86_abi_string, "sysv") == 0)
2854 ix86_abi = SYSV_ABI;
2855 else if (strcmp (ix86_abi_string, "ms") == 0)
2858 error ("unknown ABI (%s) for %sabi=%s %s",
2859 ix86_abi_string, prefix, suffix, sw);
2862 ix86_abi = DEFAULT_ABI;
2864 if (ix86_cmodel_string != 0)
2866 if (!strcmp (ix86_cmodel_string, "small"))
2867 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2868 else if (!strcmp (ix86_cmodel_string, "medium"))
2869 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2870 else if (!strcmp (ix86_cmodel_string, "large"))
2871 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2873 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2874 else if (!strcmp (ix86_cmodel_string, "32"))
2875 ix86_cmodel = CM_32;
2876 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2877 ix86_cmodel = CM_KERNEL;
2879 error ("bad value (%s) for %scmodel=%s %s",
2880 ix86_cmodel_string, prefix, suffix, sw);
2884 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2885 use of rip-relative addressing. This eliminates fixups that
2886 would otherwise be needed if this object is to be placed in a
2887 DLL, and is essentially just as efficient as direct addressing. */
2888 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2889 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2890 else if (TARGET_64BIT)
2891 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2893 ix86_cmodel = CM_32;
2895 if (ix86_asm_string != 0)
2898 && !strcmp (ix86_asm_string, "intel"))
2899 ix86_asm_dialect = ASM_INTEL;
2900 else if (!strcmp (ix86_asm_string, "att"))
2901 ix86_asm_dialect = ASM_ATT;
2903 error ("bad value (%s) for %sasm=%s %s",
2904 ix86_asm_string, prefix, suffix, sw);
2906 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2907 error ("code model %qs not supported in the %s bit mode",
2908 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2909 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2910 sorry ("%i-bit mode not compiled in",
2911 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2913 for (i = 0; i < pta_size; i++)
2914 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2916 ix86_schedule = processor_alias_table[i].schedule;
2917 ix86_arch = processor_alias_table[i].processor;
2918 /* Default cpu tuning to the architecture. */
2919 ix86_tune = ix86_arch;
2921 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2922 error ("CPU you selected does not support x86-64 "
2925 if (processor_alias_table[i].flags & PTA_MMX
2926 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2927 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2928 if (processor_alias_table[i].flags & PTA_3DNOW
2929 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2930 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2931 if (processor_alias_table[i].flags & PTA_3DNOW_A
2932 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2933 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2934 if (processor_alias_table[i].flags & PTA_SSE
2935 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2936 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2937 if (processor_alias_table[i].flags & PTA_SSE2
2938 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2939 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2940 if (processor_alias_table[i].flags & PTA_SSE3
2941 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2942 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2943 if (processor_alias_table[i].flags & PTA_SSSE3
2944 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2945 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2946 if (processor_alias_table[i].flags & PTA_SSE4_1
2947 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2948 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2949 if (processor_alias_table[i].flags & PTA_SSE4_2
2950 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2951 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2952 if (processor_alias_table[i].flags & PTA_AVX
2953 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2954 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2955 if (processor_alias_table[i].flags & PTA_FMA
2956 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2957 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2958 if (processor_alias_table[i].flags & PTA_SSE4A
2959 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2960 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2961 if (processor_alias_table[i].flags & PTA_FMA4
2962 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
2963 ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
2964 if (processor_alias_table[i].flags & PTA_ABM
2965 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2966 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2967 if (processor_alias_table[i].flags & PTA_CX16
2968 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2969 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2970 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2971 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2972 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2973 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2974 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2975 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2976 if (processor_alias_table[i].flags & PTA_MOVBE
2977 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
2978 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
2979 if (processor_alias_table[i].flags & PTA_AES
2980 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2981 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2982 if (processor_alias_table[i].flags & PTA_PCLMUL
2983 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2984 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2985 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2986 x86_prefetch_sse = true;
2992 error ("bad value (%s) for %sarch=%s %s",
2993 ix86_arch_string, prefix, suffix, sw);
2995 ix86_arch_mask = 1u << ix86_arch;
2996 for (i = 0; i < X86_ARCH_LAST; ++i)
2997 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2999 for (i = 0; i < pta_size; i++)
3000 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
3002 ix86_schedule = processor_alias_table[i].schedule;
3003 ix86_tune = processor_alias_table[i].processor;
3004 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
3006 if (ix86_tune_defaulted)
3008 ix86_tune_string = "x86-64";
3009 for (i = 0; i < pta_size; i++)
3010 if (! strcmp (ix86_tune_string,
3011 processor_alias_table[i].name))
3013 ix86_schedule = processor_alias_table[i].schedule;
3014 ix86_tune = processor_alias_table[i].processor;
3017 error ("CPU you selected does not support x86-64 "
3020 /* Intel CPUs have always interpreted SSE prefetch instructions as
3021 NOPs; so, we can enable SSE prefetch instructions even when
3022 -mtune (rather than -march) points us to a processor that has them.
3023 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3024 higher processors. */
3026 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
3027 x86_prefetch_sse = true;
3031 error ("bad value (%s) for %stune=%s %s",
3032 ix86_tune_string, prefix, suffix, sw);
3034 ix86_tune_mask = 1u << ix86_tune;
3035 for (i = 0; i < X86_TUNE_LAST; ++i)
3036 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3039 ix86_cost = &ix86_size_cost;
3041 ix86_cost = processor_target_table[ix86_tune].cost;
3043 /* Arrange to set up i386_stack_locals for all functions. */
3044 init_machine_status = ix86_init_machine_status;
3046 /* Validate -mregparm= value. */
3047 if (ix86_regparm_string)
3050 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
3051 i = atoi (ix86_regparm_string);
3052 if (i < 0 || i > REGPARM_MAX)
3053 error ("%sregparm=%d%s is not between 0 and %d",
3054 prefix, i, suffix, REGPARM_MAX);
3059 ix86_regparm = REGPARM_MAX;
3061 /* If the user has provided any of the -malign-* options,
3062 warn and use that value only if -falign-* is not set.
3063 Remove this code in GCC 3.2 or later. */
3064 if (ix86_align_loops_string)
3066 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
3067 prefix, suffix, suffix);
3068 if (align_loops == 0)
3070 i = atoi (ix86_align_loops_string);
3071 if (i < 0 || i > MAX_CODE_ALIGN)
3072 error ("%salign-loops=%d%s is not between 0 and %d",
3073 prefix, i, suffix, MAX_CODE_ALIGN);
3075 align_loops = 1 << i;
3079 if (ix86_align_jumps_string)
3081 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
3082 prefix, suffix, suffix);
3083 if (align_jumps == 0)
3085 i = atoi (ix86_align_jumps_string);
3086 if (i < 0 || i > MAX_CODE_ALIGN)
3087 error ("%salign-loops=%d%s is not between 0 and %d",
3088 prefix, i, suffix, MAX_CODE_ALIGN);
3090 align_jumps = 1 << i;
3094 if (ix86_align_funcs_string)
3096 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
3097 prefix, suffix, suffix);
3098 if (align_functions == 0)
3100 i = atoi (ix86_align_funcs_string);
3101 if (i < 0 || i > MAX_CODE_ALIGN)
3102 error ("%salign-loops=%d%s is not between 0 and %d",
3103 prefix, i, suffix, MAX_CODE_ALIGN);
3105 align_functions = 1 << i;
3109 /* Default align_* from the processor table. */
3110 if (align_loops == 0)
3112 align_loops = processor_target_table[ix86_tune].align_loop;
3113 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
3115 if (align_jumps == 0)
3117 align_jumps = processor_target_table[ix86_tune].align_jump;
3118 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
3120 if (align_functions == 0)
3122 align_functions = processor_target_table[ix86_tune].align_func;
3125 /* Validate -mbranch-cost= value, or provide default. */
3126 ix86_branch_cost = ix86_cost->branch_cost;
3127 if (ix86_branch_cost_string)
3129 i = atoi (ix86_branch_cost_string);
3131 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
3133 ix86_branch_cost = i;
3135 if (ix86_section_threshold_string)
3137 i = atoi (ix86_section_threshold_string);
3139 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
3141 ix86_section_threshold = i;
3144 if (ix86_tls_dialect_string)
3146 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3147 ix86_tls_dialect = TLS_DIALECT_GNU;
3148 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3149 ix86_tls_dialect = TLS_DIALECT_GNU2;
3150 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3151 ix86_tls_dialect = TLS_DIALECT_SUN;
3153 error ("bad value (%s) for %stls-dialect=%s %s",
3154 ix86_tls_dialect_string, prefix, suffix, sw);
3157 if (ix87_precision_string)
3159 i = atoi (ix87_precision_string);
3160 if (i != 32 && i != 64 && i != 80)
3161 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3166 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3168 /* Enable by default the SSE and MMX builtins. Do allow the user to
3169 explicitly disable any of these. In particular, disabling SSE and
3170 MMX for kernel code is extremely useful. */
3171 if (!ix86_arch_specified)
3173 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3174 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3177 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3181 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3183 if (!ix86_arch_specified)
3185 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3187 /* i386 ABI does not specify red zone. It still makes sense to use it
3188 when programmer takes care to stack from being destroyed. */
3189 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3190 target_flags |= MASK_NO_RED_ZONE;
3193 /* Keep nonleaf frame pointers. */
3194 if (flag_omit_frame_pointer)
3195 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3196 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3197 flag_omit_frame_pointer = 1;
3199 /* If we're doing fast math, we don't care about comparison order
3200 wrt NaNs. This lets us use a shorter comparison sequence. */
3201 if (flag_finite_math_only)
3202 target_flags &= ~MASK_IEEE_FP;
3204 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3205 since the insns won't need emulation. */
3206 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3207 target_flags &= ~MASK_NO_FANCY_MATH_387;
3209 /* Likewise, if the target doesn't have a 387, or we've specified
3210 software floating point, don't use 387 inline intrinsics. */
3212 target_flags |= MASK_NO_FANCY_MATH_387;
3214 /* Turn on MMX builtins for -msse. */
3217 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3218 x86_prefetch_sse = true;
3221 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3222 if (TARGET_SSE4_2 || TARGET_ABM)
3223 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3225 /* Validate -mpreferred-stack-boundary= value or default it to
3226 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3227 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3228 if (ix86_preferred_stack_boundary_string)
3230 i = atoi (ix86_preferred_stack_boundary_string);
3231 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3232 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3233 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3235 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3238 /* Set the default value for -mstackrealign. */
3239 if (ix86_force_align_arg_pointer == -1)
3240 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3242 /* Validate -mincoming-stack-boundary= value or default it to
3243 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3244 if (ix86_force_align_arg_pointer)
3245 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3247 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3248 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3249 if (ix86_incoming_stack_boundary_string)
3251 i = atoi (ix86_incoming_stack_boundary_string);
3252 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3253 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3254 i, TARGET_64BIT ? 4 : 2);
3257 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3258 ix86_incoming_stack_boundary
3259 = ix86_user_incoming_stack_boundary;
3263 /* Accept -msseregparm only if at least SSE support is enabled. */
3264 if (TARGET_SSEREGPARM
3266 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3268 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3269 if (ix86_fpmath_string != 0)
3271 if (! strcmp (ix86_fpmath_string, "387"))
3272 ix86_fpmath = FPMATH_387;
3273 else if (! strcmp (ix86_fpmath_string, "sse"))
3277 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3278 ix86_fpmath = FPMATH_387;
3281 ix86_fpmath = FPMATH_SSE;
3283 else if (! strcmp (ix86_fpmath_string, "387,sse")
3284 || ! strcmp (ix86_fpmath_string, "387+sse")
3285 || ! strcmp (ix86_fpmath_string, "sse,387")
3286 || ! strcmp (ix86_fpmath_string, "sse+387")
3287 || ! strcmp (ix86_fpmath_string, "both"))
3291 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3292 ix86_fpmath = FPMATH_387;
3294 else if (!TARGET_80387)
3296 warning (0, "387 instruction set disabled, using SSE arithmetics");
3297 ix86_fpmath = FPMATH_SSE;
3300 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3303 error ("bad value (%s) for %sfpmath=%s %s",
3304 ix86_fpmath_string, prefix, suffix, sw);
3307 /* If the i387 is disabled, then do not return values in it. */
3309 target_flags &= ~MASK_FLOAT_RETURNS;
3311 /* Use external vectorized library in vectorizing intrinsics. */
3312 if (ix86_veclibabi_string)
3314 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3315 ix86_veclib_handler = ix86_veclibabi_svml;
3316 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3317 ix86_veclib_handler = ix86_veclibabi_acml;
3319 error ("unknown vectorization library ABI type (%s) for "
3320 "%sveclibabi=%s %s", ix86_veclibabi_string,
3321 prefix, suffix, sw);
3324 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3325 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3327 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3329 /* ??? Unwind info is not correct around the CFG unless either a frame
3330 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3331 unwind info generation to be aware of the CFG and propagating states
3333 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3334 || flag_exceptions || flag_non_call_exceptions)
3335 && flag_omit_frame_pointer
3336 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3338 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3339 warning (0, "unwind tables currently require either a frame pointer "
3340 "or %saccumulate-outgoing-args%s for correctness",
3342 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3345 /* If stack probes are required, the space used for large function
3346 arguments on the stack must also be probed, so enable
3347 -maccumulate-outgoing-args so this happens in the prologue. */
3348 if (TARGET_STACK_PROBE
3349 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3351 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3352 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3353 "for correctness", prefix, suffix);
3354 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3357 /* For sane SSE instruction set generation we need fcomi instruction.
3358 It is safe to enable all CMOVE instructions. */
3362 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3365 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3366 p = strchr (internal_label_prefix, 'X');
3367 internal_label_prefix_len = p - internal_label_prefix;
3371 /* When scheduling description is not available, disable scheduler pass
3372 so it won't slow down the compilation and make x87 code slower. */
3373 if (!TARGET_SCHEDULE)
3374 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3376 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3377 set_param_value ("simultaneous-prefetches",
3378 ix86_cost->simultaneous_prefetches);
3379 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3380 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3381 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3382 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3383 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3384 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3386 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3387 can be optimized to ap = __builtin_next_arg (0). */
3389 targetm.expand_builtin_va_start = NULL;
3393 ix86_gen_leave = gen_leave_rex64;
3394 ix86_gen_pop1 = gen_popdi1;
3395 ix86_gen_add3 = gen_adddi3;
3396 ix86_gen_sub3 = gen_subdi3;
3397 ix86_gen_sub3_carry = gen_subdi3_carry;
3398 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3399 ix86_gen_monitor = gen_sse3_monitor64;
3400 ix86_gen_andsp = gen_anddi3;
3404 ix86_gen_leave = gen_leave;
3405 ix86_gen_pop1 = gen_popsi1;
3406 ix86_gen_add3 = gen_addsi3;
3407 ix86_gen_sub3 = gen_subsi3;
3408 ix86_gen_sub3_carry = gen_subsi3_carry;
3409 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3410 ix86_gen_monitor = gen_sse3_monitor;
3411 ix86_gen_andsp = gen_andsi3;
3415 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3417 target_flags |= MASK_CLD & ~target_flags_explicit;
3420 /* Save the initial options in case the user does function specific options */
3422 target_option_default_node = target_option_current_node
3423 = build_target_option_node ();
3426 /* Update register usage after having seen the compiler flags. */
3429 ix86_conditional_register_usage (void)
3434 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3436 if (fixed_regs[i] > 1)
3437 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3438 if (call_used_regs[i] > 1)
3439 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3442 /* The PIC register, if it exists, is fixed. */
3443 j = PIC_OFFSET_TABLE_REGNUM;
3444 if (j != INVALID_REGNUM)
3445 fixed_regs[j] = call_used_regs[j] = 1;
3447 /* The MS_ABI changes the set of call-used registers. */
3448 if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
3450 call_used_regs[SI_REG] = 0;
3451 call_used_regs[DI_REG] = 0;
3452 call_used_regs[XMM6_REG] = 0;
3453 call_used_regs[XMM7_REG] = 0;
3454 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3455 call_used_regs[i] = 0;
3458 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3459 other call-clobbered regs for 64-bit. */
3462 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3464 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3465 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3466 && call_used_regs[i])
3467 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3470 /* If MMX is disabled, squash the registers. */
3472 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3473 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3474 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3476 /* If SSE is disabled, squash the registers. */
3478 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3479 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3480 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3482 /* If the FPU is disabled, squash the registers. */
3483 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3484 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3485 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3486 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3488 /* If 32-bit, squash the 64-bit registers. */
3491 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3493 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3499 /* Save the current options */
3502 ix86_function_specific_save (struct cl_target_option *ptr)
3504 ptr->arch = ix86_arch;
3505 ptr->schedule = ix86_schedule;
3506 ptr->tune = ix86_tune;
3507 ptr->fpmath = ix86_fpmath;
3508 ptr->branch_cost = ix86_branch_cost;
3509 ptr->tune_defaulted = ix86_tune_defaulted;
3510 ptr->arch_specified = ix86_arch_specified;
3511 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3512 ptr->target_flags_explicit = target_flags_explicit;
3514 /* The fields are char but the variables are not; make sure the
3515 values fit in the fields. */
3516 gcc_assert (ptr->arch == ix86_arch);
3517 gcc_assert (ptr->schedule == ix86_schedule);
3518 gcc_assert (ptr->tune == ix86_tune);
3519 gcc_assert (ptr->fpmath == ix86_fpmath);
3520 gcc_assert (ptr->branch_cost == ix86_branch_cost);
3523 /* Restore the current options */
3526 ix86_function_specific_restore (struct cl_target_option *ptr)
3528 enum processor_type old_tune = ix86_tune;
3529 enum processor_type old_arch = ix86_arch;
3530 unsigned int ix86_arch_mask, ix86_tune_mask;
3533 ix86_arch = (enum processor_type) ptr->arch;
3534 ix86_schedule = (enum attr_cpu) ptr->schedule;
3535 ix86_tune = (enum processor_type) ptr->tune;
3536 ix86_fpmath = (enum fpmath_unit) ptr->fpmath;
3537 ix86_branch_cost = ptr->branch_cost;
3538 ix86_tune_defaulted = ptr->tune_defaulted;
3539 ix86_arch_specified = ptr->arch_specified;
3540 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3541 target_flags_explicit = ptr->target_flags_explicit;
3543 /* Recreate the arch feature tests if the arch changed */
3544 if (old_arch != ix86_arch)
3546 ix86_arch_mask = 1u << ix86_arch;
3547 for (i = 0; i < X86_ARCH_LAST; ++i)
3548 ix86_arch_features[i]
3549 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3552 /* Recreate the tune optimization tests */
3553 if (old_tune != ix86_tune)
3555 ix86_tune_mask = 1u << ix86_tune;
3556 for (i = 0; i < X86_TUNE_LAST; ++i)
3557 ix86_tune_features[i]
3558 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3562 /* Print the current options */
3565 ix86_function_specific_print (FILE *file, int indent,
3566 struct cl_target_option *ptr)
3569 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3570 NULL, NULL, NULL, false);
3572 fprintf (file, "%*sarch = %d (%s)\n",
3575 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3576 ? cpu_names[ptr->arch]
3579 fprintf (file, "%*stune = %d (%s)\n",
3582 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3583 ? cpu_names[ptr->tune]
3586 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3587 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3588 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3589 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3593 fprintf (file, "%*s%s\n", indent, "", target_string);
3594 free (target_string);
3599 /* Inner function to process the attribute((target(...))), take an argument and
3600 set the current options from the argument. If we have a list, recursively go
3604 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3609 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3610 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3611 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3612 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3627 enum ix86_opt_type type;
3632 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3633 IX86_ATTR_ISA ("abm", OPT_mabm),
3634 IX86_ATTR_ISA ("aes", OPT_maes),
3635 IX86_ATTR_ISA ("avx", OPT_mavx),
3636 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3637 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3638 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3639 IX86_ATTR_ISA ("sse", OPT_msse),
3640 IX86_ATTR_ISA ("sse2", OPT_msse2),
3641 IX86_ATTR_ISA ("sse3", OPT_msse3),
3642 IX86_ATTR_ISA ("sse4", OPT_msse4),
3643 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3644 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3645 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3646 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3647 IX86_ATTR_ISA ("fma4", OPT_mfma4),
3649 /* string options */
3650 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3651 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3652 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3655 IX86_ATTR_YES ("cld",
3659 IX86_ATTR_NO ("fancy-math-387",
3660 OPT_mfancy_math_387,
3661 MASK_NO_FANCY_MATH_387),
3663 IX86_ATTR_YES ("ieee-fp",
3667 IX86_ATTR_YES ("inline-all-stringops",
3668 OPT_minline_all_stringops,
3669 MASK_INLINE_ALL_STRINGOPS),
3671 IX86_ATTR_YES ("inline-stringops-dynamically",
3672 OPT_minline_stringops_dynamically,
3673 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3675 IX86_ATTR_NO ("align-stringops",
3676 OPT_mno_align_stringops,
3677 MASK_NO_ALIGN_STRINGOPS),
3679 IX86_ATTR_YES ("recip",
3685 /* If this is a list, recurse to get the options. */
3686 if (TREE_CODE (args) == TREE_LIST)
3690 for (; args; args = TREE_CHAIN (args))
3691 if (TREE_VALUE (args)
3692 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3698 else if (TREE_CODE (args) != STRING_CST)
3701 /* Handle multiple arguments separated by commas. */
3702 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3704 while (next_optstr && *next_optstr != '\0')
3706 char *p = next_optstr;
3708 char *comma = strchr (next_optstr, ',');
3709 const char *opt_string;
3710 size_t len, opt_len;
3715 enum ix86_opt_type type = ix86_opt_unknown;
3721 len = comma - next_optstr;
3722 next_optstr = comma + 1;
3730 /* Recognize no-xxx. */
3731 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3740 /* Find the option. */
3743 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3745 type = attrs[i].type;
3746 opt_len = attrs[i].len;
3747 if (ch == attrs[i].string[0]
3748 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3749 && memcmp (p, attrs[i].string, opt_len) == 0)
3752 mask = attrs[i].mask;
3753 opt_string = attrs[i].string;
3758 /* Process the option. */
3761 error ("attribute(target(\"%s\")) is unknown", orig_p);
3765 else if (type == ix86_opt_isa)
3766 ix86_handle_option (opt, p, opt_set_p);
3768 else if (type == ix86_opt_yes || type == ix86_opt_no)
3770 if (type == ix86_opt_no)
3771 opt_set_p = !opt_set_p;
3774 target_flags |= mask;
3776 target_flags &= ~mask;
3779 else if (type == ix86_opt_str)
3783 error ("option(\"%s\") was already specified", opt_string);
3787 p_strings[opt] = xstrdup (p + opt_len);
3797 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3800 ix86_valid_target_attribute_tree (tree args)
3802 const char *orig_arch_string = ix86_arch_string;
3803 const char *orig_tune_string = ix86_tune_string;
3804 const char *orig_fpmath_string = ix86_fpmath_string;
3805 int orig_tune_defaulted = ix86_tune_defaulted;
3806 int orig_arch_specified = ix86_arch_specified;
3807 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3810 struct cl_target_option *def
3811 = TREE_TARGET_OPTION (target_option_default_node);
3813 /* Process each of the options on the chain. */
3814 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3817 /* If the changed options are different from the default, rerun override_options,
3818 and then save the options away. The string options are are attribute options,
3819 and will be undone when we copy the save structure. */
3820 if (ix86_isa_flags != def->ix86_isa_flags
3821 || target_flags != def->target_flags
3822 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3823 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3824 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3826 /* If we are using the default tune= or arch=, undo the string assigned,
3827 and use the default. */
3828 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3829 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3830 else if (!orig_arch_specified)
3831 ix86_arch_string = NULL;
3833 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3834 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3835 else if (orig_tune_defaulted)
3836 ix86_tune_string = NULL;
3838 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3839 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3840 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3841 else if (!TARGET_64BIT && TARGET_SSE)
3842 ix86_fpmath_string = "sse,387";
3844 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3845 override_options (false);
3847 /* Add any builtin functions with the new isa if any. */
3848 ix86_add_new_builtins (ix86_isa_flags);
3850 /* Save the current options unless we are validating options for
3852 t = build_target_option_node ();
3854 ix86_arch_string = orig_arch_string;
3855 ix86_tune_string = orig_tune_string;
3856 ix86_fpmath_string = orig_fpmath_string;
3858 /* Free up memory allocated to hold the strings */
3859 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3860 if (option_strings[i])
3861 free (option_strings[i]);
3867 /* Hook to validate attribute((target("string"))). */
3870 ix86_valid_target_attribute_p (tree fndecl,
3871 tree ARG_UNUSED (name),
3873 int ARG_UNUSED (flags))
3875 struct cl_target_option cur_target;
3877 tree old_optimize = build_optimization_node ();
3878 tree new_target, new_optimize;
3879 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3881 /* If the function changed the optimization levels as well as setting target
3882 options, start with the optimizations specified. */
3883 if (func_optimize && func_optimize != old_optimize)
3884 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3886 /* The target attributes may also change some optimization flags, so update
3887 the optimization options if necessary. */
3888 cl_target_option_save (&cur_target);
3889 new_target = ix86_valid_target_attribute_tree (args);
3890 new_optimize = build_optimization_node ();
3897 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3899 if (old_optimize != new_optimize)
3900 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3903 cl_target_option_restore (&cur_target);
3905 if (old_optimize != new_optimize)
3906 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3912 /* Hook to determine if one function can safely inline another. */
3915 ix86_can_inline_p (tree caller, tree callee)
3918 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3919 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3921 /* If callee has no option attributes, then it is ok to inline. */
3925 /* If caller has no option attributes, but callee does then it is not ok to
3927 else if (!caller_tree)
3932 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3933 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3935 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
3936 can inline a SSE2 function but a SSE2 function can't inline a SSE4
3938 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3939 != callee_opts->ix86_isa_flags)
3942 /* See if we have the same non-isa options. */
3943 else if (caller_opts->target_flags != callee_opts->target_flags)
3946 /* See if arch, tune, etc. are the same. */
3947 else if (caller_opts->arch != callee_opts->arch)
3950 else if (caller_opts->tune != callee_opts->tune)
3953 else if (caller_opts->fpmath != callee_opts->fpmath)
3956 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3967 /* Remember the last target of ix86_set_current_function. */
3968 static GTY(()) tree ix86_previous_fndecl;
3970 /* Establish appropriate back-end context for processing the function
3971 FNDECL. The argument might be NULL to indicate processing at top
3972 level, outside of any function scope. */
3974 ix86_set_current_function (tree fndecl)
3976 /* Only change the context if the function changes. This hook is called
3977 several times in the course of compiling a function, and we don't want to
3978 slow things down too much or call target_reinit when it isn't safe. */
3979 if (fndecl && fndecl != ix86_previous_fndecl)
3981 tree old_tree = (ix86_previous_fndecl
3982 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3985 tree new_tree = (fndecl
3986 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3989 ix86_previous_fndecl = fndecl;
3990 if (old_tree == new_tree)
3995 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
4001 struct cl_target_option *def
4002 = TREE_TARGET_OPTION (target_option_current_node);
4004 cl_target_option_restore (def);
4011 /* Return true if this goes in large data/bss. */
4014 ix86_in_large_data_p (tree exp)
4016 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
4019 /* Functions are never large data. */
4020 if (TREE_CODE (exp) == FUNCTION_DECL)
4023 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
4025 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
4026 if (strcmp (section, ".ldata") == 0
4027 || strcmp (section, ".lbss") == 0)
4033 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
4035 /* If this is an incomplete type with size 0, then we can't put it
4036 in data because it might be too big when completed. */
4037 if (!size || size > ix86_section_threshold)
4044 /* Switch to the appropriate section for output of DECL.
4045 DECL is either a `VAR_DECL' node or a constant of some sort.
4046 RELOC indicates whether forming the initial value of DECL requires
4047 link-time relocations. */
4049 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
4053 x86_64_elf_select_section (tree decl, int reloc,
4054 unsigned HOST_WIDE_INT align)
4056 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4057 && ix86_in_large_data_p (decl))
4059 const char *sname = NULL;
4060 unsigned int flags = SECTION_WRITE;
4061 switch (categorize_decl_for_section (decl, reloc))
4066 case SECCAT_DATA_REL:
4067 sname = ".ldata.rel";
4069 case SECCAT_DATA_REL_LOCAL:
4070 sname = ".ldata.rel.local";
4072 case SECCAT_DATA_REL_RO:
4073 sname = ".ldata.rel.ro";
4075 case SECCAT_DATA_REL_RO_LOCAL:
4076 sname = ".ldata.rel.ro.local";
4080 flags |= SECTION_BSS;
4083 case SECCAT_RODATA_MERGE_STR:
4084 case SECCAT_RODATA_MERGE_STR_INIT:
4085 case SECCAT_RODATA_MERGE_CONST:
4089 case SECCAT_SRODATA:
4096 /* We don't split these for medium model. Place them into
4097 default sections and hope for best. */
4099 case SECCAT_EMUTLS_VAR:
4100 case SECCAT_EMUTLS_TMPL:
4105 /* We might get called with string constants, but get_named_section
4106 doesn't like them as they are not DECLs. Also, we need to set
4107 flags in that case. */
4109 return get_section (sname, flags, NULL);
4110 return get_named_section (decl, sname, reloc);
4113 return default_elf_select_section (decl, reloc, align);
4116 /* Build up a unique section name, expressed as a
4117 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4118 RELOC indicates whether the initial value of EXP requires
4119 link-time relocations. */
4121 static void ATTRIBUTE_UNUSED
4122 x86_64_elf_unique_section (tree decl, int reloc)
4124 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4125 && ix86_in_large_data_p (decl))
4127 const char *prefix = NULL;
4128 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4129 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
4131 switch (categorize_decl_for_section (decl, reloc))
4134 case SECCAT_DATA_REL:
4135 case SECCAT_DATA_REL_LOCAL:
4136 case SECCAT_DATA_REL_RO:
4137 case SECCAT_DATA_REL_RO_LOCAL:
4138 prefix = one_only ? ".ld" : ".ldata";
4141 prefix = one_only ? ".lb" : ".lbss";
4144 case SECCAT_RODATA_MERGE_STR:
4145 case SECCAT_RODATA_MERGE_STR_INIT:
4146 case SECCAT_RODATA_MERGE_CONST:
4147 prefix = one_only ? ".lr" : ".lrodata";
4149 case SECCAT_SRODATA:
4156 /* We don't split these for medium model. Place them into
4157 default sections and hope for best. */
4159 case SECCAT_EMUTLS_VAR:
4160 prefix = targetm.emutls.var_section;
4162 case SECCAT_EMUTLS_TMPL:
4163 prefix = targetm.emutls.tmpl_section;
4168 const char *name, *linkonce;
4171 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4172 name = targetm.strip_name_encoding (name);
4174 /* If we're using one_only, then there needs to be a .gnu.linkonce
4175 prefix to the section name. */
4176 linkonce = one_only ? ".gnu.linkonce" : "";
4178 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4180 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4184 default_unique_section (decl, reloc);
4187 #ifdef COMMON_ASM_OP
4188 /* This says how to output assembler code to declare an
4189 uninitialized external linkage data object.
4191 For medium model x86-64 we need to use .largecomm opcode for
4194 x86_elf_aligned_common (FILE *file,
4195 const char *name, unsigned HOST_WIDE_INT size,
4198 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4199 && size > (unsigned int)ix86_section_threshold)
4200 fputs (".largecomm\t", file);
4202 fputs (COMMON_ASM_OP, file);
4203 assemble_name (file, name);
4204 fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
4205 size, align / BITS_PER_UNIT);
4209 /* Utility function for targets to use in implementing
4210 ASM_OUTPUT_ALIGNED_BSS. */
4213 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4214 const char *name, unsigned HOST_WIDE_INT size,
4217 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4218 && size > (unsigned int)ix86_section_threshold)
4219 switch_to_section (get_named_section (decl, ".lbss", 0));
4221 switch_to_section (bss_section);
4222 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4223 #ifdef ASM_DECLARE_OBJECT_NAME
4224 last_assemble_variable_decl = decl;
4225 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4227 /* Standard thing is just output label for the object. */
4228 ASM_OUTPUT_LABEL (file, name);
4229 #endif /* ASM_DECLARE_OBJECT_NAME */
4230 ASM_OUTPUT_SKIP (file, size ? size : 1);
4234 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4236 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4237 make the problem with not enough registers even worse. */
4238 #ifdef INSN_SCHEDULING
4240 flag_schedule_insns = 0;
4244 /* The Darwin libraries never set errno, so we might as well
4245 avoid calling them when that's the only reason we would. */
4246 flag_errno_math = 0;
4248 /* The default values of these switches depend on the TARGET_64BIT
4249 that is not known at this moment. Mark these values with 2 and
4250 let user the to override these. In case there is no command line option
4251 specifying them, we will set the defaults in override_options. */
4253 flag_omit_frame_pointer = 2;
4254 flag_pcc_struct_return = 2;
4255 flag_asynchronous_unwind_tables = 2;
4256 flag_vect_cost_model = 1;
4257 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4258 SUBTARGET_OPTIMIZATION_OPTIONS;
4262 /* Decide whether we can make a sibling call to a function. DECL is the
4263 declaration of the function being targeted by the call and EXP is the
4264 CALL_EXPR representing the call. */
4267 ix86_function_ok_for_sibcall (tree decl, tree exp)
4269 tree type, decl_or_type;
4272 /* If we are generating position-independent code, we cannot sibcall
4273 optimize any indirect call, or a direct call to a global function,
4274 as the PLT requires %ebx be live. */
4275 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4278 /* If we need to align the outgoing stack, then sibcalling would
4279 unalign the stack, which may break the called function. */
4280 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4285 decl_or_type = decl;
4286 type = TREE_TYPE (decl);
4290 /* We're looking at the CALL_EXPR, we need the type of the function. */
4291 type = CALL_EXPR_FN (exp); /* pointer expression */
4292 type = TREE_TYPE (type); /* pointer type */
4293 type = TREE_TYPE (type); /* function type */
4294 decl_or_type = type;
4297 /* Check that the return value locations are the same. Like
4298 if we are returning floats on the 80387 register stack, we cannot
4299 make a sibcall from a function that doesn't return a float to a
4300 function that does or, conversely, from a function that does return
4301 a float to a function that doesn't; the necessary stack adjustment
4302 would not be executed. This is also the place we notice
4303 differences in the return value ABI. Note that it is ok for one
4304 of the functions to have void return type as long as the return
4305 value of the other is passed in a register. */
4306 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4307 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4309 if (STACK_REG_P (a) || STACK_REG_P (b))
4311 if (!rtx_equal_p (a, b))
4314 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4316 else if (!rtx_equal_p (a, b))
4321 /* The SYSV ABI has more call-clobbered registers;
4322 disallow sibcalls from MS to SYSV. */
4323 if (cfun->machine->call_abi == MS_ABI
4324 && ix86_function_type_abi (type) == SYSV_ABI)
4329 /* If this call is indirect, we'll need to be able to use a
4330 call-clobbered register for the address of the target function.
4331 Make sure that all such registers are not used for passing
4332 parameters. Note that DLLIMPORT functions are indirect. */
4334 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4336 if (ix86_function_regparm (type, NULL) >= 3)
4338 /* ??? Need to count the actual number of registers to be used,
4339 not the possible number of registers. Fix later. */
4345 /* Otherwise okay. That also includes certain types of indirect calls. */
4349 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4350 calling convention attributes;
4351 arguments as in struct attribute_spec.handler. */
4354 ix86_handle_cconv_attribute (tree *node, tree name,
4356 int flags ATTRIBUTE_UNUSED,
4359 if (TREE_CODE (*node) != FUNCTION_TYPE
4360 && TREE_CODE (*node) != METHOD_TYPE
4361 && TREE_CODE (*node) != FIELD_DECL
4362 && TREE_CODE (*node) != TYPE_DECL)
4364 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4366 *no_add_attrs = true;
4370 /* Can combine regparm with all attributes but fastcall. */
4371 if (is_attribute_p ("regparm", name))
4375 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4377 error ("fastcall and regparm attributes are not compatible");
4380 cst = TREE_VALUE (args);
4381 if (TREE_CODE (cst) != INTEGER_CST)
4383 warning (OPT_Wattributes,
4384 "%qE attribute requires an integer constant argument",
4386 *no_add_attrs = true;
4388 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4390 warning (OPT_Wattributes, "argument to %qE attribute larger than %d",
4392 *no_add_attrs = true;
4400 /* Do not warn when emulating the MS ABI. */
4401 if (TREE_CODE (*node) != FUNCTION_TYPE
4402 || ix86_function_type_abi (*node) != MS_ABI)
4403 warning (OPT_Wattributes, "%qE attribute ignored",
4405 *no_add_attrs = true;
4409 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4410 if (is_attribute_p ("fastcall", name))
4412 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4414 error ("fastcall and cdecl attributes are not compatible");
4416 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4418 error ("fastcall and stdcall attributes are not compatible");
4420 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4422 error ("fastcall and regparm attributes are not compatible");
4426 /* Can combine stdcall with fastcall (redundant), regparm and
4428 else if (is_attribute_p ("stdcall", name))
4430 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4432 error ("stdcall and cdecl attributes are not compatible");
4434 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4436 error ("stdcall and fastcall attributes are not compatible");
4440 /* Can combine cdecl with regparm and sseregparm. */
4441 else if (is_attribute_p ("cdecl", name))
4443 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4445 error ("stdcall and cdecl attributes are not compatible");
4447 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4449 error ("fastcall and cdecl attributes are not compatible");
4453 /* Can combine sseregparm with all attributes. */
4458 /* Return 0 if the attributes for two types are incompatible, 1 if they
4459 are compatible, and 2 if they are nearly compatible (which causes a
4460 warning to be generated). */
4463 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4465 /* Check for mismatch of non-default calling convention. */
4466 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4468 if (TREE_CODE (type1) != FUNCTION_TYPE
4469 && TREE_CODE (type1) != METHOD_TYPE)
4472 /* Check for mismatched fastcall/regparm types. */
4473 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4474 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4475 || (ix86_function_regparm (type1, NULL)
4476 != ix86_function_regparm (type2, NULL)))
4479 /* Check for mismatched sseregparm types. */
4480 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4481 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4484 /* Check for mismatched return types (cdecl vs stdcall). */
4485 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4486 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4492 /* Return the regparm value for a function with the indicated TYPE and DECL.
4493 DECL may be NULL when calling function indirectly
4494 or considering a libcall. */
4497 ix86_function_regparm (const_tree type, const_tree decl)
4503 return (ix86_function_type_abi (type) == SYSV_ABI
4504 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4506 regparm = ix86_regparm;
4507 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4510 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4514 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4517 /* Use register calling convention for local functions when possible. */
4519 && TREE_CODE (decl) == FUNCTION_DECL
4523 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4524 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE (decl));
4527 int local_regparm, globals = 0, regno;
4529 /* Make sure no regparm register is taken by a
4530 fixed register variable. */
4531 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4532 if (fixed_regs[local_regparm])
4535 /* We don't want to use regparm(3) for nested functions as
4536 these use a static chain pointer in the third argument. */
4537 if (local_regparm == 3 && DECL_STATIC_CHAIN (decl))
4540 /* Each fixed register usage increases register pressure,
4541 so less registers should be used for argument passing.
4542 This functionality can be overriden by an explicit
4544 for (regno = 0; regno <= DI_REG; regno++)
4545 if (fixed_regs[regno])
4549 = globals < local_regparm ? local_regparm - globals : 0;
4551 if (local_regparm > regparm)
4552 regparm = local_regparm;
4559 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4560 DFmode (2) arguments in SSE registers for a function with the
4561 indicated TYPE and DECL. DECL may be NULL when calling function
4562 indirectly or considering a libcall. Otherwise return 0. */
4565 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4567 gcc_assert (!TARGET_64BIT);
4569 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4570 by the sseregparm attribute. */
4571 if (TARGET_SSEREGPARM
4572 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4579 error ("Calling %qD with attribute sseregparm without "
4580 "SSE/SSE2 enabled", decl);
4582 error ("Calling %qT with attribute sseregparm without "
4583 "SSE/SSE2 enabled", type);
4591 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4592 (and DFmode for SSE2) arguments in SSE registers. */
4593 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4595 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4596 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4598 return TARGET_SSE2 ? 2 : 1;
4604 /* Return true if EAX is live at the start of the function. Used by
4605 ix86_expand_prologue to determine if we need special help before
4606 calling allocate_stack_worker. */
4609 ix86_eax_live_at_start_p (void)
4611 /* Cheat. Don't bother working forward from ix86_function_regparm
4612 to the function type to whether an actual argument is located in
4613 eax. Instead just look at cfg info, which is still close enough
4614 to correct at this point. This gives false positives for broken
4615 functions that might use uninitialized data that happens to be
4616 allocated in eax, but who cares? */
4617 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4620 /* Value is the number of bytes of arguments automatically
4621 popped when returning from a subroutine call.
4622 FUNDECL is the declaration node of the function (as a tree),
4623 FUNTYPE is the data type of the function (as a tree),
4624 or for a library call it is an identifier node for the subroutine name.
4625 SIZE is the number of bytes of arguments passed on the stack.
4627 On the 80386, the RTD insn may be used to pop them if the number
4628 of args is fixed, but if the number is variable then the caller
4629 must pop them all. RTD can't be used for library calls now
4630 because the library is compiled with the Unix compiler.
4631 Use of RTD is a selectable option, since it is incompatible with
4632 standard Unix calling sequences. If the option is not selected,
4633 the caller must always pop the args.
4635 The attribute stdcall is equivalent to RTD on a per module basis. */
4638 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4642 /* None of the 64-bit ABIs pop arguments. */
4646 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4648 /* Cdecl functions override -mrtd, and never pop the stack. */
4649 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4651 /* Stdcall and fastcall functions will pop the stack if not
4653 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4654 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4657 if (rtd && ! stdarg_p (funtype))
4661 /* Lose any fake structure return argument if it is passed on the stack. */
4662 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4663 && !KEEP_AGGREGATE_RETURN_POINTER)
4665 int nregs = ix86_function_regparm (funtype, fundecl);
4667 return GET_MODE_SIZE (Pmode);
4673 /* Argument support functions. */
4675 /* Return true when register may be used to pass function parameters. */
4677 ix86_function_arg_regno_p (int regno)
4680 const int *parm_regs;
4685 return (regno < REGPARM_MAX
4686 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4688 return (regno < REGPARM_MAX
4689 || (TARGET_MMX && MMX_REGNO_P (regno)
4690 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4691 || (TARGET_SSE && SSE_REGNO_P (regno)
4692 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4697 if (SSE_REGNO_P (regno) && TARGET_SSE)
4702 if (TARGET_SSE && SSE_REGNO_P (regno)
4703 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4707 /* TODO: The function should depend on current function ABI but
4708 builtins.c would need updating then. Therefore we use the
4711 /* RAX is used as hidden argument to va_arg functions. */
4712 if (ix86_abi == SYSV_ABI && regno == AX_REG)
4715 if (ix86_abi == MS_ABI)
4716 parm_regs = x86_64_ms_abi_int_parameter_registers;
4718 parm_regs = x86_64_int_parameter_registers;
4719 for (i = 0; i < (ix86_abi == MS_ABI
4720 ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX); i++)
4721 if (regno == parm_regs[i])
4726 /* Return if we do not know how to pass TYPE solely in registers. */
4729 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4731 if (must_pass_in_stack_var_size_or_pad (mode, type))
4734 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4735 The layout_type routine is crafty and tries to trick us into passing
4736 currently unsupported vector types on the stack by using TImode. */
4737 return (!TARGET_64BIT && mode == TImode
4738 && type && TREE_CODE (type) != VECTOR_TYPE);
4741 /* It returns the size, in bytes, of the area reserved for arguments passed
4742 in registers for the function represented by fndecl dependent to the used
4745 ix86_reg_parm_stack_space (const_tree fndecl)
4747 enum calling_abi call_abi = SYSV_ABI;
4748 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4749 call_abi = ix86_function_abi (fndecl);
4751 call_abi = ix86_function_type_abi (fndecl);
4752 if (call_abi == MS_ABI)
4757 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4760 ix86_function_type_abi (const_tree fntype)
4762 if (TARGET_64BIT && fntype != NULL)
4764 enum calling_abi abi = ix86_abi;
4765 if (abi == SYSV_ABI)
4767 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
4770 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
4778 ix86_function_ms_hook_prologue (const_tree fntype)
4782 if (lookup_attribute ("ms_hook_prologue", DECL_ATTRIBUTES (fntype)))
4784 if (decl_function_context (fntype) != NULL_TREE)
4786 error_at (DECL_SOURCE_LOCATION (fntype),
4787 "ms_hook_prologue is not compatible with nested function");
4796 static enum calling_abi
4797 ix86_function_abi (const_tree fndecl)
4801 return ix86_function_type_abi (TREE_TYPE (fndecl));
4804 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4807 ix86_cfun_abi (void)
4809 if (! cfun || ! TARGET_64BIT)
4811 return cfun->machine->call_abi;
4815 extern void init_regs (void);
4817 /* Implementation of call abi switching target hook. Specific to FNDECL
4818 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4819 for more details. */
4821 ix86_call_abi_override (const_tree fndecl)
4823 if (fndecl == NULL_TREE)
4824 cfun->machine->call_abi = ix86_abi;
4826 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4829 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4830 re-initialization of init_regs each time we switch function context since
4831 this is needed only during RTL expansion. */
4833 ix86_maybe_switch_abi (void)
4836 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4840 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4841 for a call to a function whose data type is FNTYPE.
4842 For a library call, FNTYPE is 0. */
4845 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4846 tree fntype, /* tree ptr for function decl */
4847 rtx libname, /* SYMBOL_REF of library name or 0 */
4850 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4851 memset (cum, 0, sizeof (*cum));
4854 cum->call_abi = ix86_function_abi (fndecl);
4856 cum->call_abi = ix86_function_type_abi (fntype);
4857 /* Set up the number of registers to use for passing arguments. */
4859 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4860 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
4861 "or subtarget optimization implying it");
4862 cum->nregs = ix86_regparm;
4865 if (cum->call_abi != ix86_abi)
4866 cum->nregs = (ix86_abi != SYSV_ABI
4867 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4871 cum->sse_nregs = SSE_REGPARM_MAX;
4874 if (cum->call_abi != ix86_abi)
4875 cum->sse_nregs = (ix86_abi != SYSV_ABI
4876 ? X86_64_SSE_REGPARM_MAX
4877 : X86_64_MS_SSE_REGPARM_MAX);
4881 cum->mmx_nregs = MMX_REGPARM_MAX;
4882 cum->warn_avx = true;
4883 cum->warn_sse = true;
4884 cum->warn_mmx = true;
4886 /* Because type might mismatch in between caller and callee, we need to
4887 use actual type of function for local calls.
4888 FIXME: cgraph_analyze can be told to actually record if function uses
4889 va_start so for local functions maybe_vaarg can be made aggressive
4891 FIXME: once typesytem is fixed, we won't need this code anymore. */
4893 fntype = TREE_TYPE (fndecl);
4894 cum->maybe_vaarg = (fntype
4895 ? (!prototype_p (fntype) || stdarg_p (fntype))
4900 /* If there are variable arguments, then we won't pass anything
4901 in registers in 32-bit mode. */
4902 if (stdarg_p (fntype))
4913 /* Use ecx and edx registers if function has fastcall attribute,
4914 else look for regparm information. */
4917 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4923 cum->nregs = ix86_function_regparm (fntype, fndecl);
4926 /* Set up the number of SSE registers used for passing SFmode
4927 and DFmode arguments. Warn for mismatching ABI. */
4928 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4932 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4933 But in the case of vector types, it is some vector mode.
4935 When we have only some of our vector isa extensions enabled, then there
4936 are some modes for which vector_mode_supported_p is false. For these
4937 modes, the generic vector support in gcc will choose some non-vector mode
4938 in order to implement the type. By computing the natural mode, we'll
4939 select the proper ABI location for the operand and not depend on whatever
4940 the middle-end decides to do with these vector types.
4942 The midde-end can't deal with the vector types > 16 bytes. In this
4943 case, we return the original mode and warn ABI change if CUM isn't
4946 static enum machine_mode
4947 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4949 enum machine_mode mode = TYPE_MODE (type);
4951 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4953 HOST_WIDE_INT size = int_size_in_bytes (type);
4954 if ((size == 8 || size == 16 || size == 32)
4955 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4956 && TYPE_VECTOR_SUBPARTS (type) > 1)
4958 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4960 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4961 mode = MIN_MODE_VECTOR_FLOAT;
4963 mode = MIN_MODE_VECTOR_INT;
4965 /* Get the mode which has this inner mode and number of units. */
4966 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4967 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4968 && GET_MODE_INNER (mode) == innermode)
4970 if (size == 32 && !TARGET_AVX)
4972 static bool warnedavx;
4979 warning (0, "AVX vector argument without AVX "
4980 "enabled changes the ABI");
4982 return TYPE_MODE (type);
4995 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4996 this may not agree with the mode that the type system has chosen for the
4997 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4998 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5001 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
5006 if (orig_mode != BLKmode)
5007 tmp = gen_rtx_REG (orig_mode, regno);
5010 tmp = gen_rtx_REG (mode, regno);
5011 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
5012 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
5018 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5019 of this code is to classify each 8bytes of incoming argument by the register
5020 class and assign registers accordingly. */
5022 /* Return the union class of CLASS1 and CLASS2.
5023 See the x86-64 PS ABI for details. */
5025 static enum x86_64_reg_class
5026 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
5028 /* Rule #1: If both classes are equal, this is the resulting class. */
5029 if (class1 == class2)
5032 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5034 if (class1 == X86_64_NO_CLASS)
5036 if (class2 == X86_64_NO_CLASS)
5039 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5040 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
5041 return X86_64_MEMORY_CLASS;
5043 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5044 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
5045 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
5046 return X86_64_INTEGERSI_CLASS;
5047 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
5048 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
5049 return X86_64_INTEGER_CLASS;
5051 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5053 if (class1 == X86_64_X87_CLASS
5054 || class1 == X86_64_X87UP_CLASS
5055 || class1 == X86_64_COMPLEX_X87_CLASS
5056 || class2 == X86_64_X87_CLASS
5057 || class2 == X86_64_X87UP_CLASS
5058 || class2 == X86_64_COMPLEX_X87_CLASS)
5059 return X86_64_MEMORY_CLASS;
5061 /* Rule #6: Otherwise class SSE is used. */
5062 return X86_64_SSE_CLASS;
5065 /* Classify the argument of type TYPE and mode MODE.
5066 CLASSES will be filled by the register class used to pass each word
5067 of the operand. The number of words is returned. In case the parameter
5068 should be passed in memory, 0 is returned. As a special case for zero
5069 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5071 BIT_OFFSET is used internally for handling records and specifies offset
5072 of the offset in bits modulo 256 to avoid overflow cases.
5074 See the x86-64 PS ABI for details.
5078 classify_argument (enum machine_mode mode, const_tree type,
5079 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
5081 HOST_WIDE_INT bytes =
5082 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5083 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5085 /* Variable sized entities are always passed/returned in memory. */
5089 if (mode != VOIDmode
5090 && targetm.calls.must_pass_in_stack (mode, type))
5093 if (type && AGGREGATE_TYPE_P (type))
5097 enum x86_64_reg_class subclasses[MAX_CLASSES];
5099 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5103 for (i = 0; i < words; i++)
5104 classes[i] = X86_64_NO_CLASS;
5106 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5107 signalize memory class, so handle it as special case. */
5110 classes[0] = X86_64_NO_CLASS;
5114 /* Classify each field of record and merge classes. */
5115 switch (TREE_CODE (type))
5118 /* And now merge the fields of structure. */
5119 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5121 if (TREE_CODE (field) == FIELD_DECL)
5125 if (TREE_TYPE (field) == error_mark_node)
5128 /* Bitfields are always classified as integer. Handle them
5129 early, since later code would consider them to be
5130 misaligned integers. */
5131 if (DECL_BIT_FIELD (field))
5133 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5134 i < ((int_bit_position (field) + (bit_offset % 64))
5135 + tree_low_cst (DECL_SIZE (field), 0)
5138 merge_classes (X86_64_INTEGER_CLASS,
5145 type = TREE_TYPE (field);
5147 /* Flexible array member is ignored. */
5148 if (TYPE_MODE (type) == BLKmode
5149 && TREE_CODE (type) == ARRAY_TYPE
5150 && TYPE_SIZE (type) == NULL_TREE
5151 && TYPE_DOMAIN (type) != NULL_TREE
5152 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5157 if (!warned && warn_psabi)
5160 inform (input_location,
5161 "The ABI of passing struct with"
5162 " a flexible array member has"
5163 " changed in GCC 4.4");
5167 num = classify_argument (TYPE_MODE (type), type,
5169 (int_bit_position (field)
5170 + bit_offset) % 256);
5173 pos = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5174 for (i = 0; i < num && (i + pos) < words; i++)
5176 merge_classes (subclasses[i], classes[i + pos]);
5183 /* Arrays are handled as small records. */
5186 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5187 TREE_TYPE (type), subclasses, bit_offset);
5191 /* The partial classes are now full classes. */
5192 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5193 subclasses[0] = X86_64_SSE_CLASS;
5194 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5195 && !((bit_offset % 64) == 0 && bytes == 4))
5196 subclasses[0] = X86_64_INTEGER_CLASS;
5198 for (i = 0; i < words; i++)
5199 classes[i] = subclasses[i % num];
5204 case QUAL_UNION_TYPE:
5205 /* Unions are similar to RECORD_TYPE but offset is always 0.
5207 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5209 if (TREE_CODE (field) == FIELD_DECL)
5213 if (TREE_TYPE (field) == error_mark_node)
5216 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5217 TREE_TYPE (field), subclasses,
5221 for (i = 0; i < num; i++)
5222 classes[i] = merge_classes (subclasses[i], classes[i]);
5233 /* When size > 16 bytes, if the first one isn't
5234 X86_64_SSE_CLASS or any other ones aren't
5235 X86_64_SSEUP_CLASS, everything should be passed in
5237 if (classes[0] != X86_64_SSE_CLASS)
5240 for (i = 1; i < words; i++)
5241 if (classes[i] != X86_64_SSEUP_CLASS)
5245 /* Final merger cleanup. */
5246 for (i = 0; i < words; i++)
5248 /* If one class is MEMORY, everything should be passed in
5250 if (classes[i] == X86_64_MEMORY_CLASS)
5253 /* The X86_64_SSEUP_CLASS should be always preceded by
5254 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5255 if (classes[i] == X86_64_SSEUP_CLASS
5256 && classes[i - 1] != X86_64_SSE_CLASS
5257 && classes[i - 1] != X86_64_SSEUP_CLASS)
5259 /* The first one should never be X86_64_SSEUP_CLASS. */
5260 gcc_assert (i != 0);
5261 classes[i] = X86_64_SSE_CLASS;
5264 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5265 everything should be passed in memory. */
5266 if (classes[i] == X86_64_X87UP_CLASS
5267 && (classes[i - 1] != X86_64_X87_CLASS))
5271 /* The first one should never be X86_64_X87UP_CLASS. */
5272 gcc_assert (i != 0);
5273 if (!warned && warn_psabi)
5276 inform (input_location,
5277 "The ABI of passing union with long double"
5278 " has changed in GCC 4.4");
5286 /* Compute alignment needed. We align all types to natural boundaries with
5287 exception of XFmode that is aligned to 64bits. */
5288 if (mode != VOIDmode && mode != BLKmode)
5290 int mode_alignment = GET_MODE_BITSIZE (mode);
5293 mode_alignment = 128;
5294 else if (mode == XCmode)
5295 mode_alignment = 256;
5296 if (COMPLEX_MODE_P (mode))
5297 mode_alignment /= 2;
5298 /* Misaligned fields are always returned in memory. */
5299 if (bit_offset % mode_alignment)
5303 /* for V1xx modes, just use the base mode */
5304 if (VECTOR_MODE_P (mode) && mode != V1DImode
5305 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5306 mode = GET_MODE_INNER (mode);
5308 /* Classification of atomic types. */
5313 classes[0] = X86_64_SSE_CLASS;
5316 classes[0] = X86_64_SSE_CLASS;
5317 classes[1] = X86_64_SSEUP_CLASS;
5327 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5331 classes[0] = X86_64_INTEGERSI_CLASS;
5334 else if (size <= 64)
5336 classes[0] = X86_64_INTEGER_CLASS;
5339 else if (size <= 64+32)
5341 classes[0] = X86_64_INTEGER_CLASS;
5342 classes[1] = X86_64_INTEGERSI_CLASS;
5345 else if (size <= 64+64)
5347 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5355 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5359 /* OImode shouldn't be used directly. */
5364 if (!(bit_offset % 64))
5365 classes[0] = X86_64_SSESF_CLASS;
5367 classes[0] = X86_64_SSE_CLASS;
5370 classes[0] = X86_64_SSEDF_CLASS;
5373 classes[0] = X86_64_X87_CLASS;
5374 classes[1] = X86_64_X87UP_CLASS;
5377 classes[0] = X86_64_SSE_CLASS;
5378 classes[1] = X86_64_SSEUP_CLASS;
5381 classes[0] = X86_64_SSE_CLASS;
5382 if (!(bit_offset % 64))
5388 if (!warned && warn_psabi)
5391 inform (input_location,
5392 "The ABI of passing structure with complex float"
5393 " member has changed in GCC 4.4");
5395 classes[1] = X86_64_SSESF_CLASS;
5399 classes[0] = X86_64_SSEDF_CLASS;
5400 classes[1] = X86_64_SSEDF_CLASS;
5403 classes[0] = X86_64_COMPLEX_X87_CLASS;
5406 /* This modes is larger than 16 bytes. */
5414 classes[0] = X86_64_SSE_CLASS;
5415 classes[1] = X86_64_SSEUP_CLASS;
5416 classes[2] = X86_64_SSEUP_CLASS;
5417 classes[3] = X86_64_SSEUP_CLASS;
5425 classes[0] = X86_64_SSE_CLASS;
5426 classes[1] = X86_64_SSEUP_CLASS;
5433 classes[0] = X86_64_SSE_CLASS;
5439 gcc_assert (VECTOR_MODE_P (mode));
5444 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5446 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5447 classes[0] = X86_64_INTEGERSI_CLASS;
5449 classes[0] = X86_64_INTEGER_CLASS;
5450 classes[1] = X86_64_INTEGER_CLASS;
5451 return 1 + (bytes > 8);
5455 /* Examine the argument and return set number of register required in each
5456 class. Return 0 iff parameter should be passed in memory. */
5458 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5459 int *int_nregs, int *sse_nregs)
5461 enum x86_64_reg_class regclass[MAX_CLASSES];
5462 int n = classify_argument (mode, type, regclass, 0);
5468 for (n--; n >= 0; n--)
5469 switch (regclass[n])
5471 case X86_64_INTEGER_CLASS:
5472 case X86_64_INTEGERSI_CLASS:
5475 case X86_64_SSE_CLASS:
5476 case X86_64_SSESF_CLASS:
5477 case X86_64_SSEDF_CLASS:
5480 case X86_64_NO_CLASS:
5481 case X86_64_SSEUP_CLASS:
5483 case X86_64_X87_CLASS:
5484 case X86_64_X87UP_CLASS:
5488 case X86_64_COMPLEX_X87_CLASS:
5489 return in_return ? 2 : 0;
5490 case X86_64_MEMORY_CLASS:
5496 /* Construct container for the argument used by GCC interface. See
5497 FUNCTION_ARG for the detailed description. */
5500 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5501 const_tree type, int in_return, int nintregs, int nsseregs,
5502 const int *intreg, int sse_regno)
5504 /* The following variables hold the static issued_error state. */
5505 static bool issued_sse_arg_error;
5506 static bool issued_sse_ret_error;
5507 static bool issued_x87_ret_error;
5509 enum machine_mode tmpmode;
5511 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5512 enum x86_64_reg_class regclass[MAX_CLASSES];
5516 int needed_sseregs, needed_intregs;
5517 rtx exp[MAX_CLASSES];
5520 n = classify_argument (mode, type, regclass, 0);
5523 if (!examine_argument (mode, type, in_return, &needed_intregs,
5526 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5529 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5530 some less clueful developer tries to use floating-point anyway. */
5531 if (needed_sseregs && !TARGET_SSE)
5535 if (!issued_sse_ret_error)
5537 error ("SSE register return with SSE disabled");
5538 issued_sse_ret_error = true;
5541 else if (!issued_sse_arg_error)
5543 error ("SSE register argument with SSE disabled");
5544 issued_sse_arg_error = true;
5549 /* Likewise, error if the ABI requires us to return values in the
5550 x87 registers and the user specified -mno-80387. */
5551 if (!TARGET_80387 && in_return)
5552 for (i = 0; i < n; i++)
5553 if (regclass[i] == X86_64_X87_CLASS
5554 || regclass[i] == X86_64_X87UP_CLASS
5555 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5557 if (!issued_x87_ret_error)
5559 error ("x87 register return with x87 disabled");
5560 issued_x87_ret_error = true;
5565 /* First construct simple cases. Avoid SCmode, since we want to use
5566 single register to pass this type. */
5567 if (n == 1 && mode != SCmode)
5568 switch (regclass[0])
5570 case X86_64_INTEGER_CLASS:
5571 case X86_64_INTEGERSI_CLASS:
5572 return gen_rtx_REG (mode, intreg[0]);
5573 case X86_64_SSE_CLASS:
5574 case X86_64_SSESF_CLASS:
5575 case X86_64_SSEDF_CLASS:
5576 if (mode != BLKmode)
5577 return gen_reg_or_parallel (mode, orig_mode,
5578 SSE_REGNO (sse_regno));
5580 case X86_64_X87_CLASS:
5581 case X86_64_COMPLEX_X87_CLASS:
5582 return gen_rtx_REG (mode, FIRST_STACK_REG);
5583 case X86_64_NO_CLASS:
5584 /* Zero sized array, struct or class. */
5589 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5590 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5591 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5593 && regclass[0] == X86_64_SSE_CLASS
5594 && regclass[1] == X86_64_SSEUP_CLASS
5595 && regclass[2] == X86_64_SSEUP_CLASS
5596 && regclass[3] == X86_64_SSEUP_CLASS
5598 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5601 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5602 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5603 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5604 && regclass[1] == X86_64_INTEGER_CLASS
5605 && (mode == CDImode || mode == TImode || mode == TFmode)
5606 && intreg[0] + 1 == intreg[1])
5607 return gen_rtx_REG (mode, intreg[0]);
5609 /* Otherwise figure out the entries of the PARALLEL. */
5610 for (i = 0; i < n; i++)
5614 switch (regclass[i])
5616 case X86_64_NO_CLASS:
5618 case X86_64_INTEGER_CLASS:
5619 case X86_64_INTEGERSI_CLASS:
5620 /* Merge TImodes on aligned occasions here too. */
5621 if (i * 8 + 8 > bytes)
5622 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5623 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5627 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5628 if (tmpmode == BLKmode)
5630 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5631 gen_rtx_REG (tmpmode, *intreg),
5635 case X86_64_SSESF_CLASS:
5636 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5637 gen_rtx_REG (SFmode,
5638 SSE_REGNO (sse_regno)),
5642 case X86_64_SSEDF_CLASS:
5643 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5644 gen_rtx_REG (DFmode,
5645 SSE_REGNO (sse_regno)),
5649 case X86_64_SSE_CLASS:
5657 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5667 && regclass[1] == X86_64_SSEUP_CLASS
5668 && regclass[2] == X86_64_SSEUP_CLASS
5669 && regclass[3] == X86_64_SSEUP_CLASS);
5676 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5677 gen_rtx_REG (tmpmode,
5678 SSE_REGNO (sse_regno)),
5687 /* Empty aligned struct, union or class. */
5691 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5692 for (i = 0; i < nexps; i++)
5693 XVECEXP (ret, 0, i) = exp [i];
5697 /* Update the data in CUM to advance over an argument of mode MODE
5698 and data type TYPE. (TYPE is null for libcalls where that information
5699 may not be available.) */
5702 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5703 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5719 cum->words += words;
5720 cum->nregs -= words;
5721 cum->regno += words;
5723 if (cum->nregs <= 0)
5731 /* OImode shouldn't be used directly. */
5735 if (cum->float_in_sse < 2)
5738 if (cum->float_in_sse < 1)
5755 if (!type || !AGGREGATE_TYPE_P (type))
5757 cum->sse_words += words;
5758 cum->sse_nregs -= 1;
5759 cum->sse_regno += 1;
5760 if (cum->sse_nregs <= 0)
5773 if (!type || !AGGREGATE_TYPE_P (type))
5775 cum->mmx_words += words;
5776 cum->mmx_nregs -= 1;
5777 cum->mmx_regno += 1;
5778 if (cum->mmx_nregs <= 0)
5789 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5790 tree type, HOST_WIDE_INT words, int named)
5792 int int_nregs, sse_nregs;
5794 /* Unnamed 256bit vector mode parameters are passed on stack. */
5795 if (!named && VALID_AVX256_REG_MODE (mode))
5798 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5799 cum->words += words;
5800 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5802 cum->nregs -= int_nregs;
5803 cum->sse_nregs -= sse_nregs;
5804 cum->regno += int_nregs;
5805 cum->sse_regno += sse_nregs;
5808 cum->words += words;
5812 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5813 HOST_WIDE_INT words)
5815 /* Otherwise, this should be passed indirect. */
5816 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5818 cum->words += words;
5827 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5828 tree type, int named)
5830 HOST_WIDE_INT bytes, words;
5832 if (mode == BLKmode)
5833 bytes = int_size_in_bytes (type);
5835 bytes = GET_MODE_SIZE (mode);
5836 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5839 mode = type_natural_mode (type, NULL);
5841 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5842 function_arg_advance_ms_64 (cum, bytes, words);
5843 else if (TARGET_64BIT)
5844 function_arg_advance_64 (cum, mode, type, words, named);
5846 function_arg_advance_32 (cum, mode, type, bytes, words);
5849 /* Define where to put the arguments to a function.
5850 Value is zero to push the argument on the stack,
5851 or a hard register in which to store the argument.
5853 MODE is the argument's machine mode.
5854 TYPE is the data type of the argument (as a tree).
5855 This is null for libcalls where that information may
5857 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5858 the preceding args and about the function being called.
5859 NAMED is nonzero if this argument is a named parameter
5860 (otherwise it is an extra parameter matching an ellipsis). */
5863 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5864 enum machine_mode orig_mode, tree type,
5865 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5867 static bool warnedsse, warnedmmx;
5869 /* Avoid the AL settings for the Unix64 ABI. */
5870 if (mode == VOIDmode)
5886 if (words <= cum->nregs)
5888 int regno = cum->regno;
5890 /* Fastcall allocates the first two DWORD (SImode) or
5891 smaller arguments to ECX and EDX if it isn't an
5897 || (type && AGGREGATE_TYPE_P (type)))
5900 /* ECX not EAX is the first allocated register. */
5901 if (regno == AX_REG)
5904 return gen_rtx_REG (mode, regno);
5909 if (cum->float_in_sse < 2)
5912 if (cum->float_in_sse < 1)
5916 /* In 32bit, we pass TImode in xmm registers. */
5923 if (!type || !AGGREGATE_TYPE_P (type))
5925 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5928 warning (0, "SSE vector argument without SSE enabled "
5932 return gen_reg_or_parallel (mode, orig_mode,
5933 cum->sse_regno + FIRST_SSE_REG);
5938 /* OImode shouldn't be used directly. */
5947 if (!type || !AGGREGATE_TYPE_P (type))
5950 return gen_reg_or_parallel (mode, orig_mode,
5951 cum->sse_regno + FIRST_SSE_REG);
5960 if (!type || !AGGREGATE_TYPE_P (type))
5962 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5965 warning (0, "MMX vector argument without MMX enabled "
5969 return gen_reg_or_parallel (mode, orig_mode,
5970 cum->mmx_regno + FIRST_MMX_REG);
5979 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5980 enum machine_mode orig_mode, tree type, int named)
5982 /* Handle a hidden AL argument containing number of registers
5983 for varargs x86-64 functions. */
5984 if (mode == VOIDmode)
5985 return GEN_INT (cum->maybe_vaarg
5986 ? (cum->sse_nregs < 0
5987 ? (cum->call_abi == ix86_abi
5989 : (ix86_abi != SYSV_ABI
5990 ? X86_64_SSE_REGPARM_MAX
5991 : X86_64_MS_SSE_REGPARM_MAX))
6006 /* Unnamed 256bit vector mode parameters are passed on stack. */
6012 return construct_container (mode, orig_mode, type, 0, cum->nregs,
6014 &x86_64_int_parameter_registers [cum->regno],
6019 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6020 enum machine_mode orig_mode, int named,
6021 HOST_WIDE_INT bytes)
6025 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6026 We use value of -2 to specify that current function call is MSABI. */
6027 if (mode == VOIDmode)
6028 return GEN_INT (-2);
6030 /* If we've run out of registers, it goes on the stack. */
6031 if (cum->nregs == 0)
6034 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
6036 /* Only floating point modes are passed in anything but integer regs. */
6037 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
6040 regno = cum->regno + FIRST_SSE_REG;
6045 /* Unnamed floating parameters are passed in both the
6046 SSE and integer registers. */
6047 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
6048 t2 = gen_rtx_REG (mode, regno);
6049 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
6050 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
6051 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
6054 /* Handle aggregated types passed in register. */
6055 if (orig_mode == BLKmode)
6057 if (bytes > 0 && bytes <= 8)
6058 mode = (bytes > 4 ? DImode : SImode);
6059 if (mode == BLKmode)
6063 return gen_reg_or_parallel (mode, orig_mode, regno);
6067 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
6068 tree type, int named)
6070 enum machine_mode mode = omode;
6071 HOST_WIDE_INT bytes, words;
6073 if (mode == BLKmode)
6074 bytes = int_size_in_bytes (type);
6076 bytes = GET_MODE_SIZE (mode);
6077 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6079 /* To simplify the code below, represent vector types with a vector mode
6080 even if MMX/SSE are not active. */
6081 if (type && TREE_CODE (type) == VECTOR_TYPE)
6082 mode = type_natural_mode (type, cum);
6084 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6085 return function_arg_ms_64 (cum, mode, omode, named, bytes);
6086 else if (TARGET_64BIT)
6087 return function_arg_64 (cum, mode, omode, type, named);
6089 return function_arg_32 (cum, mode, omode, type, bytes, words);
6092 /* A C expression that indicates when an argument must be passed by
6093 reference. If nonzero for an argument, a copy of that argument is
6094 made in memory and a pointer to the argument is passed instead of
6095 the argument itself. The pointer is passed in whatever way is
6096 appropriate for passing a pointer to that type. */
6099 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6100 enum machine_mode mode ATTRIBUTE_UNUSED,
6101 const_tree type, bool named ATTRIBUTE_UNUSED)
6103 /* See Windows x64 Software Convention. */
6104 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6106 int msize = (int) GET_MODE_SIZE (mode);
6109 /* Arrays are passed by reference. */
6110 if (TREE_CODE (type) == ARRAY_TYPE)
6113 if (AGGREGATE_TYPE_P (type))
6115 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6116 are passed by reference. */
6117 msize = int_size_in_bytes (type);
6121 /* __m128 is passed by reference. */
6123 case 1: case 2: case 4: case 8:
6129 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
6135 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6138 contains_aligned_value_p (tree type)
6140 enum machine_mode mode = TYPE_MODE (type);
6141 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6145 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6147 if (TYPE_ALIGN (type) < 128)
6150 if (AGGREGATE_TYPE_P (type))
6152 /* Walk the aggregates recursively. */
6153 switch (TREE_CODE (type))
6157 case QUAL_UNION_TYPE:
6161 /* Walk all the structure fields. */
6162 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6164 if (TREE_CODE (field) == FIELD_DECL
6165 && contains_aligned_value_p (TREE_TYPE (field)))
6172 /* Just for use if some languages passes arrays by value. */
6173 if (contains_aligned_value_p (TREE_TYPE (type)))
6184 /* Gives the alignment boundary, in bits, of an argument with the
6185 specified mode and type. */
6188 ix86_function_arg_boundary (enum machine_mode mode, tree type)
6193 /* Since canonical type is used for call, we convert it to
6194 canonical type if needed. */
6195 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6196 type = TYPE_CANONICAL (type);
6197 align = TYPE_ALIGN (type);
6200 align = GET_MODE_ALIGNMENT (mode);
6201 if (align < PARM_BOUNDARY)
6202 align = PARM_BOUNDARY;
6203 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6204 natural boundaries. */
6205 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6207 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6208 make an exception for SSE modes since these require 128bit
6211 The handling here differs from field_alignment. ICC aligns MMX
6212 arguments to 4 byte boundaries, while structure fields are aligned
6213 to 8 byte boundaries. */
6216 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6217 align = PARM_BOUNDARY;
6221 if (!contains_aligned_value_p (type))
6222 align = PARM_BOUNDARY;
6225 if (align > BIGGEST_ALIGNMENT)
6226 align = BIGGEST_ALIGNMENT;
6230 /* Return true if N is a possible register number of function value. */
6233 ix86_function_value_regno_p (int regno)
6240 case FIRST_FLOAT_REG:
6241 /* TODO: The function should depend on current function ABI but
6242 builtins.c would need updating then. Therefore we use the
6244 if (TARGET_64BIT && ix86_abi == MS_ABI)
6246 return TARGET_FLOAT_RETURNS_IN_80387;
6252 if (TARGET_MACHO || TARGET_64BIT)
6260 /* Define how to find the value returned by a function.
6261 VALTYPE is the data type of the value (as a tree).
6262 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6263 otherwise, FUNC is 0. */
6266 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6267 const_tree fntype, const_tree fn)
6271 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6272 we normally prevent this case when mmx is not available. However
6273 some ABIs may require the result to be returned like DImode. */
6274 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6275 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6277 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6278 we prevent this case when sse is not available. However some ABIs
6279 may require the result to be returned like integer TImode. */
6280 else if (mode == TImode
6281 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6282 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6284 /* 32-byte vector modes in %ymm0. */
6285 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6286 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6288 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6289 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6290 regno = FIRST_FLOAT_REG;
6292 /* Most things go in %eax. */
6295 /* Override FP return register with %xmm0 for local functions when
6296 SSE math is enabled or for functions with sseregparm attribute. */
6297 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6299 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6300 if ((sse_level >= 1 && mode == SFmode)
6301 || (sse_level == 2 && mode == DFmode))
6302 regno = FIRST_SSE_REG;
6305 /* OImode shouldn't be used directly. */
6306 gcc_assert (mode != OImode);
6308 return gen_rtx_REG (orig_mode, regno);
6312 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6317 /* Handle libcalls, which don't provide a type node. */
6318 if (valtype == NULL)
6330 return gen_rtx_REG (mode, FIRST_SSE_REG);
6333 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6337 return gen_rtx_REG (mode, AX_REG);
6341 ret = construct_container (mode, orig_mode, valtype, 1,
6342 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6343 x86_64_int_return_registers, 0);
6345 /* For zero sized structures, construct_container returns NULL, but we
6346 need to keep rest of compiler happy by returning meaningful value. */
6348 ret = gen_rtx_REG (orig_mode, AX_REG);
6354 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6356 unsigned int regno = AX_REG;
6360 switch (GET_MODE_SIZE (mode))
6363 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6364 && !COMPLEX_MODE_P (mode))
6365 regno = FIRST_SSE_REG;
6369 if (mode == SFmode || mode == DFmode)
6370 regno = FIRST_SSE_REG;
6376 return gen_rtx_REG (orig_mode, regno);
6380 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6381 enum machine_mode orig_mode, enum machine_mode mode)
6383 const_tree fn, fntype;
6386 if (fntype_or_decl && DECL_P (fntype_or_decl))
6387 fn = fntype_or_decl;
6388 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6390 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6391 return function_value_ms_64 (orig_mode, mode);
6392 else if (TARGET_64BIT)
6393 return function_value_64 (orig_mode, mode, valtype);
6395 return function_value_32 (orig_mode, mode, fntype, fn);
6399 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6400 bool outgoing ATTRIBUTE_UNUSED)
6402 enum machine_mode mode, orig_mode;
6404 orig_mode = TYPE_MODE (valtype);
6405 mode = type_natural_mode (valtype, NULL);
6406 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6410 ix86_libcall_value (enum machine_mode mode)
6412 return ix86_function_value_1 (NULL, NULL, mode, mode);
6415 /* Return true iff type is returned in memory. */
6417 static int ATTRIBUTE_UNUSED
6418 return_in_memory_32 (const_tree type, enum machine_mode mode)
6422 if (mode == BLKmode)
6425 size = int_size_in_bytes (type);
6427 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6430 if (VECTOR_MODE_P (mode) || mode == TImode)
6432 /* User-created vectors small enough to fit in EAX. */
6436 /* MMX/3dNow values are returned in MM0,
6437 except when it doesn't exits. */
6439 return (TARGET_MMX ? 0 : 1);
6441 /* SSE values are returned in XMM0, except when it doesn't exist. */
6443 return (TARGET_SSE ? 0 : 1);
6445 /* AVX values are returned in YMM0, except when it doesn't exist. */
6447 return TARGET_AVX ? 0 : 1;
6456 /* OImode shouldn't be used directly. */
6457 gcc_assert (mode != OImode);
6462 static int ATTRIBUTE_UNUSED
6463 return_in_memory_64 (const_tree type, enum machine_mode mode)
6465 int needed_intregs, needed_sseregs;
6466 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6469 static int ATTRIBUTE_UNUSED
6470 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6472 HOST_WIDE_INT size = int_size_in_bytes (type);
6474 /* __m128 is returned in xmm0. */
6475 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6476 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6479 /* Otherwise, the size must be exactly in [1248]. */
6480 return (size != 1 && size != 2 && size != 4 && size != 8);
6484 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6486 #ifdef SUBTARGET_RETURN_IN_MEMORY
6487 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6489 const enum machine_mode mode = type_natural_mode (type, NULL);
6493 if (ix86_function_type_abi (fntype) == MS_ABI)
6494 return return_in_memory_ms_64 (type, mode);
6496 return return_in_memory_64 (type, mode);
6499 return return_in_memory_32 (type, mode);
6503 /* Return false iff TYPE is returned in memory. This version is used
6504 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6505 but differs notably in that when MMX is available, 8-byte vectors
6506 are returned in memory, rather than in MMX registers. */
6509 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6512 enum machine_mode mode = type_natural_mode (type, NULL);
6515 return return_in_memory_64 (type, mode);
6517 if (mode == BLKmode)
6520 size = int_size_in_bytes (type);
6522 if (VECTOR_MODE_P (mode))
6524 /* Return in memory only if MMX registers *are* available. This
6525 seems backwards, but it is consistent with the existing
6532 else if (mode == TImode)
6534 else if (mode == XFmode)
6540 /* When returning SSE vector types, we have a choice of either
6541 (1) being abi incompatible with a -march switch, or
6542 (2) generating an error.
6543 Given no good solution, I think the safest thing is one warning.
6544 The user won't be able to use -Werror, but....
6546 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6547 called in response to actually generating a caller or callee that
6548 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6549 via aggregate_value_p for general type probing from tree-ssa. */
6552 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6554 static bool warnedsse, warnedmmx;
6556 if (!TARGET_64BIT && type)
6558 /* Look at the return type of the function, not the function type. */
6559 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6561 if (!TARGET_SSE && !warnedsse)
6564 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6567 warning (0, "SSE vector return without SSE enabled "
6572 if (!TARGET_MMX && !warnedmmx)
6574 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6577 warning (0, "MMX vector return without MMX enabled "
6587 /* Create the va_list data type. */
6589 /* Returns the calling convention specific va_list date type.
6590 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6593 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6595 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6597 /* For i386 we use plain pointer to argument area. */
6598 if (!TARGET_64BIT || abi == MS_ABI)
6599 return build_pointer_type (char_type_node);
6601 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6602 type_decl = build_decl (BUILTINS_LOCATION,
6603 TYPE_DECL, get_identifier ("__va_list_tag"), record);
6605 f_gpr = build_decl (BUILTINS_LOCATION,
6606 FIELD_DECL, get_identifier ("gp_offset"),
6607 unsigned_type_node);
6608 f_fpr = build_decl (BUILTINS_LOCATION,
6609 FIELD_DECL, get_identifier ("fp_offset"),
6610 unsigned_type_node);
6611 f_ovf = build_decl (BUILTINS_LOCATION,
6612 FIELD_DECL, get_identifier ("overflow_arg_area"),
6614 f_sav = build_decl (BUILTINS_LOCATION,
6615 FIELD_DECL, get_identifier ("reg_save_area"),
6618 va_list_gpr_counter_field = f_gpr;
6619 va_list_fpr_counter_field = f_fpr;
6621 DECL_FIELD_CONTEXT (f_gpr) = record;
6622 DECL_FIELD_CONTEXT (f_fpr) = record;
6623 DECL_FIELD_CONTEXT (f_ovf) = record;
6624 DECL_FIELD_CONTEXT (f_sav) = record;
6626 TREE_CHAIN (record) = type_decl;
6627 TYPE_NAME (record) = type_decl;
6628 TYPE_FIELDS (record) = f_gpr;
6629 TREE_CHAIN (f_gpr) = f_fpr;
6630 TREE_CHAIN (f_fpr) = f_ovf;
6631 TREE_CHAIN (f_ovf) = f_sav;
6633 layout_type (record);
6635 /* The correct type is an array type of one element. */
6636 return build_array_type (record, build_index_type (size_zero_node));
6639 /* Setup the builtin va_list data type and for 64-bit the additional
6640 calling convention specific va_list data types. */
6643 ix86_build_builtin_va_list (void)
6645 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
6647 /* Initialize abi specific va_list builtin types. */
6651 if (ix86_abi == MS_ABI)
6653 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6654 if (TREE_CODE (t) != RECORD_TYPE)
6655 t = build_variant_type_copy (t);
6656 sysv_va_list_type_node = t;
6661 if (TREE_CODE (t) != RECORD_TYPE)
6662 t = build_variant_type_copy (t);
6663 sysv_va_list_type_node = t;
6665 if (ix86_abi != MS_ABI)
6667 t = ix86_build_builtin_va_list_abi (MS_ABI);
6668 if (TREE_CODE (t) != RECORD_TYPE)
6669 t = build_variant_type_copy (t);
6670 ms_va_list_type_node = t;
6675 if (TREE_CODE (t) != RECORD_TYPE)
6676 t = build_variant_type_copy (t);
6677 ms_va_list_type_node = t;
6684 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6687 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6696 int regparm = ix86_regparm;
6698 if (cum->call_abi != ix86_abi)
6699 regparm = (ix86_abi != SYSV_ABI
6700 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
6702 /* GPR size of varargs save area. */
6703 if (cfun->va_list_gpr_size)
6704 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6706 ix86_varargs_gpr_size = 0;
6708 /* FPR size of varargs save area. We don't need it if we don't pass
6709 anything in SSE registers. */
6710 if (cum->sse_nregs && cfun->va_list_fpr_size)
6711 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6713 ix86_varargs_fpr_size = 0;
6715 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6718 save_area = frame_pointer_rtx;
6719 set = get_varargs_alias_set ();
6721 for (i = cum->regno;
6723 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6726 mem = gen_rtx_MEM (Pmode,
6727 plus_constant (save_area, i * UNITS_PER_WORD));
6728 MEM_NOTRAP_P (mem) = 1;
6729 set_mem_alias_set (mem, set);
6730 emit_move_insn (mem, gen_rtx_REG (Pmode,
6731 x86_64_int_parameter_registers[i]));
6734 if (ix86_varargs_fpr_size)
6736 /* Now emit code to save SSE registers. The AX parameter contains number
6737 of SSE parameter registers used to call this function. We use
6738 sse_prologue_save insn template that produces computed jump across
6739 SSE saves. We need some preparation work to get this working. */
6741 label = gen_label_rtx ();
6742 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6744 /* Compute address to jump to :
6745 label - eax*4 + nnamed_sse_arguments*4 Or
6746 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6747 tmp_reg = gen_reg_rtx (Pmode);
6748 nsse_reg = gen_reg_rtx (Pmode);
6749 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6750 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6751 gen_rtx_MULT (Pmode, nsse_reg,
6754 /* vmovaps is one byte longer than movaps. */
6756 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6757 gen_rtx_PLUS (Pmode, tmp_reg,
6763 gen_rtx_CONST (DImode,
6764 gen_rtx_PLUS (DImode,
6766 GEN_INT (cum->sse_regno
6767 * (TARGET_AVX ? 5 : 4)))));
6769 emit_move_insn (nsse_reg, label_ref);
6770 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6772 /* Compute address of memory block we save into. We always use pointer
6773 pointing 127 bytes after first byte to store - this is needed to keep
6774 instruction size limited by 4 bytes (5 bytes for AVX) with one
6775 byte displacement. */
6776 tmp_reg = gen_reg_rtx (Pmode);
6777 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6778 plus_constant (save_area,
6779 ix86_varargs_gpr_size + 127)));
6780 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6781 MEM_NOTRAP_P (mem) = 1;
6782 set_mem_alias_set (mem, set);
6783 set_mem_align (mem, BITS_PER_WORD);
6785 /* And finally do the dirty job! */
6786 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6787 GEN_INT (cum->sse_regno), label));
6792 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6794 alias_set_type set = get_varargs_alias_set ();
6797 for (i = cum->regno; i < X86_64_MS_REGPARM_MAX; i++)
6801 mem = gen_rtx_MEM (Pmode,
6802 plus_constant (virtual_incoming_args_rtx,
6803 i * UNITS_PER_WORD));
6804 MEM_NOTRAP_P (mem) = 1;
6805 set_mem_alias_set (mem, set);
6807 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6808 emit_move_insn (mem, reg);
6813 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6814 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6817 CUMULATIVE_ARGS next_cum;
6820 /* This argument doesn't appear to be used anymore. Which is good,
6821 because the old code here didn't suppress rtl generation. */
6822 gcc_assert (!no_rtl);
6827 fntype = TREE_TYPE (current_function_decl);
6829 /* For varargs, we do not want to skip the dummy va_dcl argument.
6830 For stdargs, we do want to skip the last named argument. */
6832 if (stdarg_p (fntype))
6833 function_arg_advance (&next_cum, mode, type, 1);
6835 if (cum->call_abi == MS_ABI)
6836 setup_incoming_varargs_ms_64 (&next_cum);
6838 setup_incoming_varargs_64 (&next_cum);
6841 /* Checks if TYPE is of kind va_list char *. */
6844 is_va_list_char_pointer (tree type)
6848 /* For 32-bit it is always true. */
6851 canonic = ix86_canonical_va_list_type (type);
6852 return (canonic == ms_va_list_type_node
6853 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
6856 /* Implement va_start. */
6859 ix86_va_start (tree valist, rtx nextarg)
6861 HOST_WIDE_INT words, n_gpr, n_fpr;
6862 tree f_gpr, f_fpr, f_ovf, f_sav;
6863 tree gpr, fpr, ovf, sav, t;
6866 /* Only 64bit target needs something special. */
6867 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6869 std_expand_builtin_va_start (valist, nextarg);
6873 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6874 f_fpr = TREE_CHAIN (f_gpr);
6875 f_ovf = TREE_CHAIN (f_fpr);
6876 f_sav = TREE_CHAIN (f_ovf);
6878 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6879 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6880 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6881 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6882 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6884 /* Count number of gp and fp argument registers used. */
6885 words = crtl->args.info.words;
6886 n_gpr = crtl->args.info.regno;
6887 n_fpr = crtl->args.info.sse_regno;
6889 if (cfun->va_list_gpr_size)
6891 type = TREE_TYPE (gpr);
6892 t = build2 (MODIFY_EXPR, type,
6893 gpr, build_int_cst (type, n_gpr * 8));
6894 TREE_SIDE_EFFECTS (t) = 1;
6895 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6898 if (TARGET_SSE && cfun->va_list_fpr_size)
6900 type = TREE_TYPE (fpr);
6901 t = build2 (MODIFY_EXPR, type, fpr,
6902 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6903 TREE_SIDE_EFFECTS (t) = 1;
6904 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6907 /* Find the overflow area. */
6908 type = TREE_TYPE (ovf);
6909 t = make_tree (type, crtl->args.internal_arg_pointer);
6911 t = build2 (POINTER_PLUS_EXPR, type, t,
6912 size_int (words * UNITS_PER_WORD));
6913 t = build2 (MODIFY_EXPR, type, ovf, t);
6914 TREE_SIDE_EFFECTS (t) = 1;
6915 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6917 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6919 /* Find the register save area.
6920 Prologue of the function save it right above stack frame. */
6921 type = TREE_TYPE (sav);
6922 t = make_tree (type, frame_pointer_rtx);
6923 if (!ix86_varargs_gpr_size)
6924 t = build2 (POINTER_PLUS_EXPR, type, t,
6925 size_int (-8 * X86_64_REGPARM_MAX));
6926 t = build2 (MODIFY_EXPR, type, sav, t);
6927 TREE_SIDE_EFFECTS (t) = 1;
6928 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6932 /* Implement va_arg. */
6935 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6938 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6939 tree f_gpr, f_fpr, f_ovf, f_sav;
6940 tree gpr, fpr, ovf, sav, t;
6942 tree lab_false, lab_over = NULL_TREE;
6947 enum machine_mode nat_mode;
6950 /* Only 64bit target needs something special. */
6951 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6952 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6954 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6955 f_fpr = TREE_CHAIN (f_gpr);
6956 f_ovf = TREE_CHAIN (f_fpr);
6957 f_sav = TREE_CHAIN (f_ovf);
6959 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6960 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6961 valist = build_va_arg_indirect_ref (valist);
6962 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6963 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6964 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6966 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6968 type = build_pointer_type (type);
6969 size = int_size_in_bytes (type);
6970 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6972 nat_mode = type_natural_mode (type, NULL);
6981 /* Unnamed 256bit vector mode parameters are passed on stack. */
6982 if (ix86_cfun_abi () == SYSV_ABI)
6989 container = construct_container (nat_mode, TYPE_MODE (type),
6990 type, 0, X86_64_REGPARM_MAX,
6991 X86_64_SSE_REGPARM_MAX, intreg,
6996 /* Pull the value out of the saved registers. */
6998 addr = create_tmp_var (ptr_type_node, "addr");
7002 int needed_intregs, needed_sseregs;
7004 tree int_addr, sse_addr;
7006 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7007 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7009 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
7011 need_temp = (!REG_P (container)
7012 && ((needed_intregs && TYPE_ALIGN (type) > 64)
7013 || TYPE_ALIGN (type) > 128));
7015 /* In case we are passing structure, verify that it is consecutive block
7016 on the register save area. If not we need to do moves. */
7017 if (!need_temp && !REG_P (container))
7019 /* Verify that all registers are strictly consecutive */
7020 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
7024 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7026 rtx slot = XVECEXP (container, 0, i);
7027 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
7028 || INTVAL (XEXP (slot, 1)) != i * 16)
7036 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7038 rtx slot = XVECEXP (container, 0, i);
7039 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
7040 || INTVAL (XEXP (slot, 1)) != i * 8)
7052 int_addr = create_tmp_var (ptr_type_node, "int_addr");
7053 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
7056 /* First ensure that we fit completely in registers. */
7059 t = build_int_cst (TREE_TYPE (gpr),
7060 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
7061 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
7062 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7063 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7064 gimplify_and_add (t, pre_p);
7068 t = build_int_cst (TREE_TYPE (fpr),
7069 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
7070 + X86_64_REGPARM_MAX * 8);
7071 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
7072 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7073 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7074 gimplify_and_add (t, pre_p);
7077 /* Compute index to start of area used for integer regs. */
7080 /* int_addr = gpr + sav; */
7081 t = fold_convert (sizetype, gpr);
7082 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7083 gimplify_assign (int_addr, t, pre_p);
7087 /* sse_addr = fpr + sav; */
7088 t = fold_convert (sizetype, fpr);
7089 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7090 gimplify_assign (sse_addr, t, pre_p);
7095 tree temp = create_tmp_var (type, "va_arg_tmp");
7098 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
7099 gimplify_assign (addr, t, pre_p);
7101 for (i = 0; i < XVECLEN (container, 0); i++)
7103 rtx slot = XVECEXP (container, 0, i);
7104 rtx reg = XEXP (slot, 0);
7105 enum machine_mode mode = GET_MODE (reg);
7106 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
7107 tree addr_type = build_pointer_type (piece_type);
7108 tree daddr_type = build_pointer_type_for_mode (piece_type,
7112 tree dest_addr, dest;
7114 if (SSE_REGNO_P (REGNO (reg)))
7116 src_addr = sse_addr;
7117 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
7121 src_addr = int_addr;
7122 src_offset = REGNO (reg) * 8;
7124 src_addr = fold_convert (addr_type, src_addr);
7125 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
7126 size_int (src_offset));
7127 src = build_va_arg_indirect_ref (src_addr);
7129 dest_addr = fold_convert (daddr_type, addr);
7130 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
7131 size_int (INTVAL (XEXP (slot, 1))));
7132 dest = build_va_arg_indirect_ref (dest_addr);
7134 gimplify_assign (dest, src, pre_p);
7140 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7141 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7142 gimplify_assign (gpr, t, pre_p);
7147 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7148 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7149 gimplify_assign (fpr, t, pre_p);
7152 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7154 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7157 /* ... otherwise out of the overflow area. */
7159 /* When we align parameter on stack for caller, if the parameter
7160 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7161 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7162 here with caller. */
7163 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7164 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7165 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7167 /* Care for on-stack alignment if needed. */
7168 if (arg_boundary <= 64
7169 || integer_zerop (TYPE_SIZE (type)))
7173 HOST_WIDE_INT align = arg_boundary / 8;
7174 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7175 size_int (align - 1));
7176 t = fold_convert (sizetype, t);
7177 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7179 t = fold_convert (TREE_TYPE (ovf), t);
7181 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7182 gimplify_assign (addr, t, pre_p);
7184 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7185 size_int (rsize * UNITS_PER_WORD));
7186 gimplify_assign (unshare_expr (ovf), t, pre_p);
7189 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7191 ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
7192 addr = fold_convert (ptrtype, addr);
7195 addr = build_va_arg_indirect_ref (addr);
7196 return build_va_arg_indirect_ref (addr);
7199 /* Return nonzero if OPNUM's MEM should be matched
7200 in movabs* patterns. */
7203 ix86_check_movabs (rtx insn, int opnum)
7207 set = PATTERN (insn);
7208 if (GET_CODE (set) == PARALLEL)
7209 set = XVECEXP (set, 0, 0);
7210 gcc_assert (GET_CODE (set) == SET);
7211 mem = XEXP (set, opnum);
7212 while (GET_CODE (mem) == SUBREG)
7213 mem = SUBREG_REG (mem);
7214 gcc_assert (MEM_P (mem));
7215 return (volatile_ok || !MEM_VOLATILE_P (mem));
7218 /* Initialize the table of extra 80387 mathematical constants. */
7221 init_ext_80387_constants (void)
7223 static const char * cst[5] =
7225 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7226 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7227 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7228 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7229 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7233 for (i = 0; i < 5; i++)
7235 real_from_string (&ext_80387_constants_table[i], cst[i]);
7236 /* Ensure each constant is rounded to XFmode precision. */
7237 real_convert (&ext_80387_constants_table[i],
7238 XFmode, &ext_80387_constants_table[i]);
7241 ext_80387_constants_init = 1;
7244 /* Return true if the constant is something that can be loaded with
7245 a special instruction. */
7248 standard_80387_constant_p (rtx x)
7250 enum machine_mode mode = GET_MODE (x);
7254 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7257 if (x == CONST0_RTX (mode))
7259 if (x == CONST1_RTX (mode))
7262 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7264 /* For XFmode constants, try to find a special 80387 instruction when
7265 optimizing for size or on those CPUs that benefit from them. */
7267 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7271 if (! ext_80387_constants_init)
7272 init_ext_80387_constants ();
7274 for (i = 0; i < 5; i++)
7275 if (real_identical (&r, &ext_80387_constants_table[i]))
7279 /* Load of the constant -0.0 or -1.0 will be split as
7280 fldz;fchs or fld1;fchs sequence. */
7281 if (real_isnegzero (&r))
7283 if (real_identical (&r, &dconstm1))
7289 /* Return the opcode of the special instruction to be used to load
7293 standard_80387_constant_opcode (rtx x)
7295 switch (standard_80387_constant_p (x))
7319 /* Return the CONST_DOUBLE representing the 80387 constant that is
7320 loaded by the specified special instruction. The argument IDX
7321 matches the return value from standard_80387_constant_p. */
7324 standard_80387_constant_rtx (int idx)
7328 if (! ext_80387_constants_init)
7329 init_ext_80387_constants ();
7345 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7349 /* Return 1 if X is all 0s and 2 if x is all 1s
7350 in supported SSE vector mode. */
7353 standard_sse_constant_p (rtx x)
7355 enum machine_mode mode = GET_MODE (x);
7357 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7359 if (vector_all_ones_operand (x, mode))
7375 /* Return the opcode of the special instruction to be used to load
7379 standard_sse_constant_opcode (rtx insn, rtx x)
7381 switch (standard_sse_constant_p (x))
7384 switch (get_attr_mode (insn))
7387 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7389 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7391 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7393 return "vxorps\t%x0, %x0, %x0";
7395 return "vxorpd\t%x0, %x0, %x0";
7397 return "vpxor\t%x0, %x0, %x0";
7402 return TARGET_AVX ? "vpcmpeqd\t%0, %0, %0" : "pcmpeqd\t%0, %0";
7409 /* Returns 1 if OP contains a symbol reference */
7412 symbolic_reference_mentioned_p (rtx op)
7417 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7420 fmt = GET_RTX_FORMAT (GET_CODE (op));
7421 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7427 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7428 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7432 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7439 /* Return 1 if it is appropriate to emit `ret' instructions in the
7440 body of a function. Do this only if the epilogue is simple, needing a
7441 couple of insns. Prior to reloading, we can't tell how many registers
7442 must be saved, so return 0 then. Return 0 if there is no frame
7443 marker to de-allocate. */
7446 ix86_can_use_return_insn_p (void)
7448 struct ix86_frame frame;
7450 if (! reload_completed || frame_pointer_needed)
7453 /* Don't allow more than 32 pop, since that's all we can do
7454 with one instruction. */
7455 if (crtl->args.pops_args
7456 && crtl->args.size >= 32768)
7459 ix86_compute_frame_layout (&frame);
7460 return frame.to_allocate == 0 && frame.padding0 == 0
7461 && (frame.nregs + frame.nsseregs) == 0;
7464 /* Value should be nonzero if functions must have frame pointers.
7465 Zero means the frame pointer need not be set up (and parms may
7466 be accessed via the stack pointer) in functions that seem suitable. */
7469 ix86_frame_pointer_required (void)
7471 /* If we accessed previous frames, then the generated code expects
7472 to be able to access the saved ebp value in our frame. */
7473 if (cfun->machine->accesses_prev_frame)
7476 /* Several x86 os'es need a frame pointer for other reasons,
7477 usually pertaining to setjmp. */
7478 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7481 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7482 the frame pointer by default. Turn it back on now if we've not
7483 got a leaf function. */
7484 if (TARGET_OMIT_LEAF_FRAME_POINTER
7485 && (!current_function_is_leaf
7486 || ix86_current_function_calls_tls_descriptor))
7495 /* Record that the current function accesses previous call frames. */
7498 ix86_setup_frame_addresses (void)
7500 cfun->machine->accesses_prev_frame = 1;
7503 #ifndef USE_HIDDEN_LINKONCE
7504 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7505 # define USE_HIDDEN_LINKONCE 1
7507 # define USE_HIDDEN_LINKONCE 0
7511 static int pic_labels_used;
7513 /* Fills in the label name that should be used for a pc thunk for
7514 the given register. */
7517 get_pc_thunk_name (char name[32], unsigned int regno)
7519 gcc_assert (!TARGET_64BIT);
7521 if (USE_HIDDEN_LINKONCE)
7522 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7524 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7528 /* This function generates code for -fpic that loads %ebx with
7529 the return address of the caller and then returns. */
7532 ix86_file_end (void)
7537 for (regno = 0; regno < 8; ++regno)
7541 if (! ((pic_labels_used >> regno) & 1))
7544 get_pc_thunk_name (name, regno);
7549 switch_to_section (darwin_sections[text_coal_section]);
7550 fputs ("\t.weak_definition\t", asm_out_file);
7551 assemble_name (asm_out_file, name);
7552 fputs ("\n\t.private_extern\t", asm_out_file);
7553 assemble_name (asm_out_file, name);
7554 fputs ("\n", asm_out_file);
7555 ASM_OUTPUT_LABEL (asm_out_file, name);
7559 if (USE_HIDDEN_LINKONCE)
7563 decl = build_decl (BUILTINS_LOCATION,
7564 FUNCTION_DECL, get_identifier (name),
7566 TREE_PUBLIC (decl) = 1;
7567 TREE_STATIC (decl) = 1;
7568 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
7570 (*targetm.asm_out.unique_section) (decl, 0);
7571 switch_to_section (get_named_section (decl, NULL, 0));
7573 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7574 fputs ("\t.hidden\t", asm_out_file);
7575 assemble_name (asm_out_file, name);
7576 putc ('\n', asm_out_file);
7577 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7581 switch_to_section (text_section);
7582 ASM_OUTPUT_LABEL (asm_out_file, name);
7585 xops[0] = gen_rtx_REG (Pmode, regno);
7586 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7587 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7588 output_asm_insn ("ret", xops);
7591 if (NEED_INDICATE_EXEC_STACK)
7592 file_end_indicate_exec_stack ();
7595 /* Emit code for the SET_GOT patterns. */
7598 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7604 if (TARGET_VXWORKS_RTP && flag_pic)
7606 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7607 xops[2] = gen_rtx_MEM (Pmode,
7608 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7609 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7611 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7612 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7613 an unadorned address. */
7614 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7615 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7616 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7620 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7622 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7624 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7627 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7629 output_asm_insn ("call\t%a2", xops);
7632 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7633 is what will be referenced by the Mach-O PIC subsystem. */
7635 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7638 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7639 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7642 output_asm_insn ("pop%z0\t%0", xops);
7647 get_pc_thunk_name (name, REGNO (dest));
7648 pic_labels_used |= 1 << REGNO (dest);
7650 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7651 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7652 output_asm_insn ("call\t%X2", xops);
7653 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7654 is what will be referenced by the Mach-O PIC subsystem. */
7657 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7659 targetm.asm_out.internal_label (asm_out_file, "L",
7660 CODE_LABEL_NUMBER (label));
7667 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7668 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7670 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7675 /* Generate an "push" pattern for input ARG. */
7680 if (ix86_cfa_state->reg == stack_pointer_rtx)
7681 ix86_cfa_state->offset += UNITS_PER_WORD;
7683 return gen_rtx_SET (VOIDmode,
7685 gen_rtx_PRE_DEC (Pmode,
7686 stack_pointer_rtx)),
7690 /* Return >= 0 if there is an unused call-clobbered register available
7691 for the entire function. */
7694 ix86_select_alt_pic_regnum (void)
7696 if (current_function_is_leaf && !crtl->profile
7697 && !ix86_current_function_calls_tls_descriptor)
7700 /* Can't use the same register for both PIC and DRAP. */
7702 drap = REGNO (crtl->drap_reg);
7705 for (i = 2; i >= 0; --i)
7706 if (i != drap && !df_regs_ever_live_p (i))
7710 return INVALID_REGNUM;
7713 /* Return 1 if we need to save REGNO. */
7715 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7717 if (pic_offset_table_rtx
7718 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7719 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7721 || crtl->calls_eh_return
7722 || crtl->uses_const_pool))
7724 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7729 if (crtl->calls_eh_return && maybe_eh_return)
7734 unsigned test = EH_RETURN_DATA_REGNO (i);
7735 if (test == INVALID_REGNUM)
7742 if (crtl->drap_reg && regno == REGNO (crtl->drap_reg))
7745 return (df_regs_ever_live_p (regno)
7746 && !call_used_regs[regno]
7747 && !fixed_regs[regno]
7748 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7751 /* Return number of saved general prupose registers. */
7754 ix86_nsaved_regs (void)
7759 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7760 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7765 /* Return number of saved SSE registrers. */
7768 ix86_nsaved_sseregs (void)
7773 if (ix86_cfun_abi () != MS_ABI)
7775 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7776 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7781 /* Given FROM and TO register numbers, say whether this elimination is
7782 allowed. If stack alignment is needed, we can only replace argument
7783 pointer with hard frame pointer, or replace frame pointer with stack
7784 pointer. Otherwise, frame pointer elimination is automatically
7785 handled and all other eliminations are valid. */
7788 ix86_can_eliminate (const int from, const int to)
7790 if (stack_realign_fp)
7791 return ((from == ARG_POINTER_REGNUM
7792 && to == HARD_FRAME_POINTER_REGNUM)
7793 || (from == FRAME_POINTER_REGNUM
7794 && to == STACK_POINTER_REGNUM));
7796 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : true;
7799 /* Return the offset between two registers, one to be eliminated, and the other
7800 its replacement, at the start of a routine. */
7803 ix86_initial_elimination_offset (int from, int to)
7805 struct ix86_frame frame;
7806 ix86_compute_frame_layout (&frame);
7808 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7809 return frame.hard_frame_pointer_offset;
7810 else if (from == FRAME_POINTER_REGNUM
7811 && to == HARD_FRAME_POINTER_REGNUM)
7812 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7815 gcc_assert (to == STACK_POINTER_REGNUM);
7817 if (from == ARG_POINTER_REGNUM)
7818 return frame.stack_pointer_offset;
7820 gcc_assert (from == FRAME_POINTER_REGNUM);
7821 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7825 /* In a dynamically-aligned function, we can't know the offset from
7826 stack pointer to frame pointer, so we must ensure that setjmp
7827 eliminates fp against the hard fp (%ebp) rather than trying to
7828 index from %esp up to the top of the frame across a gap that is
7829 of unknown (at compile-time) size. */
7831 ix86_builtin_setjmp_frame_value (void)
7833 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7836 /* Fill structure ix86_frame about frame of currently computed function. */
7839 ix86_compute_frame_layout (struct ix86_frame *frame)
7841 unsigned int stack_alignment_needed;
7842 HOST_WIDE_INT offset;
7843 unsigned int preferred_alignment;
7844 HOST_WIDE_INT size = get_frame_size ();
7846 frame->nregs = ix86_nsaved_regs ();
7847 frame->nsseregs = ix86_nsaved_sseregs ();
7849 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7850 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7852 /* MS ABI seem to require stack alignment to be always 16 except for function
7854 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7856 preferred_alignment = 16;
7857 stack_alignment_needed = 16;
7858 crtl->preferred_stack_boundary = 128;
7859 crtl->stack_alignment_needed = 128;
7862 gcc_assert (!size || stack_alignment_needed);
7863 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7864 gcc_assert (preferred_alignment <= stack_alignment_needed);
7866 /* During reload iteration the amount of registers saved can change.
7867 Recompute the value as needed. Do not recompute when amount of registers
7868 didn't change as reload does multiple calls to the function and does not
7869 expect the decision to change within single iteration. */
7870 if (!optimize_function_for_size_p (cfun)
7871 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7873 int count = frame->nregs;
7875 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7876 /* The fast prologue uses move instead of push to save registers. This
7877 is significantly longer, but also executes faster as modern hardware
7878 can execute the moves in parallel, but can't do that for push/pop.
7880 Be careful about choosing what prologue to emit: When function takes
7881 many instructions to execute we may use slow version as well as in
7882 case function is known to be outside hot spot (this is known with
7883 feedback only). Weight the size of function by number of registers
7884 to save as it is cheap to use one or two push instructions but very
7885 slow to use many of them. */
7887 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7888 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7889 || (flag_branch_probabilities
7890 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7891 cfun->machine->use_fast_prologue_epilogue = false;
7893 cfun->machine->use_fast_prologue_epilogue
7894 = !expensive_function_p (count);
7896 if (TARGET_PROLOGUE_USING_MOVE
7897 && cfun->machine->use_fast_prologue_epilogue)
7898 frame->save_regs_using_mov = true;
7900 frame->save_regs_using_mov = false;
7902 /* Skip return address. */
7903 offset = UNITS_PER_WORD;
7905 /* Skip pushed static chain. */
7906 if (ix86_static_chain_on_stack)
7907 offset += UNITS_PER_WORD;
7909 /* Skip saved base pointer. */
7910 if (frame_pointer_needed)
7911 offset += UNITS_PER_WORD;
7913 frame->hard_frame_pointer_offset = offset;
7915 /* Set offset to aligned because the realigned frame starts from
7917 if (stack_realign_fp)
7918 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7920 /* Register save area */
7921 offset += frame->nregs * UNITS_PER_WORD;
7923 /* Align SSE reg save area. */
7924 if (frame->nsseregs)
7925 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7927 frame->padding0 = 0;
7929 /* SSE register save area. */
7930 offset += frame->padding0 + frame->nsseregs * 16;
7933 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7934 offset += frame->va_arg_size;
7936 /* Align start of frame for local function. */
7937 frame->padding1 = ((offset + stack_alignment_needed - 1)
7938 & -stack_alignment_needed) - offset;
7940 offset += frame->padding1;
7942 /* Frame pointer points here. */
7943 frame->frame_pointer_offset = offset;
7947 /* Add outgoing arguments area. Can be skipped if we eliminated
7948 all the function calls as dead code.
7949 Skipping is however impossible when function calls alloca. Alloca
7950 expander assumes that last crtl->outgoing_args_size
7951 of stack frame are unused. */
7952 if (ACCUMULATE_OUTGOING_ARGS
7953 && (!current_function_is_leaf || cfun->calls_alloca
7954 || ix86_current_function_calls_tls_descriptor))
7956 offset += crtl->outgoing_args_size;
7957 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7960 frame->outgoing_arguments_size = 0;
7962 /* Align stack boundary. Only needed if we're calling another function
7964 if (!current_function_is_leaf || cfun->calls_alloca
7965 || ix86_current_function_calls_tls_descriptor)
7966 frame->padding2 = ((offset + preferred_alignment - 1)
7967 & -preferred_alignment) - offset;
7969 frame->padding2 = 0;
7971 offset += frame->padding2;
7973 /* We've reached end of stack frame. */
7974 frame->stack_pointer_offset = offset;
7976 /* Size prologue needs to allocate. */
7977 frame->to_allocate =
7978 (size + frame->padding1 + frame->padding2
7979 + frame->outgoing_arguments_size + frame->va_arg_size);
7981 if ((!frame->to_allocate && frame->nregs <= 1)
7982 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7983 frame->save_regs_using_mov = false;
7985 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
7986 && current_function_sp_is_unchanging
7987 && current_function_is_leaf
7988 && !ix86_current_function_calls_tls_descriptor)
7990 frame->red_zone_size = frame->to_allocate;
7991 if (frame->save_regs_using_mov)
7992 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7993 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7994 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7997 frame->red_zone_size = 0;
7998 frame->to_allocate -= frame->red_zone_size;
7999 frame->stack_pointer_offset -= frame->red_zone_size;
8002 /* Emit code to save registers in the prologue. */
8005 ix86_emit_save_regs (void)
8010 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
8011 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8013 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
8014 RTX_FRAME_RELATED_P (insn) = 1;
8018 /* Emit code to save registers using MOV insns. First register
8019 is restored from POINTER + OFFSET. */
8021 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8026 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8027 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8029 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
8031 gen_rtx_REG (Pmode, regno));
8032 RTX_FRAME_RELATED_P (insn) = 1;
8033 offset += UNITS_PER_WORD;
8037 /* Emit code to save registers using MOV insns. First register
8038 is restored from POINTER + OFFSET. */
8040 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8046 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8047 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8049 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
8050 set_mem_align (mem, 128);
8051 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
8052 RTX_FRAME_RELATED_P (insn) = 1;
8057 static GTY(()) rtx queued_cfa_restores;
8059 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8060 manipulation insn. Don't add it if the previously
8061 saved value will be left untouched within stack red-zone till return,
8062 as unwinders can find the same value in the register and
8066 ix86_add_cfa_restore_note (rtx insn, rtx reg, HOST_WIDE_INT red_offset)
8069 && !TARGET_64BIT_MS_ABI
8070 && red_offset + RED_ZONE_SIZE >= 0
8071 && crtl->args.pops_args < 65536)
8076 add_reg_note (insn, REG_CFA_RESTORE, reg);
8077 RTX_FRAME_RELATED_P (insn) = 1;
8081 = alloc_reg_note (REG_CFA_RESTORE, reg, queued_cfa_restores);
8084 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8087 ix86_add_queued_cfa_restore_notes (rtx insn)
8090 if (!queued_cfa_restores)
8092 for (last = queued_cfa_restores; XEXP (last, 1); last = XEXP (last, 1))
8094 XEXP (last, 1) = REG_NOTES (insn);
8095 REG_NOTES (insn) = queued_cfa_restores;
8096 queued_cfa_restores = NULL_RTX;
8097 RTX_FRAME_RELATED_P (insn) = 1;
8100 /* Expand prologue or epilogue stack adjustment.
8101 The pattern exist to put a dependency on all ebp-based memory accesses.
8102 STYLE should be negative if instructions should be marked as frame related,
8103 zero if %r11 register is live and cannot be freely used and positive
8107 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
8108 int style, bool set_cfa)
8113 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
8114 else if (x86_64_immediate_operand (offset, DImode))
8115 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
8119 /* r11 is used by indirect sibcall return as well, set before the
8120 epilogue and used after the epilogue. ATM indirect sibcall
8121 shouldn't be used together with huge frame sizes in one
8122 function because of the frame_size check in sibcall.c. */
8124 r11 = gen_rtx_REG (DImode, R11_REG);
8125 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
8127 RTX_FRAME_RELATED_P (insn) = 1;
8128 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
8133 ix86_add_queued_cfa_restore_notes (insn);
8139 gcc_assert (ix86_cfa_state->reg == src);
8140 ix86_cfa_state->offset += INTVAL (offset);
8141 ix86_cfa_state->reg = dest;
8143 r = gen_rtx_PLUS (Pmode, src, offset);
8144 r = gen_rtx_SET (VOIDmode, dest, r);
8145 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
8146 RTX_FRAME_RELATED_P (insn) = 1;
8149 RTX_FRAME_RELATED_P (insn) = 1;
8152 /* Find an available register to be used as dynamic realign argument
8153 pointer regsiter. Such a register will be written in prologue and
8154 used in begin of body, so it must not be
8155 1. parameter passing register.
8157 We reuse static-chain register if it is available. Otherwise, we
8158 use DI for i386 and R13 for x86-64. We chose R13 since it has
8161 Return: the regno of chosen register. */
8164 find_drap_reg (void)
8166 tree decl = cfun->decl;
8170 /* Use R13 for nested function or function need static chain.
8171 Since function with tail call may use any caller-saved
8172 registers in epilogue, DRAP must not use caller-saved
8173 register in such case. */
8174 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
8181 /* Use DI for nested function or function need static chain.
8182 Since function with tail call may use any caller-saved
8183 registers in epilogue, DRAP must not use caller-saved
8184 register in such case. */
8185 if (DECL_STATIC_CHAIN (decl) || crtl->tail_call_emit)
8188 /* Reuse static chain register if it isn't used for parameter
8190 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8191 && !lookup_attribute ("fastcall",
8192 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8199 /* Update incoming stack boundary and estimated stack alignment. */
8202 ix86_update_stack_boundary (void)
8204 /* Prefer the one specified at command line. */
8205 ix86_incoming_stack_boundary
8206 = (ix86_user_incoming_stack_boundary
8207 ? ix86_user_incoming_stack_boundary
8208 : ix86_default_incoming_stack_boundary);
8210 /* Incoming stack alignment can be changed on individual functions
8211 via force_align_arg_pointer attribute. We use the smallest
8212 incoming stack boundary. */
8213 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
8214 && lookup_attribute (ix86_force_align_arg_pointer_string,
8215 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8216 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
8218 /* The incoming stack frame has to be aligned at least at
8219 parm_stack_boundary. */
8220 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
8221 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
8223 /* Stack at entrance of main is aligned by runtime. We use the
8224 smallest incoming stack boundary. */
8225 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
8226 && DECL_NAME (current_function_decl)
8227 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8228 && DECL_FILE_SCOPE_P (current_function_decl))
8229 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8231 /* x86_64 vararg needs 16byte stack alignment for register save
8235 && crtl->stack_alignment_estimated < 128)
8236 crtl->stack_alignment_estimated = 128;
8239 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8240 needed or an rtx for DRAP otherwise. */
8243 ix86_get_drap_rtx (void)
8245 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8246 crtl->need_drap = true;
8248 if (stack_realign_drap)
8250 /* Assign DRAP to vDRAP and returns vDRAP */
8251 unsigned int regno = find_drap_reg ();
8256 arg_ptr = gen_rtx_REG (Pmode, regno);
8257 crtl->drap_reg = arg_ptr;
8260 drap_vreg = copy_to_reg (arg_ptr);
8264 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8265 RTX_FRAME_RELATED_P (insn) = 1;
8272 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8275 ix86_internal_arg_pointer (void)
8277 return virtual_incoming_args_rtx;
8280 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8281 to be generated in correct form. */
8283 ix86_finalize_stack_realign_flags (void)
8285 /* Check if stack realign is really needed after reload, and
8286 stores result in cfun */
8287 unsigned int incoming_stack_boundary
8288 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8289 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8290 unsigned int stack_realign = (incoming_stack_boundary
8291 < (current_function_is_leaf
8292 ? crtl->max_used_stack_slot_alignment
8293 : crtl->stack_alignment_needed));
8295 if (crtl->stack_realign_finalized)
8297 /* After stack_realign_needed is finalized, we can't no longer
8299 gcc_assert (crtl->stack_realign_needed == stack_realign);
8303 crtl->stack_realign_needed = stack_realign;
8304 crtl->stack_realign_finalized = true;
8308 /* Expand the prologue into a bunch of separate insns. */
8311 ix86_expand_prologue (void)
8315 struct ix86_frame frame;
8316 HOST_WIDE_INT allocate;
8317 int gen_frame_pointer = frame_pointer_needed;
8319 ix86_finalize_stack_realign_flags ();
8321 /* DRAP should not coexist with stack_realign_fp */
8322 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8324 /* Initialize CFA state for before the prologue. */
8325 ix86_cfa_state->reg = stack_pointer_rtx;
8326 ix86_cfa_state->offset = INCOMING_FRAME_SP_OFFSET;
8328 ix86_compute_frame_layout (&frame);
8330 if (ix86_function_ms_hook_prologue (current_function_decl))
8334 /* Make sure the function starts with
8335 8b ff movl.s %edi,%edi
8337 8b ec movl.s %esp,%ebp
8339 This matches the hookable function prologue in Win32 API
8340 functions in Microsoft Windows XP Service Pack 2 and newer.
8341 Wine uses this to enable Windows apps to hook the Win32 API
8342 functions provided by Wine. */
8343 insn = emit_insn (gen_vswapmov (gen_rtx_REG (SImode, DI_REG),
8344 gen_rtx_REG (SImode, DI_REG)));
8345 push = emit_insn (gen_push (hard_frame_pointer_rtx));
8346 mov = emit_insn (gen_vswapmov (hard_frame_pointer_rtx,
8347 stack_pointer_rtx));
8349 if (frame_pointer_needed && !(crtl->drap_reg
8350 && crtl->stack_realign_needed))
8352 /* The push %ebp and movl.s %esp, %ebp already set up
8353 the frame pointer. No need to do this again. */
8354 gen_frame_pointer = 0;
8355 RTX_FRAME_RELATED_P (push) = 1;
8356 RTX_FRAME_RELATED_P (mov) = 1;
8357 if (ix86_cfa_state->reg == stack_pointer_rtx)
8358 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8361 /* If the frame pointer is not needed, pop %ebp again. This
8362 could be optimized for cases where ebp needs to be backed up
8363 for some other reason. If stack realignment is needed, pop
8364 the base pointer again, align the stack, and later regenerate
8365 the frame pointer setup. The frame pointer generated by the
8366 hook prologue is not aligned, so it can't be used. */
8367 insn = emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8370 /* The first insn of a function that accepts its static chain on the
8371 stack is to push the register that would be filled in by a direct
8372 call. This insn will be skipped by the trampoline. */
8373 if (ix86_static_chain_on_stack)
8377 insn = emit_insn (gen_push (ix86_static_chain (cfun->decl, false)));
8378 emit_insn (gen_blockage ());
8380 /* We don't want to interpret this push insn as a register save,
8381 only as a stack adjustment. The real copy of the register as
8382 a save will be done later, if needed. */
8383 t = plus_constant (stack_pointer_rtx, -UNITS_PER_WORD);
8384 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8385 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8386 RTX_FRAME_RELATED_P (insn) = 1;
8389 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8390 of DRAP is needed and stack realignment is really needed after reload */
8391 if (crtl->drap_reg && crtl->stack_realign_needed)
8394 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8395 int param_ptr_offset = UNITS_PER_WORD;
8397 if (ix86_static_chain_on_stack)
8398 param_ptr_offset += UNITS_PER_WORD;
8399 if (!call_used_regs[REGNO (crtl->drap_reg)])
8400 param_ptr_offset += UNITS_PER_WORD;
8402 gcc_assert (stack_realign_drap);
8404 /* Grab the argument pointer. */
8405 x = plus_constant (stack_pointer_rtx, param_ptr_offset);
8408 /* Only need to push parameter pointer reg if it is caller
8410 if (!call_used_regs[REGNO (crtl->drap_reg)])
8412 /* Push arg pointer reg */
8413 insn = emit_insn (gen_push (y));
8414 RTX_FRAME_RELATED_P (insn) = 1;
8417 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8418 RTX_FRAME_RELATED_P (insn) = 1;
8419 ix86_cfa_state->reg = crtl->drap_reg;
8421 /* Align the stack. */
8422 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8424 GEN_INT (-align_bytes)));
8425 RTX_FRAME_RELATED_P (insn) = 1;
8427 /* Replicate the return address on the stack so that return
8428 address can be reached via (argp - 1) slot. This is needed
8429 to implement macro RETURN_ADDR_RTX and intrinsic function
8430 expand_builtin_return_addr etc. */
8432 x = gen_frame_mem (Pmode,
8433 plus_constant (x, -UNITS_PER_WORD));
8434 insn = emit_insn (gen_push (x));
8435 RTX_FRAME_RELATED_P (insn) = 1;
8438 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8439 slower on all targets. Also sdb doesn't like it. */
8441 if (gen_frame_pointer)
8443 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8444 RTX_FRAME_RELATED_P (insn) = 1;
8446 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8447 RTX_FRAME_RELATED_P (insn) = 1;
8449 if (ix86_cfa_state->reg == stack_pointer_rtx)
8450 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8453 if (stack_realign_fp)
8455 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8456 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8458 /* Align the stack. */
8459 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8461 GEN_INT (-align_bytes)));
8462 RTX_FRAME_RELATED_P (insn) = 1;
8465 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8467 if (!frame.save_regs_using_mov)
8468 ix86_emit_save_regs ();
8470 allocate += frame.nregs * UNITS_PER_WORD;
8472 /* When using red zone we may start register saving before allocating
8473 the stack frame saving one cycle of the prologue. However I will
8474 avoid doing this if I am going to have to probe the stack since
8475 at least on x86_64 the stack probe can turn into a call that clobbers
8476 a red zone location */
8477 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8478 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8479 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8480 && !crtl->stack_realign_needed)
8481 ? hard_frame_pointer_rtx
8482 : stack_pointer_rtx,
8483 -frame.nregs * UNITS_PER_WORD);
8487 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8488 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8489 GEN_INT (-allocate), -1,
8490 ix86_cfa_state->reg == stack_pointer_rtx);
8493 /* Only valid for Win32. */
8494 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8498 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8500 if (cfun->machine->call_abi == MS_ABI)
8503 eax_live = ix86_eax_live_at_start_p ();
8507 emit_insn (gen_push (eax));
8508 allocate -= UNITS_PER_WORD;
8511 emit_move_insn (eax, GEN_INT (allocate));
8514 insn = gen_allocate_stack_worker_64 (eax, eax);
8516 insn = gen_allocate_stack_worker_32 (eax, eax);
8517 insn = emit_insn (insn);
8519 if (ix86_cfa_state->reg == stack_pointer_rtx)
8521 ix86_cfa_state->offset += allocate;
8522 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8523 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8524 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8525 RTX_FRAME_RELATED_P (insn) = 1;
8530 if (frame_pointer_needed)
8531 t = plus_constant (hard_frame_pointer_rtx,
8534 - frame.nregs * UNITS_PER_WORD);
8536 t = plus_constant (stack_pointer_rtx, allocate);
8537 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8541 if (frame.save_regs_using_mov
8542 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8543 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8545 if (!frame_pointer_needed
8546 || !(frame.to_allocate + frame.padding0)
8547 || crtl->stack_realign_needed)
8548 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8550 + frame.nsseregs * 16 + frame.padding0);
8552 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8553 -frame.nregs * UNITS_PER_WORD);
8555 if (!frame_pointer_needed
8556 || !(frame.to_allocate + frame.padding0)
8557 || crtl->stack_realign_needed)
8558 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8561 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8562 - frame.nregs * UNITS_PER_WORD
8563 - frame.nsseregs * 16
8566 pic_reg_used = false;
8567 if (pic_offset_table_rtx
8568 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8571 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8573 if (alt_pic_reg_used != INVALID_REGNUM)
8574 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8576 pic_reg_used = true;
8583 if (ix86_cmodel == CM_LARGE_PIC)
8585 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8586 rtx label = gen_label_rtx ();
8588 LABEL_PRESERVE_P (label) = 1;
8589 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8590 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8591 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8592 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8593 pic_offset_table_rtx, tmp_reg));
8596 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8599 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8602 /* In the pic_reg_used case, make sure that the got load isn't deleted
8603 when mcount needs it. Blockage to avoid call movement across mcount
8604 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8606 if (crtl->profile && pic_reg_used)
8607 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8609 if (crtl->drap_reg && !crtl->stack_realign_needed)
8611 /* vDRAP is setup but after reload it turns out stack realign
8612 isn't necessary, here we will emit prologue to setup DRAP
8613 without stack realign adjustment */
8615 int drap_bp_offset = UNITS_PER_WORD * 2;
8617 if (ix86_static_chain_on_stack)
8618 drap_bp_offset += UNITS_PER_WORD;
8619 x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8620 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8623 /* Prevent instructions from being scheduled into register save push
8624 sequence when access to the redzone area is done through frame pointer.
8625 The offset between the frame pointer and the stack pointer is calculated
8626 relative to the value of the stack pointer at the end of the function
8627 prologue, and moving instructions that access redzone area via frame
8628 pointer inside push sequence violates this assumption. */
8629 if (frame_pointer_needed && frame.red_zone_size)
8630 emit_insn (gen_memory_blockage ());
8632 /* Emit cld instruction if stringops are used in the function. */
8633 if (TARGET_CLD && ix86_current_function_needs_cld)
8634 emit_insn (gen_cld ());
8637 /* Emit code to restore REG using a POP insn. */
8640 ix86_emit_restore_reg_using_pop (rtx reg, HOST_WIDE_INT red_offset)
8642 rtx insn = emit_insn (ix86_gen_pop1 (reg));
8644 if (ix86_cfa_state->reg == crtl->drap_reg
8645 && REGNO (reg) == REGNO (crtl->drap_reg))
8647 /* Previously we'd represented the CFA as an expression
8648 like *(%ebp - 8). We've just popped that value from
8649 the stack, which means we need to reset the CFA to
8650 the drap register. This will remain until we restore
8651 the stack pointer. */
8652 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8653 RTX_FRAME_RELATED_P (insn) = 1;
8657 if (ix86_cfa_state->reg == stack_pointer_rtx)
8659 ix86_cfa_state->offset -= UNITS_PER_WORD;
8660 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8661 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
8662 RTX_FRAME_RELATED_P (insn) = 1;
8665 /* When the frame pointer is the CFA, and we pop it, we are
8666 swapping back to the stack pointer as the CFA. This happens
8667 for stack frames that don't allocate other data, so we assume
8668 the stack pointer is now pointing at the return address, i.e.
8669 the function entry state, which makes the offset be 1 word. */
8670 else if (ix86_cfa_state->reg == hard_frame_pointer_rtx
8671 && reg == hard_frame_pointer_rtx)
8673 ix86_cfa_state->reg = stack_pointer_rtx;
8674 ix86_cfa_state->offset -= UNITS_PER_WORD;
8676 add_reg_note (insn, REG_CFA_DEF_CFA,
8677 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8678 GEN_INT (ix86_cfa_state->offset)));
8679 RTX_FRAME_RELATED_P (insn) = 1;
8682 ix86_add_cfa_restore_note (insn, reg, red_offset);
8685 /* Emit code to restore saved registers using POP insns. */
8688 ix86_emit_restore_regs_using_pop (HOST_WIDE_INT red_offset)
8692 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8693 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8695 ix86_emit_restore_reg_using_pop (gen_rtx_REG (Pmode, regno),
8697 red_offset += UNITS_PER_WORD;
8701 /* Emit code and notes for the LEAVE instruction. */
8704 ix86_emit_leave (HOST_WIDE_INT red_offset)
8706 rtx insn = emit_insn (ix86_gen_leave ());
8708 ix86_add_queued_cfa_restore_notes (insn);
8710 if (ix86_cfa_state->reg == hard_frame_pointer_rtx)
8712 ix86_cfa_state->reg = stack_pointer_rtx;
8713 ix86_cfa_state->offset -= UNITS_PER_WORD;
8715 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8716 copy_rtx (XVECEXP (PATTERN (insn), 0, 0)));
8717 RTX_FRAME_RELATED_P (insn) = 1;
8718 ix86_add_cfa_restore_note (insn, hard_frame_pointer_rtx, red_offset);
8722 /* Emit code to restore saved registers using MOV insns. First register
8723 is restored from POINTER + OFFSET. */
8725 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8726 HOST_WIDE_INT red_offset,
8727 int maybe_eh_return)
8730 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8733 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8734 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8736 rtx reg = gen_rtx_REG (Pmode, regno);
8738 /* Ensure that adjust_address won't be forced to produce pointer
8739 out of range allowed by x86-64 instruction set. */
8740 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8744 r11 = gen_rtx_REG (DImode, R11_REG);
8745 emit_move_insn (r11, GEN_INT (offset));
8746 emit_insn (gen_adddi3 (r11, r11, pointer));
8747 base_address = gen_rtx_MEM (Pmode, r11);
8750 insn = emit_move_insn (reg,
8751 adjust_address (base_address, Pmode, offset));
8752 offset += UNITS_PER_WORD;
8754 if (ix86_cfa_state->reg == crtl->drap_reg
8755 && regno == REGNO (crtl->drap_reg))
8757 /* Previously we'd represented the CFA as an expression
8758 like *(%ebp - 8). We've just popped that value from
8759 the stack, which means we need to reset the CFA to
8760 the drap register. This will remain until we restore
8761 the stack pointer. */
8762 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8763 RTX_FRAME_RELATED_P (insn) = 1;
8766 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8768 red_offset += UNITS_PER_WORD;
8772 /* Emit code to restore saved registers using MOV insns. First register
8773 is restored from POINTER + OFFSET. */
8775 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8776 HOST_WIDE_INT red_offset,
8777 int maybe_eh_return)
8780 rtx base_address = gen_rtx_MEM (TImode, pointer);
8783 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8784 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8786 rtx reg = gen_rtx_REG (TImode, regno);
8788 /* Ensure that adjust_address won't be forced to produce pointer
8789 out of range allowed by x86-64 instruction set. */
8790 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8794 r11 = gen_rtx_REG (DImode, R11_REG);
8795 emit_move_insn (r11, GEN_INT (offset));
8796 emit_insn (gen_adddi3 (r11, r11, pointer));
8797 base_address = gen_rtx_MEM (TImode, r11);
8800 mem = adjust_address (base_address, TImode, offset);
8801 set_mem_align (mem, 128);
8802 insn = emit_move_insn (reg, mem);
8805 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8811 /* Restore function stack, frame, and registers. */
8814 ix86_expand_epilogue (int style)
8817 struct ix86_frame frame;
8818 HOST_WIDE_INT offset, red_offset;
8819 struct machine_cfa_state cfa_state_save = *ix86_cfa_state;
8822 ix86_finalize_stack_realign_flags ();
8824 /* When stack is realigned, SP must be valid. */
8825 sp_valid = (!frame_pointer_needed
8826 || current_function_sp_is_unchanging
8827 || stack_realign_fp);
8829 ix86_compute_frame_layout (&frame);
8831 /* See the comment about red zone and frame
8832 pointer usage in ix86_expand_prologue. */
8833 if (frame_pointer_needed && frame.red_zone_size)
8834 emit_insn (gen_memory_blockage ());
8836 using_drap = crtl->drap_reg && crtl->stack_realign_needed;
8837 gcc_assert (!using_drap || ix86_cfa_state->reg == crtl->drap_reg);
8839 /* Calculate start of saved registers relative to ebp. Special care
8840 must be taken for the normal return case of a function using
8841 eh_return: the eax and edx registers are marked as saved, but not
8842 restored along this path. */
8843 offset = frame.nregs;
8844 if (crtl->calls_eh_return && style != 2)
8846 offset *= -UNITS_PER_WORD;
8847 offset -= frame.nsseregs * 16 + frame.padding0;
8849 /* Calculate start of saved registers relative to esp on entry of the
8850 function. When realigning stack, this needs to be the most negative
8851 value possible at runtime. */
8852 red_offset = offset;
8854 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8856 else if (stack_realign_fp)
8857 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8859 if (ix86_static_chain_on_stack)
8860 red_offset -= UNITS_PER_WORD;
8861 if (frame_pointer_needed)
8862 red_offset -= UNITS_PER_WORD;
8864 /* If we're only restoring one register and sp is not valid then
8865 using a move instruction to restore the register since it's
8866 less work than reloading sp and popping the register.
8868 The default code result in stack adjustment using add/lea instruction,
8869 while this code results in LEAVE instruction (or discrete equivalent),
8870 so it is profitable in some other cases as well. Especially when there
8871 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8872 and there is exactly one register to pop. This heuristic may need some
8873 tuning in future. */
8874 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8875 || (TARGET_EPILOGUE_USING_MOVE
8876 && cfun->machine->use_fast_prologue_epilogue
8877 && ((frame.nregs + frame.nsseregs) > 1
8878 || (frame.to_allocate + frame.padding0) != 0))
8879 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8880 && (frame.to_allocate + frame.padding0) != 0)
8881 || (frame_pointer_needed && TARGET_USE_LEAVE
8882 && cfun->machine->use_fast_prologue_epilogue
8883 && (frame.nregs + frame.nsseregs) == 1)
8884 || crtl->calls_eh_return)
8886 /* Restore registers. We can use ebp or esp to address the memory
8887 locations. If both are available, default to ebp, since offsets
8888 are known to be small. Only exception is esp pointing directly
8889 to the end of block of saved registers, where we may simplify
8892 If we are realigning stack with bp and sp, regs restore can't
8893 be addressed by bp. sp must be used instead. */
8895 if (!frame_pointer_needed
8896 || (sp_valid && !(frame.to_allocate + frame.padding0))
8897 || stack_realign_fp)
8899 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8900 frame.to_allocate, red_offset,
8902 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8904 + frame.nsseregs * 16
8907 + frame.nsseregs * 16
8908 + frame.padding0, style == 2);
8912 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8915 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8917 + frame.nsseregs * 16
8920 + frame.nsseregs * 16
8921 + frame.padding0, style == 2);
8924 red_offset -= offset;
8926 /* eh_return epilogues need %ecx added to the stack pointer. */
8929 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8931 /* Stack align doesn't work with eh_return. */
8932 gcc_assert (!crtl->stack_realign_needed);
8933 /* Neither does regparm nested functions. */
8934 gcc_assert (!ix86_static_chain_on_stack);
8936 if (frame_pointer_needed)
8938 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8939 tmp = plus_constant (tmp, UNITS_PER_WORD);
8940 tmp = emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8942 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8943 tmp = emit_move_insn (hard_frame_pointer_rtx, tmp);
8945 /* Note that we use SA as a temporary CFA, as the return
8946 address is at the proper place relative to it. We
8947 pretend this happens at the FP restore insn because
8948 prior to this insn the FP would be stored at the wrong
8949 offset relative to SA, and after this insn we have no
8950 other reasonable register to use for the CFA. We don't
8951 bother resetting the CFA to the SP for the duration of
8953 add_reg_note (tmp, REG_CFA_DEF_CFA,
8954 plus_constant (sa, UNITS_PER_WORD));
8955 ix86_add_queued_cfa_restore_notes (tmp);
8956 add_reg_note (tmp, REG_CFA_RESTORE, hard_frame_pointer_rtx);
8957 RTX_FRAME_RELATED_P (tmp) = 1;
8958 ix86_cfa_state->reg = sa;
8959 ix86_cfa_state->offset = UNITS_PER_WORD;
8961 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8962 const0_rtx, style, false);
8966 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8967 tmp = plus_constant (tmp, (frame.to_allocate
8968 + frame.nregs * UNITS_PER_WORD
8969 + frame.nsseregs * 16
8971 tmp = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8972 ix86_add_queued_cfa_restore_notes (tmp);
8974 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
8975 if (ix86_cfa_state->offset != UNITS_PER_WORD)
8977 ix86_cfa_state->offset = UNITS_PER_WORD;
8978 add_reg_note (tmp, REG_CFA_DEF_CFA,
8979 plus_constant (stack_pointer_rtx,
8981 RTX_FRAME_RELATED_P (tmp) = 1;
8985 else if (!frame_pointer_needed)
8986 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8987 GEN_INT (frame.to_allocate
8988 + frame.nregs * UNITS_PER_WORD
8989 + frame.nsseregs * 16
8991 style, !using_drap);
8992 /* If not an i386, mov & pop is faster than "leave". */
8993 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8994 || !cfun->machine->use_fast_prologue_epilogue)
8995 ix86_emit_leave (red_offset);
8998 pro_epilogue_adjust_stack (stack_pointer_rtx,
8999 hard_frame_pointer_rtx,
9000 const0_rtx, style, !using_drap);
9002 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx, red_offset);
9007 /* First step is to deallocate the stack frame so that we can
9010 If we realign stack with frame pointer, then stack pointer
9011 won't be able to recover via lea $offset(%bp), %sp, because
9012 there is a padding area between bp and sp for realign.
9013 "add $to_allocate, %sp" must be used instead. */
9016 gcc_assert (frame_pointer_needed);
9017 gcc_assert (!stack_realign_fp);
9018 pro_epilogue_adjust_stack (stack_pointer_rtx,
9019 hard_frame_pointer_rtx,
9020 GEN_INT (offset), style, false);
9021 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
9024 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9025 GEN_INT (frame.nsseregs * 16
9029 else if (frame.to_allocate || frame.padding0 || frame.nsseregs)
9031 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
9032 frame.to_allocate, red_offset,
9034 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9035 GEN_INT (frame.to_allocate
9036 + frame.nsseregs * 16
9037 + frame.padding0), style,
9038 !using_drap && !frame_pointer_needed);
9041 ix86_emit_restore_regs_using_pop (red_offset + frame.nsseregs * 16
9043 red_offset -= offset;
9045 if (frame_pointer_needed)
9047 /* Leave results in shorter dependency chains on CPUs that are
9048 able to grok it fast. */
9049 if (TARGET_USE_LEAVE)
9050 ix86_emit_leave (red_offset);
9053 /* For stack realigned really happens, recover stack
9054 pointer to hard frame pointer is a must, if not using
9056 if (stack_realign_fp)
9057 pro_epilogue_adjust_stack (stack_pointer_rtx,
9058 hard_frame_pointer_rtx,
9059 const0_rtx, style, !using_drap);
9060 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx,
9068 int param_ptr_offset = UNITS_PER_WORD;
9071 gcc_assert (stack_realign_drap);
9073 if (ix86_static_chain_on_stack)
9074 param_ptr_offset += UNITS_PER_WORD;
9075 if (!call_used_regs[REGNO (crtl->drap_reg)])
9076 param_ptr_offset += UNITS_PER_WORD;
9078 insn = emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
9080 GEN_INT (-param_ptr_offset)));
9082 ix86_cfa_state->reg = stack_pointer_rtx;
9083 ix86_cfa_state->offset = param_ptr_offset;
9085 add_reg_note (insn, REG_CFA_DEF_CFA,
9086 gen_rtx_PLUS (Pmode, ix86_cfa_state->reg,
9087 GEN_INT (ix86_cfa_state->offset)));
9088 RTX_FRAME_RELATED_P (insn) = 1;
9090 if (!call_used_regs[REGNO (crtl->drap_reg)])
9091 ix86_emit_restore_reg_using_pop (crtl->drap_reg, -UNITS_PER_WORD);
9094 /* Remove the saved static chain from the stack. The use of ECX is
9095 merely as a scratch register, not as the actual static chain. */
9096 if (ix86_static_chain_on_stack)
9100 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
9101 ix86_cfa_state->offset += UNITS_PER_WORD;
9103 r = gen_rtx_REG (Pmode, CX_REG);
9104 insn = emit_insn (ix86_gen_pop1 (r));
9106 r = plus_constant (stack_pointer_rtx, UNITS_PER_WORD);
9107 r = gen_rtx_SET (VOIDmode, stack_pointer_rtx, r);
9108 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
9109 RTX_FRAME_RELATED_P (insn) = 1;
9112 /* Sibcall epilogues don't want a return instruction. */
9115 *ix86_cfa_state = cfa_state_save;
9119 if (crtl->args.pops_args && crtl->args.size)
9121 rtx popc = GEN_INT (crtl->args.pops_args);
9123 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9124 address, do explicit add, and jump indirectly to the caller. */
9126 if (crtl->args.pops_args >= 65536)
9128 rtx ecx = gen_rtx_REG (SImode, CX_REG);
9131 /* There is no "pascal" calling convention in any 64bit ABI. */
9132 gcc_assert (!TARGET_64BIT);
9134 insn = emit_insn (gen_popsi1 (ecx));
9135 ix86_cfa_state->offset -= UNITS_PER_WORD;
9137 add_reg_note (insn, REG_CFA_ADJUST_CFA,
9138 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
9139 add_reg_note (insn, REG_CFA_REGISTER,
9140 gen_rtx_SET (VOIDmode, ecx, pc_rtx));
9141 RTX_FRAME_RELATED_P (insn) = 1;
9143 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9145 emit_jump_insn (gen_return_indirect_internal (ecx));
9148 emit_jump_insn (gen_return_pop_internal (popc));
9151 emit_jump_insn (gen_return_internal ());
9153 /* Restore the state back to the state from the prologue,
9154 so that it's correct for the next epilogue. */
9155 *ix86_cfa_state = cfa_state_save;
9158 /* Reset from the function's potential modifications. */
9161 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9162 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9164 if (pic_offset_table_rtx)
9165 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
9167 /* Mach-O doesn't support labels at the end of objects, so if
9168 it looks like we might want one, insert a NOP. */
9170 rtx insn = get_last_insn ();
9173 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
9174 insn = PREV_INSN (insn);
9178 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
9179 fputs ("\tnop\n", file);
9185 /* Extract the parts of an RTL expression that is a valid memory address
9186 for an instruction. Return 0 if the structure of the address is
9187 grossly off. Return -1 if the address contains ASHIFT, so it is not
9188 strictly valid, but still used for computing length of lea instruction. */
9191 ix86_decompose_address (rtx addr, struct ix86_address *out)
9193 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
9194 rtx base_reg, index_reg;
9195 HOST_WIDE_INT scale = 1;
9196 rtx scale_rtx = NULL_RTX;
9198 enum ix86_address_seg seg = SEG_DEFAULT;
9200 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
9202 else if (GET_CODE (addr) == PLUS)
9212 addends[n++] = XEXP (op, 1);
9215 while (GET_CODE (op) == PLUS);
9220 for (i = n; i >= 0; --i)
9223 switch (GET_CODE (op))
9228 index = XEXP (op, 0);
9229 scale_rtx = XEXP (op, 1);
9233 if (XINT (op, 1) == UNSPEC_TP
9234 && TARGET_TLS_DIRECT_SEG_REFS
9235 && seg == SEG_DEFAULT)
9236 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
9265 else if (GET_CODE (addr) == MULT)
9267 index = XEXP (addr, 0); /* index*scale */
9268 scale_rtx = XEXP (addr, 1);
9270 else if (GET_CODE (addr) == ASHIFT)
9274 /* We're called for lea too, which implements ashift on occasion. */
9275 index = XEXP (addr, 0);
9276 tmp = XEXP (addr, 1);
9277 if (!CONST_INT_P (tmp))
9279 scale = INTVAL (tmp);
9280 if ((unsigned HOST_WIDE_INT) scale > 3)
9286 disp = addr; /* displacement */
9288 /* Extract the integral value of scale. */
9291 if (!CONST_INT_P (scale_rtx))
9293 scale = INTVAL (scale_rtx);
9296 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
9297 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
9299 /* Avoid useless 0 displacement. */
9300 if (disp == const0_rtx && (base || index))
9303 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9304 if (base_reg && index_reg && scale == 1
9305 && (index_reg == arg_pointer_rtx
9306 || index_reg == frame_pointer_rtx
9307 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
9310 tmp = base, base = index, index = tmp;
9311 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
9314 /* Special case: %ebp cannot be encoded as a base without a displacement.
9318 && (base_reg == hard_frame_pointer_rtx
9319 || base_reg == frame_pointer_rtx
9320 || base_reg == arg_pointer_rtx
9321 || (REG_P (base_reg)
9322 && (REGNO (base_reg) == HARD_FRAME_POINTER_REGNUM
9323 || REGNO (base_reg) == R13_REG))))
9326 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9327 Avoid this by transforming to [%esi+0].
9328 Reload calls address legitimization without cfun defined, so we need
9329 to test cfun for being non-NULL. */
9330 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
9331 && base_reg && !index_reg && !disp
9333 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
9336 /* Special case: encode reg+reg instead of reg*2. */
9337 if (!base && index && scale == 2)
9338 base = index, base_reg = index_reg, scale = 1;
9340 /* Special case: scaling cannot be encoded without base or displacement. */
9341 if (!base && !disp && index && scale != 1)
9353 /* Return cost of the memory address x.
9354 For i386, it is better to use a complex address than let gcc copy
9355 the address into a reg and make a new pseudo. But not if the address
9356 requires to two regs - that would mean more pseudos with longer
9359 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
9361 struct ix86_address parts;
9363 int ok = ix86_decompose_address (x, &parts);
9367 if (parts.base && GET_CODE (parts.base) == SUBREG)
9368 parts.base = SUBREG_REG (parts.base);
9369 if (parts.index && GET_CODE (parts.index) == SUBREG)
9370 parts.index = SUBREG_REG (parts.index);
9372 /* Attempt to minimize number of registers in the address. */
9374 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
9376 && (!REG_P (parts.index)
9377 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
9381 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
9383 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
9384 && parts.base != parts.index)
9387 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9388 since it's predecode logic can't detect the length of instructions
9389 and it degenerates to vector decoded. Increase cost of such
9390 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9391 to split such addresses or even refuse such addresses at all.
9393 Following addressing modes are affected:
9398 The first and last case may be avoidable by explicitly coding the zero in
9399 memory address, but I don't have AMD-K6 machine handy to check this
9403 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
9404 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
9405 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
9411 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9412 this is used for to form addresses to local data when -fPIC is in
9416 darwin_local_data_pic (rtx disp)
9418 return (GET_CODE (disp) == UNSPEC
9419 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
9422 /* Determine if a given RTX is a valid constant. We already know this
9423 satisfies CONSTANT_P. */
9426 legitimate_constant_p (rtx x)
9428 switch (GET_CODE (x))
9433 if (GET_CODE (x) == PLUS)
9435 if (!CONST_INT_P (XEXP (x, 1)))
9440 if (TARGET_MACHO && darwin_local_data_pic (x))
9443 /* Only some unspecs are valid as "constants". */
9444 if (GET_CODE (x) == UNSPEC)
9445 switch (XINT (x, 1))
9450 return TARGET_64BIT;
9453 x = XVECEXP (x, 0, 0);
9454 return (GET_CODE (x) == SYMBOL_REF
9455 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9457 x = XVECEXP (x, 0, 0);
9458 return (GET_CODE (x) == SYMBOL_REF
9459 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9464 /* We must have drilled down to a symbol. */
9465 if (GET_CODE (x) == LABEL_REF)
9467 if (GET_CODE (x) != SYMBOL_REF)
9472 /* TLS symbols are never valid. */
9473 if (SYMBOL_REF_TLS_MODEL (x))
9476 /* DLLIMPORT symbols are never valid. */
9477 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9478 && SYMBOL_REF_DLLIMPORT_P (x))
9483 if (GET_MODE (x) == TImode
9484 && x != CONST0_RTX (TImode)
9490 if (!standard_sse_constant_p (x))
9497 /* Otherwise we handle everything else in the move patterns. */
9501 /* Determine if it's legal to put X into the constant pool. This
9502 is not possible for the address of thread-local symbols, which
9503 is checked above. */
9506 ix86_cannot_force_const_mem (rtx x)
9508 /* We can always put integral constants and vectors in memory. */
9509 switch (GET_CODE (x))
9519 return !legitimate_constant_p (x);
9523 /* Nonzero if the constant value X is a legitimate general operand
9524 when generating PIC code. It is given that flag_pic is on and
9525 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9528 legitimate_pic_operand_p (rtx x)
9532 switch (GET_CODE (x))
9535 inner = XEXP (x, 0);
9536 if (GET_CODE (inner) == PLUS
9537 && CONST_INT_P (XEXP (inner, 1)))
9538 inner = XEXP (inner, 0);
9540 /* Only some unspecs are valid as "constants". */
9541 if (GET_CODE (inner) == UNSPEC)
9542 switch (XINT (inner, 1))
9547 return TARGET_64BIT;
9549 x = XVECEXP (inner, 0, 0);
9550 return (GET_CODE (x) == SYMBOL_REF
9551 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9552 case UNSPEC_MACHOPIC_OFFSET:
9553 return legitimate_pic_address_disp_p (x);
9561 return legitimate_pic_address_disp_p (x);
9568 /* Determine if a given CONST RTX is a valid memory displacement
9572 legitimate_pic_address_disp_p (rtx disp)
9576 /* In 64bit mode we can allow direct addresses of symbols and labels
9577 when they are not dynamic symbols. */
9580 rtx op0 = disp, op1;
9582 switch (GET_CODE (disp))
9588 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9590 op0 = XEXP (XEXP (disp, 0), 0);
9591 op1 = XEXP (XEXP (disp, 0), 1);
9592 if (!CONST_INT_P (op1)
9593 || INTVAL (op1) >= 16*1024*1024
9594 || INTVAL (op1) < -16*1024*1024)
9596 if (GET_CODE (op0) == LABEL_REF)
9598 if (GET_CODE (op0) != SYMBOL_REF)
9603 /* TLS references should always be enclosed in UNSPEC. */
9604 if (SYMBOL_REF_TLS_MODEL (op0))
9606 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9607 && ix86_cmodel != CM_LARGE_PIC)
9615 if (GET_CODE (disp) != CONST)
9617 disp = XEXP (disp, 0);
9621 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9622 of GOT tables. We should not need these anyway. */
9623 if (GET_CODE (disp) != UNSPEC
9624 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9625 && XINT (disp, 1) != UNSPEC_GOTOFF
9626 && XINT (disp, 1) != UNSPEC_PLTOFF))
9629 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9630 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9636 if (GET_CODE (disp) == PLUS)
9638 if (!CONST_INT_P (XEXP (disp, 1)))
9640 disp = XEXP (disp, 0);
9644 if (TARGET_MACHO && darwin_local_data_pic (disp))
9647 if (GET_CODE (disp) != UNSPEC)
9650 switch (XINT (disp, 1))
9655 /* We need to check for both symbols and labels because VxWorks loads
9656 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9658 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9659 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9661 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9662 While ABI specify also 32bit relocation but we don't produce it in
9663 small PIC model at all. */
9664 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9665 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9667 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9669 case UNSPEC_GOTTPOFF:
9670 case UNSPEC_GOTNTPOFF:
9671 case UNSPEC_INDNTPOFF:
9674 disp = XVECEXP (disp, 0, 0);
9675 return (GET_CODE (disp) == SYMBOL_REF
9676 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9678 disp = XVECEXP (disp, 0, 0);
9679 return (GET_CODE (disp) == SYMBOL_REF
9680 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9682 disp = XVECEXP (disp, 0, 0);
9683 return (GET_CODE (disp) == SYMBOL_REF
9684 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9690 /* Recognizes RTL expressions that are valid memory addresses for an
9691 instruction. The MODE argument is the machine mode for the MEM
9692 expression that wants to use this address.
9694 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9695 convert common non-canonical forms to canonical form so that they will
9699 ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9700 rtx addr, bool strict)
9702 struct ix86_address parts;
9703 rtx base, index, disp;
9704 HOST_WIDE_INT scale;
9706 if (ix86_decompose_address (addr, &parts) <= 0)
9707 /* Decomposition failed. */
9711 index = parts.index;
9713 scale = parts.scale;
9715 /* Validate base register.
9717 Don't allow SUBREG's that span more than a word here. It can lead to spill
9718 failures when the base is one word out of a two word structure, which is
9719 represented internally as a DImode int. */
9727 else if (GET_CODE (base) == SUBREG
9728 && REG_P (SUBREG_REG (base))
9729 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9731 reg = SUBREG_REG (base);
9733 /* Base is not a register. */
9736 if (GET_MODE (base) != Pmode)
9737 /* Base is not in Pmode. */
9740 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9741 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9742 /* Base is not valid. */
9746 /* Validate index register.
9748 Don't allow SUBREG's that span more than a word here -- same as above. */
9756 else if (GET_CODE (index) == SUBREG
9757 && REG_P (SUBREG_REG (index))
9758 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9760 reg = SUBREG_REG (index);
9762 /* Index is not a register. */
9765 if (GET_MODE (index) != Pmode)
9766 /* Index is not in Pmode. */
9769 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9770 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9771 /* Index is not valid. */
9775 /* Validate scale factor. */
9779 /* Scale without index. */
9782 if (scale != 2 && scale != 4 && scale != 8)
9783 /* Scale is not a valid multiplier. */
9787 /* Validate displacement. */
9790 if (GET_CODE (disp) == CONST
9791 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9792 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9793 switch (XINT (XEXP (disp, 0), 1))
9795 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9796 used. While ABI specify also 32bit relocations, we don't produce
9797 them at all and use IP relative instead. */
9800 gcc_assert (flag_pic);
9802 goto is_legitimate_pic;
9804 /* 64bit address unspec. */
9807 case UNSPEC_GOTPCREL:
9808 gcc_assert (flag_pic);
9809 goto is_legitimate_pic;
9811 case UNSPEC_GOTTPOFF:
9812 case UNSPEC_GOTNTPOFF:
9813 case UNSPEC_INDNTPOFF:
9819 /* Invalid address unspec. */
9823 else if (SYMBOLIC_CONST (disp)
9827 && MACHOPIC_INDIRECT
9828 && !machopic_operand_p (disp)
9834 if (TARGET_64BIT && (index || base))
9836 /* foo@dtpoff(%rX) is ok. */
9837 if (GET_CODE (disp) != CONST
9838 || GET_CODE (XEXP (disp, 0)) != PLUS
9839 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9840 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9841 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9842 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9843 /* Non-constant pic memory reference. */
9846 else if (! legitimate_pic_address_disp_p (disp))
9847 /* Displacement is an invalid pic construct. */
9850 /* This code used to verify that a symbolic pic displacement
9851 includes the pic_offset_table_rtx register.
9853 While this is good idea, unfortunately these constructs may
9854 be created by "adds using lea" optimization for incorrect
9863 This code is nonsensical, but results in addressing
9864 GOT table with pic_offset_table_rtx base. We can't
9865 just refuse it easily, since it gets matched by
9866 "addsi3" pattern, that later gets split to lea in the
9867 case output register differs from input. While this
9868 can be handled by separate addsi pattern for this case
9869 that never results in lea, this seems to be easier and
9870 correct fix for crash to disable this test. */
9872 else if (GET_CODE (disp) != LABEL_REF
9873 && !CONST_INT_P (disp)
9874 && (GET_CODE (disp) != CONST
9875 || !legitimate_constant_p (disp))
9876 && (GET_CODE (disp) != SYMBOL_REF
9877 || !legitimate_constant_p (disp)))
9878 /* Displacement is not constant. */
9880 else if (TARGET_64BIT
9881 && !x86_64_immediate_operand (disp, VOIDmode))
9882 /* Displacement is out of range. */
9886 /* Everything looks valid. */
9890 /* Determine if a given RTX is a valid constant address. */
9893 constant_address_p (rtx x)
9895 return CONSTANT_P (x) && ix86_legitimate_address_p (Pmode, x, 1);
9898 /* Return a unique alias set for the GOT. */
9900 static alias_set_type
9901 ix86_GOT_alias_set (void)
9903 static alias_set_type set = -1;
9905 set = new_alias_set ();
9909 /* Return a legitimate reference for ORIG (an address) using the
9910 register REG. If REG is 0, a new pseudo is generated.
9912 There are two types of references that must be handled:
9914 1. Global data references must load the address from the GOT, via
9915 the PIC reg. An insn is emitted to do this load, and the reg is
9918 2. Static data references, constant pool addresses, and code labels
9919 compute the address as an offset from the GOT, whose base is in
9920 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9921 differentiate them from global data objects. The returned
9922 address is the PIC reg + an unspec constant.
9924 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
9925 reg also appears in the address. */
9928 legitimize_pic_address (rtx orig, rtx reg)
9935 if (TARGET_MACHO && !TARGET_64BIT)
9938 reg = gen_reg_rtx (Pmode);
9939 /* Use the generic Mach-O PIC machinery. */
9940 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9944 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9946 else if (TARGET_64BIT
9947 && ix86_cmodel != CM_SMALL_PIC
9948 && gotoff_operand (addr, Pmode))
9951 /* This symbol may be referenced via a displacement from the PIC
9952 base address (@GOTOFF). */
9954 if (reload_in_progress)
9955 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9956 if (GET_CODE (addr) == CONST)
9957 addr = XEXP (addr, 0);
9958 if (GET_CODE (addr) == PLUS)
9960 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9962 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9965 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9966 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9968 tmpreg = gen_reg_rtx (Pmode);
9971 emit_move_insn (tmpreg, new_rtx);
9975 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9976 tmpreg, 1, OPTAB_DIRECT);
9979 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9981 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9983 /* This symbol may be referenced via a displacement from the PIC
9984 base address (@GOTOFF). */
9986 if (reload_in_progress)
9987 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9988 if (GET_CODE (addr) == CONST)
9989 addr = XEXP (addr, 0);
9990 if (GET_CODE (addr) == PLUS)
9992 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9994 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9997 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9998 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9999 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10003 emit_move_insn (reg, new_rtx);
10007 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
10008 /* We can't use @GOTOFF for text labels on VxWorks;
10009 see gotoff_operand. */
10010 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
10012 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10014 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
10015 return legitimize_dllimport_symbol (addr, true);
10016 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
10017 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
10018 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
10020 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
10021 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
10025 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
10027 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
10028 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10029 new_rtx = gen_const_mem (Pmode, new_rtx);
10030 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
10033 reg = gen_reg_rtx (Pmode);
10034 /* Use directly gen_movsi, otherwise the address is loaded
10035 into register for CSE. We don't want to CSE this addresses,
10036 instead we CSE addresses from the GOT table, so skip this. */
10037 emit_insn (gen_movsi (reg, new_rtx));
10042 /* This symbol must be referenced via a load from the
10043 Global Offset Table (@GOT). */
10045 if (reload_in_progress)
10046 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10047 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
10048 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10050 new_rtx = force_reg (Pmode, new_rtx);
10051 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10052 new_rtx = gen_const_mem (Pmode, new_rtx);
10053 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
10056 reg = gen_reg_rtx (Pmode);
10057 emit_move_insn (reg, new_rtx);
10063 if (CONST_INT_P (addr)
10064 && !x86_64_immediate_operand (addr, VOIDmode))
10068 emit_move_insn (reg, addr);
10072 new_rtx = force_reg (Pmode, addr);
10074 else if (GET_CODE (addr) == CONST)
10076 addr = XEXP (addr, 0);
10078 /* We must match stuff we generate before. Assume the only
10079 unspecs that can get here are ours. Not that we could do
10080 anything with them anyway.... */
10081 if (GET_CODE (addr) == UNSPEC
10082 || (GET_CODE (addr) == PLUS
10083 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
10085 gcc_assert (GET_CODE (addr) == PLUS);
10087 if (GET_CODE (addr) == PLUS)
10089 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
10091 /* Check first to see if this is a constant offset from a @GOTOFF
10092 symbol reference. */
10093 if (gotoff_operand (op0, Pmode)
10094 && CONST_INT_P (op1))
10098 if (reload_in_progress)
10099 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10100 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
10102 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
10103 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10104 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10108 emit_move_insn (reg, new_rtx);
10114 if (INTVAL (op1) < -16*1024*1024
10115 || INTVAL (op1) >= 16*1024*1024)
10117 if (!x86_64_immediate_operand (op1, Pmode))
10118 op1 = force_reg (Pmode, op1);
10119 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
10125 base = legitimize_pic_address (XEXP (addr, 0), reg);
10126 new_rtx = legitimize_pic_address (XEXP (addr, 1),
10127 base == reg ? NULL_RTX : reg);
10129 if (CONST_INT_P (new_rtx))
10130 new_rtx = plus_constant (base, INTVAL (new_rtx));
10133 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
10135 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
10136 new_rtx = XEXP (new_rtx, 1);
10138 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
10146 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10149 get_thread_pointer (int to_reg)
10153 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
10157 reg = gen_reg_rtx (Pmode);
10158 insn = gen_rtx_SET (VOIDmode, reg, tp);
10159 insn = emit_insn (insn);
10164 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10165 false if we expect this to be used for a memory address and true if
10166 we expect to load the address into a register. */
10169 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
10171 rtx dest, base, off, pic, tp;
10176 case TLS_MODEL_GLOBAL_DYNAMIC:
10177 dest = gen_reg_rtx (Pmode);
10178 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10180 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10182 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
10185 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
10186 insns = get_insns ();
10189 RTL_CONST_CALL_P (insns) = 1;
10190 emit_libcall_block (insns, dest, rax, x);
10192 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10193 emit_insn (gen_tls_global_dynamic_64 (dest, x));
10195 emit_insn (gen_tls_global_dynamic_32 (dest, x));
10197 if (TARGET_GNU2_TLS)
10199 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
10201 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10205 case TLS_MODEL_LOCAL_DYNAMIC:
10206 base = gen_reg_rtx (Pmode);
10207 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10209 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10211 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
10214 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
10215 insns = get_insns ();
10218 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
10219 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
10220 RTL_CONST_CALL_P (insns) = 1;
10221 emit_libcall_block (insns, base, rax, note);
10223 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10224 emit_insn (gen_tls_local_dynamic_base_64 (base));
10226 emit_insn (gen_tls_local_dynamic_base_32 (base));
10228 if (TARGET_GNU2_TLS)
10230 rtx x = ix86_tls_module_base ();
10232 set_unique_reg_note (get_last_insn (), REG_EQUIV,
10233 gen_rtx_MINUS (Pmode, x, tp));
10236 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
10237 off = gen_rtx_CONST (Pmode, off);
10239 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
10241 if (TARGET_GNU2_TLS)
10243 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
10245 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10250 case TLS_MODEL_INITIAL_EXEC:
10254 type = UNSPEC_GOTNTPOFF;
10258 if (reload_in_progress)
10259 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10260 pic = pic_offset_table_rtx;
10261 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
10263 else if (!TARGET_ANY_GNU_TLS)
10265 pic = gen_reg_rtx (Pmode);
10266 emit_insn (gen_set_got (pic));
10267 type = UNSPEC_GOTTPOFF;
10272 type = UNSPEC_INDNTPOFF;
10275 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
10276 off = gen_rtx_CONST (Pmode, off);
10278 off = gen_rtx_PLUS (Pmode, pic, off);
10279 off = gen_const_mem (Pmode, off);
10280 set_mem_alias_set (off, ix86_GOT_alias_set ());
10282 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10284 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10285 off = force_reg (Pmode, off);
10286 return gen_rtx_PLUS (Pmode, base, off);
10290 base = get_thread_pointer (true);
10291 dest = gen_reg_rtx (Pmode);
10292 emit_insn (gen_subsi3 (dest, base, off));
10296 case TLS_MODEL_LOCAL_EXEC:
10297 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
10298 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10299 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
10300 off = gen_rtx_CONST (Pmode, off);
10302 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10304 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10305 return gen_rtx_PLUS (Pmode, base, off);
10309 base = get_thread_pointer (true);
10310 dest = gen_reg_rtx (Pmode);
10311 emit_insn (gen_subsi3 (dest, base, off));
10316 gcc_unreachable ();
10322 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10325 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
10326 htab_t dllimport_map;
10329 get_dllimport_decl (tree decl)
10331 struct tree_map *h, in;
10334 const char *prefix;
10335 size_t namelen, prefixlen;
10340 if (!dllimport_map)
10341 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
10343 in.hash = htab_hash_pointer (decl);
10344 in.base.from = decl;
10345 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
10346 h = (struct tree_map *) *loc;
10350 *loc = h = GGC_NEW (struct tree_map);
10352 h->base.from = decl;
10353 h->to = to = build_decl (DECL_SOURCE_LOCATION (decl),
10354 VAR_DECL, NULL, ptr_type_node);
10355 DECL_ARTIFICIAL (to) = 1;
10356 DECL_IGNORED_P (to) = 1;
10357 DECL_EXTERNAL (to) = 1;
10358 TREE_READONLY (to) = 1;
10360 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10361 name = targetm.strip_name_encoding (name);
10362 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
10363 ? "*__imp_" : "*__imp__";
10364 namelen = strlen (name);
10365 prefixlen = strlen (prefix);
10366 imp_name = (char *) alloca (namelen + prefixlen + 1);
10367 memcpy (imp_name, prefix, prefixlen);
10368 memcpy (imp_name + prefixlen, name, namelen + 1);
10370 name = ggc_alloc_string (imp_name, namelen + prefixlen);
10371 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
10372 SET_SYMBOL_REF_DECL (rtl, to);
10373 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
10375 rtl = gen_const_mem (Pmode, rtl);
10376 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
10378 SET_DECL_RTL (to, rtl);
10379 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
10384 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10385 true if we require the result be a register. */
10388 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
10393 gcc_assert (SYMBOL_REF_DECL (symbol));
10394 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
10396 x = DECL_RTL (imp_decl);
10398 x = force_reg (Pmode, x);
10402 /* Try machine-dependent ways of modifying an illegitimate address
10403 to be legitimate. If we find one, return the new, valid address.
10404 This macro is used in only one place: `memory_address' in explow.c.
10406 OLDX is the address as it was before break_out_memory_refs was called.
10407 In some cases it is useful to look at this to decide what needs to be done.
10409 It is always safe for this macro to do nothing. It exists to recognize
10410 opportunities to optimize the output.
10412 For the 80386, we handle X+REG by loading X into a register R and
10413 using R+REG. R will go in a general reg and indexing will be used.
10414 However, if REG is a broken-out memory address or multiplication,
10415 nothing needs to be done because REG can certainly go in a general reg.
10417 When -fpic is used, special handling is needed for symbolic references.
10418 See comments by legitimize_pic_address in i386.c for details. */
10421 ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
10422 enum machine_mode mode)
10427 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10429 return legitimize_tls_address (x, (enum tls_model) log, false);
10430 if (GET_CODE (x) == CONST
10431 && GET_CODE (XEXP (x, 0)) == PLUS
10432 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10433 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10435 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10436 (enum tls_model) log, false);
10437 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10440 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10442 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10443 return legitimize_dllimport_symbol (x, true);
10444 if (GET_CODE (x) == CONST
10445 && GET_CODE (XEXP (x, 0)) == PLUS
10446 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10447 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10449 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10450 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10454 if (flag_pic && SYMBOLIC_CONST (x))
10455 return legitimize_pic_address (x, 0);
10457 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10458 if (GET_CODE (x) == ASHIFT
10459 && CONST_INT_P (XEXP (x, 1))
10460 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10463 log = INTVAL (XEXP (x, 1));
10464 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10465 GEN_INT (1 << log));
10468 if (GET_CODE (x) == PLUS)
10470 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10472 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10473 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10474 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10477 log = INTVAL (XEXP (XEXP (x, 0), 1));
10478 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10479 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10480 GEN_INT (1 << log));
10483 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10484 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10485 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10488 log = INTVAL (XEXP (XEXP (x, 1), 1));
10489 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10490 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10491 GEN_INT (1 << log));
10494 /* Put multiply first if it isn't already. */
10495 if (GET_CODE (XEXP (x, 1)) == MULT)
10497 rtx tmp = XEXP (x, 0);
10498 XEXP (x, 0) = XEXP (x, 1);
10503 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10504 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10505 created by virtual register instantiation, register elimination, and
10506 similar optimizations. */
10507 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10510 x = gen_rtx_PLUS (Pmode,
10511 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10512 XEXP (XEXP (x, 1), 0)),
10513 XEXP (XEXP (x, 1), 1));
10517 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10518 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10519 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10520 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10521 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10522 && CONSTANT_P (XEXP (x, 1)))
10525 rtx other = NULL_RTX;
10527 if (CONST_INT_P (XEXP (x, 1)))
10529 constant = XEXP (x, 1);
10530 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10532 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10534 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10535 other = XEXP (x, 1);
10543 x = gen_rtx_PLUS (Pmode,
10544 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10545 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10546 plus_constant (other, INTVAL (constant)));
10550 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10553 if (GET_CODE (XEXP (x, 0)) == MULT)
10556 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10559 if (GET_CODE (XEXP (x, 1)) == MULT)
10562 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10566 && REG_P (XEXP (x, 1))
10567 && REG_P (XEXP (x, 0)))
10570 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10573 x = legitimize_pic_address (x, 0);
10576 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10579 if (REG_P (XEXP (x, 0)))
10581 rtx temp = gen_reg_rtx (Pmode);
10582 rtx val = force_operand (XEXP (x, 1), temp);
10584 emit_move_insn (temp, val);
10586 XEXP (x, 1) = temp;
10590 else if (REG_P (XEXP (x, 1)))
10592 rtx temp = gen_reg_rtx (Pmode);
10593 rtx val = force_operand (XEXP (x, 0), temp);
10595 emit_move_insn (temp, val);
10597 XEXP (x, 0) = temp;
10605 /* Print an integer constant expression in assembler syntax. Addition
10606 and subtraction are the only arithmetic that may appear in these
10607 expressions. FILE is the stdio stream to write to, X is the rtx, and
10608 CODE is the operand print code from the output string. */
10611 output_pic_addr_const (FILE *file, rtx x, int code)
10615 switch (GET_CODE (x))
10618 gcc_assert (flag_pic);
10623 if (! TARGET_MACHO || TARGET_64BIT)
10624 output_addr_const (file, x);
10627 const char *name = XSTR (x, 0);
10629 /* Mark the decl as referenced so that cgraph will
10630 output the function. */
10631 if (SYMBOL_REF_DECL (x))
10632 mark_decl_referenced (SYMBOL_REF_DECL (x));
10635 if (MACHOPIC_INDIRECT
10636 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10637 name = machopic_indirection_name (x, /*stub_p=*/true);
10639 assemble_name (file, name);
10641 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10642 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10643 fputs ("@PLT", file);
10650 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10651 assemble_name (asm_out_file, buf);
10655 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10659 /* This used to output parentheses around the expression,
10660 but that does not work on the 386 (either ATT or BSD assembler). */
10661 output_pic_addr_const (file, XEXP (x, 0), code);
10665 if (GET_MODE (x) == VOIDmode)
10667 /* We can use %d if the number is <32 bits and positive. */
10668 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10669 fprintf (file, "0x%lx%08lx",
10670 (unsigned long) CONST_DOUBLE_HIGH (x),
10671 (unsigned long) CONST_DOUBLE_LOW (x));
10673 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10676 /* We can't handle floating point constants;
10677 PRINT_OPERAND must handle them. */
10678 output_operand_lossage ("floating constant misused");
10682 /* Some assemblers need integer constants to appear first. */
10683 if (CONST_INT_P (XEXP (x, 0)))
10685 output_pic_addr_const (file, XEXP (x, 0), code);
10687 output_pic_addr_const (file, XEXP (x, 1), code);
10691 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10692 output_pic_addr_const (file, XEXP (x, 1), code);
10694 output_pic_addr_const (file, XEXP (x, 0), code);
10700 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10701 output_pic_addr_const (file, XEXP (x, 0), code);
10703 output_pic_addr_const (file, XEXP (x, 1), code);
10705 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10709 gcc_assert (XVECLEN (x, 0) == 1);
10710 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10711 switch (XINT (x, 1))
10714 fputs ("@GOT", file);
10716 case UNSPEC_GOTOFF:
10717 fputs ("@GOTOFF", file);
10719 case UNSPEC_PLTOFF:
10720 fputs ("@PLTOFF", file);
10722 case UNSPEC_GOTPCREL:
10723 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10724 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10726 case UNSPEC_GOTTPOFF:
10727 /* FIXME: This might be @TPOFF in Sun ld too. */
10728 fputs ("@GOTTPOFF", file);
10731 fputs ("@TPOFF", file);
10733 case UNSPEC_NTPOFF:
10735 fputs ("@TPOFF", file);
10737 fputs ("@NTPOFF", file);
10739 case UNSPEC_DTPOFF:
10740 fputs ("@DTPOFF", file);
10742 case UNSPEC_GOTNTPOFF:
10744 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10745 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10747 fputs ("@GOTNTPOFF", file);
10749 case UNSPEC_INDNTPOFF:
10750 fputs ("@INDNTPOFF", file);
10753 case UNSPEC_MACHOPIC_OFFSET:
10755 machopic_output_function_base_name (file);
10759 output_operand_lossage ("invalid UNSPEC as operand");
10765 output_operand_lossage ("invalid expression as operand");
10769 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10770 We need to emit DTP-relative relocations. */
10772 static void ATTRIBUTE_UNUSED
10773 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10775 fputs (ASM_LONG, file);
10776 output_addr_const (file, x);
10777 fputs ("@DTPOFF", file);
10783 fputs (", 0", file);
10786 gcc_unreachable ();
10790 /* Return true if X is a representation of the PIC register. This copes
10791 with calls from ix86_find_base_term, where the register might have
10792 been replaced by a cselib value. */
10795 ix86_pic_register_p (rtx x)
10797 if (GET_CODE (x) == VALUE && CSELIB_VAL_PTR (x))
10798 return (pic_offset_table_rtx
10799 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10801 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10804 /* In the name of slightly smaller debug output, and to cater to
10805 general assembler lossage, recognize PIC+GOTOFF and turn it back
10806 into a direct symbol reference.
10808 On Darwin, this is necessary to avoid a crash, because Darwin
10809 has a different PIC label for each routine but the DWARF debugging
10810 information is not associated with any particular routine, so it's
10811 necessary to remove references to the PIC label from RTL stored by
10812 the DWARF output code. */
10815 ix86_delegitimize_address (rtx x)
10817 rtx orig_x = delegitimize_mem_from_attrs (x);
10818 /* reg_addend is NULL or a multiple of some register. */
10819 rtx reg_addend = NULL_RTX;
10820 /* const_addend is NULL or a const_int. */
10821 rtx const_addend = NULL_RTX;
10822 /* This is the result, or NULL. */
10823 rtx result = NULL_RTX;
10832 if (GET_CODE (x) != CONST
10833 || GET_CODE (XEXP (x, 0)) != UNSPEC
10834 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10835 || !MEM_P (orig_x))
10837 return XVECEXP (XEXP (x, 0), 0, 0);
10840 if (GET_CODE (x) != PLUS
10841 || GET_CODE (XEXP (x, 1)) != CONST)
10844 if (ix86_pic_register_p (XEXP (x, 0)))
10845 /* %ebx + GOT/GOTOFF */
10847 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10849 /* %ebx + %reg * scale + GOT/GOTOFF */
10850 reg_addend = XEXP (x, 0);
10851 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10852 reg_addend = XEXP (reg_addend, 1);
10853 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10854 reg_addend = XEXP (reg_addend, 0);
10857 if (!REG_P (reg_addend)
10858 && GET_CODE (reg_addend) != MULT
10859 && GET_CODE (reg_addend) != ASHIFT)
10865 x = XEXP (XEXP (x, 1), 0);
10866 if (GET_CODE (x) == PLUS
10867 && CONST_INT_P (XEXP (x, 1)))
10869 const_addend = XEXP (x, 1);
10873 if (GET_CODE (x) == UNSPEC
10874 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10875 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10876 result = XVECEXP (x, 0, 0);
10878 if (TARGET_MACHO && darwin_local_data_pic (x)
10879 && !MEM_P (orig_x))
10880 result = XVECEXP (x, 0, 0);
10886 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10888 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10892 /* If X is a machine specific address (i.e. a symbol or label being
10893 referenced as a displacement from the GOT implemented using an
10894 UNSPEC), then return the base term. Otherwise return X. */
10897 ix86_find_base_term (rtx x)
10903 if (GET_CODE (x) != CONST)
10905 term = XEXP (x, 0);
10906 if (GET_CODE (term) == PLUS
10907 && (CONST_INT_P (XEXP (term, 1))
10908 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10909 term = XEXP (term, 0);
10910 if (GET_CODE (term) != UNSPEC
10911 || XINT (term, 1) != UNSPEC_GOTPCREL)
10914 return XVECEXP (term, 0, 0);
10917 return ix86_delegitimize_address (x);
10921 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10922 int fp, FILE *file)
10924 const char *suffix;
10926 if (mode == CCFPmode || mode == CCFPUmode)
10928 code = ix86_fp_compare_code_to_integer (code);
10932 code = reverse_condition (code);
10983 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10987 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10988 Those same assemblers have the same but opposite lossage on cmov. */
10989 if (mode == CCmode)
10990 suffix = fp ? "nbe" : "a";
10991 else if (mode == CCCmode)
10994 gcc_unreachable ();
11010 gcc_unreachable ();
11014 gcc_assert (mode == CCmode || mode == CCCmode);
11031 gcc_unreachable ();
11035 /* ??? As above. */
11036 gcc_assert (mode == CCmode || mode == CCCmode);
11037 suffix = fp ? "nb" : "ae";
11040 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
11044 /* ??? As above. */
11045 if (mode == CCmode)
11047 else if (mode == CCCmode)
11048 suffix = fp ? "nb" : "ae";
11050 gcc_unreachable ();
11053 suffix = fp ? "u" : "p";
11056 suffix = fp ? "nu" : "np";
11059 gcc_unreachable ();
11061 fputs (suffix, file);
11064 /* Print the name of register X to FILE based on its machine mode and number.
11065 If CODE is 'w', pretend the mode is HImode.
11066 If CODE is 'b', pretend the mode is QImode.
11067 If CODE is 'k', pretend the mode is SImode.
11068 If CODE is 'q', pretend the mode is DImode.
11069 If CODE is 'x', pretend the mode is V4SFmode.
11070 If CODE is 't', pretend the mode is V8SFmode.
11071 If CODE is 'h', pretend the reg is the 'high' byte register.
11072 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
11073 If CODE is 'd', duplicate the operand for AVX instruction.
11077 print_reg (rtx x, int code, FILE *file)
11080 bool duplicated = code == 'd' && TARGET_AVX;
11082 gcc_assert (x == pc_rtx
11083 || (REGNO (x) != ARG_POINTER_REGNUM
11084 && REGNO (x) != FRAME_POINTER_REGNUM
11085 && REGNO (x) != FLAGS_REG
11086 && REGNO (x) != FPSR_REG
11087 && REGNO (x) != FPCR_REG));
11089 if (ASSEMBLER_DIALECT == ASM_ATT)
11094 gcc_assert (TARGET_64BIT);
11095 fputs ("rip", file);
11099 if (code == 'w' || MMX_REG_P (x))
11101 else if (code == 'b')
11103 else if (code == 'k')
11105 else if (code == 'q')
11107 else if (code == 'y')
11109 else if (code == 'h')
11111 else if (code == 'x')
11113 else if (code == 't')
11116 code = GET_MODE_SIZE (GET_MODE (x));
11118 /* Irritatingly, AMD extended registers use different naming convention
11119 from the normal registers. */
11120 if (REX_INT_REG_P (x))
11122 gcc_assert (TARGET_64BIT);
11126 error ("extended registers have no high halves");
11129 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
11132 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
11135 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
11138 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
11141 error ("unsupported operand size for extended register");
11151 if (STACK_TOP_P (x))
11160 if (! ANY_FP_REG_P (x))
11161 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
11166 reg = hi_reg_name[REGNO (x)];
11169 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
11171 reg = qi_reg_name[REGNO (x)];
11174 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
11176 reg = qi_high_reg_name[REGNO (x)];
11181 gcc_assert (!duplicated);
11183 fputs (hi_reg_name[REGNO (x)] + 1, file);
11188 gcc_unreachable ();
11194 if (ASSEMBLER_DIALECT == ASM_ATT)
11195 fprintf (file, ", %%%s", reg);
11197 fprintf (file, ", %s", reg);
11201 /* Locate some local-dynamic symbol still in use by this function
11202 so that we can print its name in some tls_local_dynamic_base
11206 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11210 if (GET_CODE (x) == SYMBOL_REF
11211 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11213 cfun->machine->some_ld_name = XSTR (x, 0);
11220 static const char *
11221 get_some_local_dynamic_name (void)
11225 if (cfun->machine->some_ld_name)
11226 return cfun->machine->some_ld_name;
11228 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11230 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
11231 return cfun->machine->some_ld_name;
11233 gcc_unreachable ();
11236 /* Meaning of CODE:
11237 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11238 C -- print opcode suffix for set/cmov insn.
11239 c -- like C, but print reversed condition
11240 E,e -- likewise, but for compare-and-branch fused insn.
11241 F,f -- likewise, but for floating-point.
11242 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11244 R -- print the prefix for register names.
11245 z -- print the opcode suffix for the size of the current operand.
11246 Z -- likewise, with special suffixes for x87 instructions.
11247 * -- print a star (in certain assembler syntax)
11248 A -- print an absolute memory reference.
11249 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11250 s -- print a shift double count, followed by the assemblers argument
11252 b -- print the QImode name of the register for the indicated operand.
11253 %b0 would print %al if operands[0] is reg 0.
11254 w -- likewise, print the HImode name of the register.
11255 k -- likewise, print the SImode name of the register.
11256 q -- likewise, print the DImode name of the register.
11257 x -- likewise, print the V4SFmode name of the register.
11258 t -- likewise, print the V8SFmode name of the register.
11259 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11260 y -- print "st(0)" instead of "st" as a register.
11261 d -- print duplicated register operand for AVX instruction.
11262 D -- print condition for SSE cmp instruction.
11263 P -- if PIC, print an @PLT suffix.
11264 X -- don't print any sort of PIC '@' suffix for a symbol.
11265 & -- print some in-use local-dynamic symbol name.
11266 H -- print a memory address offset by 8; used for sse high-parts
11267 + -- print a branch hint as 'cs' or 'ds' prefix
11268 ; -- print a semicolon (after prefixes due to bug in older gas).
11272 print_operand (FILE *file, rtx x, int code)
11279 if (ASSEMBLER_DIALECT == ASM_ATT)
11284 assemble_name (file, get_some_local_dynamic_name ());
11288 switch (ASSEMBLER_DIALECT)
11295 /* Intel syntax. For absolute addresses, registers should not
11296 be surrounded by braces. */
11300 PRINT_OPERAND (file, x, 0);
11307 gcc_unreachable ();
11310 PRINT_OPERAND (file, x, 0);
11315 if (ASSEMBLER_DIALECT == ASM_ATT)
11320 if (ASSEMBLER_DIALECT == ASM_ATT)
11325 if (ASSEMBLER_DIALECT == ASM_ATT)
11330 if (ASSEMBLER_DIALECT == ASM_ATT)
11335 if (ASSEMBLER_DIALECT == ASM_ATT)
11340 if (ASSEMBLER_DIALECT == ASM_ATT)
11345 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11347 /* Opcodes don't get size suffixes if using Intel opcodes. */
11348 if (ASSEMBLER_DIALECT == ASM_INTEL)
11351 switch (GET_MODE_SIZE (GET_MODE (x)))
11370 output_operand_lossage
11371 ("invalid operand size for operand code '%c'", code);
11376 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11378 (0, "non-integer operand used with operand code '%c'", code);
11382 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11383 if (ASSEMBLER_DIALECT == ASM_INTEL)
11386 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11388 switch (GET_MODE_SIZE (GET_MODE (x)))
11391 #ifdef HAVE_AS_IX86_FILDS
11401 #ifdef HAVE_AS_IX86_FILDQ
11404 fputs ("ll", file);
11412 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11414 /* 387 opcodes don't get size suffixes
11415 if the operands are registers. */
11416 if (STACK_REG_P (x))
11419 switch (GET_MODE_SIZE (GET_MODE (x)))
11440 output_operand_lossage
11441 ("invalid operand type used with operand code '%c'", code);
11445 output_operand_lossage
11446 ("invalid operand size for operand code '%c'", code);
11463 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11465 PRINT_OPERAND (file, x, 0);
11466 fputs (", ", file);
11471 /* Little bit of braindamage here. The SSE compare instructions
11472 does use completely different names for the comparisons that the
11473 fp conditional moves. */
11476 switch (GET_CODE (x))
11479 fputs ("eq", file);
11482 fputs ("eq_us", file);
11485 fputs ("lt", file);
11488 fputs ("nge", file);
11491 fputs ("le", file);
11494 fputs ("ngt", file);
11497 fputs ("unord", file);
11500 fputs ("neq", file);
11503 fputs ("neq_oq", file);
11506 fputs ("ge", file);
11509 fputs ("nlt", file);
11512 fputs ("gt", file);
11515 fputs ("nle", file);
11518 fputs ("ord", file);
11521 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11527 switch (GET_CODE (x))
11531 fputs ("eq", file);
11535 fputs ("lt", file);
11539 fputs ("le", file);
11542 fputs ("unord", file);
11546 fputs ("neq", file);
11550 fputs ("nlt", file);
11554 fputs ("nle", file);
11557 fputs ("ord", file);
11560 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11566 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11567 if (ASSEMBLER_DIALECT == ASM_ATT)
11569 switch (GET_MODE (x))
11571 case HImode: putc ('w', file); break;
11573 case SFmode: putc ('l', file); break;
11575 case DFmode: putc ('q', file); break;
11576 default: gcc_unreachable ();
11583 if (!COMPARISON_P (x))
11585 output_operand_lossage ("operand is neither a constant nor a "
11586 "condition code, invalid operand code "
11590 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11593 if (!COMPARISON_P (x))
11595 output_operand_lossage ("operand is neither a constant nor a "
11596 "condition code, invalid operand code "
11600 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11601 if (ASSEMBLER_DIALECT == ASM_ATT)
11604 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11607 /* Like above, but reverse condition */
11609 /* Check to see if argument to %c is really a constant
11610 and not a condition code which needs to be reversed. */
11611 if (!COMPARISON_P (x))
11613 output_operand_lossage ("operand is neither a constant nor a "
11614 "condition code, invalid operand "
11618 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11621 if (!COMPARISON_P (x))
11623 output_operand_lossage ("operand is neither a constant nor a "
11624 "condition code, invalid operand "
11628 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11629 if (ASSEMBLER_DIALECT == ASM_ATT)
11632 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11636 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11640 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11644 /* It doesn't actually matter what mode we use here, as we're
11645 only going to use this for printing. */
11646 x = adjust_address_nv (x, DImode, 8);
11654 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11657 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11660 int pred_val = INTVAL (XEXP (x, 0));
11662 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11663 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11665 int taken = pred_val > REG_BR_PROB_BASE / 2;
11666 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11668 /* Emit hints only in the case default branch prediction
11669 heuristics would fail. */
11670 if (taken != cputaken)
11672 /* We use 3e (DS) prefix for taken branches and
11673 2e (CS) prefix for not taken branches. */
11675 fputs ("ds ; ", file);
11677 fputs ("cs ; ", file);
11686 fputs (" ; ", file);
11693 output_operand_lossage ("invalid operand code '%c'", code);
11698 print_reg (x, code, file);
11700 else if (MEM_P (x))
11702 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11703 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11704 && GET_MODE (x) != BLKmode)
11707 switch (GET_MODE_SIZE (GET_MODE (x)))
11709 case 1: size = "BYTE"; break;
11710 case 2: size = "WORD"; break;
11711 case 4: size = "DWORD"; break;
11712 case 8: size = "QWORD"; break;
11713 case 12: size = "XWORD"; break;
11715 if (GET_MODE (x) == XFmode)
11721 gcc_unreachable ();
11724 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11727 else if (code == 'w')
11729 else if (code == 'k')
11732 fputs (size, file);
11733 fputs (" PTR ", file);
11737 /* Avoid (%rip) for call operands. */
11738 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11739 && !CONST_INT_P (x))
11740 output_addr_const (file, x);
11741 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11742 output_operand_lossage ("invalid constraints for operand");
11744 output_address (x);
11747 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11752 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11753 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11755 if (ASSEMBLER_DIALECT == ASM_ATT)
11757 fprintf (file, "0x%08lx", (long unsigned int) l);
11760 /* These float cases don't actually occur as immediate operands. */
11761 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11765 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11766 fputs (dstr, file);
11769 else if (GET_CODE (x) == CONST_DOUBLE
11770 && GET_MODE (x) == XFmode)
11774 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11775 fputs (dstr, file);
11780 /* We have patterns that allow zero sets of memory, for instance.
11781 In 64-bit mode, we should probably support all 8-byte vectors,
11782 since we can in fact encode that into an immediate. */
11783 if (GET_CODE (x) == CONST_VECTOR)
11785 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11791 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11793 if (ASSEMBLER_DIALECT == ASM_ATT)
11796 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11797 || GET_CODE (x) == LABEL_REF)
11799 if (ASSEMBLER_DIALECT == ASM_ATT)
11802 fputs ("OFFSET FLAT:", file);
11805 if (CONST_INT_P (x))
11806 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11808 output_pic_addr_const (file, x, code);
11810 output_addr_const (file, x);
11814 /* Print a memory operand whose address is ADDR. */
11817 print_operand_address (FILE *file, rtx addr)
11819 struct ix86_address parts;
11820 rtx base, index, disp;
11822 int ok = ix86_decompose_address (addr, &parts);
11827 index = parts.index;
11829 scale = parts.scale;
11837 if (ASSEMBLER_DIALECT == ASM_ATT)
11839 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11842 gcc_unreachable ();
11845 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11846 if (TARGET_64BIT && !base && !index)
11850 if (GET_CODE (disp) == CONST
11851 && GET_CODE (XEXP (disp, 0)) == PLUS
11852 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11853 symbol = XEXP (XEXP (disp, 0), 0);
11855 if (GET_CODE (symbol) == LABEL_REF
11856 || (GET_CODE (symbol) == SYMBOL_REF
11857 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11860 if (!base && !index)
11862 /* Displacement only requires special attention. */
11864 if (CONST_INT_P (disp))
11866 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11867 fputs ("ds:", file);
11868 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11871 output_pic_addr_const (file, disp, 0);
11873 output_addr_const (file, disp);
11877 if (ASSEMBLER_DIALECT == ASM_ATT)
11882 output_pic_addr_const (file, disp, 0);
11883 else if (GET_CODE (disp) == LABEL_REF)
11884 output_asm_label (disp);
11886 output_addr_const (file, disp);
11891 print_reg (base, 0, file);
11895 print_reg (index, 0, file);
11897 fprintf (file, ",%d", scale);
11903 rtx offset = NULL_RTX;
11907 /* Pull out the offset of a symbol; print any symbol itself. */
11908 if (GET_CODE (disp) == CONST
11909 && GET_CODE (XEXP (disp, 0)) == PLUS
11910 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11912 offset = XEXP (XEXP (disp, 0), 1);
11913 disp = gen_rtx_CONST (VOIDmode,
11914 XEXP (XEXP (disp, 0), 0));
11918 output_pic_addr_const (file, disp, 0);
11919 else if (GET_CODE (disp) == LABEL_REF)
11920 output_asm_label (disp);
11921 else if (CONST_INT_P (disp))
11924 output_addr_const (file, disp);
11930 print_reg (base, 0, file);
11933 if (INTVAL (offset) >= 0)
11935 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11939 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11946 print_reg (index, 0, file);
11948 fprintf (file, "*%d", scale);
11956 output_addr_const_extra (FILE *file, rtx x)
11960 if (GET_CODE (x) != UNSPEC)
11963 op = XVECEXP (x, 0, 0);
11964 switch (XINT (x, 1))
11966 case UNSPEC_GOTTPOFF:
11967 output_addr_const (file, op);
11968 /* FIXME: This might be @TPOFF in Sun ld. */
11969 fputs ("@GOTTPOFF", file);
11972 output_addr_const (file, op);
11973 fputs ("@TPOFF", file);
11975 case UNSPEC_NTPOFF:
11976 output_addr_const (file, op);
11978 fputs ("@TPOFF", file);
11980 fputs ("@NTPOFF", file);
11982 case UNSPEC_DTPOFF:
11983 output_addr_const (file, op);
11984 fputs ("@DTPOFF", file);
11986 case UNSPEC_GOTNTPOFF:
11987 output_addr_const (file, op);
11989 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11990 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11992 fputs ("@GOTNTPOFF", file);
11994 case UNSPEC_INDNTPOFF:
11995 output_addr_const (file, op);
11996 fputs ("@INDNTPOFF", file);
11999 case UNSPEC_MACHOPIC_OFFSET:
12000 output_addr_const (file, op);
12002 machopic_output_function_base_name (file);
12013 /* Split one or more DImode RTL references into pairs of SImode
12014 references. The RTL can be REG, offsettable MEM, integer constant, or
12015 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12016 split and "num" is its length. lo_half and hi_half are output arrays
12017 that parallel "operands". */
12020 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
12024 rtx op = operands[num];
12026 /* simplify_subreg refuse to split volatile memory addresses,
12027 but we still have to handle it. */
12030 lo_half[num] = adjust_address (op, SImode, 0);
12031 hi_half[num] = adjust_address (op, SImode, 4);
12035 lo_half[num] = simplify_gen_subreg (SImode, op,
12036 GET_MODE (op) == VOIDmode
12037 ? DImode : GET_MODE (op), 0);
12038 hi_half[num] = simplify_gen_subreg (SImode, op,
12039 GET_MODE (op) == VOIDmode
12040 ? DImode : GET_MODE (op), 4);
12044 /* Split one or more TImode RTL references into pairs of DImode
12045 references. The RTL can be REG, offsettable MEM, integer constant, or
12046 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
12047 split and "num" is its length. lo_half and hi_half are output arrays
12048 that parallel "operands". */
12051 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
12055 rtx op = operands[num];
12057 /* simplify_subreg refuse to split volatile memory addresses, but we
12058 still have to handle it. */
12061 lo_half[num] = adjust_address (op, DImode, 0);
12062 hi_half[num] = adjust_address (op, DImode, 8);
12066 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
12067 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
12072 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12073 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12074 is the expression of the binary operation. The output may either be
12075 emitted here, or returned to the caller, like all output_* functions.
12077 There is no guarantee that the operands are the same mode, as they
12078 might be within FLOAT or FLOAT_EXTEND expressions. */
12080 #ifndef SYSV386_COMPAT
12081 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12082 wants to fix the assemblers because that causes incompatibility
12083 with gcc. No-one wants to fix gcc because that causes
12084 incompatibility with assemblers... You can use the option of
12085 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12086 #define SYSV386_COMPAT 1
12090 output_387_binary_op (rtx insn, rtx *operands)
12092 static char buf[40];
12095 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
12097 #ifdef ENABLE_CHECKING
12098 /* Even if we do not want to check the inputs, this documents input
12099 constraints. Which helps in understanding the following code. */
12100 if (STACK_REG_P (operands[0])
12101 && ((REG_P (operands[1])
12102 && REGNO (operands[0]) == REGNO (operands[1])
12103 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
12104 || (REG_P (operands[2])
12105 && REGNO (operands[0]) == REGNO (operands[2])
12106 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
12107 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
12110 gcc_assert (is_sse);
12113 switch (GET_CODE (operands[3]))
12116 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12117 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12125 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12126 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12134 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12135 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12143 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12144 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12152 gcc_unreachable ();
12159 strcpy (buf, ssep);
12160 if (GET_MODE (operands[0]) == SFmode)
12161 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
12163 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
12167 strcpy (buf, ssep + 1);
12168 if (GET_MODE (operands[0]) == SFmode)
12169 strcat (buf, "ss\t{%2, %0|%0, %2}");
12171 strcat (buf, "sd\t{%2, %0|%0, %2}");
12177 switch (GET_CODE (operands[3]))
12181 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
12183 rtx temp = operands[2];
12184 operands[2] = operands[1];
12185 operands[1] = temp;
12188 /* know operands[0] == operands[1]. */
12190 if (MEM_P (operands[2]))
12196 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12198 if (STACK_TOP_P (operands[0]))
12199 /* How is it that we are storing to a dead operand[2]?
12200 Well, presumably operands[1] is dead too. We can't
12201 store the result to st(0) as st(0) gets popped on this
12202 instruction. Instead store to operands[2] (which I
12203 think has to be st(1)). st(1) will be popped later.
12204 gcc <= 2.8.1 didn't have this check and generated
12205 assembly code that the Unixware assembler rejected. */
12206 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12208 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12212 if (STACK_TOP_P (operands[0]))
12213 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12215 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12220 if (MEM_P (operands[1]))
12226 if (MEM_P (operands[2]))
12232 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12235 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12236 derived assemblers, confusingly reverse the direction of
12237 the operation for fsub{r} and fdiv{r} when the
12238 destination register is not st(0). The Intel assembler
12239 doesn't have this brain damage. Read !SYSV386_COMPAT to
12240 figure out what the hardware really does. */
12241 if (STACK_TOP_P (operands[0]))
12242 p = "{p\t%0, %2|rp\t%2, %0}";
12244 p = "{rp\t%2, %0|p\t%0, %2}";
12246 if (STACK_TOP_P (operands[0]))
12247 /* As above for fmul/fadd, we can't store to st(0). */
12248 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12250 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12255 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
12258 if (STACK_TOP_P (operands[0]))
12259 p = "{rp\t%0, %1|p\t%1, %0}";
12261 p = "{p\t%1, %0|rp\t%0, %1}";
12263 if (STACK_TOP_P (operands[0]))
12264 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
12266 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
12271 if (STACK_TOP_P (operands[0]))
12273 if (STACK_TOP_P (operands[1]))
12274 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12276 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
12279 else if (STACK_TOP_P (operands[1]))
12282 p = "{\t%1, %0|r\t%0, %1}";
12284 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
12290 p = "{r\t%2, %0|\t%0, %2}";
12292 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12298 gcc_unreachable ();
12305 /* Return needed mode for entity in optimize_mode_switching pass. */
12308 ix86_mode_needed (int entity, rtx insn)
12310 enum attr_i387_cw mode;
12312 /* The mode UNINITIALIZED is used to store control word after a
12313 function call or ASM pattern. The mode ANY specify that function
12314 has no requirements on the control word and make no changes in the
12315 bits we are interested in. */
12318 || (NONJUMP_INSN_P (insn)
12319 && (asm_noperands (PATTERN (insn)) >= 0
12320 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
12321 return I387_CW_UNINITIALIZED;
12323 if (recog_memoized (insn) < 0)
12324 return I387_CW_ANY;
12326 mode = get_attr_i387_cw (insn);
12331 if (mode == I387_CW_TRUNC)
12336 if (mode == I387_CW_FLOOR)
12341 if (mode == I387_CW_CEIL)
12346 if (mode == I387_CW_MASK_PM)
12351 gcc_unreachable ();
12354 return I387_CW_ANY;
12357 /* Output code to initialize control word copies used by trunc?f?i and
12358 rounding patterns. CURRENT_MODE is set to current control word,
12359 while NEW_MODE is set to new control word. */
12362 emit_i387_cw_initialization (int mode)
12364 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
12367 enum ix86_stack_slot slot;
12369 rtx reg = gen_reg_rtx (HImode);
12371 emit_insn (gen_x86_fnstcw_1 (stored_mode));
12372 emit_move_insn (reg, copy_rtx (stored_mode));
12374 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
12375 || optimize_function_for_size_p (cfun))
12379 case I387_CW_TRUNC:
12380 /* round toward zero (truncate) */
12381 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
12382 slot = SLOT_CW_TRUNC;
12385 case I387_CW_FLOOR:
12386 /* round down toward -oo */
12387 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12388 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
12389 slot = SLOT_CW_FLOOR;
12393 /* round up toward +oo */
12394 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12395 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
12396 slot = SLOT_CW_CEIL;
12399 case I387_CW_MASK_PM:
12400 /* mask precision exception for nearbyint() */
12401 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12402 slot = SLOT_CW_MASK_PM;
12406 gcc_unreachable ();
12413 case I387_CW_TRUNC:
12414 /* round toward zero (truncate) */
12415 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12416 slot = SLOT_CW_TRUNC;
12419 case I387_CW_FLOOR:
12420 /* round down toward -oo */
12421 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12422 slot = SLOT_CW_FLOOR;
12426 /* round up toward +oo */
12427 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12428 slot = SLOT_CW_CEIL;
12431 case I387_CW_MASK_PM:
12432 /* mask precision exception for nearbyint() */
12433 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12434 slot = SLOT_CW_MASK_PM;
12438 gcc_unreachable ();
12442 gcc_assert (slot < MAX_386_STACK_LOCALS);
12444 new_mode = assign_386_stack_local (HImode, slot);
12445 emit_move_insn (new_mode, reg);
12448 /* Output code for INSN to convert a float to a signed int. OPERANDS
12449 are the insn operands. The output may be [HSD]Imode and the input
12450 operand may be [SDX]Fmode. */
12453 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12455 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12456 int dimode_p = GET_MODE (operands[0]) == DImode;
12457 int round_mode = get_attr_i387_cw (insn);
12459 /* Jump through a hoop or two for DImode, since the hardware has no
12460 non-popping instruction. We used to do this a different way, but
12461 that was somewhat fragile and broke with post-reload splitters. */
12462 if ((dimode_p || fisttp) && !stack_top_dies)
12463 output_asm_insn ("fld\t%y1", operands);
12465 gcc_assert (STACK_TOP_P (operands[1]));
12466 gcc_assert (MEM_P (operands[0]));
12467 gcc_assert (GET_MODE (operands[1]) != TFmode);
12470 output_asm_insn ("fisttp%Z0\t%0", operands);
12473 if (round_mode != I387_CW_ANY)
12474 output_asm_insn ("fldcw\t%3", operands);
12475 if (stack_top_dies || dimode_p)
12476 output_asm_insn ("fistp%Z0\t%0", operands);
12478 output_asm_insn ("fist%Z0\t%0", operands);
12479 if (round_mode != I387_CW_ANY)
12480 output_asm_insn ("fldcw\t%2", operands);
12486 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12487 have the values zero or one, indicates the ffreep insn's operand
12488 from the OPERANDS array. */
12490 static const char *
12491 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12493 if (TARGET_USE_FFREEP)
12494 #ifdef HAVE_AS_IX86_FFREEP
12495 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12498 static char retval[32];
12499 int regno = REGNO (operands[opno]);
12501 gcc_assert (FP_REGNO_P (regno));
12503 regno -= FIRST_STACK_REG;
12505 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
12510 return opno ? "fstp\t%y1" : "fstp\t%y0";
12514 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12515 should be used. UNORDERED_P is true when fucom should be used. */
12518 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12520 int stack_top_dies;
12521 rtx cmp_op0, cmp_op1;
12522 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12526 cmp_op0 = operands[0];
12527 cmp_op1 = operands[1];
12531 cmp_op0 = operands[1];
12532 cmp_op1 = operands[2];
12537 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12538 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12539 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12540 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12542 if (GET_MODE (operands[0]) == SFmode)
12544 return &ucomiss[TARGET_AVX ? 0 : 1];
12546 return &comiss[TARGET_AVX ? 0 : 1];
12549 return &ucomisd[TARGET_AVX ? 0 : 1];
12551 return &comisd[TARGET_AVX ? 0 : 1];
12554 gcc_assert (STACK_TOP_P (cmp_op0));
12556 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12558 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12560 if (stack_top_dies)
12562 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12563 return output_387_ffreep (operands, 1);
12566 return "ftst\n\tfnstsw\t%0";
12569 if (STACK_REG_P (cmp_op1)
12571 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12572 && REGNO (cmp_op1) != FIRST_STACK_REG)
12574 /* If both the top of the 387 stack dies, and the other operand
12575 is also a stack register that dies, then this must be a
12576 `fcompp' float compare */
12580 /* There is no double popping fcomi variant. Fortunately,
12581 eflags is immune from the fstp's cc clobbering. */
12583 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12585 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12586 return output_387_ffreep (operands, 0);
12591 return "fucompp\n\tfnstsw\t%0";
12593 return "fcompp\n\tfnstsw\t%0";
12598 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12600 static const char * const alt[16] =
12602 "fcom%Z2\t%y2\n\tfnstsw\t%0",
12603 "fcomp%Z2\t%y2\n\tfnstsw\t%0",
12604 "fucom%Z2\t%y2\n\tfnstsw\t%0",
12605 "fucomp%Z2\t%y2\n\tfnstsw\t%0",
12607 "ficom%Z2\t%y2\n\tfnstsw\t%0",
12608 "ficomp%Z2\t%y2\n\tfnstsw\t%0",
12612 "fcomi\t{%y1, %0|%0, %y1}",
12613 "fcomip\t{%y1, %0|%0, %y1}",
12614 "fucomi\t{%y1, %0|%0, %y1}",
12615 "fucomip\t{%y1, %0|%0, %y1}",
12626 mask = eflags_p << 3;
12627 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12628 mask |= unordered_p << 1;
12629 mask |= stack_top_dies;
12631 gcc_assert (mask < 16);
12640 ix86_output_addr_vec_elt (FILE *file, int value)
12642 const char *directive = ASM_LONG;
12646 directive = ASM_QUAD;
12648 gcc_assert (!TARGET_64BIT);
12651 fprintf (file, "%s" LPREFIX "%d\n", directive, value);
12655 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12657 const char *directive = ASM_LONG;
12660 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12661 directive = ASM_QUAD;
12663 gcc_assert (!TARGET_64BIT);
12665 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12666 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12667 fprintf (file, "%s" LPREFIX "%d-" LPREFIX "%d\n",
12668 directive, value, rel);
12669 else if (HAVE_AS_GOTOFF_IN_DATA)
12670 fprintf (file, ASM_LONG LPREFIX "%d@GOTOFF\n", value);
12672 else if (TARGET_MACHO)
12674 fprintf (file, ASM_LONG LPREFIX "%d-", value);
12675 machopic_output_function_base_name (file);
12680 asm_fprintf (file, ASM_LONG "%U%s+[.-" LPREFIX "%d]\n",
12681 GOT_SYMBOL_NAME, value);
12684 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12688 ix86_expand_clear (rtx dest)
12692 /* We play register width games, which are only valid after reload. */
12693 gcc_assert (reload_completed);
12695 /* Avoid HImode and its attendant prefix byte. */
12696 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12697 dest = gen_rtx_REG (SImode, REGNO (dest));
12698 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12700 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12701 if (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ())
12703 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12704 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12710 /* X is an unchanging MEM. If it is a constant pool reference, return
12711 the constant pool rtx, else NULL. */
12714 maybe_get_pool_constant (rtx x)
12716 x = ix86_delegitimize_address (XEXP (x, 0));
12718 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12719 return get_pool_constant (x);
12725 ix86_expand_move (enum machine_mode mode, rtx operands[])
12728 enum tls_model model;
12733 if (GET_CODE (op1) == SYMBOL_REF)
12735 model = SYMBOL_REF_TLS_MODEL (op1);
12738 op1 = legitimize_tls_address (op1, model, true);
12739 op1 = force_operand (op1, op0);
12743 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12744 && SYMBOL_REF_DLLIMPORT_P (op1))
12745 op1 = legitimize_dllimport_symbol (op1, false);
12747 else if (GET_CODE (op1) == CONST
12748 && GET_CODE (XEXP (op1, 0)) == PLUS
12749 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12751 rtx addend = XEXP (XEXP (op1, 0), 1);
12752 rtx symbol = XEXP (XEXP (op1, 0), 0);
12755 model = SYMBOL_REF_TLS_MODEL (symbol);
12757 tmp = legitimize_tls_address (symbol, model, true);
12758 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12759 && SYMBOL_REF_DLLIMPORT_P (symbol))
12760 tmp = legitimize_dllimport_symbol (symbol, true);
12764 tmp = force_operand (tmp, NULL);
12765 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12766 op0, 1, OPTAB_DIRECT);
12772 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12774 if (TARGET_MACHO && !TARGET_64BIT)
12779 rtx temp = ((reload_in_progress
12780 || ((op0 && REG_P (op0))
12782 ? op0 : gen_reg_rtx (Pmode));
12783 op1 = machopic_indirect_data_reference (op1, temp);
12784 op1 = machopic_legitimize_pic_address (op1, mode,
12785 temp == op1 ? 0 : temp);
12787 else if (MACHOPIC_INDIRECT)
12788 op1 = machopic_indirect_data_reference (op1, 0);
12796 op1 = force_reg (Pmode, op1);
12797 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12799 rtx reg = can_create_pseudo_p () ? NULL_RTX : op0;
12800 op1 = legitimize_pic_address (op1, reg);
12809 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12810 || !push_operand (op0, mode))
12812 op1 = force_reg (mode, op1);
12814 if (push_operand (op0, mode)
12815 && ! general_no_elim_operand (op1, mode))
12816 op1 = copy_to_mode_reg (mode, op1);
12818 /* Force large constants in 64bit compilation into register
12819 to get them CSEed. */
12820 if (can_create_pseudo_p ()
12821 && (mode == DImode) && TARGET_64BIT
12822 && immediate_operand (op1, mode)
12823 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12824 && !register_operand (op0, mode)
12826 op1 = copy_to_mode_reg (mode, op1);
12828 if (can_create_pseudo_p ()
12829 && FLOAT_MODE_P (mode)
12830 && GET_CODE (op1) == CONST_DOUBLE)
12832 /* If we are loading a floating point constant to a register,
12833 force the value to memory now, since we'll get better code
12834 out the back end. */
12836 op1 = validize_mem (force_const_mem (mode, op1));
12837 if (!register_operand (op0, mode))
12839 rtx temp = gen_reg_rtx (mode);
12840 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12841 emit_move_insn (op0, temp);
12847 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12851 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12853 rtx op0 = operands[0], op1 = operands[1];
12854 unsigned int align = GET_MODE_ALIGNMENT (mode);
12856 /* Force constants other than zero into memory. We do not know how
12857 the instructions used to build constants modify the upper 64 bits
12858 of the register, once we have that information we may be able
12859 to handle some of them more efficiently. */
12860 if (can_create_pseudo_p ()
12861 && register_operand (op0, mode)
12862 && (CONSTANT_P (op1)
12863 || (GET_CODE (op1) == SUBREG
12864 && CONSTANT_P (SUBREG_REG (op1))))
12865 && !standard_sse_constant_p (op1))
12866 op1 = validize_mem (force_const_mem (mode, op1));
12868 /* We need to check memory alignment for SSE mode since attribute
12869 can make operands unaligned. */
12870 if (can_create_pseudo_p ()
12871 && SSE_REG_MODE_P (mode)
12872 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12873 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12877 /* ix86_expand_vector_move_misalign() does not like constants ... */
12878 if (CONSTANT_P (op1)
12879 || (GET_CODE (op1) == SUBREG
12880 && CONSTANT_P (SUBREG_REG (op1))))
12881 op1 = validize_mem (force_const_mem (mode, op1));
12883 /* ... nor both arguments in memory. */
12884 if (!register_operand (op0, mode)
12885 && !register_operand (op1, mode))
12886 op1 = force_reg (mode, op1);
12888 tmp[0] = op0; tmp[1] = op1;
12889 ix86_expand_vector_move_misalign (mode, tmp);
12893 /* Make operand1 a register if it isn't already. */
12894 if (can_create_pseudo_p ()
12895 && !register_operand (op0, mode)
12896 && !register_operand (op1, mode))
12898 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12902 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12905 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12906 straight to ix86_expand_vector_move. */
12907 /* Code generation for scalar reg-reg moves of single and double precision data:
12908 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12912 if (x86_sse_partial_reg_dependency == true)
12917 Code generation for scalar loads of double precision data:
12918 if (x86_sse_split_regs == true)
12919 movlpd mem, reg (gas syntax)
12923 Code generation for unaligned packed loads of single precision data
12924 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12925 if (x86_sse_unaligned_move_optimal)
12928 if (x86_sse_partial_reg_dependency == true)
12940 Code generation for unaligned packed loads of double precision data
12941 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12942 if (x86_sse_unaligned_move_optimal)
12945 if (x86_sse_split_regs == true)
12958 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12967 switch (GET_MODE_CLASS (mode))
12969 case MODE_VECTOR_INT:
12971 switch (GET_MODE_SIZE (mode))
12974 op0 = gen_lowpart (V16QImode, op0);
12975 op1 = gen_lowpart (V16QImode, op1);
12976 emit_insn (gen_avx_movdqu (op0, op1));
12979 op0 = gen_lowpart (V32QImode, op0);
12980 op1 = gen_lowpart (V32QImode, op1);
12981 emit_insn (gen_avx_movdqu256 (op0, op1));
12984 gcc_unreachable ();
12987 case MODE_VECTOR_FLOAT:
12988 op0 = gen_lowpart (mode, op0);
12989 op1 = gen_lowpart (mode, op1);
12994 emit_insn (gen_avx_movups (op0, op1));
12997 emit_insn (gen_avx_movups256 (op0, op1));
13000 emit_insn (gen_avx_movupd (op0, op1));
13003 emit_insn (gen_avx_movupd256 (op0, op1));
13006 gcc_unreachable ();
13011 gcc_unreachable ();
13019 /* If we're optimizing for size, movups is the smallest. */
13020 if (optimize_insn_for_size_p ())
13022 op0 = gen_lowpart (V4SFmode, op0);
13023 op1 = gen_lowpart (V4SFmode, op1);
13024 emit_insn (gen_sse_movups (op0, op1));
13028 /* ??? If we have typed data, then it would appear that using
13029 movdqu is the only way to get unaligned data loaded with
13031 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13033 op0 = gen_lowpart (V16QImode, op0);
13034 op1 = gen_lowpart (V16QImode, op1);
13035 emit_insn (gen_sse2_movdqu (op0, op1));
13039 if (TARGET_SSE2 && mode == V2DFmode)
13043 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13045 op0 = gen_lowpart (V2DFmode, op0);
13046 op1 = gen_lowpart (V2DFmode, op1);
13047 emit_insn (gen_sse2_movupd (op0, op1));
13051 /* When SSE registers are split into halves, we can avoid
13052 writing to the top half twice. */
13053 if (TARGET_SSE_SPLIT_REGS)
13055 emit_clobber (op0);
13060 /* ??? Not sure about the best option for the Intel chips.
13061 The following would seem to satisfy; the register is
13062 entirely cleared, breaking the dependency chain. We
13063 then store to the upper half, with a dependency depth
13064 of one. A rumor has it that Intel recommends two movsd
13065 followed by an unpacklpd, but this is unconfirmed. And
13066 given that the dependency depth of the unpacklpd would
13067 still be one, I'm not sure why this would be better. */
13068 zero = CONST0_RTX (V2DFmode);
13071 m = adjust_address (op1, DFmode, 0);
13072 emit_insn (gen_sse2_loadlpd (op0, zero, m));
13073 m = adjust_address (op1, DFmode, 8);
13074 emit_insn (gen_sse2_loadhpd (op0, op0, m));
13078 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13080 op0 = gen_lowpart (V4SFmode, op0);
13081 op1 = gen_lowpart (V4SFmode, op1);
13082 emit_insn (gen_sse_movups (op0, op1));
13086 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
13087 emit_move_insn (op0, CONST0_RTX (mode));
13089 emit_clobber (op0);
13091 if (mode != V4SFmode)
13092 op0 = gen_lowpart (V4SFmode, op0);
13093 m = adjust_address (op1, V2SFmode, 0);
13094 emit_insn (gen_sse_loadlps (op0, op0, m));
13095 m = adjust_address (op1, V2SFmode, 8);
13096 emit_insn (gen_sse_loadhps (op0, op0, m));
13099 else if (MEM_P (op0))
13101 /* If we're optimizing for size, movups is the smallest. */
13102 if (optimize_insn_for_size_p ())
13104 op0 = gen_lowpart (V4SFmode, op0);
13105 op1 = gen_lowpart (V4SFmode, op1);
13106 emit_insn (gen_sse_movups (op0, op1));
13110 /* ??? Similar to above, only less clear because of quote
13111 typeless stores unquote. */
13112 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
13113 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13115 op0 = gen_lowpart (V16QImode, op0);
13116 op1 = gen_lowpart (V16QImode, op1);
13117 emit_insn (gen_sse2_movdqu (op0, op1));
13121 if (TARGET_SSE2 && mode == V2DFmode)
13123 m = adjust_address (op0, DFmode, 0);
13124 emit_insn (gen_sse2_storelpd (m, op1));
13125 m = adjust_address (op0, DFmode, 8);
13126 emit_insn (gen_sse2_storehpd (m, op1));
13130 if (mode != V4SFmode)
13131 op1 = gen_lowpart (V4SFmode, op1);
13132 m = adjust_address (op0, V2SFmode, 0);
13133 emit_insn (gen_sse_storelps (m, op1));
13134 m = adjust_address (op0, V2SFmode, 8);
13135 emit_insn (gen_sse_storehps (m, op1));
13139 gcc_unreachable ();
13142 /* Expand a push in MODE. This is some mode for which we do not support
13143 proper push instructions, at least from the registers that we expect
13144 the value to live in. */
13147 ix86_expand_push (enum machine_mode mode, rtx x)
13151 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
13152 GEN_INT (-GET_MODE_SIZE (mode)),
13153 stack_pointer_rtx, 1, OPTAB_DIRECT);
13154 if (tmp != stack_pointer_rtx)
13155 emit_move_insn (stack_pointer_rtx, tmp);
13157 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
13159 /* When we push an operand onto stack, it has to be aligned at least
13160 at the function argument boundary. However since we don't have
13161 the argument type, we can't determine the actual argument
13163 emit_move_insn (tmp, x);
13166 /* Helper function of ix86_fixup_binary_operands to canonicalize
13167 operand order. Returns true if the operands should be swapped. */
13170 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
13173 rtx dst = operands[0];
13174 rtx src1 = operands[1];
13175 rtx src2 = operands[2];
13177 /* If the operation is not commutative, we can't do anything. */
13178 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
13181 /* Highest priority is that src1 should match dst. */
13182 if (rtx_equal_p (dst, src1))
13184 if (rtx_equal_p (dst, src2))
13187 /* Next highest priority is that immediate constants come second. */
13188 if (immediate_operand (src2, mode))
13190 if (immediate_operand (src1, mode))
13193 /* Lowest priority is that memory references should come second. */
13203 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13204 destination to use for the operation. If different from the true
13205 destination in operands[0], a copy operation will be required. */
13208 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
13211 rtx dst = operands[0];
13212 rtx src1 = operands[1];
13213 rtx src2 = operands[2];
13215 /* Canonicalize operand order. */
13216 if (ix86_swap_binary_operands_p (code, mode, operands))
13220 /* It is invalid to swap operands of different modes. */
13221 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
13228 /* Both source operands cannot be in memory. */
13229 if (MEM_P (src1) && MEM_P (src2))
13231 /* Optimization: Only read from memory once. */
13232 if (rtx_equal_p (src1, src2))
13234 src2 = force_reg (mode, src2);
13238 src2 = force_reg (mode, src2);
13241 /* If the destination is memory, and we do not have matching source
13242 operands, do things in registers. */
13243 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13244 dst = gen_reg_rtx (mode);
13246 /* Source 1 cannot be a constant. */
13247 if (CONSTANT_P (src1))
13248 src1 = force_reg (mode, src1);
13250 /* Source 1 cannot be a non-matching memory. */
13251 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13252 src1 = force_reg (mode, src1);
13254 operands[1] = src1;
13255 operands[2] = src2;
13259 /* Similarly, but assume that the destination has already been
13260 set up properly. */
13263 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
13264 enum machine_mode mode, rtx operands[])
13266 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
13267 gcc_assert (dst == operands[0]);
13270 /* Attempt to expand a binary operator. Make the expansion closer to the
13271 actual machine, then just general_operand, which will allow 3 separate
13272 memory references (one output, two input) in a single insn. */
13275 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
13278 rtx src1, src2, dst, op, clob;
13280 dst = ix86_fixup_binary_operands (code, mode, operands);
13281 src1 = operands[1];
13282 src2 = operands[2];
13284 /* Emit the instruction. */
13286 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
13287 if (reload_in_progress)
13289 /* Reload doesn't know about the flags register, and doesn't know that
13290 it doesn't want to clobber it. We can only do this with PLUS. */
13291 gcc_assert (code == PLUS);
13296 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13297 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13300 /* Fix up the destination if needed. */
13301 if (dst != operands[0])
13302 emit_move_insn (operands[0], dst);
13305 /* Return TRUE or FALSE depending on whether the binary operator meets the
13306 appropriate constraints. */
13309 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
13312 rtx dst = operands[0];
13313 rtx src1 = operands[1];
13314 rtx src2 = operands[2];
13316 /* Both source operands cannot be in memory. */
13317 if (MEM_P (src1) && MEM_P (src2))
13320 /* Canonicalize operand order for commutative operators. */
13321 if (ix86_swap_binary_operands_p (code, mode, operands))
13328 /* If the destination is memory, we must have a matching source operand. */
13329 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13332 /* Source 1 cannot be a constant. */
13333 if (CONSTANT_P (src1))
13336 /* Source 1 cannot be a non-matching memory. */
13337 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13343 /* Attempt to expand a unary operator. Make the expansion closer to the
13344 actual machine, then just general_operand, which will allow 2 separate
13345 memory references (one output, one input) in a single insn. */
13348 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
13351 int matching_memory;
13352 rtx src, dst, op, clob;
13357 /* If the destination is memory, and we do not have matching source
13358 operands, do things in registers. */
13359 matching_memory = 0;
13362 if (rtx_equal_p (dst, src))
13363 matching_memory = 1;
13365 dst = gen_reg_rtx (mode);
13368 /* When source operand is memory, destination must match. */
13369 if (MEM_P (src) && !matching_memory)
13370 src = force_reg (mode, src);
13372 /* Emit the instruction. */
13374 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
13375 if (reload_in_progress || code == NOT)
13377 /* Reload doesn't know about the flags register, and doesn't know that
13378 it doesn't want to clobber it. */
13379 gcc_assert (code == NOT);
13384 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13385 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13388 /* Fix up the destination if needed. */
13389 if (dst != operands[0])
13390 emit_move_insn (operands[0], dst);
13393 #define LEA_SEARCH_THRESHOLD 12
13395 /* Search backward for non-agu definition of register number REGNO1
13396 or register number REGNO2 in INSN's basic block until
13397 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13398 2. Reach BB boundary, or
13399 3. Reach agu definition.
13400 Returns the distance between the non-agu definition point and INSN.
13401 If no definition point, returns -1. */
13404 distance_non_agu_define (unsigned int regno1, unsigned int regno2,
13407 basic_block bb = BLOCK_FOR_INSN (insn);
13410 enum attr_type insn_type;
13412 if (insn != BB_HEAD (bb))
13414 rtx prev = PREV_INSN (insn);
13415 while (prev && distance < LEA_SEARCH_THRESHOLD)
13420 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13421 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13422 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13423 && (regno1 == DF_REF_REGNO (*def_rec)
13424 || regno2 == DF_REF_REGNO (*def_rec)))
13426 insn_type = get_attr_type (prev);
13427 if (insn_type != TYPE_LEA)
13431 if (prev == BB_HEAD (bb))
13433 prev = PREV_INSN (prev);
13437 if (distance < LEA_SEARCH_THRESHOLD)
13441 bool simple_loop = false;
13443 FOR_EACH_EDGE (e, ei, bb->preds)
13446 simple_loop = true;
13452 rtx prev = BB_END (bb);
13455 && distance < LEA_SEARCH_THRESHOLD)
13460 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13461 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13462 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13463 && (regno1 == DF_REF_REGNO (*def_rec)
13464 || regno2 == DF_REF_REGNO (*def_rec)))
13466 insn_type = get_attr_type (prev);
13467 if (insn_type != TYPE_LEA)
13471 prev = PREV_INSN (prev);
13479 /* get_attr_type may modify recog data. We want to make sure
13480 that recog data is valid for instruction INSN, on which
13481 distance_non_agu_define is called. INSN is unchanged here. */
13482 extract_insn_cached (insn);
13486 /* Return the distance between INSN and the next insn that uses
13487 register number REGNO0 in memory address. Return -1 if no such
13488 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13491 distance_agu_use (unsigned int regno0, rtx insn)
13493 basic_block bb = BLOCK_FOR_INSN (insn);
13498 if (insn != BB_END (bb))
13500 rtx next = NEXT_INSN (insn);
13501 while (next && distance < LEA_SEARCH_THRESHOLD)
13507 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13508 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13509 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13510 && regno0 == DF_REF_REGNO (*use_rec))
13512 /* Return DISTANCE if OP0 is used in memory
13513 address in NEXT. */
13517 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13518 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13519 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13520 && regno0 == DF_REF_REGNO (*def_rec))
13522 /* Return -1 if OP0 is set in NEXT. */
13526 if (next == BB_END (bb))
13528 next = NEXT_INSN (next);
13532 if (distance < LEA_SEARCH_THRESHOLD)
13536 bool simple_loop = false;
13538 FOR_EACH_EDGE (e, ei, bb->succs)
13541 simple_loop = true;
13547 rtx next = BB_HEAD (bb);
13550 && distance < LEA_SEARCH_THRESHOLD)
13556 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13557 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13558 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13559 && regno0 == DF_REF_REGNO (*use_rec))
13561 /* Return DISTANCE if OP0 is used in memory
13562 address in NEXT. */
13566 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13567 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13568 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13569 && regno0 == DF_REF_REGNO (*def_rec))
13571 /* Return -1 if OP0 is set in NEXT. */
13576 next = NEXT_INSN (next);
13584 /* Define this macro to tune LEA priority vs ADD, it take effect when
13585 there is a dilemma of choicing LEA or ADD
13586 Negative value: ADD is more preferred than LEA
13588 Positive value: LEA is more preferred than ADD*/
13589 #define IX86_LEA_PRIORITY 2
13591 /* Return true if it is ok to optimize an ADD operation to LEA
13592 operation to avoid flag register consumation. For the processors
13593 like ATOM, if the destination register of LEA holds an actual
13594 address which will be used soon, LEA is better and otherwise ADD
13598 ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13599 rtx insn, rtx operands[])
13601 unsigned int regno0 = true_regnum (operands[0]);
13602 unsigned int regno1 = true_regnum (operands[1]);
13603 unsigned int regno2;
13605 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
13606 return regno0 != regno1;
13608 regno2 = true_regnum (operands[2]);
13610 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13611 if (regno0 != regno1 && regno0 != regno2)
13615 int dist_define, dist_use;
13616 dist_define = distance_non_agu_define (regno1, regno2, insn);
13617 if (dist_define <= 0)
13620 /* If this insn has both backward non-agu dependence and forward
13621 agu dependence, the one with short distance take effect. */
13622 dist_use = distance_agu_use (regno0, insn);
13624 || (dist_define + IX86_LEA_PRIORITY) < dist_use)
13631 /* Return true if destination reg of SET_BODY is shift count of
13635 ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
13641 /* Retrieve destination of SET_BODY. */
13642 switch (GET_CODE (set_body))
13645 set_dest = SET_DEST (set_body);
13646 if (!set_dest || !REG_P (set_dest))
13650 for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
13651 if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
13659 /* Retrieve shift count of USE_BODY. */
13660 switch (GET_CODE (use_body))
13663 shift_rtx = XEXP (use_body, 1);
13666 for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
13667 if (ix86_dep_by_shift_count_body (set_body,
13668 XVECEXP (use_body, 0, i)))
13676 && (GET_CODE (shift_rtx) == ASHIFT
13677 || GET_CODE (shift_rtx) == LSHIFTRT
13678 || GET_CODE (shift_rtx) == ASHIFTRT
13679 || GET_CODE (shift_rtx) == ROTATE
13680 || GET_CODE (shift_rtx) == ROTATERT))
13682 rtx shift_count = XEXP (shift_rtx, 1);
13684 /* Return true if shift count is dest of SET_BODY. */
13685 if (REG_P (shift_count)
13686 && true_regnum (set_dest) == true_regnum (shift_count))
13693 /* Return true if destination reg of SET_INSN is shift count of
13697 ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
13699 return ix86_dep_by_shift_count_body (PATTERN (set_insn),
13700 PATTERN (use_insn));
13703 /* Return TRUE or FALSE depending on whether the unary operator meets the
13704 appropriate constraints. */
13707 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13708 enum machine_mode mode ATTRIBUTE_UNUSED,
13709 rtx operands[2] ATTRIBUTE_UNUSED)
13711 /* If one of operands is memory, source and destination must match. */
13712 if ((MEM_P (operands[0])
13713 || MEM_P (operands[1]))
13714 && ! rtx_equal_p (operands[0], operands[1]))
13719 /* Post-reload splitter for converting an SF or DFmode value in an
13720 SSE register into an unsigned SImode. */
13723 ix86_split_convert_uns_si_sse (rtx operands[])
13725 enum machine_mode vecmode;
13726 rtx value, large, zero_or_two31, input, two31, x;
13728 large = operands[1];
13729 zero_or_two31 = operands[2];
13730 input = operands[3];
13731 two31 = operands[4];
13732 vecmode = GET_MODE (large);
13733 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13735 /* Load up the value into the low element. We must ensure that the other
13736 elements are valid floats -- zero is the easiest such value. */
13739 if (vecmode == V4SFmode)
13740 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13742 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13746 input = gen_rtx_REG (vecmode, REGNO (input));
13747 emit_move_insn (value, CONST0_RTX (vecmode));
13748 if (vecmode == V4SFmode)
13749 emit_insn (gen_sse_movss (value, value, input));
13751 emit_insn (gen_sse2_movsd (value, value, input));
13754 emit_move_insn (large, two31);
13755 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13757 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13758 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13760 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13761 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13763 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13764 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13766 large = gen_rtx_REG (V4SImode, REGNO (large));
13767 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13769 x = gen_rtx_REG (V4SImode, REGNO (value));
13770 if (vecmode == V4SFmode)
13771 emit_insn (gen_sse2_cvttps2dq (x, value));
13773 emit_insn (gen_sse2_cvttpd2dq (x, value));
13776 emit_insn (gen_xorv4si3 (value, value, large));
13779 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13780 Expects the 64-bit DImode to be supplied in a pair of integral
13781 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13782 -mfpmath=sse, !optimize_size only. */
13785 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13787 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13788 rtx int_xmm, fp_xmm;
13789 rtx biases, exponents;
13792 int_xmm = gen_reg_rtx (V4SImode);
13793 if (TARGET_INTER_UNIT_MOVES)
13794 emit_insn (gen_movdi_to_sse (int_xmm, input));
13795 else if (TARGET_SSE_SPLIT_REGS)
13797 emit_clobber (int_xmm);
13798 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13802 x = gen_reg_rtx (V2DImode);
13803 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13804 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13807 x = gen_rtx_CONST_VECTOR (V4SImode,
13808 gen_rtvec (4, GEN_INT (0x43300000UL),
13809 GEN_INT (0x45300000UL),
13810 const0_rtx, const0_rtx));
13811 exponents = validize_mem (force_const_mem (V4SImode, x));
13813 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13814 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13816 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13817 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13818 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13819 (0x1.0p84 + double(fp_value_hi_xmm)).
13820 Note these exponents differ by 32. */
13822 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13824 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13825 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13826 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13827 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13828 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13829 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13830 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13831 biases = validize_mem (force_const_mem (V2DFmode, biases));
13832 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13834 /* Add the upper and lower DFmode values together. */
13836 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13839 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13840 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13841 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13844 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13847 /* Not used, but eases macroization of patterns. */
13849 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13850 rtx input ATTRIBUTE_UNUSED)
13852 gcc_unreachable ();
13855 /* Convert an unsigned SImode value into a DFmode. Only currently used
13856 for SSE, but applicable anywhere. */
13859 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13861 REAL_VALUE_TYPE TWO31r;
13864 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13865 NULL, 1, OPTAB_DIRECT);
13867 fp = gen_reg_rtx (DFmode);
13868 emit_insn (gen_floatsidf2 (fp, x));
13870 real_ldexp (&TWO31r, &dconst1, 31);
13871 x = const_double_from_real_value (TWO31r, DFmode);
13873 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13875 emit_move_insn (target, x);
13878 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13879 32-bit mode; otherwise we have a direct convert instruction. */
13882 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13884 REAL_VALUE_TYPE TWO32r;
13885 rtx fp_lo, fp_hi, x;
13887 fp_lo = gen_reg_rtx (DFmode);
13888 fp_hi = gen_reg_rtx (DFmode);
13890 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13892 real_ldexp (&TWO32r, &dconst1, 32);
13893 x = const_double_from_real_value (TWO32r, DFmode);
13894 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13896 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13898 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13901 emit_move_insn (target, x);
13904 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13905 For x86_32, -mfpmath=sse, !optimize_size only. */
13907 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13909 REAL_VALUE_TYPE ONE16r;
13910 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13912 real_ldexp (&ONE16r, &dconst1, 16);
13913 x = const_double_from_real_value (ONE16r, SFmode);
13914 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13915 NULL, 0, OPTAB_DIRECT);
13916 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13917 NULL, 0, OPTAB_DIRECT);
13918 fp_hi = gen_reg_rtx (SFmode);
13919 fp_lo = gen_reg_rtx (SFmode);
13920 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13921 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13922 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13924 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13926 if (!rtx_equal_p (target, fp_hi))
13927 emit_move_insn (target, fp_hi);
13930 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
13931 then replicate the value for all elements of the vector
13935 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13942 v = gen_rtvec (4, value, value, value, value);
13943 return gen_rtx_CONST_VECTOR (V4SImode, v);
13947 v = gen_rtvec (2, value, value);
13948 return gen_rtx_CONST_VECTOR (V2DImode, v);
13952 v = gen_rtvec (4, value, value, value, value);
13954 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13955 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13956 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13960 v = gen_rtvec (2, value, value);
13962 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13963 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13966 gcc_unreachable ();
13970 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13971 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13972 for an SSE register. If VECT is true, then replicate the mask for
13973 all elements of the vector register. If INVERT is true, then create
13974 a mask excluding the sign bit. */
13977 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13979 enum machine_mode vec_mode, imode;
13980 HOST_WIDE_INT hi, lo;
13985 /* Find the sign bit, sign extended to 2*HWI. */
13991 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13992 lo = 0x80000000, hi = lo < 0;
13998 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13999 if (HOST_BITS_PER_WIDE_INT >= 64)
14000 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
14002 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
14007 vec_mode = VOIDmode;
14008 if (HOST_BITS_PER_WIDE_INT >= 64)
14011 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
14018 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
14022 lo = ~lo, hi = ~hi;
14028 mask = immed_double_const (lo, hi, imode);
14030 vec = gen_rtvec (2, v, mask);
14031 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
14032 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
14039 gcc_unreachable ();
14043 lo = ~lo, hi = ~hi;
14045 /* Force this value into the low part of a fp vector constant. */
14046 mask = immed_double_const (lo, hi, imode);
14047 mask = gen_lowpart (mode, mask);
14049 if (vec_mode == VOIDmode)
14050 return force_reg (mode, mask);
14052 v = ix86_build_const_vector (mode, vect, mask);
14053 return force_reg (vec_mode, v);
14056 /* Generate code for floating point ABS or NEG. */
14059 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
14062 rtx mask, set, use, clob, dst, src;
14063 bool use_sse = false;
14064 bool vector_mode = VECTOR_MODE_P (mode);
14065 enum machine_mode elt_mode = mode;
14069 elt_mode = GET_MODE_INNER (mode);
14072 else if (mode == TFmode)
14074 else if (TARGET_SSE_MATH)
14075 use_sse = SSE_FLOAT_MODE_P (mode);
14077 /* NEG and ABS performed with SSE use bitwise mask operations.
14078 Create the appropriate mask now. */
14080 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
14089 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
14090 set = gen_rtx_SET (VOIDmode, dst, set);
14095 set = gen_rtx_fmt_e (code, mode, src);
14096 set = gen_rtx_SET (VOIDmode, dst, set);
14099 use = gen_rtx_USE (VOIDmode, mask);
14100 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
14101 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14102 gen_rtvec (3, set, use, clob)));
14109 /* Expand a copysign operation. Special case operand 0 being a constant. */
14112 ix86_expand_copysign (rtx operands[])
14114 enum machine_mode mode;
14115 rtx dest, op0, op1, mask, nmask;
14117 dest = operands[0];
14121 mode = GET_MODE (dest);
14123 if (GET_CODE (op0) == CONST_DOUBLE)
14125 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
14127 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
14128 op0 = simplify_unary_operation (ABS, mode, op0, mode);
14130 if (mode == SFmode || mode == DFmode)
14132 enum machine_mode vmode;
14134 vmode = mode == SFmode ? V4SFmode : V2DFmode;
14136 if (op0 == CONST0_RTX (mode))
14137 op0 = CONST0_RTX (vmode);
14140 rtx v = ix86_build_const_vector (mode, false, op0);
14142 op0 = force_reg (vmode, v);
14145 else if (op0 != CONST0_RTX (mode))
14146 op0 = force_reg (mode, op0);
14148 mask = ix86_build_signbit_mask (mode, 0, 0);
14150 if (mode == SFmode)
14151 copysign_insn = gen_copysignsf3_const;
14152 else if (mode == DFmode)
14153 copysign_insn = gen_copysigndf3_const;
14155 copysign_insn = gen_copysigntf3_const;
14157 emit_insn (copysign_insn (dest, op0, op1, mask));
14161 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
14163 nmask = ix86_build_signbit_mask (mode, 0, 1);
14164 mask = ix86_build_signbit_mask (mode, 0, 0);
14166 if (mode == SFmode)
14167 copysign_insn = gen_copysignsf3_var;
14168 else if (mode == DFmode)
14169 copysign_insn = gen_copysigndf3_var;
14171 copysign_insn = gen_copysigntf3_var;
14173 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
14177 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14178 be a constant, and so has already been expanded into a vector constant. */
14181 ix86_split_copysign_const (rtx operands[])
14183 enum machine_mode mode, vmode;
14184 rtx dest, op0, mask, x;
14186 dest = operands[0];
14188 mask = operands[3];
14190 mode = GET_MODE (dest);
14191 vmode = GET_MODE (mask);
14193 dest = simplify_gen_subreg (vmode, dest, mode, 0);
14194 x = gen_rtx_AND (vmode, dest, mask);
14195 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14197 if (op0 != CONST0_RTX (vmode))
14199 x = gen_rtx_IOR (vmode, dest, op0);
14200 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14204 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14205 so we have to do two masks. */
14208 ix86_split_copysign_var (rtx operands[])
14210 enum machine_mode mode, vmode;
14211 rtx dest, scratch, op0, op1, mask, nmask, x;
14213 dest = operands[0];
14214 scratch = operands[1];
14217 nmask = operands[4];
14218 mask = operands[5];
14220 mode = GET_MODE (dest);
14221 vmode = GET_MODE (mask);
14223 if (rtx_equal_p (op0, op1))
14225 /* Shouldn't happen often (it's useless, obviously), but when it does
14226 we'd generate incorrect code if we continue below. */
14227 emit_move_insn (dest, op0);
14231 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
14233 gcc_assert (REGNO (op1) == REGNO (scratch));
14235 x = gen_rtx_AND (vmode, scratch, mask);
14236 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14239 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14240 x = gen_rtx_NOT (vmode, dest);
14241 x = gen_rtx_AND (vmode, x, op0);
14242 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14246 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
14248 x = gen_rtx_AND (vmode, scratch, mask);
14250 else /* alternative 2,4 */
14252 gcc_assert (REGNO (mask) == REGNO (scratch));
14253 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
14254 x = gen_rtx_AND (vmode, scratch, op1);
14256 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14258 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
14260 dest = simplify_gen_subreg (vmode, op0, mode, 0);
14261 x = gen_rtx_AND (vmode, dest, nmask);
14263 else /* alternative 3,4 */
14265 gcc_assert (REGNO (nmask) == REGNO (dest));
14267 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14268 x = gen_rtx_AND (vmode, dest, op0);
14270 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14273 x = gen_rtx_IOR (vmode, dest, scratch);
14274 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14277 /* Return TRUE or FALSE depending on whether the first SET in INSN
14278 has source and destination with matching CC modes, and that the
14279 CC mode is at least as constrained as REQ_MODE. */
14282 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
14285 enum machine_mode set_mode;
14287 set = PATTERN (insn);
14288 if (GET_CODE (set) == PARALLEL)
14289 set = XVECEXP (set, 0, 0);
14290 gcc_assert (GET_CODE (set) == SET);
14291 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
14293 set_mode = GET_MODE (SET_DEST (set));
14297 if (req_mode != CCNOmode
14298 && (req_mode != CCmode
14299 || XEXP (SET_SRC (set), 1) != const0_rtx))
14303 if (req_mode == CCGCmode)
14307 if (req_mode == CCGOCmode || req_mode == CCNOmode)
14311 if (req_mode == CCZmode)
14322 gcc_unreachable ();
14325 return (GET_MODE (SET_SRC (set)) == set_mode);
14328 /* Generate insn patterns to do an integer compare of OPERANDS. */
14331 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
14333 enum machine_mode cmpmode;
14336 cmpmode = SELECT_CC_MODE (code, op0, op1);
14337 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
14339 /* This is very simple, but making the interface the same as in the
14340 FP case makes the rest of the code easier. */
14341 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
14342 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
14344 /* Return the test that should be put into the flags user, i.e.
14345 the bcc, scc, or cmov instruction. */
14346 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
14349 /* Figure out whether to use ordered or unordered fp comparisons.
14350 Return the appropriate mode to use. */
14353 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
14355 /* ??? In order to make all comparisons reversible, we do all comparisons
14356 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14357 all forms trapping and nontrapping comparisons, we can make inequality
14358 comparisons trapping again, since it results in better code when using
14359 FCOM based compares. */
14360 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
14364 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
14366 enum machine_mode mode = GET_MODE (op0);
14368 if (SCALAR_FLOAT_MODE_P (mode))
14370 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14371 return ix86_fp_compare_mode (code);
14376 /* Only zero flag is needed. */
14377 case EQ: /* ZF=0 */
14378 case NE: /* ZF!=0 */
14380 /* Codes needing carry flag. */
14381 case GEU: /* CF=0 */
14382 case LTU: /* CF=1 */
14383 /* Detect overflow checks. They need just the carry flag. */
14384 if (GET_CODE (op0) == PLUS
14385 && rtx_equal_p (op1, XEXP (op0, 0)))
14389 case GTU: /* CF=0 & ZF=0 */
14390 case LEU: /* CF=1 | ZF=1 */
14391 /* Detect overflow checks. They need just the carry flag. */
14392 if (GET_CODE (op0) == MINUS
14393 && rtx_equal_p (op1, XEXP (op0, 0)))
14397 /* Codes possibly doable only with sign flag when
14398 comparing against zero. */
14399 case GE: /* SF=OF or SF=0 */
14400 case LT: /* SF<>OF or SF=1 */
14401 if (op1 == const0_rtx)
14404 /* For other cases Carry flag is not required. */
14406 /* Codes doable only with sign flag when comparing
14407 against zero, but we miss jump instruction for it
14408 so we need to use relational tests against overflow
14409 that thus needs to be zero. */
14410 case GT: /* ZF=0 & SF=OF */
14411 case LE: /* ZF=1 | SF<>OF */
14412 if (op1 == const0_rtx)
14416 /* strcmp pattern do (use flags) and combine may ask us for proper
14421 gcc_unreachable ();
14425 /* Return the fixed registers used for condition codes. */
14428 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
14435 /* If two condition code modes are compatible, return a condition code
14436 mode which is compatible with both. Otherwise, return
14439 static enum machine_mode
14440 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
14445 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
14448 if ((m1 == CCGCmode && m2 == CCGOCmode)
14449 || (m1 == CCGOCmode && m2 == CCGCmode))
14455 gcc_unreachable ();
14485 /* These are only compatible with themselves, which we already
14492 /* Return a comparison we can do and that it is equivalent to
14493 swap_condition (code) apart possibly from orderedness.
14494 But, never change orderedness if TARGET_IEEE_FP, returning
14495 UNKNOWN in that case if necessary. */
14497 static enum rtx_code
14498 ix86_fp_swap_condition (enum rtx_code code)
14502 case GT: /* GTU - CF=0 & ZF=0 */
14503 return TARGET_IEEE_FP ? UNKNOWN : UNLT;
14504 case GE: /* GEU - CF=0 */
14505 return TARGET_IEEE_FP ? UNKNOWN : UNLE;
14506 case UNLT: /* LTU - CF=1 */
14507 return TARGET_IEEE_FP ? UNKNOWN : GT;
14508 case UNLE: /* LEU - CF=1 | ZF=1 */
14509 return TARGET_IEEE_FP ? UNKNOWN : GE;
14511 return swap_condition (code);
14515 /* Return cost of comparison CODE using the best strategy for performance.
14516 All following functions do use number of instructions as a cost metrics.
14517 In future this should be tweaked to compute bytes for optimize_size and
14518 take into account performance of various instructions on various CPUs. */
14521 ix86_fp_comparison_cost (enum rtx_code code)
14525 /* The cost of code using bit-twiddling on %ah. */
14542 arith_cost = TARGET_IEEE_FP ? 5 : 4;
14546 arith_cost = TARGET_IEEE_FP ? 6 : 4;
14549 gcc_unreachable ();
14552 switch (ix86_fp_comparison_strategy (code))
14554 case IX86_FPCMP_COMI:
14555 return arith_cost > 4 ? 3 : 2;
14556 case IX86_FPCMP_SAHF:
14557 return arith_cost > 4 ? 4 : 3;
14563 /* Return strategy to use for floating-point. We assume that fcomi is always
14564 preferrable where available, since that is also true when looking at size
14565 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
14567 enum ix86_fpcmp_strategy
14568 ix86_fp_comparison_strategy (enum rtx_code code ATTRIBUTE_UNUSED)
14570 /* Do fcomi/sahf based test when profitable. */
14573 return IX86_FPCMP_COMI;
14575 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_function_for_size_p (cfun)))
14576 return IX86_FPCMP_SAHF;
14578 return IX86_FPCMP_ARITH;
14581 /* Swap, force into registers, or otherwise massage the two operands
14582 to a fp comparison. The operands are updated in place; the new
14583 comparison code is returned. */
14585 static enum rtx_code
14586 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
14588 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
14589 rtx op0 = *pop0, op1 = *pop1;
14590 enum machine_mode op_mode = GET_MODE (op0);
14591 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
14593 /* All of the unordered compare instructions only work on registers.
14594 The same is true of the fcomi compare instructions. The XFmode
14595 compare instructions require registers except when comparing
14596 against zero or when converting operand 1 from fixed point to
14600 && (fpcmp_mode == CCFPUmode
14601 || (op_mode == XFmode
14602 && ! (standard_80387_constant_p (op0) == 1
14603 || standard_80387_constant_p (op1) == 1)
14604 && GET_CODE (op1) != FLOAT)
14605 || ix86_fp_comparison_strategy (code) == IX86_FPCMP_COMI))
14607 op0 = force_reg (op_mode, op0);
14608 op1 = force_reg (op_mode, op1);
14612 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14613 things around if they appear profitable, otherwise force op0
14614 into a register. */
14616 if (standard_80387_constant_p (op0) == 0
14618 && ! (standard_80387_constant_p (op1) == 0
14621 enum rtx_code new_code = ix86_fp_swap_condition (code);
14622 if (new_code != UNKNOWN)
14625 tmp = op0, op0 = op1, op1 = tmp;
14631 op0 = force_reg (op_mode, op0);
14633 if (CONSTANT_P (op1))
14635 int tmp = standard_80387_constant_p (op1);
14637 op1 = validize_mem (force_const_mem (op_mode, op1));
14641 op1 = force_reg (op_mode, op1);
14644 op1 = force_reg (op_mode, op1);
14648 /* Try to rearrange the comparison to make it cheaper. */
14649 if (ix86_fp_comparison_cost (code)
14650 > ix86_fp_comparison_cost (swap_condition (code))
14651 && (REG_P (op1) || can_create_pseudo_p ()))
14654 tmp = op0, op0 = op1, op1 = tmp;
14655 code = swap_condition (code);
14657 op0 = force_reg (op_mode, op0);
14665 /* Convert comparison codes we use to represent FP comparison to integer
14666 code that will result in proper branch. Return UNKNOWN if no such code
14670 ix86_fp_compare_code_to_integer (enum rtx_code code)
14699 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14702 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch)
14704 enum machine_mode fpcmp_mode, intcmp_mode;
14707 fpcmp_mode = ix86_fp_compare_mode (code);
14708 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14710 /* Do fcomi/sahf based test when profitable. */
14711 switch (ix86_fp_comparison_strategy (code))
14713 case IX86_FPCMP_COMI:
14714 intcmp_mode = fpcmp_mode;
14715 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14716 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14721 case IX86_FPCMP_SAHF:
14722 intcmp_mode = fpcmp_mode;
14723 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14724 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14728 scratch = gen_reg_rtx (HImode);
14729 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14730 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14733 case IX86_FPCMP_ARITH:
14734 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14735 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14736 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14738 scratch = gen_reg_rtx (HImode);
14739 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14741 /* In the unordered case, we have to check C2 for NaN's, which
14742 doesn't happen to work out to anything nice combination-wise.
14743 So do some bit twiddling on the value we've got in AH to come
14744 up with an appropriate set of condition codes. */
14746 intcmp_mode = CCNOmode;
14751 if (code == GT || !TARGET_IEEE_FP)
14753 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14758 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14759 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14760 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14761 intcmp_mode = CCmode;
14767 if (code == LT && TARGET_IEEE_FP)
14769 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14770 emit_insn (gen_cmpqi_ext_3 (scratch, const1_rtx));
14771 intcmp_mode = CCmode;
14776 emit_insn (gen_testqi_ext_ccno_0 (scratch, const1_rtx));
14782 if (code == GE || !TARGET_IEEE_FP)
14784 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14789 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14790 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch, const1_rtx));
14796 if (code == LE && TARGET_IEEE_FP)
14798 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14799 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14800 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14801 intcmp_mode = CCmode;
14806 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14812 if (code == EQ && TARGET_IEEE_FP)
14814 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14815 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14816 intcmp_mode = CCmode;
14821 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14827 if (code == NE && TARGET_IEEE_FP)
14829 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14830 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14836 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14842 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14846 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14851 gcc_unreachable ();
14859 /* Return the test that should be put into the flags user, i.e.
14860 the bcc, scc, or cmov instruction. */
14861 return gen_rtx_fmt_ee (code, VOIDmode,
14862 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14867 ix86_expand_compare (enum rtx_code code)
14870 op0 = ix86_compare_op0;
14871 op1 = ix86_compare_op1;
14873 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC)
14874 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_op0, ix86_compare_op1);
14876 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14878 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14879 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
14882 ret = ix86_expand_int_compare (code, op0, op1);
14888 ix86_expand_branch (enum rtx_code code, rtx label)
14892 switch (GET_MODE (ix86_compare_op0))
14901 tmp = ix86_expand_compare (code);
14902 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14903 gen_rtx_LABEL_REF (VOIDmode, label),
14905 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14912 /* Expand DImode branch into multiple compare+branch. */
14914 rtx lo[2], hi[2], label2;
14915 enum rtx_code code1, code2, code3;
14916 enum machine_mode submode;
14918 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14920 tmp = ix86_compare_op0;
14921 ix86_compare_op0 = ix86_compare_op1;
14922 ix86_compare_op1 = tmp;
14923 code = swap_condition (code);
14925 if (GET_MODE (ix86_compare_op0) == DImode)
14927 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14928 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14933 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14934 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14938 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14939 avoid two branches. This costs one extra insn, so disable when
14940 optimizing for size. */
14942 if ((code == EQ || code == NE)
14943 && (!optimize_insn_for_size_p ()
14944 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14949 if (hi[1] != const0_rtx)
14950 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14951 NULL_RTX, 0, OPTAB_WIDEN);
14954 if (lo[1] != const0_rtx)
14955 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14956 NULL_RTX, 0, OPTAB_WIDEN);
14958 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14959 NULL_RTX, 0, OPTAB_WIDEN);
14961 ix86_compare_op0 = tmp;
14962 ix86_compare_op1 = const0_rtx;
14963 ix86_expand_branch (code, label);
14967 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14968 op1 is a constant and the low word is zero, then we can just
14969 examine the high word. Similarly for low word -1 and
14970 less-or-equal-than or greater-than. */
14972 if (CONST_INT_P (hi[1]))
14975 case LT: case LTU: case GE: case GEU:
14976 if (lo[1] == const0_rtx)
14978 ix86_compare_op0 = hi[0];
14979 ix86_compare_op1 = hi[1];
14980 ix86_expand_branch (code, label);
14984 case LE: case LEU: case GT: case GTU:
14985 if (lo[1] == constm1_rtx)
14987 ix86_compare_op0 = hi[0];
14988 ix86_compare_op1 = hi[1];
14989 ix86_expand_branch (code, label);
14997 /* Otherwise, we need two or three jumps. */
14999 label2 = gen_label_rtx ();
15002 code2 = swap_condition (code);
15003 code3 = unsigned_condition (code);
15007 case LT: case GT: case LTU: case GTU:
15010 case LE: code1 = LT; code2 = GT; break;
15011 case GE: code1 = GT; code2 = LT; break;
15012 case LEU: code1 = LTU; code2 = GTU; break;
15013 case GEU: code1 = GTU; code2 = LTU; break;
15015 case EQ: code1 = UNKNOWN; code2 = NE; break;
15016 case NE: code2 = UNKNOWN; break;
15019 gcc_unreachable ();
15024 * if (hi(a) < hi(b)) goto true;
15025 * if (hi(a) > hi(b)) goto false;
15026 * if (lo(a) < lo(b)) goto true;
15030 ix86_compare_op0 = hi[0];
15031 ix86_compare_op1 = hi[1];
15033 if (code1 != UNKNOWN)
15034 ix86_expand_branch (code1, label);
15035 if (code2 != UNKNOWN)
15036 ix86_expand_branch (code2, label2);
15038 ix86_compare_op0 = lo[0];
15039 ix86_compare_op1 = lo[1];
15040 ix86_expand_branch (code3, label);
15042 if (code2 != UNKNOWN)
15043 emit_label (label2);
15048 /* If we have already emitted a compare insn, go straight to simple.
15049 ix86_expand_compare won't emit anything if ix86_compare_emitted
15051 gcc_assert (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC);
15056 /* Split branch based on floating point condition. */
15058 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
15059 rtx target1, rtx target2, rtx tmp, rtx pushed)
15064 if (target2 != pc_rtx)
15067 code = reverse_condition_maybe_unordered (code);
15072 condition = ix86_expand_fp_compare (code, op1, op2,
15075 /* Remove pushed operand from stack. */
15077 ix86_free_from_memory (GET_MODE (pushed));
15079 i = emit_jump_insn (gen_rtx_SET
15081 gen_rtx_IF_THEN_ELSE (VOIDmode,
15082 condition, target1, target2)));
15083 if (split_branch_probability >= 0)
15084 add_reg_note (i, REG_BR_PROB, GEN_INT (split_branch_probability));
15088 ix86_expand_setcc (enum rtx_code code, rtx dest)
15092 gcc_assert (GET_MODE (dest) == QImode);
15094 ret = ix86_expand_compare (code);
15095 PUT_MODE (ret, QImode);
15096 emit_insn (gen_rtx_SET (VOIDmode, dest, ret));
15099 /* Expand comparison setting or clearing carry flag. Return true when
15100 successful and set pop for the operation. */
15102 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
15104 enum machine_mode mode =
15105 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
15107 /* Do not handle DImode compares that go through special path. */
15108 if (mode == (TARGET_64BIT ? TImode : DImode))
15111 if (SCALAR_FLOAT_MODE_P (mode))
15113 rtx compare_op, compare_seq;
15115 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
15117 /* Shortcut: following common codes never translate
15118 into carry flag compares. */
15119 if (code == EQ || code == NE || code == UNEQ || code == LTGT
15120 || code == ORDERED || code == UNORDERED)
15123 /* These comparisons require zero flag; swap operands so they won't. */
15124 if ((code == GT || code == UNLE || code == LE || code == UNGT)
15125 && !TARGET_IEEE_FP)
15130 code = swap_condition (code);
15133 /* Try to expand the comparison and verify that we end up with
15134 carry flag based comparison. This fails to be true only when
15135 we decide to expand comparison using arithmetic that is not
15136 too common scenario. */
15138 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
15139 compare_seq = get_insns ();
15142 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15143 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15144 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
15146 code = GET_CODE (compare_op);
15148 if (code != LTU && code != GEU)
15151 emit_insn (compare_seq);
15156 if (!INTEGRAL_MODE_P (mode))
15165 /* Convert a==0 into (unsigned)a<1. */
15168 if (op1 != const0_rtx)
15171 code = (code == EQ ? LTU : GEU);
15174 /* Convert a>b into b<a or a>=b-1. */
15177 if (CONST_INT_P (op1))
15179 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
15180 /* Bail out on overflow. We still can swap operands but that
15181 would force loading of the constant into register. */
15182 if (op1 == const0_rtx
15183 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
15185 code = (code == GTU ? GEU : LTU);
15192 code = (code == GTU ? LTU : GEU);
15196 /* Convert a>=0 into (unsigned)a<0x80000000. */
15199 if (mode == DImode || op1 != const0_rtx)
15201 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15202 code = (code == LT ? GEU : LTU);
15206 if (mode == DImode || op1 != constm1_rtx)
15208 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15209 code = (code == LE ? GEU : LTU);
15215 /* Swapping operands may cause constant to appear as first operand. */
15216 if (!nonimmediate_operand (op0, VOIDmode))
15218 if (!can_create_pseudo_p ())
15220 op0 = force_reg (mode, op0);
15222 ix86_compare_op0 = op0;
15223 ix86_compare_op1 = op1;
15224 *pop = ix86_expand_compare (code);
15225 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
15230 ix86_expand_int_movcc (rtx operands[])
15232 enum rtx_code code = GET_CODE (operands[1]), compare_code;
15233 rtx compare_seq, compare_op;
15234 enum machine_mode mode = GET_MODE (operands[0]);
15235 bool sign_bit_compare_p = false;;
15238 ix86_compare_op0 = XEXP (operands[1], 0);
15239 ix86_compare_op1 = XEXP (operands[1], 1);
15240 compare_op = ix86_expand_compare (code);
15241 compare_seq = get_insns ();
15244 compare_code = GET_CODE (compare_op);
15246 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
15247 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
15248 sign_bit_compare_p = true;
15250 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15251 HImode insns, we'd be swallowed in word prefix ops. */
15253 if ((mode != HImode || TARGET_FAST_PREFIX)
15254 && (mode != (TARGET_64BIT ? TImode : DImode))
15255 && CONST_INT_P (operands[2])
15256 && CONST_INT_P (operands[3]))
15258 rtx out = operands[0];
15259 HOST_WIDE_INT ct = INTVAL (operands[2]);
15260 HOST_WIDE_INT cf = INTVAL (operands[3]);
15261 HOST_WIDE_INT diff;
15264 /* Sign bit compares are better done using shifts than we do by using
15266 if (sign_bit_compare_p
15267 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15268 ix86_compare_op1, &compare_op))
15270 /* Detect overlap between destination and compare sources. */
15273 if (!sign_bit_compare_p)
15275 bool fpcmp = false;
15277 compare_code = GET_CODE (compare_op);
15279 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15280 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15283 compare_code = ix86_fp_compare_code_to_integer (compare_code);
15286 /* To simplify rest of code, restrict to the GEU case. */
15287 if (compare_code == LTU)
15289 HOST_WIDE_INT tmp = ct;
15292 compare_code = reverse_condition (compare_code);
15293 code = reverse_condition (code);
15298 PUT_CODE (compare_op,
15299 reverse_condition_maybe_unordered
15300 (GET_CODE (compare_op)));
15302 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15306 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
15307 || reg_overlap_mentioned_p (out, ix86_compare_op1))
15308 tmp = gen_reg_rtx (mode);
15310 if (mode == DImode)
15311 emit_insn (gen_x86_movdicc_0_m1 (tmp, compare_op));
15313 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp),
15318 if (code == GT || code == GE)
15319 code = reverse_condition (code);
15322 HOST_WIDE_INT tmp = ct;
15327 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
15328 ix86_compare_op1, VOIDmode, 0, -1);
15341 tmp = expand_simple_binop (mode, PLUS,
15343 copy_rtx (tmp), 1, OPTAB_DIRECT);
15354 tmp = expand_simple_binop (mode, IOR,
15356 copy_rtx (tmp), 1, OPTAB_DIRECT);
15358 else if (diff == -1 && ct)
15368 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15370 tmp = expand_simple_binop (mode, PLUS,
15371 copy_rtx (tmp), GEN_INT (cf),
15372 copy_rtx (tmp), 1, OPTAB_DIRECT);
15380 * andl cf - ct, dest
15390 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15393 tmp = expand_simple_binop (mode, AND,
15395 gen_int_mode (cf - ct, mode),
15396 copy_rtx (tmp), 1, OPTAB_DIRECT);
15398 tmp = expand_simple_binop (mode, PLUS,
15399 copy_rtx (tmp), GEN_INT (ct),
15400 copy_rtx (tmp), 1, OPTAB_DIRECT);
15403 if (!rtx_equal_p (tmp, out))
15404 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
15406 return 1; /* DONE */
15411 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15414 tmp = ct, ct = cf, cf = tmp;
15417 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15419 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15421 /* We may be reversing unordered compare to normal compare, that
15422 is not valid in general (we may convert non-trapping condition
15423 to trapping one), however on i386 we currently emit all
15424 comparisons unordered. */
15425 compare_code = reverse_condition_maybe_unordered (compare_code);
15426 code = reverse_condition_maybe_unordered (code);
15430 compare_code = reverse_condition (compare_code);
15431 code = reverse_condition (code);
15435 compare_code = UNKNOWN;
15436 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
15437 && CONST_INT_P (ix86_compare_op1))
15439 if (ix86_compare_op1 == const0_rtx
15440 && (code == LT || code == GE))
15441 compare_code = code;
15442 else if (ix86_compare_op1 == constm1_rtx)
15446 else if (code == GT)
15451 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15452 if (compare_code != UNKNOWN
15453 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15454 && (cf == -1 || ct == -1))
15456 /* If lea code below could be used, only optimize
15457 if it results in a 2 insn sequence. */
15459 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15460 || diff == 3 || diff == 5 || diff == 9)
15461 || (compare_code == LT && ct == -1)
15462 || (compare_code == GE && cf == -1))
15465 * notl op1 (if necessary)
15473 code = reverse_condition (code);
15476 out = emit_store_flag (out, code, ix86_compare_op0,
15477 ix86_compare_op1, VOIDmode, 0, -1);
15479 out = expand_simple_binop (mode, IOR,
15481 out, 1, OPTAB_DIRECT);
15482 if (out != operands[0])
15483 emit_move_insn (operands[0], out);
15485 return 1; /* DONE */
15490 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15491 || diff == 3 || diff == 5 || diff == 9)
15492 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15494 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15500 * lea cf(dest*(ct-cf)),dest
15504 * This also catches the degenerate setcc-only case.
15510 out = emit_store_flag (out, code, ix86_compare_op0,
15511 ix86_compare_op1, VOIDmode, 0, 1);
15514 /* On x86_64 the lea instruction operates on Pmode, so we need
15515 to get arithmetics done in proper mode to match. */
15517 tmp = copy_rtx (out);
15521 out1 = copy_rtx (out);
15522 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15526 tmp = gen_rtx_PLUS (mode, tmp, out1);
15532 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15535 if (!rtx_equal_p (tmp, out))
15538 out = force_operand (tmp, copy_rtx (out));
15540 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15542 if (!rtx_equal_p (out, operands[0]))
15543 emit_move_insn (operands[0], copy_rtx (out));
15545 return 1; /* DONE */
15549 * General case: Jumpful:
15550 * xorl dest,dest cmpl op1, op2
15551 * cmpl op1, op2 movl ct, dest
15552 * setcc dest jcc 1f
15553 * decl dest movl cf, dest
15554 * andl (cf-ct),dest 1:
15557 * Size 20. Size 14.
15559 * This is reasonably steep, but branch mispredict costs are
15560 * high on modern cpus, so consider failing only if optimizing
15564 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15565 && BRANCH_COST (optimize_insn_for_speed_p (),
15570 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15575 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15577 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15579 /* We may be reversing unordered compare to normal compare,
15580 that is not valid in general (we may convert non-trapping
15581 condition to trapping one), however on i386 we currently
15582 emit all comparisons unordered. */
15583 code = reverse_condition_maybe_unordered (code);
15587 code = reverse_condition (code);
15588 if (compare_code != UNKNOWN)
15589 compare_code = reverse_condition (compare_code);
15593 if (compare_code != UNKNOWN)
15595 /* notl op1 (if needed)
15600 For x < 0 (resp. x <= -1) there will be no notl,
15601 so if possible swap the constants to get rid of the
15603 True/false will be -1/0 while code below (store flag
15604 followed by decrement) is 0/-1, so the constants need
15605 to be exchanged once more. */
15607 if (compare_code == GE || !cf)
15609 code = reverse_condition (code);
15614 HOST_WIDE_INT tmp = cf;
15619 out = emit_store_flag (out, code, ix86_compare_op0,
15620 ix86_compare_op1, VOIDmode, 0, -1);
15624 out = emit_store_flag (out, code, ix86_compare_op0,
15625 ix86_compare_op1, VOIDmode, 0, 1);
15627 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15628 copy_rtx (out), 1, OPTAB_DIRECT);
15631 out = expand_simple_binop (mode, AND, copy_rtx (out),
15632 gen_int_mode (cf - ct, mode),
15633 copy_rtx (out), 1, OPTAB_DIRECT);
15635 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15636 copy_rtx (out), 1, OPTAB_DIRECT);
15637 if (!rtx_equal_p (out, operands[0]))
15638 emit_move_insn (operands[0], copy_rtx (out));
15640 return 1; /* DONE */
15644 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15646 /* Try a few things more with specific constants and a variable. */
15649 rtx var, orig_out, out, tmp;
15651 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15652 return 0; /* FAIL */
15654 /* If one of the two operands is an interesting constant, load a
15655 constant with the above and mask it in with a logical operation. */
15657 if (CONST_INT_P (operands[2]))
15660 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15661 operands[3] = constm1_rtx, op = and_optab;
15662 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15663 operands[3] = const0_rtx, op = ior_optab;
15665 return 0; /* FAIL */
15667 else if (CONST_INT_P (operands[3]))
15670 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15671 operands[2] = constm1_rtx, op = and_optab;
15672 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15673 operands[2] = const0_rtx, op = ior_optab;
15675 return 0; /* FAIL */
15678 return 0; /* FAIL */
15680 orig_out = operands[0];
15681 tmp = gen_reg_rtx (mode);
15684 /* Recurse to get the constant loaded. */
15685 if (ix86_expand_int_movcc (operands) == 0)
15686 return 0; /* FAIL */
15688 /* Mask in the interesting variable. */
15689 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15691 if (!rtx_equal_p (out, orig_out))
15692 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15694 return 1; /* DONE */
15698 * For comparison with above,
15708 if (! nonimmediate_operand (operands[2], mode))
15709 operands[2] = force_reg (mode, operands[2]);
15710 if (! nonimmediate_operand (operands[3], mode))
15711 operands[3] = force_reg (mode, operands[3]);
15713 if (! register_operand (operands[2], VOIDmode)
15715 || ! register_operand (operands[3], VOIDmode)))
15716 operands[2] = force_reg (mode, operands[2]);
15719 && ! register_operand (operands[3], VOIDmode))
15720 operands[3] = force_reg (mode, operands[3]);
15722 emit_insn (compare_seq);
15723 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15724 gen_rtx_IF_THEN_ELSE (mode,
15725 compare_op, operands[2],
15728 return 1; /* DONE */
15731 /* Swap, force into registers, or otherwise massage the two operands
15732 to an sse comparison with a mask result. Thus we differ a bit from
15733 ix86_prepare_fp_compare_args which expects to produce a flags result.
15735 The DEST operand exists to help determine whether to commute commutative
15736 operators. The POP0/POP1 operands are updated in place. The new
15737 comparison code is returned, or UNKNOWN if not implementable. */
15739 static enum rtx_code
15740 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15741 rtx *pop0, rtx *pop1)
15749 /* We have no LTGT as an operator. We could implement it with
15750 NE & ORDERED, but this requires an extra temporary. It's
15751 not clear that it's worth it. */
15758 /* These are supported directly. */
15765 /* For commutative operators, try to canonicalize the destination
15766 operand to be first in the comparison - this helps reload to
15767 avoid extra moves. */
15768 if (!dest || !rtx_equal_p (dest, *pop1))
15776 /* These are not supported directly. Swap the comparison operands
15777 to transform into something that is supported. */
15781 code = swap_condition (code);
15785 gcc_unreachable ();
15791 /* Detect conditional moves that exactly match min/max operational
15792 semantics. Note that this is IEEE safe, as long as we don't
15793 interchange the operands.
15795 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15796 and TRUE if the operation is successful and instructions are emitted. */
15799 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15800 rtx cmp_op1, rtx if_true, rtx if_false)
15802 enum machine_mode mode;
15808 else if (code == UNGE)
15811 if_true = if_false;
15817 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15819 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15824 mode = GET_MODE (dest);
15826 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15827 but MODE may be a vector mode and thus not appropriate. */
15828 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15830 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15833 if_true = force_reg (mode, if_true);
15834 v = gen_rtvec (2, if_true, if_false);
15835 tmp = gen_rtx_UNSPEC (mode, v, u);
15839 code = is_min ? SMIN : SMAX;
15840 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15843 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15847 /* Expand an sse vector comparison. Return the register with the result. */
15850 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15851 rtx op_true, rtx op_false)
15853 enum machine_mode mode = GET_MODE (dest);
15856 cmp_op0 = force_reg (mode, cmp_op0);
15857 if (!nonimmediate_operand (cmp_op1, mode))
15858 cmp_op1 = force_reg (mode, cmp_op1);
15861 || reg_overlap_mentioned_p (dest, op_true)
15862 || reg_overlap_mentioned_p (dest, op_false))
15863 dest = gen_reg_rtx (mode);
15865 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15866 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15871 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15872 operations. This is used for both scalar and vector conditional moves. */
15875 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15877 enum machine_mode mode = GET_MODE (dest);
15880 if (op_false == CONST0_RTX (mode))
15882 op_true = force_reg (mode, op_true);
15883 x = gen_rtx_AND (mode, cmp, op_true);
15884 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15886 else if (op_true == CONST0_RTX (mode))
15888 op_false = force_reg (mode, op_false);
15889 x = gen_rtx_NOT (mode, cmp);
15890 x = gen_rtx_AND (mode, x, op_false);
15891 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15895 op_true = force_reg (mode, op_true);
15896 op_false = force_reg (mode, op_false);
15898 t2 = gen_reg_rtx (mode);
15900 t3 = gen_reg_rtx (mode);
15904 x = gen_rtx_AND (mode, op_true, cmp);
15905 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15907 x = gen_rtx_NOT (mode, cmp);
15908 x = gen_rtx_AND (mode, x, op_false);
15909 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15911 x = gen_rtx_IOR (mode, t3, t2);
15912 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15916 /* Expand a floating-point conditional move. Return true if successful. */
15919 ix86_expand_fp_movcc (rtx operands[])
15921 enum machine_mode mode = GET_MODE (operands[0]);
15922 enum rtx_code code = GET_CODE (operands[1]);
15923 rtx tmp, compare_op;
15925 ix86_compare_op0 = XEXP (operands[1], 0);
15926 ix86_compare_op1 = XEXP (operands[1], 1);
15927 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15929 enum machine_mode cmode;
15931 /* Since we've no cmove for sse registers, don't force bad register
15932 allocation just to gain access to it. Deny movcc when the
15933 comparison mode doesn't match the move mode. */
15934 cmode = GET_MODE (ix86_compare_op0);
15935 if (cmode == VOIDmode)
15936 cmode = GET_MODE (ix86_compare_op1);
15940 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15942 &ix86_compare_op1);
15943 if (code == UNKNOWN)
15946 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15947 ix86_compare_op1, operands[2],
15951 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15952 ix86_compare_op1, operands[2], operands[3]);
15953 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15957 /* The floating point conditional move instructions don't directly
15958 support conditions resulting from a signed integer comparison. */
15960 compare_op = ix86_expand_compare (code);
15961 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15963 tmp = gen_reg_rtx (QImode);
15964 ix86_expand_setcc (code, tmp);
15966 ix86_compare_op0 = tmp;
15967 ix86_compare_op1 = const0_rtx;
15968 compare_op = ix86_expand_compare (code);
15971 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15972 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15973 operands[2], operands[3])));
15978 /* Expand a floating-point vector conditional move; a vcond operation
15979 rather than a movcc operation. */
15982 ix86_expand_fp_vcond (rtx operands[])
15984 enum rtx_code code = GET_CODE (operands[3]);
15987 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15988 &operands[4], &operands[5]);
15989 if (code == UNKNOWN)
15992 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15993 operands[5], operands[1], operands[2]))
15996 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15997 operands[1], operands[2]);
15998 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
16002 /* Expand a signed/unsigned integral vector conditional move. */
16005 ix86_expand_int_vcond (rtx operands[])
16007 enum machine_mode mode = GET_MODE (operands[0]);
16008 enum rtx_code code = GET_CODE (operands[3]);
16009 bool negate = false;
16012 cop0 = operands[4];
16013 cop1 = operands[5];
16015 /* Canonicalize the comparison to EQ, GT, GTU. */
16026 code = reverse_condition (code);
16032 code = reverse_condition (code);
16038 code = swap_condition (code);
16039 x = cop0, cop0 = cop1, cop1 = x;
16043 gcc_unreachable ();
16046 /* Only SSE4.1/SSE4.2 supports V2DImode. */
16047 if (mode == V2DImode)
16052 /* SSE4.1 supports EQ. */
16053 if (!TARGET_SSE4_1)
16059 /* SSE4.2 supports GT/GTU. */
16060 if (!TARGET_SSE4_2)
16065 gcc_unreachable ();
16069 /* Unsigned parallel compare is not supported by the hardware. Play some
16070 tricks to turn this into a signed comparison against 0. */
16073 cop0 = force_reg (mode, cop0);
16082 /* Perform a parallel modulo subtraction. */
16083 t1 = gen_reg_rtx (mode);
16084 emit_insn ((mode == V4SImode
16086 : gen_subv2di3) (t1, cop0, cop1));
16088 /* Extract the original sign bit of op0. */
16089 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
16091 t2 = gen_reg_rtx (mode);
16092 emit_insn ((mode == V4SImode
16094 : gen_andv2di3) (t2, cop0, mask));
16096 /* XOR it back into the result of the subtraction. This results
16097 in the sign bit set iff we saw unsigned underflow. */
16098 x = gen_reg_rtx (mode);
16099 emit_insn ((mode == V4SImode
16101 : gen_xorv2di3) (x, t1, t2));
16109 /* Perform a parallel unsigned saturating subtraction. */
16110 x = gen_reg_rtx (mode);
16111 emit_insn (gen_rtx_SET (VOIDmode, x,
16112 gen_rtx_US_MINUS (mode, cop0, cop1)));
16119 gcc_unreachable ();
16123 cop1 = CONST0_RTX (mode);
16126 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
16127 operands[1+negate], operands[2-negate]);
16129 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
16130 operands[2-negate]);
16134 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16135 true if we should do zero extension, else sign extension. HIGH_P is
16136 true if we want the N/2 high elements, else the low elements. */
16139 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16141 enum machine_mode imode = GET_MODE (operands[1]);
16142 rtx (*unpack)(rtx, rtx, rtx);
16149 unpack = gen_vec_interleave_highv16qi;
16151 unpack = gen_vec_interleave_lowv16qi;
16155 unpack = gen_vec_interleave_highv8hi;
16157 unpack = gen_vec_interleave_lowv8hi;
16161 unpack = gen_vec_interleave_highv4si;
16163 unpack = gen_vec_interleave_lowv4si;
16166 gcc_unreachable ();
16169 dest = gen_lowpart (imode, operands[0]);
16172 se = force_reg (imode, CONST0_RTX (imode));
16174 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
16175 operands[1], pc_rtx, pc_rtx);
16177 emit_insn (unpack (dest, operands[1], se));
16180 /* This function performs the same task as ix86_expand_sse_unpack,
16181 but with SSE4.1 instructions. */
16184 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16186 enum machine_mode imode = GET_MODE (operands[1]);
16187 rtx (*unpack)(rtx, rtx);
16194 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
16196 unpack = gen_sse4_1_extendv8qiv8hi2;
16200 unpack = gen_sse4_1_zero_extendv4hiv4si2;
16202 unpack = gen_sse4_1_extendv4hiv4si2;
16206 unpack = gen_sse4_1_zero_extendv2siv2di2;
16208 unpack = gen_sse4_1_extendv2siv2di2;
16211 gcc_unreachable ();
16214 dest = operands[0];
16217 /* Shift higher 8 bytes to lower 8 bytes. */
16218 src = gen_reg_rtx (imode);
16219 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
16220 gen_lowpart (TImode, operands[1]),
16226 emit_insn (unpack (dest, src));
16229 /* Expand conditional increment or decrement using adb/sbb instructions.
16230 The default case using setcc followed by the conditional move can be
16231 done by generic code. */
16233 ix86_expand_int_addcc (rtx operands[])
16235 enum rtx_code code = GET_CODE (operands[1]);
16236 rtx (*insn)(rtx, rtx, rtx, rtx);
16238 rtx val = const0_rtx;
16239 bool fpcmp = false;
16240 enum machine_mode mode = GET_MODE (operands[0]);
16242 ix86_compare_op0 = XEXP (operands[1], 0);
16243 ix86_compare_op1 = XEXP (operands[1], 1);
16244 if (operands[3] != const1_rtx
16245 && operands[3] != constm1_rtx)
16247 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16248 ix86_compare_op1, &compare_op))
16250 code = GET_CODE (compare_op);
16252 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16253 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16256 code = ix86_fp_compare_code_to_integer (code);
16263 PUT_CODE (compare_op,
16264 reverse_condition_maybe_unordered
16265 (GET_CODE (compare_op)));
16267 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16269 PUT_MODE (compare_op, mode);
16271 /* Construct either adc or sbb insn. */
16272 if ((code == LTU) == (operands[3] == constm1_rtx))
16274 switch (GET_MODE (operands[0]))
16277 insn = gen_subqi3_carry;
16280 insn = gen_subhi3_carry;
16283 insn = gen_subsi3_carry;
16286 insn = gen_subdi3_carry;
16289 gcc_unreachable ();
16294 switch (GET_MODE (operands[0]))
16297 insn = gen_addqi3_carry;
16300 insn = gen_addhi3_carry;
16303 insn = gen_addsi3_carry;
16306 insn = gen_adddi3_carry;
16309 gcc_unreachable ();
16312 emit_insn (insn (operands[0], operands[2], val, compare_op));
16314 return 1; /* DONE */
16318 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16319 works for floating pointer parameters and nonoffsetable memories.
16320 For pushes, it returns just stack offsets; the values will be saved
16321 in the right order. Maximally three parts are generated. */
16324 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16329 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16331 size = (GET_MODE_SIZE (mode) + 4) / 8;
16333 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16334 gcc_assert (size >= 2 && size <= 4);
16336 /* Optimize constant pool reference to immediates. This is used by fp
16337 moves, that force all constants to memory to allow combining. */
16338 if (MEM_P (operand) && MEM_READONLY_P (operand))
16340 rtx tmp = maybe_get_pool_constant (operand);
16345 if (MEM_P (operand) && !offsettable_memref_p (operand))
16347 /* The only non-offsetable memories we handle are pushes. */
16348 int ok = push_operand (operand, VOIDmode);
16352 operand = copy_rtx (operand);
16353 PUT_MODE (operand, Pmode);
16354 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16358 if (GET_CODE (operand) == CONST_VECTOR)
16360 enum machine_mode imode = int_mode_for_mode (mode);
16361 /* Caution: if we looked through a constant pool memory above,
16362 the operand may actually have a different mode now. That's
16363 ok, since we want to pun this all the way back to an integer. */
16364 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16365 gcc_assert (operand != NULL);
16371 if (mode == DImode)
16372 split_di (&operand, 1, &parts[0], &parts[1]);
16377 if (REG_P (operand))
16379 gcc_assert (reload_completed);
16380 for (i = 0; i < size; i++)
16381 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16383 else if (offsettable_memref_p (operand))
16385 operand = adjust_address (operand, SImode, 0);
16386 parts[0] = operand;
16387 for (i = 1; i < size; i++)
16388 parts[i] = adjust_address (operand, SImode, 4 * i);
16390 else if (GET_CODE (operand) == CONST_DOUBLE)
16395 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16399 real_to_target (l, &r, mode);
16400 parts[3] = gen_int_mode (l[3], SImode);
16401 parts[2] = gen_int_mode (l[2], SImode);
16404 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16405 parts[2] = gen_int_mode (l[2], SImode);
16408 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16411 gcc_unreachable ();
16413 parts[1] = gen_int_mode (l[1], SImode);
16414 parts[0] = gen_int_mode (l[0], SImode);
16417 gcc_unreachable ();
16422 if (mode == TImode)
16423 split_ti (&operand, 1, &parts[0], &parts[1]);
16424 if (mode == XFmode || mode == TFmode)
16426 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16427 if (REG_P (operand))
16429 gcc_assert (reload_completed);
16430 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16431 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16433 else if (offsettable_memref_p (operand))
16435 operand = adjust_address (operand, DImode, 0);
16436 parts[0] = operand;
16437 parts[1] = adjust_address (operand, upper_mode, 8);
16439 else if (GET_CODE (operand) == CONST_DOUBLE)
16444 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16445 real_to_target (l, &r, mode);
16447 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16448 if (HOST_BITS_PER_WIDE_INT >= 64)
16451 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16452 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16455 parts[0] = immed_double_const (l[0], l[1], DImode);
16457 if (upper_mode == SImode)
16458 parts[1] = gen_int_mode (l[2], SImode);
16459 else if (HOST_BITS_PER_WIDE_INT >= 64)
16462 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16463 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16466 parts[1] = immed_double_const (l[2], l[3], DImode);
16469 gcc_unreachable ();
16476 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16477 Return false when normal moves are needed; true when all required
16478 insns have been emitted. Operands 2-4 contain the input values
16479 int the correct order; operands 5-7 contain the output values. */
16482 ix86_split_long_move (rtx operands[])
16487 int collisions = 0;
16488 enum machine_mode mode = GET_MODE (operands[0]);
16489 bool collisionparts[4];
16491 /* The DFmode expanders may ask us to move double.
16492 For 64bit target this is single move. By hiding the fact
16493 here we simplify i386.md splitters. */
16494 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16496 /* Optimize constant pool reference to immediates. This is used by
16497 fp moves, that force all constants to memory to allow combining. */
16499 if (MEM_P (operands[1])
16500 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16501 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16502 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16503 if (push_operand (operands[0], VOIDmode))
16505 operands[0] = copy_rtx (operands[0]);
16506 PUT_MODE (operands[0], Pmode);
16509 operands[0] = gen_lowpart (DImode, operands[0]);
16510 operands[1] = gen_lowpart (DImode, operands[1]);
16511 emit_move_insn (operands[0], operands[1]);
16515 /* The only non-offsettable memory we handle is push. */
16516 if (push_operand (operands[0], VOIDmode))
16519 gcc_assert (!MEM_P (operands[0])
16520 || offsettable_memref_p (operands[0]));
16522 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16523 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16525 /* When emitting push, take care for source operands on the stack. */
16526 if (push && MEM_P (operands[1])
16527 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16529 rtx src_base = XEXP (part[1][nparts - 1], 0);
16531 /* Compensate for the stack decrement by 4. */
16532 if (!TARGET_64BIT && nparts == 3
16533 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
16534 src_base = plus_constant (src_base, 4);
16536 /* src_base refers to the stack pointer and is
16537 automatically decreased by emitted push. */
16538 for (i = 0; i < nparts; i++)
16539 part[1][i] = change_address (part[1][i],
16540 GET_MODE (part[1][i]), src_base);
16543 /* We need to do copy in the right order in case an address register
16544 of the source overlaps the destination. */
16545 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16549 for (i = 0; i < nparts; i++)
16552 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16553 if (collisionparts[i])
16557 /* Collision in the middle part can be handled by reordering. */
16558 if (collisions == 1 && nparts == 3 && collisionparts [1])
16560 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16561 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16563 else if (collisions == 1
16565 && (collisionparts [1] || collisionparts [2]))
16567 if (collisionparts [1])
16569 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16570 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16574 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16575 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16579 /* If there are more collisions, we can't handle it by reordering.
16580 Do an lea to the last part and use only one colliding move. */
16581 else if (collisions > 1)
16587 base = part[0][nparts - 1];
16589 /* Handle the case when the last part isn't valid for lea.
16590 Happens in 64-bit mode storing the 12-byte XFmode. */
16591 if (GET_MODE (base) != Pmode)
16592 base = gen_rtx_REG (Pmode, REGNO (base));
16594 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16595 part[1][0] = replace_equiv_address (part[1][0], base);
16596 for (i = 1; i < nparts; i++)
16598 tmp = plus_constant (base, UNITS_PER_WORD * i);
16599 part[1][i] = replace_equiv_address (part[1][i], tmp);
16610 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16611 emit_insn (gen_addsi3 (stack_pointer_rtx,
16612 stack_pointer_rtx, GEN_INT (-4)));
16613 emit_move_insn (part[0][2], part[1][2]);
16615 else if (nparts == 4)
16617 emit_move_insn (part[0][3], part[1][3]);
16618 emit_move_insn (part[0][2], part[1][2]);
16623 /* In 64bit mode we don't have 32bit push available. In case this is
16624 register, it is OK - we will just use larger counterpart. We also
16625 retype memory - these comes from attempt to avoid REX prefix on
16626 moving of second half of TFmode value. */
16627 if (GET_MODE (part[1][1]) == SImode)
16629 switch (GET_CODE (part[1][1]))
16632 part[1][1] = adjust_address (part[1][1], DImode, 0);
16636 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16640 gcc_unreachable ();
16643 if (GET_MODE (part[1][0]) == SImode)
16644 part[1][0] = part[1][1];
16647 emit_move_insn (part[0][1], part[1][1]);
16648 emit_move_insn (part[0][0], part[1][0]);
16652 /* Choose correct order to not overwrite the source before it is copied. */
16653 if ((REG_P (part[0][0])
16654 && REG_P (part[1][1])
16655 && (REGNO (part[0][0]) == REGNO (part[1][1])
16657 && REGNO (part[0][0]) == REGNO (part[1][2]))
16659 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16661 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16663 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16665 operands[2 + i] = part[0][j];
16666 operands[6 + i] = part[1][j];
16671 for (i = 0; i < nparts; i++)
16673 operands[2 + i] = part[0][i];
16674 operands[6 + i] = part[1][i];
16678 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16679 if (optimize_insn_for_size_p ())
16681 for (j = 0; j < nparts - 1; j++)
16682 if (CONST_INT_P (operands[6 + j])
16683 && operands[6 + j] != const0_rtx
16684 && REG_P (operands[2 + j]))
16685 for (i = j; i < nparts - 1; i++)
16686 if (CONST_INT_P (operands[7 + i])
16687 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16688 operands[7 + i] = operands[2 + j];
16691 for (i = 0; i < nparts; i++)
16692 emit_move_insn (operands[2 + i], operands[6 + i]);
16697 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16698 left shift by a constant, either using a single shift or
16699 a sequence of add instructions. */
16702 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16706 emit_insn ((mode == DImode
16708 : gen_adddi3) (operand, operand, operand));
16710 else if (!optimize_insn_for_size_p ()
16711 && count * ix86_cost->add <= ix86_cost->shift_const)
16714 for (i=0; i<count; i++)
16716 emit_insn ((mode == DImode
16718 : gen_adddi3) (operand, operand, operand));
16722 emit_insn ((mode == DImode
16724 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16728 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16730 rtx low[2], high[2];
16732 const int single_width = mode == DImode ? 32 : 64;
16734 if (CONST_INT_P (operands[2]))
16736 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16737 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16739 if (count >= single_width)
16741 emit_move_insn (high[0], low[1]);
16742 emit_move_insn (low[0], const0_rtx);
16744 if (count > single_width)
16745 ix86_expand_ashl_const (high[0], count - single_width, mode);
16749 if (!rtx_equal_p (operands[0], operands[1]))
16750 emit_move_insn (operands[0], operands[1]);
16751 emit_insn ((mode == DImode
16753 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16754 ix86_expand_ashl_const (low[0], count, mode);
16759 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16761 if (operands[1] == const1_rtx)
16763 /* Assuming we've chosen a QImode capable registers, then 1 << N
16764 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16765 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16767 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16769 ix86_expand_clear (low[0]);
16770 ix86_expand_clear (high[0]);
16771 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16773 d = gen_lowpart (QImode, low[0]);
16774 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16775 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16776 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16778 d = gen_lowpart (QImode, high[0]);
16779 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16780 s = gen_rtx_NE (QImode, flags, const0_rtx);
16781 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16784 /* Otherwise, we can get the same results by manually performing
16785 a bit extract operation on bit 5/6, and then performing the two
16786 shifts. The two methods of getting 0/1 into low/high are exactly
16787 the same size. Avoiding the shift in the bit extract case helps
16788 pentium4 a bit; no one else seems to care much either way. */
16793 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16794 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16796 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16797 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16799 emit_insn ((mode == DImode
16801 : gen_lshrdi3) (high[0], high[0],
16802 GEN_INT (mode == DImode ? 5 : 6)));
16803 emit_insn ((mode == DImode
16805 : gen_anddi3) (high[0], high[0], const1_rtx));
16806 emit_move_insn (low[0], high[0]);
16807 emit_insn ((mode == DImode
16809 : gen_xordi3) (low[0], low[0], const1_rtx));
16812 emit_insn ((mode == DImode
16814 : gen_ashldi3) (low[0], low[0], operands[2]));
16815 emit_insn ((mode == DImode
16817 : gen_ashldi3) (high[0], high[0], operands[2]));
16821 if (operands[1] == constm1_rtx)
16823 /* For -1 << N, we can avoid the shld instruction, because we
16824 know that we're shifting 0...31/63 ones into a -1. */
16825 emit_move_insn (low[0], constm1_rtx);
16826 if (optimize_insn_for_size_p ())
16827 emit_move_insn (high[0], low[0]);
16829 emit_move_insn (high[0], constm1_rtx);
16833 if (!rtx_equal_p (operands[0], operands[1]))
16834 emit_move_insn (operands[0], operands[1]);
16836 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16837 emit_insn ((mode == DImode
16839 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16842 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16844 if (TARGET_CMOVE && scratch)
16846 ix86_expand_clear (scratch);
16847 emit_insn ((mode == DImode
16848 ? gen_x86_shift_adj_1
16849 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16853 emit_insn ((mode == DImode
16854 ? gen_x86_shift_adj_2
16855 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16859 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16861 rtx low[2], high[2];
16863 const int single_width = mode == DImode ? 32 : 64;
16865 if (CONST_INT_P (operands[2]))
16867 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16868 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16870 if (count == single_width * 2 - 1)
16872 emit_move_insn (high[0], high[1]);
16873 emit_insn ((mode == DImode
16875 : gen_ashrdi3) (high[0], high[0],
16876 GEN_INT (single_width - 1)));
16877 emit_move_insn (low[0], high[0]);
16880 else if (count >= single_width)
16882 emit_move_insn (low[0], high[1]);
16883 emit_move_insn (high[0], low[0]);
16884 emit_insn ((mode == DImode
16886 : gen_ashrdi3) (high[0], high[0],
16887 GEN_INT (single_width - 1)));
16888 if (count > single_width)
16889 emit_insn ((mode == DImode
16891 : gen_ashrdi3) (low[0], low[0],
16892 GEN_INT (count - single_width)));
16896 if (!rtx_equal_p (operands[0], operands[1]))
16897 emit_move_insn (operands[0], operands[1]);
16898 emit_insn ((mode == DImode
16900 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16901 emit_insn ((mode == DImode
16903 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16908 if (!rtx_equal_p (operands[0], operands[1]))
16909 emit_move_insn (operands[0], operands[1]);
16911 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16913 emit_insn ((mode == DImode
16915 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16916 emit_insn ((mode == DImode
16918 : gen_ashrdi3) (high[0], high[0], operands[2]));
16920 if (TARGET_CMOVE && scratch)
16922 emit_move_insn (scratch, high[0]);
16923 emit_insn ((mode == DImode
16925 : gen_ashrdi3) (scratch, scratch,
16926 GEN_INT (single_width - 1)));
16927 emit_insn ((mode == DImode
16928 ? gen_x86_shift_adj_1
16929 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16933 emit_insn ((mode == DImode
16934 ? gen_x86_shift_adj_3
16935 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16940 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16942 rtx low[2], high[2];
16944 const int single_width = mode == DImode ? 32 : 64;
16946 if (CONST_INT_P (operands[2]))
16948 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16949 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16951 if (count >= single_width)
16953 emit_move_insn (low[0], high[1]);
16954 ix86_expand_clear (high[0]);
16956 if (count > single_width)
16957 emit_insn ((mode == DImode
16959 : gen_lshrdi3) (low[0], low[0],
16960 GEN_INT (count - single_width)));
16964 if (!rtx_equal_p (operands[0], operands[1]))
16965 emit_move_insn (operands[0], operands[1]);
16966 emit_insn ((mode == DImode
16968 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16969 emit_insn ((mode == DImode
16971 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16976 if (!rtx_equal_p (operands[0], operands[1]))
16977 emit_move_insn (operands[0], operands[1]);
16979 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16981 emit_insn ((mode == DImode
16983 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16984 emit_insn ((mode == DImode
16986 : gen_lshrdi3) (high[0], high[0], operands[2]));
16988 /* Heh. By reversing the arguments, we can reuse this pattern. */
16989 if (TARGET_CMOVE && scratch)
16991 ix86_expand_clear (scratch);
16992 emit_insn ((mode == DImode
16993 ? gen_x86_shift_adj_1
16994 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16998 emit_insn ((mode == DImode
16999 ? gen_x86_shift_adj_2
17000 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
17004 /* Predict just emitted jump instruction to be taken with probability PROB. */
17006 predict_jump (int prob)
17008 rtx insn = get_last_insn ();
17009 gcc_assert (JUMP_P (insn));
17010 add_reg_note (insn, REG_BR_PROB, GEN_INT (prob));
17013 /* Helper function for the string operations below. Dest VARIABLE whether
17014 it is aligned to VALUE bytes. If true, jump to the label. */
17016 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
17018 rtx label = gen_label_rtx ();
17019 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
17020 if (GET_MODE (variable) == DImode)
17021 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
17023 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
17024 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
17027 predict_jump (REG_BR_PROB_BASE * 50 / 100);
17029 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17033 /* Adjust COUNTER by the VALUE. */
17035 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
17037 if (GET_MODE (countreg) == DImode)
17038 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
17040 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
17043 /* Zero extend possibly SImode EXP to Pmode register. */
17045 ix86_zero_extend_to_Pmode (rtx exp)
17048 if (GET_MODE (exp) == VOIDmode)
17049 return force_reg (Pmode, exp);
17050 if (GET_MODE (exp) == Pmode)
17051 return copy_to_mode_reg (Pmode, exp);
17052 r = gen_reg_rtx (Pmode);
17053 emit_insn (gen_zero_extendsidi2 (r, exp));
17057 /* Divide COUNTREG by SCALE. */
17059 scale_counter (rtx countreg, int scale)
17065 if (CONST_INT_P (countreg))
17066 return GEN_INT (INTVAL (countreg) / scale);
17067 gcc_assert (REG_P (countreg));
17069 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
17070 GEN_INT (exact_log2 (scale)),
17071 NULL, 1, OPTAB_DIRECT);
17075 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17076 DImode for constant loop counts. */
17078 static enum machine_mode
17079 counter_mode (rtx count_exp)
17081 if (GET_MODE (count_exp) != VOIDmode)
17082 return GET_MODE (count_exp);
17083 if (!CONST_INT_P (count_exp))
17085 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
17090 /* When SRCPTR is non-NULL, output simple loop to move memory
17091 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17092 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17093 equivalent loop to set memory by VALUE (supposed to be in MODE).
17095 The size is rounded down to whole number of chunk size moved at once.
17096 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17100 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
17101 rtx destptr, rtx srcptr, rtx value,
17102 rtx count, enum machine_mode mode, int unroll,
17105 rtx out_label, top_label, iter, tmp;
17106 enum machine_mode iter_mode = counter_mode (count);
17107 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
17108 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
17114 top_label = gen_label_rtx ();
17115 out_label = gen_label_rtx ();
17116 iter = gen_reg_rtx (iter_mode);
17118 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
17119 NULL, 1, OPTAB_DIRECT);
17120 /* Those two should combine. */
17121 if (piece_size == const1_rtx)
17123 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
17125 predict_jump (REG_BR_PROB_BASE * 10 / 100);
17127 emit_move_insn (iter, const0_rtx);
17129 emit_label (top_label);
17131 tmp = convert_modes (Pmode, iter_mode, iter, true);
17132 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
17133 destmem = change_address (destmem, mode, x_addr);
17137 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
17138 srcmem = change_address (srcmem, mode, y_addr);
17140 /* When unrolling for chips that reorder memory reads and writes,
17141 we can save registers by using single temporary.
17142 Also using 4 temporaries is overkill in 32bit mode. */
17143 if (!TARGET_64BIT && 0)
17145 for (i = 0; i < unroll; i++)
17150 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17152 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17154 emit_move_insn (destmem, srcmem);
17160 gcc_assert (unroll <= 4);
17161 for (i = 0; i < unroll; i++)
17163 tmpreg[i] = gen_reg_rtx (mode);
17167 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17169 emit_move_insn (tmpreg[i], srcmem);
17171 for (i = 0; i < unroll; i++)
17176 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17178 emit_move_insn (destmem, tmpreg[i]);
17183 for (i = 0; i < unroll; i++)
17187 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17188 emit_move_insn (destmem, value);
17191 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
17192 true, OPTAB_LIB_WIDEN);
17194 emit_move_insn (iter, tmp);
17196 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
17198 if (expected_size != -1)
17200 expected_size /= GET_MODE_SIZE (mode) * unroll;
17201 if (expected_size == 0)
17203 else if (expected_size > REG_BR_PROB_BASE)
17204 predict_jump (REG_BR_PROB_BASE - 1);
17206 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17209 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17210 iter = ix86_zero_extend_to_Pmode (iter);
17211 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17212 true, OPTAB_LIB_WIDEN);
17213 if (tmp != destptr)
17214 emit_move_insn (destptr, tmp);
17217 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17218 true, OPTAB_LIB_WIDEN);
17220 emit_move_insn (srcptr, tmp);
17222 emit_label (out_label);
17225 /* Output "rep; mov" instruction.
17226 Arguments have same meaning as for previous function */
17228 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17229 rtx destptr, rtx srcptr,
17231 enum machine_mode mode)
17237 /* If the size is known, it is shorter to use rep movs. */
17238 if (mode == QImode && CONST_INT_P (count)
17239 && !(INTVAL (count) & 3))
17242 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17243 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17244 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17245 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17246 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17247 if (mode != QImode)
17249 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17250 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17251 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17252 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17253 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17254 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17258 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17259 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17261 if (CONST_INT_P (count))
17263 count = GEN_INT (INTVAL (count)
17264 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17265 destmem = shallow_copy_rtx (destmem);
17266 srcmem = shallow_copy_rtx (srcmem);
17267 set_mem_size (destmem, count);
17268 set_mem_size (srcmem, count);
17272 if (MEM_SIZE (destmem))
17273 set_mem_size (destmem, NULL_RTX);
17274 if (MEM_SIZE (srcmem))
17275 set_mem_size (srcmem, NULL_RTX);
17277 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17281 /* Output "rep; stos" instruction.
17282 Arguments have same meaning as for previous function */
17284 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17285 rtx count, enum machine_mode mode,
17291 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17292 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17293 value = force_reg (mode, gen_lowpart (mode, value));
17294 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17295 if (mode != QImode)
17297 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17298 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17299 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17302 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17303 if (orig_value == const0_rtx && CONST_INT_P (count))
17305 count = GEN_INT (INTVAL (count)
17306 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17307 destmem = shallow_copy_rtx (destmem);
17308 set_mem_size (destmem, count);
17310 else if (MEM_SIZE (destmem))
17311 set_mem_size (destmem, NULL_RTX);
17312 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17316 emit_strmov (rtx destmem, rtx srcmem,
17317 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17319 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17320 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17321 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17324 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17326 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17327 rtx destptr, rtx srcptr, rtx count, int max_size)
17330 if (CONST_INT_P (count))
17332 HOST_WIDE_INT countval = INTVAL (count);
17335 if ((countval & 0x10) && max_size > 16)
17339 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17340 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17343 gcc_unreachable ();
17346 if ((countval & 0x08) && max_size > 8)
17349 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17352 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17353 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17357 if ((countval & 0x04) && max_size > 4)
17359 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17362 if ((countval & 0x02) && max_size > 2)
17364 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17367 if ((countval & 0x01) && max_size > 1)
17369 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17376 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17377 count, 1, OPTAB_DIRECT);
17378 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17379 count, QImode, 1, 4);
17383 /* When there are stringops, we can cheaply increase dest and src pointers.
17384 Otherwise we save code size by maintaining offset (zero is readily
17385 available from preceding rep operation) and using x86 addressing modes.
17387 if (TARGET_SINGLE_STRINGOP)
17391 rtx label = ix86_expand_aligntest (count, 4, true);
17392 src = change_address (srcmem, SImode, srcptr);
17393 dest = change_address (destmem, SImode, destptr);
17394 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17395 emit_label (label);
17396 LABEL_NUSES (label) = 1;
17400 rtx label = ix86_expand_aligntest (count, 2, true);
17401 src = change_address (srcmem, HImode, srcptr);
17402 dest = change_address (destmem, HImode, destptr);
17403 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17404 emit_label (label);
17405 LABEL_NUSES (label) = 1;
17409 rtx label = ix86_expand_aligntest (count, 1, true);
17410 src = change_address (srcmem, QImode, srcptr);
17411 dest = change_address (destmem, QImode, destptr);
17412 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17413 emit_label (label);
17414 LABEL_NUSES (label) = 1;
17419 rtx offset = force_reg (Pmode, const0_rtx);
17424 rtx label = ix86_expand_aligntest (count, 4, true);
17425 src = change_address (srcmem, SImode, srcptr);
17426 dest = change_address (destmem, SImode, destptr);
17427 emit_move_insn (dest, src);
17428 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17429 true, OPTAB_LIB_WIDEN);
17431 emit_move_insn (offset, tmp);
17432 emit_label (label);
17433 LABEL_NUSES (label) = 1;
17437 rtx label = ix86_expand_aligntest (count, 2, true);
17438 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17439 src = change_address (srcmem, HImode, tmp);
17440 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17441 dest = change_address (destmem, HImode, tmp);
17442 emit_move_insn (dest, src);
17443 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17444 true, OPTAB_LIB_WIDEN);
17446 emit_move_insn (offset, tmp);
17447 emit_label (label);
17448 LABEL_NUSES (label) = 1;
17452 rtx label = ix86_expand_aligntest (count, 1, true);
17453 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17454 src = change_address (srcmem, QImode, tmp);
17455 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17456 dest = change_address (destmem, QImode, tmp);
17457 emit_move_insn (dest, src);
17458 emit_label (label);
17459 LABEL_NUSES (label) = 1;
17464 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17466 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17467 rtx count, int max_size)
17470 expand_simple_binop (counter_mode (count), AND, count,
17471 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17472 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17473 gen_lowpart (QImode, value), count, QImode,
17477 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17479 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17483 if (CONST_INT_P (count))
17485 HOST_WIDE_INT countval = INTVAL (count);
17488 if ((countval & 0x10) && max_size > 16)
17492 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17493 emit_insn (gen_strset (destptr, dest, value));
17494 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17495 emit_insn (gen_strset (destptr, dest, value));
17498 gcc_unreachable ();
17501 if ((countval & 0x08) && max_size > 8)
17505 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17506 emit_insn (gen_strset (destptr, dest, value));
17510 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17511 emit_insn (gen_strset (destptr, dest, value));
17512 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17513 emit_insn (gen_strset (destptr, dest, value));
17517 if ((countval & 0x04) && max_size > 4)
17519 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17520 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17523 if ((countval & 0x02) && max_size > 2)
17525 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17526 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17529 if ((countval & 0x01) && max_size > 1)
17531 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17532 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17539 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17544 rtx label = ix86_expand_aligntest (count, 16, true);
17547 dest = change_address (destmem, DImode, destptr);
17548 emit_insn (gen_strset (destptr, dest, value));
17549 emit_insn (gen_strset (destptr, dest, value));
17553 dest = change_address (destmem, SImode, destptr);
17554 emit_insn (gen_strset (destptr, dest, value));
17555 emit_insn (gen_strset (destptr, dest, value));
17556 emit_insn (gen_strset (destptr, dest, value));
17557 emit_insn (gen_strset (destptr, dest, value));
17559 emit_label (label);
17560 LABEL_NUSES (label) = 1;
17564 rtx label = ix86_expand_aligntest (count, 8, true);
17567 dest = change_address (destmem, DImode, destptr);
17568 emit_insn (gen_strset (destptr, dest, value));
17572 dest = change_address (destmem, SImode, destptr);
17573 emit_insn (gen_strset (destptr, dest, value));
17574 emit_insn (gen_strset (destptr, dest, value));
17576 emit_label (label);
17577 LABEL_NUSES (label) = 1;
17581 rtx label = ix86_expand_aligntest (count, 4, true);
17582 dest = change_address (destmem, SImode, destptr);
17583 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17584 emit_label (label);
17585 LABEL_NUSES (label) = 1;
17589 rtx label = ix86_expand_aligntest (count, 2, true);
17590 dest = change_address (destmem, HImode, destptr);
17591 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17592 emit_label (label);
17593 LABEL_NUSES (label) = 1;
17597 rtx label = ix86_expand_aligntest (count, 1, true);
17598 dest = change_address (destmem, QImode, destptr);
17599 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17600 emit_label (label);
17601 LABEL_NUSES (label) = 1;
17605 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17606 DESIRED_ALIGNMENT. */
17608 expand_movmem_prologue (rtx destmem, rtx srcmem,
17609 rtx destptr, rtx srcptr, rtx count,
17610 int align, int desired_alignment)
17612 if (align <= 1 && desired_alignment > 1)
17614 rtx label = ix86_expand_aligntest (destptr, 1, false);
17615 srcmem = change_address (srcmem, QImode, srcptr);
17616 destmem = change_address (destmem, QImode, destptr);
17617 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17618 ix86_adjust_counter (count, 1);
17619 emit_label (label);
17620 LABEL_NUSES (label) = 1;
17622 if (align <= 2 && desired_alignment > 2)
17624 rtx label = ix86_expand_aligntest (destptr, 2, false);
17625 srcmem = change_address (srcmem, HImode, srcptr);
17626 destmem = change_address (destmem, HImode, destptr);
17627 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17628 ix86_adjust_counter (count, 2);
17629 emit_label (label);
17630 LABEL_NUSES (label) = 1;
17632 if (align <= 4 && desired_alignment > 4)
17634 rtx label = ix86_expand_aligntest (destptr, 4, false);
17635 srcmem = change_address (srcmem, SImode, srcptr);
17636 destmem = change_address (destmem, SImode, destptr);
17637 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17638 ix86_adjust_counter (count, 4);
17639 emit_label (label);
17640 LABEL_NUSES (label) = 1;
17642 gcc_assert (desired_alignment <= 8);
17645 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17646 ALIGN_BYTES is how many bytes need to be copied. */
17648 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17649 int desired_align, int align_bytes)
17652 rtx src_size, dst_size;
17654 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17655 if (src_align_bytes >= 0)
17656 src_align_bytes = desired_align - src_align_bytes;
17657 src_size = MEM_SIZE (src);
17658 dst_size = MEM_SIZE (dst);
17659 if (align_bytes & 1)
17661 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17662 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17664 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17666 if (align_bytes & 2)
17668 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17669 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17670 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17671 set_mem_align (dst, 2 * BITS_PER_UNIT);
17672 if (src_align_bytes >= 0
17673 && (src_align_bytes & 1) == (align_bytes & 1)
17674 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17675 set_mem_align (src, 2 * BITS_PER_UNIT);
17677 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17679 if (align_bytes & 4)
17681 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17682 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17683 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17684 set_mem_align (dst, 4 * BITS_PER_UNIT);
17685 if (src_align_bytes >= 0)
17687 unsigned int src_align = 0;
17688 if ((src_align_bytes & 3) == (align_bytes & 3))
17690 else if ((src_align_bytes & 1) == (align_bytes & 1))
17692 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17693 set_mem_align (src, src_align * BITS_PER_UNIT);
17696 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17698 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17699 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17700 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17701 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17702 if (src_align_bytes >= 0)
17704 unsigned int src_align = 0;
17705 if ((src_align_bytes & 7) == (align_bytes & 7))
17707 else if ((src_align_bytes & 3) == (align_bytes & 3))
17709 else if ((src_align_bytes & 1) == (align_bytes & 1))
17711 if (src_align > (unsigned int) desired_align)
17712 src_align = desired_align;
17713 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17714 set_mem_align (src, src_align * BITS_PER_UNIT);
17717 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17719 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17724 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17725 DESIRED_ALIGNMENT. */
17727 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17728 int align, int desired_alignment)
17730 if (align <= 1 && desired_alignment > 1)
17732 rtx label = ix86_expand_aligntest (destptr, 1, false);
17733 destmem = change_address (destmem, QImode, destptr);
17734 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17735 ix86_adjust_counter (count, 1);
17736 emit_label (label);
17737 LABEL_NUSES (label) = 1;
17739 if (align <= 2 && desired_alignment > 2)
17741 rtx label = ix86_expand_aligntest (destptr, 2, false);
17742 destmem = change_address (destmem, HImode, destptr);
17743 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17744 ix86_adjust_counter (count, 2);
17745 emit_label (label);
17746 LABEL_NUSES (label) = 1;
17748 if (align <= 4 && desired_alignment > 4)
17750 rtx label = ix86_expand_aligntest (destptr, 4, false);
17751 destmem = change_address (destmem, SImode, destptr);
17752 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17753 ix86_adjust_counter (count, 4);
17754 emit_label (label);
17755 LABEL_NUSES (label) = 1;
17757 gcc_assert (desired_alignment <= 8);
17760 /* Set enough from DST to align DST known to by aligned by ALIGN to
17761 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17763 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17764 int desired_align, int align_bytes)
17767 rtx dst_size = MEM_SIZE (dst);
17768 if (align_bytes & 1)
17770 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17772 emit_insn (gen_strset (destreg, dst,
17773 gen_lowpart (QImode, value)));
17775 if (align_bytes & 2)
17777 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17778 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17779 set_mem_align (dst, 2 * BITS_PER_UNIT);
17781 emit_insn (gen_strset (destreg, dst,
17782 gen_lowpart (HImode, value)));
17784 if (align_bytes & 4)
17786 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17787 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17788 set_mem_align (dst, 4 * BITS_PER_UNIT);
17790 emit_insn (gen_strset (destreg, dst,
17791 gen_lowpart (SImode, value)));
17793 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17794 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17795 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17797 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17801 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17802 static enum stringop_alg
17803 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17804 int *dynamic_check)
17806 const struct stringop_algs * algs;
17807 bool optimize_for_speed;
17808 /* Algorithms using the rep prefix want at least edi and ecx;
17809 additionally, memset wants eax and memcpy wants esi. Don't
17810 consider such algorithms if the user has appropriated those
17811 registers for their own purposes. */
17812 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17814 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17816 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17817 || (alg != rep_prefix_1_byte \
17818 && alg != rep_prefix_4_byte \
17819 && alg != rep_prefix_8_byte))
17820 const struct processor_costs *cost;
17822 /* Even if the string operation call is cold, we still might spend a lot
17823 of time processing large blocks. */
17824 if (optimize_function_for_size_p (cfun)
17825 || (optimize_insn_for_size_p ()
17826 && expected_size != -1 && expected_size < 256))
17827 optimize_for_speed = false;
17829 optimize_for_speed = true;
17831 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17833 *dynamic_check = -1;
17835 algs = &cost->memset[TARGET_64BIT != 0];
17837 algs = &cost->memcpy[TARGET_64BIT != 0];
17838 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17839 return stringop_alg;
17840 /* rep; movq or rep; movl is the smallest variant. */
17841 else if (!optimize_for_speed)
17843 if (!count || (count & 3))
17844 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17846 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17848 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17850 else if (expected_size != -1 && expected_size < 4)
17851 return loop_1_byte;
17852 else if (expected_size != -1)
17855 enum stringop_alg alg = libcall;
17856 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17858 /* We get here if the algorithms that were not libcall-based
17859 were rep-prefix based and we are unable to use rep prefixes
17860 based on global register usage. Break out of the loop and
17861 use the heuristic below. */
17862 if (algs->size[i].max == 0)
17864 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17866 enum stringop_alg candidate = algs->size[i].alg;
17868 if (candidate != libcall && ALG_USABLE_P (candidate))
17870 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17871 last non-libcall inline algorithm. */
17872 if (TARGET_INLINE_ALL_STRINGOPS)
17874 /* When the current size is best to be copied by a libcall,
17875 but we are still forced to inline, run the heuristic below
17876 that will pick code for medium sized blocks. */
17877 if (alg != libcall)
17881 else if (ALG_USABLE_P (candidate))
17885 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17887 /* When asked to inline the call anyway, try to pick meaningful choice.
17888 We look for maximal size of block that is faster to copy by hand and
17889 take blocks of at most of that size guessing that average size will
17890 be roughly half of the block.
17892 If this turns out to be bad, we might simply specify the preferred
17893 choice in ix86_costs. */
17894 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17895 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17898 enum stringop_alg alg;
17900 bool any_alg_usable_p = true;
17902 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17904 enum stringop_alg candidate = algs->size[i].alg;
17905 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17907 if (candidate != libcall && candidate
17908 && ALG_USABLE_P (candidate))
17909 max = algs->size[i].max;
17911 /* If there aren't any usable algorithms, then recursing on
17912 smaller sizes isn't going to find anything. Just return the
17913 simple byte-at-a-time copy loop. */
17914 if (!any_alg_usable_p)
17916 /* Pick something reasonable. */
17917 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17918 *dynamic_check = 128;
17919 return loop_1_byte;
17923 alg = decide_alg (count, max / 2, memset, dynamic_check);
17924 gcc_assert (*dynamic_check == -1);
17925 gcc_assert (alg != libcall);
17926 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17927 *dynamic_check = max;
17930 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17931 #undef ALG_USABLE_P
17934 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17935 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17937 decide_alignment (int align,
17938 enum stringop_alg alg,
17941 int desired_align = 0;
17945 gcc_unreachable ();
17947 case unrolled_loop:
17948 desired_align = GET_MODE_SIZE (Pmode);
17950 case rep_prefix_8_byte:
17953 case rep_prefix_4_byte:
17954 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17955 copying whole cacheline at once. */
17956 if (TARGET_PENTIUMPRO)
17961 case rep_prefix_1_byte:
17962 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17963 copying whole cacheline at once. */
17964 if (TARGET_PENTIUMPRO)
17978 if (desired_align < align)
17979 desired_align = align;
17980 if (expected_size != -1 && expected_size < 4)
17981 desired_align = align;
17982 return desired_align;
17985 /* Return the smallest power of 2 greater than VAL. */
17987 smallest_pow2_greater_than (int val)
17995 /* Expand string move (memcpy) operation. Use i386 string operations when
17996 profitable. expand_setmem contains similar code. The code depends upon
17997 architecture, block size and alignment, but always has the same
18000 1) Prologue guard: Conditional that jumps up to epilogues for small
18001 blocks that can be handled by epilogue alone. This is faster but
18002 also needed for correctness, since prologue assume the block is larger
18003 than the desired alignment.
18005 Optional dynamic check for size and libcall for large
18006 blocks is emitted here too, with -minline-stringops-dynamically.
18008 2) Prologue: copy first few bytes in order to get destination aligned
18009 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
18010 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
18011 We emit either a jump tree on power of two sized blocks, or a byte loop.
18013 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
18014 with specified algorithm.
18016 4) Epilogue: code copying tail of the block that is too small to be
18017 handled by main body (or up to size guarded by prologue guard). */
18020 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
18021 rtx expected_align_exp, rtx expected_size_exp)
18027 rtx jump_around_label = NULL;
18028 HOST_WIDE_INT align = 1;
18029 unsigned HOST_WIDE_INT count = 0;
18030 HOST_WIDE_INT expected_size = -1;
18031 int size_needed = 0, epilogue_size_needed;
18032 int desired_align = 0, align_bytes = 0;
18033 enum stringop_alg alg;
18035 bool need_zero_guard = false;
18037 if (CONST_INT_P (align_exp))
18038 align = INTVAL (align_exp);
18039 /* i386 can do misaligned access on reasonably increased cost. */
18040 if (CONST_INT_P (expected_align_exp)
18041 && INTVAL (expected_align_exp) > align)
18042 align = INTVAL (expected_align_exp);
18043 /* ALIGN is the minimum of destination and source alignment, but we care here
18044 just about destination alignment. */
18045 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
18046 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
18048 if (CONST_INT_P (count_exp))
18049 count = expected_size = INTVAL (count_exp);
18050 if (CONST_INT_P (expected_size_exp) && count == 0)
18051 expected_size = INTVAL (expected_size_exp);
18053 /* Make sure we don't need to care about overflow later on. */
18054 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18057 /* Step 0: Decide on preferred algorithm, desired alignment and
18058 size of chunks to be copied by main loop. */
18060 alg = decide_alg (count, expected_size, false, &dynamic_check);
18061 desired_align = decide_alignment (align, alg, expected_size);
18063 if (!TARGET_ALIGN_STRINGOPS)
18064 align = desired_align;
18066 if (alg == libcall)
18068 gcc_assert (alg != no_stringop);
18070 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
18071 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18072 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
18077 gcc_unreachable ();
18079 need_zero_guard = true;
18080 size_needed = GET_MODE_SIZE (Pmode);
18082 case unrolled_loop:
18083 need_zero_guard = true;
18084 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
18086 case rep_prefix_8_byte:
18089 case rep_prefix_4_byte:
18092 case rep_prefix_1_byte:
18096 need_zero_guard = true;
18101 epilogue_size_needed = size_needed;
18103 /* Step 1: Prologue guard. */
18105 /* Alignment code needs count to be in register. */
18106 if (CONST_INT_P (count_exp) && desired_align > align)
18108 if (INTVAL (count_exp) > desired_align
18109 && INTVAL (count_exp) > size_needed)
18112 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18113 if (align_bytes <= 0)
18116 align_bytes = desired_align - align_bytes;
18118 if (align_bytes == 0)
18119 count_exp = force_reg (counter_mode (count_exp), count_exp);
18121 gcc_assert (desired_align >= 1 && align >= 1);
18123 /* Ensure that alignment prologue won't copy past end of block. */
18124 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18126 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18127 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18128 Make sure it is power of 2. */
18129 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18133 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18135 /* If main algorithm works on QImode, no epilogue is needed.
18136 For small sizes just don't align anything. */
18137 if (size_needed == 1)
18138 desired_align = align;
18145 label = gen_label_rtx ();
18146 emit_cmp_and_jump_insns (count_exp,
18147 GEN_INT (epilogue_size_needed),
18148 LTU, 0, counter_mode (count_exp), 1, label);
18149 if (expected_size == -1 || expected_size < epilogue_size_needed)
18150 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18152 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18156 /* Emit code to decide on runtime whether library call or inline should be
18158 if (dynamic_check != -1)
18160 if (CONST_INT_P (count_exp))
18162 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
18164 emit_block_move_via_libcall (dst, src, count_exp, false);
18165 count_exp = const0_rtx;
18171 rtx hot_label = gen_label_rtx ();
18172 jump_around_label = gen_label_rtx ();
18173 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18174 LEU, 0, GET_MODE (count_exp), 1, hot_label);
18175 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18176 emit_block_move_via_libcall (dst, src, count_exp, false);
18177 emit_jump (jump_around_label);
18178 emit_label (hot_label);
18182 /* Step 2: Alignment prologue. */
18184 if (desired_align > align)
18186 if (align_bytes == 0)
18188 /* Except for the first move in epilogue, we no longer know
18189 constant offset in aliasing info. It don't seems to worth
18190 the pain to maintain it for the first move, so throw away
18192 src = change_address (src, BLKmode, srcreg);
18193 dst = change_address (dst, BLKmode, destreg);
18194 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
18199 /* If we know how many bytes need to be stored before dst is
18200 sufficiently aligned, maintain aliasing info accurately. */
18201 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
18202 desired_align, align_bytes);
18203 count_exp = plus_constant (count_exp, -align_bytes);
18204 count -= align_bytes;
18206 if (need_zero_guard
18207 && (count < (unsigned HOST_WIDE_INT) size_needed
18208 || (align_bytes == 0
18209 && count < ((unsigned HOST_WIDE_INT) size_needed
18210 + desired_align - align))))
18212 /* It is possible that we copied enough so the main loop will not
18214 gcc_assert (size_needed > 1);
18215 if (label == NULL_RTX)
18216 label = gen_label_rtx ();
18217 emit_cmp_and_jump_insns (count_exp,
18218 GEN_INT (size_needed),
18219 LTU, 0, counter_mode (count_exp), 1, label);
18220 if (expected_size == -1
18221 || expected_size < (desired_align - align) / 2 + size_needed)
18222 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18224 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18227 if (label && size_needed == 1)
18229 emit_label (label);
18230 LABEL_NUSES (label) = 1;
18232 epilogue_size_needed = 1;
18234 else if (label == NULL_RTX)
18235 epilogue_size_needed = size_needed;
18237 /* Step 3: Main loop. */
18243 gcc_unreachable ();
18245 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18246 count_exp, QImode, 1, expected_size);
18249 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18250 count_exp, Pmode, 1, expected_size);
18252 case unrolled_loop:
18253 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18254 registers for 4 temporaries anyway. */
18255 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18256 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18259 case rep_prefix_8_byte:
18260 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18263 case rep_prefix_4_byte:
18264 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18267 case rep_prefix_1_byte:
18268 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18272 /* Adjust properly the offset of src and dest memory for aliasing. */
18273 if (CONST_INT_P (count_exp))
18275 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18276 (count / size_needed) * size_needed);
18277 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18278 (count / size_needed) * size_needed);
18282 src = change_address (src, BLKmode, srcreg);
18283 dst = change_address (dst, BLKmode, destreg);
18286 /* Step 4: Epilogue to copy the remaining bytes. */
18290 /* When the main loop is done, COUNT_EXP might hold original count,
18291 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18292 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18293 bytes. Compensate if needed. */
18295 if (size_needed < epilogue_size_needed)
18298 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18299 GEN_INT (size_needed - 1), count_exp, 1,
18301 if (tmp != count_exp)
18302 emit_move_insn (count_exp, tmp);
18304 emit_label (label);
18305 LABEL_NUSES (label) = 1;
18308 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18309 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18310 epilogue_size_needed);
18311 if (jump_around_label)
18312 emit_label (jump_around_label);
18316 /* Helper function for memcpy. For QImode value 0xXY produce
18317 0xXYXYXYXY of wide specified by MODE. This is essentially
18318 a * 0x10101010, but we can do slightly better than
18319 synth_mult by unwinding the sequence by hand on CPUs with
18322 promote_duplicated_reg (enum machine_mode mode, rtx val)
18324 enum machine_mode valmode = GET_MODE (val);
18326 int nops = mode == DImode ? 3 : 2;
18328 gcc_assert (mode == SImode || mode == DImode);
18329 if (val == const0_rtx)
18330 return copy_to_mode_reg (mode, const0_rtx);
18331 if (CONST_INT_P (val))
18333 HOST_WIDE_INT v = INTVAL (val) & 255;
18337 if (mode == DImode)
18338 v |= (v << 16) << 16;
18339 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18342 if (valmode == VOIDmode)
18344 if (valmode != QImode)
18345 val = gen_lowpart (QImode, val);
18346 if (mode == QImode)
18348 if (!TARGET_PARTIAL_REG_STALL)
18350 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18351 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18352 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18353 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18355 rtx reg = convert_modes (mode, QImode, val, true);
18356 tmp = promote_duplicated_reg (mode, const1_rtx);
18357 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18362 rtx reg = convert_modes (mode, QImode, val, true);
18364 if (!TARGET_PARTIAL_REG_STALL)
18365 if (mode == SImode)
18366 emit_insn (gen_movsi_insv_1 (reg, reg));
18368 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18371 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18372 NULL, 1, OPTAB_DIRECT);
18374 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18376 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18377 NULL, 1, OPTAB_DIRECT);
18378 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18379 if (mode == SImode)
18381 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18382 NULL, 1, OPTAB_DIRECT);
18383 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18388 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18389 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18390 alignment from ALIGN to DESIRED_ALIGN. */
18392 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18397 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18398 promoted_val = promote_duplicated_reg (DImode, val);
18399 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18400 promoted_val = promote_duplicated_reg (SImode, val);
18401 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18402 promoted_val = promote_duplicated_reg (HImode, val);
18404 promoted_val = val;
18406 return promoted_val;
18409 /* Expand string clear operation (bzero). Use i386 string operations when
18410 profitable. See expand_movmem comment for explanation of individual
18411 steps performed. */
18413 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18414 rtx expected_align_exp, rtx expected_size_exp)
18419 rtx jump_around_label = NULL;
18420 HOST_WIDE_INT align = 1;
18421 unsigned HOST_WIDE_INT count = 0;
18422 HOST_WIDE_INT expected_size = -1;
18423 int size_needed = 0, epilogue_size_needed;
18424 int desired_align = 0, align_bytes = 0;
18425 enum stringop_alg alg;
18426 rtx promoted_val = NULL;
18427 bool force_loopy_epilogue = false;
18429 bool need_zero_guard = false;
18431 if (CONST_INT_P (align_exp))
18432 align = INTVAL (align_exp);
18433 /* i386 can do misaligned access on reasonably increased cost. */
18434 if (CONST_INT_P (expected_align_exp)
18435 && INTVAL (expected_align_exp) > align)
18436 align = INTVAL (expected_align_exp);
18437 if (CONST_INT_P (count_exp))
18438 count = expected_size = INTVAL (count_exp);
18439 if (CONST_INT_P (expected_size_exp) && count == 0)
18440 expected_size = INTVAL (expected_size_exp);
18442 /* Make sure we don't need to care about overflow later on. */
18443 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18446 /* Step 0: Decide on preferred algorithm, desired alignment and
18447 size of chunks to be copied by main loop. */
18449 alg = decide_alg (count, expected_size, true, &dynamic_check);
18450 desired_align = decide_alignment (align, alg, expected_size);
18452 if (!TARGET_ALIGN_STRINGOPS)
18453 align = desired_align;
18455 if (alg == libcall)
18457 gcc_assert (alg != no_stringop);
18459 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18460 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18465 gcc_unreachable ();
18467 need_zero_guard = true;
18468 size_needed = GET_MODE_SIZE (Pmode);
18470 case unrolled_loop:
18471 need_zero_guard = true;
18472 size_needed = GET_MODE_SIZE (Pmode) * 4;
18474 case rep_prefix_8_byte:
18477 case rep_prefix_4_byte:
18480 case rep_prefix_1_byte:
18484 need_zero_guard = true;
18488 epilogue_size_needed = size_needed;
18490 /* Step 1: Prologue guard. */
18492 /* Alignment code needs count to be in register. */
18493 if (CONST_INT_P (count_exp) && desired_align > align)
18495 if (INTVAL (count_exp) > desired_align
18496 && INTVAL (count_exp) > size_needed)
18499 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18500 if (align_bytes <= 0)
18503 align_bytes = desired_align - align_bytes;
18505 if (align_bytes == 0)
18507 enum machine_mode mode = SImode;
18508 if (TARGET_64BIT && (count & ~0xffffffff))
18510 count_exp = force_reg (mode, count_exp);
18513 /* Do the cheap promotion to allow better CSE across the
18514 main loop and epilogue (ie one load of the big constant in the
18515 front of all code. */
18516 if (CONST_INT_P (val_exp))
18517 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18518 desired_align, align);
18519 /* Ensure that alignment prologue won't copy past end of block. */
18520 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18522 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18523 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18524 Make sure it is power of 2. */
18525 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18527 /* To improve performance of small blocks, we jump around the VAL
18528 promoting mode. This mean that if the promoted VAL is not constant,
18529 we might not use it in the epilogue and have to use byte
18531 if (epilogue_size_needed > 2 && !promoted_val)
18532 force_loopy_epilogue = true;
18535 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18537 /* If main algorithm works on QImode, no epilogue is needed.
18538 For small sizes just don't align anything. */
18539 if (size_needed == 1)
18540 desired_align = align;
18547 label = gen_label_rtx ();
18548 emit_cmp_and_jump_insns (count_exp,
18549 GEN_INT (epilogue_size_needed),
18550 LTU, 0, counter_mode (count_exp), 1, label);
18551 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18552 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18554 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18557 if (dynamic_check != -1)
18559 rtx hot_label = gen_label_rtx ();
18560 jump_around_label = gen_label_rtx ();
18561 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18562 LEU, 0, counter_mode (count_exp), 1, hot_label);
18563 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18564 set_storage_via_libcall (dst, count_exp, val_exp, false);
18565 emit_jump (jump_around_label);
18566 emit_label (hot_label);
18569 /* Step 2: Alignment prologue. */
18571 /* Do the expensive promotion once we branched off the small blocks. */
18573 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18574 desired_align, align);
18575 gcc_assert (desired_align >= 1 && align >= 1);
18577 if (desired_align > align)
18579 if (align_bytes == 0)
18581 /* Except for the first move in epilogue, we no longer know
18582 constant offset in aliasing info. It don't seems to worth
18583 the pain to maintain it for the first move, so throw away
18585 dst = change_address (dst, BLKmode, destreg);
18586 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18591 /* If we know how many bytes need to be stored before dst is
18592 sufficiently aligned, maintain aliasing info accurately. */
18593 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18594 desired_align, align_bytes);
18595 count_exp = plus_constant (count_exp, -align_bytes);
18596 count -= align_bytes;
18598 if (need_zero_guard
18599 && (count < (unsigned HOST_WIDE_INT) size_needed
18600 || (align_bytes == 0
18601 && count < ((unsigned HOST_WIDE_INT) size_needed
18602 + desired_align - align))))
18604 /* It is possible that we copied enough so the main loop will not
18606 gcc_assert (size_needed > 1);
18607 if (label == NULL_RTX)
18608 label = gen_label_rtx ();
18609 emit_cmp_and_jump_insns (count_exp,
18610 GEN_INT (size_needed),
18611 LTU, 0, counter_mode (count_exp), 1, label);
18612 if (expected_size == -1
18613 || expected_size < (desired_align - align) / 2 + size_needed)
18614 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18616 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18619 if (label && size_needed == 1)
18621 emit_label (label);
18622 LABEL_NUSES (label) = 1;
18624 promoted_val = val_exp;
18625 epilogue_size_needed = 1;
18627 else if (label == NULL_RTX)
18628 epilogue_size_needed = size_needed;
18630 /* Step 3: Main loop. */
18636 gcc_unreachable ();
18638 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18639 count_exp, QImode, 1, expected_size);
18642 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18643 count_exp, Pmode, 1, expected_size);
18645 case unrolled_loop:
18646 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18647 count_exp, Pmode, 4, expected_size);
18649 case rep_prefix_8_byte:
18650 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18653 case rep_prefix_4_byte:
18654 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18657 case rep_prefix_1_byte:
18658 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18662 /* Adjust properly the offset of src and dest memory for aliasing. */
18663 if (CONST_INT_P (count_exp))
18664 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18665 (count / size_needed) * size_needed);
18667 dst = change_address (dst, BLKmode, destreg);
18669 /* Step 4: Epilogue to copy the remaining bytes. */
18673 /* When the main loop is done, COUNT_EXP might hold original count,
18674 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18675 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18676 bytes. Compensate if needed. */
18678 if (size_needed < epilogue_size_needed)
18681 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18682 GEN_INT (size_needed - 1), count_exp, 1,
18684 if (tmp != count_exp)
18685 emit_move_insn (count_exp, tmp);
18687 emit_label (label);
18688 LABEL_NUSES (label) = 1;
18691 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18693 if (force_loopy_epilogue)
18694 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18695 epilogue_size_needed);
18697 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18698 epilogue_size_needed);
18700 if (jump_around_label)
18701 emit_label (jump_around_label);
18705 /* Expand the appropriate insns for doing strlen if not just doing
18708 out = result, initialized with the start address
18709 align_rtx = alignment of the address.
18710 scratch = scratch register, initialized with the startaddress when
18711 not aligned, otherwise undefined
18713 This is just the body. It needs the initializations mentioned above and
18714 some address computing at the end. These things are done in i386.md. */
18717 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18721 rtx align_2_label = NULL_RTX;
18722 rtx align_3_label = NULL_RTX;
18723 rtx align_4_label = gen_label_rtx ();
18724 rtx end_0_label = gen_label_rtx ();
18726 rtx tmpreg = gen_reg_rtx (SImode);
18727 rtx scratch = gen_reg_rtx (SImode);
18731 if (CONST_INT_P (align_rtx))
18732 align = INTVAL (align_rtx);
18734 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18736 /* Is there a known alignment and is it less than 4? */
18739 rtx scratch1 = gen_reg_rtx (Pmode);
18740 emit_move_insn (scratch1, out);
18741 /* Is there a known alignment and is it not 2? */
18744 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18745 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18747 /* Leave just the 3 lower bits. */
18748 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18749 NULL_RTX, 0, OPTAB_WIDEN);
18751 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18752 Pmode, 1, align_4_label);
18753 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18754 Pmode, 1, align_2_label);
18755 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18756 Pmode, 1, align_3_label);
18760 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18761 check if is aligned to 4 - byte. */
18763 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18764 NULL_RTX, 0, OPTAB_WIDEN);
18766 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18767 Pmode, 1, align_4_label);
18770 mem = change_address (src, QImode, out);
18772 /* Now compare the bytes. */
18774 /* Compare the first n unaligned byte on a byte per byte basis. */
18775 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18776 QImode, 1, end_0_label);
18778 /* Increment the address. */
18779 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18781 /* Not needed with an alignment of 2 */
18784 emit_label (align_2_label);
18786 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18789 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18791 emit_label (align_3_label);
18794 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18797 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18800 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18801 align this loop. It gives only huge programs, but does not help to
18803 emit_label (align_4_label);
18805 mem = change_address (src, SImode, out);
18806 emit_move_insn (scratch, mem);
18807 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18809 /* This formula yields a nonzero result iff one of the bytes is zero.
18810 This saves three branches inside loop and many cycles. */
18812 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18813 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18814 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18815 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18816 gen_int_mode (0x80808080, SImode)));
18817 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18822 rtx reg = gen_reg_rtx (SImode);
18823 rtx reg2 = gen_reg_rtx (Pmode);
18824 emit_move_insn (reg, tmpreg);
18825 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18827 /* If zero is not in the first two bytes, move two bytes forward. */
18828 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18829 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18830 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18831 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18832 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18835 /* Emit lea manually to avoid clobbering of flags. */
18836 emit_insn (gen_rtx_SET (SImode, reg2,
18837 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18839 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18840 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18841 emit_insn (gen_rtx_SET (VOIDmode, out,
18842 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18849 rtx end_2_label = gen_label_rtx ();
18850 /* Is zero in the first two bytes? */
18852 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18853 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18854 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18855 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18856 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18858 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18859 JUMP_LABEL (tmp) = end_2_label;
18861 /* Not in the first two. Move two bytes forward. */
18862 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18863 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18865 emit_label (end_2_label);
18869 /* Avoid branch in fixing the byte. */
18870 tmpreg = gen_lowpart (QImode, tmpreg);
18871 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18872 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18873 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18875 emit_label (end_0_label);
18878 /* Expand strlen. */
18881 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18883 rtx addr, scratch1, scratch2, scratch3, scratch4;
18885 /* The generic case of strlen expander is long. Avoid it's
18886 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18888 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18889 && !TARGET_INLINE_ALL_STRINGOPS
18890 && !optimize_insn_for_size_p ()
18891 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18894 addr = force_reg (Pmode, XEXP (src, 0));
18895 scratch1 = gen_reg_rtx (Pmode);
18897 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18898 && !optimize_insn_for_size_p ())
18900 /* Well it seems that some optimizer does not combine a call like
18901 foo(strlen(bar), strlen(bar));
18902 when the move and the subtraction is done here. It does calculate
18903 the length just once when these instructions are done inside of
18904 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18905 often used and I use one fewer register for the lifetime of
18906 output_strlen_unroll() this is better. */
18908 emit_move_insn (out, addr);
18910 ix86_expand_strlensi_unroll_1 (out, src, align);
18912 /* strlensi_unroll_1 returns the address of the zero at the end of
18913 the string, like memchr(), so compute the length by subtracting
18914 the start address. */
18915 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18921 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18922 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18925 scratch2 = gen_reg_rtx (Pmode);
18926 scratch3 = gen_reg_rtx (Pmode);
18927 scratch4 = force_reg (Pmode, constm1_rtx);
18929 emit_move_insn (scratch3, addr);
18930 eoschar = force_reg (QImode, eoschar);
18932 src = replace_equiv_address_nv (src, scratch3);
18934 /* If .md starts supporting :P, this can be done in .md. */
18935 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18936 scratch4), UNSPEC_SCAS);
18937 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18938 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18939 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18944 /* For given symbol (function) construct code to compute address of it's PLT
18945 entry in large x86-64 PIC model. */
18947 construct_plt_address (rtx symbol)
18949 rtx tmp = gen_reg_rtx (Pmode);
18950 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18952 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18953 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18955 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18956 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18961 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18963 rtx pop, int sibcall)
18965 rtx use = NULL, call;
18967 if (pop == const0_rtx)
18969 gcc_assert (!TARGET_64BIT || !pop);
18971 if (TARGET_MACHO && !TARGET_64BIT)
18974 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18975 fnaddr = machopic_indirect_call_target (fnaddr);
18980 /* Static functions and indirect calls don't need the pic register. */
18981 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18982 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18983 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18984 use_reg (&use, pic_offset_table_rtx);
18987 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18989 rtx al = gen_rtx_REG (QImode, AX_REG);
18990 emit_move_insn (al, callarg2);
18991 use_reg (&use, al);
18994 if (ix86_cmodel == CM_LARGE_PIC
18996 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18997 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18998 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
19000 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
19001 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
19003 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
19004 fnaddr = gen_rtx_MEM (QImode, fnaddr);
19007 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
19009 call = gen_rtx_SET (VOIDmode, retval, call);
19012 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
19013 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
19014 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
19017 && ix86_cfun_abi () == MS_ABI
19018 && (!callarg2 || INTVAL (callarg2) != -2))
19020 /* We need to represent that SI and DI registers are clobbered
19022 static int clobbered_registers[] = {
19023 XMM6_REG, XMM7_REG, XMM8_REG,
19024 XMM9_REG, XMM10_REG, XMM11_REG,
19025 XMM12_REG, XMM13_REG, XMM14_REG,
19026 XMM15_REG, SI_REG, DI_REG
19029 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
19030 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
19031 UNSPEC_MS_TO_SYSV_CALL);
19035 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
19036 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
19039 (SSE_REGNO_P (clobbered_registers[i])
19041 clobbered_registers[i]));
19043 call = gen_rtx_PARALLEL (VOIDmode,
19044 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
19048 call = emit_call_insn (call);
19050 CALL_INSN_FUNCTION_USAGE (call) = use;
19054 /* Clear stack slot assignments remembered from previous functions.
19055 This is called from INIT_EXPANDERS once before RTL is emitted for each
19058 static struct machine_function *
19059 ix86_init_machine_status (void)
19061 struct machine_function *f;
19063 f = GGC_CNEW (struct machine_function);
19064 f->use_fast_prologue_epilogue_nregs = -1;
19065 f->tls_descriptor_call_expanded_p = 0;
19066 f->call_abi = ix86_abi;
19071 /* Return a MEM corresponding to a stack slot with mode MODE.
19072 Allocate a new slot if necessary.
19074 The RTL for a function can have several slots available: N is
19075 which slot to use. */
19078 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
19080 struct stack_local_entry *s;
19082 gcc_assert (n < MAX_386_STACK_LOCALS);
19084 /* Virtual slot is valid only before vregs are instantiated. */
19085 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
19087 for (s = ix86_stack_locals; s; s = s->next)
19088 if (s->mode == mode && s->n == n)
19089 return copy_rtx (s->rtl);
19091 s = (struct stack_local_entry *)
19092 ggc_alloc (sizeof (struct stack_local_entry));
19095 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
19097 s->next = ix86_stack_locals;
19098 ix86_stack_locals = s;
19102 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19104 static GTY(()) rtx ix86_tls_symbol;
19106 ix86_tls_get_addr (void)
19109 if (!ix86_tls_symbol)
19111 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
19112 (TARGET_ANY_GNU_TLS
19114 ? "___tls_get_addr"
19115 : "__tls_get_addr");
19118 return ix86_tls_symbol;
19121 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19123 static GTY(()) rtx ix86_tls_module_base_symbol;
19125 ix86_tls_module_base (void)
19128 if (!ix86_tls_module_base_symbol)
19130 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
19131 "_TLS_MODULE_BASE_");
19132 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
19133 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
19136 return ix86_tls_module_base_symbol;
19139 /* Calculate the length of the memory address in the instruction
19140 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19143 memory_address_length (rtx addr)
19145 struct ix86_address parts;
19146 rtx base, index, disp;
19150 if (GET_CODE (addr) == PRE_DEC
19151 || GET_CODE (addr) == POST_INC
19152 || GET_CODE (addr) == PRE_MODIFY
19153 || GET_CODE (addr) == POST_MODIFY)
19156 ok = ix86_decompose_address (addr, &parts);
19159 if (parts.base && GET_CODE (parts.base) == SUBREG)
19160 parts.base = SUBREG_REG (parts.base);
19161 if (parts.index && GET_CODE (parts.index) == SUBREG)
19162 parts.index = SUBREG_REG (parts.index);
19165 index = parts.index;
19170 - esp as the base always wants an index,
19171 - ebp as the base always wants a displacement,
19172 - r12 as the base always wants an index,
19173 - r13 as the base always wants a displacement. */
19175 /* Register Indirect. */
19176 if (base && !index && !disp)
19178 /* esp (for its index) and ebp (for its displacement) need
19179 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19182 && (addr == arg_pointer_rtx
19183 || addr == frame_pointer_rtx
19184 || REGNO (addr) == SP_REG
19185 || REGNO (addr) == BP_REG
19186 || REGNO (addr) == R12_REG
19187 || REGNO (addr) == R13_REG))
19191 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19192 is not disp32, but disp32(%rip), so for disp32
19193 SIB byte is needed, unless print_operand_address
19194 optimizes it into disp32(%rip) or (%rip) is implied
19196 else if (disp && !base && !index)
19203 if (GET_CODE (disp) == CONST)
19204 symbol = XEXP (disp, 0);
19205 if (GET_CODE (symbol) == PLUS
19206 && CONST_INT_P (XEXP (symbol, 1)))
19207 symbol = XEXP (symbol, 0);
19209 if (GET_CODE (symbol) != LABEL_REF
19210 && (GET_CODE (symbol) != SYMBOL_REF
19211 || SYMBOL_REF_TLS_MODEL (symbol) != 0)
19212 && (GET_CODE (symbol) != UNSPEC
19213 || (XINT (symbol, 1) != UNSPEC_GOTPCREL
19214 && XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
19221 /* Find the length of the displacement constant. */
19224 if (base && satisfies_constraint_K (disp))
19229 /* ebp always wants a displacement. Similarly r13. */
19230 else if (base && REG_P (base)
19231 && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
19234 /* An index requires the two-byte modrm form.... */
19236 /* ...like esp (or r12), which always wants an index. */
19237 || base == arg_pointer_rtx
19238 || base == frame_pointer_rtx
19239 || (base && REG_P (base)
19240 && (REGNO (base) == SP_REG || REGNO (base) == R12_REG)))
19257 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19258 is set, expect that insn have 8bit immediate alternative. */
19260 ix86_attr_length_immediate_default (rtx insn, int shortform)
19264 extract_insn_cached (insn);
19265 for (i = recog_data.n_operands - 1; i >= 0; --i)
19266 if (CONSTANT_P (recog_data.operand[i]))
19268 enum attr_mode mode = get_attr_mode (insn);
19271 if (shortform && CONST_INT_P (recog_data.operand[i]))
19273 HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
19280 ival = trunc_int_for_mode (ival, HImode);
19283 ival = trunc_int_for_mode (ival, SImode);
19288 if (IN_RANGE (ival, -128, 127))
19305 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19310 fatal_insn ("unknown insn mode", insn);
19315 /* Compute default value for "length_address" attribute. */
19317 ix86_attr_length_address_default (rtx insn)
19321 if (get_attr_type (insn) == TYPE_LEA)
19323 rtx set = PATTERN (insn), addr;
19325 if (GET_CODE (set) == PARALLEL)
19326 set = XVECEXP (set, 0, 0);
19328 gcc_assert (GET_CODE (set) == SET);
19330 addr = SET_SRC (set);
19331 if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI)
19333 if (GET_CODE (addr) == ZERO_EXTEND)
19334 addr = XEXP (addr, 0);
19335 if (GET_CODE (addr) == SUBREG)
19336 addr = SUBREG_REG (addr);
19339 return memory_address_length (addr);
19342 extract_insn_cached (insn);
19343 for (i = recog_data.n_operands - 1; i >= 0; --i)
19344 if (MEM_P (recog_data.operand[i]))
19346 constrain_operands_cached (reload_completed);
19347 if (which_alternative != -1)
19349 const char *constraints = recog_data.constraints[i];
19350 int alt = which_alternative;
19352 while (*constraints == '=' || *constraints == '+')
19355 while (*constraints++ != ',')
19357 /* Skip ignored operands. */
19358 if (*constraints == 'X')
19361 return memory_address_length (XEXP (recog_data.operand[i], 0));
19366 /* Compute default value for "length_vex" attribute. It includes
19367 2 or 3 byte VEX prefix and 1 opcode byte. */
19370 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19375 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19376 byte VEX prefix. */
19377 if (!has_0f_opcode || has_vex_w)
19380 /* We can always use 2 byte VEX prefix in 32bit. */
19384 extract_insn_cached (insn);
19386 for (i = recog_data.n_operands - 1; i >= 0; --i)
19387 if (REG_P (recog_data.operand[i]))
19389 /* REX.W bit uses 3 byte VEX prefix. */
19390 if (GET_MODE (recog_data.operand[i]) == DImode
19391 && GENERAL_REG_P (recog_data.operand[i]))
19396 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19397 if (MEM_P (recog_data.operand[i])
19398 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19405 /* Return the maximum number of instructions a cpu can issue. */
19408 ix86_issue_rate (void)
19412 case PROCESSOR_PENTIUM:
19413 case PROCESSOR_ATOM:
19417 case PROCESSOR_PENTIUMPRO:
19418 case PROCESSOR_PENTIUM4:
19419 case PROCESSOR_ATHLON:
19421 case PROCESSOR_AMDFAM10:
19422 case PROCESSOR_NOCONA:
19423 case PROCESSOR_GENERIC32:
19424 case PROCESSOR_GENERIC64:
19427 case PROCESSOR_CORE2:
19435 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19436 by DEP_INSN and nothing set by DEP_INSN. */
19439 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19443 /* Simplify the test for uninteresting insns. */
19444 if (insn_type != TYPE_SETCC
19445 && insn_type != TYPE_ICMOV
19446 && insn_type != TYPE_FCMOV
19447 && insn_type != TYPE_IBR)
19450 if ((set = single_set (dep_insn)) != 0)
19452 set = SET_DEST (set);
19455 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19456 && XVECLEN (PATTERN (dep_insn), 0) == 2
19457 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19458 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19460 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19461 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19466 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19469 /* This test is true if the dependent insn reads the flags but
19470 not any other potentially set register. */
19471 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19474 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19480 /* Return true iff USE_INSN has a memory address with operands set by
19484 ix86_agi_dependent (rtx set_insn, rtx use_insn)
19487 extract_insn_cached (use_insn);
19488 for (i = recog_data.n_operands - 1; i >= 0; --i)
19489 if (MEM_P (recog_data.operand[i]))
19491 rtx addr = XEXP (recog_data.operand[i], 0);
19492 return modified_in_p (addr, set_insn) != 0;
19498 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19500 enum attr_type insn_type, dep_insn_type;
19501 enum attr_memory memory;
19503 int dep_insn_code_number;
19505 /* Anti and output dependencies have zero cost on all CPUs. */
19506 if (REG_NOTE_KIND (link) != 0)
19509 dep_insn_code_number = recog_memoized (dep_insn);
19511 /* If we can't recognize the insns, we can't really do anything. */
19512 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19515 insn_type = get_attr_type (insn);
19516 dep_insn_type = get_attr_type (dep_insn);
19520 case PROCESSOR_PENTIUM:
19521 /* Address Generation Interlock adds a cycle of latency. */
19522 if (insn_type == TYPE_LEA)
19524 rtx addr = PATTERN (insn);
19526 if (GET_CODE (addr) == PARALLEL)
19527 addr = XVECEXP (addr, 0, 0);
19529 gcc_assert (GET_CODE (addr) == SET);
19531 addr = SET_SRC (addr);
19532 if (modified_in_p (addr, dep_insn))
19535 else if (ix86_agi_dependent (dep_insn, insn))
19538 /* ??? Compares pair with jump/setcc. */
19539 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19542 /* Floating point stores require value to be ready one cycle earlier. */
19543 if (insn_type == TYPE_FMOV
19544 && get_attr_memory (insn) == MEMORY_STORE
19545 && !ix86_agi_dependent (dep_insn, insn))
19549 case PROCESSOR_PENTIUMPRO:
19550 memory = get_attr_memory (insn);
19552 /* INT->FP conversion is expensive. */
19553 if (get_attr_fp_int_src (dep_insn))
19556 /* There is one cycle extra latency between an FP op and a store. */
19557 if (insn_type == TYPE_FMOV
19558 && (set = single_set (dep_insn)) != NULL_RTX
19559 && (set2 = single_set (insn)) != NULL_RTX
19560 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19561 && MEM_P (SET_DEST (set2)))
19564 /* Show ability of reorder buffer to hide latency of load by executing
19565 in parallel with previous instruction in case
19566 previous instruction is not needed to compute the address. */
19567 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19568 && !ix86_agi_dependent (dep_insn, insn))
19570 /* Claim moves to take one cycle, as core can issue one load
19571 at time and the next load can start cycle later. */
19572 if (dep_insn_type == TYPE_IMOV
19573 || dep_insn_type == TYPE_FMOV)
19581 memory = get_attr_memory (insn);
19583 /* The esp dependency is resolved before the instruction is really
19585 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19586 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19589 /* INT->FP conversion is expensive. */
19590 if (get_attr_fp_int_src (dep_insn))
19593 /* Show ability of reorder buffer to hide latency of load by executing
19594 in parallel with previous instruction in case
19595 previous instruction is not needed to compute the address. */
19596 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19597 && !ix86_agi_dependent (dep_insn, insn))
19599 /* Claim moves to take one cycle, as core can issue one load
19600 at time and the next load can start cycle later. */
19601 if (dep_insn_type == TYPE_IMOV
19602 || dep_insn_type == TYPE_FMOV)
19611 case PROCESSOR_ATHLON:
19613 case PROCESSOR_AMDFAM10:
19614 case PROCESSOR_ATOM:
19615 case PROCESSOR_GENERIC32:
19616 case PROCESSOR_GENERIC64:
19617 memory = get_attr_memory (insn);
19619 /* Show ability of reorder buffer to hide latency of load by executing
19620 in parallel with previous instruction in case
19621 previous instruction is not needed to compute the address. */
19622 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19623 && !ix86_agi_dependent (dep_insn, insn))
19625 enum attr_unit unit = get_attr_unit (insn);
19628 /* Because of the difference between the length of integer and
19629 floating unit pipeline preparation stages, the memory operands
19630 for floating point are cheaper.
19632 ??? For Athlon it the difference is most probably 2. */
19633 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19636 loadcost = TARGET_ATHLON ? 2 : 0;
19638 if (cost >= loadcost)
19651 /* How many alternative schedules to try. This should be as wide as the
19652 scheduling freedom in the DFA, but no wider. Making this value too
19653 large results extra work for the scheduler. */
19656 ia32_multipass_dfa_lookahead (void)
19660 case PROCESSOR_PENTIUM:
19663 case PROCESSOR_PENTIUMPRO:
19673 /* Compute the alignment given to a constant that is being placed in memory.
19674 EXP is the constant and ALIGN is the alignment that the object would
19676 The value of this function is used instead of that alignment to align
19680 ix86_constant_alignment (tree exp, int align)
19682 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19683 || TREE_CODE (exp) == INTEGER_CST)
19685 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19687 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19690 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19691 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19692 return BITS_PER_WORD;
19697 /* Compute the alignment for a static variable.
19698 TYPE is the data type, and ALIGN is the alignment that
19699 the object would ordinarily have. The value of this function is used
19700 instead of that alignment to align the object. */
19703 ix86_data_alignment (tree type, int align)
19705 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19707 if (AGGREGATE_TYPE_P (type)
19708 && TYPE_SIZE (type)
19709 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19710 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19711 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19712 && align < max_align)
19715 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19716 to 16byte boundary. */
19719 if (AGGREGATE_TYPE_P (type)
19720 && TYPE_SIZE (type)
19721 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19722 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19723 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19727 if (TREE_CODE (type) == ARRAY_TYPE)
19729 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19731 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19734 else if (TREE_CODE (type) == COMPLEX_TYPE)
19737 if (TYPE_MODE (type) == DCmode && align < 64)
19739 if ((TYPE_MODE (type) == XCmode
19740 || TYPE_MODE (type) == TCmode) && align < 128)
19743 else if ((TREE_CODE (type) == RECORD_TYPE
19744 || TREE_CODE (type) == UNION_TYPE
19745 || TREE_CODE (type) == QUAL_UNION_TYPE)
19746 && TYPE_FIELDS (type))
19748 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19750 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19753 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19754 || TREE_CODE (type) == INTEGER_TYPE)
19756 if (TYPE_MODE (type) == DFmode && align < 64)
19758 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19765 /* Compute the alignment for a local variable or a stack slot. EXP is
19766 the data type or decl itself, MODE is the widest mode available and
19767 ALIGN is the alignment that the object would ordinarily have. The
19768 value of this macro is used instead of that alignment to align the
19772 ix86_local_alignment (tree exp, enum machine_mode mode,
19773 unsigned int align)
19777 if (exp && DECL_P (exp))
19779 type = TREE_TYPE (exp);
19788 /* Don't do dynamic stack realignment for long long objects with
19789 -mpreferred-stack-boundary=2. */
19792 && ix86_preferred_stack_boundary < 64
19793 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19794 && (!type || !TYPE_USER_ALIGN (type))
19795 && (!decl || !DECL_USER_ALIGN (decl)))
19798 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19799 register in MODE. We will return the largest alignment of XF
19803 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19804 align = GET_MODE_ALIGNMENT (DFmode);
19808 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19809 to 16byte boundary. */
19812 if (AGGREGATE_TYPE_P (type)
19813 && TYPE_SIZE (type)
19814 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19815 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19816 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19819 if (TREE_CODE (type) == ARRAY_TYPE)
19821 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19823 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19826 else if (TREE_CODE (type) == COMPLEX_TYPE)
19828 if (TYPE_MODE (type) == DCmode && align < 64)
19830 if ((TYPE_MODE (type) == XCmode
19831 || TYPE_MODE (type) == TCmode) && align < 128)
19834 else if ((TREE_CODE (type) == RECORD_TYPE
19835 || TREE_CODE (type) == UNION_TYPE
19836 || TREE_CODE (type) == QUAL_UNION_TYPE)
19837 && TYPE_FIELDS (type))
19839 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19841 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19844 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19845 || TREE_CODE (type) == INTEGER_TYPE)
19848 if (TYPE_MODE (type) == DFmode && align < 64)
19850 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19856 /* Compute the minimum required alignment for dynamic stack realignment
19857 purposes for a local variable, parameter or a stack slot. EXP is
19858 the data type or decl itself, MODE is its mode and ALIGN is the
19859 alignment that the object would ordinarily have. */
19862 ix86_minimum_alignment (tree exp, enum machine_mode mode,
19863 unsigned int align)
19867 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
19870 if (exp && DECL_P (exp))
19872 type = TREE_TYPE (exp);
19881 /* Don't do dynamic stack realignment for long long objects with
19882 -mpreferred-stack-boundary=2. */
19883 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
19884 && (!type || !TYPE_USER_ALIGN (type))
19885 && (!decl || !DECL_USER_ALIGN (decl)))
19891 /* Find a location for the static chain incoming to a nested function.
19892 This is a register, unless all free registers are used by arguments. */
19895 ix86_static_chain (const_tree fndecl, bool incoming_p)
19899 if (!DECL_STATIC_CHAIN (fndecl))
19904 /* We always use R10 in 64-bit mode. */
19910 /* By default in 32-bit mode we use ECX to pass the static chain. */
19913 fntype = TREE_TYPE (fndecl);
19914 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
19916 /* Fastcall functions use ecx/edx for arguments, which leaves
19917 us with EAX for the static chain. */
19920 else if (ix86_function_regparm (fntype, fndecl) == 3)
19922 /* For regparm 3, we have no free call-clobbered registers in
19923 which to store the static chain. In order to implement this,
19924 we have the trampoline push the static chain to the stack.
19925 However, we can't push a value below the return address when
19926 we call the nested function directly, so we have to use an
19927 alternate entry point. For this we use ESI, and have the
19928 alternate entry point push ESI, so that things appear the
19929 same once we're executing the nested function. */
19932 if (fndecl == current_function_decl)
19933 ix86_static_chain_on_stack = true;
19934 return gen_frame_mem (SImode,
19935 plus_constant (arg_pointer_rtx, -8));
19941 return gen_rtx_REG (Pmode, regno);
19944 /* Emit RTL insns to initialize the variable parts of a trampoline.
19945 FNDECL is the decl of the target address; M_TRAMP is a MEM for
19946 the trampoline, and CHAIN_VALUE is an RTX for the static chain
19947 to be passed to the target function. */
19950 ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
19954 fnaddr = XEXP (DECL_RTL (fndecl), 0);
19961 /* Depending on the static chain location, either load a register
19962 with a constant, or push the constant to the stack. All of the
19963 instructions are the same size. */
19964 chain = ix86_static_chain (fndecl, true);
19967 if (REGNO (chain) == CX_REG)
19969 else if (REGNO (chain) == AX_REG)
19972 gcc_unreachable ();
19977 mem = adjust_address (m_tramp, QImode, 0);
19978 emit_move_insn (mem, gen_int_mode (opcode, QImode));
19980 mem = adjust_address (m_tramp, SImode, 1);
19981 emit_move_insn (mem, chain_value);
19983 /* Compute offset from the end of the jmp to the target function.
19984 In the case in which the trampoline stores the static chain on
19985 the stack, we need to skip the first insn which pushes the
19986 (call-saved) register static chain; this push is 1 byte. */
19987 disp = expand_binop (SImode, sub_optab, fnaddr,
19988 plus_constant (XEXP (m_tramp, 0),
19989 MEM_P (chain) ? 9 : 10),
19990 NULL_RTX, 1, OPTAB_DIRECT);
19992 mem = adjust_address (m_tramp, QImode, 5);
19993 emit_move_insn (mem, gen_int_mode (0xe9, QImode));
19995 mem = adjust_address (m_tramp, SImode, 6);
19996 emit_move_insn (mem, disp);
20002 /* Load the function address to r11. Try to load address using
20003 the shorter movl instead of movabs. We may want to support
20004 movq for kernel mode, but kernel does not use trampolines at
20006 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
20008 fnaddr = copy_to_mode_reg (DImode, fnaddr);
20010 mem = adjust_address (m_tramp, HImode, offset);
20011 emit_move_insn (mem, gen_int_mode (0xbb41, HImode));
20013 mem = adjust_address (m_tramp, SImode, offset + 2);
20014 emit_move_insn (mem, gen_lowpart (SImode, fnaddr));
20019 mem = adjust_address (m_tramp, HImode, offset);
20020 emit_move_insn (mem, gen_int_mode (0xbb49, HImode));
20022 mem = adjust_address (m_tramp, DImode, offset + 2);
20023 emit_move_insn (mem, fnaddr);
20027 /* Load static chain using movabs to r10. */
20028 mem = adjust_address (m_tramp, HImode, offset);
20029 emit_move_insn (mem, gen_int_mode (0xba49, HImode));
20031 mem = adjust_address (m_tramp, DImode, offset + 2);
20032 emit_move_insn (mem, chain_value);
20035 /* Jump to r11; the last (unused) byte is a nop, only there to
20036 pad the write out to a single 32-bit store. */
20037 mem = adjust_address (m_tramp, SImode, offset);
20038 emit_move_insn (mem, gen_int_mode (0x90e3ff49, SImode));
20041 gcc_assert (offset <= TRAMPOLINE_SIZE);
20044 #ifdef ENABLE_EXECUTE_STACK
20045 #ifdef CHECK_EXECUTE_STACK_ENABLED
20046 if (CHECK_EXECUTE_STACK_ENABLED)
20048 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
20049 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
20053 /* Codes for all the SSE/MMX builtins. */
20056 IX86_BUILTIN_ADDPS,
20057 IX86_BUILTIN_ADDSS,
20058 IX86_BUILTIN_DIVPS,
20059 IX86_BUILTIN_DIVSS,
20060 IX86_BUILTIN_MULPS,
20061 IX86_BUILTIN_MULSS,
20062 IX86_BUILTIN_SUBPS,
20063 IX86_BUILTIN_SUBSS,
20065 IX86_BUILTIN_CMPEQPS,
20066 IX86_BUILTIN_CMPLTPS,
20067 IX86_BUILTIN_CMPLEPS,
20068 IX86_BUILTIN_CMPGTPS,
20069 IX86_BUILTIN_CMPGEPS,
20070 IX86_BUILTIN_CMPNEQPS,
20071 IX86_BUILTIN_CMPNLTPS,
20072 IX86_BUILTIN_CMPNLEPS,
20073 IX86_BUILTIN_CMPNGTPS,
20074 IX86_BUILTIN_CMPNGEPS,
20075 IX86_BUILTIN_CMPORDPS,
20076 IX86_BUILTIN_CMPUNORDPS,
20077 IX86_BUILTIN_CMPEQSS,
20078 IX86_BUILTIN_CMPLTSS,
20079 IX86_BUILTIN_CMPLESS,
20080 IX86_BUILTIN_CMPNEQSS,
20081 IX86_BUILTIN_CMPNLTSS,
20082 IX86_BUILTIN_CMPNLESS,
20083 IX86_BUILTIN_CMPNGTSS,
20084 IX86_BUILTIN_CMPNGESS,
20085 IX86_BUILTIN_CMPORDSS,
20086 IX86_BUILTIN_CMPUNORDSS,
20088 IX86_BUILTIN_COMIEQSS,
20089 IX86_BUILTIN_COMILTSS,
20090 IX86_BUILTIN_COMILESS,
20091 IX86_BUILTIN_COMIGTSS,
20092 IX86_BUILTIN_COMIGESS,
20093 IX86_BUILTIN_COMINEQSS,
20094 IX86_BUILTIN_UCOMIEQSS,
20095 IX86_BUILTIN_UCOMILTSS,
20096 IX86_BUILTIN_UCOMILESS,
20097 IX86_BUILTIN_UCOMIGTSS,
20098 IX86_BUILTIN_UCOMIGESS,
20099 IX86_BUILTIN_UCOMINEQSS,
20101 IX86_BUILTIN_CVTPI2PS,
20102 IX86_BUILTIN_CVTPS2PI,
20103 IX86_BUILTIN_CVTSI2SS,
20104 IX86_BUILTIN_CVTSI642SS,
20105 IX86_BUILTIN_CVTSS2SI,
20106 IX86_BUILTIN_CVTSS2SI64,
20107 IX86_BUILTIN_CVTTPS2PI,
20108 IX86_BUILTIN_CVTTSS2SI,
20109 IX86_BUILTIN_CVTTSS2SI64,
20111 IX86_BUILTIN_MAXPS,
20112 IX86_BUILTIN_MAXSS,
20113 IX86_BUILTIN_MINPS,
20114 IX86_BUILTIN_MINSS,
20116 IX86_BUILTIN_LOADUPS,
20117 IX86_BUILTIN_STOREUPS,
20118 IX86_BUILTIN_MOVSS,
20120 IX86_BUILTIN_MOVHLPS,
20121 IX86_BUILTIN_MOVLHPS,
20122 IX86_BUILTIN_LOADHPS,
20123 IX86_BUILTIN_LOADLPS,
20124 IX86_BUILTIN_STOREHPS,
20125 IX86_BUILTIN_STORELPS,
20127 IX86_BUILTIN_MASKMOVQ,
20128 IX86_BUILTIN_MOVMSKPS,
20129 IX86_BUILTIN_PMOVMSKB,
20131 IX86_BUILTIN_MOVNTPS,
20132 IX86_BUILTIN_MOVNTQ,
20134 IX86_BUILTIN_LOADDQU,
20135 IX86_BUILTIN_STOREDQU,
20137 IX86_BUILTIN_PACKSSWB,
20138 IX86_BUILTIN_PACKSSDW,
20139 IX86_BUILTIN_PACKUSWB,
20141 IX86_BUILTIN_PADDB,
20142 IX86_BUILTIN_PADDW,
20143 IX86_BUILTIN_PADDD,
20144 IX86_BUILTIN_PADDQ,
20145 IX86_BUILTIN_PADDSB,
20146 IX86_BUILTIN_PADDSW,
20147 IX86_BUILTIN_PADDUSB,
20148 IX86_BUILTIN_PADDUSW,
20149 IX86_BUILTIN_PSUBB,
20150 IX86_BUILTIN_PSUBW,
20151 IX86_BUILTIN_PSUBD,
20152 IX86_BUILTIN_PSUBQ,
20153 IX86_BUILTIN_PSUBSB,
20154 IX86_BUILTIN_PSUBSW,
20155 IX86_BUILTIN_PSUBUSB,
20156 IX86_BUILTIN_PSUBUSW,
20159 IX86_BUILTIN_PANDN,
20163 IX86_BUILTIN_PAVGB,
20164 IX86_BUILTIN_PAVGW,
20166 IX86_BUILTIN_PCMPEQB,
20167 IX86_BUILTIN_PCMPEQW,
20168 IX86_BUILTIN_PCMPEQD,
20169 IX86_BUILTIN_PCMPGTB,
20170 IX86_BUILTIN_PCMPGTW,
20171 IX86_BUILTIN_PCMPGTD,
20173 IX86_BUILTIN_PMADDWD,
20175 IX86_BUILTIN_PMAXSW,
20176 IX86_BUILTIN_PMAXUB,
20177 IX86_BUILTIN_PMINSW,
20178 IX86_BUILTIN_PMINUB,
20180 IX86_BUILTIN_PMULHUW,
20181 IX86_BUILTIN_PMULHW,
20182 IX86_BUILTIN_PMULLW,
20184 IX86_BUILTIN_PSADBW,
20185 IX86_BUILTIN_PSHUFW,
20187 IX86_BUILTIN_PSLLW,
20188 IX86_BUILTIN_PSLLD,
20189 IX86_BUILTIN_PSLLQ,
20190 IX86_BUILTIN_PSRAW,
20191 IX86_BUILTIN_PSRAD,
20192 IX86_BUILTIN_PSRLW,
20193 IX86_BUILTIN_PSRLD,
20194 IX86_BUILTIN_PSRLQ,
20195 IX86_BUILTIN_PSLLWI,
20196 IX86_BUILTIN_PSLLDI,
20197 IX86_BUILTIN_PSLLQI,
20198 IX86_BUILTIN_PSRAWI,
20199 IX86_BUILTIN_PSRADI,
20200 IX86_BUILTIN_PSRLWI,
20201 IX86_BUILTIN_PSRLDI,
20202 IX86_BUILTIN_PSRLQI,
20204 IX86_BUILTIN_PUNPCKHBW,
20205 IX86_BUILTIN_PUNPCKHWD,
20206 IX86_BUILTIN_PUNPCKHDQ,
20207 IX86_BUILTIN_PUNPCKLBW,
20208 IX86_BUILTIN_PUNPCKLWD,
20209 IX86_BUILTIN_PUNPCKLDQ,
20211 IX86_BUILTIN_SHUFPS,
20213 IX86_BUILTIN_RCPPS,
20214 IX86_BUILTIN_RCPSS,
20215 IX86_BUILTIN_RSQRTPS,
20216 IX86_BUILTIN_RSQRTPS_NR,
20217 IX86_BUILTIN_RSQRTSS,
20218 IX86_BUILTIN_RSQRTF,
20219 IX86_BUILTIN_SQRTPS,
20220 IX86_BUILTIN_SQRTPS_NR,
20221 IX86_BUILTIN_SQRTSS,
20223 IX86_BUILTIN_UNPCKHPS,
20224 IX86_BUILTIN_UNPCKLPS,
20226 IX86_BUILTIN_ANDPS,
20227 IX86_BUILTIN_ANDNPS,
20229 IX86_BUILTIN_XORPS,
20232 IX86_BUILTIN_LDMXCSR,
20233 IX86_BUILTIN_STMXCSR,
20234 IX86_BUILTIN_SFENCE,
20236 /* 3DNow! Original */
20237 IX86_BUILTIN_FEMMS,
20238 IX86_BUILTIN_PAVGUSB,
20239 IX86_BUILTIN_PF2ID,
20240 IX86_BUILTIN_PFACC,
20241 IX86_BUILTIN_PFADD,
20242 IX86_BUILTIN_PFCMPEQ,
20243 IX86_BUILTIN_PFCMPGE,
20244 IX86_BUILTIN_PFCMPGT,
20245 IX86_BUILTIN_PFMAX,
20246 IX86_BUILTIN_PFMIN,
20247 IX86_BUILTIN_PFMUL,
20248 IX86_BUILTIN_PFRCP,
20249 IX86_BUILTIN_PFRCPIT1,
20250 IX86_BUILTIN_PFRCPIT2,
20251 IX86_BUILTIN_PFRSQIT1,
20252 IX86_BUILTIN_PFRSQRT,
20253 IX86_BUILTIN_PFSUB,
20254 IX86_BUILTIN_PFSUBR,
20255 IX86_BUILTIN_PI2FD,
20256 IX86_BUILTIN_PMULHRW,
20258 /* 3DNow! Athlon Extensions */
20259 IX86_BUILTIN_PF2IW,
20260 IX86_BUILTIN_PFNACC,
20261 IX86_BUILTIN_PFPNACC,
20262 IX86_BUILTIN_PI2FW,
20263 IX86_BUILTIN_PSWAPDSI,
20264 IX86_BUILTIN_PSWAPDSF,
20267 IX86_BUILTIN_ADDPD,
20268 IX86_BUILTIN_ADDSD,
20269 IX86_BUILTIN_DIVPD,
20270 IX86_BUILTIN_DIVSD,
20271 IX86_BUILTIN_MULPD,
20272 IX86_BUILTIN_MULSD,
20273 IX86_BUILTIN_SUBPD,
20274 IX86_BUILTIN_SUBSD,
20276 IX86_BUILTIN_CMPEQPD,
20277 IX86_BUILTIN_CMPLTPD,
20278 IX86_BUILTIN_CMPLEPD,
20279 IX86_BUILTIN_CMPGTPD,
20280 IX86_BUILTIN_CMPGEPD,
20281 IX86_BUILTIN_CMPNEQPD,
20282 IX86_BUILTIN_CMPNLTPD,
20283 IX86_BUILTIN_CMPNLEPD,
20284 IX86_BUILTIN_CMPNGTPD,
20285 IX86_BUILTIN_CMPNGEPD,
20286 IX86_BUILTIN_CMPORDPD,
20287 IX86_BUILTIN_CMPUNORDPD,
20288 IX86_BUILTIN_CMPEQSD,
20289 IX86_BUILTIN_CMPLTSD,
20290 IX86_BUILTIN_CMPLESD,
20291 IX86_BUILTIN_CMPNEQSD,
20292 IX86_BUILTIN_CMPNLTSD,
20293 IX86_BUILTIN_CMPNLESD,
20294 IX86_BUILTIN_CMPORDSD,
20295 IX86_BUILTIN_CMPUNORDSD,
20297 IX86_BUILTIN_COMIEQSD,
20298 IX86_BUILTIN_COMILTSD,
20299 IX86_BUILTIN_COMILESD,
20300 IX86_BUILTIN_COMIGTSD,
20301 IX86_BUILTIN_COMIGESD,
20302 IX86_BUILTIN_COMINEQSD,
20303 IX86_BUILTIN_UCOMIEQSD,
20304 IX86_BUILTIN_UCOMILTSD,
20305 IX86_BUILTIN_UCOMILESD,
20306 IX86_BUILTIN_UCOMIGTSD,
20307 IX86_BUILTIN_UCOMIGESD,
20308 IX86_BUILTIN_UCOMINEQSD,
20310 IX86_BUILTIN_MAXPD,
20311 IX86_BUILTIN_MAXSD,
20312 IX86_BUILTIN_MINPD,
20313 IX86_BUILTIN_MINSD,
20315 IX86_BUILTIN_ANDPD,
20316 IX86_BUILTIN_ANDNPD,
20318 IX86_BUILTIN_XORPD,
20320 IX86_BUILTIN_SQRTPD,
20321 IX86_BUILTIN_SQRTSD,
20323 IX86_BUILTIN_UNPCKHPD,
20324 IX86_BUILTIN_UNPCKLPD,
20326 IX86_BUILTIN_SHUFPD,
20328 IX86_BUILTIN_LOADUPD,
20329 IX86_BUILTIN_STOREUPD,
20330 IX86_BUILTIN_MOVSD,
20332 IX86_BUILTIN_LOADHPD,
20333 IX86_BUILTIN_LOADLPD,
20335 IX86_BUILTIN_CVTDQ2PD,
20336 IX86_BUILTIN_CVTDQ2PS,
20338 IX86_BUILTIN_CVTPD2DQ,
20339 IX86_BUILTIN_CVTPD2PI,
20340 IX86_BUILTIN_CVTPD2PS,
20341 IX86_BUILTIN_CVTTPD2DQ,
20342 IX86_BUILTIN_CVTTPD2PI,
20344 IX86_BUILTIN_CVTPI2PD,
20345 IX86_BUILTIN_CVTSI2SD,
20346 IX86_BUILTIN_CVTSI642SD,
20348 IX86_BUILTIN_CVTSD2SI,
20349 IX86_BUILTIN_CVTSD2SI64,
20350 IX86_BUILTIN_CVTSD2SS,
20351 IX86_BUILTIN_CVTSS2SD,
20352 IX86_BUILTIN_CVTTSD2SI,
20353 IX86_BUILTIN_CVTTSD2SI64,
20355 IX86_BUILTIN_CVTPS2DQ,
20356 IX86_BUILTIN_CVTPS2PD,
20357 IX86_BUILTIN_CVTTPS2DQ,
20359 IX86_BUILTIN_MOVNTI,
20360 IX86_BUILTIN_MOVNTPD,
20361 IX86_BUILTIN_MOVNTDQ,
20363 IX86_BUILTIN_MOVQ128,
20366 IX86_BUILTIN_MASKMOVDQU,
20367 IX86_BUILTIN_MOVMSKPD,
20368 IX86_BUILTIN_PMOVMSKB128,
20370 IX86_BUILTIN_PACKSSWB128,
20371 IX86_BUILTIN_PACKSSDW128,
20372 IX86_BUILTIN_PACKUSWB128,
20374 IX86_BUILTIN_PADDB128,
20375 IX86_BUILTIN_PADDW128,
20376 IX86_BUILTIN_PADDD128,
20377 IX86_BUILTIN_PADDQ128,
20378 IX86_BUILTIN_PADDSB128,
20379 IX86_BUILTIN_PADDSW128,
20380 IX86_BUILTIN_PADDUSB128,
20381 IX86_BUILTIN_PADDUSW128,
20382 IX86_BUILTIN_PSUBB128,
20383 IX86_BUILTIN_PSUBW128,
20384 IX86_BUILTIN_PSUBD128,
20385 IX86_BUILTIN_PSUBQ128,
20386 IX86_BUILTIN_PSUBSB128,
20387 IX86_BUILTIN_PSUBSW128,
20388 IX86_BUILTIN_PSUBUSB128,
20389 IX86_BUILTIN_PSUBUSW128,
20391 IX86_BUILTIN_PAND128,
20392 IX86_BUILTIN_PANDN128,
20393 IX86_BUILTIN_POR128,
20394 IX86_BUILTIN_PXOR128,
20396 IX86_BUILTIN_PAVGB128,
20397 IX86_BUILTIN_PAVGW128,
20399 IX86_BUILTIN_PCMPEQB128,
20400 IX86_BUILTIN_PCMPEQW128,
20401 IX86_BUILTIN_PCMPEQD128,
20402 IX86_BUILTIN_PCMPGTB128,
20403 IX86_BUILTIN_PCMPGTW128,
20404 IX86_BUILTIN_PCMPGTD128,
20406 IX86_BUILTIN_PMADDWD128,
20408 IX86_BUILTIN_PMAXSW128,
20409 IX86_BUILTIN_PMAXUB128,
20410 IX86_BUILTIN_PMINSW128,
20411 IX86_BUILTIN_PMINUB128,
20413 IX86_BUILTIN_PMULUDQ,
20414 IX86_BUILTIN_PMULUDQ128,
20415 IX86_BUILTIN_PMULHUW128,
20416 IX86_BUILTIN_PMULHW128,
20417 IX86_BUILTIN_PMULLW128,
20419 IX86_BUILTIN_PSADBW128,
20420 IX86_BUILTIN_PSHUFHW,
20421 IX86_BUILTIN_PSHUFLW,
20422 IX86_BUILTIN_PSHUFD,
20424 IX86_BUILTIN_PSLLDQI128,
20425 IX86_BUILTIN_PSLLWI128,
20426 IX86_BUILTIN_PSLLDI128,
20427 IX86_BUILTIN_PSLLQI128,
20428 IX86_BUILTIN_PSRAWI128,
20429 IX86_BUILTIN_PSRADI128,
20430 IX86_BUILTIN_PSRLDQI128,
20431 IX86_BUILTIN_PSRLWI128,
20432 IX86_BUILTIN_PSRLDI128,
20433 IX86_BUILTIN_PSRLQI128,
20435 IX86_BUILTIN_PSLLDQ128,
20436 IX86_BUILTIN_PSLLW128,
20437 IX86_BUILTIN_PSLLD128,
20438 IX86_BUILTIN_PSLLQ128,
20439 IX86_BUILTIN_PSRAW128,
20440 IX86_BUILTIN_PSRAD128,
20441 IX86_BUILTIN_PSRLW128,
20442 IX86_BUILTIN_PSRLD128,
20443 IX86_BUILTIN_PSRLQ128,
20445 IX86_BUILTIN_PUNPCKHBW128,
20446 IX86_BUILTIN_PUNPCKHWD128,
20447 IX86_BUILTIN_PUNPCKHDQ128,
20448 IX86_BUILTIN_PUNPCKHQDQ128,
20449 IX86_BUILTIN_PUNPCKLBW128,
20450 IX86_BUILTIN_PUNPCKLWD128,
20451 IX86_BUILTIN_PUNPCKLDQ128,
20452 IX86_BUILTIN_PUNPCKLQDQ128,
20454 IX86_BUILTIN_CLFLUSH,
20455 IX86_BUILTIN_MFENCE,
20456 IX86_BUILTIN_LFENCE,
20458 IX86_BUILTIN_BSRSI,
20459 IX86_BUILTIN_BSRDI,
20460 IX86_BUILTIN_RDPMC,
20461 IX86_BUILTIN_RDTSC,
20462 IX86_BUILTIN_RDTSCP,
20463 IX86_BUILTIN_ROLQI,
20464 IX86_BUILTIN_ROLHI,
20465 IX86_BUILTIN_RORQI,
20466 IX86_BUILTIN_RORHI,
20469 IX86_BUILTIN_ADDSUBPS,
20470 IX86_BUILTIN_HADDPS,
20471 IX86_BUILTIN_HSUBPS,
20472 IX86_BUILTIN_MOVSHDUP,
20473 IX86_BUILTIN_MOVSLDUP,
20474 IX86_BUILTIN_ADDSUBPD,
20475 IX86_BUILTIN_HADDPD,
20476 IX86_BUILTIN_HSUBPD,
20477 IX86_BUILTIN_LDDQU,
20479 IX86_BUILTIN_MONITOR,
20480 IX86_BUILTIN_MWAIT,
20483 IX86_BUILTIN_PHADDW,
20484 IX86_BUILTIN_PHADDD,
20485 IX86_BUILTIN_PHADDSW,
20486 IX86_BUILTIN_PHSUBW,
20487 IX86_BUILTIN_PHSUBD,
20488 IX86_BUILTIN_PHSUBSW,
20489 IX86_BUILTIN_PMADDUBSW,
20490 IX86_BUILTIN_PMULHRSW,
20491 IX86_BUILTIN_PSHUFB,
20492 IX86_BUILTIN_PSIGNB,
20493 IX86_BUILTIN_PSIGNW,
20494 IX86_BUILTIN_PSIGND,
20495 IX86_BUILTIN_PALIGNR,
20496 IX86_BUILTIN_PABSB,
20497 IX86_BUILTIN_PABSW,
20498 IX86_BUILTIN_PABSD,
20500 IX86_BUILTIN_PHADDW128,
20501 IX86_BUILTIN_PHADDD128,
20502 IX86_BUILTIN_PHADDSW128,
20503 IX86_BUILTIN_PHSUBW128,
20504 IX86_BUILTIN_PHSUBD128,
20505 IX86_BUILTIN_PHSUBSW128,
20506 IX86_BUILTIN_PMADDUBSW128,
20507 IX86_BUILTIN_PMULHRSW128,
20508 IX86_BUILTIN_PSHUFB128,
20509 IX86_BUILTIN_PSIGNB128,
20510 IX86_BUILTIN_PSIGNW128,
20511 IX86_BUILTIN_PSIGND128,
20512 IX86_BUILTIN_PALIGNR128,
20513 IX86_BUILTIN_PABSB128,
20514 IX86_BUILTIN_PABSW128,
20515 IX86_BUILTIN_PABSD128,
20517 /* AMDFAM10 - SSE4A New Instructions. */
20518 IX86_BUILTIN_MOVNTSD,
20519 IX86_BUILTIN_MOVNTSS,
20520 IX86_BUILTIN_EXTRQI,
20521 IX86_BUILTIN_EXTRQ,
20522 IX86_BUILTIN_INSERTQI,
20523 IX86_BUILTIN_INSERTQ,
20526 IX86_BUILTIN_BLENDPD,
20527 IX86_BUILTIN_BLENDPS,
20528 IX86_BUILTIN_BLENDVPD,
20529 IX86_BUILTIN_BLENDVPS,
20530 IX86_BUILTIN_PBLENDVB128,
20531 IX86_BUILTIN_PBLENDW128,
20536 IX86_BUILTIN_INSERTPS128,
20538 IX86_BUILTIN_MOVNTDQA,
20539 IX86_BUILTIN_MPSADBW128,
20540 IX86_BUILTIN_PACKUSDW128,
20541 IX86_BUILTIN_PCMPEQQ,
20542 IX86_BUILTIN_PHMINPOSUW128,
20544 IX86_BUILTIN_PMAXSB128,
20545 IX86_BUILTIN_PMAXSD128,
20546 IX86_BUILTIN_PMAXUD128,
20547 IX86_BUILTIN_PMAXUW128,
20549 IX86_BUILTIN_PMINSB128,
20550 IX86_BUILTIN_PMINSD128,
20551 IX86_BUILTIN_PMINUD128,
20552 IX86_BUILTIN_PMINUW128,
20554 IX86_BUILTIN_PMOVSXBW128,
20555 IX86_BUILTIN_PMOVSXBD128,
20556 IX86_BUILTIN_PMOVSXBQ128,
20557 IX86_BUILTIN_PMOVSXWD128,
20558 IX86_BUILTIN_PMOVSXWQ128,
20559 IX86_BUILTIN_PMOVSXDQ128,
20561 IX86_BUILTIN_PMOVZXBW128,
20562 IX86_BUILTIN_PMOVZXBD128,
20563 IX86_BUILTIN_PMOVZXBQ128,
20564 IX86_BUILTIN_PMOVZXWD128,
20565 IX86_BUILTIN_PMOVZXWQ128,
20566 IX86_BUILTIN_PMOVZXDQ128,
20568 IX86_BUILTIN_PMULDQ128,
20569 IX86_BUILTIN_PMULLD128,
20571 IX86_BUILTIN_ROUNDPD,
20572 IX86_BUILTIN_ROUNDPS,
20573 IX86_BUILTIN_ROUNDSD,
20574 IX86_BUILTIN_ROUNDSS,
20576 IX86_BUILTIN_PTESTZ,
20577 IX86_BUILTIN_PTESTC,
20578 IX86_BUILTIN_PTESTNZC,
20580 IX86_BUILTIN_VEC_INIT_V2SI,
20581 IX86_BUILTIN_VEC_INIT_V4HI,
20582 IX86_BUILTIN_VEC_INIT_V8QI,
20583 IX86_BUILTIN_VEC_EXT_V2DF,
20584 IX86_BUILTIN_VEC_EXT_V2DI,
20585 IX86_BUILTIN_VEC_EXT_V4SF,
20586 IX86_BUILTIN_VEC_EXT_V4SI,
20587 IX86_BUILTIN_VEC_EXT_V8HI,
20588 IX86_BUILTIN_VEC_EXT_V2SI,
20589 IX86_BUILTIN_VEC_EXT_V4HI,
20590 IX86_BUILTIN_VEC_EXT_V16QI,
20591 IX86_BUILTIN_VEC_SET_V2DI,
20592 IX86_BUILTIN_VEC_SET_V4SF,
20593 IX86_BUILTIN_VEC_SET_V4SI,
20594 IX86_BUILTIN_VEC_SET_V8HI,
20595 IX86_BUILTIN_VEC_SET_V4HI,
20596 IX86_BUILTIN_VEC_SET_V16QI,
20598 IX86_BUILTIN_VEC_PACK_SFIX,
20601 IX86_BUILTIN_CRC32QI,
20602 IX86_BUILTIN_CRC32HI,
20603 IX86_BUILTIN_CRC32SI,
20604 IX86_BUILTIN_CRC32DI,
20606 IX86_BUILTIN_PCMPESTRI128,
20607 IX86_BUILTIN_PCMPESTRM128,
20608 IX86_BUILTIN_PCMPESTRA128,
20609 IX86_BUILTIN_PCMPESTRC128,
20610 IX86_BUILTIN_PCMPESTRO128,
20611 IX86_BUILTIN_PCMPESTRS128,
20612 IX86_BUILTIN_PCMPESTRZ128,
20613 IX86_BUILTIN_PCMPISTRI128,
20614 IX86_BUILTIN_PCMPISTRM128,
20615 IX86_BUILTIN_PCMPISTRA128,
20616 IX86_BUILTIN_PCMPISTRC128,
20617 IX86_BUILTIN_PCMPISTRO128,
20618 IX86_BUILTIN_PCMPISTRS128,
20619 IX86_BUILTIN_PCMPISTRZ128,
20621 IX86_BUILTIN_PCMPGTQ,
20623 /* AES instructions */
20624 IX86_BUILTIN_AESENC128,
20625 IX86_BUILTIN_AESENCLAST128,
20626 IX86_BUILTIN_AESDEC128,
20627 IX86_BUILTIN_AESDECLAST128,
20628 IX86_BUILTIN_AESIMC128,
20629 IX86_BUILTIN_AESKEYGENASSIST128,
20631 /* PCLMUL instruction */
20632 IX86_BUILTIN_PCLMULQDQ128,
20635 IX86_BUILTIN_ADDPD256,
20636 IX86_BUILTIN_ADDPS256,
20637 IX86_BUILTIN_ADDSUBPD256,
20638 IX86_BUILTIN_ADDSUBPS256,
20639 IX86_BUILTIN_ANDPD256,
20640 IX86_BUILTIN_ANDPS256,
20641 IX86_BUILTIN_ANDNPD256,
20642 IX86_BUILTIN_ANDNPS256,
20643 IX86_BUILTIN_BLENDPD256,
20644 IX86_BUILTIN_BLENDPS256,
20645 IX86_BUILTIN_BLENDVPD256,
20646 IX86_BUILTIN_BLENDVPS256,
20647 IX86_BUILTIN_DIVPD256,
20648 IX86_BUILTIN_DIVPS256,
20649 IX86_BUILTIN_DPPS256,
20650 IX86_BUILTIN_HADDPD256,
20651 IX86_BUILTIN_HADDPS256,
20652 IX86_BUILTIN_HSUBPD256,
20653 IX86_BUILTIN_HSUBPS256,
20654 IX86_BUILTIN_MAXPD256,
20655 IX86_BUILTIN_MAXPS256,
20656 IX86_BUILTIN_MINPD256,
20657 IX86_BUILTIN_MINPS256,
20658 IX86_BUILTIN_MULPD256,
20659 IX86_BUILTIN_MULPS256,
20660 IX86_BUILTIN_ORPD256,
20661 IX86_BUILTIN_ORPS256,
20662 IX86_BUILTIN_SHUFPD256,
20663 IX86_BUILTIN_SHUFPS256,
20664 IX86_BUILTIN_SUBPD256,
20665 IX86_BUILTIN_SUBPS256,
20666 IX86_BUILTIN_XORPD256,
20667 IX86_BUILTIN_XORPS256,
20668 IX86_BUILTIN_CMPSD,
20669 IX86_BUILTIN_CMPSS,
20670 IX86_BUILTIN_CMPPD,
20671 IX86_BUILTIN_CMPPS,
20672 IX86_BUILTIN_CMPPD256,
20673 IX86_BUILTIN_CMPPS256,
20674 IX86_BUILTIN_CVTDQ2PD256,
20675 IX86_BUILTIN_CVTDQ2PS256,
20676 IX86_BUILTIN_CVTPD2PS256,
20677 IX86_BUILTIN_CVTPS2DQ256,
20678 IX86_BUILTIN_CVTPS2PD256,
20679 IX86_BUILTIN_CVTTPD2DQ256,
20680 IX86_BUILTIN_CVTPD2DQ256,
20681 IX86_BUILTIN_CVTTPS2DQ256,
20682 IX86_BUILTIN_EXTRACTF128PD256,
20683 IX86_BUILTIN_EXTRACTF128PS256,
20684 IX86_BUILTIN_EXTRACTF128SI256,
20685 IX86_BUILTIN_VZEROALL,
20686 IX86_BUILTIN_VZEROUPPER,
20687 IX86_BUILTIN_VZEROUPPER_REX64,
20688 IX86_BUILTIN_VPERMILVARPD,
20689 IX86_BUILTIN_VPERMILVARPS,
20690 IX86_BUILTIN_VPERMILVARPD256,
20691 IX86_BUILTIN_VPERMILVARPS256,
20692 IX86_BUILTIN_VPERMILPD,
20693 IX86_BUILTIN_VPERMILPS,
20694 IX86_BUILTIN_VPERMILPD256,
20695 IX86_BUILTIN_VPERMILPS256,
20696 IX86_BUILTIN_VPERM2F128PD256,
20697 IX86_BUILTIN_VPERM2F128PS256,
20698 IX86_BUILTIN_VPERM2F128SI256,
20699 IX86_BUILTIN_VBROADCASTSS,
20700 IX86_BUILTIN_VBROADCASTSD256,
20701 IX86_BUILTIN_VBROADCASTSS256,
20702 IX86_BUILTIN_VBROADCASTPD256,
20703 IX86_BUILTIN_VBROADCASTPS256,
20704 IX86_BUILTIN_VINSERTF128PD256,
20705 IX86_BUILTIN_VINSERTF128PS256,
20706 IX86_BUILTIN_VINSERTF128SI256,
20707 IX86_BUILTIN_LOADUPD256,
20708 IX86_BUILTIN_LOADUPS256,
20709 IX86_BUILTIN_STOREUPD256,
20710 IX86_BUILTIN_STOREUPS256,
20711 IX86_BUILTIN_LDDQU256,
20712 IX86_BUILTIN_MOVNTDQ256,
20713 IX86_BUILTIN_MOVNTPD256,
20714 IX86_BUILTIN_MOVNTPS256,
20715 IX86_BUILTIN_LOADDQU256,
20716 IX86_BUILTIN_STOREDQU256,
20717 IX86_BUILTIN_MASKLOADPD,
20718 IX86_BUILTIN_MASKLOADPS,
20719 IX86_BUILTIN_MASKSTOREPD,
20720 IX86_BUILTIN_MASKSTOREPS,
20721 IX86_BUILTIN_MASKLOADPD256,
20722 IX86_BUILTIN_MASKLOADPS256,
20723 IX86_BUILTIN_MASKSTOREPD256,
20724 IX86_BUILTIN_MASKSTOREPS256,
20725 IX86_BUILTIN_MOVSHDUP256,
20726 IX86_BUILTIN_MOVSLDUP256,
20727 IX86_BUILTIN_MOVDDUP256,
20729 IX86_BUILTIN_SQRTPD256,
20730 IX86_BUILTIN_SQRTPS256,
20731 IX86_BUILTIN_SQRTPS_NR256,
20732 IX86_BUILTIN_RSQRTPS256,
20733 IX86_BUILTIN_RSQRTPS_NR256,
20735 IX86_BUILTIN_RCPPS256,
20737 IX86_BUILTIN_ROUNDPD256,
20738 IX86_BUILTIN_ROUNDPS256,
20740 IX86_BUILTIN_UNPCKHPD256,
20741 IX86_BUILTIN_UNPCKLPD256,
20742 IX86_BUILTIN_UNPCKHPS256,
20743 IX86_BUILTIN_UNPCKLPS256,
20745 IX86_BUILTIN_SI256_SI,
20746 IX86_BUILTIN_PS256_PS,
20747 IX86_BUILTIN_PD256_PD,
20748 IX86_BUILTIN_SI_SI256,
20749 IX86_BUILTIN_PS_PS256,
20750 IX86_BUILTIN_PD_PD256,
20752 IX86_BUILTIN_VTESTZPD,
20753 IX86_BUILTIN_VTESTCPD,
20754 IX86_BUILTIN_VTESTNZCPD,
20755 IX86_BUILTIN_VTESTZPS,
20756 IX86_BUILTIN_VTESTCPS,
20757 IX86_BUILTIN_VTESTNZCPS,
20758 IX86_BUILTIN_VTESTZPD256,
20759 IX86_BUILTIN_VTESTCPD256,
20760 IX86_BUILTIN_VTESTNZCPD256,
20761 IX86_BUILTIN_VTESTZPS256,
20762 IX86_BUILTIN_VTESTCPS256,
20763 IX86_BUILTIN_VTESTNZCPS256,
20764 IX86_BUILTIN_PTESTZ256,
20765 IX86_BUILTIN_PTESTC256,
20766 IX86_BUILTIN_PTESTNZC256,
20768 IX86_BUILTIN_MOVMSKPD256,
20769 IX86_BUILTIN_MOVMSKPS256,
20771 /* TFmode support builtins. */
20773 IX86_BUILTIN_HUGE_VALQ,
20774 IX86_BUILTIN_FABSQ,
20775 IX86_BUILTIN_COPYSIGNQ,
20777 /* Vectorizer support builtins. */
20778 IX86_BUILTIN_CPYSGNPS,
20779 IX86_BUILTIN_CPYSGNPD,
20781 IX86_BUILTIN_CVTUDQ2PS,
20783 /* FMA4 instructions. */
20784 IX86_BUILTIN_VFMADDSS,
20785 IX86_BUILTIN_VFMADDSD,
20786 IX86_BUILTIN_VFMADDPS,
20787 IX86_BUILTIN_VFMADDPD,
20788 IX86_BUILTIN_VFMSUBSS,
20789 IX86_BUILTIN_VFMSUBSD,
20790 IX86_BUILTIN_VFMSUBPS,
20791 IX86_BUILTIN_VFMSUBPD,
20792 IX86_BUILTIN_VFMADDSUBPS,
20793 IX86_BUILTIN_VFMADDSUBPD,
20794 IX86_BUILTIN_VFMSUBADDPS,
20795 IX86_BUILTIN_VFMSUBADDPD,
20796 IX86_BUILTIN_VFNMADDSS,
20797 IX86_BUILTIN_VFNMADDSD,
20798 IX86_BUILTIN_VFNMADDPS,
20799 IX86_BUILTIN_VFNMADDPD,
20800 IX86_BUILTIN_VFNMSUBSS,
20801 IX86_BUILTIN_VFNMSUBSD,
20802 IX86_BUILTIN_VFNMSUBPS,
20803 IX86_BUILTIN_VFNMSUBPD,
20804 IX86_BUILTIN_VFMADDPS256,
20805 IX86_BUILTIN_VFMADDPD256,
20806 IX86_BUILTIN_VFMSUBPS256,
20807 IX86_BUILTIN_VFMSUBPD256,
20808 IX86_BUILTIN_VFMADDSUBPS256,
20809 IX86_BUILTIN_VFMADDSUBPD256,
20810 IX86_BUILTIN_VFMSUBADDPS256,
20811 IX86_BUILTIN_VFMSUBADDPD256,
20812 IX86_BUILTIN_VFNMADDPS256,
20813 IX86_BUILTIN_VFNMADDPD256,
20814 IX86_BUILTIN_VFNMSUBPS256,
20815 IX86_BUILTIN_VFNMSUBPD256,
20819 /* Table for the ix86 builtin decls. */
20820 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20822 /* Table of all of the builtin functions that are possible with different ISA's
20823 but are waiting to be built until a function is declared to use that
20825 struct GTY(()) builtin_isa {
20826 tree type; /* builtin type to use in the declaration */
20827 const char *name; /* function name */
20828 int isa; /* isa_flags this builtin is defined for */
20829 bool const_p; /* true if the declaration is constant */
20832 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20835 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20836 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20837 * function decl in the ix86_builtins array. Returns the function decl or
20838 * NULL_TREE, if the builtin was not added.
20840 * If the front end has a special hook for builtin functions, delay adding
20841 * builtin functions that aren't in the current ISA until the ISA is changed
20842 * with function specific optimization. Doing so, can save about 300K for the
20843 * default compiler. When the builtin is expanded, check at that time whether
20846 * If the front end doesn't have a special hook, record all builtins, even if
20847 * it isn't an instruction set in the current ISA in case the user uses
20848 * function specific options for a different ISA, so that we don't get scope
20849 * errors if a builtin is added in the middle of a function scope. */
20852 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20854 tree decl = NULL_TREE;
20856 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20858 ix86_builtins_isa[(int) code].isa = mask;
20860 if ((mask & ix86_isa_flags) != 0
20861 || (lang_hooks.builtin_function
20862 == lang_hooks.builtin_function_ext_scope))
20865 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20867 ix86_builtins[(int) code] = decl;
20868 ix86_builtins_isa[(int) code].type = NULL_TREE;
20872 ix86_builtins[(int) code] = NULL_TREE;
20873 ix86_builtins_isa[(int) code].const_p = false;
20874 ix86_builtins_isa[(int) code].type = type;
20875 ix86_builtins_isa[(int) code].name = name;
20882 /* Like def_builtin, but also marks the function decl "const". */
20885 def_builtin_const (int mask, const char *name, tree type,
20886 enum ix86_builtins code)
20888 tree decl = def_builtin (mask, name, type, code);
20890 TREE_READONLY (decl) = 1;
20892 ix86_builtins_isa[(int) code].const_p = true;
20897 /* Add any new builtin functions for a given ISA that may not have been
20898 declared. This saves a bit of space compared to adding all of the
20899 declarations to the tree, even if we didn't use them. */
20902 ix86_add_new_builtins (int isa)
20907 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20909 if ((ix86_builtins_isa[i].isa & isa) != 0
20910 && ix86_builtins_isa[i].type != NULL_TREE)
20912 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20913 ix86_builtins_isa[i].type,
20914 i, BUILT_IN_MD, NULL,
20917 ix86_builtins[i] = decl;
20918 ix86_builtins_isa[i].type = NULL_TREE;
20919 if (ix86_builtins_isa[i].const_p)
20920 TREE_READONLY (decl) = 1;
20925 /* Bits for builtin_description.flag. */
20927 /* Set when we don't support the comparison natively, and should
20928 swap_comparison in order to support it. */
20929 #define BUILTIN_DESC_SWAP_OPERANDS 1
20931 struct builtin_description
20933 const unsigned int mask;
20934 const enum insn_code icode;
20935 const char *const name;
20936 const enum ix86_builtins code;
20937 const enum rtx_code comparison;
20941 static const struct builtin_description bdesc_comi[] =
20943 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20944 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20945 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20946 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20947 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20948 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20949 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20950 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20951 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20952 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20953 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20954 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20955 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20956 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20957 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20958 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20959 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20960 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20961 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20962 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20963 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20964 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20965 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20966 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20969 static const struct builtin_description bdesc_pcmpestr[] =
20972 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20973 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20974 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20975 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20976 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20977 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20978 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20981 static const struct builtin_description bdesc_pcmpistr[] =
20984 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20985 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20986 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20987 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20988 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20989 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20990 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20993 /* Special builtin types */
20994 enum ix86_special_builtin_type
20996 SPECIAL_FTYPE_UNKNOWN,
20999 UINT64_FTYPE_PUNSIGNED,
21000 V32QI_FTYPE_PCCHAR,
21001 V16QI_FTYPE_PCCHAR,
21003 V8SF_FTYPE_PCFLOAT,
21005 V4DF_FTYPE_PCDOUBLE,
21006 V4SF_FTYPE_PCFLOAT,
21007 V2DF_FTYPE_PCDOUBLE,
21008 V8SF_FTYPE_PCV8SF_V8SF,
21009 V4DF_FTYPE_PCV4DF_V4DF,
21010 V4SF_FTYPE_V4SF_PCV2SF,
21011 V4SF_FTYPE_PCV4SF_V4SF,
21012 V2DF_FTYPE_V2DF_PCDOUBLE,
21013 V2DF_FTYPE_PCV2DF_V2DF,
21015 VOID_FTYPE_PV2SF_V4SF,
21016 VOID_FTYPE_PV4DI_V4DI,
21017 VOID_FTYPE_PV2DI_V2DI,
21018 VOID_FTYPE_PCHAR_V32QI,
21019 VOID_FTYPE_PCHAR_V16QI,
21020 VOID_FTYPE_PFLOAT_V8SF,
21021 VOID_FTYPE_PFLOAT_V4SF,
21022 VOID_FTYPE_PDOUBLE_V4DF,
21023 VOID_FTYPE_PDOUBLE_V2DF,
21025 VOID_FTYPE_PINT_INT,
21026 VOID_FTYPE_PV8SF_V8SF_V8SF,
21027 VOID_FTYPE_PV4DF_V4DF_V4DF,
21028 VOID_FTYPE_PV4SF_V4SF_V4SF,
21029 VOID_FTYPE_PV2DF_V2DF_V2DF
21032 /* Builtin types */
21033 enum ix86_builtin_type
21036 FLOAT128_FTYPE_FLOAT128,
21038 FLOAT128_FTYPE_FLOAT128_FLOAT128,
21039 INT_FTYPE_V8SF_V8SF_PTEST,
21040 INT_FTYPE_V4DI_V4DI_PTEST,
21041 INT_FTYPE_V4DF_V4DF_PTEST,
21042 INT_FTYPE_V4SF_V4SF_PTEST,
21043 INT_FTYPE_V2DI_V2DI_PTEST,
21044 INT_FTYPE_V2DF_V2DF_PTEST,
21079 V4SF_FTYPE_V4SF_VEC_MERGE,
21088 V2DF_FTYPE_V2DF_VEC_MERGE,
21099 V16QI_FTYPE_V16QI_V16QI,
21100 V16QI_FTYPE_V8HI_V8HI,
21101 V8QI_FTYPE_V8QI_V8QI,
21102 V8QI_FTYPE_V4HI_V4HI,
21103 V8HI_FTYPE_V8HI_V8HI,
21104 V8HI_FTYPE_V8HI_V8HI_COUNT,
21105 V8HI_FTYPE_V16QI_V16QI,
21106 V8HI_FTYPE_V4SI_V4SI,
21107 V8HI_FTYPE_V8HI_SI_COUNT,
21108 V8SF_FTYPE_V8SF_V8SF,
21109 V8SF_FTYPE_V8SF_V8SI,
21110 V4SI_FTYPE_V4SI_V4SI,
21111 V4SI_FTYPE_V4SI_V4SI_COUNT,
21112 V4SI_FTYPE_V8HI_V8HI,
21113 V4SI_FTYPE_V4SF_V4SF,
21114 V4SI_FTYPE_V2DF_V2DF,
21115 V4SI_FTYPE_V4SI_SI_COUNT,
21116 V4HI_FTYPE_V4HI_V4HI,
21117 V4HI_FTYPE_V4HI_V4HI_COUNT,
21118 V4HI_FTYPE_V8QI_V8QI,
21119 V4HI_FTYPE_V2SI_V2SI,
21120 V4HI_FTYPE_V4HI_SI_COUNT,
21121 V4DF_FTYPE_V4DF_V4DF,
21122 V4DF_FTYPE_V4DF_V4DI,
21123 V4SF_FTYPE_V4SF_V4SF,
21124 V4SF_FTYPE_V4SF_V4SF_SWAP,
21125 V4SF_FTYPE_V4SF_V4SI,
21126 V4SF_FTYPE_V4SF_V2SI,
21127 V4SF_FTYPE_V4SF_V2DF,
21128 V4SF_FTYPE_V4SF_DI,
21129 V4SF_FTYPE_V4SF_SI,
21130 V2DI_FTYPE_V2DI_V2DI,
21131 V2DI_FTYPE_V2DI_V2DI_COUNT,
21132 V2DI_FTYPE_V16QI_V16QI,
21133 V2DI_FTYPE_V4SI_V4SI,
21134 V2DI_FTYPE_V2DI_V16QI,
21135 V2DI_FTYPE_V2DF_V2DF,
21136 V2DI_FTYPE_V2DI_SI_COUNT,
21137 V2SI_FTYPE_V2SI_V2SI,
21138 V2SI_FTYPE_V2SI_V2SI_COUNT,
21139 V2SI_FTYPE_V4HI_V4HI,
21140 V2SI_FTYPE_V2SF_V2SF,
21141 V2SI_FTYPE_V2SI_SI_COUNT,
21142 V2DF_FTYPE_V2DF_V2DF,
21143 V2DF_FTYPE_V2DF_V2DF_SWAP,
21144 V2DF_FTYPE_V2DF_V4SF,
21145 V2DF_FTYPE_V2DF_V2DI,
21146 V2DF_FTYPE_V2DF_DI,
21147 V2DF_FTYPE_V2DF_SI,
21148 V2SF_FTYPE_V2SF_V2SF,
21149 V1DI_FTYPE_V1DI_V1DI,
21150 V1DI_FTYPE_V1DI_V1DI_COUNT,
21151 V1DI_FTYPE_V8QI_V8QI,
21152 V1DI_FTYPE_V2SI_V2SI,
21153 V1DI_FTYPE_V1DI_SI_COUNT,
21154 UINT64_FTYPE_UINT64_UINT64,
21155 UINT_FTYPE_UINT_UINT,
21156 UINT_FTYPE_UINT_USHORT,
21157 UINT_FTYPE_UINT_UCHAR,
21158 UINT16_FTYPE_UINT16_INT,
21159 UINT8_FTYPE_UINT8_INT,
21160 V8HI_FTYPE_V8HI_INT,
21161 V4SI_FTYPE_V4SI_INT,
21162 V4HI_FTYPE_V4HI_INT,
21163 V8SF_FTYPE_V8SF_INT,
21164 V4SI_FTYPE_V8SI_INT,
21165 V4SF_FTYPE_V8SF_INT,
21166 V2DF_FTYPE_V4DF_INT,
21167 V4DF_FTYPE_V4DF_INT,
21168 V4SF_FTYPE_V4SF_INT,
21169 V2DI_FTYPE_V2DI_INT,
21170 V2DI2TI_FTYPE_V2DI_INT,
21171 V2DF_FTYPE_V2DF_INT,
21172 V16QI_FTYPE_V16QI_V16QI_V16QI,
21173 V8SF_FTYPE_V8SF_V8SF_V8SF,
21174 V4DF_FTYPE_V4DF_V4DF_V4DF,
21175 V4SF_FTYPE_V4SF_V4SF_V4SF,
21176 V2DF_FTYPE_V2DF_V2DF_V2DF,
21177 V16QI_FTYPE_V16QI_V16QI_INT,
21178 V8SI_FTYPE_V8SI_V8SI_INT,
21179 V8SI_FTYPE_V8SI_V4SI_INT,
21180 V8HI_FTYPE_V8HI_V8HI_INT,
21181 V8SF_FTYPE_V8SF_V8SF_INT,
21182 V8SF_FTYPE_V8SF_V4SF_INT,
21183 V4SI_FTYPE_V4SI_V4SI_INT,
21184 V4DF_FTYPE_V4DF_V4DF_INT,
21185 V4DF_FTYPE_V4DF_V2DF_INT,
21186 V4SF_FTYPE_V4SF_V4SF_INT,
21187 V2DI_FTYPE_V2DI_V2DI_INT,
21188 V2DI2TI_FTYPE_V2DI_V2DI_INT,
21189 V1DI2DI_FTYPE_V1DI_V1DI_INT,
21190 V2DF_FTYPE_V2DF_V2DF_INT,
21191 V2DI_FTYPE_V2DI_UINT_UINT,
21192 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
21195 /* Special builtins with variable number of arguments. */
21196 static const struct builtin_description bdesc_special_args[] =
21198 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21199 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21202 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21205 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21208 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21209 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21210 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21212 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21213 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21214 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21217 /* SSE or 3DNow!A */
21218 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21219 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
21222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21226 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21232 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21236 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21239 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21242 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21243 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21246 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21247 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21248 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21250 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21251 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21252 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21253 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21254 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21256 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21257 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21258 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21259 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21260 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21261 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21262 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21264 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21265 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21266 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21268 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21269 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21270 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21271 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21272 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21273 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21274 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21275 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21278 /* Builtins with variable number of arguments. */
21279 static const struct builtin_description bdesc_args[] =
21281 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21282 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21283 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21284 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21285 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21286 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21287 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21290 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21291 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21292 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21293 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21294 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21295 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21297 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21298 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21299 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21300 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21301 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21302 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21303 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21304 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21306 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21307 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21309 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21310 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21311 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21312 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21314 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21315 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21316 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21317 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21318 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21319 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21321 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21322 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21323 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21324 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21325 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21326 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21328 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21329 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21330 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21332 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21334 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21335 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21336 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21337 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21338 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21339 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21341 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21342 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21343 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21344 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21345 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21346 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21348 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21349 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21350 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21351 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21354 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21355 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21356 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21357 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21359 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21360 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21361 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21362 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21363 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21364 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21365 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21366 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21367 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21368 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21369 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21370 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21371 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21372 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21373 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21376 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21377 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21378 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21379 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21380 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21381 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21384 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21385 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21386 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21387 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21388 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21389 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21390 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21391 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21392 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21393 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21394 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21395 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21397 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21399 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21400 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21401 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21402 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21403 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21404 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21405 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21406 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21408 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21409 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21410 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21411 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21412 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21413 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21414 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21415 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21416 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21417 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21418 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21419 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21420 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21421 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21422 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21423 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21424 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21425 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21426 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21427 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21428 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21429 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21431 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21432 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21433 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21434 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21436 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21437 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21438 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21439 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21441 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21443 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21444 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21445 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21446 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21447 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21449 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21450 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21451 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21453 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21455 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21456 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21457 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21459 /* SSE MMX or 3Dnow!A */
21460 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21461 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21462 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21464 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21465 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21466 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21467 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21469 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21470 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21472 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21477 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21481 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21484 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21486 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21487 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21490 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21494 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21495 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21497 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21501 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21502 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21503 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21504 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21505 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21512 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21514 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21515 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21517 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21518 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21519 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21522 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21524 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21525 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21526 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21527 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21529 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21531 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21532 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21533 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21536 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21537 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21538 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21539 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21541 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21543 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21545 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21547 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21549 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21550 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21551 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21552 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21553 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21554 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21555 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21556 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21558 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21559 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21560 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21561 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21562 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21563 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21564 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21565 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21567 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21568 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21570 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21571 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21572 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21573 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21575 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21576 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21578 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21579 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21580 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21581 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21582 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21585 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21586 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21587 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21588 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21590 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21591 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21592 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21593 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21594 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21595 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21596 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21597 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21599 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21600 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21601 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21603 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21604 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21606 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21607 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21609 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21611 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21612 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21613 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21614 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21616 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21617 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21618 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21619 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21620 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21621 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21622 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21624 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21625 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21626 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21627 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21628 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21629 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21630 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21632 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21633 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21634 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21635 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21637 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21638 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21639 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21641 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21643 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21644 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21646 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21649 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21650 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21653 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21654 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21656 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21657 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21658 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21659 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21660 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21661 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21664 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21665 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21666 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21667 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21668 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21669 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21671 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21672 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21673 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21674 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21675 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21676 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21677 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21678 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21679 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21680 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21681 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21682 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21683 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21684 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21685 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21686 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21687 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21688 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21689 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21690 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21691 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21692 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21693 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21694 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21697 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21698 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21701 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21702 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21703 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21704 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21705 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21706 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21707 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21708 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21709 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21710 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21712 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21713 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21714 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21715 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21716 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21717 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21718 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21719 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21720 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21721 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21722 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21723 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21724 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21726 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21727 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21728 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21729 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21730 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21731 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21732 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21733 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21734 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21735 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21736 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21737 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21740 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21741 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21742 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21743 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21745 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21746 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21747 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21750 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21751 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21752 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21753 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21754 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21757 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21758 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21759 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21760 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21763 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21764 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21766 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21767 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21768 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21769 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21772 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21775 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21776 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21777 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21778 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21779 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21780 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21781 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21782 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21783 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21784 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21785 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21787 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21788 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21789 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21790 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21791 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21792 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21793 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21794 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21795 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21796 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21797 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21798 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21799 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21800 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21803 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21804 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21805 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21810 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21814 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21815 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21816 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21817 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21818 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21821 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21822 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21825 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21826 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21827 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21828 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21829 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21830 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21831 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21832 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21833 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21834 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21835 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21836 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21837 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21838 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21839 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21840 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21842 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21843 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21844 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21846 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21848 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21849 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21850 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21854 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21855 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21857 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21859 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21860 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21862 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21865 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21866 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21867 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21869 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21870 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21871 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21872 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21873 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21874 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21875 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21876 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21877 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21878 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21879 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21880 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21881 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21882 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21883 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21885 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21886 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21890 enum multi_arg_type {
21898 static const struct builtin_description bdesc_multi_arg[] =
21900 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv4sf4, "__builtin_ia32_vfmaddss", IX86_BUILTIN_VFMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
21901 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmaddv2df4, "__builtin_ia32_vfmaddsd", IX86_BUILTIN_VFMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
21902 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4sf4, "__builtin_ia32_vfmaddps", IX86_BUILTIN_VFMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21903 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv2df4, "__builtin_ia32_vfmaddpd", IX86_BUILTIN_VFMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21904 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv4sf4, "__builtin_ia32_vfmsubss", IX86_BUILTIN_VFMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
21905 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfmsubv2df4, "__builtin_ia32_vfmsubsd", IX86_BUILTIN_VFMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
21906 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4sf4, "__builtin_ia32_vfmsubps", IX86_BUILTIN_VFMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21907 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv2df4, "__builtin_ia32_vfmsubpd", IX86_BUILTIN_VFMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21909 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv4sf4, "__builtin_ia32_vfnmaddss", IX86_BUILTIN_VFNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
21910 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmaddv2df4, "__builtin_ia32_vfnmaddsd", IX86_BUILTIN_VFNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
21911 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4sf4, "__builtin_ia32_vfnmaddps", IX86_BUILTIN_VFNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21912 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv2df4, "__builtin_ia32_vfnmaddpd", IX86_BUILTIN_VFNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21913 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv4sf4, "__builtin_ia32_vfnmsubss", IX86_BUILTIN_VFNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
21914 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_vmfnmsubv2df4, "__builtin_ia32_vfnmsubsd", IX86_BUILTIN_VFNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
21915 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4sf4, "__builtin_ia32_vfnmsubps", IX86_BUILTIN_VFNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21916 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv2df4, "__builtin_ia32_vfnmsubpd", IX86_BUILTIN_VFNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21918 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4sf4, "__builtin_ia32_vfmaddsubps", IX86_BUILTIN_VFMADDSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21919 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv2df4, "__builtin_ia32_vfmaddsubpd", IX86_BUILTIN_VFMADDSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21920 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4sf4, "__builtin_ia32_vfmsubaddps", IX86_BUILTIN_VFMSUBADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
21921 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv2df4, "__builtin_ia32_vfmsubaddpd", IX86_BUILTIN_VFMSUBADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
21923 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv8sf4256, "__builtin_ia32_vfmaddps256", IX86_BUILTIN_VFMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21924 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddv4df4256, "__builtin_ia32_vfmaddpd256", IX86_BUILTIN_VFMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
21925 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv8sf4256, "__builtin_ia32_vfmsubps256", IX86_BUILTIN_VFMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21926 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubv4df4256, "__builtin_ia32_vfmsubpd256", IX86_BUILTIN_VFMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
21928 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv8sf4256, "__builtin_ia32_vfnmaddps256", IX86_BUILTIN_VFNMADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21929 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmaddv4df4256, "__builtin_ia32_vfnmaddpd256", IX86_BUILTIN_VFNMADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
21930 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv8sf4256, "__builtin_ia32_vfnmsubps256", IX86_BUILTIN_VFNMSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21931 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fnmsubv4df4256, "__builtin_ia32_vfnmsubpd256", IX86_BUILTIN_VFNMSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
21933 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv8sf4, "__builtin_ia32_vfmaddsubps256", IX86_BUILTIN_VFMADDSUBPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21934 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmaddsubv4df4, "__builtin_ia32_vfmaddsubpd256", IX86_BUILTIN_VFMADDSUBPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
21935 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv8sf4, "__builtin_ia32_vfmsubaddps256", IX86_BUILTIN_VFMSUBADDPS256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
21936 { OPTION_MASK_ISA_FMA4, CODE_FOR_fma4i_fmsubaddv4df4, "__builtin_ia32_vfmsubaddpd256", IX86_BUILTIN_VFMSUBADDPD256, UNKNOWN, (int)MULTI_ARG_3_DF2 }
21940 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21941 in the current target ISA to allow the user to compile particular modules
21942 with different target specific options that differ from the command line
21945 ix86_init_mmx_sse_builtins (void)
21947 const struct builtin_description * d;
21950 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21951 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21952 tree V1DI_type_node
21953 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21954 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21955 tree V2DI_type_node
21956 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21957 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21958 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21959 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21960 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21961 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21962 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21964 tree pchar_type_node = build_pointer_type (char_type_node);
21965 tree pcchar_type_node
21966 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21967 tree pfloat_type_node = build_pointer_type (float_type_node);
21968 tree pcfloat_type_node
21969 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21970 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21971 tree pcv2sf_type_node
21972 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21973 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21974 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21977 tree int_ftype_v4sf_v4sf
21978 = build_function_type_list (integer_type_node,
21979 V4SF_type_node, V4SF_type_node, NULL_TREE);
21980 tree v4si_ftype_v4sf_v4sf
21981 = build_function_type_list (V4SI_type_node,
21982 V4SF_type_node, V4SF_type_node, NULL_TREE);
21983 /* MMX/SSE/integer conversions. */
21984 tree int_ftype_v4sf
21985 = build_function_type_list (integer_type_node,
21986 V4SF_type_node, NULL_TREE);
21987 tree int64_ftype_v4sf
21988 = build_function_type_list (long_long_integer_type_node,
21989 V4SF_type_node, NULL_TREE);
21990 tree int_ftype_v8qi
21991 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21992 tree v4sf_ftype_v4sf_int
21993 = build_function_type_list (V4SF_type_node,
21994 V4SF_type_node, integer_type_node, NULL_TREE);
21995 tree v4sf_ftype_v4sf_int64
21996 = build_function_type_list (V4SF_type_node,
21997 V4SF_type_node, long_long_integer_type_node,
21999 tree v4sf_ftype_v4sf_v2si
22000 = build_function_type_list (V4SF_type_node,
22001 V4SF_type_node, V2SI_type_node, NULL_TREE);
22003 /* Miscellaneous. */
22004 tree v8qi_ftype_v4hi_v4hi
22005 = build_function_type_list (V8QI_type_node,
22006 V4HI_type_node, V4HI_type_node, NULL_TREE);
22007 tree v4hi_ftype_v2si_v2si
22008 = build_function_type_list (V4HI_type_node,
22009 V2SI_type_node, V2SI_type_node, NULL_TREE);
22010 tree v4sf_ftype_v4sf_v4sf_int
22011 = build_function_type_list (V4SF_type_node,
22012 V4SF_type_node, V4SF_type_node,
22013 integer_type_node, NULL_TREE);
22014 tree v2si_ftype_v4hi_v4hi
22015 = build_function_type_list (V2SI_type_node,
22016 V4HI_type_node, V4HI_type_node, NULL_TREE);
22017 tree v4hi_ftype_v4hi_int
22018 = build_function_type_list (V4HI_type_node,
22019 V4HI_type_node, integer_type_node, NULL_TREE);
22020 tree v2si_ftype_v2si_int
22021 = build_function_type_list (V2SI_type_node,
22022 V2SI_type_node, integer_type_node, NULL_TREE);
22023 tree v1di_ftype_v1di_int
22024 = build_function_type_list (V1DI_type_node,
22025 V1DI_type_node, integer_type_node, NULL_TREE);
22027 tree void_ftype_void
22028 = build_function_type (void_type_node, void_list_node);
22029 tree void_ftype_unsigned
22030 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
22031 tree void_ftype_unsigned_unsigned
22032 = build_function_type_list (void_type_node, unsigned_type_node,
22033 unsigned_type_node, NULL_TREE);
22034 tree void_ftype_pcvoid_unsigned_unsigned
22035 = build_function_type_list (void_type_node, const_ptr_type_node,
22036 unsigned_type_node, unsigned_type_node,
22038 tree unsigned_ftype_void
22039 = build_function_type (unsigned_type_node, void_list_node);
22040 tree v2si_ftype_v4sf
22041 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
22042 /* Loads/stores. */
22043 tree void_ftype_v8qi_v8qi_pchar
22044 = build_function_type_list (void_type_node,
22045 V8QI_type_node, V8QI_type_node,
22046 pchar_type_node, NULL_TREE);
22047 tree v4sf_ftype_pcfloat
22048 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
22049 tree v4sf_ftype_v4sf_pcv2sf
22050 = build_function_type_list (V4SF_type_node,
22051 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
22052 tree void_ftype_pv2sf_v4sf
22053 = build_function_type_list (void_type_node,
22054 pv2sf_type_node, V4SF_type_node, NULL_TREE);
22055 tree void_ftype_pfloat_v4sf
22056 = build_function_type_list (void_type_node,
22057 pfloat_type_node, V4SF_type_node, NULL_TREE);
22058 tree void_ftype_pdi_di
22059 = build_function_type_list (void_type_node,
22060 pdi_type_node, long_long_unsigned_type_node,
22062 tree void_ftype_pv2di_v2di
22063 = build_function_type_list (void_type_node,
22064 pv2di_type_node, V2DI_type_node, NULL_TREE);
22065 /* Normal vector unops. */
22066 tree v4sf_ftype_v4sf
22067 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
22068 tree v16qi_ftype_v16qi
22069 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
22070 tree v8hi_ftype_v8hi
22071 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
22072 tree v4si_ftype_v4si
22073 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
22074 tree v8qi_ftype_v8qi
22075 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
22076 tree v4hi_ftype_v4hi
22077 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
22079 /* Normal vector binops. */
22080 tree v4sf_ftype_v4sf_v4sf
22081 = build_function_type_list (V4SF_type_node,
22082 V4SF_type_node, V4SF_type_node, NULL_TREE);
22083 tree v8qi_ftype_v8qi_v8qi
22084 = build_function_type_list (V8QI_type_node,
22085 V8QI_type_node, V8QI_type_node, NULL_TREE);
22086 tree v4hi_ftype_v4hi_v4hi
22087 = build_function_type_list (V4HI_type_node,
22088 V4HI_type_node, V4HI_type_node, NULL_TREE);
22089 tree v2si_ftype_v2si_v2si
22090 = build_function_type_list (V2SI_type_node,
22091 V2SI_type_node, V2SI_type_node, NULL_TREE);
22092 tree v1di_ftype_v1di_v1di
22093 = build_function_type_list (V1DI_type_node,
22094 V1DI_type_node, V1DI_type_node, NULL_TREE);
22095 tree v1di_ftype_v1di_v1di_int
22096 = build_function_type_list (V1DI_type_node,
22097 V1DI_type_node, V1DI_type_node,
22098 integer_type_node, NULL_TREE);
22099 tree v2si_ftype_v2sf
22100 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
22101 tree v2sf_ftype_v2si
22102 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
22103 tree v2si_ftype_v2si
22104 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
22105 tree v2sf_ftype_v2sf
22106 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
22107 tree v2sf_ftype_v2sf_v2sf
22108 = build_function_type_list (V2SF_type_node,
22109 V2SF_type_node, V2SF_type_node, NULL_TREE);
22110 tree v2si_ftype_v2sf_v2sf
22111 = build_function_type_list (V2SI_type_node,
22112 V2SF_type_node, V2SF_type_node, NULL_TREE);
22113 tree pint_type_node = build_pointer_type (integer_type_node);
22114 tree pdouble_type_node = build_pointer_type (double_type_node);
22115 tree pcdouble_type_node = build_pointer_type (
22116 build_type_variant (double_type_node, 1, 0));
22117 tree int_ftype_v2df_v2df
22118 = build_function_type_list (integer_type_node,
22119 V2DF_type_node, V2DF_type_node, NULL_TREE);
22121 tree void_ftype_pcvoid
22122 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
22123 tree v4sf_ftype_v4si
22124 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
22125 tree v4si_ftype_v4sf
22126 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
22127 tree v2df_ftype_v4si
22128 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
22129 tree v4si_ftype_v2df
22130 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
22131 tree v4si_ftype_v2df_v2df
22132 = build_function_type_list (V4SI_type_node,
22133 V2DF_type_node, V2DF_type_node, NULL_TREE);
22134 tree v2si_ftype_v2df
22135 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
22136 tree v4sf_ftype_v2df
22137 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
22138 tree v2df_ftype_v2si
22139 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
22140 tree v2df_ftype_v4sf
22141 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
22142 tree int_ftype_v2df
22143 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
22144 tree int64_ftype_v2df
22145 = build_function_type_list (long_long_integer_type_node,
22146 V2DF_type_node, NULL_TREE);
22147 tree v2df_ftype_v2df_int
22148 = build_function_type_list (V2DF_type_node,
22149 V2DF_type_node, integer_type_node, NULL_TREE);
22150 tree v2df_ftype_v2df_int64
22151 = build_function_type_list (V2DF_type_node,
22152 V2DF_type_node, long_long_integer_type_node,
22154 tree v4sf_ftype_v4sf_v2df
22155 = build_function_type_list (V4SF_type_node,
22156 V4SF_type_node, V2DF_type_node, NULL_TREE);
22157 tree v2df_ftype_v2df_v4sf
22158 = build_function_type_list (V2DF_type_node,
22159 V2DF_type_node, V4SF_type_node, NULL_TREE);
22160 tree v2df_ftype_v2df_v2df_int
22161 = build_function_type_list (V2DF_type_node,
22162 V2DF_type_node, V2DF_type_node,
22165 tree v2df_ftype_v2df_pcdouble
22166 = build_function_type_list (V2DF_type_node,
22167 V2DF_type_node, pcdouble_type_node, NULL_TREE);
22168 tree void_ftype_pdouble_v2df
22169 = build_function_type_list (void_type_node,
22170 pdouble_type_node, V2DF_type_node, NULL_TREE);
22171 tree void_ftype_pint_int
22172 = build_function_type_list (void_type_node,
22173 pint_type_node, integer_type_node, NULL_TREE);
22174 tree void_ftype_v16qi_v16qi_pchar
22175 = build_function_type_list (void_type_node,
22176 V16QI_type_node, V16QI_type_node,
22177 pchar_type_node, NULL_TREE);
22178 tree v2df_ftype_pcdouble
22179 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22180 tree v2df_ftype_v2df_v2df
22181 = build_function_type_list (V2DF_type_node,
22182 V2DF_type_node, V2DF_type_node, NULL_TREE);
22183 tree v16qi_ftype_v16qi_v16qi
22184 = build_function_type_list (V16QI_type_node,
22185 V16QI_type_node, V16QI_type_node, NULL_TREE);
22186 tree v8hi_ftype_v8hi_v8hi
22187 = build_function_type_list (V8HI_type_node,
22188 V8HI_type_node, V8HI_type_node, NULL_TREE);
22189 tree v4si_ftype_v4si_v4si
22190 = build_function_type_list (V4SI_type_node,
22191 V4SI_type_node, V4SI_type_node, NULL_TREE);
22192 tree v2di_ftype_v2di_v2di
22193 = build_function_type_list (V2DI_type_node,
22194 V2DI_type_node, V2DI_type_node, NULL_TREE);
22195 tree v2di_ftype_v2df_v2df
22196 = build_function_type_list (V2DI_type_node,
22197 V2DF_type_node, V2DF_type_node, NULL_TREE);
22198 tree v2df_ftype_v2df
22199 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22200 tree v2di_ftype_v2di_int
22201 = build_function_type_list (V2DI_type_node,
22202 V2DI_type_node, integer_type_node, NULL_TREE);
22203 tree v2di_ftype_v2di_v2di_int
22204 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22205 V2DI_type_node, integer_type_node, NULL_TREE);
22206 tree v4si_ftype_v4si_int
22207 = build_function_type_list (V4SI_type_node,
22208 V4SI_type_node, integer_type_node, NULL_TREE);
22209 tree v8hi_ftype_v8hi_int
22210 = build_function_type_list (V8HI_type_node,
22211 V8HI_type_node, integer_type_node, NULL_TREE);
22212 tree v4si_ftype_v8hi_v8hi
22213 = build_function_type_list (V4SI_type_node,
22214 V8HI_type_node, V8HI_type_node, NULL_TREE);
22215 tree v1di_ftype_v8qi_v8qi
22216 = build_function_type_list (V1DI_type_node,
22217 V8QI_type_node, V8QI_type_node, NULL_TREE);
22218 tree v1di_ftype_v2si_v2si
22219 = build_function_type_list (V1DI_type_node,
22220 V2SI_type_node, V2SI_type_node, NULL_TREE);
22221 tree v2di_ftype_v16qi_v16qi
22222 = build_function_type_list (V2DI_type_node,
22223 V16QI_type_node, V16QI_type_node, NULL_TREE);
22224 tree v2di_ftype_v4si_v4si
22225 = build_function_type_list (V2DI_type_node,
22226 V4SI_type_node, V4SI_type_node, NULL_TREE);
22227 tree int_ftype_v16qi
22228 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22229 tree v16qi_ftype_pcchar
22230 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22231 tree void_ftype_pchar_v16qi
22232 = build_function_type_list (void_type_node,
22233 pchar_type_node, V16QI_type_node, NULL_TREE);
22235 tree v2di_ftype_v2di_unsigned_unsigned
22236 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22237 unsigned_type_node, unsigned_type_node,
22239 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22240 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22241 unsigned_type_node, unsigned_type_node,
22243 tree v2di_ftype_v2di_v16qi
22244 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22246 tree v2df_ftype_v2df_v2df_v2df
22247 = build_function_type_list (V2DF_type_node,
22248 V2DF_type_node, V2DF_type_node,
22249 V2DF_type_node, NULL_TREE);
22250 tree v4sf_ftype_v4sf_v4sf_v4sf
22251 = build_function_type_list (V4SF_type_node,
22252 V4SF_type_node, V4SF_type_node,
22253 V4SF_type_node, NULL_TREE);
22254 tree v8hi_ftype_v16qi
22255 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22257 tree v4si_ftype_v16qi
22258 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22260 tree v2di_ftype_v16qi
22261 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22263 tree v4si_ftype_v8hi
22264 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22266 tree v2di_ftype_v8hi
22267 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22269 tree v2di_ftype_v4si
22270 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22272 tree v2di_ftype_pv2di
22273 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22275 tree v16qi_ftype_v16qi_v16qi_int
22276 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22277 V16QI_type_node, integer_type_node,
22279 tree v16qi_ftype_v16qi_v16qi_v16qi
22280 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22281 V16QI_type_node, V16QI_type_node,
22283 tree v8hi_ftype_v8hi_v8hi_int
22284 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22285 V8HI_type_node, integer_type_node,
22287 tree v4si_ftype_v4si_v4si_int
22288 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22289 V4SI_type_node, integer_type_node,
22291 tree int_ftype_v2di_v2di
22292 = build_function_type_list (integer_type_node,
22293 V2DI_type_node, V2DI_type_node,
22295 tree int_ftype_v16qi_int_v16qi_int_int
22296 = build_function_type_list (integer_type_node,
22303 tree v16qi_ftype_v16qi_int_v16qi_int_int
22304 = build_function_type_list (V16QI_type_node,
22311 tree int_ftype_v16qi_v16qi_int
22312 = build_function_type_list (integer_type_node,
22319 tree v2di_ftype_v2di
22320 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22322 tree v16qi_ftype_v8hi_v8hi
22323 = build_function_type_list (V16QI_type_node,
22324 V8HI_type_node, V8HI_type_node,
22326 tree v8hi_ftype_v4si_v4si
22327 = build_function_type_list (V8HI_type_node,
22328 V4SI_type_node, V4SI_type_node,
22330 tree v8hi_ftype_v16qi_v16qi
22331 = build_function_type_list (V8HI_type_node,
22332 V16QI_type_node, V16QI_type_node,
22334 tree v4hi_ftype_v8qi_v8qi
22335 = build_function_type_list (V4HI_type_node,
22336 V8QI_type_node, V8QI_type_node,
22338 tree unsigned_ftype_unsigned_uchar
22339 = build_function_type_list (unsigned_type_node,
22340 unsigned_type_node,
22341 unsigned_char_type_node,
22343 tree unsigned_ftype_unsigned_ushort
22344 = build_function_type_list (unsigned_type_node,
22345 unsigned_type_node,
22346 short_unsigned_type_node,
22348 tree unsigned_ftype_unsigned_unsigned
22349 = build_function_type_list (unsigned_type_node,
22350 unsigned_type_node,
22351 unsigned_type_node,
22353 tree uint64_ftype_uint64_uint64
22354 = build_function_type_list (long_long_unsigned_type_node,
22355 long_long_unsigned_type_node,
22356 long_long_unsigned_type_node,
22358 tree float_ftype_float
22359 = build_function_type_list (float_type_node,
22364 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22366 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22368 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22370 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22372 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22374 tree v8sf_ftype_v8sf
22375 = build_function_type_list (V8SF_type_node,
22378 tree v8si_ftype_v8sf
22379 = build_function_type_list (V8SI_type_node,
22382 tree v8sf_ftype_v8si
22383 = build_function_type_list (V8SF_type_node,
22386 tree v4si_ftype_v4df
22387 = build_function_type_list (V4SI_type_node,
22390 tree v4df_ftype_v4df
22391 = build_function_type_list (V4DF_type_node,
22394 tree v4df_ftype_v4si
22395 = build_function_type_list (V4DF_type_node,
22398 tree v4df_ftype_v4sf
22399 = build_function_type_list (V4DF_type_node,
22402 tree v4sf_ftype_v4df
22403 = build_function_type_list (V4SF_type_node,
22406 tree v8sf_ftype_v8sf_v8sf
22407 = build_function_type_list (V8SF_type_node,
22408 V8SF_type_node, V8SF_type_node,
22410 tree v4df_ftype_v4df_v4df
22411 = build_function_type_list (V4DF_type_node,
22412 V4DF_type_node, V4DF_type_node,
22414 tree v8sf_ftype_v8sf_int
22415 = build_function_type_list (V8SF_type_node,
22416 V8SF_type_node, integer_type_node,
22418 tree v4si_ftype_v8si_int
22419 = build_function_type_list (V4SI_type_node,
22420 V8SI_type_node, integer_type_node,
22422 tree v4df_ftype_v4df_int
22423 = build_function_type_list (V4DF_type_node,
22424 V4DF_type_node, integer_type_node,
22426 tree v4sf_ftype_v8sf_int
22427 = build_function_type_list (V4SF_type_node,
22428 V8SF_type_node, integer_type_node,
22430 tree v2df_ftype_v4df_int
22431 = build_function_type_list (V2DF_type_node,
22432 V4DF_type_node, integer_type_node,
22434 tree v8sf_ftype_v8sf_v8sf_int
22435 = build_function_type_list (V8SF_type_node,
22436 V8SF_type_node, V8SF_type_node,
22439 tree v8sf_ftype_v8sf_v8sf_v8sf
22440 = build_function_type_list (V8SF_type_node,
22441 V8SF_type_node, V8SF_type_node,
22444 tree v4df_ftype_v4df_v4df_v4df
22445 = build_function_type_list (V4DF_type_node,
22446 V4DF_type_node, V4DF_type_node,
22449 tree v8si_ftype_v8si_v8si_int
22450 = build_function_type_list (V8SI_type_node,
22451 V8SI_type_node, V8SI_type_node,
22454 tree v4df_ftype_v4df_v4df_int
22455 = build_function_type_list (V4DF_type_node,
22456 V4DF_type_node, V4DF_type_node,
22459 tree v8sf_ftype_pcfloat
22460 = build_function_type_list (V8SF_type_node,
22463 tree v4df_ftype_pcdouble
22464 = build_function_type_list (V4DF_type_node,
22465 pcdouble_type_node,
22467 tree pcv4sf_type_node
22468 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22469 tree pcv2df_type_node
22470 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22471 tree v8sf_ftype_pcv4sf
22472 = build_function_type_list (V8SF_type_node,
22475 tree v4df_ftype_pcv2df
22476 = build_function_type_list (V4DF_type_node,
22479 tree v32qi_ftype_pcchar
22480 = build_function_type_list (V32QI_type_node,
22483 tree void_ftype_pchar_v32qi
22484 = build_function_type_list (void_type_node,
22485 pchar_type_node, V32QI_type_node,
22487 tree v8si_ftype_v8si_v4si_int
22488 = build_function_type_list (V8SI_type_node,
22489 V8SI_type_node, V4SI_type_node,
22492 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22493 tree void_ftype_pv4di_v4di
22494 = build_function_type_list (void_type_node,
22495 pv4di_type_node, V4DI_type_node,
22497 tree v8sf_ftype_v8sf_v4sf_int
22498 = build_function_type_list (V8SF_type_node,
22499 V8SF_type_node, V4SF_type_node,
22502 tree v4df_ftype_v4df_v2df_int
22503 = build_function_type_list (V4DF_type_node,
22504 V4DF_type_node, V2DF_type_node,
22507 tree void_ftype_pfloat_v8sf
22508 = build_function_type_list (void_type_node,
22509 pfloat_type_node, V8SF_type_node,
22511 tree void_ftype_pdouble_v4df
22512 = build_function_type_list (void_type_node,
22513 pdouble_type_node, V4DF_type_node,
22515 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22516 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22517 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22518 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22519 tree pcv8sf_type_node
22520 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22521 tree pcv4df_type_node
22522 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22523 tree v8sf_ftype_pcv8sf_v8sf
22524 = build_function_type_list (V8SF_type_node,
22525 pcv8sf_type_node, V8SF_type_node,
22527 tree v4df_ftype_pcv4df_v4df
22528 = build_function_type_list (V4DF_type_node,
22529 pcv4df_type_node, V4DF_type_node,
22531 tree v4sf_ftype_pcv4sf_v4sf
22532 = build_function_type_list (V4SF_type_node,
22533 pcv4sf_type_node, V4SF_type_node,
22535 tree v2df_ftype_pcv2df_v2df
22536 = build_function_type_list (V2DF_type_node,
22537 pcv2df_type_node, V2DF_type_node,
22539 tree void_ftype_pv8sf_v8sf_v8sf
22540 = build_function_type_list (void_type_node,
22541 pv8sf_type_node, V8SF_type_node,
22544 tree void_ftype_pv4df_v4df_v4df
22545 = build_function_type_list (void_type_node,
22546 pv4df_type_node, V4DF_type_node,
22549 tree void_ftype_pv4sf_v4sf_v4sf
22550 = build_function_type_list (void_type_node,
22551 pv4sf_type_node, V4SF_type_node,
22554 tree void_ftype_pv2df_v2df_v2df
22555 = build_function_type_list (void_type_node,
22556 pv2df_type_node, V2DF_type_node,
22559 tree v4df_ftype_v2df
22560 = build_function_type_list (V4DF_type_node,
22563 tree v8sf_ftype_v4sf
22564 = build_function_type_list (V8SF_type_node,
22567 tree v8si_ftype_v4si
22568 = build_function_type_list (V8SI_type_node,
22571 tree v2df_ftype_v4df
22572 = build_function_type_list (V2DF_type_node,
22575 tree v4sf_ftype_v8sf
22576 = build_function_type_list (V4SF_type_node,
22579 tree v4si_ftype_v8si
22580 = build_function_type_list (V4SI_type_node,
22583 tree int_ftype_v4df
22584 = build_function_type_list (integer_type_node,
22587 tree int_ftype_v8sf
22588 = build_function_type_list (integer_type_node,
22591 tree int_ftype_v8sf_v8sf
22592 = build_function_type_list (integer_type_node,
22593 V8SF_type_node, V8SF_type_node,
22595 tree int_ftype_v4di_v4di
22596 = build_function_type_list (integer_type_node,
22597 V4DI_type_node, V4DI_type_node,
22599 tree int_ftype_v4df_v4df
22600 = build_function_type_list (integer_type_node,
22601 V4DF_type_node, V4DF_type_node,
22603 tree v8sf_ftype_v8sf_v8si
22604 = build_function_type_list (V8SF_type_node,
22605 V8SF_type_node, V8SI_type_node,
22607 tree v4df_ftype_v4df_v4di
22608 = build_function_type_list (V4DF_type_node,
22609 V4DF_type_node, V4DI_type_node,
22611 tree v4sf_ftype_v4sf_v4si
22612 = build_function_type_list (V4SF_type_node,
22613 V4SF_type_node, V4SI_type_node, NULL_TREE);
22614 tree v2df_ftype_v2df_v2di
22615 = build_function_type_list (V2DF_type_node,
22616 V2DF_type_node, V2DI_type_node, NULL_TREE);
22618 /* Integer intrinsics. */
22619 tree uint64_ftype_void
22620 = build_function_type (long_long_unsigned_type_node,
22623 = build_function_type_list (integer_type_node,
22624 integer_type_node, NULL_TREE);
22625 tree int64_ftype_int64
22626 = build_function_type_list (long_long_integer_type_node,
22627 long_long_integer_type_node,
22629 tree uint64_ftype_int
22630 = build_function_type_list (long_long_unsigned_type_node,
22631 integer_type_node, NULL_TREE);
22632 tree punsigned_type_node = build_pointer_type (unsigned_type_node);
22633 tree uint64_ftype_punsigned
22634 = build_function_type_list (long_long_unsigned_type_node,
22635 punsigned_type_node, NULL_TREE);
22636 tree ushort_ftype_ushort_int
22637 = build_function_type_list (short_unsigned_type_node,
22638 short_unsigned_type_node,
22641 tree uchar_ftype_uchar_int
22642 = build_function_type_list (unsigned_char_type_node,
22643 unsigned_char_type_node,
22649 /* Add all special builtins with variable number of operands. */
22650 for (i = 0, d = bdesc_special_args;
22651 i < ARRAY_SIZE (bdesc_special_args);
22659 switch ((enum ix86_special_builtin_type) d->flag)
22661 case VOID_FTYPE_VOID:
22662 type = void_ftype_void;
22664 case UINT64_FTYPE_VOID:
22665 type = uint64_ftype_void;
22667 case UINT64_FTYPE_PUNSIGNED:
22668 type = uint64_ftype_punsigned;
22670 case V32QI_FTYPE_PCCHAR:
22671 type = v32qi_ftype_pcchar;
22673 case V16QI_FTYPE_PCCHAR:
22674 type = v16qi_ftype_pcchar;
22676 case V8SF_FTYPE_PCV4SF:
22677 type = v8sf_ftype_pcv4sf;
22679 case V8SF_FTYPE_PCFLOAT:
22680 type = v8sf_ftype_pcfloat;
22682 case V4DF_FTYPE_PCV2DF:
22683 type = v4df_ftype_pcv2df;
22685 case V4DF_FTYPE_PCDOUBLE:
22686 type = v4df_ftype_pcdouble;
22688 case V4SF_FTYPE_PCFLOAT:
22689 type = v4sf_ftype_pcfloat;
22691 case V2DI_FTYPE_PV2DI:
22692 type = v2di_ftype_pv2di;
22694 case V2DF_FTYPE_PCDOUBLE:
22695 type = v2df_ftype_pcdouble;
22697 case V8SF_FTYPE_PCV8SF_V8SF:
22698 type = v8sf_ftype_pcv8sf_v8sf;
22700 case V4DF_FTYPE_PCV4DF_V4DF:
22701 type = v4df_ftype_pcv4df_v4df;
22703 case V4SF_FTYPE_V4SF_PCV2SF:
22704 type = v4sf_ftype_v4sf_pcv2sf;
22706 case V4SF_FTYPE_PCV4SF_V4SF:
22707 type = v4sf_ftype_pcv4sf_v4sf;
22709 case V2DF_FTYPE_V2DF_PCDOUBLE:
22710 type = v2df_ftype_v2df_pcdouble;
22712 case V2DF_FTYPE_PCV2DF_V2DF:
22713 type = v2df_ftype_pcv2df_v2df;
22715 case VOID_FTYPE_PV2SF_V4SF:
22716 type = void_ftype_pv2sf_v4sf;
22718 case VOID_FTYPE_PV4DI_V4DI:
22719 type = void_ftype_pv4di_v4di;
22721 case VOID_FTYPE_PV2DI_V2DI:
22722 type = void_ftype_pv2di_v2di;
22724 case VOID_FTYPE_PCHAR_V32QI:
22725 type = void_ftype_pchar_v32qi;
22727 case VOID_FTYPE_PCHAR_V16QI:
22728 type = void_ftype_pchar_v16qi;
22730 case VOID_FTYPE_PFLOAT_V8SF:
22731 type = void_ftype_pfloat_v8sf;
22733 case VOID_FTYPE_PFLOAT_V4SF:
22734 type = void_ftype_pfloat_v4sf;
22736 case VOID_FTYPE_PDOUBLE_V4DF:
22737 type = void_ftype_pdouble_v4df;
22739 case VOID_FTYPE_PDOUBLE_V2DF:
22740 type = void_ftype_pdouble_v2df;
22742 case VOID_FTYPE_PDI_DI:
22743 type = void_ftype_pdi_di;
22745 case VOID_FTYPE_PINT_INT:
22746 type = void_ftype_pint_int;
22748 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22749 type = void_ftype_pv8sf_v8sf_v8sf;
22751 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22752 type = void_ftype_pv4df_v4df_v4df;
22754 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22755 type = void_ftype_pv4sf_v4sf_v4sf;
22757 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22758 type = void_ftype_pv2df_v2df_v2df;
22761 gcc_unreachable ();
22764 def_builtin (d->mask, d->name, type, d->code);
22767 /* Add all builtins with variable number of operands. */
22768 for (i = 0, d = bdesc_args;
22769 i < ARRAY_SIZE (bdesc_args);
22777 switch ((enum ix86_builtin_type) d->flag)
22779 case FLOAT_FTYPE_FLOAT:
22780 type = float_ftype_float;
22782 case INT_FTYPE_V8SF_V8SF_PTEST:
22783 type = int_ftype_v8sf_v8sf;
22785 case INT_FTYPE_V4DI_V4DI_PTEST:
22786 type = int_ftype_v4di_v4di;
22788 case INT_FTYPE_V4DF_V4DF_PTEST:
22789 type = int_ftype_v4df_v4df;
22791 case INT_FTYPE_V4SF_V4SF_PTEST:
22792 type = int_ftype_v4sf_v4sf;
22794 case INT_FTYPE_V2DI_V2DI_PTEST:
22795 type = int_ftype_v2di_v2di;
22797 case INT_FTYPE_V2DF_V2DF_PTEST:
22798 type = int_ftype_v2df_v2df;
22800 case INT_FTYPE_INT:
22801 type = int_ftype_int;
22803 case UINT64_FTYPE_INT:
22804 type = uint64_ftype_int;
22806 case INT64_FTYPE_INT64:
22807 type = int64_ftype_int64;
22809 case INT64_FTYPE_V4SF:
22810 type = int64_ftype_v4sf;
22812 case INT64_FTYPE_V2DF:
22813 type = int64_ftype_v2df;
22815 case INT_FTYPE_V16QI:
22816 type = int_ftype_v16qi;
22818 case INT_FTYPE_V8QI:
22819 type = int_ftype_v8qi;
22821 case INT_FTYPE_V8SF:
22822 type = int_ftype_v8sf;
22824 case INT_FTYPE_V4DF:
22825 type = int_ftype_v4df;
22827 case INT_FTYPE_V4SF:
22828 type = int_ftype_v4sf;
22830 case INT_FTYPE_V2DF:
22831 type = int_ftype_v2df;
22833 case V16QI_FTYPE_V16QI:
22834 type = v16qi_ftype_v16qi;
22836 case V8SI_FTYPE_V8SF:
22837 type = v8si_ftype_v8sf;
22839 case V8SI_FTYPE_V4SI:
22840 type = v8si_ftype_v4si;
22842 case V8HI_FTYPE_V8HI:
22843 type = v8hi_ftype_v8hi;
22845 case V8HI_FTYPE_V16QI:
22846 type = v8hi_ftype_v16qi;
22848 case V8QI_FTYPE_V8QI:
22849 type = v8qi_ftype_v8qi;
22851 case V8SF_FTYPE_V8SF:
22852 type = v8sf_ftype_v8sf;
22854 case V8SF_FTYPE_V8SI:
22855 type = v8sf_ftype_v8si;
22857 case V8SF_FTYPE_V4SF:
22858 type = v8sf_ftype_v4sf;
22860 case V4SI_FTYPE_V4DF:
22861 type = v4si_ftype_v4df;
22863 case V4SI_FTYPE_V4SI:
22864 type = v4si_ftype_v4si;
22866 case V4SI_FTYPE_V16QI:
22867 type = v4si_ftype_v16qi;
22869 case V4SI_FTYPE_V8SI:
22870 type = v4si_ftype_v8si;
22872 case V4SI_FTYPE_V8HI:
22873 type = v4si_ftype_v8hi;
22875 case V4SI_FTYPE_V4SF:
22876 type = v4si_ftype_v4sf;
22878 case V4SI_FTYPE_V2DF:
22879 type = v4si_ftype_v2df;
22881 case V4HI_FTYPE_V4HI:
22882 type = v4hi_ftype_v4hi;
22884 case V4DF_FTYPE_V4DF:
22885 type = v4df_ftype_v4df;
22887 case V4DF_FTYPE_V4SI:
22888 type = v4df_ftype_v4si;
22890 case V4DF_FTYPE_V4SF:
22891 type = v4df_ftype_v4sf;
22893 case V4DF_FTYPE_V2DF:
22894 type = v4df_ftype_v2df;
22896 case V4SF_FTYPE_V4SF:
22897 case V4SF_FTYPE_V4SF_VEC_MERGE:
22898 type = v4sf_ftype_v4sf;
22900 case V4SF_FTYPE_V8SF:
22901 type = v4sf_ftype_v8sf;
22903 case V4SF_FTYPE_V4SI:
22904 type = v4sf_ftype_v4si;
22906 case V4SF_FTYPE_V4DF:
22907 type = v4sf_ftype_v4df;
22909 case V4SF_FTYPE_V2DF:
22910 type = v4sf_ftype_v2df;
22912 case V2DI_FTYPE_V2DI:
22913 type = v2di_ftype_v2di;
22915 case V2DI_FTYPE_V16QI:
22916 type = v2di_ftype_v16qi;
22918 case V2DI_FTYPE_V8HI:
22919 type = v2di_ftype_v8hi;
22921 case V2DI_FTYPE_V4SI:
22922 type = v2di_ftype_v4si;
22924 case V2SI_FTYPE_V2SI:
22925 type = v2si_ftype_v2si;
22927 case V2SI_FTYPE_V4SF:
22928 type = v2si_ftype_v4sf;
22930 case V2SI_FTYPE_V2DF:
22931 type = v2si_ftype_v2df;
22933 case V2SI_FTYPE_V2SF:
22934 type = v2si_ftype_v2sf;
22936 case V2DF_FTYPE_V4DF:
22937 type = v2df_ftype_v4df;
22939 case V2DF_FTYPE_V4SF:
22940 type = v2df_ftype_v4sf;
22942 case V2DF_FTYPE_V2DF:
22943 case V2DF_FTYPE_V2DF_VEC_MERGE:
22944 type = v2df_ftype_v2df;
22946 case V2DF_FTYPE_V2SI:
22947 type = v2df_ftype_v2si;
22949 case V2DF_FTYPE_V4SI:
22950 type = v2df_ftype_v4si;
22952 case V2SF_FTYPE_V2SF:
22953 type = v2sf_ftype_v2sf;
22955 case V2SF_FTYPE_V2SI:
22956 type = v2sf_ftype_v2si;
22958 case V16QI_FTYPE_V16QI_V16QI:
22959 type = v16qi_ftype_v16qi_v16qi;
22961 case V16QI_FTYPE_V8HI_V8HI:
22962 type = v16qi_ftype_v8hi_v8hi;
22964 case V8QI_FTYPE_V8QI_V8QI:
22965 type = v8qi_ftype_v8qi_v8qi;
22967 case V8QI_FTYPE_V4HI_V4HI:
22968 type = v8qi_ftype_v4hi_v4hi;
22970 case V8HI_FTYPE_V8HI_V8HI:
22971 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22972 type = v8hi_ftype_v8hi_v8hi;
22974 case V8HI_FTYPE_V16QI_V16QI:
22975 type = v8hi_ftype_v16qi_v16qi;
22977 case V8HI_FTYPE_V4SI_V4SI:
22978 type = v8hi_ftype_v4si_v4si;
22980 case V8HI_FTYPE_V8HI_SI_COUNT:
22981 type = v8hi_ftype_v8hi_int;
22983 case V8SF_FTYPE_V8SF_V8SF:
22984 type = v8sf_ftype_v8sf_v8sf;
22986 case V8SF_FTYPE_V8SF_V8SI:
22987 type = v8sf_ftype_v8sf_v8si;
22989 case V4SI_FTYPE_V4SI_V4SI:
22990 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22991 type = v4si_ftype_v4si_v4si;
22993 case V4SI_FTYPE_V8HI_V8HI:
22994 type = v4si_ftype_v8hi_v8hi;
22996 case V4SI_FTYPE_V4SF_V4SF:
22997 type = v4si_ftype_v4sf_v4sf;
22999 case V4SI_FTYPE_V2DF_V2DF:
23000 type = v4si_ftype_v2df_v2df;
23002 case V4SI_FTYPE_V4SI_SI_COUNT:
23003 type = v4si_ftype_v4si_int;
23005 case V4HI_FTYPE_V4HI_V4HI:
23006 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23007 type = v4hi_ftype_v4hi_v4hi;
23009 case V4HI_FTYPE_V8QI_V8QI:
23010 type = v4hi_ftype_v8qi_v8qi;
23012 case V4HI_FTYPE_V2SI_V2SI:
23013 type = v4hi_ftype_v2si_v2si;
23015 case V4HI_FTYPE_V4HI_SI_COUNT:
23016 type = v4hi_ftype_v4hi_int;
23018 case V4DF_FTYPE_V4DF_V4DF:
23019 type = v4df_ftype_v4df_v4df;
23021 case V4DF_FTYPE_V4DF_V4DI:
23022 type = v4df_ftype_v4df_v4di;
23024 case V4SF_FTYPE_V4SF_V4SF:
23025 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23026 type = v4sf_ftype_v4sf_v4sf;
23028 case V4SF_FTYPE_V4SF_V4SI:
23029 type = v4sf_ftype_v4sf_v4si;
23031 case V4SF_FTYPE_V4SF_V2SI:
23032 type = v4sf_ftype_v4sf_v2si;
23034 case V4SF_FTYPE_V4SF_V2DF:
23035 type = v4sf_ftype_v4sf_v2df;
23037 case V4SF_FTYPE_V4SF_DI:
23038 type = v4sf_ftype_v4sf_int64;
23040 case V4SF_FTYPE_V4SF_SI:
23041 type = v4sf_ftype_v4sf_int;
23043 case V2DI_FTYPE_V2DI_V2DI:
23044 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23045 type = v2di_ftype_v2di_v2di;
23047 case V2DI_FTYPE_V16QI_V16QI:
23048 type = v2di_ftype_v16qi_v16qi;
23050 case V2DI_FTYPE_V4SI_V4SI:
23051 type = v2di_ftype_v4si_v4si;
23053 case V2DI_FTYPE_V2DI_V16QI:
23054 type = v2di_ftype_v2di_v16qi;
23056 case V2DI_FTYPE_V2DF_V2DF:
23057 type = v2di_ftype_v2df_v2df;
23059 case V2DI_FTYPE_V2DI_SI_COUNT:
23060 type = v2di_ftype_v2di_int;
23062 case V2SI_FTYPE_V2SI_V2SI:
23063 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23064 type = v2si_ftype_v2si_v2si;
23066 case V2SI_FTYPE_V4HI_V4HI:
23067 type = v2si_ftype_v4hi_v4hi;
23069 case V2SI_FTYPE_V2SF_V2SF:
23070 type = v2si_ftype_v2sf_v2sf;
23072 case V2SI_FTYPE_V2SI_SI_COUNT:
23073 type = v2si_ftype_v2si_int;
23075 case V2DF_FTYPE_V2DF_V2DF:
23076 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23077 type = v2df_ftype_v2df_v2df;
23079 case V2DF_FTYPE_V2DF_V4SF:
23080 type = v2df_ftype_v2df_v4sf;
23082 case V2DF_FTYPE_V2DF_V2DI:
23083 type = v2df_ftype_v2df_v2di;
23085 case V2DF_FTYPE_V2DF_DI:
23086 type = v2df_ftype_v2df_int64;
23088 case V2DF_FTYPE_V2DF_SI:
23089 type = v2df_ftype_v2df_int;
23091 case V2SF_FTYPE_V2SF_V2SF:
23092 type = v2sf_ftype_v2sf_v2sf;
23094 case V1DI_FTYPE_V1DI_V1DI:
23095 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23096 type = v1di_ftype_v1di_v1di;
23098 case V1DI_FTYPE_V8QI_V8QI:
23099 type = v1di_ftype_v8qi_v8qi;
23101 case V1DI_FTYPE_V2SI_V2SI:
23102 type = v1di_ftype_v2si_v2si;
23104 case V1DI_FTYPE_V1DI_SI_COUNT:
23105 type = v1di_ftype_v1di_int;
23107 case UINT64_FTYPE_UINT64_UINT64:
23108 type = uint64_ftype_uint64_uint64;
23110 case UINT_FTYPE_UINT_UINT:
23111 type = unsigned_ftype_unsigned_unsigned;
23113 case UINT_FTYPE_UINT_USHORT:
23114 type = unsigned_ftype_unsigned_ushort;
23116 case UINT_FTYPE_UINT_UCHAR:
23117 type = unsigned_ftype_unsigned_uchar;
23119 case UINT16_FTYPE_UINT16_INT:
23120 type = ushort_ftype_ushort_int;
23122 case UINT8_FTYPE_UINT8_INT:
23123 type = uchar_ftype_uchar_int;
23125 case V8HI_FTYPE_V8HI_INT:
23126 type = v8hi_ftype_v8hi_int;
23128 case V8SF_FTYPE_V8SF_INT:
23129 type = v8sf_ftype_v8sf_int;
23131 case V4SI_FTYPE_V4SI_INT:
23132 type = v4si_ftype_v4si_int;
23134 case V4SI_FTYPE_V8SI_INT:
23135 type = v4si_ftype_v8si_int;
23137 case V4HI_FTYPE_V4HI_INT:
23138 type = v4hi_ftype_v4hi_int;
23140 case V4DF_FTYPE_V4DF_INT:
23141 type = v4df_ftype_v4df_int;
23143 case V4SF_FTYPE_V4SF_INT:
23144 type = v4sf_ftype_v4sf_int;
23146 case V4SF_FTYPE_V8SF_INT:
23147 type = v4sf_ftype_v8sf_int;
23149 case V2DI_FTYPE_V2DI_INT:
23150 case V2DI2TI_FTYPE_V2DI_INT:
23151 type = v2di_ftype_v2di_int;
23153 case V2DF_FTYPE_V2DF_INT:
23154 type = v2df_ftype_v2df_int;
23156 case V2DF_FTYPE_V4DF_INT:
23157 type = v2df_ftype_v4df_int;
23159 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23160 type = v16qi_ftype_v16qi_v16qi_v16qi;
23162 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23163 type = v8sf_ftype_v8sf_v8sf_v8sf;
23165 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23166 type = v4df_ftype_v4df_v4df_v4df;
23168 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23169 type = v4sf_ftype_v4sf_v4sf_v4sf;
23171 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23172 type = v2df_ftype_v2df_v2df_v2df;
23174 case V16QI_FTYPE_V16QI_V16QI_INT:
23175 type = v16qi_ftype_v16qi_v16qi_int;
23177 case V8SI_FTYPE_V8SI_V8SI_INT:
23178 type = v8si_ftype_v8si_v8si_int;
23180 case V8SI_FTYPE_V8SI_V4SI_INT:
23181 type = v8si_ftype_v8si_v4si_int;
23183 case V8HI_FTYPE_V8HI_V8HI_INT:
23184 type = v8hi_ftype_v8hi_v8hi_int;
23186 case V8SF_FTYPE_V8SF_V8SF_INT:
23187 type = v8sf_ftype_v8sf_v8sf_int;
23189 case V8SF_FTYPE_V8SF_V4SF_INT:
23190 type = v8sf_ftype_v8sf_v4sf_int;
23192 case V4SI_FTYPE_V4SI_V4SI_INT:
23193 type = v4si_ftype_v4si_v4si_int;
23195 case V4DF_FTYPE_V4DF_V4DF_INT:
23196 type = v4df_ftype_v4df_v4df_int;
23198 case V4DF_FTYPE_V4DF_V2DF_INT:
23199 type = v4df_ftype_v4df_v2df_int;
23201 case V4SF_FTYPE_V4SF_V4SF_INT:
23202 type = v4sf_ftype_v4sf_v4sf_int;
23204 case V2DI_FTYPE_V2DI_V2DI_INT:
23205 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23206 type = v2di_ftype_v2di_v2di_int;
23208 case V2DF_FTYPE_V2DF_V2DF_INT:
23209 type = v2df_ftype_v2df_v2df_int;
23211 case V2DI_FTYPE_V2DI_UINT_UINT:
23212 type = v2di_ftype_v2di_unsigned_unsigned;
23214 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23215 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23217 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23218 type = v1di_ftype_v1di_v1di_int;
23221 gcc_unreachable ();
23224 def_builtin_const (d->mask, d->name, type, d->code);
23227 /* pcmpestr[im] insns. */
23228 for (i = 0, d = bdesc_pcmpestr;
23229 i < ARRAY_SIZE (bdesc_pcmpestr);
23232 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23233 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23235 ftype = int_ftype_v16qi_int_v16qi_int_int;
23236 def_builtin_const (d->mask, d->name, ftype, d->code);
23239 /* pcmpistr[im] insns. */
23240 for (i = 0, d = bdesc_pcmpistr;
23241 i < ARRAY_SIZE (bdesc_pcmpistr);
23244 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23245 ftype = v16qi_ftype_v16qi_v16qi_int;
23247 ftype = int_ftype_v16qi_v16qi_int;
23248 def_builtin_const (d->mask, d->name, ftype, d->code);
23251 /* comi/ucomi insns. */
23252 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23253 if (d->mask == OPTION_MASK_ISA_SSE2)
23254 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23256 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23259 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23260 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23262 /* SSE or 3DNow!A */
23263 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23266 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23268 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23269 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23272 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23273 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23276 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23277 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23278 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23279 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23280 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23281 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23284 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23287 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23288 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23290 /* Access to the vec_init patterns. */
23291 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23292 integer_type_node, NULL_TREE);
23293 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23295 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23296 short_integer_type_node,
23297 short_integer_type_node,
23298 short_integer_type_node, NULL_TREE);
23299 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23301 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23302 char_type_node, char_type_node,
23303 char_type_node, char_type_node,
23304 char_type_node, char_type_node,
23305 char_type_node, NULL_TREE);
23306 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23308 /* Access to the vec_extract patterns. */
23309 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23310 integer_type_node, NULL_TREE);
23311 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23313 ftype = build_function_type_list (long_long_integer_type_node,
23314 V2DI_type_node, integer_type_node,
23316 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23318 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23319 integer_type_node, NULL_TREE);
23320 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23322 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23323 integer_type_node, NULL_TREE);
23324 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23326 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23327 integer_type_node, NULL_TREE);
23328 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23330 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23331 integer_type_node, NULL_TREE);
23332 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23334 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23335 integer_type_node, NULL_TREE);
23336 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23338 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23339 integer_type_node, NULL_TREE);
23340 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23342 /* Access to the vec_set patterns. */
23343 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23345 integer_type_node, NULL_TREE);
23346 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23348 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23350 integer_type_node, NULL_TREE);
23351 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23353 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23355 integer_type_node, NULL_TREE);
23356 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23358 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23360 integer_type_node, NULL_TREE);
23361 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23363 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23365 integer_type_node, NULL_TREE);
23366 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23368 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23370 integer_type_node, NULL_TREE);
23371 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23372 /* Add FMA4 multi-arg argument instructions */
23373 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23375 tree mtype = NULL_TREE;
23380 switch ((enum multi_arg_type)d->flag)
23382 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23383 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23384 case MULTI_ARG_3_SF2: mtype = v8sf_ftype_v8sf_v8sf_v8sf; break;
23385 case MULTI_ARG_3_DF2: mtype = v4df_ftype_v4df_v4df_v4df; break;
23387 case MULTI_ARG_UNKNOWN:
23389 gcc_unreachable ();
23393 def_builtin_const (d->mask, d->name, mtype, d->code);
23397 /* Internal method for ix86_init_builtins. */
23400 ix86_init_builtins_va_builtins_abi (void)
23402 tree ms_va_ref, sysv_va_ref;
23403 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23404 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23405 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23406 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23410 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23411 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23412 ms_va_ref = build_reference_type (ms_va_list_type_node);
23414 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23417 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23418 fnvoid_va_start_ms =
23419 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23420 fnvoid_va_end_sysv =
23421 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23422 fnvoid_va_start_sysv =
23423 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23425 fnvoid_va_copy_ms =
23426 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23428 fnvoid_va_copy_sysv =
23429 build_function_type_list (void_type_node, sysv_va_ref,
23430 sysv_va_ref, NULL_TREE);
23432 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23433 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23434 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23435 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23436 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23437 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23438 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23439 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23440 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23441 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23442 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23443 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23447 ix86_init_builtins (void)
23449 tree float128_type_node = make_node (REAL_TYPE);
23452 /* The __float80 type. */
23453 if (TYPE_MODE (long_double_type_node) == XFmode)
23454 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23458 /* The __float80 type. */
23459 tree float80_type_node = make_node (REAL_TYPE);
23461 TYPE_PRECISION (float80_type_node) = 80;
23462 layout_type (float80_type_node);
23463 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23467 /* The __float128 type. */
23468 TYPE_PRECISION (float128_type_node) = 128;
23469 layout_type (float128_type_node);
23470 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23473 /* TFmode support builtins. */
23474 ftype = build_function_type (float128_type_node, void_list_node);
23475 decl = add_builtin_function ("__builtin_infq", ftype,
23476 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23478 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23480 decl = add_builtin_function ("__builtin_huge_valq", ftype,
23481 IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
23483 ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl;
23485 /* We will expand them to normal call if SSE2 isn't available since
23486 they are used by libgcc. */
23487 ftype = build_function_type_list (float128_type_node,
23488 float128_type_node,
23490 decl = add_builtin_function ("__builtin_fabsq", ftype,
23491 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23492 "__fabstf2", NULL_TREE);
23493 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23494 TREE_READONLY (decl) = 1;
23496 ftype = build_function_type_list (float128_type_node,
23497 float128_type_node,
23498 float128_type_node,
23500 decl = add_builtin_function ("__builtin_copysignq", ftype,
23501 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23502 "__copysigntf3", NULL_TREE);
23503 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23504 TREE_READONLY (decl) = 1;
23506 ix86_init_mmx_sse_builtins ();
23508 ix86_init_builtins_va_builtins_abi ();
23511 /* Return the ix86 builtin for CODE. */
23514 ix86_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
23516 if (code >= IX86_BUILTIN_MAX)
23517 return error_mark_node;
23519 return ix86_builtins[code];
23522 /* Errors in the source file can cause expand_expr to return const0_rtx
23523 where we expect a vector. To avoid crashing, use one of the vector
23524 clear instructions. */
23526 safe_vector_operand (rtx x, enum machine_mode mode)
23528 if (x == const0_rtx)
23529 x = CONST0_RTX (mode);
23533 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23536 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23539 tree arg0 = CALL_EXPR_ARG (exp, 0);
23540 tree arg1 = CALL_EXPR_ARG (exp, 1);
23541 rtx op0 = expand_normal (arg0);
23542 rtx op1 = expand_normal (arg1);
23543 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23544 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23545 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23547 if (VECTOR_MODE_P (mode0))
23548 op0 = safe_vector_operand (op0, mode0);
23549 if (VECTOR_MODE_P (mode1))
23550 op1 = safe_vector_operand (op1, mode1);
23552 if (optimize || !target
23553 || GET_MODE (target) != tmode
23554 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23555 target = gen_reg_rtx (tmode);
23557 if (GET_MODE (op1) == SImode && mode1 == TImode)
23559 rtx x = gen_reg_rtx (V4SImode);
23560 emit_insn (gen_sse2_loadd (x, op1));
23561 op1 = gen_lowpart (TImode, x);
23564 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23565 op0 = copy_to_mode_reg (mode0, op0);
23566 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23567 op1 = copy_to_mode_reg (mode1, op1);
23569 pat = GEN_FCN (icode) (target, op0, op1);
23578 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23581 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23582 enum multi_arg_type m_type,
23583 enum rtx_code sub_code)
23588 bool comparison_p = false;
23590 bool last_arg_constant = false;
23591 int num_memory = 0;
23594 enum machine_mode mode;
23597 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23601 case MULTI_ARG_3_SF:
23602 case MULTI_ARG_3_DF:
23603 case MULTI_ARG_3_SF2:
23604 case MULTI_ARG_3_DF2:
23608 case MULTI_ARG_UNKNOWN:
23610 gcc_unreachable ();
23613 if (optimize || !target
23614 || GET_MODE (target) != tmode
23615 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23616 target = gen_reg_rtx (tmode);
23618 gcc_assert (nargs <= 4);
23620 for (i = 0; i < nargs; i++)
23622 tree arg = CALL_EXPR_ARG (exp, i);
23623 rtx op = expand_normal (arg);
23624 int adjust = (comparison_p) ? 1 : 0;
23625 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
23627 if (last_arg_constant && i == nargs-1)
23629 if (!CONST_INT_P (op))
23631 error ("last argument must be an immediate");
23632 return gen_reg_rtx (tmode);
23637 if (VECTOR_MODE_P (mode))
23638 op = safe_vector_operand (op, mode);
23640 /* If we aren't optimizing, only allow one memory operand to be
23642 if (memory_operand (op, mode))
23645 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23648 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23650 op = force_reg (mode, op);
23654 args[i].mode = mode;
23660 pat = GEN_FCN (icode) (target, args[0].op);
23665 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23666 GEN_INT ((int)sub_code));
23667 else if (! comparison_p)
23668 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23671 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23675 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23680 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23684 gcc_unreachable ();
23694 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23695 insns with vec_merge. */
23698 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23702 tree arg0 = CALL_EXPR_ARG (exp, 0);
23703 rtx op1, op0 = expand_normal (arg0);
23704 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23705 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23707 if (optimize || !target
23708 || GET_MODE (target) != tmode
23709 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23710 target = gen_reg_rtx (tmode);
23712 if (VECTOR_MODE_P (mode0))
23713 op0 = safe_vector_operand (op0, mode0);
23715 if ((optimize && !register_operand (op0, mode0))
23716 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23717 op0 = copy_to_mode_reg (mode0, op0);
23720 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23721 op1 = copy_to_mode_reg (mode0, op1);
23723 pat = GEN_FCN (icode) (target, op0, op1);
23730 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23733 ix86_expand_sse_compare (const struct builtin_description *d,
23734 tree exp, rtx target, bool swap)
23737 tree arg0 = CALL_EXPR_ARG (exp, 0);
23738 tree arg1 = CALL_EXPR_ARG (exp, 1);
23739 rtx op0 = expand_normal (arg0);
23740 rtx op1 = expand_normal (arg1);
23742 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23743 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23744 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23745 enum rtx_code comparison = d->comparison;
23747 if (VECTOR_MODE_P (mode0))
23748 op0 = safe_vector_operand (op0, mode0);
23749 if (VECTOR_MODE_P (mode1))
23750 op1 = safe_vector_operand (op1, mode1);
23752 /* Swap operands if we have a comparison that isn't available in
23756 rtx tmp = gen_reg_rtx (mode1);
23757 emit_move_insn (tmp, op1);
23762 if (optimize || !target
23763 || GET_MODE (target) != tmode
23764 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23765 target = gen_reg_rtx (tmode);
23767 if ((optimize && !register_operand (op0, mode0))
23768 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23769 op0 = copy_to_mode_reg (mode0, op0);
23770 if ((optimize && !register_operand (op1, mode1))
23771 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23772 op1 = copy_to_mode_reg (mode1, op1);
23774 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23775 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23782 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23785 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23789 tree arg0 = CALL_EXPR_ARG (exp, 0);
23790 tree arg1 = CALL_EXPR_ARG (exp, 1);
23791 rtx op0 = expand_normal (arg0);
23792 rtx op1 = expand_normal (arg1);
23793 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23794 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23795 enum rtx_code comparison = d->comparison;
23797 if (VECTOR_MODE_P (mode0))
23798 op0 = safe_vector_operand (op0, mode0);
23799 if (VECTOR_MODE_P (mode1))
23800 op1 = safe_vector_operand (op1, mode1);
23802 /* Swap operands if we have a comparison that isn't available in
23804 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23811 target = gen_reg_rtx (SImode);
23812 emit_move_insn (target, const0_rtx);
23813 target = gen_rtx_SUBREG (QImode, target, 0);
23815 if ((optimize && !register_operand (op0, mode0))
23816 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23817 op0 = copy_to_mode_reg (mode0, op0);
23818 if ((optimize && !register_operand (op1, mode1))
23819 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23820 op1 = copy_to_mode_reg (mode1, op1);
23822 pat = GEN_FCN (d->icode) (op0, op1);
23826 emit_insn (gen_rtx_SET (VOIDmode,
23827 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23828 gen_rtx_fmt_ee (comparison, QImode,
23832 return SUBREG_REG (target);
23835 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23838 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23842 tree arg0 = CALL_EXPR_ARG (exp, 0);
23843 tree arg1 = CALL_EXPR_ARG (exp, 1);
23844 rtx op0 = expand_normal (arg0);
23845 rtx op1 = expand_normal (arg1);
23846 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23847 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23848 enum rtx_code comparison = d->comparison;
23850 if (VECTOR_MODE_P (mode0))
23851 op0 = safe_vector_operand (op0, mode0);
23852 if (VECTOR_MODE_P (mode1))
23853 op1 = safe_vector_operand (op1, mode1);
23855 target = gen_reg_rtx (SImode);
23856 emit_move_insn (target, const0_rtx);
23857 target = gen_rtx_SUBREG (QImode, target, 0);
23859 if ((optimize && !register_operand (op0, mode0))
23860 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23861 op0 = copy_to_mode_reg (mode0, op0);
23862 if ((optimize && !register_operand (op1, mode1))
23863 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23864 op1 = copy_to_mode_reg (mode1, op1);
23866 pat = GEN_FCN (d->icode) (op0, op1);
23870 emit_insn (gen_rtx_SET (VOIDmode,
23871 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23872 gen_rtx_fmt_ee (comparison, QImode,
23876 return SUBREG_REG (target);
23879 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23882 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23883 tree exp, rtx target)
23886 tree arg0 = CALL_EXPR_ARG (exp, 0);
23887 tree arg1 = CALL_EXPR_ARG (exp, 1);
23888 tree arg2 = CALL_EXPR_ARG (exp, 2);
23889 tree arg3 = CALL_EXPR_ARG (exp, 3);
23890 tree arg4 = CALL_EXPR_ARG (exp, 4);
23891 rtx scratch0, scratch1;
23892 rtx op0 = expand_normal (arg0);
23893 rtx op1 = expand_normal (arg1);
23894 rtx op2 = expand_normal (arg2);
23895 rtx op3 = expand_normal (arg3);
23896 rtx op4 = expand_normal (arg4);
23897 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23899 tmode0 = insn_data[d->icode].operand[0].mode;
23900 tmode1 = insn_data[d->icode].operand[1].mode;
23901 modev2 = insn_data[d->icode].operand[2].mode;
23902 modei3 = insn_data[d->icode].operand[3].mode;
23903 modev4 = insn_data[d->icode].operand[4].mode;
23904 modei5 = insn_data[d->icode].operand[5].mode;
23905 modeimm = insn_data[d->icode].operand[6].mode;
23907 if (VECTOR_MODE_P (modev2))
23908 op0 = safe_vector_operand (op0, modev2);
23909 if (VECTOR_MODE_P (modev4))
23910 op2 = safe_vector_operand (op2, modev4);
23912 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23913 op0 = copy_to_mode_reg (modev2, op0);
23914 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23915 op1 = copy_to_mode_reg (modei3, op1);
23916 if ((optimize && !register_operand (op2, modev4))
23917 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23918 op2 = copy_to_mode_reg (modev4, op2);
23919 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23920 op3 = copy_to_mode_reg (modei5, op3);
23922 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23924 error ("the fifth argument must be a 8-bit immediate");
23928 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23930 if (optimize || !target
23931 || GET_MODE (target) != tmode0
23932 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23933 target = gen_reg_rtx (tmode0);
23935 scratch1 = gen_reg_rtx (tmode1);
23937 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23939 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23941 if (optimize || !target
23942 || GET_MODE (target) != tmode1
23943 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23944 target = gen_reg_rtx (tmode1);
23946 scratch0 = gen_reg_rtx (tmode0);
23948 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23952 gcc_assert (d->flag);
23954 scratch0 = gen_reg_rtx (tmode0);
23955 scratch1 = gen_reg_rtx (tmode1);
23957 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23967 target = gen_reg_rtx (SImode);
23968 emit_move_insn (target, const0_rtx);
23969 target = gen_rtx_SUBREG (QImode, target, 0);
23972 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23973 gen_rtx_fmt_ee (EQ, QImode,
23974 gen_rtx_REG ((enum machine_mode) d->flag,
23977 return SUBREG_REG (target);
23984 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23987 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23988 tree exp, rtx target)
23991 tree arg0 = CALL_EXPR_ARG (exp, 0);
23992 tree arg1 = CALL_EXPR_ARG (exp, 1);
23993 tree arg2 = CALL_EXPR_ARG (exp, 2);
23994 rtx scratch0, scratch1;
23995 rtx op0 = expand_normal (arg0);
23996 rtx op1 = expand_normal (arg1);
23997 rtx op2 = expand_normal (arg2);
23998 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
24000 tmode0 = insn_data[d->icode].operand[0].mode;
24001 tmode1 = insn_data[d->icode].operand[1].mode;
24002 modev2 = insn_data[d->icode].operand[2].mode;
24003 modev3 = insn_data[d->icode].operand[3].mode;
24004 modeimm = insn_data[d->icode].operand[4].mode;
24006 if (VECTOR_MODE_P (modev2))
24007 op0 = safe_vector_operand (op0, modev2);
24008 if (VECTOR_MODE_P (modev3))
24009 op1 = safe_vector_operand (op1, modev3);
24011 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24012 op0 = copy_to_mode_reg (modev2, op0);
24013 if ((optimize && !register_operand (op1, modev3))
24014 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
24015 op1 = copy_to_mode_reg (modev3, op1);
24017 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
24019 error ("the third argument must be a 8-bit immediate");
24023 if (d->code == IX86_BUILTIN_PCMPISTRI128)
24025 if (optimize || !target
24026 || GET_MODE (target) != tmode0
24027 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24028 target = gen_reg_rtx (tmode0);
24030 scratch1 = gen_reg_rtx (tmode1);
24032 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
24034 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
24036 if (optimize || !target
24037 || GET_MODE (target) != tmode1
24038 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24039 target = gen_reg_rtx (tmode1);
24041 scratch0 = gen_reg_rtx (tmode0);
24043 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
24047 gcc_assert (d->flag);
24049 scratch0 = gen_reg_rtx (tmode0);
24050 scratch1 = gen_reg_rtx (tmode1);
24052 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24062 target = gen_reg_rtx (SImode);
24063 emit_move_insn (target, const0_rtx);
24064 target = gen_rtx_SUBREG (QImode, target, 0);
24067 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24068 gen_rtx_fmt_ee (EQ, QImode,
24069 gen_rtx_REG ((enum machine_mode) d->flag,
24072 return SUBREG_REG (target);
24078 /* Subroutine of ix86_expand_builtin to take care of insns with
24079 variable number of operands. */
24082 ix86_expand_args_builtin (const struct builtin_description *d,
24083 tree exp, rtx target)
24085 rtx pat, real_target;
24086 unsigned int i, nargs;
24087 unsigned int nargs_constant = 0;
24088 int num_memory = 0;
24092 enum machine_mode mode;
24094 bool last_arg_count = false;
24095 enum insn_code icode = d->icode;
24096 const struct insn_data *insn_p = &insn_data[icode];
24097 enum machine_mode tmode = insn_p->operand[0].mode;
24098 enum machine_mode rmode = VOIDmode;
24100 enum rtx_code comparison = d->comparison;
24102 switch ((enum ix86_builtin_type) d->flag)
24104 case INT_FTYPE_V8SF_V8SF_PTEST:
24105 case INT_FTYPE_V4DI_V4DI_PTEST:
24106 case INT_FTYPE_V4DF_V4DF_PTEST:
24107 case INT_FTYPE_V4SF_V4SF_PTEST:
24108 case INT_FTYPE_V2DI_V2DI_PTEST:
24109 case INT_FTYPE_V2DF_V2DF_PTEST:
24110 return ix86_expand_sse_ptest (d, exp, target);
24111 case FLOAT128_FTYPE_FLOAT128:
24112 case FLOAT_FTYPE_FLOAT:
24113 case INT_FTYPE_INT:
24114 case UINT64_FTYPE_INT:
24115 case INT64_FTYPE_INT64:
24116 case INT64_FTYPE_V4SF:
24117 case INT64_FTYPE_V2DF:
24118 case INT_FTYPE_V16QI:
24119 case INT_FTYPE_V8QI:
24120 case INT_FTYPE_V8SF:
24121 case INT_FTYPE_V4DF:
24122 case INT_FTYPE_V4SF:
24123 case INT_FTYPE_V2DF:
24124 case V16QI_FTYPE_V16QI:
24125 case V8SI_FTYPE_V8SF:
24126 case V8SI_FTYPE_V4SI:
24127 case V8HI_FTYPE_V8HI:
24128 case V8HI_FTYPE_V16QI:
24129 case V8QI_FTYPE_V8QI:
24130 case V8SF_FTYPE_V8SF:
24131 case V8SF_FTYPE_V8SI:
24132 case V8SF_FTYPE_V4SF:
24133 case V4SI_FTYPE_V4SI:
24134 case V4SI_FTYPE_V16QI:
24135 case V4SI_FTYPE_V4SF:
24136 case V4SI_FTYPE_V8SI:
24137 case V4SI_FTYPE_V8HI:
24138 case V4SI_FTYPE_V4DF:
24139 case V4SI_FTYPE_V2DF:
24140 case V4HI_FTYPE_V4HI:
24141 case V4DF_FTYPE_V4DF:
24142 case V4DF_FTYPE_V4SI:
24143 case V4DF_FTYPE_V4SF:
24144 case V4DF_FTYPE_V2DF:
24145 case V4SF_FTYPE_V4SF:
24146 case V4SF_FTYPE_V4SI:
24147 case V4SF_FTYPE_V8SF:
24148 case V4SF_FTYPE_V4DF:
24149 case V4SF_FTYPE_V2DF:
24150 case V2DI_FTYPE_V2DI:
24151 case V2DI_FTYPE_V16QI:
24152 case V2DI_FTYPE_V8HI:
24153 case V2DI_FTYPE_V4SI:
24154 case V2DF_FTYPE_V2DF:
24155 case V2DF_FTYPE_V4SI:
24156 case V2DF_FTYPE_V4DF:
24157 case V2DF_FTYPE_V4SF:
24158 case V2DF_FTYPE_V2SI:
24159 case V2SI_FTYPE_V2SI:
24160 case V2SI_FTYPE_V4SF:
24161 case V2SI_FTYPE_V2SF:
24162 case V2SI_FTYPE_V2DF:
24163 case V2SF_FTYPE_V2SF:
24164 case V2SF_FTYPE_V2SI:
24167 case V4SF_FTYPE_V4SF_VEC_MERGE:
24168 case V2DF_FTYPE_V2DF_VEC_MERGE:
24169 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24170 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24171 case V16QI_FTYPE_V16QI_V16QI:
24172 case V16QI_FTYPE_V8HI_V8HI:
24173 case V8QI_FTYPE_V8QI_V8QI:
24174 case V8QI_FTYPE_V4HI_V4HI:
24175 case V8HI_FTYPE_V8HI_V8HI:
24176 case V8HI_FTYPE_V16QI_V16QI:
24177 case V8HI_FTYPE_V4SI_V4SI:
24178 case V8SF_FTYPE_V8SF_V8SF:
24179 case V8SF_FTYPE_V8SF_V8SI:
24180 case V4SI_FTYPE_V4SI_V4SI:
24181 case V4SI_FTYPE_V8HI_V8HI:
24182 case V4SI_FTYPE_V4SF_V4SF:
24183 case V4SI_FTYPE_V2DF_V2DF:
24184 case V4HI_FTYPE_V4HI_V4HI:
24185 case V4HI_FTYPE_V8QI_V8QI:
24186 case V4HI_FTYPE_V2SI_V2SI:
24187 case V4DF_FTYPE_V4DF_V4DF:
24188 case V4DF_FTYPE_V4DF_V4DI:
24189 case V4SF_FTYPE_V4SF_V4SF:
24190 case V4SF_FTYPE_V4SF_V4SI:
24191 case V4SF_FTYPE_V4SF_V2SI:
24192 case V4SF_FTYPE_V4SF_V2DF:
24193 case V4SF_FTYPE_V4SF_DI:
24194 case V4SF_FTYPE_V4SF_SI:
24195 case V2DI_FTYPE_V2DI_V2DI:
24196 case V2DI_FTYPE_V16QI_V16QI:
24197 case V2DI_FTYPE_V4SI_V4SI:
24198 case V2DI_FTYPE_V2DI_V16QI:
24199 case V2DI_FTYPE_V2DF_V2DF:
24200 case V2SI_FTYPE_V2SI_V2SI:
24201 case V2SI_FTYPE_V4HI_V4HI:
24202 case V2SI_FTYPE_V2SF_V2SF:
24203 case V2DF_FTYPE_V2DF_V2DF:
24204 case V2DF_FTYPE_V2DF_V4SF:
24205 case V2DF_FTYPE_V2DF_V2DI:
24206 case V2DF_FTYPE_V2DF_DI:
24207 case V2DF_FTYPE_V2DF_SI:
24208 case V2SF_FTYPE_V2SF_V2SF:
24209 case V1DI_FTYPE_V1DI_V1DI:
24210 case V1DI_FTYPE_V8QI_V8QI:
24211 case V1DI_FTYPE_V2SI_V2SI:
24212 if (comparison == UNKNOWN)
24213 return ix86_expand_binop_builtin (icode, exp, target);
24216 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24217 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24218 gcc_assert (comparison != UNKNOWN);
24222 case V8HI_FTYPE_V8HI_V8HI_COUNT:
24223 case V8HI_FTYPE_V8HI_SI_COUNT:
24224 case V4SI_FTYPE_V4SI_V4SI_COUNT:
24225 case V4SI_FTYPE_V4SI_SI_COUNT:
24226 case V4HI_FTYPE_V4HI_V4HI_COUNT:
24227 case V4HI_FTYPE_V4HI_SI_COUNT:
24228 case V2DI_FTYPE_V2DI_V2DI_COUNT:
24229 case V2DI_FTYPE_V2DI_SI_COUNT:
24230 case V2SI_FTYPE_V2SI_V2SI_COUNT:
24231 case V2SI_FTYPE_V2SI_SI_COUNT:
24232 case V1DI_FTYPE_V1DI_V1DI_COUNT:
24233 case V1DI_FTYPE_V1DI_SI_COUNT:
24235 last_arg_count = true;
24237 case UINT64_FTYPE_UINT64_UINT64:
24238 case UINT_FTYPE_UINT_UINT:
24239 case UINT_FTYPE_UINT_USHORT:
24240 case UINT_FTYPE_UINT_UCHAR:
24241 case UINT16_FTYPE_UINT16_INT:
24242 case UINT8_FTYPE_UINT8_INT:
24245 case V2DI2TI_FTYPE_V2DI_INT:
24248 nargs_constant = 1;
24250 case V8HI_FTYPE_V8HI_INT:
24251 case V8SF_FTYPE_V8SF_INT:
24252 case V4SI_FTYPE_V4SI_INT:
24253 case V4SI_FTYPE_V8SI_INT:
24254 case V4HI_FTYPE_V4HI_INT:
24255 case V4DF_FTYPE_V4DF_INT:
24256 case V4SF_FTYPE_V4SF_INT:
24257 case V4SF_FTYPE_V8SF_INT:
24258 case V2DI_FTYPE_V2DI_INT:
24259 case V2DF_FTYPE_V2DF_INT:
24260 case V2DF_FTYPE_V4DF_INT:
24262 nargs_constant = 1;
24264 case V16QI_FTYPE_V16QI_V16QI_V16QI:
24265 case V8SF_FTYPE_V8SF_V8SF_V8SF:
24266 case V4DF_FTYPE_V4DF_V4DF_V4DF:
24267 case V4SF_FTYPE_V4SF_V4SF_V4SF:
24268 case V2DF_FTYPE_V2DF_V2DF_V2DF:
24271 case V16QI_FTYPE_V16QI_V16QI_INT:
24272 case V8HI_FTYPE_V8HI_V8HI_INT:
24273 case V8SI_FTYPE_V8SI_V8SI_INT:
24274 case V8SI_FTYPE_V8SI_V4SI_INT:
24275 case V8SF_FTYPE_V8SF_V8SF_INT:
24276 case V8SF_FTYPE_V8SF_V4SF_INT:
24277 case V4SI_FTYPE_V4SI_V4SI_INT:
24278 case V4DF_FTYPE_V4DF_V4DF_INT:
24279 case V4DF_FTYPE_V4DF_V2DF_INT:
24280 case V4SF_FTYPE_V4SF_V4SF_INT:
24281 case V2DI_FTYPE_V2DI_V2DI_INT:
24282 case V2DF_FTYPE_V2DF_V2DF_INT:
24284 nargs_constant = 1;
24286 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24289 nargs_constant = 1;
24291 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24294 nargs_constant = 1;
24296 case V2DI_FTYPE_V2DI_UINT_UINT:
24298 nargs_constant = 2;
24300 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24302 nargs_constant = 2;
24305 gcc_unreachable ();
24308 gcc_assert (nargs <= ARRAY_SIZE (args));
24310 if (comparison != UNKNOWN)
24312 gcc_assert (nargs == 2);
24313 return ix86_expand_sse_compare (d, exp, target, swap);
24316 if (rmode == VOIDmode || rmode == tmode)
24320 || GET_MODE (target) != tmode
24321 || ! (*insn_p->operand[0].predicate) (target, tmode))
24322 target = gen_reg_rtx (tmode);
24323 real_target = target;
24327 target = gen_reg_rtx (rmode);
24328 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24331 for (i = 0; i < nargs; i++)
24333 tree arg = CALL_EXPR_ARG (exp, i);
24334 rtx op = expand_normal (arg);
24335 enum machine_mode mode = insn_p->operand[i + 1].mode;
24336 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24338 if (last_arg_count && (i + 1) == nargs)
24340 /* SIMD shift insns take either an 8-bit immediate or
24341 register as count. But builtin functions take int as
24342 count. If count doesn't match, we put it in register. */
24345 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24346 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24347 op = copy_to_reg (op);
24350 else if ((nargs - i) <= nargs_constant)
24355 case CODE_FOR_sse4_1_roundpd:
24356 case CODE_FOR_sse4_1_roundps:
24357 case CODE_FOR_sse4_1_roundsd:
24358 case CODE_FOR_sse4_1_roundss:
24359 case CODE_FOR_sse4_1_blendps:
24360 case CODE_FOR_avx_blendpd256:
24361 case CODE_FOR_avx_vpermilv4df:
24362 case CODE_FOR_avx_roundpd256:
24363 case CODE_FOR_avx_roundps256:
24364 error ("the last argument must be a 4-bit immediate");
24367 case CODE_FOR_sse4_1_blendpd:
24368 case CODE_FOR_avx_vpermilv2df:
24369 error ("the last argument must be a 2-bit immediate");
24372 case CODE_FOR_avx_vextractf128v4df:
24373 case CODE_FOR_avx_vextractf128v8sf:
24374 case CODE_FOR_avx_vextractf128v8si:
24375 case CODE_FOR_avx_vinsertf128v4df:
24376 case CODE_FOR_avx_vinsertf128v8sf:
24377 case CODE_FOR_avx_vinsertf128v8si:
24378 error ("the last argument must be a 1-bit immediate");
24381 case CODE_FOR_avx_cmpsdv2df3:
24382 case CODE_FOR_avx_cmpssv4sf3:
24383 case CODE_FOR_avx_cmppdv2df3:
24384 case CODE_FOR_avx_cmppsv4sf3:
24385 case CODE_FOR_avx_cmppdv4df3:
24386 case CODE_FOR_avx_cmppsv8sf3:
24387 error ("the last argument must be a 5-bit immediate");
24391 switch (nargs_constant)
24394 if ((nargs - i) == nargs_constant)
24396 error ("the next to last argument must be an 8-bit immediate");
24400 error ("the last argument must be an 8-bit immediate");
24403 gcc_unreachable ();
24410 if (VECTOR_MODE_P (mode))
24411 op = safe_vector_operand (op, mode);
24413 /* If we aren't optimizing, only allow one memory operand to
24415 if (memory_operand (op, mode))
24418 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24420 if (optimize || !match || num_memory > 1)
24421 op = copy_to_mode_reg (mode, op);
24425 op = copy_to_reg (op);
24426 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24431 args[i].mode = mode;
24437 pat = GEN_FCN (icode) (real_target, args[0].op);
24440 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24443 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24447 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24448 args[2].op, args[3].op);
24451 gcc_unreachable ();
24461 /* Subroutine of ix86_expand_builtin to take care of special insns
24462 with variable number of operands. */
24465 ix86_expand_special_args_builtin (const struct builtin_description *d,
24466 tree exp, rtx target)
24470 unsigned int i, nargs, arg_adjust, memory;
24474 enum machine_mode mode;
24476 enum insn_code icode = d->icode;
24477 bool last_arg_constant = false;
24478 const struct insn_data *insn_p = &insn_data[icode];
24479 enum machine_mode tmode = insn_p->operand[0].mode;
24480 enum { load, store } klass;
24482 switch ((enum ix86_special_builtin_type) d->flag)
24484 case VOID_FTYPE_VOID:
24485 emit_insn (GEN_FCN (icode) (target));
24487 case UINT64_FTYPE_VOID:
24492 case UINT64_FTYPE_PUNSIGNED:
24493 case V2DI_FTYPE_PV2DI:
24494 case V32QI_FTYPE_PCCHAR:
24495 case V16QI_FTYPE_PCCHAR:
24496 case V8SF_FTYPE_PCV4SF:
24497 case V8SF_FTYPE_PCFLOAT:
24498 case V4SF_FTYPE_PCFLOAT:
24499 case V4DF_FTYPE_PCV2DF:
24500 case V4DF_FTYPE_PCDOUBLE:
24501 case V2DF_FTYPE_PCDOUBLE:
24506 case VOID_FTYPE_PV2SF_V4SF:
24507 case VOID_FTYPE_PV4DI_V4DI:
24508 case VOID_FTYPE_PV2DI_V2DI:
24509 case VOID_FTYPE_PCHAR_V32QI:
24510 case VOID_FTYPE_PCHAR_V16QI:
24511 case VOID_FTYPE_PFLOAT_V8SF:
24512 case VOID_FTYPE_PFLOAT_V4SF:
24513 case VOID_FTYPE_PDOUBLE_V4DF:
24514 case VOID_FTYPE_PDOUBLE_V2DF:
24515 case VOID_FTYPE_PDI_DI:
24516 case VOID_FTYPE_PINT_INT:
24519 /* Reserve memory operand for target. */
24520 memory = ARRAY_SIZE (args);
24522 case V4SF_FTYPE_V4SF_PCV2SF:
24523 case V2DF_FTYPE_V2DF_PCDOUBLE:
24528 case V8SF_FTYPE_PCV8SF_V8SF:
24529 case V4DF_FTYPE_PCV4DF_V4DF:
24530 case V4SF_FTYPE_PCV4SF_V4SF:
24531 case V2DF_FTYPE_PCV2DF_V2DF:
24536 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24537 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24538 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24539 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24542 /* Reserve memory operand for target. */
24543 memory = ARRAY_SIZE (args);
24546 gcc_unreachable ();
24549 gcc_assert (nargs <= ARRAY_SIZE (args));
24551 if (klass == store)
24553 arg = CALL_EXPR_ARG (exp, 0);
24554 op = expand_normal (arg);
24555 gcc_assert (target == 0);
24556 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24564 || GET_MODE (target) != tmode
24565 || ! (*insn_p->operand[0].predicate) (target, tmode))
24566 target = gen_reg_rtx (tmode);
24569 for (i = 0; i < nargs; i++)
24571 enum machine_mode mode = insn_p->operand[i + 1].mode;
24574 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24575 op = expand_normal (arg);
24576 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24578 if (last_arg_constant && (i + 1) == nargs)
24584 error ("the last argument must be an 8-bit immediate");
24592 /* This must be the memory operand. */
24593 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24594 gcc_assert (GET_MODE (op) == mode
24595 || GET_MODE (op) == VOIDmode);
24599 /* This must be register. */
24600 if (VECTOR_MODE_P (mode))
24601 op = safe_vector_operand (op, mode);
24603 gcc_assert (GET_MODE (op) == mode
24604 || GET_MODE (op) == VOIDmode);
24605 op = copy_to_mode_reg (mode, op);
24610 args[i].mode = mode;
24616 pat = GEN_FCN (icode) (target);
24619 pat = GEN_FCN (icode) (target, args[0].op);
24622 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24625 gcc_unreachable ();
24631 return klass == store ? 0 : target;
24634 /* Return the integer constant in ARG. Constrain it to be in the range
24635 of the subparts of VEC_TYPE; issue an error if not. */
24638 get_element_number (tree vec_type, tree arg)
24640 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24642 if (!host_integerp (arg, 1)
24643 || (elt = tree_low_cst (arg, 1), elt > max))
24645 error ("selector must be an integer constant in the range 0..%wi", max);
24652 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24653 ix86_expand_vector_init. We DO have language-level syntax for this, in
24654 the form of (type){ init-list }. Except that since we can't place emms
24655 instructions from inside the compiler, we can't allow the use of MMX
24656 registers unless the user explicitly asks for it. So we do *not* define
24657 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24658 we have builtins invoked by mmintrin.h that gives us license to emit
24659 these sorts of instructions. */
24662 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24664 enum machine_mode tmode = TYPE_MODE (type);
24665 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24666 int i, n_elt = GET_MODE_NUNITS (tmode);
24667 rtvec v = rtvec_alloc (n_elt);
24669 gcc_assert (VECTOR_MODE_P (tmode));
24670 gcc_assert (call_expr_nargs (exp) == n_elt);
24672 for (i = 0; i < n_elt; ++i)
24674 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24675 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24678 if (!target || !register_operand (target, tmode))
24679 target = gen_reg_rtx (tmode);
24681 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24685 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24686 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24687 had a language-level syntax for referencing vector elements. */
24690 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24692 enum machine_mode tmode, mode0;
24697 arg0 = CALL_EXPR_ARG (exp, 0);
24698 arg1 = CALL_EXPR_ARG (exp, 1);
24700 op0 = expand_normal (arg0);
24701 elt = get_element_number (TREE_TYPE (arg0), arg1);
24703 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24704 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24705 gcc_assert (VECTOR_MODE_P (mode0));
24707 op0 = force_reg (mode0, op0);
24709 if (optimize || !target || !register_operand (target, tmode))
24710 target = gen_reg_rtx (tmode);
24712 ix86_expand_vector_extract (true, target, op0, elt);
24717 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24718 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24719 a language-level syntax for referencing vector elements. */
24722 ix86_expand_vec_set_builtin (tree exp)
24724 enum machine_mode tmode, mode1;
24725 tree arg0, arg1, arg2;
24727 rtx op0, op1, target;
24729 arg0 = CALL_EXPR_ARG (exp, 0);
24730 arg1 = CALL_EXPR_ARG (exp, 1);
24731 arg2 = CALL_EXPR_ARG (exp, 2);
24733 tmode = TYPE_MODE (TREE_TYPE (arg0));
24734 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24735 gcc_assert (VECTOR_MODE_P (tmode));
24737 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24738 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24739 elt = get_element_number (TREE_TYPE (arg0), arg2);
24741 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24742 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24744 op0 = force_reg (tmode, op0);
24745 op1 = force_reg (mode1, op1);
24747 /* OP0 is the source of these builtin functions and shouldn't be
24748 modified. Create a copy, use it and return it as target. */
24749 target = gen_reg_rtx (tmode);
24750 emit_move_insn (target, op0);
24751 ix86_expand_vector_set (true, target, op1, elt);
24756 /* Expand an expression EXP that calls a built-in function,
24757 with result going to TARGET if that's convenient
24758 (and in mode MODE if that's convenient).
24759 SUBTARGET may be used as the target for computing one of EXP's operands.
24760 IGNORE is nonzero if the value is to be ignored. */
24763 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24764 enum machine_mode mode ATTRIBUTE_UNUSED,
24765 int ignore ATTRIBUTE_UNUSED)
24767 const struct builtin_description *d;
24769 enum insn_code icode;
24770 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24771 tree arg0, arg1, arg2;
24772 rtx op0, op1, op2, pat;
24773 enum machine_mode mode0, mode1, mode2;
24774 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24776 /* Determine whether the builtin function is available under the current ISA.
24777 Originally the builtin was not created if it wasn't applicable to the
24778 current ISA based on the command line switches. With function specific
24779 options, we need to check in the context of the function making the call
24780 whether it is supported. */
24781 if (ix86_builtins_isa[fcode].isa
24782 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24784 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24785 NULL, NULL, false);
24788 error ("%qE needs unknown isa option", fndecl);
24791 gcc_assert (opts != NULL);
24792 error ("%qE needs isa option %s", fndecl, opts);
24800 case IX86_BUILTIN_MASKMOVQ:
24801 case IX86_BUILTIN_MASKMOVDQU:
24802 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24803 ? CODE_FOR_mmx_maskmovq
24804 : CODE_FOR_sse2_maskmovdqu);
24805 /* Note the arg order is different from the operand order. */
24806 arg1 = CALL_EXPR_ARG (exp, 0);
24807 arg2 = CALL_EXPR_ARG (exp, 1);
24808 arg0 = CALL_EXPR_ARG (exp, 2);
24809 op0 = expand_normal (arg0);
24810 op1 = expand_normal (arg1);
24811 op2 = expand_normal (arg2);
24812 mode0 = insn_data[icode].operand[0].mode;
24813 mode1 = insn_data[icode].operand[1].mode;
24814 mode2 = insn_data[icode].operand[2].mode;
24816 op0 = force_reg (Pmode, op0);
24817 op0 = gen_rtx_MEM (mode1, op0);
24819 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24820 op0 = copy_to_mode_reg (mode0, op0);
24821 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24822 op1 = copy_to_mode_reg (mode1, op1);
24823 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24824 op2 = copy_to_mode_reg (mode2, op2);
24825 pat = GEN_FCN (icode) (op0, op1, op2);
24831 case IX86_BUILTIN_LDMXCSR:
24832 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24833 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24834 emit_move_insn (target, op0);
24835 emit_insn (gen_sse_ldmxcsr (target));
24838 case IX86_BUILTIN_STMXCSR:
24839 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24840 emit_insn (gen_sse_stmxcsr (target));
24841 return copy_to_mode_reg (SImode, target);
24843 case IX86_BUILTIN_CLFLUSH:
24844 arg0 = CALL_EXPR_ARG (exp, 0);
24845 op0 = expand_normal (arg0);
24846 icode = CODE_FOR_sse2_clflush;
24847 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24848 op0 = copy_to_mode_reg (Pmode, op0);
24850 emit_insn (gen_sse2_clflush (op0));
24853 case IX86_BUILTIN_MONITOR:
24854 arg0 = CALL_EXPR_ARG (exp, 0);
24855 arg1 = CALL_EXPR_ARG (exp, 1);
24856 arg2 = CALL_EXPR_ARG (exp, 2);
24857 op0 = expand_normal (arg0);
24858 op1 = expand_normal (arg1);
24859 op2 = expand_normal (arg2);
24861 op0 = copy_to_mode_reg (Pmode, op0);
24863 op1 = copy_to_mode_reg (SImode, op1);
24865 op2 = copy_to_mode_reg (SImode, op2);
24866 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24869 case IX86_BUILTIN_MWAIT:
24870 arg0 = CALL_EXPR_ARG (exp, 0);
24871 arg1 = CALL_EXPR_ARG (exp, 1);
24872 op0 = expand_normal (arg0);
24873 op1 = expand_normal (arg1);
24875 op0 = copy_to_mode_reg (SImode, op0);
24877 op1 = copy_to_mode_reg (SImode, op1);
24878 emit_insn (gen_sse3_mwait (op0, op1));
24881 case IX86_BUILTIN_VEC_INIT_V2SI:
24882 case IX86_BUILTIN_VEC_INIT_V4HI:
24883 case IX86_BUILTIN_VEC_INIT_V8QI:
24884 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24886 case IX86_BUILTIN_VEC_EXT_V2DF:
24887 case IX86_BUILTIN_VEC_EXT_V2DI:
24888 case IX86_BUILTIN_VEC_EXT_V4SF:
24889 case IX86_BUILTIN_VEC_EXT_V4SI:
24890 case IX86_BUILTIN_VEC_EXT_V8HI:
24891 case IX86_BUILTIN_VEC_EXT_V2SI:
24892 case IX86_BUILTIN_VEC_EXT_V4HI:
24893 case IX86_BUILTIN_VEC_EXT_V16QI:
24894 return ix86_expand_vec_ext_builtin (exp, target);
24896 case IX86_BUILTIN_VEC_SET_V2DI:
24897 case IX86_BUILTIN_VEC_SET_V4SF:
24898 case IX86_BUILTIN_VEC_SET_V4SI:
24899 case IX86_BUILTIN_VEC_SET_V8HI:
24900 case IX86_BUILTIN_VEC_SET_V4HI:
24901 case IX86_BUILTIN_VEC_SET_V16QI:
24902 return ix86_expand_vec_set_builtin (exp);
24904 case IX86_BUILTIN_INFQ:
24905 case IX86_BUILTIN_HUGE_VALQ:
24907 REAL_VALUE_TYPE inf;
24911 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24913 tmp = validize_mem (force_const_mem (mode, tmp));
24916 target = gen_reg_rtx (mode);
24918 emit_move_insn (target, tmp);
24926 for (i = 0, d = bdesc_special_args;
24927 i < ARRAY_SIZE (bdesc_special_args);
24929 if (d->code == fcode)
24930 return ix86_expand_special_args_builtin (d, exp, target);
24932 for (i = 0, d = bdesc_args;
24933 i < ARRAY_SIZE (bdesc_args);
24935 if (d->code == fcode)
24938 case IX86_BUILTIN_FABSQ:
24939 case IX86_BUILTIN_COPYSIGNQ:
24941 /* Emit a normal call if SSE2 isn't available. */
24942 return expand_call (exp, target, ignore);
24944 return ix86_expand_args_builtin (d, exp, target);
24947 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24948 if (d->code == fcode)
24949 return ix86_expand_sse_comi (d, exp, target);
24951 for (i = 0, d = bdesc_pcmpestr;
24952 i < ARRAY_SIZE (bdesc_pcmpestr);
24954 if (d->code == fcode)
24955 return ix86_expand_sse_pcmpestr (d, exp, target);
24957 for (i = 0, d = bdesc_pcmpistr;
24958 i < ARRAY_SIZE (bdesc_pcmpistr);
24960 if (d->code == fcode)
24961 return ix86_expand_sse_pcmpistr (d, exp, target);
24963 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24964 if (d->code == fcode)
24965 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
24966 (enum multi_arg_type)d->flag,
24969 gcc_unreachable ();
24972 /* Returns a function decl for a vectorized version of the builtin function
24973 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24974 if it is not available. */
24977 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24980 enum machine_mode in_mode, out_mode;
24983 if (TREE_CODE (type_out) != VECTOR_TYPE
24984 || TREE_CODE (type_in) != VECTOR_TYPE)
24987 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24988 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24989 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24990 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24994 case BUILT_IN_SQRT:
24995 if (out_mode == DFmode && out_n == 2
24996 && in_mode == DFmode && in_n == 2)
24997 return ix86_builtins[IX86_BUILTIN_SQRTPD];
25000 case BUILT_IN_SQRTF:
25001 if (out_mode == SFmode && out_n == 4
25002 && in_mode == SFmode && in_n == 4)
25003 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
25006 case BUILT_IN_LRINT:
25007 if (out_mode == SImode && out_n == 4
25008 && in_mode == DFmode && in_n == 2)
25009 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
25012 case BUILT_IN_LRINTF:
25013 if (out_mode == SImode && out_n == 4
25014 && in_mode == SFmode && in_n == 4)
25015 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
25018 case BUILT_IN_COPYSIGN:
25019 if (out_mode == DFmode && out_n == 2
25020 && in_mode == DFmode && in_n == 2)
25021 return ix86_builtins[IX86_BUILTIN_CPYSGNPD];
25024 case BUILT_IN_COPYSIGNF:
25025 if (out_mode == SFmode && out_n == 4
25026 && in_mode == SFmode && in_n == 4)
25027 return ix86_builtins[IX86_BUILTIN_CPYSGNPS];
25034 /* Dispatch to a handler for a vectorization library. */
25035 if (ix86_veclib_handler)
25036 return (*ix86_veclib_handler) ((enum built_in_function) fn, type_out,
25042 /* Handler for an SVML-style interface to
25043 a library with vectorized intrinsics. */
25046 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
25049 tree fntype, new_fndecl, args;
25052 enum machine_mode el_mode, in_mode;
25055 /* The SVML is suitable for unsafe math only. */
25056 if (!flag_unsafe_math_optimizations)
25059 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25060 n = TYPE_VECTOR_SUBPARTS (type_out);
25061 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25062 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25063 if (el_mode != in_mode
25071 case BUILT_IN_LOG10:
25073 case BUILT_IN_TANH:
25075 case BUILT_IN_ATAN:
25076 case BUILT_IN_ATAN2:
25077 case BUILT_IN_ATANH:
25078 case BUILT_IN_CBRT:
25079 case BUILT_IN_SINH:
25081 case BUILT_IN_ASINH:
25082 case BUILT_IN_ASIN:
25083 case BUILT_IN_COSH:
25085 case BUILT_IN_ACOSH:
25086 case BUILT_IN_ACOS:
25087 if (el_mode != DFmode || n != 2)
25091 case BUILT_IN_EXPF:
25092 case BUILT_IN_LOGF:
25093 case BUILT_IN_LOG10F:
25094 case BUILT_IN_POWF:
25095 case BUILT_IN_TANHF:
25096 case BUILT_IN_TANF:
25097 case BUILT_IN_ATANF:
25098 case BUILT_IN_ATAN2F:
25099 case BUILT_IN_ATANHF:
25100 case BUILT_IN_CBRTF:
25101 case BUILT_IN_SINHF:
25102 case BUILT_IN_SINF:
25103 case BUILT_IN_ASINHF:
25104 case BUILT_IN_ASINF:
25105 case BUILT_IN_COSHF:
25106 case BUILT_IN_COSF:
25107 case BUILT_IN_ACOSHF:
25108 case BUILT_IN_ACOSF:
25109 if (el_mode != SFmode || n != 4)
25117 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25119 if (fn == BUILT_IN_LOGF)
25120 strcpy (name, "vmlsLn4");
25121 else if (fn == BUILT_IN_LOG)
25122 strcpy (name, "vmldLn2");
25125 sprintf (name, "vmls%s", bname+10);
25126 name[strlen (name)-1] = '4';
25129 sprintf (name, "vmld%s2", bname+10);
25131 /* Convert to uppercase. */
25135 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25136 args = TREE_CHAIN (args))
25140 fntype = build_function_type_list (type_out, type_in, NULL);
25142 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25144 /* Build a function declaration for the vectorized function. */
25145 new_fndecl = build_decl (BUILTINS_LOCATION,
25146 FUNCTION_DECL, get_identifier (name), fntype);
25147 TREE_PUBLIC (new_fndecl) = 1;
25148 DECL_EXTERNAL (new_fndecl) = 1;
25149 DECL_IS_NOVOPS (new_fndecl) = 1;
25150 TREE_READONLY (new_fndecl) = 1;
25155 /* Handler for an ACML-style interface to
25156 a library with vectorized intrinsics. */
25159 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25161 char name[20] = "__vr.._";
25162 tree fntype, new_fndecl, args;
25165 enum machine_mode el_mode, in_mode;
25168 /* The ACML is 64bits only and suitable for unsafe math only as
25169 it does not correctly support parts of IEEE with the required
25170 precision such as denormals. */
25172 || !flag_unsafe_math_optimizations)
25175 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25176 n = TYPE_VECTOR_SUBPARTS (type_out);
25177 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25178 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25179 if (el_mode != in_mode
25189 case BUILT_IN_LOG2:
25190 case BUILT_IN_LOG10:
25193 if (el_mode != DFmode
25198 case BUILT_IN_SINF:
25199 case BUILT_IN_COSF:
25200 case BUILT_IN_EXPF:
25201 case BUILT_IN_POWF:
25202 case BUILT_IN_LOGF:
25203 case BUILT_IN_LOG2F:
25204 case BUILT_IN_LOG10F:
25207 if (el_mode != SFmode
25216 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25217 sprintf (name + 7, "%s", bname+10);
25220 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25221 args = TREE_CHAIN (args))
25225 fntype = build_function_type_list (type_out, type_in, NULL);
25227 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25229 /* Build a function declaration for the vectorized function. */
25230 new_fndecl = build_decl (BUILTINS_LOCATION,
25231 FUNCTION_DECL, get_identifier (name), fntype);
25232 TREE_PUBLIC (new_fndecl) = 1;
25233 DECL_EXTERNAL (new_fndecl) = 1;
25234 DECL_IS_NOVOPS (new_fndecl) = 1;
25235 TREE_READONLY (new_fndecl) = 1;
25241 /* Returns a decl of a function that implements conversion of an integer vector
25242 into a floating-point vector, or vice-versa. TYPE is the type of the integer
25243 side of the conversion.
25244 Return NULL_TREE if it is not available. */
25247 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
25249 if (! (TARGET_SSE2 && TREE_CODE (type) == VECTOR_TYPE))
25255 switch (TYPE_MODE (type))
25258 return TYPE_UNSIGNED (type)
25259 ? ix86_builtins[IX86_BUILTIN_CVTUDQ2PS]
25260 : ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
25265 case FIX_TRUNC_EXPR:
25266 switch (TYPE_MODE (type))
25269 return TYPE_UNSIGNED (type)
25271 : ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
25281 /* Returns a code for a target-specific builtin that implements
25282 reciprocal of the function, or NULL_TREE if not available. */
25285 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
25286 bool sqrt ATTRIBUTE_UNUSED)
25288 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
25289 && flag_finite_math_only && !flag_trapping_math
25290 && flag_unsafe_math_optimizations))
25294 /* Machine dependent builtins. */
25297 /* Vectorized version of sqrt to rsqrt conversion. */
25298 case IX86_BUILTIN_SQRTPS_NR:
25299 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
25305 /* Normal builtins. */
25308 /* Sqrt to rsqrt conversion. */
25309 case BUILT_IN_SQRTF:
25310 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25317 /* Store OPERAND to the memory after reload is completed. This means
25318 that we can't easily use assign_stack_local. */
25320 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25324 gcc_assert (reload_completed);
25325 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25327 result = gen_rtx_MEM (mode,
25328 gen_rtx_PLUS (Pmode,
25330 GEN_INT (-RED_ZONE_SIZE)));
25331 emit_move_insn (result, operand);
25333 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25339 operand = gen_lowpart (DImode, operand);
25343 gen_rtx_SET (VOIDmode,
25344 gen_rtx_MEM (DImode,
25345 gen_rtx_PRE_DEC (DImode,
25346 stack_pointer_rtx)),
25350 gcc_unreachable ();
25352 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25361 split_di (&operand, 1, operands, operands + 1);
25363 gen_rtx_SET (VOIDmode,
25364 gen_rtx_MEM (SImode,
25365 gen_rtx_PRE_DEC (Pmode,
25366 stack_pointer_rtx)),
25369 gen_rtx_SET (VOIDmode,
25370 gen_rtx_MEM (SImode,
25371 gen_rtx_PRE_DEC (Pmode,
25372 stack_pointer_rtx)),
25377 /* Store HImodes as SImodes. */
25378 operand = gen_lowpart (SImode, operand);
25382 gen_rtx_SET (VOIDmode,
25383 gen_rtx_MEM (GET_MODE (operand),
25384 gen_rtx_PRE_DEC (SImode,
25385 stack_pointer_rtx)),
25389 gcc_unreachable ();
25391 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25396 /* Free operand from the memory. */
25398 ix86_free_from_memory (enum machine_mode mode)
25400 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25404 if (mode == DImode || TARGET_64BIT)
25408 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25409 to pop or add instruction if registers are available. */
25410 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25411 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25416 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
25417 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
25419 static const enum reg_class *
25420 i386_ira_cover_classes (void)
25422 static const enum reg_class sse_fpmath_classes[] = {
25423 GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES
25425 static const enum reg_class no_sse_fpmath_classes[] = {
25426 GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES
25429 return TARGET_SSE_MATH ? sse_fpmath_classes : no_sse_fpmath_classes;
25432 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25433 QImode must go into class Q_REGS.
25434 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25435 movdf to do mem-to-mem moves through integer regs. */
25437 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25439 enum machine_mode mode = GET_MODE (x);
25441 /* We're only allowed to return a subclass of CLASS. Many of the
25442 following checks fail for NO_REGS, so eliminate that early. */
25443 if (regclass == NO_REGS)
25446 /* All classes can load zeros. */
25447 if (x == CONST0_RTX (mode))
25450 /* Force constants into memory if we are loading a (nonzero) constant into
25451 an MMX or SSE register. This is because there are no MMX/SSE instructions
25452 to load from a constant. */
25454 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25457 /* Prefer SSE regs only, if we can use them for math. */
25458 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25459 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25461 /* Floating-point constants need more complex checks. */
25462 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25464 /* General regs can load everything. */
25465 if (reg_class_subset_p (regclass, GENERAL_REGS))
25468 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25469 zero above. We only want to wind up preferring 80387 registers if
25470 we plan on doing computation with them. */
25472 && standard_80387_constant_p (x))
25474 /* Limit class to non-sse. */
25475 if (regclass == FLOAT_SSE_REGS)
25477 if (regclass == FP_TOP_SSE_REGS)
25479 if (regclass == FP_SECOND_SSE_REGS)
25480 return FP_SECOND_REG;
25481 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25488 /* Generally when we see PLUS here, it's the function invariant
25489 (plus soft-fp const_int). Which can only be computed into general
25491 if (GET_CODE (x) == PLUS)
25492 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25494 /* QImode constants are easy to load, but non-constant QImode data
25495 must go into Q_REGS. */
25496 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25498 if (reg_class_subset_p (regclass, Q_REGS))
25500 if (reg_class_subset_p (Q_REGS, regclass))
25508 /* Discourage putting floating-point values in SSE registers unless
25509 SSE math is being used, and likewise for the 387 registers. */
25511 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25513 enum machine_mode mode = GET_MODE (x);
25515 /* Restrict the output reload class to the register bank that we are doing
25516 math on. If we would like not to return a subset of CLASS, reject this
25517 alternative: if reload cannot do this, it will still use its choice. */
25518 mode = GET_MODE (x);
25519 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25520 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25522 if (X87_FLOAT_MODE_P (mode))
25524 if (regclass == FP_TOP_SSE_REGS)
25526 else if (regclass == FP_SECOND_SSE_REGS)
25527 return FP_SECOND_REG;
25529 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25535 static enum reg_class
25536 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25537 enum machine_mode mode,
25538 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25540 /* QImode spills from non-QI registers require
25541 intermediate register on 32bit targets. */
25542 if (!in_p && mode == QImode && !TARGET_64BIT
25543 && (rclass == GENERAL_REGS
25544 || rclass == LEGACY_REGS
25545 || rclass == INDEX_REGS))
25554 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25555 regno = true_regnum (x);
25557 /* Return Q_REGS if the operand is in memory. */
25565 /* If we are copying between general and FP registers, we need a memory
25566 location. The same is true for SSE and MMX registers.
25568 To optimize register_move_cost performance, allow inline variant.
25570 The macro can't work reliably when one of the CLASSES is class containing
25571 registers from multiple units (SSE, MMX, integer). We avoid this by never
25572 combining those units in single alternative in the machine description.
25573 Ensure that this constraint holds to avoid unexpected surprises.
25575 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25576 enforce these sanity checks. */
25579 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25580 enum machine_mode mode, int strict)
25582 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25583 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25584 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25585 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25586 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25587 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25589 gcc_assert (!strict);
25593 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25596 /* ??? This is a lie. We do have moves between mmx/general, and for
25597 mmx/sse2. But by saying we need secondary memory we discourage the
25598 register allocator from using the mmx registers unless needed. */
25599 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25602 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25604 /* SSE1 doesn't have any direct moves from other classes. */
25608 /* If the target says that inter-unit moves are more expensive
25609 than moving through memory, then don't generate them. */
25610 if (!TARGET_INTER_UNIT_MOVES)
25613 /* Between SSE and general, we have moves no larger than word size. */
25614 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25622 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25623 enum machine_mode mode, int strict)
25625 return inline_secondary_memory_needed (class1, class2, mode, strict);
25628 /* Return true if the registers in CLASS cannot represent the change from
25629 modes FROM to TO. */
25632 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25633 enum reg_class regclass)
25638 /* x87 registers can't do subreg at all, as all values are reformatted
25639 to extended precision. */
25640 if (MAYBE_FLOAT_CLASS_P (regclass))
25643 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25645 /* Vector registers do not support QI or HImode loads. If we don't
25646 disallow a change to these modes, reload will assume it's ok to
25647 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25648 the vec_dupv4hi pattern. */
25649 if (GET_MODE_SIZE (from) < 4)
25652 /* Vector registers do not support subreg with nonzero offsets, which
25653 are otherwise valid for integer registers. Since we can't see
25654 whether we have a nonzero offset from here, prohibit all
25655 nonparadoxical subregs changing size. */
25656 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25663 /* Return the cost of moving data of mode M between a
25664 register and memory. A value of 2 is the default; this cost is
25665 relative to those in `REGISTER_MOVE_COST'.
25667 This function is used extensively by register_move_cost that is used to
25668 build tables at startup. Make it inline in this case.
25669 When IN is 2, return maximum of in and out move cost.
25671 If moving between registers and memory is more expensive than
25672 between two registers, you should define this macro to express the
25675 Model also increased moving costs of QImode registers in non
25679 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25683 if (FLOAT_CLASS_P (regclass))
25701 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25702 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25704 if (SSE_CLASS_P (regclass))
25707 switch (GET_MODE_SIZE (mode))
25722 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25723 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25725 if (MMX_CLASS_P (regclass))
25728 switch (GET_MODE_SIZE (mode))
25740 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25741 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25743 switch (GET_MODE_SIZE (mode))
25746 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25749 return ix86_cost->int_store[0];
25750 if (TARGET_PARTIAL_REG_DEPENDENCY
25751 && optimize_function_for_speed_p (cfun))
25752 cost = ix86_cost->movzbl_load;
25754 cost = ix86_cost->int_load[0];
25756 return MAX (cost, ix86_cost->int_store[0]);
25762 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25764 return ix86_cost->movzbl_load;
25766 return ix86_cost->int_store[0] + 4;
25771 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25772 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25774 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25775 if (mode == TFmode)
25778 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25780 cost = ix86_cost->int_load[2];
25782 cost = ix86_cost->int_store[2];
25783 return (cost * (((int) GET_MODE_SIZE (mode)
25784 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25789 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25791 return inline_memory_move_cost (mode, regclass, in);
25795 /* Return the cost of moving data from a register in class CLASS1 to
25796 one in class CLASS2.
25798 It is not required that the cost always equal 2 when FROM is the same as TO;
25799 on some machines it is expensive to move between registers if they are not
25800 general registers. */
25803 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25804 enum reg_class class2)
25806 /* In case we require secondary memory, compute cost of the store followed
25807 by load. In order to avoid bad register allocation choices, we need
25808 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25810 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25814 cost += inline_memory_move_cost (mode, class1, 2);
25815 cost += inline_memory_move_cost (mode, class2, 2);
25817 /* In case of copying from general_purpose_register we may emit multiple
25818 stores followed by single load causing memory size mismatch stall.
25819 Count this as arbitrarily high cost of 20. */
25820 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25823 /* In the case of FP/MMX moves, the registers actually overlap, and we
25824 have to switch modes in order to treat them differently. */
25825 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25826 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25832 /* Moves between SSE/MMX and integer unit are expensive. */
25833 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25834 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25836 /* ??? By keeping returned value relatively high, we limit the number
25837 of moves between integer and MMX/SSE registers for all targets.
25838 Additionally, high value prevents problem with x86_modes_tieable_p(),
25839 where integer modes in MMX/SSE registers are not tieable
25840 because of missing QImode and HImode moves to, from or between
25841 MMX/SSE registers. */
25842 return MAX (8, ix86_cost->mmxsse_to_integer);
25844 if (MAYBE_FLOAT_CLASS_P (class1))
25845 return ix86_cost->fp_move;
25846 if (MAYBE_SSE_CLASS_P (class1))
25847 return ix86_cost->sse_move;
25848 if (MAYBE_MMX_CLASS_P (class1))
25849 return ix86_cost->mmx_move;
25853 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25856 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25858 /* Flags and only flags can only hold CCmode values. */
25859 if (CC_REGNO_P (regno))
25860 return GET_MODE_CLASS (mode) == MODE_CC;
25861 if (GET_MODE_CLASS (mode) == MODE_CC
25862 || GET_MODE_CLASS (mode) == MODE_RANDOM
25863 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25865 if (FP_REGNO_P (regno))
25866 return VALID_FP_MODE_P (mode);
25867 if (SSE_REGNO_P (regno))
25869 /* We implement the move patterns for all vector modes into and
25870 out of SSE registers, even when no operation instructions
25871 are available. OImode move is available only when AVX is
25873 return ((TARGET_AVX && mode == OImode)
25874 || VALID_AVX256_REG_MODE (mode)
25875 || VALID_SSE_REG_MODE (mode)
25876 || VALID_SSE2_REG_MODE (mode)
25877 || VALID_MMX_REG_MODE (mode)
25878 || VALID_MMX_REG_MODE_3DNOW (mode));
25880 if (MMX_REGNO_P (regno))
25882 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25883 so if the register is available at all, then we can move data of
25884 the given mode into or out of it. */
25885 return (VALID_MMX_REG_MODE (mode)
25886 || VALID_MMX_REG_MODE_3DNOW (mode));
25889 if (mode == QImode)
25891 /* Take care for QImode values - they can be in non-QI regs,
25892 but then they do cause partial register stalls. */
25893 if (regno <= BX_REG || TARGET_64BIT)
25895 if (!TARGET_PARTIAL_REG_STALL)
25897 return reload_in_progress || reload_completed;
25899 /* We handle both integer and floats in the general purpose registers. */
25900 else if (VALID_INT_MODE_P (mode))
25902 else if (VALID_FP_MODE_P (mode))
25904 else if (VALID_DFP_MODE_P (mode))
25906 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25907 on to use that value in smaller contexts, this can easily force a
25908 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25909 supporting DImode, allow it. */
25910 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25916 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25917 tieable integer mode. */
25920 ix86_tieable_integer_mode_p (enum machine_mode mode)
25929 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25932 return TARGET_64BIT;
25939 /* Return true if MODE1 is accessible in a register that can hold MODE2
25940 without copying. That is, all register classes that can hold MODE2
25941 can also hold MODE1. */
25944 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25946 if (mode1 == mode2)
25949 if (ix86_tieable_integer_mode_p (mode1)
25950 && ix86_tieable_integer_mode_p (mode2))
25953 /* MODE2 being XFmode implies fp stack or general regs, which means we
25954 can tie any smaller floating point modes to it. Note that we do not
25955 tie this with TFmode. */
25956 if (mode2 == XFmode)
25957 return mode1 == SFmode || mode1 == DFmode;
25959 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25960 that we can tie it with SFmode. */
25961 if (mode2 == DFmode)
25962 return mode1 == SFmode;
25964 /* If MODE2 is only appropriate for an SSE register, then tie with
25965 any other mode acceptable to SSE registers. */
25966 if (GET_MODE_SIZE (mode2) == 16
25967 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25968 return (GET_MODE_SIZE (mode1) == 16
25969 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25971 /* If MODE2 is appropriate for an MMX register, then tie
25972 with any other mode acceptable to MMX registers. */
25973 if (GET_MODE_SIZE (mode2) == 8
25974 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25975 return (GET_MODE_SIZE (mode1) == 8
25976 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25981 /* Compute a (partial) cost for rtx X. Return true if the complete
25982 cost has been computed, and false if subexpressions should be
25983 scanned. In either case, *TOTAL contains the cost result. */
25986 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25988 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25989 enum machine_mode mode = GET_MODE (x);
25990 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25998 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
26000 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
26002 else if (flag_pic && SYMBOLIC_CONST (x)
26004 || (!GET_CODE (x) != LABEL_REF
26005 && (GET_CODE (x) != SYMBOL_REF
26006 || !SYMBOL_REF_LOCAL_P (x)))))
26013 if (mode == VOIDmode)
26016 switch (standard_80387_constant_p (x))
26021 default: /* Other constants */
26026 /* Start with (MEM (SYMBOL_REF)), since that's where
26027 it'll probably end up. Add a penalty for size. */
26028 *total = (COSTS_N_INSNS (1)
26029 + (flag_pic != 0 && !TARGET_64BIT)
26030 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
26036 /* The zero extensions is often completely free on x86_64, so make
26037 it as cheap as possible. */
26038 if (TARGET_64BIT && mode == DImode
26039 && GET_MODE (XEXP (x, 0)) == SImode)
26041 else if (TARGET_ZERO_EXTEND_WITH_AND)
26042 *total = cost->add;
26044 *total = cost->movzx;
26048 *total = cost->movsx;
26052 if (CONST_INT_P (XEXP (x, 1))
26053 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
26055 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26058 *total = cost->add;
26061 if ((value == 2 || value == 3)
26062 && cost->lea <= cost->shift_const)
26064 *total = cost->lea;
26074 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
26076 if (CONST_INT_P (XEXP (x, 1)))
26078 if (INTVAL (XEXP (x, 1)) > 32)
26079 *total = cost->shift_const + COSTS_N_INSNS (2);
26081 *total = cost->shift_const * 2;
26085 if (GET_CODE (XEXP (x, 1)) == AND)
26086 *total = cost->shift_var * 2;
26088 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
26093 if (CONST_INT_P (XEXP (x, 1)))
26094 *total = cost->shift_const;
26096 *total = cost->shift_var;
26101 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26103 /* ??? SSE scalar cost should be used here. */
26104 *total = cost->fmul;
26107 else if (X87_FLOAT_MODE_P (mode))
26109 *total = cost->fmul;
26112 else if (FLOAT_MODE_P (mode))
26114 /* ??? SSE vector cost should be used here. */
26115 *total = cost->fmul;
26120 rtx op0 = XEXP (x, 0);
26121 rtx op1 = XEXP (x, 1);
26123 if (CONST_INT_P (XEXP (x, 1)))
26125 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26126 for (nbits = 0; value != 0; value &= value - 1)
26130 /* This is arbitrary. */
26133 /* Compute costs correctly for widening multiplication. */
26134 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26135 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26136 == GET_MODE_SIZE (mode))
26138 int is_mulwiden = 0;
26139 enum machine_mode inner_mode = GET_MODE (op0);
26141 if (GET_CODE (op0) == GET_CODE (op1))
26142 is_mulwiden = 1, op1 = XEXP (op1, 0);
26143 else if (CONST_INT_P (op1))
26145 if (GET_CODE (op0) == SIGN_EXTEND)
26146 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26149 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26153 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26156 *total = (cost->mult_init[MODE_INDEX (mode)]
26157 + nbits * cost->mult_bit
26158 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26167 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26168 /* ??? SSE cost should be used here. */
26169 *total = cost->fdiv;
26170 else if (X87_FLOAT_MODE_P (mode))
26171 *total = cost->fdiv;
26172 else if (FLOAT_MODE_P (mode))
26173 /* ??? SSE vector cost should be used here. */
26174 *total = cost->fdiv;
26176 *total = cost->divide[MODE_INDEX (mode)];
26180 if (GET_MODE_CLASS (mode) == MODE_INT
26181 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26183 if (GET_CODE (XEXP (x, 0)) == PLUS
26184 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26185 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26186 && CONSTANT_P (XEXP (x, 1)))
26188 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26189 if (val == 2 || val == 4 || val == 8)
26191 *total = cost->lea;
26192 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26193 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26194 outer_code, speed);
26195 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26199 else if (GET_CODE (XEXP (x, 0)) == MULT
26200 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26202 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26203 if (val == 2 || val == 4 || val == 8)
26205 *total = cost->lea;
26206 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26207 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26211 else if (GET_CODE (XEXP (x, 0)) == PLUS)
26213 *total = cost->lea;
26214 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26215 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26216 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26223 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26225 /* ??? SSE cost should be used here. */
26226 *total = cost->fadd;
26229 else if (X87_FLOAT_MODE_P (mode))
26231 *total = cost->fadd;
26234 else if (FLOAT_MODE_P (mode))
26236 /* ??? SSE vector cost should be used here. */
26237 *total = cost->fadd;
26245 if (!TARGET_64BIT && mode == DImode)
26247 *total = (cost->add * 2
26248 + (rtx_cost (XEXP (x, 0), outer_code, speed)
26249 << (GET_MODE (XEXP (x, 0)) != DImode))
26250 + (rtx_cost (XEXP (x, 1), outer_code, speed)
26251 << (GET_MODE (XEXP (x, 1)) != DImode)));
26257 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26259 /* ??? SSE cost should be used here. */
26260 *total = cost->fchs;
26263 else if (X87_FLOAT_MODE_P (mode))
26265 *total = cost->fchs;
26268 else if (FLOAT_MODE_P (mode))
26270 /* ??? SSE vector cost should be used here. */
26271 *total = cost->fchs;
26277 if (!TARGET_64BIT && mode == DImode)
26278 *total = cost->add * 2;
26280 *total = cost->add;
26284 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
26285 && XEXP (XEXP (x, 0), 1) == const1_rtx
26286 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
26287 && XEXP (x, 1) == const0_rtx)
26289 /* This kind of construct is implemented using test[bwl].
26290 Treat it as if we had an AND. */
26291 *total = (cost->add
26292 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
26293 + rtx_cost (const1_rtx, outer_code, speed));
26299 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
26304 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26305 /* ??? SSE cost should be used here. */
26306 *total = cost->fabs;
26307 else if (X87_FLOAT_MODE_P (mode))
26308 *total = cost->fabs;
26309 else if (FLOAT_MODE_P (mode))
26310 /* ??? SSE vector cost should be used here. */
26311 *total = cost->fabs;
26315 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26316 /* ??? SSE cost should be used here. */
26317 *total = cost->fsqrt;
26318 else if (X87_FLOAT_MODE_P (mode))
26319 *total = cost->fsqrt;
26320 else if (FLOAT_MODE_P (mode))
26321 /* ??? SSE vector cost should be used here. */
26322 *total = cost->fsqrt;
26326 if (XINT (x, 1) == UNSPEC_TP)
26337 static int current_machopic_label_num;
26339 /* Given a symbol name and its associated stub, write out the
26340 definition of the stub. */
26343 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26345 unsigned int length;
26346 char *binder_name, *symbol_name, lazy_ptr_name[32];
26347 int label = ++current_machopic_label_num;
26349 /* For 64-bit we shouldn't get here. */
26350 gcc_assert (!TARGET_64BIT);
26352 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26353 symb = (*targetm.strip_name_encoding) (symb);
26355 length = strlen (stub);
26356 binder_name = XALLOCAVEC (char, length + 32);
26357 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26359 length = strlen (symb);
26360 symbol_name = XALLOCAVEC (char, length + 32);
26361 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26363 sprintf (lazy_ptr_name, "L%d$lz", label);
26366 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26368 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26370 fprintf (file, "%s:\n", stub);
26371 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26375 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26376 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26377 fprintf (file, "\tjmp\t*%%edx\n");
26380 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26382 fprintf (file, "%s:\n", binder_name);
26386 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26387 fputs ("\tpushl\t%eax\n", file);
26390 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26392 fputs ("\tjmp\tdyld_stub_binding_helper\n", file);
26394 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26395 fprintf (file, "%s:\n", lazy_ptr_name);
26396 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26397 fprintf (file, ASM_LONG "%s\n", binder_name);
26401 darwin_x86_file_end (void)
26403 darwin_file_end ();
26406 #endif /* TARGET_MACHO */
26408 /* Order the registers for register allocator. */
26411 x86_order_regs_for_local_alloc (void)
26416 /* First allocate the local general purpose registers. */
26417 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26418 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26419 reg_alloc_order [pos++] = i;
26421 /* Global general purpose registers. */
26422 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26423 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26424 reg_alloc_order [pos++] = i;
26426 /* x87 registers come first in case we are doing FP math
26428 if (!TARGET_SSE_MATH)
26429 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26430 reg_alloc_order [pos++] = i;
26432 /* SSE registers. */
26433 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26434 reg_alloc_order [pos++] = i;
26435 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26436 reg_alloc_order [pos++] = i;
26438 /* x87 registers. */
26439 if (TARGET_SSE_MATH)
26440 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26441 reg_alloc_order [pos++] = i;
26443 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26444 reg_alloc_order [pos++] = i;
26446 /* Initialize the rest of array as we do not allocate some registers
26448 while (pos < FIRST_PSEUDO_REGISTER)
26449 reg_alloc_order [pos++] = 0;
26452 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26453 struct attribute_spec.handler. */
26455 ix86_handle_abi_attribute (tree *node, tree name,
26456 tree args ATTRIBUTE_UNUSED,
26457 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26459 if (TREE_CODE (*node) != FUNCTION_TYPE
26460 && TREE_CODE (*node) != METHOD_TYPE
26461 && TREE_CODE (*node) != FIELD_DECL
26462 && TREE_CODE (*node) != TYPE_DECL)
26464 warning (OPT_Wattributes, "%qE attribute only applies to functions",
26466 *no_add_attrs = true;
26471 warning (OPT_Wattributes, "%qE attribute only available for 64-bit",
26473 *no_add_attrs = true;
26477 /* Can combine regparm with all attributes but fastcall. */
26478 if (is_attribute_p ("ms_abi", name))
26480 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26482 error ("ms_abi and sysv_abi attributes are not compatible");
26487 else if (is_attribute_p ("sysv_abi", name))
26489 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26491 error ("ms_abi and sysv_abi attributes are not compatible");
26500 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26501 struct attribute_spec.handler. */
26503 ix86_handle_struct_attribute (tree *node, tree name,
26504 tree args ATTRIBUTE_UNUSED,
26505 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26508 if (DECL_P (*node))
26510 if (TREE_CODE (*node) == TYPE_DECL)
26511 type = &TREE_TYPE (*node);
26516 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26517 || TREE_CODE (*type) == UNION_TYPE)))
26519 warning (OPT_Wattributes, "%qE attribute ignored",
26521 *no_add_attrs = true;
26524 else if ((is_attribute_p ("ms_struct", name)
26525 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26526 || ((is_attribute_p ("gcc_struct", name)
26527 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26529 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
26531 *no_add_attrs = true;
26538 ix86_handle_fndecl_attribute (tree *node, tree name,
26539 tree args ATTRIBUTE_UNUSED,
26540 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26542 if (TREE_CODE (*node) != FUNCTION_DECL)
26544 warning (OPT_Wattributes, "%qE attribute only applies to functions",
26546 *no_add_attrs = true;
26552 warning (OPT_Wattributes, "%qE attribute only available for 32-bit",
26557 #ifndef HAVE_AS_IX86_SWAP
26558 sorry ("ms_hook_prologue attribute needs assembler swap suffix support");
26565 ix86_ms_bitfield_layout_p (const_tree record_type)
26567 return (TARGET_MS_BITFIELD_LAYOUT &&
26568 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26569 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26572 /* Returns an expression indicating where the this parameter is
26573 located on entry to the FUNCTION. */
26576 x86_this_parameter (tree function)
26578 tree type = TREE_TYPE (function);
26579 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26584 const int *parm_regs;
26586 if (ix86_function_type_abi (type) == MS_ABI)
26587 parm_regs = x86_64_ms_abi_int_parameter_registers;
26589 parm_regs = x86_64_int_parameter_registers;
26590 return gen_rtx_REG (DImode, parm_regs[aggr]);
26593 nregs = ix86_function_regparm (type, function);
26595 if (nregs > 0 && !stdarg_p (type))
26599 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26600 regno = aggr ? DX_REG : CX_REG;
26608 return gen_rtx_MEM (SImode,
26609 plus_constant (stack_pointer_rtx, 4));
26612 return gen_rtx_REG (SImode, regno);
26615 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26618 /* Determine whether x86_output_mi_thunk can succeed. */
26621 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26622 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26623 HOST_WIDE_INT vcall_offset, const_tree function)
26625 /* 64-bit can handle anything. */
26629 /* For 32-bit, everything's fine if we have one free register. */
26630 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26633 /* Need a free register for vcall_offset. */
26637 /* Need a free register for GOT references. */
26638 if (flag_pic && !(*targetm.binds_local_p) (function))
26641 /* Otherwise ok. */
26645 /* Output the assembler code for a thunk function. THUNK_DECL is the
26646 declaration for the thunk function itself, FUNCTION is the decl for
26647 the target function. DELTA is an immediate constant offset to be
26648 added to THIS. If VCALL_OFFSET is nonzero, the word at
26649 *(*this + vcall_offset) should be added to THIS. */
26652 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26653 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26654 HOST_WIDE_INT vcall_offset, tree function)
26657 rtx this_param = x86_this_parameter (function);
26660 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26661 pull it in now and let DELTA benefit. */
26662 if (REG_P (this_param))
26663 this_reg = this_param;
26664 else if (vcall_offset)
26666 /* Put the this parameter into %eax. */
26667 xops[0] = this_param;
26668 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26669 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26672 this_reg = NULL_RTX;
26674 /* Adjust the this parameter by a fixed constant. */
26677 xops[0] = GEN_INT (delta);
26678 xops[1] = this_reg ? this_reg : this_param;
26681 if (!x86_64_general_operand (xops[0], DImode))
26683 tmp = gen_rtx_REG (DImode, R10_REG);
26685 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26687 xops[1] = this_param;
26689 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26692 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26695 /* Adjust the this parameter by a value stored in the vtable. */
26699 tmp = gen_rtx_REG (DImode, R10_REG);
26702 int tmp_regno = CX_REG;
26703 if (lookup_attribute ("fastcall",
26704 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26705 tmp_regno = AX_REG;
26706 tmp = gen_rtx_REG (SImode, tmp_regno);
26709 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26711 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26713 /* Adjust the this parameter. */
26714 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26715 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26717 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26718 xops[0] = GEN_INT (vcall_offset);
26720 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26721 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26723 xops[1] = this_reg;
26724 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26727 /* If necessary, drop THIS back to its stack slot. */
26728 if (this_reg && this_reg != this_param)
26730 xops[0] = this_reg;
26731 xops[1] = this_param;
26732 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26735 xops[0] = XEXP (DECL_RTL (function), 0);
26738 if (!flag_pic || (*targetm.binds_local_p) (function))
26739 output_asm_insn ("jmp\t%P0", xops);
26740 /* All thunks should be in the same object as their target,
26741 and thus binds_local_p should be true. */
26742 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26743 gcc_unreachable ();
26746 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26747 tmp = gen_rtx_CONST (Pmode, tmp);
26748 tmp = gen_rtx_MEM (QImode, tmp);
26750 output_asm_insn ("jmp\t%A0", xops);
26755 if (!flag_pic || (*targetm.binds_local_p) (function))
26756 output_asm_insn ("jmp\t%P0", xops);
26761 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26762 tmp = (gen_rtx_SYMBOL_REF
26764 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26765 tmp = gen_rtx_MEM (QImode, tmp);
26767 output_asm_insn ("jmp\t%0", xops);
26770 #endif /* TARGET_MACHO */
26772 tmp = gen_rtx_REG (SImode, CX_REG);
26773 output_set_got (tmp, NULL_RTX);
26776 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26777 output_asm_insn ("jmp\t{*}%1", xops);
26783 x86_file_start (void)
26785 default_file_start ();
26787 darwin_file_start ();
26789 if (X86_FILE_START_VERSION_DIRECTIVE)
26790 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26791 if (X86_FILE_START_FLTUSED)
26792 fputs ("\t.global\t__fltused\n", asm_out_file);
26793 if (ix86_asm_dialect == ASM_INTEL)
26794 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26798 x86_field_alignment (tree field, int computed)
26800 enum machine_mode mode;
26801 tree type = TREE_TYPE (field);
26803 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26805 mode = TYPE_MODE (strip_array_types (type));
26806 if (mode == DFmode || mode == DCmode
26807 || GET_MODE_CLASS (mode) == MODE_INT
26808 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26809 return MIN (32, computed);
26813 /* Output assembler code to FILE to increment profiler label # LABELNO
26814 for profiling a function entry. */
26816 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26820 #ifndef NO_PROFILE_COUNTERS
26821 fprintf (file, "\tleaq\t" LPREFIX "P%d@(%%rip),%%r11\n", labelno);
26824 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26825 fputs ("\tcall\t*" MCOUNT_NAME "@GOTPCREL(%rip)\n", file);
26827 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
26831 #ifndef NO_PROFILE_COUNTERS
26832 fprintf (file, "\tleal\t" LPREFIX "P%d@GOTOFF(%%ebx),%%" PROFILE_COUNT_REGISTER "\n",
26835 fputs ("\tcall\t*" MCOUNT_NAME "@GOT(%ebx)\n", file);
26839 #ifndef NO_PROFILE_COUNTERS
26840 fprintf (file, "\tmovl\t$" LPREFIX "P%d,%%" PROFILE_COUNT_REGISTER "\n",
26843 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
26847 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26848 /* We don't have exact information about the insn sizes, but we may assume
26849 quite safely that we are informed about all 1 byte insns and memory
26850 address sizes. This is enough to eliminate unnecessary padding in
26854 min_insn_size (rtx insn)
26858 if (!INSN_P (insn) || !active_insn_p (insn))
26861 /* Discard alignments we've emit and jump instructions. */
26862 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26863 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26865 if (JUMP_TABLE_DATA_P (insn))
26868 /* Important case - calls are always 5 bytes.
26869 It is common to have many calls in the row. */
26871 && symbolic_reference_mentioned_p (PATTERN (insn))
26872 && !SIBLING_CALL_P (insn))
26874 len = get_attr_length (insn);
26878 /* For normal instructions we rely on get_attr_length being exact,
26879 with a few exceptions. */
26880 if (!JUMP_P (insn))
26882 enum attr_type type = get_attr_type (insn);
26887 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
26888 || asm_noperands (PATTERN (insn)) >= 0)
26895 /* Otherwise trust get_attr_length. */
26899 l = get_attr_length_address (insn);
26900 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26909 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26913 ix86_avoid_jump_mispredicts (void)
26915 rtx insn, start = get_insns ();
26916 int nbytes = 0, njumps = 0;
26919 /* Look for all minimal intervals of instructions containing 4 jumps.
26920 The intervals are bounded by START and INSN. NBYTES is the total
26921 size of instructions in the interval including INSN and not including
26922 START. When the NBYTES is smaller than 16 bytes, it is possible
26923 that the end of START and INSN ends up in the same 16byte page.
26925 The smallest offset in the page INSN can start is the case where START
26926 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26927 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
26929 for (insn = start; insn; insn = NEXT_INSN (insn))
26933 if (LABEL_P (insn))
26935 int align = label_to_alignment (insn);
26936 int max_skip = label_to_max_skip (insn);
26940 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
26941 already in the current 16 byte page, because otherwise
26942 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
26943 bytes to reach 16 byte boundary. */
26945 || (align <= 3 && max_skip != (1 << align) - 1))
26948 fprintf (dump_file, "Label %i with max_skip %i\n",
26949 INSN_UID (insn), max_skip);
26952 while (nbytes + max_skip >= 16)
26954 start = NEXT_INSN (start);
26955 if ((JUMP_P (start)
26956 && GET_CODE (PATTERN (start)) != ADDR_VEC
26957 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26959 njumps--, isjump = 1;
26962 nbytes -= min_insn_size (start);
26968 min_size = min_insn_size (insn);
26969 nbytes += min_size;
26971 fprintf (dump_file, "Insn %i estimated to %i bytes\n",
26972 INSN_UID (insn), min_size);
26974 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26975 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26983 start = NEXT_INSN (start);
26984 if ((JUMP_P (start)
26985 && GET_CODE (PATTERN (start)) != ADDR_VEC
26986 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26988 njumps--, isjump = 1;
26991 nbytes -= min_insn_size (start);
26993 gcc_assert (njumps >= 0);
26995 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26996 INSN_UID (start), INSN_UID (insn), nbytes);
26998 if (njumps == 3 && isjump && nbytes < 16)
27000 int padsize = 15 - nbytes + min_insn_size (insn);
27003 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
27004 INSN_UID (insn), padsize);
27005 emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
27011 /* AMD Athlon works faster
27012 when RET is not destination of conditional jump or directly preceded
27013 by other jump instruction. We avoid the penalty by inserting NOP just
27014 before the RET instructions in such cases. */
27016 ix86_pad_returns (void)
27021 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
27023 basic_block bb = e->src;
27024 rtx ret = BB_END (bb);
27026 bool replace = false;
27028 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
27029 || optimize_bb_for_size_p (bb))
27031 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
27032 if (active_insn_p (prev) || LABEL_P (prev))
27034 if (prev && LABEL_P (prev))
27039 FOR_EACH_EDGE (e, ei, bb->preds)
27040 if (EDGE_FREQUENCY (e) && e->src->index >= 0
27041 && !(e->flags & EDGE_FALLTHRU))
27046 prev = prev_active_insn (ret);
27048 && ((JUMP_P (prev) && any_condjump_p (prev))
27051 /* Empty functions get branch mispredict even when the jump destination
27052 is not visible to us. */
27053 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
27058 emit_jump_insn_before (gen_return_internal_long (), ret);
27064 /* Implement machine specific optimizations. We implement padding of returns
27065 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
27069 if (optimize && optimize_function_for_speed_p (cfun))
27071 if (TARGET_PAD_RETURNS)
27072 ix86_pad_returns ();
27073 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
27074 if (TARGET_FOUR_JUMP_LIMIT)
27075 ix86_avoid_jump_mispredicts ();
27080 /* Return nonzero when QImode register that must be represented via REX prefix
27083 x86_extended_QIreg_mentioned_p (rtx insn)
27086 extract_insn_cached (insn);
27087 for (i = 0; i < recog_data.n_operands; i++)
27088 if (REG_P (recog_data.operand[i])
27089 && REGNO (recog_data.operand[i]) > BX_REG)
27094 /* Return nonzero when P points to register encoded via REX prefix.
27095 Called via for_each_rtx. */
27097 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
27099 unsigned int regno;
27102 regno = REGNO (*p);
27103 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
27106 /* Return true when INSN mentions register that must be encoded using REX
27109 x86_extended_reg_mentioned_p (rtx insn)
27111 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
27112 extended_reg_mentioned_1, NULL);
27115 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
27116 optabs would emit if we didn't have TFmode patterns. */
27119 x86_emit_floatuns (rtx operands[2])
27121 rtx neglab, donelab, i0, i1, f0, in, out;
27122 enum machine_mode mode, inmode;
27124 inmode = GET_MODE (operands[1]);
27125 gcc_assert (inmode == SImode || inmode == DImode);
27128 in = force_reg (inmode, operands[1]);
27129 mode = GET_MODE (out);
27130 neglab = gen_label_rtx ();
27131 donelab = gen_label_rtx ();
27132 f0 = gen_reg_rtx (mode);
27134 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
27136 expand_float (out, in, 0);
27138 emit_jump_insn (gen_jump (donelab));
27141 emit_label (neglab);
27143 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
27145 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
27147 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
27149 expand_float (f0, i0, 0);
27151 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
27153 emit_label (donelab);
27156 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27157 with all elements equal to VAR. Return true if successful. */
27160 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
27161 rtx target, rtx val)
27163 enum machine_mode hmode, smode, wsmode, wvmode;
27178 val = force_reg (GET_MODE_INNER (mode), val);
27179 x = gen_rtx_VEC_DUPLICATE (mode, val);
27180 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27186 if (TARGET_SSE || TARGET_3DNOW_A)
27188 val = gen_lowpart (SImode, val);
27189 x = gen_rtx_TRUNCATE (HImode, val);
27190 x = gen_rtx_VEC_DUPLICATE (mode, x);
27191 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27213 /* Extend HImode to SImode using a paradoxical SUBREG. */
27214 tmp1 = gen_reg_rtx (SImode);
27215 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27216 /* Insert the SImode value as low element of V4SImode vector. */
27217 tmp2 = gen_reg_rtx (V4SImode);
27218 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27219 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27220 CONST0_RTX (V4SImode),
27222 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27223 /* Cast the V4SImode vector back to a V8HImode vector. */
27224 tmp1 = gen_reg_rtx (V8HImode);
27225 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
27226 /* Duplicate the low short through the whole low SImode word. */
27227 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
27228 /* Cast the V8HImode vector back to a V4SImode vector. */
27229 tmp2 = gen_reg_rtx (V4SImode);
27230 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27231 /* Replicate the low element of the V4SImode vector. */
27232 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27233 /* Cast the V2SImode back to V8HImode, and store in target. */
27234 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
27245 /* Extend QImode to SImode using a paradoxical SUBREG. */
27246 tmp1 = gen_reg_rtx (SImode);
27247 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27248 /* Insert the SImode value as low element of V4SImode vector. */
27249 tmp2 = gen_reg_rtx (V4SImode);
27250 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27251 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27252 CONST0_RTX (V4SImode),
27254 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27255 /* Cast the V4SImode vector back to a V16QImode vector. */
27256 tmp1 = gen_reg_rtx (V16QImode);
27257 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
27258 /* Duplicate the low byte through the whole low SImode word. */
27259 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27260 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27261 /* Cast the V16QImode vector back to a V4SImode vector. */
27262 tmp2 = gen_reg_rtx (V4SImode);
27263 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27264 /* Replicate the low element of the V4SImode vector. */
27265 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27266 /* Cast the V2SImode back to V16QImode, and store in target. */
27267 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
27275 /* Replicate the value once into the next wider mode and recurse. */
27276 val = convert_modes (wsmode, smode, val, true);
27277 x = expand_simple_binop (wsmode, ASHIFT, val,
27278 GEN_INT (GET_MODE_BITSIZE (smode)),
27279 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27280 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
27282 x = gen_reg_rtx (wvmode);
27283 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
27284 gcc_unreachable ();
27285 emit_move_insn (target, gen_lowpart (mode, x));
27308 rtx tmp = gen_reg_rtx (hmode);
27309 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
27310 emit_insn (gen_rtx_SET (VOIDmode, target,
27311 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
27320 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27321 whose ONE_VAR element is VAR, and other elements are zero. Return true
27325 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
27326 rtx target, rtx var, int one_var)
27328 enum machine_mode vsimode;
27331 bool use_vector_set = false;
27336 /* For SSE4.1, we normally use vector set. But if the second
27337 element is zero and inter-unit moves are OK, we use movq
27339 use_vector_set = (TARGET_64BIT
27341 && !(TARGET_INTER_UNIT_MOVES
27347 use_vector_set = TARGET_SSE4_1;
27350 use_vector_set = TARGET_SSE2;
27353 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27360 use_vector_set = TARGET_AVX;
27363 /* Use ix86_expand_vector_set in 64bit mode only. */
27364 use_vector_set = TARGET_AVX && TARGET_64BIT;
27370 if (use_vector_set)
27372 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27373 var = force_reg (GET_MODE_INNER (mode), var);
27374 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27390 var = force_reg (GET_MODE_INNER (mode), var);
27391 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27392 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27397 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27398 new_target = gen_reg_rtx (mode);
27400 new_target = target;
27401 var = force_reg (GET_MODE_INNER (mode), var);
27402 x = gen_rtx_VEC_DUPLICATE (mode, var);
27403 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27404 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27407 /* We need to shuffle the value to the correct position, so
27408 create a new pseudo to store the intermediate result. */
27410 /* With SSE2, we can use the integer shuffle insns. */
27411 if (mode != V4SFmode && TARGET_SSE2)
27413 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27415 GEN_INT (one_var == 1 ? 0 : 1),
27416 GEN_INT (one_var == 2 ? 0 : 1),
27417 GEN_INT (one_var == 3 ? 0 : 1)));
27418 if (target != new_target)
27419 emit_move_insn (target, new_target);
27423 /* Otherwise convert the intermediate result to V4SFmode and
27424 use the SSE1 shuffle instructions. */
27425 if (mode != V4SFmode)
27427 tmp = gen_reg_rtx (V4SFmode);
27428 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27433 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27435 GEN_INT (one_var == 1 ? 0 : 1),
27436 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27437 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27439 if (mode != V4SFmode)
27440 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27441 else if (tmp != target)
27442 emit_move_insn (target, tmp);
27444 else if (target != new_target)
27445 emit_move_insn (target, new_target);
27450 vsimode = V4SImode;
27456 vsimode = V2SImode;
27462 /* Zero extend the variable element to SImode and recurse. */
27463 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27465 x = gen_reg_rtx (vsimode);
27466 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27468 gcc_unreachable ();
27470 emit_move_insn (target, gen_lowpart (mode, x));
27478 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27479 consisting of the values in VALS. It is known that all elements
27480 except ONE_VAR are constants. Return true if successful. */
27483 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27484 rtx target, rtx vals, int one_var)
27486 rtx var = XVECEXP (vals, 0, one_var);
27487 enum machine_mode wmode;
27490 const_vec = copy_rtx (vals);
27491 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27492 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27500 /* For the two element vectors, it's just as easy to use
27501 the general case. */
27505 /* Use ix86_expand_vector_set in 64bit mode only. */
27528 /* There's no way to set one QImode entry easily. Combine
27529 the variable value with its adjacent constant value, and
27530 promote to an HImode set. */
27531 x = XVECEXP (vals, 0, one_var ^ 1);
27534 var = convert_modes (HImode, QImode, var, true);
27535 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27536 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27537 x = GEN_INT (INTVAL (x) & 0xff);
27541 var = convert_modes (HImode, QImode, var, true);
27542 x = gen_int_mode (INTVAL (x) << 8, HImode);
27544 if (x != const0_rtx)
27545 var = expand_simple_binop (HImode, IOR, var, x, var,
27546 1, OPTAB_LIB_WIDEN);
27548 x = gen_reg_rtx (wmode);
27549 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27550 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27552 emit_move_insn (target, gen_lowpart (mode, x));
27559 emit_move_insn (target, const_vec);
27560 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27564 /* A subroutine of ix86_expand_vector_init_general. Use vector
27565 concatenate to handle the most general case: all values variable,
27566 and none identical. */
27569 ix86_expand_vector_init_concat (enum machine_mode mode,
27570 rtx target, rtx *ops, int n)
27572 enum machine_mode cmode, hmode = VOIDmode;
27573 rtx first[8], second[4];
27613 gcc_unreachable ();
27616 if (!register_operand (ops[1], cmode))
27617 ops[1] = force_reg (cmode, ops[1]);
27618 if (!register_operand (ops[0], cmode))
27619 ops[0] = force_reg (cmode, ops[0]);
27620 emit_insn (gen_rtx_SET (VOIDmode, target,
27621 gen_rtx_VEC_CONCAT (mode, ops[0],
27641 gcc_unreachable ();
27657 gcc_unreachable ();
27662 /* FIXME: We process inputs backward to help RA. PR 36222. */
27665 for (; i > 0; i -= 2, j--)
27667 first[j] = gen_reg_rtx (cmode);
27668 v = gen_rtvec (2, ops[i - 1], ops[i]);
27669 ix86_expand_vector_init (false, first[j],
27670 gen_rtx_PARALLEL (cmode, v));
27676 gcc_assert (hmode != VOIDmode);
27677 for (i = j = 0; i < n; i += 2, j++)
27679 second[j] = gen_reg_rtx (hmode);
27680 ix86_expand_vector_init_concat (hmode, second [j],
27684 ix86_expand_vector_init_concat (mode, target, second, n);
27687 ix86_expand_vector_init_concat (mode, target, first, n);
27691 gcc_unreachable ();
27695 /* A subroutine of ix86_expand_vector_init_general. Use vector
27696 interleave to handle the most general case: all values variable,
27697 and none identical. */
27700 ix86_expand_vector_init_interleave (enum machine_mode mode,
27701 rtx target, rtx *ops, int n)
27703 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27706 rtx (*gen_load_even) (rtx, rtx, rtx);
27707 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27708 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27713 gen_load_even = gen_vec_setv8hi;
27714 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27715 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27716 inner_mode = HImode;
27717 first_imode = V4SImode;
27718 second_imode = V2DImode;
27719 third_imode = VOIDmode;
27722 gen_load_even = gen_vec_setv16qi;
27723 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27724 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27725 inner_mode = QImode;
27726 first_imode = V8HImode;
27727 second_imode = V4SImode;
27728 third_imode = V2DImode;
27731 gcc_unreachable ();
27734 for (i = 0; i < n; i++)
27736 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27737 op0 = gen_reg_rtx (SImode);
27738 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27740 /* Insert the SImode value as low element of V4SImode vector. */
27741 op1 = gen_reg_rtx (V4SImode);
27742 op0 = gen_rtx_VEC_MERGE (V4SImode,
27743 gen_rtx_VEC_DUPLICATE (V4SImode,
27745 CONST0_RTX (V4SImode),
27747 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27749 /* Cast the V4SImode vector back to a vector in orignal mode. */
27750 op0 = gen_reg_rtx (mode);
27751 emit_move_insn (op0, gen_lowpart (mode, op1));
27753 /* Load even elements into the second positon. */
27754 emit_insn ((*gen_load_even) (op0,
27755 force_reg (inner_mode,
27759 /* Cast vector to FIRST_IMODE vector. */
27760 ops[i] = gen_reg_rtx (first_imode);
27761 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27764 /* Interleave low FIRST_IMODE vectors. */
27765 for (i = j = 0; i < n; i += 2, j++)
27767 op0 = gen_reg_rtx (first_imode);
27768 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27770 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27771 ops[j] = gen_reg_rtx (second_imode);
27772 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27775 /* Interleave low SECOND_IMODE vectors. */
27776 switch (second_imode)
27779 for (i = j = 0; i < n / 2; i += 2, j++)
27781 op0 = gen_reg_rtx (second_imode);
27782 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27785 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27787 ops[j] = gen_reg_rtx (third_imode);
27788 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27790 second_imode = V2DImode;
27791 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27795 op0 = gen_reg_rtx (second_imode);
27796 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27799 /* Cast the SECOND_IMODE vector back to a vector on original
27801 emit_insn (gen_rtx_SET (VOIDmode, target,
27802 gen_lowpart (mode, op0)));
27806 gcc_unreachable ();
27810 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27811 all values variable, and none identical. */
27814 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27815 rtx target, rtx vals)
27817 rtx ops[32], op0, op1;
27818 enum machine_mode half_mode = VOIDmode;
27825 if (!mmx_ok && !TARGET_SSE)
27837 n = GET_MODE_NUNITS (mode);
27838 for (i = 0; i < n; i++)
27839 ops[i] = XVECEXP (vals, 0, i);
27840 ix86_expand_vector_init_concat (mode, target, ops, n);
27844 half_mode = V16QImode;
27848 half_mode = V8HImode;
27852 n = GET_MODE_NUNITS (mode);
27853 for (i = 0; i < n; i++)
27854 ops[i] = XVECEXP (vals, 0, i);
27855 op0 = gen_reg_rtx (half_mode);
27856 op1 = gen_reg_rtx (half_mode);
27857 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27859 ix86_expand_vector_init_interleave (half_mode, op1,
27860 &ops [n >> 1], n >> 2);
27861 emit_insn (gen_rtx_SET (VOIDmode, target,
27862 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27866 if (!TARGET_SSE4_1)
27874 /* Don't use ix86_expand_vector_init_interleave if we can't
27875 move from GPR to SSE register directly. */
27876 if (!TARGET_INTER_UNIT_MOVES)
27879 n = GET_MODE_NUNITS (mode);
27880 for (i = 0; i < n; i++)
27881 ops[i] = XVECEXP (vals, 0, i);
27882 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27890 gcc_unreachable ();
27894 int i, j, n_elts, n_words, n_elt_per_word;
27895 enum machine_mode inner_mode;
27896 rtx words[4], shift;
27898 inner_mode = GET_MODE_INNER (mode);
27899 n_elts = GET_MODE_NUNITS (mode);
27900 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27901 n_elt_per_word = n_elts / n_words;
27902 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27904 for (i = 0; i < n_words; ++i)
27906 rtx word = NULL_RTX;
27908 for (j = 0; j < n_elt_per_word; ++j)
27910 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27911 elt = convert_modes (word_mode, inner_mode, elt, true);
27917 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27918 word, 1, OPTAB_LIB_WIDEN);
27919 word = expand_simple_binop (word_mode, IOR, word, elt,
27920 word, 1, OPTAB_LIB_WIDEN);
27928 emit_move_insn (target, gen_lowpart (mode, words[0]));
27929 else if (n_words == 2)
27931 rtx tmp = gen_reg_rtx (mode);
27932 emit_clobber (tmp);
27933 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27934 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27935 emit_move_insn (target, tmp);
27937 else if (n_words == 4)
27939 rtx tmp = gen_reg_rtx (V4SImode);
27940 gcc_assert (word_mode == SImode);
27941 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27942 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27943 emit_move_insn (target, gen_lowpart (mode, tmp));
27946 gcc_unreachable ();
27950 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27951 instructions unless MMX_OK is true. */
27954 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27956 enum machine_mode mode = GET_MODE (target);
27957 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27958 int n_elts = GET_MODE_NUNITS (mode);
27959 int n_var = 0, one_var = -1;
27960 bool all_same = true, all_const_zero = true;
27964 for (i = 0; i < n_elts; ++i)
27966 x = XVECEXP (vals, 0, i);
27967 if (!(CONST_INT_P (x)
27968 || GET_CODE (x) == CONST_DOUBLE
27969 || GET_CODE (x) == CONST_FIXED))
27970 n_var++, one_var = i;
27971 else if (x != CONST0_RTX (inner_mode))
27972 all_const_zero = false;
27973 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27977 /* Constants are best loaded from the constant pool. */
27980 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27984 /* If all values are identical, broadcast the value. */
27986 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27987 XVECEXP (vals, 0, 0)))
27990 /* Values where only one field is non-constant are best loaded from
27991 the pool and overwritten via move later. */
27995 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27996 XVECEXP (vals, 0, one_var),
28000 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
28004 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
28008 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
28010 enum machine_mode mode = GET_MODE (target);
28011 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28012 enum machine_mode half_mode;
28013 bool use_vec_merge = false;
28015 static rtx (*gen_extract[6][2]) (rtx, rtx)
28017 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
28018 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
28019 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
28020 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
28021 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
28022 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
28024 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
28026 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
28027 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
28028 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
28029 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
28030 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
28031 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
28041 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
28042 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
28044 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
28046 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
28047 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28053 use_vec_merge = TARGET_SSE4_1;
28061 /* For the two element vectors, we implement a VEC_CONCAT with
28062 the extraction of the other element. */
28064 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
28065 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
28068 op0 = val, op1 = tmp;
28070 op0 = tmp, op1 = val;
28072 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
28073 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28078 use_vec_merge = TARGET_SSE4_1;
28085 use_vec_merge = true;
28089 /* tmp = target = A B C D */
28090 tmp = copy_to_reg (target);
28091 /* target = A A B B */
28092 emit_insn (gen_sse_unpcklps (target, target, target));
28093 /* target = X A B B */
28094 ix86_expand_vector_set (false, target, val, 0);
28095 /* target = A X C D */
28096 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28097 const1_rtx, const0_rtx,
28098 GEN_INT (2+4), GEN_INT (3+4)));
28102 /* tmp = target = A B C D */
28103 tmp = copy_to_reg (target);
28104 /* tmp = X B C D */
28105 ix86_expand_vector_set (false, tmp, val, 0);
28106 /* target = A B X D */
28107 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28108 const0_rtx, const1_rtx,
28109 GEN_INT (0+4), GEN_INT (3+4)));
28113 /* tmp = target = A B C D */
28114 tmp = copy_to_reg (target);
28115 /* tmp = X B C D */
28116 ix86_expand_vector_set (false, tmp, val, 0);
28117 /* target = A B X D */
28118 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28119 const0_rtx, const1_rtx,
28120 GEN_INT (2+4), GEN_INT (0+4)));
28124 gcc_unreachable ();
28129 use_vec_merge = TARGET_SSE4_1;
28133 /* Element 0 handled by vec_merge below. */
28136 use_vec_merge = true;
28142 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28143 store into element 0, then shuffle them back. */
28147 order[0] = GEN_INT (elt);
28148 order[1] = const1_rtx;
28149 order[2] = const2_rtx;
28150 order[3] = GEN_INT (3);
28151 order[elt] = const0_rtx;
28153 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28154 order[1], order[2], order[3]));
28156 ix86_expand_vector_set (false, target, val, 0);
28158 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28159 order[1], order[2], order[3]));
28163 /* For SSE1, we have to reuse the V4SF code. */
28164 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
28165 gen_lowpart (SFmode, val), elt);
28170 use_vec_merge = TARGET_SSE2;
28173 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28177 use_vec_merge = TARGET_SSE4_1;
28184 half_mode = V16QImode;
28190 half_mode = V8HImode;
28196 half_mode = V4SImode;
28202 half_mode = V2DImode;
28208 half_mode = V4SFmode;
28214 half_mode = V2DFmode;
28220 /* Compute offset. */
28224 gcc_assert (i <= 1);
28226 /* Extract the half. */
28227 tmp = gen_reg_rtx (half_mode);
28228 emit_insn ((*gen_extract[j][i]) (tmp, target));
28230 /* Put val in tmp at elt. */
28231 ix86_expand_vector_set (false, tmp, val, elt);
28234 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
28243 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
28244 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
28245 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28249 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28251 emit_move_insn (mem, target);
28253 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28254 emit_move_insn (tmp, val);
28256 emit_move_insn (target, mem);
28261 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
28263 enum machine_mode mode = GET_MODE (vec);
28264 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28265 bool use_vec_extr = false;
28278 use_vec_extr = true;
28282 use_vec_extr = TARGET_SSE4_1;
28294 tmp = gen_reg_rtx (mode);
28295 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
28296 GEN_INT (elt), GEN_INT (elt),
28297 GEN_INT (elt+4), GEN_INT (elt+4)));
28301 tmp = gen_reg_rtx (mode);
28302 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
28306 gcc_unreachable ();
28309 use_vec_extr = true;
28314 use_vec_extr = TARGET_SSE4_1;
28328 tmp = gen_reg_rtx (mode);
28329 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
28330 GEN_INT (elt), GEN_INT (elt),
28331 GEN_INT (elt), GEN_INT (elt)));
28335 tmp = gen_reg_rtx (mode);
28336 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
28340 gcc_unreachable ();
28343 use_vec_extr = true;
28348 /* For SSE1, we have to reuse the V4SF code. */
28349 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
28350 gen_lowpart (V4SFmode, vec), elt);
28356 use_vec_extr = TARGET_SSE2;
28359 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28363 use_vec_extr = TARGET_SSE4_1;
28367 /* ??? Could extract the appropriate HImode element and shift. */
28374 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28375 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28377 /* Let the rtl optimizers know about the zero extension performed. */
28378 if (inner_mode == QImode || inner_mode == HImode)
28380 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28381 target = gen_lowpart (SImode, target);
28384 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28388 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28390 emit_move_insn (mem, vec);
28392 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28393 emit_move_insn (target, tmp);
28397 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28398 pattern to reduce; DEST is the destination; IN is the input vector. */
28401 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28403 rtx tmp1, tmp2, tmp3;
28405 tmp1 = gen_reg_rtx (V4SFmode);
28406 tmp2 = gen_reg_rtx (V4SFmode);
28407 tmp3 = gen_reg_rtx (V4SFmode);
28409 emit_insn (gen_sse_movhlps (tmp1, in, in));
28410 emit_insn (fn (tmp2, tmp1, in));
28412 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28413 const1_rtx, const1_rtx,
28414 GEN_INT (1+4), GEN_INT (1+4)));
28415 emit_insn (fn (dest, tmp2, tmp3));
28418 /* Target hook for scalar_mode_supported_p. */
28420 ix86_scalar_mode_supported_p (enum machine_mode mode)
28422 if (DECIMAL_FLOAT_MODE_P (mode))
28423 return default_decimal_float_supported_p ();
28424 else if (mode == TFmode)
28427 return default_scalar_mode_supported_p (mode);
28430 /* Implements target hook vector_mode_supported_p. */
28432 ix86_vector_mode_supported_p (enum machine_mode mode)
28434 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28436 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28438 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28440 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28442 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28447 /* Target hook for c_mode_for_suffix. */
28448 static enum machine_mode
28449 ix86_c_mode_for_suffix (char suffix)
28459 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28461 We do this in the new i386 backend to maintain source compatibility
28462 with the old cc0-based compiler. */
28465 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28466 tree inputs ATTRIBUTE_UNUSED,
28469 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28471 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28476 /* Implements target vector targetm.asm.encode_section_info. This
28477 is not used by netware. */
28479 static void ATTRIBUTE_UNUSED
28480 ix86_encode_section_info (tree decl, rtx rtl, int first)
28482 default_encode_section_info (decl, rtl, first);
28484 if (TREE_CODE (decl) == VAR_DECL
28485 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28486 && ix86_in_large_data_p (decl))
28487 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28490 /* Worker function for REVERSE_CONDITION. */
28493 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28495 return (mode != CCFPmode && mode != CCFPUmode
28496 ? reverse_condition (code)
28497 : reverse_condition_maybe_unordered (code));
28500 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28504 output_387_reg_move (rtx insn, rtx *operands)
28506 if (REG_P (operands[0]))
28508 if (REG_P (operands[1])
28509 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28511 if (REGNO (operands[0]) == FIRST_STACK_REG)
28512 return output_387_ffreep (operands, 0);
28513 return "fstp\t%y0";
28515 if (STACK_TOP_P (operands[0]))
28516 return "fld%Z1\t%y1";
28519 else if (MEM_P (operands[0]))
28521 gcc_assert (REG_P (operands[1]));
28522 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28523 return "fstp%Z0\t%y0";
28526 /* There is no non-popping store to memory for XFmode.
28527 So if we need one, follow the store with a load. */
28528 if (GET_MODE (operands[0]) == XFmode)
28529 return "fstp%Z0\t%y0\n\tfld%Z0\t%y0";
28531 return "fst%Z0\t%y0";
28538 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28539 FP status register is set. */
28542 ix86_emit_fp_unordered_jump (rtx label)
28544 rtx reg = gen_reg_rtx (HImode);
28547 emit_insn (gen_x86_fnstsw_1 (reg));
28549 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28551 emit_insn (gen_x86_sahf_1 (reg));
28553 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28554 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28558 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28560 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28561 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28564 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28565 gen_rtx_LABEL_REF (VOIDmode, label),
28567 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28569 emit_jump_insn (temp);
28570 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28573 /* Output code to perform a log1p XFmode calculation. */
28575 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28577 rtx label1 = gen_label_rtx ();
28578 rtx label2 = gen_label_rtx ();
28580 rtx tmp = gen_reg_rtx (XFmode);
28581 rtx tmp2 = gen_reg_rtx (XFmode);
28584 emit_insn (gen_absxf2 (tmp, op1));
28585 test = gen_rtx_GE (VOIDmode, tmp,
28586 CONST_DOUBLE_FROM_REAL_VALUE (
28587 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28589 emit_jump_insn (gen_cbranchxf4 (test, XEXP (test, 0), XEXP (test, 1), label1));
28591 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28592 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28593 emit_jump (label2);
28595 emit_label (label1);
28596 emit_move_insn (tmp, CONST1_RTX (XFmode));
28597 emit_insn (gen_addxf3 (tmp, op1, tmp));
28598 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28599 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28601 emit_label (label2);
28604 /* Output code to perform a Newton-Rhapson approximation of a single precision
28605 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28607 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28609 rtx x0, x1, e0, e1, two;
28611 x0 = gen_reg_rtx (mode);
28612 e0 = gen_reg_rtx (mode);
28613 e1 = gen_reg_rtx (mode);
28614 x1 = gen_reg_rtx (mode);
28616 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28618 if (VECTOR_MODE_P (mode))
28619 two = ix86_build_const_vector (SFmode, true, two);
28621 two = force_reg (mode, two);
28623 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28625 /* x0 = rcp(b) estimate */
28626 emit_insn (gen_rtx_SET (VOIDmode, x0,
28627 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28630 emit_insn (gen_rtx_SET (VOIDmode, e0,
28631 gen_rtx_MULT (mode, x0, b)));
28633 emit_insn (gen_rtx_SET (VOIDmode, e1,
28634 gen_rtx_MINUS (mode, two, e0)));
28636 emit_insn (gen_rtx_SET (VOIDmode, x1,
28637 gen_rtx_MULT (mode, x0, e1)));
28639 emit_insn (gen_rtx_SET (VOIDmode, res,
28640 gen_rtx_MULT (mode, a, x1)));
28643 /* Output code to perform a Newton-Rhapson approximation of a
28644 single precision floating point [reciprocal] square root. */
28646 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28649 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28652 x0 = gen_reg_rtx (mode);
28653 e0 = gen_reg_rtx (mode);
28654 e1 = gen_reg_rtx (mode);
28655 e2 = gen_reg_rtx (mode);
28656 e3 = gen_reg_rtx (mode);
28658 real_from_integer (&r, VOIDmode, -3, -1, 0);
28659 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28661 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28662 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28664 if (VECTOR_MODE_P (mode))
28666 mthree = ix86_build_const_vector (SFmode, true, mthree);
28667 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28670 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28671 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28673 /* x0 = rsqrt(a) estimate */
28674 emit_insn (gen_rtx_SET (VOIDmode, x0,
28675 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28678 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28683 zero = gen_reg_rtx (mode);
28684 mask = gen_reg_rtx (mode);
28686 zero = force_reg (mode, CONST0_RTX(mode));
28687 emit_insn (gen_rtx_SET (VOIDmode, mask,
28688 gen_rtx_NE (mode, zero, a)));
28690 emit_insn (gen_rtx_SET (VOIDmode, x0,
28691 gen_rtx_AND (mode, x0, mask)));
28695 emit_insn (gen_rtx_SET (VOIDmode, e0,
28696 gen_rtx_MULT (mode, x0, a)));
28698 emit_insn (gen_rtx_SET (VOIDmode, e1,
28699 gen_rtx_MULT (mode, e0, x0)));
28702 mthree = force_reg (mode, mthree);
28703 emit_insn (gen_rtx_SET (VOIDmode, e2,
28704 gen_rtx_PLUS (mode, e1, mthree)));
28706 mhalf = force_reg (mode, mhalf);
28708 /* e3 = -.5 * x0 */
28709 emit_insn (gen_rtx_SET (VOIDmode, e3,
28710 gen_rtx_MULT (mode, x0, mhalf)));
28712 /* e3 = -.5 * e0 */
28713 emit_insn (gen_rtx_SET (VOIDmode, e3,
28714 gen_rtx_MULT (mode, e0, mhalf)));
28715 /* ret = e2 * e3 */
28716 emit_insn (gen_rtx_SET (VOIDmode, res,
28717 gen_rtx_MULT (mode, e2, e3)));
28720 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28722 static void ATTRIBUTE_UNUSED
28723 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28726 /* With Binutils 2.15, the "@unwind" marker must be specified on
28727 every occurrence of the ".eh_frame" section, not just the first
28730 && strcmp (name, ".eh_frame") == 0)
28732 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28733 flags & SECTION_WRITE ? "aw" : "a");
28736 default_elf_asm_named_section (name, flags, decl);
28739 /* Return the mangling of TYPE if it is an extended fundamental type. */
28741 static const char *
28742 ix86_mangle_type (const_tree type)
28744 type = TYPE_MAIN_VARIANT (type);
28746 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28747 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28750 switch (TYPE_MODE (type))
28753 /* __float128 is "g". */
28756 /* "long double" or __float80 is "e". */
28763 /* For 32-bit code we can save PIC register setup by using
28764 __stack_chk_fail_local hidden function instead of calling
28765 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28766 register, so it is better to call __stack_chk_fail directly. */
28769 ix86_stack_protect_fail (void)
28771 return TARGET_64BIT
28772 ? default_external_stack_protect_fail ()
28773 : default_hidden_stack_protect_fail ();
28776 /* Select a format to encode pointers in exception handling data. CODE
28777 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28778 true if the symbol may be affected by dynamic relocations.
28780 ??? All x86 object file formats are capable of representing this.
28781 After all, the relocation needed is the same as for the call insn.
28782 Whether or not a particular assembler allows us to enter such, I
28783 guess we'll have to see. */
28785 asm_preferred_eh_data_format (int code, int global)
28789 int type = DW_EH_PE_sdata8;
28791 || ix86_cmodel == CM_SMALL_PIC
28792 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28793 type = DW_EH_PE_sdata4;
28794 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28796 if (ix86_cmodel == CM_SMALL
28797 || (ix86_cmodel == CM_MEDIUM && code))
28798 return DW_EH_PE_udata4;
28799 return DW_EH_PE_absptr;
28802 /* Expand copysign from SIGN to the positive value ABS_VALUE
28803 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28806 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28808 enum machine_mode mode = GET_MODE (sign);
28809 rtx sgn = gen_reg_rtx (mode);
28810 if (mask == NULL_RTX)
28812 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28813 if (!VECTOR_MODE_P (mode))
28815 /* We need to generate a scalar mode mask in this case. */
28816 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28817 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28818 mask = gen_reg_rtx (mode);
28819 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28823 mask = gen_rtx_NOT (mode, mask);
28824 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28825 gen_rtx_AND (mode, mask, sign)));
28826 emit_insn (gen_rtx_SET (VOIDmode, result,
28827 gen_rtx_IOR (mode, abs_value, sgn)));
28830 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28831 mask for masking out the sign-bit is stored in *SMASK, if that is
28834 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28836 enum machine_mode mode = GET_MODE (op0);
28839 xa = gen_reg_rtx (mode);
28840 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28841 if (!VECTOR_MODE_P (mode))
28843 /* We need to generate a scalar mode mask in this case. */
28844 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28845 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28846 mask = gen_reg_rtx (mode);
28847 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28849 emit_insn (gen_rtx_SET (VOIDmode, xa,
28850 gen_rtx_AND (mode, op0, mask)));
28858 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28859 swapping the operands if SWAP_OPERANDS is true. The expanded
28860 code is a forward jump to a newly created label in case the
28861 comparison is true. The generated label rtx is returned. */
28863 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28864 bool swap_operands)
28875 label = gen_label_rtx ();
28876 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28877 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28878 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28879 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28880 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28881 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28882 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28883 JUMP_LABEL (tmp) = label;
28888 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28889 using comparison code CODE. Operands are swapped for the comparison if
28890 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28892 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28893 bool swap_operands)
28895 enum machine_mode mode = GET_MODE (op0);
28896 rtx mask = gen_reg_rtx (mode);
28905 if (mode == DFmode)
28906 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28907 gen_rtx_fmt_ee (code, mode, op0, op1)));
28909 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28910 gen_rtx_fmt_ee (code, mode, op0, op1)));
28915 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28916 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28918 ix86_gen_TWO52 (enum machine_mode mode)
28920 REAL_VALUE_TYPE TWO52r;
28923 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28924 TWO52 = const_double_from_real_value (TWO52r, mode);
28925 TWO52 = force_reg (mode, TWO52);
28930 /* Expand SSE sequence for computing lround from OP1 storing
28933 ix86_expand_lround (rtx op0, rtx op1)
28935 /* C code for the stuff we're doing below:
28936 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28939 enum machine_mode mode = GET_MODE (op1);
28940 const struct real_format *fmt;
28941 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28944 /* load nextafter (0.5, 0.0) */
28945 fmt = REAL_MODE_FORMAT (mode);
28946 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28947 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28949 /* adj = copysign (0.5, op1) */
28950 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28951 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28953 /* adj = op1 + adj */
28954 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28956 /* op0 = (imode)adj */
28957 expand_fix (op0, adj, 0);
28960 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28963 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28965 /* C code for the stuff we're doing below (for do_floor):
28967 xi -= (double)xi > op1 ? 1 : 0;
28970 enum machine_mode fmode = GET_MODE (op1);
28971 enum machine_mode imode = GET_MODE (op0);
28972 rtx ireg, freg, label, tmp;
28974 /* reg = (long)op1 */
28975 ireg = gen_reg_rtx (imode);
28976 expand_fix (ireg, op1, 0);
28978 /* freg = (double)reg */
28979 freg = gen_reg_rtx (fmode);
28980 expand_float (freg, ireg, 0);
28982 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28983 label = ix86_expand_sse_compare_and_jump (UNLE,
28984 freg, op1, !do_floor);
28985 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28986 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28987 emit_move_insn (ireg, tmp);
28989 emit_label (label);
28990 LABEL_NUSES (label) = 1;
28992 emit_move_insn (op0, ireg);
28995 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28996 result in OPERAND0. */
28998 ix86_expand_rint (rtx operand0, rtx operand1)
29000 /* C code for the stuff we're doing below:
29001 xa = fabs (operand1);
29002 if (!isless (xa, 2**52))
29004 xa = xa + 2**52 - 2**52;
29005 return copysign (xa, operand1);
29007 enum machine_mode mode = GET_MODE (operand0);
29008 rtx res, xa, label, TWO52, mask;
29010 res = gen_reg_rtx (mode);
29011 emit_move_insn (res, operand1);
29013 /* xa = abs (operand1) */
29014 xa = ix86_expand_sse_fabs (res, &mask);
29016 /* if (!isless (xa, TWO52)) goto label; */
29017 TWO52 = ix86_gen_TWO52 (mode);
29018 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29020 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29021 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29023 ix86_sse_copysign_to_positive (res, xa, res, mask);
29025 emit_label (label);
29026 LABEL_NUSES (label) = 1;
29028 emit_move_insn (operand0, res);
29031 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29034 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
29036 /* C code for the stuff we expand below.
29037 double xa = fabs (x), x2;
29038 if (!isless (xa, TWO52))
29040 xa = xa + TWO52 - TWO52;
29041 x2 = copysign (xa, x);
29050 enum machine_mode mode = GET_MODE (operand0);
29051 rtx xa, TWO52, tmp, label, one, res, mask;
29053 TWO52 = ix86_gen_TWO52 (mode);
29055 /* Temporary for holding the result, initialized to the input
29056 operand to ease control flow. */
29057 res = gen_reg_rtx (mode);
29058 emit_move_insn (res, operand1);
29060 /* xa = abs (operand1) */
29061 xa = ix86_expand_sse_fabs (res, &mask);
29063 /* if (!isless (xa, TWO52)) goto label; */
29064 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29066 /* xa = xa + TWO52 - TWO52; */
29067 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29068 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29070 /* xa = copysign (xa, operand1) */
29071 ix86_sse_copysign_to_positive (xa, xa, res, mask);
29073 /* generate 1.0 or -1.0 */
29074 one = force_reg (mode,
29075 const_double_from_real_value (do_floor
29076 ? dconst1 : dconstm1, mode));
29078 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29079 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29080 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29081 gen_rtx_AND (mode, one, tmp)));
29082 /* We always need to subtract here to preserve signed zero. */
29083 tmp = expand_simple_binop (mode, MINUS,
29084 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29085 emit_move_insn (res, tmp);
29087 emit_label (label);
29088 LABEL_NUSES (label) = 1;
29090 emit_move_insn (operand0, res);
29093 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29096 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
29098 /* C code for the stuff we expand below.
29099 double xa = fabs (x), x2;
29100 if (!isless (xa, TWO52))
29102 x2 = (double)(long)x;
29109 if (HONOR_SIGNED_ZEROS (mode))
29110 return copysign (x2, x);
29113 enum machine_mode mode = GET_MODE (operand0);
29114 rtx xa, xi, TWO52, tmp, label, one, res, mask;
29116 TWO52 = ix86_gen_TWO52 (mode);
29118 /* Temporary for holding the result, initialized to the input
29119 operand to ease control flow. */
29120 res = gen_reg_rtx (mode);
29121 emit_move_insn (res, operand1);
29123 /* xa = abs (operand1) */
29124 xa = ix86_expand_sse_fabs (res, &mask);
29126 /* if (!isless (xa, TWO52)) goto label; */
29127 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29129 /* xa = (double)(long)x */
29130 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29131 expand_fix (xi, res, 0);
29132 expand_float (xa, xi, 0);
29135 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29137 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29138 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29139 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29140 gen_rtx_AND (mode, one, tmp)));
29141 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
29142 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29143 emit_move_insn (res, tmp);
29145 if (HONOR_SIGNED_ZEROS (mode))
29146 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29148 emit_label (label);
29149 LABEL_NUSES (label) = 1;
29151 emit_move_insn (operand0, res);
29154 /* Expand SSE sequence for computing round from OPERAND1 storing
29155 into OPERAND0. Sequence that works without relying on DImode truncation
29156 via cvttsd2siq that is only available on 64bit targets. */
29158 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
29160 /* C code for the stuff we expand below.
29161 double xa = fabs (x), xa2, x2;
29162 if (!isless (xa, TWO52))
29164 Using the absolute value and copying back sign makes
29165 -0.0 -> -0.0 correct.
29166 xa2 = xa + TWO52 - TWO52;
29171 else if (dxa > 0.5)
29173 x2 = copysign (xa2, x);
29176 enum machine_mode mode = GET_MODE (operand0);
29177 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
29179 TWO52 = ix86_gen_TWO52 (mode);
29181 /* Temporary for holding the result, initialized to the input
29182 operand to ease control flow. */
29183 res = gen_reg_rtx (mode);
29184 emit_move_insn (res, operand1);
29186 /* xa = abs (operand1) */
29187 xa = ix86_expand_sse_fabs (res, &mask);
29189 /* if (!isless (xa, TWO52)) goto label; */
29190 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29192 /* xa2 = xa + TWO52 - TWO52; */
29193 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29194 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29196 /* dxa = xa2 - xa; */
29197 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29199 /* generate 0.5, 1.0 and -0.5 */
29200 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29201 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29202 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
29206 tmp = gen_reg_rtx (mode);
29207 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29208 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
29209 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29210 gen_rtx_AND (mode, one, tmp)));
29211 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29212 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29213 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
29214 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29215 gen_rtx_AND (mode, one, tmp)));
29216 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29218 /* res = copysign (xa2, operand1) */
29219 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
29221 emit_label (label);
29222 LABEL_NUSES (label) = 1;
29224 emit_move_insn (operand0, res);
29227 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29230 ix86_expand_trunc (rtx operand0, rtx operand1)
29232 /* C code for SSE variant we expand below.
29233 double xa = fabs (x), x2;
29234 if (!isless (xa, TWO52))
29236 x2 = (double)(long)x;
29237 if (HONOR_SIGNED_ZEROS (mode))
29238 return copysign (x2, x);
29241 enum machine_mode mode = GET_MODE (operand0);
29242 rtx xa, xi, TWO52, label, res, mask;
29244 TWO52 = ix86_gen_TWO52 (mode);
29246 /* Temporary for holding the result, initialized to the input
29247 operand to ease control flow. */
29248 res = gen_reg_rtx (mode);
29249 emit_move_insn (res, operand1);
29251 /* xa = abs (operand1) */
29252 xa = ix86_expand_sse_fabs (res, &mask);
29254 /* if (!isless (xa, TWO52)) goto label; */
29255 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29257 /* x = (double)(long)x */
29258 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29259 expand_fix (xi, res, 0);
29260 expand_float (res, xi, 0);
29262 if (HONOR_SIGNED_ZEROS (mode))
29263 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29265 emit_label (label);
29266 LABEL_NUSES (label) = 1;
29268 emit_move_insn (operand0, res);
29271 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29274 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
29276 enum machine_mode mode = GET_MODE (operand0);
29277 rtx xa, mask, TWO52, label, one, res, smask, tmp;
29279 /* C code for SSE variant we expand below.
29280 double xa = fabs (x), x2;
29281 if (!isless (xa, TWO52))
29283 xa2 = xa + TWO52 - TWO52;
29287 x2 = copysign (xa2, x);
29291 TWO52 = ix86_gen_TWO52 (mode);
29293 /* Temporary for holding the result, initialized to the input
29294 operand to ease control flow. */
29295 res = gen_reg_rtx (mode);
29296 emit_move_insn (res, operand1);
29298 /* xa = abs (operand1) */
29299 xa = ix86_expand_sse_fabs (res, &smask);
29301 /* if (!isless (xa, TWO52)) goto label; */
29302 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29304 /* res = xa + TWO52 - TWO52; */
29305 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29306 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
29307 emit_move_insn (res, tmp);
29310 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29312 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29313 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
29314 emit_insn (gen_rtx_SET (VOIDmode, mask,
29315 gen_rtx_AND (mode, mask, one)));
29316 tmp = expand_simple_binop (mode, MINUS,
29317 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
29318 emit_move_insn (res, tmp);
29320 /* res = copysign (res, operand1) */
29321 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
29323 emit_label (label);
29324 LABEL_NUSES (label) = 1;
29326 emit_move_insn (operand0, res);
29329 /* Expand SSE sequence for computing round from OPERAND1 storing
29332 ix86_expand_round (rtx operand0, rtx operand1)
29334 /* C code for the stuff we're doing below:
29335 double xa = fabs (x);
29336 if (!isless (xa, TWO52))
29338 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29339 return copysign (xa, x);
29341 enum machine_mode mode = GET_MODE (operand0);
29342 rtx res, TWO52, xa, label, xi, half, mask;
29343 const struct real_format *fmt;
29344 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29346 /* Temporary for holding the result, initialized to the input
29347 operand to ease control flow. */
29348 res = gen_reg_rtx (mode);
29349 emit_move_insn (res, operand1);
29351 TWO52 = ix86_gen_TWO52 (mode);
29352 xa = ix86_expand_sse_fabs (res, &mask);
29353 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29355 /* load nextafter (0.5, 0.0) */
29356 fmt = REAL_MODE_FORMAT (mode);
29357 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29358 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29360 /* xa = xa + 0.5 */
29361 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29362 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29364 /* xa = (double)(int64_t)xa */
29365 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29366 expand_fix (xi, xa, 0);
29367 expand_float (xa, xi, 0);
29369 /* res = copysign (xa, operand1) */
29370 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29372 emit_label (label);
29373 LABEL_NUSES (label) = 1;
29375 emit_move_insn (operand0, res);
29378 /* Validate whether a FMA4 instruction is valid or not.
29379 OPERANDS is the array of operands.
29380 NUM is the number of operands.
29381 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
29382 NUM_MEMORY is the maximum number of memory operands to accept.
29383 NUM_MEMORY less than zero is a special case to allow an operand
29384 of an instruction to be memory operation.
29385 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
29388 ix86_fma4_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
29389 bool uses_oc0, int num_memory, bool commutative)
29395 /* Count the number of memory arguments */
29398 for (i = 0; i < num; i++)
29400 enum machine_mode mode = GET_MODE (operands[i]);
29401 if (register_operand (operands[i], mode))
29404 else if (memory_operand (operands[i], mode))
29406 mem_mask |= (1 << i);
29412 rtx pattern = PATTERN (insn);
29414 /* allow 0 for pcmov */
29415 if (GET_CODE (pattern) != SET
29416 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
29418 || operands[i] != CONST0_RTX (mode))
29423 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29424 a memory operation. */
29425 if (num_memory < 0)
29427 num_memory = -num_memory;
29428 if ((mem_mask & (1 << (num-1))) != 0)
29430 mem_mask &= ~(1 << (num-1));
29435 /* If there were no memory operations, allow the insn */
29439 /* Do not allow the destination register to be a memory operand. */
29440 else if (mem_mask & (1 << 0))
29443 /* If there are too many memory operations, disallow the instruction. While
29444 the hardware only allows 1 memory reference, before register allocation
29445 for some insns, we allow two memory operations sometimes in order to allow
29446 code like the following to be optimized:
29448 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29450 or similar cases that are vectorized into using the vfmaddss
29452 else if (mem_count > num_memory)
29455 /* Don't allow more than one memory operation if not optimizing. */
29456 else if (mem_count > 1 && !optimize)
29459 else if (num == 4 && mem_count == 1)
29461 /* formats (destination is the first argument), example vfmaddss:
29462 xmm1, xmm1, xmm2, xmm3/mem
29463 xmm1, xmm1, xmm2/mem, xmm3
29464 xmm1, xmm2, xmm3/mem, xmm1
29465 xmm1, xmm2/mem, xmm3, xmm1 */
29467 return ((mem_mask == (1 << 1))
29468 || (mem_mask == (1 << 2))
29469 || (mem_mask == (1 << 3)));
29471 /* format, example vpmacsdd:
29472 xmm1, xmm2, xmm3/mem, xmm1 */
29474 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29476 return (mem_mask == (1 << 2));
29479 else if (num == 4 && num_memory == 2)
29481 /* If there are two memory operations, we can load one of the memory ops
29482 into the destination register. This is for optimizing the
29483 multiply/add ops, which the combiner has optimized both the multiply
29484 and the add insns to have a memory operation. We have to be careful
29485 that the destination doesn't overlap with the inputs. */
29486 rtx op0 = operands[0];
29488 if (reg_mentioned_p (op0, operands[1])
29489 || reg_mentioned_p (op0, operands[2])
29490 || reg_mentioned_p (op0, operands[3]))
29493 /* formats (destination is the first argument), example vfmaddss:
29494 xmm1, xmm1, xmm2, xmm3/mem
29495 xmm1, xmm1, xmm2/mem, xmm3
29496 xmm1, xmm2, xmm3/mem, xmm1
29497 xmm1, xmm2/mem, xmm3, xmm1
29499 For the oc0 case, we will load either operands[1] or operands[3] into
29500 operands[0], so any combination of 2 memory operands is ok. */
29504 /* format, example vpmacsdd:
29505 xmm1, xmm2, xmm3/mem, xmm1
29507 For the integer multiply/add instructions be more restrictive and
29508 require operands[2] and operands[3] to be the memory operands. */
29510 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
29512 return (mem_mask == ((1 << 2) | (1 << 3)));
29515 else if (num == 3 && num_memory == 1)
29517 /* formats, example vprotb:
29518 xmm1, xmm2, xmm3/mem
29519 xmm1, xmm2/mem, xmm3 */
29521 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29523 /* format, example vpcomeq:
29524 xmm1, xmm2, xmm3/mem */
29526 return (mem_mask == (1 << 2));
29530 gcc_unreachable ();
29536 /* Fixup an FMA4 instruction that has 2 memory input references into a form the
29537 hardware will allow by using the destination register to load one of the
29538 memory operations. Presently this is used by the multiply/add routines to
29539 allow 2 memory references. */
29542 ix86_expand_fma4_multiple_memory (rtx operands[],
29544 enum machine_mode mode)
29546 rtx op0 = operands[0];
29548 || memory_operand (op0, mode)
29549 || reg_mentioned_p (op0, operands[1])
29550 || reg_mentioned_p (op0, operands[2])
29551 || reg_mentioned_p (op0, operands[3]))
29552 gcc_unreachable ();
29554 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29555 the destination register. */
29556 if (memory_operand (operands[1], mode))
29558 emit_move_insn (op0, operands[1]);
29561 else if (memory_operand (operands[3], mode))
29563 emit_move_insn (op0, operands[3]);
29567 gcc_unreachable ();
29572 /* Table of valid machine attributes. */
29573 static const struct attribute_spec ix86_attribute_table[] =
29575 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29576 /* Stdcall attribute says callee is responsible for popping arguments
29577 if they are not variable. */
29578 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29579 /* Fastcall attribute says callee is responsible for popping arguments
29580 if they are not variable. */
29581 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29582 /* Cdecl attribute says the callee is a normal C declaration */
29583 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29584 /* Regparm attribute specifies how many integer arguments are to be
29585 passed in registers. */
29586 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29587 /* Sseregparm attribute says we are using x86_64 calling conventions
29588 for FP arguments. */
29589 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29590 /* force_align_arg_pointer says this function realigns the stack at entry. */
29591 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29592 false, true, true, ix86_handle_cconv_attribute },
29593 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29594 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29595 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29596 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29598 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29599 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29600 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29601 SUBTARGET_ATTRIBUTE_TABLE,
29603 /* ms_abi and sysv_abi calling convention function attributes. */
29604 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29605 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29606 { "ms_hook_prologue", 0, 0, true, false, false, ix86_handle_fndecl_attribute },
29608 { NULL, 0, 0, false, false, false, NULL }
29611 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29613 x86_builtin_vectorization_cost (bool runtime_test)
29615 /* If the branch of the runtime test is taken - i.e. - the vectorized
29616 version is skipped - this incurs a misprediction cost (because the
29617 vectorized version is expected to be the fall-through). So we subtract
29618 the latency of a mispredicted branch from the costs that are incured
29619 when the vectorized version is executed.
29621 TODO: The values in individual target tables have to be tuned or new
29622 fields may be needed. For eg. on K8, the default branch path is the
29623 not-taken path. If the taken path is predicted correctly, the minimum
29624 penalty of going down the taken-path is 1 cycle. If the taken-path is
29625 not predicted correctly, then the minimum penalty is 10 cycles. */
29629 return (-(ix86_cost->cond_taken_branch_cost));
29635 /* This function returns the calling abi specific va_list type node.
29636 It returns the FNDECL specific va_list type. */
29639 ix86_fn_abi_va_list (tree fndecl)
29642 return va_list_type_node;
29643 gcc_assert (fndecl != NULL_TREE);
29645 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
29646 return ms_va_list_type_node;
29648 return sysv_va_list_type_node;
29651 /* Returns the canonical va_list type specified by TYPE. If there
29652 is no valid TYPE provided, it return NULL_TREE. */
29655 ix86_canonical_va_list_type (tree type)
29659 /* Resolve references and pointers to va_list type. */
29660 if (INDIRECT_REF_P (type))
29661 type = TREE_TYPE (type);
29662 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29663 type = TREE_TYPE (type);
29667 wtype = va_list_type_node;
29668 gcc_assert (wtype != NULL_TREE);
29670 if (TREE_CODE (wtype) == ARRAY_TYPE)
29672 /* If va_list is an array type, the argument may have decayed
29673 to a pointer type, e.g. by being passed to another function.
29674 In that case, unwrap both types so that we can compare the
29675 underlying records. */
29676 if (TREE_CODE (htype) == ARRAY_TYPE
29677 || POINTER_TYPE_P (htype))
29679 wtype = TREE_TYPE (wtype);
29680 htype = TREE_TYPE (htype);
29683 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29684 return va_list_type_node;
29685 wtype = sysv_va_list_type_node;
29686 gcc_assert (wtype != NULL_TREE);
29688 if (TREE_CODE (wtype) == ARRAY_TYPE)
29690 /* If va_list is an array type, the argument may have decayed
29691 to a pointer type, e.g. by being passed to another function.
29692 In that case, unwrap both types so that we can compare the
29693 underlying records. */
29694 if (TREE_CODE (htype) == ARRAY_TYPE
29695 || POINTER_TYPE_P (htype))
29697 wtype = TREE_TYPE (wtype);
29698 htype = TREE_TYPE (htype);
29701 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29702 return sysv_va_list_type_node;
29703 wtype = ms_va_list_type_node;
29704 gcc_assert (wtype != NULL_TREE);
29706 if (TREE_CODE (wtype) == ARRAY_TYPE)
29708 /* If va_list is an array type, the argument may have decayed
29709 to a pointer type, e.g. by being passed to another function.
29710 In that case, unwrap both types so that we can compare the
29711 underlying records. */
29712 if (TREE_CODE (htype) == ARRAY_TYPE
29713 || POINTER_TYPE_P (htype))
29715 wtype = TREE_TYPE (wtype);
29716 htype = TREE_TYPE (htype);
29719 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29720 return ms_va_list_type_node;
29723 return std_canonical_va_list_type (type);
29726 /* Iterate through the target-specific builtin types for va_list.
29727 IDX denotes the iterator, *PTREE is set to the result type of
29728 the va_list builtin, and *PNAME to its internal type.
29729 Returns zero if there is no element for this index, otherwise
29730 IDX should be increased upon the next call.
29731 Note, do not iterate a base builtin's name like __builtin_va_list.
29732 Used from c_common_nodes_and_builtins. */
29735 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29741 *ptree = ms_va_list_type_node;
29742 *pname = "__builtin_ms_va_list";
29745 *ptree = sysv_va_list_type_node;
29746 *pname = "__builtin_sysv_va_list";
29754 /* Initialize the GCC target structure. */
29755 #undef TARGET_RETURN_IN_MEMORY
29756 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29758 #undef TARGET_LEGITIMIZE_ADDRESS
29759 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
29761 #undef TARGET_ATTRIBUTE_TABLE
29762 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29763 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29764 # undef TARGET_MERGE_DECL_ATTRIBUTES
29765 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29768 #undef TARGET_COMP_TYPE_ATTRIBUTES
29769 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29771 #undef TARGET_INIT_BUILTINS
29772 #define TARGET_INIT_BUILTINS ix86_init_builtins
29773 #undef TARGET_BUILTIN_DECL
29774 #define TARGET_BUILTIN_DECL ix86_builtin_decl
29775 #undef TARGET_EXPAND_BUILTIN
29776 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29778 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29779 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29780 ix86_builtin_vectorized_function
29782 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29783 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29785 #undef TARGET_BUILTIN_RECIPROCAL
29786 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29788 #undef TARGET_ASM_FUNCTION_EPILOGUE
29789 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29791 #undef TARGET_ENCODE_SECTION_INFO
29792 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29793 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29795 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29798 #undef TARGET_ASM_OPEN_PAREN
29799 #define TARGET_ASM_OPEN_PAREN ""
29800 #undef TARGET_ASM_CLOSE_PAREN
29801 #define TARGET_ASM_CLOSE_PAREN ""
29803 #undef TARGET_ASM_BYTE_OP
29804 #define TARGET_ASM_BYTE_OP ASM_BYTE
29806 #undef TARGET_ASM_ALIGNED_HI_OP
29807 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29808 #undef TARGET_ASM_ALIGNED_SI_OP
29809 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29811 #undef TARGET_ASM_ALIGNED_DI_OP
29812 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29815 #undef TARGET_ASM_UNALIGNED_HI_OP
29816 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29817 #undef TARGET_ASM_UNALIGNED_SI_OP
29818 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29819 #undef TARGET_ASM_UNALIGNED_DI_OP
29820 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29822 #undef TARGET_SCHED_ADJUST_COST
29823 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29824 #undef TARGET_SCHED_ISSUE_RATE
29825 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29826 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29827 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29828 ia32_multipass_dfa_lookahead
29830 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29831 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29834 #undef TARGET_HAVE_TLS
29835 #define TARGET_HAVE_TLS true
29837 #undef TARGET_CANNOT_FORCE_CONST_MEM
29838 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29839 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29840 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29842 #undef TARGET_DELEGITIMIZE_ADDRESS
29843 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29845 #undef TARGET_MS_BITFIELD_LAYOUT_P
29846 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29849 #undef TARGET_BINDS_LOCAL_P
29850 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29852 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29853 #undef TARGET_BINDS_LOCAL_P
29854 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29857 #undef TARGET_ASM_OUTPUT_MI_THUNK
29858 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29859 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29860 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29862 #undef TARGET_ASM_FILE_START
29863 #define TARGET_ASM_FILE_START x86_file_start
29865 #undef TARGET_DEFAULT_TARGET_FLAGS
29866 #define TARGET_DEFAULT_TARGET_FLAGS \
29868 | TARGET_SUBTARGET_DEFAULT \
29869 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29871 #undef TARGET_HANDLE_OPTION
29872 #define TARGET_HANDLE_OPTION ix86_handle_option
29874 #undef TARGET_RTX_COSTS
29875 #define TARGET_RTX_COSTS ix86_rtx_costs
29876 #undef TARGET_ADDRESS_COST
29877 #define TARGET_ADDRESS_COST ix86_address_cost
29879 #undef TARGET_FIXED_CONDITION_CODE_REGS
29880 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29881 #undef TARGET_CC_MODES_COMPATIBLE
29882 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29884 #undef TARGET_MACHINE_DEPENDENT_REORG
29885 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29887 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29888 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29890 #undef TARGET_BUILD_BUILTIN_VA_LIST
29891 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29893 #undef TARGET_FN_ABI_VA_LIST
29894 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29896 #undef TARGET_CANONICAL_VA_LIST_TYPE
29897 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29899 #undef TARGET_EXPAND_BUILTIN_VA_START
29900 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29902 #undef TARGET_MD_ASM_CLOBBERS
29903 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29905 #undef TARGET_PROMOTE_PROTOTYPES
29906 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29907 #undef TARGET_STRUCT_VALUE_RTX
29908 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29909 #undef TARGET_SETUP_INCOMING_VARARGS
29910 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29911 #undef TARGET_MUST_PASS_IN_STACK
29912 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29913 #undef TARGET_PASS_BY_REFERENCE
29914 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29915 #undef TARGET_INTERNAL_ARG_POINTER
29916 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29917 #undef TARGET_UPDATE_STACK_BOUNDARY
29918 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29919 #undef TARGET_GET_DRAP_RTX
29920 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29921 #undef TARGET_STRICT_ARGUMENT_NAMING
29922 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29923 #undef TARGET_STATIC_CHAIN
29924 #define TARGET_STATIC_CHAIN ix86_static_chain
29925 #undef TARGET_TRAMPOLINE_INIT
29926 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
29928 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29929 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29931 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29932 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29934 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29935 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29937 #undef TARGET_C_MODE_FOR_SUFFIX
29938 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29941 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29942 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29945 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29946 #undef TARGET_INSERT_ATTRIBUTES
29947 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29950 #undef TARGET_MANGLE_TYPE
29951 #define TARGET_MANGLE_TYPE ix86_mangle_type
29953 #undef TARGET_STACK_PROTECT_FAIL
29954 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29956 #undef TARGET_FUNCTION_VALUE
29957 #define TARGET_FUNCTION_VALUE ix86_function_value
29959 #undef TARGET_SECONDARY_RELOAD
29960 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29962 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29963 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29965 #undef TARGET_SET_CURRENT_FUNCTION
29966 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29968 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29969 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29971 #undef TARGET_OPTION_SAVE
29972 #define TARGET_OPTION_SAVE ix86_function_specific_save
29974 #undef TARGET_OPTION_RESTORE
29975 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29977 #undef TARGET_OPTION_PRINT
29978 #define TARGET_OPTION_PRINT ix86_function_specific_print
29980 #undef TARGET_CAN_INLINE_P
29981 #define TARGET_CAN_INLINE_P ix86_can_inline_p
29983 #undef TARGET_EXPAND_TO_RTL_HOOK
29984 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29986 #undef TARGET_LEGITIMATE_ADDRESS_P
29987 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
29989 #undef TARGET_IRA_COVER_CLASSES
29990 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
29992 #undef TARGET_FRAME_POINTER_REQUIRED
29993 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
29995 #undef TARGET_CAN_ELIMINATE
29996 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
29998 struct gcc_target targetm = TARGET_INITIALIZER;
30000 #include "gt-i386.h"
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