1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
50 #include "tree-gimple.h"
52 #include "tm-constrs.h"
55 #ifndef CHECK_STACK_LIMIT
56 #define CHECK_STACK_LIMIT (-1)
59 /* Return index of given mode in mult and division cost tables. */
60 #define MODE_INDEX(mode) \
61 ((mode) == QImode ? 0 \
62 : (mode) == HImode ? 1 \
63 : (mode) == SImode ? 2 \
64 : (mode) == DImode ? 3 \
67 /* Processor costs (relative to an add) */
68 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
69 #define COSTS_N_BYTES(N) ((N) * 2)
71 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
74 struct processor_costs size_cost = { /* costs for tuning for size */
75 COSTS_N_BYTES (2), /* cost of an add instruction */
76 COSTS_N_BYTES (3), /* cost of a lea instruction */
77 COSTS_N_BYTES (2), /* variable shift costs */
78 COSTS_N_BYTES (3), /* constant shift costs */
79 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
80 COSTS_N_BYTES (3), /* HI */
81 COSTS_N_BYTES (3), /* SI */
82 COSTS_N_BYTES (3), /* DI */
83 COSTS_N_BYTES (5)}, /* other */
84 0, /* cost of multiply per each bit set */
85 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 COSTS_N_BYTES (3), /* cost of movsx */
91 COSTS_N_BYTES (3), /* cost of movzx */
94 2, /* cost for loading QImode using movzbl */
95 {2, 2, 2}, /* cost of loading integer registers
96 in QImode, HImode and SImode.
97 Relative to reg-reg move (2). */
98 {2, 2, 2}, /* cost of storing integer registers */
99 2, /* cost of reg,reg fld/fst */
100 {2, 2, 2}, /* cost of loading fp registers
101 in SFmode, DFmode and XFmode */
102 {2, 2, 2}, /* cost of storing fp registers
103 in SFmode, DFmode and XFmode */
104 3, /* cost of moving MMX register */
105 {3, 3}, /* cost of loading MMX registers
106 in SImode and DImode */
107 {3, 3}, /* cost of storing MMX registers
108 in SImode and DImode */
109 3, /* cost of moving SSE register */
110 {3, 3, 3}, /* cost of loading SSE registers
111 in SImode, DImode and TImode */
112 {3, 3, 3}, /* cost of storing SSE registers
113 in SImode, DImode and TImode */
114 3, /* MMX or SSE register to integer */
115 0, /* size of prefetch block */
116 0, /* number of parallel prefetches */
118 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
119 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
120 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
121 COSTS_N_BYTES (2), /* cost of FABS instruction. */
122 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
123 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
124 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
125 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
126 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
127 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}}
130 /* Processor costs (relative to an add) */
132 struct processor_costs i386_cost = { /* 386 specific costs */
133 COSTS_N_INSNS (1), /* cost of an add instruction */
134 COSTS_N_INSNS (1), /* cost of a lea instruction */
135 COSTS_N_INSNS (3), /* variable shift costs */
136 COSTS_N_INSNS (2), /* constant shift costs */
137 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
138 COSTS_N_INSNS (6), /* HI */
139 COSTS_N_INSNS (6), /* SI */
140 COSTS_N_INSNS (6), /* DI */
141 COSTS_N_INSNS (6)}, /* other */
142 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
143 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
144 COSTS_N_INSNS (23), /* HI */
145 COSTS_N_INSNS (23), /* SI */
146 COSTS_N_INSNS (23), /* DI */
147 COSTS_N_INSNS (23)}, /* other */
148 COSTS_N_INSNS (3), /* cost of movsx */
149 COSTS_N_INSNS (2), /* cost of movzx */
150 15, /* "large" insn */
152 4, /* cost for loading QImode using movzbl */
153 {2, 4, 2}, /* cost of loading integer registers
154 in QImode, HImode and SImode.
155 Relative to reg-reg move (2). */
156 {2, 4, 2}, /* cost of storing integer registers */
157 2, /* cost of reg,reg fld/fst */
158 {8, 8, 8}, /* cost of loading fp registers
159 in SFmode, DFmode and XFmode */
160 {8, 8, 8}, /* cost of storing fp registers
161 in SFmode, DFmode and XFmode */
162 2, /* cost of moving MMX register */
163 {4, 8}, /* cost of loading MMX registers
164 in SImode and DImode */
165 {4, 8}, /* cost of storing MMX registers
166 in SImode and DImode */
167 2, /* cost of moving SSE register */
168 {4, 8, 16}, /* cost of loading SSE registers
169 in SImode, DImode and TImode */
170 {4, 8, 16}, /* cost of storing SSE registers
171 in SImode, DImode and TImode */
172 3, /* MMX or SSE register to integer */
173 0, /* size of prefetch block */
174 0, /* number of parallel prefetches */
176 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
177 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
178 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
179 COSTS_N_INSNS (22), /* cost of FABS instruction. */
180 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
181 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
182 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
183 DUMMY_STRINGOP_ALGS},
184 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
185 DUMMY_STRINGOP_ALGS},
189 struct processor_costs i486_cost = { /* 486 specific costs */
190 COSTS_N_INSNS (1), /* cost of an add instruction */
191 COSTS_N_INSNS (1), /* cost of a lea instruction */
192 COSTS_N_INSNS (3), /* variable shift costs */
193 COSTS_N_INSNS (2), /* constant shift costs */
194 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
195 COSTS_N_INSNS (12), /* HI */
196 COSTS_N_INSNS (12), /* SI */
197 COSTS_N_INSNS (12), /* DI */
198 COSTS_N_INSNS (12)}, /* other */
199 1, /* cost of multiply per each bit set */
200 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
201 COSTS_N_INSNS (40), /* HI */
202 COSTS_N_INSNS (40), /* SI */
203 COSTS_N_INSNS (40), /* DI */
204 COSTS_N_INSNS (40)}, /* other */
205 COSTS_N_INSNS (3), /* cost of movsx */
206 COSTS_N_INSNS (2), /* cost of movzx */
207 15, /* "large" insn */
209 4, /* cost for loading QImode using movzbl */
210 {2, 4, 2}, /* cost of loading integer registers
211 in QImode, HImode and SImode.
212 Relative to reg-reg move (2). */
213 {2, 4, 2}, /* cost of storing integer registers */
214 2, /* cost of reg,reg fld/fst */
215 {8, 8, 8}, /* cost of loading fp registers
216 in SFmode, DFmode and XFmode */
217 {8, 8, 8}, /* cost of storing fp registers
218 in SFmode, DFmode and XFmode */
219 2, /* cost of moving MMX register */
220 {4, 8}, /* cost of loading MMX registers
221 in SImode and DImode */
222 {4, 8}, /* cost of storing MMX registers
223 in SImode and DImode */
224 2, /* cost of moving SSE register */
225 {4, 8, 16}, /* cost of loading SSE registers
226 in SImode, DImode and TImode */
227 {4, 8, 16}, /* cost of storing SSE registers
228 in SImode, DImode and TImode */
229 3, /* MMX or SSE register to integer */
230 0, /* size of prefetch block */
231 0, /* number of parallel prefetches */
233 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
234 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
235 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
236 COSTS_N_INSNS (3), /* cost of FABS instruction. */
237 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
238 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
239 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
240 DUMMY_STRINGOP_ALGS},
241 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
246 struct processor_costs pentium_cost = {
247 COSTS_N_INSNS (1), /* cost of an add instruction */
248 COSTS_N_INSNS (1), /* cost of a lea instruction */
249 COSTS_N_INSNS (4), /* variable shift costs */
250 COSTS_N_INSNS (1), /* constant shift costs */
251 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
252 COSTS_N_INSNS (11), /* HI */
253 COSTS_N_INSNS (11), /* SI */
254 COSTS_N_INSNS (11), /* DI */
255 COSTS_N_INSNS (11)}, /* other */
256 0, /* cost of multiply per each bit set */
257 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
258 COSTS_N_INSNS (25), /* HI */
259 COSTS_N_INSNS (25), /* SI */
260 COSTS_N_INSNS (25), /* DI */
261 COSTS_N_INSNS (25)}, /* other */
262 COSTS_N_INSNS (3), /* cost of movsx */
263 COSTS_N_INSNS (2), /* cost of movzx */
264 8, /* "large" insn */
266 6, /* cost for loading QImode using movzbl */
267 {2, 4, 2}, /* cost of loading integer registers
268 in QImode, HImode and SImode.
269 Relative to reg-reg move (2). */
270 {2, 4, 2}, /* cost of storing integer registers */
271 2, /* cost of reg,reg fld/fst */
272 {2, 2, 6}, /* cost of loading fp registers
273 in SFmode, DFmode and XFmode */
274 {4, 4, 6}, /* cost of storing fp registers
275 in SFmode, DFmode and XFmode */
276 8, /* cost of moving MMX register */
277 {8, 8}, /* cost of loading MMX registers
278 in SImode and DImode */
279 {8, 8}, /* cost of storing MMX registers
280 in SImode and DImode */
281 2, /* cost of moving SSE register */
282 {4, 8, 16}, /* cost of loading SSE registers
283 in SImode, DImode and TImode */
284 {4, 8, 16}, /* cost of storing SSE registers
285 in SImode, DImode and TImode */
286 3, /* MMX or SSE register to integer */
287 0, /* size of prefetch block */
288 0, /* number of parallel prefetches */
290 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
291 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
292 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
293 COSTS_N_INSNS (1), /* cost of FABS instruction. */
294 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
295 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
296 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
297 DUMMY_STRINGOP_ALGS},
298 {{libcall, {{-1, rep_prefix_4_byte}}},
303 struct processor_costs pentiumpro_cost = {
304 COSTS_N_INSNS (1), /* cost of an add instruction */
305 COSTS_N_INSNS (1), /* cost of a lea instruction */
306 COSTS_N_INSNS (1), /* variable shift costs */
307 COSTS_N_INSNS (1), /* constant shift costs */
308 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
309 COSTS_N_INSNS (4), /* HI */
310 COSTS_N_INSNS (4), /* SI */
311 COSTS_N_INSNS (4), /* DI */
312 COSTS_N_INSNS (4)}, /* other */
313 0, /* cost of multiply per each bit set */
314 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
315 COSTS_N_INSNS (17), /* HI */
316 COSTS_N_INSNS (17), /* SI */
317 COSTS_N_INSNS (17), /* DI */
318 COSTS_N_INSNS (17)}, /* other */
319 COSTS_N_INSNS (1), /* cost of movsx */
320 COSTS_N_INSNS (1), /* cost of movzx */
321 8, /* "large" insn */
323 2, /* cost for loading QImode using movzbl */
324 {4, 4, 4}, /* cost of loading integer registers
325 in QImode, HImode and SImode.
326 Relative to reg-reg move (2). */
327 {2, 2, 2}, /* cost of storing integer registers */
328 2, /* cost of reg,reg fld/fst */
329 {2, 2, 6}, /* cost of loading fp registers
330 in SFmode, DFmode and XFmode */
331 {4, 4, 6}, /* cost of storing fp registers
332 in SFmode, DFmode and XFmode */
333 2, /* cost of moving MMX register */
334 {2, 2}, /* cost of loading MMX registers
335 in SImode and DImode */
336 {2, 2}, /* cost of storing MMX registers
337 in SImode and DImode */
338 2, /* cost of moving SSE register */
339 {2, 2, 8}, /* cost of loading SSE registers
340 in SImode, DImode and TImode */
341 {2, 2, 8}, /* cost of storing SSE registers
342 in SImode, DImode and TImode */
343 3, /* MMX or SSE register to integer */
344 32, /* size of prefetch block */
345 6, /* number of parallel prefetches */
347 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
348 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
349 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
350 COSTS_N_INSNS (2), /* cost of FABS instruction. */
351 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
352 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
353 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
354 the alignment). For small blocks inline loop is still a noticeable win, for bigger
355 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
356 more expensive startup time in CPU, but after 4K the difference is down in the noise.
358 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
359 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
360 DUMMY_STRINGOP_ALGS},
361 {{rep_prefix_4_byte, {{1024, unrolled_loop},
362 {8192, rep_prefix_4_byte}, {-1, libcall}}},
367 struct processor_costs geode_cost = {
368 COSTS_N_INSNS (1), /* cost of an add instruction */
369 COSTS_N_INSNS (1), /* cost of a lea instruction */
370 COSTS_N_INSNS (2), /* variable shift costs */
371 COSTS_N_INSNS (1), /* constant shift costs */
372 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
373 COSTS_N_INSNS (4), /* HI */
374 COSTS_N_INSNS (7), /* SI */
375 COSTS_N_INSNS (7), /* DI */
376 COSTS_N_INSNS (7)}, /* other */
377 0, /* cost of multiply per each bit set */
378 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
379 COSTS_N_INSNS (23), /* HI */
380 COSTS_N_INSNS (39), /* SI */
381 COSTS_N_INSNS (39), /* DI */
382 COSTS_N_INSNS (39)}, /* other */
383 COSTS_N_INSNS (1), /* cost of movsx */
384 COSTS_N_INSNS (1), /* cost of movzx */
385 8, /* "large" insn */
387 1, /* cost for loading QImode using movzbl */
388 {1, 1, 1}, /* cost of loading integer registers
389 in QImode, HImode and SImode.
390 Relative to reg-reg move (2). */
391 {1, 1, 1}, /* cost of storing integer registers */
392 1, /* cost of reg,reg fld/fst */
393 {1, 1, 1}, /* cost of loading fp registers
394 in SFmode, DFmode and XFmode */
395 {4, 6, 6}, /* cost of storing fp registers
396 in SFmode, DFmode and XFmode */
398 1, /* cost of moving MMX register */
399 {1, 1}, /* cost of loading MMX registers
400 in SImode and DImode */
401 {1, 1}, /* cost of storing MMX registers
402 in SImode and DImode */
403 1, /* cost of moving SSE register */
404 {1, 1, 1}, /* cost of loading SSE registers
405 in SImode, DImode and TImode */
406 {1, 1, 1}, /* cost of storing SSE registers
407 in SImode, DImode and TImode */
408 1, /* MMX or SSE register to integer */
409 32, /* size of prefetch block */
410 1, /* number of parallel prefetches */
412 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
413 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
414 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
415 COSTS_N_INSNS (1), /* cost of FABS instruction. */
416 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
417 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
418 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
419 DUMMY_STRINGOP_ALGS},
420 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
425 struct processor_costs k6_cost = {
426 COSTS_N_INSNS (1), /* cost of an add instruction */
427 COSTS_N_INSNS (2), /* cost of a lea instruction */
428 COSTS_N_INSNS (1), /* variable shift costs */
429 COSTS_N_INSNS (1), /* constant shift costs */
430 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
431 COSTS_N_INSNS (3), /* HI */
432 COSTS_N_INSNS (3), /* SI */
433 COSTS_N_INSNS (3), /* DI */
434 COSTS_N_INSNS (3)}, /* other */
435 0, /* cost of multiply per each bit set */
436 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
437 COSTS_N_INSNS (18), /* HI */
438 COSTS_N_INSNS (18), /* SI */
439 COSTS_N_INSNS (18), /* DI */
440 COSTS_N_INSNS (18)}, /* other */
441 COSTS_N_INSNS (2), /* cost of movsx */
442 COSTS_N_INSNS (2), /* cost of movzx */
443 8, /* "large" insn */
445 3, /* cost for loading QImode using movzbl */
446 {4, 5, 4}, /* cost of loading integer registers
447 in QImode, HImode and SImode.
448 Relative to reg-reg move (2). */
449 {2, 3, 2}, /* cost of storing integer registers */
450 4, /* cost of reg,reg fld/fst */
451 {6, 6, 6}, /* cost of loading fp registers
452 in SFmode, DFmode and XFmode */
453 {4, 4, 4}, /* cost of storing fp registers
454 in SFmode, DFmode and XFmode */
455 2, /* cost of moving MMX register */
456 {2, 2}, /* cost of loading MMX registers
457 in SImode and DImode */
458 {2, 2}, /* cost of storing MMX registers
459 in SImode and DImode */
460 2, /* cost of moving SSE register */
461 {2, 2, 8}, /* cost of loading SSE registers
462 in SImode, DImode and TImode */
463 {2, 2, 8}, /* cost of storing SSE registers
464 in SImode, DImode and TImode */
465 6, /* MMX or SSE register to integer */
466 32, /* size of prefetch block */
467 1, /* number of parallel prefetches */
469 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
470 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
471 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
472 COSTS_N_INSNS (2), /* cost of FABS instruction. */
473 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
474 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
475 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
476 DUMMY_STRINGOP_ALGS},
477 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
482 struct processor_costs athlon_cost = {
483 COSTS_N_INSNS (1), /* cost of an add instruction */
484 COSTS_N_INSNS (2), /* cost of a lea instruction */
485 COSTS_N_INSNS (1), /* variable shift costs */
486 COSTS_N_INSNS (1), /* constant shift costs */
487 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
488 COSTS_N_INSNS (5), /* HI */
489 COSTS_N_INSNS (5), /* SI */
490 COSTS_N_INSNS (5), /* DI */
491 COSTS_N_INSNS (5)}, /* other */
492 0, /* cost of multiply per each bit set */
493 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
494 COSTS_N_INSNS (26), /* HI */
495 COSTS_N_INSNS (42), /* SI */
496 COSTS_N_INSNS (74), /* DI */
497 COSTS_N_INSNS (74)}, /* other */
498 COSTS_N_INSNS (1), /* cost of movsx */
499 COSTS_N_INSNS (1), /* cost of movzx */
500 8, /* "large" insn */
502 4, /* cost for loading QImode using movzbl */
503 {3, 4, 3}, /* cost of loading integer registers
504 in QImode, HImode and SImode.
505 Relative to reg-reg move (2). */
506 {3, 4, 3}, /* cost of storing integer registers */
507 4, /* cost of reg,reg fld/fst */
508 {4, 4, 12}, /* cost of loading fp registers
509 in SFmode, DFmode and XFmode */
510 {6, 6, 8}, /* cost of storing fp registers
511 in SFmode, DFmode and XFmode */
512 2, /* cost of moving MMX register */
513 {4, 4}, /* cost of loading MMX registers
514 in SImode and DImode */
515 {4, 4}, /* cost of storing MMX registers
516 in SImode and DImode */
517 2, /* cost of moving SSE register */
518 {4, 4, 6}, /* cost of loading SSE registers
519 in SImode, DImode and TImode */
520 {4, 4, 5}, /* cost of storing SSE registers
521 in SImode, DImode and TImode */
522 5, /* MMX or SSE register to integer */
523 64, /* size of prefetch block */
524 6, /* number of parallel prefetches */
526 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
527 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
528 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
529 COSTS_N_INSNS (2), /* cost of FABS instruction. */
530 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
531 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
532 /* For some reason, Athlon deals better with REP prefix (relative to loops)
533 compared to K8. Alignment becomes important after 8 bytes for memcpy and
534 128 bytes for memset. */
535 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
536 DUMMY_STRINGOP_ALGS},
537 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
542 struct processor_costs k8_cost = {
543 COSTS_N_INSNS (1), /* cost of an add instruction */
544 COSTS_N_INSNS (2), /* cost of a lea instruction */
545 COSTS_N_INSNS (1), /* variable shift costs */
546 COSTS_N_INSNS (1), /* constant shift costs */
547 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
548 COSTS_N_INSNS (4), /* HI */
549 COSTS_N_INSNS (3), /* SI */
550 COSTS_N_INSNS (4), /* DI */
551 COSTS_N_INSNS (5)}, /* other */
552 0, /* cost of multiply per each bit set */
553 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
554 COSTS_N_INSNS (26), /* HI */
555 COSTS_N_INSNS (42), /* SI */
556 COSTS_N_INSNS (74), /* DI */
557 COSTS_N_INSNS (74)}, /* other */
558 COSTS_N_INSNS (1), /* cost of movsx */
559 COSTS_N_INSNS (1), /* cost of movzx */
560 8, /* "large" insn */
562 4, /* cost for loading QImode using movzbl */
563 {3, 4, 3}, /* cost of loading integer registers
564 in QImode, HImode and SImode.
565 Relative to reg-reg move (2). */
566 {3, 4, 3}, /* cost of storing integer registers */
567 4, /* cost of reg,reg fld/fst */
568 {4, 4, 12}, /* cost of loading fp registers
569 in SFmode, DFmode and XFmode */
570 {6, 6, 8}, /* cost of storing fp registers
571 in SFmode, DFmode and XFmode */
572 2, /* cost of moving MMX register */
573 {3, 3}, /* cost of loading MMX registers
574 in SImode and DImode */
575 {4, 4}, /* cost of storing MMX registers
576 in SImode and DImode */
577 2, /* cost of moving SSE register */
578 {4, 3, 6}, /* cost of loading SSE registers
579 in SImode, DImode and TImode */
580 {4, 4, 5}, /* cost of storing SSE registers
581 in SImode, DImode and TImode */
582 5, /* MMX or SSE register to integer */
583 64, /* size of prefetch block */
584 /* New AMD processors never drop prefetches; if they cannot be performed
585 immediately, they are queued. We set number of simultaneous prefetches
586 to a large constant to reflect this (it probably is not a good idea not
587 to limit number of prefetches at all, as their execution also takes some
589 100, /* number of parallel prefetches */
591 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
592 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
593 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
594 COSTS_N_INSNS (2), /* cost of FABS instruction. */
595 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
596 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
597 /* K8 has optimized REP instruction for medium sized blocks, but for very small
598 blocks it is better to use loop. For large blocks, libcall can do
599 nontemporary accesses and beat inline considerably. */
600 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
601 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
602 {{libcall, {{8, loop}, {24, unrolled_loop},
603 {2048, rep_prefix_4_byte}, {-1, libcall}}},
604 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}
607 struct processor_costs amdfam10_cost = {
608 COSTS_N_INSNS (1), /* cost of an add instruction */
609 COSTS_N_INSNS (2), /* cost of a lea instruction */
610 COSTS_N_INSNS (1), /* variable shift costs */
611 COSTS_N_INSNS (1), /* constant shift costs */
612 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
613 COSTS_N_INSNS (4), /* HI */
614 COSTS_N_INSNS (3), /* SI */
615 COSTS_N_INSNS (4), /* DI */
616 COSTS_N_INSNS (5)}, /* other */
617 0, /* cost of multiply per each bit set */
618 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
619 COSTS_N_INSNS (35), /* HI */
620 COSTS_N_INSNS (51), /* SI */
621 COSTS_N_INSNS (83), /* DI */
622 COSTS_N_INSNS (83)}, /* other */
623 COSTS_N_INSNS (1), /* cost of movsx */
624 COSTS_N_INSNS (1), /* cost of movzx */
625 8, /* "large" insn */
627 4, /* cost for loading QImode using movzbl */
628 {3, 4, 3}, /* cost of loading integer registers
629 in QImode, HImode and SImode.
630 Relative to reg-reg move (2). */
631 {3, 4, 3}, /* cost of storing integer registers */
632 4, /* cost of reg,reg fld/fst */
633 {4, 4, 12}, /* cost of loading fp registers
634 in SFmode, DFmode and XFmode */
635 {6, 6, 8}, /* cost of storing fp registers
636 in SFmode, DFmode and XFmode */
637 2, /* cost of moving MMX register */
638 {3, 3}, /* cost of loading MMX registers
639 in SImode and DImode */
640 {4, 4}, /* cost of storing MMX registers
641 in SImode and DImode */
642 2, /* cost of moving SSE register */
643 {4, 4, 3}, /* cost of loading SSE registers
644 in SImode, DImode and TImode */
645 {4, 4, 5}, /* cost of storing SSE registers
646 in SImode, DImode and TImode */
647 3, /* MMX or SSE register to integer */
649 MOVD reg64, xmmreg Double FSTORE 4
650 MOVD reg32, xmmreg Double FSTORE 4
652 MOVD reg64, xmmreg Double FADD 3
654 MOVD reg32, xmmreg Double FADD 3
656 64, /* size of prefetch block */
657 /* New AMD processors never drop prefetches; if they cannot be performed
658 immediately, they are queued. We set number of simultaneous prefetches
659 to a large constant to reflect this (it probably is not a good idea not
660 to limit number of prefetches at all, as their execution also takes some
662 100, /* number of parallel prefetches */
664 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
665 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
666 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
667 COSTS_N_INSNS (2), /* cost of FABS instruction. */
668 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
669 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
671 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
672 very small blocks it is better to use loop. For large blocks, libcall can
673 do nontemporary accesses and beat inline considerably. */
674 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
675 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
676 {{libcall, {{8, loop}, {24, unrolled_loop},
677 {2048, rep_prefix_4_byte}, {-1, libcall}}},
678 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}
682 struct processor_costs pentium4_cost = {
683 COSTS_N_INSNS (1), /* cost of an add instruction */
684 COSTS_N_INSNS (3), /* cost of a lea instruction */
685 COSTS_N_INSNS (4), /* variable shift costs */
686 COSTS_N_INSNS (4), /* constant shift costs */
687 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
688 COSTS_N_INSNS (15), /* HI */
689 COSTS_N_INSNS (15), /* SI */
690 COSTS_N_INSNS (15), /* DI */
691 COSTS_N_INSNS (15)}, /* other */
692 0, /* cost of multiply per each bit set */
693 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
694 COSTS_N_INSNS (56), /* HI */
695 COSTS_N_INSNS (56), /* SI */
696 COSTS_N_INSNS (56), /* DI */
697 COSTS_N_INSNS (56)}, /* other */
698 COSTS_N_INSNS (1), /* cost of movsx */
699 COSTS_N_INSNS (1), /* cost of movzx */
700 16, /* "large" insn */
702 2, /* cost for loading QImode using movzbl */
703 {4, 5, 4}, /* cost of loading integer registers
704 in QImode, HImode and SImode.
705 Relative to reg-reg move (2). */
706 {2, 3, 2}, /* cost of storing integer registers */
707 2, /* cost of reg,reg fld/fst */
708 {2, 2, 6}, /* cost of loading fp registers
709 in SFmode, DFmode and XFmode */
710 {4, 4, 6}, /* cost of storing fp registers
711 in SFmode, DFmode and XFmode */
712 2, /* cost of moving MMX register */
713 {2, 2}, /* cost of loading MMX registers
714 in SImode and DImode */
715 {2, 2}, /* cost of storing MMX registers
716 in SImode and DImode */
717 12, /* cost of moving SSE register */
718 {12, 12, 12}, /* cost of loading SSE registers
719 in SImode, DImode and TImode */
720 {2, 2, 8}, /* cost of storing SSE registers
721 in SImode, DImode and TImode */
722 10, /* MMX or SSE register to integer */
723 64, /* size of prefetch block */
724 6, /* number of parallel prefetches */
726 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
727 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
728 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
729 COSTS_N_INSNS (2), /* cost of FABS instruction. */
730 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
731 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
732 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
733 DUMMY_STRINGOP_ALGS},
734 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
736 DUMMY_STRINGOP_ALGS},
740 struct processor_costs nocona_cost = {
741 COSTS_N_INSNS (1), /* cost of an add instruction */
742 COSTS_N_INSNS (1), /* cost of a lea instruction */
743 COSTS_N_INSNS (1), /* variable shift costs */
744 COSTS_N_INSNS (1), /* constant shift costs */
745 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
746 COSTS_N_INSNS (10), /* HI */
747 COSTS_N_INSNS (10), /* SI */
748 COSTS_N_INSNS (10), /* DI */
749 COSTS_N_INSNS (10)}, /* other */
750 0, /* cost of multiply per each bit set */
751 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
752 COSTS_N_INSNS (66), /* HI */
753 COSTS_N_INSNS (66), /* SI */
754 COSTS_N_INSNS (66), /* DI */
755 COSTS_N_INSNS (66)}, /* other */
756 COSTS_N_INSNS (1), /* cost of movsx */
757 COSTS_N_INSNS (1), /* cost of movzx */
758 16, /* "large" insn */
760 4, /* cost for loading QImode using movzbl */
761 {4, 4, 4}, /* cost of loading integer registers
762 in QImode, HImode and SImode.
763 Relative to reg-reg move (2). */
764 {4, 4, 4}, /* cost of storing integer registers */
765 3, /* cost of reg,reg fld/fst */
766 {12, 12, 12}, /* cost of loading fp registers
767 in SFmode, DFmode and XFmode */
768 {4, 4, 4}, /* cost of storing fp registers
769 in SFmode, DFmode and XFmode */
770 6, /* cost of moving MMX register */
771 {12, 12}, /* cost of loading MMX registers
772 in SImode and DImode */
773 {12, 12}, /* cost of storing MMX registers
774 in SImode and DImode */
775 6, /* cost of moving SSE register */
776 {12, 12, 12}, /* cost of loading SSE registers
777 in SImode, DImode and TImode */
778 {12, 12, 12}, /* cost of storing SSE registers
779 in SImode, DImode and TImode */
780 8, /* MMX or SSE register to integer */
781 128, /* size of prefetch block */
782 8, /* number of parallel prefetches */
784 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
785 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
786 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
787 COSTS_N_INSNS (3), /* cost of FABS instruction. */
788 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
789 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
790 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
791 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
792 {100000, unrolled_loop}, {-1, libcall}}}},
793 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
795 {libcall, {{24, loop}, {64, unrolled_loop},
796 {8192, rep_prefix_8_byte}, {-1, libcall}}}}
800 struct processor_costs core2_cost = {
801 COSTS_N_INSNS (1), /* cost of an add instruction */
802 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
803 COSTS_N_INSNS (1), /* variable shift costs */
804 COSTS_N_INSNS (1), /* constant shift costs */
805 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
806 COSTS_N_INSNS (3), /* HI */
807 COSTS_N_INSNS (3), /* SI */
808 COSTS_N_INSNS (3), /* DI */
809 COSTS_N_INSNS (3)}, /* other */
810 0, /* cost of multiply per each bit set */
811 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
812 COSTS_N_INSNS (22), /* HI */
813 COSTS_N_INSNS (22), /* SI */
814 COSTS_N_INSNS (22), /* DI */
815 COSTS_N_INSNS (22)}, /* other */
816 COSTS_N_INSNS (1), /* cost of movsx */
817 COSTS_N_INSNS (1), /* cost of movzx */
818 8, /* "large" insn */
820 2, /* cost for loading QImode using movzbl */
821 {6, 6, 6}, /* cost of loading integer registers
822 in QImode, HImode and SImode.
823 Relative to reg-reg move (2). */
824 {4, 4, 4}, /* cost of storing integer registers */
825 2, /* cost of reg,reg fld/fst */
826 {6, 6, 6}, /* cost of loading fp registers
827 in SFmode, DFmode and XFmode */
828 {4, 4, 4}, /* cost of loading integer registers */
829 2, /* cost of moving MMX register */
830 {6, 6}, /* cost of loading MMX registers
831 in SImode and DImode */
832 {4, 4}, /* cost of storing MMX registers
833 in SImode and DImode */
834 2, /* cost of moving SSE register */
835 {6, 6, 6}, /* cost of loading SSE registers
836 in SImode, DImode and TImode */
837 {4, 4, 4}, /* cost of storing SSE registers
838 in SImode, DImode and TImode */
839 2, /* MMX or SSE register to integer */
840 128, /* size of prefetch block */
841 8, /* number of parallel prefetches */
843 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
844 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
845 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
846 COSTS_N_INSNS (1), /* cost of FABS instruction. */
847 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
848 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
849 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
850 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
851 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
852 {{libcall, {{8, loop}, {15, unrolled_loop},
853 {2048, rep_prefix_4_byte}, {-1, libcall}}},
854 {libcall, {{24, loop}, {32, unrolled_loop},
855 {8192, rep_prefix_8_byte}, {-1, libcall}}}}
858 /* Generic64 should produce code tuned for Nocona and K8. */
860 struct processor_costs generic64_cost = {
861 COSTS_N_INSNS (1), /* cost of an add instruction */
862 /* On all chips taken into consideration lea is 2 cycles and more. With
863 this cost however our current implementation of synth_mult results in
864 use of unnecessary temporary registers causing regression on several
865 SPECfp benchmarks. */
866 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
867 COSTS_N_INSNS (1), /* variable shift costs */
868 COSTS_N_INSNS (1), /* constant shift costs */
869 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
870 COSTS_N_INSNS (4), /* HI */
871 COSTS_N_INSNS (3), /* SI */
872 COSTS_N_INSNS (4), /* DI */
873 COSTS_N_INSNS (2)}, /* other */
874 0, /* cost of multiply per each bit set */
875 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
876 COSTS_N_INSNS (26), /* HI */
877 COSTS_N_INSNS (42), /* SI */
878 COSTS_N_INSNS (74), /* DI */
879 COSTS_N_INSNS (74)}, /* other */
880 COSTS_N_INSNS (1), /* cost of movsx */
881 COSTS_N_INSNS (1), /* cost of movzx */
882 8, /* "large" insn */
884 4, /* cost for loading QImode using movzbl */
885 {4, 4, 4}, /* cost of loading integer registers
886 in QImode, HImode and SImode.
887 Relative to reg-reg move (2). */
888 {4, 4, 4}, /* cost of storing integer registers */
889 4, /* cost of reg,reg fld/fst */
890 {12, 12, 12}, /* cost of loading fp registers
891 in SFmode, DFmode and XFmode */
892 {6, 6, 8}, /* cost of storing fp registers
893 in SFmode, DFmode and XFmode */
894 2, /* cost of moving MMX register */
895 {8, 8}, /* cost of loading MMX registers
896 in SImode and DImode */
897 {8, 8}, /* cost of storing MMX registers
898 in SImode and DImode */
899 2, /* cost of moving SSE register */
900 {8, 8, 8}, /* cost of loading SSE registers
901 in SImode, DImode and TImode */
902 {8, 8, 8}, /* cost of storing SSE registers
903 in SImode, DImode and TImode */
904 5, /* MMX or SSE register to integer */
905 64, /* size of prefetch block */
906 6, /* number of parallel prefetches */
907 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
908 is increased to perhaps more appropriate value of 5. */
910 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
911 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
912 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
913 COSTS_N_INSNS (8), /* cost of FABS instruction. */
914 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
915 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
916 {DUMMY_STRINGOP_ALGS,
917 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
918 {DUMMY_STRINGOP_ALGS,
919 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}
922 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
924 struct processor_costs generic32_cost = {
925 COSTS_N_INSNS (1), /* cost of an add instruction */
926 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
927 COSTS_N_INSNS (1), /* variable shift costs */
928 COSTS_N_INSNS (1), /* constant shift costs */
929 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
930 COSTS_N_INSNS (4), /* HI */
931 COSTS_N_INSNS (3), /* SI */
932 COSTS_N_INSNS (4), /* DI */
933 COSTS_N_INSNS (2)}, /* other */
934 0, /* cost of multiply per each bit set */
935 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
936 COSTS_N_INSNS (26), /* HI */
937 COSTS_N_INSNS (42), /* SI */
938 COSTS_N_INSNS (74), /* DI */
939 COSTS_N_INSNS (74)}, /* other */
940 COSTS_N_INSNS (1), /* cost of movsx */
941 COSTS_N_INSNS (1), /* cost of movzx */
942 8, /* "large" insn */
944 4, /* cost for loading QImode using movzbl */
945 {4, 4, 4}, /* cost of loading integer registers
946 in QImode, HImode and SImode.
947 Relative to reg-reg move (2). */
948 {4, 4, 4}, /* cost of storing integer registers */
949 4, /* cost of reg,reg fld/fst */
950 {12, 12, 12}, /* cost of loading fp registers
951 in SFmode, DFmode and XFmode */
952 {6, 6, 8}, /* cost of storing fp registers
953 in SFmode, DFmode and XFmode */
954 2, /* cost of moving MMX register */
955 {8, 8}, /* cost of loading MMX registers
956 in SImode and DImode */
957 {8, 8}, /* cost of storing MMX registers
958 in SImode and DImode */
959 2, /* cost of moving SSE register */
960 {8, 8, 8}, /* cost of loading SSE registers
961 in SImode, DImode and TImode */
962 {8, 8, 8}, /* cost of storing SSE registers
963 in SImode, DImode and TImode */
964 5, /* MMX or SSE register to integer */
965 64, /* size of prefetch block */
966 6, /* number of parallel prefetches */
968 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
969 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
970 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
971 COSTS_N_INSNS (8), /* cost of FABS instruction. */
972 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
973 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
974 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
975 DUMMY_STRINGOP_ALGS},
976 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
977 DUMMY_STRINGOP_ALGS},
980 const struct processor_costs *ix86_cost = &pentium_cost;
982 /* Processor feature/optimization bitmasks. */
983 #define m_386 (1<<PROCESSOR_I386)
984 #define m_486 (1<<PROCESSOR_I486)
985 #define m_PENT (1<<PROCESSOR_PENTIUM)
986 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
987 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
988 #define m_NOCONA (1<<PROCESSOR_NOCONA)
989 #define m_CORE2 (1<<PROCESSOR_CORE2)
991 #define m_GEODE (1<<PROCESSOR_GEODE)
992 #define m_K6 (1<<PROCESSOR_K6)
993 #define m_K6_GEODE (m_K6 | m_GEODE)
994 #define m_K8 (1<<PROCESSOR_K8)
995 #define m_ATHLON (1<<PROCESSOR_ATHLON)
996 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
997 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
998 #define m_ATHLON_K8_AMDFAM10 (m_K8 | m_ATHLON | m_AMDFAM10)
1000 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1001 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1003 /* Generic instruction choice should be common subset of supported CPUs
1004 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1005 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1007 /* Feature tests against the various tunings. */
1008 unsigned int ix86_tune_features[X86_TUNE_LAST] = {
1009 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1010 negatively, so enabling for Generic64 seems like good code size
1011 tradeoff. We can't enable it for 32bit generic because it does not
1012 work well with PPro base chips. */
1013 m_386 | m_K6_GEODE | m_ATHLON_K8_AMDFAM10 | m_CORE2 | m_GENERIC64,
1015 /* X86_TUNE_PUSH_MEMORY */
1016 m_386 | m_K6_GEODE | m_ATHLON_K8_AMDFAM10 | m_PENT4
1017 | m_NOCONA | m_CORE2 | m_GENERIC,
1019 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1022 /* X86_TUNE_USE_BIT_TEST */
1025 /* X86_TUNE_UNROLL_STRLEN */
1026 m_486 | m_PENT | m_PPRO | m_ATHLON_K8_AMDFAM10 | m_K6 | m_CORE2 | m_GENERIC,
1028 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1029 m_PPRO | m_K6_GEODE | m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_GENERIC,
1031 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1032 on simulation result. But after P4 was made, no performance benefit
1033 was observed with branch hints. It also increases the code size.
1034 As a result, icc never generates branch hints. */
1037 /* X86_TUNE_DOUBLE_WITH_ADD */
1040 /* X86_TUNE_USE_SAHF */
1041 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1042 | m_NOCONA | m_CORE2 | m_GENERIC,
1044 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1045 partial dependencies. */
1046 m_ATHLON_K8_AMDFAM10 | m_PPRO | m_PENT4 | m_NOCONA
1047 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1049 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1050 register stalls on Generic32 compilation setting as well. However
1051 in current implementation the partial register stalls are not eliminated
1052 very well - they can be introduced via subregs synthesized by combine
1053 and can happen in caller/callee saving sequences. Because this option
1054 pays back little on PPro based chips and is in conflict with partial reg
1055 dependencies used by Athlon/P4 based chips, it is better to leave it off
1056 for generic32 for now. */
1059 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1060 m_CORE2 | m_GENERIC,
1062 /* X86_TUNE_USE_HIMODE_FIOP */
1063 m_386 | m_486 | m_K6_GEODE,
1065 /* X86_TUNE_USE_SIMODE_FIOP */
1066 ~(m_PPRO | m_ATHLON_K8_AMDFAM10 | m_PENT | m_CORE2 | m_GENERIC),
1068 /* X86_TUNE_USE_MOV0 */
1071 /* X86_TUNE_USE_CLTD */
1072 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1074 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1077 /* X86_TUNE_SPLIT_LONG_MOVES */
1080 /* X86_TUNE_READ_MODIFY_WRITE */
1083 /* X86_TUNE_READ_MODIFY */
1086 /* X86_TUNE_PROMOTE_QIMODE */
1087 m_K6_GEODE | m_PENT | m_386 | m_486 | m_ATHLON_K8_AMDFAM10 | m_CORE2
1088 | m_GENERIC /* | m_PENT4 ? */,
1090 /* X86_TUNE_FAST_PREFIX */
1091 ~(m_PENT | m_486 | m_386),
1093 /* X86_TUNE_SINGLE_STRINGOP */
1094 m_386 | m_PENT4 | m_NOCONA,
1096 /* X86_TUNE_QIMODE_MATH */
1099 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1100 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1101 might be considered for Generic32 if our scheme for avoiding partial
1102 stalls was more effective. */
1105 /* X86_TUNE_PROMOTE_QI_REGS */
1108 /* X86_TUNE_PROMOTE_HI_REGS */
1111 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1112 m_ATHLON_K8_AMDFAM10 | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1114 /* X86_TUNE_ADD_ESP_8 */
1115 m_ATHLON_K8_AMDFAM10 | m_PPRO | m_K6_GEODE | m_386
1116 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1118 /* X86_TUNE_SUB_ESP_4 */
1119 m_ATHLON_K8_AMDFAM10 | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1121 /* X86_TUNE_SUB_ESP_8 */
1122 m_ATHLON_K8_AMDFAM10 | m_PPRO | m_386 | m_486
1123 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1125 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1126 for DFmode copies */
1127 ~(m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1128 | m_GENERIC | m_GEODE),
1130 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1131 m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1133 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1134 conflict here in between PPro/Pentium4 based chips that thread 128bit
1135 SSE registers as single units versus K8 based chips that divide SSE
1136 registers to two 64bit halves. This knob promotes all store destinations
1137 to be 128bit to allow register renaming on 128bit SSE units, but usually
1138 results in one extra microop on 64bit SSE units. Experimental results
1139 shows that disabling this option on P4 brings over 20% SPECfp regression,
1140 while enabling it on K8 brings roughly 2.4% regression that can be partly
1141 masked by careful scheduling of moves. */
1142 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1144 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1147 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1148 are resolved on SSE register parts instead of whole registers, so we may
1149 maintain just lower part of scalar values in proper format leaving the
1150 upper part undefined. */
1153 /* X86_TUNE_SSE_TYPELESS_STORES */
1154 m_ATHLON_K8_AMDFAM10,
1156 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1157 m_PPRO | m_PENT4 | m_NOCONA,
1159 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1160 m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1162 /* X86_TUNE_PROLOGUE_USING_MOVE */
1163 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1165 /* X86_TUNE_EPILOGUE_USING_MOVE */
1166 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1168 /* X86_TUNE_SHIFT1 */
1171 /* X86_TUNE_USE_FFREEP */
1172 m_ATHLON_K8_AMDFAM10,
1174 /* X86_TUNE_INTER_UNIT_MOVES */
1175 ~(m_ATHLON_K8_AMDFAM10 | m_GENERIC),
1177 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1178 than 4 branch instructions in the 16 byte window. */
1179 m_PPRO | m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1181 /* X86_TUNE_SCHEDULE */
1182 m_PPRO | m_ATHLON_K8_AMDFAM10 | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1184 /* X86_TUNE_USE_BT */
1185 m_ATHLON_K8_AMDFAM10,
1187 /* X86_TUNE_USE_INCDEC */
1188 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1190 /* X86_TUNE_PAD_RETURNS */
1191 m_ATHLON_K8_AMDFAM10 | m_CORE2 | m_GENERIC,
1193 /* X86_TUNE_EXT_80387_CONSTANTS */
1194 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1196 /* X86_TUNE_SHORTEN_X87_SSE */
1199 /* X86_TUNE_AVOID_VECTOR_DECODE */
1202 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1203 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1206 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1207 vector path on AMD machines. */
1208 m_K8 | m_GENERIC64 | m_AMDFAM10,
1210 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1212 m_K8 | m_GENERIC64 | m_AMDFAM10,
1214 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1218 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1219 but one byte longer. */
1222 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1223 operand that cannot be represented using a modRM byte. The XOR
1224 replacement is long decoded, so this split helps here as well. */
1228 /* Feature tests against the various architecture variations. */
1229 unsigned int ix86_arch_features[X86_ARCH_LAST] = {
1230 /* X86_ARCH_CMOVE */
1231 m_PPRO | m_GEODE | m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA,
1233 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1236 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1239 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1242 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1246 static const unsigned int x86_accumulate_outgoing_args
1247 = m_ATHLON_K8_AMDFAM10 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1249 static const unsigned int x86_arch_always_fancy_math_387
1250 = m_PENT | m_PPRO | m_ATHLON_K8_AMDFAM10 | m_PENT4
1251 | m_NOCONA | m_CORE2 | m_GENERIC;
1253 static enum stringop_alg stringop_alg = no_stringop;
1255 /* In case the average insn count for single function invocation is
1256 lower than this constant, emit fast (but longer) prologue and
1258 #define FAST_PROLOGUE_INSN_COUNT 20
1260 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1261 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1262 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1263 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1265 /* Array of the smallest class containing reg number REGNO, indexed by
1266 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1268 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1270 /* ax, dx, cx, bx */
1271 AREG, DREG, CREG, BREG,
1272 /* si, di, bp, sp */
1273 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1275 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1276 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1279 /* flags, fpsr, fpcr, frame */
1280 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1281 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1283 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1285 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1286 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1287 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1291 /* The "default" register map used in 32bit mode. */
1293 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1295 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1296 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1297 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1298 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1299 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1300 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1301 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1304 static int const x86_64_int_parameter_registers[6] =
1306 5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
1307 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1310 static int const x86_64_ms_abi_int_parameter_registers[4] =
1312 2 /*RCX*/, 1 /*RDX*/,
1313 FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
1316 static int const x86_64_int_return_registers[4] =
1318 0 /*RAX*/, 1 /*RDX*/, 5 /*RDI*/, 4 /*RSI*/
1321 /* The "default" register map used in 64bit mode. */
1322 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1324 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1325 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1326 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1327 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1328 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1329 8,9,10,11,12,13,14,15, /* extended integer registers */
1330 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1333 /* Define the register numbers to be used in Dwarf debugging information.
1334 The SVR4 reference port C compiler uses the following register numbers
1335 in its Dwarf output code:
1336 0 for %eax (gcc regno = 0)
1337 1 for %ecx (gcc regno = 2)
1338 2 for %edx (gcc regno = 1)
1339 3 for %ebx (gcc regno = 3)
1340 4 for %esp (gcc regno = 7)
1341 5 for %ebp (gcc regno = 6)
1342 6 for %esi (gcc regno = 4)
1343 7 for %edi (gcc regno = 5)
1344 The following three DWARF register numbers are never generated by
1345 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1346 believes these numbers have these meanings.
1347 8 for %eip (no gcc equivalent)
1348 9 for %eflags (gcc regno = 17)
1349 10 for %trapno (no gcc equivalent)
1350 It is not at all clear how we should number the FP stack registers
1351 for the x86 architecture. If the version of SDB on x86/svr4 were
1352 a bit less brain dead with respect to floating-point then we would
1353 have a precedent to follow with respect to DWARF register numbers
1354 for x86 FP registers, but the SDB on x86/svr4 is so completely
1355 broken with respect to FP registers that it is hardly worth thinking
1356 of it as something to strive for compatibility with.
1357 The version of x86/svr4 SDB I have at the moment does (partially)
1358 seem to believe that DWARF register number 11 is associated with
1359 the x86 register %st(0), but that's about all. Higher DWARF
1360 register numbers don't seem to be associated with anything in
1361 particular, and even for DWARF regno 11, SDB only seems to under-
1362 stand that it should say that a variable lives in %st(0) (when
1363 asked via an `=' command) if we said it was in DWARF regno 11,
1364 but SDB still prints garbage when asked for the value of the
1365 variable in question (via a `/' command).
1366 (Also note that the labels SDB prints for various FP stack regs
1367 when doing an `x' command are all wrong.)
1368 Note that these problems generally don't affect the native SVR4
1369 C compiler because it doesn't allow the use of -O with -g and
1370 because when it is *not* optimizing, it allocates a memory
1371 location for each floating-point variable, and the memory
1372 location is what gets described in the DWARF AT_location
1373 attribute for the variable in question.
1374 Regardless of the severe mental illness of the x86/svr4 SDB, we
1375 do something sensible here and we use the following DWARF
1376 register numbers. Note that these are all stack-top-relative
1378 11 for %st(0) (gcc regno = 8)
1379 12 for %st(1) (gcc regno = 9)
1380 13 for %st(2) (gcc regno = 10)
1381 14 for %st(3) (gcc regno = 11)
1382 15 for %st(4) (gcc regno = 12)
1383 16 for %st(5) (gcc regno = 13)
1384 17 for %st(6) (gcc regno = 14)
1385 18 for %st(7) (gcc regno = 15)
1387 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1389 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1390 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1391 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1392 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1393 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1394 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1395 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1398 /* Test and compare insns in i386.md store the information needed to
1399 generate branch and scc insns here. */
1401 rtx ix86_compare_op0 = NULL_RTX;
1402 rtx ix86_compare_op1 = NULL_RTX;
1403 rtx ix86_compare_emitted = NULL_RTX;
1405 /* Size of the register save area. */
1406 #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)
1408 /* Define the structure for the machine field in struct function. */
1410 struct stack_local_entry GTY(())
1412 unsigned short mode;
1415 struct stack_local_entry *next;
1418 /* Structure describing stack frame layout.
1419 Stack grows downward:
1425 saved frame pointer if frame_pointer_needed
1426 <- HARD_FRAME_POINTER
1431 [va_arg registers] (
1432 > to_allocate <- FRAME_POINTER
1442 HOST_WIDE_INT frame;
1444 int outgoing_arguments_size;
1447 HOST_WIDE_INT to_allocate;
1448 /* The offsets relative to ARG_POINTER. */
1449 HOST_WIDE_INT frame_pointer_offset;
1450 HOST_WIDE_INT hard_frame_pointer_offset;
1451 HOST_WIDE_INT stack_pointer_offset;
1453 /* When save_regs_using_mov is set, emit prologue using
1454 move instead of push instructions. */
1455 bool save_regs_using_mov;
1458 /* Code model option. */
1459 enum cmodel ix86_cmodel;
1461 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1463 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1465 /* Which unit we are generating floating point math for. */
1466 enum fpmath_unit ix86_fpmath;
1468 /* Which cpu are we scheduling for. */
1469 enum processor_type ix86_tune;
1471 /* Which instruction set architecture to use. */
1472 enum processor_type ix86_arch;
1474 /* true if sse prefetch instruction is not NOOP. */
1475 int x86_prefetch_sse;
1477 /* ix86_regparm_string as a number */
1478 static int ix86_regparm;
1480 /* -mstackrealign option */
1481 extern int ix86_force_align_arg_pointer;
1482 static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer";
1484 /* Preferred alignment for stack boundary in bits. */
1485 unsigned int ix86_preferred_stack_boundary;
1487 /* Values 1-5: see jump.c */
1488 int ix86_branch_cost;
1490 /* Variables which are this size or smaller are put in the data/bss
1491 or ldata/lbss sections. */
1493 int ix86_section_threshold = 65536;
1495 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1496 char internal_label_prefix[16];
1497 int internal_label_prefix_len;
1499 /* Register class used for passing given 64bit part of the argument.
1500 These represent classes as documented by the PS ABI, with the exception
1501 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1502 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1504 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1505 whenever possible (upper half does contain padding). */
1506 enum x86_64_reg_class
1509 X86_64_INTEGER_CLASS,
1510 X86_64_INTEGERSI_CLASS,
1517 X86_64_COMPLEX_X87_CLASS,
1520 static const char * const x86_64_reg_class_name[] =
1522 "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
1523 "sseup", "x87", "x87up", "cplx87", "no"
1526 #define MAX_CLASSES 4
1528 /* Table of constants used by fldpi, fldln2, etc.... */
1529 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1530 static bool ext_80387_constants_init = 0;
1533 static struct machine_function * ix86_init_machine_status (void);
1534 static rtx ix86_function_value (tree, tree, bool);
1535 static int ix86_function_regparm (tree, tree);
1536 static void ix86_compute_frame_layout (struct ix86_frame *);
1537 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1541 /* The svr4 ABI for the i386 says that records and unions are returned
1543 #ifndef DEFAULT_PCC_STRUCT_RETURN
1544 #define DEFAULT_PCC_STRUCT_RETURN 1
1547 /* Implement TARGET_HANDLE_OPTION. */
1550 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1557 target_flags &= ~MASK_3DNOW_A;
1558 target_flags_explicit |= MASK_3DNOW_A;
1565 target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
1566 target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
1573 target_flags &= ~(MASK_SSE2 | MASK_SSE3 | MASK_SSSE3
1574 | MASK_SSE4_1 | MASK_SSE4A);
1575 target_flags_explicit |= (MASK_SSE2 | MASK_SSE3 | MASK_SSSE3
1576 | MASK_SSE4_1 | MASK_SSE4A);
1583 target_flags &= ~(MASK_SSE3 | MASK_SSSE3 | MASK_SSE4_1
1585 target_flags_explicit |= (MASK_SSE3 | MASK_SSSE3
1586 | MASK_SSE4_1 | MASK_SSE4A);
1593 target_flags &= ~(MASK_SSSE3 | MASK_SSE4_1 | MASK_SSE4A);
1594 target_flags_explicit |= (MASK_SSSE3 | MASK_SSE4_1
1602 target_flags &= ~(MASK_SSE4_1 | MASK_SSE4A);
1603 target_flags_explicit |= MASK_SSE4_1 | MASK_SSE4A;
1610 target_flags &= ~MASK_SSE4A;
1611 target_flags_explicit |= MASK_SSE4A;
1618 target_flags &= ~MASK_SSE4_1;
1619 target_flags_explicit |= MASK_SSE4_1;
1628 /* Sometimes certain combinations of command options do not make
1629 sense on a particular target machine. You can define a macro
1630 `OVERRIDE_OPTIONS' to take account of this. This macro, if
1631 defined, is executed once just after all the command options have
1634 Don't use this macro to turn on various extra optimizations for
1635 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
1638 override_options (void)
1641 int ix86_tune_defaulted = 0;
1642 unsigned int ix86_arch_mask, ix86_tune_mask;
1644 /* Comes from final.c -- no real reason to change it. */
1645 #define MAX_CODE_ALIGN 16
1649 const struct processor_costs *cost; /* Processor costs */
1650 const int target_enable; /* Target flags to enable. */
1651 const int target_disable; /* Target flags to disable. */
1652 const int align_loop; /* Default alignments. */
1653 const int align_loop_max_skip;
1654 const int align_jump;
1655 const int align_jump_max_skip;
1656 const int align_func;
1658 const processor_target_table[PROCESSOR_max] =
1660 {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
1661 {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
1662 {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
1663 {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
1664 {&geode_cost, 0, 0, 0, 0, 0, 0, 0},
1665 {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
1666 {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
1667 {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
1668 {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
1669 {&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
1670 {&core2_cost, 0, 0, 16, 7, 16, 7, 16},
1671 {&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
1672 {&generic64_cost, 0, 0, 16, 7, 16, 7, 16},
1673 {&amdfam10_cost, 0, 0, 32, 24, 32, 7, 32}
1676 static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
1679 const char *const name; /* processor name or nickname. */
1680 const enum processor_type processor;
1681 const enum pta_flags
1687 PTA_PREFETCH_SSE = 1 << 4,
1689 PTA_3DNOW_A = 1 << 6,
1693 PTA_POPCNT = 1 << 10,
1695 PTA_SSE4A = 1 << 12,
1696 PTA_NO_SAHF = 1 << 13,
1697 PTA_SSE4_1 = 1 << 14
1700 const processor_alias_table[] =
1702 {"i386", PROCESSOR_I386, 0},
1703 {"i486", PROCESSOR_I486, 0},
1704 {"i586", PROCESSOR_PENTIUM, 0},
1705 {"pentium", PROCESSOR_PENTIUM, 0},
1706 {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
1707 {"winchip-c6", PROCESSOR_I486, PTA_MMX},
1708 {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1709 {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
1710 {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_PREFETCH_SSE | PTA_SSE},
1711 {"i686", PROCESSOR_PENTIUMPRO, 0},
1712 {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
1713 {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
1714 {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1715 {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
1716 {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
1717 {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1718 | PTA_MMX | PTA_PREFETCH_SSE},
1719 {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
1720 | PTA_MMX | PTA_PREFETCH_SSE},
1721 {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
1722 | PTA_MMX | PTA_PREFETCH_SSE},
1723 {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
1724 | PTA_MMX | PTA_PREFETCH_SSE
1725 | PTA_CX16 | PTA_NO_SAHF},
1726 {"core2", PROCESSOR_CORE2, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3
1727 | PTA_64BIT | PTA_MMX
1728 | PTA_PREFETCH_SSE | PTA_CX16},
1729 {"geode", PROCESSOR_GEODE, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1731 {"k6", PROCESSOR_K6, PTA_MMX},
1732 {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1733 {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
1734 {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1736 {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
1737 | PTA_3DNOW | PTA_3DNOW_A},
1738 {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1739 | PTA_3DNOW_A | PTA_SSE},
1740 {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1741 | PTA_3DNOW_A | PTA_SSE},
1742 {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1743 | PTA_3DNOW_A | PTA_SSE},
1744 {"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
1745 | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
1746 {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1747 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1749 {"k8-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
1750 | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1751 | PTA_SSE3 | PTA_NO_SAHF},
1752 {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1753 | PTA_64BIT | PTA_3DNOW_A | PTA_SSE
1754 | PTA_SSE2 | PTA_NO_SAHF},
1755 {"opteron-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1756 | PTA_64BIT | PTA_3DNOW_A | PTA_SSE
1757 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
1758 {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1759 | PTA_64BIT | PTA_3DNOW_A | PTA_SSE
1760 | PTA_SSE2 | PTA_NO_SAHF},
1761 {"athlon64-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1762 | PTA_64BIT | PTA_3DNOW_A | PTA_SSE
1763 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
1764 {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1765 | PTA_64BIT | PTA_3DNOW_A | PTA_SSE
1766 | PTA_SSE2 | PTA_NO_SAHF},
1767 {"amdfam10", PROCESSOR_AMDFAM10, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1768 | PTA_64BIT | PTA_3DNOW_A | PTA_SSE
1769 | PTA_SSE2 | PTA_SSE3 | PTA_POPCNT
1770 | PTA_ABM | PTA_SSE4A | PTA_CX16},
1771 {"barcelona", PROCESSOR_AMDFAM10, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
1772 | PTA_64BIT | PTA_3DNOW_A | PTA_SSE
1773 | PTA_SSE2 | PTA_SSE3 | PTA_POPCNT
1774 | PTA_ABM | PTA_SSE4A | PTA_CX16},
1775 {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },
1776 {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ },
1779 int const pta_size = ARRAY_SIZE (processor_alias_table);
1781 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1782 SUBTARGET_OVERRIDE_OPTIONS;
1785 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1786 SUBSUBTARGET_OVERRIDE_OPTIONS;
1789 /* -fPIC is the default for x86_64. */
1790 if (TARGET_MACHO && TARGET_64BIT)
1793 /* Set the default values for switches whose default depends on TARGET_64BIT
1794 in case they weren't overwritten by command line options. */
1797 /* Mach-O doesn't support omitting the frame pointer for now. */
1798 if (flag_omit_frame_pointer == 2)
1799 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
1800 if (flag_asynchronous_unwind_tables == 2)
1801 flag_asynchronous_unwind_tables = 1;
1802 if (flag_pcc_struct_return == 2)
1803 flag_pcc_struct_return = 0;
1807 if (flag_omit_frame_pointer == 2)
1808 flag_omit_frame_pointer = 0;
1809 if (flag_asynchronous_unwind_tables == 2)
1810 flag_asynchronous_unwind_tables = 0;
1811 if (flag_pcc_struct_return == 2)
1812 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
1815 /* Need to check -mtune=generic first. */
1816 if (ix86_tune_string)
1818 if (!strcmp (ix86_tune_string, "generic")
1819 || !strcmp (ix86_tune_string, "i686")
1820 /* As special support for cross compilers we read -mtune=native
1821 as -mtune=generic. With native compilers we won't see the
1822 -mtune=native, as it was changed by the driver. */
1823 || !strcmp (ix86_tune_string, "native"))
1826 ix86_tune_string = "generic64";
1828 ix86_tune_string = "generic32";
1830 else if (!strncmp (ix86_tune_string, "generic", 7))
1831 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
1835 if (ix86_arch_string)
1836 ix86_tune_string = ix86_arch_string;
1837 if (!ix86_tune_string)
1839 ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT];
1840 ix86_tune_defaulted = 1;
1843 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
1844 need to use a sensible tune option. */
1845 if (!strcmp (ix86_tune_string, "generic")
1846 || !strcmp (ix86_tune_string, "x86-64")
1847 || !strcmp (ix86_tune_string, "i686"))
1850 ix86_tune_string = "generic64";
1852 ix86_tune_string = "generic32";
1855 if (ix86_stringop_string)
1857 if (!strcmp (ix86_stringop_string, "rep_byte"))
1858 stringop_alg = rep_prefix_1_byte;
1859 else if (!strcmp (ix86_stringop_string, "libcall"))
1860 stringop_alg = libcall;
1861 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
1862 stringop_alg = rep_prefix_4_byte;
1863 else if (!strcmp (ix86_stringop_string, "rep_8byte"))
1864 stringop_alg = rep_prefix_8_byte;
1865 else if (!strcmp (ix86_stringop_string, "byte_loop"))
1866 stringop_alg = loop_1_byte;
1867 else if (!strcmp (ix86_stringop_string, "loop"))
1868 stringop_alg = loop;
1869 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
1870 stringop_alg = unrolled_loop;
1872 error ("bad value (%s) for -mstringop-strategy= switch", ix86_stringop_string);
1874 if (!strcmp (ix86_tune_string, "x86-64"))
1875 warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or "
1876 "-mtune=generic instead as appropriate.");
1878 if (!ix86_arch_string)
1879 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
1880 if (!strcmp (ix86_arch_string, "generic"))
1881 error ("generic CPU can be used only for -mtune= switch");
1882 if (!strncmp (ix86_arch_string, "generic", 7))
1883 error ("bad value (%s) for -march= switch", ix86_arch_string);
1885 if (ix86_cmodel_string != 0)
1887 if (!strcmp (ix86_cmodel_string, "small"))
1888 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1889 else if (!strcmp (ix86_cmodel_string, "medium"))
1890 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
1891 else if (!strcmp (ix86_cmodel_string, "large"))
1892 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
1894 error ("code model %s does not support PIC mode", ix86_cmodel_string);
1895 else if (!strcmp (ix86_cmodel_string, "32"))
1896 ix86_cmodel = CM_32;
1897 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
1898 ix86_cmodel = CM_KERNEL;
1900 error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
1904 /* For TARGET_64BIT_MS_ABI, force pic on, in order to enable the
1905 use of rip-relative addressing. This eliminates fixups that
1906 would otherwise be needed if this object is to be placed in a
1907 DLL, and is essentially just as efficient as direct addressing. */
1908 if (TARGET_64BIT_MS_ABI)
1909 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
1910 else if (TARGET_64BIT)
1911 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
1913 ix86_cmodel = CM_32;
1915 if (ix86_asm_string != 0)
1918 && !strcmp (ix86_asm_string, "intel"))
1919 ix86_asm_dialect = ASM_INTEL;
1920 else if (!strcmp (ix86_asm_string, "att"))
1921 ix86_asm_dialect = ASM_ATT;
1923 error ("bad value (%s) for -masm= switch", ix86_asm_string);
1925 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
1926 error ("code model %qs not supported in the %s bit mode",
1927 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
1928 if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0))
1929 sorry ("%i-bit mode not compiled in",
1930 (target_flags & MASK_64BIT) ? 64 : 32);
1932 for (i = 0; i < pta_size; i++)
1933 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
1935 ix86_arch = processor_alias_table[i].processor;
1936 /* Default cpu tuning to the architecture. */
1937 ix86_tune = ix86_arch;
1938 if (processor_alias_table[i].flags & PTA_MMX
1939 && !(target_flags_explicit & MASK_MMX))
1940 target_flags |= MASK_MMX;
1941 if (processor_alias_table[i].flags & PTA_3DNOW
1942 && !(target_flags_explicit & MASK_3DNOW))
1943 target_flags |= MASK_3DNOW;
1944 if (processor_alias_table[i].flags & PTA_3DNOW_A
1945 && !(target_flags_explicit & MASK_3DNOW_A))
1946 target_flags |= MASK_3DNOW_A;
1947 if (processor_alias_table[i].flags & PTA_SSE
1948 && !(target_flags_explicit & MASK_SSE))
1949 target_flags |= MASK_SSE;
1950 if (processor_alias_table[i].flags & PTA_SSE2
1951 && !(target_flags_explicit & MASK_SSE2))
1952 target_flags |= MASK_SSE2;
1953 if (processor_alias_table[i].flags & PTA_SSE3
1954 && !(target_flags_explicit & MASK_SSE3))
1955 target_flags |= MASK_SSE3;
1956 if (processor_alias_table[i].flags & PTA_SSSE3
1957 && !(target_flags_explicit & MASK_SSSE3))
1958 target_flags |= MASK_SSSE3;
1959 if (processor_alias_table[i].flags & PTA_SSE4_1
1960 && !(target_flags_explicit & MASK_SSE4_1))
1961 target_flags |= MASK_SSE4_1;
1962 if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
1963 x86_prefetch_sse = true;
1964 if (processor_alias_table[i].flags & PTA_CX16)
1965 x86_cmpxchg16b = true;
1966 if (processor_alias_table[i].flags & PTA_POPCNT
1967 && !(target_flags_explicit & MASK_POPCNT))
1968 target_flags |= MASK_POPCNT;
1969 if (processor_alias_table[i].flags & PTA_ABM
1970 && !(target_flags_explicit & MASK_ABM))
1971 target_flags |= MASK_ABM;
1972 if (processor_alias_table[i].flags & PTA_SSE4A
1973 && !(target_flags_explicit & MASK_SSE4A))
1974 target_flags |= MASK_SSE4A;
1975 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF)))
1977 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1978 error ("CPU you selected does not support x86-64 "
1984 error ("bad value (%s) for -march= switch", ix86_arch_string);
1986 ix86_arch_mask = 1u << ix86_arch;
1987 for (i = 0; i < X86_ARCH_LAST; ++i)
1988 ix86_arch_features[i] &= ix86_arch_mask;
1990 for (i = 0; i < pta_size; i++)
1991 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
1993 ix86_tune = processor_alias_table[i].processor;
1994 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
1996 if (ix86_tune_defaulted)
1998 ix86_tune_string = "x86-64";
1999 for (i = 0; i < pta_size; i++)
2000 if (! strcmp (ix86_tune_string,
2001 processor_alias_table[i].name))
2003 ix86_tune = processor_alias_table[i].processor;
2006 error ("CPU you selected does not support x86-64 "
2009 /* Intel CPUs have always interpreted SSE prefetch instructions as
2010 NOPs; so, we can enable SSE prefetch instructions even when
2011 -mtune (rather than -march) points us to a processor that has them.
2012 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2013 higher processors. */
2014 if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE))
2015 x86_prefetch_sse = true;
2019 error ("bad value (%s) for -mtune= switch", ix86_tune_string);
2021 ix86_tune_mask = 1u << ix86_tune;
2022 for (i = 0; i < X86_TUNE_LAST; ++i)
2023 ix86_tune_features[i] &= ix86_tune_mask;
2026 ix86_cost = &size_cost;
2028 ix86_cost = processor_target_table[ix86_tune].cost;
2029 target_flags |= processor_target_table[ix86_tune].target_enable;
2030 target_flags &= ~processor_target_table[ix86_tune].target_disable;
2032 /* Arrange to set up i386_stack_locals for all functions. */
2033 init_machine_status = ix86_init_machine_status;
2035 /* Validate -mregparm= value. */
2036 if (ix86_regparm_string)
2039 warning (0, "-mregparm is ignored in 64-bit mode");
2040 i = atoi (ix86_regparm_string);
2041 if (i < 0 || i > REGPARM_MAX)
2042 error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
2047 ix86_regparm = REGPARM_MAX;
2049 /* If the user has provided any of the -malign-* options,
2050 warn and use that value only if -falign-* is not set.
2051 Remove this code in GCC 3.2 or later. */
2052 if (ix86_align_loops_string)
2054 warning (0, "-malign-loops is obsolete, use -falign-loops");
2055 if (align_loops == 0)
2057 i = atoi (ix86_align_loops_string);
2058 if (i < 0 || i > MAX_CODE_ALIGN)
2059 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2061 align_loops = 1 << i;
2065 if (ix86_align_jumps_string)
2067 warning (0, "-malign-jumps is obsolete, use -falign-jumps");
2068 if (align_jumps == 0)
2070 i = atoi (ix86_align_jumps_string);
2071 if (i < 0 || i > MAX_CODE_ALIGN)
2072 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2074 align_jumps = 1 << i;
2078 if (ix86_align_funcs_string)
2080 warning (0, "-malign-functions is obsolete, use -falign-functions");
2081 if (align_functions == 0)
2083 i = atoi (ix86_align_funcs_string);
2084 if (i < 0 || i > MAX_CODE_ALIGN)
2085 error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
2087 align_functions = 1 << i;
2091 /* Default align_* from the processor table. */
2092 if (align_loops == 0)
2094 align_loops = processor_target_table[ix86_tune].align_loop;
2095 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2097 if (align_jumps == 0)
2099 align_jumps = processor_target_table[ix86_tune].align_jump;
2100 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2102 if (align_functions == 0)
2104 align_functions = processor_target_table[ix86_tune].align_func;
2107 /* Validate -mbranch-cost= value, or provide default. */
2108 ix86_branch_cost = ix86_cost->branch_cost;
2109 if (ix86_branch_cost_string)
2111 i = atoi (ix86_branch_cost_string);
2113 error ("-mbranch-cost=%d is not between 0 and 5", i);
2115 ix86_branch_cost = i;
2117 if (ix86_section_threshold_string)
2119 i = atoi (ix86_section_threshold_string);
2121 error ("-mlarge-data-threshold=%d is negative", i);
2123 ix86_section_threshold = i;
2126 if (ix86_tls_dialect_string)
2128 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2129 ix86_tls_dialect = TLS_DIALECT_GNU;
2130 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
2131 ix86_tls_dialect = TLS_DIALECT_GNU2;
2132 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
2133 ix86_tls_dialect = TLS_DIALECT_SUN;
2135 error ("bad value (%s) for -mtls-dialect= switch",
2136 ix86_tls_dialect_string);
2139 if (ix87_precision_string)
2141 i = atoi (ix87_precision_string);
2142 if (i != 32 && i != 64 && i != 80)
2143 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
2146 /* Keep nonleaf frame pointers. */
2147 if (flag_omit_frame_pointer)
2148 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
2149 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
2150 flag_omit_frame_pointer = 1;
2152 /* If we're doing fast math, we don't care about comparison order
2153 wrt NaNs. This lets us use a shorter comparison sequence. */
2154 if (flag_finite_math_only)
2155 target_flags &= ~MASK_IEEE_FP;
2157 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
2158 since the insns won't need emulation. */
2159 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
2160 target_flags &= ~MASK_NO_FANCY_MATH_387;
2162 /* Likewise, if the target doesn't have a 387, or we've specified
2163 software floating point, don't use 387 inline intrinsics. */
2165 target_flags |= MASK_NO_FANCY_MATH_387;
2167 /* Turn on SSSE3 builtins for -msse4.1. */
2169 target_flags |= MASK_SSSE3;
2171 /* Turn on SSE3 builtins for -mssse3. */
2173 target_flags |= MASK_SSE3;
2175 /* Turn on SSE3 builtins for -msse4a. */
2177 target_flags |= MASK_SSE3;
2179 /* Turn on SSE2 builtins for -msse3. */
2181 target_flags |= MASK_SSE2;
2183 /* Turn on SSE builtins for -msse2. */
2185 target_flags |= MASK_SSE;
2187 /* Turn on MMX builtins for -msse. */
2190 target_flags |= MASK_MMX & ~target_flags_explicit;
2191 x86_prefetch_sse = true;
2194 /* Turn on MMX builtins for 3Dnow. */
2196 target_flags |= MASK_MMX;
2198 /* Turn on POPCNT builtins for -mabm. */
2200 target_flags |= MASK_POPCNT;
2205 warning (0, "-mrtd is ignored in 64bit mode");
2207 /* Enable by default the SSE and MMX builtins. Do allow the user to
2208 explicitly disable any of these. In particular, disabling SSE and
2209 MMX for kernel code is extremely useful. */
2211 |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | TARGET_SUBTARGET64_DEFAULT)
2212 & ~target_flags_explicit);
2216 /* i386 ABI does not specify red zone. It still makes sense to use it
2217 when programmer takes care to stack from being destroyed. */
2218 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
2219 target_flags |= MASK_NO_RED_ZONE;
2222 /* Validate -mpreferred-stack-boundary= value, or provide default.
2223 The default of 128 bits is for Pentium III's SSE __m128. We can't
2224 change it because of optimize_size. Otherwise, we can't mix object
2225 files compiled with -Os and -On. */
2226 ix86_preferred_stack_boundary = 128;
2227 if (ix86_preferred_stack_boundary_string)
2229 i = atoi (ix86_preferred_stack_boundary_string);
2230 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
2231 error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
2232 TARGET_64BIT ? 4 : 2);
2234 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
2237 /* Accept -msseregparm only if at least SSE support is enabled. */
2238 if (TARGET_SSEREGPARM
2240 error ("-msseregparm used without SSE enabled");
2242 ix86_fpmath = TARGET_FPMATH_DEFAULT;
2243 if (ix86_fpmath_string != 0)
2245 if (! strcmp (ix86_fpmath_string, "387"))
2246 ix86_fpmath = FPMATH_387;
2247 else if (! strcmp (ix86_fpmath_string, "sse"))
2251 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2252 ix86_fpmath = FPMATH_387;
2255 ix86_fpmath = FPMATH_SSE;
2257 else if (! strcmp (ix86_fpmath_string, "387,sse")
2258 || ! strcmp (ix86_fpmath_string, "sse,387"))
2262 warning (0, "SSE instruction set disabled, using 387 arithmetics");
2263 ix86_fpmath = FPMATH_387;
2265 else if (!TARGET_80387)
2267 warning (0, "387 instruction set disabled, using SSE arithmetics");
2268 ix86_fpmath = FPMATH_SSE;
2271 ix86_fpmath = FPMATH_SSE | FPMATH_387;
2274 error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
2277 /* If the i387 is disabled, then do not return values in it. */
2279 target_flags &= ~MASK_FLOAT_RETURNS;
2281 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
2282 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2284 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2286 /* ??? Unwind info is not correct around the CFG unless either a frame
2287 pointer is present or M_A_O_A is set. Fixing this requires rewriting
2288 unwind info generation to be aware of the CFG and propagating states
2290 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
2291 || flag_exceptions || flag_non_call_exceptions)
2292 && flag_omit_frame_pointer
2293 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
2295 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
2296 warning (0, "unwind tables currently require either a frame pointer "
2297 "or -maccumulate-outgoing-args for correctness");
2298 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
2301 /* For sane SSE instruction set generation we need fcomi instruction.
2302 It is safe to enable all CMOVE instructions. */
2306 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
2309 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
2310 p = strchr (internal_label_prefix, 'X');
2311 internal_label_prefix_len = p - internal_label_prefix;
2315 /* When scheduling description is not available, disable scheduler pass
2316 so it won't slow down the compilation and make x87 code slower. */
2317 if (!TARGET_SCHEDULE)
2318 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
2320 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
2321 set_param_value ("simultaneous-prefetches",
2322 ix86_cost->simultaneous_prefetches);
2323 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
2324 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
2327 /* Return true if this goes in large data/bss. */
2330 ix86_in_large_data_p (tree exp)
2332 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
2335 /* Functions are never large data. */
2336 if (TREE_CODE (exp) == FUNCTION_DECL)
2339 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
2341 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
2342 if (strcmp (section, ".ldata") == 0
2343 || strcmp (section, ".lbss") == 0)
2349 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
2351 /* If this is an incomplete type with size 0, then we can't put it
2352 in data because it might be too big when completed. */
2353 if (!size || size > ix86_section_threshold)
2360 /* Switch to the appropriate section for output of DECL.
2361 DECL is either a `VAR_DECL' node or a constant of some sort.
2362 RELOC indicates whether forming the initial value of DECL requires
2363 link-time relocations. */
2365 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
2369 x86_64_elf_select_section (tree decl, int reloc,
2370 unsigned HOST_WIDE_INT align)
2372 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2373 && ix86_in_large_data_p (decl))
2375 const char *sname = NULL;
2376 unsigned int flags = SECTION_WRITE;
2377 switch (categorize_decl_for_section (decl, reloc))
2382 case SECCAT_DATA_REL:
2383 sname = ".ldata.rel";
2385 case SECCAT_DATA_REL_LOCAL:
2386 sname = ".ldata.rel.local";
2388 case SECCAT_DATA_REL_RO:
2389 sname = ".ldata.rel.ro";
2391 case SECCAT_DATA_REL_RO_LOCAL:
2392 sname = ".ldata.rel.ro.local";
2396 flags |= SECTION_BSS;
2399 case SECCAT_RODATA_MERGE_STR:
2400 case SECCAT_RODATA_MERGE_STR_INIT:
2401 case SECCAT_RODATA_MERGE_CONST:
2405 case SECCAT_SRODATA:
2412 /* We don't split these for medium model. Place them into
2413 default sections and hope for best. */
2418 /* We might get called with string constants, but get_named_section
2419 doesn't like them as they are not DECLs. Also, we need to set
2420 flags in that case. */
2422 return get_section (sname, flags, NULL);
2423 return get_named_section (decl, sname, reloc);
2426 return default_elf_select_section (decl, reloc, align);
2429 /* Build up a unique section name, expressed as a
2430 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
2431 RELOC indicates whether the initial value of EXP requires
2432 link-time relocations. */
2434 static void ATTRIBUTE_UNUSED
2435 x86_64_elf_unique_section (tree decl, int reloc)
2437 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2438 && ix86_in_large_data_p (decl))
2440 const char *prefix = NULL;
2441 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
2442 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
2444 switch (categorize_decl_for_section (decl, reloc))
2447 case SECCAT_DATA_REL:
2448 case SECCAT_DATA_REL_LOCAL:
2449 case SECCAT_DATA_REL_RO:
2450 case SECCAT_DATA_REL_RO_LOCAL:
2451 prefix = one_only ? ".gnu.linkonce.ld." : ".ldata.";
2454 prefix = one_only ? ".gnu.linkonce.lb." : ".lbss.";
2457 case SECCAT_RODATA_MERGE_STR:
2458 case SECCAT_RODATA_MERGE_STR_INIT:
2459 case SECCAT_RODATA_MERGE_CONST:
2460 prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata.";
2462 case SECCAT_SRODATA:
2469 /* We don't split these for medium model. Place them into
2470 default sections and hope for best. */
2478 plen = strlen (prefix);
2480 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
2481 name = targetm.strip_name_encoding (name);
2482 nlen = strlen (name);
2484 string = alloca (nlen + plen + 1);
2485 memcpy (string, prefix, plen);
2486 memcpy (string + plen, name, nlen + 1);
2488 DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
2492 default_unique_section (decl, reloc);
2495 #ifdef COMMON_ASM_OP
2496 /* This says how to output assembler code to declare an
2497 uninitialized external linkage data object.
2499 For medium model x86-64 we need to use .largecomm opcode for
2502 x86_elf_aligned_common (FILE *file,
2503 const char *name, unsigned HOST_WIDE_INT size,
2506 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2507 && size > (unsigned int)ix86_section_threshold)
2508 fprintf (file, ".largecomm\t");
2510 fprintf (file, "%s", COMMON_ASM_OP);
2511 assemble_name (file, name);
2512 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
2513 size, align / BITS_PER_UNIT);
2517 /* Utility function for targets to use in implementing
2518 ASM_OUTPUT_ALIGNED_BSS. */
2521 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
2522 const char *name, unsigned HOST_WIDE_INT size,
2525 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
2526 && size > (unsigned int)ix86_section_threshold)
2527 switch_to_section (get_named_section (decl, ".lbss", 0));
2529 switch_to_section (bss_section);
2530 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
2531 #ifdef ASM_DECLARE_OBJECT_NAME
2532 last_assemble_variable_decl = decl;
2533 ASM_DECLARE_OBJECT_NAME (file, name, decl);
2535 /* Standard thing is just output label for the object. */
2536 ASM_OUTPUT_LABEL (file, name);
2537 #endif /* ASM_DECLARE_OBJECT_NAME */
2538 ASM_OUTPUT_SKIP (file, size ? size : 1);
2542 optimization_options (int level, int size ATTRIBUTE_UNUSED)
2544 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
2545 make the problem with not enough registers even worse. */
2546 #ifdef INSN_SCHEDULING
2548 flag_schedule_insns = 0;
2552 /* The Darwin libraries never set errno, so we might as well
2553 avoid calling them when that's the only reason we would. */
2554 flag_errno_math = 0;
2556 /* The default values of these switches depend on the TARGET_64BIT
2557 that is not known at this moment. Mark these values with 2 and
2558 let user the to override these. In case there is no command line option
2559 specifying them, we will set the defaults in override_options. */
2561 flag_omit_frame_pointer = 2;
2562 flag_pcc_struct_return = 2;
2563 flag_asynchronous_unwind_tables = 2;
2564 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
2565 SUBTARGET_OPTIMIZATION_OPTIONS;
2569 /* Decide whether we can make a sibling call to a function. DECL is the
2570 declaration of the function being targeted by the call and EXP is the
2571 CALL_EXPR representing the call. */
2574 ix86_function_ok_for_sibcall (tree decl, tree exp)
2579 /* If we are generating position-independent code, we cannot sibcall
2580 optimize any indirect call, or a direct call to a global function,
2581 as the PLT requires %ebx be live. */
2582 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
2589 func = TREE_TYPE (CALL_EXPR_FN (exp));
2590 if (POINTER_TYPE_P (func))
2591 func = TREE_TYPE (func);
2594 /* Check that the return value locations are the same. Like
2595 if we are returning floats on the 80387 register stack, we cannot
2596 make a sibcall from a function that doesn't return a float to a
2597 function that does or, conversely, from a function that does return
2598 a float to a function that doesn't; the necessary stack adjustment
2599 would not be executed. This is also the place we notice
2600 differences in the return value ABI. Note that it is ok for one
2601 of the functions to have void return type as long as the return
2602 value of the other is passed in a register. */
2603 a = ix86_function_value (TREE_TYPE (exp), func, false);
2604 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
2606 if (STACK_REG_P (a) || STACK_REG_P (b))
2608 if (!rtx_equal_p (a, b))
2611 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
2613 else if (!rtx_equal_p (a, b))
2616 /* If this call is indirect, we'll need to be able to use a call-clobbered
2617 register for the address of the target function. Make sure that all
2618 such registers are not used for passing parameters. */
2619 if (!decl && !TARGET_64BIT)
2623 /* We're looking at the CALL_EXPR, we need the type of the function. */
2624 type = CALL_EXPR_FN (exp); /* pointer expression */
2625 type = TREE_TYPE (type); /* pointer type */
2626 type = TREE_TYPE (type); /* function type */
2628 if (ix86_function_regparm (type, NULL) >= 3)
2630 /* ??? Need to count the actual number of registers to be used,
2631 not the possible number of registers. Fix later. */
2636 /* Dllimport'd functions are also called indirectly. */
2637 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
2638 && decl && DECL_DLLIMPORT_P (decl)
2639 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
2642 /* If we forced aligned the stack, then sibcalling would unalign the
2643 stack, which may break the called function. */
2644 if (cfun->machine->force_align_arg_pointer)
2647 /* Otherwise okay. That also includes certain types of indirect calls. */
2651 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
2652 calling convention attributes;
2653 arguments as in struct attribute_spec.handler. */
2656 ix86_handle_cconv_attribute (tree *node, tree name,
2658 int flags ATTRIBUTE_UNUSED,
2661 if (TREE_CODE (*node) != FUNCTION_TYPE
2662 && TREE_CODE (*node) != METHOD_TYPE
2663 && TREE_CODE (*node) != FIELD_DECL
2664 && TREE_CODE (*node) != TYPE_DECL)
2666 warning (OPT_Wattributes, "%qs attribute only applies to functions",
2667 IDENTIFIER_POINTER (name));
2668 *no_add_attrs = true;
2672 /* Can combine regparm with all attributes but fastcall. */
2673 if (is_attribute_p ("regparm", name))
2677 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2679 error ("fastcall and regparm attributes are not compatible");
2682 cst = TREE_VALUE (args);
2683 if (TREE_CODE (cst) != INTEGER_CST)
2685 warning (OPT_Wattributes,
2686 "%qs attribute requires an integer constant argument",
2687 IDENTIFIER_POINTER (name));
2688 *no_add_attrs = true;
2690 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
2692 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
2693 IDENTIFIER_POINTER (name), REGPARM_MAX);
2694 *no_add_attrs = true;
2698 && lookup_attribute (ix86_force_align_arg_pointer_string,
2699 TYPE_ATTRIBUTES (*node))
2700 && compare_tree_int (cst, REGPARM_MAX-1))
2702 error ("%s functions limited to %d register parameters",
2703 ix86_force_align_arg_pointer_string, REGPARM_MAX-1);
2711 /* Do not warn when emulating the MS ABI. */
2712 if (!TARGET_64BIT_MS_ABI)
2713 warning (OPT_Wattributes, "%qs attribute ignored",
2714 IDENTIFIER_POINTER (name));
2715 *no_add_attrs = true;
2719 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
2720 if (is_attribute_p ("fastcall", name))
2722 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2724 error ("fastcall and cdecl attributes are not compatible");
2726 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2728 error ("fastcall and stdcall attributes are not compatible");
2730 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
2732 error ("fastcall and regparm attributes are not compatible");
2736 /* Can combine stdcall with fastcall (redundant), regparm and
2738 else if (is_attribute_p ("stdcall", name))
2740 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
2742 error ("stdcall and cdecl attributes are not compatible");
2744 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2746 error ("stdcall and fastcall attributes are not compatible");
2750 /* Can combine cdecl with regparm and sseregparm. */
2751 else if (is_attribute_p ("cdecl", name))
2753 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
2755 error ("stdcall and cdecl attributes are not compatible");
2757 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
2759 error ("fastcall and cdecl attributes are not compatible");
2763 /* Can combine sseregparm with all attributes. */
2768 /* Return 0 if the attributes for two types are incompatible, 1 if they
2769 are compatible, and 2 if they are nearly compatible (which causes a
2770 warning to be generated). */
2773 ix86_comp_type_attributes (tree type1, tree type2)
2775 /* Check for mismatch of non-default calling convention. */
2776 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
2778 if (TREE_CODE (type1) != FUNCTION_TYPE)
2781 /* Check for mismatched fastcall/regparm types. */
2782 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
2783 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
2784 || (ix86_function_regparm (type1, NULL)
2785 != ix86_function_regparm (type2, NULL)))
2788 /* Check for mismatched sseregparm types. */
2789 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
2790 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
2793 /* Check for mismatched return types (cdecl vs stdcall). */
2794 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
2795 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
2801 /* Return the regparm value for a function with the indicated TYPE and DECL.
2802 DECL may be NULL when calling function indirectly
2803 or considering a libcall. */
2806 ix86_function_regparm (tree type, tree decl)
2809 int regparm = ix86_regparm;
2814 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
2816 return TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
2818 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
2821 /* Use register calling convention for local functions when possible. */
2822 if (decl && TREE_CODE (decl) == FUNCTION_DECL
2823 && flag_unit_at_a_time && !profile_flag)
2825 struct cgraph_local_info *i = cgraph_local_info (decl);
2828 int local_regparm, globals = 0, regno;
2831 /* Make sure no regparm register is taken by a
2832 global register variable. */
2833 for (local_regparm = 0; local_regparm < 3; local_regparm++)
2834 if (global_regs[local_regparm])
2837 /* We can't use regparm(3) for nested functions as these use
2838 static chain pointer in third argument. */
2839 if (local_regparm == 3
2840 && (decl_function_context (decl)
2841 || ix86_force_align_arg_pointer)
2842 && !DECL_NO_STATIC_CHAIN (decl))
2845 /* If the function realigns its stackpointer, the prologue will
2846 clobber %ecx. If we've already generated code for the callee,
2847 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
2848 scanning the attributes for the self-realigning property. */
2849 f = DECL_STRUCT_FUNCTION (decl);
2850 if (local_regparm == 3
2851 && (f ? !!f->machine->force_align_arg_pointer
2852 : !!lookup_attribute (ix86_force_align_arg_pointer_string,
2853 TYPE_ATTRIBUTES (TREE_TYPE (decl)))))
2856 /* Each global register variable increases register preassure,
2857 so the more global reg vars there are, the smaller regparm
2858 optimization use, unless requested by the user explicitly. */
2859 for (regno = 0; regno < 6; regno++)
2860 if (global_regs[regno])
2863 = globals < local_regparm ? local_regparm - globals : 0;
2865 if (local_regparm > regparm)
2866 regparm = local_regparm;
2873 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
2874 DFmode (2) arguments in SSE registers for a function with the
2875 indicated TYPE and DECL. DECL may be NULL when calling function
2876 indirectly or considering a libcall. Otherwise return 0. */
2879 ix86_function_sseregparm (tree type, tree decl)
2881 gcc_assert (!TARGET_64BIT);
2883 /* Use SSE registers to pass SFmode and DFmode arguments if requested
2884 by the sseregparm attribute. */
2885 if (TARGET_SSEREGPARM
2886 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
2891 error ("Calling %qD with attribute sseregparm without "
2892 "SSE/SSE2 enabled", decl);
2894 error ("Calling %qT with attribute sseregparm without "
2895 "SSE/SSE2 enabled", type);
2902 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
2903 (and DFmode for SSE2) arguments in SSE registers. */
2904 if (decl && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag)
2906 struct cgraph_local_info *i = cgraph_local_info (decl);
2908 return TARGET_SSE2 ? 2 : 1;
2914 /* Return true if EAX is live at the start of the function. Used by
2915 ix86_expand_prologue to determine if we need special help before
2916 calling allocate_stack_worker. */
2919 ix86_eax_live_at_start_p (void)
2921 /* Cheat. Don't bother working forward from ix86_function_regparm
2922 to the function type to whether an actual argument is located in
2923 eax. Instead just look at cfg info, which is still close enough
2924 to correct at this point. This gives false positives for broken
2925 functions that might use uninitialized data that happens to be
2926 allocated in eax, but who cares? */
2927 return REGNO_REG_SET_P (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end, 0);
2930 /* Return true if TYPE has a variable argument list. */
2933 type_has_variadic_args_p (tree type)
2935 tree n, t = TYPE_ARG_TYPES (type);
2940 while ((n = TREE_CHAIN (t)) != NULL)
2943 return TREE_VALUE (t) != void_type_node;
2946 /* Value is the number of bytes of arguments automatically
2947 popped when returning from a subroutine call.
2948 FUNDECL is the declaration node of the function (as a tree),
2949 FUNTYPE is the data type of the function (as a tree),
2950 or for a library call it is an identifier node for the subroutine name.
2951 SIZE is the number of bytes of arguments passed on the stack.
2953 On the 80386, the RTD insn may be used to pop them if the number
2954 of args is fixed, but if the number is variable then the caller
2955 must pop them all. RTD can't be used for library calls now
2956 because the library is compiled with the Unix compiler.
2957 Use of RTD is a selectable option, since it is incompatible with
2958 standard Unix calling sequences. If the option is not selected,
2959 the caller must always pop the args.
2961 The attribute stdcall is equivalent to RTD on a per module basis. */
2964 ix86_return_pops_args (tree fundecl, tree funtype, int size)
2968 /* None of the 64-bit ABIs pop arguments. */
2972 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
2974 /* Cdecl functions override -mrtd, and never pop the stack. */
2975 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
2977 /* Stdcall and fastcall functions will pop the stack if not
2979 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
2980 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
2983 if (rtd && ! type_has_variadic_args_p (funtype))
2987 /* Lose any fake structure return argument if it is passed on the stack. */
2988 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
2989 && !KEEP_AGGREGATE_RETURN_POINTER)
2991 int nregs = ix86_function_regparm (funtype, fundecl);
2993 return GET_MODE_SIZE (Pmode);
2999 /* Argument support functions. */
3001 /* Return true when register may be used to pass function parameters. */
3003 ix86_function_arg_regno_p (int regno)
3006 const int *parm_regs;
3011 return (regno < REGPARM_MAX
3012 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
3014 return (regno < REGPARM_MAX
3015 || (TARGET_MMX && MMX_REGNO_P (regno)
3016 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
3017 || (TARGET_SSE && SSE_REGNO_P (regno)
3018 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
3023 if (SSE_REGNO_P (regno) && TARGET_SSE)
3028 if (TARGET_SSE && SSE_REGNO_P (regno)
3029 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
3033 /* RAX is used as hidden argument to va_arg functions. */
3034 if (!TARGET_64BIT_MS_ABI && regno == 0)
3037 if (TARGET_64BIT_MS_ABI)
3038 parm_regs = x86_64_ms_abi_int_parameter_registers;
3040 parm_regs = x86_64_int_parameter_registers;
3041 for (i = 0; i < REGPARM_MAX; i++)
3042 if (regno == parm_regs[i])
3047 /* Return if we do not know how to pass TYPE solely in registers. */
3050 ix86_must_pass_in_stack (enum machine_mode mode, tree type)
3052 if (must_pass_in_stack_var_size_or_pad (mode, type))
3055 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
3056 The layout_type routine is crafty and tries to trick us into passing
3057 currently unsupported vector types on the stack by using TImode. */
3058 return (!TARGET_64BIT && mode == TImode
3059 && type && TREE_CODE (type) != VECTOR_TYPE);
3062 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3063 for a call to a function whose data type is FNTYPE.
3064 For a library call, FNTYPE is 0. */
3067 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
3068 tree fntype, /* tree ptr for function decl */
3069 rtx libname, /* SYMBOL_REF of library name or 0 */
3072 memset (cum, 0, sizeof (*cum));
3074 /* Set up the number of registers to use for passing arguments. */
3075 cum->nregs = ix86_regparm;
3077 cum->sse_nregs = SSE_REGPARM_MAX;
3079 cum->mmx_nregs = MMX_REGPARM_MAX;
3080 cum->warn_sse = true;
3081 cum->warn_mmx = true;
3082 cum->maybe_vaarg = (fntype
3083 ? (!TYPE_ARG_TYPES (fntype)
3084 || type_has_variadic_args_p (fntype))
3089 /* If there are variable arguments, then we won't pass anything
3090 in registers in 32-bit mode. */
3091 if (cum->maybe_vaarg)
3101 /* Use ecx and edx registers if function has fastcall attribute,
3102 else look for regparm information. */
3105 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
3111 cum->nregs = ix86_function_regparm (fntype, fndecl);
3114 /* Set up the number of SSE registers used for passing SFmode
3115 and DFmode arguments. Warn for mismatching ABI. */
3116 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl);
3120 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
3121 But in the case of vector types, it is some vector mode.
3123 When we have only some of our vector isa extensions enabled, then there
3124 are some modes for which vector_mode_supported_p is false. For these
3125 modes, the generic vector support in gcc will choose some non-vector mode
3126 in order to implement the type. By computing the natural mode, we'll
3127 select the proper ABI location for the operand and not depend on whatever
3128 the middle-end decides to do with these vector types. */
3130 static enum machine_mode
3131 type_natural_mode (tree type)
3133 enum machine_mode mode = TYPE_MODE (type);
3135 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
3137 HOST_WIDE_INT size = int_size_in_bytes (type);
3138 if ((size == 8 || size == 16)
3139 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
3140 && TYPE_VECTOR_SUBPARTS (type) > 1)
3142 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
3144 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
3145 mode = MIN_MODE_VECTOR_FLOAT;
3147 mode = MIN_MODE_VECTOR_INT;
3149 /* Get the mode which has this inner mode and number of units. */
3150 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
3151 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
3152 && GET_MODE_INNER (mode) == innermode)
3162 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
3163 this may not agree with the mode that the type system has chosen for the
3164 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
3165 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
3168 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
3173 if (orig_mode != BLKmode)
3174 tmp = gen_rtx_REG (orig_mode, regno);
3177 tmp = gen_rtx_REG (mode, regno);
3178 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
3179 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
3185 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
3186 of this code is to classify each 8bytes of incoming argument by the register
3187 class and assign registers accordingly. */
3189 /* Return the union class of CLASS1 and CLASS2.
3190 See the x86-64 PS ABI for details. */
3192 static enum x86_64_reg_class
3193 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
3195 /* Rule #1: If both classes are equal, this is the resulting class. */
3196 if (class1 == class2)
3199 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
3201 if (class1 == X86_64_NO_CLASS)
3203 if (class2 == X86_64_NO_CLASS)
3206 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
3207 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
3208 return X86_64_MEMORY_CLASS;
3210 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
3211 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
3212 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
3213 return X86_64_INTEGERSI_CLASS;
3214 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
3215 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
3216 return X86_64_INTEGER_CLASS;
3218 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
3220 if (class1 == X86_64_X87_CLASS
3221 || class1 == X86_64_X87UP_CLASS
3222 || class1 == X86_64_COMPLEX_X87_CLASS
3223 || class2 == X86_64_X87_CLASS
3224 || class2 == X86_64_X87UP_CLASS
3225 || class2 == X86_64_COMPLEX_X87_CLASS)
3226 return X86_64_MEMORY_CLASS;
3228 /* Rule #6: Otherwise class SSE is used. */
3229 return X86_64_SSE_CLASS;
3232 /* Classify the argument of type TYPE and mode MODE.
3233 CLASSES will be filled by the register class used to pass each word
3234 of the operand. The number of words is returned. In case the parameter
3235 should be passed in memory, 0 is returned. As a special case for zero
3236 sized containers, classes[0] will be NO_CLASS and 1 is returned.
3238 BIT_OFFSET is used internally for handling records and specifies offset
3239 of the offset in bits modulo 256 to avoid overflow cases.
3241 See the x86-64 PS ABI for details.
3245 classify_argument (enum machine_mode mode, tree type,
3246 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
3248 HOST_WIDE_INT bytes =
3249 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3250 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3252 /* Variable sized entities are always passed/returned in memory. */
3256 if (mode != VOIDmode
3257 && targetm.calls.must_pass_in_stack (mode, type))
3260 if (type && AGGREGATE_TYPE_P (type))
3264 enum x86_64_reg_class subclasses[MAX_CLASSES];
3266 /* On x86-64 we pass structures larger than 16 bytes on the stack. */
3270 for (i = 0; i < words; i++)
3271 classes[i] = X86_64_NO_CLASS;
3273 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
3274 signalize memory class, so handle it as special case. */
3277 classes[0] = X86_64_NO_CLASS;
3281 /* Classify each field of record and merge classes. */
3282 switch (TREE_CODE (type))
3285 /* And now merge the fields of structure. */
3286 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3288 if (TREE_CODE (field) == FIELD_DECL)
3292 if (TREE_TYPE (field) == error_mark_node)
3295 /* Bitfields are always classified as integer. Handle them
3296 early, since later code would consider them to be
3297 misaligned integers. */
3298 if (DECL_BIT_FIELD (field))
3300 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3301 i < ((int_bit_position (field) + (bit_offset % 64))
3302 + tree_low_cst (DECL_SIZE (field), 0)
3305 merge_classes (X86_64_INTEGER_CLASS,
3310 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3311 TREE_TYPE (field), subclasses,
3312 (int_bit_position (field)
3313 + bit_offset) % 256);
3316 for (i = 0; i < num; i++)
3319 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
3321 merge_classes (subclasses[i], classes[i + pos]);
3329 /* Arrays are handled as small records. */
3332 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
3333 TREE_TYPE (type), subclasses, bit_offset);
3337 /* The partial classes are now full classes. */
3338 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
3339 subclasses[0] = X86_64_SSE_CLASS;
3340 if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
3341 subclasses[0] = X86_64_INTEGER_CLASS;
3343 for (i = 0; i < words; i++)
3344 classes[i] = subclasses[i % num];
3349 case QUAL_UNION_TYPE:
3350 /* Unions are similar to RECORD_TYPE but offset is always 0.
3352 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3354 if (TREE_CODE (field) == FIELD_DECL)
3358 if (TREE_TYPE (field) == error_mark_node)
3361 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
3362 TREE_TYPE (field), subclasses,
3366 for (i = 0; i < num; i++)
3367 classes[i] = merge_classes (subclasses[i], classes[i]);
3376 /* Final merger cleanup. */
3377 for (i = 0; i < words; i++)
3379 /* If one class is MEMORY, everything should be passed in
3381 if (classes[i] == X86_64_MEMORY_CLASS)
3384 /* The X86_64_SSEUP_CLASS should be always preceded by
3385 X86_64_SSE_CLASS. */
3386 if (classes[i] == X86_64_SSEUP_CLASS
3387 && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
3388 classes[i] = X86_64_SSE_CLASS;
3390 /* X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS. */
3391 if (classes[i] == X86_64_X87UP_CLASS
3392 && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
3393 classes[i] = X86_64_SSE_CLASS;
3398 /* Compute alignment needed. We align all types to natural boundaries with
3399 exception of XFmode that is aligned to 64bits. */
3400 if (mode != VOIDmode && mode != BLKmode)
3402 int mode_alignment = GET_MODE_BITSIZE (mode);
3405 mode_alignment = 128;
3406 else if (mode == XCmode)
3407 mode_alignment = 256;
3408 if (COMPLEX_MODE_P (mode))
3409 mode_alignment /= 2;
3410 /* Misaligned fields are always returned in memory. */
3411 if (bit_offset % mode_alignment)
3415 /* for V1xx modes, just use the base mode */
3416 if (VECTOR_MODE_P (mode)
3417 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
3418 mode = GET_MODE_INNER (mode);
3420 /* Classification of atomic types. */
3425 classes[0] = X86_64_SSE_CLASS;
3428 classes[0] = X86_64_SSE_CLASS;
3429 classes[1] = X86_64_SSEUP_CLASS;
3438 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3439 classes[0] = X86_64_INTEGERSI_CLASS;
3441 classes[0] = X86_64_INTEGER_CLASS;
3445 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
3450 if (!(bit_offset % 64))
3451 classes[0] = X86_64_SSESF_CLASS;
3453 classes[0] = X86_64_SSE_CLASS;
3456 classes[0] = X86_64_SSEDF_CLASS;
3459 classes[0] = X86_64_X87_CLASS;
3460 classes[1] = X86_64_X87UP_CLASS;
3463 classes[0] = X86_64_SSE_CLASS;
3464 classes[1] = X86_64_SSEUP_CLASS;
3467 classes[0] = X86_64_SSE_CLASS;
3470 classes[0] = X86_64_SSEDF_CLASS;
3471 classes[1] = X86_64_SSEDF_CLASS;
3474 classes[0] = X86_64_COMPLEX_X87_CLASS;
3477 /* This modes is larger than 16 bytes. */
3485 classes[0] = X86_64_SSE_CLASS;
3486 classes[1] = X86_64_SSEUP_CLASS;
3492 classes[0] = X86_64_SSE_CLASS;
3498 gcc_assert (VECTOR_MODE_P (mode));
3503 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
3505 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
3506 classes[0] = X86_64_INTEGERSI_CLASS;
3508 classes[0] = X86_64_INTEGER_CLASS;
3509 classes[1] = X86_64_INTEGER_CLASS;
3510 return 1 + (bytes > 8);
3514 /* Examine the argument and return set number of register required in each
3515 class. Return 0 iff parameter should be passed in memory. */
3517 examine_argument (enum machine_mode mode, tree type, int in_return,
3518 int *int_nregs, int *sse_nregs)
3520 enum x86_64_reg_class class[MAX_CLASSES];
3521 int n = classify_argument (mode, type, class, 0);
3527 for (n--; n >= 0; n--)
3530 case X86_64_INTEGER_CLASS:
3531 case X86_64_INTEGERSI_CLASS:
3534 case X86_64_SSE_CLASS:
3535 case X86_64_SSESF_CLASS:
3536 case X86_64_SSEDF_CLASS:
3539 case X86_64_NO_CLASS:
3540 case X86_64_SSEUP_CLASS:
3542 case X86_64_X87_CLASS:
3543 case X86_64_X87UP_CLASS:
3547 case X86_64_COMPLEX_X87_CLASS:
3548 return in_return ? 2 : 0;
3549 case X86_64_MEMORY_CLASS:
3555 /* Construct container for the argument used by GCC interface. See
3556 FUNCTION_ARG for the detailed description. */
3559 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
3560 tree type, int in_return, int nintregs, int nsseregs,
3561 const int *intreg, int sse_regno)
3563 /* The following variables hold the static issued_error state. */
3564 static bool issued_sse_arg_error;
3565 static bool issued_sse_ret_error;
3566 static bool issued_x87_ret_error;
3568 enum machine_mode tmpmode;
3570 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
3571 enum x86_64_reg_class class[MAX_CLASSES];
3575 int needed_sseregs, needed_intregs;
3576 rtx exp[MAX_CLASSES];
3579 n = classify_argument (mode, type, class, 0);
3582 if (!examine_argument (mode, type, in_return, &needed_intregs,
3585 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
3588 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
3589 some less clueful developer tries to use floating-point anyway. */
3590 if (needed_sseregs && !TARGET_SSE)
3594 if (!issued_sse_ret_error)
3596 error ("SSE register return with SSE disabled");
3597 issued_sse_ret_error = true;
3600 else if (!issued_sse_arg_error)
3602 error ("SSE register argument with SSE disabled");
3603 issued_sse_arg_error = true;
3608 /* Likewise, error if the ABI requires us to return values in the
3609 x87 registers and the user specified -mno-80387. */
3610 if (!TARGET_80387 && in_return)
3611 for (i = 0; i < n; i++)
3612 if (class[i] == X86_64_X87_CLASS
3613 || class[i] == X86_64_X87UP_CLASS
3614 || class[i] == X86_64_COMPLEX_X87_CLASS)
3616 if (!issued_x87_ret_error)
3618 error ("x87 register return with x87 disabled");
3619 issued_x87_ret_error = true;
3624 /* First construct simple cases. Avoid SCmode, since we want to use
3625 single register to pass this type. */
3626 if (n == 1 && mode != SCmode)
3629 case X86_64_INTEGER_CLASS:
3630 case X86_64_INTEGERSI_CLASS:
3631 return gen_rtx_REG (mode, intreg[0]);
3632 case X86_64_SSE_CLASS:
3633 case X86_64_SSESF_CLASS:
3634 case X86_64_SSEDF_CLASS:
3635 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
3636 case X86_64_X87_CLASS:
3637 case X86_64_COMPLEX_X87_CLASS:
3638 return gen_rtx_REG (mode, FIRST_STACK_REG);
3639 case X86_64_NO_CLASS:
3640 /* Zero sized array, struct or class. */
3645 if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS
3647 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
3650 && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
3651 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
3652 if (n == 2 && class[0] == X86_64_INTEGER_CLASS
3653 && class[1] == X86_64_INTEGER_CLASS
3654 && (mode == CDImode || mode == TImode || mode == TFmode)
3655 && intreg[0] + 1 == intreg[1])
3656 return gen_rtx_REG (mode, intreg[0]);
3658 /* Otherwise figure out the entries of the PARALLEL. */
3659 for (i = 0; i < n; i++)
3663 case X86_64_NO_CLASS:
3665 case X86_64_INTEGER_CLASS:
3666 case X86_64_INTEGERSI_CLASS:
3667 /* Merge TImodes on aligned occasions here too. */
3668 if (i * 8 + 8 > bytes)
3669 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
3670 else if (class[i] == X86_64_INTEGERSI_CLASS)
3674 /* We've requested 24 bytes we don't have mode for. Use DImode. */
3675 if (tmpmode == BLKmode)
3677 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3678 gen_rtx_REG (tmpmode, *intreg),
3682 case X86_64_SSESF_CLASS:
3683 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3684 gen_rtx_REG (SFmode,
3685 SSE_REGNO (sse_regno)),
3689 case X86_64_SSEDF_CLASS:
3690 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3691 gen_rtx_REG (DFmode,
3692 SSE_REGNO (sse_regno)),
3696 case X86_64_SSE_CLASS:
3697 if (i < n - 1 && class[i + 1] == X86_64_SSEUP_CLASS)
3701 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
3702 gen_rtx_REG (tmpmode,
3703 SSE_REGNO (sse_regno)),
3705 if (tmpmode == TImode)
3714 /* Empty aligned struct, union or class. */
3718 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
3719 for (i = 0; i < nexps; i++)
3720 XVECEXP (ret, 0, i) = exp [i];
3724 /* Update the data in CUM to advance over an argument of mode MODE
3725 and data type TYPE. (TYPE is null for libcalls where that information
3726 may not be available.) */
3729 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3730 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
3746 cum->words += words;
3747 cum->nregs -= words;
3748 cum->regno += words;
3750 if (cum->nregs <= 0)
3758 if (cum->float_in_sse < 2)
3761 if (cum->float_in_sse < 1)
3772 if (!type || !AGGREGATE_TYPE_P (type))
3774 cum->sse_words += words;
3775 cum->sse_nregs -= 1;
3776 cum->sse_regno += 1;
3777 if (cum->sse_nregs <= 0)
3789 if (!type || !AGGREGATE_TYPE_P (type))
3791 cum->mmx_words += words;
3792 cum->mmx_nregs -= 1;
3793 cum->mmx_regno += 1;
3794 if (cum->mmx_nregs <= 0)
3805 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3806 tree type, HOST_WIDE_INT words)
3808 int int_nregs, sse_nregs;
3810 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
3811 cum->words += words;
3812 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
3814 cum->nregs -= int_nregs;
3815 cum->sse_nregs -= sse_nregs;
3816 cum->regno += int_nregs;
3817 cum->sse_regno += sse_nregs;
3820 cum->words += words;
3824 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
3825 HOST_WIDE_INT words)
3827 /* Otherwise, this should be passed indirect. */
3828 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
3830 cum->words += words;
3839 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3840 tree type, int named ATTRIBUTE_UNUSED)
3842 HOST_WIDE_INT bytes, words;
3844 if (mode == BLKmode)
3845 bytes = int_size_in_bytes (type);
3847 bytes = GET_MODE_SIZE (mode);
3848 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3851 mode = type_natural_mode (type);
3853 if (TARGET_64BIT_MS_ABI)
3854 function_arg_advance_ms_64 (cum, bytes, words);
3855 else if (TARGET_64BIT)
3856 function_arg_advance_64 (cum, mode, type, words);
3858 function_arg_advance_32 (cum, mode, type, bytes, words);
3861 /* Define where to put the arguments to a function.
3862 Value is zero to push the argument on the stack,
3863 or a hard register in which to store the argument.
3865 MODE is the argument's machine mode.
3866 TYPE is the data type of the argument (as a tree).
3867 This is null for libcalls where that information may
3869 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3870 the preceding args and about the function being called.
3871 NAMED is nonzero if this argument is a named parameter
3872 (otherwise it is an extra parameter matching an ellipsis). */
3875 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3876 enum machine_mode orig_mode, tree type,
3877 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
3879 static bool warnedsse, warnedmmx;
3881 /* Avoid the AL settings for the Unix64 ABI. */
3882 if (mode == VOIDmode)
3898 if (words <= cum->nregs)
3900 int regno = cum->regno;
3902 /* Fastcall allocates the first two DWORD (SImode) or
3903 smaller arguments to ECX and EDX. */
3906 if (mode == BLKmode || mode == DImode)
3909 /* ECX not EAX is the first allocated register. */
3913 return gen_rtx_REG (mode, regno);
3918 if (cum->float_in_sse < 2)
3921 if (cum->float_in_sse < 1)
3931 if (!type || !AGGREGATE_TYPE_P (type))
3933 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
3936 warning (0, "SSE vector argument without SSE enabled "
3940 return gen_reg_or_parallel (mode, orig_mode,
3941 cum->sse_regno + FIRST_SSE_REG);
3949 if (!type || !AGGREGATE_TYPE_P (type))
3951 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
3954 warning (0, "MMX vector argument without MMX enabled "
3958 return gen_reg_or_parallel (mode, orig_mode,
3959 cum->mmx_regno + FIRST_MMX_REG);
3968 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3969 enum machine_mode orig_mode, tree type)
3971 /* Handle a hidden AL argument containing number of registers
3972 for varargs x86-64 functions. */
3973 if (mode == VOIDmode)
3974 return GEN_INT (cum->maybe_vaarg
3975 ? (cum->sse_nregs < 0
3980 return construct_container (mode, orig_mode, type, 0, cum->nregs,
3982 &x86_64_int_parameter_registers [cum->regno],
3987 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3988 enum machine_mode orig_mode, int named)
3992 /* Avoid the AL settings for the Unix64 ABI. */
3993 if (mode == VOIDmode)
3996 /* If we've run out of registers, it goes on the stack. */
3997 if (cum->nregs == 0)
4000 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
4002 /* Only floating point modes are passed in anything but integer regs. */
4003 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
4006 regno = cum->regno + FIRST_SSE_REG;
4011 /* Unnamed floating parameters are passed in both the
4012 SSE and integer registers. */
4013 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
4014 t2 = gen_rtx_REG (mode, regno);
4015 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
4016 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
4017 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
4021 return gen_reg_or_parallel (mode, orig_mode, regno);
4025 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
4026 tree type, int named)
4028 enum machine_mode mode = omode;
4029 HOST_WIDE_INT bytes, words;
4031 if (mode == BLKmode)
4032 bytes = int_size_in_bytes (type);
4034 bytes = GET_MODE_SIZE (mode);
4035 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4037 /* To simplify the code below, represent vector types with a vector mode
4038 even if MMX/SSE are not active. */
4039 if (type && TREE_CODE (type) == VECTOR_TYPE)
4040 mode = type_natural_mode (type);
4042 if (TARGET_64BIT_MS_ABI)
4043 return function_arg_ms_64 (cum, mode, omode, named);
4044 else if (TARGET_64BIT)
4045 return function_arg_64 (cum, mode, omode, type);
4047 return function_arg_32 (cum, mode, omode, type, bytes, words);
4050 /* A C expression that indicates when an argument must be passed by
4051 reference. If nonzero for an argument, a copy of that argument is
4052 made in memory and a pointer to the argument is passed instead of
4053 the argument itself. The pointer is passed in whatever way is
4054 appropriate for passing a pointer to that type. */
4057 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4058 enum machine_mode mode ATTRIBUTE_UNUSED,
4059 tree type, bool named ATTRIBUTE_UNUSED)
4061 if (TARGET_64BIT_MS_ABI)
4065 /* Arrays are passed by reference. */
4066 if (TREE_CODE (type) == ARRAY_TYPE)
4069 if (AGGREGATE_TYPE_P (type))
4071 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
4072 are passed by reference. */
4073 int el2 = exact_log2 (int_size_in_bytes (type));
4074 return !(el2 >= 0 && el2 <= 3);
4078 /* __m128 is passed by reference. */
4079 /* ??? How to handle complex? For now treat them as structs,
4080 and pass them by reference if they're too large. */
4081 if (GET_MODE_SIZE (mode) > 8)
4084 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
4090 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
4091 ABI. Only called if TARGET_SSE. */
4093 contains_128bit_aligned_vector_p (tree type)
4095 enum machine_mode mode = TYPE_MODE (type);
4096 if (SSE_REG_MODE_P (mode)
4097 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
4099 if (TYPE_ALIGN (type) < 128)
4102 if (AGGREGATE_TYPE_P (type))
4104 /* Walk the aggregates recursively. */
4105 switch (TREE_CODE (type))
4109 case QUAL_UNION_TYPE:
4113 /* Walk all the structure fields. */
4114 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4116 if (TREE_CODE (field) == FIELD_DECL
4117 && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
4124 /* Just for use if some languages passes arrays by value. */
4125 if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
4136 /* Gives the alignment boundary, in bits, of an argument with the
4137 specified mode and type. */
4140 ix86_function_arg_boundary (enum machine_mode mode, tree type)
4144 align = TYPE_ALIGN (type);
4146 align = GET_MODE_ALIGNMENT (mode);
4147 if (align < PARM_BOUNDARY)
4148 align = PARM_BOUNDARY;
4151 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
4152 make an exception for SSE modes since these require 128bit
4155 The handling here differs from field_alignment. ICC aligns MMX
4156 arguments to 4 byte boundaries, while structure fields are aligned
4157 to 8 byte boundaries. */
4159 align = PARM_BOUNDARY;
4162 if (!SSE_REG_MODE_P (mode))
4163 align = PARM_BOUNDARY;
4167 if (!contains_128bit_aligned_vector_p (type))
4168 align = PARM_BOUNDARY;
4176 /* Return true if N is a possible register number of function value. */
4179 ix86_function_value_regno_p (int regno)
4186 case FIRST_FLOAT_REG:
4187 if (TARGET_64BIT_MS_ABI)
4189 return TARGET_FLOAT_RETURNS_IN_80387;
4195 if (TARGET_MACHO || TARGET_64BIT)
4203 /* Define how to find the value returned by a function.
4204 VALTYPE is the data type of the value (as a tree).
4205 If the precise function being called is known, FUNC is its FUNCTION_DECL;
4206 otherwise, FUNC is 0. */
4209 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
4210 tree fntype, tree fn)
4214 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
4215 we normally prevent this case when mmx is not available. However
4216 some ABIs may require the result to be returned like DImode. */
4217 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4218 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
4220 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
4221 we prevent this case when sse is not available. However some ABIs
4222 may require the result to be returned like integer TImode. */
4223 else if (mode == TImode
4224 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4225 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
4227 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
4228 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
4229 regno = FIRST_FLOAT_REG;
4231 /* Most things go in %eax. */
4234 /* Override FP return register with %xmm0 for local functions when
4235 SSE math is enabled or for functions with sseregparm attribute. */
4236 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
4238 int sse_level = ix86_function_sseregparm (fntype, fn);
4239 if ((sse_level >= 1 && mode == SFmode)
4240 || (sse_level == 2 && mode == DFmode))
4241 regno = FIRST_SSE_REG;
4244 return gen_rtx_REG (orig_mode, regno);
4248 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
4253 /* Handle libcalls, which don't provide a type node. */
4254 if (valtype == NULL)
4266 return gen_rtx_REG (mode, FIRST_SSE_REG);
4269 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
4273 return gen_rtx_REG (mode, 0);
4277 ret = construct_container (mode, orig_mode, valtype, 1,
4278 REGPARM_MAX, SSE_REGPARM_MAX,
4279 x86_64_int_return_registers, 0);
4281 /* For zero sized structures, construct_container returns NULL, but we
4282 need to keep rest of compiler happy by returning meaningful value. */
4284 ret = gen_rtx_REG (orig_mode, 0);
4290 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
4292 unsigned int regno = 0;
4296 if (mode == SFmode || mode == DFmode)
4297 regno = FIRST_SSE_REG;
4298 else if (VECTOR_MODE_P (mode) || GET_MODE_SIZE (mode) == 16)
4299 regno = FIRST_SSE_REG;
4302 return gen_rtx_REG (orig_mode, regno);
4306 ix86_function_value_1 (tree valtype, tree fntype_or_decl,
4307 enum machine_mode orig_mode, enum machine_mode mode)
4312 if (fntype_or_decl && DECL_P (fntype_or_decl))
4313 fn = fntype_or_decl;
4314 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
4316 if (TARGET_64BIT_MS_ABI)
4317 return function_value_ms_64 (orig_mode, mode);
4318 else if (TARGET_64BIT)
4319 return function_value_64 (orig_mode, mode, valtype);
4321 return function_value_32 (orig_mode, mode, fntype, fn);
4325 ix86_function_value (tree valtype, tree fntype_or_decl,
4326 bool outgoing ATTRIBUTE_UNUSED)
4328 enum machine_mode mode, orig_mode;
4330 orig_mode = TYPE_MODE (valtype);
4331 mode = type_natural_mode (valtype);
4332 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
4336 ix86_libcall_value (enum machine_mode mode)
4338 return ix86_function_value_1 (NULL, NULL, mode, mode);
4341 /* Return true iff type is returned in memory. */
4344 return_in_memory_32 (tree type, enum machine_mode mode)
4348 if (mode == BLKmode)
4351 size = int_size_in_bytes (type);
4353 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
4356 if (VECTOR_MODE_P (mode) || mode == TImode)
4358 /* User-created vectors small enough to fit in EAX. */
4362 /* MMX/3dNow values are returned in MM0,
4363 except when it doesn't exits. */
4365 return (TARGET_MMX ? 0 : 1);
4367 /* SSE values are returned in XMM0, except when it doesn't exist. */
4369 return (TARGET_SSE ? 0 : 1);
4384 return_in_memory_64 (tree type, enum machine_mode mode)
4386 int needed_intregs, needed_sseregs;
4387 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
4391 return_in_memory_ms_64 (tree type, enum machine_mode mode)
4393 HOST_WIDE_INT size = int_size_in_bytes (type);
4395 /* __m128 and friends are returned in xmm0. */
4396 if (size == 16 && VECTOR_MODE_P (mode))
4399 /* Otherwise, the size must be exactly in [1248]. */
4400 return (size != 1 && size != 2 && size != 4 && size != 8);
4404 ix86_return_in_memory (tree type)
4406 enum machine_mode mode = type_natural_mode (type);
4408 if (TARGET_64BIT_MS_ABI)
4409 return return_in_memory_ms_64 (type, mode);
4410 else if (TARGET_64BIT)
4411 return return_in_memory_64 (type, mode);
4413 return return_in_memory_32 (type, mode);
4416 /* Return false iff TYPE is returned in memory. This version is used
4417 on Solaris 10. It is similar to the generic ix86_return_in_memory,
4418 but differs notably in that when MMX is available, 8-byte vectors
4419 are returned in memory, rather than in MMX registers. */
4422 ix86_sol10_return_in_memory (tree type)
4425 enum machine_mode mode = type_natural_mode (type);
4428 return return_in_memory_64 (type, mode);
4430 if (mode == BLKmode)
4433 size = int_size_in_bytes (type);
4435 if (VECTOR_MODE_P (mode))
4437 /* Return in memory only if MMX registers *are* available. This
4438 seems backwards, but it is consistent with the existing
4445 else if (mode == TImode)
4447 else if (mode == XFmode)
4453 /* When returning SSE vector types, we have a choice of either
4454 (1) being abi incompatible with a -march switch, or
4455 (2) generating an error.
4456 Given no good solution, I think the safest thing is one warning.
4457 The user won't be able to use -Werror, but....
4459 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
4460 called in response to actually generating a caller or callee that
4461 uses such a type. As opposed to RETURN_IN_MEMORY, which is called
4462 via aggregate_value_p for general type probing from tree-ssa. */
4465 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
4467 static bool warnedsse, warnedmmx;
4469 if (!TARGET_64BIT && type)
4471 /* Look at the return type of the function, not the function type. */
4472 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
4474 if (!TARGET_SSE && !warnedsse)
4477 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
4480 warning (0, "SSE vector return without SSE enabled "
4485 if (!TARGET_MMX && !warnedmmx)
4487 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
4490 warning (0, "MMX vector return without MMX enabled "
4500 /* Create the va_list data type. */
4503 ix86_build_builtin_va_list (void)
4505 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
4507 /* For i386 we use plain pointer to argument area. */
4508 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
4509 return build_pointer_type (char_type_node);
4511 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4512 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4514 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
4515 unsigned_type_node);
4516 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
4517 unsigned_type_node);
4518 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4520 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4523 va_list_gpr_counter_field = f_gpr;
4524 va_list_fpr_counter_field = f_fpr;
4526 DECL_FIELD_CONTEXT (f_gpr) = record;
4527 DECL_FIELD_CONTEXT (f_fpr) = record;
4528 DECL_FIELD_CONTEXT (f_ovf) = record;
4529 DECL_FIELD_CONTEXT (f_sav) = record;
4531 TREE_CHAIN (record) = type_decl;
4532 TYPE_NAME (record) = type_decl;
4533 TYPE_FIELDS (record) = f_gpr;
4534 TREE_CHAIN (f_gpr) = f_fpr;
4535 TREE_CHAIN (f_fpr) = f_ovf;
4536 TREE_CHAIN (f_ovf) = f_sav;
4538 layout_type (record);
4540 /* The correct type is an array type of one element. */
4541 return build_array_type (record, build_index_type (size_zero_node));
4544 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4547 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
4557 if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size)
4560 /* Indicate to allocate space on the stack for varargs save area. */
4561 ix86_save_varrargs_registers = 1;
4562 cfun->stack_alignment_needed = 128;
4564 save_area = frame_pointer_rtx;
4565 set = get_varargs_alias_set ();
4567 for (i = cum->regno;
4569 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
4572 mem = gen_rtx_MEM (Pmode,
4573 plus_constant (save_area, i * UNITS_PER_WORD));
4574 MEM_NOTRAP_P (mem) = 1;
4575 set_mem_alias_set (mem, set);
4576 emit_move_insn (mem, gen_rtx_REG (Pmode,
4577 x86_64_int_parameter_registers[i]));
4580 if (cum->sse_nregs && cfun->va_list_fpr_size)
4582 /* Now emit code to save SSE registers. The AX parameter contains number
4583 of SSE parameter registers used to call this function. We use
4584 sse_prologue_save insn template that produces computed jump across
4585 SSE saves. We need some preparation work to get this working. */
4587 label = gen_label_rtx ();
4588 label_ref = gen_rtx_LABEL_REF (Pmode, label);
4590 /* Compute address to jump to :
4591 label - 5*eax + nnamed_sse_arguments*5 */
4592 tmp_reg = gen_reg_rtx (Pmode);
4593 nsse_reg = gen_reg_rtx (Pmode);
4594 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, 0)));
4595 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4596 gen_rtx_MULT (Pmode, nsse_reg,
4601 gen_rtx_CONST (DImode,
4602 gen_rtx_PLUS (DImode,
4604 GEN_INT (cum->sse_regno * 4))));
4606 emit_move_insn (nsse_reg, label_ref);
4607 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
4609 /* Compute address of memory block we save into. We always use pointer
4610 pointing 127 bytes after first byte to store - this is needed to keep
4611 instruction size limited by 4 bytes. */
4612 tmp_reg = gen_reg_rtx (Pmode);
4613 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
4614 plus_constant (save_area,
4615 8 * REGPARM_MAX + 127)));
4616 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
4617 MEM_NOTRAP_P (mem) = 1;
4618 set_mem_alias_set (mem, set);
4619 set_mem_align (mem, BITS_PER_WORD);
4621 /* And finally do the dirty job! */
4622 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
4623 GEN_INT (cum->sse_regno), label));
4628 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
4630 int set = get_varargs_alias_set ();
4633 for (i = cum->regno; i < REGPARM_MAX; i++)
4637 mem = gen_rtx_MEM (Pmode,
4638 plus_constant (virtual_incoming_args_rtx,
4639 i * UNITS_PER_WORD));
4640 MEM_NOTRAP_P (mem) = 1;
4641 set_mem_alias_set (mem, set);
4643 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
4644 emit_move_insn (mem, reg);
4649 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4650 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4653 CUMULATIVE_ARGS next_cum;
4657 /* This argument doesn't appear to be used anymore. Which is good,
4658 because the old code here didn't suppress rtl generation. */
4659 gcc_assert (!no_rtl);
4664 fntype = TREE_TYPE (current_function_decl);
4665 stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
4666 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4667 != void_type_node));
4669 /* For varargs, we do not want to skip the dummy va_dcl argument.
4670 For stdargs, we do want to skip the last named argument. */
4673 function_arg_advance (&next_cum, mode, type, 1);
4675 if (TARGET_64BIT_MS_ABI)
4676 setup_incoming_varargs_ms_64 (&next_cum);
4678 setup_incoming_varargs_64 (&next_cum);
4681 /* Implement va_start. */
4684 ix86_va_start (tree valist, rtx nextarg)
4686 HOST_WIDE_INT words, n_gpr, n_fpr;
4687 tree f_gpr, f_fpr, f_ovf, f_sav;
4688 tree gpr, fpr, ovf, sav, t;
4691 /* Only 64bit target needs something special. */
4692 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
4694 std_expand_builtin_va_start (valist, nextarg);
4698 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4699 f_fpr = TREE_CHAIN (f_gpr);
4700 f_ovf = TREE_CHAIN (f_fpr);
4701 f_sav = TREE_CHAIN (f_ovf);
4703 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4704 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
4705 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
4706 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
4707 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4709 /* Count number of gp and fp argument registers used. */
4710 words = current_function_args_info.words;
4711 n_gpr = current_function_args_info.regno;
4712 n_fpr = current_function_args_info.sse_regno;
4714 if (cfun->va_list_gpr_size)
4716 type = TREE_TYPE (gpr);
4717 t = build2 (GIMPLE_MODIFY_STMT, type, gpr,
4718 build_int_cst (type, n_gpr * 8));
4719 TREE_SIDE_EFFECTS (t) = 1;
4720 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4723 if (cfun->va_list_fpr_size)
4725 type = TREE_TYPE (fpr);
4726 t = build2 (GIMPLE_MODIFY_STMT, type, fpr,
4727 build_int_cst (type, n_fpr * 16 + 8*REGPARM_MAX));
4728 TREE_SIDE_EFFECTS (t) = 1;
4729 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4732 /* Find the overflow area. */
4733 type = TREE_TYPE (ovf);
4734 t = make_tree (type, virtual_incoming_args_rtx);
4736 t = build2 (PLUS_EXPR, type, t,
4737 build_int_cst (type, words * UNITS_PER_WORD));
4738 t = build2 (GIMPLE_MODIFY_STMT, type, ovf, t);
4739 TREE_SIDE_EFFECTS (t) = 1;
4740 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4742 if (cfun->va_list_gpr_size || cfun->va_list_fpr_size)
4744 /* Find the register save area.
4745 Prologue of the function save it right above stack frame. */
4746 type = TREE_TYPE (sav);
4747 t = make_tree (type, frame_pointer_rtx);
4748 t = build2 (GIMPLE_MODIFY_STMT, type, sav, t);
4749 TREE_SIDE_EFFECTS (t) = 1;
4750 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4754 /* Implement va_arg. */
4757 ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
4759 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
4760 tree f_gpr, f_fpr, f_ovf, f_sav;
4761 tree gpr, fpr, ovf, sav, t;
4763 tree lab_false, lab_over = NULL_TREE;
4768 enum machine_mode nat_mode;
4770 /* Only 64bit target needs something special. */
4771 if (!TARGET_64BIT || TARGET_64BIT_MS_ABI)
4772 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4774 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4775 f_fpr = TREE_CHAIN (f_gpr);
4776 f_ovf = TREE_CHAIN (f_fpr);
4777 f_sav = TREE_CHAIN (f_ovf);
4779 valist = build_va_arg_indirect_ref (valist);
4780 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
4781 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
4782 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
4783 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4785 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
4787 type = build_pointer_type (type);
4788 size = int_size_in_bytes (type);
4789 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4791 nat_mode = type_natural_mode (type);
4792 container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
4793 REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);
4795 /* Pull the value out of the saved registers. */
4797 addr = create_tmp_var (ptr_type_node, "addr");
4798 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
4802 int needed_intregs, needed_sseregs;
4804 tree int_addr, sse_addr;
4806 lab_false = create_artificial_label ();
4807 lab_over = create_artificial_label ();
4809 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
4811 need_temp = (!REG_P (container)
4812 && ((needed_intregs && TYPE_ALIGN (type) > 64)
4813 || TYPE_ALIGN (type) > 128));
4815 /* In case we are passing structure, verify that it is consecutive block
4816 on the register save area. If not we need to do moves. */
4817 if (!need_temp && !REG_P (container))
4819 /* Verify that all registers are strictly consecutive */
4820 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
4824 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
4826 rtx slot = XVECEXP (container, 0, i);
4827 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
4828 || INTVAL (XEXP (slot, 1)) != i * 16)
4836 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
4838 rtx slot = XVECEXP (container, 0, i);
4839 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
4840 || INTVAL (XEXP (slot, 1)) != i * 8)
4852 int_addr = create_tmp_var (ptr_type_node, "int_addr");
4853 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
4854 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
4855 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
4858 /* First ensure that we fit completely in registers. */
4861 t = build_int_cst (TREE_TYPE (gpr),
4862 (REGPARM_MAX - needed_intregs + 1) * 8);
4863 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
4864 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
4865 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
4866 gimplify_and_add (t, pre_p);
4870 t = build_int_cst (TREE_TYPE (fpr),
4871 (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
4873 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
4874 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
4875 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
4876 gimplify_and_add (t, pre_p);
4879 /* Compute index to start of area used for integer regs. */
4882 /* int_addr = gpr + sav; */
4883 t = fold_convert (ptr_type_node, gpr);
4884 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
4885 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, int_addr, t);
4886 gimplify_and_add (t, pre_p);
4890 /* sse_addr = fpr + sav; */
4891 t = fold_convert (ptr_type_node, fpr);
4892 t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
4893 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, sse_addr, t);
4894 gimplify_and_add (t, pre_p);
4899 tree temp = create_tmp_var (type, "va_arg_tmp");
4902 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
4903 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
4904 gimplify_and_add (t, pre_p);
4906 for (i = 0; i < XVECLEN (container, 0); i++)
4908 rtx slot = XVECEXP (container, 0, i);
4909 rtx reg = XEXP (slot, 0);
4910 enum machine_mode mode = GET_MODE (reg);
4911 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
4912 tree addr_type = build_pointer_type (piece_type);
4915 tree dest_addr, dest;
4917 if (SSE_REGNO_P (REGNO (reg)))
4919 src_addr = sse_addr;
4920 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
4924 src_addr = int_addr;
4925 src_offset = REGNO (reg) * 8;
4927 src_addr = fold_convert (addr_type, src_addr);
4928 src_addr = fold_build2 (PLUS_EXPR, addr_type, src_addr,
4929 size_int (src_offset));
4930 src = build_va_arg_indirect_ref (src_addr);
4932 dest_addr = fold_convert (addr_type, addr);
4933 dest_addr = fold_build2 (PLUS_EXPR, addr_type, dest_addr,
4934 size_int (INTVAL (XEXP (slot, 1))));
4935 dest = build_va_arg_indirect_ref (dest_addr);
4937 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, dest, src);
4938 gimplify_and_add (t, pre_p);
4944 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4945 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
4946 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr, t);
4947 gimplify_and_add (t, pre_p);
4951 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
4952 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
4953 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr, t);
4954 gimplify_and_add (t, pre_p);
4957 t = build1 (GOTO_EXPR, void_type_node, lab_over);
4958 gimplify_and_add (t, pre_p);
4960 t = build1 (LABEL_EXPR, void_type_node, lab_false);
4961 append_to_statement_list (t, pre_p);
4964 /* ... otherwise out of the overflow area. */
4966 /* Care for on-stack alignment if needed. */
4967 if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64
4968 || integer_zerop (TYPE_SIZE (type)))
4972 HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
4973 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), ovf,
4974 build_int_cst (TREE_TYPE (ovf), align - 1));
4975 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
4976 build_int_cst (TREE_TYPE (t), -align));
4978 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
4980 t2 = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
4981 gimplify_and_add (t2, pre_p);
4983 t = build2 (PLUS_EXPR, TREE_TYPE (t), t,
4984 build_int_cst (TREE_TYPE (t), rsize * UNITS_PER_WORD));
4985 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
4986 gimplify_and_add (t, pre_p);
4990 t = build1 (LABEL_EXPR, void_type_node, lab_over);
4991 append_to_statement_list (t, pre_p);
4994 ptrtype = build_pointer_type (type);
4995 addr = fold_convert (ptrtype, addr);
4998 addr = build_va_arg_indirect_ref (addr);
4999 return build_va_arg_indirect_ref (addr);
5002 /* Return nonzero if OPNUM's MEM should be matched
5003 in movabs* patterns. */
5006 ix86_check_movabs (rtx insn, int opnum)
5010 set = PATTERN (insn);
5011 if (GET_CODE (set) == PARALLEL)
5012 set = XVECEXP (set, 0, 0);
5013 gcc_assert (GET_CODE (set) == SET);
5014 mem = XEXP (set, opnum);
5015 while (GET_CODE (mem) == SUBREG)
5016 mem = SUBREG_REG (mem);
5017 gcc_assert (MEM_P (mem));
5018 return (volatile_ok || !MEM_VOLATILE_P (mem));
5021 /* Initialize the table of extra 80387 mathematical constants. */
5024 init_ext_80387_constants (void)
5026 static const char * cst[5] =
5028 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
5029 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
5030 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
5031 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
5032 "3.1415926535897932385128089594061862044", /* 4: fldpi */
5036 for (i = 0; i < 5; i++)
5038 real_from_string (&ext_80387_constants_table[i], cst[i]);
5039 /* Ensure each constant is rounded to XFmode precision. */
5040 real_convert (&ext_80387_constants_table[i],
5041 XFmode, &ext_80387_constants_table[i]);
5044 ext_80387_constants_init = 1;
5047 /* Return true if the constant is something that can be loaded with
5048 a special instruction. */
5051 standard_80387_constant_p (rtx x)
5053 enum machine_mode mode = GET_MODE (x);
5057 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
5060 if (x == CONST0_RTX (mode))
5062 if (x == CONST1_RTX (mode))
5065 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5067 /* For XFmode constants, try to find a special 80387 instruction when
5068 optimizing for size or on those CPUs that benefit from them. */
5070 && (optimize_size || TARGET_EXT_80387_CONSTANTS))
5074 if (! ext_80387_constants_init)
5075 init_ext_80387_constants ();
5077 for (i = 0; i < 5; i++)
5078 if (real_identical (&r, &ext_80387_constants_table[i]))
5082 /* Load of the constant -0.0 or -1.0 will be split as
5083 fldz;fchs or fld1;fchs sequence. */
5084 if (real_isnegzero (&r))
5086 if (real_identical (&r, &dconstm1))
5092 /* Return the opcode of the special instruction to be used to load
5096 standard_80387_constant_opcode (rtx x)
5098 switch (standard_80387_constant_p (x))
5122 /* Return the CONST_DOUBLE representing the 80387 constant that is
5123 loaded by the specified special instruction. The argument IDX
5124 matches the return value from standard_80387_constant_p. */
5127 standard_80387_constant_rtx (int idx)
5131 if (! ext_80387_constants_init)
5132 init_ext_80387_constants ();
5148 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
5152 /* Return 1 if mode is a valid mode for sse. */
5154 standard_sse_mode_p (enum machine_mode mode)
5171 /* Return 1 if X is FP constant we can load to SSE register w/o using memory.
5174 standard_sse_constant_p (rtx x)
5176 enum machine_mode mode = GET_MODE (x);
5178 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
5180 if (vector_all_ones_operand (x, mode)
5181 && standard_sse_mode_p (mode))
5182 return TARGET_SSE2 ? 2 : -1;
5187 /* Return the opcode of the special instruction to be used to load
5191 standard_sse_constant_opcode (rtx insn, rtx x)
5193 switch (standard_sse_constant_p (x))
5196 if (get_attr_mode (insn) == MODE_V4SF)
5197 return "xorps\t%0, %0";
5198 else if (get_attr_mode (insn) == MODE_V2DF)
5199 return "xorpd\t%0, %0";
5201 return "pxor\t%0, %0";
5203 return "pcmpeqd\t%0, %0";
5208 /* Returns 1 if OP contains a symbol reference */
5211 symbolic_reference_mentioned_p (rtx op)
5216 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
5219 fmt = GET_RTX_FORMAT (GET_CODE (op));
5220 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
5226 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
5227 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
5231 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
5238 /* Return 1 if it is appropriate to emit `ret' instructions in the
5239 body of a function. Do this only if the epilogue is simple, needing a
5240 couple of insns. Prior to reloading, we can't tell how many registers
5241 must be saved, so return 0 then. Return 0 if there is no frame
5242 marker to de-allocate. */
5245 ix86_can_use_return_insn_p (void)
5247 struct ix86_frame frame;
5249 if (! reload_completed || frame_pointer_needed)
5252 /* Don't allow more than 32 pop, since that's all we can do
5253 with one instruction. */
5254 if (current_function_pops_args
5255 && current_function_args_size >= 32768)
5258 ix86_compute_frame_layout (&frame);
5259 return frame.to_allocate == 0 && frame.nregs == 0;
5262 /* Value should be nonzero if functions must have frame pointers.
5263 Zero means the frame pointer need not be set up (and parms may
5264 be accessed via the stack pointer) in functions that seem suitable. */
5267 ix86_frame_pointer_required (void)
5269 /* If we accessed previous frames, then the generated code expects
5270 to be able to access the saved ebp value in our frame. */
5271 if (cfun->machine->accesses_prev_frame)
5274 /* Several x86 os'es need a frame pointer for other reasons,
5275 usually pertaining to setjmp. */
5276 if (SUBTARGET_FRAME_POINTER_REQUIRED)
5279 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
5280 the frame pointer by default. Turn it back on now if we've not
5281 got a leaf function. */
5282 if (TARGET_OMIT_LEAF_FRAME_POINTER
5283 && (!current_function_is_leaf
5284 || ix86_current_function_calls_tls_descriptor))
5287 if (current_function_profile)
5293 /* Record that the current function accesses previous call frames. */
5296 ix86_setup_frame_addresses (void)
5298 cfun->machine->accesses_prev_frame = 1;
5301 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
5302 # define USE_HIDDEN_LINKONCE 1
5304 # define USE_HIDDEN_LINKONCE 0
5307 static int pic_labels_used;
5309 /* Fills in the label name that should be used for a pc thunk for
5310 the given register. */
5313 get_pc_thunk_name (char name[32], unsigned int regno)
5315 gcc_assert (!TARGET_64BIT);
5317 if (USE_HIDDEN_LINKONCE)
5318 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
5320 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
5324 /* This function generates code for -fpic that loads %ebx with
5325 the return address of the caller and then returns. */
5328 ix86_file_end (void)
5333 for (regno = 0; regno < 8; ++regno)
5337 if (! ((pic_labels_used >> regno) & 1))
5340 get_pc_thunk_name (name, regno);
5345 switch_to_section (darwin_sections[text_coal_section]);
5346 fputs ("\t.weak_definition\t", asm_out_file);
5347 assemble_name (asm_out_file, name);
5348 fputs ("\n\t.private_extern\t", asm_out_file);
5349 assemble_name (asm_out_file, name);
5350 fputs ("\n", asm_out_file);
5351 ASM_OUTPUT_LABEL (asm_out_file, name);
5355 if (USE_HIDDEN_LINKONCE)
5359 decl = build_decl (FUNCTION_DECL, get_identifier (name),
5361 TREE_PUBLIC (decl) = 1;
5362 TREE_STATIC (decl) = 1;
5363 DECL_ONE_ONLY (decl) = 1;
5365 (*targetm.asm_out.unique_section) (decl, 0);
5366 switch_to_section (get_named_section (decl, NULL, 0));
5368 (*targetm.asm_out.globalize_label) (asm_out_file, name);
5369 fputs ("\t.hidden\t", asm_out_file);
5370 assemble_name (asm_out_file, name);
5371 fputc ('\n', asm_out_file);
5372 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
5376 switch_to_section (text_section);
5377 ASM_OUTPUT_LABEL (asm_out_file, name);
5380 xops[0] = gen_rtx_REG (SImode, regno);
5381 xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
5382 output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
5383 output_asm_insn ("ret", xops);
5386 if (NEED_INDICATE_EXEC_STACK)
5387 file_end_indicate_exec_stack ();
5390 /* Emit code for the SET_GOT patterns. */
5393 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
5399 if (TARGET_VXWORKS_RTP && flag_pic)
5401 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
5402 xops[2] = gen_rtx_MEM (Pmode,
5403 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
5404 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5406 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
5407 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
5408 an unadorned address. */
5409 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
5410 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
5411 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
5415 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
5417 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
5419 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
5422 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
5424 output_asm_insn ("call\t%a2", xops);
5427 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5428 is what will be referenced by the Mach-O PIC subsystem. */
5430 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5433 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5434 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
5437 output_asm_insn ("pop{l}\t%0", xops);
5442 get_pc_thunk_name (name, REGNO (dest));
5443 pic_labels_used |= 1 << REGNO (dest);
5445 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5446 xops[2] = gen_rtx_MEM (QImode, xops[2]);
5447 output_asm_insn ("call\t%X2", xops);
5448 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
5449 is what will be referenced by the Mach-O PIC subsystem. */
5452 ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
5454 targetm.asm_out.internal_label (asm_out_file, "L",
5455 CODE_LABEL_NUMBER (label));
5462 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
5463 output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
5465 output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
5470 /* Generate an "push" pattern for input ARG. */
5475 return gen_rtx_SET (VOIDmode,
5477 gen_rtx_PRE_DEC (Pmode,
5478 stack_pointer_rtx)),
5482 /* Return >= 0 if there is an unused call-clobbered register available
5483 for the entire function. */
5486 ix86_select_alt_pic_regnum (void)
5488 if (current_function_is_leaf && !current_function_profile
5489 && !ix86_current_function_calls_tls_descriptor)
5492 for (i = 2; i >= 0; --i)
5493 if (!regs_ever_live[i])
5497 return INVALID_REGNUM;
5500 /* Return 1 if we need to save REGNO. */
5502 ix86_save_reg (unsigned int regno, int maybe_eh_return)
5504 if (pic_offset_table_rtx
5505 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
5506 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
5507 || current_function_profile
5508 || current_function_calls_eh_return
5509 || current_function_uses_const_pool))
5511 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
5516 if (current_function_calls_eh_return && maybe_eh_return)
5521 unsigned test = EH_RETURN_DATA_REGNO (i);
5522 if (test == INVALID_REGNUM)
5529 if (cfun->machine->force_align_arg_pointer
5530 && regno == REGNO (cfun->machine->force_align_arg_pointer))
5533 return (regs_ever_live[regno]
5534 && !call_used_regs[regno]
5535 && !fixed_regs[regno]
5536 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
5539 /* Return number of registers to be saved on the stack. */
5542 ix86_nsaved_regs (void)
5547 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
5548 if (ix86_save_reg (regno, true))
5553 /* Return the offset between two registers, one to be eliminated, and the other
5554 its replacement, at the start of a routine. */
5557 ix86_initial_elimination_offset (int from, int to)
5559 struct ix86_frame frame;
5560 ix86_compute_frame_layout (&frame);
5562 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
5563 return frame.hard_frame_pointer_offset;
5564 else if (from == FRAME_POINTER_REGNUM
5565 && to == HARD_FRAME_POINTER_REGNUM)
5566 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
5569 gcc_assert (to == STACK_POINTER_REGNUM);
5571 if (from == ARG_POINTER_REGNUM)
5572 return frame.stack_pointer_offset;
5574 gcc_assert (from == FRAME_POINTER_REGNUM);
5575 return frame.stack_pointer_offset - frame.frame_pointer_offset;
5579 /* Fill structure ix86_frame about frame of currently computed function. */
5582 ix86_compute_frame_layout (struct ix86_frame *frame)
5584 HOST_WIDE_INT total_size;
5585 unsigned int stack_alignment_needed;
5586 HOST_WIDE_INT offset;
5587 unsigned int preferred_alignment;
5588 HOST_WIDE_INT size = get_frame_size ();
5590 frame->nregs = ix86_nsaved_regs ();
5593 stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
5594 preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;
5596 /* During reload iteration the amount of registers saved can change.
5597 Recompute the value as needed. Do not recompute when amount of registers
5598 didn't change as reload does multiple calls to the function and does not
5599 expect the decision to change within single iteration. */
5601 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
5603 int count = frame->nregs;
5605 cfun->machine->use_fast_prologue_epilogue_nregs = count;
5606 /* The fast prologue uses move instead of push to save registers. This
5607 is significantly longer, but also executes faster as modern hardware
5608 can execute the moves in parallel, but can't do that for push/pop.
5610 Be careful about choosing what prologue to emit: When function takes
5611 many instructions to execute we may use slow version as well as in
5612 case function is known to be outside hot spot (this is known with
5613 feedback only). Weight the size of function by number of registers
5614 to save as it is cheap to use one or two push instructions but very
5615 slow to use many of them. */
5617 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
5618 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
5619 || (flag_branch_probabilities
5620 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
5621 cfun->machine->use_fast_prologue_epilogue = false;
5623 cfun->machine->use_fast_prologue_epilogue
5624 = !expensive_function_p (count);
5626 if (TARGET_PROLOGUE_USING_MOVE
5627 && cfun->machine->use_fast_prologue_epilogue)
5628 frame->save_regs_using_mov = true;
5630 frame->save_regs_using_mov = false;
5633 /* Skip return address and saved base pointer. */
5634 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
5636 frame->hard_frame_pointer_offset = offset;
5638 /* Do some sanity checking of stack_alignment_needed and
5639 preferred_alignment, since i386 port is the only using those features
5640 that may break easily. */
5642 gcc_assert (!size || stack_alignment_needed);
5643 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
5644 gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
5645 gcc_assert (stack_alignment_needed
5646 <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT);
5648 if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
5649 stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;
5651 /* Register save area */
5652 offset += frame->nregs * UNITS_PER_WORD;
5655 if (ix86_save_varrargs_registers)
5657 offset += X86_64_VARARGS_SIZE;
5658 frame->va_arg_size = X86_64_VARARGS_SIZE;
5661 frame->va_arg_size = 0;
5663 /* Align start of frame for local function. */
5664 frame->padding1 = ((offset + stack_alignment_needed - 1)
5665 & -stack_alignment_needed) - offset;
5667 offset += frame->padding1;
5669 /* Frame pointer points here. */
5670 frame->frame_pointer_offset = offset;
5674 /* Add outgoing arguments area. Can be skipped if we eliminated
5675 all the function calls as dead code.
5676 Skipping is however impossible when function calls alloca. Alloca
5677 expander assumes that last current_function_outgoing_args_size
5678 of stack frame are unused. */
5679 if (ACCUMULATE_OUTGOING_ARGS
5680 && (!current_function_is_leaf || current_function_calls_alloca
5681 || ix86_current_function_calls_tls_descriptor))
5683 offset += current_function_outgoing_args_size;
5684 frame->outgoing_arguments_size = current_function_outgoing_args_size;
5687 frame->outgoing_arguments_size = 0;
5689 /* Align stack boundary. Only needed if we're calling another function
5691 if (!current_function_is_leaf || current_function_calls_alloca
5692 || ix86_current_function_calls_tls_descriptor)
5693 frame->padding2 = ((offset + preferred_alignment - 1)
5694 & -preferred_alignment) - offset;
5696 frame->padding2 = 0;
5698 offset += frame->padding2;
5700 /* We've reached end of stack frame. */
5701 frame->stack_pointer_offset = offset;
5703 /* Size prologue needs to allocate. */
5704 frame->to_allocate =
5705 (size + frame->padding1 + frame->padding2
5706 + frame->outgoing_arguments_size + frame->va_arg_size);
5708 if ((!frame->to_allocate && frame->nregs <= 1)
5709 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
5710 frame->save_regs_using_mov = false;
5712 if (TARGET_RED_ZONE && current_function_sp_is_unchanging
5713 && current_function_is_leaf
5714 && !ix86_current_function_calls_tls_descriptor)
5716 frame->red_zone_size = frame->to_allocate;
5717 if (frame->save_regs_using_mov)
5718 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
5719 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
5720 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
5723 frame->red_zone_size = 0;
5724 frame->to_allocate -= frame->red_zone_size;
5725 frame->stack_pointer_offset -= frame->red_zone_size;
5727 fprintf (stderr, "\n");
5728 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
5729 fprintf (stderr, "size: %ld\n", (long)size);
5730 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
5731 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
5732 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
5733 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
5734 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
5735 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
5736 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
5737 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
5738 (long)frame->hard_frame_pointer_offset);
5739 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
5740 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
5741 fprintf (stderr, "current_function_calls_alloca: %ld\n", (long)current_function_calls_alloca);
5742 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
5746 /* Emit code to save registers in the prologue. */
5749 ix86_emit_save_regs (void)
5754 for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; )
5755 if (ix86_save_reg (regno, true))
5757 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
5758 RTX_FRAME_RELATED_P (insn) = 1;
5762 /* Emit code to save registers using MOV insns. First register
5763 is restored from POINTER + OFFSET. */
5765 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
5770 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5771 if (ix86_save_reg (regno, true))
5773 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
5775 gen_rtx_REG (Pmode, regno));
5776 RTX_FRAME_RELATED_P (insn) = 1;
5777 offset += UNITS_PER_WORD;
5781 /* Expand prologue or epilogue stack adjustment.
5782 The pattern exist to put a dependency on all ebp-based memory accesses.
5783 STYLE should be negative if instructions should be marked as frame related,
5784 zero if %r11 register is live and cannot be freely used and positive
5788 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
5793 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
5794 else if (x86_64_immediate_operand (offset, DImode))
5795 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
5799 /* r11 is used by indirect sibcall return as well, set before the
5800 epilogue and used after the epilogue. ATM indirect sibcall
5801 shouldn't be used together with huge frame sizes in one
5802 function because of the frame_size check in sibcall.c. */
5804 r11 = gen_rtx_REG (DImode, R11_REG);
5805 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
5807 RTX_FRAME_RELATED_P (insn) = 1;
5808 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
5812 RTX_FRAME_RELATED_P (insn) = 1;
5815 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
5818 ix86_internal_arg_pointer (void)
5820 bool has_force_align_arg_pointer =
5821 (0 != lookup_attribute (ix86_force_align_arg_pointer_string,
5822 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))));
5823 if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN
5824 && DECL_NAME (current_function_decl)
5825 && MAIN_NAME_P (DECL_NAME (current_function_decl))
5826 && DECL_FILE_SCOPE_P (current_function_decl))
5827 || ix86_force_align_arg_pointer
5828 || has_force_align_arg_pointer)
5830 /* Nested functions can't realign the stack due to a register
5832 if (DECL_CONTEXT (current_function_decl)
5833 && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL)
5835 if (ix86_force_align_arg_pointer)
5836 warning (0, "-mstackrealign ignored for nested functions");
5837 if (has_force_align_arg_pointer)
5838 error ("%s not supported for nested functions",
5839 ix86_force_align_arg_pointer_string);
5840 return virtual_incoming_args_rtx;
5842 cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, 2);
5843 return copy_to_reg (cfun->machine->force_align_arg_pointer);
5846 return virtual_incoming_args_rtx;
5849 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
5850 This is called from dwarf2out.c to emit call frame instructions
5851 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
5853 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
5855 rtx unspec = SET_SRC (pattern);
5856 gcc_assert (GET_CODE (unspec) == UNSPEC);
5860 case UNSPEC_REG_SAVE:
5861 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
5862 SET_DEST (pattern));
5864 case UNSPEC_DEF_CFA:
5865 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
5866 INTVAL (XVECEXP (unspec, 0, 0)));
5873 /* Expand the prologue into a bunch of separate insns. */
5876 ix86_expand_prologue (void)
5880 struct ix86_frame frame;
5881 HOST_WIDE_INT allocate;
5883 ix86_compute_frame_layout (&frame);
5885 if (cfun->machine->force_align_arg_pointer)
5889 /* Grab the argument pointer. */
5890 x = plus_constant (stack_pointer_rtx, 4);
5891 y = cfun->machine->force_align_arg_pointer;
5892 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
5893 RTX_FRAME_RELATED_P (insn) = 1;
5895 /* The unwind info consists of two parts: install the fafp as the cfa,
5896 and record the fafp as the "save register" of the stack pointer.
5897 The later is there in order that the unwinder can see where it
5898 should restore the stack pointer across the and insn. */
5899 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA);
5900 x = gen_rtx_SET (VOIDmode, y, x);
5901 RTX_FRAME_RELATED_P (x) = 1;
5902 y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx),
5904 y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y);
5905 RTX_FRAME_RELATED_P (y) = 1;
5906 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y));
5907 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
5908 REG_NOTES (insn) = x;
5910 /* Align the stack. */
5911 emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx,
5914 /* And here we cheat like madmen with the unwind info. We force the
5915 cfa register back to sp+4, which is exactly what it was at the
5916 start of the function. Re-pushing the return address results in
5917 the return at the same spot relative to the cfa, and thus is
5918 correct wrt the unwind info. */
5919 x = cfun->machine->force_align_arg_pointer;
5920 x = gen_frame_mem (Pmode, plus_constant (x, -4));
5921 insn = emit_insn (gen_push (x));
5922 RTX_FRAME_RELATED_P (insn) = 1;
5925 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA);
5926 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
5927 x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL);
5928 REG_NOTES (insn) = x;
5931 /* Note: AT&T enter does NOT have reversed args. Enter is probably
5932 slower on all targets. Also sdb doesn't like it. */
5934 if (frame_pointer_needed)
5936 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
5937 RTX_FRAME_RELATED_P (insn) = 1;
5939 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
5940 RTX_FRAME_RELATED_P (insn) = 1;
5943 allocate = frame.to_allocate;
5945 if (!frame.save_regs_using_mov)
5946 ix86_emit_save_regs ();
5948 allocate += frame.nregs * UNITS_PER_WORD;
5950 /* When using red zone we may start register saving before allocating
5951 the stack frame saving one cycle of the prologue. */
5952 if (TARGET_RED_ZONE && frame.save_regs_using_mov)
5953 ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
5954 : stack_pointer_rtx,
5955 -frame.nregs * UNITS_PER_WORD);
5959 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
5960 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
5961 GEN_INT (-allocate), -1);
5964 /* Only valid for Win32. */
5965 rtx eax = gen_rtx_REG (Pmode, 0);
5969 gcc_assert (!TARGET_64BIT || TARGET_64BIT_MS_ABI);
5971 if (TARGET_64BIT_MS_ABI)
5974 eax_live = ix86_eax_live_at_start_p ();
5978 emit_insn (gen_push (eax));
5979 allocate -= UNITS_PER_WORD;
5982 emit_move_insn (eax, GEN_INT (allocate));
5985 insn = gen_allocate_stack_worker_64 (eax);
5987 insn = gen_allocate_stack_worker_32 (eax);
5988 insn = emit_insn (insn);
5989 RTX_FRAME_RELATED_P (insn) = 1;
5990 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
5991 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
5992 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
5993 t, REG_NOTES (insn));
5997 if (frame_pointer_needed)
5998 t = plus_constant (hard_frame_pointer_rtx,
6001 - frame.nregs * UNITS_PER_WORD);
6003 t = plus_constant (stack_pointer_rtx, allocate);
6004 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
6008 if (frame.save_regs_using_mov && !TARGET_RED_ZONE)
6010 if (!frame_pointer_needed || !frame.to_allocate)
6011 ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
6013 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
6014 -frame.nregs * UNITS_PER_WORD);
6017 pic_reg_used = false;
6018 if (pic_offset_table_rtx
6019 && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
6020 || current_function_profile))
6022 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
6024 if (alt_pic_reg_used != INVALID_REGNUM)
6025 REGNO (pic_offset_table_rtx) = alt_pic_reg_used;
6027 pic_reg_used = true;
6034 if (ix86_cmodel == CM_LARGE_PIC)
6036 rtx tmp_reg = gen_rtx_REG (DImode,
6037 FIRST_REX_INT_REG + 3 /* R11 */);
6038 rtx label = gen_label_rtx ();
6040 LABEL_PRESERVE_P (label) = 1;
6041 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
6042 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
6043 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, NULL);
6044 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
6045 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, NULL);
6046 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
6047 pic_offset_table_rtx, tmp_reg));
6050 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
6053 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
6055 /* Even with accurate pre-reload life analysis, we can wind up
6056 deleting all references to the pic register after reload.
6057 Consider if cross-jumping unifies two sides of a branch
6058 controlled by a comparison vs the only read from a global.
6059 In which case, allow the set_got to be deleted, though we're
6060 too late to do anything about the ebx save in the prologue. */
6061 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, NULL);
6064 /* Prevent function calls from be scheduled before the call to mcount.
6065 In the pic_reg_used case, make sure that the got load isn't deleted. */
6066 if (current_function_profile)
6067 emit_insn (gen_blockage (pic_reg_used ? pic_offset_table_rtx : const0_rtx));
6070 /* Emit code to restore saved registers using MOV insns. First register
6071 is restored from POINTER + OFFSET. */
6073 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
6074 int maybe_eh_return)
6077 rtx base_address = gen_rtx_MEM (Pmode, pointer);
6079 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6080 if (ix86_save_reg (regno, maybe_eh_return))
6082 /* Ensure that adjust_address won't be forced to produce pointer
6083 out of range allowed by x86-64 instruction set. */
6084 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
6088 r11 = gen_rtx_REG (DImode, R11_REG);
6089 emit_move_insn (r11, GEN_INT (offset));
6090 emit_insn (gen_adddi3 (r11, r11, pointer));
6091 base_address = gen_rtx_MEM (Pmode, r11);
6094 emit_move_insn (gen_rtx_REG (Pmode, regno),
6095 adjust_address (base_address, Pmode, offset));
6096 offset += UNITS_PER_WORD;
6100 /* Restore function stack, frame, and registers. */
6103 ix86_expand_epilogue (int style)
6106 int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
6107 struct ix86_frame frame;
6108 HOST_WIDE_INT offset;
6110 ix86_compute_frame_layout (&frame);
6112 /* Calculate start of saved registers relative to ebp. Special care
6113 must be taken for the normal return case of a function using
6114 eh_return: the eax and edx registers are marked as saved, but not
6115 restored along this path. */
6116 offset = frame.nregs;
6117 if (current_function_calls_eh_return && style != 2)
6119 offset *= -UNITS_PER_WORD;
6121 /* If we're only restoring one register and sp is not valid then
6122 using a move instruction to restore the register since it's
6123 less work than reloading sp and popping the register.
6125 The default code result in stack adjustment using add/lea instruction,
6126 while this code results in LEAVE instruction (or discrete equivalent),
6127 so it is profitable in some other cases as well. Especially when there
6128 are no registers to restore. We also use this code when TARGET_USE_LEAVE
6129 and there is exactly one register to pop. This heuristic may need some
6130 tuning in future. */
6131 if ((!sp_valid && frame.nregs <= 1)
6132 || (TARGET_EPILOGUE_USING_MOVE
6133 && cfun->machine->use_fast_prologue_epilogue
6134 && (frame.nregs > 1 || frame.to_allocate))
6135 || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
6136 || (frame_pointer_needed && TARGET_USE_LEAVE
6137 && cfun->machine->use_fast_prologue_epilogue
6138 && frame.nregs == 1)
6139 || current_function_calls_eh_return)
6141 /* Restore registers. We can use ebp or esp to address the memory
6142 locations. If both are available, default to ebp, since offsets
6143 are known to be small. Only exception is esp pointing directly to the
6144 end of block of saved registers, where we may simplify addressing
6147 if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
6148 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
6149 frame.to_allocate, style == 2);
6151 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
6152 offset, style == 2);
6154 /* eh_return epilogues need %ecx added to the stack pointer. */
6157 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
6159 if (frame_pointer_needed)
6161 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
6162 tmp = plus_constant (tmp, UNITS_PER_WORD);
6163 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
6165 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
6166 emit_move_insn (hard_frame_pointer_rtx, tmp);
6168 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
6173 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
6174 tmp = plus_constant (tmp, (frame.to_allocate
6175 + frame.nregs * UNITS_PER_WORD));
6176 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
6179 else if (!frame_pointer_needed)
6180 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6181 GEN_INT (frame.to_allocate
6182 + frame.nregs * UNITS_PER_WORD),
6184 /* If not an i386, mov & pop is faster than "leave". */
6185 else if (TARGET_USE_LEAVE || optimize_size
6186 || !cfun->machine->use_fast_prologue_epilogue)
6187 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6190 pro_epilogue_adjust_stack (stack_pointer_rtx,
6191 hard_frame_pointer_rtx,
6194 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6196 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6201 /* First step is to deallocate the stack frame so that we can
6202 pop the registers. */
6205 gcc_assert (frame_pointer_needed);
6206 pro_epilogue_adjust_stack (stack_pointer_rtx,
6207 hard_frame_pointer_rtx,
6208 GEN_INT (offset), style);
6210 else if (frame.to_allocate)
6211 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
6212 GEN_INT (frame.to_allocate), style);
6214 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
6215 if (ix86_save_reg (regno, false))
6218 emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
6220 emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
6222 if (frame_pointer_needed)
6224 /* Leave results in shorter dependency chains on CPUs that are
6225 able to grok it fast. */
6226 if (TARGET_USE_LEAVE)
6227 emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
6228 else if (TARGET_64BIT)
6229 emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
6231 emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
6235 if (cfun->machine->force_align_arg_pointer)
6237 emit_insn (gen_addsi3 (stack_pointer_rtx,
6238 cfun->machine->force_align_arg_pointer,
6242 /* Sibcall epilogues don't want a return instruction. */
6246 if (current_function_pops_args && current_function_args_size)
6248 rtx popc = GEN_INT (current_function_pops_args);
6250 /* i386 can only pop 64K bytes. If asked to pop more, pop
6251 return address, do explicit add, and jump indirectly to the
6254 if (current_function_pops_args >= 65536)
6256 rtx ecx = gen_rtx_REG (SImode, 2);
6258 /* There is no "pascal" calling convention in any 64bit ABI. */
6259 gcc_assert (!TARGET_64BIT);
6261 emit_insn (gen_popsi1 (ecx));
6262 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
6263 emit_jump_insn (gen_return_indirect_internal (ecx));
6266 emit_jump_insn (gen_return_pop_internal (popc));
6269 emit_jump_insn (gen_return_internal ());
6272 /* Reset from the function's potential modifications. */
6275 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6276 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6278 if (pic_offset_table_rtx)
6279 REGNO (pic_offset_table_rtx) = REAL_PIC_OFFSET_TABLE_REGNUM;
6281 /* Mach-O doesn't support labels at the end of objects, so if
6282 it looks like we might want one, insert a NOP. */
6284 rtx insn = get_last_insn ();
6287 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
6288 insn = PREV_INSN (insn);
6292 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
6293 fputs ("\tnop\n", file);
6299 /* Extract the parts of an RTL expression that is a valid memory address
6300 for an instruction. Return 0 if the structure of the address is
6301 grossly off. Return -1 if the address contains ASHIFT, so it is not
6302 strictly valid, but still used for computing length of lea instruction. */
6305 ix86_decompose_address (rtx addr, struct ix86_address *out)
6307 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
6308 rtx base_reg, index_reg;
6309 HOST_WIDE_INT scale = 1;
6310 rtx scale_rtx = NULL_RTX;
6312 enum ix86_address_seg seg = SEG_DEFAULT;
6314 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
6316 else if (GET_CODE (addr) == PLUS)
6326 addends[n++] = XEXP (op, 1);
6329 while (GET_CODE (op) == PLUS);
6334 for (i = n; i >= 0; --i)
6337 switch (GET_CODE (op))
6342 index = XEXP (op, 0);
6343 scale_rtx = XEXP (op, 1);
6347 if (XINT (op, 1) == UNSPEC_TP
6348 && TARGET_TLS_DIRECT_SEG_REFS
6349 && seg == SEG_DEFAULT)
6350 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
6379 else if (GET_CODE (addr) == MULT)
6381 index = XEXP (addr, 0); /* index*scale */
6382 scale_rtx = XEXP (addr, 1);
6384 else if (GET_CODE (addr) == ASHIFT)
6388 /* We're called for lea too, which implements ashift on occasion. */
6389 index = XEXP (addr, 0);
6390 tmp = XEXP (addr, 1);
6391 if (!CONST_INT_P (tmp))
6393 scale = INTVAL (tmp);
6394 if ((unsigned HOST_WIDE_INT) scale > 3)
6400 disp = addr; /* displacement */
6402 /* Extract the integral value of scale. */
6405 if (!CONST_INT_P (scale_rtx))
6407 scale = INTVAL (scale_rtx);
6410 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
6411 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
6413 /* Allow arg pointer and stack pointer as index if there is not scaling. */
6414 if (base_reg && index_reg && scale == 1
6415 && (index_reg == arg_pointer_rtx
6416 || index_reg == frame_pointer_rtx
6417 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
6420 tmp = base, base = index, index = tmp;
6421 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
6424 /* Special case: %ebp cannot be encoded as a base without a displacement. */
6425 if ((base_reg == hard_frame_pointer_rtx
6426 || base_reg == frame_pointer_rtx
6427 || base_reg == arg_pointer_rtx) && !disp)
6430 /* Special case: on K6, [%esi] makes the instruction vector decoded.
6431 Avoid this by transforming to [%esi+0]. */
6432 if (ix86_tune == PROCESSOR_K6 && !optimize_size
6433 && base_reg && !index_reg && !disp
6435 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
6438 /* Special case: encode reg+reg instead of reg*2. */
6439 if (!base && index && scale && scale == 2)
6440 base = index, base_reg = index_reg, scale = 1;
6442 /* Special case: scaling cannot be encoded without base or displacement. */
6443 if (!base && !disp && index && scale != 1)
6455 /* Return cost of the memory address x.
6456 For i386, it is better to use a complex address than let gcc copy
6457 the address into a reg and make a new pseudo. But not if the address
6458 requires to two regs - that would mean more pseudos with longer
6461 ix86_address_cost (rtx x)
6463 struct ix86_address parts;
6465 int ok = ix86_decompose_address (x, &parts);
6469 if (parts.base && GET_CODE (parts.base) == SUBREG)
6470 parts.base = SUBREG_REG (parts.base);
6471 if (parts.index && GET_CODE (parts.index) == SUBREG)
6472 parts.index = SUBREG_REG (parts.index);
6474 /* More complex memory references are better. */
6475 if (parts.disp && parts.disp != const0_rtx)
6477 if (parts.seg != SEG_DEFAULT)
6480 /* Attempt to minimize number of registers in the address. */
6482 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
6484 && (!REG_P (parts.index)
6485 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
6489 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
6491 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
6492 && parts.base != parts.index)
6495 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
6496 since it's predecode logic can't detect the length of instructions
6497 and it degenerates to vector decoded. Increase cost of such
6498 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
6499 to split such addresses or even refuse such addresses at all.
6501 Following addressing modes are affected:
6506 The first and last case may be avoidable by explicitly coding the zero in
6507 memory address, but I don't have AMD-K6 machine handy to check this
6511 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
6512 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
6513 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
6519 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
6520 this is used for to form addresses to local data when -fPIC is in
6524 darwin_local_data_pic (rtx disp)
6526 if (GET_CODE (disp) == MINUS)
6528 if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
6529 || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
6530 if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
6532 const char *sym_name = XSTR (XEXP (disp, 1), 0);
6533 if (! strcmp (sym_name, "<pic base>"))
6541 /* Determine if a given RTX is a valid constant. We already know this
6542 satisfies CONSTANT_P. */
6545 legitimate_constant_p (rtx x)
6547 switch (GET_CODE (x))
6552 if (GET_CODE (x) == PLUS)
6554 if (!CONST_INT_P (XEXP (x, 1)))
6559 if (TARGET_MACHO && darwin_local_data_pic (x))
6562 /* Only some unspecs are valid as "constants". */
6563 if (GET_CODE (x) == UNSPEC)
6564 switch (XINT (x, 1))
6569 return TARGET_64BIT;
6572 x = XVECEXP (x, 0, 0);
6573 return (GET_CODE (x) == SYMBOL_REF
6574 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
6576 x = XVECEXP (x, 0, 0);
6577 return (GET_CODE (x) == SYMBOL_REF
6578 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
6583 /* We must have drilled down to a symbol. */
6584 if (GET_CODE (x) == LABEL_REF)
6586 if (GET_CODE (x) != SYMBOL_REF)
6591 /* TLS symbols are never valid. */
6592 if (SYMBOL_REF_TLS_MODEL (x))
6595 /* DLLIMPORT symbols are never valid. */
6596 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
6597 && SYMBOL_REF_DLLIMPORT_P (x))
6602 if (GET_MODE (x) == TImode
6603 && x != CONST0_RTX (TImode)
6609 if (x == CONST0_RTX (GET_MODE (x)))
6617 /* Otherwise we handle everything else in the move patterns. */
6621 /* Determine if it's legal to put X into the constant pool. This
6622 is not possible for the address of thread-local symbols, which
6623 is checked above. */
6626 ix86_cannot_force_const_mem (rtx x)
6628 /* We can always put integral constants and vectors in memory. */
6629 switch (GET_CODE (x))
6639 return !legitimate_constant_p (x);
6642 /* Determine if a given RTX is a valid constant address. */
6645 constant_address_p (rtx x)
6647 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
6650 /* Nonzero if the constant value X is a legitimate general operand
6651 when generating PIC code. It is given that flag_pic is on and
6652 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
6655 legitimate_pic_operand_p (rtx x)
6659 switch (GET_CODE (x))
6662 inner = XEXP (x, 0);
6663 if (GET_CODE (inner) == PLUS
6664 && CONST_INT_P (XEXP (inner, 1)))
6665 inner = XEXP (inner, 0);
6667 /* Only some unspecs are valid as "constants". */
6668 if (GET_CODE (inner) == UNSPEC)
6669 switch (XINT (inner, 1))
6674 return TARGET_64BIT;
6676 x = XVECEXP (inner, 0, 0);
6677 return (GET_CODE (x) == SYMBOL_REF
6678 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
6686 return legitimate_pic_address_disp_p (x);
6693 /* Determine if a given CONST RTX is a valid memory displacement
6697 legitimate_pic_address_disp_p (rtx disp)
6701 /* In 64bit mode we can allow direct addresses of symbols and labels
6702 when they are not dynamic symbols. */
6705 rtx op0 = disp, op1;
6707 switch (GET_CODE (disp))
6713 if (GET_CODE (XEXP (disp, 0)) != PLUS)
6715 op0 = XEXP (XEXP (disp, 0), 0);
6716 op1 = XEXP (XEXP (disp, 0), 1);
6717 if (!CONST_INT_P (op1)
6718 || INTVAL (op1) >= 16*1024*1024
6719 || INTVAL (op1) < -16*1024*1024)
6721 if (GET_CODE (op0) == LABEL_REF)
6723 if (GET_CODE (op0) != SYMBOL_REF)
6728 /* TLS references should always be enclosed in UNSPEC. */
6729 if (SYMBOL_REF_TLS_MODEL (op0))
6731 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
6732 && ix86_cmodel != CM_LARGE_PIC)
6740 if (GET_CODE (disp) != CONST)
6742 disp = XEXP (disp, 0);
6746 /* We are unsafe to allow PLUS expressions. This limit allowed distance
6747 of GOT tables. We should not need these anyway. */
6748 if (GET_CODE (disp) != UNSPEC
6749 || (XINT (disp, 1) != UNSPEC_GOTPCREL
6750 && XINT (disp, 1) != UNSPEC_GOTOFF
6751 && XINT (disp, 1) != UNSPEC_PLTOFF))
6754 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
6755 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
6761 if (GET_CODE (disp) == PLUS)
6763 if (!CONST_INT_P (XEXP (disp, 1)))
6765 disp = XEXP (disp, 0);
6769 if (TARGET_MACHO && darwin_local_data_pic (disp))
6772 if (GET_CODE (disp) != UNSPEC)
6775 switch (XINT (disp, 1))
6780 /* We need to check for both symbols and labels because VxWorks loads
6781 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
6783 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
6784 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
6786 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
6787 While ABI specify also 32bit relocation but we don't produce it in
6788 small PIC model at all. */
6789 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
6790 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
6792 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
6794 case UNSPEC_GOTTPOFF:
6795 case UNSPEC_GOTNTPOFF:
6796 case UNSPEC_INDNTPOFF:
6799 disp = XVECEXP (disp, 0, 0);
6800 return (GET_CODE (disp) == SYMBOL_REF
6801 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
6803 disp = XVECEXP (disp, 0, 0);
6804 return (GET_CODE (disp) == SYMBOL_REF
6805 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
6807 disp = XVECEXP (disp, 0, 0);
6808 return (GET_CODE (disp) == SYMBOL_REF
6809 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
6815 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
6816 memory address for an instruction. The MODE argument is the machine mode
6817 for the MEM expression that wants to use this address.
6819 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
6820 convert common non-canonical forms to canonical form so that they will
6824 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
6825 rtx addr, int strict)
6827 struct ix86_address parts;
6828 rtx base, index, disp;
6829 HOST_WIDE_INT scale;
6830 const char *reason = NULL;
6831 rtx reason_rtx = NULL_RTX;
6833 if (ix86_decompose_address (addr, &parts) <= 0)
6835 reason = "decomposition failed";
6840 index = parts.index;
6842 scale = parts.scale;
6844 /* Validate base register.
6846 Don't allow SUBREG's that span more than a word here. It can lead to spill
6847 failures when the base is one word out of a two word structure, which is
6848 represented internally as a DImode int. */
6857 else if (GET_CODE (base) == SUBREG
6858 && REG_P (SUBREG_REG (base))
6859 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
6861 reg = SUBREG_REG (base);
6864 reason = "base is not a register";
6868 if (GET_MODE (base) != Pmode)
6870 reason = "base is not in Pmode";
6874 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
6875 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
6877 reason = "base is not valid";
6882 /* Validate index register.
6884 Don't allow SUBREG's that span more than a word here -- same as above. */
6893 else if (GET_CODE (index) == SUBREG
6894 && REG_P (SUBREG_REG (index))
6895 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
6897 reg = SUBREG_REG (index);
6900 reason = "index is not a register";
6904 if (GET_MODE (index) != Pmode)
6906 reason = "index is not in Pmode";
6910 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
6911 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
6913 reason = "index is not valid";
6918 /* Validate scale factor. */
6921 reason_rtx = GEN_INT (scale);
6924 reason = "scale without index";
6928 if (scale != 2 && scale != 4 && scale != 8)
6930 reason = "scale is not a valid multiplier";
6935 /* Validate displacement. */
6940 if (GET_CODE (disp) == CONST
6941 && GET_CODE (XEXP (disp, 0)) == UNSPEC)
6942 switch (XINT (XEXP (disp, 0), 1))
6944 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
6945 used. While ABI specify also 32bit relocations, we don't produce
6946 them at all and use IP relative instead. */
6949 gcc_assert (flag_pic);
6951 goto is_legitimate_pic;
6952 reason = "64bit address unspec";
6955 case UNSPEC_GOTPCREL:
6956 gcc_assert (flag_pic);
6957 goto is_legitimate_pic;
6959 case UNSPEC_GOTTPOFF:
6960 case UNSPEC_GOTNTPOFF:
6961 case UNSPEC_INDNTPOFF:
6967 reason = "invalid address unspec";
6971 else if (SYMBOLIC_CONST (disp)
6975 && MACHOPIC_INDIRECT
6976 && !machopic_operand_p (disp)
6982 if (TARGET_64BIT && (index || base))
6984 /* foo@dtpoff(%rX) is ok. */
6985 if (GET_CODE (disp) != CONST
6986 || GET_CODE (XEXP (disp, 0)) != PLUS
6987 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
6988 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
6989 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
6990 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
6992 reason = "non-constant pic memory reference";
6996 else if (! legitimate_pic_address_disp_p (disp))
6998 reason = "displacement is an invalid pic construct";
7002 /* This code used to verify that a symbolic pic displacement
7003 includes the pic_offset_table_rtx register.
7005 While this is good idea, unfortunately these constructs may
7006 be created by "adds using lea" optimization for incorrect
7015 This code is nonsensical, but results in addressing
7016 GOT table with pic_offset_table_rtx base. We can't
7017 just refuse it easily, since it gets matched by
7018 "addsi3" pattern, that later gets split to lea in the
7019 case output register differs from input. While this
7020 can be handled by separate addsi pattern for this case
7021 that never results in lea, this seems to be easier and
7022 correct fix for crash to disable this test. */
7024 else if (GET_CODE (disp) != LABEL_REF
7025 && !CONST_INT_P (disp)
7026 && (GET_CODE (disp) != CONST
7027 || !legitimate_constant_p (disp))
7028 && (GET_CODE (disp) != SYMBOL_REF
7029 || !legitimate_constant_p (disp)))
7031 reason = "displacement is not constant";
7034 else if (TARGET_64BIT
7035 && !x86_64_immediate_operand (disp, VOIDmode))
7037 reason = "displacement is out of range";
7042 /* Everything looks valid. */
7049 /* Return a unique alias set for the GOT. */
7051 static HOST_WIDE_INT
7052 ix86_GOT_alias_set (void)
7054 static HOST_WIDE_INT set = -1;
7056 set = new_alias_set ();
7060 /* Return a legitimate reference for ORIG (an address) using the
7061 register REG. If REG is 0, a new pseudo is generated.
7063 There are two types of references that must be handled:
7065 1. Global data references must load the address from the GOT, via
7066 the PIC reg. An insn is emitted to do this load, and the reg is
7069 2. Static data references, constant pool addresses, and code labels
7070 compute the address as an offset from the GOT, whose base is in
7071 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
7072 differentiate them from global data objects. The returned
7073 address is the PIC reg + an unspec constant.
7075 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
7076 reg also appears in the address. */
7079 legitimize_pic_address (rtx orig, rtx reg)
7086 if (TARGET_MACHO && !TARGET_64BIT)
7089 reg = gen_reg_rtx (Pmode);
7090 /* Use the generic Mach-O PIC machinery. */
7091 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
7095 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
7097 else if (TARGET_64BIT
7098 && ix86_cmodel != CM_SMALL_PIC
7099 && gotoff_operand (addr, Pmode))
7102 /* This symbol may be referenced via a displacement from the PIC
7103 base address (@GOTOFF). */
7105 if (reload_in_progress)
7106 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
7107 if (GET_CODE (addr) == CONST)
7108 addr = XEXP (addr, 0);
7109 if (GET_CODE (addr) == PLUS)
7111 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7113 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
7116 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7117 new = gen_rtx_CONST (Pmode, new);
7119 tmpreg = gen_reg_rtx (Pmode);
7122 emit_move_insn (tmpreg, new);
7126 new = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
7127 tmpreg, 1, OPTAB_DIRECT);
7130 else new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
7132 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
7134 /* This symbol may be referenced via a displacement from the PIC
7135 base address (@GOTOFF). */
7137 if (reload_in_progress)
7138 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
7139 if (GET_CODE (addr) == CONST)
7140 addr = XEXP (addr, 0);
7141 if (GET_CODE (addr) == PLUS)
7143 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
7145 new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
7148 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
7149 new = gen_rtx_CONST (Pmode, new);
7150 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
7154 emit_move_insn (reg, new);
7158 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
7159 /* We can't use @GOTOFF for text labels on VxWorks;
7160 see gotoff_operand. */
7161 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
7163 /* Given that we've already handled dllimport variables separately
7164 in legitimize_address, and all other variables should satisfy
7165 legitimate_pic_address_disp_p, we should never arrive here. */
7166 gcc_assert (!TARGET_64BIT_MS_ABI);
7168 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
7170 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
7171 new = gen_rtx_CONST (Pmode, new);
7172 new = gen_const_mem (Pmode, new);
7173 set_mem_alias_set (new, ix86_GOT_alias_set ());
7176 reg = gen_reg_rtx (Pmode);
7177 /* Use directly gen_movsi, otherwise the address is loaded
7178 into register for CSE. We don't want to CSE this addresses,
7179 instead we CSE addresses from the GOT table, so skip this. */
7180 emit_insn (gen_movsi (reg, new));
7185 /* This symbol must be referenced via a load from the
7186 Global Offset Table (@GOT). */
7188 if (reload_in_progress)
7189 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
7190 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
7191 new = gen_rtx_CONST (Pmode, new);
7193 new = force_reg (Pmode, new);
7194 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
7195 new = gen_const_mem (Pmode, new);
7196 set_mem_alias_set (new, ix86_GOT_alias_set ());
7199 reg = gen_reg_rtx (Pmode);
7200 emit_move_insn (reg, new);
7206 if (CONST_INT_P (addr)
7207 && !x86_64_immediate_operand (addr, VOIDmode))
7211 emit_move_insn (reg, addr);
7215 new = force_reg (Pmode, addr);
7217 else if (GET_CODE (addr) == CONST)
7219 addr = XEXP (addr, 0);
7221 /* We must match stuff we generate before. Assume the only
7222 unspecs that can get here are ours. Not that we could do
7223 anything with them anyway.... */
7224 if (GET_CODE (addr) == UNSPEC
7225 || (GET_CODE (addr) == PLUS
7226 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
7228 gcc_assert (GET_CODE (addr) == PLUS);
7230 if (GET_CODE (addr) == PLUS)
7232 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
7234 /* Check first to see if this is a constant offset from a @GOTOFF
7235 symbol reference. */
7236 if (gotoff_operand (op0, Pmode)
7237 && CONST_INT_P (op1))
7241 if (reload_in_progress)
7242 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
7243 new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
7245 new = gen_rtx_PLUS (Pmode, new, op1);
7246 new = gen_rtx_CONST (Pmode, new);
7247 new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
7251 emit_move_insn (reg, new);
7257 if (INTVAL (op1) < -16*1024*1024
7258 || INTVAL (op1) >= 16*1024*1024)
7260 if (!x86_64_immediate_operand (op1, Pmode))
7261 op1 = force_reg (Pmode, op1);
7262 new = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
7268 base = legitimize_pic_address (XEXP (addr, 0), reg);
7269 new = legitimize_pic_address (XEXP (addr, 1),
7270 base == reg ? NULL_RTX : reg);
7272 if (CONST_INT_P (new))
7273 new = plus_constant (base, INTVAL (new));
7276 if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
7278 base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
7279 new = XEXP (new, 1);
7281 new = gen_rtx_PLUS (Pmode, base, new);
7289 /* Load the thread pointer. If TO_REG is true, force it into a register. */
7292 get_thread_pointer (int to_reg)
7296 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
7300 reg = gen_reg_rtx (Pmode);
7301 insn = gen_rtx_SET (VOIDmode, reg, tp);
7302 insn = emit_insn (insn);
7307 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
7308 false if we expect this to be used for a memory address and true if
7309 we expect to load the address into a register. */
7312 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
7314 rtx dest, base, off, pic, tp;
7319 case TLS_MODEL_GLOBAL_DYNAMIC:
7320 dest = gen_reg_rtx (Pmode);
7321 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7323 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7325 rtx rax = gen_rtx_REG (Pmode, 0), insns;
7328 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
7329 insns = get_insns ();
7332 CONST_OR_PURE_CALL_P (insns) = 1;
7333 emit_libcall_block (insns, dest, rax, x);
7335 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7336 emit_insn (gen_tls_global_dynamic_64 (dest, x));
7338 emit_insn (gen_tls_global_dynamic_32 (dest, x));
7340 if (TARGET_GNU2_TLS)
7342 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
7344 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7348 case TLS_MODEL_LOCAL_DYNAMIC:
7349 base = gen_reg_rtx (Pmode);
7350 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
7352 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
7354 rtx rax = gen_rtx_REG (Pmode, 0), insns, note;
7357 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
7358 insns = get_insns ();
7361 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
7362 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
7363 CONST_OR_PURE_CALL_P (insns) = 1;
7364 emit_libcall_block (insns, base, rax, note);
7366 else if (TARGET_64BIT && TARGET_GNU2_TLS)
7367 emit_insn (gen_tls_local_dynamic_base_64 (base));
7369 emit_insn (gen_tls_local_dynamic_base_32 (base));
7371 if (TARGET_GNU2_TLS)
7373 rtx x = ix86_tls_module_base ();
7375 set_unique_reg_note (get_last_insn (), REG_EQUIV,
7376 gen_rtx_MINUS (Pmode, x, tp));
7379 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
7380 off = gen_rtx_CONST (Pmode, off);
7382 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
7384 if (TARGET_GNU2_TLS)
7386 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
7388 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
7393 case TLS_MODEL_INITIAL_EXEC:
7397 type = UNSPEC_GOTNTPOFF;
7401 if (reload_in_progress)
7402 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
7403 pic = pic_offset_table_rtx;
7404 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
7406 else if (!TARGET_ANY_GNU_TLS)
7408 pic = gen_reg_rtx (Pmode);
7409 emit_insn (gen_set_got (pic));
7410 type = UNSPEC_GOTTPOFF;
7415 type = UNSPEC_INDNTPOFF;
7418 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
7419 off = gen_rtx_CONST (Pmode, off);
7421 off = gen_rtx_PLUS (Pmode, pic, off);
7422 off = gen_const_mem (Pmode, off);
7423 set_mem_alias_set (off, ix86_GOT_alias_set ());
7425 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7427 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7428 off = force_reg (Pmode, off);
7429 return gen_rtx_PLUS (Pmode, base, off);
7433 base = get_thread_pointer (true);
7434 dest = gen_reg_rtx (Pmode);
7435 emit_insn (gen_subsi3 (dest, base, off));
7439 case TLS_MODEL_LOCAL_EXEC:
7440 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
7441 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7442 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
7443 off = gen_rtx_CONST (Pmode, off);
7445 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
7447 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
7448 return gen_rtx_PLUS (Pmode, base, off);
7452 base = get_thread_pointer (true);
7453 dest = gen_reg_rtx (Pmode);
7454 emit_insn (gen_subsi3 (dest, base, off));
7465 /* Create or return the unique __imp_DECL dllimport symbol corresponding
7468 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
7469 htab_t dllimport_map;
7472 get_dllimport_decl (tree decl)
7474 struct tree_map *h, in;
7478 size_t namelen, prefixlen;
7484 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
7486 in.hash = htab_hash_pointer (decl);
7487 in.base.from = decl;
7488 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
7493 *loc = h = ggc_alloc (sizeof (struct tree_map));
7495 h->base.from = decl;
7496 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
7497 DECL_ARTIFICIAL (to) = 1;
7498 DECL_IGNORED_P (to) = 1;
7499 DECL_EXTERNAL (to) = 1;
7500 TREE_READONLY (to) = 1;
7502 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
7503 name = targetm.strip_name_encoding (name);
7504 if (name[0] == FASTCALL_PREFIX)
7510 prefix = "*__imp__";
7512 namelen = strlen (name);
7513 prefixlen = strlen (prefix);
7514 imp_name = alloca (namelen + prefixlen + 1);
7515 memcpy (imp_name, prefix, prefixlen);
7516 memcpy (imp_name + prefixlen, name, namelen + 1);
7518 name = ggc_alloc_string (imp_name, namelen + prefixlen);
7519 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
7520 SET_SYMBOL_REF_DECL (rtl, to);
7521 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
7523 rtl = gen_const_mem (Pmode, rtl);
7524 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
7526 SET_DECL_RTL (to, rtl);
7531 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
7532 true if we require the result be a register. */
7535 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
7540 gcc_assert (SYMBOL_REF_DECL (symbol));
7541 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
7543 x = DECL_RTL (imp_decl);
7545 x = force_reg (Pmode, x);
7549 /* Try machine-dependent ways of modifying an illegitimate address
7550 to be legitimate. If we find one, return the new, valid address.
7551 This macro is used in only one place: `memory_address' in explow.c.
7553 OLDX is the address as it was before break_out_memory_refs was called.
7554 In some cases it is useful to look at this to decide what needs to be done.
7556 MODE and WIN are passed so that this macro can use
7557 GO_IF_LEGITIMATE_ADDRESS.
7559 It is always safe for this macro to do nothing. It exists to recognize
7560 opportunities to optimize the output.
7562 For the 80386, we handle X+REG by loading X into a register R and
7563 using R+REG. R will go in a general reg and indexing will be used.
7564 However, if REG is a broken-out memory address or multiplication,
7565 nothing needs to be done because REG can certainly go in a general reg.
7567 When -fpic is used, special handling is needed for symbolic references.
7568 See comments by legitimize_pic_address in i386.c for details. */
7571 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
7576 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
7578 return legitimize_tls_address (x, log, false);
7579 if (GET_CODE (x) == CONST
7580 && GET_CODE (XEXP (x, 0)) == PLUS
7581 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
7582 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
7584 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0), log, false);
7585 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
7588 if (flag_pic && SYMBOLIC_CONST (x))
7589 return legitimize_pic_address (x, 0);
7591 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
7593 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
7594 return legitimize_dllimport_symbol (x, true);
7595 if (GET_CODE (x) == CONST
7596 && GET_CODE (XEXP (x, 0)) == PLUS
7597 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
7598 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
7600 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
7601 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
7605 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
7606 if (GET_CODE (x) == ASHIFT
7607 && CONST_INT_P (XEXP (x, 1))
7608 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
7611 log = INTVAL (XEXP (x, 1));
7612 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
7613 GEN_INT (1 << log));
7616 if (GET_CODE (x) == PLUS)
7618 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
7620 if (GET_CODE (XEXP (x, 0)) == ASHIFT
7621 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7622 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
7625 log = INTVAL (XEXP (XEXP (x, 0), 1));
7626 XEXP (x, 0) = gen_rtx_MULT (Pmode,
7627 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
7628 GEN_INT (1 << log));
7631 if (GET_CODE (XEXP (x, 1)) == ASHIFT
7632 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
7633 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
7636 log = INTVAL (XEXP (XEXP (x, 1), 1));
7637 XEXP (x, 1) = gen_rtx_MULT (Pmode,
7638 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
7639 GEN_INT (1 << log));
7642 /* Put multiply first if it isn't already. */
7643 if (GET_CODE (XEXP (x, 1)) == MULT)
7645 rtx tmp = XEXP (x, 0);
7646 XEXP (x, 0) = XEXP (x, 1);
7651 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
7652 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
7653 created by virtual register instantiation, register elimination, and
7654 similar optimizations. */
7655 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
7658 x = gen_rtx_PLUS (Pmode,
7659 gen_rtx_PLUS (Pmode, XEXP (x, 0),
7660 XEXP (XEXP (x, 1), 0)),
7661 XEXP (XEXP (x, 1), 1));
7665 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
7666 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
7667 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
7668 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
7669 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
7670 && CONSTANT_P (XEXP (x, 1)))
7673 rtx other = NULL_RTX;
7675 if (CONST_INT_P (XEXP (x, 1)))
7677 constant = XEXP (x, 1);
7678 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
7680 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
7682 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
7683 other = XEXP (x, 1);
7691 x = gen_rtx_PLUS (Pmode,
7692 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
7693 XEXP (XEXP (XEXP (x, 0), 1), 0)),
7694 plus_constant (other, INTVAL (constant)));
7698 if (changed && legitimate_address_p (mode, x, FALSE))
7701 if (GET_CODE (XEXP (x, 0)) == MULT)
7704 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
7707 if (GET_CODE (XEXP (x, 1)) == MULT)
7710 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
7714 && REG_P (XEXP (x, 1))
7715 && REG_P (XEXP (x, 0)))
7718 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
7721 x = legitimize_pic_address (x, 0);
7724 if (changed && legitimate_address_p (mode, x, FALSE))
7727 if (REG_P (XEXP (x, 0)))
7729 rtx temp = gen_reg_rtx (Pmode);
7730 rtx val = force_operand (XEXP (x, 1), temp);
7732 emit_move_insn (temp, val);
7738 else if (REG_P (XEXP (x, 1)))
7740 rtx temp = gen_reg_rtx (Pmode);
7741 rtx val = force_operand (XEXP (x, 0), temp);
7743 emit_move_insn (temp, val);
7753 /* Print an integer constant expression in assembler syntax. Addition
7754 and subtraction are the only arithmetic that may appear in these
7755 expressions. FILE is the stdio stream to write to, X is the rtx, and
7756 CODE is the operand print code from the output string. */
7759 output_pic_addr_const (FILE *file, rtx x, int code)
7763 switch (GET_CODE (x))
7766 gcc_assert (flag_pic);
7771 if (! TARGET_MACHO || TARGET_64BIT)
7772 output_addr_const (file, x);
7775 const char *name = XSTR (x, 0);
7777 /* Mark the decl as referenced so that cgraph will
7778 output the function. */
7779 if (SYMBOL_REF_DECL (x))
7780 mark_decl_referenced (SYMBOL_REF_DECL (x));
7783 if (MACHOPIC_INDIRECT
7784 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
7785 name = machopic_indirection_name (x, /*stub_p=*/true);
7787 assemble_name (file, name);
7789 if (!TARGET_MACHO && !TARGET_64BIT_MS_ABI
7790 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
7791 fputs ("@PLT", file);
7798 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
7799 assemble_name (asm_out_file, buf);
7803 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
7807 /* This used to output parentheses around the expression,
7808 but that does not work on the 386 (either ATT or BSD assembler). */
7809 output_pic_addr_const (file, XEXP (x, 0), code);
7813 if (GET_MODE (x) == VOIDmode)
7815 /* We can use %d if the number is <32 bits and positive. */
7816 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
7817 fprintf (file, "0x%lx%08lx",
7818 (unsigned long) CONST_DOUBLE_HIGH (x),
7819 (unsigned long) CONST_DOUBLE_LOW (x));
7821 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
7824 /* We can't handle floating point constants;
7825 PRINT_OPERAND must handle them. */
7826 output_operand_lossage ("floating constant misused");
7830 /* Some assemblers need integer constants to appear first. */
7831 if (CONST_INT_P (XEXP (x, 0)))
7833 output_pic_addr_const (file, XEXP (x, 0), code);
7835 output_pic_addr_const (file, XEXP (x, 1), code);
7839 gcc_assert (CONST_INT_P (XEXP (x, 1)));
7840 output_pic_addr_const (file, XEXP (x, 1), code);
7842 output_pic_addr_const (file, XEXP (x, 0), code);
7848 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
7849 output_pic_addr_const (file, XEXP (x, 0), code);
7851 output_pic_addr_const (file, XEXP (x, 1), code);
7853 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
7857 gcc_assert (XVECLEN (x, 0) == 1);
7858 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
7859 switch (XINT (x, 1))
7862 fputs ("@GOT", file);
7865 fputs ("@GOTOFF", file);
7868 fputs ("@PLTOFF", file);
7870 case UNSPEC_GOTPCREL:
7871 fputs ("@GOTPCREL(%rip)", file);
7873 case UNSPEC_GOTTPOFF:
7874 /* FIXME: This might be @TPOFF in Sun ld too. */
7875 fputs ("@GOTTPOFF", file);
7878 fputs ("@TPOFF", file);
7882 fputs ("@TPOFF", file);
7884 fputs ("@NTPOFF", file);
7887 fputs ("@DTPOFF", file);
7889 case UNSPEC_GOTNTPOFF:
7891 fputs ("@GOTTPOFF(%rip)", file);
7893 fputs ("@GOTNTPOFF", file);
7895 case UNSPEC_INDNTPOFF:
7896 fputs ("@INDNTPOFF", file);
7899 output_operand_lossage ("invalid UNSPEC as operand");
7905 output_operand_lossage ("invalid expression as operand");
7909 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
7910 We need to emit DTP-relative relocations. */
7912 static void ATTRIBUTE_UNUSED
7913 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
7915 fputs (ASM_LONG, file);
7916 output_addr_const (file, x);
7917 fputs ("@DTPOFF", file);
7923 fputs (", 0", file);
7930 /* In the name of slightly smaller debug output, and to cater to
7931 general assembler lossage, recognize PIC+GOTOFF and turn it back
7932 into a direct symbol reference.
7934 On Darwin, this is necessary to avoid a crash, because Darwin
7935 has a different PIC label for each routine but the DWARF debugging
7936 information is not associated with any particular routine, so it's
7937 necessary to remove references to the PIC label from RTL stored by
7938 the DWARF output code. */
7941 ix86_delegitimize_address (rtx orig_x)
7944 /* reg_addend is NULL or a multiple of some register. */
7945 rtx reg_addend = NULL_RTX;
7946 /* const_addend is NULL or a const_int. */
7947 rtx const_addend = NULL_RTX;
7948 /* This is the result, or NULL. */
7949 rtx result = NULL_RTX;
7956 if (GET_CODE (x) != CONST
7957 || GET_CODE (XEXP (x, 0)) != UNSPEC
7958 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
7961 return XVECEXP (XEXP (x, 0), 0, 0);
7964 if (GET_CODE (x) != PLUS
7965 || GET_CODE (XEXP (x, 1)) != CONST)
7968 if (REG_P (XEXP (x, 0))
7969 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
7970 /* %ebx + GOT/GOTOFF */
7972 else if (GET_CODE (XEXP (x, 0)) == PLUS)
7974 /* %ebx + %reg * scale + GOT/GOTOFF */
7975 reg_addend = XEXP (x, 0);
7976 if (REG_P (XEXP (reg_addend, 0))
7977 && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM)
7978 reg_addend = XEXP (reg_addend, 1);
7979 else if (REG_P (XEXP (reg_addend, 1))
7980 && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM)
7981 reg_addend = XEXP (reg_addend, 0);
7984 if (!REG_P (reg_addend)
7985 && GET_CODE (reg_addend) != MULT
7986 && GET_CODE (reg_addend) != ASHIFT)
7992 x = XEXP (XEXP (x, 1), 0);
7993 if (GET_CODE (x) == PLUS
7994 && CONST_INT_P (XEXP (x, 1)))
7996 const_addend = XEXP (x, 1);
8000 if (GET_CODE (x) == UNSPEC
8001 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
8002 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
8003 result = XVECEXP (x, 0, 0);
8005 if (TARGET_MACHO && darwin_local_data_pic (x)
8007 result = XEXP (x, 0);
8013 result = gen_rtx_PLUS (Pmode, result, const_addend);
8015 result = gen_rtx_PLUS (Pmode, reg_addend, result);
8019 /* If X is a machine specific address (i.e. a symbol or label being
8020 referenced as a displacement from the GOT implemented using an
8021 UNSPEC), then return the base term. Otherwise return X. */
8024 ix86_find_base_term (rtx x)
8030 if (GET_CODE (x) != CONST)
8033 if (GET_CODE (term) == PLUS
8034 && (CONST_INT_P (XEXP (term, 1))
8035 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
8036 term = XEXP (term, 0);
8037 if (GET_CODE (term) != UNSPEC
8038 || XINT (term, 1) != UNSPEC_GOTPCREL)
8041 term = XVECEXP (term, 0, 0);
8043 if (GET_CODE (term) != SYMBOL_REF
8044 && GET_CODE (term) != LABEL_REF)
8050 term = ix86_delegitimize_address (x);
8052 if (GET_CODE (term) != SYMBOL_REF
8053 && GET_CODE (term) != LABEL_REF)
8060 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
8065 if (mode == CCFPmode || mode == CCFPUmode)
8067 enum rtx_code second_code, bypass_code;
8068 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
8069 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
8070 code = ix86_fp_compare_code_to_integer (code);
8074 code = reverse_condition (code);
8085 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
8089 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
8090 Those same assemblers have the same but opposite lossage on cmov. */
8091 gcc_assert (mode == CCmode);
8092 suffix = fp ? "nbe" : "a";
8112 gcc_assert (mode == CCmode);
8134 gcc_assert (mode == CCmode);
8135 suffix = fp ? "nb" : "ae";
8138 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
8142 gcc_assert (mode == CCmode);
8146 suffix = fp ? "u" : "p";
8149 suffix = fp ? "nu" : "np";
8154 fputs (suffix, file);
8157 /* Print the name of register X to FILE based on its machine mode and number.
8158 If CODE is 'w', pretend the mode is HImode.
8159 If CODE is 'b', pretend the mode is QImode.
8160 If CODE is 'k', pretend the mode is SImode.
8161 If CODE is 'q', pretend the mode is DImode.
8162 If CODE is 'h', pretend the reg is the 'high' byte register.
8163 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
8166 print_reg (rtx x, int code, FILE *file)
8168 gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
8169 && REGNO (x) != FRAME_POINTER_REGNUM
8170 && REGNO (x) != FLAGS_REG
8171 && REGNO (x) != FPSR_REG
8172 && REGNO (x) != FPCR_REG);
8174 if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
8177 if (code == 'w' || MMX_REG_P (x))
8179 else if (code == 'b')
8181 else if (code == 'k')
8183 else if (code == 'q')
8185 else if (code == 'y')
8187 else if (code == 'h')
8190 code = GET_MODE_SIZE (GET_MODE (x));
8192 /* Irritatingly, AMD extended registers use different naming convention
8193 from the normal registers. */
8194 if (REX_INT_REG_P (x))
8196 gcc_assert (TARGET_64BIT);
8200 error ("extended registers have no high halves");
8203 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
8206 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
8209 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
8212 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
8215 error ("unsupported operand size for extended register");
8223 if (STACK_TOP_P (x))
8225 fputs ("st(0)", file);
8232 if (! ANY_FP_REG_P (x))
8233 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
8238 fputs (hi_reg_name[REGNO (x)], file);
8241 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
8243 fputs (qi_reg_name[REGNO (x)], file);
8246 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
8248 fputs (qi_high_reg_name[REGNO (x)], file);
8255 /* Locate some local-dynamic symbol still in use by this function
8256 so that we can print its name in some tls_local_dynamic_base
8260 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8264 if (GET_CODE (x) == SYMBOL_REF
8265 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8267 cfun->machine->some_ld_name = XSTR (x, 0);
8275 get_some_local_dynamic_name (void)
8279 if (cfun->machine->some_ld_name)
8280 return cfun->machine->some_ld_name;
8282 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8284 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
8285 return cfun->machine->some_ld_name;
8291 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
8292 C -- print opcode suffix for set/cmov insn.
8293 c -- like C, but print reversed condition
8294 F,f -- likewise, but for floating-point.
8295 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
8297 R -- print the prefix for register names.
8298 z -- print the opcode suffix for the size of the current operand.
8299 * -- print a star (in certain assembler syntax)
8300 A -- print an absolute memory reference.
8301 w -- print the operand as if it's a "word" (HImode) even if it isn't.
8302 s -- print a shift double count, followed by the assemblers argument
8304 b -- print the QImode name of the register for the indicated operand.
8305 %b0 would print %al if operands[0] is reg 0.
8306 w -- likewise, print the HImode name of the register.
8307 k -- likewise, print the SImode name of the register.
8308 q -- likewise, print the DImode name of the register.
8309 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
8310 y -- print "st(0)" instead of "st" as a register.
8311 D -- print condition for SSE cmp instruction.
8312 P -- if PIC, print an @PLT suffix.
8313 X -- don't print any sort of PIC '@' suffix for a symbol.
8314 & -- print some in-use local-dynamic symbol name.
8315 H -- print a memory address offset by 8; used for sse high-parts
8319 print_operand (FILE *file, rtx x, int code)
8326 if (ASSEMBLER_DIALECT == ASM_ATT)
8331 assemble_name (file, get_some_local_dynamic_name ());
8335 switch (ASSEMBLER_DIALECT)
8342 /* Intel syntax. For absolute addresses, registers should not
8343 be surrounded by braces. */
8347 PRINT_OPERAND (file, x, 0);
8357 PRINT_OPERAND (file, x, 0);
8362 if (ASSEMBLER_DIALECT == ASM_ATT)
8367 if (ASSEMBLER_DIALECT == ASM_ATT)
8372 if (ASSEMBLER_DIALECT == ASM_ATT)
8377 if (ASSEMBLER_DIALECT == ASM_ATT)
8382 if (ASSEMBLER_DIALECT == ASM_ATT)
8387 if (ASSEMBLER_DIALECT == ASM_ATT)
8392 /* 387 opcodes don't get size suffixes if the operands are
8394 if (STACK_REG_P (x))
8397 /* Likewise if using Intel opcodes. */
8398 if (ASSEMBLER_DIALECT == ASM_INTEL)
8401 /* This is the size of op from size of operand. */
8402 switch (GET_MODE_SIZE (GET_MODE (x)))
8411 #ifdef HAVE_GAS_FILDS_FISTS
8421 if (GET_MODE (x) == SFmode)
8436 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
8438 #ifdef GAS_MNEMONICS
8464 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
8466 PRINT_OPERAND (file, x, 0);
8472 /* Little bit of braindamage here. The SSE compare instructions
8473 does use completely different names for the comparisons that the
8474 fp conditional moves. */
8475 switch (GET_CODE (x))
8490 fputs ("unord", file);
8494 fputs ("neq", file);
8498 fputs ("nlt", file);
8502 fputs ("nle", file);
8505 fputs ("ord", file);
8512 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8513 if (ASSEMBLER_DIALECT == ASM_ATT)
8515 switch (GET_MODE (x))
8517 case HImode: putc ('w', file); break;
8519 case SFmode: putc ('l', file); break;
8521 case DFmode: putc ('q', file); break;
8522 default: gcc_unreachable ();
8529 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
8532 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8533 if (ASSEMBLER_DIALECT == ASM_ATT)
8536 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
8539 /* Like above, but reverse condition */
8541 /* Check to see if argument to %c is really a constant
8542 and not a condition code which needs to be reversed. */
8543 if (!COMPARISON_P (x))
8545 output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
8548 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
8551 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
8552 if (ASSEMBLER_DIALECT == ASM_ATT)
8555 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
8559 /* It doesn't actually matter what mode we use here, as we're
8560 only going to use this for printing. */
8561 x = adjust_address_nv (x, DImode, 8);
8568 if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
8571 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
8574 int pred_val = INTVAL (XEXP (x, 0));
8576 if (pred_val < REG_BR_PROB_BASE * 45 / 100
8577 || pred_val > REG_BR_PROB_BASE * 55 / 100)
8579 int taken = pred_val > REG_BR_PROB_BASE / 2;
8580 int cputaken = final_forward_branch_p (current_output_insn) == 0;
8582 /* Emit hints only in the case default branch prediction
8583 heuristics would fail. */
8584 if (taken != cputaken)
8586 /* We use 3e (DS) prefix for taken branches and
8587 2e (CS) prefix for not taken branches. */
8589 fputs ("ds ; ", file);
8591 fputs ("cs ; ", file);
8598 output_operand_lossage ("invalid operand code '%c'", code);
8603 print_reg (x, code, file);
8607 /* No `byte ptr' prefix for call instructions. */
8608 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
8611 switch (GET_MODE_SIZE (GET_MODE (x)))
8613 case 1: size = "BYTE"; break;
8614 case 2: size = "WORD"; break;
8615 case 4: size = "DWORD"; break;
8616 case 8: size = "QWORD"; break;
8617 case 12: size = "XWORD"; break;
8618 case 16: size = "XMMWORD"; break;
8623 /* Check for explicit size override (codes 'b', 'w' and 'k') */
8626 else if (code == 'w')
8628 else if (code == 'k')
8632 fputs (" PTR ", file);
8636 /* Avoid (%rip) for call operands. */
8637 if (CONSTANT_ADDRESS_P (x) && code == 'P'
8638 && !CONST_INT_P (x))
8639 output_addr_const (file, x);
8640 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
8641 output_operand_lossage ("invalid constraints for operand");
8646 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
8651 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8652 REAL_VALUE_TO_TARGET_SINGLE (r, l);
8654 if (ASSEMBLER_DIALECT == ASM_ATT)
8656 fprintf (file, "0x%08lx", l);
8659 /* These float cases don't actually occur as immediate operands. */
8660 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
8664 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
8665 fprintf (file, "%s", dstr);
8668 else if (GET_CODE (x) == CONST_DOUBLE
8669 && GET_MODE (x) == XFmode)
8673 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
8674 fprintf (file, "%s", dstr);
8679 /* We have patterns that allow zero sets of memory, for instance.
8680 In 64-bit mode, we should probably support all 8-byte vectors,
8681 since we can in fact encode that into an immediate. */
8682 if (GET_CODE (x) == CONST_VECTOR)
8684 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
8690 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
8692 if (ASSEMBLER_DIALECT == ASM_ATT)
8695 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
8696 || GET_CODE (x) == LABEL_REF)
8698 if (ASSEMBLER_DIALECT == ASM_ATT)
8701 fputs ("OFFSET FLAT:", file);
8704 if (CONST_INT_P (x))
8705 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
8707 output_pic_addr_const (file, x, code);
8709 output_addr_const (file, x);
8713 /* Print a memory operand whose address is ADDR. */
8716 print_operand_address (FILE *file, rtx addr)
8718 struct ix86_address parts;
8719 rtx base, index, disp;
8721 int ok = ix86_decompose_address (addr, &parts);
8726 index = parts.index;
8728 scale = parts.scale;
8736 if (USER_LABEL_PREFIX[0] == 0)
8738 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
8744 if (!base && !index)
8746 /* Displacement only requires special attention. */
8748 if (CONST_INT_P (disp))
8750 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
8752 if (USER_LABEL_PREFIX[0] == 0)
8754 fputs ("ds:", file);
8756 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
8759 output_pic_addr_const (file, disp, 0);
8761 output_addr_const (file, disp);
8763 /* Use one byte shorter RIP relative addressing for 64bit mode. */
8766 if (GET_CODE (disp) == CONST
8767 && GET_CODE (XEXP (disp, 0)) == PLUS
8768 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
8769 disp = XEXP (XEXP (disp, 0), 0);
8770 if (GET_CODE (disp) == LABEL_REF
8771 || (GET_CODE (disp) == SYMBOL_REF
8772 && SYMBOL_REF_TLS_MODEL (disp) == 0))
8773 fputs ("(%rip)", file);
8778 if (ASSEMBLER_DIALECT == ASM_ATT)
8783 output_pic_addr_const (file, disp, 0);
8784 else if (GET_CODE (disp) == LABEL_REF)
8785 output_asm_label (disp);
8787 output_addr_const (file, disp);
8792 print_reg (base, 0, file);
8796 print_reg (index, 0, file);
8798 fprintf (file, ",%d", scale);
8804 rtx offset = NULL_RTX;
8808 /* Pull out the offset of a symbol; print any symbol itself. */
8809 if (GET_CODE (disp) == CONST
8810 && GET_CODE (XEXP (disp, 0)) == PLUS
8811 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
8813 offset = XEXP (XEXP (disp, 0), 1);
8814 disp = gen_rtx_CONST (VOIDmode,
8815 XEXP (XEXP (disp, 0), 0));
8819 output_pic_addr_const (file, disp, 0);
8820 else if (GET_CODE (disp) == LABEL_REF)
8821 output_asm_label (disp);
8822 else if (CONST_INT_P (disp))
8825 output_addr_const (file, disp);
8831 print_reg (base, 0, file);
8834 if (INTVAL (offset) >= 0)
8836 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
8840 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
8847 print_reg (index, 0, file);
8849 fprintf (file, "*%d", scale);
8857 output_addr_const_extra (FILE *file, rtx x)
8861 if (GET_CODE (x) != UNSPEC)
8864 op = XVECEXP (x, 0, 0);
8865 switch (XINT (x, 1))
8867 case UNSPEC_GOTTPOFF:
8868 output_addr_const (file, op);
8869 /* FIXME: This might be @TPOFF in Sun ld. */
8870 fputs ("@GOTTPOFF", file);
8873 output_addr_const (file, op);
8874 fputs ("@TPOFF", file);
8877 output_addr_const (file, op);
8879 fputs ("@TPOFF", file);
8881 fputs ("@NTPOFF", file);
8884 output_addr_const (file, op);
8885 fputs ("@DTPOFF", file);
8887 case UNSPEC_GOTNTPOFF:
8888 output_addr_const (file, op);
8890 fputs ("@GOTTPOFF(%rip)", file);
8892 fputs ("@GOTNTPOFF", file);
8894 case UNSPEC_INDNTPOFF:
8895 output_addr_const (file, op);
8896 fputs ("@INDNTPOFF", file);
8906 /* Split one or more DImode RTL references into pairs of SImode
8907 references. The RTL can be REG, offsettable MEM, integer constant, or
8908 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8909 split and "num" is its length. lo_half and hi_half are output arrays
8910 that parallel "operands". */
8913 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
8917 rtx op = operands[num];
8919 /* simplify_subreg refuse to split volatile memory addresses,
8920 but we still have to handle it. */
8923 lo_half[num] = adjust_address (op, SImode, 0);
8924 hi_half[num] = adjust_address (op, SImode, 4);
8928 lo_half[num] = simplify_gen_subreg (SImode, op,
8929 GET_MODE (op) == VOIDmode
8930 ? DImode : GET_MODE (op), 0);
8931 hi_half[num] = simplify_gen_subreg (SImode, op,
8932 GET_MODE (op) == VOIDmode
8933 ? DImode : GET_MODE (op), 4);
8937 /* Split one or more TImode RTL references into pairs of DImode
8938 references. The RTL can be REG, offsettable MEM, integer constant, or
8939 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
8940 split and "num" is its length. lo_half and hi_half are output arrays
8941 that parallel "operands". */
8944 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
8948 rtx op = operands[num];
8950 /* simplify_subreg refuse to split volatile memory addresses, but we
8951 still have to handle it. */
8954 lo_half[num] = adjust_address (op, DImode, 0);
8955 hi_half[num] = adjust_address (op, DImode, 8);
8959 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
8960 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
8965 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
8966 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
8967 is the expression of the binary operation. The output may either be
8968 emitted here, or returned to the caller, like all output_* functions.
8970 There is no guarantee that the operands are the same mode, as they
8971 might be within FLOAT or FLOAT_EXTEND expressions. */
8973 #ifndef SYSV386_COMPAT
8974 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
8975 wants to fix the assemblers because that causes incompatibility
8976 with gcc. No-one wants to fix gcc because that causes
8977 incompatibility with assemblers... You can use the option of
8978 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
8979 #define SYSV386_COMPAT 1
8983 output_387_binary_op (rtx insn, rtx *operands)
8985 static char buf[30];
8988 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
8990 #ifdef ENABLE_CHECKING
8991 /* Even if we do not want to check the inputs, this documents input
8992 constraints. Which helps in understanding the following code. */
8993 if (STACK_REG_P (operands[0])
8994 && ((REG_P (operands[1])
8995 && REGNO (operands[0]) == REGNO (operands[1])
8996 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
8997 || (REG_P (operands[2])
8998 && REGNO (operands[0]) == REGNO (operands[2])
8999 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
9000 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
9003 gcc_assert (is_sse);
9006 switch (GET_CODE (operands[3]))
9009 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9010 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9018 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9019 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9027 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9028 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9036 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
9037 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
9051 if (GET_MODE (operands[0]) == SFmode)
9052 strcat (buf, "ss\t{%2, %0|%0, %2}");
9054 strcat (buf, "sd\t{%2, %0|%0, %2}");
9059 switch (GET_CODE (operands[3]))
9063 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
9065 rtx temp = operands[2];
9066 operands[2] = operands[1];
9070 /* know operands[0] == operands[1]. */
9072 if (MEM_P (operands[2]))
9078 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9080 if (STACK_TOP_P (operands[0]))
9081 /* How is it that we are storing to a dead operand[2]?
9082 Well, presumably operands[1] is dead too. We can't
9083 store the result to st(0) as st(0) gets popped on this
9084 instruction. Instead store to operands[2] (which I
9085 think has to be st(1)). st(1) will be popped later.
9086 gcc <= 2.8.1 didn't have this check and generated
9087 assembly code that the Unixware assembler rejected. */
9088 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9090 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9094 if (STACK_TOP_P (operands[0]))
9095 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9097 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9102 if (MEM_P (operands[1]))
9108 if (MEM_P (operands[2]))
9114 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
9117 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
9118 derived assemblers, confusingly reverse the direction of
9119 the operation for fsub{r} and fdiv{r} when the
9120 destination register is not st(0). The Intel assembler
9121 doesn't have this brain damage. Read !SYSV386_COMPAT to
9122 figure out what the hardware really does. */
9123 if (STACK_TOP_P (operands[0]))
9124 p = "{p\t%0, %2|rp\t%2, %0}";
9126 p = "{rp\t%2, %0|p\t%0, %2}";
9128 if (STACK_TOP_P (operands[0]))
9129 /* As above for fmul/fadd, we can't store to st(0). */
9130 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
9132 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
9137 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
9140 if (STACK_TOP_P (operands[0]))
9141 p = "{rp\t%0, %1|p\t%1, %0}";
9143 p = "{p\t%1, %0|rp\t%0, %1}";
9145 if (STACK_TOP_P (operands[0]))
9146 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
9148 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
9153 if (STACK_TOP_P (operands[0]))
9155 if (STACK_TOP_P (operands[1]))
9156 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
9158 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
9161 else if (STACK_TOP_P (operands[1]))
9164 p = "{\t%1, %0|r\t%0, %1}";
9166 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
9172 p = "{r\t%2, %0|\t%0, %2}";
9174 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
9187 /* Return needed mode for entity in optimize_mode_switching pass. */
9190 ix86_mode_needed (int entity, rtx insn)
9192 enum attr_i387_cw mode;
9194 /* The mode UNINITIALIZED is used to store control word after a
9195 function call or ASM pattern. The mode ANY specify that function
9196 has no requirements on the control word and make no changes in the
9197 bits we are interested in. */
9200 || (NONJUMP_INSN_P (insn)
9201 && (asm_noperands (PATTERN (insn)) >= 0
9202 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
9203 return I387_CW_UNINITIALIZED;
9205 if (recog_memoized (insn) < 0)
9208 mode = get_attr_i387_cw (insn);
9213 if (mode == I387_CW_TRUNC)
9218 if (mode == I387_CW_FLOOR)
9223 if (mode == I387_CW_CEIL)
9228 if (mode == I387_CW_MASK_PM)
9239 /* Output code to initialize control word copies used by trunc?f?i and
9240 rounding patterns. CURRENT_MODE is set to current control word,
9241 while NEW_MODE is set to new control word. */
9244 emit_i387_cw_initialization (int mode)
9246 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
9251 rtx reg = gen_reg_rtx (HImode);
9253 emit_insn (gen_x86_fnstcw_1 (stored_mode));
9254 emit_move_insn (reg, copy_rtx (stored_mode));
9256 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
9261 /* round toward zero (truncate) */
9262 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
9263 slot = SLOT_CW_TRUNC;
9267 /* round down toward -oo */
9268 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9269 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
9270 slot = SLOT_CW_FLOOR;
9274 /* round up toward +oo */
9275 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
9276 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
9277 slot = SLOT_CW_CEIL;
9280 case I387_CW_MASK_PM:
9281 /* mask precision exception for nearbyint() */
9282 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9283 slot = SLOT_CW_MASK_PM;
9295 /* round toward zero (truncate) */
9296 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
9297 slot = SLOT_CW_TRUNC;
9301 /* round down toward -oo */
9302 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
9303 slot = SLOT_CW_FLOOR;
9307 /* round up toward +oo */
9308 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
9309 slot = SLOT_CW_CEIL;
9312 case I387_CW_MASK_PM:
9313 /* mask precision exception for nearbyint() */
9314 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
9315 slot = SLOT_CW_MASK_PM;
9323 gcc_assert (slot < MAX_386_STACK_LOCALS);
9325 new_mode = assign_386_stack_local (HImode, slot);
9326 emit_move_insn (new_mode, reg);
9329 /* Output code for INSN to convert a float to a signed int. OPERANDS
9330 are the insn operands. The output may be [HSD]Imode and the input
9331 operand may be [SDX]Fmode. */
9334 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
9336 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9337 int dimode_p = GET_MODE (operands[0]) == DImode;
9338 int round_mode = get_attr_i387_cw (insn);
9340 /* Jump through a hoop or two for DImode, since the hardware has no
9341 non-popping instruction. We used to do this a different way, but
9342 that was somewhat fragile and broke with post-reload splitters. */
9343 if ((dimode_p || fisttp) && !stack_top_dies)
9344 output_asm_insn ("fld\t%y1", operands);
9346 gcc_assert (STACK_TOP_P (operands[1]));
9347 gcc_assert (MEM_P (operands[0]));
9348 gcc_assert (GET_MODE (operands[1]) != TFmode);
9351 output_asm_insn ("fisttp%z0\t%0", operands);
9354 if (round_mode != I387_CW_ANY)
9355 output_asm_insn ("fldcw\t%3", operands);
9356 if (stack_top_dies || dimode_p)
9357 output_asm_insn ("fistp%z0\t%0", operands);
9359 output_asm_insn ("fist%z0\t%0", operands);
9360 if (round_mode != I387_CW_ANY)
9361 output_asm_insn ("fldcw\t%2", operands);
9367 /* Output code for x87 ffreep insn. The OPNO argument, which may only
9368 have the values zero or one, indicates the ffreep insn's operand
9369 from the OPERANDS array. */
9372 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
9374 if (TARGET_USE_FFREEP)
9375 #if HAVE_AS_IX86_FFREEP
9376 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
9379 static char retval[] = ".word\t0xc_df";
9380 int regno = REGNO (operands[opno]);
9382 gcc_assert (FP_REGNO_P (regno));
9384 retval[9] = '0' + (regno - FIRST_STACK_REG);
9389 return opno ? "fstp\t%y1" : "fstp\t%y0";
9393 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
9394 should be used. UNORDERED_P is true when fucom should be used. */
9397 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
9400 rtx cmp_op0, cmp_op1;
9401 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
9405 cmp_op0 = operands[0];
9406 cmp_op1 = operands[1];
9410 cmp_op0 = operands[1];
9411 cmp_op1 = operands[2];
9416 if (GET_MODE (operands[0]) == SFmode)
9418 return "ucomiss\t{%1, %0|%0, %1}";
9420 return "comiss\t{%1, %0|%0, %1}";
9423 return "ucomisd\t{%1, %0|%0, %1}";
9425 return "comisd\t{%1, %0|%0, %1}";
9428 gcc_assert (STACK_TOP_P (cmp_op0));
9430 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
9432 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
9436 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
9437 return output_387_ffreep (operands, 1);
9440 return "ftst\n\tfnstsw\t%0";
9443 if (STACK_REG_P (cmp_op1)
9445 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
9446 && REGNO (cmp_op1) != FIRST_STACK_REG)
9448 /* If both the top of the 387 stack dies, and the other operand
9449 is also a stack register that dies, then this must be a
9450 `fcompp' float compare */
9454 /* There is no double popping fcomi variant. Fortunately,
9455 eflags is immune from the fstp's cc clobbering. */
9457 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
9459 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
9460 return output_387_ffreep (operands, 0);
9465 return "fucompp\n\tfnstsw\t%0";
9467 return "fcompp\n\tfnstsw\t%0";
9472 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
9474 static const char * const alt[16] =
9476 "fcom%z2\t%y2\n\tfnstsw\t%0",
9477 "fcomp%z2\t%y2\n\tfnstsw\t%0",
9478 "fucom%z2\t%y2\n\tfnstsw\t%0",
9479 "fucomp%z2\t%y2\n\tfnstsw\t%0",
9481 "ficom%z2\t%y2\n\tfnstsw\t%0",
9482 "ficomp%z2\t%y2\n\tfnstsw\t%0",
9486 "fcomi\t{%y1, %0|%0, %y1}",
9487 "fcomip\t{%y1, %0|%0, %y1}",
9488 "fucomi\t{%y1, %0|%0, %y1}",
9489 "fucomip\t{%y1, %0|%0, %y1}",
9500 mask = eflags_p << 3;
9501 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
9502 mask |= unordered_p << 1;
9503 mask |= stack_top_dies;
9505 gcc_assert (mask < 16);
9514 ix86_output_addr_vec_elt (FILE *file, int value)
9516 const char *directive = ASM_LONG;
9520 directive = ASM_QUAD;
9522 gcc_assert (!TARGET_64BIT);
9525 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
9529 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
9531 const char *directive = ASM_LONG;
9534 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
9535 directive = ASM_QUAD;
9537 gcc_assert (!TARGET_64BIT);
9539 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
9540 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
9541 fprintf (file, "%s%s%d-%s%d\n",
9542 directive, LPREFIX, value, LPREFIX, rel);
9543 else if (HAVE_AS_GOTOFF_IN_DATA)
9544 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
9546 else if (TARGET_MACHO)
9548 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
9549 machopic_output_function_base_name (file);
9550 fprintf(file, "\n");
9554 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
9555 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
9558 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
9562 ix86_expand_clear (rtx dest)
9566 /* We play register width games, which are only valid after reload. */
9567 gcc_assert (reload_completed);
9569 /* Avoid HImode and its attendant prefix byte. */
9570 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
9571 dest = gen_rtx_REG (SImode, REGNO (dest));
9572 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
9574 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
9575 if (reload_completed && (!TARGET_USE_MOV0 || optimize_size))
9577 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, 17));
9578 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
9584 /* X is an unchanging MEM. If it is a constant pool reference, return
9585 the constant pool rtx, else NULL. */
9588 maybe_get_pool_constant (rtx x)
9590 x = ix86_delegitimize_address (XEXP (x, 0));
9592 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
9593 return get_pool_constant (x);
9599 ix86_expand_move (enum machine_mode mode, rtx operands[])
9601 int strict = (reload_in_progress || reload_completed);
9603 enum tls_model model;
9608 if (GET_CODE (op1) == SYMBOL_REF)
9610 model = SYMBOL_REF_TLS_MODEL (op1);
9613 op1 = legitimize_tls_address (op1, model, true);
9614 op1 = force_operand (op1, op0);
9618 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9619 && SYMBOL_REF_DLLIMPORT_P (op1))
9620 op1 = legitimize_dllimport_symbol (op1, false);
9622 else if (GET_CODE (op1) == CONST
9623 && GET_CODE (XEXP (op1, 0)) == PLUS
9624 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
9626 rtx addend = XEXP (XEXP (op1, 0), 1);
9627 rtx symbol = XEXP (XEXP (op1, 0), 0);
9630 model = SYMBOL_REF_TLS_MODEL (symbol);
9632 tmp = legitimize_tls_address (symbol, model, true);
9633 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9634 && SYMBOL_REF_DLLIMPORT_P (symbol))
9635 tmp = legitimize_dllimport_symbol (symbol, true);
9639 tmp = force_operand (tmp, NULL);
9640 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
9641 op0, 1, OPTAB_DIRECT);
9647 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
9649 if (TARGET_MACHO && !TARGET_64BIT)
9654 rtx temp = ((reload_in_progress
9655 || ((op0 && REG_P (op0))
9657 ? op0 : gen_reg_rtx (Pmode));
9658 op1 = machopic_indirect_data_reference (op1, temp);
9659 op1 = machopic_legitimize_pic_address (op1, mode,
9660 temp == op1 ? 0 : temp);
9662 else if (MACHOPIC_INDIRECT)
9663 op1 = machopic_indirect_data_reference (op1, 0);
9671 op1 = force_reg (Pmode, op1);
9672 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
9674 rtx reg = no_new_pseudos ? op0 : NULL_RTX;
9675 op1 = legitimize_pic_address (op1, reg);
9684 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
9685 || !push_operand (op0, mode))
9687 op1 = force_reg (mode, op1);
9689 if (push_operand (op0, mode)
9690 && ! general_no_elim_operand (op1, mode))
9691 op1 = copy_to_mode_reg (mode, op1);
9693 /* Force large constants in 64bit compilation into register
9694 to get them CSEed. */
9695 if (TARGET_64BIT && mode == DImode
9696 && immediate_operand (op1, mode)
9697 && !x86_64_zext_immediate_operand (op1, VOIDmode)
9698 && !register_operand (op0, mode)
9699 && optimize && !reload_completed && !reload_in_progress)
9700 op1 = copy_to_mode_reg (mode, op1);
9702 if (FLOAT_MODE_P (mode))
9704 /* If we are loading a floating point constant to a register,
9705 force the value to memory now, since we'll get better code
9706 out the back end. */
9710 else if (GET_CODE (op1) == CONST_DOUBLE)
9712 op1 = validize_mem (force_const_mem (mode, op1));
9713 if (!register_operand (op0, mode))
9715 rtx temp = gen_reg_rtx (mode);
9716 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
9717 emit_move_insn (op0, temp);
9724 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
9728 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
9730 rtx op0 = operands[0], op1 = operands[1];
9731 unsigned int align = GET_MODE_ALIGNMENT (mode);
9733 /* Force constants other than zero into memory. We do not know how
9734 the instructions used to build constants modify the upper 64 bits
9735 of the register, once we have that information we may be able
9736 to handle some of them more efficiently. */
9737 if ((reload_in_progress | reload_completed) == 0
9738 && register_operand (op0, mode)
9739 && (CONSTANT_P (op1)
9740 || (GET_CODE (op1) == SUBREG
9741 && CONSTANT_P (SUBREG_REG (op1))))
9742 && standard_sse_constant_p (op1) <= 0)
9743 op1 = validize_mem (force_const_mem (mode, op1));
9745 /* TDmode values are passed as TImode on the stack. Timode values
9746 are moved via xmm registers, and moving them to stack can result in
9747 unaligned memory access. Use ix86_expand_vector_move_misalign()
9748 if memory operand is not aligned correctly. */
9750 && (mode == TImode) && !TARGET_64BIT
9751 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
9752 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
9756 /* ix86_expand_vector_move_misalign() does not like constants ... */
9757 if (CONSTANT_P (op1)
9758 || (GET_CODE (op1) == SUBREG
9759 && CONSTANT_P (SUBREG_REG (op1))))
9760 op1 = validize_mem (force_const_mem (mode, op1));
9762 /* ... nor both arguments in memory. */
9763 if (!register_operand (op0, mode)
9764 && !register_operand (op1, mode))
9765 op1 = force_reg (mode, op1);
9767 tmp[0] = op0; tmp[1] = op1;
9768 ix86_expand_vector_move_misalign (mode, tmp);
9772 /* Make operand1 a register if it isn't already. */
9774 && !register_operand (op0, mode)
9775 && !register_operand (op1, mode))
9777 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
9781 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
9784 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
9785 straight to ix86_expand_vector_move. */
9786 /* Code generation for scalar reg-reg moves of single and double precision data:
9787 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
9791 if (x86_sse_partial_reg_dependency == true)
9796 Code generation for scalar loads of double precision data:
9797 if (x86_sse_split_regs == true)
9798 movlpd mem, reg (gas syntax)
9802 Code generation for unaligned packed loads of single precision data
9803 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
9804 if (x86_sse_unaligned_move_optimal)
9807 if (x86_sse_partial_reg_dependency == true)
9819 Code generation for unaligned packed loads of double precision data
9820 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
9821 if (x86_sse_unaligned_move_optimal)
9824 if (x86_sse_split_regs == true)
9837 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
9846 /* If we're optimizing for size, movups is the smallest. */
9849 op0 = gen_lowpart (V4SFmode, op0);
9850 op1 = gen_lowpart (V4SFmode, op1);
9851 emit_insn (gen_sse_movups (op0, op1));
9855 /* ??? If we have typed data, then it would appear that using
9856 movdqu is the only way to get unaligned data loaded with
9858 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
9860 op0 = gen_lowpart (V16QImode, op0);
9861 op1 = gen_lowpart (V16QImode, op1);
9862 emit_insn (gen_sse2_movdqu (op0, op1));
9866 if (TARGET_SSE2 && mode == V2DFmode)
9870 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
9872 op0 = gen_lowpart (V2DFmode, op0);
9873 op1 = gen_lowpart (V2DFmode, op1);
9874 emit_insn (gen_sse2_movupd (op0, op1));
9878 /* When SSE registers are split into halves, we can avoid
9879 writing to the top half twice. */
9880 if (TARGET_SSE_SPLIT_REGS)
9882 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
9887 /* ??? Not sure about the best option for the Intel chips.
9888 The following would seem to satisfy; the register is
9889 entirely cleared, breaking the dependency chain. We
9890 then store to the upper half, with a dependency depth
9891 of one. A rumor has it that Intel recommends two movsd
9892 followed by an unpacklpd, but this is unconfirmed. And
9893 given that the dependency depth of the unpacklpd would
9894 still be one, I'm not sure why this would be better. */
9895 zero = CONST0_RTX (V2DFmode);
9898 m = adjust_address (op1, DFmode, 0);
9899 emit_insn (gen_sse2_loadlpd (op0, zero, m));
9900 m = adjust_address (op1, DFmode, 8);
9901 emit_insn (gen_sse2_loadhpd (op0, op0, m));
9905 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
9907 op0 = gen_lowpart (V4SFmode, op0);
9908 op1 = gen_lowpart (V4SFmode, op1);
9909 emit_insn (gen_sse_movups (op0, op1));
9913 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
9914 emit_move_insn (op0, CONST0_RTX (mode));
9916 emit_insn (gen_rtx_CLOBBER (VOIDmode, op0));
9918 if (mode != V4SFmode)
9919 op0 = gen_lowpart (V4SFmode, op0);
9920 m = adjust_address (op1, V2SFmode, 0);
9921 emit_insn (gen_sse_loadlps (op0, op0, m));
9922 m = adjust_address (op1, V2SFmode, 8);
9923 emit_insn (gen_sse_loadhps (op0, op0, m));
9926 else if (MEM_P (op0))
9928 /* If we're optimizing for size, movups is the smallest. */
9931 op0 = gen_lowpart (V4SFmode, op0);
9932 op1 = gen_lowpart (V4SFmode, op1);
9933 emit_insn (gen_sse_movups (op0, op1));
9937 /* ??? Similar to above, only less clear because of quote
9938 typeless stores unquote. */
9939 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
9940 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
9942 op0 = gen_lowpart (V16QImode, op0);
9943 op1 = gen_lowpart (V16QImode, op1);
9944 emit_insn (gen_sse2_movdqu (op0, op1));
9948 if (TARGET_SSE2 && mode == V2DFmode)
9950 m = adjust_address (op0, DFmode, 0);
9951 emit_insn (gen_sse2_storelpd (m, op1));
9952 m = adjust_address (op0, DFmode, 8);
9953 emit_insn (gen_sse2_storehpd (m, op1));
9957 if (mode != V4SFmode)
9958 op1 = gen_lowpart (V4SFmode, op1);
9959 m = adjust_address (op0, V2SFmode, 0);
9960 emit_insn (gen_sse_storelps (m, op1));
9961 m = adjust_address (op0, V2SFmode, 8);
9962 emit_insn (gen_sse_storehps (m, op1));
9969 /* Expand a push in MODE. This is some mode for which we do not support
9970 proper push instructions, at least from the registers that we expect
9971 the value to live in. */
9974 ix86_expand_push (enum machine_mode mode, rtx x)
9978 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
9979 GEN_INT (-GET_MODE_SIZE (mode)),
9980 stack_pointer_rtx, 1, OPTAB_DIRECT);
9981 if (tmp != stack_pointer_rtx)
9982 emit_move_insn (stack_pointer_rtx, tmp);
9984 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
9985 emit_move_insn (tmp, x);
9988 /* Helper function of ix86_fixup_binary_operands to canonicalize
9989 operand order. Returns true if the operands should be swapped. */
9992 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
9995 rtx dst = operands[0];
9996 rtx src1 = operands[1];
9997 rtx src2 = operands[2];
9999 /* If the operation is not commutative, we can't do anything. */
10000 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
10003 /* Highest priority is that src1 should match dst. */
10004 if (rtx_equal_p (dst, src1))
10006 if (rtx_equal_p (dst, src2))
10009 /* Next highest priority is that immediate constants come second. */
10010 if (immediate_operand (src2, mode))
10012 if (immediate_operand (src1, mode))
10015 /* Lowest priority is that memory references should come second. */
10025 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
10026 destination to use for the operation. If different from the true
10027 destination in operands[0], a copy operation will be required. */
10030 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
10033 rtx dst = operands[0];
10034 rtx src1 = operands[1];
10035 rtx src2 = operands[2];
10037 /* Canonicalize operand order. */
10038 if (ix86_swap_binary_operands_p (code, mode, operands))
10045 /* Both source operands cannot be in memory. */
10046 if (MEM_P (src1) && MEM_P (src2))
10048 /* Optimization: Only read from memory once. */
10049 if (rtx_equal_p (src1, src2))
10051 src2 = force_reg (mode, src2);
10055 src2 = force_reg (mode, src2);
10058 /* If the destination is memory, and we do not have matching source
10059 operands, do things in registers. */
10060 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10061 dst = gen_reg_rtx (mode);
10063 /* Source 1 cannot be a constant. */
10064 if (CONSTANT_P (src1))
10065 src1 = force_reg (mode, src1);
10067 /* Source 1 cannot be a non-matching memory. */
10068 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10069 src1 = force_reg (mode, src1);
10071 operands[1] = src1;
10072 operands[2] = src2;
10076 /* Similarly, but assume that the destination has already been
10077 set up properly. */
10080 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
10081 enum machine_mode mode, rtx operands[])
10083 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
10084 gcc_assert (dst == operands[0]);
10087 /* Attempt to expand a binary operator. Make the expansion closer to the
10088 actual machine, then just general_operand, which will allow 3 separate
10089 memory references (one output, two input) in a single insn. */
10092 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
10095 rtx src1, src2, dst, op, clob;
10097 dst = ix86_fixup_binary_operands (code, mode, operands);
10098 src1 = operands[1];
10099 src2 = operands[2];
10101 /* Emit the instruction. */
10103 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
10104 if (reload_in_progress)
10106 /* Reload doesn't know about the flags register, and doesn't know that
10107 it doesn't want to clobber it. We can only do this with PLUS. */
10108 gcc_assert (code == PLUS);
10113 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10114 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10117 /* Fix up the destination if needed. */
10118 if (dst != operands[0])
10119 emit_move_insn (operands[0], dst);
10122 /* Return TRUE or FALSE depending on whether the binary operator meets the
10123 appropriate constraints. */
10126 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
10129 rtx dst = operands[0];
10130 rtx src1 = operands[1];
10131 rtx src2 = operands[2];
10133 /* Both source operands cannot be in memory. */
10134 if (MEM_P (src1) && MEM_P (src2))
10137 /* Canonicalize operand order for commutative operators. */
10138 if (ix86_swap_binary_operands_p (code, mode, operands))
10145 /* If the destination is memory, we must have a matching source operand. */
10146 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
10149 /* Source 1 cannot be a constant. */
10150 if (CONSTANT_P (src1))
10153 /* Source 1 cannot be a non-matching memory. */
10154 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
10160 /* Attempt to expand a unary operator. Make the expansion closer to the
10161 actual machine, then just general_operand, which will allow 2 separate
10162 memory references (one output, one input) in a single insn. */
10165 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
10168 int matching_memory;
10169 rtx src, dst, op, clob;
10174 /* If the destination is memory, and we do not have matching source
10175 operands, do things in registers. */
10176 matching_memory = 0;
10179 if (rtx_equal_p (dst, src))
10180 matching_memory = 1;
10182 dst = gen_reg_rtx (mode);
10185 /* When source operand is memory, destination must match. */
10186 if (MEM_P (src) && !matching_memory)
10187 src = force_reg (mode, src);
10189 /* Emit the instruction. */
10191 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
10192 if (reload_in_progress || code == NOT)
10194 /* Reload doesn't know about the flags register, and doesn't know that
10195 it doesn't want to clobber it. */
10196 gcc_assert (code == NOT);
10201 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10202 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
10205 /* Fix up the destination if needed. */
10206 if (dst != operands[0])
10207 emit_move_insn (operands[0], dst);
10210 /* Return TRUE or FALSE depending on whether the unary operator meets the
10211 appropriate constraints. */
10214 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
10215 enum machine_mode mode ATTRIBUTE_UNUSED,
10216 rtx operands[2] ATTRIBUTE_UNUSED)
10218 /* If one of operands is memory, source and destination must match. */
10219 if ((MEM_P (operands[0])
10220 || MEM_P (operands[1]))
10221 && ! rtx_equal_p (operands[0], operands[1]))
10226 /* Post-reload splitter for converting an SF or DFmode value in an
10227 SSE register into an unsigned SImode. */
10230 ix86_split_convert_uns_si_sse (rtx operands[])
10232 enum machine_mode vecmode;
10233 rtx value, large, zero_or_two31, input, two31, x;
10235 large = operands[1];
10236 zero_or_two31 = operands[2];
10237 input = operands[3];
10238 two31 = operands[4];
10239 vecmode = GET_MODE (large);
10240 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
10242 /* Load up the value into the low element. We must ensure that the other
10243 elements are valid floats -- zero is the easiest such value. */
10246 if (vecmode == V4SFmode)
10247 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
10249 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
10253 input = gen_rtx_REG (vecmode, REGNO (input));
10254 emit_move_insn (value, CONST0_RTX (vecmode));
10255 if (vecmode == V4SFmode)
10256 emit_insn (gen_sse_movss (value, value, input));
10258 emit_insn (gen_sse2_movsd (value, value, input));
10261 emit_move_insn (large, two31);
10262 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
10264 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
10265 emit_insn (gen_rtx_SET (VOIDmode, large, x));
10267 x = gen_rtx_AND (vecmode, zero_or_two31, large);
10268 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
10270 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
10271 emit_insn (gen_rtx_SET (VOIDmode, value, x));
10273 large = gen_rtx_REG (V4SImode, REGNO (large));
10274 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
10276 x = gen_rtx_REG (V4SImode, REGNO (value));
10277 if (vecmode == V4SFmode)
10278 emit_insn (gen_sse2_cvttps2dq (x, value));
10280 emit_insn (gen_sse2_cvttpd2dq (x, value));
10283 emit_insn (gen_xorv4si3 (value, value, large));
10286 /* Convert an unsigned DImode value into a DFmode, using only SSE.
10287 Expects the 64-bit DImode to be supplied in a pair of integral
10288 registers. Requires SSE2; will use SSE3 if available. For x86_32,
10289 -mfpmath=sse, !optimize_size only. */
10292 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
10294 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
10295 rtx int_xmm, fp_xmm;
10296 rtx biases, exponents;
10299 int_xmm = gen_reg_rtx (V4SImode);
10300 if (TARGET_INTER_UNIT_MOVES)
10301 emit_insn (gen_movdi_to_sse (int_xmm, input));
10302 else if (TARGET_SSE_SPLIT_REGS)
10304 emit_insn (gen_rtx_CLOBBER (VOIDmode, int_xmm));
10305 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
10309 x = gen_reg_rtx (V2DImode);
10310 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
10311 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
10314 x = gen_rtx_CONST_VECTOR (V4SImode,
10315 gen_rtvec (4, GEN_INT (0x43300000UL),
10316 GEN_INT (0x45300000UL),
10317 const0_rtx, const0_rtx));
10318 exponents = validize_mem (force_const_mem (V4SImode, x));
10320 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
10321 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
10323 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
10324 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
10325 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
10326 (0x1.0p84 + double(fp_value_hi_xmm)).
10327 Note these exponents differ by 32. */
10329 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
10331 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
10332 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
10333 real_ldexp (&bias_lo_rvt, &dconst1, 52);
10334 real_ldexp (&bias_hi_rvt, &dconst1, 84);
10335 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
10336 x = const_double_from_real_value (bias_hi_rvt, DFmode);
10337 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
10338 biases = validize_mem (force_const_mem (V2DFmode, biases));
10339 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
10341 /* Add the upper and lower DFmode values together. */
10343 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
10346 x = copy_to_mode_reg (V2DFmode, fp_xmm);
10347 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
10348 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
10351 ix86_expand_vector_extract (false, target, fp_xmm, 0);
10354 /* Convert an unsigned SImode value into a DFmode. Only currently used
10355 for SSE, but applicable anywhere. */
10358 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
10360 REAL_VALUE_TYPE TWO31r;
10363 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
10364 NULL, 1, OPTAB_DIRECT);
10366 fp = gen_reg_rtx (DFmode);
10367 emit_insn (gen_floatsidf2 (fp, x));
10369 real_ldexp (&TWO31r, &dconst1, 31);
10370 x = const_double_from_real_value (TWO31r, DFmode);
10372 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
10374 emit_move_insn (target, x);
10377 /* Convert a signed DImode value into a DFmode. Only used for SSE in
10378 32-bit mode; otherwise we have a direct convert instruction. */
10381 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
10383 REAL_VALUE_TYPE TWO32r;
10384 rtx fp_lo, fp_hi, x;
10386 fp_lo = gen_reg_rtx (DFmode);
10387 fp_hi = gen_reg_rtx (DFmode);
10389 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
10391 real_ldexp (&TWO32r, &dconst1, 32);
10392 x = const_double_from_real_value (TWO32r, DFmode);
10393 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
10395 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
10397 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
10400 emit_move_insn (target, x);
10403 /* Convert an unsigned SImode value into a SFmode, using only SSE.
10404 For x86_32, -mfpmath=sse, !optimize_size only. */
10406 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
10408 REAL_VALUE_TYPE ONE16r;
10409 rtx fp_hi, fp_lo, int_hi, int_lo, x;
10411 real_ldexp (&ONE16r, &dconst1, 16);
10412 x = const_double_from_real_value (ONE16r, SFmode);
10413 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
10414 NULL, 0, OPTAB_DIRECT);
10415 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
10416 NULL, 0, OPTAB_DIRECT);
10417 fp_hi = gen_reg_rtx (SFmode);
10418 fp_lo = gen_reg_rtx (SFmode);
10419 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
10420 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
10421 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
10423 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
10425 if (!rtx_equal_p (target, fp_hi))
10426 emit_move_insn (target, fp_hi);
10429 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
10430 then replicate the value for all elements of the vector
10434 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
10441 v = gen_rtvec (4, value, value, value, value);
10443 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
10444 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
10445 return gen_rtx_CONST_VECTOR (V4SFmode, v);
10449 v = gen_rtvec (2, value, value);
10451 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
10452 return gen_rtx_CONST_VECTOR (V2DFmode, v);
10455 gcc_unreachable ();
10459 /* A subroutine of ix86_expand_fp_absneg_operator and copysign expanders.
10460 Create a mask for the sign bit in MODE for an SSE register. If VECT is
10461 true, then replicate the mask for all elements of the vector register.
10462 If INVERT is true, then create a mask excluding the sign bit. */
10465 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
10467 enum machine_mode vec_mode;
10468 HOST_WIDE_INT hi, lo;
10473 /* Find the sign bit, sign extended to 2*HWI. */
10474 if (mode == SFmode)
10475 lo = 0x80000000, hi = lo < 0;
10476 else if (HOST_BITS_PER_WIDE_INT >= 64)
10477 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
10479 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
10482 lo = ~lo, hi = ~hi;
10484 /* Force this value into the low part of a fp vector constant. */
10485 mask = immed_double_const (lo, hi, mode == SFmode ? SImode : DImode);
10486 mask = gen_lowpart (mode, mask);
10488 v = ix86_build_const_vector (mode, vect, mask);
10489 vec_mode = (mode == SFmode) ? V4SFmode : V2DFmode;
10490 return force_reg (vec_mode, v);
10493 /* Generate code for floating point ABS or NEG. */
10496 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
10499 rtx mask, set, use, clob, dst, src;
10500 bool matching_memory;
10501 bool use_sse = false;
10502 bool vector_mode = VECTOR_MODE_P (mode);
10503 enum machine_mode elt_mode = mode;
10507 elt_mode = GET_MODE_INNER (mode);
10510 else if (TARGET_SSE_MATH)
10511 use_sse = SSE_FLOAT_MODE_P (mode);
10513 /* NEG and ABS performed with SSE use bitwise mask operations.
10514 Create the appropriate mask now. */
10516 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
10523 /* If the destination is memory, and we don't have matching source
10524 operands or we're using the x87, do things in registers. */
10525 matching_memory = false;
10528 if (use_sse && rtx_equal_p (dst, src))
10529 matching_memory = true;
10531 dst = gen_reg_rtx (mode);
10533 if (MEM_P (src) && !matching_memory)
10534 src = force_reg (mode, src);
10538 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
10539 set = gen_rtx_SET (VOIDmode, dst, set);
10544 set = gen_rtx_fmt_e (code, mode, src);
10545 set = gen_rtx_SET (VOIDmode, dst, set);
10548 use = gen_rtx_USE (VOIDmode, mask);
10549 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
10550 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10551 gen_rtvec (3, set, use, clob)));
10557 if (dst != operands[0])
10558 emit_move_insn (operands[0], dst);
10561 /* Expand a copysign operation. Special case operand 0 being a constant. */
10564 ix86_expand_copysign (rtx operands[])
10566 enum machine_mode mode, vmode;
10567 rtx dest, op0, op1, mask, nmask;
10569 dest = operands[0];
10573 mode = GET_MODE (dest);
10574 vmode = mode == SFmode ? V4SFmode : V2DFmode;
10576 if (GET_CODE (op0) == CONST_DOUBLE)
10580 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
10581 op0 = simplify_unary_operation (ABS, mode, op0, mode);
10583 if (op0 == CONST0_RTX (mode))
10584 op0 = CONST0_RTX (vmode);
10587 if (mode == SFmode)
10588 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
10589 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
10591 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
10592 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
10595 mask = ix86_build_signbit_mask (mode, 0, 0);
10597 if (mode == SFmode)
10598 emit_insn (gen_copysignsf3_const (dest, op0, op1, mask));
10600 emit_insn (gen_copysigndf3_const (dest, op0, op1, mask));
10604 nmask = ix86_build_signbit_mask (mode, 0, 1);
10605 mask = ix86_build_signbit_mask (mode, 0, 0);
10607 if (mode == SFmode)
10608 emit_insn (gen_copysignsf3_var (dest, NULL, op0, op1, nmask, mask));
10610 emit_insn (gen_copysigndf3_var (dest, NULL, op0, op1, nmask, mask));
10614 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
10615 be a constant, and so has already been expanded into a vector constant. */
10618 ix86_split_copysign_const (rtx operands[])
10620 enum machine_mode mode, vmode;
10621 rtx dest, op0, op1, mask, x;
10623 dest = operands[0];
10626 mask = operands[3];
10628 mode = GET_MODE (dest);
10629 vmode = GET_MODE (mask);
10631 dest = simplify_gen_subreg (vmode, dest, mode, 0);
10632 x = gen_rtx_AND (vmode, dest, mask);
10633 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10635 if (op0 != CONST0_RTX (vmode))
10637 x = gen_rtx_IOR (vmode, dest, op0);
10638 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10642 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
10643 so we have to do two masks. */
10646 ix86_split_copysign_var (rtx operands[])
10648 enum machine_mode mode, vmode;
10649 rtx dest, scratch, op0, op1, mask, nmask, x;
10651 dest = operands[0];
10652 scratch = operands[1];
10655 nmask = operands[4];
10656 mask = operands[5];
10658 mode = GET_MODE (dest);
10659 vmode = GET_MODE (mask);
10661 if (rtx_equal_p (op0, op1))
10663 /* Shouldn't happen often (it's useless, obviously), but when it does
10664 we'd generate incorrect code if we continue below. */
10665 emit_move_insn (dest, op0);
10669 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
10671 gcc_assert (REGNO (op1) == REGNO (scratch));
10673 x = gen_rtx_AND (vmode, scratch, mask);
10674 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
10677 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
10678 x = gen_rtx_NOT (vmode, dest);
10679 x = gen_rtx_AND (vmode, x, op0);
10680 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10684 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
10686 x = gen_rtx_AND (vmode, scratch, mask);
10688 else /* alternative 2,4 */
10690 gcc_assert (REGNO (mask) == REGNO (scratch));
10691 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
10692 x = gen_rtx_AND (vmode, scratch, op1);
10694 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
10696 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
10698 dest = simplify_gen_subreg (vmode, op0, mode, 0);
10699 x = gen_rtx_AND (vmode, dest, nmask);
10701 else /* alternative 3,4 */
10703 gcc_assert (REGNO (nmask) == REGNO (dest));
10705 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
10706 x = gen_rtx_AND (vmode, dest, op0);
10708 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10711 x = gen_rtx_IOR (vmode, dest, scratch);
10712 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
10715 /* Return TRUE or FALSE depending on whether the first SET in INSN
10716 has source and destination with matching CC modes, and that the
10717 CC mode is at least as constrained as REQ_MODE. */
10720 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
10723 enum machine_mode set_mode;
10725 set = PATTERN (insn);
10726 if (GET_CODE (set) == PARALLEL)
10727 set = XVECEXP (set, 0, 0);
10728 gcc_assert (GET_CODE (set) == SET);
10729 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
10731 set_mode = GET_MODE (SET_DEST (set));
10735 if (req_mode != CCNOmode
10736 && (req_mode != CCmode
10737 || XEXP (SET_SRC (set), 1) != const0_rtx))
10741 if (req_mode == CCGCmode)
10745 if (req_mode == CCGOCmode || req_mode == CCNOmode)
10749 if (req_mode == CCZmode)
10756 gcc_unreachable ();
10759 return (GET_MODE (SET_SRC (set)) == set_mode);
10762 /* Generate insn patterns to do an integer compare of OPERANDS. */
10765 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
10767 enum machine_mode cmpmode;
10770 cmpmode = SELECT_CC_MODE (code, op0, op1);
10771 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
10773 /* This is very simple, but making the interface the same as in the
10774 FP case makes the rest of the code easier. */
10775 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
10776 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
10778 /* Return the test that should be put into the flags user, i.e.
10779 the bcc, scc, or cmov instruction. */
10780 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
10783 /* Figure out whether to use ordered or unordered fp comparisons.
10784 Return the appropriate mode to use. */
10787 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
10789 /* ??? In order to make all comparisons reversible, we do all comparisons
10790 non-trapping when compiling for IEEE. Once gcc is able to distinguish
10791 all forms trapping and nontrapping comparisons, we can make inequality
10792 comparisons trapping again, since it results in better code when using
10793 FCOM based compares. */
10794 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
10798 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
10800 enum machine_mode mode = GET_MODE (op0);
10802 if (SCALAR_FLOAT_MODE_P (mode))
10804 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
10805 return ix86_fp_compare_mode (code);
10810 /* Only zero flag is needed. */
10811 case EQ: /* ZF=0 */
10812 case NE: /* ZF!=0 */
10814 /* Codes needing carry flag. */
10815 case GEU: /* CF=0 */
10816 case GTU: /* CF=0 & ZF=0 */
10817 case LTU: /* CF=1 */
10818 case LEU: /* CF=1 | ZF=1 */
10820 /* Codes possibly doable only with sign flag when
10821 comparing against zero. */
10822 case GE: /* SF=OF or SF=0 */
10823 case LT: /* SF<>OF or SF=1 */
10824 if (op1 == const0_rtx)
10827 /* For other cases Carry flag is not required. */
10829 /* Codes doable only with sign flag when comparing
10830 against zero, but we miss jump instruction for it
10831 so we need to use relational tests against overflow
10832 that thus needs to be zero. */
10833 case GT: /* ZF=0 & SF=OF */
10834 case LE: /* ZF=1 | SF<>OF */
10835 if (op1 == const0_rtx)
10839 /* strcmp pattern do (use flags) and combine may ask us for proper
10844 gcc_unreachable ();
10848 /* Return the fixed registers used for condition codes. */
10851 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
10858 /* If two condition code modes are compatible, return a condition code
10859 mode which is compatible with both. Otherwise, return
10862 static enum machine_mode
10863 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
10868 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
10871 if ((m1 == CCGCmode && m2 == CCGOCmode)
10872 || (m1 == CCGOCmode && m2 == CCGCmode))
10878 gcc_unreachable ();
10900 /* These are only compatible with themselves, which we already
10906 /* Split comparison code CODE into comparisons we can do using branch
10907 instructions. BYPASS_CODE is comparison code for branch that will
10908 branch around FIRST_CODE and SECOND_CODE. If some of branches
10909 is not required, set value to UNKNOWN.
10910 We never require more than two branches. */
10913 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
10914 enum rtx_code *first_code,
10915 enum rtx_code *second_code)
10917 *first_code = code;
10918 *bypass_code = UNKNOWN;
10919 *second_code = UNKNOWN;
10921 /* The fcomi comparison sets flags as follows:
10931 case GT: /* GTU - CF=0 & ZF=0 */
10932 case GE: /* GEU - CF=0 */
10933 case ORDERED: /* PF=0 */
10934 case UNORDERED: /* PF=1 */
10935 case UNEQ: /* EQ - ZF=1 */
10936 case UNLT: /* LTU - CF=1 */
10937 case UNLE: /* LEU - CF=1 | ZF=1 */
10938 case LTGT: /* EQ - ZF=0 */
10940 case LT: /* LTU - CF=1 - fails on unordered */
10941 *first_code = UNLT;
10942 *bypass_code = UNORDERED;
10944 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
10945 *first_code = UNLE;
10946 *bypass_code = UNORDERED;
10948 case EQ: /* EQ - ZF=1 - fails on unordered */
10949 *first_code = UNEQ;
10950 *bypass_code = UNORDERED;
10952 case NE: /* NE - ZF=0 - fails on unordered */
10953 *first_code = LTGT;
10954 *second_code = UNORDERED;
10956 case UNGE: /* GEU - CF=0 - fails on unordered */
10958 *second_code = UNORDERED;
10960 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
10962 *second_code = UNORDERED;
10965 gcc_unreachable ();
10967 if (!TARGET_IEEE_FP)
10969 *second_code = UNKNOWN;
10970 *bypass_code = UNKNOWN;
10974 /* Return cost of comparison done fcom + arithmetics operations on AX.
10975 All following functions do use number of instructions as a cost metrics.
10976 In future this should be tweaked to compute bytes for optimize_size and
10977 take into account performance of various instructions on various CPUs. */
10979 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
10981 if (!TARGET_IEEE_FP)
10983 /* The cost of code output by ix86_expand_fp_compare. */
11007 gcc_unreachable ();
11011 /* Return cost of comparison done using fcomi operation.
11012 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11014 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
11016 enum rtx_code bypass_code, first_code, second_code;
11017 /* Return arbitrarily high cost when instruction is not supported - this
11018 prevents gcc from using it. */
11021 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11022 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
11025 /* Return cost of comparison done using sahf operation.
11026 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11028 ix86_fp_comparison_sahf_cost (enum rtx_code code)
11030 enum rtx_code bypass_code, first_code, second_code;
11031 /* Return arbitrarily high cost when instruction is not preferred - this
11032 avoids gcc from using it. */
11033 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_size)))
11035 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11036 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
11039 /* Compute cost of the comparison done using any method.
11040 See ix86_fp_comparison_arithmetics_cost for the metrics. */
11042 ix86_fp_comparison_cost (enum rtx_code code)
11044 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
11047 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
11048 sahf_cost = ix86_fp_comparison_sahf_cost (code);
11050 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
11051 if (min > sahf_cost)
11053 if (min > fcomi_cost)
11058 /* Return true if we should use an FCOMI instruction for this
11062 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
11064 enum rtx_code swapped_code = swap_condition (code);
11066 return ((ix86_fp_comparison_cost (code)
11067 == ix86_fp_comparison_fcomi_cost (code))
11068 || (ix86_fp_comparison_cost (swapped_code)
11069 == ix86_fp_comparison_fcomi_cost (swapped_code)));
11072 /* Swap, force into registers, or otherwise massage the two operands
11073 to a fp comparison. The operands are updated in place; the new
11074 comparison code is returned. */
11076 static enum rtx_code
11077 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
11079 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
11080 rtx op0 = *pop0, op1 = *pop1;
11081 enum machine_mode op_mode = GET_MODE (op0);
11082 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
11084 /* All of the unordered compare instructions only work on registers.
11085 The same is true of the fcomi compare instructions. The XFmode
11086 compare instructions require registers except when comparing
11087 against zero or when converting operand 1 from fixed point to
11091 && (fpcmp_mode == CCFPUmode
11092 || (op_mode == XFmode
11093 && ! (standard_80387_constant_p (op0) == 1
11094 || standard_80387_constant_p (op1) == 1)
11095 && GET_CODE (op1) != FLOAT)
11096 || ix86_use_fcomi_compare (code)))
11098 op0 = force_reg (op_mode, op0);
11099 op1 = force_reg (op_mode, op1);
11103 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
11104 things around if they appear profitable, otherwise force op0
11105 into a register. */
11107 if (standard_80387_constant_p (op0) == 0
11109 && ! (standard_80387_constant_p (op1) == 0
11113 tmp = op0, op0 = op1, op1 = tmp;
11114 code = swap_condition (code);
11118 op0 = force_reg (op_mode, op0);
11120 if (CONSTANT_P (op1))
11122 int tmp = standard_80387_constant_p (op1);
11124 op1 = validize_mem (force_const_mem (op_mode, op1));
11128 op1 = force_reg (op_mode, op1);
11131 op1 = force_reg (op_mode, op1);
11135 /* Try to rearrange the comparison to make it cheaper. */
11136 if (ix86_fp_comparison_cost (code)
11137 > ix86_fp_comparison_cost (swap_condition (code))
11138 && (REG_P (op1) || !no_new_pseudos))
11141 tmp = op0, op0 = op1, op1 = tmp;
11142 code = swap_condition (code);
11144 op0 = force_reg (op_mode, op0);
11152 /* Convert comparison codes we use to represent FP comparison to integer
11153 code that will result in proper branch. Return UNKNOWN if no such code
11157 ix86_fp_compare_code_to_integer (enum rtx_code code)
11186 /* Generate insn patterns to do a floating point compare of OPERANDS. */
11189 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
11190 rtx *second_test, rtx *bypass_test)
11192 enum machine_mode fpcmp_mode, intcmp_mode;
11194 int cost = ix86_fp_comparison_cost (code);
11195 enum rtx_code bypass_code, first_code, second_code;
11197 fpcmp_mode = ix86_fp_compare_mode (code);
11198 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
11201 *second_test = NULL_RTX;
11203 *bypass_test = NULL_RTX;
11205 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11207 /* Do fcomi/sahf based test when profitable. */
11208 if ((TARGET_CMOVE || TARGET_SAHF)
11209 && (bypass_code == UNKNOWN || bypass_test)
11210 && (second_code == UNKNOWN || second_test)
11211 && ix86_fp_comparison_arithmetics_cost (code) > cost)
11215 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11216 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
11222 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11223 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
11225 scratch = gen_reg_rtx (HImode);
11226 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
11227 emit_insn (gen_x86_sahf_1 (scratch));
11230 /* The FP codes work out to act like unsigned. */
11231 intcmp_mode = fpcmp_mode;
11233 if (bypass_code != UNKNOWN)
11234 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
11235 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11237 if (second_code != UNKNOWN)
11238 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
11239 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11244 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
11245 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
11246 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
11248 scratch = gen_reg_rtx (HImode);
11249 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
11251 /* In the unordered case, we have to check C2 for NaN's, which
11252 doesn't happen to work out to anything nice combination-wise.
11253 So do some bit twiddling on the value we've got in AH to come
11254 up with an appropriate set of condition codes. */
11256 intcmp_mode = CCNOmode;
11261 if (code == GT || !TARGET_IEEE_FP)
11263 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11268 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11269 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11270 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
11271 intcmp_mode = CCmode;
11277 if (code == LT && TARGET_IEEE_FP)
11279 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11280 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
11281 intcmp_mode = CCmode;
11286 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
11292 if (code == GE || !TARGET_IEEE_FP)
11294 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
11299 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11300 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11307 if (code == LE && TARGET_IEEE_FP)
11309 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11310 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
11311 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11312 intcmp_mode = CCmode;
11317 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
11323 if (code == EQ && TARGET_IEEE_FP)
11325 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11326 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
11327 intcmp_mode = CCmode;
11332 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11339 if (code == NE && TARGET_IEEE_FP)
11341 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
11342 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
11348 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
11354 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11358 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
11363 gcc_unreachable ();
11367 /* Return the test that should be put into the flags user, i.e.
11368 the bcc, scc, or cmov instruction. */
11369 return gen_rtx_fmt_ee (code, VOIDmode,
11370 gen_rtx_REG (intcmp_mode, FLAGS_REG),
11375 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
11378 op0 = ix86_compare_op0;
11379 op1 = ix86_compare_op1;
11382 *second_test = NULL_RTX;
11384 *bypass_test = NULL_RTX;
11386 if (ix86_compare_emitted)
11388 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
11389 ix86_compare_emitted = NULL_RTX;
11391 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
11393 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
11394 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
11395 second_test, bypass_test);
11398 ret = ix86_expand_int_compare (code, op0, op1);
11403 /* Return true if the CODE will result in nontrivial jump sequence. */
11405 ix86_fp_jump_nontrivial_p (enum rtx_code code)
11407 enum rtx_code bypass_code, first_code, second_code;
11410 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11411 return bypass_code != UNKNOWN || second_code != UNKNOWN;
11415 ix86_expand_branch (enum rtx_code code, rtx label)
11419 /* If we have emitted a compare insn, go straight to simple.
11420 ix86_expand_compare won't emit anything if ix86_compare_emitted
11422 if (ix86_compare_emitted)
11425 switch (GET_MODE (ix86_compare_op0))
11431 tmp = ix86_expand_compare (code, NULL, NULL);
11432 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11433 gen_rtx_LABEL_REF (VOIDmode, label),
11435 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
11444 enum rtx_code bypass_code, first_code, second_code;
11446 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
11447 &ix86_compare_op1);
11449 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
11451 /* Check whether we will use the natural sequence with one jump. If
11452 so, we can expand jump early. Otherwise delay expansion by
11453 creating compound insn to not confuse optimizers. */
11454 if (bypass_code == UNKNOWN && second_code == UNKNOWN
11457 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
11458 gen_rtx_LABEL_REF (VOIDmode, label),
11459 pc_rtx, NULL_RTX, NULL_RTX);
11463 tmp = gen_rtx_fmt_ee (code, VOIDmode,
11464 ix86_compare_op0, ix86_compare_op1);
11465 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
11466 gen_rtx_LABEL_REF (VOIDmode, label),
11468 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
11470 use_fcomi = ix86_use_fcomi_compare (code);
11471 vec = rtvec_alloc (3 + !use_fcomi);
11472 RTVEC_ELT (vec, 0) = tmp;
11474 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 18));
11476 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, 17));
11479 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
11481 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
11490 /* Expand DImode branch into multiple compare+branch. */
11492 rtx lo[2], hi[2], label2;
11493 enum rtx_code code1, code2, code3;
11494 enum machine_mode submode;
11496 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
11498 tmp = ix86_compare_op0;
11499 ix86_compare_op0 = ix86_compare_op1;
11500 ix86_compare_op1 = tmp;
11501 code = swap_condition (code);
11503 if (GET_MODE (ix86_compare_op0) == DImode)
11505 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
11506 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
11511 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
11512 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
11516 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
11517 avoid two branches. This costs one extra insn, so disable when
11518 optimizing for size. */
11520 if ((code == EQ || code == NE)
11522 || hi[1] == const0_rtx || lo[1] == const0_rtx))
11527 if (hi[1] != const0_rtx)
11528 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
11529 NULL_RTX, 0, OPTAB_WIDEN);
11532 if (lo[1] != const0_rtx)
11533 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
11534 NULL_RTX, 0, OPTAB_WIDEN);
11536 tmp = expand_binop (submode, ior_optab, xor1, xor0,
11537 NULL_RTX, 0, OPTAB_WIDEN);
11539 ix86_compare_op0 = tmp;
11540 ix86_compare_op1 = const0_rtx;
11541 ix86_expand_branch (code, label);
11545 /* Otherwise, if we are doing less-than or greater-or-equal-than,
11546 op1 is a constant and the low word is zero, then we can just
11547 examine the high word. */
11549 if (CONST_INT_P (hi[1]) && lo[1] == const0_rtx)
11552 case LT: case LTU: case GE: case GEU:
11553 ix86_compare_op0 = hi[0];
11554 ix86_compare_op1 = hi[1];
11555 ix86_expand_branch (code, label);
11561 /* Otherwise, we need two or three jumps. */
11563 label2 = gen_label_rtx ();
11566 code2 = swap_condition (code);
11567 code3 = unsigned_condition (code);
11571 case LT: case GT: case LTU: case GTU:
11574 case LE: code1 = LT; code2 = GT; break;
11575 case GE: code1 = GT; code2 = LT; break;
11576 case LEU: code1 = LTU; code2 = GTU; break;
11577 case GEU: code1 = GTU; code2 = LTU; break;
11579 case EQ: code1 = UNKNOWN; code2 = NE; break;
11580 case NE: code2 = UNKNOWN; break;
11583 gcc_unreachable ();
11588 * if (hi(a) < hi(b)) goto true;
11589 * if (hi(a) > hi(b)) goto false;
11590 * if (lo(a) < lo(b)) goto true;
11594 ix86_compare_op0 = hi[0];
11595 ix86_compare_op1 = hi[1];
11597 if (code1 != UNKNOWN)
11598 ix86_expand_branch (code1, label);
11599 if (code2 != UNKNOWN)
11600 ix86_expand_branch (code2, label2);
11602 ix86_compare_op0 = lo[0];
11603 ix86_compare_op1 = lo[1];
11604 ix86_expand_branch (code3, label);
11606 if (code2 != UNKNOWN)
11607 emit_label (label2);
11612 gcc_unreachable ();
11616 /* Split branch based on floating point condition. */
11618 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
11619 rtx target1, rtx target2, rtx tmp, rtx pushed)
11621 rtx second, bypass;
11622 rtx label = NULL_RTX;
11624 int bypass_probability = -1, second_probability = -1, probability = -1;
11627 if (target2 != pc_rtx)
11630 code = reverse_condition_maybe_unordered (code);
11635 condition = ix86_expand_fp_compare (code, op1, op2,
11636 tmp, &second, &bypass);
11638 /* Remove pushed operand from stack. */
11640 ix86_free_from_memory (GET_MODE (pushed));
11642 if (split_branch_probability >= 0)
11644 /* Distribute the probabilities across the jumps.
11645 Assume the BYPASS and SECOND to be always test
11647 probability = split_branch_probability;
11649 /* Value of 1 is low enough to make no need for probability
11650 to be updated. Later we may run some experiments and see
11651 if unordered values are more frequent in practice. */
11653 bypass_probability = 1;
11655 second_probability = 1;
11657 if (bypass != NULL_RTX)
11659 label = gen_label_rtx ();
11660 i = emit_jump_insn (gen_rtx_SET
11662 gen_rtx_IF_THEN_ELSE (VOIDmode,
11664 gen_rtx_LABEL_REF (VOIDmode,
11667 if (bypass_probability >= 0)
11669 = gen_rtx_EXPR_LIST (REG_BR_PROB,
11670 GEN_INT (bypass_probability),
11673 i = emit_jump_insn (gen_rtx_SET
11675 gen_rtx_IF_THEN_ELSE (VOIDmode,
11676 condition, target1, target2)));
11677 if (probability >= 0)
11679 = gen_rtx_EXPR_LIST (REG_BR_PROB,
11680 GEN_INT (probability),
11682 if (second != NULL_RTX)
11684 i = emit_jump_insn (gen_rtx_SET
11686 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
11688 if (second_probability >= 0)
11690 = gen_rtx_EXPR_LIST (REG_BR_PROB,
11691 GEN_INT (second_probability),
11694 if (label != NULL_RTX)
11695 emit_label (label);
11699 ix86_expand_setcc (enum rtx_code code, rtx dest)
11701 rtx ret, tmp, tmpreg, equiv;
11702 rtx second_test, bypass_test;
11704 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
11705 return 0; /* FAIL */
11707 gcc_assert (GET_MODE (dest) == QImode);
11709 ret = ix86_expand_compare (code, &second_test, &bypass_test);
11710 PUT_MODE (ret, QImode);
11715 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
11716 if (bypass_test || second_test)
11718 rtx test = second_test;
11720 rtx tmp2 = gen_reg_rtx (QImode);
11723 gcc_assert (!second_test);
11724 test = bypass_test;
11726 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
11728 PUT_MODE (test, QImode);
11729 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
11732 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
11734 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
11737 /* Attach a REG_EQUAL note describing the comparison result. */
11738 if (ix86_compare_op0 && ix86_compare_op1)
11740 equiv = simplify_gen_relational (code, QImode,
11741 GET_MODE (ix86_compare_op0),
11742 ix86_compare_op0, ix86_compare_op1);
11743 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
11746 return 1; /* DONE */
11749 /* Expand comparison setting or clearing carry flag. Return true when
11750 successful and set pop for the operation. */
11752 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
11754 enum machine_mode mode =
11755 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
11757 /* Do not handle DImode compares that go through special path.
11758 Also we can't deal with FP compares yet. This is possible to add. */
11759 if (mode == (TARGET_64BIT ? TImode : DImode))
11762 if (SCALAR_FLOAT_MODE_P (mode))
11764 rtx second_test = NULL, bypass_test = NULL;
11765 rtx compare_op, compare_seq;
11767 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
11769 /* Shortcut: following common codes never translate
11770 into carry flag compares. */
11771 if (code == EQ || code == NE || code == UNEQ || code == LTGT
11772 || code == ORDERED || code == UNORDERED)
11775 /* These comparisons require zero flag; swap operands so they won't. */
11776 if ((code == GT || code == UNLE || code == LE || code == UNGT)
11777 && !TARGET_IEEE_FP)
11782 code = swap_condition (code);
11785 /* Try to expand the comparison and verify that we end up with carry flag
11786 based comparison. This is fails to be true only when we decide to expand
11787 comparison using arithmetic that is not too common scenario. */
11789 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
11790 &second_test, &bypass_test);
11791 compare_seq = get_insns ();
11794 if (second_test || bypass_test)
11796 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
11797 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
11798 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
11800 code = GET_CODE (compare_op);
11801 if (code != LTU && code != GEU)
11803 emit_insn (compare_seq);
11807 if (!INTEGRAL_MODE_P (mode))
11815 /* Convert a==0 into (unsigned)a<1. */
11818 if (op1 != const0_rtx)
11821 code = (code == EQ ? LTU : GEU);
11824 /* Convert a>b into b<a or a>=b-1. */
11827 if (CONST_INT_P (op1))
11829 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
11830 /* Bail out on overflow. We still can swap operands but that
11831 would force loading of the constant into register. */
11832 if (op1 == const0_rtx
11833 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
11835 code = (code == GTU ? GEU : LTU);
11842 code = (code == GTU ? LTU : GEU);
11846 /* Convert a>=0 into (unsigned)a<0x80000000. */
11849 if (mode == DImode || op1 != const0_rtx)
11851 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
11852 code = (code == LT ? GEU : LTU);
11856 if (mode == DImode || op1 != constm1_rtx)
11858 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
11859 code = (code == LE ? GEU : LTU);
11865 /* Swapping operands may cause constant to appear as first operand. */
11866 if (!nonimmediate_operand (op0, VOIDmode))
11868 if (no_new_pseudos)
11870 op0 = force_reg (mode, op0);
11872 ix86_compare_op0 = op0;
11873 ix86_compare_op1 = op1;
11874 *pop = ix86_expand_compare (code, NULL, NULL);
11875 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
11880 ix86_expand_int_movcc (rtx operands[])
11882 enum rtx_code code = GET_CODE (operands[1]), compare_code;
11883 rtx compare_seq, compare_op;
11884 rtx second_test, bypass_test;
11885 enum machine_mode mode = GET_MODE (operands[0]);
11886 bool sign_bit_compare_p = false;;
11889 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
11890 compare_seq = get_insns ();
11893 compare_code = GET_CODE (compare_op);
11895 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
11896 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
11897 sign_bit_compare_p = true;
11899 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
11900 HImode insns, we'd be swallowed in word prefix ops. */
11902 if ((mode != HImode || TARGET_FAST_PREFIX)
11903 && (mode != (TARGET_64BIT ? TImode : DImode))
11904 && CONST_INT_P (operands[2])
11905 && CONST_INT_P (operands[3]))
11907 rtx out = operands[0];
11908 HOST_WIDE_INT ct = INTVAL (operands[2]);
11909 HOST_WIDE_INT cf = INTVAL (operands[3]);
11910 HOST_WIDE_INT diff;
11913 /* Sign bit compares are better done using shifts than we do by using
11915 if (sign_bit_compare_p
11916 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
11917 ix86_compare_op1, &compare_op))
11919 /* Detect overlap between destination and compare sources. */
11922 if (!sign_bit_compare_p)
11924 bool fpcmp = false;
11926 compare_code = GET_CODE (compare_op);
11928 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
11929 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
11932 compare_code = ix86_fp_compare_code_to_integer (compare_code);
11935 /* To simplify rest of code, restrict to the GEU case. */
11936 if (compare_code == LTU)
11938 HOST_WIDE_INT tmp = ct;
11941 compare_code = reverse_condition (compare_code);
11942 code = reverse_condition (code);
11947 PUT_CODE (compare_op,
11948 reverse_condition_maybe_unordered
11949 (GET_CODE (compare_op)));
11951 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
11955 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
11956 || reg_overlap_mentioned_p (out, ix86_compare_op1))
11957 tmp = gen_reg_rtx (mode);
11959 if (mode == DImode)
11960 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
11962 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
11966 if (code == GT || code == GE)
11967 code = reverse_condition (code);
11970 HOST_WIDE_INT tmp = ct;
11975 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
11976 ix86_compare_op1, VOIDmode, 0, -1);
11989 tmp = expand_simple_binop (mode, PLUS,
11991 copy_rtx (tmp), 1, OPTAB_DIRECT);
12002 tmp = expand_simple_binop (mode, IOR,
12004 copy_rtx (tmp), 1, OPTAB_DIRECT);
12006 else if (diff == -1 && ct)
12016 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12018 tmp = expand_simple_binop (mode, PLUS,
12019 copy_rtx (tmp), GEN_INT (cf),
12020 copy_rtx (tmp), 1, OPTAB_DIRECT);
12028 * andl cf - ct, dest
12038 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
12041 tmp = expand_simple_binop (mode, AND,
12043 gen_int_mode (cf - ct, mode),
12044 copy_rtx (tmp), 1, OPTAB_DIRECT);
12046 tmp = expand_simple_binop (mode, PLUS,
12047 copy_rtx (tmp), GEN_INT (ct),
12048 copy_rtx (tmp), 1, OPTAB_DIRECT);
12051 if (!rtx_equal_p (tmp, out))
12052 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
12054 return 1; /* DONE */
12059 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12062 tmp = ct, ct = cf, cf = tmp;
12065 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12067 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12069 /* We may be reversing unordered compare to normal compare, that
12070 is not valid in general (we may convert non-trapping condition
12071 to trapping one), however on i386 we currently emit all
12072 comparisons unordered. */
12073 compare_code = reverse_condition_maybe_unordered (compare_code);
12074 code = reverse_condition_maybe_unordered (code);
12078 compare_code = reverse_condition (compare_code);
12079 code = reverse_condition (code);
12083 compare_code = UNKNOWN;
12084 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
12085 && CONST_INT_P (ix86_compare_op1))
12087 if (ix86_compare_op1 == const0_rtx
12088 && (code == LT || code == GE))
12089 compare_code = code;
12090 else if (ix86_compare_op1 == constm1_rtx)
12094 else if (code == GT)
12099 /* Optimize dest = (op0 < 0) ? -1 : cf. */
12100 if (compare_code != UNKNOWN
12101 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
12102 && (cf == -1 || ct == -1))
12104 /* If lea code below could be used, only optimize
12105 if it results in a 2 insn sequence. */
12107 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
12108 || diff == 3 || diff == 5 || diff == 9)
12109 || (compare_code == LT && ct == -1)
12110 || (compare_code == GE && cf == -1))
12113 * notl op1 (if necessary)
12121 code = reverse_condition (code);
12124 out = emit_store_flag (out, code, ix86_compare_op0,
12125 ix86_compare_op1, VOIDmode, 0, -1);
12127 out = expand_simple_binop (mode, IOR,
12129 out, 1, OPTAB_DIRECT);
12130 if (out != operands[0])
12131 emit_move_insn (operands[0], out);
12133 return 1; /* DONE */
12138 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
12139 || diff == 3 || diff == 5 || diff == 9)
12140 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
12142 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
12148 * lea cf(dest*(ct-cf)),dest
12152 * This also catches the degenerate setcc-only case.
12158 out = emit_store_flag (out, code, ix86_compare_op0,
12159 ix86_compare_op1, VOIDmode, 0, 1);
12162 /* On x86_64 the lea instruction operates on Pmode, so we need
12163 to get arithmetics done in proper mode to match. */
12165 tmp = copy_rtx (out);
12169 out1 = copy_rtx (out);
12170 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
12174 tmp = gen_rtx_PLUS (mode, tmp, out1);
12180 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
12183 if (!rtx_equal_p (tmp, out))
12186 out = force_operand (tmp, copy_rtx (out));
12188 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
12190 if (!rtx_equal_p (out, operands[0]))
12191 emit_move_insn (operands[0], copy_rtx (out));
12193 return 1; /* DONE */
12197 * General case: Jumpful:
12198 * xorl dest,dest cmpl op1, op2
12199 * cmpl op1, op2 movl ct, dest
12200 * setcc dest jcc 1f
12201 * decl dest movl cf, dest
12202 * andl (cf-ct),dest 1:
12205 * Size 20. Size 14.
12207 * This is reasonably steep, but branch mispredict costs are
12208 * high on modern cpus, so consider failing only if optimizing
12212 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12213 && BRANCH_COST >= 2)
12217 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
12222 if (SCALAR_FLOAT_MODE_P (cmp_mode))
12224 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
12226 /* We may be reversing unordered compare to normal compare,
12227 that is not valid in general (we may convert non-trapping
12228 condition to trapping one), however on i386 we currently
12229 emit all comparisons unordered. */
12230 code = reverse_condition_maybe_unordered (code);
12234 code = reverse_condition (code);
12235 if (compare_code != UNKNOWN)
12236 compare_code = reverse_condition (compare_code);
12240 if (compare_code != UNKNOWN)
12242 /* notl op1 (if needed)
12247 For x < 0 (resp. x <= -1) there will be no notl,
12248 so if possible swap the constants to get rid of the
12250 True/false will be -1/0 while code below (store flag
12251 followed by decrement) is 0/-1, so the constants need
12252 to be exchanged once more. */
12254 if (compare_code == GE || !cf)
12256 code = reverse_condition (code);
12261 HOST_WIDE_INT tmp = cf;
12266 out = emit_store_flag (out, code, ix86_compare_op0,
12267 ix86_compare_op1, VOIDmode, 0, -1);
12271 out = emit_store_flag (out, code, ix86_compare_op0,
12272 ix86_compare_op1, VOIDmode, 0, 1);
12274 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
12275 copy_rtx (out), 1, OPTAB_DIRECT);
12278 out = expand_simple_binop (mode, AND, copy_rtx (out),
12279 gen_int_mode (cf - ct, mode),
12280 copy_rtx (out), 1, OPTAB_DIRECT);
12282 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
12283 copy_rtx (out), 1, OPTAB_DIRECT);
12284 if (!rtx_equal_p (out, operands[0]))
12285 emit_move_insn (operands[0], copy_rtx (out));
12287 return 1; /* DONE */
12291 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
12293 /* Try a few things more with specific constants and a variable. */
12296 rtx var, orig_out, out, tmp;
12298 if (BRANCH_COST <= 2)
12299 return 0; /* FAIL */
12301 /* If one of the two operands is an interesting constant, load a
12302 constant with the above and mask it in with a logical operation. */
12304 if (CONST_INT_P (operands[2]))
12307 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
12308 operands[3] = constm1_rtx, op = and_optab;
12309 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
12310 operands[3] = const0_rtx, op = ior_optab;
12312 return 0; /* FAIL */
12314 else if (CONST_INT_P (operands[3]))
12317 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
12318 operands[2] = constm1_rtx, op = and_optab;
12319 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
12320 operands[2] = const0_rtx, op = ior_optab;
12322 return 0; /* FAIL */
12325 return 0; /* FAIL */
12327 orig_out = operands[0];
12328 tmp = gen_reg_rtx (mode);
12331 /* Recurse to get the constant loaded. */
12332 if (ix86_expand_int_movcc (operands) == 0)
12333 return 0; /* FAIL */
12335 /* Mask in the interesting variable. */
12336 out = expand_binop (mode, op, var, tmp, orig_out, 0,
12338 if (!rtx_equal_p (out, orig_out))
12339 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
12341 return 1; /* DONE */
12345 * For comparison with above,
12355 if (! nonimmediate_operand (operands[2], mode))
12356 operands[2] = force_reg (mode, operands[2]);
12357 if (! nonimmediate_operand (operands[3], mode))
12358 operands[3] = force_reg (mode, operands[3]);
12360 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
12362 rtx tmp = gen_reg_rtx (mode);
12363 emit_move_insn (tmp, operands[3]);
12366 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
12368 rtx tmp = gen_reg_rtx (mode);
12369 emit_move_insn (tmp, operands[2]);
12373 if (! register_operand (operands[2], VOIDmode)
12375 || ! register_operand (operands[3], VOIDmode)))
12376 operands[2] = force_reg (mode, operands[2]);
12379 && ! register_operand (operands[3], VOIDmode))
12380 operands[3] = force_reg (mode, operands[3]);
12382 emit_insn (compare_seq);
12383 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
12384 gen_rtx_IF_THEN_ELSE (mode,
12385 compare_op, operands[2],
12388 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
12389 gen_rtx_IF_THEN_ELSE (mode,
12391 copy_rtx (operands[3]),
12392 copy_rtx (operands[0]))));
12394 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
12395 gen_rtx_IF_THEN_ELSE (mode,
12397 copy_rtx (operands[2]),
12398 copy_rtx (operands[0]))));
12400 return 1; /* DONE */
12403 /* Swap, force into registers, or otherwise massage the two operands
12404 to an sse comparison with a mask result. Thus we differ a bit from
12405 ix86_prepare_fp_compare_args which expects to produce a flags result.
12407 The DEST operand exists to help determine whether to commute commutative
12408 operators. The POP0/POP1 operands are updated in place. The new
12409 comparison code is returned, or UNKNOWN if not implementable. */
12411 static enum rtx_code
12412 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
12413 rtx *pop0, rtx *pop1)
12421 /* We have no LTGT as an operator. We could implement it with
12422 NE & ORDERED, but this requires an extra temporary. It's
12423 not clear that it's worth it. */
12430 /* These are supported directly. */
12437 /* For commutative operators, try to canonicalize the destination
12438 operand to be first in the comparison - this helps reload to
12439 avoid extra moves. */
12440 if (!dest || !rtx_equal_p (dest, *pop1))
12448 /* These are not supported directly. Swap the comparison operands
12449 to transform into something that is supported. */
12453 code = swap_condition (code);
12457 gcc_unreachable ();
12463 /* Detect conditional moves that exactly match min/max operational
12464 semantics. Note that this is IEEE safe, as long as we don't
12465 interchange the operands.
12467 Returns FALSE if this conditional move doesn't match a MIN/MAX,
12468 and TRUE if the operation is successful and instructions are emitted. */
12471 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
12472 rtx cmp_op1, rtx if_true, rtx if_false)
12474 enum machine_mode mode;
12480 else if (code == UNGE)
12483 if_true = if_false;
12489 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
12491 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
12496 mode = GET_MODE (dest);
12498 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
12499 but MODE may be a vector mode and thus not appropriate. */
12500 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
12502 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
12505 if_true = force_reg (mode, if_true);
12506 v = gen_rtvec (2, if_true, if_false);
12507 tmp = gen_rtx_UNSPEC (mode, v, u);
12511 code = is_min ? SMIN : SMAX;
12512 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
12515 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
12519 /* Expand an sse vector comparison. Return the register with the result. */
12522 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
12523 rtx op_true, rtx op_false)
12525 enum machine_mode mode = GET_MODE (dest);
12528 cmp_op0 = force_reg (mode, cmp_op0);
12529 if (!nonimmediate_operand (cmp_op1, mode))
12530 cmp_op1 = force_reg (mode, cmp_op1);
12533 || reg_overlap_mentioned_p (dest, op_true)
12534 || reg_overlap_mentioned_p (dest, op_false))
12535 dest = gen_reg_rtx (mode);
12537 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
12538 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12543 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
12544 operations. This is used for both scalar and vector conditional moves. */
12547 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
12549 enum machine_mode mode = GET_MODE (dest);
12552 if (op_false == CONST0_RTX (mode))
12554 op_true = force_reg (mode, op_true);
12555 x = gen_rtx_AND (mode, cmp, op_true);
12556 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12558 else if (op_true == CONST0_RTX (mode))
12560 op_false = force_reg (mode, op_false);
12561 x = gen_rtx_NOT (mode, cmp);
12562 x = gen_rtx_AND (mode, x, op_false);
12563 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12567 op_true = force_reg (mode, op_true);
12568 op_false = force_reg (mode, op_false);
12570 t2 = gen_reg_rtx (mode);
12572 t3 = gen_reg_rtx (mode);
12576 x = gen_rtx_AND (mode, op_true, cmp);
12577 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
12579 x = gen_rtx_NOT (mode, cmp);
12580 x = gen_rtx_AND (mode, x, op_false);
12581 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
12583 x = gen_rtx_IOR (mode, t3, t2);
12584 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
12588 /* Expand a floating-point conditional move. Return true if successful. */
12591 ix86_expand_fp_movcc (rtx operands[])
12593 enum machine_mode mode = GET_MODE (operands[0]);
12594 enum rtx_code code = GET_CODE (operands[1]);
12595 rtx tmp, compare_op, second_test, bypass_test;
12597 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
12599 enum machine_mode cmode;
12601 /* Since we've no cmove for sse registers, don't force bad register
12602 allocation just to gain access to it. Deny movcc when the
12603 comparison mode doesn't match the move mode. */
12604 cmode = GET_MODE (ix86_compare_op0);
12605 if (cmode == VOIDmode)
12606 cmode = GET_MODE (ix86_compare_op1);
12610 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
12612 &ix86_compare_op1);
12613 if (code == UNKNOWN)
12616 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
12617 ix86_compare_op1, operands[2],
12621 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
12622 ix86_compare_op1, operands[2], operands[3]);
12623 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
12627 /* The floating point conditional move instructions don't directly
12628 support conditions resulting from a signed integer comparison. */
12630 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12632 /* The floating point conditional move instructions don't directly
12633 support signed integer comparisons. */
12635 if (!fcmov_comparison_operator (compare_op, VOIDmode))
12637 gcc_assert (!second_test && !bypass_test);
12638 tmp = gen_reg_rtx (QImode);
12639 ix86_expand_setcc (code, tmp);
12641 ix86_compare_op0 = tmp;
12642 ix86_compare_op1 = const0_rtx;
12643 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
12645 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
12647 tmp = gen_reg_rtx (mode);
12648 emit_move_insn (tmp, operands[3]);
12651 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
12653 tmp = gen_reg_rtx (mode);
12654 emit_move_insn (tmp, operands[2]);
12658 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
12659 gen_rtx_IF_THEN_ELSE (mode, compare_op,
12660 operands[2], operands[3])));
12662 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
12663 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
12664 operands[3], operands[0])));
12666 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
12667 gen_rtx_IF_THEN_ELSE (mode, second_test,
12668 operands[2], operands[0])));
12673 /* Expand a floating-point vector conditional move; a vcond operation
12674 rather than a movcc operation. */
12677 ix86_expand_fp_vcond (rtx operands[])
12679 enum rtx_code code = GET_CODE (operands[3]);
12682 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
12683 &operands[4], &operands[5]);
12684 if (code == UNKNOWN)
12687 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
12688 operands[5], operands[1], operands[2]))
12691 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
12692 operands[1], operands[2]);
12693 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
12697 /* Expand a signed integral vector conditional move. */
12700 ix86_expand_int_vcond (rtx operands[])
12702 enum machine_mode mode = GET_MODE (operands[0]);
12703 enum rtx_code code = GET_CODE (operands[3]);
12704 bool negate = false;
12707 cop0 = operands[4];
12708 cop1 = operands[5];
12710 /* Canonicalize the comparison to EQ, GT, GTU. */
12721 code = reverse_condition (code);
12727 code = reverse_condition (code);
12733 code = swap_condition (code);
12734 x = cop0, cop0 = cop1, cop1 = x;
12738 gcc_unreachable ();
12741 /* Unsigned parallel compare is not supported by the hardware. Play some
12742 tricks to turn this into a signed comparison against 0. */
12745 cop0 = force_reg (mode, cop0);
12753 /* Perform a parallel modulo subtraction. */
12754 t1 = gen_reg_rtx (mode);
12755 emit_insn (gen_subv4si3 (t1, cop0, cop1));
12757 /* Extract the original sign bit of op0. */
12758 mask = GEN_INT (-0x80000000);
12759 mask = gen_rtx_CONST_VECTOR (mode,
12760 gen_rtvec (4, mask, mask, mask, mask));
12761 mask = force_reg (mode, mask);
12762 t2 = gen_reg_rtx (mode);
12763 emit_insn (gen_andv4si3 (t2, cop0, mask));
12765 /* XOR it back into the result of the subtraction. This results
12766 in the sign bit set iff we saw unsigned underflow. */
12767 x = gen_reg_rtx (mode);
12768 emit_insn (gen_xorv4si3 (x, t1, t2));
12776 /* Perform a parallel unsigned saturating subtraction. */
12777 x = gen_reg_rtx (mode);
12778 emit_insn (gen_rtx_SET (VOIDmode, x,
12779 gen_rtx_US_MINUS (mode, cop0, cop1)));
12786 gcc_unreachable ();
12790 cop1 = CONST0_RTX (mode);
12793 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
12794 operands[1+negate], operands[2-negate]);
12796 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
12797 operands[2-negate]);
12801 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
12802 true if we should do zero extension, else sign extension. HIGH_P is
12803 true if we want the N/2 high elements, else the low elements. */
12806 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
12808 enum machine_mode imode = GET_MODE (operands[1]);
12809 rtx (*unpack)(rtx, rtx, rtx);
12816 unpack = gen_vec_interleave_highv16qi;
12818 unpack = gen_vec_interleave_lowv16qi;
12822 unpack = gen_vec_interleave_highv8hi;
12824 unpack = gen_vec_interleave_lowv8hi;
12828 unpack = gen_vec_interleave_highv4si;
12830 unpack = gen_vec_interleave_lowv4si;
12833 gcc_unreachable ();
12836 dest = gen_lowpart (imode, operands[0]);
12839 se = force_reg (imode, CONST0_RTX (imode));
12841 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
12842 operands[1], pc_rtx, pc_rtx);
12844 emit_insn (unpack (dest, operands[1], se));
12847 /* This function performs the same task as ix86_expand_sse_unpack,
12848 but with SSE4.1 instructions. */
12851 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
12853 enum machine_mode imode = GET_MODE (operands[1]);
12854 rtx (*unpack)(rtx, rtx);
12861 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
12863 unpack = gen_sse4_1_extendv8qiv8hi2;
12867 unpack = gen_sse4_1_zero_extendv4hiv4si2;
12869 unpack = gen_sse4_1_extendv4hiv4si2;
12873 unpack = gen_sse4_1_zero_extendv2siv2di2;
12875 unpack = gen_sse4_1_extendv2siv2di2;
12878 gcc_unreachable ();
12881 dest = operands[0];
12884 /* Shift higher 8 bytes to lower 8 bytes. */
12885 src = gen_reg_rtx (imode);
12886 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
12887 gen_lowpart (TImode, operands[1]),
12893 emit_insn (unpack (dest, src));
12896 /* Expand conditional increment or decrement using adb/sbb instructions.
12897 The default case using setcc followed by the conditional move can be
12898 done by generic code. */
12900 ix86_expand_int_addcc (rtx operands[])
12902 enum rtx_code code = GET_CODE (operands[1]);
12904 rtx val = const0_rtx;
12905 bool fpcmp = false;
12906 enum machine_mode mode = GET_MODE (operands[0]);
12908 if (operands[3] != const1_rtx
12909 && operands[3] != constm1_rtx)
12911 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
12912 ix86_compare_op1, &compare_op))
12914 code = GET_CODE (compare_op);
12916 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
12917 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
12920 code = ix86_fp_compare_code_to_integer (code);
12927 PUT_CODE (compare_op,
12928 reverse_condition_maybe_unordered
12929 (GET_CODE (compare_op)));
12931 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
12933 PUT_MODE (compare_op, mode);
12935 /* Construct either adc or sbb insn. */
12936 if ((code == LTU) == (operands[3] == constm1_rtx))
12938 switch (GET_MODE (operands[0]))
12941 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
12944 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
12947 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
12950 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
12953 gcc_unreachable ();
12958 switch (GET_MODE (operands[0]))
12961 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
12964 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
12967 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
12970 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
12973 gcc_unreachable ();
12976 return 1; /* DONE */
12980 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
12981 works for floating pointer parameters and nonoffsetable memories.
12982 For pushes, it returns just stack offsets; the values will be saved
12983 in the right order. Maximally three parts are generated. */
12986 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
12991 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
12993 size = (GET_MODE_SIZE (mode) + 4) / 8;
12995 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
12996 gcc_assert (size >= 2 && size <= 3);
12998 /* Optimize constant pool reference to immediates. This is used by fp
12999 moves, that force all constants to memory to allow combining. */
13000 if (MEM_P (operand) && MEM_READONLY_P (operand))
13002 rtx tmp = maybe_get_pool_constant (operand);
13007 if (MEM_P (operand) && !offsettable_memref_p (operand))
13009 /* The only non-offsetable memories we handle are pushes. */
13010 int ok = push_operand (operand, VOIDmode);
13014 operand = copy_rtx (operand);
13015 PUT_MODE (operand, Pmode);
13016 parts[0] = parts[1] = parts[2] = operand;
13020 if (GET_CODE (operand) == CONST_VECTOR)
13022 enum machine_mode imode = int_mode_for_mode (mode);
13023 /* Caution: if we looked through a constant pool memory above,
13024 the operand may actually have a different mode now. That's
13025 ok, since we want to pun this all the way back to an integer. */
13026 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
13027 gcc_assert (operand != NULL);
13033 if (mode == DImode)
13034 split_di (&operand, 1, &parts[0], &parts[1]);
13037 if (REG_P (operand))
13039 gcc_assert (reload_completed);
13040 parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0);
13041 parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1);
13043 parts[2] = gen_rtx_REG (SImode, REGNO (operand) + 2);
13045 else if (offsettable_memref_p (operand))
13047 operand = adjust_address (operand, SImode, 0);
13048 parts[0] = operand;
13049 parts[1] = adjust_address (operand, SImode, 4);
13051 parts[2] = adjust_address (operand, SImode, 8);
13053 else if (GET_CODE (operand) == CONST_DOUBLE)
13058 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13062 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
13063 parts[2] = gen_int_mode (l[2], SImode);
13066 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
13069 gcc_unreachable ();
13071 parts[1] = gen_int_mode (l[1], SImode);
13072 parts[0] = gen_int_mode (l[0], SImode);
13075 gcc_unreachable ();
13080 if (mode == TImode)
13081 split_ti (&operand, 1, &parts[0], &parts[1]);
13082 if (mode == XFmode || mode == TFmode)
13084 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
13085 if (REG_P (operand))
13087 gcc_assert (reload_completed);
13088 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
13089 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
13091 else if (offsettable_memref_p (operand))
13093 operand = adjust_address (operand, DImode, 0);
13094 parts[0] = operand;
13095 parts[1] = adjust_address (operand, upper_mode, 8);
13097 else if (GET_CODE (operand) == CONST_DOUBLE)
13102 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
13103 real_to_target (l, &r, mode);
13105 /* Do not use shift by 32 to avoid warning on 32bit systems. */
13106 if (HOST_BITS_PER_WIDE_INT >= 64)
13109 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
13110 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
13113 parts[0] = immed_double_const (l[0], l[1], DImode);
13115 if (upper_mode == SImode)
13116 parts[1] = gen_int_mode (l[2], SImode);
13117 else if (HOST_BITS_PER_WIDE_INT >= 64)
13120 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
13121 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
13124 parts[1] = immed_double_const (l[2], l[3], DImode);
13127 gcc_unreachable ();
13134 /* Emit insns to perform a move or push of DI, DF, and XF values.
13135 Return false when normal moves are needed; true when all required
13136 insns have been emitted. Operands 2-4 contain the input values
13137 int the correct order; operands 5-7 contain the output values. */
13140 ix86_split_long_move (rtx operands[])
13145 int collisions = 0;
13146 enum machine_mode mode = GET_MODE (operands[0]);
13148 /* The DFmode expanders may ask us to move double.
13149 For 64bit target this is single move. By hiding the fact
13150 here we simplify i386.md splitters. */
13151 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
13153 /* Optimize constant pool reference to immediates. This is used by
13154 fp moves, that force all constants to memory to allow combining. */
13156 if (MEM_P (operands[1])
13157 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
13158 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
13159 operands[1] = get_pool_constant (XEXP (operands[1], 0));
13160 if (push_operand (operands[0], VOIDmode))
13162 operands[0] = copy_rtx (operands[0]);
13163 PUT_MODE (operands[0], Pmode);
13166 operands[0] = gen_lowpart (DImode, operands[0]);
13167 operands[1] = gen_lowpart (DImode, operands[1]);
13168 emit_move_insn (operands[0], operands[1]);
13172 /* The only non-offsettable memory we handle is push. */
13173 if (push_operand (operands[0], VOIDmode))
13176 gcc_assert (!MEM_P (operands[0])
13177 || offsettable_memref_p (operands[0]));
13179 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
13180 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
13182 /* When emitting push, take care for source operands on the stack. */
13183 if (push && MEM_P (operands[1])
13184 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
13187 part[1][1] = change_address (part[1][1], GET_MODE (part[1][1]),
13188 XEXP (part[1][2], 0));
13189 part[1][0] = change_address (part[1][0], GET_MODE (part[1][0]),
13190 XEXP (part[1][1], 0));
13193 /* We need to do copy in the right order in case an address register
13194 of the source overlaps the destination. */
13195 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
13197 if (reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)))
13199 if (reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
13202 && reg_overlap_mentioned_p (part[0][2], XEXP (part[1][0], 0)))
13205 /* Collision in the middle part can be handled by reordering. */
13206 if (collisions == 1 && nparts == 3
13207 && reg_overlap_mentioned_p (part[0][1], XEXP (part[1][0], 0)))
13210 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
13211 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
13214 /* If there are more collisions, we can't handle it by reordering.
13215 Do an lea to the last part and use only one colliding move. */
13216 else if (collisions > 1)
13222 base = part[0][nparts - 1];
13224 /* Handle the case when the last part isn't valid for lea.
13225 Happens in 64-bit mode storing the 12-byte XFmode. */
13226 if (GET_MODE (base) != Pmode)
13227 base = gen_rtx_REG (Pmode, REGNO (base));
13229 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
13230 part[1][0] = replace_equiv_address (part[1][0], base);
13231 part[1][1] = replace_equiv_address (part[1][1],
13232 plus_constant (base, UNITS_PER_WORD));
13234 part[1][2] = replace_equiv_address (part[1][2],
13235 plus_constant (base, 8));
13245 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
13246 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
13247 emit_move_insn (part[0][2], part[1][2]);
13252 /* In 64bit mode we don't have 32bit push available. In case this is
13253 register, it is OK - we will just use larger counterpart. We also
13254 retype memory - these comes from attempt to avoid REX prefix on
13255 moving of second half of TFmode value. */
13256 if (GET_MODE (part[1][1]) == SImode)
13258 switch (GET_CODE (part[1][1]))
13261 part[1][1] = adjust_address (part[1][1], DImode, 0);
13265 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
13269 gcc_unreachable ();
13272 if (GET_MODE (part[1][0]) == SImode)
13273 part[1][0] = part[1][1];
13276 emit_move_insn (part[0][1], part[1][1]);
13277 emit_move_insn (part[0][0], part[1][0]);
13281 /* Choose correct order to not overwrite the source before it is copied. */
13282 if ((REG_P (part[0][0])
13283 && REG_P (part[1][1])
13284 && (REGNO (part[0][0]) == REGNO (part[1][1])
13286 && REGNO (part[0][0]) == REGNO (part[1][2]))))
13288 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
13292 operands[2] = part[0][2];
13293 operands[3] = part[0][1];
13294 operands[4] = part[0][0];
13295 operands[5] = part[1][2];
13296 operands[6] = part[1][1];
13297 operands[7] = part[1][0];
13301 operands[2] = part[0][1];
13302 operands[3] = part[0][0];
13303 operands[5] = part[1][1];
13304 operands[6] = part[1][0];
13311 operands[2] = part[0][0];
13312 operands[3] = part[0][1];
13313 operands[4] = part[0][2];
13314 operands[5] = part[1][0];
13315 operands[6] = part[1][1];
13316 operands[7] = part[1][2];
13320 operands[2] = part[0][0];
13321 operands[3] = part[0][1];
13322 operands[5] = part[1][0];
13323 operands[6] = part[1][1];
13327 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
13330 if (CONST_INT_P (operands[5])
13331 && operands[5] != const0_rtx
13332 && REG_P (operands[2]))
13334 if (CONST_INT_P (operands[6])
13335 && INTVAL (operands[6]) == INTVAL (operands[5]))
13336 operands[6] = operands[2];
13339 && CONST_INT_P (operands[7])
13340 && INTVAL (operands[7]) == INTVAL (operands[5]))
13341 operands[7] = operands[2];
13345 && CONST_INT_P (operands[6])
13346 && operands[6] != const0_rtx
13347 && REG_P (operands[3])
13348 && CONST_INT_P (operands[7])
13349 && INTVAL (operands[7]) == INTVAL (operands[6]))
13350 operands[7] = operands[3];
13353 emit_move_insn (operands[2], operands[5]);
13354 emit_move_insn (operands[3], operands[6]);
13356 emit_move_insn (operands[4], operands[7]);
13361 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
13362 left shift by a constant, either using a single shift or
13363 a sequence of add instructions. */
13366 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
13370 emit_insn ((mode == DImode
13372 : gen_adddi3) (operand, operand, operand));
13374 else if (!optimize_size
13375 && count * ix86_cost->add <= ix86_cost->shift_const)
13378 for (i=0; i<count; i++)
13380 emit_insn ((mode == DImode
13382 : gen_adddi3) (operand, operand, operand));
13386 emit_insn ((mode == DImode
13388 : gen_ashldi3) (operand, operand, GEN_INT (count)));
13392 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
13394 rtx low[2], high[2];
13396 const int single_width = mode == DImode ? 32 : 64;
13398 if (CONST_INT_P (operands[2]))
13400 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
13401 count = INTVAL (operands[2]) & (single_width * 2 - 1);
13403 if (count >= single_width)
13405 emit_move_insn (high[0], low[1]);
13406 emit_move_insn (low[0], const0_rtx);
13408 if (count > single_width)
13409 ix86_expand_ashl_const (high[0], count - single_width, mode);
13413 if (!rtx_equal_p (operands[0], operands[1]))
13414 emit_move_insn (operands[0], operands[1]);
13415 emit_insn ((mode == DImode
13417 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
13418 ix86_expand_ashl_const (low[0], count, mode);
13423 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
13425 if (operands[1] == const1_rtx)
13427 /* Assuming we've chosen a QImode capable registers, then 1 << N
13428 can be done with two 32/64-bit shifts, no branches, no cmoves. */
13429 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
13431 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
13433 ix86_expand_clear (low[0]);
13434 ix86_expand_clear (high[0]);
13435 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
13437 d = gen_lowpart (QImode, low[0]);
13438 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
13439 s = gen_rtx_EQ (QImode, flags, const0_rtx);
13440 emit_insn (gen_rtx_SET (VOIDmode, d, s));
13442 d = gen_lowpart (QImode, high[0]);
13443 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
13444 s = gen_rtx_NE (QImode, flags, const0_rtx);
13445 emit_insn (gen_rtx_SET (VOIDmode, d, s));
13448 /* Otherwise, we can get the same results by manually performing
13449 a bit extract operation on bit 5/6, and then performing the two
13450 shifts. The two methods of getting 0/1 into low/high are exactly
13451 the same size. Avoiding the shift in the bit extract case helps
13452 pentium4 a bit; no one else seems to care much either way. */
13457 if (TARGET_PARTIAL_REG_STALL && !optimize_size)
13458 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
13460 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
13461 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
13463 emit_insn ((mode == DImode
13465 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
13466 emit_insn ((mode == DImode
13468 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
13469 emit_move_insn (low[0], high[0]);
13470 emit_insn ((mode == DImode
13472 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
13475 emit_insn ((mode == DImode
13477 : gen_ashldi3) (low[0], low[0], operands[2]));
13478 emit_insn ((mode == DImode
13480 : gen_ashldi3) (high[0], high[0], operands[2]));
13484 if (operands[1] == constm1_rtx)
13486 /* For -1 << N, we can avoid the shld instruction, because we
13487 know that we're shifting 0...31/63 ones into a -1. */
13488 emit_move_insn (low[0], constm1_rtx);
13490 emit_move_insn (high[0], low[0]);
13492 emit_move_insn (high[0], constm1_rtx);
13496 if (!rtx_equal_p (operands[0], operands[1]))
13497 emit_move_insn (operands[0], operands[1]);
13499 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
13500 emit_insn ((mode == DImode
13502 : gen_x86_64_shld) (high[0], low[0], operands[2]));
13505 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
13507 if (TARGET_CMOVE && scratch)
13509 ix86_expand_clear (scratch);
13510 emit_insn ((mode == DImode
13511 ? gen_x86_shift_adj_1
13512 : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch));
13515 emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2]));
13519 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
13521 rtx low[2], high[2];
13523 const int single_width = mode == DImode ? 32 : 64;
13525 if (CONST_INT_P (operands[2]))
13527 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
13528 count = INTVAL (operands[2]) & (single_width * 2 - 1);
13530 if (count == single_width * 2 - 1)
13532 emit_move_insn (high[0], high[1]);
13533 emit_insn ((mode == DImode
13535 : gen_ashrdi3) (high[0], high[0],
13536 GEN_INT (single_width - 1)));
13537 emit_move_insn (low[0], high[0]);
13540 else if (count >= single_width)
13542 emit_move_insn (low[0], high[1]);
13543 emit_move_insn (high[0], low[0]);
13544 emit_insn ((mode == DImode
13546 : gen_ashrdi3) (high[0], high[0],
13547 GEN_INT (single_width - 1)));
13548 if (count > single_width)
13549 emit_insn ((mode == DImode
13551 : gen_ashrdi3) (low[0], low[0],
13552 GEN_INT (count - single_width)));
13556 if (!rtx_equal_p (operands[0], operands[1]))
13557 emit_move_insn (operands[0], operands[1]);
13558 emit_insn ((mode == DImode
13560 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
13561 emit_insn ((mode == DImode
13563 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
13568 if (!rtx_equal_p (operands[0], operands[1]))
13569 emit_move_insn (operands[0], operands[1]);
13571 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
13573 emit_insn ((mode == DImode
13575 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
13576 emit_insn ((mode == DImode
13578 : gen_ashrdi3) (high[0], high[0], operands[2]));
13580 if (TARGET_CMOVE && scratch)
13582 emit_move_insn (scratch, high[0]);
13583 emit_insn ((mode == DImode
13585 : gen_ashrdi3) (scratch, scratch,
13586 GEN_INT (single_width - 1)));
13587 emit_insn ((mode == DImode
13588 ? gen_x86_shift_adj_1
13589 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
13593 emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2]));
13598 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
13600 rtx low[2], high[2];
13602 const int single_width = mode == DImode ? 32 : 64;
13604 if (CONST_INT_P (operands[2]))
13606 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
13607 count = INTVAL (operands[2]) & (single_width * 2 - 1);
13609 if (count >= single_width)
13611 emit_move_insn (low[0], high[1]);
13612 ix86_expand_clear (high[0]);
13614 if (count > single_width)
13615 emit_insn ((mode == DImode
13617 : gen_lshrdi3) (low[0], low[0],
13618 GEN_INT (count - single_width)));
13622 if (!rtx_equal_p (operands[0], operands[1]))
13623 emit_move_insn (operands[0], operands[1]);
13624 emit_insn ((mode == DImode
13626 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
13627 emit_insn ((mode == DImode
13629 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
13634 if (!rtx_equal_p (operands[0], operands[1]))
13635 emit_move_insn (operands[0], operands[1]);
13637 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
13639 emit_insn ((mode == DImode
13641 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
13642 emit_insn ((mode == DImode
13644 : gen_lshrdi3) (high[0], high[0], operands[2]));
13646 /* Heh. By reversing the arguments, we can reuse this pattern. */
13647 if (TARGET_CMOVE && scratch)
13649 ix86_expand_clear (scratch);
13650 emit_insn ((mode == DImode
13651 ? gen_x86_shift_adj_1
13652 : gen_x86_64_shift_adj) (low[0], high[0], operands[2],
13656 emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2]));
13660 /* Predict just emitted jump instruction to be taken with probability PROB. */
13662 predict_jump (int prob)
13664 rtx insn = get_last_insn ();
13665 gcc_assert (JUMP_P (insn));
13667 = gen_rtx_EXPR_LIST (REG_BR_PROB,
13672 /* Helper function for the string operations below. Dest VARIABLE whether
13673 it is aligned to VALUE bytes. If true, jump to the label. */
13675 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
13677 rtx label = gen_label_rtx ();
13678 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
13679 if (GET_MODE (variable) == DImode)
13680 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
13682 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
13683 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
13686 predict_jump (REG_BR_PROB_BASE * 50 / 100);
13688 predict_jump (REG_BR_PROB_BASE * 90 / 100);
13692 /* Adjust COUNTER by the VALUE. */
13694 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
13696 if (GET_MODE (countreg) == DImode)
13697 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
13699 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
13702 /* Zero extend possibly SImode EXP to Pmode register. */
13704 ix86_zero_extend_to_Pmode (rtx exp)
13707 if (GET_MODE (exp) == VOIDmode)
13708 return force_reg (Pmode, exp);
13709 if (GET_MODE (exp) == Pmode)
13710 return copy_to_mode_reg (Pmode, exp);
13711 r = gen_reg_rtx (Pmode);
13712 emit_insn (gen_zero_extendsidi2 (r, exp));
13716 /* Divide COUNTREG by SCALE. */
13718 scale_counter (rtx countreg, int scale)
13721 rtx piece_size_mask;
13725 if (CONST_INT_P (countreg))
13726 return GEN_INT (INTVAL (countreg) / scale);
13727 gcc_assert (REG_P (countreg));
13729 piece_size_mask = GEN_INT (scale - 1);
13730 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
13731 GEN_INT (exact_log2 (scale)),
13732 NULL, 1, OPTAB_DIRECT);
13736 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
13737 DImode for constant loop counts. */
13739 static enum machine_mode
13740 counter_mode (rtx count_exp)
13742 if (GET_MODE (count_exp) != VOIDmode)
13743 return GET_MODE (count_exp);
13744 if (GET_CODE (count_exp) != CONST_INT)
13746 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
13751 /* When SRCPTR is non-NULL, output simple loop to move memory
13752 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
13753 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
13754 equivalent loop to set memory by VALUE (supposed to be in MODE).
13756 The size is rounded down to whole number of chunk size moved at once.
13757 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
13761 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
13762 rtx destptr, rtx srcptr, rtx value,
13763 rtx count, enum machine_mode mode, int unroll,
13766 rtx out_label, top_label, iter, tmp;
13767 enum machine_mode iter_mode = counter_mode (count);
13768 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
13769 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
13775 top_label = gen_label_rtx ();
13776 out_label = gen_label_rtx ();
13777 iter = gen_reg_rtx (iter_mode);
13779 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
13780 NULL, 1, OPTAB_DIRECT);
13781 /* Those two should combine. */
13782 if (piece_size == const1_rtx)
13784 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
13786 predict_jump (REG_BR_PROB_BASE * 10 / 100);
13788 emit_move_insn (iter, const0_rtx);
13790 emit_label (top_label);
13792 tmp = convert_modes (Pmode, iter_mode, iter, true);
13793 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
13794 destmem = change_address (destmem, mode, x_addr);
13798 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
13799 srcmem = change_address (srcmem, mode, y_addr);
13801 /* When unrolling for chips that reorder memory reads and writes,
13802 we can save registers by using single temporary.
13803 Also using 4 temporaries is overkill in 32bit mode. */
13804 if (!TARGET_64BIT && 0)
13806 for (i = 0; i < unroll; i++)
13811 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
13813 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
13815 emit_move_insn (destmem, srcmem);
13821 gcc_assert (unroll <= 4);
13822 for (i = 0; i < unroll; i++)
13824 tmpreg[i] = gen_reg_rtx (mode);
13828 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
13830 emit_move_insn (tmpreg[i], srcmem);
13832 for (i = 0; i < unroll; i++)
13837 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
13839 emit_move_insn (destmem, tmpreg[i]);
13844 for (i = 0; i < unroll; i++)
13848 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
13849 emit_move_insn (destmem, value);
13852 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
13853 true, OPTAB_LIB_WIDEN);
13855 emit_move_insn (iter, tmp);
13857 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
13859 if (expected_size != -1)
13861 expected_size /= GET_MODE_SIZE (mode) * unroll;
13862 if (expected_size == 0)
13864 else if (expected_size > REG_BR_PROB_BASE)
13865 predict_jump (REG_BR_PROB_BASE - 1);
13867 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
13870 predict_jump (REG_BR_PROB_BASE * 80 / 100);
13871 iter = ix86_zero_extend_to_Pmode (iter);
13872 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
13873 true, OPTAB_LIB_WIDEN);
13874 if (tmp != destptr)
13875 emit_move_insn (destptr, tmp);
13878 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
13879 true, OPTAB_LIB_WIDEN);
13881 emit_move_insn (srcptr, tmp);
13883 emit_label (out_label);
13886 /* Output "rep; mov" instruction.
13887 Arguments have same meaning as for previous function */
13889 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
13890 rtx destptr, rtx srcptr,
13892 enum machine_mode mode)
13898 /* If the size is known, it is shorter to use rep movs. */
13899 if (mode == QImode && CONST_INT_P (count)
13900 && !(INTVAL (count) & 3))
13903 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
13904 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
13905 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
13906 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
13907 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
13908 if (mode != QImode)
13910 destexp = gen_rtx_ASHIFT (Pmode, countreg,
13911 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
13912 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
13913 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
13914 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
13915 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
13919 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
13920 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
13922 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
13926 /* Output "rep; stos" instruction.
13927 Arguments have same meaning as for previous function */
13929 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
13931 enum machine_mode mode)
13936 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
13937 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
13938 value = force_reg (mode, gen_lowpart (mode, value));
13939 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
13940 if (mode != QImode)
13942 destexp = gen_rtx_ASHIFT (Pmode, countreg,
13943 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
13944 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
13947 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
13948 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
13952 emit_strmov (rtx destmem, rtx srcmem,
13953 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
13955 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
13956 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
13957 emit_insn (gen_strmov (destptr, dest, srcptr, src));
13960 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
13962 expand_movmem_epilogue (rtx destmem, rtx srcmem,
13963 rtx destptr, rtx srcptr, rtx count, int max_size)
13966 if (CONST_INT_P (count))
13968 HOST_WIDE_INT countval = INTVAL (count);
13971 if ((countval & 0x10) && max_size > 16)
13975 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
13976 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
13979 gcc_unreachable ();
13982 if ((countval & 0x08) && max_size > 8)
13985 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
13988 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
13989 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
13993 if ((countval & 0x04) && max_size > 4)
13995 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
13998 if ((countval & 0x02) && max_size > 2)
14000 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
14003 if ((countval & 0x01) && max_size > 1)
14005 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
14012 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
14013 count, 1, OPTAB_DIRECT);
14014 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
14015 count, QImode, 1, 4);
14019 /* When there are stringops, we can cheaply increase dest and src pointers.
14020 Otherwise we save code size by maintaining offset (zero is readily
14021 available from preceding rep operation) and using x86 addressing modes.
14023 if (TARGET_SINGLE_STRINGOP)
14027 rtx label = ix86_expand_aligntest (count, 4, true);
14028 src = change_address (srcmem, SImode, srcptr);
14029 dest = change_address (destmem, SImode, destptr);
14030 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14031 emit_label (label);
14032 LABEL_NUSES (label) = 1;
14036 rtx label = ix86_expand_aligntest (count, 2, true);
14037 src = change_address (srcmem, HImode, srcptr);
14038 dest = change_address (destmem, HImode, destptr);
14039 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14040 emit_label (label);
14041 LABEL_NUSES (label) = 1;
14045 rtx label = ix86_expand_aligntest (count, 1, true);
14046 src = change_address (srcmem, QImode, srcptr);
14047 dest = change_address (destmem, QImode, destptr);
14048 emit_insn (gen_strmov (destptr, dest, srcptr, src));
14049 emit_label (label);
14050 LABEL_NUSES (label) = 1;
14055 rtx offset = force_reg (Pmode, const0_rtx);
14060 rtx label = ix86_expand_aligntest (count, 4, true);
14061 src = change_address (srcmem, SImode, srcptr);
14062 dest = change_address (destmem, SImode, destptr);
14063 emit_move_insn (dest, src);
14064 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
14065 true, OPTAB_LIB_WIDEN);
14067 emit_move_insn (offset, tmp);
14068 emit_label (label);
14069 LABEL_NUSES (label) = 1;
14073 rtx label = ix86_expand_aligntest (count, 2, true);
14074 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14075 src = change_address (srcmem, HImode, tmp);
14076 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14077 dest = change_address (destmem, HImode, tmp);
14078 emit_move_insn (dest, src);
14079 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
14080 true, OPTAB_LIB_WIDEN);
14082 emit_move_insn (offset, tmp);
14083 emit_label (label);
14084 LABEL_NUSES (label) = 1;
14088 rtx label = ix86_expand_aligntest (count, 1, true);
14089 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
14090 src = change_address (srcmem, QImode, tmp);
14091 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
14092 dest = change_address (destmem, QImode, tmp);
14093 emit_move_insn (dest, src);
14094 emit_label (label);
14095 LABEL_NUSES (label) = 1;
14100 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14102 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
14103 rtx count, int max_size)
14106 expand_simple_binop (counter_mode (count), AND, count,
14107 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
14108 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
14109 gen_lowpart (QImode, value), count, QImode,
14113 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
14115 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
14119 if (CONST_INT_P (count))
14121 HOST_WIDE_INT countval = INTVAL (count);
14124 if ((countval & 0x10) && max_size > 16)
14128 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
14129 emit_insn (gen_strset (destptr, dest, value));
14130 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
14131 emit_insn (gen_strset (destptr, dest, value));
14134 gcc_unreachable ();
14137 if ((countval & 0x08) && max_size > 8)
14141 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
14142 emit_insn (gen_strset (destptr, dest, value));
14146 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
14147 emit_insn (gen_strset (destptr, dest, value));
14148 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
14149 emit_insn (gen_strset (destptr, dest, value));
14153 if ((countval & 0x04) && max_size > 4)
14155 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
14156 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
14159 if ((countval & 0x02) && max_size > 2)
14161 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
14162 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
14165 if ((countval & 0x01) && max_size > 1)
14167 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
14168 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
14175 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
14180 rtx label = ix86_expand_aligntest (count, 16, true);
14183 dest = change_address (destmem, DImode, destptr);
14184 emit_insn (gen_strset (destptr, dest, value));
14185 emit_insn (gen_strset (destptr, dest, value));
14189 dest = change_address (destmem, SImode, destptr);
14190 emit_insn (gen_strset (destptr, dest, value));
14191 emit_insn (gen_strset (destptr, dest, value));
14192 emit_insn (gen_strset (destptr, dest, value));
14193 emit_insn (gen_strset (destptr, dest, value));
14195 emit_label (label);
14196 LABEL_NUSES (label) = 1;
14200 rtx label = ix86_expand_aligntest (count, 8, true);
14203 dest = change_address (destmem, DImode, destptr);
14204 emit_insn (gen_strset (destptr, dest, value));
14208 dest = change_address (destmem, SImode, destptr);
14209 emit_insn (gen_strset (destptr, dest, value));
14210 emit_insn (gen_strset (destptr, dest, value));
14212 emit_label (label);
14213 LABEL_NUSES (label) = 1;
14217 rtx label = ix86_expand_aligntest (count, 4, true);
14218 dest = change_address (destmem, SImode, destptr);
14219 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
14220 emit_label (label);
14221 LABEL_NUSES (label) = 1;
14225 rtx label = ix86_expand_aligntest (count, 2, true);
14226 dest = change_address (destmem, HImode, destptr);
14227 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
14228 emit_label (label);
14229 LABEL_NUSES (label) = 1;
14233 rtx label = ix86_expand_aligntest (count, 1, true);
14234 dest = change_address (destmem, QImode, destptr);
14235 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
14236 emit_label (label);
14237 LABEL_NUSES (label) = 1;
14241 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
14242 DESIRED_ALIGNMENT. */
14244 expand_movmem_prologue (rtx destmem, rtx srcmem,
14245 rtx destptr, rtx srcptr, rtx count,
14246 int align, int desired_alignment)
14248 if (align <= 1 && desired_alignment > 1)
14250 rtx label = ix86_expand_aligntest (destptr, 1, false);
14251 srcmem = change_address (srcmem, QImode, srcptr);
14252 destmem = change_address (destmem, QImode, destptr);
14253 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
14254 ix86_adjust_counter (count, 1);
14255 emit_label (label);
14256 LABEL_NUSES (label) = 1;
14258 if (align <= 2 && desired_alignment > 2)
14260 rtx label = ix86_expand_aligntest (destptr, 2, false);
14261 srcmem = change_address (srcmem, HImode, srcptr);
14262 destmem = change_address (destmem, HImode, destptr);
14263 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
14264 ix86_adjust_counter (count, 2);
14265 emit_label (label);
14266 LABEL_NUSES (label) = 1;
14268 if (align <= 4 && desired_alignment > 4)
14270 rtx label = ix86_expand_aligntest (destptr, 4, false);
14271 srcmem = change_address (srcmem, SImode, srcptr);
14272 destmem = change_address (destmem, SImode, destptr);
14273 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
14274 ix86_adjust_counter (count, 4);
14275 emit_label (label);
14276 LABEL_NUSES (label) = 1;
14278 gcc_assert (desired_alignment <= 8);
14281 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
14282 DESIRED_ALIGNMENT. */
14284 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
14285 int align, int desired_alignment)
14287 if (align <= 1 && desired_alignment > 1)
14289 rtx label = ix86_expand_aligntest (destptr, 1, false);
14290 destmem = change_address (destmem, QImode, destptr);
14291 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
14292 ix86_adjust_counter (count, 1);
14293 emit_label (label);
14294 LABEL_NUSES (label) = 1;
14296 if (align <= 2 && desired_alignment > 2)
14298 rtx label = ix86_expand_aligntest (destptr, 2, false);
14299 destmem = change_address (destmem, HImode, destptr);
14300 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
14301 ix86_adjust_counter (count, 2);
14302 emit_label (label);
14303 LABEL_NUSES (label) = 1;
14305 if (align <= 4 && desired_alignment > 4)
14307 rtx label = ix86_expand_aligntest (destptr, 4, false);
14308 destmem = change_address (destmem, SImode, destptr);
14309 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
14310 ix86_adjust_counter (count, 4);
14311 emit_label (label);
14312 LABEL_NUSES (label) = 1;
14314 gcc_assert (desired_alignment <= 8);
14317 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
14318 static enum stringop_alg
14319 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
14320 int *dynamic_check)
14322 const struct stringop_algs * algs;
14324 *dynamic_check = -1;
14326 algs = &ix86_cost->memset[TARGET_64BIT != 0];
14328 algs = &ix86_cost->memcpy[TARGET_64BIT != 0];
14329 if (stringop_alg != no_stringop)
14330 return stringop_alg;
14331 /* rep; movq or rep; movl is the smallest variant. */
14332 else if (optimize_size)
14334 if (!count || (count & 3))
14335 return rep_prefix_1_byte;
14337 return rep_prefix_4_byte;
14339 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
14341 else if (expected_size != -1 && expected_size < 4)
14342 return loop_1_byte;
14343 else if (expected_size != -1)
14346 enum stringop_alg alg = libcall;
14347 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
14349 gcc_assert (algs->size[i].max);
14350 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
14352 if (algs->size[i].alg != libcall)
14353 alg = algs->size[i].alg;
14354 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
14355 last non-libcall inline algorithm. */
14356 if (TARGET_INLINE_ALL_STRINGOPS)
14358 /* When the current size is best to be copied by a libcall,
14359 but we are still forced to inline, run the heuristic bellow
14360 that will pick code for medium sized blocks. */
14361 if (alg != libcall)
14366 return algs->size[i].alg;
14369 gcc_assert (TARGET_INLINE_ALL_STRINGOPS);
14371 /* When asked to inline the call anyway, try to pick meaningful choice.
14372 We look for maximal size of block that is faster to copy by hand and
14373 take blocks of at most of that size guessing that average size will
14374 be roughly half of the block.
14376 If this turns out to be bad, we might simply specify the preferred
14377 choice in ix86_costs. */
14378 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
14379 && algs->unknown_size == libcall)
14382 enum stringop_alg alg;
14385 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
14386 if (algs->size[i].alg != libcall && algs->size[i].alg)
14387 max = algs->size[i].max;
14390 alg = decide_alg (count, max / 2, memset, dynamic_check);
14391 gcc_assert (*dynamic_check == -1);
14392 gcc_assert (alg != libcall);
14393 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
14394 *dynamic_check = max;
14397 return algs->unknown_size;
14400 /* Decide on alignment. We know that the operand is already aligned to ALIGN
14401 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
14403 decide_alignment (int align,
14404 enum stringop_alg alg,
14407 int desired_align = 0;
14411 gcc_unreachable ();
14413 case unrolled_loop:
14414 desired_align = GET_MODE_SIZE (Pmode);
14416 case rep_prefix_8_byte:
14419 case rep_prefix_4_byte:
14420 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
14421 copying whole cacheline at once. */
14422 if (TARGET_PENTIUMPRO)
14427 case rep_prefix_1_byte:
14428 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
14429 copying whole cacheline at once. */
14430 if (TARGET_PENTIUMPRO)
14444 if (desired_align < align)
14445 desired_align = align;
14446 if (expected_size != -1 && expected_size < 4)
14447 desired_align = align;
14448 return desired_align;
14451 /* Return the smallest power of 2 greater than VAL. */
14453 smallest_pow2_greater_than (int val)
14461 /* Expand string move (memcpy) operation. Use i386 string operations when
14462 profitable. expand_clrmem contains similar code. The code depends upon
14463 architecture, block size and alignment, but always has the same
14466 1) Prologue guard: Conditional that jumps up to epilogues for small
14467 blocks that can be handled by epilogue alone. This is faster but
14468 also needed for correctness, since prologue assume the block is larger
14469 than the desired alignment.
14471 Optional dynamic check for size and libcall for large
14472 blocks is emitted here too, with -minline-stringops-dynamically.
14474 2) Prologue: copy first few bytes in order to get destination aligned
14475 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
14476 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
14477 We emit either a jump tree on power of two sized blocks, or a byte loop.
14479 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
14480 with specified algorithm.
14482 4) Epilogue: code copying tail of the block that is too small to be
14483 handled by main body (or up to size guarded by prologue guard). */
14486 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
14487 rtx expected_align_exp, rtx expected_size_exp)
14493 rtx jump_around_label = NULL;
14494 HOST_WIDE_INT align = 1;
14495 unsigned HOST_WIDE_INT count = 0;
14496 HOST_WIDE_INT expected_size = -1;
14497 int size_needed = 0, epilogue_size_needed;
14498 int desired_align = 0;
14499 enum stringop_alg alg;
14502 if (CONST_INT_P (align_exp))
14503 align = INTVAL (align_exp);
14504 /* i386 can do misaligned access on reasonably increased cost. */
14505 if (CONST_INT_P (expected_align_exp)
14506 && INTVAL (expected_align_exp) > align)
14507 align = INTVAL (expected_align_exp);
14508 if (CONST_INT_P (count_exp))
14509 count = expected_size = INTVAL (count_exp);
14510 if (CONST_INT_P (expected_size_exp) && count == 0)
14511 expected_size = INTVAL (expected_size_exp);
14513 /* Step 0: Decide on preferred algorithm, desired alignment and
14514 size of chunks to be copied by main loop. */
14516 alg = decide_alg (count, expected_size, false, &dynamic_check);
14517 desired_align = decide_alignment (align, alg, expected_size);
14519 if (!TARGET_ALIGN_STRINGOPS)
14520 align = desired_align;
14522 if (alg == libcall)
14524 gcc_assert (alg != no_stringop);
14526 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
14527 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
14528 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
14533 gcc_unreachable ();
14535 size_needed = GET_MODE_SIZE (Pmode);
14537 case unrolled_loop:
14538 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
14540 case rep_prefix_8_byte:
14543 case rep_prefix_4_byte:
14546 case rep_prefix_1_byte:
14552 epilogue_size_needed = size_needed;
14554 /* Step 1: Prologue guard. */
14556 /* Alignment code needs count to be in register. */
14557 if (CONST_INT_P (count_exp) && desired_align > align)
14559 enum machine_mode mode = SImode;
14560 if (TARGET_64BIT && (count & ~0xffffffff))
14562 count_exp = force_reg (mode, count_exp);
14564 gcc_assert (desired_align >= 1 && align >= 1);
14566 /* Ensure that alignment prologue won't copy past end of block. */
14567 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
14569 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
14570 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
14571 Make sure it is power of 2. */
14572 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
14574 label = gen_label_rtx ();
14575 emit_cmp_and_jump_insns (count_exp,
14576 GEN_INT (epilogue_size_needed),
14577 LTU, 0, counter_mode (count_exp), 1, label);
14578 if (GET_CODE (count_exp) == CONST_INT)
14580 else if (expected_size == -1 || expected_size < epilogue_size_needed)
14581 predict_jump (REG_BR_PROB_BASE * 60 / 100);
14583 predict_jump (REG_BR_PROB_BASE * 20 / 100);
14585 /* Emit code to decide on runtime whether library call or inline should be
14587 if (dynamic_check != -1)
14589 rtx hot_label = gen_label_rtx ();
14590 jump_around_label = gen_label_rtx ();
14591 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
14592 LEU, 0, GET_MODE (count_exp), 1, hot_label);
14593 predict_jump (REG_BR_PROB_BASE * 90 / 100);
14594 emit_block_move_via_libcall (dst, src, count_exp, false);
14595 emit_jump (jump_around_label);
14596 emit_label (hot_label);
14599 /* Step 2: Alignment prologue. */
14601 if (desired_align > align)
14603 /* Except for the first move in epilogue, we no longer know
14604 constant offset in aliasing info. It don't seems to worth
14605 the pain to maintain it for the first move, so throw away
14607 src = change_address (src, BLKmode, srcreg);
14608 dst = change_address (dst, BLKmode, destreg);
14609 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
14612 if (label && size_needed == 1)
14614 emit_label (label);
14615 LABEL_NUSES (label) = 1;
14619 /* Step 3: Main loop. */
14625 gcc_unreachable ();
14627 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
14628 count_exp, QImode, 1, expected_size);
14631 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
14632 count_exp, Pmode, 1, expected_size);
14634 case unrolled_loop:
14635 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
14636 registers for 4 temporaries anyway. */
14637 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
14638 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
14641 case rep_prefix_8_byte:
14642 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
14645 case rep_prefix_4_byte:
14646 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
14649 case rep_prefix_1_byte:
14650 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
14654 /* Adjust properly the offset of src and dest memory for aliasing. */
14655 if (CONST_INT_P (count_exp))
14657 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
14658 (count / size_needed) * size_needed);
14659 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
14660 (count / size_needed) * size_needed);
14664 src = change_address (src, BLKmode, srcreg);
14665 dst = change_address (dst, BLKmode, destreg);
14668 /* Step 4: Epilogue to copy the remaining bytes. */
14672 /* When the main loop is done, COUNT_EXP might hold original count,
14673 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
14674 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
14675 bytes. Compensate if needed. */
14677 if (size_needed < epilogue_size_needed)
14680 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
14681 GEN_INT (size_needed - 1), count_exp, 1,
14683 if (tmp != count_exp)
14684 emit_move_insn (count_exp, tmp);
14686 emit_label (label);
14687 LABEL_NUSES (label) = 1;
14690 if (count_exp != const0_rtx && epilogue_size_needed > 1)
14691 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
14692 epilogue_size_needed);
14693 if (jump_around_label)
14694 emit_label (jump_around_label);
14698 /* Helper function for memcpy. For QImode value 0xXY produce
14699 0xXYXYXYXY of wide specified by MODE. This is essentially
14700 a * 0x10101010, but we can do slightly better than
14701 synth_mult by unwinding the sequence by hand on CPUs with
14704 promote_duplicated_reg (enum machine_mode mode, rtx val)
14706 enum machine_mode valmode = GET_MODE (val);
14708 int nops = mode == DImode ? 3 : 2;
14710 gcc_assert (mode == SImode || mode == DImode);
14711 if (val == const0_rtx)
14712 return copy_to_mode_reg (mode, const0_rtx);
14713 if (CONST_INT_P (val))
14715 HOST_WIDE_INT v = INTVAL (val) & 255;
14719 if (mode == DImode)
14720 v |= (v << 16) << 16;
14721 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
14724 if (valmode == VOIDmode)
14726 if (valmode != QImode)
14727 val = gen_lowpart (QImode, val);
14728 if (mode == QImode)
14730 if (!TARGET_PARTIAL_REG_STALL)
14732 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
14733 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
14734 <= (ix86_cost->shift_const + ix86_cost->add) * nops
14735 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
14737 rtx reg = convert_modes (mode, QImode, val, true);
14738 tmp = promote_duplicated_reg (mode, const1_rtx);
14739 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
14744 rtx reg = convert_modes (mode, QImode, val, true);
14746 if (!TARGET_PARTIAL_REG_STALL)
14747 if (mode == SImode)
14748 emit_insn (gen_movsi_insv_1 (reg, reg));
14750 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
14753 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
14754 NULL, 1, OPTAB_DIRECT);
14756 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
14758 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
14759 NULL, 1, OPTAB_DIRECT);
14760 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
14761 if (mode == SImode)
14763 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
14764 NULL, 1, OPTAB_DIRECT);
14765 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
14770 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
14771 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
14772 alignment from ALIGN to DESIRED_ALIGN. */
14774 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
14779 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
14780 promoted_val = promote_duplicated_reg (DImode, val);
14781 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
14782 promoted_val = promote_duplicated_reg (SImode, val);
14783 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
14784 promoted_val = promote_duplicated_reg (HImode, val);
14786 promoted_val = val;
14788 return promoted_val;
14791 /* Expand string clear operation (bzero). Use i386 string operations when
14792 profitable. See expand_movmem comment for explanation of individual
14793 steps performed. */
14795 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
14796 rtx expected_align_exp, rtx expected_size_exp)
14801 rtx jump_around_label = NULL;
14802 HOST_WIDE_INT align = 1;
14803 unsigned HOST_WIDE_INT count = 0;
14804 HOST_WIDE_INT expected_size = -1;
14805 int size_needed = 0, epilogue_size_needed;
14806 int desired_align = 0;
14807 enum stringop_alg alg;
14808 rtx promoted_val = NULL;
14809 bool force_loopy_epilogue = false;
14812 if (CONST_INT_P (align_exp))
14813 align = INTVAL (align_exp);
14814 /* i386 can do misaligned access on reasonably increased cost. */
14815 if (CONST_INT_P (expected_align_exp)
14816 && INTVAL (expected_align_exp) > align)
14817 align = INTVAL (expected_align_exp);
14818 if (CONST_INT_P (count_exp))
14819 count = expected_size = INTVAL (count_exp);
14820 if (CONST_INT_P (expected_size_exp) && count == 0)
14821 expected_size = INTVAL (expected_size_exp);
14823 /* Step 0: Decide on preferred algorithm, desired alignment and
14824 size of chunks to be copied by main loop. */
14826 alg = decide_alg (count, expected_size, true, &dynamic_check);
14827 desired_align = decide_alignment (align, alg, expected_size);
14829 if (!TARGET_ALIGN_STRINGOPS)
14830 align = desired_align;
14832 if (alg == libcall)
14834 gcc_assert (alg != no_stringop);
14836 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
14837 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
14842 gcc_unreachable ();
14844 size_needed = GET_MODE_SIZE (Pmode);
14846 case unrolled_loop:
14847 size_needed = GET_MODE_SIZE (Pmode) * 4;
14849 case rep_prefix_8_byte:
14852 case rep_prefix_4_byte:
14855 case rep_prefix_1_byte:
14860 epilogue_size_needed = size_needed;
14862 /* Step 1: Prologue guard. */
14864 /* Alignment code needs count to be in register. */
14865 if (CONST_INT_P (count_exp) && desired_align > align)
14867 enum machine_mode mode = SImode;
14868 if (TARGET_64BIT && (count & ~0xffffffff))
14870 count_exp = force_reg (mode, count_exp);
14872 /* Do the cheap promotion to allow better CSE across the
14873 main loop and epilogue (ie one load of the big constant in the
14874 front of all code. */
14875 if (CONST_INT_P (val_exp))
14876 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
14877 desired_align, align);
14878 /* Ensure that alignment prologue won't copy past end of block. */
14879 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
14881 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
14882 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
14883 Make sure it is power of 2. */
14884 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
14886 /* To improve performance of small blocks, we jump around the VAL
14887 promoting mode. This mean that if the promoted VAL is not constant,
14888 we might not use it in the epilogue and have to use byte
14890 if (epilogue_size_needed > 2 && !promoted_val)
14891 force_loopy_epilogue = true;
14892 label = gen_label_rtx ();
14893 emit_cmp_and_jump_insns (count_exp,
14894 GEN_INT (epilogue_size_needed),
14895 LTU, 0, counter_mode (count_exp), 1, label);
14896 if (GET_CODE (count_exp) == CONST_INT)
14898 else if (expected_size == -1 || expected_size <= epilogue_size_needed)
14899 predict_jump (REG_BR_PROB_BASE * 60 / 100);
14901 predict_jump (REG_BR_PROB_BASE * 20 / 100);
14903 if (dynamic_check != -1)
14905 rtx hot_label = gen_label_rtx ();
14906 jump_around_label = gen_label_rtx ();
14907 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
14908 LEU, 0, counter_mode (count_exp), 1, hot_label);
14909 predict_jump (REG_BR_PROB_BASE * 90 / 100);
14910 set_storage_via_libcall (dst, count_exp, val_exp, false);
14911 emit_jump (jump_around_label);
14912 emit_label (hot_label);
14915 /* Step 2: Alignment prologue. */
14917 /* Do the expensive promotion once we branched off the small blocks. */
14919 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
14920 desired_align, align);
14921 gcc_assert (desired_align >= 1 && align >= 1);
14923 if (desired_align > align)
14925 /* Except for the first move in epilogue, we no longer know
14926 constant offset in aliasing info. It don't seems to worth
14927 the pain to maintain it for the first move, so throw away
14929 dst = change_address (dst, BLKmode, destreg);
14930 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
14933 if (label && size_needed == 1)
14935 emit_label (label);
14936 LABEL_NUSES (label) = 1;
14940 /* Step 3: Main loop. */
14946 gcc_unreachable ();
14948 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
14949 count_exp, QImode, 1, expected_size);
14952 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
14953 count_exp, Pmode, 1, expected_size);
14955 case unrolled_loop:
14956 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
14957 count_exp, Pmode, 4, expected_size);
14959 case rep_prefix_8_byte:
14960 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
14963 case rep_prefix_4_byte:
14964 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
14967 case rep_prefix_1_byte:
14968 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
14972 /* Adjust properly the offset of src and dest memory for aliasing. */
14973 if (CONST_INT_P (count_exp))
14974 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
14975 (count / size_needed) * size_needed);
14977 dst = change_address (dst, BLKmode, destreg);
14979 /* Step 4: Epilogue to copy the remaining bytes. */
14983 /* When the main loop is done, COUNT_EXP might hold original count,
14984 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
14985 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
14986 bytes. Compensate if needed. */
14988 if (size_needed < desired_align - align)
14991 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
14992 GEN_INT (size_needed - 1), count_exp, 1,
14994 size_needed = desired_align - align + 1;
14995 if (tmp != count_exp)
14996 emit_move_insn (count_exp, tmp);
14998 emit_label (label);
14999 LABEL_NUSES (label) = 1;
15001 if (count_exp != const0_rtx && epilogue_size_needed > 1)
15003 if (force_loopy_epilogue)
15004 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
15007 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
15010 if (jump_around_label)
15011 emit_label (jump_around_label);
15015 /* Expand the appropriate insns for doing strlen if not just doing
15018 out = result, initialized with the start address
15019 align_rtx = alignment of the address.
15020 scratch = scratch register, initialized with the startaddress when
15021 not aligned, otherwise undefined
15023 This is just the body. It needs the initializations mentioned above and
15024 some address computing at the end. These things are done in i386.md. */
15027 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
15031 rtx align_2_label = NULL_RTX;
15032 rtx align_3_label = NULL_RTX;
15033 rtx align_4_label = gen_label_rtx ();
15034 rtx end_0_label = gen_label_rtx ();
15036 rtx tmpreg = gen_reg_rtx (SImode);
15037 rtx scratch = gen_reg_rtx (SImode);
15041 if (CONST_INT_P (align_rtx))
15042 align = INTVAL (align_rtx);
15044 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
15046 /* Is there a known alignment and is it less than 4? */
15049 rtx scratch1 = gen_reg_rtx (Pmode);
15050 emit_move_insn (scratch1, out);
15051 /* Is there a known alignment and is it not 2? */
15054 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
15055 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
15057 /* Leave just the 3 lower bits. */
15058 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
15059 NULL_RTX, 0, OPTAB_WIDEN);
15061 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
15062 Pmode, 1, align_4_label);
15063 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
15064 Pmode, 1, align_2_label);
15065 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
15066 Pmode, 1, align_3_label);
15070 /* Since the alignment is 2, we have to check 2 or 0 bytes;
15071 check if is aligned to 4 - byte. */
15073 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
15074 NULL_RTX, 0, OPTAB_WIDEN);
15076 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
15077 Pmode, 1, align_4_label);
15080 mem = change_address (src, QImode, out);
15082 /* Now compare the bytes. */
15084 /* Compare the first n unaligned byte on a byte per byte basis. */
15085 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
15086 QImode, 1, end_0_label);
15088 /* Increment the address. */
15090 emit_insn (gen_adddi3 (out, out, const1_rtx));
15092 emit_insn (gen_addsi3 (out, out, const1_rtx));
15094 /* Not needed with an alignment of 2 */
15097 emit_label (align_2_label);
15099 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
15103 emit_insn (gen_adddi3 (out, out, const1_rtx));
15105 emit_insn (gen_addsi3 (out, out, const1_rtx));
15107 emit_label (align_3_label);
15110 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
15114 emit_insn (gen_adddi3 (out, out, const1_rtx));
15116 emit_insn (gen_addsi3 (out, out, const1_rtx));
15119 /* Generate loop to check 4 bytes at a time. It is not a good idea to
15120 align this loop. It gives only huge programs, but does not help to
15122 emit_label (align_4_label);
15124 mem = change_address (src, SImode, out);
15125 emit_move_insn (scratch, mem);
15127 emit_insn (gen_adddi3 (out, out, GEN_INT (4)));
15129 emit_insn (gen_addsi3 (out, out, GEN_INT (4)));
15131 /* This formula yields a nonzero result iff one of the bytes is zero.
15132 This saves three branches inside loop and many cycles. */
15134 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
15135 emit_insn (gen_one_cmplsi2 (scratch, scratch));
15136 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
15137 emit_insn (gen_andsi3 (tmpreg, tmpreg,
15138 gen_int_mode (0x80808080, SImode)));
15139 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
15144 rtx reg = gen_reg_rtx (SImode);
15145 rtx reg2 = gen_reg_rtx (Pmode);
15146 emit_move_insn (reg, tmpreg);
15147 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
15149 /* If zero is not in the first two bytes, move two bytes forward. */
15150 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
15151 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
15152 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
15153 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
15154 gen_rtx_IF_THEN_ELSE (SImode, tmp,
15157 /* Emit lea manually to avoid clobbering of flags. */
15158 emit_insn (gen_rtx_SET (SImode, reg2,
15159 gen_rtx_PLUS (Pmode, out, const2_rtx)));
15161 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
15162 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
15163 emit_insn (gen_rtx_SET (VOIDmode, out,
15164 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
15171 rtx end_2_label = gen_label_rtx ();
15172 /* Is zero in the first two bytes? */
15174 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
15175 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
15176 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
15177 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
15178 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
15180 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
15181 JUMP_LABEL (tmp) = end_2_label;
15183 /* Not in the first two. Move two bytes forward. */
15184 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
15186 emit_insn (gen_adddi3 (out, out, const2_rtx));
15188 emit_insn (gen_addsi3 (out, out, const2_rtx));
15190 emit_label (end_2_label);
15194 /* Avoid branch in fixing the byte. */
15195 tmpreg = gen_lowpart (QImode, tmpreg);
15196 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
15197 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, 17), const0_rtx);
15199 emit_insn (gen_subdi3_carry_rex64 (out, out, GEN_INT (3), cmp));
15201 emit_insn (gen_subsi3_carry (out, out, GEN_INT (3), cmp));
15203 emit_label (end_0_label);
15206 /* Expand strlen. */
15209 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
15211 rtx addr, scratch1, scratch2, scratch3, scratch4;
15213 /* The generic case of strlen expander is long. Avoid it's
15214 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
15216 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
15217 && !TARGET_INLINE_ALL_STRINGOPS
15219 && (!CONST_INT_P (align) || INTVAL (align) < 4))
15222 addr = force_reg (Pmode, XEXP (src, 0));
15223 scratch1 = gen_reg_rtx (Pmode);
15225 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
15228 /* Well it seems that some optimizer does not combine a call like
15229 foo(strlen(bar), strlen(bar));
15230 when the move and the subtraction is done here. It does calculate
15231 the length just once when these instructions are done inside of
15232 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
15233 often used and I use one fewer register for the lifetime of
15234 output_strlen_unroll() this is better. */
15236 emit_move_insn (out, addr);
15238 ix86_expand_strlensi_unroll_1 (out, src, align);
15240 /* strlensi_unroll_1 returns the address of the zero at the end of
15241 the string, like memchr(), so compute the length by subtracting
15242 the start address. */
15244 emit_insn (gen_subdi3 (out, out, addr));
15246 emit_insn (gen_subsi3 (out, out, addr));
15251 scratch2 = gen_reg_rtx (Pmode);
15252 scratch3 = gen_reg_rtx (Pmode);
15253 scratch4 = force_reg (Pmode, constm1_rtx);
15255 emit_move_insn (scratch3, addr);
15256 eoschar = force_reg (QImode, eoschar);
15258 src = replace_equiv_address_nv (src, scratch3);
15260 /* If .md starts supporting :P, this can be done in .md. */
15261 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
15262 scratch4), UNSPEC_SCAS);
15263 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
15266 emit_insn (gen_one_cmpldi2 (scratch2, scratch1));
15267 emit_insn (gen_adddi3 (out, scratch2, constm1_rtx));
15271 emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
15272 emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
15278 /* For given symbol (function) construct code to compute address of it's PLT
15279 entry in large x86-64 PIC model. */
15281 construct_plt_address (rtx symbol)
15283 rtx tmp = gen_reg_rtx (Pmode);
15284 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
15286 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15287 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
15289 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
15290 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
15295 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
15296 rtx callarg2 ATTRIBUTE_UNUSED,
15297 rtx pop, int sibcall)
15299 rtx use = NULL, call;
15301 if (pop == const0_rtx)
15303 gcc_assert (!TARGET_64BIT || !pop);
15305 if (TARGET_MACHO && !TARGET_64BIT)
15308 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
15309 fnaddr = machopic_indirect_call_target (fnaddr);
15314 /* Static functions and indirect calls don't need the pic register. */
15315 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
15316 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
15317 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
15318 use_reg (&use, pic_offset_table_rtx);
15321 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
15323 rtx al = gen_rtx_REG (QImode, 0);
15324 emit_move_insn (al, callarg2);
15325 use_reg (&use, al);
15328 if (ix86_cmodel == CM_LARGE_PIC
15329 && GET_CODE (fnaddr) == MEM
15330 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
15331 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
15332 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
15333 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
15335 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
15336 fnaddr = gen_rtx_MEM (QImode, fnaddr);
15338 if (sibcall && TARGET_64BIT
15339 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
15342 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
15343 fnaddr = gen_rtx_REG (Pmode, R11_REG);
15344 emit_move_insn (fnaddr, addr);
15345 fnaddr = gen_rtx_MEM (QImode, fnaddr);
15348 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
15350 call = gen_rtx_SET (VOIDmode, retval, call);
15353 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
15354 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
15355 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
15358 call = emit_call_insn (call);
15360 CALL_INSN_FUNCTION_USAGE (call) = use;
15364 /* Clear stack slot assignments remembered from previous functions.
15365 This is called from INIT_EXPANDERS once before RTL is emitted for each
15368 static struct machine_function *
15369 ix86_init_machine_status (void)
15371 struct machine_function *f;
15373 f = ggc_alloc_cleared (sizeof (struct machine_function));
15374 f->use_fast_prologue_epilogue_nregs = -1;
15375 f->tls_descriptor_call_expanded_p = 0;
15380 /* Return a MEM corresponding to a stack slot with mode MODE.
15381 Allocate a new slot if necessary.
15383 The RTL for a function can have several slots available: N is
15384 which slot to use. */
15387 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
15389 struct stack_local_entry *s;
15391 gcc_assert (n < MAX_386_STACK_LOCALS);
15393 for (s = ix86_stack_locals; s; s = s->next)
15394 if (s->mode == mode && s->n == n)
15395 return copy_rtx (s->rtl);
15397 s = (struct stack_local_entry *)
15398 ggc_alloc (sizeof (struct stack_local_entry));
15401 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
15403 s->next = ix86_stack_locals;
15404 ix86_stack_locals = s;
15408 /* Construct the SYMBOL_REF for the tls_get_addr function. */
15410 static GTY(()) rtx ix86_tls_symbol;
15412 ix86_tls_get_addr (void)
15415 if (!ix86_tls_symbol)
15417 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
15418 (TARGET_ANY_GNU_TLS
15420 ? "___tls_get_addr"
15421 : "__tls_get_addr");
15424 return ix86_tls_symbol;
15427 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
15429 static GTY(()) rtx ix86_tls_module_base_symbol;
15431 ix86_tls_module_base (void)
15434 if (!ix86_tls_module_base_symbol)
15436 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
15437 "_TLS_MODULE_BASE_");
15438 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
15439 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
15442 return ix86_tls_module_base_symbol;
15445 /* Calculate the length of the memory address in the instruction
15446 encoding. Does not include the one-byte modrm, opcode, or prefix. */
15449 memory_address_length (rtx addr)
15451 struct ix86_address parts;
15452 rtx base, index, disp;
15456 if (GET_CODE (addr) == PRE_DEC
15457 || GET_CODE (addr) == POST_INC
15458 || GET_CODE (addr) == PRE_MODIFY
15459 || GET_CODE (addr) == POST_MODIFY)
15462 ok = ix86_decompose_address (addr, &parts);
15465 if (parts.base && GET_CODE (parts.base) == SUBREG)
15466 parts.base = SUBREG_REG (parts.base);
15467 if (parts.index && GET_CODE (parts.index) == SUBREG)
15468 parts.index = SUBREG_REG (parts.index);
15471 index = parts.index;
15476 - esp as the base always wants an index,
15477 - ebp as the base always wants a displacement. */
15479 /* Register Indirect. */
15480 if (base && !index && !disp)
15482 /* esp (for its index) and ebp (for its displacement) need
15483 the two-byte modrm form. */
15484 if (addr == stack_pointer_rtx
15485 || addr == arg_pointer_rtx
15486 || addr == frame_pointer_rtx
15487 || addr == hard_frame_pointer_rtx)
15491 /* Direct Addressing. */
15492 else if (disp && !base && !index)
15497 /* Find the length of the displacement constant. */
15500 if (base && satisfies_constraint_K (disp))
15505 /* ebp always wants a displacement. */
15506 else if (base == hard_frame_pointer_rtx)
15509 /* An index requires the two-byte modrm form.... */
15511 /* ...like esp, which always wants an index. */
15512 || base == stack_pointer_rtx
15513 || base == arg_pointer_rtx
15514 || base == frame_pointer_rtx)
15521 /* Compute default value for "length_immediate" attribute. When SHORTFORM
15522 is set, expect that insn have 8bit immediate alternative. */
15524 ix86_attr_length_immediate_default (rtx insn, int shortform)
15528 extract_insn_cached (insn);
15529 for (i = recog_data.n_operands - 1; i >= 0; --i)
15530 if (CONSTANT_P (recog_data.operand[i]))
15533 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
15537 switch (get_attr_mode (insn))
15548 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
15553 fatal_insn ("unknown insn mode", insn);
15559 /* Compute default value for "length_address" attribute. */
15561 ix86_attr_length_address_default (rtx insn)
15565 if (get_attr_type (insn) == TYPE_LEA)
15567 rtx set = PATTERN (insn);
15569 if (GET_CODE (set) == PARALLEL)
15570 set = XVECEXP (set, 0, 0);
15572 gcc_assert (GET_CODE (set) == SET);
15574 return memory_address_length (SET_SRC (set));
15577 extract_insn_cached (insn);
15578 for (i = recog_data.n_operands - 1; i >= 0; --i)
15579 if (MEM_P (recog_data.operand[i]))
15581 return memory_address_length (XEXP (recog_data.operand[i], 0));
15587 /* Return the maximum number of instructions a cpu can issue. */
15590 ix86_issue_rate (void)
15594 case PROCESSOR_PENTIUM:
15598 case PROCESSOR_PENTIUMPRO:
15599 case PROCESSOR_PENTIUM4:
15600 case PROCESSOR_ATHLON:
15602 case PROCESSOR_AMDFAM10:
15603 case PROCESSOR_NOCONA:
15604 case PROCESSOR_GENERIC32:
15605 case PROCESSOR_GENERIC64:
15608 case PROCESSOR_CORE2:
15616 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
15617 by DEP_INSN and nothing set by DEP_INSN. */
15620 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
15624 /* Simplify the test for uninteresting insns. */
15625 if (insn_type != TYPE_SETCC
15626 && insn_type != TYPE_ICMOV
15627 && insn_type != TYPE_FCMOV
15628 && insn_type != TYPE_IBR)
15631 if ((set = single_set (dep_insn)) != 0)
15633 set = SET_DEST (set);
15636 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
15637 && XVECLEN (PATTERN (dep_insn), 0) == 2
15638 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
15639 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
15641 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
15642 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
15647 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
15650 /* This test is true if the dependent insn reads the flags but
15651 not any other potentially set register. */
15652 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
15655 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
15661 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
15662 address with operands set by DEP_INSN. */
15665 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
15669 if (insn_type == TYPE_LEA
15672 addr = PATTERN (insn);
15674 if (GET_CODE (addr) == PARALLEL)
15675 addr = XVECEXP (addr, 0, 0);
15677 gcc_assert (GET_CODE (addr) == SET);
15679 addr = SET_SRC (addr);
15684 extract_insn_cached (insn);
15685 for (i = recog_data.n_operands - 1; i >= 0; --i)
15686 if (MEM_P (recog_data.operand[i]))
15688 addr = XEXP (recog_data.operand[i], 0);
15695 return modified_in_p (addr, dep_insn);
15699 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
15701 enum attr_type insn_type, dep_insn_type;
15702 enum attr_memory memory;
15704 int dep_insn_code_number;
15706 /* Anti and output dependencies have zero cost on all CPUs. */
15707 if (REG_NOTE_KIND (link) != 0)
15710 dep_insn_code_number = recog_memoized (dep_insn);
15712 /* If we can't recognize the insns, we can't really do anything. */
15713 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
15716 insn_type = get_attr_type (insn);
15717 dep_insn_type = get_attr_type (dep_insn);
15721 case PROCESSOR_PENTIUM:
15722 /* Address Generation Interlock adds a cycle of latency. */
15723 if (ix86_agi_dependent (insn, dep_insn, insn_type))
15726 /* ??? Compares pair with jump/setcc. */
15727 if (ix86_flags_dependent (insn, dep_insn, insn_type))
15730 /* Floating point stores require value to be ready one cycle earlier. */
15731 if (insn_type == TYPE_FMOV
15732 && get_attr_memory (insn) == MEMORY_STORE
15733 && !ix86_agi_dependent (insn, dep_insn, insn_type))
15737 case PROCESSOR_PENTIUMPRO:
15738 memory = get_attr_memory (insn);
15740 /* INT->FP conversion is expensive. */
15741 if (get_attr_fp_int_src (dep_insn))
15744 /* There is one cycle extra latency between an FP op and a store. */
15745 if (insn_type == TYPE_FMOV
15746 && (set = single_set (dep_insn)) != NULL_RTX
15747 && (set2 = single_set (insn)) != NULL_RTX
15748 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
15749 && MEM_P (SET_DEST (set2)))
15752 /* Show ability of reorder buffer to hide latency of load by executing
15753 in parallel with previous instruction in case
15754 previous instruction is not needed to compute the address. */
15755 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
15756 && !ix86_agi_dependent (insn, dep_insn, insn_type))
15758 /* Claim moves to take one cycle, as core can issue one load
15759 at time and the next load can start cycle later. */
15760 if (dep_insn_type == TYPE_IMOV
15761 || dep_insn_type == TYPE_FMOV)
15769 memory = get_attr_memory (insn);
15771 /* The esp dependency is resolved before the instruction is really
15773 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
15774 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
15777 /* INT->FP conversion is expensive. */
15778 if (get_attr_fp_int_src (dep_insn))
15781 /* Show ability of reorder buffer to hide latency of load by executing
15782 in parallel with previous instruction in case
15783 previous instruction is not needed to compute the address. */
15784 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
15785 && !ix86_agi_dependent (insn, dep_insn, insn_type))
15787 /* Claim moves to take one cycle, as core can issue one load
15788 at time and the next load can start cycle later. */
15789 if (dep_insn_type == TYPE_IMOV
15790 || dep_insn_type == TYPE_FMOV)
15799 case PROCESSOR_ATHLON:
15801 case PROCESSOR_AMDFAM10:
15802 case PROCESSOR_GENERIC32:
15803 case PROCESSOR_GENERIC64:
15804 memory = get_attr_memory (insn);
15806 /* Show ability of reorder buffer to hide latency of load by executing
15807 in parallel with previous instruction in case
15808 previous instruction is not needed to compute the address. */
15809 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
15810 && !ix86_agi_dependent (insn, dep_insn, insn_type))
15812 enum attr_unit unit = get_attr_unit (insn);
15815 /* Because of the difference between the length of integer and
15816 floating unit pipeline preparation stages, the memory operands
15817 for floating point are cheaper.
15819 ??? For Athlon it the difference is most probably 2. */
15820 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
15823 loadcost = TARGET_ATHLON ? 2 : 0;
15825 if (cost >= loadcost)
15838 /* How many alternative schedules to try. This should be as wide as the
15839 scheduling freedom in the DFA, but no wider. Making this value too
15840 large results extra work for the scheduler. */
15843 ia32_multipass_dfa_lookahead (void)
15845 if (ix86_tune == PROCESSOR_PENTIUM)
15848 if (ix86_tune == PROCESSOR_PENTIUMPRO
15849 || ix86_tune == PROCESSOR_K6)
15857 /* Compute the alignment given to a constant that is being placed in memory.
15858 EXP is the constant and ALIGN is the alignment that the object would
15860 The value of this function is used instead of that alignment to align
15864 ix86_constant_alignment (tree exp, int align)
15866 if (TREE_CODE (exp) == REAL_CST)
15868 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
15870 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
15873 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
15874 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
15875 return BITS_PER_WORD;
15880 /* Compute the alignment for a static variable.
15881 TYPE is the data type, and ALIGN is the alignment that
15882 the object would ordinarily have. The value of this function is used
15883 instead of that alignment to align the object. */
15886 ix86_data_alignment (tree type, int align)
15888 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
15890 if (AGGREGATE_TYPE_P (type)
15891 && TYPE_SIZE (type)
15892 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
15893 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
15894 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
15895 && align < max_align)
15898 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
15899 to 16byte boundary. */
15902 if (AGGREGATE_TYPE_P (type)
15903 && TYPE_SIZE (type)
15904 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
15905 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
15906 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
15910 if (TREE_CODE (type) == ARRAY_TYPE)
15912 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
15914 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
15917 else if (TREE_CODE (type) == COMPLEX_TYPE)
15920 if (TYPE_MODE (type) == DCmode && align < 64)
15922 if (TYPE_MODE (type) == XCmode && align < 128)
15925 else if ((TREE_CODE (type) == RECORD_TYPE
15926 || TREE_CODE (type) == UNION_TYPE
15927 || TREE_CODE (type) == QUAL_UNION_TYPE)
15928 && TYPE_FIELDS (type))
15930 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
15932 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
15935 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
15936 || TREE_CODE (type) == INTEGER_TYPE)
15938 if (TYPE_MODE (type) == DFmode && align < 64)
15940 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
15947 /* Compute the alignment for a local variable.
15948 TYPE is the data type, and ALIGN is the alignment that
15949 the object would ordinarily have. The value of this macro is used
15950 instead of that alignment to align the object. */
15953 ix86_local_alignment (tree type, int align)
15955 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
15956 to 16byte boundary. */
15959 if (AGGREGATE_TYPE_P (type)
15960 && TYPE_SIZE (type)
15961 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
15962 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
15963 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
15966 if (TREE_CODE (type) == ARRAY_TYPE)
15968 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
15970 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
15973 else if (TREE_CODE (type) == COMPLEX_TYPE)
15975 if (TYPE_MODE (type) == DCmode && align < 64)
15977 if (TYPE_MODE (type) == XCmode && align < 128)
15980 else if ((TREE_CODE (type) == RECORD_TYPE
15981 || TREE_CODE (type) == UNION_TYPE
15982 || TREE_CODE (type) == QUAL_UNION_TYPE)
15983 && TYPE_FIELDS (type))
15985 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
15987 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
15990 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
15991 || TREE_CODE (type) == INTEGER_TYPE)
15994 if (TYPE_MODE (type) == DFmode && align < 64)
15996 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
16002 /* Emit RTL insns to initialize the variable parts of a trampoline.
16003 FNADDR is an RTX for the address of the function's pure code.
16004 CXT is an RTX for the static chain value for the function. */
16006 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
16010 /* Compute offset from the end of the jmp to the target function. */
16011 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
16012 plus_constant (tramp, 10),
16013 NULL_RTX, 1, OPTAB_DIRECT);
16014 emit_move_insn (gen_rtx_MEM (QImode, tramp),
16015 gen_int_mode (0xb9, QImode));
16016 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
16017 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
16018 gen_int_mode (0xe9, QImode));
16019 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
16024 /* Try to load address using shorter movl instead of movabs.
16025 We may want to support movq for kernel mode, but kernel does not use
16026 trampolines at the moment. */
16027 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
16029 fnaddr = copy_to_mode_reg (DImode, fnaddr);
16030 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16031 gen_int_mode (0xbb41, HImode));
16032 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
16033 gen_lowpart (SImode, fnaddr));
16038 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16039 gen_int_mode (0xbb49, HImode));
16040 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16044 /* Load static chain using movabs to r10. */
16045 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16046 gen_int_mode (0xba49, HImode));
16047 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
16050 /* Jump to the r11 */
16051 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
16052 gen_int_mode (0xff49, HImode));
16053 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
16054 gen_int_mode (0xe3, QImode));
16056 gcc_assert (offset <= TRAMPOLINE_SIZE);
16059 #ifdef ENABLE_EXECUTE_STACK
16060 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
16061 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
16065 /* Codes for all the SSE/MMX builtins. */
16068 IX86_BUILTIN_ADDPS,
16069 IX86_BUILTIN_ADDSS,
16070 IX86_BUILTIN_DIVPS,
16071 IX86_BUILTIN_DIVSS,
16072 IX86_BUILTIN_MULPS,
16073 IX86_BUILTIN_MULSS,
16074 IX86_BUILTIN_SUBPS,
16075 IX86_BUILTIN_SUBSS,
16077 IX86_BUILTIN_CMPEQPS,
16078 IX86_BUILTIN_CMPLTPS,
16079 IX86_BUILTIN_CMPLEPS,
16080 IX86_BUILTIN_CMPGTPS,
16081 IX86_BUILTIN_CMPGEPS,
16082 IX86_BUILTIN_CMPNEQPS,
16083 IX86_BUILTIN_CMPNLTPS,
16084 IX86_BUILTIN_CMPNLEPS,
16085 IX86_BUILTIN_CMPNGTPS,
16086 IX86_BUILTIN_CMPNGEPS,
16087 IX86_BUILTIN_CMPORDPS,
16088 IX86_BUILTIN_CMPUNORDPS,
16089 IX86_BUILTIN_CMPEQSS,
16090 IX86_BUILTIN_CMPLTSS,
16091 IX86_BUILTIN_CMPLESS,
16092 IX86_BUILTIN_CMPNEQSS,
16093 IX86_BUILTIN_CMPNLTSS,
16094 IX86_BUILTIN_CMPNLESS,
16095 IX86_BUILTIN_CMPNGTSS,
16096 IX86_BUILTIN_CMPNGESS,
16097 IX86_BUILTIN_CMPORDSS,
16098 IX86_BUILTIN_CMPUNORDSS,
16100 IX86_BUILTIN_COMIEQSS,
16101 IX86_BUILTIN_COMILTSS,
16102 IX86_BUILTIN_COMILESS,
16103 IX86_BUILTIN_COMIGTSS,
16104 IX86_BUILTIN_COMIGESS,
16105 IX86_BUILTIN_COMINEQSS,
16106 IX86_BUILTIN_UCOMIEQSS,
16107 IX86_BUILTIN_UCOMILTSS,
16108 IX86_BUILTIN_UCOMILESS,
16109 IX86_BUILTIN_UCOMIGTSS,
16110 IX86_BUILTIN_UCOMIGESS,
16111 IX86_BUILTIN_UCOMINEQSS,
16113 IX86_BUILTIN_CVTPI2PS,
16114 IX86_BUILTIN_CVTPS2PI,
16115 IX86_BUILTIN_CVTSI2SS,
16116 IX86_BUILTIN_CVTSI642SS,
16117 IX86_BUILTIN_CVTSS2SI,
16118 IX86_BUILTIN_CVTSS2SI64,
16119 IX86_BUILTIN_CVTTPS2PI,
16120 IX86_BUILTIN_CVTTSS2SI,
16121 IX86_BUILTIN_CVTTSS2SI64,
16123 IX86_BUILTIN_MAXPS,
16124 IX86_BUILTIN_MAXSS,
16125 IX86_BUILTIN_MINPS,
16126 IX86_BUILTIN_MINSS,
16128 IX86_BUILTIN_LOADUPS,
16129 IX86_BUILTIN_STOREUPS,
16130 IX86_BUILTIN_MOVSS,
16132 IX86_BUILTIN_MOVHLPS,
16133 IX86_BUILTIN_MOVLHPS,
16134 IX86_BUILTIN_LOADHPS,
16135 IX86_BUILTIN_LOADLPS,
16136 IX86_BUILTIN_STOREHPS,
16137 IX86_BUILTIN_STORELPS,
16139 IX86_BUILTIN_MASKMOVQ,
16140 IX86_BUILTIN_MOVMSKPS,
16141 IX86_BUILTIN_PMOVMSKB,
16143 IX86_BUILTIN_MOVNTPS,
16144 IX86_BUILTIN_MOVNTQ,
16146 IX86_BUILTIN_LOADDQU,
16147 IX86_BUILTIN_STOREDQU,
16149 IX86_BUILTIN_PACKSSWB,
16150 IX86_BUILTIN_PACKSSDW,
16151 IX86_BUILTIN_PACKUSWB,
16153 IX86_BUILTIN_PADDB,
16154 IX86_BUILTIN_PADDW,
16155 IX86_BUILTIN_PADDD,
16156 IX86_BUILTIN_PADDQ,
16157 IX86_BUILTIN_PADDSB,
16158 IX86_BUILTIN_PADDSW,
16159 IX86_BUILTIN_PADDUSB,
16160 IX86_BUILTIN_PADDUSW,
16161 IX86_BUILTIN_PSUBB,
16162 IX86_BUILTIN_PSUBW,
16163 IX86_BUILTIN_PSUBD,
16164 IX86_BUILTIN_PSUBQ,
16165 IX86_BUILTIN_PSUBSB,
16166 IX86_BUILTIN_PSUBSW,
16167 IX86_BUILTIN_PSUBUSB,
16168 IX86_BUILTIN_PSUBUSW,
16171 IX86_BUILTIN_PANDN,
16175 IX86_BUILTIN_PAVGB,
16176 IX86_BUILTIN_PAVGW,
16178 IX86_BUILTIN_PCMPEQB,
16179 IX86_BUILTIN_PCMPEQW,
16180 IX86_BUILTIN_PCMPEQD,
16181 IX86_BUILTIN_PCMPGTB,
16182 IX86_BUILTIN_PCMPGTW,
16183 IX86_BUILTIN_PCMPGTD,
16185 IX86_BUILTIN_PMADDWD,
16187 IX86_BUILTIN_PMAXSW,
16188 IX86_BUILTIN_PMAXUB,
16189 IX86_BUILTIN_PMINSW,
16190 IX86_BUILTIN_PMINUB,
16192 IX86_BUILTIN_PMULHUW,
16193 IX86_BUILTIN_PMULHW,
16194 IX86_BUILTIN_PMULLW,
16196 IX86_BUILTIN_PSADBW,
16197 IX86_BUILTIN_PSHUFW,
16199 IX86_BUILTIN_PSLLW,
16200 IX86_BUILTIN_PSLLD,
16201 IX86_BUILTIN_PSLLQ,
16202 IX86_BUILTIN_PSRAW,
16203 IX86_BUILTIN_PSRAD,
16204 IX86_BUILTIN_PSRLW,
16205 IX86_BUILTIN_PSRLD,
16206 IX86_BUILTIN_PSRLQ,
16207 IX86_BUILTIN_PSLLWI,
16208 IX86_BUILTIN_PSLLDI,
16209 IX86_BUILTIN_PSLLQI,
16210 IX86_BUILTIN_PSRAWI,
16211 IX86_BUILTIN_PSRADI,
16212 IX86_BUILTIN_PSRLWI,
16213 IX86_BUILTIN_PSRLDI,
16214 IX86_BUILTIN_PSRLQI,
16216 IX86_BUILTIN_PUNPCKHBW,
16217 IX86_BUILTIN_PUNPCKHWD,
16218 IX86_BUILTIN_PUNPCKHDQ,
16219 IX86_BUILTIN_PUNPCKLBW,
16220 IX86_BUILTIN_PUNPCKLWD,
16221 IX86_BUILTIN_PUNPCKLDQ,
16223 IX86_BUILTIN_SHUFPS,
16225 IX86_BUILTIN_RCPPS,
16226 IX86_BUILTIN_RCPSS,
16227 IX86_BUILTIN_RSQRTPS,
16228 IX86_BUILTIN_RSQRTSS,
16229 IX86_BUILTIN_SQRTPS,
16230 IX86_BUILTIN_SQRTSS,
16232 IX86_BUILTIN_UNPCKHPS,
16233 IX86_BUILTIN_UNPCKLPS,
16235 IX86_BUILTIN_ANDPS,
16236 IX86_BUILTIN_ANDNPS,
16238 IX86_BUILTIN_XORPS,
16241 IX86_BUILTIN_LDMXCSR,
16242 IX86_BUILTIN_STMXCSR,
16243 IX86_BUILTIN_SFENCE,
16245 /* 3DNow! Original */
16246 IX86_BUILTIN_FEMMS,
16247 IX86_BUILTIN_PAVGUSB,
16248 IX86_BUILTIN_PF2ID,
16249 IX86_BUILTIN_PFACC,
16250 IX86_BUILTIN_PFADD,
16251 IX86_BUILTIN_PFCMPEQ,
16252 IX86_BUILTIN_PFCMPGE,
16253 IX86_BUILTIN_PFCMPGT,
16254 IX86_BUILTIN_PFMAX,
16255 IX86_BUILTIN_PFMIN,
16256 IX86_BUILTIN_PFMUL,
16257 IX86_BUILTIN_PFRCP,
16258 IX86_BUILTIN_PFRCPIT1,
16259 IX86_BUILTIN_PFRCPIT2,
16260 IX86_BUILTIN_PFRSQIT1,
16261 IX86_BUILTIN_PFRSQRT,
16262 IX86_BUILTIN_PFSUB,
16263 IX86_BUILTIN_PFSUBR,
16264 IX86_BUILTIN_PI2FD,
16265 IX86_BUILTIN_PMULHRW,
16267 /* 3DNow! Athlon Extensions */
16268 IX86_BUILTIN_PF2IW,
16269 IX86_BUILTIN_PFNACC,
16270 IX86_BUILTIN_PFPNACC,
16271 IX86_BUILTIN_PI2FW,
16272 IX86_BUILTIN_PSWAPDSI,
16273 IX86_BUILTIN_PSWAPDSF,
16276 IX86_BUILTIN_ADDPD,
16277 IX86_BUILTIN_ADDSD,
16278 IX86_BUILTIN_DIVPD,
16279 IX86_BUILTIN_DIVSD,
16280 IX86_BUILTIN_MULPD,
16281 IX86_BUILTIN_MULSD,
16282 IX86_BUILTIN_SUBPD,
16283 IX86_BUILTIN_SUBSD,
16285 IX86_BUILTIN_CMPEQPD,
16286 IX86_BUILTIN_CMPLTPD,
16287 IX86_BUILTIN_CMPLEPD,
16288 IX86_BUILTIN_CMPGTPD,
16289 IX86_BUILTIN_CMPGEPD,
16290 IX86_BUILTIN_CMPNEQPD,
16291 IX86_BUILTIN_CMPNLTPD,
16292 IX86_BUILTIN_CMPNLEPD,
16293 IX86_BUILTIN_CMPNGTPD,
16294 IX86_BUILTIN_CMPNGEPD,
16295 IX86_BUILTIN_CMPORDPD,
16296 IX86_BUILTIN_CMPUNORDPD,
16297 IX86_BUILTIN_CMPEQSD,
16298 IX86_BUILTIN_CMPLTSD,
16299 IX86_BUILTIN_CMPLESD,
16300 IX86_BUILTIN_CMPNEQSD,
16301 IX86_BUILTIN_CMPNLTSD,
16302 IX86_BUILTIN_CMPNLESD,
16303 IX86_BUILTIN_CMPORDSD,
16304 IX86_BUILTIN_CMPUNORDSD,
16306 IX86_BUILTIN_COMIEQSD,
16307 IX86_BUILTIN_COMILTSD,
16308 IX86_BUILTIN_COMILESD,
16309 IX86_BUILTIN_COMIGTSD,
16310 IX86_BUILTIN_COMIGESD,
16311 IX86_BUILTIN_COMINEQSD,
16312 IX86_BUILTIN_UCOMIEQSD,
16313 IX86_BUILTIN_UCOMILTSD,
16314 IX86_BUILTIN_UCOMILESD,
16315 IX86_BUILTIN_UCOMIGTSD,
16316 IX86_BUILTIN_UCOMIGESD,
16317 IX86_BUILTIN_UCOMINEQSD,
16319 IX86_BUILTIN_MAXPD,
16320 IX86_BUILTIN_MAXSD,
16321 IX86_BUILTIN_MINPD,
16322 IX86_BUILTIN_MINSD,
16324 IX86_BUILTIN_ANDPD,
16325 IX86_BUILTIN_ANDNPD,
16327 IX86_BUILTIN_XORPD,
16329 IX86_BUILTIN_SQRTPD,
16330 IX86_BUILTIN_SQRTSD,
16332 IX86_BUILTIN_UNPCKHPD,
16333 IX86_BUILTIN_UNPCKLPD,
16335 IX86_BUILTIN_SHUFPD,
16337 IX86_BUILTIN_LOADUPD,
16338 IX86_BUILTIN_STOREUPD,
16339 IX86_BUILTIN_MOVSD,
16341 IX86_BUILTIN_LOADHPD,
16342 IX86_BUILTIN_LOADLPD,
16344 IX86_BUILTIN_CVTDQ2PD,
16345 IX86_BUILTIN_CVTDQ2PS,
16347 IX86_BUILTIN_CVTPD2DQ,
16348 IX86_BUILTIN_CVTPD2PI,
16349 IX86_BUILTIN_CVTPD2PS,
16350 IX86_BUILTIN_CVTTPD2DQ,
16351 IX86_BUILTIN_CVTTPD2PI,
16353 IX86_BUILTIN_CVTPI2PD,
16354 IX86_BUILTIN_CVTSI2SD,
16355 IX86_BUILTIN_CVTSI642SD,
16357 IX86_BUILTIN_CVTSD2SI,
16358 IX86_BUILTIN_CVTSD2SI64,
16359 IX86_BUILTIN_CVTSD2SS,
16360 IX86_BUILTIN_CVTSS2SD,
16361 IX86_BUILTIN_CVTTSD2SI,
16362 IX86_BUILTIN_CVTTSD2SI64,
16364 IX86_BUILTIN_CVTPS2DQ,
16365 IX86_BUILTIN_CVTPS2PD,
16366 IX86_BUILTIN_CVTTPS2DQ,
16368 IX86_BUILTIN_MOVNTI,
16369 IX86_BUILTIN_MOVNTPD,
16370 IX86_BUILTIN_MOVNTDQ,
16373 IX86_BUILTIN_MASKMOVDQU,
16374 IX86_BUILTIN_MOVMSKPD,
16375 IX86_BUILTIN_PMOVMSKB128,
16377 IX86_BUILTIN_PACKSSWB128,
16378 IX86_BUILTIN_PACKSSDW128,
16379 IX86_BUILTIN_PACKUSWB128,
16381 IX86_BUILTIN_PADDB128,
16382 IX86_BUILTIN_PADDW128,
16383 IX86_BUILTIN_PADDD128,
16384 IX86_BUILTIN_PADDQ128,
16385 IX86_BUILTIN_PADDSB128,
16386 IX86_BUILTIN_PADDSW128,
16387 IX86_BUILTIN_PADDUSB128,
16388 IX86_BUILTIN_PADDUSW128,
16389 IX86_BUILTIN_PSUBB128,
16390 IX86_BUILTIN_PSUBW128,
16391 IX86_BUILTIN_PSUBD128,
16392 IX86_BUILTIN_PSUBQ128,
16393 IX86_BUILTIN_PSUBSB128,
16394 IX86_BUILTIN_PSUBSW128,
16395 IX86_BUILTIN_PSUBUSB128,
16396 IX86_BUILTIN_PSUBUSW128,
16398 IX86_BUILTIN_PAND128,
16399 IX86_BUILTIN_PANDN128,
16400 IX86_BUILTIN_POR128,
16401 IX86_BUILTIN_PXOR128,
16403 IX86_BUILTIN_PAVGB128,
16404 IX86_BUILTIN_PAVGW128,
16406 IX86_BUILTIN_PCMPEQB128,
16407 IX86_BUILTIN_PCMPEQW128,
16408 IX86_BUILTIN_PCMPEQD128,
16409 IX86_BUILTIN_PCMPGTB128,
16410 IX86_BUILTIN_PCMPGTW128,
16411 IX86_BUILTIN_PCMPGTD128,
16413 IX86_BUILTIN_PMADDWD128,
16415 IX86_BUILTIN_PMAXSW128,
16416 IX86_BUILTIN_PMAXUB128,
16417 IX86_BUILTIN_PMINSW128,
16418 IX86_BUILTIN_PMINUB128,
16420 IX86_BUILTIN_PMULUDQ,
16421 IX86_BUILTIN_PMULUDQ128,
16422 IX86_BUILTIN_PMULHUW128,
16423 IX86_BUILTIN_PMULHW128,
16424 IX86_BUILTIN_PMULLW128,
16426 IX86_BUILTIN_PSADBW128,
16427 IX86_BUILTIN_PSHUFHW,
16428 IX86_BUILTIN_PSHUFLW,
16429 IX86_BUILTIN_PSHUFD,
16431 IX86_BUILTIN_PSLLDQI128,
16432 IX86_BUILTIN_PSLLWI128,
16433 IX86_BUILTIN_PSLLDI128,
16434 IX86_BUILTIN_PSLLQI128,
16435 IX86_BUILTIN_PSRAWI128,
16436 IX86_BUILTIN_PSRADI128,
16437 IX86_BUILTIN_PSRLDQI128,
16438 IX86_BUILTIN_PSRLWI128,
16439 IX86_BUILTIN_PSRLDI128,
16440 IX86_BUILTIN_PSRLQI128,
16442 IX86_BUILTIN_PSLLDQ128,
16443 IX86_BUILTIN_PSLLW128,
16444 IX86_BUILTIN_PSLLD128,
16445 IX86_BUILTIN_PSLLQ128,
16446 IX86_BUILTIN_PSRAW128,
16447 IX86_BUILTIN_PSRAD128,
16448 IX86_BUILTIN_PSRLW128,
16449 IX86_BUILTIN_PSRLD128,
16450 IX86_BUILTIN_PSRLQ128,
16452 IX86_BUILTIN_PUNPCKHBW128,
16453 IX86_BUILTIN_PUNPCKHWD128,
16454 IX86_BUILTIN_PUNPCKHDQ128,
16455 IX86_BUILTIN_PUNPCKHQDQ128,
16456 IX86_BUILTIN_PUNPCKLBW128,
16457 IX86_BUILTIN_PUNPCKLWD128,
16458 IX86_BUILTIN_PUNPCKLDQ128,
16459 IX86_BUILTIN_PUNPCKLQDQ128,
16461 IX86_BUILTIN_CLFLUSH,
16462 IX86_BUILTIN_MFENCE,
16463 IX86_BUILTIN_LFENCE,
16465 /* Prescott New Instructions. */
16466 IX86_BUILTIN_ADDSUBPS,
16467 IX86_BUILTIN_HADDPS,
16468 IX86_BUILTIN_HSUBPS,
16469 IX86_BUILTIN_MOVSHDUP,
16470 IX86_BUILTIN_MOVSLDUP,
16471 IX86_BUILTIN_ADDSUBPD,
16472 IX86_BUILTIN_HADDPD,
16473 IX86_BUILTIN_HSUBPD,
16474 IX86_BUILTIN_LDDQU,
16476 IX86_BUILTIN_MONITOR,
16477 IX86_BUILTIN_MWAIT,
16480 IX86_BUILTIN_PHADDW,
16481 IX86_BUILTIN_PHADDD,
16482 IX86_BUILTIN_PHADDSW,
16483 IX86_BUILTIN_PHSUBW,
16484 IX86_BUILTIN_PHSUBD,
16485 IX86_BUILTIN_PHSUBSW,
16486 IX86_BUILTIN_PMADDUBSW,
16487 IX86_BUILTIN_PMULHRSW,
16488 IX86_BUILTIN_PSHUFB,
16489 IX86_BUILTIN_PSIGNB,
16490 IX86_BUILTIN_PSIGNW,
16491 IX86_BUILTIN_PSIGND,
16492 IX86_BUILTIN_PALIGNR,
16493 IX86_BUILTIN_PABSB,
16494 IX86_BUILTIN_PABSW,
16495 IX86_BUILTIN_PABSD,
16497 IX86_BUILTIN_PHADDW128,
16498 IX86_BUILTIN_PHADDD128,
16499 IX86_BUILTIN_PHADDSW128,
16500 IX86_BUILTIN_PHSUBW128,
16501 IX86_BUILTIN_PHSUBD128,
16502 IX86_BUILTIN_PHSUBSW128,
16503 IX86_BUILTIN_PMADDUBSW128,
16504 IX86_BUILTIN_PMULHRSW128,
16505 IX86_BUILTIN_PSHUFB128,
16506 IX86_BUILTIN_PSIGNB128,
16507 IX86_BUILTIN_PSIGNW128,
16508 IX86_BUILTIN_PSIGND128,
16509 IX86_BUILTIN_PALIGNR128,
16510 IX86_BUILTIN_PABSB128,
16511 IX86_BUILTIN_PABSW128,
16512 IX86_BUILTIN_PABSD128,
16514 /* AMDFAM10 - SSE4A New Instructions. */
16515 IX86_BUILTIN_MOVNTSD,
16516 IX86_BUILTIN_MOVNTSS,
16517 IX86_BUILTIN_EXTRQI,
16518 IX86_BUILTIN_EXTRQ,
16519 IX86_BUILTIN_INSERTQI,
16520 IX86_BUILTIN_INSERTQ,
16523 IX86_BUILTIN_BLENDPD,
16524 IX86_BUILTIN_BLENDPS,
16525 IX86_BUILTIN_BLENDVPD,
16526 IX86_BUILTIN_BLENDVPS,
16527 IX86_BUILTIN_PBLENDVB128,
16528 IX86_BUILTIN_PBLENDW128,
16533 IX86_BUILTIN_INSERTPS128,
16535 IX86_BUILTIN_MOVNTDQA,
16536 IX86_BUILTIN_MPSADBW128,
16537 IX86_BUILTIN_PACKUSDW128,
16538 IX86_BUILTIN_PCMPEQQ,
16539 IX86_BUILTIN_PHMINPOSUW128,
16541 IX86_BUILTIN_PMAXSB128,
16542 IX86_BUILTIN_PMAXSD128,
16543 IX86_BUILTIN_PMAXUD128,
16544 IX86_BUILTIN_PMAXUW128,
16546 IX86_BUILTIN_PMINSB128,
16547 IX86_BUILTIN_PMINSD128,
16548 IX86_BUILTIN_PMINUD128,
16549 IX86_BUILTIN_PMINUW128,
16551 IX86_BUILTIN_PMOVSXBW128,
16552 IX86_BUILTIN_PMOVSXBD128,
16553 IX86_BUILTIN_PMOVSXBQ128,
16554 IX86_BUILTIN_PMOVSXWD128,
16555 IX86_BUILTIN_PMOVSXWQ128,
16556 IX86_BUILTIN_PMOVSXDQ128,
16558 IX86_BUILTIN_PMOVZXBW128,
16559 IX86_BUILTIN_PMOVZXBD128,
16560 IX86_BUILTIN_PMOVZXBQ128,
16561 IX86_BUILTIN_PMOVZXWD128,
16562 IX86_BUILTIN_PMOVZXWQ128,
16563 IX86_BUILTIN_PMOVZXDQ128,
16565 IX86_BUILTIN_PMULDQ128,
16566 IX86_BUILTIN_PMULLD128,
16568 IX86_BUILTIN_ROUNDPD,
16569 IX86_BUILTIN_ROUNDPS,
16570 IX86_BUILTIN_ROUNDSD,
16571 IX86_BUILTIN_ROUNDSS,
16573 IX86_BUILTIN_PTESTZ,
16574 IX86_BUILTIN_PTESTC,
16575 IX86_BUILTIN_PTESTNZC,
16577 IX86_BUILTIN_VEC_INIT_V2SI,
16578 IX86_BUILTIN_VEC_INIT_V4HI,
16579 IX86_BUILTIN_VEC_INIT_V8QI,
16580 IX86_BUILTIN_VEC_EXT_V2DF,
16581 IX86_BUILTIN_VEC_EXT_V2DI,
16582 IX86_BUILTIN_VEC_EXT_V4SF,
16583 IX86_BUILTIN_VEC_EXT_V4SI,
16584 IX86_BUILTIN_VEC_EXT_V8HI,
16585 IX86_BUILTIN_VEC_EXT_V2SI,
16586 IX86_BUILTIN_VEC_EXT_V4HI,
16587 IX86_BUILTIN_VEC_EXT_V16QI,
16588 IX86_BUILTIN_VEC_SET_V2DI,
16589 IX86_BUILTIN_VEC_SET_V4SF,
16590 IX86_BUILTIN_VEC_SET_V4SI,
16591 IX86_BUILTIN_VEC_SET_V8HI,
16592 IX86_BUILTIN_VEC_SET_V4HI,
16593 IX86_BUILTIN_VEC_SET_V16QI,
16598 /* Table for the ix86 builtin decls. */
16599 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
16601 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Do so,
16602 * if the target_flags include one of MASK. Stores the function decl
16603 * in the ix86_builtins array.
16604 * Returns the function decl or NULL_TREE, if the builtin was not added. */
16607 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
16609 tree decl = NULL_TREE;
16611 if (mask & target_flags
16612 && (!(mask & MASK_64BIT) || TARGET_64BIT))
16614 decl = add_builtin_function (name, type, code, BUILT_IN_MD,
16616 ix86_builtins[(int) code] = decl;
16622 /* Like def_builtin, but also marks the function decl "const". */
16625 def_builtin_const (int mask, const char *name, tree type,
16626 enum ix86_builtins code)
16628 tree decl = def_builtin (mask, name, type, code);
16630 TREE_READONLY (decl) = 1;
16634 /* Bits for builtin_description.flag. */
16636 /* Set when we don't support the comparison natively, and should
16637 swap_comparison in order to support it. */
16638 #define BUILTIN_DESC_SWAP_OPERANDS 1
16640 struct builtin_description
16642 const unsigned int mask;
16643 const enum insn_code icode;
16644 const char *const name;
16645 const enum ix86_builtins code;
16646 const enum rtx_code comparison;
16647 const unsigned int flag;
16650 static const struct builtin_description bdesc_comi[] =
16652 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
16653 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
16654 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
16655 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
16656 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
16657 { MASK_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
16658 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
16659 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
16660 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
16661 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
16662 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
16663 { MASK_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
16664 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
16665 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
16666 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
16667 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
16668 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
16669 { MASK_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
16670 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
16671 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
16672 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
16673 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
16674 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
16675 { MASK_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
16678 static const struct builtin_description bdesc_ptest[] =
16681 { MASK_SSE4_1, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, 0 },
16682 { MASK_SSE4_1, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, 0 },
16683 { MASK_SSE4_1, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, 0 },
16686 /* SSE builtins with 3 arguments and the last argument must be a 8 bit
16687 constant or xmm0. */
16688 static const struct builtin_description bdesc_sse_3arg[] =
16691 { MASK_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, 0, 0 },
16692 { MASK_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, 0, 0 },
16693 { MASK_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, 0, 0 },
16694 { MASK_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, 0, 0 },
16695 { MASK_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, 0, 0 },
16696 { MASK_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, 0, 0 },
16697 { MASK_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, 0, 0 },
16698 { MASK_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, 0, 0 },
16699 { MASK_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, 0, 0 },
16700 { MASK_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, 0, 0 },
16701 { MASK_SSE4_1, CODE_FOR_sse4_1_roundsd, 0, IX86_BUILTIN_ROUNDSD, 0, 0 },
16702 { MASK_SSE4_1, CODE_FOR_sse4_1_roundss, 0, IX86_BUILTIN_ROUNDSS, 0, 0 },
16705 static const struct builtin_description bdesc_2arg[] =
16708 { MASK_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, 0, 0 },
16709 { MASK_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, 0, 0 },
16710 { MASK_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, 0, 0 },
16711 { MASK_SSE, CODE_FOR_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, 0, 0 },
16712 { MASK_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, 0, 0 },
16713 { MASK_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, 0, 0 },
16714 { MASK_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, 0, 0 },
16715 { MASK_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, 0, 0 },
16717 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
16718 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
16719 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
16720 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT,
16721 BUILTIN_DESC_SWAP_OPERANDS },
16722 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE,
16723 BUILTIN_DESC_SWAP_OPERANDS },
16724 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
16725 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 },
16726 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 },
16727 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 },
16728 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE,
16729 BUILTIN_DESC_SWAP_OPERANDS },
16730 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT,
16731 BUILTIN_DESC_SWAP_OPERANDS },
16732 { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 },
16733 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
16734 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
16735 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 },
16736 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 },
16737 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 },
16738 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 },
16739 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 },
16740 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE,
16741 BUILTIN_DESC_SWAP_OPERANDS },
16742 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT,
16743 BUILTIN_DESC_SWAP_OPERANDS },
16744 { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, 0 },
16746 { MASK_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, 0, 0 },
16747 { MASK_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, 0, 0 },
16748 { MASK_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, 0, 0 },
16749 { MASK_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, 0, 0 },
16751 { MASK_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, 0, 0 },
16752 { MASK_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, 0, 0 },
16753 { MASK_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, 0, 0 },
16754 { MASK_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, 0, 0 },
16756 { MASK_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, 0, 0 },
16757 { MASK_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, 0, 0 },
16758 { MASK_SSE, CODE_FOR_sse_movlhps, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, 0, 0 },
16759 { MASK_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, 0, 0 },
16760 { MASK_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, 0, 0 },
16763 { MASK_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, 0, 0 },
16764 { MASK_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, 0, 0 },
16765 { MASK_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, 0, 0 },
16766 { MASK_SSE2, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, 0, 0 },
16767 { MASK_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, 0, 0 },
16768 { MASK_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, 0, 0 },
16769 { MASK_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, 0, 0 },
16770 { MASK_SSE2, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, 0, 0 },
16772 { MASK_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, 0, 0 },
16773 { MASK_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, 0, 0 },
16774 { MASK_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, 0, 0 },
16775 { MASK_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, 0, 0 },
16776 { MASK_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, 0, 0 },
16777 { MASK_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, 0, 0 },
16778 { MASK_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, 0, 0 },
16779 { MASK_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, 0, 0 },
16781 { MASK_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, 0, 0 },
16782 { MASK_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, 0, 0 },
16783 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, 0, 0 },
16785 { MASK_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, 0, 0 },
16786 { MASK_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, 0, 0 },
16787 { MASK_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, 0, 0 },
16788 { MASK_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, 0, 0 },
16790 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, 0, 0 },
16791 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, 0, 0 },
16793 { MASK_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, 0, 0 },
16794 { MASK_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, 0, 0 },
16795 { MASK_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, 0, 0 },
16796 { MASK_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, 0, 0 },
16797 { MASK_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, 0, 0 },
16798 { MASK_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, 0, 0 },
16800 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, 0, 0 },
16801 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, 0, 0 },
16802 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, 0, 0 },
16803 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, 0, 0 },
16805 { MASK_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, 0, 0 },
16806 { MASK_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, 0, 0 },
16807 { MASK_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, 0, 0 },
16808 { MASK_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, 0, 0 },
16809 { MASK_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, 0, 0 },
16810 { MASK_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, 0, 0 },
16813 { MASK_MMX, CODE_FOR_mmx_packsswb, 0, IX86_BUILTIN_PACKSSWB, 0, 0 },
16814 { MASK_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, 0, 0 },
16815 { MASK_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, 0, 0 },
16817 { MASK_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, 0, 0 },
16818 { MASK_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, 0, 0 },
16819 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, 0, 0 },
16821 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLW, 0, 0 },
16822 { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLWI, 0, 0 },
16823 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLD, 0, 0 },
16824 { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLDI, 0, 0 },
16825 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQ, 0, 0 },
16826 { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQI, 0, 0 },
16828 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLW, 0, 0 },
16829 { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLWI, 0, 0 },
16830 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLD, 0, 0 },
16831 { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLDI, 0, 0 },
16832 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQ, 0, 0 },
16833 { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQI, 0, 0 },
16835 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAW, 0, 0 },
16836 { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAWI, 0, 0 },
16837 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRAD, 0, 0 },
16838 { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRADI, 0, 0 },
16840 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, 0, 0 },
16841 { MASK_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, 0, 0 },
16844 { MASK_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, 0, 0 },
16845 { MASK_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, 0, 0 },
16846 { MASK_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, 0, 0 },
16847 { MASK_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, 0, 0 },
16848 { MASK_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, 0, 0 },
16849 { MASK_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, 0, 0 },
16850 { MASK_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, 0, 0 },
16851 { MASK_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, 0, 0 },
16853 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
16854 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
16855 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
16856 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT,
16857 BUILTIN_DESC_SWAP_OPERANDS },
16858 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE,
16859 BUILTIN_DESC_SWAP_OPERANDS },
16860 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
16861 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 },
16862 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 },
16863 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 },
16864 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE,
16865 BUILTIN_DESC_SWAP_OPERANDS },
16866 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT,
16867 BUILTIN_DESC_SWAP_OPERANDS },
16868 { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 },
16869 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
16870 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
16871 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 },
16872 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 },
16873 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 },
16874 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 },
16875 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 },
16876 { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 },
16878 { MASK_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, 0, 0 },
16879 { MASK_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, 0, 0 },
16880 { MASK_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, 0, 0 },
16881 { MASK_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, 0, 0 },
16883 { MASK_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, 0, 0 },
16884 { MASK_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, 0, 0 },
16885 { MASK_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, 0, 0 },
16886 { MASK_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, 0, 0 },
16888 { MASK_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, 0, 0 },
16889 { MASK_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, 0, 0 },
16890 { MASK_SSE2, CODE_FOR_sse2_unpcklpd, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, 0, 0 },
16893 { MASK_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, 0, 0 },
16894 { MASK_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, 0, 0 },
16895 { MASK_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, 0, 0 },
16896 { MASK_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, 0, 0 },
16897 { MASK_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, 0, 0 },
16898 { MASK_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, 0, 0 },
16899 { MASK_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, 0, 0 },
16900 { MASK_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, 0, 0 },
16902 { MASK_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 },
16903 { MASK_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 },
16904 { MASK_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, 0, 0 },
16905 { MASK_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, 0, 0 },
16906 { MASK_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, 0, 0 },
16907 { MASK_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, 0, 0 },
16908 { MASK_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, 0, 0 },
16909 { MASK_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, 0, 0 },
16911 { MASK_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, 0, 0 },
16912 { MASK_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, 0, 0 },
16914 { MASK_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, 0, 0 },
16915 { MASK_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, 0, 0 },
16916 { MASK_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, 0, 0 },
16917 { MASK_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, 0, 0 },
16919 { MASK_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, 0, 0 },
16920 { MASK_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, 0, 0 },
16922 { MASK_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, 0, 0 },
16923 { MASK_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, 0, 0 },
16924 { MASK_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, 0, 0 },
16925 { MASK_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, 0, 0 },
16926 { MASK_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, 0, 0 },
16927 { MASK_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, 0, 0 },
16929 { MASK_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, 0, 0 },
16930 { MASK_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, 0, 0 },
16931 { MASK_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, 0, 0 },
16932 { MASK_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, 0, 0 },
16934 { MASK_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, 0, 0 },
16935 { MASK_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, 0, 0 },
16936 { MASK_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, 0, 0 },
16937 { MASK_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, 0, 0 },
16938 { MASK_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, 0, 0 },
16939 { MASK_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, 0, 0 },
16940 { MASK_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, 0, 0 },
16941 { MASK_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, 0, 0 },
16943 { MASK_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, 0, 0 },
16944 { MASK_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, 0, 0 },
16945 { MASK_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, 0, 0 },
16947 { MASK_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, 0, 0 },
16948 { MASK_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, 0, 0 },
16950 { MASK_SSE2, CODE_FOR_sse2_umulsidi3, 0, IX86_BUILTIN_PMULUDQ, 0, 0 },
16951 { MASK_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, 0, 0 },
16953 { MASK_SSE2, CODE_FOR_ashlv8hi3, 0, IX86_BUILTIN_PSLLWI128, 0, 0 },
16954 { MASK_SSE2, CODE_FOR_ashlv4si3, 0, IX86_BUILTIN_PSLLDI128, 0, 0 },
16955 { MASK_SSE2, CODE_FOR_ashlv2di3, 0, IX86_BUILTIN_PSLLQI128, 0, 0 },
16957 { MASK_SSE2, CODE_FOR_lshrv8hi3, 0, IX86_BUILTIN_PSRLWI128, 0, 0 },
16958 { MASK_SSE2, CODE_FOR_lshrv4si3, 0, IX86_BUILTIN_PSRLDI128, 0, 0 },
16959 { MASK_SSE2, CODE_FOR_lshrv2di3, 0, IX86_BUILTIN_PSRLQI128, 0, 0 },
16961 { MASK_SSE2, CODE_FOR_ashrv8hi3, 0, IX86_BUILTIN_PSRAWI128, 0, 0 },
16962 { MASK_SSE2, CODE_FOR_ashrv4si3, 0, IX86_BUILTIN_PSRADI128, 0, 0 },
16964 { MASK_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, 0, 0 },
16966 { MASK_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, 0, 0 },
16967 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, 0, 0 },
16968 { MASK_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 },
16969 { MASK_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 },
16972 { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 },
16973 { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 },
16974 { MASK_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 },
16975 { MASK_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 },
16976 { MASK_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 },
16977 { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 },
16980 { MASK_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, 0, 0 },
16981 { MASK_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, 0, 0 },
16982 { MASK_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, 0, 0 },
16983 { MASK_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, 0, 0 },
16984 { MASK_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, 0, 0 },
16985 { MASK_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, 0, 0 },
16986 { MASK_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, 0, 0 },
16987 { MASK_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, 0, 0 },
16988 { MASK_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, 0, 0 },
16989 { MASK_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, 0, 0 },
16990 { MASK_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, 0, 0 },
16991 { MASK_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, 0, 0 },
16992 { MASK_SSSE3, CODE_FOR_ssse3_pmaddubswv8hi3, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, 0, 0 },
16993 { MASK_SSSE3, CODE_FOR_ssse3_pmaddubswv4hi3, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, 0, 0 },
16994 { MASK_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, 0, 0 },
16995 { MASK_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, 0, 0 },
16996 { MASK_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, 0, 0 },
16997 { MASK_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, 0, 0 },
16998 { MASK_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, 0, 0 },
16999 { MASK_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, 0, 0 },
17000 { MASK_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, 0, 0 },
17001 { MASK_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, 0, 0 },
17002 { MASK_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, 0, 0 },
17003 { MASK_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, 0, 0 },
17006 { MASK_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, 0, 0 },
17007 { MASK_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, 0, 0 },
17008 { MASK_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, 0, 0 },
17009 { MASK_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, 0, 0 },
17010 { MASK_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, 0, 0 },
17011 { MASK_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, 0, 0 },
17012 { MASK_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, 0, 0 },
17013 { MASK_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, 0, 0 },
17014 { MASK_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, 0, 0 },
17015 { MASK_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, 0, 0 },
17016 { MASK_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, 0, IX86_BUILTIN_PMULDQ128, 0, 0 },
17017 { MASK_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, 0, 0 },
17020 static const struct builtin_description bdesc_1arg[] =
17022 { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB, 0, 0 },
17023 { MASK_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, 0, 0 },
17025 { MASK_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, 0, 0 },
17026 { MASK_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, 0, 0 },
17027 { MASK_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, 0, 0 },
17029 { MASK_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, 0, 0 },
17030 { MASK_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, 0, 0 },
17031 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, 0, 0 },
17032 { MASK_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, 0, 0 },
17033 { MASK_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, 0, 0 },
17034 { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, 0, 0 },
17036 { MASK_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, 0, 0 },
17037 { MASK_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, 0, 0 },
17039 { MASK_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, 0, 0 },
17041 { MASK_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, 0, 0 },
17042 { MASK_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, 0, 0 },
17044 { MASK_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, 0, 0 },
17045 { MASK_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, 0, 0 },
17046 { MASK_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, 0, 0 },
17047 { MASK_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, 0, 0 },
17048 { MASK_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, 0, 0 },
17050 { MASK_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, 0, 0 },
17052 { MASK_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, 0, 0 },
17053 { MASK_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, 0, 0 },
17054 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, 0, 0 },
17055 { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, 0, 0 },
17057 { MASK_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, 0, 0 },
17058 { MASK_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 },
17059 { MASK_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 },
17062 { MASK_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, 0, 0 },
17063 { MASK_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, 0, 0 },
17066 { MASK_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, 0, 0 },
17067 { MASK_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, 0, 0 },
17068 { MASK_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, 0, 0 },
17069 { MASK_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, 0, 0 },
17070 { MASK_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, 0, 0 },
17071 { MASK_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, 0, 0 },
17074 { MASK_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVSXBW128, 0, 0 },
17075 { MASK_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVSXBD128, 0, 0 },
17076 { MASK_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVSXBQ128, 0, 0 },
17077 { MASK_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVSXWD128, 0, 0 },
17078 { MASK_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVSXWQ128, 0, 0 },
17079 { MASK_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, 0, IX86_BUILTIN_PMOVSXDQ128, 0, 0 },
17080 { MASK_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, 0, IX86_BUILTIN_PMOVZXBW128, 0, 0 },
17081 { MASK_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, 0, IX86_BUILTIN_PMOVZXBD128, 0, 0 },
17082 { MASK_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, 0, IX86_BUILTIN_PMOVZXBQ128, 0, 0 },
17083 { MASK_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, 0, IX86_BUILTIN_PMOVZXWD128, 0, 0 },
17084 { MASK_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, 0, IX86_BUILTIN_PMOVZXWQ128, 0, 0 },
17085 { MASK_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, 0, IX86_BUILTIN_PMOVZXDQ128, 0, 0 },
17086 { MASK_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, 0, 0 },
17088 /* Fake 1 arg builtins with a constant smaller than 8 bits as the
17090 { MASK_SSE4_1, CODE_FOR_sse4_1_roundpd, 0, IX86_BUILTIN_ROUNDPD, 0, 0 },
17091 { MASK_SSE4_1, CODE_FOR_sse4_1_roundps, 0, IX86_BUILTIN_ROUNDPS, 0, 0 },
17094 /* Set up all the MMX/SSE builtins. This is not called if TARGET_MMX
17095 is zero. Otherwise, if TARGET_SSE is not set, only expand the MMX
17098 ix86_init_mmx_sse_builtins (void)
17100 const struct builtin_description * d;
17103 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
17104 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
17105 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
17106 tree V2DI_type_node
17107 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
17108 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
17109 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
17110 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
17111 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
17112 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
17113 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
17115 tree pchar_type_node = build_pointer_type (char_type_node);
17116 tree pcchar_type_node = build_pointer_type (
17117 build_type_variant (char_type_node, 1, 0));
17118 tree pfloat_type_node = build_pointer_type (float_type_node);
17119 tree pcfloat_type_node = build_pointer_type (
17120 build_type_variant (float_type_node, 1, 0));
17121 tree pv2si_type_node = build_pointer_type (V2SI_type_node);
17122 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
17123 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
17126 tree int_ftype_v4sf_v4sf
17127 = build_function_type_list (integer_type_node,
17128 V4SF_type_node, V4SF_type_node, NULL_TREE);
17129 tree v4si_ftype_v4sf_v4sf
17130 = build_function_type_list (V4SI_type_node,
17131 V4SF_type_node, V4SF_type_node, NULL_TREE);
17132 /* MMX/SSE/integer conversions. */
17133 tree int_ftype_v4sf
17134 = build_function_type_list (integer_type_node,
17135 V4SF_type_node, NULL_TREE);
17136 tree int64_ftype_v4sf
17137 = build_function_type_list (long_long_integer_type_node,
17138 V4SF_type_node, NULL_TREE);
17139 tree int_ftype_v8qi
17140 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
17141 tree v4sf_ftype_v4sf_int
17142 = build_function_type_list (V4SF_type_node,
17143 V4SF_type_node, integer_type_node, NULL_TREE);
17144 tree v4sf_ftype_v4sf_int64
17145 = build_function_type_list (V4SF_type_node,
17146 V4SF_type_node, long_long_integer_type_node,
17148 tree v4sf_ftype_v4sf_v2si
17149 = build_function_type_list (V4SF_type_node,
17150 V4SF_type_node, V2SI_type_node, NULL_TREE);
17152 /* Miscellaneous. */
17153 tree v8qi_ftype_v4hi_v4hi
17154 = build_function_type_list (V8QI_type_node,
17155 V4HI_type_node, V4HI_type_node, NULL_TREE);
17156 tree v4hi_ftype_v2si_v2si
17157 = build_function_type_list (V4HI_type_node,
17158 V2SI_type_node, V2SI_type_node, NULL_TREE);
17159 tree v4sf_ftype_v4sf_v4sf_int
17160 = build_function_type_list (V4SF_type_node,
17161 V4SF_type_node, V4SF_type_node,
17162 integer_type_node, NULL_TREE);
17163 tree v2si_ftype_v4hi_v4hi
17164 = build_function_type_list (V2SI_type_node,
17165 V4HI_type_node, V4HI_type_node, NULL_TREE);
17166 tree v4hi_ftype_v4hi_int
17167 = build_function_type_list (V4HI_type_node,
17168 V4HI_type_node, integer_type_node, NULL_TREE);
17169 tree v4hi_ftype_v4hi_di
17170 = build_function_type_list (V4HI_type_node,
17171 V4HI_type_node, long_long_unsigned_type_node,
17173 tree v2si_ftype_v2si_di
17174 = build_function_type_list (V2SI_type_node,
17175 V2SI_type_node, long_long_unsigned_type_node,
17177 tree void_ftype_void
17178 = build_function_type (void_type_node, void_list_node);
17179 tree void_ftype_unsigned
17180 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
17181 tree void_ftype_unsigned_unsigned
17182 = build_function_type_list (void_type_node, unsigned_type_node,
17183 unsigned_type_node, NULL_TREE);
17184 tree void_ftype_pcvoid_unsigned_unsigned
17185 = build_function_type_list (void_type_node, const_ptr_type_node,
17186 unsigned_type_node, unsigned_type_node,
17188 tree unsigned_ftype_void
17189 = build_function_type (unsigned_type_node, void_list_node);
17190 tree v2si_ftype_v4sf
17191 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
17192 /* Loads/stores. */
17193 tree void_ftype_v8qi_v8qi_pchar
17194 = build_function_type_list (void_type_node,
17195 V8QI_type_node, V8QI_type_node,
17196 pchar_type_node, NULL_TREE);
17197 tree v4sf_ftype_pcfloat
17198 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
17199 /* @@@ the type is bogus */
17200 tree v4sf_ftype_v4sf_pv2si
17201 = build_function_type_list (V4SF_type_node,
17202 V4SF_type_node, pv2si_type_node, NULL_TREE);
17203 tree void_ftype_pv2si_v4sf
17204 = build_function_type_list (void_type_node,
17205 pv2si_type_node, V4SF_type_node, NULL_TREE);
17206 tree void_ftype_pfloat_v4sf
17207 = build_function_type_list (void_type_node,
17208 pfloat_type_node, V4SF_type_node, NULL_TREE);
17209 tree void_ftype_pdi_di
17210 = build_function_type_list (void_type_node,
17211 pdi_type_node, long_long_unsigned_type_node,
17213 tree void_ftype_pv2di_v2di
17214 = build_function_type_list (void_type_node,
17215 pv2di_type_node, V2DI_type_node, NULL_TREE);
17216 /* Normal vector unops. */
17217 tree v4sf_ftype_v4sf
17218 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
17219 tree v16qi_ftype_v16qi
17220 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
17221 tree v8hi_ftype_v8hi
17222 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
17223 tree v4si_ftype_v4si
17224 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
17225 tree v8qi_ftype_v8qi
17226 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
17227 tree v4hi_ftype_v4hi
17228 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
17230 /* Normal vector binops. */
17231 tree v4sf_ftype_v4sf_v4sf
17232 = build_function_type_list (V4SF_type_node,
17233 V4SF_type_node, V4SF_type_node, NULL_TREE);
17234 tree v8qi_ftype_v8qi_v8qi
17235 = build_function_type_list (V8QI_type_node,
17236 V8QI_type_node, V8QI_type_node, NULL_TREE);
17237 tree v4hi_ftype_v4hi_v4hi
17238 = build_function_type_list (V4HI_type_node,
17239 V4HI_type_node, V4HI_type_node, NULL_TREE);
17240 tree v2si_ftype_v2si_v2si
17241 = build_function_type_list (V2SI_type_node,
17242 V2SI_type_node, V2SI_type_node, NULL_TREE);
17243 tree di_ftype_di_di
17244 = build_function_type_list (long_long_unsigned_type_node,
17245 long_long_unsigned_type_node,
17246 long_long_unsigned_type_node, NULL_TREE);
17248 tree di_ftype_di_di_int
17249 = build_function_type_list (long_long_unsigned_type_node,
17250 long_long_unsigned_type_node,
17251 long_long_unsigned_type_node,
17252 integer_type_node, NULL_TREE);
17254 tree v2si_ftype_v2sf
17255 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
17256 tree v2sf_ftype_v2si
17257 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
17258 tree v2si_ftype_v2si
17259 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
17260 tree v2sf_ftype_v2sf
17261 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
17262 tree v2sf_ftype_v2sf_v2sf
17263 = build_function_type_list (V2SF_type_node,
17264 V2SF_type_node, V2SF_type_node, NULL_TREE);
17265 tree v2si_ftype_v2sf_v2sf
17266 = build_function_type_list (V2SI_type_node,
17267 V2SF_type_node, V2SF_type_node, NULL_TREE);
17268 tree pint_type_node = build_pointer_type (integer_type_node);
17269 tree pdouble_type_node = build_pointer_type (double_type_node);
17270 tree pcdouble_type_node = build_pointer_type (
17271 build_type_variant (double_type_node, 1, 0));
17272 tree int_ftype_v2df_v2df
17273 = build_function_type_list (integer_type_node,
17274 V2DF_type_node, V2DF_type_node, NULL_TREE);
17276 tree void_ftype_pcvoid
17277 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
17278 tree v4sf_ftype_v4si
17279 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
17280 tree v4si_ftype_v4sf
17281 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
17282 tree v2df_ftype_v4si
17283 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
17284 tree v4si_ftype_v2df
17285 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
17286 tree v2si_ftype_v2df
17287 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
17288 tree v4sf_ftype_v2df
17289 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
17290 tree v2df_ftype_v2si
17291 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
17292 tree v2df_ftype_v4sf
17293 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
17294 tree int_ftype_v2df
17295 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
17296 tree int64_ftype_v2df
17297 = build_function_type_list (long_long_integer_type_node,
17298 V2DF_type_node, NULL_TREE);
17299 tree v2df_ftype_v2df_int
17300 = build_function_type_list (V2DF_type_node,
17301 V2DF_type_node, integer_type_node, NULL_TREE);
17302 tree v2df_ftype_v2df_int64
17303 = build_function_type_list (V2DF_type_node,
17304 V2DF_type_node, long_long_integer_type_node,
17306 tree v4sf_ftype_v4sf_v2df
17307 = build_function_type_list (V4SF_type_node,
17308 V4SF_type_node, V2DF_type_node, NULL_TREE);
17309 tree v2df_ftype_v2df_v4sf
17310 = build_function_type_list (V2DF_type_node,
17311 V2DF_type_node, V4SF_type_node, NULL_TREE);
17312 tree v2df_ftype_v2df_v2df_int
17313 = build_function_type_list (V2DF_type_node,
17314 V2DF_type_node, V2DF_type_node,
17317 tree v2df_ftype_v2df_pcdouble
17318 = build_function_type_list (V2DF_type_node,
17319 V2DF_type_node, pcdouble_type_node, NULL_TREE);
17320 tree void_ftype_pdouble_v2df
17321 = build_function_type_list (void_type_node,
17322 pdouble_type_node, V2DF_type_node, NULL_TREE);
17323 tree void_ftype_pint_int
17324 = build_function_type_list (void_type_node,
17325 pint_type_node, integer_type_node, NULL_TREE);
17326 tree void_ftype_v16qi_v16qi_pchar
17327 = build_function_type_list (void_type_node,
17328 V16QI_type_node, V16QI_type_node,
17329 pchar_type_node, NULL_TREE);
17330 tree v2df_ftype_pcdouble
17331 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
17332 tree v2df_ftype_v2df_v2df
17333 = build_function_type_list (V2DF_type_node,
17334 V2DF_type_node, V2DF_type_node, NULL_TREE);
17335 tree v16qi_ftype_v16qi_v16qi
17336 = build_function_type_list (V16QI_type_node,
17337 V16QI_type_node, V16QI_type_node, NULL_TREE);
17338 tree v8hi_ftype_v8hi_v8hi
17339 = build_function_type_list (V8HI_type_node,
17340 V8HI_type_node, V8HI_type_node, NULL_TREE);
17341 tree v4si_ftype_v4si_v4si
17342 = build_function_type_list (V4SI_type_node,
17343 V4SI_type_node, V4SI_type_node, NULL_TREE);
17344 tree v2di_ftype_v2di_v2di
17345 = build_function_type_list (V2DI_type_node,
17346 V2DI_type_node, V2DI_type_node, NULL_TREE);
17347 tree v2di_ftype_v2df_v2df
17348 = build_function_type_list (V2DI_type_node,
17349 V2DF_type_node, V2DF_type_node, NULL_TREE);
17350 tree v2df_ftype_v2df
17351 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
17352 tree v2di_ftype_v2di_int
17353 = build_function_type_list (V2DI_type_node,
17354 V2DI_type_node, integer_type_node, NULL_TREE);
17355 tree v2di_ftype_v2di_v2di_int
17356 = build_function_type_list (V2DI_type_node, V2DI_type_node,
17357 V2DI_type_node, integer_type_node, NULL_TREE);
17358 tree v4si_ftype_v4si_int
17359 = build_function_type_list (V4SI_type_node,
17360 V4SI_type_node, integer_type_node, NULL_TREE);
17361 tree v8hi_ftype_v8hi_int
17362 = build_function_type_list (V8HI_type_node,
17363 V8HI_type_node, integer_type_node, NULL_TREE);
17364 tree v4si_ftype_v8hi_v8hi
17365 = build_function_type_list (V4SI_type_node,
17366 V8HI_type_node, V8HI_type_node, NULL_TREE);
17367 tree di_ftype_v8qi_v8qi
17368 = build_function_type_list (long_long_unsigned_type_node,
17369 V8QI_type_node, V8QI_type_node, NULL_TREE);
17370 tree di_ftype_v2si_v2si
17371 = build_function_type_list (long_long_unsigned_type_node,
17372 V2SI_type_node, V2SI_type_node, NULL_TREE);
17373 tree v2di_ftype_v16qi_v16qi
17374 = build_function_type_list (V2DI_type_node,
17375 V16QI_type_node, V16QI_type_node, NULL_TREE);
17376 tree v2di_ftype_v4si_v4si
17377 = build_function_type_list (V2DI_type_node,
17378 V4SI_type_node, V4SI_type_node, NULL_TREE);
17379 tree int_ftype_v16qi
17380 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
17381 tree v16qi_ftype_pcchar
17382 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
17383 tree void_ftype_pchar_v16qi
17384 = build_function_type_list (void_type_node,
17385 pchar_type_node, V16QI_type_node, NULL_TREE);
17387 tree v2di_ftype_v2di_unsigned_unsigned
17388 = build_function_type_list (V2DI_type_node, V2DI_type_node,
17389 unsigned_type_node, unsigned_type_node,
17391 tree v2di_ftype_v2di_v2di_unsigned_unsigned
17392 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
17393 unsigned_type_node, unsigned_type_node,
17395 tree v2di_ftype_v2di_v16qi
17396 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
17398 tree v2df_ftype_v2df_v2df_v2df
17399 = build_function_type_list (V2DF_type_node,
17400 V2DF_type_node, V2DF_type_node,
17401 V2DF_type_node, NULL_TREE);
17402 tree v4sf_ftype_v4sf_v4sf_v4sf
17403 = build_function_type_list (V4SF_type_node,
17404 V4SF_type_node, V4SF_type_node,
17405 V4SF_type_node, NULL_TREE);
17406 tree v8hi_ftype_v16qi
17407 = build_function_type_list (V8HI_type_node, V16QI_type_node,
17409 tree v4si_ftype_v16qi
17410 = build_function_type_list (V4SI_type_node, V16QI_type_node,
17412 tree v2di_ftype_v16qi
17413 = build_function_type_list (V2DI_type_node, V16QI_type_node,
17415 tree v4si_ftype_v8hi
17416 = build_function_type_list (V4SI_type_node, V8HI_type_node,
17418 tree v2di_ftype_v8hi
17419 = build_function_type_list (V2DI_type_node, V8HI_type_node,
17421 tree v2di_ftype_v4si
17422 = build_function_type_list (V2DI_type_node, V4SI_type_node,
17424 tree v2di_ftype_pv2di
17425 = build_function_type_list (V2DI_type_node, pv2di_type_node,
17427 tree v16qi_ftype_v16qi_v16qi_int
17428 = build_function_type_list (V16QI_type_node, V16QI_type_node,
17429 V16QI_type_node, integer_type_node,
17431 tree v16qi_ftype_v16qi_v16qi_v16qi
17432 = build_function_type_list (V16QI_type_node, V16QI_type_node,
17433 V16QI_type_node, V16QI_type_node,
17435 tree v8hi_ftype_v8hi_v8hi_int
17436 = build_function_type_list (V8HI_type_node, V8HI_type_node,
17437 V8HI_type_node, integer_type_node,
17439 tree v4si_ftype_v4si_v4si_int
17440 = build_function_type_list (V4SI_type_node, V4SI_type_node,
17441 V4SI_type_node, integer_type_node,
17443 tree int_ftype_v2di_v2di
17444 = build_function_type_list (integer_type_node,
17445 V2DI_type_node, V2DI_type_node,
17449 tree float128_type;
17452 /* The __float80 type. */
17453 if (TYPE_MODE (long_double_type_node) == XFmode)
17454 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
17458 /* The __float80 type. */
17459 float80_type = make_node (REAL_TYPE);
17460 TYPE_PRECISION (float80_type) = 80;
17461 layout_type (float80_type);
17462 (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
17467 float128_type = make_node (REAL_TYPE);
17468 TYPE_PRECISION (float128_type) = 128;
17469 layout_type (float128_type);
17470 (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
17473 /* Add all SSE builtins that are more or less simple operations on
17475 for (i = 0, d = bdesc_sse_3arg;
17476 i < ARRAY_SIZE (bdesc_sse_3arg);
17479 /* Use one of the operands; the target can have a different mode for
17480 mask-generating compares. */
17481 enum machine_mode mode;
17486 mode = insn_data[d->icode].operand[1].mode;
17491 type = v16qi_ftype_v16qi_v16qi_int;
17494 type = v8hi_ftype_v8hi_v8hi_int;
17497 type = v4si_ftype_v4si_v4si_int;
17500 type = v2di_ftype_v2di_v2di_int;
17503 type = v2df_ftype_v2df_v2df_int;
17506 type = v4sf_ftype_v4sf_v4sf_int;
17509 gcc_unreachable ();
17512 /* Override for variable blends. */
17515 case CODE_FOR_sse4_1_blendvpd:
17516 type = v2df_ftype_v2df_v2df_v2df;
17518 case CODE_FOR_sse4_1_blendvps:
17519 type = v4sf_ftype_v4sf_v4sf_v4sf;
17521 case CODE_FOR_sse4_1_pblendvb:
17522 type = v16qi_ftype_v16qi_v16qi_v16qi;
17528 def_builtin (d->mask, d->name, type, d->code);
17531 /* Add all builtins that are more or less simple operations on two
17533 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
17535 /* Use one of the operands; the target can have a different mode for
17536 mask-generating compares. */
17537 enum machine_mode mode;
17542 mode = insn_data[d->icode].operand[1].mode;
17547 type = v16qi_ftype_v16qi_v16qi;
17550 type = v8hi_ftype_v8hi_v8hi;
17553 type = v4si_ftype_v4si_v4si;
17556 type = v2di_ftype_v2di_v2di;
17559 type = v2df_ftype_v2df_v2df;
17562 type = v4sf_ftype_v4sf_v4sf;
17565 type = v8qi_ftype_v8qi_v8qi;
17568 type = v4hi_ftype_v4hi_v4hi;
17571 type = v2si_ftype_v2si_v2si;
17574 type = di_ftype_di_di;
17578 gcc_unreachable ();
17581 /* Override for comparisons. */
17582 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
17583 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3)
17584 type = v4si_ftype_v4sf_v4sf;
17586 if (d->icode == CODE_FOR_sse2_maskcmpv2df3
17587 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
17588 type = v2di_ftype_v2df_v2df;
17590 def_builtin (d->mask, d->name, type, d->code);
17593 /* Add all builtins that are more or less simple operations on 1 operand. */
17594 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
17596 enum machine_mode mode;
17601 mode = insn_data[d->icode].operand[1].mode;
17606 type = v16qi_ftype_v16qi;
17609 type = v8hi_ftype_v8hi;
17612 type = v4si_ftype_v4si;
17615 type = v2df_ftype_v2df;
17618 type = v4sf_ftype_v4sf;
17621 type = v8qi_ftype_v8qi;
17624 type = v4hi_ftype_v4hi;
17627 type = v2si_ftype_v2si;
17634 def_builtin (d->mask, d->name, type, d->code);
17637 /* Add the remaining MMX insns with somewhat more complicated types. */
17638 def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS);
17639 def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW);
17640 def_builtin (MASK_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD);
17641 def_builtin (MASK_MMX, "__builtin_ia32_psllq", di_ftype_di_di, IX86_BUILTIN_PSLLQ);
17643 def_builtin (MASK_MMX, "__builtin_ia32_psrlw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRLW);
17644 def_builtin (MASK_MMX, "__builtin_ia32_psrld", v2si_ftype_v2si_di, IX86_BUILTIN_PSRLD);
17645 def_builtin (MASK_MMX, "__builtin_ia32_psrlq", di_ftype_di_di, IX86_BUILTIN_PSRLQ);
17647 def_builtin (MASK_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRAW);
17648 def_builtin (MASK_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_di, IX86_BUILTIN_PSRAD);
17650 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW);
17651 def_builtin (MASK_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD);
17653 /* comi/ucomi insns. */
17654 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
17655 if (d->mask == MASK_SSE2)
17656 def_builtin (d->mask, d->name, int_ftype_v2df_v2df, d->code);
17658 def_builtin (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
17661 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
17662 def_builtin (d->mask, d->name, int_ftype_v2di_v2di, d->code);
17664 def_builtin (MASK_MMX, "__builtin_ia32_packsswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKSSWB);
17665 def_builtin (MASK_MMX, "__builtin_ia32_packssdw", v4hi_ftype_v2si_v2si, IX86_BUILTIN_PACKSSDW);
17666 def_builtin (MASK_MMX, "__builtin_ia32_packuswb", v8qi_ftype_v4hi_v4hi, IX86_BUILTIN_PACKUSWB);
17668 def_builtin (MASK_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
17669 def_builtin (MASK_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
17670 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtpi2ps", v4sf_ftype_v4sf_v2si, IX86_BUILTIN_CVTPI2PS);
17671 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTPS2PI);
17672 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtsi2ss", v4sf_ftype_v4sf_int, IX86_BUILTIN_CVTSI2SS);
17673 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtsi642ss", v4sf_ftype_v4sf_int64, IX86_BUILTIN_CVTSI642SS);
17674 def_builtin_const (MASK_SSE, "__builtin_ia32_cvtss2si", int_ftype_v4sf, IX86_BUILTIN_CVTSS2SI);
17675 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvtss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTSS2SI64);
17676 def_builtin_const (MASK_SSE, "__builtin_ia32_cvttps2pi", v2si_ftype_v4sf, IX86_BUILTIN_CVTTPS2PI);
17677 def_builtin_const (MASK_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI);
17678 def_builtin_const (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64);
17680 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
17682 def_builtin (MASK_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS);
17683 def_builtin (MASK_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS);
17685 def_builtin (MASK_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS);
17686 def_builtin (MASK_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS);
17687 def_builtin (MASK_SSE, "__builtin_ia32_storehps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STOREHPS);
17688 def_builtin (MASK_SSE, "__builtin_ia32_storelps", void_ftype_pv2si_v4sf, IX86_BUILTIN_STORELPS);
17690 def_builtin (MASK_SSE, "__builtin_ia32_movmskps", int_ftype_v4sf, IX86_BUILTIN_MOVMSKPS);
17691 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pmovmskb", int_ftype_v8qi, IX86_BUILTIN_PMOVMSKB);
17692 def_builtin (MASK_SSE, "__builtin_ia32_movntps", void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTPS);
17693 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_movntq", void_ftype_pdi_di, IX86_BUILTIN_MOVNTQ);
17695 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_sfence", void_ftype_void, IX86_BUILTIN_SFENCE);
17697 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_psadbw", di_ftype_v8qi_v8qi, IX86_BUILTIN_PSADBW);
17699 def_builtin (MASK_SSE, "__builtin_ia32_rcpps", v4sf_ftype_v4sf, IX86_BUILTIN_RCPPS);
17700 def_builtin (MASK_SSE, "__builtin_ia32_rcpss", v4sf_ftype_v4sf, IX86_BUILTIN_RCPSS);
17701 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTPS);
17702 def_builtin (MASK_SSE, "__builtin_ia32_rsqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_RSQRTSS);
17703 def_builtin_const (MASK_SSE, "__builtin_ia32_sqrtps", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTPS);
17704 def_builtin_const (MASK_SSE, "__builtin_ia32_sqrtss", v4sf_ftype_v4sf, IX86_BUILTIN_SQRTSS);
17706 def_builtin (MASK_SSE, "__builtin_ia32_shufps", v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_SHUFPS);
17708 /* Original 3DNow! */
17709 def_builtin (MASK_3DNOW, "__builtin_ia32_femms", void_ftype_void, IX86_BUILTIN_FEMMS);
17710 def_builtin (MASK_3DNOW, "__builtin_ia32_pavgusb", v8qi_ftype_v8qi_v8qi, IX86_BUILTIN_PAVGUSB);
17711 def_builtin (MASK_3DNOW, "__builtin_ia32_pf2id", v2si_ftype_v2sf, IX86_BUILTIN_PF2ID);
17712 def_builtin (MASK_3DNOW, "__builtin_ia32_pfacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFACC);
17713 def_builtin (MASK_3DNOW, "__builtin_ia32_pfadd", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFADD);
17714 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpeq", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPEQ);
17715 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpge", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGE);
17716 def_builtin (MASK_3DNOW, "__builtin_ia32_pfcmpgt", v2si_ftype_v2sf_v2sf, IX86_BUILTIN_PFCMPGT);
17717 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmax", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMAX);
17718 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmin", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMIN);
17719 def_builtin (MASK_3DNOW, "__builtin_ia32_pfmul", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFMUL);
17720 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcp", v2sf_ftype_v2sf, IX86_BUILTIN_PFRCP);
17721 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT1);
17722 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrcpit2", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRCPIT2);
17723 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqrt", v2sf_ftype_v2sf, IX86_BUILTIN_PFRSQRT);
17724 def_builtin (MASK_3DNOW, "__builtin_ia32_pfrsqit1", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFRSQIT1);
17725 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsub", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUB);
17726 def_builtin (MASK_3DNOW, "__builtin_ia32_pfsubr", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFSUBR);
17727 def_builtin (MASK_3DNOW, "__builtin_ia32_pi2fd", v2sf_ftype_v2si, IX86_BUILTIN_PI2FD);
17728 def_builtin (MASK_3DNOW, "__builtin_ia32_pmulhrw", v4hi_ftype_v4hi_v4hi, IX86_BUILTIN_PMULHRW);
17730 /* 3DNow! extension as used in the Athlon CPU. */
17731 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pf2iw", v2si_ftype_v2sf, IX86_BUILTIN_PF2IW);
17732 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFNACC);
17733 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pfpnacc", v2sf_ftype_v2sf_v2sf, IX86_BUILTIN_PFPNACC);
17734 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pi2fw", v2sf_ftype_v2si, IX86_BUILTIN_PI2FW);
17735 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF);
17736 def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI);
17739 def_builtin (MASK_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
17741 def_builtin (MASK_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
17742 def_builtin (MASK_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
17744 def_builtin (MASK_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD);
17745 def_builtin (MASK_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD);
17747 def_builtin (MASK_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD);
17748 def_builtin (MASK_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128);
17749 def_builtin (MASK_SSE2, "__builtin_ia32_movnti", void_ftype_pint_int, IX86_BUILTIN_MOVNTI);
17750 def_builtin (MASK_SSE2, "__builtin_ia32_movntpd", void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTPD);
17751 def_builtin (MASK_SSE2, "__builtin_ia32_movntdq", void_ftype_pv2di_v2di, IX86_BUILTIN_MOVNTDQ);
17753 def_builtin (MASK_SSE2, "__builtin_ia32_pshufd", v4si_ftype_v4si_int, IX86_BUILTIN_PSHUFD);
17754 def_builtin (MASK_SSE2, "__builtin_ia32_pshuflw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFLW);
17755 def_builtin (MASK_SSE2, "__builtin_ia32_pshufhw", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSHUFHW);
17756 def_builtin (MASK_SSE2, "__builtin_ia32_psadbw128", v2di_ftype_v16qi_v16qi, IX86_BUILTIN_PSADBW128);
17758 def_builtin_const (MASK_SSE2, "__builtin_ia32_sqrtpd", v2df_ftype_v2df, IX86_BUILTIN_SQRTPD);
17759 def_builtin_const (MASK_SSE2, "__builtin_ia32_sqrtsd", v2df_ftype_v2df, IX86_BUILTIN_SQRTSD);
17761 def_builtin (MASK_SSE2, "__builtin_ia32_shufpd", v2df_ftype_v2df_v2df_int, IX86_BUILTIN_SHUFPD);
17763 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtdq2pd", v2df_ftype_v4si, IX86_BUILTIN_CVTDQ2PD);
17764 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtdq2ps", v4sf_ftype_v4si, IX86_BUILTIN_CVTDQ2PS);
17766 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTPD2DQ);
17767 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTPD2PI);
17768 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpd2ps", v4sf_ftype_v2df, IX86_BUILTIN_CVTPD2PS);
17769 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttpd2dq", v4si_ftype_v2df, IX86_BUILTIN_CVTTPD2DQ);
17770 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttpd2pi", v2si_ftype_v2df, IX86_BUILTIN_CVTTPD2PI);
17772 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtpi2pd", v2df_ftype_v2si, IX86_BUILTIN_CVTPI2PD);
17774 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsd2si", int_ftype_v2df, IX86_BUILTIN_CVTSD2SI);
17775 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttsd2si", int_ftype_v2df, IX86_BUILTIN_CVTTSD2SI);
17776 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTSD2SI64);
17777 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvttsd2si64", int64_ftype_v2df, IX86_BUILTIN_CVTTSD2SI64);
17779 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTPS2DQ);
17780 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtps2pd", v2df_ftype_v4sf, IX86_BUILTIN_CVTPS2PD);
17781 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvttps2dq", v4si_ftype_v4sf, IX86_BUILTIN_CVTTPS2DQ);
17783 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsi2sd", v2df_ftype_v2df_int, IX86_BUILTIN_CVTSI2SD);
17784 def_builtin_const (MASK_SSE2 | MASK_64BIT, "__builtin_ia32_cvtsi642sd", v2df_ftype_v2df_int64, IX86_BUILTIN_CVTSI642SD);
17785 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS);
17786 def_builtin_const (MASK_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD);
17788 def_builtin (MASK_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
17789 def_builtin (MASK_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE);
17790 def_builtin (MASK_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
17792 def_builtin (MASK_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
17793 def_builtin (MASK_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
17795 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
17796 def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
17798 def_builtin (MASK_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128);
17799 def_builtin (MASK_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128);
17800 def_builtin (MASK_SSE2, "__builtin_ia32_pslldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSLLDI128);
17801 def_builtin (MASK_SSE2, "__builtin_ia32_psllqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLQI128);
17802 def_builtin (MASK_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSLLW128);
17803 def_builtin (MASK_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSLLD128);
17804 def_builtin (MASK_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128);
17806 def_builtin (MASK_SSE2, "__builtin_ia32_psrldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLDQI128);
17807 def_builtin (MASK_SSE2, "__builtin_ia32_psrlwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRLWI128);
17808 def_builtin (MASK_SSE2, "__builtin_ia32_psrldi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRLDI128);
17809 def_builtin (MASK_SSE2, "__builtin_ia32_psrlqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSRLQI128);
17810 def_builtin (MASK_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRLW128);
17811 def_builtin (MASK_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRLD128);
17812 def_builtin (MASK_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128);
17814 def_builtin (MASK_SSE2, "__builtin_ia32_psrawi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSRAWI128);
17815 def_builtin (MASK_SSE2, "__builtin_ia32_psradi128", v4si_ftype_v4si_int, IX86_BUILTIN_PSRADI128);
17816 def_builtin (MASK_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRAW128);
17817 def_builtin (MASK_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRAD128);
17819 def_builtin (MASK_SSE2, "__builtin_ia32_pmaddwd128", v4si_ftype_v8hi_v8hi, IX86_BUILTIN_PMADDWD128);
17821 /* Prescott New Instructions. */
17822 def_builtin (MASK_SSE3, "__builtin_ia32_monitor",
17823 void_ftype_pcvoid_unsigned_unsigned,
17824 IX86_BUILTIN_MONITOR);
17825 def_builtin (MASK_SSE3, "__builtin_ia32_mwait",
17826 void_ftype_unsigned_unsigned,
17827 IX86_BUILTIN_MWAIT);
17828 def_builtin (MASK_SSE3, "__builtin_ia32_lddqu",
17829 v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU);
17832 def_builtin (MASK_SSSE3, "__builtin_ia32_palignr128",
17833 v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PALIGNR128);
17834 def_builtin (MASK_SSSE3, "__builtin_ia32_palignr", di_ftype_di_di_int,
17835 IX86_BUILTIN_PALIGNR);
17838 def_builtin (MASK_SSE4_1, "__builtin_ia32_movntdqa",
17839 v2di_ftype_pv2di, IX86_BUILTIN_MOVNTDQA);
17840 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovsxbw128",
17841 v8hi_ftype_v16qi, IX86_BUILTIN_PMOVSXBW128);
17842 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovsxbd128",
17843 v4si_ftype_v16qi, IX86_BUILTIN_PMOVSXBD128);
17844 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovsxbq128",
17845 v2di_ftype_v16qi, IX86_BUILTIN_PMOVSXBQ128);
17846 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovsxwd128",
17847 v4si_ftype_v8hi, IX86_BUILTIN_PMOVSXWD128);
17848 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovsxwq128",
17849 v2di_ftype_v8hi, IX86_BUILTIN_PMOVSXWQ128);
17850 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovsxdq128",
17851 v2di_ftype_v4si, IX86_BUILTIN_PMOVSXDQ128);
17852 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovzxbw128",
17853 v8hi_ftype_v16qi, IX86_BUILTIN_PMOVZXBW128);
17854 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovzxbd128",
17855 v4si_ftype_v16qi, IX86_BUILTIN_PMOVZXBD128);
17856 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovzxbq128",
17857 v2di_ftype_v16qi, IX86_BUILTIN_PMOVZXBQ128);
17858 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovzxwd128",
17859 v4si_ftype_v8hi, IX86_BUILTIN_PMOVZXWD128);
17860 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovzxwq128",
17861 v2di_ftype_v8hi, IX86_BUILTIN_PMOVZXWQ128);
17862 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmovzxdq128",
17863 v2di_ftype_v4si, IX86_BUILTIN_PMOVZXDQ128);
17864 def_builtin (MASK_SSE4_1, "__builtin_ia32_pmuldq128",
17865 v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULDQ128);
17866 def_builtin_const (MASK_SSE4_1, "__builtin_ia32_roundpd",
17867 v2df_ftype_v2df_int, IX86_BUILTIN_ROUNDPD);
17868 def_builtin_const (MASK_SSE4_1, "__builtin_ia32_roundps",
17869 v4sf_ftype_v4sf_int, IX86_BUILTIN_ROUNDPS);
17870 def_builtin_const (MASK_SSE4_1, "__builtin_ia32_roundsd",
17871 v2df_ftype_v2df_v2df_int, IX86_BUILTIN_ROUNDSD);
17872 def_builtin_const (MASK_SSE4_1, "__builtin_ia32_roundss",
17873 v4sf_ftype_v4sf_v4sf_int, IX86_BUILTIN_ROUNDSS);
17875 /* AMDFAM10 SSE4A New built-ins */
17876 def_builtin (MASK_SSE4A, "__builtin_ia32_movntsd",
17877 void_ftype_pdouble_v2df, IX86_BUILTIN_MOVNTSD);
17878 def_builtin (MASK_SSE4A, "__builtin_ia32_movntss",
17879 void_ftype_pfloat_v4sf, IX86_BUILTIN_MOVNTSS);
17880 def_builtin (MASK_SSE4A, "__builtin_ia32_extrqi",
17881 v2di_ftype_v2di_unsigned_unsigned, IX86_BUILTIN_EXTRQI);
17882 def_builtin (MASK_SSE4A, "__builtin_ia32_extrq",
17883 v2di_ftype_v2di_v16qi, IX86_BUILTIN_EXTRQ);
17884 def_builtin (MASK_SSE4A, "__builtin_ia32_insertqi",
17885 v2di_ftype_v2di_v2di_unsigned_unsigned, IX86_BUILTIN_INSERTQI);
17886 def_builtin (MASK_SSE4A, "__builtin_ia32_insertq",
17887 v2di_ftype_v2di_v2di, IX86_BUILTIN_INSERTQ);
17889 /* Access to the vec_init patterns. */
17890 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
17891 integer_type_node, NULL_TREE);
17892 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si",
17893 ftype, IX86_BUILTIN_VEC_INIT_V2SI);
17895 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
17896 short_integer_type_node,
17897 short_integer_type_node,
17898 short_integer_type_node, NULL_TREE);
17899 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v4hi",
17900 ftype, IX86_BUILTIN_VEC_INIT_V4HI);
17902 ftype = build_function_type_list (V8QI_type_node, char_type_node,
17903 char_type_node, char_type_node,
17904 char_type_node, char_type_node,
17905 char_type_node, char_type_node,
17906 char_type_node, NULL_TREE);
17907 def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v8qi",
17908 ftype, IX86_BUILTIN_VEC_INIT_V8QI);
17910 /* Access to the vec_extract patterns. */
17911 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17912 integer_type_node, NULL_TREE);
17913 def_builtin (MASK_SSE2, "__builtin_ia32_vec_ext_v2df",
17914 ftype, IX86_BUILTIN_VEC_EXT_V2DF);
17916 ftype = build_function_type_list (long_long_integer_type_node,
17917 V2DI_type_node, integer_type_node,
17919 def_builtin (MASK_SSE2, "__builtin_ia32_vec_ext_v2di",
17920 ftype, IX86_BUILTIN_VEC_EXT_V2DI);
17922 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17923 integer_type_node, NULL_TREE);
17924 def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4sf",
17925 ftype, IX86_BUILTIN_VEC_EXT_V4SF);
17927 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17928 integer_type_node, NULL_TREE);
17929 def_builtin (MASK_SSE2, "__builtin_ia32_vec_ext_v4si",
17930 ftype, IX86_BUILTIN_VEC_EXT_V4SI);
17932 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17933 integer_type_node, NULL_TREE);
17934 def_builtin (MASK_SSE2, "__builtin_ia32_vec_ext_v8hi",
17935 ftype, IX86_BUILTIN_VEC_EXT_V8HI);
17937 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
17938 integer_type_node, NULL_TREE);
17939 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_ext_v4hi",
17940 ftype, IX86_BUILTIN_VEC_EXT_V4HI);
17942 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
17943 integer_type_node, NULL_TREE);
17944 def_builtin (MASK_MMX, "__builtin_ia32_vec_ext_v2si",
17945 ftype, IX86_BUILTIN_VEC_EXT_V2SI);
17947 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17948 integer_type_node, NULL_TREE);
17949 def_builtin (MASK_SSE2, "__builtin_ia32_vec_ext_v16qi",
17950 ftype, IX86_BUILTIN_VEC_EXT_V16QI);
17952 /* Access to the vec_set patterns. */
17953 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17955 integer_type_node, NULL_TREE);
17956 def_builtin (MASK_SSE4_1 | MASK_64BIT, "__builtin_ia32_vec_set_v2di",
17957 ftype, IX86_BUILTIN_VEC_SET_V2DI);
17959 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17961 integer_type_node, NULL_TREE);
17962 def_builtin (MASK_SSE4_1, "__builtin_ia32_vec_set_v4sf",
17963 ftype, IX86_BUILTIN_VEC_SET_V4SF);
17965 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17967 integer_type_node, NULL_TREE);
17968 def_builtin (MASK_SSE4_1, "__builtin_ia32_vec_set_v4si",
17969 ftype, IX86_BUILTIN_VEC_SET_V4SI);
17971 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17973 integer_type_node, NULL_TREE);
17974 def_builtin (MASK_SSE2, "__builtin_ia32_vec_set_v8hi",
17975 ftype, IX86_BUILTIN_VEC_SET_V8HI);
17977 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
17979 integer_type_node, NULL_TREE);
17980 def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_set_v4hi",
17981 ftype, IX86_BUILTIN_VEC_SET_V4HI);
17983 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17985 integer_type_node, NULL_TREE);
17986 def_builtin (MASK_SSE4_1, "__builtin_ia32_vec_set_v16qi",
17987 ftype, IX86_BUILTIN_VEC_SET_V16QI);
17991 ix86_init_builtins (void)
17994 ix86_init_mmx_sse_builtins ();
17997 /* Errors in the source file can cause expand_expr to return const0_rtx
17998 where we expect a vector. To avoid crashing, use one of the vector
17999 clear instructions. */
18001 safe_vector_operand (rtx x, enum machine_mode mode)
18003 if (x == const0_rtx)
18004 x = CONST0_RTX (mode);
18008 /* Subroutine of ix86_expand_builtin to take care of SSE insns with
18009 4 operands. The third argument must be a constant smaller than 8
18013 ix86_expand_sse_4_operands_builtin (enum insn_code icode, tree exp,
18017 tree arg0 = CALL_EXPR_ARG (exp, 0);
18018 tree arg1 = CALL_EXPR_ARG (exp, 1);
18019 tree arg2 = CALL_EXPR_ARG (exp, 2);
18020 rtx op0 = expand_normal (arg0);
18021 rtx op1 = expand_normal (arg1);
18022 rtx op2 = expand_normal (arg2);
18023 enum machine_mode tmode = insn_data[icode].operand[0].mode;
18024 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
18025 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
18026 enum machine_mode mode2;
18029 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
18030 op0 = copy_to_mode_reg (mode0, op0);
18031 if ((optimize && !register_operand (op1, mode1))
18032 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
18033 op1 = copy_to_mode_reg (mode1, op1);
18037 case CODE_FOR_sse4_1_blendvpd:
18038 case CODE_FOR_sse4_1_blendvps:
18039 case CODE_FOR_sse4_1_pblendvb:
18040 /* The third argument of variable blends must be xmm0. */
18041 xmm0 = gen_rtx_REG (tmode, FIRST_SSE_REG);
18042 emit_move_insn (xmm0, op2);
18046 mode2 = insn_data[icode].operand[2].mode;
18047 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
18051 case CODE_FOR_sse4_1_roundsd:
18052 case CODE_FOR_sse4_1_roundss:
18053 error ("the third argument must be a 4-bit immediate");
18056 error ("the third argument must be a 8-bit immediate");
18066 || GET_MODE (target) != tmode
18067 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18068 target = gen_reg_rtx (tmode);
18069 pat = GEN_FCN (icode) (target, op0, op1, op2);
18076 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
18079 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
18082 tree arg0 = CALL_EXPR_ARG (exp, 0);
18083 tree arg1 = CALL_EXPR_ARG (exp, 1);
18084 rtx op0 = expand_normal (arg0);
18085 rtx op1 = expand_normal (arg1);
18086 enum machine_mode tmode = insn_data[icode].operand[0].mode;
18087 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
18088 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
18090 if (VECTOR_MODE_P (mode0))
18091 op0 = safe_vector_operand (op0, mode0);
18092 if (VECTOR_MODE_P (mode1))
18093 op1 = safe_vector_operand (op1, mode1);
18095 if (optimize || !target
18096 || GET_MODE (target) != tmode
18097 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18098 target = gen_reg_rtx (tmode);
18100 if (GET_MODE (op1) == SImode && mode1 == TImode)
18102 rtx x = gen_reg_rtx (V4SImode);
18103 emit_insn (gen_sse2_loadd (x, op1));
18104 op1 = gen_lowpart (TImode, x);
18107 /* The insn must want input operands in the same modes as the
18109 gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
18110 && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
18112 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
18113 op0 = copy_to_mode_reg (mode0, op0);
18114 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
18115 op1 = copy_to_mode_reg (mode1, op1);
18117 /* ??? Using ix86_fixup_binary_operands is problematic when
18118 we've got mismatched modes. Fake it. */
18124 if (tmode == mode0 && tmode == mode1)
18126 target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops);
18130 else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops))
18132 op0 = force_reg (mode0, op0);
18133 op1 = force_reg (mode1, op1);
18134 target = gen_reg_rtx (tmode);
18137 pat = GEN_FCN (icode) (target, op0, op1);
18144 /* Subroutine of ix86_expand_builtin to take care of stores. */
18147 ix86_expand_store_builtin (enum insn_code icode, tree exp)
18150 tree arg0 = CALL_EXPR_ARG (exp, 0);
18151 tree arg1 = CALL_EXPR_ARG (exp, 1);
18152 rtx op0 = expand_normal (arg0);
18153 rtx op1 = expand_normal (arg1);
18154 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
18155 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
18157 if (VECTOR_MODE_P (mode1))
18158 op1 = safe_vector_operand (op1, mode1);
18160 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
18161 op1 = copy_to_mode_reg (mode1, op1);
18163 pat = GEN_FCN (icode) (op0, op1);
18169 /* Subroutine of ix86_expand_builtin to take care of unop insns. */
18172 ix86_expand_unop_builtin (enum insn_code icode, tree exp,
18173 rtx target, int do_load)
18176 tree arg0 = CALL_EXPR_ARG (exp, 0);
18177 rtx op0 = expand_normal (arg0);
18178 enum machine_mode tmode = insn_data[icode].operand[0].mode;
18179 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
18181 if (optimize || !target
18182 || GET_MODE (target) != tmode
18183 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18184 target = gen_reg_rtx (tmode);
18186 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
18189 if (VECTOR_MODE_P (mode0))
18190 op0 = safe_vector_operand (op0, mode0);
18192 if ((optimize && !register_operand (op0, mode0))
18193 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
18194 op0 = copy_to_mode_reg (mode0, op0);
18199 case CODE_FOR_sse4_1_roundpd:
18200 case CODE_FOR_sse4_1_roundps:
18202 tree arg1 = CALL_EXPR_ARG (exp, 1);
18203 rtx op1 = expand_normal (arg1);
18204 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
18206 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
18208 error ("the second argument must be a 4-bit immediate");
18211 pat = GEN_FCN (icode) (target, op0, op1);
18215 pat = GEN_FCN (icode) (target, op0);
18225 /* Subroutine of ix86_expand_builtin to take care of three special unop insns:
18226 sqrtss, rsqrtss, rcpss. */
18229 ix86_expand_unop1_builtin (enum insn_code icode, tree exp, rtx target)
18232 tree arg0 = CALL_EXPR_ARG (exp, 0);
18233 rtx op1, op0 = expand_normal (arg0);
18234 enum machine_mode tmode = insn_data[icode].operand[0].mode;
18235 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
18237 if (optimize || !target
18238 || GET_MODE (target) != tmode
18239 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18240 target = gen_reg_rtx (tmode);
18242 if (VECTOR_MODE_P (mode0))
18243 op0 = safe_vector_operand (op0, mode0);
18245 if ((optimize && !register_operand (op0, mode0))
18246 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
18247 op0 = copy_to_mode_reg (mode0, op0);
18250 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
18251 op1 = copy_to_mode_reg (mode0, op1);
18253 pat = GEN_FCN (icode) (target, op0, op1);
18260 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
18263 ix86_expand_sse_compare (const struct builtin_description *d, tree exp,
18267 tree arg0 = CALL_EXPR_ARG (exp, 0);
18268 tree arg1 = CALL_EXPR_ARG (exp, 1);
18269 rtx op0 = expand_normal (arg0);
18270 rtx op1 = expand_normal (arg1);
18272 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
18273 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
18274 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
18275 enum rtx_code comparison = d->comparison;
18277 if (VECTOR_MODE_P (mode0))
18278 op0 = safe_vector_operand (op0, mode0);
18279 if (VECTOR_MODE_P (mode1))
18280 op1 = safe_vector_operand (op1, mode1);
18282 /* Swap operands if we have a comparison that isn't available in
18284 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
18286 rtx tmp = gen_reg_rtx (mode1);
18287 emit_move_insn (tmp, op1);
18292 if (optimize || !target
18293 || GET_MODE (target) != tmode
18294 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
18295 target = gen_reg_rtx (tmode);
18297 if ((optimize && !register_operand (op0, mode0))
18298 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
18299 op0 = copy_to_mode_reg (mode0, op0);
18300 if ((optimize && !register_operand (op1, mode1))
18301 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
18302 op1 = copy_to_mode_reg (mode1, op1);
18304 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
18305 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
18312 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
18315 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
18319 tree arg0 = CALL_EXPR_ARG (exp, 0);
18320 tree arg1 = CALL_EXPR_ARG (exp, 1);
18321 rtx op0 = expand_normal (arg0);
18322 rtx op1 = expand_normal (arg1);
18323 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
18324 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
18325 enum rtx_code comparison = d->comparison;
18327 if (VECTOR_MODE_P (mode0))
18328 op0 = safe_vector_operand (op0, mode0);
18329 if (VECTOR_MODE_P (mode1))
18330 op1 = safe_vector_operand (op1, mode1);
18332 /* Swap operands if we have a comparison that isn't available in
18334 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
18341 target = gen_reg_rtx (SImode);
18342 emit_move_insn (target, const0_rtx);
18343 target = gen_rtx_SUBREG (QImode, target, 0);
18345 if ((optimize && !register_operand (op0, mode0))
18346 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
18347 op0 = copy_to_mode_reg (mode0, op0);
18348 if ((optimize && !register_operand (op1, mode1))
18349 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
18350 op1 = copy_to_mode_reg (mode1, op1);
18352 pat = GEN_FCN (d->icode) (op0, op1);
18356 emit_insn (gen_rtx_SET (VOIDmode,
18357 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
18358 gen_rtx_fmt_ee (comparison, QImode,
18362 return SUBREG_REG (target);
18365 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
18368 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
18372 tree arg0 = CALL_EXPR_ARG (exp, 0);
18373 tree arg1 = CALL_EXPR_ARG (exp, 1);
18374 rtx op0 = expand_normal (arg0);
18375 rtx op1 = expand_normal (arg1);
18376 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
18377 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
18378 enum rtx_code comparison = d->comparison;
18380 if (VECTOR_MODE_P (mode0))
18381 op0 = safe_vector_operand (op0, mode0);
18382 if (VECTOR_MODE_P (mode1))
18383 op1 = safe_vector_operand (op1, mode1);
18385 target = gen_reg_rtx (SImode);
18386 emit_move_insn (target, const0_rtx);
18387 target = gen_rtx_SUBREG (QImode, target, 0);
18389 if ((optimize && !register_operand (op0, mode0))
18390 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
18391 op0 = copy_to_mode_reg (mode0, op0);
18392 if ((optimize && !register_operand (op1, mode1))
18393 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
18394 op1 = copy_to_mode_reg (mode1, op1);
18396 pat = GEN_FCN (d->icode) (op0, op1);
18400 emit_insn (gen_rtx_SET (VOIDmode,
18401 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
18402 gen_rtx_fmt_ee (comparison, QImode,
18406 return SUBREG_REG (target);
18409 /* Return the integer constant in ARG. Constrain it to be in the range
18410 of the subparts of VEC_TYPE; issue an error if not. */
18413 get_element_number (tree vec_type, tree arg)
18415 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
18417 if (!host_integerp (arg, 1)
18418 || (elt = tree_low_cst (arg, 1), elt > max))
18420 error ("selector must be an integer constant in the range 0..%wi", max);
18427 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
18428 ix86_expand_vector_init. We DO have language-level syntax for this, in
18429 the form of (type){ init-list }. Except that since we can't place emms
18430 instructions from inside the compiler, we can't allow the use of MMX
18431 registers unless the user explicitly asks for it. So we do *not* define
18432 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
18433 we have builtins invoked by mmintrin.h that gives us license to emit
18434 these sorts of instructions. */
18437 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
18439 enum machine_mode tmode = TYPE_MODE (type);
18440 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
18441 int i, n_elt = GET_MODE_NUNITS (tmode);
18442 rtvec v = rtvec_alloc (n_elt);
18444 gcc_assert (VECTOR_MODE_P (tmode));
18445 gcc_assert (call_expr_nargs (exp) == n_elt);
18447 for (i = 0; i < n_elt; ++i)
18449 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
18450 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
18453 if (!target || !register_operand (target, tmode))
18454 target = gen_reg_rtx (tmode);
18456 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
18460 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
18461 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
18462 had a language-level syntax for referencing vector elements. */
18465 ix86_expand_vec_ext_builtin (tree exp, rtx target)
18467 enum machine_mode tmode, mode0;
18472 arg0 = CALL_EXPR_ARG (exp, 0);
18473 arg1 = CALL_EXPR_ARG (exp, 1);
18475 op0 = expand_normal (arg0);
18476 elt = get_element_number (TREE_TYPE (arg0), arg1);
18478 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
18479 mode0 = TYPE_MODE (TREE_TYPE (arg0));
18480 gcc_assert (VECTOR_MODE_P (mode0));
18482 op0 = force_reg (mode0, op0);
18484 if (optimize || !target || !register_operand (target, tmode))
18485 target = gen_reg_rtx (tmode);
18487 ix86_expand_vector_extract (true, target, op0, elt);
18492 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
18493 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
18494 a language-level syntax for referencing vector elements. */
18497 ix86_expand_vec_set_builtin (tree exp)
18499 enum machine_mode tmode, mode1;
18500 tree arg0, arg1, arg2;
18502 rtx op0, op1, target;
18504 arg0 = CALL_EXPR_ARG (exp, 0);
18505 arg1 = CALL_EXPR_ARG (exp, 1);
18506 arg2 = CALL_EXPR_ARG (exp, 2);
18508 tmode = TYPE_MODE (TREE_TYPE (arg0));
18509 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
18510 gcc_assert (VECTOR_MODE_P (tmode));
18512 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
18513 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
18514 elt = get_element_number (TREE_TYPE (arg0), arg2);
18516 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
18517 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
18519 op0 = force_reg (tmode, op0);
18520 op1 = force_reg (mode1, op1);
18522 /* OP0 is the source of these builtin functions and shouldn't be
18523 modified. Create a copy, use it and return it as target. */
18524 target = gen_reg_rtx (tmode);
18525 emit_move_insn (target, op0);
18526 ix86_expand_vector_set (true, target, op1, elt);
18531 /* Expand an expression EXP that calls a built-in function,
18532 with result going to TARGET if that's convenient
18533 (and in mode MODE if that's convenient).
18534 SUBTARGET may be used as the target for computing one of EXP's operands.
18535 IGNORE is nonzero if the value is to be ignored. */
18538 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
18539 enum machine_mode mode ATTRIBUTE_UNUSED,
18540 int ignore ATTRIBUTE_UNUSED)
18542 const struct builtin_description *d;
18544 enum insn_code icode;
18545 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
18546 tree arg0, arg1, arg2, arg3;
18547 rtx op0, op1, op2, op3, pat;
18548 enum machine_mode tmode, mode0, mode1, mode2, mode3, mode4;
18549 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
18553 case IX86_BUILTIN_EMMS:
18554 emit_insn (gen_mmx_emms ());
18557 case IX86_BUILTIN_SFENCE:
18558 emit_insn (gen_sse_sfence ());
18561 case IX86_BUILTIN_MASKMOVQ:
18562 case IX86_BUILTIN_MASKMOVDQU:
18563 icode = (fcode == IX86_BUILTIN_MASKMOVQ
18564 ? CODE_FOR_mmx_maskmovq
18565 : CODE_FOR_sse2_maskmovdqu);
18566 /* Note the arg order is different from the operand order. */
18567 arg1 = CALL_EXPR_ARG (exp, 0);
18568 arg2 = CALL_EXPR_ARG (exp, 1);
18569 arg0 = CALL_EXPR_ARG (exp, 2);
18570 op0 = expand_normal (arg0);
18571 op1 = expand_normal (arg1);
18572 op2 = expand_normal (arg2);
18573 mode0 = insn_data[icode].operand[0].mode;
18574 mode1 = insn_data[icode].operand[1].mode;
18575 mode2 = insn_data[icode].operand[2].mode;
18577 op0 = force_reg (Pmode, op0);
18578 op0 = gen_rtx_MEM (mode1, op0);
18580 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
18581 op0 = copy_to_mode_reg (mode0, op0);
18582 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
18583 op1 = copy_to_mode_reg (mode1, op1);
18584 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
18585 op2 = copy_to_mode_reg (mode2, op2);
18586 pat = GEN_FCN (icode) (op0, op1, op2);
18592 case IX86_BUILTIN_SQRTSS:
18593 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, exp, target);
18594 case IX86_BUILTIN_RSQRTSS:
18595 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, exp, target);
18596 case IX86_BUILTIN_RCPSS:
18597 return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, exp, target);
18599 case IX86_BUILTIN_LOADUPS:
18600 return ix86_expand_unop_builtin (CODE_FOR_sse_movups, exp, target, 1);
18602 case IX86_BUILTIN_STOREUPS:
18603 return ix86_expand_store_builtin (CODE_FOR_sse_movups, exp);
18605 case IX86_BUILTIN_LOADHPS:
18606 case IX86_BUILTIN_LOADLPS:
18607 case IX86_BUILTIN_LOADHPD:
18608 case IX86_BUILTIN_LOADLPD:
18609 icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps
18610 : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps
18611 : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd
18612 : CODE_FOR_sse2_loadlpd);
18613 arg0 = CALL_EXPR_ARG (exp, 0);
18614 arg1 = CALL_EXPR_ARG (exp, 1);
18615 op0 = expand_normal (arg0);
18616 op1 = expand_normal (arg1);
18617 tmode = insn_data[icode].operand[0].mode;
18618 mode0 = insn_data[icode].operand[1].mode;
18619 mode1 = insn_data[icode].operand[2].mode;
18621 op0 = force_reg (mode0, op0);
18622 op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
18623 if (optimize || target == 0
18624 || GET_MODE (target) != tmode
18625 || !register_operand (target, tmode))
18626 target = gen_reg_rtx (tmode);
18627 pat = GEN_FCN (icode) (target, op0, op1);
18633 case IX86_BUILTIN_STOREHPS:
18634 case IX86_BUILTIN_STORELPS:
18635 icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps
18636 : CODE_FOR_sse_storelps);
18637 arg0 = CALL_EXPR_ARG (exp, 0);
18638 arg1 = CALL_EXPR_ARG (exp, 1);
18639 op0 = expand_normal (arg0);
18640 op1 = expand_normal (arg1);
18641 mode0 = insn_data[icode].operand[0].mode;
18642 mode1 = insn_data[icode].operand[1].mode;
18644 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
18645 op1 = force_reg (mode1, op1);
18647 pat = GEN_FCN (icode) (op0, op1);
18653 case IX86_BUILTIN_MOVNTPS:
18654 return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, exp);
18655 case IX86_BUILTIN_MOVNTQ:
18656 return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, exp);
18658 case IX86_BUILTIN_LDMXCSR:
18659 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
18660 target = assign_386_stack_local (SImode, SLOT_TEMP);
18661 emit_move_insn (target, op0);
18662 emit_insn (gen_sse_ldmxcsr (target));
18665 case IX86_BUILTIN_STMXCSR:
18666 target = assign_386_stack_local (SImode, SLOT_TEMP);
18667 emit_insn (gen_sse_stmxcsr (target));
18668 return copy_to_mode_reg (SImode, target);
18670 case IX86_BUILTIN_SHUFPS:
18671 case IX86_BUILTIN_SHUFPD:
18672 icode = (fcode == IX86_BUILTIN_SHUFPS
18673 ? CODE_FOR_sse_shufps
18674 : CODE_FOR_sse2_shufpd);
18675 arg0 = CALL_EXPR_ARG (exp, 0);
18676 arg1 = CALL_EXPR_ARG (exp, 1);
18677 arg2 = CALL_EXPR_ARG (exp, 2);
18678 op0 = expand_normal (arg0);
18679 op1 = expand_normal (arg1);
18680 op2 = expand_normal (arg2);
18681 tmode = insn_data[icode].operand[0].mode;
18682 mode0 = insn_data[icode].operand[1].mode;
18683 mode1 = insn_data[icode].operand[2].mode;
18684 mode2 = insn_data[icode].operand[3].mode;
18686 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
18687 op0 = copy_to_mode_reg (mode0, op0);
18688 if ((optimize && !register_operand (op1, mode1))
18689 || !(*insn_data[icode].operand[2].predicate) (op1, mode1))
18690 op1 = copy_to_mode_reg (mode1, op1);
18691 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
18693 /* @@@ better error message */
18694 error ("mask must be an immediate");
18695 return gen_reg_rtx (tmode);
18697 if (optimize || target == 0
18698 || GET_MODE (target) != tmode
18699 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18700 target = gen_reg_rtx (tmode);
18701 pat = GEN_FCN (icode) (target, op0, op1, op2);
18707 case IX86_BUILTIN_PSHUFW:
18708 case IX86_BUILTIN_PSHUFD:
18709 case IX86_BUILTIN_PSHUFHW:
18710 case IX86_BUILTIN_PSHUFLW:
18711 icode = ( fcode == IX86_BUILTIN_PSHUFHW ? CODE_FOR_sse2_pshufhw
18712 : fcode == IX86_BUILTIN_PSHUFLW ? CODE_FOR_sse2_pshuflw
18713 : fcode == IX86_BUILTIN_PSHUFD ? CODE_FOR_sse2_pshufd
18714 : CODE_FOR_mmx_pshufw);
18715 arg0 = CALL_EXPR_ARG (exp, 0);
18716 arg1 = CALL_EXPR_ARG (exp, 1);
18717 op0 = expand_normal (arg0);
18718 op1 = expand_normal (arg1);
18719 tmode = insn_data[icode].operand[0].mode;
18720 mode1 = insn_data[icode].operand[1].mode;
18721 mode2 = insn_data[icode].operand[2].mode;
18723 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
18724 op0 = copy_to_mode_reg (mode1, op0);
18725 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
18727 /* @@@ better error message */
18728 error ("mask must be an immediate");
18732 || GET_MODE (target) != tmode
18733 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
18734 target = gen_reg_rtx (tmode);
18735 pat = GEN_FCN (icode) (target, op0, op1);
18741 case IX86_BUILTIN_PSLLWI128:
18742 icode = CODE_FOR_ashlv8hi3;
18744 case IX86_BUILTIN_PSLLDI128:
18745 icode = CODE_FOR_ashlv4si3;
18747 case IX86_BUILTIN_PSLLQI128:
18748 icode = CODE_FOR_ashlv2di3;
18750 case IX86_BUILTIN_PSRAWI128:
18751 icode = CODE_FOR_ashrv8hi3;
18753 case IX86_BUILTIN_PSRADI128:
18754 icode = CODE_FOR_ashrv4si3;
18756 case IX86_BUILTIN_PSRLWI128:
18757 icode = CODE_FOR_lshrv8hi3;
18759 case IX86_BUILTIN_PSRLDI128:
18760 icode = CODE_FOR_lshrv4si3;
18762 case IX86_BUILTIN_PSRLQI128:
18763 icode = CODE_FOR_lshrv2di3;
18766 arg0 = CALL_EXPR_ARG (exp, 0);
18767 arg1 = CALL_EXPR_ARG (exp, 1);
18768 op0 = expand_normal (arg0);
18769 op1 = expand_normal (arg1);
18771 if (!CONST_INT_P (op1))
18773 error ("shift must be an immediate");
18776 if (INTVAL (op1) < 0 || INTVAL (op1) > 255)
18777 op1 = GEN_INT (255);
18779 tmode = insn_data[icode].operand[0].mode;
18780 mode1 = insn_data[icode].operand[1].mode;
18781 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
18782 op0 = copy_to_reg (op0);
18784 target = gen_reg_rtx (tmode);
18785 pat = GEN_FCN (icode) (target, op0, op1);
18791 case IX86_BUILTIN_PSLLW128:
18792 icode = CODE_FOR_ashlv8hi3;
18794 case IX86_BUILTIN_PSLLD128:
18795 icode = CODE_FOR_ashlv4si3;
18797 case IX86_BUILTIN_PSLLQ128:
18798 icode = CODE_FOR_ashlv2di3;
18800 case IX86_BUILTIN_PSRAW128:
18801 icode = CODE_FOR_ashrv8hi3;
18803 case IX86_BUILTIN_PSRAD128:
18804 icode = CODE_FOR_ashrv4si3;
18806 case IX86_BUILTIN_PSRLW128:
18807 icode = CODE_FOR_lshrv8hi3;
18809 case IX86_BUILTIN_PSRLD128:
18810 icode = CODE_FOR_lshrv4si3;
18812 case IX86_BUILTIN_PSRLQ128:
18813 icode = CODE_FOR_lshrv2di3;
18816 arg0 = CALL_EXPR_ARG (exp, 0);
18817 arg1 = CALL_EXPR_ARG (exp, 1);
18818 op0 = expand_normal (arg0);
18819 op1 = expand_normal (arg1);
18821 tmode = insn_data[icode].operand[0].mode;
18822 mode1 = insn_data[icode].operand[1].mode;
18824 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
18825 op0 = copy_to_reg (op0);
18827 op1 = simplify_gen_subreg (TImode, op1, GET_MODE (op1), 0);
18828 if (! (*insn_data[icode].operand[2].predicate) (op1, TImode))
18829 op1 = copy_to_reg (op1);
18831 target = gen_reg_rtx (tmode);
18832 pat = GEN_FCN (icode) (target, op0, op1);
18838 case IX86_BUILTIN_PSLLDQI128:
18839 case IX86_BUILTIN_PSRLDQI128:
18840 icode = (fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3
18841 : CODE_FOR_sse2_lshrti3);
18842 arg0 = CALL_EXPR_ARG (exp, 0);
18843 arg1 = CALL_EXPR_ARG (exp, 1);
18844 op0 = expand_normal (arg0);
18845 op1 = expand_normal (arg1);
18846 tmode = insn_data[icode].operand[0].mode;
18847 mode1 = insn_data[icode].operand[1].mode;
18848 mode2 = insn_data[icode].operand[2].mode;
18850 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
18852 op0 = copy_to_reg (op0);
18853 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
18855 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
18857 error ("shift must be an immediate");
18860 target = gen_reg_rtx (V2DImode);
18861 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0),
18868 case IX86_BUILTIN_FEMMS:
18869 emit_insn (gen_mmx_femms ());
18872 case IX86_BUILTIN_PAVGUSB:
18873 return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, exp, target);
18875 case IX86_BUILTIN_PF2ID:
18876 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, exp, target, 0);
18878 case IX86_BUILTIN_PFACC:
18879 return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, exp, target);
18881 case IX86_BUILTIN_PFADD:
18882 return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, exp, target);
18884 case IX86_BUILTIN_PFCMPEQ:
18885 return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, exp, target);
18887 case IX86_BUILTIN_PFCMPGE:
18888 return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, exp, target);
18890 case IX86_BUILTIN_PFCMPGT:
18891 return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, exp, target);
18893 case IX86_BUILTIN_PFMAX:
18894 return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, exp, target);
18896 case IX86_BUILTIN_PFMIN:
18897 return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, exp, target);
18899 case IX86_BUILTIN_PFMUL:
18900 return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, exp, target);
18902 case IX86_BUILTIN_PFRCP:
18903 return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, exp, target, 0);
18905 case IX86_BUILTIN_PFRCPIT1:
18906 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, exp, target);
18908 case IX86_BUILTIN_PFRCPIT2:
18909 return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, exp, target);
18911 case IX86_BUILTIN_PFRSQIT1:
18912 return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, exp, target);
18914 case IX86_BUILTIN_PFRSQRT:
18915 return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, exp, target, 0);
18917 case IX86_BUILTIN_PFSUB:
18918 return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, exp, target);
18920 case IX86_BUILTIN_PFSUBR:
18921 return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, exp, target);
18923 case IX86_BUILTIN_PI2FD:
18924 return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, exp, target, 0);
18926 case IX86_BUILTIN_PMULHRW:
18927 return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, exp, target);
18929 case IX86_BUILTIN_PF2IW:
18930 return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, exp, target, 0);
18932 case IX86_BUILTIN_PFNACC:
18933 return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, exp, target);
18935 case IX86_BUILTIN_PFPNACC:
18936 return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, exp, target);
18938 case IX86_BUILTIN_PI2FW:
18939 return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, exp, target, 0);
18941 case IX86_BUILTIN_PSWAPDSI:
18942 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, exp, target, 0);
18944 case IX86_BUILTIN_PSWAPDSF:
18945 return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, exp, target, 0);
18947 case IX86_BUILTIN_SQRTSD:
18948 return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, exp, target);
18949 case IX86_BUILTIN_LOADUPD:
18950 return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, exp, target, 1);
18951 case IX86_BUILTIN_STOREUPD:
18952 return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, exp);
18954 case IX86_BUILTIN_MFENCE:
18955 emit_insn (gen_sse2_mfence ());
18957 case IX86_BUILTIN_LFENCE:
18958 emit_insn (gen_sse2_lfence ());
18961 case IX86_BUILTIN_CLFLUSH:
18962 arg0 = CALL_EXPR_ARG (exp, 0);
18963 op0 = expand_normal (arg0);
18964 icode = CODE_FOR_sse2_clflush;
18965 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
18966 op0 = copy_to_mode_reg (Pmode, op0);
18968 emit_insn (gen_sse2_clflush (op0));
18971 case IX86_BUILTIN_MOVNTPD:
18972 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2df, exp);
18973 case IX86_BUILTIN_MOVNTDQ:
18974 return ix86_expand_store_builtin (CODE_FOR_sse2_movntv2di, exp);
18975 case IX86_BUILTIN_MOVNTI:
18976 return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, exp);
18978 case IX86_BUILTIN_LOADDQU:
18979 return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, exp, target, 1);
18980 case IX86_BUILTIN_STOREDQU:
18981 return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, exp);
18983 case IX86_BUILTIN_MONITOR:
18984 arg0 = CALL_EXPR_ARG (exp, 0);
18985 arg1 = CALL_EXPR_ARG (exp, 1);
18986 arg2 = CALL_EXPR_ARG (exp, 2);
18987 op0 = expand_normal (arg0);
18988 op1 = expand_normal (arg1);
18989 op2 = expand_normal (arg2);
18991 op0 = copy_to_mode_reg (Pmode, op0);
18993 op1 = copy_to_mode_reg (SImode, op1);
18995 op2 = copy_to_mode_reg (SImode, op2);
18997 emit_insn (gen_sse3_monitor (op0, op1, op2));
18999 emit_insn (gen_sse3_monitor64 (op0, op1, op2));
19002 case IX86_BUILTIN_MWAIT:
19003 arg0 = CALL_EXPR_ARG (exp, 0);
19004 arg1 = CALL_EXPR_ARG (exp, 1);
19005 op0 = expand_normal (arg0);
19006 op1 = expand_normal (arg1);
19008 op0 = copy_to_mode_reg (SImode, op0);
19010 op1 = copy_to_mode_reg (SImode, op1);
19011 emit_insn (gen_sse3_mwait (op0, op1));
19014 case IX86_BUILTIN_LDDQU:
19015 return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, exp,
19018 case IX86_BUILTIN_PALIGNR:
19019 case IX86_BUILTIN_PALIGNR128:
19020 if (fcode == IX86_BUILTIN_PALIGNR)
19022 icode = CODE_FOR_ssse3_palignrdi;
19027 icode = CODE_FOR_ssse3_palignrti;
19030 arg0 = CALL_EXPR_ARG (exp, 0);
19031 arg1 = CALL_EXPR_ARG (exp, 1);
19032 arg2 = CALL_EXPR_ARG (exp, 2);
19033 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
19034 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
19035 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
19036 tmode = insn_data[icode].operand[0].mode;
19037 mode1 = insn_data[icode].operand[1].mode;
19038 mode2 = insn_data[icode].operand[2].mode;
19039 mode3 = insn_data[icode].operand[3].mode;
19041 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19043 op0 = copy_to_reg (op0);
19044 op0 = simplify_gen_subreg (mode1, op0, GET_MODE (op0), 0);
19046 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
19048 op1 = copy_to_reg (op1);
19049 op1 = simplify_gen_subreg (mode2, op1, GET_MODE (op1), 0);
19051 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
19053 error ("shift must be an immediate");
19056 target = gen_reg_rtx (mode);
19057 pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, mode, 0),
19064 case IX86_BUILTIN_MOVNTDQA:
19065 return ix86_expand_unop_builtin (CODE_FOR_sse4_1_movntdqa, exp,
19068 case IX86_BUILTIN_MOVNTSD:
19069 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv2df, exp);
19071 case IX86_BUILTIN_MOVNTSS:
19072 return ix86_expand_store_builtin (CODE_FOR_sse4a_vmmovntv4sf, exp);
19074 case IX86_BUILTIN_INSERTQ:
19075 case IX86_BUILTIN_EXTRQ:
19076 icode = (fcode == IX86_BUILTIN_EXTRQ
19077 ? CODE_FOR_sse4a_extrq
19078 : CODE_FOR_sse4a_insertq);
19079 arg0 = CALL_EXPR_ARG (exp, 0);
19080 arg1 = CALL_EXPR_ARG (exp, 1);
19081 op0 = expand_normal (arg0);
19082 op1 = expand_normal (arg1);
19083 tmode = insn_data[icode].operand[0].mode;
19084 mode1 = insn_data[icode].operand[1].mode;
19085 mode2 = insn_data[icode].operand[2].mode;
19086 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19087 op0 = copy_to_mode_reg (mode1, op0);
19088 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
19089 op1 = copy_to_mode_reg (mode2, op1);
19090 if (optimize || target == 0
19091 || GET_MODE (target) != tmode
19092 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19093 target = gen_reg_rtx (tmode);
19094 pat = GEN_FCN (icode) (target, op0, op1);
19100 case IX86_BUILTIN_EXTRQI:
19101 icode = CODE_FOR_sse4a_extrqi;
19102 arg0 = CALL_EXPR_ARG (exp, 0);
19103 arg1 = CALL_EXPR_ARG (exp, 1);
19104 arg2 = CALL_EXPR_ARG (exp, 2);
19105 op0 = expand_normal (arg0);
19106 op1 = expand_normal (arg1);
19107 op2 = expand_normal (arg2);
19108 tmode = insn_data[icode].operand[0].mode;
19109 mode1 = insn_data[icode].operand[1].mode;
19110 mode2 = insn_data[icode].operand[2].mode;
19111 mode3 = insn_data[icode].operand[3].mode;
19112 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19113 op0 = copy_to_mode_reg (mode1, op0);
19114 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
19116 error ("index mask must be an immediate");
19117 return gen_reg_rtx (tmode);
19119 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
19121 error ("length mask must be an immediate");
19122 return gen_reg_rtx (tmode);
19124 if (optimize || target == 0
19125 || GET_MODE (target) != tmode
19126 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19127 target = gen_reg_rtx (tmode);
19128 pat = GEN_FCN (icode) (target, op0, op1, op2);
19134 case IX86_BUILTIN_INSERTQI:
19135 icode = CODE_FOR_sse4a_insertqi;
19136 arg0 = CALL_EXPR_ARG (exp, 0);
19137 arg1 = CALL_EXPR_ARG (exp, 1);
19138 arg2 = CALL_EXPR_ARG (exp, 2);
19139 arg3 = CALL_EXPR_ARG (exp, 3);
19140 op0 = expand_normal (arg0);
19141 op1 = expand_normal (arg1);
19142 op2 = expand_normal (arg2);
19143 op3 = expand_normal (arg3);
19144 tmode = insn_data[icode].operand[0].mode;
19145 mode1 = insn_data[icode].operand[1].mode;
19146 mode2 = insn_data[icode].operand[2].mode;
19147 mode3 = insn_data[icode].operand[3].mode;
19148 mode4 = insn_data[icode].operand[4].mode;
19150 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
19151 op0 = copy_to_mode_reg (mode1, op0);
19153 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
19154 op1 = copy_to_mode_reg (mode2, op1);
19156 if (! (*insn_data[icode].operand[3].predicate) (op2, mode3))
19158 error ("index mask must be an immediate");
19159 return gen_reg_rtx (tmode);
19161 if (! (*insn_data[icode].operand[4].predicate) (op3, mode4))
19163 error ("length mask must be an immediate");
19164 return gen_reg_rtx (tmode);
19166 if (optimize || target == 0
19167 || GET_MODE (target) != tmode
19168 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
19169 target = gen_reg_rtx (tmode);
19170 pat = GEN_FCN (icode) (target, op0, op1, op2, op3);
19176 case IX86_BUILTIN_VEC_INIT_V2SI:
19177 case IX86_BUILTIN_VEC_INIT_V4HI:
19178 case IX86_BUILTIN_VEC_INIT_V8QI:
19179 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
19181 case IX86_BUILTIN_VEC_EXT_V2DF:
19182 case IX86_BUILTIN_VEC_EXT_V2DI:
19183 case IX86_BUILTIN_VEC_EXT_V4SF:
19184 case IX86_BUILTIN_VEC_EXT_V4SI:
19185 case IX86_BUILTIN_VEC_EXT_V8HI:
19186 case IX86_BUILTIN_VEC_EXT_V2SI:
19187 case IX86_BUILTIN_VEC_EXT_V4HI:
19188 case IX86_BUILTIN_VEC_EXT_V16QI:
19189 return ix86_expand_vec_ext_builtin (exp, target);
19191 case IX86_BUILTIN_VEC_SET_V2DI:
19192 case IX86_BUILTIN_VEC_SET_V4SF:
19193 case IX86_BUILTIN_VEC_SET_V4SI:
19194 case IX86_BUILTIN_VEC_SET_V8HI:
19195 case IX86_BUILTIN_VEC_SET_V4HI:
19196 case IX86_BUILTIN_VEC_SET_V16QI:
19197 return ix86_expand_vec_set_builtin (exp);
19203 for (i = 0, d = bdesc_sse_3arg;
19204 i < ARRAY_SIZE (bdesc_sse_3arg);
19206 if (d->code == fcode)
19207 return ix86_expand_sse_4_operands_builtin (d->icode, exp,
19210 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
19211 if (d->code == fcode)
19213 /* Compares are treated specially. */
19214 if (d->icode == CODE_FOR_sse_maskcmpv4sf3
19215 || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3
19216 || d->icode == CODE_FOR_sse2_maskcmpv2df3
19217 || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3)
19218 return ix86_expand_sse_compare (d, exp, target);
19220 return ix86_expand_binop_builtin (d->icode, exp, target);
19223 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
19224 if (d->code == fcode)
19225 return ix86_expand_unop_builtin (d->icode, exp, target, 0);
19227 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
19228 if (d->code == fcode)
19229 return ix86_expand_sse_comi (d, exp, target);
19231 for (i = 0, d = bdesc_ptest; i < ARRAY_SIZE (bdesc_ptest); i++, d++)
19232 if (d->code == fcode)
19233 return ix86_expand_sse_ptest (d, exp, target);
19235 gcc_unreachable ();
19238 /* Returns a function decl for a vectorized version of the builtin function
19239 with builtin function code FN and the result vector type TYPE, or NULL_TREE
19240 if it is not available. */
19243 ix86_builtin_vectorized_function (enum built_in_function fn, tree type_out,
19246 enum machine_mode in_mode, out_mode;
19249 if (TREE_CODE (type_out) != VECTOR_TYPE
19250 || TREE_CODE (type_in) != VECTOR_TYPE)
19253 out_mode = TYPE_MODE (TREE_TYPE (type_out));
19254 out_n = TYPE_VECTOR_SUBPARTS (type_out);
19255 in_mode = TYPE_MODE (TREE_TYPE (type_in));
19256 in_n = TYPE_VECTOR_SUBPARTS (type_in);
19260 case BUILT_IN_SQRT:
19261 if (out_mode == DFmode && out_n == 2
19262 && in_mode == DFmode && in_n == 2)
19263 return ix86_builtins[IX86_BUILTIN_SQRTPD];
19266 case BUILT_IN_SQRTF:
19267 if (out_mode == SFmode && out_n == 4
19268 && in_mode == SFmode && in_n == 4)
19269 return ix86_builtins[IX86_BUILTIN_SQRTPS];
19272 case BUILT_IN_LRINTF:
19273 if (out_mode == SImode && out_n == 4
19274 && in_mode == SFmode && in_n == 4)
19275 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
19285 /* Returns a decl of a function that implements conversion of the
19286 input vector of type TYPE, or NULL_TREE if it is not available. */
19289 ix86_builtin_conversion (enum tree_code code, tree type)
19291 if (TREE_CODE (type) != VECTOR_TYPE)
19297 switch (TYPE_MODE (type))
19300 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
19305 case FIX_TRUNC_EXPR:
19306 switch (TYPE_MODE (type))
19309 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
19319 /* Store OPERAND to the memory after reload is completed. This means
19320 that we can't easily use assign_stack_local. */
19322 ix86_force_to_memory (enum machine_mode mode, rtx operand)
19326 gcc_assert (reload_completed);
19327 if (TARGET_RED_ZONE)
19329 result = gen_rtx_MEM (mode,
19330 gen_rtx_PLUS (Pmode,
19332 GEN_INT (-RED_ZONE_SIZE)));
19333 emit_move_insn (result, operand);
19335 else if (!TARGET_RED_ZONE && TARGET_64BIT)
19341 operand = gen_lowpart (DImode, operand);
19345 gen_rtx_SET (VOIDmode,
19346 gen_rtx_MEM (DImode,
19347 gen_rtx_PRE_DEC (DImode,
19348 stack_pointer_rtx)),
19352 gcc_unreachable ();
19354 result = gen_rtx_MEM (mode, stack_pointer_rtx);
19363 split_di (&operand, 1, operands, operands + 1);
19365 gen_rtx_SET (VOIDmode,
19366 gen_rtx_MEM (SImode,
19367 gen_rtx_PRE_DEC (Pmode,
19368 stack_pointer_rtx)),
19371 gen_rtx_SET (VOIDmode,
19372 gen_rtx_MEM (SImode,
19373 gen_rtx_PRE_DEC (Pmode,
19374 stack_pointer_rtx)),
19379 /* Store HImodes as SImodes. */
19380 operand = gen_lowpart (SImode, operand);
19384 gen_rtx_SET (VOIDmode,
19385 gen_rtx_MEM (GET_MODE (operand),
19386 gen_rtx_PRE_DEC (SImode,
19387 stack_pointer_rtx)),
19391 gcc_unreachable ();
19393 result = gen_rtx_MEM (mode, stack_pointer_rtx);
19398 /* Free operand from the memory. */
19400 ix86_free_from_memory (enum machine_mode mode)
19402 if (!TARGET_RED_ZONE)
19406 if (mode == DImode || TARGET_64BIT)
19410 /* Use LEA to deallocate stack space. In peephole2 it will be converted
19411 to pop or add instruction if registers are available. */
19412 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
19413 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
19418 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
19419 QImode must go into class Q_REGS.
19420 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
19421 movdf to do mem-to-mem moves through integer regs. */
19423 ix86_preferred_reload_class (rtx x, enum reg_class class)
19425 enum machine_mode mode = GET_MODE (x);
19427 /* We're only allowed to return a subclass of CLASS. Many of the
19428 following checks fail for NO_REGS, so eliminate that early. */
19429 if (class == NO_REGS)
19432 /* All classes can load zeros. */
19433 if (x == CONST0_RTX (mode))
19436 /* Force constants into memory if we are loading a (nonzero) constant into
19437 an MMX or SSE register. This is because there are no MMX/SSE instructions
19438 to load from a constant. */
19440 && (MAYBE_MMX_CLASS_P (class) || MAYBE_SSE_CLASS_P (class)))
19443 /* Prefer SSE regs only, if we can use them for math. */
19444 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
19445 return SSE_CLASS_P (class) ? class : NO_REGS;
19447 /* Floating-point constants need more complex checks. */
19448 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
19450 /* General regs can load everything. */
19451 if (reg_class_subset_p (class, GENERAL_REGS))
19454 /* Floats can load 0 and 1 plus some others. Note that we eliminated
19455 zero above. We only want to wind up preferring 80387 registers if
19456 we plan on doing computation with them. */
19458 && standard_80387_constant_p (x))
19460 /* Limit class to non-sse. */
19461 if (class == FLOAT_SSE_REGS)
19463 if (class == FP_TOP_SSE_REGS)
19465 if (class == FP_SECOND_SSE_REGS)
19466 return FP_SECOND_REG;
19467 if (class == FLOAT_INT_REGS || class == FLOAT_REGS)
19474 /* Generally when we see PLUS here, it's the function invariant
19475 (plus soft-fp const_int). Which can only be computed into general
19477 if (GET_CODE (x) == PLUS)
19478 return reg_class_subset_p (class, GENERAL_REGS) ? class : NO_REGS;
19480 /* QImode constants are easy to load, but non-constant QImode data
19481 must go into Q_REGS. */
19482 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
19484 if (reg_class_subset_p (class, Q_REGS))
19486 if (reg_class_subset_p (Q_REGS, class))
19494 /* Discourage putting floating-point values in SSE registers unless
19495 SSE math is being used, and likewise for the 387 registers. */
19497 ix86_preferred_output_reload_class (rtx x, enum reg_class class)
19499 enum machine_mode mode = GET_MODE (x);
19501 /* Restrict the output reload class to the register bank that we are doing
19502 math on. If we would like not to return a subset of CLASS, reject this
19503 alternative: if reload cannot do this, it will still use its choice. */
19504 mode = GET_MODE (x);
19505 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
19506 return MAYBE_SSE_CLASS_P (class) ? SSE_REGS : NO_REGS;
19508 if (X87_FLOAT_MODE_P (mode))
19510 if (class == FP_TOP_SSE_REGS)
19512 else if (class == FP_SECOND_SSE_REGS)
19513 return FP_SECOND_REG;
19515 return FLOAT_CLASS_P (class) ? class : NO_REGS;
19521 /* If we are copying between general and FP registers, we need a memory
19522 location. The same is true for SSE and MMX registers.
19524 The macro can't work reliably when one of the CLASSES is class containing
19525 registers from multiple units (SSE, MMX, integer). We avoid this by never
19526 combining those units in single alternative in the machine description.
19527 Ensure that this constraint holds to avoid unexpected surprises.
19529 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
19530 enforce these sanity checks. */
19533 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
19534 enum machine_mode mode, int strict)
19536 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
19537 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
19538 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
19539 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
19540 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
19541 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
19543 gcc_assert (!strict);
19547 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
19550 /* ??? This is a lie. We do have moves between mmx/general, and for
19551 mmx/sse2. But by saying we need secondary memory we discourage the
19552 register allocator from using the mmx registers unless needed. */
19553 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
19556 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
19558 /* SSE1 doesn't have any direct moves from other classes. */
19562 /* If the target says that inter-unit moves are more expensive
19563 than moving through memory, then don't generate them. */
19564 if (!TARGET_INTER_UNIT_MOVES)
19567 /* Between SSE and general, we have moves no larger than word size. */
19568 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
19575 /* Return true if the registers in CLASS cannot represent the change from
19576 modes FROM to TO. */
19579 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
19580 enum reg_class class)
19585 /* x87 registers can't do subreg at all, as all values are reformatted
19586 to extended precision. */
19587 if (MAYBE_FLOAT_CLASS_P (class))
19590 if (MAYBE_SSE_CLASS_P (class) || MAYBE_MMX_CLASS_P (class))
19592 /* Vector registers do not support QI or HImode loads. If we don't
19593 disallow a change to these modes, reload will assume it's ok to
19594 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
19595 the vec_dupv4hi pattern. */
19596 if (GET_MODE_SIZE (from) < 4)
19599 /* Vector registers do not support subreg with nonzero offsets, which
19600 are otherwise valid for integer registers. Since we can't see
19601 whether we have a nonzero offset from here, prohibit all
19602 nonparadoxical subregs changing size. */
19603 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
19610 /* Return the cost of moving data from a register in class CLASS1 to
19611 one in class CLASS2.
19613 It is not required that the cost always equal 2 when FROM is the same as TO;
19614 on some machines it is expensive to move between registers if they are not
19615 general registers. */
19618 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
19619 enum reg_class class2)
19621 /* In case we require secondary memory, compute cost of the store followed
19622 by load. In order to avoid bad register allocation choices, we need
19623 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
19625 if (ix86_secondary_memory_needed (class1, class2, mode, 0))
19629 cost += MAX (MEMORY_MOVE_COST (mode, class1, 0),
19630 MEMORY_MOVE_COST (mode, class1, 1));
19631 cost += MAX (MEMORY_MOVE_COST (mode, class2, 0),
19632 MEMORY_MOVE_COST (mode, class2, 1));
19634 /* In case of copying from general_purpose_register we may emit multiple
19635 stores followed by single load causing memory size mismatch stall.
19636 Count this as arbitrarily high cost of 20. */
19637 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
19640 /* In the case of FP/MMX moves, the registers actually overlap, and we
19641 have to switch modes in order to treat them differently. */
19642 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
19643 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
19649 /* Moves between SSE/MMX and integer unit are expensive. */
19650 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
19651 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
19652 return ix86_cost->mmxsse_to_integer;
19653 if (MAYBE_FLOAT_CLASS_P (class1))
19654 return ix86_cost->fp_move;
19655 if (MAYBE_SSE_CLASS_P (class1))
19656 return ix86_cost->sse_move;
19657 if (MAYBE_MMX_CLASS_P (class1))
19658 return ix86_cost->mmx_move;
19662 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
19665 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
19667 /* Flags and only flags can only hold CCmode values. */
19668 if (CC_REGNO_P (regno))
19669 return GET_MODE_CLASS (mode) == MODE_CC;
19670 if (GET_MODE_CLASS (mode) == MODE_CC
19671 || GET_MODE_CLASS (mode) == MODE_RANDOM
19672 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
19674 if (FP_REGNO_P (regno))
19675 return VALID_FP_MODE_P (mode);
19676 if (SSE_REGNO_P (regno))
19678 /* We implement the move patterns for all vector modes into and
19679 out of SSE registers, even when no operation instructions
19681 return (VALID_SSE_REG_MODE (mode)
19682 || VALID_SSE2_REG_MODE (mode)
19683 || VALID_MMX_REG_MODE (mode)
19684 || VALID_MMX_REG_MODE_3DNOW (mode));
19686 if (MMX_REGNO_P (regno))
19688 /* We implement the move patterns for 3DNOW modes even in MMX mode,
19689 so if the register is available at all, then we can move data of
19690 the given mode into or out of it. */
19691 return (VALID_MMX_REG_MODE (mode)
19692 || VALID_MMX_REG_MODE_3DNOW (mode));
19695 if (mode == QImode)
19697 /* Take care for QImode values - they can be in non-QI regs,
19698 but then they do cause partial register stalls. */
19699 if (regno < 4 || TARGET_64BIT)
19701 if (!TARGET_PARTIAL_REG_STALL)
19703 return reload_in_progress || reload_completed;
19705 /* We handle both integer and floats in the general purpose registers. */
19706 else if (VALID_INT_MODE_P (mode))
19708 else if (VALID_FP_MODE_P (mode))
19710 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
19711 on to use that value in smaller contexts, this can easily force a
19712 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
19713 supporting DImode, allow it. */
19714 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
19720 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
19721 tieable integer mode. */
19724 ix86_tieable_integer_mode_p (enum machine_mode mode)
19733 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
19736 return TARGET_64BIT;
19743 /* Return true if MODE1 is accessible in a register that can hold MODE2
19744 without copying. That is, all register classes that can hold MODE2
19745 can also hold MODE1. */
19748 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
19750 if (mode1 == mode2)
19753 if (ix86_tieable_integer_mode_p (mode1)
19754 && ix86_tieable_integer_mode_p (mode2))
19757 /* MODE2 being XFmode implies fp stack or general regs, which means we
19758 can tie any smaller floating point modes to it. Note that we do not
19759 tie this with TFmode. */
19760 if (mode2 == XFmode)
19761 return mode1 == SFmode || mode1 == DFmode;
19763 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
19764 that we can tie it with SFmode. */
19765 if (mode2 == DFmode)
19766 return mode1 == SFmode;
19768 /* If MODE2 is only appropriate for an SSE register, then tie with
19769 any other mode acceptable to SSE registers. */
19770 if (GET_MODE_SIZE (mode2) == 16
19771 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
19772 return (GET_MODE_SIZE (mode1) == 16
19773 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
19775 /* If MODE2 is appropriate for an MMX register, then tie
19776 with any other mode acceptable to MMX registers. */
19777 if (GET_MODE_SIZE (mode2) == 8
19778 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
19779 return (GET_MODE_SIZE (mode1) == 8
19780 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
19785 /* Return the cost of moving data of mode M between a
19786 register and memory. A value of 2 is the default; this cost is
19787 relative to those in `REGISTER_MOVE_COST'.
19789 If moving between registers and memory is more expensive than
19790 between two registers, you should define this macro to express the
19793 Model also increased moving costs of QImode registers in non
19797 ix86_memory_move_cost (enum machine_mode mode, enum reg_class class, int in)
19799 if (FLOAT_CLASS_P (class))
19816 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
19818 if (SSE_CLASS_P (class))
19821 switch (GET_MODE_SIZE (mode))
19835 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
19837 if (MMX_CLASS_P (class))
19840 switch (GET_MODE_SIZE (mode))
19851 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
19853 switch (GET_MODE_SIZE (mode))
19857 return (Q_CLASS_P (class) ? ix86_cost->int_load[0]
19858 : ix86_cost->movzbl_load);
19860 return (Q_CLASS_P (class) ? ix86_cost->int_store[0]
19861 : ix86_cost->int_store[0] + 4);
19864 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
19866 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
19867 if (mode == TFmode)
19869 return ((in ? ix86_cost->int_load[2] : ix86_cost->int_store[2])
19870 * (((int) GET_MODE_SIZE (mode)
19871 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
19875 /* Compute a (partial) cost for rtx X. Return true if the complete
19876 cost has been computed, and false if subexpressions should be
19877 scanned. In either case, *TOTAL contains the cost result. */
19880 ix86_rtx_costs (rtx x, int code, int outer_code, int *total)
19882 enum machine_mode mode = GET_MODE (x);
19890 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
19892 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
19894 else if (flag_pic && SYMBOLIC_CONST (x)
19896 || (!GET_CODE (x) != LABEL_REF
19897 && (GET_CODE (x) != SYMBOL_REF
19898 || !SYMBOL_REF_LOCAL_P (x)))))
19905 if (mode == VOIDmode)
19908 switch (standard_80387_constant_p (x))
19913 default: /* Other constants */
19918 /* Start with (MEM (SYMBOL_REF)), since that's where
19919 it'll probably end up. Add a penalty for size. */
19920 *total = (COSTS_N_INSNS (1)
19921 + (flag_pic != 0 && !TARGET_64BIT)
19922 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
19928 /* The zero extensions is often completely free on x86_64, so make
19929 it as cheap as possible. */
19930 if (TARGET_64BIT && mode == DImode
19931 && GET_MODE (XEXP (x, 0)) == SImode)
19933 else if (TARGET_ZERO_EXTEND_WITH_AND)
19934 *total = ix86_cost->add;
19936 *total = ix86_cost->movzx;
19940 *total = ix86_cost->movsx;
19944 if (CONST_INT_P (XEXP (x, 1))
19945 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
19947 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
19950 *total = ix86_cost->add;
19953 if ((value == 2 || value == 3)
19954 && ix86_cost->lea <= ix86_cost->shift_const)
19956 *total = ix86_cost->lea;
19966 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
19968 if (CONST_INT_P (XEXP (x, 1)))
19970 if (INTVAL (XEXP (x, 1)) > 32)
19971 *total = ix86_cost->shift_const + COSTS_N_INSNS (2);
19973 *total = ix86_cost->shift_const * 2;
19977 if (GET_CODE (XEXP (x, 1)) == AND)
19978 *total = ix86_cost->shift_var * 2;
19980 *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2);
19985 if (CONST_INT_P (XEXP (x, 1)))
19986 *total = ix86_cost->shift_const;
19988 *total = ix86_cost->shift_var;
19993 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
19995 /* ??? SSE scalar cost should be used here. */
19996 *total = ix86_cost->fmul;
19999 else if (X87_FLOAT_MODE_P (mode))
20001 *total = ix86_cost->fmul;
20004 else if (FLOAT_MODE_P (mode))
20006 /* ??? SSE vector cost should be used here. */
20007 *total = ix86_cost->fmul;
20012 rtx op0 = XEXP (x, 0);
20013 rtx op1 = XEXP (x, 1);
20015 if (CONST_INT_P (XEXP (x, 1)))
20017 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
20018 for (nbits = 0; value != 0; value &= value - 1)
20022 /* This is arbitrary. */
20025 /* Compute costs correctly for widening multiplication. */
20026 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op1) == ZERO_EXTEND)
20027 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
20028 == GET_MODE_SIZE (mode))
20030 int is_mulwiden = 0;
20031 enum machine_mode inner_mode = GET_MODE (op0);
20033 if (GET_CODE (op0) == GET_CODE (op1))
20034 is_mulwiden = 1, op1 = XEXP (op1, 0);
20035 else if (CONST_INT_P (op1))
20037 if (GET_CODE (op0) == SIGN_EXTEND)
20038 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
20041 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
20045 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
20048 *total = (ix86_cost->mult_init[MODE_INDEX (mode)]
20049 + nbits * ix86_cost->mult_bit
20050 + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code));
20059 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
20060 /* ??? SSE cost should be used here. */
20061 *total = ix86_cost->fdiv;
20062 else if (X87_FLOAT_MODE_P (mode))
20063 *total = ix86_cost->fdiv;
20064 else if (FLOAT_MODE_P (mode))
20065 /* ??? SSE vector cost should be used here. */
20066 *total = ix86_cost->fdiv;
20068 *total = ix86_cost->divide[MODE_INDEX (mode)];
20072 if (GET_MODE_CLASS (mode) == MODE_INT
20073 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
20075 if (GET_CODE (XEXP (x, 0)) == PLUS
20076 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
20077 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
20078 && CONSTANT_P (XEXP (x, 1)))
20080 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
20081 if (val == 2 || val == 4 || val == 8)
20083 *total = ix86_cost->lea;
20084 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
20085 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
20087 *total += rtx_cost (XEXP (x, 1), outer_code);
20091 else if (GET_CODE (XEXP (x, 0)) == MULT
20092 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
20094 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
20095 if (val == 2 || val == 4 || val == 8)
20097 *total = ix86_cost->lea;
20098 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
20099 *total += rtx_cost (XEXP (x, 1), outer_code);
20103 else if (GET_CODE (XEXP (x, 0)) == PLUS)
20105 *total = ix86_cost->lea;
20106 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code);
20107 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code);
20108 *total += rtx_cost (XEXP (x, 1), outer_code);
20115 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
20117 /* ??? SSE cost should be used here. */
20118 *total = ix86_cost->fadd;
20121 else if (X87_FLOAT_MODE_P (mode))
20123 *total = ix86_cost->fadd;
20126 else if (FLOAT_MODE_P (mode))
20128 /* ??? SSE vector cost should be used here. */
20129 *total = ix86_cost->fadd;
20137 if (!TARGET_64BIT && mode == DImode)
20139 *total = (ix86_cost->add * 2
20140 + (rtx_cost (XEXP (x, 0), outer_code)
20141 << (GET_MODE (XEXP (x, 0)) != DImode))
20142 + (rtx_cost (XEXP (x, 1), outer_code)
20143 << (GET_MODE (XEXP (x, 1)) != DImode)));
20149 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
20151 /* ??? SSE cost should be used here. */
20152 *total = ix86_cost->fchs;
20155 else if (X87_FLOAT_MODE_P (mode))
20157 *total = ix86_cost->fchs;
20160 else if (FLOAT_MODE_P (mode))
20162 /* ??? SSE vector cost should be used here. */
20163 *total = ix86_cost->fchs;
20169 if (!TARGET_64BIT && mode == DImode)
20170 *total = ix86_cost->add * 2;
20172 *total = ix86_cost->add;
20176 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
20177 && XEXP (XEXP (x, 0), 1) == const1_rtx
20178 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
20179 && XEXP (x, 1) == const0_rtx)
20181 /* This kind of construct is implemented using test[bwl].
20182 Treat it as if we had an AND. */
20183 *total = (ix86_cost->add
20184 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
20185 + rtx_cost (const1_rtx, outer_code));
20191 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
20196 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
20197 /* ??? SSE cost should be used here. */
20198 *total = ix86_cost->fabs;
20199 else if (X87_FLOAT_MODE_P (mode))
20200 *total = ix86_cost->fabs;
20201 else if (FLOAT_MODE_P (mode))
20202 /* ??? SSE vector cost should be used here. */
20203 *total = ix86_cost->fabs;
20207 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
20208 /* ??? SSE cost should be used here. */
20209 *total = ix86_cost->fsqrt;
20210 else if (X87_FLOAT_MODE_P (mode))
20211 *total = ix86_cost->fsqrt;
20212 else if (FLOAT_MODE_P (mode))
20213 /* ??? SSE vector cost should be used here. */
20214 *total = ix86_cost->fsqrt;
20218 if (XINT (x, 1) == UNSPEC_TP)
20229 static int current_machopic_label_num;
20231 /* Given a symbol name and its associated stub, write out the
20232 definition of the stub. */
20235 machopic_output_stub (FILE *file, const char *symb, const char *stub)
20237 unsigned int length;
20238 char *binder_name, *symbol_name, lazy_ptr_name[32];
20239 int label = ++current_machopic_label_num;
20241 /* For 64-bit we shouldn't get here. */
20242 gcc_assert (!TARGET_64BIT);
20244 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
20245 symb = (*targetm.strip_name_encoding) (symb);
20247 length = strlen (stub);
20248 binder_name = alloca (length + 32);
20249 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
20251 length = strlen (symb);
20252 symbol_name = alloca (length + 32);
20253 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
20255 sprintf (lazy_ptr_name, "L%d$lz", label);
20258 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
20260 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
20262 fprintf (file, "%s:\n", stub);
20263 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20267 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
20268 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
20269 fprintf (file, "\tjmp\t*%%edx\n");
20272 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
20274 fprintf (file, "%s:\n", binder_name);
20278 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
20279 fprintf (file, "\tpushl\t%%eax\n");
20282 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
20284 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
20286 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
20287 fprintf (file, "%s:\n", lazy_ptr_name);
20288 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20289 fprintf (file, "\t.long %s\n", binder_name);
20293 darwin_x86_file_end (void)
20295 darwin_file_end ();
20298 #endif /* TARGET_MACHO */
20300 /* Order the registers for register allocator. */
20303 x86_order_regs_for_local_alloc (void)
20308 /* First allocate the local general purpose registers. */
20309 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
20310 if (GENERAL_REGNO_P (i) && call_used_regs[i])
20311 reg_alloc_order [pos++] = i;
20313 /* Global general purpose registers. */
20314 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
20315 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
20316 reg_alloc_order [pos++] = i;
20318 /* x87 registers come first in case we are doing FP math
20320 if (!TARGET_SSE_MATH)
20321 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
20322 reg_alloc_order [pos++] = i;
20324 /* SSE registers. */
20325 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
20326 reg_alloc_order [pos++] = i;
20327 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
20328 reg_alloc_order [pos++] = i;
20330 /* x87 registers. */
20331 if (TARGET_SSE_MATH)
20332 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
20333 reg_alloc_order [pos++] = i;
20335 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
20336 reg_alloc_order [pos++] = i;
20338 /* Initialize the rest of array as we do not allocate some registers
20340 while (pos < FIRST_PSEUDO_REGISTER)
20341 reg_alloc_order [pos++] = 0;
20344 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
20345 struct attribute_spec.handler. */
20347 ix86_handle_struct_attribute (tree *node, tree name,
20348 tree args ATTRIBUTE_UNUSED,
20349 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
20352 if (DECL_P (*node))
20354 if (TREE_CODE (*node) == TYPE_DECL)
20355 type = &TREE_TYPE (*node);
20360 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
20361 || TREE_CODE (*type) == UNION_TYPE)))
20363 warning (OPT_Wattributes, "%qs attribute ignored",
20364 IDENTIFIER_POINTER (name));
20365 *no_add_attrs = true;
20368 else if ((is_attribute_p ("ms_struct", name)
20369 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
20370 || ((is_attribute_p ("gcc_struct", name)
20371 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
20373 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
20374 IDENTIFIER_POINTER (name));
20375 *no_add_attrs = true;
20382 ix86_ms_bitfield_layout_p (tree record_type)
20384 return (TARGET_MS_BITFIELD_LAYOUT &&
20385 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
20386 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
20389 /* Returns an expression indicating where the this parameter is
20390 located on entry to the FUNCTION. */
20393 x86_this_parameter (tree function)
20395 tree type = TREE_TYPE (function);
20396 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
20400 const int *parm_regs;
20402 if (TARGET_64BIT_MS_ABI)
20403 parm_regs = x86_64_ms_abi_int_parameter_registers;
20405 parm_regs = x86_64_int_parameter_registers;
20406 return gen_rtx_REG (DImode, parm_regs[aggr]);
20409 if (ix86_function_regparm (type, function) > 0
20410 && !type_has_variadic_args_p (type))
20413 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
20415 return gen_rtx_REG (SImode, regno);
20418 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
20421 /* Determine whether x86_output_mi_thunk can succeed. */
20424 x86_can_output_mi_thunk (tree thunk ATTRIBUTE_UNUSED,
20425 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
20426 HOST_WIDE_INT vcall_offset, tree function)
20428 /* 64-bit can handle anything. */
20432 /* For 32-bit, everything's fine if we have one free register. */
20433 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
20436 /* Need a free register for vcall_offset. */
20440 /* Need a free register for GOT references. */
20441 if (flag_pic && !(*targetm.binds_local_p) (function))
20444 /* Otherwise ok. */
20448 /* Output the assembler code for a thunk function. THUNK_DECL is the
20449 declaration for the thunk function itself, FUNCTION is the decl for
20450 the target function. DELTA is an immediate constant offset to be
20451 added to THIS. If VCALL_OFFSET is nonzero, the word at
20452 *(*this + vcall_offset) should be added to THIS. */
20455 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
20456 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
20457 HOST_WIDE_INT vcall_offset, tree function)
20460 rtx this = x86_this_parameter (function);
20463 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
20464 pull it in now and let DELTA benefit. */
20467 else if (vcall_offset)
20469 /* Put the this parameter into %eax. */
20471 xops[1] = this_reg = gen_rtx_REG (Pmode, 0);
20472 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
20475 this_reg = NULL_RTX;
20477 /* Adjust the this parameter by a fixed constant. */
20480 xops[0] = GEN_INT (delta);
20481 xops[1] = this_reg ? this_reg : this;
20484 if (!x86_64_general_operand (xops[0], DImode))
20486 tmp = gen_rtx_REG (DImode, R10_REG);
20488 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
20492 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
20495 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
20498 /* Adjust the this parameter by a value stored in the vtable. */
20502 tmp = gen_rtx_REG (DImode, R10_REG);
20505 int tmp_regno = 2 /* ECX */;
20506 if (lookup_attribute ("fastcall",
20507 TYPE_ATTRIBUTES (TREE_TYPE (function))))
20508 tmp_regno = 0 /* EAX */;
20509 tmp = gen_rtx_REG (SImode, tmp_regno);
20512 xops[0] = gen_rtx_MEM (Pmode, this_reg);
20515 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
20517 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
20519 /* Adjust the this parameter. */
20520 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
20521 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
20523 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
20524 xops[0] = GEN_INT (vcall_offset);
20526 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
20527 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
20529 xops[1] = this_reg;
20531 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
20533 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
20536 /* If necessary, drop THIS back to its stack slot. */
20537 if (this_reg && this_reg != this)
20539 xops[0] = this_reg;
20541 output_asm_insn ("mov{l}\t{%0, %1|%1, %0}", xops);
20544 xops[0] = XEXP (DECL_RTL (function), 0);
20547 if (!flag_pic || (*targetm.binds_local_p) (function))
20548 output_asm_insn ("jmp\t%P0", xops);
20549 /* All thunks should be in the same object as their target,
20550 and thus binds_local_p should be true. */
20551 else if (TARGET_64BIT_MS_ABI)
20552 gcc_unreachable ();
20555 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
20556 tmp = gen_rtx_CONST (Pmode, tmp);
20557 tmp = gen_rtx_MEM (QImode, tmp);
20559 output_asm_insn ("jmp\t%A0", xops);
20564 if (!flag_pic || (*targetm.binds_local_p) (function))
20565 output_asm_insn ("jmp\t%P0", xops);
20570 rtx sym_ref = XEXP (DECL_RTL (function), 0);
20571 tmp = (gen_rtx_SYMBOL_REF
20573 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
20574 tmp = gen_rtx_MEM (QImode, tmp);
20576 output_asm_insn ("jmp\t%0", xops);
20579 #endif /* TARGET_MACHO */
20581 tmp = gen_rtx_REG (SImode, 2 /* ECX */);
20582 output_set_got (tmp, NULL_RTX);
20585 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
20586 output_asm_insn ("jmp\t{*}%1", xops);
20592 x86_file_start (void)
20594 default_file_start ();
20596 darwin_file_start ();
20598 if (X86_FILE_START_VERSION_DIRECTIVE)
20599 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
20600 if (X86_FILE_START_FLTUSED)
20601 fputs ("\t.global\t__fltused\n", asm_out_file);
20602 if (ix86_asm_dialect == ASM_INTEL)
20603 fputs ("\t.intel_syntax\n", asm_out_file);
20607 x86_field_alignment (tree field, int computed)
20609 enum machine_mode mode;
20610 tree type = TREE_TYPE (field);
20612 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
20614 mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
20615 ? get_inner_array_type (type) : type);
20616 if (mode == DFmode || mode == DCmode
20617 || GET_MODE_CLASS (mode) == MODE_INT
20618 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
20619 return MIN (32, computed);
20623 /* Output assembler code to FILE to increment profiler label # LABELNO
20624 for profiling a function entry. */
20626 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
20630 #ifndef NO_PROFILE_COUNTERS
20631 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
20634 if (!TARGET_64BIT_MS_ABI && flag_pic)
20635 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
20637 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
20641 #ifndef NO_PROFILE_COUNTERS
20642 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
20643 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
20645 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
20649 #ifndef NO_PROFILE_COUNTERS
20650 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
20651 PROFILE_COUNT_REGISTER);
20653 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
20657 /* We don't have exact information about the insn sizes, but we may assume
20658 quite safely that we are informed about all 1 byte insns and memory
20659 address sizes. This is enough to eliminate unnecessary padding in
20663 min_insn_size (rtx insn)
20667 if (!INSN_P (insn) || !active_insn_p (insn))
20670 /* Discard alignments we've emit and jump instructions. */
20671 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
20672 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
20675 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
20676 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
20679 /* Important case - calls are always 5 bytes.
20680 It is common to have many calls in the row. */
20682 && symbolic_reference_mentioned_p (PATTERN (insn))
20683 && !SIBLING_CALL_P (insn))
20685 if (get_attr_length (insn) <= 1)
20688 /* For normal instructions we may rely on the sizes of addresses
20689 and the presence of symbol to require 4 bytes of encoding.
20690 This is not the case for jumps where references are PC relative. */
20691 if (!JUMP_P (insn))
20693 l = get_attr_length_address (insn);
20694 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
20703 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
20707 ix86_avoid_jump_misspredicts (void)
20709 rtx insn, start = get_insns ();
20710 int nbytes = 0, njumps = 0;
20713 /* Look for all minimal intervals of instructions containing 4 jumps.
20714 The intervals are bounded by START and INSN. NBYTES is the total
20715 size of instructions in the interval including INSN and not including
20716 START. When the NBYTES is smaller than 16 bytes, it is possible
20717 that the end of START and INSN ends up in the same 16byte page.
20719 The smallest offset in the page INSN can start is the case where START
20720 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
20721 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
20723 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
20726 nbytes += min_insn_size (insn);
20728 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
20729 INSN_UID (insn), min_insn_size (insn));
20731 && GET_CODE (PATTERN (insn)) != ADDR_VEC
20732 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
20740 start = NEXT_INSN (start);
20741 if ((JUMP_P (start)
20742 && GET_CODE (PATTERN (start)) != ADDR_VEC
20743 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
20745 njumps--, isjump = 1;
20748 nbytes -= min_insn_size (start);
20750 gcc_assert (njumps >= 0);
20752 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
20753 INSN_UID (start), INSN_UID (insn), nbytes);
20755 if (njumps == 3 && isjump && nbytes < 16)
20757 int padsize = 15 - nbytes + min_insn_size (insn);
20760 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
20761 INSN_UID (insn), padsize);
20762 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
20767 /* AMD Athlon works faster
20768 when RET is not destination of conditional jump or directly preceded
20769 by other jump instruction. We avoid the penalty by inserting NOP just
20770 before the RET instructions in such cases. */
20772 ix86_pad_returns (void)
20777 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
20779 basic_block bb = e->src;
20780 rtx ret = BB_END (bb);
20782 bool replace = false;
20784 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
20785 || !maybe_hot_bb_p (bb))
20787 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
20788 if (active_insn_p (prev) || LABEL_P (prev))
20790 if (prev && LABEL_P (prev))
20795 FOR_EACH_EDGE (e, ei, bb->preds)
20796 if (EDGE_FREQUENCY (e) && e->src->index >= 0
20797 && !(e->flags & EDGE_FALLTHRU))
20802 prev = prev_active_insn (ret);
20804 && ((JUMP_P (prev) && any_condjump_p (prev))
20807 /* Empty functions get branch mispredict even when the jump destination
20808 is not visible to us. */
20809 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
20814 emit_insn_before (gen_return_internal_long (), ret);
20820 /* Implement machine specific optimizations. We implement padding of returns
20821 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
20825 if (TARGET_PAD_RETURNS && optimize && !optimize_size)
20826 ix86_pad_returns ();
20827 if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
20828 ix86_avoid_jump_misspredicts ();
20831 /* Return nonzero when QImode register that must be represented via REX prefix
20834 x86_extended_QIreg_mentioned_p (rtx insn)
20837 extract_insn_cached (insn);
20838 for (i = 0; i < recog_data.n_operands; i++)
20839 if (REG_P (recog_data.operand[i])
20840 && REGNO (recog_data.operand[i]) >= 4)
20845 /* Return nonzero when P points to register encoded via REX prefix.
20846 Called via for_each_rtx. */
20848 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
20850 unsigned int regno;
20853 regno = REGNO (*p);
20854 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
20857 /* Return true when INSN mentions register that must be encoded using REX
20860 x86_extended_reg_mentioned_p (rtx insn)
20862 return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
20865 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
20866 optabs would emit if we didn't have TFmode patterns. */
20869 x86_emit_floatuns (rtx operands[2])
20871 rtx neglab, donelab, i0, i1, f0, in, out;
20872 enum machine_mode mode, inmode;
20874 inmode = GET_MODE (operands[1]);
20875 gcc_assert (inmode == SImode || inmode == DImode);
20878 in = force_reg (inmode, operands[1]);
20879 mode = GET_MODE (out);
20880 neglab = gen_label_rtx ();
20881 donelab = gen_label_rtx ();
20882 f0 = gen_reg_rtx (mode);
20884 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
20886 expand_float (out, in, 0);
20888 emit_jump_insn (gen_jump (donelab));
20891 emit_label (neglab);
20893 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
20895 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
20897 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
20899 expand_float (f0, i0, 0);
20901 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
20903 emit_label (donelab);
20906 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
20907 with all elements equal to VAR. Return true if successful. */
20910 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
20911 rtx target, rtx val)
20913 enum machine_mode smode, wsmode, wvmode;
20928 val = force_reg (GET_MODE_INNER (mode), val);
20929 x = gen_rtx_VEC_DUPLICATE (mode, val);
20930 emit_insn (gen_rtx_SET (VOIDmode, target, x));
20936 if (TARGET_SSE || TARGET_3DNOW_A)
20938 val = gen_lowpart (SImode, val);
20939 x = gen_rtx_TRUNCATE (HImode, val);
20940 x = gen_rtx_VEC_DUPLICATE (mode, x);
20941 emit_insn (gen_rtx_SET (VOIDmode, target, x));
20963 /* Extend HImode to SImode using a paradoxical SUBREG. */
20964 tmp1 = gen_reg_rtx (SImode);
20965 emit_move_insn (tmp1, gen_lowpart (SImode, val));
20966 /* Insert the SImode value as low element of V4SImode vector. */
20967 tmp2 = gen_reg_rtx (V4SImode);
20968 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
20969 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
20970 CONST0_RTX (V4SImode),
20972 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
20973 /* Cast the V4SImode vector back to a V8HImode vector. */
20974 tmp1 = gen_reg_rtx (V8HImode);
20975 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
20976 /* Duplicate the low short through the whole low SImode word. */
20977 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
20978 /* Cast the V8HImode vector back to a V4SImode vector. */
20979 tmp2 = gen_reg_rtx (V4SImode);
20980 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
20981 /* Replicate the low element of the V4SImode vector. */
20982 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
20983 /* Cast the V2SImode back to V8HImode, and store in target. */
20984 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
20995 /* Extend QImode to SImode using a paradoxical SUBREG. */
20996 tmp1 = gen_reg_rtx (SImode);
20997 emit_move_insn (tmp1, gen_lowpart (SImode, val));
20998 /* Insert the SImode value as low element of V4SImode vector. */
20999 tmp2 = gen_reg_rtx (V4SImode);
21000 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
21001 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
21002 CONST0_RTX (V4SImode),
21004 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
21005 /* Cast the V4SImode vector back to a V16QImode vector. */
21006 tmp1 = gen_reg_rtx (V16QImode);
21007 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
21008 /* Duplicate the low byte through the whole low SImode word. */
21009 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
21010 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
21011 /* Cast the V16QImode vector back to a V4SImode vector. */
21012 tmp2 = gen_reg_rtx (V4SImode);
21013 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
21014 /* Replicate the low element of the V4SImode vector. */
21015 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
21016 /* Cast the V2SImode back to V16QImode, and store in target. */
21017 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
21025 /* Replicate the value once into the next wider mode and recurse. */
21026 val = convert_modes (wsmode, smode, val, true);
21027 x = expand_simple_binop (wsmode, ASHIFT, val,
21028 GEN_INT (GET_MODE_BITSIZE (smode)),
21029 NULL_RTX, 1, OPTAB_LIB_WIDEN);
21030 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
21032 x = gen_reg_rtx (wvmode);
21033 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
21034 gcc_unreachable ();
21035 emit_move_insn (target, gen_lowpart (mode, x));
21043 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
21044 whose ONE_VAR element is VAR, and other elements are zero. Return true
21048 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
21049 rtx target, rtx var, int one_var)
21051 enum machine_mode vsimode;
21067 var = force_reg (GET_MODE_INNER (mode), var);
21068 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
21069 emit_insn (gen_rtx_SET (VOIDmode, target, x));
21074 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
21075 new_target = gen_reg_rtx (mode);
21077 new_target = target;
21078 var = force_reg (GET_MODE_INNER (mode), var);
21079 x = gen_rtx_VEC_DUPLICATE (mode, var);
21080 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
21081 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
21084 /* We need to shuffle the value to the correct position, so
21085 create a new pseudo to store the intermediate result. */
21087 /* With SSE2, we can use the integer shuffle insns. */
21088 if (mode != V4SFmode && TARGET_SSE2)
21090 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
21092 GEN_INT (one_var == 1 ? 0 : 1),
21093 GEN_INT (one_var == 2 ? 0 : 1),
21094 GEN_INT (one_var == 3 ? 0 : 1)));
21095 if (target != new_target)
21096 emit_move_insn (target, new_target);
21100 /* Otherwise convert the intermediate result to V4SFmode and
21101 use the SSE1 shuffle instructions. */
21102 if (mode != V4SFmode)
21104 tmp = gen_reg_rtx (V4SFmode);
21105 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
21110 emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp,
21112 GEN_INT (one_var == 1 ? 0 : 1),
21113 GEN_INT (one_var == 2 ? 0+4 : 1+4),
21114 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
21116 if (mode != V4SFmode)
21117 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
21118 else if (tmp != target)
21119 emit_move_insn (target, tmp);
21121 else if (target != new_target)
21122 emit_move_insn (target, new_target);
21127 vsimode = V4SImode;
21133 vsimode = V2SImode;
21139 /* Zero extend the variable element to SImode and recurse. */
21140 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
21142 x = gen_reg_rtx (vsimode);
21143 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
21145 gcc_unreachable ();
21147 emit_move_insn (target, gen_lowpart (mode, x));
21155 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
21156 consisting of the values in VALS. It is known that all elements
21157 except ONE_VAR are constants. Return true if successful. */
21160 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
21161 rtx target, rtx vals, int one_var)
21163 rtx var = XVECEXP (vals, 0, one_var);
21164 enum machine_mode wmode;
21167 const_vec = copy_rtx (vals);
21168 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
21169 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
21177 /* For the two element vectors, it's just as easy to use
21178 the general case. */
21194 /* There's no way to set one QImode entry easily. Combine
21195 the variable value with its adjacent constant value, and
21196 promote to an HImode set. */
21197 x = XVECEXP (vals, 0, one_var ^ 1);
21200 var = convert_modes (HImode, QImode, var, true);
21201 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
21202 NULL_RTX, 1, OPTAB_LIB_WIDEN);
21203 x = GEN_INT (INTVAL (x) & 0xff);
21207 var = convert_modes (HImode, QImode, var, true);
21208 x = gen_int_mode (INTVAL (x) << 8, HImode);
21210 if (x != const0_rtx)
21211 var = expand_simple_binop (HImode, IOR, var, x, var,
21212 1, OPTAB_LIB_WIDEN);
21214 x = gen_reg_rtx (wmode);
21215 emit_move_insn (x, gen_lowpart (wmode, const_vec));
21216 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
21218 emit_move_insn (target, gen_lowpart (mode, x));
21225 emit_move_insn (target, const_vec);
21226 ix86_expand_vector_set (mmx_ok, target, var, one_var);
21230 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
21231 all values variable, and none identical. */
21234 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
21235 rtx target, rtx vals)
21237 enum machine_mode half_mode = GET_MODE_INNER (mode);
21238 rtx op0 = NULL, op1 = NULL;
21239 bool use_vec_concat = false;
21245 if (!mmx_ok && !TARGET_SSE)
21251 /* For the two element vectors, we always implement VEC_CONCAT. */
21252 op0 = XVECEXP (vals, 0, 0);
21253 op1 = XVECEXP (vals, 0, 1);
21254 use_vec_concat = true;
21258 half_mode = V2SFmode;
21261 half_mode = V2SImode;
21267 /* For V4SF and V4SI, we implement a concat of two V2 vectors.
21268 Recurse to load the two halves. */
21270 op0 = gen_reg_rtx (half_mode);
21271 v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1));
21272 ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v));
21274 op1 = gen_reg_rtx (half_mode);
21275 v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3));
21276 ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v));
21278 use_vec_concat = true;
21289 gcc_unreachable ();
21292 if (use_vec_concat)
21294 if (!register_operand (op0, half_mode))
21295 op0 = force_reg (half_mode, op0);
21296 if (!register_operand (op1, half_mode))
21297 op1 = force_reg (half_mode, op1);
21299 emit_insn (gen_rtx_SET (VOIDmode, target,
21300 gen_rtx_VEC_CONCAT (mode, op0, op1)));
21304 int i, j, n_elts, n_words, n_elt_per_word;
21305 enum machine_mode inner_mode;
21306 rtx words[4], shift;
21308 inner_mode = GET_MODE_INNER (mode);
21309 n_elts = GET_MODE_NUNITS (mode);
21310 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
21311 n_elt_per_word = n_elts / n_words;
21312 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
21314 for (i = 0; i < n_words; ++i)
21316 rtx word = NULL_RTX;
21318 for (j = 0; j < n_elt_per_word; ++j)
21320 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
21321 elt = convert_modes (word_mode, inner_mode, elt, true);
21327 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
21328 word, 1, OPTAB_LIB_WIDEN);
21329 word = expand_simple_binop (word_mode, IOR, word, elt,
21330 word, 1, OPTAB_LIB_WIDEN);
21338 emit_move_insn (target, gen_lowpart (mode, words[0]));
21339 else if (n_words == 2)
21341 rtx tmp = gen_reg_rtx (mode);
21342 emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp));
21343 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
21344 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
21345 emit_move_insn (target, tmp);
21347 else if (n_words == 4)
21349 rtx tmp = gen_reg_rtx (V4SImode);
21350 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
21351 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
21352 emit_move_insn (target, gen_lowpart (mode, tmp));
21355 gcc_unreachable ();
21359 /* Initialize vector TARGET via VALS. Suppress the use of MMX
21360 instructions unless MMX_OK is true. */
21363 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
21365 enum machine_mode mode = GET_MODE (target);
21366 enum machine_mode inner_mode = GET_MODE_INNER (mode);
21367 int n_elts = GET_MODE_NUNITS (mode);
21368 int n_var = 0, one_var = -1;
21369 bool all_same = true, all_const_zero = true;
21373 for (i = 0; i < n_elts; ++i)
21375 x = XVECEXP (vals, 0, i);
21376 if (!CONSTANT_P (x))
21377 n_var++, one_var = i;
21378 else if (x != CONST0_RTX (inner_mode))
21379 all_const_zero = false;
21380 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
21384 /* Constants are best loaded from the constant pool. */
21387 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
21391 /* If all values are identical, broadcast the value. */
21393 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
21394 XVECEXP (vals, 0, 0)))
21397 /* Values where only one field is non-constant are best loaded from
21398 the pool and overwritten via move later. */
21402 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
21403 XVECEXP (vals, 0, one_var),
21407 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
21411 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
21415 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
21417 enum machine_mode mode = GET_MODE (target);
21418 enum machine_mode inner_mode = GET_MODE_INNER (mode);
21419 bool use_vec_merge = false;
21428 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
21429 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
21431 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
21433 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
21434 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
21440 use_vec_merge = TARGET_SSE4_1;
21448 /* For the two element vectors, we implement a VEC_CONCAT with
21449 the extraction of the other element. */
21451 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
21452 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
21455 op0 = val, op1 = tmp;
21457 op0 = tmp, op1 = val;
21459 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
21460 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
21465 use_vec_merge = TARGET_SSE4_1;
21472 use_vec_merge = true;
21476 /* tmp = target = A B C D */
21477 tmp = copy_to_reg (target);
21478 /* target = A A B B */
21479 emit_insn (gen_sse_unpcklps (target, target, target));
21480 /* target = X A B B */
21481 ix86_expand_vector_set (false, target, val, 0);
21482 /* target = A X C D */
21483 emit_insn (gen_sse_shufps_1 (target, target, tmp,
21484 GEN_INT (1), GEN_INT (0),
21485 GEN_INT (2+4), GEN_INT (3+4)));
21489 /* tmp = target = A B C D */
21490 tmp = copy_to_reg (target);
21491 /* tmp = X B C D */
21492 ix86_expand_vector_set (false, tmp, val, 0);
21493 /* target = A B X D */
21494 emit_insn (gen_sse_shufps_1 (target, target, tmp,
21495 GEN_INT (0), GEN_INT (1),
21496 GEN_INT (0+4), GEN_INT (3+4)));
21500 /* tmp = target = A B C D */
21501 tmp = copy_to_reg (target);
21502 /* tmp = X B C D */
21503 ix86_expand_vector_set (false, tmp, val, 0);
21504 /* target = A B X D */
21505 emit_insn (gen_sse_shufps_1 (target, target, tmp,
21506 GEN_INT (0), GEN_INT (1),
21507 GEN_INT (2+4), GEN_INT (0+4)));
21511 gcc_unreachable ();
21516 use_vec_merge = TARGET_SSE4_1;
21520 /* Element 0 handled by vec_merge below. */
21523 use_vec_merge = true;
21529 /* With SSE2, use integer shuffles to swap element 0 and ELT,
21530 store into element 0, then shuffle them back. */
21534 order[0] = GEN_INT (elt);
21535 order[1] = const1_rtx;
21536 order[2] = const2_rtx;
21537 order[3] = GEN_INT (3);
21538 order[elt] = const0_rtx;
21540 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
21541 order[1], order[2], order[3]));
21543 ix86_expand_vector_set (false, target, val, 0);
21545 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
21546 order[1], order[2], order[3]));
21550 /* For SSE1, we have to reuse the V4SF code. */
21551 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
21552 gen_lowpart (SFmode, val), elt);
21557 use_vec_merge = TARGET_SSE2;
21560 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
21564 use_vec_merge = TARGET_SSE4_1;
21574 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
21575 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
21576 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
21580 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
21582 emit_move_insn (mem, target);
21584 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
21585 emit_move_insn (tmp, val);
21587 emit_move_insn (target, mem);
21592 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
21594 enum machine_mode mode = GET_MODE (vec);
21595 enum machine_mode inner_mode = GET_MODE_INNER (mode);
21596 bool use_vec_extr = false;
21609 use_vec_extr = true;
21613 use_vec_extr = TARGET_SSE4_1;
21625 tmp = gen_reg_rtx (mode);
21626 emit_insn (gen_sse_shufps_1 (tmp, vec, vec,
21627 GEN_INT (elt), GEN_INT (elt),
21628 GEN_INT (elt+4), GEN_INT (elt+4)));
21632 tmp = gen_reg_rtx (mode);
21633 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
21637 gcc_unreachable ();
21640 use_vec_extr = true;
21645 use_vec_extr = TARGET_SSE4_1;
21659 tmp = gen_reg_rtx (mode);
21660 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
21661 GEN_INT (elt), GEN_INT (elt),
21662 GEN_INT (elt), GEN_INT (elt)));
21666 tmp = gen_reg_rtx (mode);
21667 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
21671 gcc_unreachable ();
21674 use_vec_extr = true;
21679 /* For SSE1, we have to reuse the V4SF code. */
21680 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
21681 gen_lowpart (V4SFmode, vec), elt);
21687 use_vec_extr = TARGET_SSE2;
21690 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
21694 use_vec_extr = TARGET_SSE4_1;
21698 /* ??? Could extract the appropriate HImode element and shift. */
21705 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
21706 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
21708 /* Let the rtl optimizers know about the zero extension performed. */
21709 if (inner_mode == QImode || inner_mode == HImode)
21711 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
21712 target = gen_lowpart (SImode, target);
21715 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
21719 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
21721 emit_move_insn (mem, vec);
21723 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
21724 emit_move_insn (target, tmp);
21728 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
21729 pattern to reduce; DEST is the destination; IN is the input vector. */
21732 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
21734 rtx tmp1, tmp2, tmp3;
21736 tmp1 = gen_reg_rtx (V4SFmode);
21737 tmp2 = gen_reg_rtx (V4SFmode);
21738 tmp3 = gen_reg_rtx (V4SFmode);
21740 emit_insn (gen_sse_movhlps (tmp1, in, in));
21741 emit_insn (fn (tmp2, tmp1, in));
21743 emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2,
21744 GEN_INT (1), GEN_INT (1),
21745 GEN_INT (1+4), GEN_INT (1+4)));
21746 emit_insn (fn (dest, tmp2, tmp3));
21749 /* Target hook for scalar_mode_supported_p. */
21751 ix86_scalar_mode_supported_p (enum machine_mode mode)
21753 if (DECIMAL_FLOAT_MODE_P (mode))
21755 else if (mode == TFmode)
21756 return TARGET_64BIT;
21758 return default_scalar_mode_supported_p (mode);
21761 /* Implements target hook vector_mode_supported_p. */
21763 ix86_vector_mode_supported_p (enum machine_mode mode)
21765 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
21767 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
21769 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
21771 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
21776 /* Worker function for TARGET_MD_ASM_CLOBBERS.
21778 We do this in the new i386 backend to maintain source compatibility
21779 with the old cc0-based compiler. */
21782 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
21783 tree inputs ATTRIBUTE_UNUSED,
21786 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
21788 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
21793 /* Implements target vector targetm.asm.encode_section_info. This
21794 is not used by netware. */
21796 static void ATTRIBUTE_UNUSED
21797 ix86_encode_section_info (tree decl, rtx rtl, int first)
21799 default_encode_section_info (decl, rtl, first);
21801 if (TREE_CODE (decl) == VAR_DECL
21802 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
21803 && ix86_in_large_data_p (decl))
21804 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
21807 /* Worker function for REVERSE_CONDITION. */
21810 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
21812 return (mode != CCFPmode && mode != CCFPUmode
21813 ? reverse_condition (code)
21814 : reverse_condition_maybe_unordered (code));
21817 /* Output code to perform an x87 FP register move, from OPERANDS[1]
21821 output_387_reg_move (rtx insn, rtx *operands)
21823 if (REG_P (operands[0]))
21825 if (REG_P (operands[1])
21826 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
21828 if (REGNO (operands[0]) == FIRST_STACK_REG)
21829 return output_387_ffreep (operands, 0);
21830 return "fstp\t%y0";
21832 if (STACK_TOP_P (operands[0]))
21833 return "fld%z1\t%y1";
21836 else if (MEM_P (operands[0]))
21838 gcc_assert (REG_P (operands[1]));
21839 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
21840 return "fstp%z0\t%y0";
21843 /* There is no non-popping store to memory for XFmode.
21844 So if we need one, follow the store with a load. */
21845 if (GET_MODE (operands[0]) == XFmode)
21846 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
21848 return "fst%z0\t%y0";
21855 /* Output code to perform a conditional jump to LABEL, if C2 flag in
21856 FP status register is set. */
21859 ix86_emit_fp_unordered_jump (rtx label)
21861 rtx reg = gen_reg_rtx (HImode);
21864 emit_insn (gen_x86_fnstsw_1 (reg));
21866 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_size))
21868 emit_insn (gen_x86_sahf_1 (reg));
21870 temp = gen_rtx_REG (CCmode, FLAGS_REG);
21871 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
21875 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
21877 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
21878 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
21881 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
21882 gen_rtx_LABEL_REF (VOIDmode, label),
21884 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
21886 emit_jump_insn (temp);
21887 predict_jump (REG_BR_PROB_BASE * 10 / 100);
21890 /* Output code to perform a log1p XFmode calculation. */
21892 void ix86_emit_i387_log1p (rtx op0, rtx op1)
21894 rtx label1 = gen_label_rtx ();
21895 rtx label2 = gen_label_rtx ();
21897 rtx tmp = gen_reg_rtx (XFmode);
21898 rtx tmp2 = gen_reg_rtx (XFmode);
21900 emit_insn (gen_absxf2 (tmp, op1));
21901 emit_insn (gen_cmpxf (tmp,
21902 CONST_DOUBLE_FROM_REAL_VALUE (
21903 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
21905 emit_jump_insn (gen_bge (label1));
21907 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
21908 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
21909 emit_jump (label2);
21911 emit_label (label1);
21912 emit_move_insn (tmp, CONST1_RTX (XFmode));
21913 emit_insn (gen_addxf3 (tmp, op1, tmp));
21914 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
21915 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
21917 emit_label (label2);
21920 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
21922 static void ATTRIBUTE_UNUSED
21923 i386_solaris_elf_named_section (const char *name, unsigned int flags,
21926 /* With Binutils 2.15, the "@unwind" marker must be specified on
21927 every occurrence of the ".eh_frame" section, not just the first
21930 && strcmp (name, ".eh_frame") == 0)
21932 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
21933 flags & SECTION_WRITE ? "aw" : "a");
21936 default_elf_asm_named_section (name, flags, decl);
21939 /* Return the mangling of TYPE if it is an extended fundamental type. */
21941 static const char *
21942 ix86_mangle_fundamental_type (tree type)
21944 switch (TYPE_MODE (type))
21947 /* __float128 is "g". */
21950 /* "long double" or __float80 is "e". */
21957 /* For 32-bit code we can save PIC register setup by using
21958 __stack_chk_fail_local hidden function instead of calling
21959 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
21960 register, so it is better to call __stack_chk_fail directly. */
21963 ix86_stack_protect_fail (void)
21965 return TARGET_64BIT
21966 ? default_external_stack_protect_fail ()
21967 : default_hidden_stack_protect_fail ();
21970 /* Select a format to encode pointers in exception handling data. CODE
21971 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
21972 true if the symbol may be affected by dynamic relocations.
21974 ??? All x86 object file formats are capable of representing this.
21975 After all, the relocation needed is the same as for the call insn.
21976 Whether or not a particular assembler allows us to enter such, I
21977 guess we'll have to see. */
21979 asm_preferred_eh_data_format (int code, int global)
21983 int type = DW_EH_PE_sdata8;
21985 || ix86_cmodel == CM_SMALL_PIC
21986 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
21987 type = DW_EH_PE_sdata4;
21988 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
21990 if (ix86_cmodel == CM_SMALL
21991 || (ix86_cmodel == CM_MEDIUM && code))
21992 return DW_EH_PE_udata4;
21993 return DW_EH_PE_absptr;
21996 /* Expand copysign from SIGN to the positive value ABS_VALUE
21997 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
22000 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
22002 enum machine_mode mode = GET_MODE (sign);
22003 rtx sgn = gen_reg_rtx (mode);
22004 if (mask == NULL_RTX)
22006 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
22007 if (!VECTOR_MODE_P (mode))
22009 /* We need to generate a scalar mode mask in this case. */
22010 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
22011 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
22012 mask = gen_reg_rtx (mode);
22013 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
22017 mask = gen_rtx_NOT (mode, mask);
22018 emit_insn (gen_rtx_SET (VOIDmode, sgn,
22019 gen_rtx_AND (mode, mask, sign)));
22020 emit_insn (gen_rtx_SET (VOIDmode, result,
22021 gen_rtx_IOR (mode, abs_value, sgn)));
22024 /* Expand fabs (OP0) and return a new rtx that holds the result. The
22025 mask for masking out the sign-bit is stored in *SMASK, if that is
22028 ix86_expand_sse_fabs (rtx op0, rtx *smask)
22030 enum machine_mode mode = GET_MODE (op0);
22033 xa = gen_reg_rtx (mode);
22034 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
22035 if (!VECTOR_MODE_P (mode))
22037 /* We need to generate a scalar mode mask in this case. */
22038 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
22039 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
22040 mask = gen_reg_rtx (mode);
22041 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
22043 emit_insn (gen_rtx_SET (VOIDmode, xa,
22044 gen_rtx_AND (mode, op0, mask)));
22052 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
22053 swapping the operands if SWAP_OPERANDS is true. The expanded
22054 code is a forward jump to a newly created label in case the
22055 comparison is true. The generated label rtx is returned. */
22057 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
22058 bool swap_operands)
22069 label = gen_label_rtx ();
22070 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
22071 emit_insn (gen_rtx_SET (VOIDmode, tmp,
22072 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
22073 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
22074 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
22075 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
22076 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
22077 JUMP_LABEL (tmp) = label;
22082 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
22083 using comparison code CODE. Operands are swapped for the comparison if
22084 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
22086 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
22087 bool swap_operands)
22089 enum machine_mode mode = GET_MODE (op0);
22090 rtx mask = gen_reg_rtx (mode);
22099 if (mode == DFmode)
22100 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
22101 gen_rtx_fmt_ee (code, mode, op0, op1)));
22103 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
22104 gen_rtx_fmt_ee (code, mode, op0, op1)));
22109 /* Generate and return a rtx of mode MODE for 2**n where n is the number
22110 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
22112 ix86_gen_TWO52 (enum machine_mode mode)
22114 REAL_VALUE_TYPE TWO52r;
22117 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
22118 TWO52 = const_double_from_real_value (TWO52r, mode);
22119 TWO52 = force_reg (mode, TWO52);
22124 /* Expand SSE sequence for computing lround from OP1 storing
22127 ix86_expand_lround (rtx op0, rtx op1)
22129 /* C code for the stuff we're doing below:
22130 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
22133 enum machine_mode mode = GET_MODE (op1);
22134 const struct real_format *fmt;
22135 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
22138 /* load nextafter (0.5, 0.0) */
22139 fmt = REAL_MODE_FORMAT (mode);
22140 real_2expN (&half_minus_pred_half, -(fmt->p) - 1);
22141 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
22143 /* adj = copysign (0.5, op1) */
22144 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
22145 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
22147 /* adj = op1 + adj */
22148 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
22150 /* op0 = (imode)adj */
22151 expand_fix (op0, adj, 0);
22154 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
22157 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
22159 /* C code for the stuff we're doing below (for do_floor):
22161 xi -= (double)xi > op1 ? 1 : 0;
22164 enum machine_mode fmode = GET_MODE (op1);
22165 enum machine_mode imode = GET_MODE (op0);
22166 rtx ireg, freg, label, tmp;
22168 /* reg = (long)op1 */
22169 ireg = gen_reg_rtx (imode);
22170 expand_fix (ireg, op1, 0);
22172 /* freg = (double)reg */
22173 freg = gen_reg_rtx (fmode);
22174 expand_float (freg, ireg, 0);
22176 /* ireg = (freg > op1) ? ireg - 1 : ireg */
22177 label = ix86_expand_sse_compare_and_jump (UNLE,
22178 freg, op1, !do_floor);
22179 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
22180 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
22181 emit_move_insn (ireg, tmp);
22183 emit_label (label);
22184 LABEL_NUSES (label) = 1;
22186 emit_move_insn (op0, ireg);
22189 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
22190 result in OPERAND0. */
22192 ix86_expand_rint (rtx operand0, rtx operand1)
22194 /* C code for the stuff we're doing below:
22195 xa = fabs (operand1);
22196 if (!isless (xa, 2**52))
22198 xa = xa + 2**52 - 2**52;
22199 return copysign (xa, operand1);
22201 enum machine_mode mode = GET_MODE (operand0);
22202 rtx res, xa, label, TWO52, mask;
22204 res = gen_reg_rtx (mode);
22205 emit_move_insn (res, operand1);
22207 /* xa = abs (operand1) */
22208 xa = ix86_expand_sse_fabs (res, &mask);
22210 /* if (!isless (xa, TWO52)) goto label; */
22211 TWO52 = ix86_gen_TWO52 (mode);
22212 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
22214 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
22215 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
22217 ix86_sse_copysign_to_positive (res, xa, res, mask);
22219 emit_label (label);
22220 LABEL_NUSES (label) = 1;
22222 emit_move_insn (operand0, res);
22225 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
22228 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
22230 /* C code for the stuff we expand below.
22231 double xa = fabs (x), x2;
22232 if (!isless (xa, TWO52))
22234 xa = xa + TWO52 - TWO52;
22235 x2 = copysign (xa, x);
22244 enum machine_mode mode = GET_MODE (operand0);
22245 rtx xa, TWO52, tmp, label, one, res, mask;
22247 TWO52 = ix86_gen_TWO52 (mode);
22249 /* Temporary for holding the result, initialized to the input
22250 operand to ease control flow. */
22251 res = gen_reg_rtx (mode);
22252 emit_move_insn (res, operand1);
22254 /* xa = abs (operand1) */
22255 xa = ix86_expand_sse_fabs (res, &mask);
22257 /* if (!isless (xa, TWO52)) goto label; */
22258 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
22260 /* xa = xa + TWO52 - TWO52; */
22261 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
22262 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
22264 /* xa = copysign (xa, operand1) */
22265 ix86_sse_copysign_to_positive (xa, xa, res, mask);
22267 /* generate 1.0 or -1.0 */
22268 one = force_reg (mode,
22269 const_double_from_real_value (do_floor
22270 ? dconst1 : dconstm1, mode));
22272 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
22273 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
22274 emit_insn (gen_rtx_SET (VOIDmode, tmp,
22275 gen_rtx_AND (mode, one, tmp)));
22276 /* We always need to subtract here to preserve signed zero. */
22277 tmp = expand_simple_binop (mode, MINUS,
22278 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
22279 emit_move_insn (res, tmp);
22281 emit_label (label);
22282 LABEL_NUSES (label) = 1;
22284 emit_move_insn (operand0, res);
22287 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
22290 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
22292 /* C code for the stuff we expand below.
22293 double xa = fabs (x), x2;
22294 if (!isless (xa, TWO52))
22296 x2 = (double)(long)x;
22303 if (HONOR_SIGNED_ZEROS (mode))
22304 return copysign (x2, x);
22307 enum machine_mode mode = GET_MODE (operand0);
22308 rtx xa, xi, TWO52, tmp, label, one, res, mask;
22310 TWO52 = ix86_gen_TWO52 (mode);
22312 /* Temporary for holding the result, initialized to the input
22313 operand to ease control flow. */
22314 res = gen_reg_rtx (mode);
22315 emit_move_insn (res, operand1);
22317 /* xa = abs (operand1) */
22318 xa = ix86_expand_sse_fabs (res, &mask);
22320 /* if (!isless (xa, TWO52)) goto label; */
22321 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
22323 /* xa = (double)(long)x */
22324 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
22325 expand_fix (xi, res, 0);
22326 expand_float (xa, xi, 0);
22329 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
22331 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
22332 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
22333 emit_insn (gen_rtx_SET (VOIDmode, tmp,
22334 gen_rtx_AND (mode, one, tmp)));
22335 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
22336 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
22337 emit_move_insn (res, tmp);
22339 if (HONOR_SIGNED_ZEROS (mode))
22340 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
22342 emit_label (label);
22343 LABEL_NUSES (label) = 1;
22345 emit_move_insn (operand0, res);
22348 /* Expand SSE sequence for computing round from OPERAND1 storing
22349 into OPERAND0. Sequence that works without relying on DImode truncation
22350 via cvttsd2siq that is only available on 64bit targets. */
22352 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
22354 /* C code for the stuff we expand below.
22355 double xa = fabs (x), xa2, x2;
22356 if (!isless (xa, TWO52))
22358 Using the absolute value and copying back sign makes
22359 -0.0 -> -0.0 correct.
22360 xa2 = xa + TWO52 - TWO52;
22365 else if (dxa > 0.5)
22367 x2 = copysign (xa2, x);
22370 enum machine_mode mode = GET_MODE (operand0);
22371 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
22373 TWO52 = ix86_gen_TWO52 (mode);
22375 /* Temporary for holding the result, initialized to the input
22376 operand to ease control flow. */
22377 res = gen_reg_rtx (mode);
22378 emit_move_insn (res, operand1);
22380 /* xa = abs (operand1) */
22381 xa = ix86_expand_sse_fabs (res, &mask);
22383 /* if (!isless (xa, TWO52)) goto label; */
22384 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
22386 /* xa2 = xa + TWO52 - TWO52; */
22387 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
22388 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
22390 /* dxa = xa2 - xa; */
22391 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
22393 /* generate 0.5, 1.0 and -0.5 */
22394 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
22395 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
22396 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
22400 tmp = gen_reg_rtx (mode);
22401 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
22402 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
22403 emit_insn (gen_rtx_SET (VOIDmode, tmp,
22404 gen_rtx_AND (mode, one, tmp)));
22405 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
22406 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
22407 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
22408 emit_insn (gen_rtx_SET (VOIDmode, tmp,
22409 gen_rtx_AND (mode, one, tmp)));
22410 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
22412 /* res = copysign (xa2, operand1) */
22413 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
22415 emit_label (label);
22416 LABEL_NUSES (label) = 1;
22418 emit_move_insn (operand0, res);
22421 /* Expand SSE sequence for computing trunc from OPERAND1 storing
22424 ix86_expand_trunc (rtx operand0, rtx operand1)
22426 /* C code for SSE variant we expand below.
22427 double xa = fabs (x), x2;
22428 if (!isless (xa, TWO52))
22430 x2 = (double)(long)x;
22431 if (HONOR_SIGNED_ZEROS (mode))
22432 return copysign (x2, x);
22435 enum machine_mode mode = GET_MODE (operand0);
22436 rtx xa, xi, TWO52, label, res, mask;
22438 TWO52 = ix86_gen_TWO52 (mode);
22440 /* Temporary for holding the result, initialized to the input
22441 operand to ease control flow. */
22442 res = gen_reg_rtx (mode);
22443 emit_move_insn (res, operand1);
22445 /* xa = abs (operand1) */
22446 xa = ix86_expand_sse_fabs (res, &mask);
22448 /* if (!isless (xa, TWO52)) goto label; */
22449 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
22451 /* x = (double)(long)x */
22452 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
22453 expand_fix (xi, res, 0);
22454 expand_float (res, xi, 0);
22456 if (HONOR_SIGNED_ZEROS (mode))
22457 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
22459 emit_label (label);
22460 LABEL_NUSES (label) = 1;
22462 emit_move_insn (operand0, res);
22465 /* Expand SSE sequence for computing trunc from OPERAND1 storing
22468 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
22470 enum machine_mode mode = GET_MODE (operand0);
22471 rtx xa, mask, TWO52, label, one, res, smask, tmp;
22473 /* C code for SSE variant we expand below.
22474 double xa = fabs (x), x2;
22475 if (!isless (xa, TWO52))
22477 xa2 = xa + TWO52 - TWO52;
22481 x2 = copysign (xa2, x);
22485 TWO52 = ix86_gen_TWO52 (mode);
22487 /* Temporary for holding the result, initialized to the input
22488 operand to ease control flow. */
22489 res = gen_reg_rtx (mode);
22490 emit_move_insn (res, operand1);
22492 /* xa = abs (operand1) */
22493 xa = ix86_expand_sse_fabs (res, &smask);
22495 /* if (!isless (xa, TWO52)) goto label; */
22496 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
22498 /* res = xa + TWO52 - TWO52; */
22499 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
22500 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
22501 emit_move_insn (res, tmp);
22504 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
22506 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
22507 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
22508 emit_insn (gen_rtx_SET (VOIDmode, mask,
22509 gen_rtx_AND (mode, mask, one)));
22510 tmp = expand_simple_binop (mode, MINUS,
22511 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
22512 emit_move_insn (res, tmp);
22514 /* res = copysign (res, operand1) */
22515 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
22517 emit_label (label);
22518 LABEL_NUSES (label) = 1;
22520 emit_move_insn (operand0, res);
22523 /* Expand SSE sequence for computing round from OPERAND1 storing
22526 ix86_expand_round (rtx operand0, rtx operand1)
22528 /* C code for the stuff we're doing below:
22529 double xa = fabs (x);
22530 if (!isless (xa, TWO52))
22532 xa = (double)(long)(xa + nextafter (0.5, 0.0));
22533 return copysign (xa, x);
22535 enum machine_mode mode = GET_MODE (operand0);
22536 rtx res, TWO52, xa, label, xi, half, mask;
22537 const struct real_format *fmt;
22538 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
22540 /* Temporary for holding the result, initialized to the input
22541 operand to ease control flow. */
22542 res = gen_reg_rtx (mode);
22543 emit_move_insn (res, operand1);
22545 TWO52 = ix86_gen_TWO52 (mode);
22546 xa = ix86_expand_sse_fabs (res, &mask);
22547 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
22549 /* load nextafter (0.5, 0.0) */
22550 fmt = REAL_MODE_FORMAT (mode);
22551 real_2expN (&half_minus_pred_half, -(fmt->p) - 1);
22552 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
22554 /* xa = xa + 0.5 */
22555 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
22556 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
22558 /* xa = (double)(int64_t)xa */
22559 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
22560 expand_fix (xi, xa, 0);
22561 expand_float (xa, xi, 0);
22563 /* res = copysign (xa, operand1) */
22564 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
22566 emit_label (label);
22567 LABEL_NUSES (label) = 1;
22569 emit_move_insn (operand0, res);
22573 /* Table of valid machine attributes. */
22574 static const struct attribute_spec ix86_attribute_table[] =
22576 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
22577 /* Stdcall attribute says callee is responsible for popping arguments
22578 if they are not variable. */
22579 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
22580 /* Fastcall attribute says callee is responsible for popping arguments
22581 if they are not variable. */
22582 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
22583 /* Cdecl attribute says the callee is a normal C declaration */
22584 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
22585 /* Regparm attribute specifies how many integer arguments are to be
22586 passed in registers. */
22587 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
22588 /* Sseregparm attribute says we are using x86_64 calling conventions
22589 for FP arguments. */
22590 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
22591 /* force_align_arg_pointer says this function realigns the stack at entry. */
22592 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
22593 false, true, true, ix86_handle_cconv_attribute },
22594 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
22595 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
22596 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
22597 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
22599 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
22600 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
22601 #ifdef SUBTARGET_ATTRIBUTE_TABLE
22602 SUBTARGET_ATTRIBUTE_TABLE,
22604 { NULL, 0, 0, false, false, false, NULL }
22607 /* Initialize the GCC target structure. */
22608 #undef TARGET_ATTRIBUTE_TABLE
22609 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
22610 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
22611 # undef TARGET_MERGE_DECL_ATTRIBUTES
22612 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
22615 #undef TARGET_COMP_TYPE_ATTRIBUTES
22616 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
22618 #undef TARGET_INIT_BUILTINS
22619 #define TARGET_INIT_BUILTINS ix86_init_builtins
22620 #undef TARGET_EXPAND_BUILTIN
22621 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
22623 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
22624 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION ix86_builtin_vectorized_function
22625 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
22626 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_builtin_conversion
22628 #undef TARGET_ASM_FUNCTION_EPILOGUE
22629 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
22631 #undef TARGET_ENCODE_SECTION_INFO
22632 #ifndef SUBTARGET_ENCODE_SECTION_INFO
22633 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
22635 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
22638 #undef TARGET_ASM_OPEN_PAREN
22639 #define TARGET_ASM_OPEN_PAREN ""
22640 #undef TARGET_ASM_CLOSE_PAREN
22641 #define TARGET_ASM_CLOSE_PAREN ""
22643 #undef TARGET_ASM_ALIGNED_HI_OP
22644 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
22645 #undef TARGET_ASM_ALIGNED_SI_OP
22646 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
22648 #undef TARGET_ASM_ALIGNED_DI_OP
22649 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
22652 #undef TARGET_ASM_UNALIGNED_HI_OP
22653 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
22654 #undef TARGET_ASM_UNALIGNED_SI_OP
22655 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
22656 #undef TARGET_ASM_UNALIGNED_DI_OP
22657 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
22659 #undef TARGET_SCHED_ADJUST_COST
22660 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
22661 #undef TARGET_SCHED_ISSUE_RATE
22662 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
22663 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
22664 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
22665 ia32_multipass_dfa_lookahead
22667 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
22668 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
22671 #undef TARGET_HAVE_TLS
22672 #define TARGET_HAVE_TLS true
22674 #undef TARGET_CANNOT_FORCE_CONST_MEM
22675 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
22676 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
22677 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_rtx_true
22679 #undef TARGET_DELEGITIMIZE_ADDRESS
22680 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
22682 #undef TARGET_MS_BITFIELD_LAYOUT_P
22683 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
22686 #undef TARGET_BINDS_LOCAL_P
22687 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
22689 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
22690 #undef TARGET_BINDS_LOCAL_P
22691 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
22694 #undef TARGET_ASM_OUTPUT_MI_THUNK
22695 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
22696 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
22697 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
22699 #undef TARGET_ASM_FILE_START
22700 #define TARGET_ASM_FILE_START x86_file_start
22702 #undef TARGET_DEFAULT_TARGET_FLAGS
22703 #define TARGET_DEFAULT_TARGET_FLAGS \
22705 | TARGET_64BIT_DEFAULT \
22706 | TARGET_SUBTARGET_DEFAULT \
22707 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
22709 #undef TARGET_HANDLE_OPTION
22710 #define TARGET_HANDLE_OPTION ix86_handle_option
22712 #undef TARGET_RTX_COSTS
22713 #define TARGET_RTX_COSTS ix86_rtx_costs
22714 #undef TARGET_ADDRESS_COST
22715 #define TARGET_ADDRESS_COST ix86_address_cost
22717 #undef TARGET_FIXED_CONDITION_CODE_REGS
22718 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
22719 #undef TARGET_CC_MODES_COMPATIBLE
22720 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
22722 #undef TARGET_MACHINE_DEPENDENT_REORG
22723 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
22725 #undef TARGET_BUILD_BUILTIN_VA_LIST
22726 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
22728 #undef TARGET_MD_ASM_CLOBBERS
22729 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
22731 #undef TARGET_PROMOTE_PROTOTYPES
22732 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
22733 #undef TARGET_STRUCT_VALUE_RTX
22734 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
22735 #undef TARGET_SETUP_INCOMING_VARARGS
22736 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
22737 #undef TARGET_MUST_PASS_IN_STACK
22738 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
22739 #undef TARGET_PASS_BY_REFERENCE
22740 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
22741 #undef TARGET_INTERNAL_ARG_POINTER
22742 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
22743 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
22744 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
22745 #undef TARGET_STRICT_ARGUMENT_NAMING
22746 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
22748 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
22749 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
22751 #undef TARGET_SCALAR_MODE_SUPPORTED_P
22752 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
22754 #undef TARGET_VECTOR_MODE_SUPPORTED_P
22755 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
22758 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
22759 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
22762 #ifdef SUBTARGET_INSERT_ATTRIBUTES
22763 #undef TARGET_INSERT_ATTRIBUTES
22764 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
22767 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
22768 #define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type
22770 #undef TARGET_STACK_PROTECT_FAIL
22771 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
22773 #undef TARGET_FUNCTION_VALUE
22774 #define TARGET_FUNCTION_VALUE ix86_function_value
22776 struct gcc_target targetm = TARGET_INITIALIZER;
22778 #include "gt-i386.h"
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