1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
58 static int x86_builtin_vectorization_cost (bool);
59 static rtx legitimize_dllimport_symbol (rtx, bool);
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
80 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
81 COSTS_N_BYTES (2), /* cost of an add instruction */
82 COSTS_N_BYTES (3), /* cost of a lea instruction */
83 COSTS_N_BYTES (2), /* variable shift costs */
84 COSTS_N_BYTES (3), /* constant shift costs */
85 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 0, /* cost of multiply per each bit set */
91 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
92 COSTS_N_BYTES (3), /* HI */
93 COSTS_N_BYTES (3), /* SI */
94 COSTS_N_BYTES (3), /* DI */
95 COSTS_N_BYTES (5)}, /* other */
96 COSTS_N_BYTES (3), /* cost of movsx */
97 COSTS_N_BYTES (3), /* cost of movzx */
100 2, /* cost for loading QImode using movzbl */
101 {2, 2, 2}, /* cost of loading integer registers
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
104 {2, 2, 2}, /* cost of storing integer registers */
105 2, /* cost of reg,reg fld/fst */
106 {2, 2, 2}, /* cost of loading fp registers
107 in SFmode, DFmode and XFmode */
108 {2, 2, 2}, /* cost of storing fp registers
109 in SFmode, DFmode and XFmode */
110 3, /* cost of moving MMX register */
111 {3, 3}, /* cost of loading MMX registers
112 in SImode and DImode */
113 {3, 3}, /* cost of storing MMX registers
114 in SImode and DImode */
115 3, /* cost of moving SSE register */
116 {3, 3, 3}, /* cost of loading SSE registers
117 in SImode, DImode and TImode */
118 {3, 3, 3}, /* cost of storing SSE registers
119 in SImode, DImode and TImode */
120 3, /* MMX or SSE register to integer */
121 0, /* size of l1 cache */
122 0, /* size of l2 cache */
123 0, /* size of prefetch block */
124 0, /* number of parallel prefetches */
126 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
127 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
128 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
129 COSTS_N_BYTES (2), /* cost of FABS instruction. */
130 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
131 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
132 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
133 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
134 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
135 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
136 1, /* scalar_stmt_cost. */
137 1, /* scalar load_cost. */
138 1, /* scalar_store_cost. */
139 1, /* vec_stmt_cost. */
140 1, /* vec_to_scalar_cost. */
141 1, /* scalar_to_vec_cost. */
142 1, /* vec_align_load_cost. */
143 1, /* vec_unalign_load_cost. */
144 1, /* vec_store_cost. */
145 1, /* cond_taken_branch_cost. */
146 1, /* cond_not_taken_branch_cost. */
149 /* Processor costs (relative to an add) */
151 struct processor_costs i386_cost = { /* 386 specific costs */
152 COSTS_N_INSNS (1), /* cost of an add instruction */
153 COSTS_N_INSNS (1), /* cost of a lea instruction */
154 COSTS_N_INSNS (3), /* variable shift costs */
155 COSTS_N_INSNS (2), /* constant shift costs */
156 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
157 COSTS_N_INSNS (6), /* HI */
158 COSTS_N_INSNS (6), /* SI */
159 COSTS_N_INSNS (6), /* DI */
160 COSTS_N_INSNS (6)}, /* other */
161 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
162 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
163 COSTS_N_INSNS (23), /* HI */
164 COSTS_N_INSNS (23), /* SI */
165 COSTS_N_INSNS (23), /* DI */
166 COSTS_N_INSNS (23)}, /* other */
167 COSTS_N_INSNS (3), /* cost of movsx */
168 COSTS_N_INSNS (2), /* cost of movzx */
169 15, /* "large" insn */
171 4, /* cost for loading QImode using movzbl */
172 {2, 4, 2}, /* cost of loading integer registers
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
175 {2, 4, 2}, /* cost of storing integer registers */
176 2, /* cost of reg,reg fld/fst */
177 {8, 8, 8}, /* cost of loading fp registers
178 in SFmode, DFmode and XFmode */
179 {8, 8, 8}, /* cost of storing fp registers
180 in SFmode, DFmode and XFmode */
181 2, /* cost of moving MMX register */
182 {4, 8}, /* cost of loading MMX registers
183 in SImode and DImode */
184 {4, 8}, /* cost of storing MMX registers
185 in SImode and DImode */
186 2, /* cost of moving SSE register */
187 {4, 8, 16}, /* cost of loading SSE registers
188 in SImode, DImode and TImode */
189 {4, 8, 16}, /* cost of storing SSE registers
190 in SImode, DImode and TImode */
191 3, /* MMX or SSE register to integer */
192 0, /* size of l1 cache */
193 0, /* size of l2 cache */
194 0, /* size of prefetch block */
195 0, /* number of parallel prefetches */
197 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
198 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
199 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
200 COSTS_N_INSNS (22), /* cost of FABS instruction. */
201 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
202 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
203 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
204 DUMMY_STRINGOP_ALGS},
205 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
206 DUMMY_STRINGOP_ALGS},
207 1, /* scalar_stmt_cost. */
208 1, /* scalar load_cost. */
209 1, /* scalar_store_cost. */
210 1, /* vec_stmt_cost. */
211 1, /* vec_to_scalar_cost. */
212 1, /* scalar_to_vec_cost. */
213 1, /* vec_align_load_cost. */
214 2, /* vec_unalign_load_cost. */
215 1, /* vec_store_cost. */
216 3, /* cond_taken_branch_cost. */
217 1, /* cond_not_taken_branch_cost. */
221 struct processor_costs i486_cost = { /* 486 specific costs */
222 COSTS_N_INSNS (1), /* cost of an add instruction */
223 COSTS_N_INSNS (1), /* cost of a lea instruction */
224 COSTS_N_INSNS (3), /* variable shift costs */
225 COSTS_N_INSNS (2), /* constant shift costs */
226 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
227 COSTS_N_INSNS (12), /* HI */
228 COSTS_N_INSNS (12), /* SI */
229 COSTS_N_INSNS (12), /* DI */
230 COSTS_N_INSNS (12)}, /* other */
231 1, /* cost of multiply per each bit set */
232 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
233 COSTS_N_INSNS (40), /* HI */
234 COSTS_N_INSNS (40), /* SI */
235 COSTS_N_INSNS (40), /* DI */
236 COSTS_N_INSNS (40)}, /* other */
237 COSTS_N_INSNS (3), /* cost of movsx */
238 COSTS_N_INSNS (2), /* cost of movzx */
239 15, /* "large" insn */
241 4, /* cost for loading QImode using movzbl */
242 {2, 4, 2}, /* cost of loading integer registers
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
245 {2, 4, 2}, /* cost of storing integer registers */
246 2, /* cost of reg,reg fld/fst */
247 {8, 8, 8}, /* cost of loading fp registers
248 in SFmode, DFmode and XFmode */
249 {8, 8, 8}, /* cost of storing fp registers
250 in SFmode, DFmode and XFmode */
251 2, /* cost of moving MMX register */
252 {4, 8}, /* cost of loading MMX registers
253 in SImode and DImode */
254 {4, 8}, /* cost of storing MMX registers
255 in SImode and DImode */
256 2, /* cost of moving SSE register */
257 {4, 8, 16}, /* cost of loading SSE registers
258 in SImode, DImode and TImode */
259 {4, 8, 16}, /* cost of storing SSE registers
260 in SImode, DImode and TImode */
261 3, /* MMX or SSE register to integer */
262 4, /* size of l1 cache. 486 has 8kB cache
263 shared for code and data, so 4kB is
264 not really precise. */
265 4, /* size of l2 cache */
266 0, /* size of prefetch block */
267 0, /* number of parallel prefetches */
269 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
270 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
271 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
272 COSTS_N_INSNS (3), /* cost of FABS instruction. */
273 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
274 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
275 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
276 DUMMY_STRINGOP_ALGS},
277 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
278 DUMMY_STRINGOP_ALGS},
279 1, /* scalar_stmt_cost. */
280 1, /* scalar load_cost. */
281 1, /* scalar_store_cost. */
282 1, /* vec_stmt_cost. */
283 1, /* vec_to_scalar_cost. */
284 1, /* scalar_to_vec_cost. */
285 1, /* vec_align_load_cost. */
286 2, /* vec_unalign_load_cost. */
287 1, /* vec_store_cost. */
288 3, /* cond_taken_branch_cost. */
289 1, /* cond_not_taken_branch_cost. */
293 struct processor_costs pentium_cost = {
294 COSTS_N_INSNS (1), /* cost of an add instruction */
295 COSTS_N_INSNS (1), /* cost of a lea instruction */
296 COSTS_N_INSNS (4), /* variable shift costs */
297 COSTS_N_INSNS (1), /* constant shift costs */
298 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
299 COSTS_N_INSNS (11), /* HI */
300 COSTS_N_INSNS (11), /* SI */
301 COSTS_N_INSNS (11), /* DI */
302 COSTS_N_INSNS (11)}, /* other */
303 0, /* cost of multiply per each bit set */
304 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
305 COSTS_N_INSNS (25), /* HI */
306 COSTS_N_INSNS (25), /* SI */
307 COSTS_N_INSNS (25), /* DI */
308 COSTS_N_INSNS (25)}, /* other */
309 COSTS_N_INSNS (3), /* cost of movsx */
310 COSTS_N_INSNS (2), /* cost of movzx */
311 8, /* "large" insn */
313 6, /* cost for loading QImode using movzbl */
314 {2, 4, 2}, /* cost of loading integer registers
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
317 {2, 4, 2}, /* cost of storing integer registers */
318 2, /* cost of reg,reg fld/fst */
319 {2, 2, 6}, /* cost of loading fp registers
320 in SFmode, DFmode and XFmode */
321 {4, 4, 6}, /* cost of storing fp registers
322 in SFmode, DFmode and XFmode */
323 8, /* cost of moving MMX register */
324 {8, 8}, /* cost of loading MMX registers
325 in SImode and DImode */
326 {8, 8}, /* cost of storing MMX registers
327 in SImode and DImode */
328 2, /* cost of moving SSE register */
329 {4, 8, 16}, /* cost of loading SSE registers
330 in SImode, DImode and TImode */
331 {4, 8, 16}, /* cost of storing SSE registers
332 in SImode, DImode and TImode */
333 3, /* MMX or SSE register to integer */
334 8, /* size of l1 cache. */
335 8, /* size of l2 cache */
336 0, /* size of prefetch block */
337 0, /* number of parallel prefetches */
339 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
340 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
341 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
342 COSTS_N_INSNS (1), /* cost of FABS instruction. */
343 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
344 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
345 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
346 DUMMY_STRINGOP_ALGS},
347 {{libcall, {{-1, rep_prefix_4_byte}}},
348 DUMMY_STRINGOP_ALGS},
349 1, /* scalar_stmt_cost. */
350 1, /* scalar load_cost. */
351 1, /* scalar_store_cost. */
352 1, /* vec_stmt_cost. */
353 1, /* vec_to_scalar_cost. */
354 1, /* scalar_to_vec_cost. */
355 1, /* vec_align_load_cost. */
356 2, /* vec_unalign_load_cost. */
357 1, /* vec_store_cost. */
358 3, /* cond_taken_branch_cost. */
359 1, /* cond_not_taken_branch_cost. */
363 struct processor_costs pentiumpro_cost = {
364 COSTS_N_INSNS (1), /* cost of an add instruction */
365 COSTS_N_INSNS (1), /* cost of a lea instruction */
366 COSTS_N_INSNS (1), /* variable shift costs */
367 COSTS_N_INSNS (1), /* constant shift costs */
368 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
369 COSTS_N_INSNS (4), /* HI */
370 COSTS_N_INSNS (4), /* SI */
371 COSTS_N_INSNS (4), /* DI */
372 COSTS_N_INSNS (4)}, /* other */
373 0, /* cost of multiply per each bit set */
374 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
375 COSTS_N_INSNS (17), /* HI */
376 COSTS_N_INSNS (17), /* SI */
377 COSTS_N_INSNS (17), /* DI */
378 COSTS_N_INSNS (17)}, /* other */
379 COSTS_N_INSNS (1), /* cost of movsx */
380 COSTS_N_INSNS (1), /* cost of movzx */
381 8, /* "large" insn */
383 2, /* cost for loading QImode using movzbl */
384 {4, 4, 4}, /* cost of loading integer registers
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
387 {2, 2, 2}, /* cost of storing integer registers */
388 2, /* cost of reg,reg fld/fst */
389 {2, 2, 6}, /* cost of loading fp registers
390 in SFmode, DFmode and XFmode */
391 {4, 4, 6}, /* cost of storing fp registers
392 in SFmode, DFmode and XFmode */
393 2, /* cost of moving MMX register */
394 {2, 2}, /* cost of loading MMX registers
395 in SImode and DImode */
396 {2, 2}, /* cost of storing MMX registers
397 in SImode and DImode */
398 2, /* cost of moving SSE register */
399 {2, 2, 8}, /* cost of loading SSE registers
400 in SImode, DImode and TImode */
401 {2, 2, 8}, /* cost of storing SSE registers
402 in SImode, DImode and TImode */
403 3, /* MMX or SSE register to integer */
404 8, /* size of l1 cache. */
405 256, /* size of l2 cache */
406 32, /* size of prefetch block */
407 6, /* number of parallel prefetches */
409 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
410 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
411 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
412 COSTS_N_INSNS (2), /* cost of FABS instruction. */
413 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
414 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
420 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
422 DUMMY_STRINGOP_ALGS},
423 {{rep_prefix_4_byte, {{1024, unrolled_loop},
424 {8192, rep_prefix_4_byte}, {-1, libcall}}},
425 DUMMY_STRINGOP_ALGS},
426 1, /* scalar_stmt_cost. */
427 1, /* scalar load_cost. */
428 1, /* scalar_store_cost. */
429 1, /* vec_stmt_cost. */
430 1, /* vec_to_scalar_cost. */
431 1, /* scalar_to_vec_cost. */
432 1, /* vec_align_load_cost. */
433 2, /* vec_unalign_load_cost. */
434 1, /* vec_store_cost. */
435 3, /* cond_taken_branch_cost. */
436 1, /* cond_not_taken_branch_cost. */
440 struct processor_costs geode_cost = {
441 COSTS_N_INSNS (1), /* cost of an add instruction */
442 COSTS_N_INSNS (1), /* cost of a lea instruction */
443 COSTS_N_INSNS (2), /* variable shift costs */
444 COSTS_N_INSNS (1), /* constant shift costs */
445 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
446 COSTS_N_INSNS (4), /* HI */
447 COSTS_N_INSNS (7), /* SI */
448 COSTS_N_INSNS (7), /* DI */
449 COSTS_N_INSNS (7)}, /* other */
450 0, /* cost of multiply per each bit set */
451 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
452 COSTS_N_INSNS (23), /* HI */
453 COSTS_N_INSNS (39), /* SI */
454 COSTS_N_INSNS (39), /* DI */
455 COSTS_N_INSNS (39)}, /* other */
456 COSTS_N_INSNS (1), /* cost of movsx */
457 COSTS_N_INSNS (1), /* cost of movzx */
458 8, /* "large" insn */
460 1, /* cost for loading QImode using movzbl */
461 {1, 1, 1}, /* cost of loading integer registers
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
464 {1, 1, 1}, /* cost of storing integer registers */
465 1, /* cost of reg,reg fld/fst */
466 {1, 1, 1}, /* cost of loading fp registers
467 in SFmode, DFmode and XFmode */
468 {4, 6, 6}, /* cost of storing fp registers
469 in SFmode, DFmode and XFmode */
471 1, /* cost of moving MMX register */
472 {1, 1}, /* cost of loading MMX registers
473 in SImode and DImode */
474 {1, 1}, /* cost of storing MMX registers
475 in SImode and DImode */
476 1, /* cost of moving SSE register */
477 {1, 1, 1}, /* cost of loading SSE registers
478 in SImode, DImode and TImode */
479 {1, 1, 1}, /* cost of storing SSE registers
480 in SImode, DImode and TImode */
481 1, /* MMX or SSE register to integer */
482 64, /* size of l1 cache. */
483 128, /* size of l2 cache. */
484 32, /* size of prefetch block */
485 1, /* number of parallel prefetches */
487 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
488 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
489 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
490 COSTS_N_INSNS (1), /* cost of FABS instruction. */
491 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
492 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
493 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
494 DUMMY_STRINGOP_ALGS},
495 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
496 DUMMY_STRINGOP_ALGS},
497 1, /* scalar_stmt_cost. */
498 1, /* scalar load_cost. */
499 1, /* scalar_store_cost. */
500 1, /* vec_stmt_cost. */
501 1, /* vec_to_scalar_cost. */
502 1, /* scalar_to_vec_cost. */
503 1, /* vec_align_load_cost. */
504 2, /* vec_unalign_load_cost. */
505 1, /* vec_store_cost. */
506 3, /* cond_taken_branch_cost. */
507 1, /* cond_not_taken_branch_cost. */
511 struct processor_costs k6_cost = {
512 COSTS_N_INSNS (1), /* cost of an add instruction */
513 COSTS_N_INSNS (2), /* cost of a lea instruction */
514 COSTS_N_INSNS (1), /* variable shift costs */
515 COSTS_N_INSNS (1), /* constant shift costs */
516 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
517 COSTS_N_INSNS (3), /* HI */
518 COSTS_N_INSNS (3), /* SI */
519 COSTS_N_INSNS (3), /* DI */
520 COSTS_N_INSNS (3)}, /* other */
521 0, /* cost of multiply per each bit set */
522 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
523 COSTS_N_INSNS (18), /* HI */
524 COSTS_N_INSNS (18), /* SI */
525 COSTS_N_INSNS (18), /* DI */
526 COSTS_N_INSNS (18)}, /* other */
527 COSTS_N_INSNS (2), /* cost of movsx */
528 COSTS_N_INSNS (2), /* cost of movzx */
529 8, /* "large" insn */
531 3, /* cost for loading QImode using movzbl */
532 {4, 5, 4}, /* cost of loading integer registers
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
535 {2, 3, 2}, /* cost of storing integer registers */
536 4, /* cost of reg,reg fld/fst */
537 {6, 6, 6}, /* cost of loading fp registers
538 in SFmode, DFmode and XFmode */
539 {4, 4, 4}, /* cost of storing fp registers
540 in SFmode, DFmode and XFmode */
541 2, /* cost of moving MMX register */
542 {2, 2}, /* cost of loading MMX registers
543 in SImode and DImode */
544 {2, 2}, /* cost of storing MMX registers
545 in SImode and DImode */
546 2, /* cost of moving SSE register */
547 {2, 2, 8}, /* cost of loading SSE registers
548 in SImode, DImode and TImode */
549 {2, 2, 8}, /* cost of storing SSE registers
550 in SImode, DImode and TImode */
551 6, /* MMX or SSE register to integer */
552 32, /* size of l1 cache. */
553 32, /* size of l2 cache. Some models
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
557 32, /* size of prefetch block */
558 1, /* number of parallel prefetches */
560 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
561 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
562 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
563 COSTS_N_INSNS (2), /* cost of FABS instruction. */
564 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
565 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
566 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
567 DUMMY_STRINGOP_ALGS},
568 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
569 DUMMY_STRINGOP_ALGS},
570 1, /* scalar_stmt_cost. */
571 1, /* scalar load_cost. */
572 1, /* scalar_store_cost. */
573 1, /* vec_stmt_cost. */
574 1, /* vec_to_scalar_cost. */
575 1, /* scalar_to_vec_cost. */
576 1, /* vec_align_load_cost. */
577 2, /* vec_unalign_load_cost. */
578 1, /* vec_store_cost. */
579 3, /* cond_taken_branch_cost. */
580 1, /* cond_not_taken_branch_cost. */
584 struct processor_costs athlon_cost = {
585 COSTS_N_INSNS (1), /* cost of an add instruction */
586 COSTS_N_INSNS (2), /* cost of a lea instruction */
587 COSTS_N_INSNS (1), /* variable shift costs */
588 COSTS_N_INSNS (1), /* constant shift costs */
589 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
590 COSTS_N_INSNS (5), /* HI */
591 COSTS_N_INSNS (5), /* SI */
592 COSTS_N_INSNS (5), /* DI */
593 COSTS_N_INSNS (5)}, /* other */
594 0, /* cost of multiply per each bit set */
595 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
596 COSTS_N_INSNS (26), /* HI */
597 COSTS_N_INSNS (42), /* SI */
598 COSTS_N_INSNS (74), /* DI */
599 COSTS_N_INSNS (74)}, /* other */
600 COSTS_N_INSNS (1), /* cost of movsx */
601 COSTS_N_INSNS (1), /* cost of movzx */
602 8, /* "large" insn */
604 4, /* cost for loading QImode using movzbl */
605 {3, 4, 3}, /* cost of loading integer registers
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
608 {3, 4, 3}, /* cost of storing integer registers */
609 4, /* cost of reg,reg fld/fst */
610 {4, 4, 12}, /* cost of loading fp registers
611 in SFmode, DFmode and XFmode */
612 {6, 6, 8}, /* cost of storing fp registers
613 in SFmode, DFmode and XFmode */
614 2, /* cost of moving MMX register */
615 {4, 4}, /* cost of loading MMX registers
616 in SImode and DImode */
617 {4, 4}, /* cost of storing MMX registers
618 in SImode and DImode */
619 2, /* cost of moving SSE register */
620 {4, 4, 6}, /* cost of loading SSE registers
621 in SImode, DImode and TImode */
622 {4, 4, 5}, /* cost of storing SSE registers
623 in SImode, DImode and TImode */
624 5, /* MMX or SSE register to integer */
625 64, /* size of l1 cache. */
626 256, /* size of l2 cache. */
627 64, /* size of prefetch block */
628 6, /* number of parallel prefetches */
630 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
631 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
632 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
633 COSTS_N_INSNS (2), /* cost of FABS instruction. */
634 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
635 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
639 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
640 DUMMY_STRINGOP_ALGS},
641 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
642 DUMMY_STRINGOP_ALGS},
643 1, /* scalar_stmt_cost. */
644 1, /* scalar load_cost. */
645 1, /* scalar_store_cost. */
646 1, /* vec_stmt_cost. */
647 1, /* vec_to_scalar_cost. */
648 1, /* scalar_to_vec_cost. */
649 1, /* vec_align_load_cost. */
650 2, /* vec_unalign_load_cost. */
651 1, /* vec_store_cost. */
652 3, /* cond_taken_branch_cost. */
653 1, /* cond_not_taken_branch_cost. */
657 struct processor_costs k8_cost = {
658 COSTS_N_INSNS (1), /* cost of an add instruction */
659 COSTS_N_INSNS (2), /* cost of a lea instruction */
660 COSTS_N_INSNS (1), /* variable shift costs */
661 COSTS_N_INSNS (1), /* constant shift costs */
662 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
663 COSTS_N_INSNS (4), /* HI */
664 COSTS_N_INSNS (3), /* SI */
665 COSTS_N_INSNS (4), /* DI */
666 COSTS_N_INSNS (5)}, /* other */
667 0, /* cost of multiply per each bit set */
668 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
669 COSTS_N_INSNS (26), /* HI */
670 COSTS_N_INSNS (42), /* SI */
671 COSTS_N_INSNS (74), /* DI */
672 COSTS_N_INSNS (74)}, /* other */
673 COSTS_N_INSNS (1), /* cost of movsx */
674 COSTS_N_INSNS (1), /* cost of movzx */
675 8, /* "large" insn */
677 4, /* cost for loading QImode using movzbl */
678 {3, 4, 3}, /* cost of loading integer registers
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
681 {3, 4, 3}, /* cost of storing integer registers */
682 4, /* cost of reg,reg fld/fst */
683 {4, 4, 12}, /* cost of loading fp registers
684 in SFmode, DFmode and XFmode */
685 {6, 6, 8}, /* cost of storing fp registers
686 in SFmode, DFmode and XFmode */
687 2, /* cost of moving MMX register */
688 {3, 3}, /* cost of loading MMX registers
689 in SImode and DImode */
690 {4, 4}, /* cost of storing MMX registers
691 in SImode and DImode */
692 2, /* cost of moving SSE register */
693 {4, 3, 6}, /* cost of loading SSE registers
694 in SImode, DImode and TImode */
695 {4, 4, 5}, /* cost of storing SSE registers
696 in SImode, DImode and TImode */
697 5, /* MMX or SSE register to integer */
698 64, /* size of l1 cache. */
699 512, /* size of l2 cache. */
700 64, /* size of prefetch block */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
706 100, /* number of parallel prefetches */
708 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
709 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
710 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
711 COSTS_N_INSNS (2), /* cost of FABS instruction. */
712 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
713 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
717 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
718 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 {{libcall, {{8, loop}, {24, unrolled_loop},
720 {2048, rep_prefix_4_byte}, {-1, libcall}}},
721 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
722 4, /* scalar_stmt_cost. */
723 2, /* scalar load_cost. */
724 2, /* scalar_store_cost. */
725 5, /* vec_stmt_cost. */
726 0, /* vec_to_scalar_cost. */
727 2, /* scalar_to_vec_cost. */
728 2, /* vec_align_load_cost. */
729 3, /* vec_unalign_load_cost. */
730 3, /* vec_store_cost. */
731 3, /* cond_taken_branch_cost. */
732 2, /* cond_not_taken_branch_cost. */
735 struct processor_costs amdfam10_cost = {
736 COSTS_N_INSNS (1), /* cost of an add instruction */
737 COSTS_N_INSNS (2), /* cost of a lea instruction */
738 COSTS_N_INSNS (1), /* variable shift costs */
739 COSTS_N_INSNS (1), /* constant shift costs */
740 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
741 COSTS_N_INSNS (4), /* HI */
742 COSTS_N_INSNS (3), /* SI */
743 COSTS_N_INSNS (4), /* DI */
744 COSTS_N_INSNS (5)}, /* other */
745 0, /* cost of multiply per each bit set */
746 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
747 COSTS_N_INSNS (35), /* HI */
748 COSTS_N_INSNS (51), /* SI */
749 COSTS_N_INSNS (83), /* DI */
750 COSTS_N_INSNS (83)}, /* other */
751 COSTS_N_INSNS (1), /* cost of movsx */
752 COSTS_N_INSNS (1), /* cost of movzx */
753 8, /* "large" insn */
755 4, /* cost for loading QImode using movzbl */
756 {3, 4, 3}, /* cost of loading integer registers
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
759 {3, 4, 3}, /* cost of storing integer registers */
760 4, /* cost of reg,reg fld/fst */
761 {4, 4, 12}, /* cost of loading fp registers
762 in SFmode, DFmode and XFmode */
763 {6, 6, 8}, /* cost of storing fp registers
764 in SFmode, DFmode and XFmode */
765 2, /* cost of moving MMX register */
766 {3, 3}, /* cost of loading MMX registers
767 in SImode and DImode */
768 {4, 4}, /* cost of storing MMX registers
769 in SImode and DImode */
770 2, /* cost of moving SSE register */
771 {4, 4, 3}, /* cost of loading SSE registers
772 in SImode, DImode and TImode */
773 {4, 4, 5}, /* cost of storing SSE registers
774 in SImode, DImode and TImode */
775 3, /* MMX or SSE register to integer */
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
780 MOVD reg64, xmmreg Double FADD 3
782 MOVD reg32, xmmreg Double FADD 3
784 64, /* size of l1 cache. */
785 512, /* size of l2 cache. */
786 64, /* size of prefetch block */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
792 100, /* number of parallel prefetches */
794 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
795 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
796 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
797 COSTS_N_INSNS (2), /* cost of FABS instruction. */
798 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
799 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
804 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
805 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 {{libcall, {{8, loop}, {24, unrolled_loop},
807 {2048, rep_prefix_4_byte}, {-1, libcall}}},
808 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
809 4, /* scalar_stmt_cost. */
810 2, /* scalar load_cost. */
811 2, /* scalar_store_cost. */
812 6, /* vec_stmt_cost. */
813 0, /* vec_to_scalar_cost. */
814 2, /* scalar_to_vec_cost. */
815 2, /* vec_align_load_cost. */
816 2, /* vec_unalign_load_cost. */
817 2, /* vec_store_cost. */
818 2, /* cond_taken_branch_cost. */
819 1, /* cond_not_taken_branch_cost. */
823 struct processor_costs pentium4_cost = {
824 COSTS_N_INSNS (1), /* cost of an add instruction */
825 COSTS_N_INSNS (3), /* cost of a lea instruction */
826 COSTS_N_INSNS (4), /* variable shift costs */
827 COSTS_N_INSNS (4), /* constant shift costs */
828 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
829 COSTS_N_INSNS (15), /* HI */
830 COSTS_N_INSNS (15), /* SI */
831 COSTS_N_INSNS (15), /* DI */
832 COSTS_N_INSNS (15)}, /* other */
833 0, /* cost of multiply per each bit set */
834 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
835 COSTS_N_INSNS (56), /* HI */
836 COSTS_N_INSNS (56), /* SI */
837 COSTS_N_INSNS (56), /* DI */
838 COSTS_N_INSNS (56)}, /* other */
839 COSTS_N_INSNS (1), /* cost of movsx */
840 COSTS_N_INSNS (1), /* cost of movzx */
841 16, /* "large" insn */
843 2, /* cost for loading QImode using movzbl */
844 {4, 5, 4}, /* cost of loading integer registers
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
847 {2, 3, 2}, /* cost of storing integer registers */
848 2, /* cost of reg,reg fld/fst */
849 {2, 2, 6}, /* cost of loading fp registers
850 in SFmode, DFmode and XFmode */
851 {4, 4, 6}, /* cost of storing fp registers
852 in SFmode, DFmode and XFmode */
853 2, /* cost of moving MMX register */
854 {2, 2}, /* cost of loading MMX registers
855 in SImode and DImode */
856 {2, 2}, /* cost of storing MMX registers
857 in SImode and DImode */
858 12, /* cost of moving SSE register */
859 {12, 12, 12}, /* cost of loading SSE registers
860 in SImode, DImode and TImode */
861 {2, 2, 8}, /* cost of storing SSE registers
862 in SImode, DImode and TImode */
863 10, /* MMX or SSE register to integer */
864 8, /* size of l1 cache. */
865 256, /* size of l2 cache. */
866 64, /* size of prefetch block */
867 6, /* number of parallel prefetches */
869 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
870 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
871 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
872 COSTS_N_INSNS (2), /* cost of FABS instruction. */
873 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
874 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
875 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
876 DUMMY_STRINGOP_ALGS},
877 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
879 DUMMY_STRINGOP_ALGS},
880 1, /* scalar_stmt_cost. */
881 1, /* scalar load_cost. */
882 1, /* scalar_store_cost. */
883 1, /* vec_stmt_cost. */
884 1, /* vec_to_scalar_cost. */
885 1, /* scalar_to_vec_cost. */
886 1, /* vec_align_load_cost. */
887 2, /* vec_unalign_load_cost. */
888 1, /* vec_store_cost. */
889 3, /* cond_taken_branch_cost. */
890 1, /* cond_not_taken_branch_cost. */
894 struct processor_costs nocona_cost = {
895 COSTS_N_INSNS (1), /* cost of an add instruction */
896 COSTS_N_INSNS (1), /* cost of a lea instruction */
897 COSTS_N_INSNS (1), /* variable shift costs */
898 COSTS_N_INSNS (1), /* constant shift costs */
899 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
900 COSTS_N_INSNS (10), /* HI */
901 COSTS_N_INSNS (10), /* SI */
902 COSTS_N_INSNS (10), /* DI */
903 COSTS_N_INSNS (10)}, /* other */
904 0, /* cost of multiply per each bit set */
905 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
906 COSTS_N_INSNS (66), /* HI */
907 COSTS_N_INSNS (66), /* SI */
908 COSTS_N_INSNS (66), /* DI */
909 COSTS_N_INSNS (66)}, /* other */
910 COSTS_N_INSNS (1), /* cost of movsx */
911 COSTS_N_INSNS (1), /* cost of movzx */
912 16, /* "large" insn */
914 4, /* cost for loading QImode using movzbl */
915 {4, 4, 4}, /* cost of loading integer registers
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
918 {4, 4, 4}, /* cost of storing integer registers */
919 3, /* cost of reg,reg fld/fst */
920 {12, 12, 12}, /* cost of loading fp registers
921 in SFmode, DFmode and XFmode */
922 {4, 4, 4}, /* cost of storing fp registers
923 in SFmode, DFmode and XFmode */
924 6, /* cost of moving MMX register */
925 {12, 12}, /* cost of loading MMX registers
926 in SImode and DImode */
927 {12, 12}, /* cost of storing MMX registers
928 in SImode and DImode */
929 6, /* cost of moving SSE register */
930 {12, 12, 12}, /* cost of loading SSE registers
931 in SImode, DImode and TImode */
932 {12, 12, 12}, /* cost of storing SSE registers
933 in SImode, DImode and TImode */
934 8, /* MMX or SSE register to integer */
935 8, /* size of l1 cache. */
936 1024, /* size of l2 cache. */
937 128, /* size of prefetch block */
938 8, /* number of parallel prefetches */
940 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
941 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
942 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
943 COSTS_N_INSNS (3), /* cost of FABS instruction. */
944 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
945 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
946 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
947 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
948 {100000, unrolled_loop}, {-1, libcall}}}},
949 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
951 {libcall, {{24, loop}, {64, unrolled_loop},
952 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
953 1, /* scalar_stmt_cost. */
954 1, /* scalar load_cost. */
955 1, /* scalar_store_cost. */
956 1, /* vec_stmt_cost. */
957 1, /* vec_to_scalar_cost. */
958 1, /* scalar_to_vec_cost. */
959 1, /* vec_align_load_cost. */
960 2, /* vec_unalign_load_cost. */
961 1, /* vec_store_cost. */
962 3, /* cond_taken_branch_cost. */
963 1, /* cond_not_taken_branch_cost. */
967 struct processor_costs core2_cost = {
968 COSTS_N_INSNS (1), /* cost of an add instruction */
969 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
970 COSTS_N_INSNS (1), /* variable shift costs */
971 COSTS_N_INSNS (1), /* constant shift costs */
972 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
973 COSTS_N_INSNS (3), /* HI */
974 COSTS_N_INSNS (3), /* SI */
975 COSTS_N_INSNS (3), /* DI */
976 COSTS_N_INSNS (3)}, /* other */
977 0, /* cost of multiply per each bit set */
978 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
979 COSTS_N_INSNS (22), /* HI */
980 COSTS_N_INSNS (22), /* SI */
981 COSTS_N_INSNS (22), /* DI */
982 COSTS_N_INSNS (22)}, /* other */
983 COSTS_N_INSNS (1), /* cost of movsx */
984 COSTS_N_INSNS (1), /* cost of movzx */
985 8, /* "large" insn */
987 2, /* cost for loading QImode using movzbl */
988 {6, 6, 6}, /* cost of loading integer registers
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
991 {4, 4, 4}, /* cost of storing integer registers */
992 2, /* cost of reg,reg fld/fst */
993 {6, 6, 6}, /* cost of loading fp registers
994 in SFmode, DFmode and XFmode */
995 {4, 4, 4}, /* cost of storing fp registers
996 in SFmode, DFmode and XFmode */
997 2, /* cost of moving MMX register */
998 {6, 6}, /* cost of loading MMX registers
999 in SImode and DImode */
1000 {4, 4}, /* cost of storing MMX registers
1001 in SImode and DImode */
1002 2, /* cost of moving SSE register */
1003 {6, 6, 6}, /* cost of loading SSE registers
1004 in SImode, DImode and TImode */
1005 {4, 4, 4}, /* cost of storing SSE registers
1006 in SImode, DImode and TImode */
1007 2, /* MMX or SSE register to integer */
1008 32, /* size of l1 cache. */
1009 2048, /* size of l2 cache. */
1010 128, /* size of prefetch block */
1011 8, /* number of parallel prefetches */
1012 3, /* Branch cost */
1013 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1014 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1015 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1016 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1017 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1018 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1019 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1020 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 {{libcall, {{8, loop}, {15, unrolled_loop},
1023 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1024 {libcall, {{24, loop}, {32, unrolled_loop},
1025 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1026 1, /* scalar_stmt_cost. */
1027 1, /* scalar load_cost. */
1028 1, /* scalar_store_cost. */
1029 1, /* vec_stmt_cost. */
1030 1, /* vec_to_scalar_cost. */
1031 1, /* scalar_to_vec_cost. */
1032 1, /* vec_align_load_cost. */
1033 2, /* vec_unalign_load_cost. */
1034 1, /* vec_store_cost. */
1035 3, /* cond_taken_branch_cost. */
1036 1, /* cond_not_taken_branch_cost. */
1039 /* Generic64 should produce code tuned for Nocona and K8. */
1041 struct processor_costs generic64_cost = {
1042 COSTS_N_INSNS (1), /* cost of an add instruction */
1043 /* On all chips taken into consideration lea is 2 cycles and more. With
1044 this cost however our current implementation of synth_mult results in
1045 use of unnecessary temporary registers causing regression on several
1046 SPECfp benchmarks. */
1047 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1048 COSTS_N_INSNS (1), /* variable shift costs */
1049 COSTS_N_INSNS (1), /* constant shift costs */
1050 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1051 COSTS_N_INSNS (4), /* HI */
1052 COSTS_N_INSNS (3), /* SI */
1053 COSTS_N_INSNS (4), /* DI */
1054 COSTS_N_INSNS (2)}, /* other */
1055 0, /* cost of multiply per each bit set */
1056 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1057 COSTS_N_INSNS (26), /* HI */
1058 COSTS_N_INSNS (42), /* SI */
1059 COSTS_N_INSNS (74), /* DI */
1060 COSTS_N_INSNS (74)}, /* other */
1061 COSTS_N_INSNS (1), /* cost of movsx */
1062 COSTS_N_INSNS (1), /* cost of movzx */
1063 8, /* "large" insn */
1064 17, /* MOVE_RATIO */
1065 4, /* cost for loading QImode using movzbl */
1066 {4, 4, 4}, /* cost of loading integer registers
1067 in QImode, HImode and SImode.
1068 Relative to reg-reg move (2). */
1069 {4, 4, 4}, /* cost of storing integer registers */
1070 4, /* cost of reg,reg fld/fst */
1071 {12, 12, 12}, /* cost of loading fp registers
1072 in SFmode, DFmode and XFmode */
1073 {6, 6, 8}, /* cost of storing fp registers
1074 in SFmode, DFmode and XFmode */
1075 2, /* cost of moving MMX register */
1076 {8, 8}, /* cost of loading MMX registers
1077 in SImode and DImode */
1078 {8, 8}, /* cost of storing MMX registers
1079 in SImode and DImode */
1080 2, /* cost of moving SSE register */
1081 {8, 8, 8}, /* cost of loading SSE registers
1082 in SImode, DImode and TImode */
1083 {8, 8, 8}, /* cost of storing SSE registers
1084 in SImode, DImode and TImode */
1085 5, /* MMX or SSE register to integer */
1086 32, /* size of l1 cache. */
1087 512, /* size of l2 cache. */
1088 64, /* size of prefetch block */
1089 6, /* number of parallel prefetches */
1090 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1091 is increased to perhaps more appropriate value of 5. */
1092 3, /* Branch cost */
1093 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1094 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1095 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1096 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1097 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1098 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 {DUMMY_STRINGOP_ALGS,
1102 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1103 1, /* scalar_stmt_cost. */
1104 1, /* scalar load_cost. */
1105 1, /* scalar_store_cost. */
1106 1, /* vec_stmt_cost. */
1107 1, /* vec_to_scalar_cost. */
1108 1, /* scalar_to_vec_cost. */
1109 1, /* vec_align_load_cost. */
1110 2, /* vec_unalign_load_cost. */
1111 1, /* vec_store_cost. */
1112 3, /* cond_taken_branch_cost. */
1113 1, /* cond_not_taken_branch_cost. */
1116 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1118 struct processor_costs generic32_cost = {
1119 COSTS_N_INSNS (1), /* cost of an add instruction */
1120 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1121 COSTS_N_INSNS (1), /* variable shift costs */
1122 COSTS_N_INSNS (1), /* constant shift costs */
1123 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1124 COSTS_N_INSNS (4), /* HI */
1125 COSTS_N_INSNS (3), /* SI */
1126 COSTS_N_INSNS (4), /* DI */
1127 COSTS_N_INSNS (2)}, /* other */
1128 0, /* cost of multiply per each bit set */
1129 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1130 COSTS_N_INSNS (26), /* HI */
1131 COSTS_N_INSNS (42), /* SI */
1132 COSTS_N_INSNS (74), /* DI */
1133 COSTS_N_INSNS (74)}, /* other */
1134 COSTS_N_INSNS (1), /* cost of movsx */
1135 COSTS_N_INSNS (1), /* cost of movzx */
1136 8, /* "large" insn */
1137 17, /* MOVE_RATIO */
1138 4, /* cost for loading QImode using movzbl */
1139 {4, 4, 4}, /* cost of loading integer registers
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1142 {4, 4, 4}, /* cost of storing integer registers */
1143 4, /* cost of reg,reg fld/fst */
1144 {12, 12, 12}, /* cost of loading fp registers
1145 in SFmode, DFmode and XFmode */
1146 {6, 6, 8}, /* cost of storing fp registers
1147 in SFmode, DFmode and XFmode */
1148 2, /* cost of moving MMX register */
1149 {8, 8}, /* cost of loading MMX registers
1150 in SImode and DImode */
1151 {8, 8}, /* cost of storing MMX registers
1152 in SImode and DImode */
1153 2, /* cost of moving SSE register */
1154 {8, 8, 8}, /* cost of loading SSE registers
1155 in SImode, DImode and TImode */
1156 {8, 8, 8}, /* cost of storing SSE registers
1157 in SImode, DImode and TImode */
1158 5, /* MMX or SSE register to integer */
1159 32, /* size of l1 cache. */
1160 256, /* size of l2 cache. */
1161 64, /* size of prefetch block */
1162 6, /* number of parallel prefetches */
1163 3, /* Branch cost */
1164 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1165 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1166 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1167 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1168 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1169 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1173 DUMMY_STRINGOP_ALGS},
1174 1, /* scalar_stmt_cost. */
1175 1, /* scalar load_cost. */
1176 1, /* scalar_store_cost. */
1177 1, /* vec_stmt_cost. */
1178 1, /* vec_to_scalar_cost. */
1179 1, /* scalar_to_vec_cost. */
1180 1, /* vec_align_load_cost. */
1181 2, /* vec_unalign_load_cost. */
1182 1, /* vec_store_cost. */
1183 3, /* cond_taken_branch_cost. */
1184 1, /* cond_not_taken_branch_cost. */
1187 const struct processor_costs *ix86_cost = &pentium_cost;
1189 /* Processor feature/optimization bitmasks. */
1190 #define m_386 (1<<PROCESSOR_I386)
1191 #define m_486 (1<<PROCESSOR_I486)
1192 #define m_PENT (1<<PROCESSOR_PENTIUM)
1193 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1194 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1196 #define m_CORE2 (1<<PROCESSOR_CORE2)
1198 #define m_GEODE (1<<PROCESSOR_GEODE)
1199 #define m_K6 (1<<PROCESSOR_K6)
1200 #define m_K6_GEODE (m_K6 | m_GEODE)
1201 #define m_K8 (1<<PROCESSOR_K8)
1202 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1203 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1204 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1205 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1207 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1208 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1210 /* Generic instruction choice should be common subset of supported CPUs
1211 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1212 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1214 /* Feature tests against the various tunings. */
1215 unsigned char ix86_tune_features[X86_TUNE_LAST];
1217 /* Feature tests against the various tunings used to create ix86_tune_features
1218 based on the processor mask. */
1219 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1220 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1221 negatively, so enabling for Generic64 seems like good code size
1222 tradeoff. We can't enable it for 32bit generic because it does not
1223 work well with PPro base chips. */
1224 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1226 /* X86_TUNE_PUSH_MEMORY */
1227 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1228 | m_NOCONA | m_CORE2 | m_GENERIC,
1230 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1233 /* X86_TUNE_UNROLL_STRLEN */
1234 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1236 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1237 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1239 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240 on simulation result. But after P4 was made, no performance benefit
1241 was observed with branch hints. It also increases the code size.
1242 As a result, icc never generates branch hints. */
1245 /* X86_TUNE_DOUBLE_WITH_ADD */
1248 /* X86_TUNE_USE_SAHF */
1249 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1250 | m_NOCONA | m_CORE2 | m_GENERIC,
1252 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253 partial dependencies. */
1254 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1255 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1257 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1258 register stalls on Generic32 compilation setting as well. However
1259 in current implementation the partial register stalls are not eliminated
1260 very well - they can be introduced via subregs synthesized by combine
1261 and can happen in caller/callee saving sequences. Because this option
1262 pays back little on PPro based chips and is in conflict with partial reg
1263 dependencies used by Athlon/P4 based chips, it is better to leave it off
1264 for generic32 for now. */
1267 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1268 m_CORE2 | m_GENERIC,
1270 /* X86_TUNE_USE_HIMODE_FIOP */
1271 m_386 | m_486 | m_K6_GEODE,
1273 /* X86_TUNE_USE_SIMODE_FIOP */
1274 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1276 /* X86_TUNE_USE_MOV0 */
1279 /* X86_TUNE_USE_CLTD */
1280 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1282 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1285 /* X86_TUNE_SPLIT_LONG_MOVES */
1288 /* X86_TUNE_READ_MODIFY_WRITE */
1291 /* X86_TUNE_READ_MODIFY */
1294 /* X86_TUNE_PROMOTE_QIMODE */
1295 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1296 | m_GENERIC /* | m_PENT4 ? */,
1298 /* X86_TUNE_FAST_PREFIX */
1299 ~(m_PENT | m_486 | m_386),
1301 /* X86_TUNE_SINGLE_STRINGOP */
1302 m_386 | m_PENT4 | m_NOCONA,
1304 /* X86_TUNE_QIMODE_MATH */
1307 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1308 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1309 might be considered for Generic32 if our scheme for avoiding partial
1310 stalls was more effective. */
1313 /* X86_TUNE_PROMOTE_QI_REGS */
1316 /* X86_TUNE_PROMOTE_HI_REGS */
1319 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1320 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1322 /* X86_TUNE_ADD_ESP_8 */
1323 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1324 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_4 */
1327 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1329 /* X86_TUNE_SUB_ESP_8 */
1330 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1331 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1333 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334 for DFmode copies */
1335 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1336 | m_GENERIC | m_GEODE),
1338 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1339 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1341 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342 conflict here in between PPro/Pentium4 based chips that thread 128bit
1343 SSE registers as single units versus K8 based chips that divide SSE
1344 registers to two 64bit halves. This knob promotes all store destinations
1345 to be 128bit to allow register renaming on 128bit SSE units, but usually
1346 results in one extra microop on 64bit SSE units. Experimental results
1347 shows that disabling this option on P4 brings over 20% SPECfp regression,
1348 while enabling it on K8 brings roughly 2.4% regression that can be partly
1349 masked by careful scheduling of moves. */
1350 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1352 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1355 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1356 are resolved on SSE register parts instead of whole registers, so we may
1357 maintain just lower part of scalar values in proper format leaving the
1358 upper part undefined. */
1361 /* X86_TUNE_SSE_TYPELESS_STORES */
1364 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1365 m_PPRO | m_PENT4 | m_NOCONA,
1367 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1368 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_PROLOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_EPILOGUE_USING_MOVE */
1374 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1376 /* X86_TUNE_SHIFT1 */
1379 /* X86_TUNE_USE_FFREEP */
1382 /* X86_TUNE_INTER_UNIT_MOVES */
1383 ~(m_AMD_MULTIPLE | m_GENERIC),
1385 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1388 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389 than 4 branch instructions in the 16 byte window. */
1390 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_SCHEDULE */
1393 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1395 /* X86_TUNE_USE_BT */
1396 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1398 /* X86_TUNE_USE_INCDEC */
1399 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1401 /* X86_TUNE_PAD_RETURNS */
1402 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_EXT_80387_CONSTANTS */
1405 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1407 /* X86_TUNE_SHORTEN_X87_SSE */
1410 /* X86_TUNE_AVOID_VECTOR_DECODE */
1413 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1414 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1417 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1418 vector path on AMD machines. */
1419 m_K8 | m_GENERIC64 | m_AMDFAM10,
1421 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1423 m_K8 | m_GENERIC64 | m_AMDFAM10,
1425 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1429 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1430 but one byte longer. */
1433 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1434 operand that cannot be represented using a modRM byte. The XOR
1435 replacement is long decoded, so this split helps here as well. */
1438 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1440 m_AMDFAM10 | m_GENERIC,
1442 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1443 from integer to FP. */
1446 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1447 with a subsequent conditional jump instruction into a single
1448 compare-and-branch uop. */
1452 /* Feature tests against the various architecture variations. */
1453 unsigned char ix86_arch_features[X86_ARCH_LAST];
1455 /* Feature tests against the various architecture variations, used to create
1456 ix86_arch_features based on the processor mask. */
1457 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1458 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1459 ~(m_386 | m_486 | m_PENT | m_K6),
1461 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1464 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1467 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1470 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1474 static const unsigned int x86_accumulate_outgoing_args
1475 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1477 static const unsigned int x86_arch_always_fancy_math_387
1478 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1479 | m_NOCONA | m_CORE2 | m_GENERIC;
1481 static enum stringop_alg stringop_alg = no_stringop;
1483 /* In case the average insn count for single function invocation is
1484 lower than this constant, emit fast (but longer) prologue and
1486 #define FAST_PROLOGUE_INSN_COUNT 20
1488 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1489 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1490 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1491 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1493 /* Array of the smallest class containing reg number REGNO, indexed by
1494 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1496 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1498 /* ax, dx, cx, bx */
1499 AREG, DREG, CREG, BREG,
1500 /* si, di, bp, sp */
1501 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1503 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1504 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1507 /* flags, fpsr, fpcr, frame */
1508 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1510 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1513 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1516 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1517 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1518 /* SSE REX registers */
1519 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1523 /* The "default" register map used in 32bit mode. */
1525 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1527 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1528 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1529 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1530 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1531 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1532 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1533 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1536 /* The "default" register map used in 64bit mode. */
1538 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1540 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1541 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1542 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1543 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1544 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1545 8,9,10,11,12,13,14,15, /* extended integer registers */
1546 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1549 /* Define the register numbers to be used in Dwarf debugging information.
1550 The SVR4 reference port C compiler uses the following register numbers
1551 in its Dwarf output code:
1552 0 for %eax (gcc regno = 0)
1553 1 for %ecx (gcc regno = 2)
1554 2 for %edx (gcc regno = 1)
1555 3 for %ebx (gcc regno = 3)
1556 4 for %esp (gcc regno = 7)
1557 5 for %ebp (gcc regno = 6)
1558 6 for %esi (gcc regno = 4)
1559 7 for %edi (gcc regno = 5)
1560 The following three DWARF register numbers are never generated by
1561 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1562 believes these numbers have these meanings.
1563 8 for %eip (no gcc equivalent)
1564 9 for %eflags (gcc regno = 17)
1565 10 for %trapno (no gcc equivalent)
1566 It is not at all clear how we should number the FP stack registers
1567 for the x86 architecture. If the version of SDB on x86/svr4 were
1568 a bit less brain dead with respect to floating-point then we would
1569 have a precedent to follow with respect to DWARF register numbers
1570 for x86 FP registers, but the SDB on x86/svr4 is so completely
1571 broken with respect to FP registers that it is hardly worth thinking
1572 of it as something to strive for compatibility with.
1573 The version of x86/svr4 SDB I have at the moment does (partially)
1574 seem to believe that DWARF register number 11 is associated with
1575 the x86 register %st(0), but that's about all. Higher DWARF
1576 register numbers don't seem to be associated with anything in
1577 particular, and even for DWARF regno 11, SDB only seems to under-
1578 stand that it should say that a variable lives in %st(0) (when
1579 asked via an `=' command) if we said it was in DWARF regno 11,
1580 but SDB still prints garbage when asked for the value of the
1581 variable in question (via a `/' command).
1582 (Also note that the labels SDB prints for various FP stack regs
1583 when doing an `x' command are all wrong.)
1584 Note that these problems generally don't affect the native SVR4
1585 C compiler because it doesn't allow the use of -O with -g and
1586 because when it is *not* optimizing, it allocates a memory
1587 location for each floating-point variable, and the memory
1588 location is what gets described in the DWARF AT_location
1589 attribute for the variable in question.
1590 Regardless of the severe mental illness of the x86/svr4 SDB, we
1591 do something sensible here and we use the following DWARF
1592 register numbers. Note that these are all stack-top-relative
1594 11 for %st(0) (gcc regno = 8)
1595 12 for %st(1) (gcc regno = 9)
1596 13 for %st(2) (gcc regno = 10)
1597 14 for %st(3) (gcc regno = 11)
1598 15 for %st(4) (gcc regno = 12)
1599 16 for %st(5) (gcc regno = 13)
1600 17 for %st(6) (gcc regno = 14)
1601 18 for %st(7) (gcc regno = 15)
1603 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1605 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1606 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1607 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1608 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1609 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1610 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1611 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1614 /* Test and compare insns in i386.md store the information needed to
1615 generate branch and scc insns here. */
1617 rtx ix86_compare_op0 = NULL_RTX;
1618 rtx ix86_compare_op1 = NULL_RTX;
1619 rtx ix86_compare_emitted = NULL_RTX;
1621 /* Define parameter passing and return registers. */
1623 static int const x86_64_int_parameter_registers[6] =
1625 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1628 static int const x86_64_ms_abi_int_parameter_registers[4] =
1630 CX_REG, DX_REG, R8_REG, R9_REG
1633 static int const x86_64_int_return_registers[4] =
1635 AX_REG, DX_REG, DI_REG, SI_REG
1638 /* Define the structure for the machine field in struct function. */
1640 struct stack_local_entry GTY(())
1642 unsigned short mode;
1645 struct stack_local_entry *next;
1648 /* Structure describing stack frame layout.
1649 Stack grows downward:
1655 saved frame pointer if frame_pointer_needed
1656 <- HARD_FRAME_POINTER
1665 [va_arg registers] (
1666 > to_allocate <- FRAME_POINTER
1678 HOST_WIDE_INT frame;
1680 int outgoing_arguments_size;
1683 HOST_WIDE_INT to_allocate;
1684 /* The offsets relative to ARG_POINTER. */
1685 HOST_WIDE_INT frame_pointer_offset;
1686 HOST_WIDE_INT hard_frame_pointer_offset;
1687 HOST_WIDE_INT stack_pointer_offset;
1689 /* When save_regs_using_mov is set, emit prologue using
1690 move instead of push instructions. */
1691 bool save_regs_using_mov;
1694 /* Code model option. */
1695 enum cmodel ix86_cmodel;
1697 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1699 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1701 /* Which unit we are generating floating point math for. */
1702 enum fpmath_unit ix86_fpmath;
1704 /* Which cpu are we scheduling for. */
1705 enum attr_cpu ix86_schedule;
1707 /* Which cpu are we optimizing for. */
1708 enum processor_type ix86_tune;
1710 /* Which instruction set architecture to use. */
1711 enum processor_type ix86_arch;
1713 /* true if sse prefetch instruction is not NOOP. */
1714 int x86_prefetch_sse;
1716 /* ix86_regparm_string as a number */
1717 static int ix86_regparm;
1719 /* -mstackrealign option */
1720 extern int ix86_force_align_arg_pointer;
1721 static const char ix86_force_align_arg_pointer_string[]
1722 = "force_align_arg_pointer";
1724 static rtx (*ix86_gen_leave) (void);
1725 static rtx (*ix86_gen_pop1) (rtx);
1726 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1727 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1728 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1729 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1730 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1731 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1733 /* Preferred alignment for stack boundary in bits. */
1734 unsigned int ix86_preferred_stack_boundary;
1736 /* Alignment for incoming stack boundary in bits specified at
1738 static unsigned int ix86_user_incoming_stack_boundary;
1740 /* Default alignment for incoming stack boundary in bits. */
1741 static unsigned int ix86_default_incoming_stack_boundary;
1743 /* Alignment for incoming stack boundary in bits. */
1744 unsigned int ix86_incoming_stack_boundary;
1746 /* Values 1-5: see jump.c */
1747 int ix86_branch_cost;
1749 /* Calling abi specific va_list type nodes. */
1750 static GTY(()) tree sysv_va_list_type_node;
1751 static GTY(()) tree ms_va_list_type_node;
1753 /* Variables which are this size or smaller are put in the data/bss
1754 or ldata/lbss sections. */
1756 int ix86_section_threshold = 65536;
1758 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1759 char internal_label_prefix[16];
1760 int internal_label_prefix_len;
1762 /* Fence to use after loop using movnt. */
1765 /* Register class used for passing given 64bit part of the argument.
1766 These represent classes as documented by the PS ABI, with the exception
1767 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1768 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1770 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1771 whenever possible (upper half does contain padding). */
1772 enum x86_64_reg_class
1775 X86_64_INTEGER_CLASS,
1776 X86_64_INTEGERSI_CLASS,
1783 X86_64_COMPLEX_X87_CLASS,
1787 #define MAX_CLASSES 4
1789 /* Table of constants used by fldpi, fldln2, etc.... */
1790 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1791 static bool ext_80387_constants_init = 0;
1794 static struct machine_function * ix86_init_machine_status (void);
1795 static rtx ix86_function_value (const_tree, const_tree, bool);
1796 static int ix86_function_regparm (const_tree, const_tree);
1797 static void ix86_compute_frame_layout (struct ix86_frame *);
1798 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1800 static void ix86_add_new_builtins (int);
1802 enum ix86_function_specific_strings
1804 IX86_FUNCTION_SPECIFIC_ARCH,
1805 IX86_FUNCTION_SPECIFIC_TUNE,
1806 IX86_FUNCTION_SPECIFIC_FPMATH,
1807 IX86_FUNCTION_SPECIFIC_MAX
1810 static char *ix86_target_string (int, int, const char *, const char *,
1811 const char *, bool);
1812 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1813 static void ix86_function_specific_save (struct cl_target_option *);
1814 static void ix86_function_specific_restore (struct cl_target_option *);
1815 static void ix86_function_specific_print (FILE *, int,
1816 struct cl_target_option *);
1817 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1818 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1819 static bool ix86_can_inline_p (tree, tree);
1820 static void ix86_set_current_function (tree);
1823 /* The svr4 ABI for the i386 says that records and unions are returned
1825 #ifndef DEFAULT_PCC_STRUCT_RETURN
1826 #define DEFAULT_PCC_STRUCT_RETURN 1
1829 /* Whether -mtune= or -march= were specified */
1830 static int ix86_tune_defaulted;
1831 static int ix86_arch_specified;
1833 /* Bit flags that specify the ISA we are compiling for. */
1834 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1836 /* A mask of ix86_isa_flags that includes bit X if X
1837 was set or cleared on the command line. */
1838 static int ix86_isa_flags_explicit;
1840 /* Define a set of ISAs which are available when a given ISA is
1841 enabled. MMX and SSE ISAs are handled separately. */
1843 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1844 #define OPTION_MASK_ISA_3DNOW_SET \
1845 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1847 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1848 #define OPTION_MASK_ISA_SSE2_SET \
1849 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1850 #define OPTION_MASK_ISA_SSE3_SET \
1851 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1852 #define OPTION_MASK_ISA_SSSE3_SET \
1853 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1854 #define OPTION_MASK_ISA_SSE4_1_SET \
1855 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1856 #define OPTION_MASK_ISA_SSE4_2_SET \
1857 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1858 #define OPTION_MASK_ISA_AVX_SET \
1859 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1860 #define OPTION_MASK_ISA_FMA_SET \
1861 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1863 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1865 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1867 #define OPTION_MASK_ISA_SSE4A_SET \
1868 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1869 #define OPTION_MASK_ISA_SSE5_SET \
1870 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1872 /* AES and PCLMUL need SSE2 because they use xmm registers */
1873 #define OPTION_MASK_ISA_AES_SET \
1874 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1875 #define OPTION_MASK_ISA_PCLMUL_SET \
1876 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1878 #define OPTION_MASK_ISA_ABM_SET \
1879 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1880 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1881 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1882 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1884 /* Define a set of ISAs which aren't available when a given ISA is
1885 disabled. MMX and SSE ISAs are handled separately. */
1887 #define OPTION_MASK_ISA_MMX_UNSET \
1888 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1889 #define OPTION_MASK_ISA_3DNOW_UNSET \
1890 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1891 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1893 #define OPTION_MASK_ISA_SSE_UNSET \
1894 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1895 #define OPTION_MASK_ISA_SSE2_UNSET \
1896 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1897 #define OPTION_MASK_ISA_SSE3_UNSET \
1898 (OPTION_MASK_ISA_SSE3 \
1899 | OPTION_MASK_ISA_SSSE3_UNSET \
1900 | OPTION_MASK_ISA_SSE4A_UNSET )
1901 #define OPTION_MASK_ISA_SSSE3_UNSET \
1902 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1903 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1904 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1905 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1906 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1907 #define OPTION_MASK_ISA_AVX_UNSET \
1908 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1909 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1911 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1913 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1915 #define OPTION_MASK_ISA_SSE4A_UNSET \
1916 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1917 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1918 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1919 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1920 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1921 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1922 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1923 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1925 /* Vectorization library interface and handlers. */
1926 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1927 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1928 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1930 /* Processor target table, indexed by processor number */
1933 const struct processor_costs *cost; /* Processor costs */
1934 const int align_loop; /* Default alignments. */
1935 const int align_loop_max_skip;
1936 const int align_jump;
1937 const int align_jump_max_skip;
1938 const int align_func;
1941 static const struct ptt processor_target_table[PROCESSOR_max] =
1943 {&i386_cost, 4, 3, 4, 3, 4},
1944 {&i486_cost, 16, 15, 16, 15, 16},
1945 {&pentium_cost, 16, 7, 16, 7, 16},
1946 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1947 {&geode_cost, 0, 0, 0, 0, 0},
1948 {&k6_cost, 32, 7, 32, 7, 32},
1949 {&athlon_cost, 16, 7, 16, 7, 16},
1950 {&pentium4_cost, 0, 0, 0, 0, 0},
1951 {&k8_cost, 16, 7, 16, 7, 16},
1952 {&nocona_cost, 0, 0, 0, 0, 0},
1953 {&core2_cost, 16, 10, 16, 10, 16},
1954 {&generic32_cost, 16, 7, 16, 7, 16},
1955 {&generic64_cost, 16, 10, 16, 10, 16},
1956 {&amdfam10_cost, 32, 24, 32, 7, 32}
1959 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1984 /* Implement TARGET_HANDLE_OPTION. */
1987 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1994 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1995 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1999 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2000 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2007 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2008 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2012 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2013 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2023 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2024 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2028 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2029 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2036 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2037 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2041 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2042 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2049 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2050 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2054 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2055 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2062 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2063 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2067 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2068 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2075 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2076 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2080 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2081 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2088 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2089 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2093 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2094 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2101 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2102 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2106 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2107 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2114 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2115 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2119 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2120 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2125 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2126 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2130 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2131 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2137 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2138 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2142 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2143 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2150 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2151 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2155 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2156 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2163 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2164 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2168 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2169 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2176 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2177 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2181 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2182 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2189 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2190 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2194 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2195 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2202 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2203 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2207 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2208 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2215 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2216 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2220 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2221 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2228 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2229 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2233 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2234 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2243 /* Return a string the documents the current -m options. The caller is
2244 responsible for freeing the string. */
2247 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2248 const char *fpmath, bool add_nl_p)
2250 struct ix86_target_opts
2252 const char *option; /* option string */
2253 int mask; /* isa mask options */
2256 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2257 preceding options while match those first. */
2258 static struct ix86_target_opts isa_opts[] =
2260 { "-m64", OPTION_MASK_ISA_64BIT },
2261 { "-msse5", OPTION_MASK_ISA_SSE5 },
2262 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2263 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2264 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2265 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2266 { "-msse3", OPTION_MASK_ISA_SSE3 },
2267 { "-msse2", OPTION_MASK_ISA_SSE2 },
2268 { "-msse", OPTION_MASK_ISA_SSE },
2269 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2270 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2271 { "-mmmx", OPTION_MASK_ISA_MMX },
2272 { "-mabm", OPTION_MASK_ISA_ABM },
2273 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2274 { "-maes", OPTION_MASK_ISA_AES },
2275 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2279 static struct ix86_target_opts flag_opts[] =
2281 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2282 { "-m80387", MASK_80387 },
2283 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2284 { "-malign-double", MASK_ALIGN_DOUBLE },
2285 { "-mcld", MASK_CLD },
2286 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2287 { "-mieee-fp", MASK_IEEE_FP },
2288 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2289 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2290 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2291 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2292 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2293 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2294 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2295 { "-mno-red-zone", MASK_NO_RED_ZONE },
2296 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2297 { "-mrecip", MASK_RECIP },
2298 { "-mrtd", MASK_RTD },
2299 { "-msseregparm", MASK_SSEREGPARM },
2300 { "-mstack-arg-probe", MASK_STACK_PROBE },
2301 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2304 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2307 char target_other[40];
2316 memset (opts, '\0', sizeof (opts));
2318 /* Add -march= option. */
2321 opts[num][0] = "-march=";
2322 opts[num++][1] = arch;
2325 /* Add -mtune= option. */
2328 opts[num][0] = "-mtune=";
2329 opts[num++][1] = tune;
2332 /* Pick out the options in isa options. */
2333 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2335 if ((isa & isa_opts[i].mask) != 0)
2337 opts[num++][0] = isa_opts[i].option;
2338 isa &= ~ isa_opts[i].mask;
2342 if (isa && add_nl_p)
2344 opts[num++][0] = isa_other;
2345 sprintf (isa_other, "(other isa: 0x%x)", isa);
2348 /* Add flag options. */
2349 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2351 if ((flags & flag_opts[i].mask) != 0)
2353 opts[num++][0] = flag_opts[i].option;
2354 flags &= ~ flag_opts[i].mask;
2358 if (flags && add_nl_p)
2360 opts[num++][0] = target_other;
2361 sprintf (target_other, "(other flags: 0x%x)", isa);
2364 /* Add -fpmath= option. */
2367 opts[num][0] = "-mfpmath=";
2368 opts[num++][1] = fpmath;
2375 gcc_assert (num < ARRAY_SIZE (opts));
2377 /* Size the string. */
2379 sep_len = (add_nl_p) ? 3 : 1;
2380 for (i = 0; i < num; i++)
2383 for (j = 0; j < 2; j++)
2385 len += strlen (opts[i][j]);
2388 /* Build the string. */
2389 ret = ptr = (char *) xmalloc (len);
2392 for (i = 0; i < num; i++)
2396 for (j = 0; j < 2; j++)
2397 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2404 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2412 for (j = 0; j < 2; j++)
2415 memcpy (ptr, opts[i][j], len2[j]);
2417 line_len += len2[j];
2422 gcc_assert (ret + len >= ptr);
2427 /* Function that is callable from the debugger to print the current
2430 ix86_debug_options (void)
2432 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2433 ix86_arch_string, ix86_tune_string,
2434 ix86_fpmath_string, true);
2438 fprintf (stderr, "%s\n\n", opts);
2442 fprintf (stderr, "<no options>\n\n");
2447 /* Sometimes certain combinations of command options do not make
2448 sense on a particular target machine. You can define a macro
2449 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2450 defined, is executed once just after all the command options have
2453 Don't use this macro to turn on various extra optimizations for
2454 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2457 override_options (bool main_args_p)
2460 unsigned int ix86_arch_mask, ix86_tune_mask;
2465 /* Comes from final.c -- no real reason to change it. */
2466 #define MAX_CODE_ALIGN 16
2474 PTA_PREFETCH_SSE = 1 << 4,
2476 PTA_3DNOW_A = 1 << 6,
2480 PTA_POPCNT = 1 << 10,
2482 PTA_SSE4A = 1 << 12,
2483 PTA_NO_SAHF = 1 << 13,
2484 PTA_SSE4_1 = 1 << 14,
2485 PTA_SSE4_2 = 1 << 15,
2488 PTA_PCLMUL = 1 << 18,
2495 const char *const name; /* processor name or nickname. */
2496 const enum processor_type processor;
2497 const enum attr_cpu schedule;
2498 const unsigned /*enum pta_flags*/ flags;
2500 const processor_alias_table[] =
2502 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2503 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2504 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2505 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2506 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2507 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2508 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2509 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2510 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2511 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2512 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2513 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2514 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2516 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2518 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2519 PTA_MMX | PTA_SSE | PTA_SSE2},
2520 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2521 PTA_MMX |PTA_SSE | PTA_SSE2},
2522 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2523 PTA_MMX | PTA_SSE | PTA_SSE2},
2524 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2525 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2526 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2527 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2528 | PTA_CX16 | PTA_NO_SAHF},
2529 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2530 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2531 | PTA_SSSE3 | PTA_CX16},
2532 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2533 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2534 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2535 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2536 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2537 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2538 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2539 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2540 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2541 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2542 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2543 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2544 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2545 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2546 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2547 {"x86-64", PROCESSOR_K8, CPU_K8,
2548 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2549 {"k8", PROCESSOR_K8, CPU_K8,
2550 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2551 | PTA_SSE2 | PTA_NO_SAHF},
2552 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2553 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2554 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2555 {"opteron", PROCESSOR_K8, CPU_K8,
2556 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2557 | PTA_SSE2 | PTA_NO_SAHF},
2558 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2559 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2560 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2561 {"athlon64", PROCESSOR_K8, CPU_K8,
2562 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2563 | PTA_SSE2 | PTA_NO_SAHF},
2564 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2565 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2566 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2567 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2568 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2569 | PTA_SSE2 | PTA_NO_SAHF},
2570 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2571 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2572 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2573 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2574 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2575 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2576 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2577 0 /* flags are only used for -march switch. */ },
2578 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2579 PTA_64BIT /* flags are only used for -march switch. */ },
2582 int const pta_size = ARRAY_SIZE (processor_alias_table);
2584 /* Set up prefix/suffix so the error messages refer to either the command
2585 line argument, or the attribute(target). */
2594 prefix = "option(\"";
2599 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2600 SUBTARGET_OVERRIDE_OPTIONS;
2603 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2604 SUBSUBTARGET_OVERRIDE_OPTIONS;
2607 /* -fPIC is the default for x86_64. */
2608 if (TARGET_MACHO && TARGET_64BIT)
2611 /* Set the default values for switches whose default depends on TARGET_64BIT
2612 in case they weren't overwritten by command line options. */
2615 /* Mach-O doesn't support omitting the frame pointer for now. */
2616 if (flag_omit_frame_pointer == 2)
2617 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2618 if (flag_asynchronous_unwind_tables == 2)
2619 flag_asynchronous_unwind_tables = 1;
2620 if (flag_pcc_struct_return == 2)
2621 flag_pcc_struct_return = 0;
2625 if (flag_omit_frame_pointer == 2)
2626 flag_omit_frame_pointer = 0;
2627 if (flag_asynchronous_unwind_tables == 2)
2628 flag_asynchronous_unwind_tables = 0;
2629 if (flag_pcc_struct_return == 2)
2630 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2633 /* Need to check -mtune=generic first. */
2634 if (ix86_tune_string)
2636 if (!strcmp (ix86_tune_string, "generic")
2637 || !strcmp (ix86_tune_string, "i686")
2638 /* As special support for cross compilers we read -mtune=native
2639 as -mtune=generic. With native compilers we won't see the
2640 -mtune=native, as it was changed by the driver. */
2641 || !strcmp (ix86_tune_string, "native"))
2644 ix86_tune_string = "generic64";
2646 ix86_tune_string = "generic32";
2648 /* If this call is for setting the option attribute, allow the
2649 generic32/generic64 that was previously set. */
2650 else if (!main_args_p
2651 && (!strcmp (ix86_tune_string, "generic32")
2652 || !strcmp (ix86_tune_string, "generic64")))
2654 else if (!strncmp (ix86_tune_string, "generic", 7))
2655 error ("bad value (%s) for %stune=%s %s",
2656 ix86_tune_string, prefix, suffix, sw);
2660 if (ix86_arch_string)
2661 ix86_tune_string = ix86_arch_string;
2662 if (!ix86_tune_string)
2664 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2665 ix86_tune_defaulted = 1;
2668 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2669 need to use a sensible tune option. */
2670 if (!strcmp (ix86_tune_string, "generic")
2671 || !strcmp (ix86_tune_string, "x86-64")
2672 || !strcmp (ix86_tune_string, "i686"))
2675 ix86_tune_string = "generic64";
2677 ix86_tune_string = "generic32";
2680 if (ix86_stringop_string)
2682 if (!strcmp (ix86_stringop_string, "rep_byte"))
2683 stringop_alg = rep_prefix_1_byte;
2684 else if (!strcmp (ix86_stringop_string, "libcall"))
2685 stringop_alg = libcall;
2686 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2687 stringop_alg = rep_prefix_4_byte;
2688 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2690 /* rep; movq isn't available in 32-bit code. */
2691 stringop_alg = rep_prefix_8_byte;
2692 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2693 stringop_alg = loop_1_byte;
2694 else if (!strcmp (ix86_stringop_string, "loop"))
2695 stringop_alg = loop;
2696 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2697 stringop_alg = unrolled_loop;
2699 error ("bad value (%s) for %sstringop-strategy=%s %s",
2700 ix86_stringop_string, prefix, suffix, sw);
2702 if (!strcmp (ix86_tune_string, "x86-64"))
2703 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2704 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2705 prefix, suffix, prefix, suffix, prefix, suffix);
2707 if (!ix86_arch_string)
2708 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2710 ix86_arch_specified = 1;
2712 if (!strcmp (ix86_arch_string, "generic"))
2713 error ("generic CPU can be used only for %stune=%s %s",
2714 prefix, suffix, sw);
2715 if (!strncmp (ix86_arch_string, "generic", 7))
2716 error ("bad value (%s) for %sarch=%s %s",
2717 ix86_arch_string, prefix, suffix, sw);
2719 if (ix86_cmodel_string != 0)
2721 if (!strcmp (ix86_cmodel_string, "small"))
2722 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2723 else if (!strcmp (ix86_cmodel_string, "medium"))
2724 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2725 else if (!strcmp (ix86_cmodel_string, "large"))
2726 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2728 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2729 else if (!strcmp (ix86_cmodel_string, "32"))
2730 ix86_cmodel = CM_32;
2731 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2732 ix86_cmodel = CM_KERNEL;
2734 error ("bad value (%s) for %scmodel=%s %s",
2735 ix86_cmodel_string, prefix, suffix, sw);
2739 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2740 use of rip-relative addressing. This eliminates fixups that
2741 would otherwise be needed if this object is to be placed in a
2742 DLL, and is essentially just as efficient as direct addressing. */
2743 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2744 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2745 else if (TARGET_64BIT)
2746 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2748 ix86_cmodel = CM_32;
2750 if (ix86_asm_string != 0)
2753 && !strcmp (ix86_asm_string, "intel"))
2754 ix86_asm_dialect = ASM_INTEL;
2755 else if (!strcmp (ix86_asm_string, "att"))
2756 ix86_asm_dialect = ASM_ATT;
2758 error ("bad value (%s) for %sasm=%s %s",
2759 ix86_asm_string, prefix, suffix, sw);
2761 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2762 error ("code model %qs not supported in the %s bit mode",
2763 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2764 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2765 sorry ("%i-bit mode not compiled in",
2766 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2768 for (i = 0; i < pta_size; i++)
2769 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2771 ix86_schedule = processor_alias_table[i].schedule;
2772 ix86_arch = processor_alias_table[i].processor;
2773 /* Default cpu tuning to the architecture. */
2774 ix86_tune = ix86_arch;
2776 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2777 error ("CPU you selected does not support x86-64 "
2780 if (processor_alias_table[i].flags & PTA_MMX
2781 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2782 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2783 if (processor_alias_table[i].flags & PTA_3DNOW
2784 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2785 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2786 if (processor_alias_table[i].flags & PTA_3DNOW_A
2787 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2788 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2789 if (processor_alias_table[i].flags & PTA_SSE
2790 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2791 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2792 if (processor_alias_table[i].flags & PTA_SSE2
2793 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2794 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2795 if (processor_alias_table[i].flags & PTA_SSE3
2796 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2797 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2798 if (processor_alias_table[i].flags & PTA_SSSE3
2799 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2800 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2801 if (processor_alias_table[i].flags & PTA_SSE4_1
2802 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2803 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2804 if (processor_alias_table[i].flags & PTA_SSE4_2
2805 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2806 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2807 if (processor_alias_table[i].flags & PTA_AVX
2808 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2809 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2810 if (processor_alias_table[i].flags & PTA_FMA
2811 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2812 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2813 if (processor_alias_table[i].flags & PTA_SSE4A
2814 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2815 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2816 if (processor_alias_table[i].flags & PTA_SSE5
2817 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2818 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2819 if (processor_alias_table[i].flags & PTA_ABM
2820 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2821 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2822 if (processor_alias_table[i].flags & PTA_CX16
2823 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2824 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2825 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2826 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2827 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2828 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2829 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2830 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2831 if (processor_alias_table[i].flags & PTA_AES
2832 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2833 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2834 if (processor_alias_table[i].flags & PTA_PCLMUL
2835 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2836 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2837 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2838 x86_prefetch_sse = true;
2844 error ("bad value (%s) for %sarch=%s %s",
2845 ix86_arch_string, prefix, suffix, sw);
2847 ix86_arch_mask = 1u << ix86_arch;
2848 for (i = 0; i < X86_ARCH_LAST; ++i)
2849 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2851 for (i = 0; i < pta_size; i++)
2852 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2854 ix86_schedule = processor_alias_table[i].schedule;
2855 ix86_tune = processor_alias_table[i].processor;
2856 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2858 if (ix86_tune_defaulted)
2860 ix86_tune_string = "x86-64";
2861 for (i = 0; i < pta_size; i++)
2862 if (! strcmp (ix86_tune_string,
2863 processor_alias_table[i].name))
2865 ix86_schedule = processor_alias_table[i].schedule;
2866 ix86_tune = processor_alias_table[i].processor;
2869 error ("CPU you selected does not support x86-64 "
2872 /* Intel CPUs have always interpreted SSE prefetch instructions as
2873 NOPs; so, we can enable SSE prefetch instructions even when
2874 -mtune (rather than -march) points us to a processor that has them.
2875 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2876 higher processors. */
2878 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2879 x86_prefetch_sse = true;
2883 error ("bad value (%s) for %stune=%s %s",
2884 ix86_tune_string, prefix, suffix, sw);
2886 ix86_tune_mask = 1u << ix86_tune;
2887 for (i = 0; i < X86_TUNE_LAST; ++i)
2888 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
2891 ix86_cost = &ix86_size_cost;
2893 ix86_cost = processor_target_table[ix86_tune].cost;
2895 /* Arrange to set up i386_stack_locals for all functions. */
2896 init_machine_status = ix86_init_machine_status;
2898 /* Validate -mregparm= value. */
2899 if (ix86_regparm_string)
2902 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
2903 i = atoi (ix86_regparm_string);
2904 if (i < 0 || i > REGPARM_MAX)
2905 error ("%sregparm=%d%s is not between 0 and %d",
2906 prefix, i, suffix, REGPARM_MAX);
2911 ix86_regparm = REGPARM_MAX;
2913 /* If the user has provided any of the -malign-* options,
2914 warn and use that value only if -falign-* is not set.
2915 Remove this code in GCC 3.2 or later. */
2916 if (ix86_align_loops_string)
2918 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
2919 prefix, suffix, suffix);
2920 if (align_loops == 0)
2922 i = atoi (ix86_align_loops_string);
2923 if (i < 0 || i > MAX_CODE_ALIGN)
2924 error ("%salign-loops=%d%s is not between 0 and %d",
2925 prefix, i, suffix, MAX_CODE_ALIGN);
2927 align_loops = 1 << i;
2931 if (ix86_align_jumps_string)
2933 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
2934 prefix, suffix, suffix);
2935 if (align_jumps == 0)
2937 i = atoi (ix86_align_jumps_string);
2938 if (i < 0 || i > MAX_CODE_ALIGN)
2939 error ("%salign-loops=%d%s is not between 0 and %d",
2940 prefix, i, suffix, MAX_CODE_ALIGN);
2942 align_jumps = 1 << i;
2946 if (ix86_align_funcs_string)
2948 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
2949 prefix, suffix, suffix);
2950 if (align_functions == 0)
2952 i = atoi (ix86_align_funcs_string);
2953 if (i < 0 || i > MAX_CODE_ALIGN)
2954 error ("%salign-loops=%d%s is not between 0 and %d",
2955 prefix, i, suffix, MAX_CODE_ALIGN);
2957 align_functions = 1 << i;
2961 /* Default align_* from the processor table. */
2962 if (align_loops == 0)
2964 align_loops = processor_target_table[ix86_tune].align_loop;
2965 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2967 if (align_jumps == 0)
2969 align_jumps = processor_target_table[ix86_tune].align_jump;
2970 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2972 if (align_functions == 0)
2974 align_functions = processor_target_table[ix86_tune].align_func;
2977 /* Validate -mbranch-cost= value, or provide default. */
2978 ix86_branch_cost = ix86_cost->branch_cost;
2979 if (ix86_branch_cost_string)
2981 i = atoi (ix86_branch_cost_string);
2983 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
2985 ix86_branch_cost = i;
2987 if (ix86_section_threshold_string)
2989 i = atoi (ix86_section_threshold_string);
2991 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
2993 ix86_section_threshold = i;
2996 if (ix86_tls_dialect_string)
2998 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2999 ix86_tls_dialect = TLS_DIALECT_GNU;
3000 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3001 ix86_tls_dialect = TLS_DIALECT_GNU2;
3002 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3003 ix86_tls_dialect = TLS_DIALECT_SUN;
3005 error ("bad value (%s) for %stls-dialect=%s %s",
3006 ix86_tls_dialect_string, prefix, suffix, sw);
3009 if (ix87_precision_string)
3011 i = atoi (ix87_precision_string);
3012 if (i != 32 && i != 64 && i != 80)
3013 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3018 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3020 /* Enable by default the SSE and MMX builtins. Do allow the user to
3021 explicitly disable any of these. In particular, disabling SSE and
3022 MMX for kernel code is extremely useful. */
3023 if (!ix86_arch_specified)
3025 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3026 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3029 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3033 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3035 if (!ix86_arch_specified)
3037 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3039 /* i386 ABI does not specify red zone. It still makes sense to use it
3040 when programmer takes care to stack from being destroyed. */
3041 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3042 target_flags |= MASK_NO_RED_ZONE;
3045 /* Keep nonleaf frame pointers. */
3046 if (flag_omit_frame_pointer)
3047 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3048 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3049 flag_omit_frame_pointer = 1;
3051 /* If we're doing fast math, we don't care about comparison order
3052 wrt NaNs. This lets us use a shorter comparison sequence. */
3053 if (flag_finite_math_only)
3054 target_flags &= ~MASK_IEEE_FP;
3056 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3057 since the insns won't need emulation. */
3058 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3059 target_flags &= ~MASK_NO_FANCY_MATH_387;
3061 /* Likewise, if the target doesn't have a 387, or we've specified
3062 software floating point, don't use 387 inline intrinsics. */
3064 target_flags |= MASK_NO_FANCY_MATH_387;
3066 /* Turn on MMX builtins for -msse. */
3069 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3070 x86_prefetch_sse = true;
3073 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3074 if (TARGET_SSE4_2 || TARGET_ABM)
3075 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3077 /* Validate -mpreferred-stack-boundary= value or default it to
3078 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3079 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3080 if (ix86_preferred_stack_boundary_string)
3082 i = atoi (ix86_preferred_stack_boundary_string);
3083 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3084 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3085 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3087 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3090 /* Set the default value for -mstackrealign. */
3091 if (ix86_force_align_arg_pointer == -1)
3092 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3094 /* Validate -mincoming-stack-boundary= value or default it to
3095 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3096 if (ix86_force_align_arg_pointer)
3097 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3099 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3100 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3101 if (ix86_incoming_stack_boundary_string)
3103 i = atoi (ix86_incoming_stack_boundary_string);
3104 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3105 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3106 i, TARGET_64BIT ? 4 : 2);
3109 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3110 ix86_incoming_stack_boundary
3111 = ix86_user_incoming_stack_boundary;
3115 /* Accept -msseregparm only if at least SSE support is enabled. */
3116 if (TARGET_SSEREGPARM
3118 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3120 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3121 if (ix86_fpmath_string != 0)
3123 if (! strcmp (ix86_fpmath_string, "387"))
3124 ix86_fpmath = FPMATH_387;
3125 else if (! strcmp (ix86_fpmath_string, "sse"))
3129 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3130 ix86_fpmath = FPMATH_387;
3133 ix86_fpmath = FPMATH_SSE;
3135 else if (! strcmp (ix86_fpmath_string, "387,sse")
3136 || ! strcmp (ix86_fpmath_string, "387+sse")
3137 || ! strcmp (ix86_fpmath_string, "sse,387")
3138 || ! strcmp (ix86_fpmath_string, "sse+387")
3139 || ! strcmp (ix86_fpmath_string, "both"))
3143 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3144 ix86_fpmath = FPMATH_387;
3146 else if (!TARGET_80387)
3148 warning (0, "387 instruction set disabled, using SSE arithmetics");
3149 ix86_fpmath = FPMATH_SSE;
3152 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3155 error ("bad value (%s) for %sfpmath=%s %s",
3156 ix86_fpmath_string, prefix, suffix, sw);
3159 /* If the i387 is disabled, then do not return values in it. */
3161 target_flags &= ~MASK_FLOAT_RETURNS;
3163 /* Use external vectorized library in vectorizing intrinsics. */
3164 if (ix86_veclibabi_string)
3166 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3167 ix86_veclib_handler = ix86_veclibabi_svml;
3168 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3169 ix86_veclib_handler = ix86_veclibabi_acml;
3171 error ("unknown vectorization library ABI type (%s) for "
3172 "%sveclibabi=%s %s", ix86_veclibabi_string,
3173 prefix, suffix, sw);
3176 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3177 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3179 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3181 /* ??? Unwind info is not correct around the CFG unless either a frame
3182 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3183 unwind info generation to be aware of the CFG and propagating states
3185 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3186 || flag_exceptions || flag_non_call_exceptions)
3187 && flag_omit_frame_pointer
3188 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3190 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3191 warning (0, "unwind tables currently require either a frame pointer "
3192 "or %saccumulate-outgoing-args%s for correctness",
3194 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3197 /* If stack probes are required, the space used for large function
3198 arguments on the stack must also be probed, so enable
3199 -maccumulate-outgoing-args so this happens in the prologue. */
3200 if (TARGET_STACK_PROBE
3201 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3203 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3204 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3205 "for correctness", prefix, suffix);
3206 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3209 /* For sane SSE instruction set generation we need fcomi instruction.
3210 It is safe to enable all CMOVE instructions. */
3214 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3217 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3218 p = strchr (internal_label_prefix, 'X');
3219 internal_label_prefix_len = p - internal_label_prefix;
3223 /* When scheduling description is not available, disable scheduler pass
3224 so it won't slow down the compilation and make x87 code slower. */
3225 if (!TARGET_SCHEDULE)
3226 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3228 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3229 set_param_value ("simultaneous-prefetches",
3230 ix86_cost->simultaneous_prefetches);
3231 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3232 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3233 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3234 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3235 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3236 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3238 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3239 can be optimized to ap = __builtin_next_arg (0). */
3241 targetm.expand_builtin_va_start = NULL;
3245 ix86_gen_leave = gen_leave_rex64;
3246 ix86_gen_pop1 = gen_popdi1;
3247 ix86_gen_add3 = gen_adddi3;
3248 ix86_gen_sub3 = gen_subdi3;
3249 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3250 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3251 ix86_gen_monitor = gen_sse3_monitor64;
3252 ix86_gen_andsp = gen_anddi3;
3256 ix86_gen_leave = gen_leave;
3257 ix86_gen_pop1 = gen_popsi1;
3258 ix86_gen_add3 = gen_addsi3;
3259 ix86_gen_sub3 = gen_subsi3;
3260 ix86_gen_sub3_carry = gen_subsi3_carry;
3261 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3262 ix86_gen_monitor = gen_sse3_monitor;
3263 ix86_gen_andsp = gen_andsi3;
3267 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3269 target_flags |= MASK_CLD & ~target_flags_explicit;
3272 /* Save the initial options in case the user does function specific options */
3274 target_option_default_node = target_option_current_node
3275 = build_target_option_node ();
3278 /* Save the current options */
3281 ix86_function_specific_save (struct cl_target_option *ptr)
3283 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3284 gcc_assert (IN_RANGE (ix86_schedule, 0, 255));
3285 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3286 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3287 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3289 ptr->arch = ix86_arch;
3290 ptr->schedule = ix86_schedule;
3291 ptr->tune = ix86_tune;
3292 ptr->fpmath = ix86_fpmath;
3293 ptr->branch_cost = ix86_branch_cost;
3294 ptr->tune_defaulted = ix86_tune_defaulted;
3295 ptr->arch_specified = ix86_arch_specified;
3296 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3297 ptr->target_flags_explicit = target_flags_explicit;
3300 /* Restore the current options */
3303 ix86_function_specific_restore (struct cl_target_option *ptr)
3305 enum processor_type old_tune = ix86_tune;
3306 enum processor_type old_arch = ix86_arch;
3307 unsigned int ix86_arch_mask, ix86_tune_mask;
3310 ix86_arch = ptr->arch;
3311 ix86_schedule = ptr->schedule;
3312 ix86_tune = ptr->tune;
3313 ix86_fpmath = ptr->fpmath;
3314 ix86_branch_cost = ptr->branch_cost;
3315 ix86_tune_defaulted = ptr->tune_defaulted;
3316 ix86_arch_specified = ptr->arch_specified;
3317 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3318 target_flags_explicit = ptr->target_flags_explicit;
3320 /* Recreate the arch feature tests if the arch changed */
3321 if (old_arch != ix86_arch)
3323 ix86_arch_mask = 1u << ix86_arch;
3324 for (i = 0; i < X86_ARCH_LAST; ++i)
3325 ix86_arch_features[i]
3326 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3329 /* Recreate the tune optimization tests */
3330 if (old_tune != ix86_tune)
3332 ix86_tune_mask = 1u << ix86_tune;
3333 for (i = 0; i < X86_TUNE_LAST; ++i)
3334 ix86_tune_features[i]
3335 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3339 /* Print the current options */
3342 ix86_function_specific_print (FILE *file, int indent,
3343 struct cl_target_option *ptr)
3346 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3347 NULL, NULL, NULL, false);
3349 fprintf (file, "%*sarch = %d (%s)\n",
3352 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3353 ? cpu_names[ptr->arch]
3356 fprintf (file, "%*stune = %d (%s)\n",
3359 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3360 ? cpu_names[ptr->tune]
3363 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3364 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3365 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3366 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3370 fprintf (file, "%*s%s\n", indent, "", target_string);
3371 free (target_string);
3376 /* Inner function to process the attribute((target(...))), take an argument and
3377 set the current options from the argument. If we have a list, recursively go
3381 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3386 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3387 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3388 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3389 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3404 enum ix86_opt_type type;
3409 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3410 IX86_ATTR_ISA ("abm", OPT_mabm),
3411 IX86_ATTR_ISA ("aes", OPT_maes),
3412 IX86_ATTR_ISA ("avx", OPT_mavx),
3413 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3414 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3415 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3416 IX86_ATTR_ISA ("sse", OPT_msse),
3417 IX86_ATTR_ISA ("sse2", OPT_msse2),
3418 IX86_ATTR_ISA ("sse3", OPT_msse3),
3419 IX86_ATTR_ISA ("sse4", OPT_msse4),
3420 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3421 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3422 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3423 IX86_ATTR_ISA ("sse5", OPT_msse5),
3424 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3426 /* string options */
3427 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3428 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3429 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3432 IX86_ATTR_YES ("cld",
3436 IX86_ATTR_NO ("fancy-math-387",
3437 OPT_mfancy_math_387,
3438 MASK_NO_FANCY_MATH_387),
3440 IX86_ATTR_NO ("fused-madd",
3442 MASK_NO_FUSED_MADD),
3444 IX86_ATTR_YES ("ieee-fp",
3448 IX86_ATTR_YES ("inline-all-stringops",
3449 OPT_minline_all_stringops,
3450 MASK_INLINE_ALL_STRINGOPS),
3452 IX86_ATTR_YES ("inline-stringops-dynamically",
3453 OPT_minline_stringops_dynamically,
3454 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3456 IX86_ATTR_NO ("align-stringops",
3457 OPT_mno_align_stringops,
3458 MASK_NO_ALIGN_STRINGOPS),
3460 IX86_ATTR_YES ("recip",
3466 /* If this is a list, recurse to get the options. */
3467 if (TREE_CODE (args) == TREE_LIST)
3471 for (; args; args = TREE_CHAIN (args))
3472 if (TREE_VALUE (args)
3473 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3479 else if (TREE_CODE (args) != STRING_CST)
3482 /* Handle multiple arguments separated by commas. */
3483 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3485 while (next_optstr && *next_optstr != '\0')
3487 char *p = next_optstr;
3489 char *comma = strchr (next_optstr, ',');
3490 const char *opt_string;
3491 size_t len, opt_len;
3496 enum ix86_opt_type type = ix86_opt_unknown;
3502 len = comma - next_optstr;
3503 next_optstr = comma + 1;
3511 /* Recognize no-xxx. */
3512 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3521 /* Find the option. */
3524 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3526 type = attrs[i].type;
3527 opt_len = attrs[i].len;
3528 if (ch == attrs[i].string[0]
3529 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3530 && memcmp (p, attrs[i].string, opt_len) == 0)
3533 mask = attrs[i].mask;
3534 opt_string = attrs[i].string;
3539 /* Process the option. */
3542 error ("attribute(target(\"%s\")) is unknown", orig_p);
3546 else if (type == ix86_opt_isa)
3547 ix86_handle_option (opt, p, opt_set_p);
3549 else if (type == ix86_opt_yes || type == ix86_opt_no)
3551 if (type == ix86_opt_no)
3552 opt_set_p = !opt_set_p;
3555 target_flags |= mask;
3557 target_flags &= ~mask;
3560 else if (type == ix86_opt_str)
3564 error ("option(\"%s\") was already specified", opt_string);
3568 p_strings[opt] = xstrdup (p + opt_len);
3578 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3581 ix86_valid_target_attribute_tree (tree args)
3583 const char *orig_arch_string = ix86_arch_string;
3584 const char *orig_tune_string = ix86_tune_string;
3585 const char *orig_fpmath_string = ix86_fpmath_string;
3586 int orig_tune_defaulted = ix86_tune_defaulted;
3587 int orig_arch_specified = ix86_arch_specified;
3588 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3591 struct cl_target_option *def
3592 = TREE_TARGET_OPTION (target_option_default_node);
3594 /* Process each of the options on the chain. */
3595 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3598 /* If the changed options are different from the default, rerun override_options,
3599 and then save the options away. The string options are are attribute options,
3600 and will be undone when we copy the save structure. */
3601 if (ix86_isa_flags != def->ix86_isa_flags
3602 || target_flags != def->target_flags
3603 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3604 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3605 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3607 /* If we are using the default tune= or arch=, undo the string assigned,
3608 and use the default. */
3609 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3610 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3611 else if (!orig_arch_specified)
3612 ix86_arch_string = NULL;
3614 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3615 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3616 else if (orig_tune_defaulted)
3617 ix86_tune_string = NULL;
3619 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3620 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3621 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3622 else if (!TARGET_64BIT && TARGET_SSE)
3623 ix86_fpmath_string = "sse,387";
3625 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3626 override_options (false);
3628 /* Add any builtin functions with the new isa if any. */
3629 ix86_add_new_builtins (ix86_isa_flags);
3631 /* Save the current options unless we are validating options for
3633 t = build_target_option_node ();
3635 ix86_arch_string = orig_arch_string;
3636 ix86_tune_string = orig_tune_string;
3637 ix86_fpmath_string = orig_fpmath_string;
3639 /* Free up memory allocated to hold the strings */
3640 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3641 if (option_strings[i])
3642 free (option_strings[i]);
3648 /* Hook to validate attribute((target("string"))). */
3651 ix86_valid_target_attribute_p (tree fndecl,
3652 tree ARG_UNUSED (name),
3654 int ARG_UNUSED (flags))
3656 struct cl_target_option cur_target;
3658 tree old_optimize = build_optimization_node ();
3659 tree new_target, new_optimize;
3660 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3662 /* If the function changed the optimization levels as well as setting target
3663 options, start with the optimizations specified. */
3664 if (func_optimize && func_optimize != old_optimize)
3665 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3667 /* The target attributes may also change some optimization flags, so update
3668 the optimization options if necessary. */
3669 cl_target_option_save (&cur_target);
3670 new_target = ix86_valid_target_attribute_tree (args);
3671 new_optimize = build_optimization_node ();
3678 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3680 if (old_optimize != new_optimize)
3681 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3684 cl_target_option_restore (&cur_target);
3686 if (old_optimize != new_optimize)
3687 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3693 /* Hook to determine if one function can safely inline another. */
3696 ix86_can_inline_p (tree caller, tree callee)
3699 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3700 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3702 /* If callee has no option attributes, then it is ok to inline. */
3706 /* If caller has no option attributes, but callee does then it is not ok to
3708 else if (!caller_tree)
3713 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3714 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3716 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3717 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3719 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3720 != callee_opts->ix86_isa_flags)
3723 /* See if we have the same non-isa options. */
3724 else if (caller_opts->target_flags != callee_opts->target_flags)
3727 /* See if arch, tune, etc. are the same. */
3728 else if (caller_opts->arch != callee_opts->arch)
3731 else if (caller_opts->tune != callee_opts->tune)
3734 else if (caller_opts->fpmath != callee_opts->fpmath)
3737 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3748 /* Remember the last target of ix86_set_current_function. */
3749 static GTY(()) tree ix86_previous_fndecl;
3751 /* Establish appropriate back-end context for processing the function
3752 FNDECL. The argument might be NULL to indicate processing at top
3753 level, outside of any function scope. */
3755 ix86_set_current_function (tree fndecl)
3757 /* Only change the context if the function changes. This hook is called
3758 several times in the course of compiling a function, and we don't want to
3759 slow things down too much or call target_reinit when it isn't safe. */
3760 if (fndecl && fndecl != ix86_previous_fndecl)
3762 tree old_tree = (ix86_previous_fndecl
3763 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3766 tree new_tree = (fndecl
3767 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3770 ix86_previous_fndecl = fndecl;
3771 if (old_tree == new_tree)
3776 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3782 struct cl_target_option *def
3783 = TREE_TARGET_OPTION (target_option_current_node);
3785 cl_target_option_restore (def);
3792 /* Return true if this goes in large data/bss. */
3795 ix86_in_large_data_p (tree exp)
3797 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3800 /* Functions are never large data. */
3801 if (TREE_CODE (exp) == FUNCTION_DECL)
3804 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3806 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3807 if (strcmp (section, ".ldata") == 0
3808 || strcmp (section, ".lbss") == 0)
3814 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3816 /* If this is an incomplete type with size 0, then we can't put it
3817 in data because it might be too big when completed. */
3818 if (!size || size > ix86_section_threshold)
3825 /* Switch to the appropriate section for output of DECL.
3826 DECL is either a `VAR_DECL' node or a constant of some sort.
3827 RELOC indicates whether forming the initial value of DECL requires
3828 link-time relocations. */
3830 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3834 x86_64_elf_select_section (tree decl, int reloc,
3835 unsigned HOST_WIDE_INT align)
3837 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3838 && ix86_in_large_data_p (decl))
3840 const char *sname = NULL;
3841 unsigned int flags = SECTION_WRITE;
3842 switch (categorize_decl_for_section (decl, reloc))
3847 case SECCAT_DATA_REL:
3848 sname = ".ldata.rel";
3850 case SECCAT_DATA_REL_LOCAL:
3851 sname = ".ldata.rel.local";
3853 case SECCAT_DATA_REL_RO:
3854 sname = ".ldata.rel.ro";
3856 case SECCAT_DATA_REL_RO_LOCAL:
3857 sname = ".ldata.rel.ro.local";
3861 flags |= SECTION_BSS;
3864 case SECCAT_RODATA_MERGE_STR:
3865 case SECCAT_RODATA_MERGE_STR_INIT:
3866 case SECCAT_RODATA_MERGE_CONST:
3870 case SECCAT_SRODATA:
3877 /* We don't split these for medium model. Place them into
3878 default sections and hope for best. */
3880 case SECCAT_EMUTLS_VAR:
3881 case SECCAT_EMUTLS_TMPL:
3886 /* We might get called with string constants, but get_named_section
3887 doesn't like them as they are not DECLs. Also, we need to set
3888 flags in that case. */
3890 return get_section (sname, flags, NULL);
3891 return get_named_section (decl, sname, reloc);
3894 return default_elf_select_section (decl, reloc, align);
3897 /* Build up a unique section name, expressed as a
3898 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3899 RELOC indicates whether the initial value of EXP requires
3900 link-time relocations. */
3902 static void ATTRIBUTE_UNUSED
3903 x86_64_elf_unique_section (tree decl, int reloc)
3905 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3906 && ix86_in_large_data_p (decl))
3908 const char *prefix = NULL;
3909 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3910 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3912 switch (categorize_decl_for_section (decl, reloc))
3915 case SECCAT_DATA_REL:
3916 case SECCAT_DATA_REL_LOCAL:
3917 case SECCAT_DATA_REL_RO:
3918 case SECCAT_DATA_REL_RO_LOCAL:
3919 prefix = one_only ? ".ld" : ".ldata";
3922 prefix = one_only ? ".lb" : ".lbss";
3925 case SECCAT_RODATA_MERGE_STR:
3926 case SECCAT_RODATA_MERGE_STR_INIT:
3927 case SECCAT_RODATA_MERGE_CONST:
3928 prefix = one_only ? ".lr" : ".lrodata";
3930 case SECCAT_SRODATA:
3937 /* We don't split these for medium model. Place them into
3938 default sections and hope for best. */
3940 case SECCAT_EMUTLS_VAR:
3941 prefix = targetm.emutls.var_section;
3943 case SECCAT_EMUTLS_TMPL:
3944 prefix = targetm.emutls.tmpl_section;
3949 const char *name, *linkonce;
3952 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3953 name = targetm.strip_name_encoding (name);
3955 /* If we're using one_only, then there needs to be a .gnu.linkonce
3956 prefix to the section name. */
3957 linkonce = one_only ? ".gnu.linkonce" : "";
3959 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
3961 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
3965 default_unique_section (decl, reloc);
3968 #ifdef COMMON_ASM_OP
3969 /* This says how to output assembler code to declare an
3970 uninitialized external linkage data object.
3972 For medium model x86-64 we need to use .largecomm opcode for
3975 x86_elf_aligned_common (FILE *file,
3976 const char *name, unsigned HOST_WIDE_INT size,
3979 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3980 && size > (unsigned int)ix86_section_threshold)
3981 fprintf (file, ".largecomm\t");
3983 fprintf (file, "%s", COMMON_ASM_OP);
3984 assemble_name (file, name);
3985 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
3986 size, align / BITS_PER_UNIT);
3990 /* Utility function for targets to use in implementing
3991 ASM_OUTPUT_ALIGNED_BSS. */
3994 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
3995 const char *name, unsigned HOST_WIDE_INT size,
3998 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3999 && size > (unsigned int)ix86_section_threshold)
4000 switch_to_section (get_named_section (decl, ".lbss", 0));
4002 switch_to_section (bss_section);
4003 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4004 #ifdef ASM_DECLARE_OBJECT_NAME
4005 last_assemble_variable_decl = decl;
4006 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4008 /* Standard thing is just output label for the object. */
4009 ASM_OUTPUT_LABEL (file, name);
4010 #endif /* ASM_DECLARE_OBJECT_NAME */
4011 ASM_OUTPUT_SKIP (file, size ? size : 1);
4015 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4017 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4018 make the problem with not enough registers even worse. */
4019 #ifdef INSN_SCHEDULING
4021 flag_schedule_insns = 0;
4025 /* The Darwin libraries never set errno, so we might as well
4026 avoid calling them when that's the only reason we would. */
4027 flag_errno_math = 0;
4029 /* The default values of these switches depend on the TARGET_64BIT
4030 that is not known at this moment. Mark these values with 2 and
4031 let user the to override these. In case there is no command line option
4032 specifying them, we will set the defaults in override_options. */
4034 flag_omit_frame_pointer = 2;
4035 flag_pcc_struct_return = 2;
4036 flag_asynchronous_unwind_tables = 2;
4037 flag_vect_cost_model = 1;
4038 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4039 SUBTARGET_OPTIMIZATION_OPTIONS;
4043 /* Decide whether we can make a sibling call to a function. DECL is the
4044 declaration of the function being targeted by the call and EXP is the
4045 CALL_EXPR representing the call. */
4048 ix86_function_ok_for_sibcall (tree decl, tree exp)
4053 /* If we are generating position-independent code, we cannot sibcall
4054 optimize any indirect call, or a direct call to a global function,
4055 as the PLT requires %ebx be live. */
4056 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4063 func = TREE_TYPE (CALL_EXPR_FN (exp));
4064 if (POINTER_TYPE_P (func))
4065 func = TREE_TYPE (func);
4068 /* Check that the return value locations are the same. Like
4069 if we are returning floats on the 80387 register stack, we cannot
4070 make a sibcall from a function that doesn't return a float to a
4071 function that does or, conversely, from a function that does return
4072 a float to a function that doesn't; the necessary stack adjustment
4073 would not be executed. This is also the place we notice
4074 differences in the return value ABI. Note that it is ok for one
4075 of the functions to have void return type as long as the return
4076 value of the other is passed in a register. */
4077 a = ix86_function_value (TREE_TYPE (exp), func, false);
4078 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4080 if (STACK_REG_P (a) || STACK_REG_P (b))
4082 if (!rtx_equal_p (a, b))
4085 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4087 else if (!rtx_equal_p (a, b))
4090 /* If this call is indirect, we'll need to be able to use a call-clobbered
4091 register for the address of the target function. Make sure that all
4092 such registers are not used for passing parameters. */
4093 if (!decl && !TARGET_64BIT)
4097 /* We're looking at the CALL_EXPR, we need the type of the function. */
4098 type = CALL_EXPR_FN (exp); /* pointer expression */
4099 type = TREE_TYPE (type); /* pointer type */
4100 type = TREE_TYPE (type); /* function type */
4102 if (ix86_function_regparm (type, NULL) >= 3)
4104 /* ??? Need to count the actual number of registers to be used,
4105 not the possible number of registers. Fix later. */
4110 /* Dllimport'd functions are also called indirectly. */
4111 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
4113 && decl && DECL_DLLIMPORT_P (decl)
4114 && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
4117 /* If we need to align the outgoing stack, then sibcalling would
4118 unalign the stack, which may break the called function. */
4119 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4122 /* Otherwise okay. That also includes certain types of indirect calls. */
4126 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4127 calling convention attributes;
4128 arguments as in struct attribute_spec.handler. */
4131 ix86_handle_cconv_attribute (tree *node, tree name,
4133 int flags ATTRIBUTE_UNUSED,
4136 if (TREE_CODE (*node) != FUNCTION_TYPE
4137 && TREE_CODE (*node) != METHOD_TYPE
4138 && TREE_CODE (*node) != FIELD_DECL
4139 && TREE_CODE (*node) != TYPE_DECL)
4141 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4142 IDENTIFIER_POINTER (name));
4143 *no_add_attrs = true;
4147 /* Can combine regparm with all attributes but fastcall. */
4148 if (is_attribute_p ("regparm", name))
4152 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4154 error ("fastcall and regparm attributes are not compatible");
4157 cst = TREE_VALUE (args);
4158 if (TREE_CODE (cst) != INTEGER_CST)
4160 warning (OPT_Wattributes,
4161 "%qs attribute requires an integer constant argument",
4162 IDENTIFIER_POINTER (name));
4163 *no_add_attrs = true;
4165 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4167 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
4168 IDENTIFIER_POINTER (name), REGPARM_MAX);
4169 *no_add_attrs = true;
4177 /* Do not warn when emulating the MS ABI. */
4178 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4179 warning (OPT_Wattributes, "%qs attribute ignored",
4180 IDENTIFIER_POINTER (name));
4181 *no_add_attrs = true;
4185 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4186 if (is_attribute_p ("fastcall", name))
4188 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4190 error ("fastcall and cdecl attributes are not compatible");
4192 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4194 error ("fastcall and stdcall attributes are not compatible");
4196 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4198 error ("fastcall and regparm attributes are not compatible");
4202 /* Can combine stdcall with fastcall (redundant), regparm and
4204 else if (is_attribute_p ("stdcall", name))
4206 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4208 error ("stdcall and cdecl attributes are not compatible");
4210 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4212 error ("stdcall and fastcall attributes are not compatible");
4216 /* Can combine cdecl with regparm and sseregparm. */
4217 else if (is_attribute_p ("cdecl", name))
4219 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4221 error ("stdcall and cdecl attributes are not compatible");
4223 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4225 error ("fastcall and cdecl attributes are not compatible");
4229 /* Can combine sseregparm with all attributes. */
4234 /* Return 0 if the attributes for two types are incompatible, 1 if they
4235 are compatible, and 2 if they are nearly compatible (which causes a
4236 warning to be generated). */
4239 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4241 /* Check for mismatch of non-default calling convention. */
4242 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4244 if (TREE_CODE (type1) != FUNCTION_TYPE
4245 && TREE_CODE (type1) != METHOD_TYPE)
4248 /* Check for mismatched fastcall/regparm types. */
4249 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4250 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4251 || (ix86_function_regparm (type1, NULL)
4252 != ix86_function_regparm (type2, NULL)))
4255 /* Check for mismatched sseregparm types. */
4256 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4257 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4260 /* Check for mismatched return types (cdecl vs stdcall). */
4261 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4262 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4268 /* Return the regparm value for a function with the indicated TYPE and DECL.
4269 DECL may be NULL when calling function indirectly
4270 or considering a libcall. */
4273 ix86_function_regparm (const_tree type, const_tree decl)
4278 static bool error_issued;
4281 return (ix86_function_type_abi (type) == SYSV_ABI
4282 ? X86_64_REGPARM_MAX : X64_REGPARM_MAX);
4284 regparm = ix86_regparm;
4285 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4289 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4291 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4293 /* We can't use regparm(3) for nested functions because
4294 these pass static chain pointer in %ecx register. */
4295 if (!error_issued && regparm == 3
4296 && decl_function_context (decl)
4297 && !DECL_NO_STATIC_CHAIN (decl))
4299 error ("nested functions are limited to 2 register parameters");
4300 error_issued = true;
4308 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4311 /* Use register calling convention for local functions when possible. */
4312 if (decl && TREE_CODE (decl) == FUNCTION_DECL
4315 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4316 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4319 int local_regparm, globals = 0, regno;
4322 /* Make sure no regparm register is taken by a
4323 fixed register variable. */
4324 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4325 if (fixed_regs[local_regparm])
4328 /* We can't use regparm(3) for nested functions as these use
4329 static chain pointer in third argument. */
4330 if (local_regparm == 3
4331 && decl_function_context (decl)
4332 && !DECL_NO_STATIC_CHAIN (decl))
4335 /* If the function realigns its stackpointer, the prologue will
4336 clobber %ecx. If we've already generated code for the callee,
4337 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4338 scanning the attributes for the self-realigning property. */
4339 f = DECL_STRUCT_FUNCTION (decl);
4340 /* Since current internal arg pointer won't conflict with
4341 parameter passing regs, so no need to change stack
4342 realignment and adjust regparm number.
4344 Each fixed register usage increases register pressure,
4345 so less registers should be used for argument passing.
4346 This functionality can be overriden by an explicit
4348 for (regno = 0; regno <= DI_REG; regno++)
4349 if (fixed_regs[regno])
4353 = globals < local_regparm ? local_regparm - globals : 0;
4355 if (local_regparm > regparm)
4356 regparm = local_regparm;
4363 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4364 DFmode (2) arguments in SSE registers for a function with the
4365 indicated TYPE and DECL. DECL may be NULL when calling function
4366 indirectly or considering a libcall. Otherwise return 0. */
4369 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4371 gcc_assert (!TARGET_64BIT);
4373 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4374 by the sseregparm attribute. */
4375 if (TARGET_SSEREGPARM
4376 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4383 error ("Calling %qD with attribute sseregparm without "
4384 "SSE/SSE2 enabled", decl);
4386 error ("Calling %qT with attribute sseregparm without "
4387 "SSE/SSE2 enabled", type);
4395 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4396 (and DFmode for SSE2) arguments in SSE registers. */
4397 if (decl && TARGET_SSE_MATH && !profile_flag)
4399 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4400 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4402 return TARGET_SSE2 ? 2 : 1;
4408 /* Return true if EAX is live at the start of the function. Used by
4409 ix86_expand_prologue to determine if we need special help before
4410 calling allocate_stack_worker. */
4413 ix86_eax_live_at_start_p (void)
4415 /* Cheat. Don't bother working forward from ix86_function_regparm
4416 to the function type to whether an actual argument is located in
4417 eax. Instead just look at cfg info, which is still close enough
4418 to correct at this point. This gives false positives for broken
4419 functions that might use uninitialized data that happens to be
4420 allocated in eax, but who cares? */
4421 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4424 /* Value is the number of bytes of arguments automatically
4425 popped when returning from a subroutine call.
4426 FUNDECL is the declaration node of the function (as a tree),
4427 FUNTYPE is the data type of the function (as a tree),
4428 or for a library call it is an identifier node for the subroutine name.
4429 SIZE is the number of bytes of arguments passed on the stack.
4431 On the 80386, the RTD insn may be used to pop them if the number
4432 of args is fixed, but if the number is variable then the caller
4433 must pop them all. RTD can't be used for library calls now
4434 because the library is compiled with the Unix compiler.
4435 Use of RTD is a selectable option, since it is incompatible with
4436 standard Unix calling sequences. If the option is not selected,
4437 the caller must always pop the args.
4439 The attribute stdcall is equivalent to RTD on a per module basis. */
4442 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4446 /* None of the 64-bit ABIs pop arguments. */
4450 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4452 /* Cdecl functions override -mrtd, and never pop the stack. */
4453 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4455 /* Stdcall and fastcall functions will pop the stack if not
4457 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4458 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4461 if (rtd && ! stdarg_p (funtype))
4465 /* Lose any fake structure return argument if it is passed on the stack. */
4466 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4467 && !KEEP_AGGREGATE_RETURN_POINTER)
4469 int nregs = ix86_function_regparm (funtype, fundecl);
4471 return GET_MODE_SIZE (Pmode);
4477 /* Argument support functions. */
4479 /* Return true when register may be used to pass function parameters. */
4481 ix86_function_arg_regno_p (int regno)
4484 const int *parm_regs;
4489 return (regno < REGPARM_MAX
4490 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4492 return (regno < REGPARM_MAX
4493 || (TARGET_MMX && MMX_REGNO_P (regno)
4494 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4495 || (TARGET_SSE && SSE_REGNO_P (regno)
4496 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4501 if (SSE_REGNO_P (regno) && TARGET_SSE)
4506 if (TARGET_SSE && SSE_REGNO_P (regno)
4507 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4511 /* TODO: The function should depend on current function ABI but
4512 builtins.c would need updating then. Therefore we use the
4515 /* RAX is used as hidden argument to va_arg functions. */
4516 if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
4519 if (DEFAULT_ABI == MS_ABI)
4520 parm_regs = x86_64_ms_abi_int_parameter_registers;
4522 parm_regs = x86_64_int_parameter_registers;
4523 for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
4524 : X86_64_REGPARM_MAX); i++)
4525 if (regno == parm_regs[i])
4530 /* Return if we do not know how to pass TYPE solely in registers. */
4533 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4535 if (must_pass_in_stack_var_size_or_pad (mode, type))
4538 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4539 The layout_type routine is crafty and tries to trick us into passing
4540 currently unsupported vector types on the stack by using TImode. */
4541 return (!TARGET_64BIT && mode == TImode
4542 && type && TREE_CODE (type) != VECTOR_TYPE);
4545 /* It returns the size, in bytes, of the area reserved for arguments passed
4546 in registers for the function represented by fndecl dependent to the used
4549 ix86_reg_parm_stack_space (const_tree fndecl)
4551 int call_abi = SYSV_ABI;
4552 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4553 call_abi = ix86_function_abi (fndecl);
4555 call_abi = ix86_function_type_abi (fndecl);
4556 if (call_abi == MS_ABI)
4561 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4564 ix86_function_type_abi (const_tree fntype)
4566 if (TARGET_64BIT && fntype != NULL)
4569 if (DEFAULT_ABI == SYSV_ABI)
4570 abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
4572 abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
4580 ix86_function_abi (const_tree fndecl)
4584 return ix86_function_type_abi (TREE_TYPE (fndecl));
4587 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4590 ix86_cfun_abi (void)
4592 if (! cfun || ! TARGET_64BIT)
4594 return cfun->machine->call_abi;
4598 extern void init_regs (void);
4600 /* Implementation of call abi switching target hook. Specific to FNDECL
4601 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4602 for more details. */
4604 ix86_call_abi_override (const_tree fndecl)
4606 if (fndecl == NULL_TREE)
4607 cfun->machine->call_abi = DEFAULT_ABI;
4609 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4612 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4613 re-initialization of init_regs each time we switch function context since
4614 this is needed only during RTL expansion. */
4616 ix86_maybe_switch_abi (void)
4619 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4623 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4624 for a call to a function whose data type is FNTYPE.
4625 For a library call, FNTYPE is 0. */
4628 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4629 tree fntype, /* tree ptr for function decl */
4630 rtx libname, /* SYMBOL_REF of library name or 0 */
4633 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4634 memset (cum, 0, sizeof (*cum));
4637 cum->call_abi = ix86_function_abi (fndecl);
4639 cum->call_abi = ix86_function_type_abi (fntype);
4640 /* Set up the number of registers to use for passing arguments. */
4642 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4643 sorry ("ms_abi attribute require -maccumulate-outgoing-args or subtarget optimization implying it");
4644 cum->nregs = ix86_regparm;
4647 if (cum->call_abi != DEFAULT_ABI)
4648 cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
4653 cum->sse_nregs = SSE_REGPARM_MAX;
4656 if (cum->call_abi != DEFAULT_ABI)
4657 cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4658 : X64_SSE_REGPARM_MAX;
4662 cum->mmx_nregs = MMX_REGPARM_MAX;
4663 cum->warn_avx = true;
4664 cum->warn_sse = true;
4665 cum->warn_mmx = true;
4667 /* Because type might mismatch in between caller and callee, we need to
4668 use actual type of function for local calls.
4669 FIXME: cgraph_analyze can be told to actually record if function uses
4670 va_start so for local functions maybe_vaarg can be made aggressive
4672 FIXME: once typesytem is fixed, we won't need this code anymore. */
4674 fntype = TREE_TYPE (fndecl);
4675 cum->maybe_vaarg = (fntype
4676 ? (!prototype_p (fntype) || stdarg_p (fntype))
4681 /* If there are variable arguments, then we won't pass anything
4682 in registers in 32-bit mode. */
4683 if (stdarg_p (fntype))
4694 /* Use ecx and edx registers if function has fastcall attribute,
4695 else look for regparm information. */
4698 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4704 cum->nregs = ix86_function_regparm (fntype, fndecl);
4707 /* Set up the number of SSE registers used for passing SFmode
4708 and DFmode arguments. Warn for mismatching ABI. */
4709 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4713 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4714 But in the case of vector types, it is some vector mode.
4716 When we have only some of our vector isa extensions enabled, then there
4717 are some modes for which vector_mode_supported_p is false. For these
4718 modes, the generic vector support in gcc will choose some non-vector mode
4719 in order to implement the type. By computing the natural mode, we'll
4720 select the proper ABI location for the operand and not depend on whatever
4721 the middle-end decides to do with these vector types.
4723 The midde-end can't deal with the vector types > 16 bytes. In this
4724 case, we return the original mode and warn ABI change if CUM isn't
4727 static enum machine_mode
4728 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4730 enum machine_mode mode = TYPE_MODE (type);
4732 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4734 HOST_WIDE_INT size = int_size_in_bytes (type);
4735 if ((size == 8 || size == 16 || size == 32)
4736 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4737 && TYPE_VECTOR_SUBPARTS (type) > 1)
4739 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4741 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4742 mode = MIN_MODE_VECTOR_FLOAT;
4744 mode = MIN_MODE_VECTOR_INT;
4746 /* Get the mode which has this inner mode and number of units. */
4747 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4748 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4749 && GET_MODE_INNER (mode) == innermode)
4751 if (size == 32 && !TARGET_AVX)
4753 static bool warnedavx;
4760 warning (0, "AVX vector argument without AVX "
4761 "enabled changes the ABI");
4763 return TYPE_MODE (type);
4776 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4777 this may not agree with the mode that the type system has chosen for the
4778 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4779 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4782 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4787 if (orig_mode != BLKmode)
4788 tmp = gen_rtx_REG (orig_mode, regno);
4791 tmp = gen_rtx_REG (mode, regno);
4792 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4793 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4799 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4800 of this code is to classify each 8bytes of incoming argument by the register
4801 class and assign registers accordingly. */
4803 /* Return the union class of CLASS1 and CLASS2.
4804 See the x86-64 PS ABI for details. */
4806 static enum x86_64_reg_class
4807 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4809 /* Rule #1: If both classes are equal, this is the resulting class. */
4810 if (class1 == class2)
4813 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4815 if (class1 == X86_64_NO_CLASS)
4817 if (class2 == X86_64_NO_CLASS)
4820 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4821 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4822 return X86_64_MEMORY_CLASS;
4824 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4825 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4826 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4827 return X86_64_INTEGERSI_CLASS;
4828 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4829 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4830 return X86_64_INTEGER_CLASS;
4832 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4834 if (class1 == X86_64_X87_CLASS
4835 || class1 == X86_64_X87UP_CLASS
4836 || class1 == X86_64_COMPLEX_X87_CLASS
4837 || class2 == X86_64_X87_CLASS
4838 || class2 == X86_64_X87UP_CLASS
4839 || class2 == X86_64_COMPLEX_X87_CLASS)
4840 return X86_64_MEMORY_CLASS;
4842 /* Rule #6: Otherwise class SSE is used. */
4843 return X86_64_SSE_CLASS;
4846 /* Classify the argument of type TYPE and mode MODE.
4847 CLASSES will be filled by the register class used to pass each word
4848 of the operand. The number of words is returned. In case the parameter
4849 should be passed in memory, 0 is returned. As a special case for zero
4850 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4852 BIT_OFFSET is used internally for handling records and specifies offset
4853 of the offset in bits modulo 256 to avoid overflow cases.
4855 See the x86-64 PS ABI for details.
4859 classify_argument (enum machine_mode mode, const_tree type,
4860 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4862 HOST_WIDE_INT bytes =
4863 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4864 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4866 /* Variable sized entities are always passed/returned in memory. */
4870 if (mode != VOIDmode
4871 && targetm.calls.must_pass_in_stack (mode, type))
4874 if (type && AGGREGATE_TYPE_P (type))
4878 enum x86_64_reg_class subclasses[MAX_CLASSES];
4880 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
4884 for (i = 0; i < words; i++)
4885 classes[i] = X86_64_NO_CLASS;
4887 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4888 signalize memory class, so handle it as special case. */
4891 classes[0] = X86_64_NO_CLASS;
4895 /* Classify each field of record and merge classes. */
4896 switch (TREE_CODE (type))
4899 /* And now merge the fields of structure. */
4900 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4902 if (TREE_CODE (field) == FIELD_DECL)
4906 if (TREE_TYPE (field) == error_mark_node)
4909 /* Bitfields are always classified as integer. Handle them
4910 early, since later code would consider them to be
4911 misaligned integers. */
4912 if (DECL_BIT_FIELD (field))
4914 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4915 i < ((int_bit_position (field) + (bit_offset % 64))
4916 + tree_low_cst (DECL_SIZE (field), 0)
4919 merge_classes (X86_64_INTEGER_CLASS,
4924 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4925 TREE_TYPE (field), subclasses,
4926 (int_bit_position (field)
4927 + bit_offset) % 256);
4930 for (i = 0; i < num; i++)
4933 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4935 merge_classes (subclasses[i], classes[i + pos]);
4943 /* Arrays are handled as small records. */
4946 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
4947 TREE_TYPE (type), subclasses, bit_offset);
4951 /* The partial classes are now full classes. */
4952 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
4953 subclasses[0] = X86_64_SSE_CLASS;
4954 if (subclasses[0] == X86_64_INTEGERSI_CLASS
4955 && !((bit_offset % 64) == 0 && bytes == 4))
4956 subclasses[0] = X86_64_INTEGER_CLASS;
4958 for (i = 0; i < words; i++)
4959 classes[i] = subclasses[i % num];
4964 case QUAL_UNION_TYPE:
4965 /* Unions are similar to RECORD_TYPE but offset is always 0.
4967 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4969 if (TREE_CODE (field) == FIELD_DECL)
4973 if (TREE_TYPE (field) == error_mark_node)
4976 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
4977 TREE_TYPE (field), subclasses,
4981 for (i = 0; i < num; i++)
4982 classes[i] = merge_classes (subclasses[i], classes[i]);
4993 /* When size > 16 bytes, if the first one isn't
4994 X86_64_SSE_CLASS or any other ones aren't
4995 X86_64_SSEUP_CLASS, everything should be passed in
4997 if (classes[0] != X86_64_SSE_CLASS)
5000 for (i = 1; i < words; i++)
5001 if (classes[i] != X86_64_SSEUP_CLASS)
5005 /* Final merger cleanup. */
5006 for (i = 0; i < words; i++)
5008 /* If one class is MEMORY, everything should be passed in
5010 if (classes[i] == X86_64_MEMORY_CLASS)
5013 /* The X86_64_SSEUP_CLASS should be always preceded by
5014 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5015 if (classes[i] == X86_64_SSEUP_CLASS
5016 && classes[i - 1] != X86_64_SSE_CLASS
5017 && classes[i - 1] != X86_64_SSEUP_CLASS)
5019 /* The first one should never be X86_64_SSEUP_CLASS. */
5020 gcc_assert (i != 0);
5021 classes[i] = X86_64_SSE_CLASS;
5024 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5025 everything should be passed in memory. */
5026 if (classes[i] == X86_64_X87UP_CLASS
5027 && (classes[i - 1] != X86_64_X87_CLASS))
5031 /* The first one should never be X86_64_X87UP_CLASS. */
5032 gcc_assert (i != 0);
5033 if (!warned && warn_psabi)
5036 inform (input_location,
5037 "The ABI of passing union with long double"
5038 " has changed in GCC 4.4");
5046 /* Compute alignment needed. We align all types to natural boundaries with
5047 exception of XFmode that is aligned to 64bits. */
5048 if (mode != VOIDmode && mode != BLKmode)
5050 int mode_alignment = GET_MODE_BITSIZE (mode);
5053 mode_alignment = 128;
5054 else if (mode == XCmode)
5055 mode_alignment = 256;
5056 if (COMPLEX_MODE_P (mode))
5057 mode_alignment /= 2;
5058 /* Misaligned fields are always returned in memory. */
5059 if (bit_offset % mode_alignment)
5063 /* for V1xx modes, just use the base mode */
5064 if (VECTOR_MODE_P (mode) && mode != V1DImode
5065 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5066 mode = GET_MODE_INNER (mode);
5068 /* Classification of atomic types. */
5073 classes[0] = X86_64_SSE_CLASS;
5076 classes[0] = X86_64_SSE_CLASS;
5077 classes[1] = X86_64_SSEUP_CLASS;
5087 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5091 classes[0] = X86_64_INTEGERSI_CLASS;
5094 else if (size <= 64)
5096 classes[0] = X86_64_INTEGER_CLASS;
5099 else if (size <= 64+32)
5101 classes[0] = X86_64_INTEGER_CLASS;
5102 classes[1] = X86_64_INTEGERSI_CLASS;
5105 else if (size <= 64+64)
5107 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5115 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5119 /* OImode shouldn't be used directly. */
5124 if (!(bit_offset % 64))
5125 classes[0] = X86_64_SSESF_CLASS;
5127 classes[0] = X86_64_SSE_CLASS;
5130 classes[0] = X86_64_SSEDF_CLASS;
5133 classes[0] = X86_64_X87_CLASS;
5134 classes[1] = X86_64_X87UP_CLASS;
5137 classes[0] = X86_64_SSE_CLASS;
5138 classes[1] = X86_64_SSEUP_CLASS;
5141 classes[0] = X86_64_SSE_CLASS;
5144 classes[0] = X86_64_SSEDF_CLASS;
5145 classes[1] = X86_64_SSEDF_CLASS;
5148 classes[0] = X86_64_COMPLEX_X87_CLASS;
5151 /* This modes is larger than 16 bytes. */
5159 classes[0] = X86_64_SSE_CLASS;
5160 classes[1] = X86_64_SSEUP_CLASS;
5161 classes[2] = X86_64_SSEUP_CLASS;
5162 classes[3] = X86_64_SSEUP_CLASS;
5170 classes[0] = X86_64_SSE_CLASS;
5171 classes[1] = X86_64_SSEUP_CLASS;
5178 classes[0] = X86_64_SSE_CLASS;
5184 gcc_assert (VECTOR_MODE_P (mode));
5189 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5191 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5192 classes[0] = X86_64_INTEGERSI_CLASS;
5194 classes[0] = X86_64_INTEGER_CLASS;
5195 classes[1] = X86_64_INTEGER_CLASS;
5196 return 1 + (bytes > 8);
5200 /* Examine the argument and return set number of register required in each
5201 class. Return 0 iff parameter should be passed in memory. */
5203 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5204 int *int_nregs, int *sse_nregs)
5206 enum x86_64_reg_class regclass[MAX_CLASSES];
5207 int n = classify_argument (mode, type, regclass, 0);
5213 for (n--; n >= 0; n--)
5214 switch (regclass[n])
5216 case X86_64_INTEGER_CLASS:
5217 case X86_64_INTEGERSI_CLASS:
5220 case X86_64_SSE_CLASS:
5221 case X86_64_SSESF_CLASS:
5222 case X86_64_SSEDF_CLASS:
5225 case X86_64_NO_CLASS:
5226 case X86_64_SSEUP_CLASS:
5228 case X86_64_X87_CLASS:
5229 case X86_64_X87UP_CLASS:
5233 case X86_64_COMPLEX_X87_CLASS:
5234 return in_return ? 2 : 0;
5235 case X86_64_MEMORY_CLASS:
5241 /* Construct container for the argument used by GCC interface. See
5242 FUNCTION_ARG for the detailed description. */
5245 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5246 const_tree type, int in_return, int nintregs, int nsseregs,
5247 const int *intreg, int sse_regno)
5249 /* The following variables hold the static issued_error state. */
5250 static bool issued_sse_arg_error;
5251 static bool issued_sse_ret_error;
5252 static bool issued_x87_ret_error;
5254 enum machine_mode tmpmode;
5256 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5257 enum x86_64_reg_class regclass[MAX_CLASSES];
5261 int needed_sseregs, needed_intregs;
5262 rtx exp[MAX_CLASSES];
5265 n = classify_argument (mode, type, regclass, 0);
5268 if (!examine_argument (mode, type, in_return, &needed_intregs,
5271 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5274 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5275 some less clueful developer tries to use floating-point anyway. */
5276 if (needed_sseregs && !TARGET_SSE)
5280 if (!issued_sse_ret_error)
5282 error ("SSE register return with SSE disabled");
5283 issued_sse_ret_error = true;
5286 else if (!issued_sse_arg_error)
5288 error ("SSE register argument with SSE disabled");
5289 issued_sse_arg_error = true;
5294 /* Likewise, error if the ABI requires us to return values in the
5295 x87 registers and the user specified -mno-80387. */
5296 if (!TARGET_80387 && in_return)
5297 for (i = 0; i < n; i++)
5298 if (regclass[i] == X86_64_X87_CLASS
5299 || regclass[i] == X86_64_X87UP_CLASS
5300 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5302 if (!issued_x87_ret_error)
5304 error ("x87 register return with x87 disabled");
5305 issued_x87_ret_error = true;
5310 /* First construct simple cases. Avoid SCmode, since we want to use
5311 single register to pass this type. */
5312 if (n == 1 && mode != SCmode)
5313 switch (regclass[0])
5315 case X86_64_INTEGER_CLASS:
5316 case X86_64_INTEGERSI_CLASS:
5317 return gen_rtx_REG (mode, intreg[0]);
5318 case X86_64_SSE_CLASS:
5319 case X86_64_SSESF_CLASS:
5320 case X86_64_SSEDF_CLASS:
5321 return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
5322 case X86_64_X87_CLASS:
5323 case X86_64_COMPLEX_X87_CLASS:
5324 return gen_rtx_REG (mode, FIRST_STACK_REG);
5325 case X86_64_NO_CLASS:
5326 /* Zero sized array, struct or class. */
5331 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5332 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5333 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5335 && regclass[0] == X86_64_SSE_CLASS
5336 && regclass[1] == X86_64_SSEUP_CLASS
5337 && regclass[2] == X86_64_SSEUP_CLASS
5338 && regclass[3] == X86_64_SSEUP_CLASS
5340 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5343 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5344 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5345 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5346 && regclass[1] == X86_64_INTEGER_CLASS
5347 && (mode == CDImode || mode == TImode || mode == TFmode)
5348 && intreg[0] + 1 == intreg[1])
5349 return gen_rtx_REG (mode, intreg[0]);
5351 /* Otherwise figure out the entries of the PARALLEL. */
5352 for (i = 0; i < n; i++)
5356 switch (regclass[i])
5358 case X86_64_NO_CLASS:
5360 case X86_64_INTEGER_CLASS:
5361 case X86_64_INTEGERSI_CLASS:
5362 /* Merge TImodes on aligned occasions here too. */
5363 if (i * 8 + 8 > bytes)
5364 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5365 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5369 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5370 if (tmpmode == BLKmode)
5372 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5373 gen_rtx_REG (tmpmode, *intreg),
5377 case X86_64_SSESF_CLASS:
5378 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5379 gen_rtx_REG (SFmode,
5380 SSE_REGNO (sse_regno)),
5384 case X86_64_SSEDF_CLASS:
5385 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5386 gen_rtx_REG (DFmode,
5387 SSE_REGNO (sse_regno)),
5391 case X86_64_SSE_CLASS:
5399 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5409 && regclass[1] == X86_64_SSEUP_CLASS
5410 && regclass[2] == X86_64_SSEUP_CLASS
5411 && regclass[3] == X86_64_SSEUP_CLASS);
5418 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5419 gen_rtx_REG (tmpmode,
5420 SSE_REGNO (sse_regno)),
5429 /* Empty aligned struct, union or class. */
5433 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5434 for (i = 0; i < nexps; i++)
5435 XVECEXP (ret, 0, i) = exp [i];
5439 /* Update the data in CUM to advance over an argument of mode MODE
5440 and data type TYPE. (TYPE is null for libcalls where that information
5441 may not be available.) */
5444 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5445 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5461 cum->words += words;
5462 cum->nregs -= words;
5463 cum->regno += words;
5465 if (cum->nregs <= 0)
5473 /* OImode shouldn't be used directly. */
5477 if (cum->float_in_sse < 2)
5480 if (cum->float_in_sse < 1)
5497 if (!type || !AGGREGATE_TYPE_P (type))
5499 cum->sse_words += words;
5500 cum->sse_nregs -= 1;
5501 cum->sse_regno += 1;
5502 if (cum->sse_nregs <= 0)
5515 if (!type || !AGGREGATE_TYPE_P (type))
5517 cum->mmx_words += words;
5518 cum->mmx_nregs -= 1;
5519 cum->mmx_regno += 1;
5520 if (cum->mmx_nregs <= 0)
5531 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5532 tree type, HOST_WIDE_INT words, int named)
5534 int int_nregs, sse_nregs;
5536 /* Unnamed 256bit vector mode parameters are passed on stack. */
5537 if (!named && VALID_AVX256_REG_MODE (mode))
5540 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5541 cum->words += words;
5542 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5544 cum->nregs -= int_nregs;
5545 cum->sse_nregs -= sse_nregs;
5546 cum->regno += int_nregs;
5547 cum->sse_regno += sse_nregs;
5550 cum->words += words;
5554 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5555 HOST_WIDE_INT words)
5557 /* Otherwise, this should be passed indirect. */
5558 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5560 cum->words += words;
5569 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5570 tree type, int named)
5572 HOST_WIDE_INT bytes, words;
5574 if (mode == BLKmode)
5575 bytes = int_size_in_bytes (type);
5577 bytes = GET_MODE_SIZE (mode);
5578 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5581 mode = type_natural_mode (type, NULL);
5583 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5584 function_arg_advance_ms_64 (cum, bytes, words);
5585 else if (TARGET_64BIT)
5586 function_arg_advance_64 (cum, mode, type, words, named);
5588 function_arg_advance_32 (cum, mode, type, bytes, words);
5591 /* Define where to put the arguments to a function.
5592 Value is zero to push the argument on the stack,
5593 or a hard register in which to store the argument.
5595 MODE is the argument's machine mode.
5596 TYPE is the data type of the argument (as a tree).
5597 This is null for libcalls where that information may
5599 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5600 the preceding args and about the function being called.
5601 NAMED is nonzero if this argument is a named parameter
5602 (otherwise it is an extra parameter matching an ellipsis). */
5605 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5606 enum machine_mode orig_mode, tree type,
5607 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5609 static bool warnedsse, warnedmmx;
5611 /* Avoid the AL settings for the Unix64 ABI. */
5612 if (mode == VOIDmode)
5628 if (words <= cum->nregs)
5630 int regno = cum->regno;
5632 /* Fastcall allocates the first two DWORD (SImode) or
5633 smaller arguments to ECX and EDX if it isn't an
5639 || (type && AGGREGATE_TYPE_P (type)))
5642 /* ECX not EAX is the first allocated register. */
5643 if (regno == AX_REG)
5646 return gen_rtx_REG (mode, regno);
5651 if (cum->float_in_sse < 2)
5654 if (cum->float_in_sse < 1)
5658 /* In 32bit, we pass TImode in xmm registers. */
5665 if (!type || !AGGREGATE_TYPE_P (type))
5667 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5670 warning (0, "SSE vector argument without SSE enabled "
5674 return gen_reg_or_parallel (mode, orig_mode,
5675 cum->sse_regno + FIRST_SSE_REG);
5680 /* OImode shouldn't be used directly. */
5689 if (!type || !AGGREGATE_TYPE_P (type))
5692 return gen_reg_or_parallel (mode, orig_mode,
5693 cum->sse_regno + FIRST_SSE_REG);
5702 if (!type || !AGGREGATE_TYPE_P (type))
5704 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5707 warning (0, "MMX vector argument without MMX enabled "
5711 return gen_reg_or_parallel (mode, orig_mode,
5712 cum->mmx_regno + FIRST_MMX_REG);
5721 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5722 enum machine_mode orig_mode, tree type, int named)
5724 /* Handle a hidden AL argument containing number of registers
5725 for varargs x86-64 functions. */
5726 if (mode == VOIDmode)
5727 return GEN_INT (cum->maybe_vaarg
5728 ? (cum->sse_nregs < 0
5729 ? (cum->call_abi == DEFAULT_ABI
5731 : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5732 : X64_SSE_REGPARM_MAX))
5747 /* Unnamed 256bit vector mode parameters are passed on stack. */
5753 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5755 &x86_64_int_parameter_registers [cum->regno],
5760 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5761 enum machine_mode orig_mode, int named,
5762 HOST_WIDE_INT bytes)
5766 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5767 We use value of -2 to specify that current function call is MSABI. */
5768 if (mode == VOIDmode)
5769 return GEN_INT (-2);
5771 /* If we've run out of registers, it goes on the stack. */
5772 if (cum->nregs == 0)
5775 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5777 /* Only floating point modes are passed in anything but integer regs. */
5778 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5781 regno = cum->regno + FIRST_SSE_REG;
5786 /* Unnamed floating parameters are passed in both the
5787 SSE and integer registers. */
5788 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5789 t2 = gen_rtx_REG (mode, regno);
5790 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5791 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5792 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5795 /* Handle aggregated types passed in register. */
5796 if (orig_mode == BLKmode)
5798 if (bytes > 0 && bytes <= 8)
5799 mode = (bytes > 4 ? DImode : SImode);
5800 if (mode == BLKmode)
5804 return gen_reg_or_parallel (mode, orig_mode, regno);
5808 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5809 tree type, int named)
5811 enum machine_mode mode = omode;
5812 HOST_WIDE_INT bytes, words;
5814 if (mode == BLKmode)
5815 bytes = int_size_in_bytes (type);
5817 bytes = GET_MODE_SIZE (mode);
5818 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5820 /* To simplify the code below, represent vector types with a vector mode
5821 even if MMX/SSE are not active. */
5822 if (type && TREE_CODE (type) == VECTOR_TYPE)
5823 mode = type_natural_mode (type, cum);
5825 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5826 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5827 else if (TARGET_64BIT)
5828 return function_arg_64 (cum, mode, omode, type, named);
5830 return function_arg_32 (cum, mode, omode, type, bytes, words);
5833 /* A C expression that indicates when an argument must be passed by
5834 reference. If nonzero for an argument, a copy of that argument is
5835 made in memory and a pointer to the argument is passed instead of
5836 the argument itself. The pointer is passed in whatever way is
5837 appropriate for passing a pointer to that type. */
5840 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5841 enum machine_mode mode ATTRIBUTE_UNUSED,
5842 const_tree type, bool named ATTRIBUTE_UNUSED)
5844 /* See Windows x64 Software Convention. */
5845 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5847 int msize = (int) GET_MODE_SIZE (mode);
5850 /* Arrays are passed by reference. */
5851 if (TREE_CODE (type) == ARRAY_TYPE)
5854 if (AGGREGATE_TYPE_P (type))
5856 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5857 are passed by reference. */
5858 msize = int_size_in_bytes (type);
5862 /* __m128 is passed by reference. */
5864 case 1: case 2: case 4: case 8:
5870 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
5876 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
5879 contains_aligned_value_p (tree type)
5881 enum machine_mode mode = TYPE_MODE (type);
5882 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
5886 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
5888 if (TYPE_ALIGN (type) < 128)
5891 if (AGGREGATE_TYPE_P (type))
5893 /* Walk the aggregates recursively. */
5894 switch (TREE_CODE (type))
5898 case QUAL_UNION_TYPE:
5902 /* Walk all the structure fields. */
5903 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5905 if (TREE_CODE (field) == FIELD_DECL
5906 && contains_aligned_value_p (TREE_TYPE (field)))
5913 /* Just for use if some languages passes arrays by value. */
5914 if (contains_aligned_value_p (TREE_TYPE (type)))
5925 /* Gives the alignment boundary, in bits, of an argument with the
5926 specified mode and type. */
5929 ix86_function_arg_boundary (enum machine_mode mode, tree type)
5934 /* Since canonical type is used for call, we convert it to
5935 canonical type if needed. */
5936 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
5937 type = TYPE_CANONICAL (type);
5938 align = TYPE_ALIGN (type);
5941 align = GET_MODE_ALIGNMENT (mode);
5942 if (align < PARM_BOUNDARY)
5943 align = PARM_BOUNDARY;
5944 /* In 32bit, only _Decimal128 and __float128 are aligned to their
5945 natural boundaries. */
5946 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
5948 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
5949 make an exception for SSE modes since these require 128bit
5952 The handling here differs from field_alignment. ICC aligns MMX
5953 arguments to 4 byte boundaries, while structure fields are aligned
5954 to 8 byte boundaries. */
5957 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
5958 align = PARM_BOUNDARY;
5962 if (!contains_aligned_value_p (type))
5963 align = PARM_BOUNDARY;
5966 if (align > BIGGEST_ALIGNMENT)
5967 align = BIGGEST_ALIGNMENT;
5971 /* Return true if N is a possible register number of function value. */
5974 ix86_function_value_regno_p (int regno)
5981 case FIRST_FLOAT_REG:
5982 /* TODO: The function should depend on current function ABI but
5983 builtins.c would need updating then. Therefore we use the
5985 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
5987 return TARGET_FLOAT_RETURNS_IN_80387;
5993 if (TARGET_MACHO || TARGET_64BIT)
6001 /* Define how to find the value returned by a function.
6002 VALTYPE is the data type of the value (as a tree).
6003 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6004 otherwise, FUNC is 0. */
6007 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6008 const_tree fntype, const_tree fn)
6012 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6013 we normally prevent this case when mmx is not available. However
6014 some ABIs may require the result to be returned like DImode. */
6015 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6016 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6018 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6019 we prevent this case when sse is not available. However some ABIs
6020 may require the result to be returned like integer TImode. */
6021 else if (mode == TImode
6022 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6023 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6025 /* 32-byte vector modes in %ymm0. */
6026 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6027 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6029 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6030 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6031 regno = FIRST_FLOAT_REG;
6033 /* Most things go in %eax. */
6036 /* Override FP return register with %xmm0 for local functions when
6037 SSE math is enabled or for functions with sseregparm attribute. */
6038 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6040 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6041 if ((sse_level >= 1 && mode == SFmode)
6042 || (sse_level == 2 && mode == DFmode))
6043 regno = FIRST_SSE_REG;
6046 /* OImode shouldn't be used directly. */
6047 gcc_assert (mode != OImode);
6049 return gen_rtx_REG (orig_mode, regno);
6053 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6058 /* Handle libcalls, which don't provide a type node. */
6059 if (valtype == NULL)
6071 return gen_rtx_REG (mode, FIRST_SSE_REG);
6074 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6078 return gen_rtx_REG (mode, AX_REG);
6082 ret = construct_container (mode, orig_mode, valtype, 1,
6083 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6084 x86_64_int_return_registers, 0);
6086 /* For zero sized structures, construct_container returns NULL, but we
6087 need to keep rest of compiler happy by returning meaningful value. */
6089 ret = gen_rtx_REG (orig_mode, AX_REG);
6095 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6097 unsigned int regno = AX_REG;
6101 switch (GET_MODE_SIZE (mode))
6104 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6105 && !COMPLEX_MODE_P (mode))
6106 regno = FIRST_SSE_REG;
6110 if (mode == SFmode || mode == DFmode)
6111 regno = FIRST_SSE_REG;
6117 return gen_rtx_REG (orig_mode, regno);
6121 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6122 enum machine_mode orig_mode, enum machine_mode mode)
6124 const_tree fn, fntype;
6127 if (fntype_or_decl && DECL_P (fntype_or_decl))
6128 fn = fntype_or_decl;
6129 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6131 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6132 return function_value_ms_64 (orig_mode, mode);
6133 else if (TARGET_64BIT)
6134 return function_value_64 (orig_mode, mode, valtype);
6136 return function_value_32 (orig_mode, mode, fntype, fn);
6140 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6141 bool outgoing ATTRIBUTE_UNUSED)
6143 enum machine_mode mode, orig_mode;
6145 orig_mode = TYPE_MODE (valtype);
6146 mode = type_natural_mode (valtype, NULL);
6147 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6151 ix86_libcall_value (enum machine_mode mode)
6153 return ix86_function_value_1 (NULL, NULL, mode, mode);
6156 /* Return true iff type is returned in memory. */
6158 static int ATTRIBUTE_UNUSED
6159 return_in_memory_32 (const_tree type, enum machine_mode mode)
6163 if (mode == BLKmode)
6166 size = int_size_in_bytes (type);
6168 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6171 if (VECTOR_MODE_P (mode) || mode == TImode)
6173 /* User-created vectors small enough to fit in EAX. */
6177 /* MMX/3dNow values are returned in MM0,
6178 except when it doesn't exits. */
6180 return (TARGET_MMX ? 0 : 1);
6182 /* SSE values are returned in XMM0, except when it doesn't exist. */
6184 return (TARGET_SSE ? 0 : 1);
6186 /* AVX values are returned in YMM0, except when it doesn't exist. */
6188 return TARGET_AVX ? 0 : 1;
6197 /* OImode shouldn't be used directly. */
6198 gcc_assert (mode != OImode);
6203 static int ATTRIBUTE_UNUSED
6204 return_in_memory_64 (const_tree type, enum machine_mode mode)
6206 int needed_intregs, needed_sseregs;
6207 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6210 static int ATTRIBUTE_UNUSED
6211 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6213 HOST_WIDE_INT size = int_size_in_bytes (type);
6215 /* __m128 is returned in xmm0. */
6216 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6217 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6220 /* Otherwise, the size must be exactly in [1248]. */
6221 return (size != 1 && size != 2 && size != 4 && size != 8);
6225 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6227 #ifdef SUBTARGET_RETURN_IN_MEMORY
6228 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6230 const enum machine_mode mode = type_natural_mode (type, NULL);
6234 if (ix86_function_type_abi (fntype) == MS_ABI)
6235 return return_in_memory_ms_64 (type, mode);
6237 return return_in_memory_64 (type, mode);
6240 return return_in_memory_32 (type, mode);
6244 /* Return false iff TYPE is returned in memory. This version is used
6245 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6246 but differs notably in that when MMX is available, 8-byte vectors
6247 are returned in memory, rather than in MMX registers. */
6250 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6253 enum machine_mode mode = type_natural_mode (type, NULL);
6256 return return_in_memory_64 (type, mode);
6258 if (mode == BLKmode)
6261 size = int_size_in_bytes (type);
6263 if (VECTOR_MODE_P (mode))
6265 /* Return in memory only if MMX registers *are* available. This
6266 seems backwards, but it is consistent with the existing
6273 else if (mode == TImode)
6275 else if (mode == XFmode)
6281 /* When returning SSE vector types, we have a choice of either
6282 (1) being abi incompatible with a -march switch, or
6283 (2) generating an error.
6284 Given no good solution, I think the safest thing is one warning.
6285 The user won't be able to use -Werror, but....
6287 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6288 called in response to actually generating a caller or callee that
6289 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6290 via aggregate_value_p for general type probing from tree-ssa. */
6293 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6295 static bool warnedsse, warnedmmx;
6297 if (!TARGET_64BIT && type)
6299 /* Look at the return type of the function, not the function type. */
6300 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6302 if (!TARGET_SSE && !warnedsse)
6305 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6308 warning (0, "SSE vector return without SSE enabled "
6313 if (!TARGET_MMX && !warnedmmx)
6315 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6318 warning (0, "MMX vector return without MMX enabled "
6328 /* Create the va_list data type. */
6330 /* Returns the calling convention specific va_list date type.
6331 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6334 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6336 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6338 /* For i386 we use plain pointer to argument area. */
6339 if (!TARGET_64BIT || abi == MS_ABI)
6340 return build_pointer_type (char_type_node);
6342 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6343 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6345 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6346 unsigned_type_node);
6347 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6348 unsigned_type_node);
6349 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6351 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6354 va_list_gpr_counter_field = f_gpr;
6355 va_list_fpr_counter_field = f_fpr;
6357 DECL_FIELD_CONTEXT (f_gpr) = record;
6358 DECL_FIELD_CONTEXT (f_fpr) = record;
6359 DECL_FIELD_CONTEXT (f_ovf) = record;
6360 DECL_FIELD_CONTEXT (f_sav) = record;
6362 TREE_CHAIN (record) = type_decl;
6363 TYPE_NAME (record) = type_decl;
6364 TYPE_FIELDS (record) = f_gpr;
6365 TREE_CHAIN (f_gpr) = f_fpr;
6366 TREE_CHAIN (f_fpr) = f_ovf;
6367 TREE_CHAIN (f_ovf) = f_sav;
6369 layout_type (record);
6371 /* The correct type is an array type of one element. */
6372 return build_array_type (record, build_index_type (size_zero_node));
6375 /* Setup the builtin va_list data type and for 64-bit the additional
6376 calling convention specific va_list data types. */
6379 ix86_build_builtin_va_list (void)
6381 tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI);
6383 /* Initialize abi specific va_list builtin types. */
6387 if (DEFAULT_ABI == MS_ABI)
6389 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6390 if (TREE_CODE (t) != RECORD_TYPE)
6391 t = build_variant_type_copy (t);
6392 sysv_va_list_type_node = t;
6397 if (TREE_CODE (t) != RECORD_TYPE)
6398 t = build_variant_type_copy (t);
6399 sysv_va_list_type_node = t;
6401 if (DEFAULT_ABI != MS_ABI)
6403 t = ix86_build_builtin_va_list_abi (MS_ABI);
6404 if (TREE_CODE (t) != RECORD_TYPE)
6405 t = build_variant_type_copy (t);
6406 ms_va_list_type_node = t;
6411 if (TREE_CODE (t) != RECORD_TYPE)
6412 t = build_variant_type_copy (t);
6413 ms_va_list_type_node = t;
6420 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6423 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6432 int regparm = ix86_regparm;
6434 if (cum->call_abi != DEFAULT_ABI)
6435 regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6437 /* GPR size of varargs save area. */
6438 if (cfun->va_list_gpr_size)
6439 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6441 ix86_varargs_gpr_size = 0;
6443 /* FPR size of varargs save area. We don't need it if we don't pass
6444 anything in SSE registers. */
6445 if (cum->sse_nregs && cfun->va_list_fpr_size)
6446 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6448 ix86_varargs_fpr_size = 0;
6450 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6453 save_area = frame_pointer_rtx;
6454 set = get_varargs_alias_set ();
6456 for (i = cum->regno;
6458 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6461 mem = gen_rtx_MEM (Pmode,
6462 plus_constant (save_area, i * UNITS_PER_WORD));
6463 MEM_NOTRAP_P (mem) = 1;
6464 set_mem_alias_set (mem, set);
6465 emit_move_insn (mem, gen_rtx_REG (Pmode,
6466 x86_64_int_parameter_registers[i]));
6469 if (ix86_varargs_fpr_size)
6471 /* Now emit code to save SSE registers. The AX parameter contains number
6472 of SSE parameter registers used to call this function. We use
6473 sse_prologue_save insn template that produces computed jump across
6474 SSE saves. We need some preparation work to get this working. */
6476 label = gen_label_rtx ();
6477 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6479 /* Compute address to jump to :
6480 label - eax*4 + nnamed_sse_arguments*4 Or
6481 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6482 tmp_reg = gen_reg_rtx (Pmode);
6483 nsse_reg = gen_reg_rtx (Pmode);
6484 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6485 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6486 gen_rtx_MULT (Pmode, nsse_reg,
6489 /* vmovaps is one byte longer than movaps. */
6491 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6492 gen_rtx_PLUS (Pmode, tmp_reg,
6498 gen_rtx_CONST (DImode,
6499 gen_rtx_PLUS (DImode,
6501 GEN_INT (cum->sse_regno
6502 * (TARGET_AVX ? 5 : 4)))));
6504 emit_move_insn (nsse_reg, label_ref);
6505 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6507 /* Compute address of memory block we save into. We always use pointer
6508 pointing 127 bytes after first byte to store - this is needed to keep
6509 instruction size limited by 4 bytes (5 bytes for AVX) with one
6510 byte displacement. */
6511 tmp_reg = gen_reg_rtx (Pmode);
6512 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6513 plus_constant (save_area,
6514 ix86_varargs_gpr_size + 127)));
6515 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6516 MEM_NOTRAP_P (mem) = 1;
6517 set_mem_alias_set (mem, set);
6518 set_mem_align (mem, BITS_PER_WORD);
6520 /* And finally do the dirty job! */
6521 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6522 GEN_INT (cum->sse_regno), label));
6527 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6529 alias_set_type set = get_varargs_alias_set ();
6532 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6536 mem = gen_rtx_MEM (Pmode,
6537 plus_constant (virtual_incoming_args_rtx,
6538 i * UNITS_PER_WORD));
6539 MEM_NOTRAP_P (mem) = 1;
6540 set_mem_alias_set (mem, set);
6542 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6543 emit_move_insn (mem, reg);
6548 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6549 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6552 CUMULATIVE_ARGS next_cum;
6555 /* This argument doesn't appear to be used anymore. Which is good,
6556 because the old code here didn't suppress rtl generation. */
6557 gcc_assert (!no_rtl);
6562 fntype = TREE_TYPE (current_function_decl);
6564 /* For varargs, we do not want to skip the dummy va_dcl argument.
6565 For stdargs, we do want to skip the last named argument. */
6567 if (stdarg_p (fntype))
6568 function_arg_advance (&next_cum, mode, type, 1);
6570 if (cum->call_abi == MS_ABI)
6571 setup_incoming_varargs_ms_64 (&next_cum);
6573 setup_incoming_varargs_64 (&next_cum);
6576 /* Checks if TYPE is of kind va_list char *. */
6579 is_va_list_char_pointer (tree type)
6583 /* For 32-bit it is always true. */
6586 canonic = ix86_canonical_va_list_type (type);
6587 return (canonic == ms_va_list_type_node
6588 || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node));
6591 /* Implement va_start. */
6594 ix86_va_start (tree valist, rtx nextarg)
6596 HOST_WIDE_INT words, n_gpr, n_fpr;
6597 tree f_gpr, f_fpr, f_ovf, f_sav;
6598 tree gpr, fpr, ovf, sav, t;
6601 /* Only 64bit target needs something special. */
6602 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6604 std_expand_builtin_va_start (valist, nextarg);
6608 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6609 f_fpr = TREE_CHAIN (f_gpr);
6610 f_ovf = TREE_CHAIN (f_fpr);
6611 f_sav = TREE_CHAIN (f_ovf);
6613 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6614 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6615 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6616 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6617 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6619 /* Count number of gp and fp argument registers used. */
6620 words = crtl->args.info.words;
6621 n_gpr = crtl->args.info.regno;
6622 n_fpr = crtl->args.info.sse_regno;
6624 if (cfun->va_list_gpr_size)
6626 type = TREE_TYPE (gpr);
6627 t = build2 (MODIFY_EXPR, type,
6628 gpr, build_int_cst (type, n_gpr * 8));
6629 TREE_SIDE_EFFECTS (t) = 1;
6630 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6633 if (TARGET_SSE && cfun->va_list_fpr_size)
6635 type = TREE_TYPE (fpr);
6636 t = build2 (MODIFY_EXPR, type, fpr,
6637 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6638 TREE_SIDE_EFFECTS (t) = 1;
6639 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6642 /* Find the overflow area. */
6643 type = TREE_TYPE (ovf);
6644 t = make_tree (type, crtl->args.internal_arg_pointer);
6646 t = build2 (POINTER_PLUS_EXPR, type, t,
6647 size_int (words * UNITS_PER_WORD));
6648 t = build2 (MODIFY_EXPR, type, ovf, t);
6649 TREE_SIDE_EFFECTS (t) = 1;
6650 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6652 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6654 /* Find the register save area.
6655 Prologue of the function save it right above stack frame. */
6656 type = TREE_TYPE (sav);
6657 t = make_tree (type, frame_pointer_rtx);
6658 if (!ix86_varargs_gpr_size)
6659 t = build2 (POINTER_PLUS_EXPR, type, t,
6660 size_int (-8 * X86_64_REGPARM_MAX));
6661 t = build2 (MODIFY_EXPR, type, sav, t);
6662 TREE_SIDE_EFFECTS (t) = 1;
6663 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6667 /* Implement va_arg. */
6670 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6673 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6674 tree f_gpr, f_fpr, f_ovf, f_sav;
6675 tree gpr, fpr, ovf, sav, t;
6677 tree lab_false, lab_over = NULL_TREE;
6682 enum machine_mode nat_mode;
6685 /* Only 64bit target needs something special. */
6686 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6687 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6689 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6690 f_fpr = TREE_CHAIN (f_gpr);
6691 f_ovf = TREE_CHAIN (f_fpr);
6692 f_sav = TREE_CHAIN (f_ovf);
6694 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6695 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6696 valist = build_va_arg_indirect_ref (valist);
6697 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6698 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6699 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6701 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6703 type = build_pointer_type (type);
6704 size = int_size_in_bytes (type);
6705 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6707 nat_mode = type_natural_mode (type, NULL);
6716 /* Unnamed 256bit vector mode parameters are passed on stack. */
6717 if (ix86_cfun_abi () == SYSV_ABI)
6724 container = construct_container (nat_mode, TYPE_MODE (type),
6725 type, 0, X86_64_REGPARM_MAX,
6726 X86_64_SSE_REGPARM_MAX, intreg,
6731 /* Pull the value out of the saved registers. */
6733 addr = create_tmp_var (ptr_type_node, "addr");
6734 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6738 int needed_intregs, needed_sseregs;
6740 tree int_addr, sse_addr;
6742 lab_false = create_artificial_label ();
6743 lab_over = create_artificial_label ();
6745 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6747 need_temp = (!REG_P (container)
6748 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6749 || TYPE_ALIGN (type) > 128));
6751 /* In case we are passing structure, verify that it is consecutive block
6752 on the register save area. If not we need to do moves. */
6753 if (!need_temp && !REG_P (container))
6755 /* Verify that all registers are strictly consecutive */
6756 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6760 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6762 rtx slot = XVECEXP (container, 0, i);
6763 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6764 || INTVAL (XEXP (slot, 1)) != i * 16)
6772 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6774 rtx slot = XVECEXP (container, 0, i);
6775 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6776 || INTVAL (XEXP (slot, 1)) != i * 8)
6788 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6789 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6790 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6791 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6794 /* First ensure that we fit completely in registers. */
6797 t = build_int_cst (TREE_TYPE (gpr),
6798 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6799 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6800 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6801 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6802 gimplify_and_add (t, pre_p);
6806 t = build_int_cst (TREE_TYPE (fpr),
6807 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6808 + X86_64_REGPARM_MAX * 8);
6809 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6810 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6811 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6812 gimplify_and_add (t, pre_p);
6815 /* Compute index to start of area used for integer regs. */
6818 /* int_addr = gpr + sav; */
6819 t = fold_convert (sizetype, gpr);
6820 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6821 gimplify_assign (int_addr, t, pre_p);
6825 /* sse_addr = fpr + sav; */
6826 t = fold_convert (sizetype, fpr);
6827 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6828 gimplify_assign (sse_addr, t, pre_p);
6833 tree temp = create_tmp_var (type, "va_arg_tmp");
6836 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
6837 gimplify_assign (addr, t, pre_p);
6839 for (i = 0; i < XVECLEN (container, 0); i++)
6841 rtx slot = XVECEXP (container, 0, i);
6842 rtx reg = XEXP (slot, 0);
6843 enum machine_mode mode = GET_MODE (reg);
6844 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
6845 tree addr_type = build_pointer_type (piece_type);
6846 tree daddr_type = build_pointer_type_for_mode (piece_type,
6850 tree dest_addr, dest;
6852 if (SSE_REGNO_P (REGNO (reg)))
6854 src_addr = sse_addr;
6855 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
6859 src_addr = int_addr;
6860 src_offset = REGNO (reg) * 8;
6862 src_addr = fold_convert (addr_type, src_addr);
6863 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
6864 size_int (src_offset));
6865 src = build_va_arg_indirect_ref (src_addr);
6867 dest_addr = fold_convert (daddr_type, addr);
6868 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
6869 size_int (INTVAL (XEXP (slot, 1))));
6870 dest = build_va_arg_indirect_ref (dest_addr);
6872 gimplify_assign (dest, src, pre_p);
6878 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
6879 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
6880 gimplify_assign (gpr, t, pre_p);
6885 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
6886 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
6887 gimplify_assign (fpr, t, pre_p);
6890 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
6892 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
6895 /* ... otherwise out of the overflow area. */
6897 /* When we align parameter on stack for caller, if the parameter
6898 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6899 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6900 here with caller. */
6901 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
6902 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6903 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6905 /* Care for on-stack alignment if needed. */
6906 if (arg_boundary <= 64
6907 || integer_zerop (TYPE_SIZE (type)))
6911 HOST_WIDE_INT align = arg_boundary / 8;
6912 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
6913 size_int (align - 1));
6914 t = fold_convert (sizetype, t);
6915 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6917 t = fold_convert (TREE_TYPE (ovf), t);
6919 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6920 gimplify_assign (addr, t, pre_p);
6922 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
6923 size_int (rsize * UNITS_PER_WORD));
6924 gimplify_assign (unshare_expr (ovf), t, pre_p);
6927 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
6929 ptrtype = build_pointer_type (type);
6930 addr = fold_convert (ptrtype, addr);
6933 addr = build_va_arg_indirect_ref (addr);
6934 return build_va_arg_indirect_ref (addr);
6937 /* Return nonzero if OPNUM's MEM should be matched
6938 in movabs* patterns. */
6941 ix86_check_movabs (rtx insn, int opnum)
6945 set = PATTERN (insn);
6946 if (GET_CODE (set) == PARALLEL)
6947 set = XVECEXP (set, 0, 0);
6948 gcc_assert (GET_CODE (set) == SET);
6949 mem = XEXP (set, opnum);
6950 while (GET_CODE (mem) == SUBREG)
6951 mem = SUBREG_REG (mem);
6952 gcc_assert (MEM_P (mem));
6953 return (volatile_ok || !MEM_VOLATILE_P (mem));
6956 /* Initialize the table of extra 80387 mathematical constants. */
6959 init_ext_80387_constants (void)
6961 static const char * cst[5] =
6963 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
6964 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
6965 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
6966 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
6967 "3.1415926535897932385128089594061862044", /* 4: fldpi */
6971 for (i = 0; i < 5; i++)
6973 real_from_string (&ext_80387_constants_table[i], cst[i]);
6974 /* Ensure each constant is rounded to XFmode precision. */
6975 real_convert (&ext_80387_constants_table[i],
6976 XFmode, &ext_80387_constants_table[i]);
6979 ext_80387_constants_init = 1;
6982 /* Return true if the constant is something that can be loaded with
6983 a special instruction. */
6986 standard_80387_constant_p (rtx x)
6988 enum machine_mode mode = GET_MODE (x);
6992 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
6995 if (x == CONST0_RTX (mode))
6997 if (x == CONST1_RTX (mode))
7000 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7002 /* For XFmode constants, try to find a special 80387 instruction when
7003 optimizing for size or on those CPUs that benefit from them. */
7005 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7009 if (! ext_80387_constants_init)
7010 init_ext_80387_constants ();
7012 for (i = 0; i < 5; i++)
7013 if (real_identical (&r, &ext_80387_constants_table[i]))
7017 /* Load of the constant -0.0 or -1.0 will be split as
7018 fldz;fchs or fld1;fchs sequence. */
7019 if (real_isnegzero (&r))
7021 if (real_identical (&r, &dconstm1))
7027 /* Return the opcode of the special instruction to be used to load
7031 standard_80387_constant_opcode (rtx x)
7033 switch (standard_80387_constant_p (x))
7057 /* Return the CONST_DOUBLE representing the 80387 constant that is
7058 loaded by the specified special instruction. The argument IDX
7059 matches the return value from standard_80387_constant_p. */
7062 standard_80387_constant_rtx (int idx)
7066 if (! ext_80387_constants_init)
7067 init_ext_80387_constants ();
7083 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7087 /* Return 1 if mode is a valid mode for sse. */
7089 standard_sse_mode_p (enum machine_mode mode)
7106 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7107 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7108 modes and AVX is enabled. */
7111 standard_sse_constant_p (rtx x)
7113 enum machine_mode mode = GET_MODE (x);
7115 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7117 if (vector_all_ones_operand (x, mode))
7119 if (standard_sse_mode_p (mode))
7120 return TARGET_SSE2 ? 2 : -2;
7121 else if (VALID_AVX256_REG_MODE (mode))
7122 return TARGET_AVX ? 3 : -3;
7128 /* Return the opcode of the special instruction to be used to load
7132 standard_sse_constant_opcode (rtx insn, rtx x)
7134 switch (standard_sse_constant_p (x))
7137 switch (get_attr_mode (insn))
7140 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7142 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7144 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7146 return "vxorps\t%x0, %x0, %x0";
7148 return "vxorpd\t%x0, %x0, %x0";
7150 return "vpxor\t%x0, %x0, %x0";
7156 switch (get_attr_mode (insn))
7161 return "vpcmpeqd\t%0, %0, %0";
7167 return "pcmpeqd\t%0, %0";
7172 /* Returns 1 if OP contains a symbol reference */
7175 symbolic_reference_mentioned_p (rtx op)
7180 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7183 fmt = GET_RTX_FORMAT (GET_CODE (op));
7184 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7190 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7191 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7195 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7202 /* Return 1 if it is appropriate to emit `ret' instructions in the
7203 body of a function. Do this only if the epilogue is simple, needing a
7204 couple of insns. Prior to reloading, we can't tell how many registers
7205 must be saved, so return 0 then. Return 0 if there is no frame
7206 marker to de-allocate. */
7209 ix86_can_use_return_insn_p (void)
7211 struct ix86_frame frame;
7213 if (! reload_completed || frame_pointer_needed)
7216 /* Don't allow more than 32 pop, since that's all we can do
7217 with one instruction. */
7218 if (crtl->args.pops_args
7219 && crtl->args.size >= 32768)
7222 ix86_compute_frame_layout (&frame);
7223 return frame.to_allocate == 0 && (frame.nregs + frame.nsseregs) == 0;
7226 /* Value should be nonzero if functions must have frame pointers.
7227 Zero means the frame pointer need not be set up (and parms may
7228 be accessed via the stack pointer) in functions that seem suitable. */
7231 ix86_frame_pointer_required (void)
7233 /* If we accessed previous frames, then the generated code expects
7234 to be able to access the saved ebp value in our frame. */
7235 if (cfun->machine->accesses_prev_frame)
7238 /* Several x86 os'es need a frame pointer for other reasons,
7239 usually pertaining to setjmp. */
7240 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7243 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7244 the frame pointer by default. Turn it back on now if we've not
7245 got a leaf function. */
7246 if (TARGET_OMIT_LEAF_FRAME_POINTER
7247 && (!current_function_is_leaf
7248 || ix86_current_function_calls_tls_descriptor))
7257 /* Record that the current function accesses previous call frames. */
7260 ix86_setup_frame_addresses (void)
7262 cfun->machine->accesses_prev_frame = 1;
7265 #if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7266 # define USE_HIDDEN_LINKONCE 1
7268 # define USE_HIDDEN_LINKONCE 0
7271 static int pic_labels_used;
7273 /* Fills in the label name that should be used for a pc thunk for
7274 the given register. */
7277 get_pc_thunk_name (char name[32], unsigned int regno)
7279 gcc_assert (!TARGET_64BIT);
7281 if (USE_HIDDEN_LINKONCE)
7282 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7284 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7288 /* This function generates code for -fpic that loads %ebx with
7289 the return address of the caller and then returns. */
7292 ix86_file_end (void)
7297 for (regno = 0; regno < 8; ++regno)
7301 if (! ((pic_labels_used >> regno) & 1))
7304 get_pc_thunk_name (name, regno);
7309 switch_to_section (darwin_sections[text_coal_section]);
7310 fputs ("\t.weak_definition\t", asm_out_file);
7311 assemble_name (asm_out_file, name);
7312 fputs ("\n\t.private_extern\t", asm_out_file);
7313 assemble_name (asm_out_file, name);
7314 fputs ("\n", asm_out_file);
7315 ASM_OUTPUT_LABEL (asm_out_file, name);
7319 if (USE_HIDDEN_LINKONCE)
7323 decl = build_decl (FUNCTION_DECL, get_identifier (name),
7325 TREE_PUBLIC (decl) = 1;
7326 TREE_STATIC (decl) = 1;
7327 DECL_ONE_ONLY (decl) = 1;
7329 (*targetm.asm_out.unique_section) (decl, 0);
7330 switch_to_section (get_named_section (decl, NULL, 0));
7332 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7333 fputs ("\t.hidden\t", asm_out_file);
7334 assemble_name (asm_out_file, name);
7335 fputc ('\n', asm_out_file);
7336 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7340 switch_to_section (text_section);
7341 ASM_OUTPUT_LABEL (asm_out_file, name);
7344 xops[0] = gen_rtx_REG (Pmode, regno);
7345 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7346 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7347 output_asm_insn ("ret", xops);
7350 if (NEED_INDICATE_EXEC_STACK)
7351 file_end_indicate_exec_stack ();
7354 /* Emit code for the SET_GOT patterns. */
7357 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7363 if (TARGET_VXWORKS_RTP && flag_pic)
7365 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7366 xops[2] = gen_rtx_MEM (Pmode,
7367 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7368 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7370 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7371 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7372 an unadorned address. */
7373 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7374 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7375 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7379 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7381 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7383 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7386 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7388 output_asm_insn ("call\t%a2", xops);
7391 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7392 is what will be referenced by the Mach-O PIC subsystem. */
7394 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7397 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7398 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7401 output_asm_insn ("pop%z0\t%0", xops);
7406 get_pc_thunk_name (name, REGNO (dest));
7407 pic_labels_used |= 1 << REGNO (dest);
7409 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7410 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7411 output_asm_insn ("call\t%X2", xops);
7412 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7413 is what will be referenced by the Mach-O PIC subsystem. */
7416 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7418 targetm.asm_out.internal_label (asm_out_file, "L",
7419 CODE_LABEL_NUMBER (label));
7426 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7427 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7429 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7434 /* Generate an "push" pattern for input ARG. */
7439 return gen_rtx_SET (VOIDmode,
7441 gen_rtx_PRE_DEC (Pmode,
7442 stack_pointer_rtx)),
7446 /* Return >= 0 if there is an unused call-clobbered register available
7447 for the entire function. */
7450 ix86_select_alt_pic_regnum (void)
7452 if (current_function_is_leaf && !crtl->profile
7453 && !ix86_current_function_calls_tls_descriptor)
7456 /* Can't use the same register for both PIC and DRAP. */
7458 drap = REGNO (crtl->drap_reg);
7461 for (i = 2; i >= 0; --i)
7462 if (i != drap && !df_regs_ever_live_p (i))
7466 return INVALID_REGNUM;
7469 /* Return 1 if we need to save REGNO. */
7471 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7473 if (pic_offset_table_rtx
7474 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7475 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7477 || crtl->calls_eh_return
7478 || crtl->uses_const_pool))
7480 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7485 if (crtl->calls_eh_return && maybe_eh_return)
7490 unsigned test = EH_RETURN_DATA_REGNO (i);
7491 if (test == INVALID_REGNUM)
7499 && regno == REGNO (crtl->drap_reg))
7502 return (df_regs_ever_live_p (regno)
7503 && !call_used_regs[regno]
7504 && !fixed_regs[regno]
7505 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7508 /* Return number of saved general prupose registers. */
7511 ix86_nsaved_regs (void)
7516 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7517 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7522 /* Return number of saved SSE registrers. */
7525 ix86_nsaved_sseregs (void)
7530 if (ix86_cfun_abi () != MS_ABI)
7532 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7533 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7538 /* Given FROM and TO register numbers, say whether this elimination is
7539 allowed. If stack alignment is needed, we can only replace argument
7540 pointer with hard frame pointer, or replace frame pointer with stack
7541 pointer. Otherwise, frame pointer elimination is automatically
7542 handled and all other eliminations are valid. */
7545 ix86_can_eliminate (int from, int to)
7547 if (stack_realign_fp)
7548 return ((from == ARG_POINTER_REGNUM
7549 && to == HARD_FRAME_POINTER_REGNUM)
7550 || (from == FRAME_POINTER_REGNUM
7551 && to == STACK_POINTER_REGNUM));
7553 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7556 /* Return the offset between two registers, one to be eliminated, and the other
7557 its replacement, at the start of a routine. */
7560 ix86_initial_elimination_offset (int from, int to)
7562 struct ix86_frame frame;
7563 ix86_compute_frame_layout (&frame);
7565 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7566 return frame.hard_frame_pointer_offset;
7567 else if (from == FRAME_POINTER_REGNUM
7568 && to == HARD_FRAME_POINTER_REGNUM)
7569 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7572 gcc_assert (to == STACK_POINTER_REGNUM);
7574 if (from == ARG_POINTER_REGNUM)
7575 return frame.stack_pointer_offset;
7577 gcc_assert (from == FRAME_POINTER_REGNUM);
7578 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7582 /* In a dynamically-aligned function, we can't know the offset from
7583 stack pointer to frame pointer, so we must ensure that setjmp
7584 eliminates fp against the hard fp (%ebp) rather than trying to
7585 index from %esp up to the top of the frame across a gap that is
7586 of unknown (at compile-time) size. */
7588 ix86_builtin_setjmp_frame_value (void)
7590 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7593 /* Fill structure ix86_frame about frame of currently computed function. */
7596 ix86_compute_frame_layout (struct ix86_frame *frame)
7598 HOST_WIDE_INT total_size;
7599 unsigned int stack_alignment_needed;
7600 HOST_WIDE_INT offset;
7601 unsigned int preferred_alignment;
7602 HOST_WIDE_INT size = get_frame_size ();
7604 frame->nregs = ix86_nsaved_regs ();
7605 frame->nsseregs = ix86_nsaved_sseregs ();
7608 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7609 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7611 /* MS ABI seem to require stack alignment to be always 16 except for function
7613 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7615 preferred_alignment = 16;
7616 stack_alignment_needed = 16;
7617 crtl->preferred_stack_boundary = 128;
7618 crtl->stack_alignment_needed = 128;
7621 gcc_assert (!size || stack_alignment_needed);
7622 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7623 gcc_assert (preferred_alignment <= stack_alignment_needed);
7625 /* During reload iteration the amount of registers saved can change.
7626 Recompute the value as needed. Do not recompute when amount of registers
7627 didn't change as reload does multiple calls to the function and does not
7628 expect the decision to change within single iteration. */
7629 if (!optimize_function_for_size_p (cfun)
7630 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7632 int count = frame->nregs;
7634 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7635 /* The fast prologue uses move instead of push to save registers. This
7636 is significantly longer, but also executes faster as modern hardware
7637 can execute the moves in parallel, but can't do that for push/pop.
7639 Be careful about choosing what prologue to emit: When function takes
7640 many instructions to execute we may use slow version as well as in
7641 case function is known to be outside hot spot (this is known with
7642 feedback only). Weight the size of function by number of registers
7643 to save as it is cheap to use one or two push instructions but very
7644 slow to use many of them. */
7646 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7647 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7648 || (flag_branch_probabilities
7649 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7650 cfun->machine->use_fast_prologue_epilogue = false;
7652 cfun->machine->use_fast_prologue_epilogue
7653 = !expensive_function_p (count);
7655 if (TARGET_PROLOGUE_USING_MOVE
7656 && cfun->machine->use_fast_prologue_epilogue)
7657 frame->save_regs_using_mov = true;
7659 frame->save_regs_using_mov = false;
7662 /* Skip return address and saved base pointer. */
7663 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7665 frame->hard_frame_pointer_offset = offset;
7667 /* Set offset to aligned because the realigned frame starts from
7669 if (stack_realign_fp)
7670 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7672 /* Register save area */
7673 offset += frame->nregs * UNITS_PER_WORD;
7675 /* Align SSE reg save area. */
7676 if (frame->nsseregs)
7677 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7679 frame->padding0 = 0;
7681 /* SSE register save area. */
7682 offset += frame->padding0 + frame->nsseregs * 16;
7685 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7686 offset += frame->va_arg_size;
7688 /* Align start of frame for local function. */
7689 frame->padding1 = ((offset + stack_alignment_needed - 1)
7690 & -stack_alignment_needed) - offset;
7692 offset += frame->padding1;
7694 /* Frame pointer points here. */
7695 frame->frame_pointer_offset = offset;
7699 /* Add outgoing arguments area. Can be skipped if we eliminated
7700 all the function calls as dead code.
7701 Skipping is however impossible when function calls alloca. Alloca
7702 expander assumes that last crtl->outgoing_args_size
7703 of stack frame are unused. */
7704 if (ACCUMULATE_OUTGOING_ARGS
7705 && (!current_function_is_leaf || cfun->calls_alloca
7706 || ix86_current_function_calls_tls_descriptor))
7708 offset += crtl->outgoing_args_size;
7709 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7712 frame->outgoing_arguments_size = 0;
7714 /* Align stack boundary. Only needed if we're calling another function
7716 if (!current_function_is_leaf || cfun->calls_alloca
7717 || ix86_current_function_calls_tls_descriptor)
7718 frame->padding2 = ((offset + preferred_alignment - 1)
7719 & -preferred_alignment) - offset;
7721 frame->padding2 = 0;
7723 offset += frame->padding2;
7725 /* We've reached end of stack frame. */
7726 frame->stack_pointer_offset = offset;
7728 /* Size prologue needs to allocate. */
7729 frame->to_allocate =
7730 (size + frame->padding1 + frame->padding2
7731 + frame->outgoing_arguments_size + frame->va_arg_size);
7733 if ((!frame->to_allocate && frame->nregs <= 1)
7734 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7735 frame->save_regs_using_mov = false;
7737 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && current_function_sp_is_unchanging
7738 && current_function_is_leaf
7739 && !ix86_current_function_calls_tls_descriptor)
7741 frame->red_zone_size = frame->to_allocate;
7742 if (frame->save_regs_using_mov)
7743 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7744 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7745 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7748 frame->red_zone_size = 0;
7749 frame->to_allocate -= frame->red_zone_size;
7750 frame->stack_pointer_offset -= frame->red_zone_size;
7752 fprintf (stderr, "\n");
7753 fprintf (stderr, "size: %ld\n", (long)size);
7754 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7755 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7756 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7757 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7758 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7759 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7760 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7761 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7762 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7763 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7764 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7765 (long)frame->hard_frame_pointer_offset);
7766 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7767 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7768 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7769 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7773 /* Emit code to save registers in the prologue. */
7776 ix86_emit_save_regs (void)
7781 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7782 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7784 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7785 RTX_FRAME_RELATED_P (insn) = 1;
7789 /* Emit code to save registers using MOV insns. First register
7790 is restored from POINTER + OFFSET. */
7792 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7797 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7798 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7800 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7802 gen_rtx_REG (Pmode, regno));
7803 RTX_FRAME_RELATED_P (insn) = 1;
7804 offset += UNITS_PER_WORD;
7808 /* Emit code to save registers using MOV insns. First register
7809 is restored from POINTER + OFFSET. */
7811 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7817 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7818 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7820 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
7821 set_mem_align (mem, 128);
7822 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
7823 RTX_FRAME_RELATED_P (insn) = 1;
7828 /* Expand prologue or epilogue stack adjustment.
7829 The pattern exist to put a dependency on all ebp-based memory accesses.
7830 STYLE should be negative if instructions should be marked as frame related,
7831 zero if %r11 register is live and cannot be freely used and positive
7835 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
7840 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
7841 else if (x86_64_immediate_operand (offset, DImode))
7842 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
7846 /* r11 is used by indirect sibcall return as well, set before the
7847 epilogue and used after the epilogue. ATM indirect sibcall
7848 shouldn't be used together with huge frame sizes in one
7849 function because of the frame_size check in sibcall.c. */
7851 r11 = gen_rtx_REG (DImode, R11_REG);
7852 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
7854 RTX_FRAME_RELATED_P (insn) = 1;
7855 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
7859 RTX_FRAME_RELATED_P (insn) = 1;
7862 /* Find an available register to be used as dynamic realign argument
7863 pointer regsiter. Such a register will be written in prologue and
7864 used in begin of body, so it must not be
7865 1. parameter passing register.
7867 We reuse static-chain register if it is available. Otherwise, we
7868 use DI for i386 and R13 for x86-64. We chose R13 since it has
7871 Return: the regno of chosen register. */
7874 find_drap_reg (void)
7876 tree decl = cfun->decl;
7880 /* Use R13 for nested function or function need static chain.
7881 Since function with tail call may use any caller-saved
7882 registers in epilogue, DRAP must not use caller-saved
7883 register in such case. */
7884 if ((decl_function_context (decl)
7885 && !DECL_NO_STATIC_CHAIN (decl))
7886 || crtl->tail_call_emit)
7893 /* Use DI for nested function or function need static chain.
7894 Since function with tail call may use any caller-saved
7895 registers in epilogue, DRAP must not use caller-saved
7896 register in such case. */
7897 if ((decl_function_context (decl)
7898 && !DECL_NO_STATIC_CHAIN (decl))
7899 || crtl->tail_call_emit)
7902 /* Reuse static chain register if it isn't used for parameter
7904 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
7905 && !lookup_attribute ("fastcall",
7906 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
7913 /* Update incoming stack boundary and estimated stack alignment. */
7916 ix86_update_stack_boundary (void)
7918 /* Prefer the one specified at command line. */
7919 ix86_incoming_stack_boundary
7920 = (ix86_user_incoming_stack_boundary
7921 ? ix86_user_incoming_stack_boundary
7922 : ix86_default_incoming_stack_boundary);
7924 /* Incoming stack alignment can be changed on individual functions
7925 via force_align_arg_pointer attribute. We use the smallest
7926 incoming stack boundary. */
7927 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
7928 && lookup_attribute (ix86_force_align_arg_pointer_string,
7929 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
7930 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
7932 /* The incoming stack frame has to be aligned at least at
7933 parm_stack_boundary. */
7934 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
7935 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
7937 /* Stack at entrance of main is aligned by runtime. We use the
7938 smallest incoming stack boundary. */
7939 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
7940 && DECL_NAME (current_function_decl)
7941 && MAIN_NAME_P (DECL_NAME (current_function_decl))
7942 && DECL_FILE_SCOPE_P (current_function_decl))
7943 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
7945 /* x86_64 vararg needs 16byte stack alignment for register save
7949 && crtl->stack_alignment_estimated < 128)
7950 crtl->stack_alignment_estimated = 128;
7953 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
7954 needed or an rtx for DRAP otherwise. */
7957 ix86_get_drap_rtx (void)
7959 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
7960 crtl->need_drap = true;
7962 if (stack_realign_drap)
7964 /* Assign DRAP to vDRAP and returns vDRAP */
7965 unsigned int regno = find_drap_reg ();
7970 arg_ptr = gen_rtx_REG (Pmode, regno);
7971 crtl->drap_reg = arg_ptr;
7974 drap_vreg = copy_to_reg (arg_ptr);
7978 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
7979 RTX_FRAME_RELATED_P (insn) = 1;
7986 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
7989 ix86_internal_arg_pointer (void)
7991 return virtual_incoming_args_rtx;
7994 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
7995 This is called from dwarf2out.c to emit call frame instructions
7996 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
7998 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
8000 rtx unspec = SET_SRC (pattern);
8001 gcc_assert (GET_CODE (unspec) == UNSPEC);
8005 case UNSPEC_REG_SAVE:
8006 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
8007 SET_DEST (pattern));
8009 case UNSPEC_DEF_CFA:
8010 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
8011 INTVAL (XVECEXP (unspec, 0, 0)));
8018 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8019 to be generated in correct form. */
8021 ix86_finalize_stack_realign_flags (void)
8023 /* Check if stack realign is really needed after reload, and
8024 stores result in cfun */
8025 unsigned int incoming_stack_boundary
8026 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8027 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8028 unsigned int stack_realign = (incoming_stack_boundary
8029 < (current_function_is_leaf
8030 ? crtl->max_used_stack_slot_alignment
8031 : crtl->stack_alignment_needed));
8033 if (crtl->stack_realign_finalized)
8035 /* After stack_realign_needed is finalized, we can't no longer
8037 gcc_assert (crtl->stack_realign_needed == stack_realign);
8041 crtl->stack_realign_needed = stack_realign;
8042 crtl->stack_realign_finalized = true;
8046 /* Expand the prologue into a bunch of separate insns. */
8049 ix86_expand_prologue (void)
8053 struct ix86_frame frame;
8054 HOST_WIDE_INT allocate;
8056 ix86_finalize_stack_realign_flags ();
8058 /* DRAP should not coexist with stack_realign_fp */
8059 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8061 ix86_compute_frame_layout (&frame);
8063 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8064 of DRAP is needed and stack realignment is really needed after reload */
8065 if (crtl->drap_reg && crtl->stack_realign_needed)
8068 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8069 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8070 ? 0 : UNITS_PER_WORD);
8072 gcc_assert (stack_realign_drap);
8074 /* Grab the argument pointer. */
8075 x = plus_constant (stack_pointer_rtx,
8076 (UNITS_PER_WORD + param_ptr_offset));
8079 /* Only need to push parameter pointer reg if it is caller
8081 if (!call_used_regs[REGNO (crtl->drap_reg)])
8083 /* Push arg pointer reg */
8084 insn = emit_insn (gen_push (y));
8085 RTX_FRAME_RELATED_P (insn) = 1;
8088 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8089 RTX_FRAME_RELATED_P (insn) = 1;
8091 /* Align the stack. */
8092 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8094 GEN_INT (-align_bytes)));
8095 RTX_FRAME_RELATED_P (insn) = 1;
8097 /* Replicate the return address on the stack so that return
8098 address can be reached via (argp - 1) slot. This is needed
8099 to implement macro RETURN_ADDR_RTX and intrinsic function
8100 expand_builtin_return_addr etc. */
8102 x = gen_frame_mem (Pmode,
8103 plus_constant (x, -UNITS_PER_WORD));
8104 insn = emit_insn (gen_push (x));
8105 RTX_FRAME_RELATED_P (insn) = 1;
8108 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8109 slower on all targets. Also sdb doesn't like it. */
8111 if (frame_pointer_needed)
8113 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8114 RTX_FRAME_RELATED_P (insn) = 1;
8116 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8117 RTX_FRAME_RELATED_P (insn) = 1;
8120 if (stack_realign_fp)
8122 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8123 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8125 /* Align the stack. */
8126 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8128 GEN_INT (-align_bytes)));
8129 RTX_FRAME_RELATED_P (insn) = 1;
8132 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8134 if (!frame.save_regs_using_mov)
8135 ix86_emit_save_regs ();
8137 allocate += frame.nregs * UNITS_PER_WORD;
8139 /* When using red zone we may start register saving before allocating
8140 the stack frame saving one cycle of the prologue. However I will
8141 avoid doing this if I am going to have to probe the stack since
8142 at least on x86_64 the stack probe can turn into a call that clobbers
8143 a red zone location */
8144 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8145 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8146 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8147 && !crtl->stack_realign_needed)
8148 ? hard_frame_pointer_rtx
8149 : stack_pointer_rtx,
8150 -frame.nregs * UNITS_PER_WORD);
8154 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8155 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8156 GEN_INT (-allocate), -1);
8159 /* Only valid for Win32. */
8160 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8164 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8166 if (cfun->machine->call_abi == MS_ABI)
8169 eax_live = ix86_eax_live_at_start_p ();
8173 emit_insn (gen_push (eax));
8174 allocate -= UNITS_PER_WORD;
8177 emit_move_insn (eax, GEN_INT (allocate));
8180 insn = gen_allocate_stack_worker_64 (eax, eax);
8182 insn = gen_allocate_stack_worker_32 (eax, eax);
8183 insn = emit_insn (insn);
8184 RTX_FRAME_RELATED_P (insn) = 1;
8185 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8186 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8187 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8188 t, REG_NOTES (insn));
8192 if (frame_pointer_needed)
8193 t = plus_constant (hard_frame_pointer_rtx,
8196 - frame.nregs * UNITS_PER_WORD);
8198 t = plus_constant (stack_pointer_rtx, allocate);
8199 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8203 if (frame.save_regs_using_mov
8204 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8205 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8207 if (!frame_pointer_needed
8208 || !frame.to_allocate
8209 || crtl->stack_realign_needed)
8210 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8212 + frame.nsseregs * 16 + frame.padding0);
8214 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8215 -frame.nregs * UNITS_PER_WORD);
8217 if (!frame_pointer_needed
8218 || !frame.to_allocate
8219 || crtl->stack_realign_needed)
8220 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8223 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8224 - frame.nregs * UNITS_PER_WORD
8225 - frame.nsseregs * 16
8228 pic_reg_used = false;
8229 if (pic_offset_table_rtx
8230 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8233 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8235 if (alt_pic_reg_used != INVALID_REGNUM)
8236 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8238 pic_reg_used = true;
8245 if (ix86_cmodel == CM_LARGE_PIC)
8247 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8248 rtx label = gen_label_rtx ();
8250 LABEL_PRESERVE_P (label) = 1;
8251 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8252 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8253 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8254 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8255 pic_offset_table_rtx, tmp_reg));
8258 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8261 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8264 /* In the pic_reg_used case, make sure that the got load isn't deleted
8265 when mcount needs it. Blockage to avoid call movement across mcount
8266 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8268 if (crtl->profile && pic_reg_used)
8269 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8271 if (crtl->drap_reg && !crtl->stack_realign_needed)
8273 /* vDRAP is setup but after reload it turns out stack realign
8274 isn't necessary, here we will emit prologue to setup DRAP
8275 without stack realign adjustment */
8276 int drap_bp_offset = UNITS_PER_WORD * 2;
8277 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8278 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8281 /* Prevent instructions from being scheduled into register save push
8282 sequence when access to the redzone area is done through frame pointer.
8283 The offset betweeh the frame pointer and the stack pointer is calculated
8284 relative to the value of the stack pointer at the end of the function
8285 prologue, and moving instructions that access redzone area via frame
8286 pointer inside push sequence violates this assumption. */
8287 if (frame_pointer_needed && frame.red_zone_size)
8288 emit_insn (gen_memory_blockage ());
8290 /* Emit cld instruction if stringops are used in the function. */
8291 if (TARGET_CLD && ix86_current_function_needs_cld)
8292 emit_insn (gen_cld ());
8295 /* Emit code to restore saved registers using MOV insns. First register
8296 is restored from POINTER + OFFSET. */
8298 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8299 int maybe_eh_return)
8302 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8304 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8305 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8307 /* Ensure that adjust_address won't be forced to produce pointer
8308 out of range allowed by x86-64 instruction set. */
8309 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8313 r11 = gen_rtx_REG (DImode, R11_REG);
8314 emit_move_insn (r11, GEN_INT (offset));
8315 emit_insn (gen_adddi3 (r11, r11, pointer));
8316 base_address = gen_rtx_MEM (Pmode, r11);
8319 emit_move_insn (gen_rtx_REG (Pmode, regno),
8320 adjust_address (base_address, Pmode, offset));
8321 offset += UNITS_PER_WORD;
8325 /* Emit code to restore saved registers using MOV insns. First register
8326 is restored from POINTER + OFFSET. */
8328 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8329 int maybe_eh_return)
8332 rtx base_address = gen_rtx_MEM (TImode, pointer);
8335 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8336 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8338 /* Ensure that adjust_address won't be forced to produce pointer
8339 out of range allowed by x86-64 instruction set. */
8340 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8344 r11 = gen_rtx_REG (DImode, R11_REG);
8345 emit_move_insn (r11, GEN_INT (offset));
8346 emit_insn (gen_adddi3 (r11, r11, pointer));
8347 base_address = gen_rtx_MEM (TImode, r11);
8350 mem = adjust_address (base_address, TImode, offset);
8351 set_mem_align (mem, 128);
8352 emit_move_insn (gen_rtx_REG (TImode, regno), mem);
8357 /* Restore function stack, frame, and registers. */
8360 ix86_expand_epilogue (int style)
8364 struct ix86_frame frame;
8365 HOST_WIDE_INT offset;
8367 ix86_finalize_stack_realign_flags ();
8369 /* When stack is realigned, SP must be valid. */
8370 sp_valid = (!frame_pointer_needed
8371 || current_function_sp_is_unchanging
8372 || stack_realign_fp);
8374 ix86_compute_frame_layout (&frame);
8376 /* See the comment about red zone and frame
8377 pointer usage in ix86_expand_prologue. */
8378 if (frame_pointer_needed && frame.red_zone_size)
8379 emit_insn (gen_memory_blockage ());
8381 /* Calculate start of saved registers relative to ebp. Special care
8382 must be taken for the normal return case of a function using
8383 eh_return: the eax and edx registers are marked as saved, but not
8384 restored along this path. */
8385 offset = frame.nregs;
8386 if (crtl->calls_eh_return && style != 2)
8388 offset *= -UNITS_PER_WORD;
8389 offset -= frame.nsseregs * 16 + frame.padding0;
8391 /* If we're only restoring one register and sp is not valid then
8392 using a move instruction to restore the register since it's
8393 less work than reloading sp and popping the register.
8395 The default code result in stack adjustment using add/lea instruction,
8396 while this code results in LEAVE instruction (or discrete equivalent),
8397 so it is profitable in some other cases as well. Especially when there
8398 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8399 and there is exactly one register to pop. This heuristic may need some
8400 tuning in future. */
8401 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8402 || (TARGET_EPILOGUE_USING_MOVE
8403 && cfun->machine->use_fast_prologue_epilogue
8404 && ((frame.nregs + frame.nsseregs) > 1 || frame.to_allocate))
8405 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs) && frame.to_allocate)
8406 || (frame_pointer_needed && TARGET_USE_LEAVE
8407 && cfun->machine->use_fast_prologue_epilogue
8408 && (frame.nregs + frame.nsseregs) == 1)
8409 || crtl->calls_eh_return)
8411 /* Restore registers. We can use ebp or esp to address the memory
8412 locations. If both are available, default to ebp, since offsets
8413 are known to be small. Only exception is esp pointing directly
8414 to the end of block of saved registers, where we may simplify
8417 If we are realigning stack with bp and sp, regs restore can't
8418 be addressed by bp. sp must be used instead. */
8420 if (!frame_pointer_needed
8421 || (sp_valid && !frame.to_allocate)
8422 || stack_realign_fp)
8424 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8425 frame.to_allocate, style == 2);
8426 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8428 + frame.nsseregs * 16
8429 + frame.padding0, style == 2);
8433 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8434 offset, style == 2);
8435 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8437 + frame.nsseregs * 16
8438 + frame.padding0, style == 2);
8441 /* eh_return epilogues need %ecx added to the stack pointer. */
8444 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8446 /* Stack align doesn't work with eh_return. */
8447 gcc_assert (!crtl->stack_realign_needed);
8449 if (frame_pointer_needed)
8451 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8452 tmp = plus_constant (tmp, UNITS_PER_WORD);
8453 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8455 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8456 emit_move_insn (hard_frame_pointer_rtx, tmp);
8458 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8463 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8464 tmp = plus_constant (tmp, (frame.to_allocate
8465 + frame.nregs * UNITS_PER_WORD
8466 + frame.nsseregs * 16
8468 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8471 else if (!frame_pointer_needed)
8472 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8473 GEN_INT (frame.to_allocate
8474 + frame.nregs * UNITS_PER_WORD
8475 + frame.nsseregs * 16
8478 /* If not an i386, mov & pop is faster than "leave". */
8479 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8480 || !cfun->machine->use_fast_prologue_epilogue)
8481 emit_insn ((*ix86_gen_leave) ());
8484 pro_epilogue_adjust_stack (stack_pointer_rtx,
8485 hard_frame_pointer_rtx,
8488 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8493 /* First step is to deallocate the stack frame so that we can
8496 If we realign stack with frame pointer, then stack pointer
8497 won't be able to recover via lea $offset(%bp), %sp, because
8498 there is a padding area between bp and sp for realign.
8499 "add $to_allocate, %sp" must be used instead. */
8502 gcc_assert (frame_pointer_needed);
8503 gcc_assert (!stack_realign_fp);
8504 pro_epilogue_adjust_stack (stack_pointer_rtx,
8505 hard_frame_pointer_rtx,
8506 GEN_INT (offset), style);
8507 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8508 frame.to_allocate, style == 2);
8509 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8510 GEN_INT (frame.nsseregs * 16), style);
8512 else if (frame.to_allocate || frame.nsseregs)
8514 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8517 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8518 GEN_INT (frame.to_allocate
8519 + frame.nsseregs * 16
8520 + frame.padding0), style);
8523 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8524 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8525 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8526 if (frame_pointer_needed)
8528 /* Leave results in shorter dependency chains on CPUs that are
8529 able to grok it fast. */
8530 if (TARGET_USE_LEAVE)
8531 emit_insn ((*ix86_gen_leave) ());
8534 /* For stack realigned really happens, recover stack
8535 pointer to hard frame pointer is a must, if not using
8537 if (stack_realign_fp)
8538 pro_epilogue_adjust_stack (stack_pointer_rtx,
8539 hard_frame_pointer_rtx,
8541 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8546 if (crtl->drap_reg && crtl->stack_realign_needed)
8548 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8549 ? 0 : UNITS_PER_WORD);
8550 gcc_assert (stack_realign_drap);
8551 emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8553 GEN_INT (-(UNITS_PER_WORD
8554 + param_ptr_offset))));
8555 if (!call_used_regs[REGNO (crtl->drap_reg)])
8556 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8560 /* Sibcall epilogues don't want a return instruction. */
8564 if (crtl->args.pops_args && crtl->args.size)
8566 rtx popc = GEN_INT (crtl->args.pops_args);
8568 /* i386 can only pop 64K bytes. If asked to pop more, pop
8569 return address, do explicit add, and jump indirectly to the
8572 if (crtl->args.pops_args >= 65536)
8574 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8576 /* There is no "pascal" calling convention in any 64bit ABI. */
8577 gcc_assert (!TARGET_64BIT);
8579 emit_insn (gen_popsi1 (ecx));
8580 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8581 emit_jump_insn (gen_return_indirect_internal (ecx));
8584 emit_jump_insn (gen_return_pop_internal (popc));
8587 emit_jump_insn (gen_return_internal ());
8590 /* Reset from the function's potential modifications. */
8593 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8594 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8596 if (pic_offset_table_rtx)
8597 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8599 /* Mach-O doesn't support labels at the end of objects, so if
8600 it looks like we might want one, insert a NOP. */
8602 rtx insn = get_last_insn ();
8605 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8606 insn = PREV_INSN (insn);
8610 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8611 fputs ("\tnop\n", file);
8617 /* Extract the parts of an RTL expression that is a valid memory address
8618 for an instruction. Return 0 if the structure of the address is
8619 grossly off. Return -1 if the address contains ASHIFT, so it is not
8620 strictly valid, but still used for computing length of lea instruction. */
8623 ix86_decompose_address (rtx addr, struct ix86_address *out)
8625 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8626 rtx base_reg, index_reg;
8627 HOST_WIDE_INT scale = 1;
8628 rtx scale_rtx = NULL_RTX;
8630 enum ix86_address_seg seg = SEG_DEFAULT;
8632 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8634 else if (GET_CODE (addr) == PLUS)
8644 addends[n++] = XEXP (op, 1);
8647 while (GET_CODE (op) == PLUS);
8652 for (i = n; i >= 0; --i)
8655 switch (GET_CODE (op))
8660 index = XEXP (op, 0);
8661 scale_rtx = XEXP (op, 1);
8665 if (XINT (op, 1) == UNSPEC_TP
8666 && TARGET_TLS_DIRECT_SEG_REFS
8667 && seg == SEG_DEFAULT)
8668 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8697 else if (GET_CODE (addr) == MULT)
8699 index = XEXP (addr, 0); /* index*scale */
8700 scale_rtx = XEXP (addr, 1);
8702 else if (GET_CODE (addr) == ASHIFT)
8706 /* We're called for lea too, which implements ashift on occasion. */
8707 index = XEXP (addr, 0);
8708 tmp = XEXP (addr, 1);
8709 if (!CONST_INT_P (tmp))
8711 scale = INTVAL (tmp);
8712 if ((unsigned HOST_WIDE_INT) scale > 3)
8718 disp = addr; /* displacement */
8720 /* Extract the integral value of scale. */
8723 if (!CONST_INT_P (scale_rtx))
8725 scale = INTVAL (scale_rtx);
8728 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8729 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8731 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8732 if (base_reg && index_reg && scale == 1
8733 && (index_reg == arg_pointer_rtx
8734 || index_reg == frame_pointer_rtx
8735 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8738 tmp = base, base = index, index = tmp;
8739 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8742 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8743 if ((base_reg == hard_frame_pointer_rtx
8744 || base_reg == frame_pointer_rtx
8745 || base_reg == arg_pointer_rtx) && !disp)
8748 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8749 Avoid this by transforming to [%esi+0].
8750 Reload calls address legitimization without cfun defined, so we need
8751 to test cfun for being non-NULL. */
8752 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
8753 && base_reg && !index_reg && !disp
8755 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
8758 /* Special case: encode reg+reg instead of reg*2. */
8759 if (!base && index && scale && scale == 2)
8760 base = index, base_reg = index_reg, scale = 1;
8762 /* Special case: scaling cannot be encoded without base or displacement. */
8763 if (!base && !disp && index && scale != 1)
8775 /* Return cost of the memory address x.
8776 For i386, it is better to use a complex address than let gcc copy
8777 the address into a reg and make a new pseudo. But not if the address
8778 requires to two regs - that would mean more pseudos with longer
8781 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8783 struct ix86_address parts;
8785 int ok = ix86_decompose_address (x, &parts);
8789 if (parts.base && GET_CODE (parts.base) == SUBREG)
8790 parts.base = SUBREG_REG (parts.base);
8791 if (parts.index && GET_CODE (parts.index) == SUBREG)
8792 parts.index = SUBREG_REG (parts.index);
8794 /* Attempt to minimize number of registers in the address. */
8796 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8798 && (!REG_P (parts.index)
8799 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8803 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8805 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8806 && parts.base != parts.index)
8809 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8810 since it's predecode logic can't detect the length of instructions
8811 and it degenerates to vector decoded. Increase cost of such
8812 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8813 to split such addresses or even refuse such addresses at all.
8815 Following addressing modes are affected:
8820 The first and last case may be avoidable by explicitly coding the zero in
8821 memory address, but I don't have AMD-K6 machine handy to check this
8825 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8826 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8827 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
8833 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8834 this is used for to form addresses to local data when -fPIC is in
8838 darwin_local_data_pic (rtx disp)
8840 return (GET_CODE (disp) == UNSPEC
8841 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
8844 /* Determine if a given RTX is a valid constant. We already know this
8845 satisfies CONSTANT_P. */
8848 legitimate_constant_p (rtx x)
8850 switch (GET_CODE (x))
8855 if (GET_CODE (x) == PLUS)
8857 if (!CONST_INT_P (XEXP (x, 1)))
8862 if (TARGET_MACHO && darwin_local_data_pic (x))
8865 /* Only some unspecs are valid as "constants". */
8866 if (GET_CODE (x) == UNSPEC)
8867 switch (XINT (x, 1))
8872 return TARGET_64BIT;
8875 x = XVECEXP (x, 0, 0);
8876 return (GET_CODE (x) == SYMBOL_REF
8877 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8879 x = XVECEXP (x, 0, 0);
8880 return (GET_CODE (x) == SYMBOL_REF
8881 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
8886 /* We must have drilled down to a symbol. */
8887 if (GET_CODE (x) == LABEL_REF)
8889 if (GET_CODE (x) != SYMBOL_REF)
8894 /* TLS symbols are never valid. */
8895 if (SYMBOL_REF_TLS_MODEL (x))
8898 /* DLLIMPORT symbols are never valid. */
8899 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
8900 && SYMBOL_REF_DLLIMPORT_P (x))
8905 if (GET_MODE (x) == TImode
8906 && x != CONST0_RTX (TImode)
8912 if (x == CONST0_RTX (GET_MODE (x)))
8920 /* Otherwise we handle everything else in the move patterns. */
8924 /* Determine if it's legal to put X into the constant pool. This
8925 is not possible for the address of thread-local symbols, which
8926 is checked above. */
8929 ix86_cannot_force_const_mem (rtx x)
8931 /* We can always put integral constants and vectors in memory. */
8932 switch (GET_CODE (x))
8942 return !legitimate_constant_p (x);
8945 /* Determine if a given RTX is a valid constant address. */
8948 constant_address_p (rtx x)
8950 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
8953 /* Nonzero if the constant value X is a legitimate general operand
8954 when generating PIC code. It is given that flag_pic is on and
8955 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
8958 legitimate_pic_operand_p (rtx x)
8962 switch (GET_CODE (x))
8965 inner = XEXP (x, 0);
8966 if (GET_CODE (inner) == PLUS
8967 && CONST_INT_P (XEXP (inner, 1)))
8968 inner = XEXP (inner, 0);
8970 /* Only some unspecs are valid as "constants". */
8971 if (GET_CODE (inner) == UNSPEC)
8972 switch (XINT (inner, 1))
8977 return TARGET_64BIT;
8979 x = XVECEXP (inner, 0, 0);
8980 return (GET_CODE (x) == SYMBOL_REF
8981 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
8982 case UNSPEC_MACHOPIC_OFFSET:
8983 return legitimate_pic_address_disp_p (x);
8991 return legitimate_pic_address_disp_p (x);
8998 /* Determine if a given CONST RTX is a valid memory displacement
9002 legitimate_pic_address_disp_p (rtx disp)
9006 /* In 64bit mode we can allow direct addresses of symbols and labels
9007 when they are not dynamic symbols. */
9010 rtx op0 = disp, op1;
9012 switch (GET_CODE (disp))
9018 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9020 op0 = XEXP (XEXP (disp, 0), 0);
9021 op1 = XEXP (XEXP (disp, 0), 1);
9022 if (!CONST_INT_P (op1)
9023 || INTVAL (op1) >= 16*1024*1024
9024 || INTVAL (op1) < -16*1024*1024)
9026 if (GET_CODE (op0) == LABEL_REF)
9028 if (GET_CODE (op0) != SYMBOL_REF)
9033 /* TLS references should always be enclosed in UNSPEC. */
9034 if (SYMBOL_REF_TLS_MODEL (op0))
9036 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9037 && ix86_cmodel != CM_LARGE_PIC)
9045 if (GET_CODE (disp) != CONST)
9047 disp = XEXP (disp, 0);
9051 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9052 of GOT tables. We should not need these anyway. */
9053 if (GET_CODE (disp) != UNSPEC
9054 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9055 && XINT (disp, 1) != UNSPEC_GOTOFF
9056 && XINT (disp, 1) != UNSPEC_PLTOFF))
9059 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9060 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9066 if (GET_CODE (disp) == PLUS)
9068 if (!CONST_INT_P (XEXP (disp, 1)))
9070 disp = XEXP (disp, 0);
9074 if (TARGET_MACHO && darwin_local_data_pic (disp))
9077 if (GET_CODE (disp) != UNSPEC)
9080 switch (XINT (disp, 1))
9085 /* We need to check for both symbols and labels because VxWorks loads
9086 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9088 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9089 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9091 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9092 While ABI specify also 32bit relocation but we don't produce it in
9093 small PIC model at all. */
9094 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9095 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9097 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9099 case UNSPEC_GOTTPOFF:
9100 case UNSPEC_GOTNTPOFF:
9101 case UNSPEC_INDNTPOFF:
9104 disp = XVECEXP (disp, 0, 0);
9105 return (GET_CODE (disp) == SYMBOL_REF
9106 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9108 disp = XVECEXP (disp, 0, 0);
9109 return (GET_CODE (disp) == SYMBOL_REF
9110 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9112 disp = XVECEXP (disp, 0, 0);
9113 return (GET_CODE (disp) == SYMBOL_REF
9114 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9120 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
9121 memory address for an instruction. The MODE argument is the machine mode
9122 for the MEM expression that wants to use this address.
9124 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9125 convert common non-canonical forms to canonical form so that they will
9129 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9130 rtx addr, int strict)
9132 struct ix86_address parts;
9133 rtx base, index, disp;
9134 HOST_WIDE_INT scale;
9135 const char *reason = NULL;
9136 rtx reason_rtx = NULL_RTX;
9138 if (ix86_decompose_address (addr, &parts) <= 0)
9140 reason = "decomposition failed";
9145 index = parts.index;
9147 scale = parts.scale;
9149 /* Validate base register.
9151 Don't allow SUBREG's that span more than a word here. It can lead to spill
9152 failures when the base is one word out of a two word structure, which is
9153 represented internally as a DImode int. */
9162 else if (GET_CODE (base) == SUBREG
9163 && REG_P (SUBREG_REG (base))
9164 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9166 reg = SUBREG_REG (base);
9169 reason = "base is not a register";
9173 if (GET_MODE (base) != Pmode)
9175 reason = "base is not in Pmode";
9179 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9180 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9182 reason = "base is not valid";
9187 /* Validate index register.
9189 Don't allow SUBREG's that span more than a word here -- same as above. */
9198 else if (GET_CODE (index) == SUBREG
9199 && REG_P (SUBREG_REG (index))
9200 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9202 reg = SUBREG_REG (index);
9205 reason = "index is not a register";
9209 if (GET_MODE (index) != Pmode)
9211 reason = "index is not in Pmode";
9215 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9216 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9218 reason = "index is not valid";
9223 /* Validate scale factor. */
9226 reason_rtx = GEN_INT (scale);
9229 reason = "scale without index";
9233 if (scale != 2 && scale != 4 && scale != 8)
9235 reason = "scale is not a valid multiplier";
9240 /* Validate displacement. */
9245 if (GET_CODE (disp) == CONST
9246 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9247 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9248 switch (XINT (XEXP (disp, 0), 1))
9250 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9251 used. While ABI specify also 32bit relocations, we don't produce
9252 them at all and use IP relative instead. */
9255 gcc_assert (flag_pic);
9257 goto is_legitimate_pic;
9258 reason = "64bit address unspec";
9261 case UNSPEC_GOTPCREL:
9262 gcc_assert (flag_pic);
9263 goto is_legitimate_pic;
9265 case UNSPEC_GOTTPOFF:
9266 case UNSPEC_GOTNTPOFF:
9267 case UNSPEC_INDNTPOFF:
9273 reason = "invalid address unspec";
9277 else if (SYMBOLIC_CONST (disp)
9281 && MACHOPIC_INDIRECT
9282 && !machopic_operand_p (disp)
9288 if (TARGET_64BIT && (index || base))
9290 /* foo@dtpoff(%rX) is ok. */
9291 if (GET_CODE (disp) != CONST
9292 || GET_CODE (XEXP (disp, 0)) != PLUS
9293 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9294 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9295 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9296 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9298 reason = "non-constant pic memory reference";
9302 else if (! legitimate_pic_address_disp_p (disp))
9304 reason = "displacement is an invalid pic construct";
9308 /* This code used to verify that a symbolic pic displacement
9309 includes the pic_offset_table_rtx register.
9311 While this is good idea, unfortunately these constructs may
9312 be created by "adds using lea" optimization for incorrect
9321 This code is nonsensical, but results in addressing
9322 GOT table with pic_offset_table_rtx base. We can't
9323 just refuse it easily, since it gets matched by
9324 "addsi3" pattern, that later gets split to lea in the
9325 case output register differs from input. While this
9326 can be handled by separate addsi pattern for this case
9327 that never results in lea, this seems to be easier and
9328 correct fix for crash to disable this test. */
9330 else if (GET_CODE (disp) != LABEL_REF
9331 && !CONST_INT_P (disp)
9332 && (GET_CODE (disp) != CONST
9333 || !legitimate_constant_p (disp))
9334 && (GET_CODE (disp) != SYMBOL_REF
9335 || !legitimate_constant_p (disp)))
9337 reason = "displacement is not constant";
9340 else if (TARGET_64BIT
9341 && !x86_64_immediate_operand (disp, VOIDmode))
9343 reason = "displacement is out of range";
9348 /* Everything looks valid. */
9355 /* Return a unique alias set for the GOT. */
9357 static alias_set_type
9358 ix86_GOT_alias_set (void)
9360 static alias_set_type set = -1;
9362 set = new_alias_set ();
9366 /* Return a legitimate reference for ORIG (an address) using the
9367 register REG. If REG is 0, a new pseudo is generated.
9369 There are two types of references that must be handled:
9371 1. Global data references must load the address from the GOT, via
9372 the PIC reg. An insn is emitted to do this load, and the reg is
9375 2. Static data references, constant pool addresses, and code labels
9376 compute the address as an offset from the GOT, whose base is in
9377 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9378 differentiate them from global data objects. The returned
9379 address is the PIC reg + an unspec constant.
9381 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9382 reg also appears in the address. */
9385 legitimize_pic_address (rtx orig, rtx reg)
9392 if (TARGET_MACHO && !TARGET_64BIT)
9395 reg = gen_reg_rtx (Pmode);
9396 /* Use the generic Mach-O PIC machinery. */
9397 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9401 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9403 else if (TARGET_64BIT
9404 && ix86_cmodel != CM_SMALL_PIC
9405 && gotoff_operand (addr, Pmode))
9408 /* This symbol may be referenced via a displacement from the PIC
9409 base address (@GOTOFF). */
9411 if (reload_in_progress)
9412 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9413 if (GET_CODE (addr) == CONST)
9414 addr = XEXP (addr, 0);
9415 if (GET_CODE (addr) == PLUS)
9417 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9419 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9422 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9423 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9425 tmpreg = gen_reg_rtx (Pmode);
9428 emit_move_insn (tmpreg, new_rtx);
9432 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9433 tmpreg, 1, OPTAB_DIRECT);
9436 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9438 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9440 /* This symbol may be referenced via a displacement from the PIC
9441 base address (@GOTOFF). */
9443 if (reload_in_progress)
9444 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9445 if (GET_CODE (addr) == CONST)
9446 addr = XEXP (addr, 0);
9447 if (GET_CODE (addr) == PLUS)
9449 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9451 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9454 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9455 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9456 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9460 emit_move_insn (reg, new_rtx);
9464 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9465 /* We can't use @GOTOFF for text labels on VxWorks;
9466 see gotoff_operand. */
9467 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9469 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9471 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9472 return legitimize_dllimport_symbol (addr, true);
9473 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9474 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9475 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9477 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9478 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9482 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9484 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9485 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9486 new_rtx = gen_const_mem (Pmode, new_rtx);
9487 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9490 reg = gen_reg_rtx (Pmode);
9491 /* Use directly gen_movsi, otherwise the address is loaded
9492 into register for CSE. We don't want to CSE this addresses,
9493 instead we CSE addresses from the GOT table, so skip this. */
9494 emit_insn (gen_movsi (reg, new_rtx));
9499 /* This symbol must be referenced via a load from the
9500 Global Offset Table (@GOT). */
9502 if (reload_in_progress)
9503 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9504 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9505 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9507 new_rtx = force_reg (Pmode, new_rtx);
9508 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9509 new_rtx = gen_const_mem (Pmode, new_rtx);
9510 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9513 reg = gen_reg_rtx (Pmode);
9514 emit_move_insn (reg, new_rtx);
9520 if (CONST_INT_P (addr)
9521 && !x86_64_immediate_operand (addr, VOIDmode))
9525 emit_move_insn (reg, addr);
9529 new_rtx = force_reg (Pmode, addr);
9531 else if (GET_CODE (addr) == CONST)
9533 addr = XEXP (addr, 0);
9535 /* We must match stuff we generate before. Assume the only
9536 unspecs that can get here are ours. Not that we could do
9537 anything with them anyway.... */
9538 if (GET_CODE (addr) == UNSPEC
9539 || (GET_CODE (addr) == PLUS
9540 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9542 gcc_assert (GET_CODE (addr) == PLUS);
9544 if (GET_CODE (addr) == PLUS)
9546 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9548 /* Check first to see if this is a constant offset from a @GOTOFF
9549 symbol reference. */
9550 if (gotoff_operand (op0, Pmode)
9551 && CONST_INT_P (op1))
9555 if (reload_in_progress)
9556 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9557 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9559 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9560 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9561 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9565 emit_move_insn (reg, new_rtx);
9571 if (INTVAL (op1) < -16*1024*1024
9572 || INTVAL (op1) >= 16*1024*1024)
9574 if (!x86_64_immediate_operand (op1, Pmode))
9575 op1 = force_reg (Pmode, op1);
9576 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9582 base = legitimize_pic_address (XEXP (addr, 0), reg);
9583 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9584 base == reg ? NULL_RTX : reg);
9586 if (CONST_INT_P (new_rtx))
9587 new_rtx = plus_constant (base, INTVAL (new_rtx));
9590 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9592 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9593 new_rtx = XEXP (new_rtx, 1);
9595 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9603 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9606 get_thread_pointer (int to_reg)
9610 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9614 reg = gen_reg_rtx (Pmode);
9615 insn = gen_rtx_SET (VOIDmode, reg, tp);
9616 insn = emit_insn (insn);
9621 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9622 false if we expect this to be used for a memory address and true if
9623 we expect to load the address into a register. */
9626 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9628 rtx dest, base, off, pic, tp;
9633 case TLS_MODEL_GLOBAL_DYNAMIC:
9634 dest = gen_reg_rtx (Pmode);
9635 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9637 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9639 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9642 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9643 insns = get_insns ();
9646 RTL_CONST_CALL_P (insns) = 1;
9647 emit_libcall_block (insns, dest, rax, x);
9649 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9650 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9652 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9654 if (TARGET_GNU2_TLS)
9656 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9658 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9662 case TLS_MODEL_LOCAL_DYNAMIC:
9663 base = gen_reg_rtx (Pmode);
9664 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9666 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9668 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9671 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9672 insns = get_insns ();
9675 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9676 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9677 RTL_CONST_CALL_P (insns) = 1;
9678 emit_libcall_block (insns, base, rax, note);
9680 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9681 emit_insn (gen_tls_local_dynamic_base_64 (base));
9683 emit_insn (gen_tls_local_dynamic_base_32 (base));
9685 if (TARGET_GNU2_TLS)
9687 rtx x = ix86_tls_module_base ();
9689 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9690 gen_rtx_MINUS (Pmode, x, tp));
9693 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9694 off = gen_rtx_CONST (Pmode, off);
9696 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9698 if (TARGET_GNU2_TLS)
9700 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9702 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9707 case TLS_MODEL_INITIAL_EXEC:
9711 type = UNSPEC_GOTNTPOFF;
9715 if (reload_in_progress)
9716 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9717 pic = pic_offset_table_rtx;
9718 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9720 else if (!TARGET_ANY_GNU_TLS)
9722 pic = gen_reg_rtx (Pmode);
9723 emit_insn (gen_set_got (pic));
9724 type = UNSPEC_GOTTPOFF;
9729 type = UNSPEC_INDNTPOFF;
9732 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9733 off = gen_rtx_CONST (Pmode, off);
9735 off = gen_rtx_PLUS (Pmode, pic, off);
9736 off = gen_const_mem (Pmode, off);
9737 set_mem_alias_set (off, ix86_GOT_alias_set ());
9739 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9741 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9742 off = force_reg (Pmode, off);
9743 return gen_rtx_PLUS (Pmode, base, off);
9747 base = get_thread_pointer (true);
9748 dest = gen_reg_rtx (Pmode);
9749 emit_insn (gen_subsi3 (dest, base, off));
9753 case TLS_MODEL_LOCAL_EXEC:
9754 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9755 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9756 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9757 off = gen_rtx_CONST (Pmode, off);
9759 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9761 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9762 return gen_rtx_PLUS (Pmode, base, off);
9766 base = get_thread_pointer (true);
9767 dest = gen_reg_rtx (Pmode);
9768 emit_insn (gen_subsi3 (dest, base, off));
9779 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9782 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9783 htab_t dllimport_map;
9786 get_dllimport_decl (tree decl)
9788 struct tree_map *h, in;
9792 size_t namelen, prefixlen;
9798 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9800 in.hash = htab_hash_pointer (decl);
9801 in.base.from = decl;
9802 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9803 h = (struct tree_map *) *loc;
9807 *loc = h = GGC_NEW (struct tree_map);
9809 h->base.from = decl;
9810 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9811 DECL_ARTIFICIAL (to) = 1;
9812 DECL_IGNORED_P (to) = 1;
9813 DECL_EXTERNAL (to) = 1;
9814 TREE_READONLY (to) = 1;
9816 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9817 name = targetm.strip_name_encoding (name);
9818 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9819 ? "*__imp_" : "*__imp__";
9820 namelen = strlen (name);
9821 prefixlen = strlen (prefix);
9822 imp_name = (char *) alloca (namelen + prefixlen + 1);
9823 memcpy (imp_name, prefix, prefixlen);
9824 memcpy (imp_name + prefixlen, name, namelen + 1);
9826 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9827 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9828 SET_SYMBOL_REF_DECL (rtl, to);
9829 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
9831 rtl = gen_const_mem (Pmode, rtl);
9832 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
9834 SET_DECL_RTL (to, rtl);
9835 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
9840 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9841 true if we require the result be a register. */
9844 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
9849 gcc_assert (SYMBOL_REF_DECL (symbol));
9850 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
9852 x = DECL_RTL (imp_decl);
9854 x = force_reg (Pmode, x);
9858 /* Try machine-dependent ways of modifying an illegitimate address
9859 to be legitimate. If we find one, return the new, valid address.
9860 This macro is used in only one place: `memory_address' in explow.c.
9862 OLDX is the address as it was before break_out_memory_refs was called.
9863 In some cases it is useful to look at this to decide what needs to be done.
9865 MODE and WIN are passed so that this macro can use
9866 GO_IF_LEGITIMATE_ADDRESS.
9868 It is always safe for this macro to do nothing. It exists to recognize
9869 opportunities to optimize the output.
9871 For the 80386, we handle X+REG by loading X into a register R and
9872 using R+REG. R will go in a general reg and indexing will be used.
9873 However, if REG is a broken-out memory address or multiplication,
9874 nothing needs to be done because REG can certainly go in a general reg.
9876 When -fpic is used, special handling is needed for symbolic references.
9877 See comments by legitimize_pic_address in i386.c for details. */
9880 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
9885 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
9887 return legitimize_tls_address (x, (enum tls_model) log, false);
9888 if (GET_CODE (x) == CONST
9889 && GET_CODE (XEXP (x, 0)) == PLUS
9890 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9891 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
9893 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
9894 (enum tls_model) log, false);
9895 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9898 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9900 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
9901 return legitimize_dllimport_symbol (x, true);
9902 if (GET_CODE (x) == CONST
9903 && GET_CODE (XEXP (x, 0)) == PLUS
9904 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9905 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
9907 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
9908 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
9912 if (flag_pic && SYMBOLIC_CONST (x))
9913 return legitimize_pic_address (x, 0);
9915 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
9916 if (GET_CODE (x) == ASHIFT
9917 && CONST_INT_P (XEXP (x, 1))
9918 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
9921 log = INTVAL (XEXP (x, 1));
9922 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
9923 GEN_INT (1 << log));
9926 if (GET_CODE (x) == PLUS)
9928 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
9930 if (GET_CODE (XEXP (x, 0)) == ASHIFT
9931 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9932 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
9935 log = INTVAL (XEXP (XEXP (x, 0), 1));
9936 XEXP (x, 0) = gen_rtx_MULT (Pmode,
9937 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
9938 GEN_INT (1 << log));
9941 if (GET_CODE (XEXP (x, 1)) == ASHIFT
9942 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
9943 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
9946 log = INTVAL (XEXP (XEXP (x, 1), 1));
9947 XEXP (x, 1) = gen_rtx_MULT (Pmode,
9948 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
9949 GEN_INT (1 << log));
9952 /* Put multiply first if it isn't already. */
9953 if (GET_CODE (XEXP (x, 1)) == MULT)
9955 rtx tmp = XEXP (x, 0);
9956 XEXP (x, 0) = XEXP (x, 1);
9961 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
9962 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
9963 created by virtual register instantiation, register elimination, and
9964 similar optimizations. */
9965 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
9968 x = gen_rtx_PLUS (Pmode,
9969 gen_rtx_PLUS (Pmode, XEXP (x, 0),
9970 XEXP (XEXP (x, 1), 0)),
9971 XEXP (XEXP (x, 1), 1));
9975 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
9976 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
9977 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
9978 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
9979 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
9980 && CONSTANT_P (XEXP (x, 1)))
9983 rtx other = NULL_RTX;
9985 if (CONST_INT_P (XEXP (x, 1)))
9987 constant = XEXP (x, 1);
9988 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
9990 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
9992 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
9993 other = XEXP (x, 1);
10001 x = gen_rtx_PLUS (Pmode,
10002 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10003 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10004 plus_constant (other, INTVAL (constant)));
10008 if (changed && legitimate_address_p (mode, x, FALSE))
10011 if (GET_CODE (XEXP (x, 0)) == MULT)
10014 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10017 if (GET_CODE (XEXP (x, 1)) == MULT)
10020 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10024 && REG_P (XEXP (x, 1))
10025 && REG_P (XEXP (x, 0)))
10028 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10031 x = legitimize_pic_address (x, 0);
10034 if (changed && legitimate_address_p (mode, x, FALSE))
10037 if (REG_P (XEXP (x, 0)))
10039 rtx temp = gen_reg_rtx (Pmode);
10040 rtx val = force_operand (XEXP (x, 1), temp);
10042 emit_move_insn (temp, val);
10044 XEXP (x, 1) = temp;
10048 else if (REG_P (XEXP (x, 1)))
10050 rtx temp = gen_reg_rtx (Pmode);
10051 rtx val = force_operand (XEXP (x, 0), temp);
10053 emit_move_insn (temp, val);
10055 XEXP (x, 0) = temp;
10063 /* Print an integer constant expression in assembler syntax. Addition
10064 and subtraction are the only arithmetic that may appear in these
10065 expressions. FILE is the stdio stream to write to, X is the rtx, and
10066 CODE is the operand print code from the output string. */
10069 output_pic_addr_const (FILE *file, rtx x, int code)
10073 switch (GET_CODE (x))
10076 gcc_assert (flag_pic);
10081 if (! TARGET_MACHO || TARGET_64BIT)
10082 output_addr_const (file, x);
10085 const char *name = XSTR (x, 0);
10087 /* Mark the decl as referenced so that cgraph will
10088 output the function. */
10089 if (SYMBOL_REF_DECL (x))
10090 mark_decl_referenced (SYMBOL_REF_DECL (x));
10093 if (MACHOPIC_INDIRECT
10094 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10095 name = machopic_indirection_name (x, /*stub_p=*/true);
10097 assemble_name (file, name);
10099 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10100 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10101 fputs ("@PLT", file);
10108 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10109 assemble_name (asm_out_file, buf);
10113 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10117 /* This used to output parentheses around the expression,
10118 but that does not work on the 386 (either ATT or BSD assembler). */
10119 output_pic_addr_const (file, XEXP (x, 0), code);
10123 if (GET_MODE (x) == VOIDmode)
10125 /* We can use %d if the number is <32 bits and positive. */
10126 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10127 fprintf (file, "0x%lx%08lx",
10128 (unsigned long) CONST_DOUBLE_HIGH (x),
10129 (unsigned long) CONST_DOUBLE_LOW (x));
10131 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10134 /* We can't handle floating point constants;
10135 PRINT_OPERAND must handle them. */
10136 output_operand_lossage ("floating constant misused");
10140 /* Some assemblers need integer constants to appear first. */
10141 if (CONST_INT_P (XEXP (x, 0)))
10143 output_pic_addr_const (file, XEXP (x, 0), code);
10145 output_pic_addr_const (file, XEXP (x, 1), code);
10149 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10150 output_pic_addr_const (file, XEXP (x, 1), code);
10152 output_pic_addr_const (file, XEXP (x, 0), code);
10158 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10159 output_pic_addr_const (file, XEXP (x, 0), code);
10161 output_pic_addr_const (file, XEXP (x, 1), code);
10163 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10167 gcc_assert (XVECLEN (x, 0) == 1);
10168 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10169 switch (XINT (x, 1))
10172 fputs ("@GOT", file);
10174 case UNSPEC_GOTOFF:
10175 fputs ("@GOTOFF", file);
10177 case UNSPEC_PLTOFF:
10178 fputs ("@PLTOFF", file);
10180 case UNSPEC_GOTPCREL:
10181 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10182 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10184 case UNSPEC_GOTTPOFF:
10185 /* FIXME: This might be @TPOFF in Sun ld too. */
10186 fputs ("@GOTTPOFF", file);
10189 fputs ("@TPOFF", file);
10191 case UNSPEC_NTPOFF:
10193 fputs ("@TPOFF", file);
10195 fputs ("@NTPOFF", file);
10197 case UNSPEC_DTPOFF:
10198 fputs ("@DTPOFF", file);
10200 case UNSPEC_GOTNTPOFF:
10202 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10203 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10205 fputs ("@GOTNTPOFF", file);
10207 case UNSPEC_INDNTPOFF:
10208 fputs ("@INDNTPOFF", file);
10211 case UNSPEC_MACHOPIC_OFFSET:
10213 machopic_output_function_base_name (file);
10217 output_operand_lossage ("invalid UNSPEC as operand");
10223 output_operand_lossage ("invalid expression as operand");
10227 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10228 We need to emit DTP-relative relocations. */
10230 static void ATTRIBUTE_UNUSED
10231 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10233 fputs (ASM_LONG, file);
10234 output_addr_const (file, x);
10235 fputs ("@DTPOFF", file);
10241 fputs (", 0", file);
10244 gcc_unreachable ();
10248 /* Return true if X is a representation of the PIC register. This copes
10249 with calls from ix86_find_base_term, where the register might have
10250 been replaced by a cselib value. */
10253 ix86_pic_register_p (rtx x)
10255 if (GET_CODE (x) == VALUE)
10256 return (pic_offset_table_rtx
10257 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10259 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10262 /* In the name of slightly smaller debug output, and to cater to
10263 general assembler lossage, recognize PIC+GOTOFF and turn it back
10264 into a direct symbol reference.
10266 On Darwin, this is necessary to avoid a crash, because Darwin
10267 has a different PIC label for each routine but the DWARF debugging
10268 information is not associated with any particular routine, so it's
10269 necessary to remove references to the PIC label from RTL stored by
10270 the DWARF output code. */
10273 ix86_delegitimize_address (rtx orig_x)
10276 /* reg_addend is NULL or a multiple of some register. */
10277 rtx reg_addend = NULL_RTX;
10278 /* const_addend is NULL or a const_int. */
10279 rtx const_addend = NULL_RTX;
10280 /* This is the result, or NULL. */
10281 rtx result = NULL_RTX;
10288 if (GET_CODE (x) != CONST
10289 || GET_CODE (XEXP (x, 0)) != UNSPEC
10290 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10291 || !MEM_P (orig_x))
10293 return XVECEXP (XEXP (x, 0), 0, 0);
10296 if (GET_CODE (x) != PLUS
10297 || GET_CODE (XEXP (x, 1)) != CONST)
10300 if (ix86_pic_register_p (XEXP (x, 0)))
10301 /* %ebx + GOT/GOTOFF */
10303 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10305 /* %ebx + %reg * scale + GOT/GOTOFF */
10306 reg_addend = XEXP (x, 0);
10307 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10308 reg_addend = XEXP (reg_addend, 1);
10309 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10310 reg_addend = XEXP (reg_addend, 0);
10313 if (!REG_P (reg_addend)
10314 && GET_CODE (reg_addend) != MULT
10315 && GET_CODE (reg_addend) != ASHIFT)
10321 x = XEXP (XEXP (x, 1), 0);
10322 if (GET_CODE (x) == PLUS
10323 && CONST_INT_P (XEXP (x, 1)))
10325 const_addend = XEXP (x, 1);
10329 if (GET_CODE (x) == UNSPEC
10330 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10331 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10332 result = XVECEXP (x, 0, 0);
10334 if (TARGET_MACHO && darwin_local_data_pic (x)
10335 && !MEM_P (orig_x))
10336 result = XVECEXP (x, 0, 0);
10342 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10344 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10348 /* If X is a machine specific address (i.e. a symbol or label being
10349 referenced as a displacement from the GOT implemented using an
10350 UNSPEC), then return the base term. Otherwise return X. */
10353 ix86_find_base_term (rtx x)
10359 if (GET_CODE (x) != CONST)
10361 term = XEXP (x, 0);
10362 if (GET_CODE (term) == PLUS
10363 && (CONST_INT_P (XEXP (term, 1))
10364 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10365 term = XEXP (term, 0);
10366 if (GET_CODE (term) != UNSPEC
10367 || XINT (term, 1) != UNSPEC_GOTPCREL)
10370 return XVECEXP (term, 0, 0);
10373 return ix86_delegitimize_address (x);
10377 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10378 int fp, FILE *file)
10380 const char *suffix;
10382 if (mode == CCFPmode || mode == CCFPUmode)
10384 enum rtx_code second_code, bypass_code;
10385 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10386 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10387 code = ix86_fp_compare_code_to_integer (code);
10391 code = reverse_condition (code);
10442 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10446 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10447 Those same assemblers have the same but opposite lossage on cmov. */
10448 if (mode == CCmode)
10449 suffix = fp ? "nbe" : "a";
10450 else if (mode == CCCmode)
10453 gcc_unreachable ();
10469 gcc_unreachable ();
10473 gcc_assert (mode == CCmode || mode == CCCmode);
10490 gcc_unreachable ();
10494 /* ??? As above. */
10495 gcc_assert (mode == CCmode || mode == CCCmode);
10496 suffix = fp ? "nb" : "ae";
10499 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10503 /* ??? As above. */
10504 if (mode == CCmode)
10506 else if (mode == CCCmode)
10507 suffix = fp ? "nb" : "ae";
10509 gcc_unreachable ();
10512 suffix = fp ? "u" : "p";
10515 suffix = fp ? "nu" : "np";
10518 gcc_unreachable ();
10520 fputs (suffix, file);
10523 /* Print the name of register X to FILE based on its machine mode and number.
10524 If CODE is 'w', pretend the mode is HImode.
10525 If CODE is 'b', pretend the mode is QImode.
10526 If CODE is 'k', pretend the mode is SImode.
10527 If CODE is 'q', pretend the mode is DImode.
10528 If CODE is 'x', pretend the mode is V4SFmode.
10529 If CODE is 't', pretend the mode is V8SFmode.
10530 If CODE is 'h', pretend the reg is the 'high' byte register.
10531 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10532 If CODE is 'd', duplicate the operand for AVX instruction.
10536 print_reg (rtx x, int code, FILE *file)
10539 bool duplicated = code == 'd' && TARGET_AVX;
10541 gcc_assert (x == pc_rtx
10542 || (REGNO (x) != ARG_POINTER_REGNUM
10543 && REGNO (x) != FRAME_POINTER_REGNUM
10544 && REGNO (x) != FLAGS_REG
10545 && REGNO (x) != FPSR_REG
10546 && REGNO (x) != FPCR_REG));
10548 if (ASSEMBLER_DIALECT == ASM_ATT)
10553 gcc_assert (TARGET_64BIT);
10554 fputs ("rip", file);
10558 if (code == 'w' || MMX_REG_P (x))
10560 else if (code == 'b')
10562 else if (code == 'k')
10564 else if (code == 'q')
10566 else if (code == 'y')
10568 else if (code == 'h')
10570 else if (code == 'x')
10572 else if (code == 't')
10575 code = GET_MODE_SIZE (GET_MODE (x));
10577 /* Irritatingly, AMD extended registers use different naming convention
10578 from the normal registers. */
10579 if (REX_INT_REG_P (x))
10581 gcc_assert (TARGET_64BIT);
10585 error ("extended registers have no high halves");
10588 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10591 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10594 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10597 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10600 error ("unsupported operand size for extended register");
10610 if (STACK_TOP_P (x))
10619 if (! ANY_FP_REG_P (x))
10620 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10625 reg = hi_reg_name[REGNO (x)];
10628 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10630 reg = qi_reg_name[REGNO (x)];
10633 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10635 reg = qi_high_reg_name[REGNO (x)];
10640 gcc_assert (!duplicated);
10642 fputs (hi_reg_name[REGNO (x)] + 1, file);
10647 gcc_unreachable ();
10653 if (ASSEMBLER_DIALECT == ASM_ATT)
10654 fprintf (file, ", %%%s", reg);
10656 fprintf (file, ", %s", reg);
10660 /* Locate some local-dynamic symbol still in use by this function
10661 so that we can print its name in some tls_local_dynamic_base
10665 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10669 if (GET_CODE (x) == SYMBOL_REF
10670 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10672 cfun->machine->some_ld_name = XSTR (x, 0);
10679 static const char *
10680 get_some_local_dynamic_name (void)
10684 if (cfun->machine->some_ld_name)
10685 return cfun->machine->some_ld_name;
10687 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10689 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10690 return cfun->machine->some_ld_name;
10692 gcc_unreachable ();
10695 /* Meaning of CODE:
10696 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10697 C -- print opcode suffix for set/cmov insn.
10698 c -- like C, but print reversed condition
10699 E,e -- likewise, but for compare-and-branch fused insn.
10700 F,f -- likewise, but for floating-point.
10701 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10703 R -- print the prefix for register names.
10704 z -- print the opcode suffix for the size of the current operand.
10705 * -- print a star (in certain assembler syntax)
10706 A -- print an absolute memory reference.
10707 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10708 s -- print a shift double count, followed by the assemblers argument
10710 b -- print the QImode name of the register for the indicated operand.
10711 %b0 would print %al if operands[0] is reg 0.
10712 w -- likewise, print the HImode name of the register.
10713 k -- likewise, print the SImode name of the register.
10714 q -- likewise, print the DImode name of the register.
10715 x -- likewise, print the V4SFmode name of the register.
10716 t -- likewise, print the V8SFmode name of the register.
10717 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10718 y -- print "st(0)" instead of "st" as a register.
10719 d -- print duplicated register operand for AVX instruction.
10720 D -- print condition for SSE cmp instruction.
10721 P -- if PIC, print an @PLT suffix.
10722 X -- don't print any sort of PIC '@' suffix for a symbol.
10723 & -- print some in-use local-dynamic symbol name.
10724 H -- print a memory address offset by 8; used for sse high-parts
10725 Y -- print condition for SSE5 com* instruction.
10726 + -- print a branch hint as 'cs' or 'ds' prefix
10727 ; -- print a semicolon (after prefixes due to bug in older gas).
10731 print_operand (FILE *file, rtx x, int code)
10738 if (ASSEMBLER_DIALECT == ASM_ATT)
10743 assemble_name (file, get_some_local_dynamic_name ());
10747 switch (ASSEMBLER_DIALECT)
10754 /* Intel syntax. For absolute addresses, registers should not
10755 be surrounded by braces. */
10759 PRINT_OPERAND (file, x, 0);
10766 gcc_unreachable ();
10769 PRINT_OPERAND (file, x, 0);
10774 if (ASSEMBLER_DIALECT == ASM_ATT)
10779 if (ASSEMBLER_DIALECT == ASM_ATT)
10784 if (ASSEMBLER_DIALECT == ASM_ATT)
10789 if (ASSEMBLER_DIALECT == ASM_ATT)
10794 if (ASSEMBLER_DIALECT == ASM_ATT)
10799 if (ASSEMBLER_DIALECT == ASM_ATT)
10804 /* 387 opcodes don't get size suffixes if the operands are
10806 if (STACK_REG_P (x))
10809 /* Likewise if using Intel opcodes. */
10810 if (ASSEMBLER_DIALECT == ASM_INTEL)
10813 /* This is the size of op from size of operand. */
10814 switch (GET_MODE_SIZE (GET_MODE (x)))
10823 #ifdef HAVE_GAS_FILDS_FISTS
10833 if (GET_MODE (x) == SFmode)
10848 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10852 #ifdef GAS_MNEMONICS
10867 gcc_unreachable ();
10884 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
10886 PRINT_OPERAND (file, x, 0);
10887 fputs (", ", file);
10892 /* Little bit of braindamage here. The SSE compare instructions
10893 does use completely different names for the comparisons that the
10894 fp conditional moves. */
10897 switch (GET_CODE (x))
10900 fputs ("eq", file);
10903 fputs ("eq_us", file);
10906 fputs ("lt", file);
10909 fputs ("nge", file);
10912 fputs ("le", file);
10915 fputs ("ngt", file);
10918 fputs ("unord", file);
10921 fputs ("neq", file);
10924 fputs ("neq_oq", file);
10927 fputs ("ge", file);
10930 fputs ("nlt", file);
10933 fputs ("gt", file);
10936 fputs ("nle", file);
10939 fputs ("ord", file);
10942 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
10948 switch (GET_CODE (x))
10952 fputs ("eq", file);
10956 fputs ("lt", file);
10960 fputs ("le", file);
10963 fputs ("unord", file);
10967 fputs ("neq", file);
10971 fputs ("nlt", file);
10975 fputs ("nle", file);
10978 fputs ("ord", file);
10981 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
10987 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
10988 if (ASSEMBLER_DIALECT == ASM_ATT)
10990 switch (GET_MODE (x))
10992 case HImode: putc ('w', file); break;
10994 case SFmode: putc ('l', file); break;
10996 case DFmode: putc ('q', file); break;
10997 default: gcc_unreachable ();
11004 if (!COMPARISON_P (x))
11006 output_operand_lossage ("operand is neither a constant nor a "
11007 "condition code, invalid operand code "
11011 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11014 if (!COMPARISON_P (x))
11016 output_operand_lossage ("operand is neither a constant nor a "
11017 "condition code, invalid operand code "
11021 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11022 if (ASSEMBLER_DIALECT == ASM_ATT)
11025 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11028 /* Like above, but reverse condition */
11030 /* Check to see if argument to %c is really a constant
11031 and not a condition code which needs to be reversed. */
11032 if (!COMPARISON_P (x))
11034 output_operand_lossage ("operand is neither a constant nor a "
11035 "condition code, invalid operand "
11039 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11042 if (!COMPARISON_P (x))
11044 output_operand_lossage ("operand is neither a constant nor a "
11045 "condition code, invalid operand "
11049 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11050 if (ASSEMBLER_DIALECT == ASM_ATT)
11053 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11057 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11061 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11065 /* It doesn't actually matter what mode we use here, as we're
11066 only going to use this for printing. */
11067 x = adjust_address_nv (x, DImode, 8);
11075 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11078 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11081 int pred_val = INTVAL (XEXP (x, 0));
11083 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11084 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11086 int taken = pred_val > REG_BR_PROB_BASE / 2;
11087 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11089 /* Emit hints only in the case default branch prediction
11090 heuristics would fail. */
11091 if (taken != cputaken)
11093 /* We use 3e (DS) prefix for taken branches and
11094 2e (CS) prefix for not taken branches. */
11096 fputs ("ds ; ", file);
11098 fputs ("cs ; ", file);
11106 switch (GET_CODE (x))
11109 fputs ("neq", file);
11112 fputs ("eq", file);
11116 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11120 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11124 fputs ("le", file);
11128 fputs ("lt", file);
11131 fputs ("unord", file);
11134 fputs ("ord", file);
11137 fputs ("ueq", file);
11140 fputs ("nlt", file);
11143 fputs ("nle", file);
11146 fputs ("ule", file);
11149 fputs ("ult", file);
11152 fputs ("une", file);
11155 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11162 fputs (" ; ", file);
11169 output_operand_lossage ("invalid operand code '%c'", code);
11174 print_reg (x, code, file);
11176 else if (MEM_P (x))
11178 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11179 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11180 && GET_MODE (x) != BLKmode)
11183 switch (GET_MODE_SIZE (GET_MODE (x)))
11185 case 1: size = "BYTE"; break;
11186 case 2: size = "WORD"; break;
11187 case 4: size = "DWORD"; break;
11188 case 8: size = "QWORD"; break;
11189 case 12: size = "XWORD"; break;
11191 if (GET_MODE (x) == XFmode)
11197 gcc_unreachable ();
11200 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11203 else if (code == 'w')
11205 else if (code == 'k')
11208 fputs (size, file);
11209 fputs (" PTR ", file);
11213 /* Avoid (%rip) for call operands. */
11214 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11215 && !CONST_INT_P (x))
11216 output_addr_const (file, x);
11217 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11218 output_operand_lossage ("invalid constraints for operand");
11220 output_address (x);
11223 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11228 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11229 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11231 if (ASSEMBLER_DIALECT == ASM_ATT)
11233 fprintf (file, "0x%08lx", (long unsigned int) l);
11236 /* These float cases don't actually occur as immediate operands. */
11237 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11241 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11242 fprintf (file, "%s", dstr);
11245 else if (GET_CODE (x) == CONST_DOUBLE
11246 && GET_MODE (x) == XFmode)
11250 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11251 fprintf (file, "%s", dstr);
11256 /* We have patterns that allow zero sets of memory, for instance.
11257 In 64-bit mode, we should probably support all 8-byte vectors,
11258 since we can in fact encode that into an immediate. */
11259 if (GET_CODE (x) == CONST_VECTOR)
11261 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11267 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11269 if (ASSEMBLER_DIALECT == ASM_ATT)
11272 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11273 || GET_CODE (x) == LABEL_REF)
11275 if (ASSEMBLER_DIALECT == ASM_ATT)
11278 fputs ("OFFSET FLAT:", file);
11281 if (CONST_INT_P (x))
11282 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11284 output_pic_addr_const (file, x, code);
11286 output_addr_const (file, x);
11290 /* Print a memory operand whose address is ADDR. */
11293 print_operand_address (FILE *file, rtx addr)
11295 struct ix86_address parts;
11296 rtx base, index, disp;
11298 int ok = ix86_decompose_address (addr, &parts);
11303 index = parts.index;
11305 scale = parts.scale;
11313 if (ASSEMBLER_DIALECT == ASM_ATT)
11315 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11318 gcc_unreachable ();
11321 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11322 if (TARGET_64BIT && !base && !index)
11326 if (GET_CODE (disp) == CONST
11327 && GET_CODE (XEXP (disp, 0)) == PLUS
11328 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11329 symbol = XEXP (XEXP (disp, 0), 0);
11331 if (GET_CODE (symbol) == LABEL_REF
11332 || (GET_CODE (symbol) == SYMBOL_REF
11333 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11336 if (!base && !index)
11338 /* Displacement only requires special attention. */
11340 if (CONST_INT_P (disp))
11342 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11343 fputs ("ds:", file);
11344 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11347 output_pic_addr_const (file, disp, 0);
11349 output_addr_const (file, disp);
11353 if (ASSEMBLER_DIALECT == ASM_ATT)
11358 output_pic_addr_const (file, disp, 0);
11359 else if (GET_CODE (disp) == LABEL_REF)
11360 output_asm_label (disp);
11362 output_addr_const (file, disp);
11367 print_reg (base, 0, file);
11371 print_reg (index, 0, file);
11373 fprintf (file, ",%d", scale);
11379 rtx offset = NULL_RTX;
11383 /* Pull out the offset of a symbol; print any symbol itself. */
11384 if (GET_CODE (disp) == CONST
11385 && GET_CODE (XEXP (disp, 0)) == PLUS
11386 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11388 offset = XEXP (XEXP (disp, 0), 1);
11389 disp = gen_rtx_CONST (VOIDmode,
11390 XEXP (XEXP (disp, 0), 0));
11394 output_pic_addr_const (file, disp, 0);
11395 else if (GET_CODE (disp) == LABEL_REF)
11396 output_asm_label (disp);
11397 else if (CONST_INT_P (disp))
11400 output_addr_const (file, disp);
11406 print_reg (base, 0, file);
11409 if (INTVAL (offset) >= 0)
11411 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11415 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11422 print_reg (index, 0, file);
11424 fprintf (file, "*%d", scale);
11432 output_addr_const_extra (FILE *file, rtx x)
11436 if (GET_CODE (x) != UNSPEC)
11439 op = XVECEXP (x, 0, 0);
11440 switch (XINT (x, 1))
11442 case UNSPEC_GOTTPOFF:
11443 output_addr_const (file, op);
11444 /* FIXME: This might be @TPOFF in Sun ld. */
11445 fputs ("@GOTTPOFF", file);
11448 output_addr_const (file, op);
11449 fputs ("@TPOFF", file);
11451 case UNSPEC_NTPOFF:
11452 output_addr_const (file, op);
11454 fputs ("@TPOFF", file);
11456 fputs ("@NTPOFF", file);
11458 case UNSPEC_DTPOFF:
11459 output_addr_const (file, op);
11460 fputs ("@DTPOFF", file);
11462 case UNSPEC_GOTNTPOFF:
11463 output_addr_const (file, op);
11465 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11466 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11468 fputs ("@GOTNTPOFF", file);
11470 case UNSPEC_INDNTPOFF:
11471 output_addr_const (file, op);
11472 fputs ("@INDNTPOFF", file);
11475 case UNSPEC_MACHOPIC_OFFSET:
11476 output_addr_const (file, op);
11478 machopic_output_function_base_name (file);
11489 /* Split one or more DImode RTL references into pairs of SImode
11490 references. The RTL can be REG, offsettable MEM, integer constant, or
11491 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11492 split and "num" is its length. lo_half and hi_half are output arrays
11493 that parallel "operands". */
11496 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11500 rtx op = operands[num];
11502 /* simplify_subreg refuse to split volatile memory addresses,
11503 but we still have to handle it. */
11506 lo_half[num] = adjust_address (op, SImode, 0);
11507 hi_half[num] = adjust_address (op, SImode, 4);
11511 lo_half[num] = simplify_gen_subreg (SImode, op,
11512 GET_MODE (op) == VOIDmode
11513 ? DImode : GET_MODE (op), 0);
11514 hi_half[num] = simplify_gen_subreg (SImode, op,
11515 GET_MODE (op) == VOIDmode
11516 ? DImode : GET_MODE (op), 4);
11520 /* Split one or more TImode RTL references into pairs of DImode
11521 references. The RTL can be REG, offsettable MEM, integer constant, or
11522 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11523 split and "num" is its length. lo_half and hi_half are output arrays
11524 that parallel "operands". */
11527 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11531 rtx op = operands[num];
11533 /* simplify_subreg refuse to split volatile memory addresses, but we
11534 still have to handle it. */
11537 lo_half[num] = adjust_address (op, DImode, 0);
11538 hi_half[num] = adjust_address (op, DImode, 8);
11542 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11543 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11548 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11549 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11550 is the expression of the binary operation. The output may either be
11551 emitted here, or returned to the caller, like all output_* functions.
11553 There is no guarantee that the operands are the same mode, as they
11554 might be within FLOAT or FLOAT_EXTEND expressions. */
11556 #ifndef SYSV386_COMPAT
11557 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11558 wants to fix the assemblers because that causes incompatibility
11559 with gcc. No-one wants to fix gcc because that causes
11560 incompatibility with assemblers... You can use the option of
11561 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11562 #define SYSV386_COMPAT 1
11566 output_387_binary_op (rtx insn, rtx *operands)
11568 static char buf[40];
11571 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
11573 #ifdef ENABLE_CHECKING
11574 /* Even if we do not want to check the inputs, this documents input
11575 constraints. Which helps in understanding the following code. */
11576 if (STACK_REG_P (operands[0])
11577 && ((REG_P (operands[1])
11578 && REGNO (operands[0]) == REGNO (operands[1])
11579 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
11580 || (REG_P (operands[2])
11581 && REGNO (operands[0]) == REGNO (operands[2])
11582 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
11583 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
11586 gcc_assert (is_sse);
11589 switch (GET_CODE (operands[3]))
11592 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11593 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11601 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11602 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11610 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11611 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11619 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11620 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11628 gcc_unreachable ();
11635 strcpy (buf, ssep);
11636 if (GET_MODE (operands[0]) == SFmode)
11637 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
11639 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
11643 strcpy (buf, ssep + 1);
11644 if (GET_MODE (operands[0]) == SFmode)
11645 strcat (buf, "ss\t{%2, %0|%0, %2}");
11647 strcat (buf, "sd\t{%2, %0|%0, %2}");
11653 switch (GET_CODE (operands[3]))
11657 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11659 rtx temp = operands[2];
11660 operands[2] = operands[1];
11661 operands[1] = temp;
11664 /* know operands[0] == operands[1]. */
11666 if (MEM_P (operands[2]))
11672 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11674 if (STACK_TOP_P (operands[0]))
11675 /* How is it that we are storing to a dead operand[2]?
11676 Well, presumably operands[1] is dead too. We can't
11677 store the result to st(0) as st(0) gets popped on this
11678 instruction. Instead store to operands[2] (which I
11679 think has to be st(1)). st(1) will be popped later.
11680 gcc <= 2.8.1 didn't have this check and generated
11681 assembly code that the Unixware assembler rejected. */
11682 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11684 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11688 if (STACK_TOP_P (operands[0]))
11689 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11691 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11696 if (MEM_P (operands[1]))
11702 if (MEM_P (operands[2]))
11708 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11711 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11712 derived assemblers, confusingly reverse the direction of
11713 the operation for fsub{r} and fdiv{r} when the
11714 destination register is not st(0). The Intel assembler
11715 doesn't have this brain damage. Read !SYSV386_COMPAT to
11716 figure out what the hardware really does. */
11717 if (STACK_TOP_P (operands[0]))
11718 p = "{p\t%0, %2|rp\t%2, %0}";
11720 p = "{rp\t%2, %0|p\t%0, %2}";
11722 if (STACK_TOP_P (operands[0]))
11723 /* As above for fmul/fadd, we can't store to st(0). */
11724 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11726 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11731 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11734 if (STACK_TOP_P (operands[0]))
11735 p = "{rp\t%0, %1|p\t%1, %0}";
11737 p = "{p\t%1, %0|rp\t%0, %1}";
11739 if (STACK_TOP_P (operands[0]))
11740 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11742 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11747 if (STACK_TOP_P (operands[0]))
11749 if (STACK_TOP_P (operands[1]))
11750 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11752 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11755 else if (STACK_TOP_P (operands[1]))
11758 p = "{\t%1, %0|r\t%0, %1}";
11760 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11766 p = "{r\t%2, %0|\t%0, %2}";
11768 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11774 gcc_unreachable ();
11781 /* Return needed mode for entity in optimize_mode_switching pass. */
11784 ix86_mode_needed (int entity, rtx insn)
11786 enum attr_i387_cw mode;
11788 /* The mode UNINITIALIZED is used to store control word after a
11789 function call or ASM pattern. The mode ANY specify that function
11790 has no requirements on the control word and make no changes in the
11791 bits we are interested in. */
11794 || (NONJUMP_INSN_P (insn)
11795 && (asm_noperands (PATTERN (insn)) >= 0
11796 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
11797 return I387_CW_UNINITIALIZED;
11799 if (recog_memoized (insn) < 0)
11800 return I387_CW_ANY;
11802 mode = get_attr_i387_cw (insn);
11807 if (mode == I387_CW_TRUNC)
11812 if (mode == I387_CW_FLOOR)
11817 if (mode == I387_CW_CEIL)
11822 if (mode == I387_CW_MASK_PM)
11827 gcc_unreachable ();
11830 return I387_CW_ANY;
11833 /* Output code to initialize control word copies used by trunc?f?i and
11834 rounding patterns. CURRENT_MODE is set to current control word,
11835 while NEW_MODE is set to new control word. */
11838 emit_i387_cw_initialization (int mode)
11840 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
11843 enum ix86_stack_slot slot;
11845 rtx reg = gen_reg_rtx (HImode);
11847 emit_insn (gen_x86_fnstcw_1 (stored_mode));
11848 emit_move_insn (reg, copy_rtx (stored_mode));
11850 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
11851 || optimize_function_for_size_p (cfun))
11855 case I387_CW_TRUNC:
11856 /* round toward zero (truncate) */
11857 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
11858 slot = SLOT_CW_TRUNC;
11861 case I387_CW_FLOOR:
11862 /* round down toward -oo */
11863 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11864 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
11865 slot = SLOT_CW_FLOOR;
11869 /* round up toward +oo */
11870 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11871 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
11872 slot = SLOT_CW_CEIL;
11875 case I387_CW_MASK_PM:
11876 /* mask precision exception for nearbyint() */
11877 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11878 slot = SLOT_CW_MASK_PM;
11882 gcc_unreachable ();
11889 case I387_CW_TRUNC:
11890 /* round toward zero (truncate) */
11891 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
11892 slot = SLOT_CW_TRUNC;
11895 case I387_CW_FLOOR:
11896 /* round down toward -oo */
11897 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
11898 slot = SLOT_CW_FLOOR;
11902 /* round up toward +oo */
11903 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
11904 slot = SLOT_CW_CEIL;
11907 case I387_CW_MASK_PM:
11908 /* mask precision exception for nearbyint() */
11909 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
11910 slot = SLOT_CW_MASK_PM;
11914 gcc_unreachable ();
11918 gcc_assert (slot < MAX_386_STACK_LOCALS);
11920 new_mode = assign_386_stack_local (HImode, slot);
11921 emit_move_insn (new_mode, reg);
11924 /* Output code for INSN to convert a float to a signed int. OPERANDS
11925 are the insn operands. The output may be [HSD]Imode and the input
11926 operand may be [SDX]Fmode. */
11929 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
11931 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
11932 int dimode_p = GET_MODE (operands[0]) == DImode;
11933 int round_mode = get_attr_i387_cw (insn);
11935 /* Jump through a hoop or two for DImode, since the hardware has no
11936 non-popping instruction. We used to do this a different way, but
11937 that was somewhat fragile and broke with post-reload splitters. */
11938 if ((dimode_p || fisttp) && !stack_top_dies)
11939 output_asm_insn ("fld\t%y1", operands);
11941 gcc_assert (STACK_TOP_P (operands[1]));
11942 gcc_assert (MEM_P (operands[0]));
11943 gcc_assert (GET_MODE (operands[1]) != TFmode);
11946 output_asm_insn ("fisttp%z0\t%0", operands);
11949 if (round_mode != I387_CW_ANY)
11950 output_asm_insn ("fldcw\t%3", operands);
11951 if (stack_top_dies || dimode_p)
11952 output_asm_insn ("fistp%z0\t%0", operands);
11954 output_asm_insn ("fist%z0\t%0", operands);
11955 if (round_mode != I387_CW_ANY)
11956 output_asm_insn ("fldcw\t%2", operands);
11962 /* Output code for x87 ffreep insn. The OPNO argument, which may only
11963 have the values zero or one, indicates the ffreep insn's operand
11964 from the OPERANDS array. */
11966 static const char *
11967 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
11969 if (TARGET_USE_FFREEP)
11970 #if HAVE_AS_IX86_FFREEP
11971 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
11974 static char retval[] = ".word\t0xc_df";
11975 int regno = REGNO (operands[opno]);
11977 gcc_assert (FP_REGNO_P (regno));
11979 retval[9] = '0' + (regno - FIRST_STACK_REG);
11984 return opno ? "fstp\t%y1" : "fstp\t%y0";
11988 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
11989 should be used. UNORDERED_P is true when fucom should be used. */
11992 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
11994 int stack_top_dies;
11995 rtx cmp_op0, cmp_op1;
11996 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12000 cmp_op0 = operands[0];
12001 cmp_op1 = operands[1];
12005 cmp_op0 = operands[1];
12006 cmp_op1 = operands[2];
12011 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12012 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12013 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12014 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12016 if (GET_MODE (operands[0]) == SFmode)
12018 return &ucomiss[TARGET_AVX ? 0 : 1];
12020 return &comiss[TARGET_AVX ? 0 : 1];
12023 return &ucomisd[TARGET_AVX ? 0 : 1];
12025 return &comisd[TARGET_AVX ? 0 : 1];
12028 gcc_assert (STACK_TOP_P (cmp_op0));
12030 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12032 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12034 if (stack_top_dies)
12036 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12037 return output_387_ffreep (operands, 1);
12040 return "ftst\n\tfnstsw\t%0";
12043 if (STACK_REG_P (cmp_op1)
12045 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12046 && REGNO (cmp_op1) != FIRST_STACK_REG)
12048 /* If both the top of the 387 stack dies, and the other operand
12049 is also a stack register that dies, then this must be a
12050 `fcompp' float compare */
12054 /* There is no double popping fcomi variant. Fortunately,
12055 eflags is immune from the fstp's cc clobbering. */
12057 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12059 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12060 return output_387_ffreep (operands, 0);
12065 return "fucompp\n\tfnstsw\t%0";
12067 return "fcompp\n\tfnstsw\t%0";
12072 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12074 static const char * const alt[16] =
12076 "fcom%z2\t%y2\n\tfnstsw\t%0",
12077 "fcomp%z2\t%y2\n\tfnstsw\t%0",
12078 "fucom%z2\t%y2\n\tfnstsw\t%0",
12079 "fucomp%z2\t%y2\n\tfnstsw\t%0",
12081 "ficom%z2\t%y2\n\tfnstsw\t%0",
12082 "ficomp%z2\t%y2\n\tfnstsw\t%0",
12086 "fcomi\t{%y1, %0|%0, %y1}",
12087 "fcomip\t{%y1, %0|%0, %y1}",
12088 "fucomi\t{%y1, %0|%0, %y1}",
12089 "fucomip\t{%y1, %0|%0, %y1}",
12100 mask = eflags_p << 3;
12101 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12102 mask |= unordered_p << 1;
12103 mask |= stack_top_dies;
12105 gcc_assert (mask < 16);
12114 ix86_output_addr_vec_elt (FILE *file, int value)
12116 const char *directive = ASM_LONG;
12120 directive = ASM_QUAD;
12122 gcc_assert (!TARGET_64BIT);
12125 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
12129 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12131 const char *directive = ASM_LONG;
12134 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12135 directive = ASM_QUAD;
12137 gcc_assert (!TARGET_64BIT);
12139 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12140 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12141 fprintf (file, "%s%s%d-%s%d\n",
12142 directive, LPREFIX, value, LPREFIX, rel);
12143 else if (HAVE_AS_GOTOFF_IN_DATA)
12144 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
12146 else if (TARGET_MACHO)
12148 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
12149 machopic_output_function_base_name (file);
12150 fprintf(file, "\n");
12154 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
12155 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
12158 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12162 ix86_expand_clear (rtx dest)
12166 /* We play register width games, which are only valid after reload. */
12167 gcc_assert (reload_completed);
12169 /* Avoid HImode and its attendant prefix byte. */
12170 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12171 dest = gen_rtx_REG (SImode, REGNO (dest));
12172 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12174 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12175 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12177 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12178 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12184 /* X is an unchanging MEM. If it is a constant pool reference, return
12185 the constant pool rtx, else NULL. */
12188 maybe_get_pool_constant (rtx x)
12190 x = ix86_delegitimize_address (XEXP (x, 0));
12192 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12193 return get_pool_constant (x);
12199 ix86_expand_move (enum machine_mode mode, rtx operands[])
12202 enum tls_model model;
12207 if (GET_CODE (op1) == SYMBOL_REF)
12209 model = SYMBOL_REF_TLS_MODEL (op1);
12212 op1 = legitimize_tls_address (op1, model, true);
12213 op1 = force_operand (op1, op0);
12217 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12218 && SYMBOL_REF_DLLIMPORT_P (op1))
12219 op1 = legitimize_dllimport_symbol (op1, false);
12221 else if (GET_CODE (op1) == CONST
12222 && GET_CODE (XEXP (op1, 0)) == PLUS
12223 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12225 rtx addend = XEXP (XEXP (op1, 0), 1);
12226 rtx symbol = XEXP (XEXP (op1, 0), 0);
12229 model = SYMBOL_REF_TLS_MODEL (symbol);
12231 tmp = legitimize_tls_address (symbol, model, true);
12232 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12233 && SYMBOL_REF_DLLIMPORT_P (symbol))
12234 tmp = legitimize_dllimport_symbol (symbol, true);
12238 tmp = force_operand (tmp, NULL);
12239 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12240 op0, 1, OPTAB_DIRECT);
12246 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12248 if (TARGET_MACHO && !TARGET_64BIT)
12253 rtx temp = ((reload_in_progress
12254 || ((op0 && REG_P (op0))
12256 ? op0 : gen_reg_rtx (Pmode));
12257 op1 = machopic_indirect_data_reference (op1, temp);
12258 op1 = machopic_legitimize_pic_address (op1, mode,
12259 temp == op1 ? 0 : temp);
12261 else if (MACHOPIC_INDIRECT)
12262 op1 = machopic_indirect_data_reference (op1, 0);
12270 op1 = force_reg (Pmode, op1);
12271 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12273 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
12274 op1 = legitimize_pic_address (op1, reg);
12283 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12284 || !push_operand (op0, mode))
12286 op1 = force_reg (mode, op1);
12288 if (push_operand (op0, mode)
12289 && ! general_no_elim_operand (op1, mode))
12290 op1 = copy_to_mode_reg (mode, op1);
12292 /* Force large constants in 64bit compilation into register
12293 to get them CSEed. */
12294 if (can_create_pseudo_p ()
12295 && (mode == DImode) && TARGET_64BIT
12296 && immediate_operand (op1, mode)
12297 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12298 && !register_operand (op0, mode)
12300 op1 = copy_to_mode_reg (mode, op1);
12302 if (can_create_pseudo_p ()
12303 && FLOAT_MODE_P (mode)
12304 && GET_CODE (op1) == CONST_DOUBLE)
12306 /* If we are loading a floating point constant to a register,
12307 force the value to memory now, since we'll get better code
12308 out the back end. */
12310 op1 = validize_mem (force_const_mem (mode, op1));
12311 if (!register_operand (op0, mode))
12313 rtx temp = gen_reg_rtx (mode);
12314 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12315 emit_move_insn (op0, temp);
12321 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12325 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12327 rtx op0 = operands[0], op1 = operands[1];
12328 unsigned int align = GET_MODE_ALIGNMENT (mode);
12330 /* Force constants other than zero into memory. We do not know how
12331 the instructions used to build constants modify the upper 64 bits
12332 of the register, once we have that information we may be able
12333 to handle some of them more efficiently. */
12334 if (can_create_pseudo_p ()
12335 && register_operand (op0, mode)
12336 && (CONSTANT_P (op1)
12337 || (GET_CODE (op1) == SUBREG
12338 && CONSTANT_P (SUBREG_REG (op1))))
12339 && standard_sse_constant_p (op1) <= 0)
12340 op1 = validize_mem (force_const_mem (mode, op1));
12342 /* We need to check memory alignment for SSE mode since attribute
12343 can make operands unaligned. */
12344 if (can_create_pseudo_p ()
12345 && SSE_REG_MODE_P (mode)
12346 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12347 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12351 /* ix86_expand_vector_move_misalign() does not like constants ... */
12352 if (CONSTANT_P (op1)
12353 || (GET_CODE (op1) == SUBREG
12354 && CONSTANT_P (SUBREG_REG (op1))))
12355 op1 = validize_mem (force_const_mem (mode, op1));
12357 /* ... nor both arguments in memory. */
12358 if (!register_operand (op0, mode)
12359 && !register_operand (op1, mode))
12360 op1 = force_reg (mode, op1);
12362 tmp[0] = op0; tmp[1] = op1;
12363 ix86_expand_vector_move_misalign (mode, tmp);
12367 /* Make operand1 a register if it isn't already. */
12368 if (can_create_pseudo_p ()
12369 && !register_operand (op0, mode)
12370 && !register_operand (op1, mode))
12372 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12376 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12379 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12380 straight to ix86_expand_vector_move. */
12381 /* Code generation for scalar reg-reg moves of single and double precision data:
12382 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12386 if (x86_sse_partial_reg_dependency == true)
12391 Code generation for scalar loads of double precision data:
12392 if (x86_sse_split_regs == true)
12393 movlpd mem, reg (gas syntax)
12397 Code generation for unaligned packed loads of single precision data
12398 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12399 if (x86_sse_unaligned_move_optimal)
12402 if (x86_sse_partial_reg_dependency == true)
12414 Code generation for unaligned packed loads of double precision data
12415 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12416 if (x86_sse_unaligned_move_optimal)
12419 if (x86_sse_split_regs == true)
12432 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12441 switch (GET_MODE_CLASS (mode))
12443 case MODE_VECTOR_INT:
12445 switch (GET_MODE_SIZE (mode))
12448 op0 = gen_lowpart (V16QImode, op0);
12449 op1 = gen_lowpart (V16QImode, op1);
12450 emit_insn (gen_avx_movdqu (op0, op1));
12453 op0 = gen_lowpart (V32QImode, op0);
12454 op1 = gen_lowpart (V32QImode, op1);
12455 emit_insn (gen_avx_movdqu256 (op0, op1));
12458 gcc_unreachable ();
12461 case MODE_VECTOR_FLOAT:
12462 op0 = gen_lowpart (mode, op0);
12463 op1 = gen_lowpart (mode, op1);
12468 emit_insn (gen_avx_movups (op0, op1));
12471 emit_insn (gen_avx_movups256 (op0, op1));
12474 emit_insn (gen_avx_movupd (op0, op1));
12477 emit_insn (gen_avx_movupd256 (op0, op1));
12480 gcc_unreachable ();
12485 gcc_unreachable ();
12493 /* If we're optimizing for size, movups is the smallest. */
12494 if (optimize_insn_for_size_p ())
12496 op0 = gen_lowpart (V4SFmode, op0);
12497 op1 = gen_lowpart (V4SFmode, op1);
12498 emit_insn (gen_sse_movups (op0, op1));
12502 /* ??? If we have typed data, then it would appear that using
12503 movdqu is the only way to get unaligned data loaded with
12505 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12507 op0 = gen_lowpart (V16QImode, op0);
12508 op1 = gen_lowpart (V16QImode, op1);
12509 emit_insn (gen_sse2_movdqu (op0, op1));
12513 if (TARGET_SSE2 && mode == V2DFmode)
12517 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12519 op0 = gen_lowpart (V2DFmode, op0);
12520 op1 = gen_lowpart (V2DFmode, op1);
12521 emit_insn (gen_sse2_movupd (op0, op1));
12525 /* When SSE registers are split into halves, we can avoid
12526 writing to the top half twice. */
12527 if (TARGET_SSE_SPLIT_REGS)
12529 emit_clobber (op0);
12534 /* ??? Not sure about the best option for the Intel chips.
12535 The following would seem to satisfy; the register is
12536 entirely cleared, breaking the dependency chain. We
12537 then store to the upper half, with a dependency depth
12538 of one. A rumor has it that Intel recommends two movsd
12539 followed by an unpacklpd, but this is unconfirmed. And
12540 given that the dependency depth of the unpacklpd would
12541 still be one, I'm not sure why this would be better. */
12542 zero = CONST0_RTX (V2DFmode);
12545 m = adjust_address (op1, DFmode, 0);
12546 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12547 m = adjust_address (op1, DFmode, 8);
12548 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12552 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12554 op0 = gen_lowpart (V4SFmode, op0);
12555 op1 = gen_lowpart (V4SFmode, op1);
12556 emit_insn (gen_sse_movups (op0, op1));
12560 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
12561 emit_move_insn (op0, CONST0_RTX (mode));
12563 emit_clobber (op0);
12565 if (mode != V4SFmode)
12566 op0 = gen_lowpart (V4SFmode, op0);
12567 m = adjust_address (op1, V2SFmode, 0);
12568 emit_insn (gen_sse_loadlps (op0, op0, m));
12569 m = adjust_address (op1, V2SFmode, 8);
12570 emit_insn (gen_sse_loadhps (op0, op0, m));
12573 else if (MEM_P (op0))
12575 /* If we're optimizing for size, movups is the smallest. */
12576 if (optimize_insn_for_size_p ())
12578 op0 = gen_lowpart (V4SFmode, op0);
12579 op1 = gen_lowpart (V4SFmode, op1);
12580 emit_insn (gen_sse_movups (op0, op1));
12584 /* ??? Similar to above, only less clear because of quote
12585 typeless stores unquote. */
12586 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
12587 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12589 op0 = gen_lowpart (V16QImode, op0);
12590 op1 = gen_lowpart (V16QImode, op1);
12591 emit_insn (gen_sse2_movdqu (op0, op1));
12595 if (TARGET_SSE2 && mode == V2DFmode)
12597 m = adjust_address (op0, DFmode, 0);
12598 emit_insn (gen_sse2_storelpd (m, op1));
12599 m = adjust_address (op0, DFmode, 8);
12600 emit_insn (gen_sse2_storehpd (m, op1));
12604 if (mode != V4SFmode)
12605 op1 = gen_lowpart (V4SFmode, op1);
12606 m = adjust_address (op0, V2SFmode, 0);
12607 emit_insn (gen_sse_storelps (m, op1));
12608 m = adjust_address (op0, V2SFmode, 8);
12609 emit_insn (gen_sse_storehps (m, op1));
12613 gcc_unreachable ();
12616 /* Expand a push in MODE. This is some mode for which we do not support
12617 proper push instructions, at least from the registers that we expect
12618 the value to live in. */
12621 ix86_expand_push (enum machine_mode mode, rtx x)
12625 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
12626 GEN_INT (-GET_MODE_SIZE (mode)),
12627 stack_pointer_rtx, 1, OPTAB_DIRECT);
12628 if (tmp != stack_pointer_rtx)
12629 emit_move_insn (stack_pointer_rtx, tmp);
12631 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
12633 /* When we push an operand onto stack, it has to be aligned at least
12634 at the function argument boundary. However since we don't have
12635 the argument type, we can't determine the actual argument
12637 emit_move_insn (tmp, x);
12640 /* Helper function of ix86_fixup_binary_operands to canonicalize
12641 operand order. Returns true if the operands should be swapped. */
12644 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
12647 rtx dst = operands[0];
12648 rtx src1 = operands[1];
12649 rtx src2 = operands[2];
12651 /* If the operation is not commutative, we can't do anything. */
12652 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
12655 /* Highest priority is that src1 should match dst. */
12656 if (rtx_equal_p (dst, src1))
12658 if (rtx_equal_p (dst, src2))
12661 /* Next highest priority is that immediate constants come second. */
12662 if (immediate_operand (src2, mode))
12664 if (immediate_operand (src1, mode))
12667 /* Lowest priority is that memory references should come second. */
12677 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12678 destination to use for the operation. If different from the true
12679 destination in operands[0], a copy operation will be required. */
12682 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
12685 rtx dst = operands[0];
12686 rtx src1 = operands[1];
12687 rtx src2 = operands[2];
12689 /* Canonicalize operand order. */
12690 if (ix86_swap_binary_operands_p (code, mode, operands))
12694 /* It is invalid to swap operands of different modes. */
12695 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12702 /* Both source operands cannot be in memory. */
12703 if (MEM_P (src1) && MEM_P (src2))
12705 /* Optimization: Only read from memory once. */
12706 if (rtx_equal_p (src1, src2))
12708 src2 = force_reg (mode, src2);
12712 src2 = force_reg (mode, src2);
12715 /* If the destination is memory, and we do not have matching source
12716 operands, do things in registers. */
12717 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12718 dst = gen_reg_rtx (mode);
12720 /* Source 1 cannot be a constant. */
12721 if (CONSTANT_P (src1))
12722 src1 = force_reg (mode, src1);
12724 /* Source 1 cannot be a non-matching memory. */
12725 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12726 src1 = force_reg (mode, src1);
12728 operands[1] = src1;
12729 operands[2] = src2;
12733 /* Similarly, but assume that the destination has already been
12734 set up properly. */
12737 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12738 enum machine_mode mode, rtx operands[])
12740 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12741 gcc_assert (dst == operands[0]);
12744 /* Attempt to expand a binary operator. Make the expansion closer to the
12745 actual machine, then just general_operand, which will allow 3 separate
12746 memory references (one output, two input) in a single insn. */
12749 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12752 rtx src1, src2, dst, op, clob;
12754 dst = ix86_fixup_binary_operands (code, mode, operands);
12755 src1 = operands[1];
12756 src2 = operands[2];
12758 /* Emit the instruction. */
12760 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12761 if (reload_in_progress)
12763 /* Reload doesn't know about the flags register, and doesn't know that
12764 it doesn't want to clobber it. We can only do this with PLUS. */
12765 gcc_assert (code == PLUS);
12770 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12771 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12774 /* Fix up the destination if needed. */
12775 if (dst != operands[0])
12776 emit_move_insn (operands[0], dst);
12779 /* Return TRUE or FALSE depending on whether the binary operator meets the
12780 appropriate constraints. */
12783 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12786 rtx dst = operands[0];
12787 rtx src1 = operands[1];
12788 rtx src2 = operands[2];
12790 /* Both source operands cannot be in memory. */
12791 if (MEM_P (src1) && MEM_P (src2))
12794 /* Canonicalize operand order for commutative operators. */
12795 if (ix86_swap_binary_operands_p (code, mode, operands))
12802 /* If the destination is memory, we must have a matching source operand. */
12803 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12806 /* Source 1 cannot be a constant. */
12807 if (CONSTANT_P (src1))
12810 /* Source 1 cannot be a non-matching memory. */
12811 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12817 /* Attempt to expand a unary operator. Make the expansion closer to the
12818 actual machine, then just general_operand, which will allow 2 separate
12819 memory references (one output, one input) in a single insn. */
12822 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
12825 int matching_memory;
12826 rtx src, dst, op, clob;
12831 /* If the destination is memory, and we do not have matching source
12832 operands, do things in registers. */
12833 matching_memory = 0;
12836 if (rtx_equal_p (dst, src))
12837 matching_memory = 1;
12839 dst = gen_reg_rtx (mode);
12842 /* When source operand is memory, destination must match. */
12843 if (MEM_P (src) && !matching_memory)
12844 src = force_reg (mode, src);
12846 /* Emit the instruction. */
12848 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
12849 if (reload_in_progress || code == NOT)
12851 /* Reload doesn't know about the flags register, and doesn't know that
12852 it doesn't want to clobber it. */
12853 gcc_assert (code == NOT);
12858 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12859 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12862 /* Fix up the destination if needed. */
12863 if (dst != operands[0])
12864 emit_move_insn (operands[0], dst);
12867 /* Return TRUE or FALSE depending on whether the unary operator meets the
12868 appropriate constraints. */
12871 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
12872 enum machine_mode mode ATTRIBUTE_UNUSED,
12873 rtx operands[2] ATTRIBUTE_UNUSED)
12875 /* If one of operands is memory, source and destination must match. */
12876 if ((MEM_P (operands[0])
12877 || MEM_P (operands[1]))
12878 && ! rtx_equal_p (operands[0], operands[1]))
12883 /* Post-reload splitter for converting an SF or DFmode value in an
12884 SSE register into an unsigned SImode. */
12887 ix86_split_convert_uns_si_sse (rtx operands[])
12889 enum machine_mode vecmode;
12890 rtx value, large, zero_or_two31, input, two31, x;
12892 large = operands[1];
12893 zero_or_two31 = operands[2];
12894 input = operands[3];
12895 two31 = operands[4];
12896 vecmode = GET_MODE (large);
12897 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
12899 /* Load up the value into the low element. We must ensure that the other
12900 elements are valid floats -- zero is the easiest such value. */
12903 if (vecmode == V4SFmode)
12904 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
12906 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
12910 input = gen_rtx_REG (vecmode, REGNO (input));
12911 emit_move_insn (value, CONST0_RTX (vecmode));
12912 if (vecmode == V4SFmode)
12913 emit_insn (gen_sse_movss (value, value, input));
12915 emit_insn (gen_sse2_movsd (value, value, input));
12918 emit_move_insn (large, two31);
12919 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
12921 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
12922 emit_insn (gen_rtx_SET (VOIDmode, large, x));
12924 x = gen_rtx_AND (vecmode, zero_or_two31, large);
12925 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
12927 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
12928 emit_insn (gen_rtx_SET (VOIDmode, value, x));
12930 large = gen_rtx_REG (V4SImode, REGNO (large));
12931 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
12933 x = gen_rtx_REG (V4SImode, REGNO (value));
12934 if (vecmode == V4SFmode)
12935 emit_insn (gen_sse2_cvttps2dq (x, value));
12937 emit_insn (gen_sse2_cvttpd2dq (x, value));
12940 emit_insn (gen_xorv4si3 (value, value, large));
12943 /* Convert an unsigned DImode value into a DFmode, using only SSE.
12944 Expects the 64-bit DImode to be supplied in a pair of integral
12945 registers. Requires SSE2; will use SSE3 if available. For x86_32,
12946 -mfpmath=sse, !optimize_size only. */
12949 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
12951 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
12952 rtx int_xmm, fp_xmm;
12953 rtx biases, exponents;
12956 int_xmm = gen_reg_rtx (V4SImode);
12957 if (TARGET_INTER_UNIT_MOVES)
12958 emit_insn (gen_movdi_to_sse (int_xmm, input));
12959 else if (TARGET_SSE_SPLIT_REGS)
12961 emit_clobber (int_xmm);
12962 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
12966 x = gen_reg_rtx (V2DImode);
12967 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
12968 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
12971 x = gen_rtx_CONST_VECTOR (V4SImode,
12972 gen_rtvec (4, GEN_INT (0x43300000UL),
12973 GEN_INT (0x45300000UL),
12974 const0_rtx, const0_rtx));
12975 exponents = validize_mem (force_const_mem (V4SImode, x));
12977 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
12978 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
12980 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
12981 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
12982 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
12983 (0x1.0p84 + double(fp_value_hi_xmm)).
12984 Note these exponents differ by 32. */
12986 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
12988 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
12989 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
12990 real_ldexp (&bias_lo_rvt, &dconst1, 52);
12991 real_ldexp (&bias_hi_rvt, &dconst1, 84);
12992 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
12993 x = const_double_from_real_value (bias_hi_rvt, DFmode);
12994 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
12995 biases = validize_mem (force_const_mem (V2DFmode, biases));
12996 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
12998 /* Add the upper and lower DFmode values together. */
13000 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13003 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13004 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13005 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13008 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13011 /* Not used, but eases macroization of patterns. */
13013 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13014 rtx input ATTRIBUTE_UNUSED)
13016 gcc_unreachable ();
13019 /* Convert an unsigned SImode value into a DFmode. Only currently used
13020 for SSE, but applicable anywhere. */
13023 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13025 REAL_VALUE_TYPE TWO31r;
13028 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13029 NULL, 1, OPTAB_DIRECT);
13031 fp = gen_reg_rtx (DFmode);
13032 emit_insn (gen_floatsidf2 (fp, x));
13034 real_ldexp (&TWO31r, &dconst1, 31);
13035 x = const_double_from_real_value (TWO31r, DFmode);
13037 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13039 emit_move_insn (target, x);
13042 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13043 32-bit mode; otherwise we have a direct convert instruction. */
13046 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13048 REAL_VALUE_TYPE TWO32r;
13049 rtx fp_lo, fp_hi, x;
13051 fp_lo = gen_reg_rtx (DFmode);
13052 fp_hi = gen_reg_rtx (DFmode);
13054 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13056 real_ldexp (&TWO32r, &dconst1, 32);
13057 x = const_double_from_real_value (TWO32r, DFmode);
13058 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13060 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13062 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13065 emit_move_insn (target, x);
13068 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13069 For x86_32, -mfpmath=sse, !optimize_size only. */
13071 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13073 REAL_VALUE_TYPE ONE16r;
13074 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13076 real_ldexp (&ONE16r, &dconst1, 16);
13077 x = const_double_from_real_value (ONE16r, SFmode);
13078 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13079 NULL, 0, OPTAB_DIRECT);
13080 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13081 NULL, 0, OPTAB_DIRECT);
13082 fp_hi = gen_reg_rtx (SFmode);
13083 fp_lo = gen_reg_rtx (SFmode);
13084 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13085 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13086 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13088 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13090 if (!rtx_equal_p (target, fp_hi))
13091 emit_move_insn (target, fp_hi);
13094 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
13095 then replicate the value for all elements of the vector
13099 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13106 v = gen_rtvec (4, value, value, value, value);
13107 return gen_rtx_CONST_VECTOR (V4SImode, v);
13111 v = gen_rtvec (2, value, value);
13112 return gen_rtx_CONST_VECTOR (V2DImode, v);
13116 v = gen_rtvec (4, value, value, value, value);
13118 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13119 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13120 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13124 v = gen_rtvec (2, value, value);
13126 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13127 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13130 gcc_unreachable ();
13134 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13135 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13136 for an SSE register. If VECT is true, then replicate the mask for
13137 all elements of the vector register. If INVERT is true, then create
13138 a mask excluding the sign bit. */
13141 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13143 enum machine_mode vec_mode, imode;
13144 HOST_WIDE_INT hi, lo;
13149 /* Find the sign bit, sign extended to 2*HWI. */
13155 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13156 lo = 0x80000000, hi = lo < 0;
13162 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13163 if (HOST_BITS_PER_WIDE_INT >= 64)
13164 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13166 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13171 vec_mode = VOIDmode;
13172 if (HOST_BITS_PER_WIDE_INT >= 64)
13175 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13182 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13186 lo = ~lo, hi = ~hi;
13192 mask = immed_double_const (lo, hi, imode);
13194 vec = gen_rtvec (2, v, mask);
13195 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13196 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13203 gcc_unreachable ();
13207 lo = ~lo, hi = ~hi;
13209 /* Force this value into the low part of a fp vector constant. */
13210 mask = immed_double_const (lo, hi, imode);
13211 mask = gen_lowpart (mode, mask);
13213 if (vec_mode == VOIDmode)
13214 return force_reg (mode, mask);
13216 v = ix86_build_const_vector (mode, vect, mask);
13217 return force_reg (vec_mode, v);
13220 /* Generate code for floating point ABS or NEG. */
13223 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
13226 rtx mask, set, use, clob, dst, src;
13227 bool use_sse = false;
13228 bool vector_mode = VECTOR_MODE_P (mode);
13229 enum machine_mode elt_mode = mode;
13233 elt_mode = GET_MODE_INNER (mode);
13236 else if (mode == TFmode)
13238 else if (TARGET_SSE_MATH)
13239 use_sse = SSE_FLOAT_MODE_P (mode);
13241 /* NEG and ABS performed with SSE use bitwise mask operations.
13242 Create the appropriate mask now. */
13244 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
13253 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
13254 set = gen_rtx_SET (VOIDmode, dst, set);
13259 set = gen_rtx_fmt_e (code, mode, src);
13260 set = gen_rtx_SET (VOIDmode, dst, set);
13263 use = gen_rtx_USE (VOIDmode, mask);
13264 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13265 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13266 gen_rtvec (3, set, use, clob)));
13273 /* Expand a copysign operation. Special case operand 0 being a constant. */
13276 ix86_expand_copysign (rtx operands[])
13278 enum machine_mode mode;
13279 rtx dest, op0, op1, mask, nmask;
13281 dest = operands[0];
13285 mode = GET_MODE (dest);
13287 if (GET_CODE (op0) == CONST_DOUBLE)
13289 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
13291 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
13292 op0 = simplify_unary_operation (ABS, mode, op0, mode);
13294 if (mode == SFmode || mode == DFmode)
13296 enum machine_mode vmode;
13298 vmode = mode == SFmode ? V4SFmode : V2DFmode;
13300 if (op0 == CONST0_RTX (mode))
13301 op0 = CONST0_RTX (vmode);
13306 if (mode == SFmode)
13307 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
13308 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13310 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
13312 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
13315 else if (op0 != CONST0_RTX (mode))
13316 op0 = force_reg (mode, op0);
13318 mask = ix86_build_signbit_mask (mode, 0, 0);
13320 if (mode == SFmode)
13321 copysign_insn = gen_copysignsf3_const;
13322 else if (mode == DFmode)
13323 copysign_insn = gen_copysigndf3_const;
13325 copysign_insn = gen_copysigntf3_const;
13327 emit_insn (copysign_insn (dest, op0, op1, mask));
13331 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
13333 nmask = ix86_build_signbit_mask (mode, 0, 1);
13334 mask = ix86_build_signbit_mask (mode, 0, 0);
13336 if (mode == SFmode)
13337 copysign_insn = gen_copysignsf3_var;
13338 else if (mode == DFmode)
13339 copysign_insn = gen_copysigndf3_var;
13341 copysign_insn = gen_copysigntf3_var;
13343 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
13347 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13348 be a constant, and so has already been expanded into a vector constant. */
13351 ix86_split_copysign_const (rtx operands[])
13353 enum machine_mode mode, vmode;
13354 rtx dest, op0, op1, mask, x;
13356 dest = operands[0];
13359 mask = operands[3];
13361 mode = GET_MODE (dest);
13362 vmode = GET_MODE (mask);
13364 dest = simplify_gen_subreg (vmode, dest, mode, 0);
13365 x = gen_rtx_AND (vmode, dest, mask);
13366 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13368 if (op0 != CONST0_RTX (vmode))
13370 x = gen_rtx_IOR (vmode, dest, op0);
13371 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13375 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13376 so we have to do two masks. */
13379 ix86_split_copysign_var (rtx operands[])
13381 enum machine_mode mode, vmode;
13382 rtx dest, scratch, op0, op1, mask, nmask, x;
13384 dest = operands[0];
13385 scratch = operands[1];
13388 nmask = operands[4];
13389 mask = operands[5];
13391 mode = GET_MODE (dest);
13392 vmode = GET_MODE (mask);
13394 if (rtx_equal_p (op0, op1))
13396 /* Shouldn't happen often (it's useless, obviously), but when it does
13397 we'd generate incorrect code if we continue below. */
13398 emit_move_insn (dest, op0);
13402 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
13404 gcc_assert (REGNO (op1) == REGNO (scratch));
13406 x = gen_rtx_AND (vmode, scratch, mask);
13407 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13410 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13411 x = gen_rtx_NOT (vmode, dest);
13412 x = gen_rtx_AND (vmode, x, op0);
13413 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13417 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
13419 x = gen_rtx_AND (vmode, scratch, mask);
13421 else /* alternative 2,4 */
13423 gcc_assert (REGNO (mask) == REGNO (scratch));
13424 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
13425 x = gen_rtx_AND (vmode, scratch, op1);
13427 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13429 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
13431 dest = simplify_gen_subreg (vmode, op0, mode, 0);
13432 x = gen_rtx_AND (vmode, dest, nmask);
13434 else /* alternative 3,4 */
13436 gcc_assert (REGNO (nmask) == REGNO (dest));
13438 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13439 x = gen_rtx_AND (vmode, dest, op0);
13441 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13444 x = gen_rtx_IOR (vmode, dest, scratch);
13445 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13448 /* Return TRUE or FALSE depending on whether the first SET in INSN
13449 has source and destination with matching CC modes, and that the
13450 CC mode is at least as constrained as REQ_MODE. */
13453 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
13456 enum machine_mode set_mode;
13458 set = PATTERN (insn);
13459 if (GET_CODE (set) == PARALLEL)
13460 set = XVECEXP (set, 0, 0);
13461 gcc_assert (GET_CODE (set) == SET);
13462 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
13464 set_mode = GET_MODE (SET_DEST (set));
13468 if (req_mode != CCNOmode
13469 && (req_mode != CCmode
13470 || XEXP (SET_SRC (set), 1) != const0_rtx))
13474 if (req_mode == CCGCmode)
13478 if (req_mode == CCGOCmode || req_mode == CCNOmode)
13482 if (req_mode == CCZmode)
13493 gcc_unreachable ();
13496 return (GET_MODE (SET_SRC (set)) == set_mode);
13499 /* Generate insn patterns to do an integer compare of OPERANDS. */
13502 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
13504 enum machine_mode cmpmode;
13507 cmpmode = SELECT_CC_MODE (code, op0, op1);
13508 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
13510 /* This is very simple, but making the interface the same as in the
13511 FP case makes the rest of the code easier. */
13512 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
13513 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
13515 /* Return the test that should be put into the flags user, i.e.
13516 the bcc, scc, or cmov instruction. */
13517 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
13520 /* Figure out whether to use ordered or unordered fp comparisons.
13521 Return the appropriate mode to use. */
13524 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
13526 /* ??? In order to make all comparisons reversible, we do all comparisons
13527 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13528 all forms trapping and nontrapping comparisons, we can make inequality
13529 comparisons trapping again, since it results in better code when using
13530 FCOM based compares. */
13531 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
13535 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
13537 enum machine_mode mode = GET_MODE (op0);
13539 if (SCALAR_FLOAT_MODE_P (mode))
13541 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
13542 return ix86_fp_compare_mode (code);
13547 /* Only zero flag is needed. */
13548 case EQ: /* ZF=0 */
13549 case NE: /* ZF!=0 */
13551 /* Codes needing carry flag. */
13552 case GEU: /* CF=0 */
13553 case LTU: /* CF=1 */
13554 /* Detect overflow checks. They need just the carry flag. */
13555 if (GET_CODE (op0) == PLUS
13556 && rtx_equal_p (op1, XEXP (op0, 0)))
13560 case GTU: /* CF=0 & ZF=0 */
13561 case LEU: /* CF=1 | ZF=1 */
13562 /* Detect overflow checks. They need just the carry flag. */
13563 if (GET_CODE (op0) == MINUS
13564 && rtx_equal_p (op1, XEXP (op0, 0)))
13568 /* Codes possibly doable only with sign flag when
13569 comparing against zero. */
13570 case GE: /* SF=OF or SF=0 */
13571 case LT: /* SF<>OF or SF=1 */
13572 if (op1 == const0_rtx)
13575 /* For other cases Carry flag is not required. */
13577 /* Codes doable only with sign flag when comparing
13578 against zero, but we miss jump instruction for it
13579 so we need to use relational tests against overflow
13580 that thus needs to be zero. */
13581 case GT: /* ZF=0 & SF=OF */
13582 case LE: /* ZF=1 | SF<>OF */
13583 if (op1 == const0_rtx)
13587 /* strcmp pattern do (use flags) and combine may ask us for proper
13592 gcc_unreachable ();
13596 /* Return the fixed registers used for condition codes. */
13599 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
13606 /* If two condition code modes are compatible, return a condition code
13607 mode which is compatible with both. Otherwise, return
13610 static enum machine_mode
13611 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
13616 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
13619 if ((m1 == CCGCmode && m2 == CCGOCmode)
13620 || (m1 == CCGOCmode && m2 == CCGCmode))
13626 gcc_unreachable ();
13656 /* These are only compatible with themselves, which we already
13662 /* Split comparison code CODE into comparisons we can do using branch
13663 instructions. BYPASS_CODE is comparison code for branch that will
13664 branch around FIRST_CODE and SECOND_CODE. If some of branches
13665 is not required, set value to UNKNOWN.
13666 We never require more than two branches. */
13669 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
13670 enum rtx_code *first_code,
13671 enum rtx_code *second_code)
13673 *first_code = code;
13674 *bypass_code = UNKNOWN;
13675 *second_code = UNKNOWN;
13677 /* The fcomi comparison sets flags as follows:
13687 case GT: /* GTU - CF=0 & ZF=0 */
13688 case GE: /* GEU - CF=0 */
13689 case ORDERED: /* PF=0 */
13690 case UNORDERED: /* PF=1 */
13691 case UNEQ: /* EQ - ZF=1 */
13692 case UNLT: /* LTU - CF=1 */
13693 case UNLE: /* LEU - CF=1 | ZF=1 */
13694 case LTGT: /* EQ - ZF=0 */
13696 case LT: /* LTU - CF=1 - fails on unordered */
13697 *first_code = UNLT;
13698 *bypass_code = UNORDERED;
13700 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
13701 *first_code = UNLE;
13702 *bypass_code = UNORDERED;
13704 case EQ: /* EQ - ZF=1 - fails on unordered */
13705 *first_code = UNEQ;
13706 *bypass_code = UNORDERED;
13708 case NE: /* NE - ZF=0 - fails on unordered */
13709 *first_code = LTGT;
13710 *second_code = UNORDERED;
13712 case UNGE: /* GEU - CF=0 - fails on unordered */
13714 *second_code = UNORDERED;
13716 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
13718 *second_code = UNORDERED;
13721 gcc_unreachable ();
13723 if (!TARGET_IEEE_FP)
13725 *second_code = UNKNOWN;
13726 *bypass_code = UNKNOWN;
13730 /* Return cost of comparison done fcom + arithmetics operations on AX.
13731 All following functions do use number of instructions as a cost metrics.
13732 In future this should be tweaked to compute bytes for optimize_size and
13733 take into account performance of various instructions on various CPUs. */
13735 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
13737 if (!TARGET_IEEE_FP)
13739 /* The cost of code output by ix86_expand_fp_compare. */
13763 gcc_unreachable ();
13767 /* Return cost of comparison done using fcomi operation.
13768 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13770 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
13772 enum rtx_code bypass_code, first_code, second_code;
13773 /* Return arbitrarily high cost when instruction is not supported - this
13774 prevents gcc from using it. */
13777 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13778 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
13781 /* Return cost of comparison done using sahf operation.
13782 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13784 ix86_fp_comparison_sahf_cost (enum rtx_code code)
13786 enum rtx_code bypass_code, first_code, second_code;
13787 /* Return arbitrarily high cost when instruction is not preferred - this
13788 avoids gcc from using it. */
13789 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
13791 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13792 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
13795 /* Compute cost of the comparison done using any method.
13796 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13798 ix86_fp_comparison_cost (enum rtx_code code)
13800 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
13803 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
13804 sahf_cost = ix86_fp_comparison_sahf_cost (code);
13806 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
13807 if (min > sahf_cost)
13809 if (min > fcomi_cost)
13814 /* Return true if we should use an FCOMI instruction for this
13818 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
13820 enum rtx_code swapped_code = swap_condition (code);
13822 return ((ix86_fp_comparison_cost (code)
13823 == ix86_fp_comparison_fcomi_cost (code))
13824 || (ix86_fp_comparison_cost (swapped_code)
13825 == ix86_fp_comparison_fcomi_cost (swapped_code)));
13828 /* Swap, force into registers, or otherwise massage the two operands
13829 to a fp comparison. The operands are updated in place; the new
13830 comparison code is returned. */
13832 static enum rtx_code
13833 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
13835 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
13836 rtx op0 = *pop0, op1 = *pop1;
13837 enum machine_mode op_mode = GET_MODE (op0);
13838 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
13840 /* All of the unordered compare instructions only work on registers.
13841 The same is true of the fcomi compare instructions. The XFmode
13842 compare instructions require registers except when comparing
13843 against zero or when converting operand 1 from fixed point to
13847 && (fpcmp_mode == CCFPUmode
13848 || (op_mode == XFmode
13849 && ! (standard_80387_constant_p (op0) == 1
13850 || standard_80387_constant_p (op1) == 1)
13851 && GET_CODE (op1) != FLOAT)
13852 || ix86_use_fcomi_compare (code)))
13854 op0 = force_reg (op_mode, op0);
13855 op1 = force_reg (op_mode, op1);
13859 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13860 things around if they appear profitable, otherwise force op0
13861 into a register. */
13863 if (standard_80387_constant_p (op0) == 0
13865 && ! (standard_80387_constant_p (op1) == 0
13869 tmp = op0, op0 = op1, op1 = tmp;
13870 code = swap_condition (code);
13874 op0 = force_reg (op_mode, op0);
13876 if (CONSTANT_P (op1))
13878 int tmp = standard_80387_constant_p (op1);
13880 op1 = validize_mem (force_const_mem (op_mode, op1));
13884 op1 = force_reg (op_mode, op1);
13887 op1 = force_reg (op_mode, op1);
13891 /* Try to rearrange the comparison to make it cheaper. */
13892 if (ix86_fp_comparison_cost (code)
13893 > ix86_fp_comparison_cost (swap_condition (code))
13894 && (REG_P (op1) || can_create_pseudo_p ()))
13897 tmp = op0, op0 = op1, op1 = tmp;
13898 code = swap_condition (code);
13900 op0 = force_reg (op_mode, op0);
13908 /* Convert comparison codes we use to represent FP comparison to integer
13909 code that will result in proper branch. Return UNKNOWN if no such code
13913 ix86_fp_compare_code_to_integer (enum rtx_code code)
13942 /* Generate insn patterns to do a floating point compare of OPERANDS. */
13945 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
13946 rtx *second_test, rtx *bypass_test)
13948 enum machine_mode fpcmp_mode, intcmp_mode;
13950 int cost = ix86_fp_comparison_cost (code);
13951 enum rtx_code bypass_code, first_code, second_code;
13953 fpcmp_mode = ix86_fp_compare_mode (code);
13954 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
13957 *second_test = NULL_RTX;
13959 *bypass_test = NULL_RTX;
13961 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13963 /* Do fcomi/sahf based test when profitable. */
13964 if (ix86_fp_comparison_arithmetics_cost (code) > cost
13965 && (bypass_code == UNKNOWN || bypass_test)
13966 && (second_code == UNKNOWN || second_test))
13968 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
13969 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
13975 gcc_assert (TARGET_SAHF);
13978 scratch = gen_reg_rtx (HImode);
13979 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
13981 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
13984 /* The FP codes work out to act like unsigned. */
13985 intcmp_mode = fpcmp_mode;
13987 if (bypass_code != UNKNOWN)
13988 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
13989 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13991 if (second_code != UNKNOWN)
13992 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
13993 gen_rtx_REG (intcmp_mode, FLAGS_REG),
13998 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
13999 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14000 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14002 scratch = gen_reg_rtx (HImode);
14003 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14005 /* In the unordered case, we have to check C2 for NaN's, which
14006 doesn't happen to work out to anything nice combination-wise.
14007 So do some bit twiddling on the value we've got in AH to come
14008 up with an appropriate set of condition codes. */
14010 intcmp_mode = CCNOmode;
14015 if (code == GT || !TARGET_IEEE_FP)
14017 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14022 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14023 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14024 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14025 intcmp_mode = CCmode;
14031 if (code == LT && TARGET_IEEE_FP)
14033 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14034 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
14035 intcmp_mode = CCmode;
14040 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
14046 if (code == GE || !TARGET_IEEE_FP)
14048 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14053 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14054 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14061 if (code == LE && TARGET_IEEE_FP)
14063 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14064 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14065 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14066 intcmp_mode = CCmode;
14071 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14077 if (code == EQ && TARGET_IEEE_FP)
14079 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14080 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14081 intcmp_mode = CCmode;
14086 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14093 if (code == NE && TARGET_IEEE_FP)
14095 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14096 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14102 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14108 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14112 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14117 gcc_unreachable ();
14121 /* Return the test that should be put into the flags user, i.e.
14122 the bcc, scc, or cmov instruction. */
14123 return gen_rtx_fmt_ee (code, VOIDmode,
14124 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14129 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
14132 op0 = ix86_compare_op0;
14133 op1 = ix86_compare_op1;
14136 *second_test = NULL_RTX;
14138 *bypass_test = NULL_RTX;
14140 if (ix86_compare_emitted)
14142 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
14143 ix86_compare_emitted = NULL_RTX;
14145 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14147 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14148 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14149 second_test, bypass_test);
14152 ret = ix86_expand_int_compare (code, op0, op1);
14157 /* Return true if the CODE will result in nontrivial jump sequence. */
14159 ix86_fp_jump_nontrivial_p (enum rtx_code code)
14161 enum rtx_code bypass_code, first_code, second_code;
14164 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14165 return bypass_code != UNKNOWN || second_code != UNKNOWN;
14169 ix86_expand_branch (enum rtx_code code, rtx label)
14173 /* If we have emitted a compare insn, go straight to simple.
14174 ix86_expand_compare won't emit anything if ix86_compare_emitted
14176 if (ix86_compare_emitted)
14179 switch (GET_MODE (ix86_compare_op0))
14185 tmp = ix86_expand_compare (code, NULL, NULL);
14186 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14187 gen_rtx_LABEL_REF (VOIDmode, label),
14189 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14198 enum rtx_code bypass_code, first_code, second_code;
14200 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
14201 &ix86_compare_op1);
14203 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14205 /* Check whether we will use the natural sequence with one jump. If
14206 so, we can expand jump early. Otherwise delay expansion by
14207 creating compound insn to not confuse optimizers. */
14208 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
14210 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
14211 gen_rtx_LABEL_REF (VOIDmode, label),
14212 pc_rtx, NULL_RTX, NULL_RTX);
14216 tmp = gen_rtx_fmt_ee (code, VOIDmode,
14217 ix86_compare_op0, ix86_compare_op1);
14218 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14219 gen_rtx_LABEL_REF (VOIDmode, label),
14221 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
14223 use_fcomi = ix86_use_fcomi_compare (code);
14224 vec = rtvec_alloc (3 + !use_fcomi);
14225 RTVEC_ELT (vec, 0) = tmp;
14227 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
14229 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
14232 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
14234 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
14243 /* Expand DImode branch into multiple compare+branch. */
14245 rtx lo[2], hi[2], label2;
14246 enum rtx_code code1, code2, code3;
14247 enum machine_mode submode;
14249 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14251 tmp = ix86_compare_op0;
14252 ix86_compare_op0 = ix86_compare_op1;
14253 ix86_compare_op1 = tmp;
14254 code = swap_condition (code);
14256 if (GET_MODE (ix86_compare_op0) == DImode)
14258 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14259 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14264 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14265 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14269 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14270 avoid two branches. This costs one extra insn, so disable when
14271 optimizing for size. */
14273 if ((code == EQ || code == NE)
14274 && (!optimize_insn_for_size_p ()
14275 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14280 if (hi[1] != const0_rtx)
14281 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14282 NULL_RTX, 0, OPTAB_WIDEN);
14285 if (lo[1] != const0_rtx)
14286 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14287 NULL_RTX, 0, OPTAB_WIDEN);
14289 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14290 NULL_RTX, 0, OPTAB_WIDEN);
14292 ix86_compare_op0 = tmp;
14293 ix86_compare_op1 = const0_rtx;
14294 ix86_expand_branch (code, label);
14298 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14299 op1 is a constant and the low word is zero, then we can just
14300 examine the high word. Similarly for low word -1 and
14301 less-or-equal-than or greater-than. */
14303 if (CONST_INT_P (hi[1]))
14306 case LT: case LTU: case GE: case GEU:
14307 if (lo[1] == const0_rtx)
14309 ix86_compare_op0 = hi[0];
14310 ix86_compare_op1 = hi[1];
14311 ix86_expand_branch (code, label);
14315 case LE: case LEU: case GT: case GTU:
14316 if (lo[1] == constm1_rtx)
14318 ix86_compare_op0 = hi[0];
14319 ix86_compare_op1 = hi[1];
14320 ix86_expand_branch (code, label);
14328 /* Otherwise, we need two or three jumps. */
14330 label2 = gen_label_rtx ();
14333 code2 = swap_condition (code);
14334 code3 = unsigned_condition (code);
14338 case LT: case GT: case LTU: case GTU:
14341 case LE: code1 = LT; code2 = GT; break;
14342 case GE: code1 = GT; code2 = LT; break;
14343 case LEU: code1 = LTU; code2 = GTU; break;
14344 case GEU: code1 = GTU; code2 = LTU; break;
14346 case EQ: code1 = UNKNOWN; code2 = NE; break;
14347 case NE: code2 = UNKNOWN; break;
14350 gcc_unreachable ();
14355 * if (hi(a) < hi(b)) goto true;
14356 * if (hi(a) > hi(b)) goto false;
14357 * if (lo(a) < lo(b)) goto true;
14361 ix86_compare_op0 = hi[0];
14362 ix86_compare_op1 = hi[1];
14364 if (code1 != UNKNOWN)
14365 ix86_expand_branch (code1, label);
14366 if (code2 != UNKNOWN)
14367 ix86_expand_branch (code2, label2);
14369 ix86_compare_op0 = lo[0];
14370 ix86_compare_op1 = lo[1];
14371 ix86_expand_branch (code3, label);
14373 if (code2 != UNKNOWN)
14374 emit_label (label2);
14379 gcc_unreachable ();
14383 /* Split branch based on floating point condition. */
14385 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14386 rtx target1, rtx target2, rtx tmp, rtx pushed)
14388 rtx second, bypass;
14389 rtx label = NULL_RTX;
14391 int bypass_probability = -1, second_probability = -1, probability = -1;
14394 if (target2 != pc_rtx)
14397 code = reverse_condition_maybe_unordered (code);
14402 condition = ix86_expand_fp_compare (code, op1, op2,
14403 tmp, &second, &bypass);
14405 /* Remove pushed operand from stack. */
14407 ix86_free_from_memory (GET_MODE (pushed));
14409 if (split_branch_probability >= 0)
14411 /* Distribute the probabilities across the jumps.
14412 Assume the BYPASS and SECOND to be always test
14414 probability = split_branch_probability;
14416 /* Value of 1 is low enough to make no need for probability
14417 to be updated. Later we may run some experiments and see
14418 if unordered values are more frequent in practice. */
14420 bypass_probability = 1;
14422 second_probability = 1;
14424 if (bypass != NULL_RTX)
14426 label = gen_label_rtx ();
14427 i = emit_jump_insn (gen_rtx_SET
14429 gen_rtx_IF_THEN_ELSE (VOIDmode,
14431 gen_rtx_LABEL_REF (VOIDmode,
14434 if (bypass_probability >= 0)
14436 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14437 GEN_INT (bypass_probability),
14440 i = emit_jump_insn (gen_rtx_SET
14442 gen_rtx_IF_THEN_ELSE (VOIDmode,
14443 condition, target1, target2)));
14444 if (probability >= 0)
14446 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14447 GEN_INT (probability),
14449 if (second != NULL_RTX)
14451 i = emit_jump_insn (gen_rtx_SET
14453 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
14455 if (second_probability >= 0)
14457 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14458 GEN_INT (second_probability),
14461 if (label != NULL_RTX)
14462 emit_label (label);
14466 ix86_expand_setcc (enum rtx_code code, rtx dest)
14468 rtx ret, tmp, tmpreg, equiv;
14469 rtx second_test, bypass_test;
14471 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
14472 return 0; /* FAIL */
14474 gcc_assert (GET_MODE (dest) == QImode);
14476 ret = ix86_expand_compare (code, &second_test, &bypass_test);
14477 PUT_MODE (ret, QImode);
14482 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
14483 if (bypass_test || second_test)
14485 rtx test = second_test;
14487 rtx tmp2 = gen_reg_rtx (QImode);
14490 gcc_assert (!second_test);
14491 test = bypass_test;
14493 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
14495 PUT_MODE (test, QImode);
14496 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
14499 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
14501 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
14504 /* Attach a REG_EQUAL note describing the comparison result. */
14505 if (ix86_compare_op0 && ix86_compare_op1)
14507 equiv = simplify_gen_relational (code, QImode,
14508 GET_MODE (ix86_compare_op0),
14509 ix86_compare_op0, ix86_compare_op1);
14510 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
14513 return 1; /* DONE */
14516 /* Expand comparison setting or clearing carry flag. Return true when
14517 successful and set pop for the operation. */
14519 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
14521 enum machine_mode mode =
14522 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
14524 /* Do not handle DImode compares that go through special path. */
14525 if (mode == (TARGET_64BIT ? TImode : DImode))
14528 if (SCALAR_FLOAT_MODE_P (mode))
14530 rtx second_test = NULL, bypass_test = NULL;
14531 rtx compare_op, compare_seq;
14533 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14535 /* Shortcut: following common codes never translate
14536 into carry flag compares. */
14537 if (code == EQ || code == NE || code == UNEQ || code == LTGT
14538 || code == ORDERED || code == UNORDERED)
14541 /* These comparisons require zero flag; swap operands so they won't. */
14542 if ((code == GT || code == UNLE || code == LE || code == UNGT)
14543 && !TARGET_IEEE_FP)
14548 code = swap_condition (code);
14551 /* Try to expand the comparison and verify that we end up with
14552 carry flag based comparison. This fails to be true only when
14553 we decide to expand comparison using arithmetic that is not
14554 too common scenario. */
14556 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14557 &second_test, &bypass_test);
14558 compare_seq = get_insns ();
14561 if (second_test || bypass_test)
14564 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14565 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14566 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
14568 code = GET_CODE (compare_op);
14570 if (code != LTU && code != GEU)
14573 emit_insn (compare_seq);
14578 if (!INTEGRAL_MODE_P (mode))
14587 /* Convert a==0 into (unsigned)a<1. */
14590 if (op1 != const0_rtx)
14593 code = (code == EQ ? LTU : GEU);
14596 /* Convert a>b into b<a or a>=b-1. */
14599 if (CONST_INT_P (op1))
14601 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
14602 /* Bail out on overflow. We still can swap operands but that
14603 would force loading of the constant into register. */
14604 if (op1 == const0_rtx
14605 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
14607 code = (code == GTU ? GEU : LTU);
14614 code = (code == GTU ? LTU : GEU);
14618 /* Convert a>=0 into (unsigned)a<0x80000000. */
14621 if (mode == DImode || op1 != const0_rtx)
14623 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14624 code = (code == LT ? GEU : LTU);
14628 if (mode == DImode || op1 != constm1_rtx)
14630 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14631 code = (code == LE ? GEU : LTU);
14637 /* Swapping operands may cause constant to appear as first operand. */
14638 if (!nonimmediate_operand (op0, VOIDmode))
14640 if (!can_create_pseudo_p ())
14642 op0 = force_reg (mode, op0);
14644 ix86_compare_op0 = op0;
14645 ix86_compare_op1 = op1;
14646 *pop = ix86_expand_compare (code, NULL, NULL);
14647 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
14652 ix86_expand_int_movcc (rtx operands[])
14654 enum rtx_code code = GET_CODE (operands[1]), compare_code;
14655 rtx compare_seq, compare_op;
14656 rtx second_test, bypass_test;
14657 enum machine_mode mode = GET_MODE (operands[0]);
14658 bool sign_bit_compare_p = false;;
14661 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14662 compare_seq = get_insns ();
14665 compare_code = GET_CODE (compare_op);
14667 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
14668 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
14669 sign_bit_compare_p = true;
14671 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14672 HImode insns, we'd be swallowed in word prefix ops. */
14674 if ((mode != HImode || TARGET_FAST_PREFIX)
14675 && (mode != (TARGET_64BIT ? TImode : DImode))
14676 && CONST_INT_P (operands[2])
14677 && CONST_INT_P (operands[3]))
14679 rtx out = operands[0];
14680 HOST_WIDE_INT ct = INTVAL (operands[2]);
14681 HOST_WIDE_INT cf = INTVAL (operands[3]);
14682 HOST_WIDE_INT diff;
14685 /* Sign bit compares are better done using shifts than we do by using
14687 if (sign_bit_compare_p
14688 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
14689 ix86_compare_op1, &compare_op))
14691 /* Detect overlap between destination and compare sources. */
14694 if (!sign_bit_compare_p)
14696 bool fpcmp = false;
14698 compare_code = GET_CODE (compare_op);
14700 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14701 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14704 compare_code = ix86_fp_compare_code_to_integer (compare_code);
14707 /* To simplify rest of code, restrict to the GEU case. */
14708 if (compare_code == LTU)
14710 HOST_WIDE_INT tmp = ct;
14713 compare_code = reverse_condition (compare_code);
14714 code = reverse_condition (code);
14719 PUT_CODE (compare_op,
14720 reverse_condition_maybe_unordered
14721 (GET_CODE (compare_op)));
14723 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14727 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
14728 || reg_overlap_mentioned_p (out, ix86_compare_op1))
14729 tmp = gen_reg_rtx (mode);
14731 if (mode == DImode)
14732 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
14734 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
14738 if (code == GT || code == GE)
14739 code = reverse_condition (code);
14742 HOST_WIDE_INT tmp = ct;
14747 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
14748 ix86_compare_op1, VOIDmode, 0, -1);
14761 tmp = expand_simple_binop (mode, PLUS,
14763 copy_rtx (tmp), 1, OPTAB_DIRECT);
14774 tmp = expand_simple_binop (mode, IOR,
14776 copy_rtx (tmp), 1, OPTAB_DIRECT);
14778 else if (diff == -1 && ct)
14788 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14790 tmp = expand_simple_binop (mode, PLUS,
14791 copy_rtx (tmp), GEN_INT (cf),
14792 copy_rtx (tmp), 1, OPTAB_DIRECT);
14800 * andl cf - ct, dest
14810 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14813 tmp = expand_simple_binop (mode, AND,
14815 gen_int_mode (cf - ct, mode),
14816 copy_rtx (tmp), 1, OPTAB_DIRECT);
14818 tmp = expand_simple_binop (mode, PLUS,
14819 copy_rtx (tmp), GEN_INT (ct),
14820 copy_rtx (tmp), 1, OPTAB_DIRECT);
14823 if (!rtx_equal_p (tmp, out))
14824 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
14826 return 1; /* DONE */
14831 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14834 tmp = ct, ct = cf, cf = tmp;
14837 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14839 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14841 /* We may be reversing unordered compare to normal compare, that
14842 is not valid in general (we may convert non-trapping condition
14843 to trapping one), however on i386 we currently emit all
14844 comparisons unordered. */
14845 compare_code = reverse_condition_maybe_unordered (compare_code);
14846 code = reverse_condition_maybe_unordered (code);
14850 compare_code = reverse_condition (compare_code);
14851 code = reverse_condition (code);
14855 compare_code = UNKNOWN;
14856 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
14857 && CONST_INT_P (ix86_compare_op1))
14859 if (ix86_compare_op1 == const0_rtx
14860 && (code == LT || code == GE))
14861 compare_code = code;
14862 else if (ix86_compare_op1 == constm1_rtx)
14866 else if (code == GT)
14871 /* Optimize dest = (op0 < 0) ? -1 : cf. */
14872 if (compare_code != UNKNOWN
14873 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
14874 && (cf == -1 || ct == -1))
14876 /* If lea code below could be used, only optimize
14877 if it results in a 2 insn sequence. */
14879 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
14880 || diff == 3 || diff == 5 || diff == 9)
14881 || (compare_code == LT && ct == -1)
14882 || (compare_code == GE && cf == -1))
14885 * notl op1 (if necessary)
14893 code = reverse_condition (code);
14896 out = emit_store_flag (out, code, ix86_compare_op0,
14897 ix86_compare_op1, VOIDmode, 0, -1);
14899 out = expand_simple_binop (mode, IOR,
14901 out, 1, OPTAB_DIRECT);
14902 if (out != operands[0])
14903 emit_move_insn (operands[0], out);
14905 return 1; /* DONE */
14910 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
14911 || diff == 3 || diff == 5 || diff == 9)
14912 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
14914 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
14920 * lea cf(dest*(ct-cf)),dest
14924 * This also catches the degenerate setcc-only case.
14930 out = emit_store_flag (out, code, ix86_compare_op0,
14931 ix86_compare_op1, VOIDmode, 0, 1);
14934 /* On x86_64 the lea instruction operates on Pmode, so we need
14935 to get arithmetics done in proper mode to match. */
14937 tmp = copy_rtx (out);
14941 out1 = copy_rtx (out);
14942 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
14946 tmp = gen_rtx_PLUS (mode, tmp, out1);
14952 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
14955 if (!rtx_equal_p (tmp, out))
14958 out = force_operand (tmp, copy_rtx (out));
14960 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
14962 if (!rtx_equal_p (out, operands[0]))
14963 emit_move_insn (operands[0], copy_rtx (out));
14965 return 1; /* DONE */
14969 * General case: Jumpful:
14970 * xorl dest,dest cmpl op1, op2
14971 * cmpl op1, op2 movl ct, dest
14972 * setcc dest jcc 1f
14973 * decl dest movl cf, dest
14974 * andl (cf-ct),dest 1:
14977 * Size 20. Size 14.
14979 * This is reasonably steep, but branch mispredict costs are
14980 * high on modern cpus, so consider failing only if optimizing
14984 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
14985 && BRANCH_COST (optimize_insn_for_speed_p (),
14990 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14995 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14997 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14999 /* We may be reversing unordered compare to normal compare,
15000 that is not valid in general (we may convert non-trapping
15001 condition to trapping one), however on i386 we currently
15002 emit all comparisons unordered. */
15003 code = reverse_condition_maybe_unordered (code);
15007 code = reverse_condition (code);
15008 if (compare_code != UNKNOWN)
15009 compare_code = reverse_condition (compare_code);
15013 if (compare_code != UNKNOWN)
15015 /* notl op1 (if needed)
15020 For x < 0 (resp. x <= -1) there will be no notl,
15021 so if possible swap the constants to get rid of the
15023 True/false will be -1/0 while code below (store flag
15024 followed by decrement) is 0/-1, so the constants need
15025 to be exchanged once more. */
15027 if (compare_code == GE || !cf)
15029 code = reverse_condition (code);
15034 HOST_WIDE_INT tmp = cf;
15039 out = emit_store_flag (out, code, ix86_compare_op0,
15040 ix86_compare_op1, VOIDmode, 0, -1);
15044 out = emit_store_flag (out, code, ix86_compare_op0,
15045 ix86_compare_op1, VOIDmode, 0, 1);
15047 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15048 copy_rtx (out), 1, OPTAB_DIRECT);
15051 out = expand_simple_binop (mode, AND, copy_rtx (out),
15052 gen_int_mode (cf - ct, mode),
15053 copy_rtx (out), 1, OPTAB_DIRECT);
15055 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15056 copy_rtx (out), 1, OPTAB_DIRECT);
15057 if (!rtx_equal_p (out, operands[0]))
15058 emit_move_insn (operands[0], copy_rtx (out));
15060 return 1; /* DONE */
15064 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15066 /* Try a few things more with specific constants and a variable. */
15069 rtx var, orig_out, out, tmp;
15071 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15072 return 0; /* FAIL */
15074 /* If one of the two operands is an interesting constant, load a
15075 constant with the above and mask it in with a logical operation. */
15077 if (CONST_INT_P (operands[2]))
15080 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15081 operands[3] = constm1_rtx, op = and_optab;
15082 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15083 operands[3] = const0_rtx, op = ior_optab;
15085 return 0; /* FAIL */
15087 else if (CONST_INT_P (operands[3]))
15090 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15091 operands[2] = constm1_rtx, op = and_optab;
15092 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15093 operands[2] = const0_rtx, op = ior_optab;
15095 return 0; /* FAIL */
15098 return 0; /* FAIL */
15100 orig_out = operands[0];
15101 tmp = gen_reg_rtx (mode);
15104 /* Recurse to get the constant loaded. */
15105 if (ix86_expand_int_movcc (operands) == 0)
15106 return 0; /* FAIL */
15108 /* Mask in the interesting variable. */
15109 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15111 if (!rtx_equal_p (out, orig_out))
15112 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15114 return 1; /* DONE */
15118 * For comparison with above,
15128 if (! nonimmediate_operand (operands[2], mode))
15129 operands[2] = force_reg (mode, operands[2]);
15130 if (! nonimmediate_operand (operands[3], mode))
15131 operands[3] = force_reg (mode, operands[3]);
15133 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15135 rtx tmp = gen_reg_rtx (mode);
15136 emit_move_insn (tmp, operands[3]);
15139 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15141 rtx tmp = gen_reg_rtx (mode);
15142 emit_move_insn (tmp, operands[2]);
15146 if (! register_operand (operands[2], VOIDmode)
15148 || ! register_operand (operands[3], VOIDmode)))
15149 operands[2] = force_reg (mode, operands[2]);
15152 && ! register_operand (operands[3], VOIDmode))
15153 operands[3] = force_reg (mode, operands[3]);
15155 emit_insn (compare_seq);
15156 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15157 gen_rtx_IF_THEN_ELSE (mode,
15158 compare_op, operands[2],
15161 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15162 gen_rtx_IF_THEN_ELSE (mode,
15164 copy_rtx (operands[3]),
15165 copy_rtx (operands[0]))));
15167 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15168 gen_rtx_IF_THEN_ELSE (mode,
15170 copy_rtx (operands[2]),
15171 copy_rtx (operands[0]))));
15173 return 1; /* DONE */
15176 /* Swap, force into registers, or otherwise massage the two operands
15177 to an sse comparison with a mask result. Thus we differ a bit from
15178 ix86_prepare_fp_compare_args which expects to produce a flags result.
15180 The DEST operand exists to help determine whether to commute commutative
15181 operators. The POP0/POP1 operands are updated in place. The new
15182 comparison code is returned, or UNKNOWN if not implementable. */
15184 static enum rtx_code
15185 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15186 rtx *pop0, rtx *pop1)
15194 /* We have no LTGT as an operator. We could implement it with
15195 NE & ORDERED, but this requires an extra temporary. It's
15196 not clear that it's worth it. */
15203 /* These are supported directly. */
15210 /* For commutative operators, try to canonicalize the destination
15211 operand to be first in the comparison - this helps reload to
15212 avoid extra moves. */
15213 if (!dest || !rtx_equal_p (dest, *pop1))
15221 /* These are not supported directly. Swap the comparison operands
15222 to transform into something that is supported. */
15226 code = swap_condition (code);
15230 gcc_unreachable ();
15236 /* Detect conditional moves that exactly match min/max operational
15237 semantics. Note that this is IEEE safe, as long as we don't
15238 interchange the operands.
15240 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15241 and TRUE if the operation is successful and instructions are emitted. */
15244 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15245 rtx cmp_op1, rtx if_true, rtx if_false)
15247 enum machine_mode mode;
15253 else if (code == UNGE)
15256 if_true = if_false;
15262 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15264 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15269 mode = GET_MODE (dest);
15271 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15272 but MODE may be a vector mode and thus not appropriate. */
15273 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15275 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15278 if_true = force_reg (mode, if_true);
15279 v = gen_rtvec (2, if_true, if_false);
15280 tmp = gen_rtx_UNSPEC (mode, v, u);
15284 code = is_min ? SMIN : SMAX;
15285 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15288 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15292 /* Expand an sse vector comparison. Return the register with the result. */
15295 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15296 rtx op_true, rtx op_false)
15298 enum machine_mode mode = GET_MODE (dest);
15301 cmp_op0 = force_reg (mode, cmp_op0);
15302 if (!nonimmediate_operand (cmp_op1, mode))
15303 cmp_op1 = force_reg (mode, cmp_op1);
15306 || reg_overlap_mentioned_p (dest, op_true)
15307 || reg_overlap_mentioned_p (dest, op_false))
15308 dest = gen_reg_rtx (mode);
15310 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15311 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15316 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15317 operations. This is used for both scalar and vector conditional moves. */
15320 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15322 enum machine_mode mode = GET_MODE (dest);
15325 if (op_false == CONST0_RTX (mode))
15327 op_true = force_reg (mode, op_true);
15328 x = gen_rtx_AND (mode, cmp, op_true);
15329 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15331 else if (op_true == CONST0_RTX (mode))
15333 op_false = force_reg (mode, op_false);
15334 x = gen_rtx_NOT (mode, cmp);
15335 x = gen_rtx_AND (mode, x, op_false);
15336 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15338 else if (TARGET_SSE5)
15340 rtx pcmov = gen_rtx_SET (mode, dest,
15341 gen_rtx_IF_THEN_ELSE (mode, cmp,
15348 op_true = force_reg (mode, op_true);
15349 op_false = force_reg (mode, op_false);
15351 t2 = gen_reg_rtx (mode);
15353 t3 = gen_reg_rtx (mode);
15357 x = gen_rtx_AND (mode, op_true, cmp);
15358 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15360 x = gen_rtx_NOT (mode, cmp);
15361 x = gen_rtx_AND (mode, x, op_false);
15362 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15364 x = gen_rtx_IOR (mode, t3, t2);
15365 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15369 /* Expand a floating-point conditional move. Return true if successful. */
15372 ix86_expand_fp_movcc (rtx operands[])
15374 enum machine_mode mode = GET_MODE (operands[0]);
15375 enum rtx_code code = GET_CODE (operands[1]);
15376 rtx tmp, compare_op, second_test, bypass_test;
15378 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15380 enum machine_mode cmode;
15382 /* Since we've no cmove for sse registers, don't force bad register
15383 allocation just to gain access to it. Deny movcc when the
15384 comparison mode doesn't match the move mode. */
15385 cmode = GET_MODE (ix86_compare_op0);
15386 if (cmode == VOIDmode)
15387 cmode = GET_MODE (ix86_compare_op1);
15391 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15393 &ix86_compare_op1);
15394 if (code == UNKNOWN)
15397 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15398 ix86_compare_op1, operands[2],
15402 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15403 ix86_compare_op1, operands[2], operands[3]);
15404 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15408 /* The floating point conditional move instructions don't directly
15409 support conditions resulting from a signed integer comparison. */
15411 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15413 /* The floating point conditional move instructions don't directly
15414 support signed integer comparisons. */
15416 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15418 gcc_assert (!second_test && !bypass_test);
15419 tmp = gen_reg_rtx (QImode);
15420 ix86_expand_setcc (code, tmp);
15422 ix86_compare_op0 = tmp;
15423 ix86_compare_op1 = const0_rtx;
15424 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15426 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15428 tmp = gen_reg_rtx (mode);
15429 emit_move_insn (tmp, operands[3]);
15432 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15434 tmp = gen_reg_rtx (mode);
15435 emit_move_insn (tmp, operands[2]);
15439 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15440 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15441 operands[2], operands[3])));
15443 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15444 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
15445 operands[3], operands[0])));
15447 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15448 gen_rtx_IF_THEN_ELSE (mode, second_test,
15449 operands[2], operands[0])));
15454 /* Expand a floating-point vector conditional move; a vcond operation
15455 rather than a movcc operation. */
15458 ix86_expand_fp_vcond (rtx operands[])
15460 enum rtx_code code = GET_CODE (operands[3]);
15463 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15464 &operands[4], &operands[5]);
15465 if (code == UNKNOWN)
15468 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15469 operands[5], operands[1], operands[2]))
15472 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15473 operands[1], operands[2]);
15474 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15478 /* Expand a signed/unsigned integral vector conditional move. */
15481 ix86_expand_int_vcond (rtx operands[])
15483 enum machine_mode mode = GET_MODE (operands[0]);
15484 enum rtx_code code = GET_CODE (operands[3]);
15485 bool negate = false;
15488 cop0 = operands[4];
15489 cop1 = operands[5];
15491 /* SSE5 supports all of the comparisons on all vector int types. */
15494 /* Canonicalize the comparison to EQ, GT, GTU. */
15505 code = reverse_condition (code);
15511 code = reverse_condition (code);
15517 code = swap_condition (code);
15518 x = cop0, cop0 = cop1, cop1 = x;
15522 gcc_unreachable ();
15525 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15526 if (mode == V2DImode)
15531 /* SSE4.1 supports EQ. */
15532 if (!TARGET_SSE4_1)
15538 /* SSE4.2 supports GT/GTU. */
15539 if (!TARGET_SSE4_2)
15544 gcc_unreachable ();
15548 /* Unsigned parallel compare is not supported by the hardware. Play some
15549 tricks to turn this into a signed comparison against 0. */
15552 cop0 = force_reg (mode, cop0);
15561 /* Perform a parallel modulo subtraction. */
15562 t1 = gen_reg_rtx (mode);
15563 emit_insn ((mode == V4SImode
15565 : gen_subv2di3) (t1, cop0, cop1));
15567 /* Extract the original sign bit of op0. */
15568 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
15570 t2 = gen_reg_rtx (mode);
15571 emit_insn ((mode == V4SImode
15573 : gen_andv2di3) (t2, cop0, mask));
15575 /* XOR it back into the result of the subtraction. This results
15576 in the sign bit set iff we saw unsigned underflow. */
15577 x = gen_reg_rtx (mode);
15578 emit_insn ((mode == V4SImode
15580 : gen_xorv2di3) (x, t1, t2));
15588 /* Perform a parallel unsigned saturating subtraction. */
15589 x = gen_reg_rtx (mode);
15590 emit_insn (gen_rtx_SET (VOIDmode, x,
15591 gen_rtx_US_MINUS (mode, cop0, cop1)));
15598 gcc_unreachable ();
15602 cop1 = CONST0_RTX (mode);
15606 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
15607 operands[1+negate], operands[2-negate]);
15609 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
15610 operands[2-negate]);
15614 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15615 true if we should do zero extension, else sign extension. HIGH_P is
15616 true if we want the N/2 high elements, else the low elements. */
15619 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15621 enum machine_mode imode = GET_MODE (operands[1]);
15622 rtx (*unpack)(rtx, rtx, rtx);
15629 unpack = gen_vec_interleave_highv16qi;
15631 unpack = gen_vec_interleave_lowv16qi;
15635 unpack = gen_vec_interleave_highv8hi;
15637 unpack = gen_vec_interleave_lowv8hi;
15641 unpack = gen_vec_interleave_highv4si;
15643 unpack = gen_vec_interleave_lowv4si;
15646 gcc_unreachable ();
15649 dest = gen_lowpart (imode, operands[0]);
15652 se = force_reg (imode, CONST0_RTX (imode));
15654 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
15655 operands[1], pc_rtx, pc_rtx);
15657 emit_insn (unpack (dest, operands[1], se));
15660 /* This function performs the same task as ix86_expand_sse_unpack,
15661 but with SSE4.1 instructions. */
15664 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15666 enum machine_mode imode = GET_MODE (operands[1]);
15667 rtx (*unpack)(rtx, rtx);
15674 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
15676 unpack = gen_sse4_1_extendv8qiv8hi2;
15680 unpack = gen_sse4_1_zero_extendv4hiv4si2;
15682 unpack = gen_sse4_1_extendv4hiv4si2;
15686 unpack = gen_sse4_1_zero_extendv2siv2di2;
15688 unpack = gen_sse4_1_extendv2siv2di2;
15691 gcc_unreachable ();
15694 dest = operands[0];
15697 /* Shift higher 8 bytes to lower 8 bytes. */
15698 src = gen_reg_rtx (imode);
15699 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
15700 gen_lowpart (TImode, operands[1]),
15706 emit_insn (unpack (dest, src));
15709 /* This function performs the same task as ix86_expand_sse_unpack,
15710 but with sse5 instructions. */
15713 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15715 enum machine_mode imode = GET_MODE (operands[1]);
15716 int pperm_bytes[16];
15718 int h = (high_p) ? 8 : 0;
15721 rtvec v = rtvec_alloc (16);
15724 rtx op0 = operands[0], op1 = operands[1];
15729 vs = rtvec_alloc (8);
15730 h2 = (high_p) ? 8 : 0;
15731 for (i = 0; i < 8; i++)
15733 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
15734 pperm_bytes[2*i+1] = ((unsigned_p)
15736 : PPERM_SIGN | PPERM_SRC2 | i | h);
15739 for (i = 0; i < 16; i++)
15740 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15742 for (i = 0; i < 8; i++)
15743 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15745 p = gen_rtx_PARALLEL (VOIDmode, vs);
15746 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15748 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
15750 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
15754 vs = rtvec_alloc (4);
15755 h2 = (high_p) ? 4 : 0;
15756 for (i = 0; i < 4; i++)
15758 sign_extend = ((unsigned_p)
15760 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
15761 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
15762 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
15763 pperm_bytes[4*i+2] = sign_extend;
15764 pperm_bytes[4*i+3] = sign_extend;
15767 for (i = 0; i < 16; i++)
15768 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15770 for (i = 0; i < 4; i++)
15771 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15773 p = gen_rtx_PARALLEL (VOIDmode, vs);
15774 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15776 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
15778 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
15782 vs = rtvec_alloc (2);
15783 h2 = (high_p) ? 2 : 0;
15784 for (i = 0; i < 2; i++)
15786 sign_extend = ((unsigned_p)
15788 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
15789 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
15790 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
15791 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
15792 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
15793 pperm_bytes[8*i+4] = sign_extend;
15794 pperm_bytes[8*i+5] = sign_extend;
15795 pperm_bytes[8*i+6] = sign_extend;
15796 pperm_bytes[8*i+7] = sign_extend;
15799 for (i = 0; i < 16; i++)
15800 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15802 for (i = 0; i < 2; i++)
15803 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15805 p = gen_rtx_PARALLEL (VOIDmode, vs);
15806 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15808 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
15810 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
15814 gcc_unreachable ();
15820 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15821 next narrower integer vector type */
15823 ix86_expand_sse5_pack (rtx operands[3])
15825 enum machine_mode imode = GET_MODE (operands[0]);
15826 int pperm_bytes[16];
15828 rtvec v = rtvec_alloc (16);
15830 rtx op0 = operands[0];
15831 rtx op1 = operands[1];
15832 rtx op2 = operands[2];
15837 for (i = 0; i < 8; i++)
15839 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
15840 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
15843 for (i = 0; i < 16; i++)
15844 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15846 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15847 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
15851 for (i = 0; i < 4; i++)
15853 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
15854 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
15855 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
15856 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
15859 for (i = 0; i < 16; i++)
15860 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15862 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15863 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
15867 for (i = 0; i < 2; i++)
15869 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
15870 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
15871 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
15872 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
15873 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
15874 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
15875 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
15876 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
15879 for (i = 0; i < 16; i++)
15880 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15882 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15883 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
15887 gcc_unreachable ();
15893 /* Expand conditional increment or decrement using adb/sbb instructions.
15894 The default case using setcc followed by the conditional move can be
15895 done by generic code. */
15897 ix86_expand_int_addcc (rtx operands[])
15899 enum rtx_code code = GET_CODE (operands[1]);
15901 rtx val = const0_rtx;
15902 bool fpcmp = false;
15903 enum machine_mode mode = GET_MODE (operands[0]);
15905 if (operands[3] != const1_rtx
15906 && operands[3] != constm1_rtx)
15908 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15909 ix86_compare_op1, &compare_op))
15911 code = GET_CODE (compare_op);
15913 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15914 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15917 code = ix86_fp_compare_code_to_integer (code);
15924 PUT_CODE (compare_op,
15925 reverse_condition_maybe_unordered
15926 (GET_CODE (compare_op)));
15928 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15930 PUT_MODE (compare_op, mode);
15932 /* Construct either adc or sbb insn. */
15933 if ((code == LTU) == (operands[3] == constm1_rtx))
15935 switch (GET_MODE (operands[0]))
15938 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
15941 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
15944 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
15947 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15950 gcc_unreachable ();
15955 switch (GET_MODE (operands[0]))
15958 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
15961 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
15964 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
15967 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
15970 gcc_unreachable ();
15973 return 1; /* DONE */
15977 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
15978 works for floating pointer parameters and nonoffsetable memories.
15979 For pushes, it returns just stack offsets; the values will be saved
15980 in the right order. Maximally three parts are generated. */
15983 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
15988 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
15990 size = (GET_MODE_SIZE (mode) + 4) / 8;
15992 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
15993 gcc_assert (size >= 2 && size <= 4);
15995 /* Optimize constant pool reference to immediates. This is used by fp
15996 moves, that force all constants to memory to allow combining. */
15997 if (MEM_P (operand) && MEM_READONLY_P (operand))
15999 rtx tmp = maybe_get_pool_constant (operand);
16004 if (MEM_P (operand) && !offsettable_memref_p (operand))
16006 /* The only non-offsetable memories we handle are pushes. */
16007 int ok = push_operand (operand, VOIDmode);
16011 operand = copy_rtx (operand);
16012 PUT_MODE (operand, Pmode);
16013 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16017 if (GET_CODE (operand) == CONST_VECTOR)
16019 enum machine_mode imode = int_mode_for_mode (mode);
16020 /* Caution: if we looked through a constant pool memory above,
16021 the operand may actually have a different mode now. That's
16022 ok, since we want to pun this all the way back to an integer. */
16023 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16024 gcc_assert (operand != NULL);
16030 if (mode == DImode)
16031 split_di (&operand, 1, &parts[0], &parts[1]);
16036 if (REG_P (operand))
16038 gcc_assert (reload_completed);
16039 for (i = 0; i < size; i++)
16040 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16042 else if (offsettable_memref_p (operand))
16044 operand = adjust_address (operand, SImode, 0);
16045 parts[0] = operand;
16046 for (i = 1; i < size; i++)
16047 parts[i] = adjust_address (operand, SImode, 4 * i);
16049 else if (GET_CODE (operand) == CONST_DOUBLE)
16054 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16058 real_to_target (l, &r, mode);
16059 parts[3] = gen_int_mode (l[3], SImode);
16060 parts[2] = gen_int_mode (l[2], SImode);
16063 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16064 parts[2] = gen_int_mode (l[2], SImode);
16067 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16070 gcc_unreachable ();
16072 parts[1] = gen_int_mode (l[1], SImode);
16073 parts[0] = gen_int_mode (l[0], SImode);
16076 gcc_unreachable ();
16081 if (mode == TImode)
16082 split_ti (&operand, 1, &parts[0], &parts[1]);
16083 if (mode == XFmode || mode == TFmode)
16085 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16086 if (REG_P (operand))
16088 gcc_assert (reload_completed);
16089 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16090 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16092 else if (offsettable_memref_p (operand))
16094 operand = adjust_address (operand, DImode, 0);
16095 parts[0] = operand;
16096 parts[1] = adjust_address (operand, upper_mode, 8);
16098 else if (GET_CODE (operand) == CONST_DOUBLE)
16103 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16104 real_to_target (l, &r, mode);
16106 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16107 if (HOST_BITS_PER_WIDE_INT >= 64)
16110 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16111 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16114 parts[0] = immed_double_const (l[0], l[1], DImode);
16116 if (upper_mode == SImode)
16117 parts[1] = gen_int_mode (l[2], SImode);
16118 else if (HOST_BITS_PER_WIDE_INT >= 64)
16121 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16122 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16125 parts[1] = immed_double_const (l[2], l[3], DImode);
16128 gcc_unreachable ();
16135 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16136 Return false when normal moves are needed; true when all required
16137 insns have been emitted. Operands 2-4 contain the input values
16138 int the correct order; operands 5-7 contain the output values. */
16141 ix86_split_long_move (rtx operands[])
16146 int collisions = 0;
16147 enum machine_mode mode = GET_MODE (operands[0]);
16148 bool collisionparts[4];
16150 /* The DFmode expanders may ask us to move double.
16151 For 64bit target this is single move. By hiding the fact
16152 here we simplify i386.md splitters. */
16153 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16155 /* Optimize constant pool reference to immediates. This is used by
16156 fp moves, that force all constants to memory to allow combining. */
16158 if (MEM_P (operands[1])
16159 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16160 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16161 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16162 if (push_operand (operands[0], VOIDmode))
16164 operands[0] = copy_rtx (operands[0]);
16165 PUT_MODE (operands[0], Pmode);
16168 operands[0] = gen_lowpart (DImode, operands[0]);
16169 operands[1] = gen_lowpart (DImode, operands[1]);
16170 emit_move_insn (operands[0], operands[1]);
16174 /* The only non-offsettable memory we handle is push. */
16175 if (push_operand (operands[0], VOIDmode))
16178 gcc_assert (!MEM_P (operands[0])
16179 || offsettable_memref_p (operands[0]));
16181 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16182 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16184 /* When emitting push, take care for source operands on the stack. */
16185 if (push && MEM_P (operands[1])
16186 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16187 for (i = 0; i < nparts - 1; i++)
16188 part[1][i] = change_address (part[1][i],
16189 GET_MODE (part[1][i]),
16190 XEXP (part[1][i + 1], 0));
16192 /* We need to do copy in the right order in case an address register
16193 of the source overlaps the destination. */
16194 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16198 for (i = 0; i < nparts; i++)
16201 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16202 if (collisionparts[i])
16206 /* Collision in the middle part can be handled by reordering. */
16207 if (collisions == 1 && nparts == 3 && collisionparts [1])
16209 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16210 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16212 else if (collisions == 1
16214 && (collisionparts [1] || collisionparts [2]))
16216 if (collisionparts [1])
16218 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16219 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16223 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16224 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16228 /* If there are more collisions, we can't handle it by reordering.
16229 Do an lea to the last part and use only one colliding move. */
16230 else if (collisions > 1)
16236 base = part[0][nparts - 1];
16238 /* Handle the case when the last part isn't valid for lea.
16239 Happens in 64-bit mode storing the 12-byte XFmode. */
16240 if (GET_MODE (base) != Pmode)
16241 base = gen_rtx_REG (Pmode, REGNO (base));
16243 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16244 part[1][0] = replace_equiv_address (part[1][0], base);
16245 for (i = 1; i < nparts; i++)
16247 tmp = plus_constant (base, UNITS_PER_WORD * i);
16248 part[1][i] = replace_equiv_address (part[1][i], tmp);
16259 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16260 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, GEN_INT (-4)));
16261 emit_move_insn (part[0][2], part[1][2]);
16263 else if (nparts == 4)
16265 emit_move_insn (part[0][3], part[1][3]);
16266 emit_move_insn (part[0][2], part[1][2]);
16271 /* In 64bit mode we don't have 32bit push available. In case this is
16272 register, it is OK - we will just use larger counterpart. We also
16273 retype memory - these comes from attempt to avoid REX prefix on
16274 moving of second half of TFmode value. */
16275 if (GET_MODE (part[1][1]) == SImode)
16277 switch (GET_CODE (part[1][1]))
16280 part[1][1] = adjust_address (part[1][1], DImode, 0);
16284 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16288 gcc_unreachable ();
16291 if (GET_MODE (part[1][0]) == SImode)
16292 part[1][0] = part[1][1];
16295 emit_move_insn (part[0][1], part[1][1]);
16296 emit_move_insn (part[0][0], part[1][0]);
16300 /* Choose correct order to not overwrite the source before it is copied. */
16301 if ((REG_P (part[0][0])
16302 && REG_P (part[1][1])
16303 && (REGNO (part[0][0]) == REGNO (part[1][1])
16305 && REGNO (part[0][0]) == REGNO (part[1][2]))
16307 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16309 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16311 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16313 operands[2 + i] = part[0][j];
16314 operands[6 + i] = part[1][j];
16319 for (i = 0; i < nparts; i++)
16321 operands[2 + i] = part[0][i];
16322 operands[6 + i] = part[1][i];
16326 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16327 if (optimize_insn_for_size_p ())
16329 for (j = 0; j < nparts - 1; j++)
16330 if (CONST_INT_P (operands[6 + j])
16331 && operands[6 + j] != const0_rtx
16332 && REG_P (operands[2 + j]))
16333 for (i = j; i < nparts - 1; i++)
16334 if (CONST_INT_P (operands[7 + i])
16335 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16336 operands[7 + i] = operands[2 + j];
16339 for (i = 0; i < nparts; i++)
16340 emit_move_insn (operands[2 + i], operands[6 + i]);
16345 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16346 left shift by a constant, either using a single shift or
16347 a sequence of add instructions. */
16350 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16354 emit_insn ((mode == DImode
16356 : gen_adddi3) (operand, operand, operand));
16358 else if (!optimize_insn_for_size_p ()
16359 && count * ix86_cost->add <= ix86_cost->shift_const)
16362 for (i=0; i<count; i++)
16364 emit_insn ((mode == DImode
16366 : gen_adddi3) (operand, operand, operand));
16370 emit_insn ((mode == DImode
16372 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16376 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16378 rtx low[2], high[2];
16380 const int single_width = mode == DImode ? 32 : 64;
16382 if (CONST_INT_P (operands[2]))
16384 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16385 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16387 if (count >= single_width)
16389 emit_move_insn (high[0], low[1]);
16390 emit_move_insn (low[0], const0_rtx);
16392 if (count > single_width)
16393 ix86_expand_ashl_const (high[0], count - single_width, mode);
16397 if (!rtx_equal_p (operands[0], operands[1]))
16398 emit_move_insn (operands[0], operands[1]);
16399 emit_insn ((mode == DImode
16401 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16402 ix86_expand_ashl_const (low[0], count, mode);
16407 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16409 if (operands[1] == const1_rtx)
16411 /* Assuming we've chosen a QImode capable registers, then 1 << N
16412 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16413 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16415 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16417 ix86_expand_clear (low[0]);
16418 ix86_expand_clear (high[0]);
16419 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16421 d = gen_lowpart (QImode, low[0]);
16422 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16423 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16424 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16426 d = gen_lowpart (QImode, high[0]);
16427 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16428 s = gen_rtx_NE (QImode, flags, const0_rtx);
16429 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16432 /* Otherwise, we can get the same results by manually performing
16433 a bit extract operation on bit 5/6, and then performing the two
16434 shifts. The two methods of getting 0/1 into low/high are exactly
16435 the same size. Avoiding the shift in the bit extract case helps
16436 pentium4 a bit; no one else seems to care much either way. */
16441 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16442 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16444 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16445 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16447 emit_insn ((mode == DImode
16449 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
16450 emit_insn ((mode == DImode
16452 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
16453 emit_move_insn (low[0], high[0]);
16454 emit_insn ((mode == DImode
16456 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
16459 emit_insn ((mode == DImode
16461 : gen_ashldi3) (low[0], low[0], operands[2]));
16462 emit_insn ((mode == DImode
16464 : gen_ashldi3) (high[0], high[0], operands[2]));
16468 if (operands[1] == constm1_rtx)
16470 /* For -1 << N, we can avoid the shld instruction, because we
16471 know that we're shifting 0...31/63 ones into a -1. */
16472 emit_move_insn (low[0], constm1_rtx);
16473 if (optimize_insn_for_size_p ())
16474 emit_move_insn (high[0], low[0]);
16476 emit_move_insn (high[0], constm1_rtx);
16480 if (!rtx_equal_p (operands[0], operands[1]))
16481 emit_move_insn (operands[0], operands[1]);
16483 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16484 emit_insn ((mode == DImode
16486 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16489 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16491 if (TARGET_CMOVE && scratch)
16493 ix86_expand_clear (scratch);
16494 emit_insn ((mode == DImode
16495 ? gen_x86_shift_adj_1
16496 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16500 emit_insn ((mode == DImode
16501 ? gen_x86_shift_adj_2
16502 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16506 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16508 rtx low[2], high[2];
16510 const int single_width = mode == DImode ? 32 : 64;
16512 if (CONST_INT_P (operands[2]))
16514 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16515 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16517 if (count == single_width * 2 - 1)
16519 emit_move_insn (high[0], high[1]);
16520 emit_insn ((mode == DImode
16522 : gen_ashrdi3) (high[0], high[0],
16523 GEN_INT (single_width - 1)));
16524 emit_move_insn (low[0], high[0]);
16527 else if (count >= single_width)
16529 emit_move_insn (low[0], high[1]);
16530 emit_move_insn (high[0], low[0]);
16531 emit_insn ((mode == DImode
16533 : gen_ashrdi3) (high[0], high[0],
16534 GEN_INT (single_width - 1)));
16535 if (count > single_width)
16536 emit_insn ((mode == DImode
16538 : gen_ashrdi3) (low[0], low[0],
16539 GEN_INT (count - single_width)));
16543 if (!rtx_equal_p (operands[0], operands[1]))
16544 emit_move_insn (operands[0], operands[1]);
16545 emit_insn ((mode == DImode
16547 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16548 emit_insn ((mode == DImode
16550 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16555 if (!rtx_equal_p (operands[0], operands[1]))
16556 emit_move_insn (operands[0], operands[1]);
16558 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16560 emit_insn ((mode == DImode
16562 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16563 emit_insn ((mode == DImode
16565 : gen_ashrdi3) (high[0], high[0], operands[2]));
16567 if (TARGET_CMOVE && scratch)
16569 emit_move_insn (scratch, high[0]);
16570 emit_insn ((mode == DImode
16572 : gen_ashrdi3) (scratch, scratch,
16573 GEN_INT (single_width - 1)));
16574 emit_insn ((mode == DImode
16575 ? gen_x86_shift_adj_1
16576 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16580 emit_insn ((mode == DImode
16581 ? gen_x86_shift_adj_3
16582 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16587 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16589 rtx low[2], high[2];
16591 const int single_width = mode == DImode ? 32 : 64;
16593 if (CONST_INT_P (operands[2]))
16595 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16596 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16598 if (count >= single_width)
16600 emit_move_insn (low[0], high[1]);
16601 ix86_expand_clear (high[0]);
16603 if (count > single_width)
16604 emit_insn ((mode == DImode
16606 : gen_lshrdi3) (low[0], low[0],
16607 GEN_INT (count - single_width)));
16611 if (!rtx_equal_p (operands[0], operands[1]))
16612 emit_move_insn (operands[0], operands[1]);
16613 emit_insn ((mode == DImode
16615 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16616 emit_insn ((mode == DImode
16618 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16623 if (!rtx_equal_p (operands[0], operands[1]))
16624 emit_move_insn (operands[0], operands[1]);
16626 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16628 emit_insn ((mode == DImode
16630 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16631 emit_insn ((mode == DImode
16633 : gen_lshrdi3) (high[0], high[0], operands[2]));
16635 /* Heh. By reversing the arguments, we can reuse this pattern. */
16636 if (TARGET_CMOVE && scratch)
16638 ix86_expand_clear (scratch);
16639 emit_insn ((mode == DImode
16640 ? gen_x86_shift_adj_1
16641 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16645 emit_insn ((mode == DImode
16646 ? gen_x86_shift_adj_2
16647 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16651 /* Predict just emitted jump instruction to be taken with probability PROB. */
16653 predict_jump (int prob)
16655 rtx insn = get_last_insn ();
16656 gcc_assert (JUMP_P (insn));
16658 = gen_rtx_EXPR_LIST (REG_BR_PROB,
16663 /* Helper function for the string operations below. Dest VARIABLE whether
16664 it is aligned to VALUE bytes. If true, jump to the label. */
16666 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16668 rtx label = gen_label_rtx ();
16669 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16670 if (GET_MODE (variable) == DImode)
16671 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16673 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16674 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16677 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16679 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16683 /* Adjust COUNTER by the VALUE. */
16685 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16687 if (GET_MODE (countreg) == DImode)
16688 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16690 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16693 /* Zero extend possibly SImode EXP to Pmode register. */
16695 ix86_zero_extend_to_Pmode (rtx exp)
16698 if (GET_MODE (exp) == VOIDmode)
16699 return force_reg (Pmode, exp);
16700 if (GET_MODE (exp) == Pmode)
16701 return copy_to_mode_reg (Pmode, exp);
16702 r = gen_reg_rtx (Pmode);
16703 emit_insn (gen_zero_extendsidi2 (r, exp));
16707 /* Divide COUNTREG by SCALE. */
16709 scale_counter (rtx countreg, int scale)
16712 rtx piece_size_mask;
16716 if (CONST_INT_P (countreg))
16717 return GEN_INT (INTVAL (countreg) / scale);
16718 gcc_assert (REG_P (countreg));
16720 piece_size_mask = GEN_INT (scale - 1);
16721 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16722 GEN_INT (exact_log2 (scale)),
16723 NULL, 1, OPTAB_DIRECT);
16727 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16728 DImode for constant loop counts. */
16730 static enum machine_mode
16731 counter_mode (rtx count_exp)
16733 if (GET_MODE (count_exp) != VOIDmode)
16734 return GET_MODE (count_exp);
16735 if (GET_CODE (count_exp) != CONST_INT)
16737 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
16742 /* When SRCPTR is non-NULL, output simple loop to move memory
16743 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16744 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16745 equivalent loop to set memory by VALUE (supposed to be in MODE).
16747 The size is rounded down to whole number of chunk size moved at once.
16748 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16752 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
16753 rtx destptr, rtx srcptr, rtx value,
16754 rtx count, enum machine_mode mode, int unroll,
16757 rtx out_label, top_label, iter, tmp;
16758 enum machine_mode iter_mode = counter_mode (count);
16759 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
16760 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
16766 top_label = gen_label_rtx ();
16767 out_label = gen_label_rtx ();
16768 iter = gen_reg_rtx (iter_mode);
16770 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
16771 NULL, 1, OPTAB_DIRECT);
16772 /* Those two should combine. */
16773 if (piece_size == const1_rtx)
16775 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
16777 predict_jump (REG_BR_PROB_BASE * 10 / 100);
16779 emit_move_insn (iter, const0_rtx);
16781 emit_label (top_label);
16783 tmp = convert_modes (Pmode, iter_mode, iter, true);
16784 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
16785 destmem = change_address (destmem, mode, x_addr);
16789 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
16790 srcmem = change_address (srcmem, mode, y_addr);
16792 /* When unrolling for chips that reorder memory reads and writes,
16793 we can save registers by using single temporary.
16794 Also using 4 temporaries is overkill in 32bit mode. */
16795 if (!TARGET_64BIT && 0)
16797 for (i = 0; i < unroll; i++)
16802 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16804 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16806 emit_move_insn (destmem, srcmem);
16812 gcc_assert (unroll <= 4);
16813 for (i = 0; i < unroll; i++)
16815 tmpreg[i] = gen_reg_rtx (mode);
16819 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16821 emit_move_insn (tmpreg[i], srcmem);
16823 for (i = 0; i < unroll; i++)
16828 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16830 emit_move_insn (destmem, tmpreg[i]);
16835 for (i = 0; i < unroll; i++)
16839 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16840 emit_move_insn (destmem, value);
16843 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
16844 true, OPTAB_LIB_WIDEN);
16846 emit_move_insn (iter, tmp);
16848 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
16850 if (expected_size != -1)
16852 expected_size /= GET_MODE_SIZE (mode) * unroll;
16853 if (expected_size == 0)
16855 else if (expected_size > REG_BR_PROB_BASE)
16856 predict_jump (REG_BR_PROB_BASE - 1);
16858 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
16861 predict_jump (REG_BR_PROB_BASE * 80 / 100);
16862 iter = ix86_zero_extend_to_Pmode (iter);
16863 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
16864 true, OPTAB_LIB_WIDEN);
16865 if (tmp != destptr)
16866 emit_move_insn (destptr, tmp);
16869 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
16870 true, OPTAB_LIB_WIDEN);
16872 emit_move_insn (srcptr, tmp);
16874 emit_label (out_label);
16877 /* Output "rep; mov" instruction.
16878 Arguments have same meaning as for previous function */
16880 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
16881 rtx destptr, rtx srcptr,
16883 enum machine_mode mode)
16889 /* If the size is known, it is shorter to use rep movs. */
16890 if (mode == QImode && CONST_INT_P (count)
16891 && !(INTVAL (count) & 3))
16894 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16895 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16896 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
16897 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
16898 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16899 if (mode != QImode)
16901 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16902 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16903 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16904 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
16905 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16906 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
16910 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16911 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
16913 if (CONST_INT_P (count))
16915 count = GEN_INT (INTVAL (count)
16916 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16917 destmem = shallow_copy_rtx (destmem);
16918 srcmem = shallow_copy_rtx (srcmem);
16919 set_mem_size (destmem, count);
16920 set_mem_size (srcmem, count);
16924 if (MEM_SIZE (destmem))
16925 set_mem_size (destmem, NULL_RTX);
16926 if (MEM_SIZE (srcmem))
16927 set_mem_size (srcmem, NULL_RTX);
16929 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
16933 /* Output "rep; stos" instruction.
16934 Arguments have same meaning as for previous function */
16936 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
16937 rtx count, enum machine_mode mode,
16943 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
16944 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
16945 value = force_reg (mode, gen_lowpart (mode, value));
16946 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
16947 if (mode != QImode)
16949 destexp = gen_rtx_ASHIFT (Pmode, countreg,
16950 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
16951 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
16954 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
16955 if (orig_value == const0_rtx && CONST_INT_P (count))
16957 count = GEN_INT (INTVAL (count)
16958 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
16959 destmem = shallow_copy_rtx (destmem);
16960 set_mem_size (destmem, count);
16962 else if (MEM_SIZE (destmem))
16963 set_mem_size (destmem, NULL_RTX);
16964 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
16968 emit_strmov (rtx destmem, rtx srcmem,
16969 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
16971 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
16972 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
16973 emit_insn (gen_strmov (destptr, dest, srcptr, src));
16976 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
16978 expand_movmem_epilogue (rtx destmem, rtx srcmem,
16979 rtx destptr, rtx srcptr, rtx count, int max_size)
16982 if (CONST_INT_P (count))
16984 HOST_WIDE_INT countval = INTVAL (count);
16987 if ((countval & 0x10) && max_size > 16)
16991 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
16992 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
16995 gcc_unreachable ();
16998 if ((countval & 0x08) && max_size > 8)
17001 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17004 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17005 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17009 if ((countval & 0x04) && max_size > 4)
17011 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17014 if ((countval & 0x02) && max_size > 2)
17016 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17019 if ((countval & 0x01) && max_size > 1)
17021 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17028 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17029 count, 1, OPTAB_DIRECT);
17030 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17031 count, QImode, 1, 4);
17035 /* When there are stringops, we can cheaply increase dest and src pointers.
17036 Otherwise we save code size by maintaining offset (zero is readily
17037 available from preceding rep operation) and using x86 addressing modes.
17039 if (TARGET_SINGLE_STRINGOP)
17043 rtx label = ix86_expand_aligntest (count, 4, true);
17044 src = change_address (srcmem, SImode, srcptr);
17045 dest = change_address (destmem, SImode, destptr);
17046 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17047 emit_label (label);
17048 LABEL_NUSES (label) = 1;
17052 rtx label = ix86_expand_aligntest (count, 2, true);
17053 src = change_address (srcmem, HImode, srcptr);
17054 dest = change_address (destmem, HImode, destptr);
17055 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17056 emit_label (label);
17057 LABEL_NUSES (label) = 1;
17061 rtx label = ix86_expand_aligntest (count, 1, true);
17062 src = change_address (srcmem, QImode, srcptr);
17063 dest = change_address (destmem, QImode, destptr);
17064 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17065 emit_label (label);
17066 LABEL_NUSES (label) = 1;
17071 rtx offset = force_reg (Pmode, const0_rtx);
17076 rtx label = ix86_expand_aligntest (count, 4, true);
17077 src = change_address (srcmem, SImode, srcptr);
17078 dest = change_address (destmem, SImode, destptr);
17079 emit_move_insn (dest, src);
17080 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17081 true, OPTAB_LIB_WIDEN);
17083 emit_move_insn (offset, tmp);
17084 emit_label (label);
17085 LABEL_NUSES (label) = 1;
17089 rtx label = ix86_expand_aligntest (count, 2, true);
17090 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17091 src = change_address (srcmem, HImode, tmp);
17092 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17093 dest = change_address (destmem, HImode, tmp);
17094 emit_move_insn (dest, src);
17095 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17096 true, OPTAB_LIB_WIDEN);
17098 emit_move_insn (offset, tmp);
17099 emit_label (label);
17100 LABEL_NUSES (label) = 1;
17104 rtx label = ix86_expand_aligntest (count, 1, true);
17105 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17106 src = change_address (srcmem, QImode, tmp);
17107 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17108 dest = change_address (destmem, QImode, tmp);
17109 emit_move_insn (dest, src);
17110 emit_label (label);
17111 LABEL_NUSES (label) = 1;
17116 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17118 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17119 rtx count, int max_size)
17122 expand_simple_binop (counter_mode (count), AND, count,
17123 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17124 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17125 gen_lowpart (QImode, value), count, QImode,
17129 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17131 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17135 if (CONST_INT_P (count))
17137 HOST_WIDE_INT countval = INTVAL (count);
17140 if ((countval & 0x10) && max_size > 16)
17144 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17145 emit_insn (gen_strset (destptr, dest, value));
17146 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17147 emit_insn (gen_strset (destptr, dest, value));
17150 gcc_unreachable ();
17153 if ((countval & 0x08) && max_size > 8)
17157 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17158 emit_insn (gen_strset (destptr, dest, value));
17162 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17163 emit_insn (gen_strset (destptr, dest, value));
17164 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17165 emit_insn (gen_strset (destptr, dest, value));
17169 if ((countval & 0x04) && max_size > 4)
17171 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17172 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17175 if ((countval & 0x02) && max_size > 2)
17177 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17178 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17181 if ((countval & 0x01) && max_size > 1)
17183 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17184 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17191 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17196 rtx label = ix86_expand_aligntest (count, 16, true);
17199 dest = change_address (destmem, DImode, destptr);
17200 emit_insn (gen_strset (destptr, dest, value));
17201 emit_insn (gen_strset (destptr, dest, value));
17205 dest = change_address (destmem, SImode, destptr);
17206 emit_insn (gen_strset (destptr, dest, value));
17207 emit_insn (gen_strset (destptr, dest, value));
17208 emit_insn (gen_strset (destptr, dest, value));
17209 emit_insn (gen_strset (destptr, dest, value));
17211 emit_label (label);
17212 LABEL_NUSES (label) = 1;
17216 rtx label = ix86_expand_aligntest (count, 8, true);
17219 dest = change_address (destmem, DImode, destptr);
17220 emit_insn (gen_strset (destptr, dest, value));
17224 dest = change_address (destmem, SImode, destptr);
17225 emit_insn (gen_strset (destptr, dest, value));
17226 emit_insn (gen_strset (destptr, dest, value));
17228 emit_label (label);
17229 LABEL_NUSES (label) = 1;
17233 rtx label = ix86_expand_aligntest (count, 4, true);
17234 dest = change_address (destmem, SImode, destptr);
17235 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17236 emit_label (label);
17237 LABEL_NUSES (label) = 1;
17241 rtx label = ix86_expand_aligntest (count, 2, true);
17242 dest = change_address (destmem, HImode, destptr);
17243 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17244 emit_label (label);
17245 LABEL_NUSES (label) = 1;
17249 rtx label = ix86_expand_aligntest (count, 1, true);
17250 dest = change_address (destmem, QImode, destptr);
17251 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17252 emit_label (label);
17253 LABEL_NUSES (label) = 1;
17257 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17258 DESIRED_ALIGNMENT. */
17260 expand_movmem_prologue (rtx destmem, rtx srcmem,
17261 rtx destptr, rtx srcptr, rtx count,
17262 int align, int desired_alignment)
17264 if (align <= 1 && desired_alignment > 1)
17266 rtx label = ix86_expand_aligntest (destptr, 1, false);
17267 srcmem = change_address (srcmem, QImode, srcptr);
17268 destmem = change_address (destmem, QImode, destptr);
17269 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17270 ix86_adjust_counter (count, 1);
17271 emit_label (label);
17272 LABEL_NUSES (label) = 1;
17274 if (align <= 2 && desired_alignment > 2)
17276 rtx label = ix86_expand_aligntest (destptr, 2, false);
17277 srcmem = change_address (srcmem, HImode, srcptr);
17278 destmem = change_address (destmem, HImode, destptr);
17279 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17280 ix86_adjust_counter (count, 2);
17281 emit_label (label);
17282 LABEL_NUSES (label) = 1;
17284 if (align <= 4 && desired_alignment > 4)
17286 rtx label = ix86_expand_aligntest (destptr, 4, false);
17287 srcmem = change_address (srcmem, SImode, srcptr);
17288 destmem = change_address (destmem, SImode, destptr);
17289 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17290 ix86_adjust_counter (count, 4);
17291 emit_label (label);
17292 LABEL_NUSES (label) = 1;
17294 gcc_assert (desired_alignment <= 8);
17297 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17298 ALIGN_BYTES is how many bytes need to be copied. */
17300 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17301 int desired_align, int align_bytes)
17304 rtx src_size, dst_size;
17306 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17307 if (src_align_bytes >= 0)
17308 src_align_bytes = desired_align - src_align_bytes;
17309 src_size = MEM_SIZE (src);
17310 dst_size = MEM_SIZE (dst);
17311 if (align_bytes & 1)
17313 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17314 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17316 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17318 if (align_bytes & 2)
17320 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17321 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17322 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17323 set_mem_align (dst, 2 * BITS_PER_UNIT);
17324 if (src_align_bytes >= 0
17325 && (src_align_bytes & 1) == (align_bytes & 1)
17326 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17327 set_mem_align (src, 2 * BITS_PER_UNIT);
17329 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17331 if (align_bytes & 4)
17333 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17334 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17335 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17336 set_mem_align (dst, 4 * BITS_PER_UNIT);
17337 if (src_align_bytes >= 0)
17339 unsigned int src_align = 0;
17340 if ((src_align_bytes & 3) == (align_bytes & 3))
17342 else if ((src_align_bytes & 1) == (align_bytes & 1))
17344 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17345 set_mem_align (src, src_align * BITS_PER_UNIT);
17348 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17350 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17351 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17352 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17353 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17354 if (src_align_bytes >= 0)
17356 unsigned int src_align = 0;
17357 if ((src_align_bytes & 7) == (align_bytes & 7))
17359 else if ((src_align_bytes & 3) == (align_bytes & 3))
17361 else if ((src_align_bytes & 1) == (align_bytes & 1))
17363 if (src_align > (unsigned int) desired_align)
17364 src_align = desired_align;
17365 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17366 set_mem_align (src, src_align * BITS_PER_UNIT);
17369 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17371 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17376 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17377 DESIRED_ALIGNMENT. */
17379 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17380 int align, int desired_alignment)
17382 if (align <= 1 && desired_alignment > 1)
17384 rtx label = ix86_expand_aligntest (destptr, 1, false);
17385 destmem = change_address (destmem, QImode, destptr);
17386 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17387 ix86_adjust_counter (count, 1);
17388 emit_label (label);
17389 LABEL_NUSES (label) = 1;
17391 if (align <= 2 && desired_alignment > 2)
17393 rtx label = ix86_expand_aligntest (destptr, 2, false);
17394 destmem = change_address (destmem, HImode, destptr);
17395 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17396 ix86_adjust_counter (count, 2);
17397 emit_label (label);
17398 LABEL_NUSES (label) = 1;
17400 if (align <= 4 && desired_alignment > 4)
17402 rtx label = ix86_expand_aligntest (destptr, 4, false);
17403 destmem = change_address (destmem, SImode, destptr);
17404 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17405 ix86_adjust_counter (count, 4);
17406 emit_label (label);
17407 LABEL_NUSES (label) = 1;
17409 gcc_assert (desired_alignment <= 8);
17412 /* Set enough from DST to align DST known to by aligned by ALIGN to
17413 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17415 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17416 int desired_align, int align_bytes)
17419 rtx dst_size = MEM_SIZE (dst);
17420 if (align_bytes & 1)
17422 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17424 emit_insn (gen_strset (destreg, dst,
17425 gen_lowpart (QImode, value)));
17427 if (align_bytes & 2)
17429 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17430 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17431 set_mem_align (dst, 2 * BITS_PER_UNIT);
17433 emit_insn (gen_strset (destreg, dst,
17434 gen_lowpart (HImode, value)));
17436 if (align_bytes & 4)
17438 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17439 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17440 set_mem_align (dst, 4 * BITS_PER_UNIT);
17442 emit_insn (gen_strset (destreg, dst,
17443 gen_lowpart (SImode, value)));
17445 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17446 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17447 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17449 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17453 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17454 static enum stringop_alg
17455 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17456 int *dynamic_check)
17458 const struct stringop_algs * algs;
17459 bool optimize_for_speed;
17460 /* Algorithms using the rep prefix want at least edi and ecx;
17461 additionally, memset wants eax and memcpy wants esi. Don't
17462 consider such algorithms if the user has appropriated those
17463 registers for their own purposes. */
17464 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17466 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17468 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17469 || (alg != rep_prefix_1_byte \
17470 && alg != rep_prefix_4_byte \
17471 && alg != rep_prefix_8_byte))
17472 const struct processor_costs *cost;
17474 /* Even if the string operation call is cold, we still might spend a lot
17475 of time processing large blocks. */
17476 if (optimize_function_for_size_p (cfun)
17477 || (optimize_insn_for_size_p ()
17478 && expected_size != -1 && expected_size < 256))
17479 optimize_for_speed = false;
17481 optimize_for_speed = true;
17483 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17485 *dynamic_check = -1;
17487 algs = &cost->memset[TARGET_64BIT != 0];
17489 algs = &cost->memcpy[TARGET_64BIT != 0];
17490 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17491 return stringop_alg;
17492 /* rep; movq or rep; movl is the smallest variant. */
17493 else if (!optimize_for_speed)
17495 if (!count || (count & 3))
17496 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17498 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17500 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17502 else if (expected_size != -1 && expected_size < 4)
17503 return loop_1_byte;
17504 else if (expected_size != -1)
17507 enum stringop_alg alg = libcall;
17508 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17510 /* We get here if the algorithms that were not libcall-based
17511 were rep-prefix based and we are unable to use rep prefixes
17512 based on global register usage. Break out of the loop and
17513 use the heuristic below. */
17514 if (algs->size[i].max == 0)
17516 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17518 enum stringop_alg candidate = algs->size[i].alg;
17520 if (candidate != libcall && ALG_USABLE_P (candidate))
17522 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17523 last non-libcall inline algorithm. */
17524 if (TARGET_INLINE_ALL_STRINGOPS)
17526 /* When the current size is best to be copied by a libcall,
17527 but we are still forced to inline, run the heuristic below
17528 that will pick code for medium sized blocks. */
17529 if (alg != libcall)
17533 else if (ALG_USABLE_P (candidate))
17537 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17539 /* When asked to inline the call anyway, try to pick meaningful choice.
17540 We look for maximal size of block that is faster to copy by hand and
17541 take blocks of at most of that size guessing that average size will
17542 be roughly half of the block.
17544 If this turns out to be bad, we might simply specify the preferred
17545 choice in ix86_costs. */
17546 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17547 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17550 enum stringop_alg alg;
17552 bool any_alg_usable_p = true;
17554 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17556 enum stringop_alg candidate = algs->size[i].alg;
17557 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17559 if (candidate != libcall && candidate
17560 && ALG_USABLE_P (candidate))
17561 max = algs->size[i].max;
17563 /* If there aren't any usable algorithms, then recursing on
17564 smaller sizes isn't going to find anything. Just return the
17565 simple byte-at-a-time copy loop. */
17566 if (!any_alg_usable_p)
17568 /* Pick something reasonable. */
17569 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17570 *dynamic_check = 128;
17571 return loop_1_byte;
17575 alg = decide_alg (count, max / 2, memset, dynamic_check);
17576 gcc_assert (*dynamic_check == -1);
17577 gcc_assert (alg != libcall);
17578 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17579 *dynamic_check = max;
17582 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17583 #undef ALG_USABLE_P
17586 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17587 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17589 decide_alignment (int align,
17590 enum stringop_alg alg,
17593 int desired_align = 0;
17597 gcc_unreachable ();
17599 case unrolled_loop:
17600 desired_align = GET_MODE_SIZE (Pmode);
17602 case rep_prefix_8_byte:
17605 case rep_prefix_4_byte:
17606 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17607 copying whole cacheline at once. */
17608 if (TARGET_PENTIUMPRO)
17613 case rep_prefix_1_byte:
17614 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17615 copying whole cacheline at once. */
17616 if (TARGET_PENTIUMPRO)
17630 if (desired_align < align)
17631 desired_align = align;
17632 if (expected_size != -1 && expected_size < 4)
17633 desired_align = align;
17634 return desired_align;
17637 /* Return the smallest power of 2 greater than VAL. */
17639 smallest_pow2_greater_than (int val)
17647 /* Expand string move (memcpy) operation. Use i386 string operations when
17648 profitable. expand_setmem contains similar code. The code depends upon
17649 architecture, block size and alignment, but always has the same
17652 1) Prologue guard: Conditional that jumps up to epilogues for small
17653 blocks that can be handled by epilogue alone. This is faster but
17654 also needed for correctness, since prologue assume the block is larger
17655 than the desired alignment.
17657 Optional dynamic check for size and libcall for large
17658 blocks is emitted here too, with -minline-stringops-dynamically.
17660 2) Prologue: copy first few bytes in order to get destination aligned
17661 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17662 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17663 We emit either a jump tree on power of two sized blocks, or a byte loop.
17665 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17666 with specified algorithm.
17668 4) Epilogue: code copying tail of the block that is too small to be
17669 handled by main body (or up to size guarded by prologue guard). */
17672 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17673 rtx expected_align_exp, rtx expected_size_exp)
17679 rtx jump_around_label = NULL;
17680 HOST_WIDE_INT align = 1;
17681 unsigned HOST_WIDE_INT count = 0;
17682 HOST_WIDE_INT expected_size = -1;
17683 int size_needed = 0, epilogue_size_needed;
17684 int desired_align = 0, align_bytes = 0;
17685 enum stringop_alg alg;
17687 bool need_zero_guard = false;
17689 if (CONST_INT_P (align_exp))
17690 align = INTVAL (align_exp);
17691 /* i386 can do misaligned access on reasonably increased cost. */
17692 if (CONST_INT_P (expected_align_exp)
17693 && INTVAL (expected_align_exp) > align)
17694 align = INTVAL (expected_align_exp);
17695 /* ALIGN is the minimum of destination and source alignment, but we care here
17696 just about destination alignment. */
17697 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17698 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17700 if (CONST_INT_P (count_exp))
17701 count = expected_size = INTVAL (count_exp);
17702 if (CONST_INT_P (expected_size_exp) && count == 0)
17703 expected_size = INTVAL (expected_size_exp);
17705 /* Make sure we don't need to care about overflow later on. */
17706 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17709 /* Step 0: Decide on preferred algorithm, desired alignment and
17710 size of chunks to be copied by main loop. */
17712 alg = decide_alg (count, expected_size, false, &dynamic_check);
17713 desired_align = decide_alignment (align, alg, expected_size);
17715 if (!TARGET_ALIGN_STRINGOPS)
17716 align = desired_align;
17718 if (alg == libcall)
17720 gcc_assert (alg != no_stringop);
17722 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
17723 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17724 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
17729 gcc_unreachable ();
17731 need_zero_guard = true;
17732 size_needed = GET_MODE_SIZE (Pmode);
17734 case unrolled_loop:
17735 need_zero_guard = true;
17736 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
17738 case rep_prefix_8_byte:
17741 case rep_prefix_4_byte:
17744 case rep_prefix_1_byte:
17748 need_zero_guard = true;
17753 epilogue_size_needed = size_needed;
17755 /* Step 1: Prologue guard. */
17757 /* Alignment code needs count to be in register. */
17758 if (CONST_INT_P (count_exp) && desired_align > align)
17760 if (INTVAL (count_exp) > desired_align
17761 && INTVAL (count_exp) > size_needed)
17764 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
17765 if (align_bytes <= 0)
17768 align_bytes = desired_align - align_bytes;
17770 if (align_bytes == 0)
17771 count_exp = force_reg (counter_mode (count_exp), count_exp);
17773 gcc_assert (desired_align >= 1 && align >= 1);
17775 /* Ensure that alignment prologue won't copy past end of block. */
17776 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17778 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17779 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17780 Make sure it is power of 2. */
17781 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17785 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
17787 /* If main algorithm works on QImode, no epilogue is needed.
17788 For small sizes just don't align anything. */
17789 if (size_needed == 1)
17790 desired_align = align;
17797 label = gen_label_rtx ();
17798 emit_cmp_and_jump_insns (count_exp,
17799 GEN_INT (epilogue_size_needed),
17800 LTU, 0, counter_mode (count_exp), 1, label);
17801 if (expected_size == -1 || expected_size < epilogue_size_needed)
17802 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17804 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17808 /* Emit code to decide on runtime whether library call or inline should be
17810 if (dynamic_check != -1)
17812 if (CONST_INT_P (count_exp))
17814 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
17816 emit_block_move_via_libcall (dst, src, count_exp, false);
17817 count_exp = const0_rtx;
17823 rtx hot_label = gen_label_rtx ();
17824 jump_around_label = gen_label_rtx ();
17825 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17826 LEU, 0, GET_MODE (count_exp), 1, hot_label);
17827 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17828 emit_block_move_via_libcall (dst, src, count_exp, false);
17829 emit_jump (jump_around_label);
17830 emit_label (hot_label);
17834 /* Step 2: Alignment prologue. */
17836 if (desired_align > align)
17838 if (align_bytes == 0)
17840 /* Except for the first move in epilogue, we no longer know
17841 constant offset in aliasing info. It don't seems to worth
17842 the pain to maintain it for the first move, so throw away
17844 src = change_address (src, BLKmode, srcreg);
17845 dst = change_address (dst, BLKmode, destreg);
17846 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
17851 /* If we know how many bytes need to be stored before dst is
17852 sufficiently aligned, maintain aliasing info accurately. */
17853 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
17854 desired_align, align_bytes);
17855 count_exp = plus_constant (count_exp, -align_bytes);
17856 count -= align_bytes;
17858 if (need_zero_guard
17859 && (count < (unsigned HOST_WIDE_INT) size_needed
17860 || (align_bytes == 0
17861 && count < ((unsigned HOST_WIDE_INT) size_needed
17862 + desired_align - align))))
17864 /* It is possible that we copied enough so the main loop will not
17866 gcc_assert (size_needed > 1);
17867 if (label == NULL_RTX)
17868 label = gen_label_rtx ();
17869 emit_cmp_and_jump_insns (count_exp,
17870 GEN_INT (size_needed),
17871 LTU, 0, counter_mode (count_exp), 1, label);
17872 if (expected_size == -1
17873 || expected_size < (desired_align - align) / 2 + size_needed)
17874 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17876 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17879 if (label && size_needed == 1)
17881 emit_label (label);
17882 LABEL_NUSES (label) = 1;
17884 epilogue_size_needed = 1;
17886 else if (label == NULL_RTX)
17887 epilogue_size_needed = size_needed;
17889 /* Step 3: Main loop. */
17895 gcc_unreachable ();
17897 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17898 count_exp, QImode, 1, expected_size);
17901 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17902 count_exp, Pmode, 1, expected_size);
17904 case unrolled_loop:
17905 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
17906 registers for 4 temporaries anyway. */
17907 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
17908 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
17911 case rep_prefix_8_byte:
17912 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17915 case rep_prefix_4_byte:
17916 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17919 case rep_prefix_1_byte:
17920 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
17924 /* Adjust properly the offset of src and dest memory for aliasing. */
17925 if (CONST_INT_P (count_exp))
17927 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
17928 (count / size_needed) * size_needed);
17929 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
17930 (count / size_needed) * size_needed);
17934 src = change_address (src, BLKmode, srcreg);
17935 dst = change_address (dst, BLKmode, destreg);
17938 /* Step 4: Epilogue to copy the remaining bytes. */
17942 /* When the main loop is done, COUNT_EXP might hold original count,
17943 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
17944 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
17945 bytes. Compensate if needed. */
17947 if (size_needed < epilogue_size_needed)
17950 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
17951 GEN_INT (size_needed - 1), count_exp, 1,
17953 if (tmp != count_exp)
17954 emit_move_insn (count_exp, tmp);
17956 emit_label (label);
17957 LABEL_NUSES (label) = 1;
17960 if (count_exp != const0_rtx && epilogue_size_needed > 1)
17961 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
17962 epilogue_size_needed);
17963 if (jump_around_label)
17964 emit_label (jump_around_label);
17968 /* Helper function for memcpy. For QImode value 0xXY produce
17969 0xXYXYXYXY of wide specified by MODE. This is essentially
17970 a * 0x10101010, but we can do slightly better than
17971 synth_mult by unwinding the sequence by hand on CPUs with
17974 promote_duplicated_reg (enum machine_mode mode, rtx val)
17976 enum machine_mode valmode = GET_MODE (val);
17978 int nops = mode == DImode ? 3 : 2;
17980 gcc_assert (mode == SImode || mode == DImode);
17981 if (val == const0_rtx)
17982 return copy_to_mode_reg (mode, const0_rtx);
17983 if (CONST_INT_P (val))
17985 HOST_WIDE_INT v = INTVAL (val) & 255;
17989 if (mode == DImode)
17990 v |= (v << 16) << 16;
17991 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
17994 if (valmode == VOIDmode)
17996 if (valmode != QImode)
17997 val = gen_lowpart (QImode, val);
17998 if (mode == QImode)
18000 if (!TARGET_PARTIAL_REG_STALL)
18002 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18003 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18004 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18005 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18007 rtx reg = convert_modes (mode, QImode, val, true);
18008 tmp = promote_duplicated_reg (mode, const1_rtx);
18009 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18014 rtx reg = convert_modes (mode, QImode, val, true);
18016 if (!TARGET_PARTIAL_REG_STALL)
18017 if (mode == SImode)
18018 emit_insn (gen_movsi_insv_1 (reg, reg));
18020 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18023 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18024 NULL, 1, OPTAB_DIRECT);
18026 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18028 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18029 NULL, 1, OPTAB_DIRECT);
18030 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18031 if (mode == SImode)
18033 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18034 NULL, 1, OPTAB_DIRECT);
18035 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18040 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18041 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18042 alignment from ALIGN to DESIRED_ALIGN. */
18044 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18049 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18050 promoted_val = promote_duplicated_reg (DImode, val);
18051 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18052 promoted_val = promote_duplicated_reg (SImode, val);
18053 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18054 promoted_val = promote_duplicated_reg (HImode, val);
18056 promoted_val = val;
18058 return promoted_val;
18061 /* Expand string clear operation (bzero). Use i386 string operations when
18062 profitable. See expand_movmem comment for explanation of individual
18063 steps performed. */
18065 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18066 rtx expected_align_exp, rtx expected_size_exp)
18071 rtx jump_around_label = NULL;
18072 HOST_WIDE_INT align = 1;
18073 unsigned HOST_WIDE_INT count = 0;
18074 HOST_WIDE_INT expected_size = -1;
18075 int size_needed = 0, epilogue_size_needed;
18076 int desired_align = 0, align_bytes = 0;
18077 enum stringop_alg alg;
18078 rtx promoted_val = NULL;
18079 bool force_loopy_epilogue = false;
18081 bool need_zero_guard = false;
18083 if (CONST_INT_P (align_exp))
18084 align = INTVAL (align_exp);
18085 /* i386 can do misaligned access on reasonably increased cost. */
18086 if (CONST_INT_P (expected_align_exp)
18087 && INTVAL (expected_align_exp) > align)
18088 align = INTVAL (expected_align_exp);
18089 if (CONST_INT_P (count_exp))
18090 count = expected_size = INTVAL (count_exp);
18091 if (CONST_INT_P (expected_size_exp) && count == 0)
18092 expected_size = INTVAL (expected_size_exp);
18094 /* Make sure we don't need to care about overflow later on. */
18095 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18098 /* Step 0: Decide on preferred algorithm, desired alignment and
18099 size of chunks to be copied by main loop. */
18101 alg = decide_alg (count, expected_size, true, &dynamic_check);
18102 desired_align = decide_alignment (align, alg, expected_size);
18104 if (!TARGET_ALIGN_STRINGOPS)
18105 align = desired_align;
18107 if (alg == libcall)
18109 gcc_assert (alg != no_stringop);
18111 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18112 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18117 gcc_unreachable ();
18119 need_zero_guard = true;
18120 size_needed = GET_MODE_SIZE (Pmode);
18122 case unrolled_loop:
18123 need_zero_guard = true;
18124 size_needed = GET_MODE_SIZE (Pmode) * 4;
18126 case rep_prefix_8_byte:
18129 case rep_prefix_4_byte:
18132 case rep_prefix_1_byte:
18136 need_zero_guard = true;
18140 epilogue_size_needed = size_needed;
18142 /* Step 1: Prologue guard. */
18144 /* Alignment code needs count to be in register. */
18145 if (CONST_INT_P (count_exp) && desired_align > align)
18147 if (INTVAL (count_exp) > desired_align
18148 && INTVAL (count_exp) > size_needed)
18151 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18152 if (align_bytes <= 0)
18155 align_bytes = desired_align - align_bytes;
18157 if (align_bytes == 0)
18159 enum machine_mode mode = SImode;
18160 if (TARGET_64BIT && (count & ~0xffffffff))
18162 count_exp = force_reg (mode, count_exp);
18165 /* Do the cheap promotion to allow better CSE across the
18166 main loop and epilogue (ie one load of the big constant in the
18167 front of all code. */
18168 if (CONST_INT_P (val_exp))
18169 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18170 desired_align, align);
18171 /* Ensure that alignment prologue won't copy past end of block. */
18172 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18174 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18175 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18176 Make sure it is power of 2. */
18177 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18179 /* To improve performance of small blocks, we jump around the VAL
18180 promoting mode. This mean that if the promoted VAL is not constant,
18181 we might not use it in the epilogue and have to use byte
18183 if (epilogue_size_needed > 2 && !promoted_val)
18184 force_loopy_epilogue = true;
18187 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18189 /* If main algorithm works on QImode, no epilogue is needed.
18190 For small sizes just don't align anything. */
18191 if (size_needed == 1)
18192 desired_align = align;
18199 label = gen_label_rtx ();
18200 emit_cmp_and_jump_insns (count_exp,
18201 GEN_INT (epilogue_size_needed),
18202 LTU, 0, counter_mode (count_exp), 1, label);
18203 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18204 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18206 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18209 if (dynamic_check != -1)
18211 rtx hot_label = gen_label_rtx ();
18212 jump_around_label = gen_label_rtx ();
18213 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18214 LEU, 0, counter_mode (count_exp), 1, hot_label);
18215 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18216 set_storage_via_libcall (dst, count_exp, val_exp, false);
18217 emit_jump (jump_around_label);
18218 emit_label (hot_label);
18221 /* Step 2: Alignment prologue. */
18223 /* Do the expensive promotion once we branched off the small blocks. */
18225 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18226 desired_align, align);
18227 gcc_assert (desired_align >= 1 && align >= 1);
18229 if (desired_align > align)
18231 if (align_bytes == 0)
18233 /* Except for the first move in epilogue, we no longer know
18234 constant offset in aliasing info. It don't seems to worth
18235 the pain to maintain it for the first move, so throw away
18237 dst = change_address (dst, BLKmode, destreg);
18238 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18243 /* If we know how many bytes need to be stored before dst is
18244 sufficiently aligned, maintain aliasing info accurately. */
18245 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18246 desired_align, align_bytes);
18247 count_exp = plus_constant (count_exp, -align_bytes);
18248 count -= align_bytes;
18250 if (need_zero_guard
18251 && (count < (unsigned HOST_WIDE_INT) size_needed
18252 || (align_bytes == 0
18253 && count < ((unsigned HOST_WIDE_INT) size_needed
18254 + desired_align - align))))
18256 /* It is possible that we copied enough so the main loop will not
18258 gcc_assert (size_needed > 1);
18259 if (label == NULL_RTX)
18260 label = gen_label_rtx ();
18261 emit_cmp_and_jump_insns (count_exp,
18262 GEN_INT (size_needed),
18263 LTU, 0, counter_mode (count_exp), 1, label);
18264 if (expected_size == -1
18265 || expected_size < (desired_align - align) / 2 + size_needed)
18266 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18268 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18271 if (label && size_needed == 1)
18273 emit_label (label);
18274 LABEL_NUSES (label) = 1;
18276 promoted_val = val_exp;
18277 epilogue_size_needed = 1;
18279 else if (label == NULL_RTX)
18280 epilogue_size_needed = size_needed;
18282 /* Step 3: Main loop. */
18288 gcc_unreachable ();
18290 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18291 count_exp, QImode, 1, expected_size);
18294 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18295 count_exp, Pmode, 1, expected_size);
18297 case unrolled_loop:
18298 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18299 count_exp, Pmode, 4, expected_size);
18301 case rep_prefix_8_byte:
18302 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18305 case rep_prefix_4_byte:
18306 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18309 case rep_prefix_1_byte:
18310 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18314 /* Adjust properly the offset of src and dest memory for aliasing. */
18315 if (CONST_INT_P (count_exp))
18316 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18317 (count / size_needed) * size_needed);
18319 dst = change_address (dst, BLKmode, destreg);
18321 /* Step 4: Epilogue to copy the remaining bytes. */
18325 /* When the main loop is done, COUNT_EXP might hold original count,
18326 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18327 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18328 bytes. Compensate if needed. */
18330 if (size_needed < epilogue_size_needed)
18333 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18334 GEN_INT (size_needed - 1), count_exp, 1,
18336 if (tmp != count_exp)
18337 emit_move_insn (count_exp, tmp);
18339 emit_label (label);
18340 LABEL_NUSES (label) = 1;
18343 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18345 if (force_loopy_epilogue)
18346 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18347 epilogue_size_needed);
18349 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18350 epilogue_size_needed);
18352 if (jump_around_label)
18353 emit_label (jump_around_label);
18357 /* Expand the appropriate insns for doing strlen if not just doing
18360 out = result, initialized with the start address
18361 align_rtx = alignment of the address.
18362 scratch = scratch register, initialized with the startaddress when
18363 not aligned, otherwise undefined
18365 This is just the body. It needs the initializations mentioned above and
18366 some address computing at the end. These things are done in i386.md. */
18369 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18373 rtx align_2_label = NULL_RTX;
18374 rtx align_3_label = NULL_RTX;
18375 rtx align_4_label = gen_label_rtx ();
18376 rtx end_0_label = gen_label_rtx ();
18378 rtx tmpreg = gen_reg_rtx (SImode);
18379 rtx scratch = gen_reg_rtx (SImode);
18383 if (CONST_INT_P (align_rtx))
18384 align = INTVAL (align_rtx);
18386 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18388 /* Is there a known alignment and is it less than 4? */
18391 rtx scratch1 = gen_reg_rtx (Pmode);
18392 emit_move_insn (scratch1, out);
18393 /* Is there a known alignment and is it not 2? */
18396 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18397 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18399 /* Leave just the 3 lower bits. */
18400 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18401 NULL_RTX, 0, OPTAB_WIDEN);
18403 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18404 Pmode, 1, align_4_label);
18405 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18406 Pmode, 1, align_2_label);
18407 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18408 Pmode, 1, align_3_label);
18412 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18413 check if is aligned to 4 - byte. */
18415 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18416 NULL_RTX, 0, OPTAB_WIDEN);
18418 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18419 Pmode, 1, align_4_label);
18422 mem = change_address (src, QImode, out);
18424 /* Now compare the bytes. */
18426 /* Compare the first n unaligned byte on a byte per byte basis. */
18427 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18428 QImode, 1, end_0_label);
18430 /* Increment the address. */
18431 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18433 /* Not needed with an alignment of 2 */
18436 emit_label (align_2_label);
18438 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18441 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18443 emit_label (align_3_label);
18446 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18449 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18452 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18453 align this loop. It gives only huge programs, but does not help to
18455 emit_label (align_4_label);
18457 mem = change_address (src, SImode, out);
18458 emit_move_insn (scratch, mem);
18459 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18461 /* This formula yields a nonzero result iff one of the bytes is zero.
18462 This saves three branches inside loop and many cycles. */
18464 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18465 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18466 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18467 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18468 gen_int_mode (0x80808080, SImode)));
18469 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18474 rtx reg = gen_reg_rtx (SImode);
18475 rtx reg2 = gen_reg_rtx (Pmode);
18476 emit_move_insn (reg, tmpreg);
18477 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18479 /* If zero is not in the first two bytes, move two bytes forward. */
18480 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18481 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18482 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18483 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18484 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18487 /* Emit lea manually to avoid clobbering of flags. */
18488 emit_insn (gen_rtx_SET (SImode, reg2,
18489 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18491 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18492 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18493 emit_insn (gen_rtx_SET (VOIDmode, out,
18494 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18501 rtx end_2_label = gen_label_rtx ();
18502 /* Is zero in the first two bytes? */
18504 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18505 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18506 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18507 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18508 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18510 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18511 JUMP_LABEL (tmp) = end_2_label;
18513 /* Not in the first two. Move two bytes forward. */
18514 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18515 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18517 emit_label (end_2_label);
18521 /* Avoid branch in fixing the byte. */
18522 tmpreg = gen_lowpart (QImode, tmpreg);
18523 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18524 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18525 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18527 emit_label (end_0_label);
18530 /* Expand strlen. */
18533 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18535 rtx addr, scratch1, scratch2, scratch3, scratch4;
18537 /* The generic case of strlen expander is long. Avoid it's
18538 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18540 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18541 && !TARGET_INLINE_ALL_STRINGOPS
18542 && !optimize_insn_for_size_p ()
18543 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18546 addr = force_reg (Pmode, XEXP (src, 0));
18547 scratch1 = gen_reg_rtx (Pmode);
18549 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18550 && !optimize_insn_for_size_p ())
18552 /* Well it seems that some optimizer does not combine a call like
18553 foo(strlen(bar), strlen(bar));
18554 when the move and the subtraction is done here. It does calculate
18555 the length just once when these instructions are done inside of
18556 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18557 often used and I use one fewer register for the lifetime of
18558 output_strlen_unroll() this is better. */
18560 emit_move_insn (out, addr);
18562 ix86_expand_strlensi_unroll_1 (out, src, align);
18564 /* strlensi_unroll_1 returns the address of the zero at the end of
18565 the string, like memchr(), so compute the length by subtracting
18566 the start address. */
18567 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18573 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18574 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18577 scratch2 = gen_reg_rtx (Pmode);
18578 scratch3 = gen_reg_rtx (Pmode);
18579 scratch4 = force_reg (Pmode, constm1_rtx);
18581 emit_move_insn (scratch3, addr);
18582 eoschar = force_reg (QImode, eoschar);
18584 src = replace_equiv_address_nv (src, scratch3);
18586 /* If .md starts supporting :P, this can be done in .md. */
18587 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18588 scratch4), UNSPEC_SCAS);
18589 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18590 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18591 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18596 /* For given symbol (function) construct code to compute address of it's PLT
18597 entry in large x86-64 PIC model. */
18599 construct_plt_address (rtx symbol)
18601 rtx tmp = gen_reg_rtx (Pmode);
18602 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18604 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18605 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18607 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18608 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18613 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18615 rtx pop, int sibcall)
18617 rtx use = NULL, call;
18619 if (pop == const0_rtx)
18621 gcc_assert (!TARGET_64BIT || !pop);
18623 if (TARGET_MACHO && !TARGET_64BIT)
18626 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18627 fnaddr = machopic_indirect_call_target (fnaddr);
18632 /* Static functions and indirect calls don't need the pic register. */
18633 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18634 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18635 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18636 use_reg (&use, pic_offset_table_rtx);
18639 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18641 rtx al = gen_rtx_REG (QImode, AX_REG);
18642 emit_move_insn (al, callarg2);
18643 use_reg (&use, al);
18646 if (ix86_cmodel == CM_LARGE_PIC
18647 && GET_CODE (fnaddr) == MEM
18648 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18649 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18650 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18651 else if (! call_insn_operand (XEXP (fnaddr, 0), Pmode))
18653 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18654 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18656 if (sibcall && TARGET_64BIT
18657 && !constant_call_address_operand (XEXP (fnaddr, 0), Pmode))
18660 addr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18661 fnaddr = gen_rtx_REG (Pmode, R11_REG);
18662 emit_move_insn (fnaddr, addr);
18663 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18666 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18668 call = gen_rtx_SET (VOIDmode, retval, call);
18671 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18672 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18673 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18676 && ix86_cfun_abi () == MS_ABI
18677 && (!callarg2 || INTVAL (callarg2) != -2))
18679 /* We need to represent that SI and DI registers are clobbered
18681 static int clobbered_registers[] = {
18682 XMM6_REG, XMM7_REG, XMM8_REG,
18683 XMM9_REG, XMM10_REG, XMM11_REG,
18684 XMM12_REG, XMM13_REG, XMM14_REG,
18685 XMM15_REG, SI_REG, DI_REG
18688 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18689 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18690 UNSPEC_MS_TO_SYSV_CALL);
18694 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18695 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18698 (SSE_REGNO_P (clobbered_registers[i])
18700 clobbered_registers[i]));
18702 call = gen_rtx_PARALLEL (VOIDmode,
18703 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18707 call = emit_call_insn (call);
18709 CALL_INSN_FUNCTION_USAGE (call) = use;
18713 /* Clear stack slot assignments remembered from previous functions.
18714 This is called from INIT_EXPANDERS once before RTL is emitted for each
18717 static struct machine_function *
18718 ix86_init_machine_status (void)
18720 struct machine_function *f;
18722 f = GGC_CNEW (struct machine_function);
18723 f->use_fast_prologue_epilogue_nregs = -1;
18724 f->tls_descriptor_call_expanded_p = 0;
18725 f->call_abi = DEFAULT_ABI;
18730 /* Return a MEM corresponding to a stack slot with mode MODE.
18731 Allocate a new slot if necessary.
18733 The RTL for a function can have several slots available: N is
18734 which slot to use. */
18737 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
18739 struct stack_local_entry *s;
18741 gcc_assert (n < MAX_386_STACK_LOCALS);
18743 /* Virtual slot is valid only before vregs are instantiated. */
18744 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
18746 for (s = ix86_stack_locals; s; s = s->next)
18747 if (s->mode == mode && s->n == n)
18748 return copy_rtx (s->rtl);
18750 s = (struct stack_local_entry *)
18751 ggc_alloc (sizeof (struct stack_local_entry));
18754 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
18756 s->next = ix86_stack_locals;
18757 ix86_stack_locals = s;
18761 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18763 static GTY(()) rtx ix86_tls_symbol;
18765 ix86_tls_get_addr (void)
18768 if (!ix86_tls_symbol)
18770 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
18771 (TARGET_ANY_GNU_TLS
18773 ? "___tls_get_addr"
18774 : "__tls_get_addr");
18777 return ix86_tls_symbol;
18780 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18782 static GTY(()) rtx ix86_tls_module_base_symbol;
18784 ix86_tls_module_base (void)
18787 if (!ix86_tls_module_base_symbol)
18789 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
18790 "_TLS_MODULE_BASE_");
18791 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
18792 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
18795 return ix86_tls_module_base_symbol;
18798 /* Calculate the length of the memory address in the instruction
18799 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18802 memory_address_length (rtx addr)
18804 struct ix86_address parts;
18805 rtx base, index, disp;
18809 if (GET_CODE (addr) == PRE_DEC
18810 || GET_CODE (addr) == POST_INC
18811 || GET_CODE (addr) == PRE_MODIFY
18812 || GET_CODE (addr) == POST_MODIFY)
18815 ok = ix86_decompose_address (addr, &parts);
18818 if (parts.base && GET_CODE (parts.base) == SUBREG)
18819 parts.base = SUBREG_REG (parts.base);
18820 if (parts.index && GET_CODE (parts.index) == SUBREG)
18821 parts.index = SUBREG_REG (parts.index);
18824 index = parts.index;
18829 - esp as the base always wants an index,
18830 - ebp as the base always wants a displacement. */
18832 /* Register Indirect. */
18833 if (base && !index && !disp)
18835 /* esp (for its index) and ebp (for its displacement) need
18836 the two-byte modrm form. */
18837 if (addr == stack_pointer_rtx
18838 || addr == arg_pointer_rtx
18839 || addr == frame_pointer_rtx
18840 || addr == hard_frame_pointer_rtx)
18844 /* Direct Addressing. */
18845 else if (disp && !base && !index)
18850 /* Find the length of the displacement constant. */
18853 if (base && satisfies_constraint_K (disp))
18858 /* ebp always wants a displacement. */
18859 else if (base == hard_frame_pointer_rtx)
18862 /* An index requires the two-byte modrm form.... */
18864 /* ...like esp, which always wants an index. */
18865 || base == stack_pointer_rtx
18866 || base == arg_pointer_rtx
18867 || base == frame_pointer_rtx)
18874 /* Compute default value for "length_immediate" attribute. When SHORTFORM
18875 is set, expect that insn have 8bit immediate alternative. */
18877 ix86_attr_length_immediate_default (rtx insn, int shortform)
18881 extract_insn_cached (insn);
18882 for (i = recog_data.n_operands - 1; i >= 0; --i)
18883 if (CONSTANT_P (recog_data.operand[i]))
18886 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
18890 switch (get_attr_mode (insn))
18901 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
18906 fatal_insn ("unknown insn mode", insn);
18912 /* Compute default value for "length_address" attribute. */
18914 ix86_attr_length_address_default (rtx insn)
18918 if (get_attr_type (insn) == TYPE_LEA)
18920 rtx set = PATTERN (insn);
18922 if (GET_CODE (set) == PARALLEL)
18923 set = XVECEXP (set, 0, 0);
18925 gcc_assert (GET_CODE (set) == SET);
18927 return memory_address_length (SET_SRC (set));
18930 extract_insn_cached (insn);
18931 for (i = recog_data.n_operands - 1; i >= 0; --i)
18932 if (MEM_P (recog_data.operand[i]))
18934 return memory_address_length (XEXP (recog_data.operand[i], 0));
18940 /* Compute default value for "length_vex" attribute. It includes
18941 2 or 3 byte VEX prefix and 1 opcode byte. */
18944 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
18949 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
18950 byte VEX prefix. */
18951 if (!has_0f_opcode || has_vex_w)
18954 /* We can always use 2 byte VEX prefix in 32bit. */
18958 extract_insn_cached (insn);
18960 for (i = recog_data.n_operands - 1; i >= 0; --i)
18961 if (REG_P (recog_data.operand[i]))
18963 /* REX.W bit uses 3 byte VEX prefix. */
18964 if (GET_MODE (recog_data.operand[i]) == DImode)
18969 /* REX.X or REX.B bits use 3 byte VEX prefix. */
18970 if (MEM_P (recog_data.operand[i])
18971 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
18978 /* Return the maximum number of instructions a cpu can issue. */
18981 ix86_issue_rate (void)
18985 case PROCESSOR_PENTIUM:
18989 case PROCESSOR_PENTIUMPRO:
18990 case PROCESSOR_PENTIUM4:
18991 case PROCESSOR_ATHLON:
18993 case PROCESSOR_AMDFAM10:
18994 case PROCESSOR_NOCONA:
18995 case PROCESSOR_GENERIC32:
18996 case PROCESSOR_GENERIC64:
18999 case PROCESSOR_CORE2:
19007 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19008 by DEP_INSN and nothing set by DEP_INSN. */
19011 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19015 /* Simplify the test for uninteresting insns. */
19016 if (insn_type != TYPE_SETCC
19017 && insn_type != TYPE_ICMOV
19018 && insn_type != TYPE_FCMOV
19019 && insn_type != TYPE_IBR)
19022 if ((set = single_set (dep_insn)) != 0)
19024 set = SET_DEST (set);
19027 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19028 && XVECLEN (PATTERN (dep_insn), 0) == 2
19029 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19030 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19032 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19033 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19038 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19041 /* This test is true if the dependent insn reads the flags but
19042 not any other potentially set register. */
19043 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19046 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19052 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
19053 address with operands set by DEP_INSN. */
19056 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19060 if (insn_type == TYPE_LEA
19063 addr = PATTERN (insn);
19065 if (GET_CODE (addr) == PARALLEL)
19066 addr = XVECEXP (addr, 0, 0);
19068 gcc_assert (GET_CODE (addr) == SET);
19070 addr = SET_SRC (addr);
19075 extract_insn_cached (insn);
19076 for (i = recog_data.n_operands - 1; i >= 0; --i)
19077 if (MEM_P (recog_data.operand[i]))
19079 addr = XEXP (recog_data.operand[i], 0);
19086 return modified_in_p (addr, dep_insn);
19090 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19092 enum attr_type insn_type, dep_insn_type;
19093 enum attr_memory memory;
19095 int dep_insn_code_number;
19097 /* Anti and output dependencies have zero cost on all CPUs. */
19098 if (REG_NOTE_KIND (link) != 0)
19101 dep_insn_code_number = recog_memoized (dep_insn);
19103 /* If we can't recognize the insns, we can't really do anything. */
19104 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19107 insn_type = get_attr_type (insn);
19108 dep_insn_type = get_attr_type (dep_insn);
19112 case PROCESSOR_PENTIUM:
19113 /* Address Generation Interlock adds a cycle of latency. */
19114 if (ix86_agi_dependent (insn, dep_insn, insn_type))
19117 /* ??? Compares pair with jump/setcc. */
19118 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19121 /* Floating point stores require value to be ready one cycle earlier. */
19122 if (insn_type == TYPE_FMOV
19123 && get_attr_memory (insn) == MEMORY_STORE
19124 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19128 case PROCESSOR_PENTIUMPRO:
19129 memory = get_attr_memory (insn);
19131 /* INT->FP conversion is expensive. */
19132 if (get_attr_fp_int_src (dep_insn))
19135 /* There is one cycle extra latency between an FP op and a store. */
19136 if (insn_type == TYPE_FMOV
19137 && (set = single_set (dep_insn)) != NULL_RTX
19138 && (set2 = single_set (insn)) != NULL_RTX
19139 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19140 && MEM_P (SET_DEST (set2)))
19143 /* Show ability of reorder buffer to hide latency of load by executing
19144 in parallel with previous instruction in case
19145 previous instruction is not needed to compute the address. */
19146 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19147 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19149 /* Claim moves to take one cycle, as core can issue one load
19150 at time and the next load can start cycle later. */
19151 if (dep_insn_type == TYPE_IMOV
19152 || dep_insn_type == TYPE_FMOV)
19160 memory = get_attr_memory (insn);
19162 /* The esp dependency is resolved before the instruction is really
19164 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19165 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19168 /* INT->FP conversion is expensive. */
19169 if (get_attr_fp_int_src (dep_insn))
19172 /* Show ability of reorder buffer to hide latency of load by executing
19173 in parallel with previous instruction in case
19174 previous instruction is not needed to compute the address. */
19175 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19176 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19178 /* Claim moves to take one cycle, as core can issue one load
19179 at time and the next load can start cycle later. */
19180 if (dep_insn_type == TYPE_IMOV
19181 || dep_insn_type == TYPE_FMOV)
19190 case PROCESSOR_ATHLON:
19192 case PROCESSOR_AMDFAM10:
19193 case PROCESSOR_GENERIC32:
19194 case PROCESSOR_GENERIC64:
19195 memory = get_attr_memory (insn);
19197 /* Show ability of reorder buffer to hide latency of load by executing
19198 in parallel with previous instruction in case
19199 previous instruction is not needed to compute the address. */
19200 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19201 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19203 enum attr_unit unit = get_attr_unit (insn);
19206 /* Because of the difference between the length of integer and
19207 floating unit pipeline preparation stages, the memory operands
19208 for floating point are cheaper.
19210 ??? For Athlon it the difference is most probably 2. */
19211 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19214 loadcost = TARGET_ATHLON ? 2 : 0;
19216 if (cost >= loadcost)
19229 /* How many alternative schedules to try. This should be as wide as the
19230 scheduling freedom in the DFA, but no wider. Making this value too
19231 large results extra work for the scheduler. */
19234 ia32_multipass_dfa_lookahead (void)
19238 case PROCESSOR_PENTIUM:
19241 case PROCESSOR_PENTIUMPRO:
19251 /* Compute the alignment given to a constant that is being placed in memory.
19252 EXP is the constant and ALIGN is the alignment that the object would
19254 The value of this function is used instead of that alignment to align
19258 ix86_constant_alignment (tree exp, int align)
19260 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19261 || TREE_CODE (exp) == INTEGER_CST)
19263 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19265 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19268 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19269 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19270 return BITS_PER_WORD;
19275 /* Compute the alignment for a static variable.
19276 TYPE is the data type, and ALIGN is the alignment that
19277 the object would ordinarily have. The value of this function is used
19278 instead of that alignment to align the object. */
19281 ix86_data_alignment (tree type, int align)
19283 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19285 if (AGGREGATE_TYPE_P (type)
19286 && TYPE_SIZE (type)
19287 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19288 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19289 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19290 && align < max_align)
19293 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19294 to 16byte boundary. */
19297 if (AGGREGATE_TYPE_P (type)
19298 && TYPE_SIZE (type)
19299 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19300 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19301 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19305 if (TREE_CODE (type) == ARRAY_TYPE)
19307 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19309 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19312 else if (TREE_CODE (type) == COMPLEX_TYPE)
19315 if (TYPE_MODE (type) == DCmode && align < 64)
19317 if ((TYPE_MODE (type) == XCmode
19318 || TYPE_MODE (type) == TCmode) && align < 128)
19321 else if ((TREE_CODE (type) == RECORD_TYPE
19322 || TREE_CODE (type) == UNION_TYPE
19323 || TREE_CODE (type) == QUAL_UNION_TYPE)
19324 && TYPE_FIELDS (type))
19326 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19328 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19331 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19332 || TREE_CODE (type) == INTEGER_TYPE)
19334 if (TYPE_MODE (type) == DFmode && align < 64)
19336 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19343 /* Compute the alignment for a local variable or a stack slot. EXP is
19344 the data type or decl itself, MODE is the widest mode available and
19345 ALIGN is the alignment that the object would ordinarily have. The
19346 value of this macro is used instead of that alignment to align the
19350 ix86_local_alignment (tree exp, enum machine_mode mode,
19351 unsigned int align)
19355 if (exp && DECL_P (exp))
19357 type = TREE_TYPE (exp);
19366 /* Don't do dynamic stack realignment for long long objects with
19367 -mpreferred-stack-boundary=2. */
19370 && ix86_preferred_stack_boundary < 64
19371 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19372 && (!type || !TYPE_USER_ALIGN (type))
19373 && (!decl || !DECL_USER_ALIGN (decl)))
19376 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19377 register in MODE. We will return the largest alignment of XF
19381 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19382 align = GET_MODE_ALIGNMENT (DFmode);
19386 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19387 to 16byte boundary. */
19390 if (AGGREGATE_TYPE_P (type)
19391 && TYPE_SIZE (type)
19392 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19393 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19394 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19397 if (TREE_CODE (type) == ARRAY_TYPE)
19399 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19401 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19404 else if (TREE_CODE (type) == COMPLEX_TYPE)
19406 if (TYPE_MODE (type) == DCmode && align < 64)
19408 if ((TYPE_MODE (type) == XCmode
19409 || TYPE_MODE (type) == TCmode) && align < 128)
19412 else if ((TREE_CODE (type) == RECORD_TYPE
19413 || TREE_CODE (type) == UNION_TYPE
19414 || TREE_CODE (type) == QUAL_UNION_TYPE)
19415 && TYPE_FIELDS (type))
19417 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19419 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19422 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19423 || TREE_CODE (type) == INTEGER_TYPE)
19426 if (TYPE_MODE (type) == DFmode && align < 64)
19428 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19434 /* Emit RTL insns to initialize the variable parts of a trampoline.
19435 FNADDR is an RTX for the address of the function's pure code.
19436 CXT is an RTX for the static chain value for the function. */
19438 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19442 /* Compute offset from the end of the jmp to the target function. */
19443 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19444 plus_constant (tramp, 10),
19445 NULL_RTX, 1, OPTAB_DIRECT);
19446 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19447 gen_int_mode (0xb9, QImode));
19448 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19449 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19450 gen_int_mode (0xe9, QImode));
19451 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19456 /* Try to load address using shorter movl instead of movabs.
19457 We may want to support movq for kernel mode, but kernel does not use
19458 trampolines at the moment. */
19459 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19461 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19462 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19463 gen_int_mode (0xbb41, HImode));
19464 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19465 gen_lowpart (SImode, fnaddr));
19470 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19471 gen_int_mode (0xbb49, HImode));
19472 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19476 /* Load static chain using movabs to r10. */
19477 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19478 gen_int_mode (0xba49, HImode));
19479 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19482 /* Jump to the r11 */
19483 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19484 gen_int_mode (0xff49, HImode));
19485 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
19486 gen_int_mode (0xe3, QImode));
19488 gcc_assert (offset <= TRAMPOLINE_SIZE);
19491 #ifdef ENABLE_EXECUTE_STACK
19492 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19493 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
19497 /* Codes for all the SSE/MMX builtins. */
19500 IX86_BUILTIN_ADDPS,
19501 IX86_BUILTIN_ADDSS,
19502 IX86_BUILTIN_DIVPS,
19503 IX86_BUILTIN_DIVSS,
19504 IX86_BUILTIN_MULPS,
19505 IX86_BUILTIN_MULSS,
19506 IX86_BUILTIN_SUBPS,
19507 IX86_BUILTIN_SUBSS,
19509 IX86_BUILTIN_CMPEQPS,
19510 IX86_BUILTIN_CMPLTPS,
19511 IX86_BUILTIN_CMPLEPS,
19512 IX86_BUILTIN_CMPGTPS,
19513 IX86_BUILTIN_CMPGEPS,
19514 IX86_BUILTIN_CMPNEQPS,
19515 IX86_BUILTIN_CMPNLTPS,
19516 IX86_BUILTIN_CMPNLEPS,
19517 IX86_BUILTIN_CMPNGTPS,
19518 IX86_BUILTIN_CMPNGEPS,
19519 IX86_BUILTIN_CMPORDPS,
19520 IX86_BUILTIN_CMPUNORDPS,
19521 IX86_BUILTIN_CMPEQSS,
19522 IX86_BUILTIN_CMPLTSS,
19523 IX86_BUILTIN_CMPLESS,
19524 IX86_BUILTIN_CMPNEQSS,
19525 IX86_BUILTIN_CMPNLTSS,
19526 IX86_BUILTIN_CMPNLESS,
19527 IX86_BUILTIN_CMPNGTSS,
19528 IX86_BUILTIN_CMPNGESS,
19529 IX86_BUILTIN_CMPORDSS,
19530 IX86_BUILTIN_CMPUNORDSS,
19532 IX86_BUILTIN_COMIEQSS,
19533 IX86_BUILTIN_COMILTSS,
19534 IX86_BUILTIN_COMILESS,
19535 IX86_BUILTIN_COMIGTSS,
19536 IX86_BUILTIN_COMIGESS,
19537 IX86_BUILTIN_COMINEQSS,
19538 IX86_BUILTIN_UCOMIEQSS,
19539 IX86_BUILTIN_UCOMILTSS,
19540 IX86_BUILTIN_UCOMILESS,
19541 IX86_BUILTIN_UCOMIGTSS,
19542 IX86_BUILTIN_UCOMIGESS,
19543 IX86_BUILTIN_UCOMINEQSS,
19545 IX86_BUILTIN_CVTPI2PS,
19546 IX86_BUILTIN_CVTPS2PI,
19547 IX86_BUILTIN_CVTSI2SS,
19548 IX86_BUILTIN_CVTSI642SS,
19549 IX86_BUILTIN_CVTSS2SI,
19550 IX86_BUILTIN_CVTSS2SI64,
19551 IX86_BUILTIN_CVTTPS2PI,
19552 IX86_BUILTIN_CVTTSS2SI,
19553 IX86_BUILTIN_CVTTSS2SI64,
19555 IX86_BUILTIN_MAXPS,
19556 IX86_BUILTIN_MAXSS,
19557 IX86_BUILTIN_MINPS,
19558 IX86_BUILTIN_MINSS,
19560 IX86_BUILTIN_LOADUPS,
19561 IX86_BUILTIN_STOREUPS,
19562 IX86_BUILTIN_MOVSS,
19564 IX86_BUILTIN_MOVHLPS,
19565 IX86_BUILTIN_MOVLHPS,
19566 IX86_BUILTIN_LOADHPS,
19567 IX86_BUILTIN_LOADLPS,
19568 IX86_BUILTIN_STOREHPS,
19569 IX86_BUILTIN_STORELPS,
19571 IX86_BUILTIN_MASKMOVQ,
19572 IX86_BUILTIN_MOVMSKPS,
19573 IX86_BUILTIN_PMOVMSKB,
19575 IX86_BUILTIN_MOVNTPS,
19576 IX86_BUILTIN_MOVNTQ,
19578 IX86_BUILTIN_LOADDQU,
19579 IX86_BUILTIN_STOREDQU,
19581 IX86_BUILTIN_PACKSSWB,
19582 IX86_BUILTIN_PACKSSDW,
19583 IX86_BUILTIN_PACKUSWB,
19585 IX86_BUILTIN_PADDB,
19586 IX86_BUILTIN_PADDW,
19587 IX86_BUILTIN_PADDD,
19588 IX86_BUILTIN_PADDQ,
19589 IX86_BUILTIN_PADDSB,
19590 IX86_BUILTIN_PADDSW,
19591 IX86_BUILTIN_PADDUSB,
19592 IX86_BUILTIN_PADDUSW,
19593 IX86_BUILTIN_PSUBB,
19594 IX86_BUILTIN_PSUBW,
19595 IX86_BUILTIN_PSUBD,
19596 IX86_BUILTIN_PSUBQ,
19597 IX86_BUILTIN_PSUBSB,
19598 IX86_BUILTIN_PSUBSW,
19599 IX86_BUILTIN_PSUBUSB,
19600 IX86_BUILTIN_PSUBUSW,
19603 IX86_BUILTIN_PANDN,
19607 IX86_BUILTIN_PAVGB,
19608 IX86_BUILTIN_PAVGW,
19610 IX86_BUILTIN_PCMPEQB,
19611 IX86_BUILTIN_PCMPEQW,
19612 IX86_BUILTIN_PCMPEQD,
19613 IX86_BUILTIN_PCMPGTB,
19614 IX86_BUILTIN_PCMPGTW,
19615 IX86_BUILTIN_PCMPGTD,
19617 IX86_BUILTIN_PMADDWD,
19619 IX86_BUILTIN_PMAXSW,
19620 IX86_BUILTIN_PMAXUB,
19621 IX86_BUILTIN_PMINSW,
19622 IX86_BUILTIN_PMINUB,
19624 IX86_BUILTIN_PMULHUW,
19625 IX86_BUILTIN_PMULHW,
19626 IX86_BUILTIN_PMULLW,
19628 IX86_BUILTIN_PSADBW,
19629 IX86_BUILTIN_PSHUFW,
19631 IX86_BUILTIN_PSLLW,
19632 IX86_BUILTIN_PSLLD,
19633 IX86_BUILTIN_PSLLQ,
19634 IX86_BUILTIN_PSRAW,
19635 IX86_BUILTIN_PSRAD,
19636 IX86_BUILTIN_PSRLW,
19637 IX86_BUILTIN_PSRLD,
19638 IX86_BUILTIN_PSRLQ,
19639 IX86_BUILTIN_PSLLWI,
19640 IX86_BUILTIN_PSLLDI,
19641 IX86_BUILTIN_PSLLQI,
19642 IX86_BUILTIN_PSRAWI,
19643 IX86_BUILTIN_PSRADI,
19644 IX86_BUILTIN_PSRLWI,
19645 IX86_BUILTIN_PSRLDI,
19646 IX86_BUILTIN_PSRLQI,
19648 IX86_BUILTIN_PUNPCKHBW,
19649 IX86_BUILTIN_PUNPCKHWD,
19650 IX86_BUILTIN_PUNPCKHDQ,
19651 IX86_BUILTIN_PUNPCKLBW,
19652 IX86_BUILTIN_PUNPCKLWD,
19653 IX86_BUILTIN_PUNPCKLDQ,
19655 IX86_BUILTIN_SHUFPS,
19657 IX86_BUILTIN_RCPPS,
19658 IX86_BUILTIN_RCPSS,
19659 IX86_BUILTIN_RSQRTPS,
19660 IX86_BUILTIN_RSQRTPS_NR,
19661 IX86_BUILTIN_RSQRTSS,
19662 IX86_BUILTIN_RSQRTF,
19663 IX86_BUILTIN_SQRTPS,
19664 IX86_BUILTIN_SQRTPS_NR,
19665 IX86_BUILTIN_SQRTSS,
19667 IX86_BUILTIN_UNPCKHPS,
19668 IX86_BUILTIN_UNPCKLPS,
19670 IX86_BUILTIN_ANDPS,
19671 IX86_BUILTIN_ANDNPS,
19673 IX86_BUILTIN_XORPS,
19676 IX86_BUILTIN_LDMXCSR,
19677 IX86_BUILTIN_STMXCSR,
19678 IX86_BUILTIN_SFENCE,
19680 /* 3DNow! Original */
19681 IX86_BUILTIN_FEMMS,
19682 IX86_BUILTIN_PAVGUSB,
19683 IX86_BUILTIN_PF2ID,
19684 IX86_BUILTIN_PFACC,
19685 IX86_BUILTIN_PFADD,
19686 IX86_BUILTIN_PFCMPEQ,
19687 IX86_BUILTIN_PFCMPGE,
19688 IX86_BUILTIN_PFCMPGT,
19689 IX86_BUILTIN_PFMAX,
19690 IX86_BUILTIN_PFMIN,
19691 IX86_BUILTIN_PFMUL,
19692 IX86_BUILTIN_PFRCP,
19693 IX86_BUILTIN_PFRCPIT1,
19694 IX86_BUILTIN_PFRCPIT2,
19695 IX86_BUILTIN_PFRSQIT1,
19696 IX86_BUILTIN_PFRSQRT,
19697 IX86_BUILTIN_PFSUB,
19698 IX86_BUILTIN_PFSUBR,
19699 IX86_BUILTIN_PI2FD,
19700 IX86_BUILTIN_PMULHRW,
19702 /* 3DNow! Athlon Extensions */
19703 IX86_BUILTIN_PF2IW,
19704 IX86_BUILTIN_PFNACC,
19705 IX86_BUILTIN_PFPNACC,
19706 IX86_BUILTIN_PI2FW,
19707 IX86_BUILTIN_PSWAPDSI,
19708 IX86_BUILTIN_PSWAPDSF,
19711 IX86_BUILTIN_ADDPD,
19712 IX86_BUILTIN_ADDSD,
19713 IX86_BUILTIN_DIVPD,
19714 IX86_BUILTIN_DIVSD,
19715 IX86_BUILTIN_MULPD,
19716 IX86_BUILTIN_MULSD,
19717 IX86_BUILTIN_SUBPD,
19718 IX86_BUILTIN_SUBSD,
19720 IX86_BUILTIN_CMPEQPD,
19721 IX86_BUILTIN_CMPLTPD,
19722 IX86_BUILTIN_CMPLEPD,
19723 IX86_BUILTIN_CMPGTPD,
19724 IX86_BUILTIN_CMPGEPD,
19725 IX86_BUILTIN_CMPNEQPD,
19726 IX86_BUILTIN_CMPNLTPD,
19727 IX86_BUILTIN_CMPNLEPD,
19728 IX86_BUILTIN_CMPNGTPD,
19729 IX86_BUILTIN_CMPNGEPD,
19730 IX86_BUILTIN_CMPORDPD,
19731 IX86_BUILTIN_CMPUNORDPD,
19732 IX86_BUILTIN_CMPEQSD,
19733 IX86_BUILTIN_CMPLTSD,
19734 IX86_BUILTIN_CMPLESD,
19735 IX86_BUILTIN_CMPNEQSD,
19736 IX86_BUILTIN_CMPNLTSD,
19737 IX86_BUILTIN_CMPNLESD,
19738 IX86_BUILTIN_CMPORDSD,
19739 IX86_BUILTIN_CMPUNORDSD,
19741 IX86_BUILTIN_COMIEQSD,
19742 IX86_BUILTIN_COMILTSD,
19743 IX86_BUILTIN_COMILESD,
19744 IX86_BUILTIN_COMIGTSD,
19745 IX86_BUILTIN_COMIGESD,
19746 IX86_BUILTIN_COMINEQSD,
19747 IX86_BUILTIN_UCOMIEQSD,
19748 IX86_BUILTIN_UCOMILTSD,
19749 IX86_BUILTIN_UCOMILESD,
19750 IX86_BUILTIN_UCOMIGTSD,
19751 IX86_BUILTIN_UCOMIGESD,
19752 IX86_BUILTIN_UCOMINEQSD,
19754 IX86_BUILTIN_MAXPD,
19755 IX86_BUILTIN_MAXSD,
19756 IX86_BUILTIN_MINPD,
19757 IX86_BUILTIN_MINSD,
19759 IX86_BUILTIN_ANDPD,
19760 IX86_BUILTIN_ANDNPD,
19762 IX86_BUILTIN_XORPD,
19764 IX86_BUILTIN_SQRTPD,
19765 IX86_BUILTIN_SQRTSD,
19767 IX86_BUILTIN_UNPCKHPD,
19768 IX86_BUILTIN_UNPCKLPD,
19770 IX86_BUILTIN_SHUFPD,
19772 IX86_BUILTIN_LOADUPD,
19773 IX86_BUILTIN_STOREUPD,
19774 IX86_BUILTIN_MOVSD,
19776 IX86_BUILTIN_LOADHPD,
19777 IX86_BUILTIN_LOADLPD,
19779 IX86_BUILTIN_CVTDQ2PD,
19780 IX86_BUILTIN_CVTDQ2PS,
19782 IX86_BUILTIN_CVTPD2DQ,
19783 IX86_BUILTIN_CVTPD2PI,
19784 IX86_BUILTIN_CVTPD2PS,
19785 IX86_BUILTIN_CVTTPD2DQ,
19786 IX86_BUILTIN_CVTTPD2PI,
19788 IX86_BUILTIN_CVTPI2PD,
19789 IX86_BUILTIN_CVTSI2SD,
19790 IX86_BUILTIN_CVTSI642SD,
19792 IX86_BUILTIN_CVTSD2SI,
19793 IX86_BUILTIN_CVTSD2SI64,
19794 IX86_BUILTIN_CVTSD2SS,
19795 IX86_BUILTIN_CVTSS2SD,
19796 IX86_BUILTIN_CVTTSD2SI,
19797 IX86_BUILTIN_CVTTSD2SI64,
19799 IX86_BUILTIN_CVTPS2DQ,
19800 IX86_BUILTIN_CVTPS2PD,
19801 IX86_BUILTIN_CVTTPS2DQ,
19803 IX86_BUILTIN_MOVNTI,
19804 IX86_BUILTIN_MOVNTPD,
19805 IX86_BUILTIN_MOVNTDQ,
19807 IX86_BUILTIN_MOVQ128,
19810 IX86_BUILTIN_MASKMOVDQU,
19811 IX86_BUILTIN_MOVMSKPD,
19812 IX86_BUILTIN_PMOVMSKB128,
19814 IX86_BUILTIN_PACKSSWB128,
19815 IX86_BUILTIN_PACKSSDW128,
19816 IX86_BUILTIN_PACKUSWB128,
19818 IX86_BUILTIN_PADDB128,
19819 IX86_BUILTIN_PADDW128,
19820 IX86_BUILTIN_PADDD128,
19821 IX86_BUILTIN_PADDQ128,
19822 IX86_BUILTIN_PADDSB128,
19823 IX86_BUILTIN_PADDSW128,
19824 IX86_BUILTIN_PADDUSB128,
19825 IX86_BUILTIN_PADDUSW128,
19826 IX86_BUILTIN_PSUBB128,
19827 IX86_BUILTIN_PSUBW128,
19828 IX86_BUILTIN_PSUBD128,
19829 IX86_BUILTIN_PSUBQ128,
19830 IX86_BUILTIN_PSUBSB128,
19831 IX86_BUILTIN_PSUBSW128,
19832 IX86_BUILTIN_PSUBUSB128,
19833 IX86_BUILTIN_PSUBUSW128,
19835 IX86_BUILTIN_PAND128,
19836 IX86_BUILTIN_PANDN128,
19837 IX86_BUILTIN_POR128,
19838 IX86_BUILTIN_PXOR128,
19840 IX86_BUILTIN_PAVGB128,
19841 IX86_BUILTIN_PAVGW128,
19843 IX86_BUILTIN_PCMPEQB128,
19844 IX86_BUILTIN_PCMPEQW128,
19845 IX86_BUILTIN_PCMPEQD128,
19846 IX86_BUILTIN_PCMPGTB128,
19847 IX86_BUILTIN_PCMPGTW128,
19848 IX86_BUILTIN_PCMPGTD128,
19850 IX86_BUILTIN_PMADDWD128,
19852 IX86_BUILTIN_PMAXSW128,
19853 IX86_BUILTIN_PMAXUB128,
19854 IX86_BUILTIN_PMINSW128,
19855 IX86_BUILTIN_PMINUB128,
19857 IX86_BUILTIN_PMULUDQ,
19858 IX86_BUILTIN_PMULUDQ128,
19859 IX86_BUILTIN_PMULHUW128,
19860 IX86_BUILTIN_PMULHW128,
19861 IX86_BUILTIN_PMULLW128,
19863 IX86_BUILTIN_PSADBW128,
19864 IX86_BUILTIN_PSHUFHW,
19865 IX86_BUILTIN_PSHUFLW,
19866 IX86_BUILTIN_PSHUFD,
19868 IX86_BUILTIN_PSLLDQI128,
19869 IX86_BUILTIN_PSLLWI128,
19870 IX86_BUILTIN_PSLLDI128,
19871 IX86_BUILTIN_PSLLQI128,
19872 IX86_BUILTIN_PSRAWI128,
19873 IX86_BUILTIN_PSRADI128,
19874 IX86_BUILTIN_PSRLDQI128,
19875 IX86_BUILTIN_PSRLWI128,
19876 IX86_BUILTIN_PSRLDI128,
19877 IX86_BUILTIN_PSRLQI128,
19879 IX86_BUILTIN_PSLLDQ128,
19880 IX86_BUILTIN_PSLLW128,
19881 IX86_BUILTIN_PSLLD128,
19882 IX86_BUILTIN_PSLLQ128,
19883 IX86_BUILTIN_PSRAW128,
19884 IX86_BUILTIN_PSRAD128,
19885 IX86_BUILTIN_PSRLW128,
19886 IX86_BUILTIN_PSRLD128,
19887 IX86_BUILTIN_PSRLQ128,
19889 IX86_BUILTIN_PUNPCKHBW128,
19890 IX86_BUILTIN_PUNPCKHWD128,
19891 IX86_BUILTIN_PUNPCKHDQ128,
19892 IX86_BUILTIN_PUNPCKHQDQ128,
19893 IX86_BUILTIN_PUNPCKLBW128,
19894 IX86_BUILTIN_PUNPCKLWD128,
19895 IX86_BUILTIN_PUNPCKLDQ128,
19896 IX86_BUILTIN_PUNPCKLQDQ128,
19898 IX86_BUILTIN_CLFLUSH,
19899 IX86_BUILTIN_MFENCE,
19900 IX86_BUILTIN_LFENCE,
19903 IX86_BUILTIN_ADDSUBPS,
19904 IX86_BUILTIN_HADDPS,
19905 IX86_BUILTIN_HSUBPS,
19906 IX86_BUILTIN_MOVSHDUP,
19907 IX86_BUILTIN_MOVSLDUP,
19908 IX86_BUILTIN_ADDSUBPD,
19909 IX86_BUILTIN_HADDPD,
19910 IX86_BUILTIN_HSUBPD,
19911 IX86_BUILTIN_LDDQU,
19913 IX86_BUILTIN_MONITOR,
19914 IX86_BUILTIN_MWAIT,
19917 IX86_BUILTIN_PHADDW,
19918 IX86_BUILTIN_PHADDD,
19919 IX86_BUILTIN_PHADDSW,
19920 IX86_BUILTIN_PHSUBW,
19921 IX86_BUILTIN_PHSUBD,
19922 IX86_BUILTIN_PHSUBSW,
19923 IX86_BUILTIN_PMADDUBSW,
19924 IX86_BUILTIN_PMULHRSW,
19925 IX86_BUILTIN_PSHUFB,
19926 IX86_BUILTIN_PSIGNB,
19927 IX86_BUILTIN_PSIGNW,
19928 IX86_BUILTIN_PSIGND,
19929 IX86_BUILTIN_PALIGNR,
19930 IX86_BUILTIN_PABSB,
19931 IX86_BUILTIN_PABSW,
19932 IX86_BUILTIN_PABSD,
19934 IX86_BUILTIN_PHADDW128,
19935 IX86_BUILTIN_PHADDD128,
19936 IX86_BUILTIN_PHADDSW128,
19937 IX86_BUILTIN_PHSUBW128,
19938 IX86_BUILTIN_PHSUBD128,
19939 IX86_BUILTIN_PHSUBSW128,
19940 IX86_BUILTIN_PMADDUBSW128,
19941 IX86_BUILTIN_PMULHRSW128,
19942 IX86_BUILTIN_PSHUFB128,
19943 IX86_BUILTIN_PSIGNB128,
19944 IX86_BUILTIN_PSIGNW128,
19945 IX86_BUILTIN_PSIGND128,
19946 IX86_BUILTIN_PALIGNR128,
19947 IX86_BUILTIN_PABSB128,
19948 IX86_BUILTIN_PABSW128,
19949 IX86_BUILTIN_PABSD128,
19951 /* AMDFAM10 - SSE4A New Instructions. */
19952 IX86_BUILTIN_MOVNTSD,
19953 IX86_BUILTIN_MOVNTSS,
19954 IX86_BUILTIN_EXTRQI,
19955 IX86_BUILTIN_EXTRQ,
19956 IX86_BUILTIN_INSERTQI,
19957 IX86_BUILTIN_INSERTQ,
19960 IX86_BUILTIN_BLENDPD,
19961 IX86_BUILTIN_BLENDPS,
19962 IX86_BUILTIN_BLENDVPD,
19963 IX86_BUILTIN_BLENDVPS,
19964 IX86_BUILTIN_PBLENDVB128,
19965 IX86_BUILTIN_PBLENDW128,
19970 IX86_BUILTIN_INSERTPS128,
19972 IX86_BUILTIN_MOVNTDQA,
19973 IX86_BUILTIN_MPSADBW128,
19974 IX86_BUILTIN_PACKUSDW128,
19975 IX86_BUILTIN_PCMPEQQ,
19976 IX86_BUILTIN_PHMINPOSUW128,
19978 IX86_BUILTIN_PMAXSB128,
19979 IX86_BUILTIN_PMAXSD128,
19980 IX86_BUILTIN_PMAXUD128,
19981 IX86_BUILTIN_PMAXUW128,
19983 IX86_BUILTIN_PMINSB128,
19984 IX86_BUILTIN_PMINSD128,
19985 IX86_BUILTIN_PMINUD128,
19986 IX86_BUILTIN_PMINUW128,
19988 IX86_BUILTIN_PMOVSXBW128,
19989 IX86_BUILTIN_PMOVSXBD128,
19990 IX86_BUILTIN_PMOVSXBQ128,
19991 IX86_BUILTIN_PMOVSXWD128,
19992 IX86_BUILTIN_PMOVSXWQ128,
19993 IX86_BUILTIN_PMOVSXDQ128,
19995 IX86_BUILTIN_PMOVZXBW128,
19996 IX86_BUILTIN_PMOVZXBD128,
19997 IX86_BUILTIN_PMOVZXBQ128,
19998 IX86_BUILTIN_PMOVZXWD128,
19999 IX86_BUILTIN_PMOVZXWQ128,
20000 IX86_BUILTIN_PMOVZXDQ128,
20002 IX86_BUILTIN_PMULDQ128,
20003 IX86_BUILTIN_PMULLD128,
20005 IX86_BUILTIN_ROUNDPD,
20006 IX86_BUILTIN_ROUNDPS,
20007 IX86_BUILTIN_ROUNDSD,
20008 IX86_BUILTIN_ROUNDSS,
20010 IX86_BUILTIN_PTESTZ,
20011 IX86_BUILTIN_PTESTC,
20012 IX86_BUILTIN_PTESTNZC,
20014 IX86_BUILTIN_VEC_INIT_V2SI,
20015 IX86_BUILTIN_VEC_INIT_V4HI,
20016 IX86_BUILTIN_VEC_INIT_V8QI,
20017 IX86_BUILTIN_VEC_EXT_V2DF,
20018 IX86_BUILTIN_VEC_EXT_V2DI,
20019 IX86_BUILTIN_VEC_EXT_V4SF,
20020 IX86_BUILTIN_VEC_EXT_V4SI,
20021 IX86_BUILTIN_VEC_EXT_V8HI,
20022 IX86_BUILTIN_VEC_EXT_V2SI,
20023 IX86_BUILTIN_VEC_EXT_V4HI,
20024 IX86_BUILTIN_VEC_EXT_V16QI,
20025 IX86_BUILTIN_VEC_SET_V2DI,
20026 IX86_BUILTIN_VEC_SET_V4SF,
20027 IX86_BUILTIN_VEC_SET_V4SI,
20028 IX86_BUILTIN_VEC_SET_V8HI,
20029 IX86_BUILTIN_VEC_SET_V4HI,
20030 IX86_BUILTIN_VEC_SET_V16QI,
20032 IX86_BUILTIN_VEC_PACK_SFIX,
20035 IX86_BUILTIN_CRC32QI,
20036 IX86_BUILTIN_CRC32HI,
20037 IX86_BUILTIN_CRC32SI,
20038 IX86_BUILTIN_CRC32DI,
20040 IX86_BUILTIN_PCMPESTRI128,
20041 IX86_BUILTIN_PCMPESTRM128,
20042 IX86_BUILTIN_PCMPESTRA128,
20043 IX86_BUILTIN_PCMPESTRC128,
20044 IX86_BUILTIN_PCMPESTRO128,
20045 IX86_BUILTIN_PCMPESTRS128,
20046 IX86_BUILTIN_PCMPESTRZ128,
20047 IX86_BUILTIN_PCMPISTRI128,
20048 IX86_BUILTIN_PCMPISTRM128,
20049 IX86_BUILTIN_PCMPISTRA128,
20050 IX86_BUILTIN_PCMPISTRC128,
20051 IX86_BUILTIN_PCMPISTRO128,
20052 IX86_BUILTIN_PCMPISTRS128,
20053 IX86_BUILTIN_PCMPISTRZ128,
20055 IX86_BUILTIN_PCMPGTQ,
20057 /* AES instructions */
20058 IX86_BUILTIN_AESENC128,
20059 IX86_BUILTIN_AESENCLAST128,
20060 IX86_BUILTIN_AESDEC128,
20061 IX86_BUILTIN_AESDECLAST128,
20062 IX86_BUILTIN_AESIMC128,
20063 IX86_BUILTIN_AESKEYGENASSIST128,
20065 /* PCLMUL instruction */
20066 IX86_BUILTIN_PCLMULQDQ128,
20069 IX86_BUILTIN_ADDPD256,
20070 IX86_BUILTIN_ADDPS256,
20071 IX86_BUILTIN_ADDSUBPD256,
20072 IX86_BUILTIN_ADDSUBPS256,
20073 IX86_BUILTIN_ANDPD256,
20074 IX86_BUILTIN_ANDPS256,
20075 IX86_BUILTIN_ANDNPD256,
20076 IX86_BUILTIN_ANDNPS256,
20077 IX86_BUILTIN_BLENDPD256,
20078 IX86_BUILTIN_BLENDPS256,
20079 IX86_BUILTIN_BLENDVPD256,
20080 IX86_BUILTIN_BLENDVPS256,
20081 IX86_BUILTIN_DIVPD256,
20082 IX86_BUILTIN_DIVPS256,
20083 IX86_BUILTIN_DPPS256,
20084 IX86_BUILTIN_HADDPD256,
20085 IX86_BUILTIN_HADDPS256,
20086 IX86_BUILTIN_HSUBPD256,
20087 IX86_BUILTIN_HSUBPS256,
20088 IX86_BUILTIN_MAXPD256,
20089 IX86_BUILTIN_MAXPS256,
20090 IX86_BUILTIN_MINPD256,
20091 IX86_BUILTIN_MINPS256,
20092 IX86_BUILTIN_MULPD256,
20093 IX86_BUILTIN_MULPS256,
20094 IX86_BUILTIN_ORPD256,
20095 IX86_BUILTIN_ORPS256,
20096 IX86_BUILTIN_SHUFPD256,
20097 IX86_BUILTIN_SHUFPS256,
20098 IX86_BUILTIN_SUBPD256,
20099 IX86_BUILTIN_SUBPS256,
20100 IX86_BUILTIN_XORPD256,
20101 IX86_BUILTIN_XORPS256,
20102 IX86_BUILTIN_CMPSD,
20103 IX86_BUILTIN_CMPSS,
20104 IX86_BUILTIN_CMPPD,
20105 IX86_BUILTIN_CMPPS,
20106 IX86_BUILTIN_CMPPD256,
20107 IX86_BUILTIN_CMPPS256,
20108 IX86_BUILTIN_CVTDQ2PD256,
20109 IX86_BUILTIN_CVTDQ2PS256,
20110 IX86_BUILTIN_CVTPD2PS256,
20111 IX86_BUILTIN_CVTPS2DQ256,
20112 IX86_BUILTIN_CVTPS2PD256,
20113 IX86_BUILTIN_CVTTPD2DQ256,
20114 IX86_BUILTIN_CVTPD2DQ256,
20115 IX86_BUILTIN_CVTTPS2DQ256,
20116 IX86_BUILTIN_EXTRACTF128PD256,
20117 IX86_BUILTIN_EXTRACTF128PS256,
20118 IX86_BUILTIN_EXTRACTF128SI256,
20119 IX86_BUILTIN_VZEROALL,
20120 IX86_BUILTIN_VZEROUPPER,
20121 IX86_BUILTIN_VZEROUPPER_REX64,
20122 IX86_BUILTIN_VPERMILVARPD,
20123 IX86_BUILTIN_VPERMILVARPS,
20124 IX86_BUILTIN_VPERMILVARPD256,
20125 IX86_BUILTIN_VPERMILVARPS256,
20126 IX86_BUILTIN_VPERMILPD,
20127 IX86_BUILTIN_VPERMILPS,
20128 IX86_BUILTIN_VPERMILPD256,
20129 IX86_BUILTIN_VPERMILPS256,
20130 IX86_BUILTIN_VPERM2F128PD256,
20131 IX86_BUILTIN_VPERM2F128PS256,
20132 IX86_BUILTIN_VPERM2F128SI256,
20133 IX86_BUILTIN_VBROADCASTSS,
20134 IX86_BUILTIN_VBROADCASTSD256,
20135 IX86_BUILTIN_VBROADCASTSS256,
20136 IX86_BUILTIN_VBROADCASTPD256,
20137 IX86_BUILTIN_VBROADCASTPS256,
20138 IX86_BUILTIN_VINSERTF128PD256,
20139 IX86_BUILTIN_VINSERTF128PS256,
20140 IX86_BUILTIN_VINSERTF128SI256,
20141 IX86_BUILTIN_LOADUPD256,
20142 IX86_BUILTIN_LOADUPS256,
20143 IX86_BUILTIN_STOREUPD256,
20144 IX86_BUILTIN_STOREUPS256,
20145 IX86_BUILTIN_LDDQU256,
20146 IX86_BUILTIN_MOVNTDQ256,
20147 IX86_BUILTIN_MOVNTPD256,
20148 IX86_BUILTIN_MOVNTPS256,
20149 IX86_BUILTIN_LOADDQU256,
20150 IX86_BUILTIN_STOREDQU256,
20151 IX86_BUILTIN_MASKLOADPD,
20152 IX86_BUILTIN_MASKLOADPS,
20153 IX86_BUILTIN_MASKSTOREPD,
20154 IX86_BUILTIN_MASKSTOREPS,
20155 IX86_BUILTIN_MASKLOADPD256,
20156 IX86_BUILTIN_MASKLOADPS256,
20157 IX86_BUILTIN_MASKSTOREPD256,
20158 IX86_BUILTIN_MASKSTOREPS256,
20159 IX86_BUILTIN_MOVSHDUP256,
20160 IX86_BUILTIN_MOVSLDUP256,
20161 IX86_BUILTIN_MOVDDUP256,
20163 IX86_BUILTIN_SQRTPD256,
20164 IX86_BUILTIN_SQRTPS256,
20165 IX86_BUILTIN_SQRTPS_NR256,
20166 IX86_BUILTIN_RSQRTPS256,
20167 IX86_BUILTIN_RSQRTPS_NR256,
20169 IX86_BUILTIN_RCPPS256,
20171 IX86_BUILTIN_ROUNDPD256,
20172 IX86_BUILTIN_ROUNDPS256,
20174 IX86_BUILTIN_UNPCKHPD256,
20175 IX86_BUILTIN_UNPCKLPD256,
20176 IX86_BUILTIN_UNPCKHPS256,
20177 IX86_BUILTIN_UNPCKLPS256,
20179 IX86_BUILTIN_SI256_SI,
20180 IX86_BUILTIN_PS256_PS,
20181 IX86_BUILTIN_PD256_PD,
20182 IX86_BUILTIN_SI_SI256,
20183 IX86_BUILTIN_PS_PS256,
20184 IX86_BUILTIN_PD_PD256,
20186 IX86_BUILTIN_VTESTZPD,
20187 IX86_BUILTIN_VTESTCPD,
20188 IX86_BUILTIN_VTESTNZCPD,
20189 IX86_BUILTIN_VTESTZPS,
20190 IX86_BUILTIN_VTESTCPS,
20191 IX86_BUILTIN_VTESTNZCPS,
20192 IX86_BUILTIN_VTESTZPD256,
20193 IX86_BUILTIN_VTESTCPD256,
20194 IX86_BUILTIN_VTESTNZCPD256,
20195 IX86_BUILTIN_VTESTZPS256,
20196 IX86_BUILTIN_VTESTCPS256,
20197 IX86_BUILTIN_VTESTNZCPS256,
20198 IX86_BUILTIN_PTESTZ256,
20199 IX86_BUILTIN_PTESTC256,
20200 IX86_BUILTIN_PTESTNZC256,
20202 IX86_BUILTIN_MOVMSKPD256,
20203 IX86_BUILTIN_MOVMSKPS256,
20205 /* TFmode support builtins. */
20207 IX86_BUILTIN_FABSQ,
20208 IX86_BUILTIN_COPYSIGNQ,
20210 /* SSE5 instructions */
20211 IX86_BUILTIN_FMADDSS,
20212 IX86_BUILTIN_FMADDSD,
20213 IX86_BUILTIN_FMADDPS,
20214 IX86_BUILTIN_FMADDPD,
20215 IX86_BUILTIN_FMSUBSS,
20216 IX86_BUILTIN_FMSUBSD,
20217 IX86_BUILTIN_FMSUBPS,
20218 IX86_BUILTIN_FMSUBPD,
20219 IX86_BUILTIN_FNMADDSS,
20220 IX86_BUILTIN_FNMADDSD,
20221 IX86_BUILTIN_FNMADDPS,
20222 IX86_BUILTIN_FNMADDPD,
20223 IX86_BUILTIN_FNMSUBSS,
20224 IX86_BUILTIN_FNMSUBSD,
20225 IX86_BUILTIN_FNMSUBPS,
20226 IX86_BUILTIN_FNMSUBPD,
20227 IX86_BUILTIN_PCMOV,
20228 IX86_BUILTIN_PCMOV_V2DI,
20229 IX86_BUILTIN_PCMOV_V4SI,
20230 IX86_BUILTIN_PCMOV_V8HI,
20231 IX86_BUILTIN_PCMOV_V16QI,
20232 IX86_BUILTIN_PCMOV_V4SF,
20233 IX86_BUILTIN_PCMOV_V2DF,
20234 IX86_BUILTIN_PPERM,
20235 IX86_BUILTIN_PERMPS,
20236 IX86_BUILTIN_PERMPD,
20237 IX86_BUILTIN_PMACSSWW,
20238 IX86_BUILTIN_PMACSWW,
20239 IX86_BUILTIN_PMACSSWD,
20240 IX86_BUILTIN_PMACSWD,
20241 IX86_BUILTIN_PMACSSDD,
20242 IX86_BUILTIN_PMACSDD,
20243 IX86_BUILTIN_PMACSSDQL,
20244 IX86_BUILTIN_PMACSSDQH,
20245 IX86_BUILTIN_PMACSDQL,
20246 IX86_BUILTIN_PMACSDQH,
20247 IX86_BUILTIN_PMADCSSWD,
20248 IX86_BUILTIN_PMADCSWD,
20249 IX86_BUILTIN_PHADDBW,
20250 IX86_BUILTIN_PHADDBD,
20251 IX86_BUILTIN_PHADDBQ,
20252 IX86_BUILTIN_PHADDWD,
20253 IX86_BUILTIN_PHADDWQ,
20254 IX86_BUILTIN_PHADDDQ,
20255 IX86_BUILTIN_PHADDUBW,
20256 IX86_BUILTIN_PHADDUBD,
20257 IX86_BUILTIN_PHADDUBQ,
20258 IX86_BUILTIN_PHADDUWD,
20259 IX86_BUILTIN_PHADDUWQ,
20260 IX86_BUILTIN_PHADDUDQ,
20261 IX86_BUILTIN_PHSUBBW,
20262 IX86_BUILTIN_PHSUBWD,
20263 IX86_BUILTIN_PHSUBDQ,
20264 IX86_BUILTIN_PROTB,
20265 IX86_BUILTIN_PROTW,
20266 IX86_BUILTIN_PROTD,
20267 IX86_BUILTIN_PROTQ,
20268 IX86_BUILTIN_PROTB_IMM,
20269 IX86_BUILTIN_PROTW_IMM,
20270 IX86_BUILTIN_PROTD_IMM,
20271 IX86_BUILTIN_PROTQ_IMM,
20272 IX86_BUILTIN_PSHLB,
20273 IX86_BUILTIN_PSHLW,
20274 IX86_BUILTIN_PSHLD,
20275 IX86_BUILTIN_PSHLQ,
20276 IX86_BUILTIN_PSHAB,
20277 IX86_BUILTIN_PSHAW,
20278 IX86_BUILTIN_PSHAD,
20279 IX86_BUILTIN_PSHAQ,
20280 IX86_BUILTIN_FRCZSS,
20281 IX86_BUILTIN_FRCZSD,
20282 IX86_BUILTIN_FRCZPS,
20283 IX86_BUILTIN_FRCZPD,
20284 IX86_BUILTIN_CVTPH2PS,
20285 IX86_BUILTIN_CVTPS2PH,
20287 IX86_BUILTIN_COMEQSS,
20288 IX86_BUILTIN_COMNESS,
20289 IX86_BUILTIN_COMLTSS,
20290 IX86_BUILTIN_COMLESS,
20291 IX86_BUILTIN_COMGTSS,
20292 IX86_BUILTIN_COMGESS,
20293 IX86_BUILTIN_COMUEQSS,
20294 IX86_BUILTIN_COMUNESS,
20295 IX86_BUILTIN_COMULTSS,
20296 IX86_BUILTIN_COMULESS,
20297 IX86_BUILTIN_COMUGTSS,
20298 IX86_BUILTIN_COMUGESS,
20299 IX86_BUILTIN_COMORDSS,
20300 IX86_BUILTIN_COMUNORDSS,
20301 IX86_BUILTIN_COMFALSESS,
20302 IX86_BUILTIN_COMTRUESS,
20304 IX86_BUILTIN_COMEQSD,
20305 IX86_BUILTIN_COMNESD,
20306 IX86_BUILTIN_COMLTSD,
20307 IX86_BUILTIN_COMLESD,
20308 IX86_BUILTIN_COMGTSD,
20309 IX86_BUILTIN_COMGESD,
20310 IX86_BUILTIN_COMUEQSD,
20311 IX86_BUILTIN_COMUNESD,
20312 IX86_BUILTIN_COMULTSD,
20313 IX86_BUILTIN_COMULESD,
20314 IX86_BUILTIN_COMUGTSD,
20315 IX86_BUILTIN_COMUGESD,
20316 IX86_BUILTIN_COMORDSD,
20317 IX86_BUILTIN_COMUNORDSD,
20318 IX86_BUILTIN_COMFALSESD,
20319 IX86_BUILTIN_COMTRUESD,
20321 IX86_BUILTIN_COMEQPS,
20322 IX86_BUILTIN_COMNEPS,
20323 IX86_BUILTIN_COMLTPS,
20324 IX86_BUILTIN_COMLEPS,
20325 IX86_BUILTIN_COMGTPS,
20326 IX86_BUILTIN_COMGEPS,
20327 IX86_BUILTIN_COMUEQPS,
20328 IX86_BUILTIN_COMUNEPS,
20329 IX86_BUILTIN_COMULTPS,
20330 IX86_BUILTIN_COMULEPS,
20331 IX86_BUILTIN_COMUGTPS,
20332 IX86_BUILTIN_COMUGEPS,
20333 IX86_BUILTIN_COMORDPS,
20334 IX86_BUILTIN_COMUNORDPS,
20335 IX86_BUILTIN_COMFALSEPS,
20336 IX86_BUILTIN_COMTRUEPS,
20338 IX86_BUILTIN_COMEQPD,
20339 IX86_BUILTIN_COMNEPD,
20340 IX86_BUILTIN_COMLTPD,
20341 IX86_BUILTIN_COMLEPD,
20342 IX86_BUILTIN_COMGTPD,
20343 IX86_BUILTIN_COMGEPD,
20344 IX86_BUILTIN_COMUEQPD,
20345 IX86_BUILTIN_COMUNEPD,
20346 IX86_BUILTIN_COMULTPD,
20347 IX86_BUILTIN_COMULEPD,
20348 IX86_BUILTIN_COMUGTPD,
20349 IX86_BUILTIN_COMUGEPD,
20350 IX86_BUILTIN_COMORDPD,
20351 IX86_BUILTIN_COMUNORDPD,
20352 IX86_BUILTIN_COMFALSEPD,
20353 IX86_BUILTIN_COMTRUEPD,
20355 IX86_BUILTIN_PCOMEQUB,
20356 IX86_BUILTIN_PCOMNEUB,
20357 IX86_BUILTIN_PCOMLTUB,
20358 IX86_BUILTIN_PCOMLEUB,
20359 IX86_BUILTIN_PCOMGTUB,
20360 IX86_BUILTIN_PCOMGEUB,
20361 IX86_BUILTIN_PCOMFALSEUB,
20362 IX86_BUILTIN_PCOMTRUEUB,
20363 IX86_BUILTIN_PCOMEQUW,
20364 IX86_BUILTIN_PCOMNEUW,
20365 IX86_BUILTIN_PCOMLTUW,
20366 IX86_BUILTIN_PCOMLEUW,
20367 IX86_BUILTIN_PCOMGTUW,
20368 IX86_BUILTIN_PCOMGEUW,
20369 IX86_BUILTIN_PCOMFALSEUW,
20370 IX86_BUILTIN_PCOMTRUEUW,
20371 IX86_BUILTIN_PCOMEQUD,
20372 IX86_BUILTIN_PCOMNEUD,
20373 IX86_BUILTIN_PCOMLTUD,
20374 IX86_BUILTIN_PCOMLEUD,
20375 IX86_BUILTIN_PCOMGTUD,
20376 IX86_BUILTIN_PCOMGEUD,
20377 IX86_BUILTIN_PCOMFALSEUD,
20378 IX86_BUILTIN_PCOMTRUEUD,
20379 IX86_BUILTIN_PCOMEQUQ,
20380 IX86_BUILTIN_PCOMNEUQ,
20381 IX86_BUILTIN_PCOMLTUQ,
20382 IX86_BUILTIN_PCOMLEUQ,
20383 IX86_BUILTIN_PCOMGTUQ,
20384 IX86_BUILTIN_PCOMGEUQ,
20385 IX86_BUILTIN_PCOMFALSEUQ,
20386 IX86_BUILTIN_PCOMTRUEUQ,
20388 IX86_BUILTIN_PCOMEQB,
20389 IX86_BUILTIN_PCOMNEB,
20390 IX86_BUILTIN_PCOMLTB,
20391 IX86_BUILTIN_PCOMLEB,
20392 IX86_BUILTIN_PCOMGTB,
20393 IX86_BUILTIN_PCOMGEB,
20394 IX86_BUILTIN_PCOMFALSEB,
20395 IX86_BUILTIN_PCOMTRUEB,
20396 IX86_BUILTIN_PCOMEQW,
20397 IX86_BUILTIN_PCOMNEW,
20398 IX86_BUILTIN_PCOMLTW,
20399 IX86_BUILTIN_PCOMLEW,
20400 IX86_BUILTIN_PCOMGTW,
20401 IX86_BUILTIN_PCOMGEW,
20402 IX86_BUILTIN_PCOMFALSEW,
20403 IX86_BUILTIN_PCOMTRUEW,
20404 IX86_BUILTIN_PCOMEQD,
20405 IX86_BUILTIN_PCOMNED,
20406 IX86_BUILTIN_PCOMLTD,
20407 IX86_BUILTIN_PCOMLED,
20408 IX86_BUILTIN_PCOMGTD,
20409 IX86_BUILTIN_PCOMGED,
20410 IX86_BUILTIN_PCOMFALSED,
20411 IX86_BUILTIN_PCOMTRUED,
20412 IX86_BUILTIN_PCOMEQQ,
20413 IX86_BUILTIN_PCOMNEQ,
20414 IX86_BUILTIN_PCOMLTQ,
20415 IX86_BUILTIN_PCOMLEQ,
20416 IX86_BUILTIN_PCOMGTQ,
20417 IX86_BUILTIN_PCOMGEQ,
20418 IX86_BUILTIN_PCOMFALSEQ,
20419 IX86_BUILTIN_PCOMTRUEQ,
20424 /* Table for the ix86 builtin decls. */
20425 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20427 /* Table of all of the builtin functions that are possible with different ISA's
20428 but are waiting to be built until a function is declared to use that
20430 struct builtin_isa GTY(())
20432 tree type; /* builtin type to use in the declaration */
20433 const char *name; /* function name */
20434 int isa; /* isa_flags this builtin is defined for */
20435 bool const_p; /* true if the declaration is constant */
20438 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20441 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20442 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20443 * function decl in the ix86_builtins array. Returns the function decl or
20444 * NULL_TREE, if the builtin was not added.
20446 * If the front end has a special hook for builtin functions, delay adding
20447 * builtin functions that aren't in the current ISA until the ISA is changed
20448 * with function specific optimization. Doing so, can save about 300K for the
20449 * default compiler. When the builtin is expanded, check at that time whether
20452 * If the front end doesn't have a special hook, record all builtins, even if
20453 * it isn't an instruction set in the current ISA in case the user uses
20454 * function specific options for a different ISA, so that we don't get scope
20455 * errors if a builtin is added in the middle of a function scope. */
20458 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20460 tree decl = NULL_TREE;
20462 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20464 ix86_builtins_isa[(int) code].isa = mask;
20466 if ((mask & ix86_isa_flags) != 0
20467 || (lang_hooks.builtin_function
20468 == lang_hooks.builtin_function_ext_scope))
20471 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20473 ix86_builtins[(int) code] = decl;
20474 ix86_builtins_isa[(int) code].type = NULL_TREE;
20478 ix86_builtins[(int) code] = NULL_TREE;
20479 ix86_builtins_isa[(int) code].const_p = false;
20480 ix86_builtins_isa[(int) code].type = type;
20481 ix86_builtins_isa[(int) code].name = name;
20488 /* Like def_builtin, but also marks the function decl "const". */
20491 def_builtin_const (int mask, const char *name, tree type,
20492 enum ix86_builtins code)
20494 tree decl = def_builtin (mask, name, type, code);
20496 TREE_READONLY (decl) = 1;
20498 ix86_builtins_isa[(int) code].const_p = true;
20503 /* Add any new builtin functions for a given ISA that may not have been
20504 declared. This saves a bit of space compared to adding all of the
20505 declarations to the tree, even if we didn't use them. */
20508 ix86_add_new_builtins (int isa)
20513 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20515 if ((ix86_builtins_isa[i].isa & isa) != 0
20516 && ix86_builtins_isa[i].type != NULL_TREE)
20518 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20519 ix86_builtins_isa[i].type,
20520 i, BUILT_IN_MD, NULL,
20523 ix86_builtins[i] = decl;
20524 ix86_builtins_isa[i].type = NULL_TREE;
20525 if (ix86_builtins_isa[i].const_p)
20526 TREE_READONLY (decl) = 1;
20531 /* Bits for builtin_description.flag. */
20533 /* Set when we don't support the comparison natively, and should
20534 swap_comparison in order to support it. */
20535 #define BUILTIN_DESC_SWAP_OPERANDS 1
20537 struct builtin_description
20539 const unsigned int mask;
20540 const enum insn_code icode;
20541 const char *const name;
20542 const enum ix86_builtins code;
20543 const enum rtx_code comparison;
20547 static const struct builtin_description bdesc_comi[] =
20549 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20550 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20551 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20552 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20553 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20554 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20555 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20556 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20557 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20558 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20559 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20560 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20561 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20562 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20563 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20564 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20565 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20566 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20567 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20568 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20569 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20570 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20571 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20572 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20575 static const struct builtin_description bdesc_pcmpestr[] =
20578 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20579 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20580 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20581 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20582 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20583 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20584 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20587 static const struct builtin_description bdesc_pcmpistr[] =
20590 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20591 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20592 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20593 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20594 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20595 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20596 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20599 /* Special builtin types */
20600 enum ix86_special_builtin_type
20602 SPECIAL_FTYPE_UNKNOWN,
20604 V32QI_FTYPE_PCCHAR,
20605 V16QI_FTYPE_PCCHAR,
20607 V8SF_FTYPE_PCFLOAT,
20609 V4DF_FTYPE_PCDOUBLE,
20610 V4SF_FTYPE_PCFLOAT,
20611 V2DF_FTYPE_PCDOUBLE,
20612 V8SF_FTYPE_PCV8SF_V8SF,
20613 V4DF_FTYPE_PCV4DF_V4DF,
20614 V4SF_FTYPE_V4SF_PCV2SF,
20615 V4SF_FTYPE_PCV4SF_V4SF,
20616 V2DF_FTYPE_V2DF_PCDOUBLE,
20617 V2DF_FTYPE_PCV2DF_V2DF,
20619 VOID_FTYPE_PV2SF_V4SF,
20620 VOID_FTYPE_PV4DI_V4DI,
20621 VOID_FTYPE_PV2DI_V2DI,
20622 VOID_FTYPE_PCHAR_V32QI,
20623 VOID_FTYPE_PCHAR_V16QI,
20624 VOID_FTYPE_PFLOAT_V8SF,
20625 VOID_FTYPE_PFLOAT_V4SF,
20626 VOID_FTYPE_PDOUBLE_V4DF,
20627 VOID_FTYPE_PDOUBLE_V2DF,
20629 VOID_FTYPE_PINT_INT,
20630 VOID_FTYPE_PV8SF_V8SF_V8SF,
20631 VOID_FTYPE_PV4DF_V4DF_V4DF,
20632 VOID_FTYPE_PV4SF_V4SF_V4SF,
20633 VOID_FTYPE_PV2DF_V2DF_V2DF
20636 /* Builtin types */
20637 enum ix86_builtin_type
20640 FLOAT128_FTYPE_FLOAT128,
20642 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20643 INT_FTYPE_V8SF_V8SF_PTEST,
20644 INT_FTYPE_V4DI_V4DI_PTEST,
20645 INT_FTYPE_V4DF_V4DF_PTEST,
20646 INT_FTYPE_V4SF_V4SF_PTEST,
20647 INT_FTYPE_V2DI_V2DI_PTEST,
20648 INT_FTYPE_V2DF_V2DF_PTEST,
20680 V4SF_FTYPE_V4SF_VEC_MERGE,
20689 V2DF_FTYPE_V2DF_VEC_MERGE,
20700 V16QI_FTYPE_V16QI_V16QI,
20701 V16QI_FTYPE_V8HI_V8HI,
20702 V8QI_FTYPE_V8QI_V8QI,
20703 V8QI_FTYPE_V4HI_V4HI,
20704 V8HI_FTYPE_V8HI_V8HI,
20705 V8HI_FTYPE_V8HI_V8HI_COUNT,
20706 V8HI_FTYPE_V16QI_V16QI,
20707 V8HI_FTYPE_V4SI_V4SI,
20708 V8HI_FTYPE_V8HI_SI_COUNT,
20709 V8SF_FTYPE_V8SF_V8SF,
20710 V8SF_FTYPE_V8SF_V8SI,
20711 V4SI_FTYPE_V4SI_V4SI,
20712 V4SI_FTYPE_V4SI_V4SI_COUNT,
20713 V4SI_FTYPE_V8HI_V8HI,
20714 V4SI_FTYPE_V4SF_V4SF,
20715 V4SI_FTYPE_V2DF_V2DF,
20716 V4SI_FTYPE_V4SI_SI_COUNT,
20717 V4HI_FTYPE_V4HI_V4HI,
20718 V4HI_FTYPE_V4HI_V4HI_COUNT,
20719 V4HI_FTYPE_V8QI_V8QI,
20720 V4HI_FTYPE_V2SI_V2SI,
20721 V4HI_FTYPE_V4HI_SI_COUNT,
20722 V4DF_FTYPE_V4DF_V4DF,
20723 V4DF_FTYPE_V4DF_V4DI,
20724 V4SF_FTYPE_V4SF_V4SF,
20725 V4SF_FTYPE_V4SF_V4SF_SWAP,
20726 V4SF_FTYPE_V4SF_V4SI,
20727 V4SF_FTYPE_V4SF_V2SI,
20728 V4SF_FTYPE_V4SF_V2DF,
20729 V4SF_FTYPE_V4SF_DI,
20730 V4SF_FTYPE_V4SF_SI,
20731 V2DI_FTYPE_V2DI_V2DI,
20732 V2DI_FTYPE_V2DI_V2DI_COUNT,
20733 V2DI_FTYPE_V16QI_V16QI,
20734 V2DI_FTYPE_V4SI_V4SI,
20735 V2DI_FTYPE_V2DI_V16QI,
20736 V2DI_FTYPE_V2DF_V2DF,
20737 V2DI_FTYPE_V2DI_SI_COUNT,
20738 V2SI_FTYPE_V2SI_V2SI,
20739 V2SI_FTYPE_V2SI_V2SI_COUNT,
20740 V2SI_FTYPE_V4HI_V4HI,
20741 V2SI_FTYPE_V2SF_V2SF,
20742 V2SI_FTYPE_V2SI_SI_COUNT,
20743 V2DF_FTYPE_V2DF_V2DF,
20744 V2DF_FTYPE_V2DF_V2DF_SWAP,
20745 V2DF_FTYPE_V2DF_V4SF,
20746 V2DF_FTYPE_V2DF_V2DI,
20747 V2DF_FTYPE_V2DF_DI,
20748 V2DF_FTYPE_V2DF_SI,
20749 V2SF_FTYPE_V2SF_V2SF,
20750 V1DI_FTYPE_V1DI_V1DI,
20751 V1DI_FTYPE_V1DI_V1DI_COUNT,
20752 V1DI_FTYPE_V8QI_V8QI,
20753 V1DI_FTYPE_V2SI_V2SI,
20754 V1DI_FTYPE_V1DI_SI_COUNT,
20755 UINT64_FTYPE_UINT64_UINT64,
20756 UINT_FTYPE_UINT_UINT,
20757 UINT_FTYPE_UINT_USHORT,
20758 UINT_FTYPE_UINT_UCHAR,
20759 V8HI_FTYPE_V8HI_INT,
20760 V4SI_FTYPE_V4SI_INT,
20761 V4HI_FTYPE_V4HI_INT,
20762 V8SF_FTYPE_V8SF_INT,
20763 V4SI_FTYPE_V8SI_INT,
20764 V4SF_FTYPE_V8SF_INT,
20765 V2DF_FTYPE_V4DF_INT,
20766 V4DF_FTYPE_V4DF_INT,
20767 V4SF_FTYPE_V4SF_INT,
20768 V2DI_FTYPE_V2DI_INT,
20769 V2DI2TI_FTYPE_V2DI_INT,
20770 V2DF_FTYPE_V2DF_INT,
20771 V16QI_FTYPE_V16QI_V16QI_V16QI,
20772 V8SF_FTYPE_V8SF_V8SF_V8SF,
20773 V4DF_FTYPE_V4DF_V4DF_V4DF,
20774 V4SF_FTYPE_V4SF_V4SF_V4SF,
20775 V2DF_FTYPE_V2DF_V2DF_V2DF,
20776 V16QI_FTYPE_V16QI_V16QI_INT,
20777 V8SI_FTYPE_V8SI_V8SI_INT,
20778 V8SI_FTYPE_V8SI_V4SI_INT,
20779 V8HI_FTYPE_V8HI_V8HI_INT,
20780 V8SF_FTYPE_V8SF_V8SF_INT,
20781 V8SF_FTYPE_V8SF_V4SF_INT,
20782 V4SI_FTYPE_V4SI_V4SI_INT,
20783 V4DF_FTYPE_V4DF_V4DF_INT,
20784 V4DF_FTYPE_V4DF_V2DF_INT,
20785 V4SF_FTYPE_V4SF_V4SF_INT,
20786 V2DI_FTYPE_V2DI_V2DI_INT,
20787 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20788 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20789 V2DF_FTYPE_V2DF_V2DF_INT,
20790 V2DI_FTYPE_V2DI_UINT_UINT,
20791 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20794 /* Special builtins with variable number of arguments. */
20795 static const struct builtin_description bdesc_special_args[] =
20798 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20801 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20804 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20805 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20806 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20808 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20809 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20810 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20811 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20813 /* SSE or 3DNow!A */
20814 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20815 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
20818 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20819 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20820 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20821 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
20822 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20823 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
20824 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
20825 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
20826 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20828 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20829 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20832 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20835 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
20838 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20839 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20842 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
20843 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
20844 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
20846 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20848 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20849 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
20850 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
20852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
20853 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
20854 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20855 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20856 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20857 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
20858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
20860 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
20861 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
20862 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
20864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
20865 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
20866 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
20867 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
20868 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
20869 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
20870 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
20871 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
20874 /* Builtins with variable number of arguments. */
20875 static const struct builtin_description bdesc_args[] =
20878 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20879 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20880 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20881 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20882 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20883 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20885 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20886 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20887 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20888 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20889 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20890 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20891 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20892 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20894 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20895 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20897 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20898 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20899 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20900 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20902 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20903 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20904 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20905 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20906 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20907 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20909 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20910 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20911 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
20912 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20913 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
20914 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
20916 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20917 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
20918 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
20920 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
20922 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20923 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20924 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20925 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20926 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20927 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20929 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20930 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20931 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
20932 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20933 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20934 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
20936 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
20937 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
20938 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
20939 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
20942 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20943 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20944 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20945 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20947 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
20948 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20949 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20950 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20951 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20952 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
20953 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20954 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20955 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20956 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20957 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20958 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20959 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20960 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20961 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
20964 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
20965 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
20966 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
20967 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
20968 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20969 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
20972 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
20973 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20974 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20975 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20976 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20977 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
20978 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20979 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20980 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20981 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
20982 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
20983 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
20985 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
20987 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20988 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20989 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20990 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20991 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20992 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20993 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20994 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
20996 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
20997 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
20998 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
20999 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21000 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21001 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21002 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21003 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21004 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21005 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21006 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21007 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21008 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21009 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21010 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21011 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21012 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21013 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21014 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21015 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21016 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21017 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21019 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21020 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21022 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21024 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21025 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21026 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21027 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21029 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21030 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21031 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21032 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21033 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21035 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21036 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21037 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21039 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21041 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21042 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21043 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21045 /* SSE MMX or 3Dnow!A */
21046 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21047 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21048 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21050 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21051 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21052 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21053 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21055 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21056 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21058 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21061 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21063 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21064 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21065 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21066 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21067 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21069 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21070 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21071 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21072 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21073 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21075 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21077 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21078 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21079 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21080 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21082 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21083 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21084 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21086 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21087 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21088 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21089 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21090 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21091 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21092 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21093 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21095 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21096 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21097 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21098 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21099 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21100 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21101 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21103 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21104 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21107 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21108 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21109 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21110 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21111 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21112 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21113 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21114 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21116 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21117 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21118 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21119 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21121 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21122 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21123 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21124 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21126 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21127 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21128 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21130 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21132 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21133 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21134 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21135 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21136 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21137 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21138 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21139 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21141 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21142 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21143 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21144 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21145 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21146 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21147 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21148 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21150 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21151 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21153 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21154 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21155 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21156 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21158 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21161 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21162 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21163 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21164 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21165 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21166 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21168 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21169 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21170 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21171 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21173 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21174 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21175 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21176 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21177 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21178 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21179 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21180 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21182 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21183 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21184 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21186 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21187 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21189 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21190 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21192 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21194 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21195 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21196 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21197 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21199 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21200 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21201 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21202 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21203 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21204 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21205 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21207 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21208 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21209 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21210 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21211 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21212 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21213 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21215 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21216 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21217 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21218 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21220 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21226 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21227 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21229 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21232 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21233 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21236 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21237 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21239 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21240 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21241 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21242 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21243 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21244 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21247 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21248 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21249 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21250 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21251 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21252 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21254 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21255 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21256 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21257 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21258 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21259 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21260 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21261 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21262 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21263 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21264 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21265 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21266 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21267 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21268 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21269 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21270 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21271 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21272 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21273 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21274 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21275 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21276 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21277 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21280 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21281 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21284 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21285 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21286 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21287 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21288 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21289 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21290 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21291 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21292 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21293 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21295 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21296 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21297 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21298 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21299 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21300 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21301 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21302 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21303 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21304 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21305 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21306 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21307 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21309 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21310 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21311 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21312 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21313 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21314 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21315 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21316 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21317 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21318 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21319 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21320 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21322 /* SSE4.1 and SSE5 */
21323 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21324 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21325 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21326 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21328 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21329 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21330 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21333 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21334 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21335 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21336 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21337 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21340 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21341 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21342 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21343 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21346 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21347 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21349 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21350 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21351 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21352 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21355 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21358 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21359 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21360 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21361 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21362 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21363 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21364 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21365 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21366 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21367 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21368 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21369 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21370 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21371 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21372 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21373 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21374 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21375 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21376 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21377 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21378 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21379 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21380 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21381 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21382 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21383 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21385 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21386 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21387 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21388 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21390 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21391 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21392 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21393 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21394 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21395 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21396 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21397 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21398 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21399 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21400 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21401 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21402 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21403 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21404 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21405 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21406 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21407 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21408 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21409 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21410 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21411 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21412 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21413 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21414 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21415 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21416 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21417 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21418 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21419 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21420 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21421 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21422 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21423 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21425 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21426 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21427 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21429 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21430 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21431 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21432 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21433 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21435 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21437 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21438 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21440 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21441 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21442 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21443 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21445 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21446 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21447 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21448 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21449 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21450 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21452 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21453 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21454 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21455 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21456 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21457 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21458 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21459 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21460 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21461 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21462 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21463 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21464 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21465 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21466 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21468 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21469 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21473 enum multi_arg_type {
21483 MULTI_ARG_3_PERMPS,
21484 MULTI_ARG_3_PERMPD,
21491 MULTI_ARG_2_DI_IMM,
21492 MULTI_ARG_2_SI_IMM,
21493 MULTI_ARG_2_HI_IMM,
21494 MULTI_ARG_2_QI_IMM,
21495 MULTI_ARG_2_SF_CMP,
21496 MULTI_ARG_2_DF_CMP,
21497 MULTI_ARG_2_DI_CMP,
21498 MULTI_ARG_2_SI_CMP,
21499 MULTI_ARG_2_HI_CMP,
21500 MULTI_ARG_2_QI_CMP,
21523 static const struct builtin_description bdesc_multi_arg[] =
21525 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
21526 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
21527 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
21528 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
21529 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
21530 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
21531 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
21532 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
21533 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
21534 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
21535 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
21536 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
21537 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
21538 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
21539 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
21540 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
21541 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
21542 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
21543 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
21544 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
21545 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
21546 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
21547 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
21548 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
21549 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
21550 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
21551 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
21552 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
21553 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21554 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
21555 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
21556 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
21557 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21558 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21559 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21560 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21561 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21562 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
21563 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
21564 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
21565 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
21566 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
21567 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
21568 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
21569 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
21570 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
21571 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
21572 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
21573 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
21574 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
21575 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
21576 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
21577 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
21578 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
21579 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
21580 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
21581 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
21582 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
21583 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
21584 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
21585 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
21586 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
21587 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
21588 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
21589 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
21590 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
21591 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
21592 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
21593 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
21594 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
21595 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
21596 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
21597 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
21598 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
21599 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
21601 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
21602 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21603 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21604 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21605 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21606 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21607 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21608 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21609 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21610 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21611 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21612 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21613 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21614 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21615 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21616 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21618 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21619 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21620 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21621 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21622 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21623 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21624 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21625 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21626 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21627 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21628 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21629 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21630 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21631 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21632 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21633 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21635 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21636 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21637 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21638 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21639 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21640 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21641 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21642 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21643 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21644 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21645 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21646 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21647 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21648 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21649 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21650 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21652 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21653 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21654 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21655 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21656 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21657 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21658 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21659 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21660 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21661 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21662 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21663 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21664 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21665 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21666 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21667 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21669 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21670 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21671 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21672 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21673 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21674 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21675 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21677 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21678 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21679 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21680 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21681 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21682 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21683 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21685 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21686 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21687 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21688 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21689 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21690 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21691 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21693 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21694 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21695 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21696 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21697 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21698 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21699 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21701 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21702 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21703 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21704 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21705 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21706 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21707 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21709 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21710 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21711 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21712 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21713 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21714 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21715 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21717 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21718 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21719 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21720 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21721 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21722 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21723 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21725 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21726 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21727 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21728 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21729 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21730 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21731 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21733 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21734 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21735 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21736 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21737 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21738 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21739 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21740 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21742 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21743 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21744 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21745 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21746 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21747 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21748 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21749 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21751 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21752 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21753 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21754 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21755 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21756 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21757 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21758 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21761 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21762 in the current target ISA to allow the user to compile particular modules
21763 with different target specific options that differ from the command line
21766 ix86_init_mmx_sse_builtins (void)
21768 const struct builtin_description * d;
21771 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21772 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21773 tree V1DI_type_node
21774 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21775 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21776 tree V2DI_type_node
21777 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21778 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21779 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21780 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21781 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21782 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21783 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21785 tree pchar_type_node = build_pointer_type (char_type_node);
21786 tree pcchar_type_node
21787 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21788 tree pfloat_type_node = build_pointer_type (float_type_node);
21789 tree pcfloat_type_node
21790 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21791 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21792 tree pcv2sf_type_node
21793 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21794 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21795 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21798 tree int_ftype_v4sf_v4sf
21799 = build_function_type_list (integer_type_node,
21800 V4SF_type_node, V4SF_type_node, NULL_TREE);
21801 tree v4si_ftype_v4sf_v4sf
21802 = build_function_type_list (V4SI_type_node,
21803 V4SF_type_node, V4SF_type_node, NULL_TREE);
21804 /* MMX/SSE/integer conversions. */
21805 tree int_ftype_v4sf
21806 = build_function_type_list (integer_type_node,
21807 V4SF_type_node, NULL_TREE);
21808 tree int64_ftype_v4sf
21809 = build_function_type_list (long_long_integer_type_node,
21810 V4SF_type_node, NULL_TREE);
21811 tree int_ftype_v8qi
21812 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21813 tree v4sf_ftype_v4sf_int
21814 = build_function_type_list (V4SF_type_node,
21815 V4SF_type_node, integer_type_node, NULL_TREE);
21816 tree v4sf_ftype_v4sf_int64
21817 = build_function_type_list (V4SF_type_node,
21818 V4SF_type_node, long_long_integer_type_node,
21820 tree v4sf_ftype_v4sf_v2si
21821 = build_function_type_list (V4SF_type_node,
21822 V4SF_type_node, V2SI_type_node, NULL_TREE);
21824 /* Miscellaneous. */
21825 tree v8qi_ftype_v4hi_v4hi
21826 = build_function_type_list (V8QI_type_node,
21827 V4HI_type_node, V4HI_type_node, NULL_TREE);
21828 tree v4hi_ftype_v2si_v2si
21829 = build_function_type_list (V4HI_type_node,
21830 V2SI_type_node, V2SI_type_node, NULL_TREE);
21831 tree v4sf_ftype_v4sf_v4sf_int
21832 = build_function_type_list (V4SF_type_node,
21833 V4SF_type_node, V4SF_type_node,
21834 integer_type_node, NULL_TREE);
21835 tree v2si_ftype_v4hi_v4hi
21836 = build_function_type_list (V2SI_type_node,
21837 V4HI_type_node, V4HI_type_node, NULL_TREE);
21838 tree v4hi_ftype_v4hi_int
21839 = build_function_type_list (V4HI_type_node,
21840 V4HI_type_node, integer_type_node, NULL_TREE);
21841 tree v2si_ftype_v2si_int
21842 = build_function_type_list (V2SI_type_node,
21843 V2SI_type_node, integer_type_node, NULL_TREE);
21844 tree v1di_ftype_v1di_int
21845 = build_function_type_list (V1DI_type_node,
21846 V1DI_type_node, integer_type_node, NULL_TREE);
21848 tree void_ftype_void
21849 = build_function_type (void_type_node, void_list_node);
21850 tree void_ftype_unsigned
21851 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
21852 tree void_ftype_unsigned_unsigned
21853 = build_function_type_list (void_type_node, unsigned_type_node,
21854 unsigned_type_node, NULL_TREE);
21855 tree void_ftype_pcvoid_unsigned_unsigned
21856 = build_function_type_list (void_type_node, const_ptr_type_node,
21857 unsigned_type_node, unsigned_type_node,
21859 tree unsigned_ftype_void
21860 = build_function_type (unsigned_type_node, void_list_node);
21861 tree v2si_ftype_v4sf
21862 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
21863 /* Loads/stores. */
21864 tree void_ftype_v8qi_v8qi_pchar
21865 = build_function_type_list (void_type_node,
21866 V8QI_type_node, V8QI_type_node,
21867 pchar_type_node, NULL_TREE);
21868 tree v4sf_ftype_pcfloat
21869 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
21870 tree v4sf_ftype_v4sf_pcv2sf
21871 = build_function_type_list (V4SF_type_node,
21872 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
21873 tree void_ftype_pv2sf_v4sf
21874 = build_function_type_list (void_type_node,
21875 pv2sf_type_node, V4SF_type_node, NULL_TREE);
21876 tree void_ftype_pfloat_v4sf
21877 = build_function_type_list (void_type_node,
21878 pfloat_type_node, V4SF_type_node, NULL_TREE);
21879 tree void_ftype_pdi_di
21880 = build_function_type_list (void_type_node,
21881 pdi_type_node, long_long_unsigned_type_node,
21883 tree void_ftype_pv2di_v2di
21884 = build_function_type_list (void_type_node,
21885 pv2di_type_node, V2DI_type_node, NULL_TREE);
21886 /* Normal vector unops. */
21887 tree v4sf_ftype_v4sf
21888 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
21889 tree v16qi_ftype_v16qi
21890 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
21891 tree v8hi_ftype_v8hi
21892 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
21893 tree v4si_ftype_v4si
21894 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
21895 tree v8qi_ftype_v8qi
21896 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
21897 tree v4hi_ftype_v4hi
21898 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
21900 /* Normal vector binops. */
21901 tree v4sf_ftype_v4sf_v4sf
21902 = build_function_type_list (V4SF_type_node,
21903 V4SF_type_node, V4SF_type_node, NULL_TREE);
21904 tree v8qi_ftype_v8qi_v8qi
21905 = build_function_type_list (V8QI_type_node,
21906 V8QI_type_node, V8QI_type_node, NULL_TREE);
21907 tree v4hi_ftype_v4hi_v4hi
21908 = build_function_type_list (V4HI_type_node,
21909 V4HI_type_node, V4HI_type_node, NULL_TREE);
21910 tree v2si_ftype_v2si_v2si
21911 = build_function_type_list (V2SI_type_node,
21912 V2SI_type_node, V2SI_type_node, NULL_TREE);
21913 tree v1di_ftype_v1di_v1di
21914 = build_function_type_list (V1DI_type_node,
21915 V1DI_type_node, V1DI_type_node, NULL_TREE);
21916 tree v1di_ftype_v1di_v1di_int
21917 = build_function_type_list (V1DI_type_node,
21918 V1DI_type_node, V1DI_type_node,
21919 integer_type_node, NULL_TREE);
21920 tree v2si_ftype_v2sf
21921 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
21922 tree v2sf_ftype_v2si
21923 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
21924 tree v2si_ftype_v2si
21925 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
21926 tree v2sf_ftype_v2sf
21927 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
21928 tree v2sf_ftype_v2sf_v2sf
21929 = build_function_type_list (V2SF_type_node,
21930 V2SF_type_node, V2SF_type_node, NULL_TREE);
21931 tree v2si_ftype_v2sf_v2sf
21932 = build_function_type_list (V2SI_type_node,
21933 V2SF_type_node, V2SF_type_node, NULL_TREE);
21934 tree pint_type_node = build_pointer_type (integer_type_node);
21935 tree pdouble_type_node = build_pointer_type (double_type_node);
21936 tree pcdouble_type_node = build_pointer_type (
21937 build_type_variant (double_type_node, 1, 0));
21938 tree int_ftype_v2df_v2df
21939 = build_function_type_list (integer_type_node,
21940 V2DF_type_node, V2DF_type_node, NULL_TREE);
21942 tree void_ftype_pcvoid
21943 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
21944 tree v4sf_ftype_v4si
21945 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
21946 tree v4si_ftype_v4sf
21947 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
21948 tree v2df_ftype_v4si
21949 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
21950 tree v4si_ftype_v2df
21951 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
21952 tree v4si_ftype_v2df_v2df
21953 = build_function_type_list (V4SI_type_node,
21954 V2DF_type_node, V2DF_type_node, NULL_TREE);
21955 tree v2si_ftype_v2df
21956 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
21957 tree v4sf_ftype_v2df
21958 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
21959 tree v2df_ftype_v2si
21960 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
21961 tree v2df_ftype_v4sf
21962 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
21963 tree int_ftype_v2df
21964 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
21965 tree int64_ftype_v2df
21966 = build_function_type_list (long_long_integer_type_node,
21967 V2DF_type_node, NULL_TREE);
21968 tree v2df_ftype_v2df_int
21969 = build_function_type_list (V2DF_type_node,
21970 V2DF_type_node, integer_type_node, NULL_TREE);
21971 tree v2df_ftype_v2df_int64
21972 = build_function_type_list (V2DF_type_node,
21973 V2DF_type_node, long_long_integer_type_node,
21975 tree v4sf_ftype_v4sf_v2df
21976 = build_function_type_list (V4SF_type_node,
21977 V4SF_type_node, V2DF_type_node, NULL_TREE);
21978 tree v2df_ftype_v2df_v4sf
21979 = build_function_type_list (V2DF_type_node,
21980 V2DF_type_node, V4SF_type_node, NULL_TREE);
21981 tree v2df_ftype_v2df_v2df_int
21982 = build_function_type_list (V2DF_type_node,
21983 V2DF_type_node, V2DF_type_node,
21986 tree v2df_ftype_v2df_pcdouble
21987 = build_function_type_list (V2DF_type_node,
21988 V2DF_type_node, pcdouble_type_node, NULL_TREE);
21989 tree void_ftype_pdouble_v2df
21990 = build_function_type_list (void_type_node,
21991 pdouble_type_node, V2DF_type_node, NULL_TREE);
21992 tree void_ftype_pint_int
21993 = build_function_type_list (void_type_node,
21994 pint_type_node, integer_type_node, NULL_TREE);
21995 tree void_ftype_v16qi_v16qi_pchar
21996 = build_function_type_list (void_type_node,
21997 V16QI_type_node, V16QI_type_node,
21998 pchar_type_node, NULL_TREE);
21999 tree v2df_ftype_pcdouble
22000 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22001 tree v2df_ftype_v2df_v2df
22002 = build_function_type_list (V2DF_type_node,
22003 V2DF_type_node, V2DF_type_node, NULL_TREE);
22004 tree v16qi_ftype_v16qi_v16qi
22005 = build_function_type_list (V16QI_type_node,
22006 V16QI_type_node, V16QI_type_node, NULL_TREE);
22007 tree v8hi_ftype_v8hi_v8hi
22008 = build_function_type_list (V8HI_type_node,
22009 V8HI_type_node, V8HI_type_node, NULL_TREE);
22010 tree v4si_ftype_v4si_v4si
22011 = build_function_type_list (V4SI_type_node,
22012 V4SI_type_node, V4SI_type_node, NULL_TREE);
22013 tree v2di_ftype_v2di_v2di
22014 = build_function_type_list (V2DI_type_node,
22015 V2DI_type_node, V2DI_type_node, NULL_TREE);
22016 tree v2di_ftype_v2df_v2df
22017 = build_function_type_list (V2DI_type_node,
22018 V2DF_type_node, V2DF_type_node, NULL_TREE);
22019 tree v2df_ftype_v2df
22020 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22021 tree v2di_ftype_v2di_int
22022 = build_function_type_list (V2DI_type_node,
22023 V2DI_type_node, integer_type_node, NULL_TREE);
22024 tree v2di_ftype_v2di_v2di_int
22025 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22026 V2DI_type_node, integer_type_node, NULL_TREE);
22027 tree v4si_ftype_v4si_int
22028 = build_function_type_list (V4SI_type_node,
22029 V4SI_type_node, integer_type_node, NULL_TREE);
22030 tree v8hi_ftype_v8hi_int
22031 = build_function_type_list (V8HI_type_node,
22032 V8HI_type_node, integer_type_node, NULL_TREE);
22033 tree v4si_ftype_v8hi_v8hi
22034 = build_function_type_list (V4SI_type_node,
22035 V8HI_type_node, V8HI_type_node, NULL_TREE);
22036 tree v1di_ftype_v8qi_v8qi
22037 = build_function_type_list (V1DI_type_node,
22038 V8QI_type_node, V8QI_type_node, NULL_TREE);
22039 tree v1di_ftype_v2si_v2si
22040 = build_function_type_list (V1DI_type_node,
22041 V2SI_type_node, V2SI_type_node, NULL_TREE);
22042 tree v2di_ftype_v16qi_v16qi
22043 = build_function_type_list (V2DI_type_node,
22044 V16QI_type_node, V16QI_type_node, NULL_TREE);
22045 tree v2di_ftype_v4si_v4si
22046 = build_function_type_list (V2DI_type_node,
22047 V4SI_type_node, V4SI_type_node, NULL_TREE);
22048 tree int_ftype_v16qi
22049 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22050 tree v16qi_ftype_pcchar
22051 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22052 tree void_ftype_pchar_v16qi
22053 = build_function_type_list (void_type_node,
22054 pchar_type_node, V16QI_type_node, NULL_TREE);
22056 tree v2di_ftype_v2di_unsigned_unsigned
22057 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22058 unsigned_type_node, unsigned_type_node,
22060 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22061 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22062 unsigned_type_node, unsigned_type_node,
22064 tree v2di_ftype_v2di_v16qi
22065 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22067 tree v2df_ftype_v2df_v2df_v2df
22068 = build_function_type_list (V2DF_type_node,
22069 V2DF_type_node, V2DF_type_node,
22070 V2DF_type_node, NULL_TREE);
22071 tree v4sf_ftype_v4sf_v4sf_v4sf
22072 = build_function_type_list (V4SF_type_node,
22073 V4SF_type_node, V4SF_type_node,
22074 V4SF_type_node, NULL_TREE);
22075 tree v8hi_ftype_v16qi
22076 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22078 tree v4si_ftype_v16qi
22079 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22081 tree v2di_ftype_v16qi
22082 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22084 tree v4si_ftype_v8hi
22085 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22087 tree v2di_ftype_v8hi
22088 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22090 tree v2di_ftype_v4si
22091 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22093 tree v2di_ftype_pv2di
22094 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22096 tree v16qi_ftype_v16qi_v16qi_int
22097 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22098 V16QI_type_node, integer_type_node,
22100 tree v16qi_ftype_v16qi_v16qi_v16qi
22101 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22102 V16QI_type_node, V16QI_type_node,
22104 tree v8hi_ftype_v8hi_v8hi_int
22105 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22106 V8HI_type_node, integer_type_node,
22108 tree v4si_ftype_v4si_v4si_int
22109 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22110 V4SI_type_node, integer_type_node,
22112 tree int_ftype_v2di_v2di
22113 = build_function_type_list (integer_type_node,
22114 V2DI_type_node, V2DI_type_node,
22116 tree int_ftype_v16qi_int_v16qi_int_int
22117 = build_function_type_list (integer_type_node,
22124 tree v16qi_ftype_v16qi_int_v16qi_int_int
22125 = build_function_type_list (V16QI_type_node,
22132 tree int_ftype_v16qi_v16qi_int
22133 = build_function_type_list (integer_type_node,
22139 /* SSE5 instructions */
22140 tree v2di_ftype_v2di_v2di_v2di
22141 = build_function_type_list (V2DI_type_node,
22147 tree v4si_ftype_v4si_v4si_v4si
22148 = build_function_type_list (V4SI_type_node,
22154 tree v4si_ftype_v4si_v4si_v2di
22155 = build_function_type_list (V4SI_type_node,
22161 tree v8hi_ftype_v8hi_v8hi_v8hi
22162 = build_function_type_list (V8HI_type_node,
22168 tree v8hi_ftype_v8hi_v8hi_v4si
22169 = build_function_type_list (V8HI_type_node,
22175 tree v2df_ftype_v2df_v2df_v16qi
22176 = build_function_type_list (V2DF_type_node,
22182 tree v4sf_ftype_v4sf_v4sf_v16qi
22183 = build_function_type_list (V4SF_type_node,
22189 tree v2di_ftype_v2di_si
22190 = build_function_type_list (V2DI_type_node,
22195 tree v4si_ftype_v4si_si
22196 = build_function_type_list (V4SI_type_node,
22201 tree v8hi_ftype_v8hi_si
22202 = build_function_type_list (V8HI_type_node,
22207 tree v16qi_ftype_v16qi_si
22208 = build_function_type_list (V16QI_type_node,
22212 tree v4sf_ftype_v4hi
22213 = build_function_type_list (V4SF_type_node,
22217 tree v4hi_ftype_v4sf
22218 = build_function_type_list (V4HI_type_node,
22222 tree v2di_ftype_v2di
22223 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22225 tree v16qi_ftype_v8hi_v8hi
22226 = build_function_type_list (V16QI_type_node,
22227 V8HI_type_node, V8HI_type_node,
22229 tree v8hi_ftype_v4si_v4si
22230 = build_function_type_list (V8HI_type_node,
22231 V4SI_type_node, V4SI_type_node,
22233 tree v8hi_ftype_v16qi_v16qi
22234 = build_function_type_list (V8HI_type_node,
22235 V16QI_type_node, V16QI_type_node,
22237 tree v4hi_ftype_v8qi_v8qi
22238 = build_function_type_list (V4HI_type_node,
22239 V8QI_type_node, V8QI_type_node,
22241 tree unsigned_ftype_unsigned_uchar
22242 = build_function_type_list (unsigned_type_node,
22243 unsigned_type_node,
22244 unsigned_char_type_node,
22246 tree unsigned_ftype_unsigned_ushort
22247 = build_function_type_list (unsigned_type_node,
22248 unsigned_type_node,
22249 short_unsigned_type_node,
22251 tree unsigned_ftype_unsigned_unsigned
22252 = build_function_type_list (unsigned_type_node,
22253 unsigned_type_node,
22254 unsigned_type_node,
22256 tree uint64_ftype_uint64_uint64
22257 = build_function_type_list (long_long_unsigned_type_node,
22258 long_long_unsigned_type_node,
22259 long_long_unsigned_type_node,
22261 tree float_ftype_float
22262 = build_function_type_list (float_type_node,
22267 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22269 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22271 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22273 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22275 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22277 tree v8sf_ftype_v8sf
22278 = build_function_type_list (V8SF_type_node,
22281 tree v8si_ftype_v8sf
22282 = build_function_type_list (V8SI_type_node,
22285 tree v8sf_ftype_v8si
22286 = build_function_type_list (V8SF_type_node,
22289 tree v4si_ftype_v4df
22290 = build_function_type_list (V4SI_type_node,
22293 tree v4df_ftype_v4df
22294 = build_function_type_list (V4DF_type_node,
22297 tree v4df_ftype_v4si
22298 = build_function_type_list (V4DF_type_node,
22301 tree v4df_ftype_v4sf
22302 = build_function_type_list (V4DF_type_node,
22305 tree v4sf_ftype_v4df
22306 = build_function_type_list (V4SF_type_node,
22309 tree v8sf_ftype_v8sf_v8sf
22310 = build_function_type_list (V8SF_type_node,
22311 V8SF_type_node, V8SF_type_node,
22313 tree v4df_ftype_v4df_v4df
22314 = build_function_type_list (V4DF_type_node,
22315 V4DF_type_node, V4DF_type_node,
22317 tree v8sf_ftype_v8sf_int
22318 = build_function_type_list (V8SF_type_node,
22319 V8SF_type_node, integer_type_node,
22321 tree v4si_ftype_v8si_int
22322 = build_function_type_list (V4SI_type_node,
22323 V8SI_type_node, integer_type_node,
22325 tree v4df_ftype_v4df_int
22326 = build_function_type_list (V4DF_type_node,
22327 V4DF_type_node, integer_type_node,
22329 tree v4sf_ftype_v8sf_int
22330 = build_function_type_list (V4SF_type_node,
22331 V8SF_type_node, integer_type_node,
22333 tree v2df_ftype_v4df_int
22334 = build_function_type_list (V2DF_type_node,
22335 V4DF_type_node, integer_type_node,
22337 tree v8sf_ftype_v8sf_v8sf_int
22338 = build_function_type_list (V8SF_type_node,
22339 V8SF_type_node, V8SF_type_node,
22342 tree v8sf_ftype_v8sf_v8sf_v8sf
22343 = build_function_type_list (V8SF_type_node,
22344 V8SF_type_node, V8SF_type_node,
22347 tree v4df_ftype_v4df_v4df_v4df
22348 = build_function_type_list (V4DF_type_node,
22349 V4DF_type_node, V4DF_type_node,
22352 tree v8si_ftype_v8si_v8si_int
22353 = build_function_type_list (V8SI_type_node,
22354 V8SI_type_node, V8SI_type_node,
22357 tree v4df_ftype_v4df_v4df_int
22358 = build_function_type_list (V4DF_type_node,
22359 V4DF_type_node, V4DF_type_node,
22362 tree v8sf_ftype_pcfloat
22363 = build_function_type_list (V8SF_type_node,
22366 tree v4df_ftype_pcdouble
22367 = build_function_type_list (V4DF_type_node,
22368 pcdouble_type_node,
22370 tree pcv4sf_type_node
22371 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22372 tree pcv2df_type_node
22373 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22374 tree v8sf_ftype_pcv4sf
22375 = build_function_type_list (V8SF_type_node,
22378 tree v4df_ftype_pcv2df
22379 = build_function_type_list (V4DF_type_node,
22382 tree v32qi_ftype_pcchar
22383 = build_function_type_list (V32QI_type_node,
22386 tree void_ftype_pchar_v32qi
22387 = build_function_type_list (void_type_node,
22388 pchar_type_node, V32QI_type_node,
22390 tree v8si_ftype_v8si_v4si_int
22391 = build_function_type_list (V8SI_type_node,
22392 V8SI_type_node, V4SI_type_node,
22395 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22396 tree void_ftype_pv4di_v4di
22397 = build_function_type_list (void_type_node,
22398 pv4di_type_node, V4DI_type_node,
22400 tree v8sf_ftype_v8sf_v4sf_int
22401 = build_function_type_list (V8SF_type_node,
22402 V8SF_type_node, V4SF_type_node,
22405 tree v4df_ftype_v4df_v2df_int
22406 = build_function_type_list (V4DF_type_node,
22407 V4DF_type_node, V2DF_type_node,
22410 tree void_ftype_pfloat_v8sf
22411 = build_function_type_list (void_type_node,
22412 pfloat_type_node, V8SF_type_node,
22414 tree void_ftype_pdouble_v4df
22415 = build_function_type_list (void_type_node,
22416 pdouble_type_node, V4DF_type_node,
22418 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22419 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22420 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22421 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22422 tree pcv8sf_type_node
22423 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22424 tree pcv4df_type_node
22425 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22426 tree v8sf_ftype_pcv8sf_v8sf
22427 = build_function_type_list (V8SF_type_node,
22428 pcv8sf_type_node, V8SF_type_node,
22430 tree v4df_ftype_pcv4df_v4df
22431 = build_function_type_list (V4DF_type_node,
22432 pcv4df_type_node, V4DF_type_node,
22434 tree v4sf_ftype_pcv4sf_v4sf
22435 = build_function_type_list (V4SF_type_node,
22436 pcv4sf_type_node, V4SF_type_node,
22438 tree v2df_ftype_pcv2df_v2df
22439 = build_function_type_list (V2DF_type_node,
22440 pcv2df_type_node, V2DF_type_node,
22442 tree void_ftype_pv8sf_v8sf_v8sf
22443 = build_function_type_list (void_type_node,
22444 pv8sf_type_node, V8SF_type_node,
22447 tree void_ftype_pv4df_v4df_v4df
22448 = build_function_type_list (void_type_node,
22449 pv4df_type_node, V4DF_type_node,
22452 tree void_ftype_pv4sf_v4sf_v4sf
22453 = build_function_type_list (void_type_node,
22454 pv4sf_type_node, V4SF_type_node,
22457 tree void_ftype_pv2df_v2df_v2df
22458 = build_function_type_list (void_type_node,
22459 pv2df_type_node, V2DF_type_node,
22462 tree v4df_ftype_v2df
22463 = build_function_type_list (V4DF_type_node,
22466 tree v8sf_ftype_v4sf
22467 = build_function_type_list (V8SF_type_node,
22470 tree v8si_ftype_v4si
22471 = build_function_type_list (V8SI_type_node,
22474 tree v2df_ftype_v4df
22475 = build_function_type_list (V2DF_type_node,
22478 tree v4sf_ftype_v8sf
22479 = build_function_type_list (V4SF_type_node,
22482 tree v4si_ftype_v8si
22483 = build_function_type_list (V4SI_type_node,
22486 tree int_ftype_v4df
22487 = build_function_type_list (integer_type_node,
22490 tree int_ftype_v8sf
22491 = build_function_type_list (integer_type_node,
22494 tree int_ftype_v8sf_v8sf
22495 = build_function_type_list (integer_type_node,
22496 V8SF_type_node, V8SF_type_node,
22498 tree int_ftype_v4di_v4di
22499 = build_function_type_list (integer_type_node,
22500 V4DI_type_node, V4DI_type_node,
22502 tree int_ftype_v4df_v4df
22503 = build_function_type_list (integer_type_node,
22504 V4DF_type_node, V4DF_type_node,
22506 tree v8sf_ftype_v8sf_v8si
22507 = build_function_type_list (V8SF_type_node,
22508 V8SF_type_node, V8SI_type_node,
22510 tree v4df_ftype_v4df_v4di
22511 = build_function_type_list (V4DF_type_node,
22512 V4DF_type_node, V4DI_type_node,
22514 tree v4sf_ftype_v4sf_v4si
22515 = build_function_type_list (V4SF_type_node,
22516 V4SF_type_node, V4SI_type_node, NULL_TREE);
22517 tree v2df_ftype_v2df_v2di
22518 = build_function_type_list (V2DF_type_node,
22519 V2DF_type_node, V2DI_type_node, NULL_TREE);
22523 /* Add all special builtins with variable number of operands. */
22524 for (i = 0, d = bdesc_special_args;
22525 i < ARRAY_SIZE (bdesc_special_args);
22533 switch ((enum ix86_special_builtin_type) d->flag)
22535 case VOID_FTYPE_VOID:
22536 type = void_ftype_void;
22538 case V32QI_FTYPE_PCCHAR:
22539 type = v32qi_ftype_pcchar;
22541 case V16QI_FTYPE_PCCHAR:
22542 type = v16qi_ftype_pcchar;
22544 case V8SF_FTYPE_PCV4SF:
22545 type = v8sf_ftype_pcv4sf;
22547 case V8SF_FTYPE_PCFLOAT:
22548 type = v8sf_ftype_pcfloat;
22550 case V4DF_FTYPE_PCV2DF:
22551 type = v4df_ftype_pcv2df;
22553 case V4DF_FTYPE_PCDOUBLE:
22554 type = v4df_ftype_pcdouble;
22556 case V4SF_FTYPE_PCFLOAT:
22557 type = v4sf_ftype_pcfloat;
22559 case V2DI_FTYPE_PV2DI:
22560 type = v2di_ftype_pv2di;
22562 case V2DF_FTYPE_PCDOUBLE:
22563 type = v2df_ftype_pcdouble;
22565 case V8SF_FTYPE_PCV8SF_V8SF:
22566 type = v8sf_ftype_pcv8sf_v8sf;
22568 case V4DF_FTYPE_PCV4DF_V4DF:
22569 type = v4df_ftype_pcv4df_v4df;
22571 case V4SF_FTYPE_V4SF_PCV2SF:
22572 type = v4sf_ftype_v4sf_pcv2sf;
22574 case V4SF_FTYPE_PCV4SF_V4SF:
22575 type = v4sf_ftype_pcv4sf_v4sf;
22577 case V2DF_FTYPE_V2DF_PCDOUBLE:
22578 type = v2df_ftype_v2df_pcdouble;
22580 case V2DF_FTYPE_PCV2DF_V2DF:
22581 type = v2df_ftype_pcv2df_v2df;
22583 case VOID_FTYPE_PV2SF_V4SF:
22584 type = void_ftype_pv2sf_v4sf;
22586 case VOID_FTYPE_PV4DI_V4DI:
22587 type = void_ftype_pv4di_v4di;
22589 case VOID_FTYPE_PV2DI_V2DI:
22590 type = void_ftype_pv2di_v2di;
22592 case VOID_FTYPE_PCHAR_V32QI:
22593 type = void_ftype_pchar_v32qi;
22595 case VOID_FTYPE_PCHAR_V16QI:
22596 type = void_ftype_pchar_v16qi;
22598 case VOID_FTYPE_PFLOAT_V8SF:
22599 type = void_ftype_pfloat_v8sf;
22601 case VOID_FTYPE_PFLOAT_V4SF:
22602 type = void_ftype_pfloat_v4sf;
22604 case VOID_FTYPE_PDOUBLE_V4DF:
22605 type = void_ftype_pdouble_v4df;
22607 case VOID_FTYPE_PDOUBLE_V2DF:
22608 type = void_ftype_pdouble_v2df;
22610 case VOID_FTYPE_PDI_DI:
22611 type = void_ftype_pdi_di;
22613 case VOID_FTYPE_PINT_INT:
22614 type = void_ftype_pint_int;
22616 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22617 type = void_ftype_pv8sf_v8sf_v8sf;
22619 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22620 type = void_ftype_pv4df_v4df_v4df;
22622 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22623 type = void_ftype_pv4sf_v4sf_v4sf;
22625 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22626 type = void_ftype_pv2df_v2df_v2df;
22629 gcc_unreachable ();
22632 def_builtin (d->mask, d->name, type, d->code);
22635 /* Add all builtins with variable number of operands. */
22636 for (i = 0, d = bdesc_args;
22637 i < ARRAY_SIZE (bdesc_args);
22645 switch ((enum ix86_builtin_type) d->flag)
22647 case FLOAT_FTYPE_FLOAT:
22648 type = float_ftype_float;
22650 case INT_FTYPE_V8SF_V8SF_PTEST:
22651 type = int_ftype_v8sf_v8sf;
22653 case INT_FTYPE_V4DI_V4DI_PTEST:
22654 type = int_ftype_v4di_v4di;
22656 case INT_FTYPE_V4DF_V4DF_PTEST:
22657 type = int_ftype_v4df_v4df;
22659 case INT_FTYPE_V4SF_V4SF_PTEST:
22660 type = int_ftype_v4sf_v4sf;
22662 case INT_FTYPE_V2DI_V2DI_PTEST:
22663 type = int_ftype_v2di_v2di;
22665 case INT_FTYPE_V2DF_V2DF_PTEST:
22666 type = int_ftype_v2df_v2df;
22668 case INT64_FTYPE_V4SF:
22669 type = int64_ftype_v4sf;
22671 case INT64_FTYPE_V2DF:
22672 type = int64_ftype_v2df;
22674 case INT_FTYPE_V16QI:
22675 type = int_ftype_v16qi;
22677 case INT_FTYPE_V8QI:
22678 type = int_ftype_v8qi;
22680 case INT_FTYPE_V8SF:
22681 type = int_ftype_v8sf;
22683 case INT_FTYPE_V4DF:
22684 type = int_ftype_v4df;
22686 case INT_FTYPE_V4SF:
22687 type = int_ftype_v4sf;
22689 case INT_FTYPE_V2DF:
22690 type = int_ftype_v2df;
22692 case V16QI_FTYPE_V16QI:
22693 type = v16qi_ftype_v16qi;
22695 case V8SI_FTYPE_V8SF:
22696 type = v8si_ftype_v8sf;
22698 case V8SI_FTYPE_V4SI:
22699 type = v8si_ftype_v4si;
22701 case V8HI_FTYPE_V8HI:
22702 type = v8hi_ftype_v8hi;
22704 case V8HI_FTYPE_V16QI:
22705 type = v8hi_ftype_v16qi;
22707 case V8QI_FTYPE_V8QI:
22708 type = v8qi_ftype_v8qi;
22710 case V8SF_FTYPE_V8SF:
22711 type = v8sf_ftype_v8sf;
22713 case V8SF_FTYPE_V8SI:
22714 type = v8sf_ftype_v8si;
22716 case V8SF_FTYPE_V4SF:
22717 type = v8sf_ftype_v4sf;
22719 case V4SI_FTYPE_V4DF:
22720 type = v4si_ftype_v4df;
22722 case V4SI_FTYPE_V4SI:
22723 type = v4si_ftype_v4si;
22725 case V4SI_FTYPE_V16QI:
22726 type = v4si_ftype_v16qi;
22728 case V4SI_FTYPE_V8SI:
22729 type = v4si_ftype_v8si;
22731 case V4SI_FTYPE_V8HI:
22732 type = v4si_ftype_v8hi;
22734 case V4SI_FTYPE_V4SF:
22735 type = v4si_ftype_v4sf;
22737 case V4SI_FTYPE_V2DF:
22738 type = v4si_ftype_v2df;
22740 case V4HI_FTYPE_V4HI:
22741 type = v4hi_ftype_v4hi;
22743 case V4DF_FTYPE_V4DF:
22744 type = v4df_ftype_v4df;
22746 case V4DF_FTYPE_V4SI:
22747 type = v4df_ftype_v4si;
22749 case V4DF_FTYPE_V4SF:
22750 type = v4df_ftype_v4sf;
22752 case V4DF_FTYPE_V2DF:
22753 type = v4df_ftype_v2df;
22755 case V4SF_FTYPE_V4SF:
22756 case V4SF_FTYPE_V4SF_VEC_MERGE:
22757 type = v4sf_ftype_v4sf;
22759 case V4SF_FTYPE_V8SF:
22760 type = v4sf_ftype_v8sf;
22762 case V4SF_FTYPE_V4SI:
22763 type = v4sf_ftype_v4si;
22765 case V4SF_FTYPE_V4DF:
22766 type = v4sf_ftype_v4df;
22768 case V4SF_FTYPE_V2DF:
22769 type = v4sf_ftype_v2df;
22771 case V2DI_FTYPE_V2DI:
22772 type = v2di_ftype_v2di;
22774 case V2DI_FTYPE_V16QI:
22775 type = v2di_ftype_v16qi;
22777 case V2DI_FTYPE_V8HI:
22778 type = v2di_ftype_v8hi;
22780 case V2DI_FTYPE_V4SI:
22781 type = v2di_ftype_v4si;
22783 case V2SI_FTYPE_V2SI:
22784 type = v2si_ftype_v2si;
22786 case V2SI_FTYPE_V4SF:
22787 type = v2si_ftype_v4sf;
22789 case V2SI_FTYPE_V2DF:
22790 type = v2si_ftype_v2df;
22792 case V2SI_FTYPE_V2SF:
22793 type = v2si_ftype_v2sf;
22795 case V2DF_FTYPE_V4DF:
22796 type = v2df_ftype_v4df;
22798 case V2DF_FTYPE_V4SF:
22799 type = v2df_ftype_v4sf;
22801 case V2DF_FTYPE_V2DF:
22802 case V2DF_FTYPE_V2DF_VEC_MERGE:
22803 type = v2df_ftype_v2df;
22805 case V2DF_FTYPE_V2SI:
22806 type = v2df_ftype_v2si;
22808 case V2DF_FTYPE_V4SI:
22809 type = v2df_ftype_v4si;
22811 case V2SF_FTYPE_V2SF:
22812 type = v2sf_ftype_v2sf;
22814 case V2SF_FTYPE_V2SI:
22815 type = v2sf_ftype_v2si;
22817 case V16QI_FTYPE_V16QI_V16QI:
22818 type = v16qi_ftype_v16qi_v16qi;
22820 case V16QI_FTYPE_V8HI_V8HI:
22821 type = v16qi_ftype_v8hi_v8hi;
22823 case V8QI_FTYPE_V8QI_V8QI:
22824 type = v8qi_ftype_v8qi_v8qi;
22826 case V8QI_FTYPE_V4HI_V4HI:
22827 type = v8qi_ftype_v4hi_v4hi;
22829 case V8HI_FTYPE_V8HI_V8HI:
22830 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22831 type = v8hi_ftype_v8hi_v8hi;
22833 case V8HI_FTYPE_V16QI_V16QI:
22834 type = v8hi_ftype_v16qi_v16qi;
22836 case V8HI_FTYPE_V4SI_V4SI:
22837 type = v8hi_ftype_v4si_v4si;
22839 case V8HI_FTYPE_V8HI_SI_COUNT:
22840 type = v8hi_ftype_v8hi_int;
22842 case V8SF_FTYPE_V8SF_V8SF:
22843 type = v8sf_ftype_v8sf_v8sf;
22845 case V8SF_FTYPE_V8SF_V8SI:
22846 type = v8sf_ftype_v8sf_v8si;
22848 case V4SI_FTYPE_V4SI_V4SI:
22849 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22850 type = v4si_ftype_v4si_v4si;
22852 case V4SI_FTYPE_V8HI_V8HI:
22853 type = v4si_ftype_v8hi_v8hi;
22855 case V4SI_FTYPE_V4SF_V4SF:
22856 type = v4si_ftype_v4sf_v4sf;
22858 case V4SI_FTYPE_V2DF_V2DF:
22859 type = v4si_ftype_v2df_v2df;
22861 case V4SI_FTYPE_V4SI_SI_COUNT:
22862 type = v4si_ftype_v4si_int;
22864 case V4HI_FTYPE_V4HI_V4HI:
22865 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22866 type = v4hi_ftype_v4hi_v4hi;
22868 case V4HI_FTYPE_V8QI_V8QI:
22869 type = v4hi_ftype_v8qi_v8qi;
22871 case V4HI_FTYPE_V2SI_V2SI:
22872 type = v4hi_ftype_v2si_v2si;
22874 case V4HI_FTYPE_V4HI_SI_COUNT:
22875 type = v4hi_ftype_v4hi_int;
22877 case V4DF_FTYPE_V4DF_V4DF:
22878 type = v4df_ftype_v4df_v4df;
22880 case V4DF_FTYPE_V4DF_V4DI:
22881 type = v4df_ftype_v4df_v4di;
22883 case V4SF_FTYPE_V4SF_V4SF:
22884 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22885 type = v4sf_ftype_v4sf_v4sf;
22887 case V4SF_FTYPE_V4SF_V4SI:
22888 type = v4sf_ftype_v4sf_v4si;
22890 case V4SF_FTYPE_V4SF_V2SI:
22891 type = v4sf_ftype_v4sf_v2si;
22893 case V4SF_FTYPE_V4SF_V2DF:
22894 type = v4sf_ftype_v4sf_v2df;
22896 case V4SF_FTYPE_V4SF_DI:
22897 type = v4sf_ftype_v4sf_int64;
22899 case V4SF_FTYPE_V4SF_SI:
22900 type = v4sf_ftype_v4sf_int;
22902 case V2DI_FTYPE_V2DI_V2DI:
22903 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22904 type = v2di_ftype_v2di_v2di;
22906 case V2DI_FTYPE_V16QI_V16QI:
22907 type = v2di_ftype_v16qi_v16qi;
22909 case V2DI_FTYPE_V4SI_V4SI:
22910 type = v2di_ftype_v4si_v4si;
22912 case V2DI_FTYPE_V2DI_V16QI:
22913 type = v2di_ftype_v2di_v16qi;
22915 case V2DI_FTYPE_V2DF_V2DF:
22916 type = v2di_ftype_v2df_v2df;
22918 case V2DI_FTYPE_V2DI_SI_COUNT:
22919 type = v2di_ftype_v2di_int;
22921 case V2SI_FTYPE_V2SI_V2SI:
22922 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22923 type = v2si_ftype_v2si_v2si;
22925 case V2SI_FTYPE_V4HI_V4HI:
22926 type = v2si_ftype_v4hi_v4hi;
22928 case V2SI_FTYPE_V2SF_V2SF:
22929 type = v2si_ftype_v2sf_v2sf;
22931 case V2SI_FTYPE_V2SI_SI_COUNT:
22932 type = v2si_ftype_v2si_int;
22934 case V2DF_FTYPE_V2DF_V2DF:
22935 case V2DF_FTYPE_V2DF_V2DF_SWAP:
22936 type = v2df_ftype_v2df_v2df;
22938 case V2DF_FTYPE_V2DF_V4SF:
22939 type = v2df_ftype_v2df_v4sf;
22941 case V2DF_FTYPE_V2DF_V2DI:
22942 type = v2df_ftype_v2df_v2di;
22944 case V2DF_FTYPE_V2DF_DI:
22945 type = v2df_ftype_v2df_int64;
22947 case V2DF_FTYPE_V2DF_SI:
22948 type = v2df_ftype_v2df_int;
22950 case V2SF_FTYPE_V2SF_V2SF:
22951 type = v2sf_ftype_v2sf_v2sf;
22953 case V1DI_FTYPE_V1DI_V1DI:
22954 case V1DI_FTYPE_V1DI_V1DI_COUNT:
22955 type = v1di_ftype_v1di_v1di;
22957 case V1DI_FTYPE_V8QI_V8QI:
22958 type = v1di_ftype_v8qi_v8qi;
22960 case V1DI_FTYPE_V2SI_V2SI:
22961 type = v1di_ftype_v2si_v2si;
22963 case V1DI_FTYPE_V1DI_SI_COUNT:
22964 type = v1di_ftype_v1di_int;
22966 case UINT64_FTYPE_UINT64_UINT64:
22967 type = uint64_ftype_uint64_uint64;
22969 case UINT_FTYPE_UINT_UINT:
22970 type = unsigned_ftype_unsigned_unsigned;
22972 case UINT_FTYPE_UINT_USHORT:
22973 type = unsigned_ftype_unsigned_ushort;
22975 case UINT_FTYPE_UINT_UCHAR:
22976 type = unsigned_ftype_unsigned_uchar;
22978 case V8HI_FTYPE_V8HI_INT:
22979 type = v8hi_ftype_v8hi_int;
22981 case V8SF_FTYPE_V8SF_INT:
22982 type = v8sf_ftype_v8sf_int;
22984 case V4SI_FTYPE_V4SI_INT:
22985 type = v4si_ftype_v4si_int;
22987 case V4SI_FTYPE_V8SI_INT:
22988 type = v4si_ftype_v8si_int;
22990 case V4HI_FTYPE_V4HI_INT:
22991 type = v4hi_ftype_v4hi_int;
22993 case V4DF_FTYPE_V4DF_INT:
22994 type = v4df_ftype_v4df_int;
22996 case V4SF_FTYPE_V4SF_INT:
22997 type = v4sf_ftype_v4sf_int;
22999 case V4SF_FTYPE_V8SF_INT:
23000 type = v4sf_ftype_v8sf_int;
23002 case V2DI_FTYPE_V2DI_INT:
23003 case V2DI2TI_FTYPE_V2DI_INT:
23004 type = v2di_ftype_v2di_int;
23006 case V2DF_FTYPE_V2DF_INT:
23007 type = v2df_ftype_v2df_int;
23009 case V2DF_FTYPE_V4DF_INT:
23010 type = v2df_ftype_v4df_int;
23012 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23013 type = v16qi_ftype_v16qi_v16qi_v16qi;
23015 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23016 type = v8sf_ftype_v8sf_v8sf_v8sf;
23018 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23019 type = v4df_ftype_v4df_v4df_v4df;
23021 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23022 type = v4sf_ftype_v4sf_v4sf_v4sf;
23024 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23025 type = v2df_ftype_v2df_v2df_v2df;
23027 case V16QI_FTYPE_V16QI_V16QI_INT:
23028 type = v16qi_ftype_v16qi_v16qi_int;
23030 case V8SI_FTYPE_V8SI_V8SI_INT:
23031 type = v8si_ftype_v8si_v8si_int;
23033 case V8SI_FTYPE_V8SI_V4SI_INT:
23034 type = v8si_ftype_v8si_v4si_int;
23036 case V8HI_FTYPE_V8HI_V8HI_INT:
23037 type = v8hi_ftype_v8hi_v8hi_int;
23039 case V8SF_FTYPE_V8SF_V8SF_INT:
23040 type = v8sf_ftype_v8sf_v8sf_int;
23042 case V8SF_FTYPE_V8SF_V4SF_INT:
23043 type = v8sf_ftype_v8sf_v4sf_int;
23045 case V4SI_FTYPE_V4SI_V4SI_INT:
23046 type = v4si_ftype_v4si_v4si_int;
23048 case V4DF_FTYPE_V4DF_V4DF_INT:
23049 type = v4df_ftype_v4df_v4df_int;
23051 case V4DF_FTYPE_V4DF_V2DF_INT:
23052 type = v4df_ftype_v4df_v2df_int;
23054 case V4SF_FTYPE_V4SF_V4SF_INT:
23055 type = v4sf_ftype_v4sf_v4sf_int;
23057 case V2DI_FTYPE_V2DI_V2DI_INT:
23058 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23059 type = v2di_ftype_v2di_v2di_int;
23061 case V2DF_FTYPE_V2DF_V2DF_INT:
23062 type = v2df_ftype_v2df_v2df_int;
23064 case V2DI_FTYPE_V2DI_UINT_UINT:
23065 type = v2di_ftype_v2di_unsigned_unsigned;
23067 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23068 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23070 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23071 type = v1di_ftype_v1di_v1di_int;
23074 gcc_unreachable ();
23077 def_builtin_const (d->mask, d->name, type, d->code);
23080 /* pcmpestr[im] insns. */
23081 for (i = 0, d = bdesc_pcmpestr;
23082 i < ARRAY_SIZE (bdesc_pcmpestr);
23085 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23086 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23088 ftype = int_ftype_v16qi_int_v16qi_int_int;
23089 def_builtin_const (d->mask, d->name, ftype, d->code);
23092 /* pcmpistr[im] insns. */
23093 for (i = 0, d = bdesc_pcmpistr;
23094 i < ARRAY_SIZE (bdesc_pcmpistr);
23097 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23098 ftype = v16qi_ftype_v16qi_v16qi_int;
23100 ftype = int_ftype_v16qi_v16qi_int;
23101 def_builtin_const (d->mask, d->name, ftype, d->code);
23104 /* comi/ucomi insns. */
23105 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23106 if (d->mask == OPTION_MASK_ISA_SSE2)
23107 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23109 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23112 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23113 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23115 /* SSE or 3DNow!A */
23116 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23119 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23121 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23122 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23125 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23126 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23129 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23130 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23131 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23132 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23133 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23134 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23137 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23140 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23141 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23143 /* Access to the vec_init patterns. */
23144 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23145 integer_type_node, NULL_TREE);
23146 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23148 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23149 short_integer_type_node,
23150 short_integer_type_node,
23151 short_integer_type_node, NULL_TREE);
23152 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23154 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23155 char_type_node, char_type_node,
23156 char_type_node, char_type_node,
23157 char_type_node, char_type_node,
23158 char_type_node, NULL_TREE);
23159 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23161 /* Access to the vec_extract patterns. */
23162 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23163 integer_type_node, NULL_TREE);
23164 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23166 ftype = build_function_type_list (long_long_integer_type_node,
23167 V2DI_type_node, integer_type_node,
23169 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23171 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23172 integer_type_node, NULL_TREE);
23173 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23175 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23176 integer_type_node, NULL_TREE);
23177 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23179 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23180 integer_type_node, NULL_TREE);
23181 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23183 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23184 integer_type_node, NULL_TREE);
23185 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23187 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23188 integer_type_node, NULL_TREE);
23189 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23191 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23192 integer_type_node, NULL_TREE);
23193 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23195 /* Access to the vec_set patterns. */
23196 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23198 integer_type_node, NULL_TREE);
23199 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23201 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23203 integer_type_node, NULL_TREE);
23204 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23206 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23208 integer_type_node, NULL_TREE);
23209 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23211 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23213 integer_type_node, NULL_TREE);
23214 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23216 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23218 integer_type_node, NULL_TREE);
23219 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23221 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23223 integer_type_node, NULL_TREE);
23224 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23226 /* Add SSE5 multi-arg argument instructions */
23227 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23229 tree mtype = NULL_TREE;
23234 switch ((enum multi_arg_type)d->flag)
23236 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23237 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23238 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
23239 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
23240 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
23241 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
23242 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
23243 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
23244 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
23245 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
23246 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
23247 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
23248 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
23249 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
23250 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
23251 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
23252 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
23253 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
23254 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
23255 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
23256 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
23257 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
23258 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
23259 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
23260 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
23261 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
23262 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
23263 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
23264 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
23265 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
23266 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
23267 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
23268 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
23269 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
23270 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
23271 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
23272 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
23273 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
23274 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
23275 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
23276 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
23277 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
23278 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
23279 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
23280 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
23281 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
23282 case MULTI_ARG_UNKNOWN:
23284 gcc_unreachable ();
23288 def_builtin_const (d->mask, d->name, mtype, d->code);
23292 /* Internal method for ix86_init_builtins. */
23295 ix86_init_builtins_va_builtins_abi (void)
23297 tree ms_va_ref, sysv_va_ref;
23298 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23299 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23300 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23301 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23305 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23306 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23307 ms_va_ref = build_reference_type (ms_va_list_type_node);
23309 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23312 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23313 fnvoid_va_start_ms =
23314 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23315 fnvoid_va_end_sysv =
23316 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23317 fnvoid_va_start_sysv =
23318 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23320 fnvoid_va_copy_ms =
23321 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23323 fnvoid_va_copy_sysv =
23324 build_function_type_list (void_type_node, sysv_va_ref,
23325 sysv_va_ref, NULL_TREE);
23327 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23328 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23329 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23330 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23331 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23332 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23333 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23334 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23335 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23336 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23337 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23338 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23342 ix86_init_builtins (void)
23344 tree float128_type_node = make_node (REAL_TYPE);
23347 /* The __float80 type. */
23348 if (TYPE_MODE (long_double_type_node) == XFmode)
23349 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23353 /* The __float80 type. */
23354 tree float80_type_node = make_node (REAL_TYPE);
23356 TYPE_PRECISION (float80_type_node) = 80;
23357 layout_type (float80_type_node);
23358 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23362 /* The __float128 type. */
23363 TYPE_PRECISION (float128_type_node) = 128;
23364 layout_type (float128_type_node);
23365 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23368 /* TFmode support builtins. */
23369 ftype = build_function_type (float128_type_node, void_list_node);
23370 decl = add_builtin_function ("__builtin_infq", ftype,
23371 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23373 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23375 /* We will expand them to normal call if SSE2 isn't available since
23376 they are used by libgcc. */
23377 ftype = build_function_type_list (float128_type_node,
23378 float128_type_node,
23380 decl = add_builtin_function ("__builtin_fabsq", ftype,
23381 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23382 "__fabstf2", NULL_TREE);
23383 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23384 TREE_READONLY (decl) = 1;
23386 ftype = build_function_type_list (float128_type_node,
23387 float128_type_node,
23388 float128_type_node,
23390 decl = add_builtin_function ("__builtin_copysignq", ftype,
23391 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23392 "__copysigntf3", NULL_TREE);
23393 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23394 TREE_READONLY (decl) = 1;
23396 ix86_init_mmx_sse_builtins ();
23398 ix86_init_builtins_va_builtins_abi ();
23401 /* Errors in the source file can cause expand_expr to return const0_rtx
23402 where we expect a vector. To avoid crashing, use one of the vector
23403 clear instructions. */
23405 safe_vector_operand (rtx x, enum machine_mode mode)
23407 if (x == const0_rtx)
23408 x = CONST0_RTX (mode);
23412 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23415 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23418 tree arg0 = CALL_EXPR_ARG (exp, 0);
23419 tree arg1 = CALL_EXPR_ARG (exp, 1);
23420 rtx op0 = expand_normal (arg0);
23421 rtx op1 = expand_normal (arg1);
23422 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23423 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23424 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23426 if (VECTOR_MODE_P (mode0))
23427 op0 = safe_vector_operand (op0, mode0);
23428 if (VECTOR_MODE_P (mode1))
23429 op1 = safe_vector_operand (op1, mode1);
23431 if (optimize || !target
23432 || GET_MODE (target) != tmode
23433 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23434 target = gen_reg_rtx (tmode);
23436 if (GET_MODE (op1) == SImode && mode1 == TImode)
23438 rtx x = gen_reg_rtx (V4SImode);
23439 emit_insn (gen_sse2_loadd (x, op1));
23440 op1 = gen_lowpart (TImode, x);
23443 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23444 op0 = copy_to_mode_reg (mode0, op0);
23445 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23446 op1 = copy_to_mode_reg (mode1, op1);
23448 pat = GEN_FCN (icode) (target, op0, op1);
23457 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23460 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23461 enum multi_arg_type m_type,
23462 enum insn_code sub_code)
23467 bool comparison_p = false;
23469 bool last_arg_constant = false;
23470 int num_memory = 0;
23473 enum machine_mode mode;
23476 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23480 case MULTI_ARG_3_SF:
23481 case MULTI_ARG_3_DF:
23482 case MULTI_ARG_3_DI:
23483 case MULTI_ARG_3_SI:
23484 case MULTI_ARG_3_SI_DI:
23485 case MULTI_ARG_3_HI:
23486 case MULTI_ARG_3_HI_SI:
23487 case MULTI_ARG_3_QI:
23488 case MULTI_ARG_3_PERMPS:
23489 case MULTI_ARG_3_PERMPD:
23493 case MULTI_ARG_2_SF:
23494 case MULTI_ARG_2_DF:
23495 case MULTI_ARG_2_DI:
23496 case MULTI_ARG_2_SI:
23497 case MULTI_ARG_2_HI:
23498 case MULTI_ARG_2_QI:
23502 case MULTI_ARG_2_DI_IMM:
23503 case MULTI_ARG_2_SI_IMM:
23504 case MULTI_ARG_2_HI_IMM:
23505 case MULTI_ARG_2_QI_IMM:
23507 last_arg_constant = true;
23510 case MULTI_ARG_1_SF:
23511 case MULTI_ARG_1_DF:
23512 case MULTI_ARG_1_DI:
23513 case MULTI_ARG_1_SI:
23514 case MULTI_ARG_1_HI:
23515 case MULTI_ARG_1_QI:
23516 case MULTI_ARG_1_SI_DI:
23517 case MULTI_ARG_1_HI_DI:
23518 case MULTI_ARG_1_HI_SI:
23519 case MULTI_ARG_1_QI_DI:
23520 case MULTI_ARG_1_QI_SI:
23521 case MULTI_ARG_1_QI_HI:
23522 case MULTI_ARG_1_PH2PS:
23523 case MULTI_ARG_1_PS2PH:
23527 case MULTI_ARG_2_SF_CMP:
23528 case MULTI_ARG_2_DF_CMP:
23529 case MULTI_ARG_2_DI_CMP:
23530 case MULTI_ARG_2_SI_CMP:
23531 case MULTI_ARG_2_HI_CMP:
23532 case MULTI_ARG_2_QI_CMP:
23534 comparison_p = true;
23537 case MULTI_ARG_2_SF_TF:
23538 case MULTI_ARG_2_DF_TF:
23539 case MULTI_ARG_2_DI_TF:
23540 case MULTI_ARG_2_SI_TF:
23541 case MULTI_ARG_2_HI_TF:
23542 case MULTI_ARG_2_QI_TF:
23547 case MULTI_ARG_UNKNOWN:
23549 gcc_unreachable ();
23552 if (optimize || !target
23553 || GET_MODE (target) != tmode
23554 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23555 target = gen_reg_rtx (tmode);
23557 gcc_assert (nargs <= 4);
23559 for (i = 0; i < nargs; i++)
23561 tree arg = CALL_EXPR_ARG (exp, i);
23562 rtx op = expand_normal (arg);
23563 int adjust = (comparison_p) ? 1 : 0;
23564 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
23566 if (last_arg_constant && i == nargs-1)
23568 if (GET_CODE (op) != CONST_INT)
23570 error ("last argument must be an immediate");
23571 return gen_reg_rtx (tmode);
23576 if (VECTOR_MODE_P (mode))
23577 op = safe_vector_operand (op, mode);
23579 /* If we aren't optimizing, only allow one memory operand to be
23581 if (memory_operand (op, mode))
23584 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23587 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23589 op = force_reg (mode, op);
23593 args[i].mode = mode;
23599 pat = GEN_FCN (icode) (target, args[0].op);
23604 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23605 GEN_INT ((int)sub_code));
23606 else if (! comparison_p)
23607 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23610 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23614 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23619 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23623 gcc_unreachable ();
23633 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23634 insns with vec_merge. */
23637 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23641 tree arg0 = CALL_EXPR_ARG (exp, 0);
23642 rtx op1, op0 = expand_normal (arg0);
23643 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23644 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23646 if (optimize || !target
23647 || GET_MODE (target) != tmode
23648 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23649 target = gen_reg_rtx (tmode);
23651 if (VECTOR_MODE_P (mode0))
23652 op0 = safe_vector_operand (op0, mode0);
23654 if ((optimize && !register_operand (op0, mode0))
23655 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23656 op0 = copy_to_mode_reg (mode0, op0);
23659 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23660 op1 = copy_to_mode_reg (mode0, op1);
23662 pat = GEN_FCN (icode) (target, op0, op1);
23669 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23672 ix86_expand_sse_compare (const struct builtin_description *d,
23673 tree exp, rtx target, bool swap)
23676 tree arg0 = CALL_EXPR_ARG (exp, 0);
23677 tree arg1 = CALL_EXPR_ARG (exp, 1);
23678 rtx op0 = expand_normal (arg0);
23679 rtx op1 = expand_normal (arg1);
23681 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23682 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23683 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23684 enum rtx_code comparison = d->comparison;
23686 if (VECTOR_MODE_P (mode0))
23687 op0 = safe_vector_operand (op0, mode0);
23688 if (VECTOR_MODE_P (mode1))
23689 op1 = safe_vector_operand (op1, mode1);
23691 /* Swap operands if we have a comparison that isn't available in
23695 rtx tmp = gen_reg_rtx (mode1);
23696 emit_move_insn (tmp, op1);
23701 if (optimize || !target
23702 || GET_MODE (target) != tmode
23703 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23704 target = gen_reg_rtx (tmode);
23706 if ((optimize && !register_operand (op0, mode0))
23707 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23708 op0 = copy_to_mode_reg (mode0, op0);
23709 if ((optimize && !register_operand (op1, mode1))
23710 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23711 op1 = copy_to_mode_reg (mode1, op1);
23713 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23714 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23721 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23724 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23728 tree arg0 = CALL_EXPR_ARG (exp, 0);
23729 tree arg1 = CALL_EXPR_ARG (exp, 1);
23730 rtx op0 = expand_normal (arg0);
23731 rtx op1 = expand_normal (arg1);
23732 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23733 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23734 enum rtx_code comparison = d->comparison;
23736 if (VECTOR_MODE_P (mode0))
23737 op0 = safe_vector_operand (op0, mode0);
23738 if (VECTOR_MODE_P (mode1))
23739 op1 = safe_vector_operand (op1, mode1);
23741 /* Swap operands if we have a comparison that isn't available in
23743 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23750 target = gen_reg_rtx (SImode);
23751 emit_move_insn (target, const0_rtx);
23752 target = gen_rtx_SUBREG (QImode, target, 0);
23754 if ((optimize && !register_operand (op0, mode0))
23755 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23756 op0 = copy_to_mode_reg (mode0, op0);
23757 if ((optimize && !register_operand (op1, mode1))
23758 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23759 op1 = copy_to_mode_reg (mode1, op1);
23761 pat = GEN_FCN (d->icode) (op0, op1);
23765 emit_insn (gen_rtx_SET (VOIDmode,
23766 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23767 gen_rtx_fmt_ee (comparison, QImode,
23771 return SUBREG_REG (target);
23774 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23777 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23781 tree arg0 = CALL_EXPR_ARG (exp, 0);
23782 tree arg1 = CALL_EXPR_ARG (exp, 1);
23783 rtx op0 = expand_normal (arg0);
23784 rtx op1 = expand_normal (arg1);
23785 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23786 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23787 enum rtx_code comparison = d->comparison;
23789 if (VECTOR_MODE_P (mode0))
23790 op0 = safe_vector_operand (op0, mode0);
23791 if (VECTOR_MODE_P (mode1))
23792 op1 = safe_vector_operand (op1, mode1);
23794 target = gen_reg_rtx (SImode);
23795 emit_move_insn (target, const0_rtx);
23796 target = gen_rtx_SUBREG (QImode, target, 0);
23798 if ((optimize && !register_operand (op0, mode0))
23799 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23800 op0 = copy_to_mode_reg (mode0, op0);
23801 if ((optimize && !register_operand (op1, mode1))
23802 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23803 op1 = copy_to_mode_reg (mode1, op1);
23805 pat = GEN_FCN (d->icode) (op0, op1);
23809 emit_insn (gen_rtx_SET (VOIDmode,
23810 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23811 gen_rtx_fmt_ee (comparison, QImode,
23815 return SUBREG_REG (target);
23818 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23821 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23822 tree exp, rtx target)
23825 tree arg0 = CALL_EXPR_ARG (exp, 0);
23826 tree arg1 = CALL_EXPR_ARG (exp, 1);
23827 tree arg2 = CALL_EXPR_ARG (exp, 2);
23828 tree arg3 = CALL_EXPR_ARG (exp, 3);
23829 tree arg4 = CALL_EXPR_ARG (exp, 4);
23830 rtx scratch0, scratch1;
23831 rtx op0 = expand_normal (arg0);
23832 rtx op1 = expand_normal (arg1);
23833 rtx op2 = expand_normal (arg2);
23834 rtx op3 = expand_normal (arg3);
23835 rtx op4 = expand_normal (arg4);
23836 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23838 tmode0 = insn_data[d->icode].operand[0].mode;
23839 tmode1 = insn_data[d->icode].operand[1].mode;
23840 modev2 = insn_data[d->icode].operand[2].mode;
23841 modei3 = insn_data[d->icode].operand[3].mode;
23842 modev4 = insn_data[d->icode].operand[4].mode;
23843 modei5 = insn_data[d->icode].operand[5].mode;
23844 modeimm = insn_data[d->icode].operand[6].mode;
23846 if (VECTOR_MODE_P (modev2))
23847 op0 = safe_vector_operand (op0, modev2);
23848 if (VECTOR_MODE_P (modev4))
23849 op2 = safe_vector_operand (op2, modev4);
23851 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23852 op0 = copy_to_mode_reg (modev2, op0);
23853 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23854 op1 = copy_to_mode_reg (modei3, op1);
23855 if ((optimize && !register_operand (op2, modev4))
23856 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23857 op2 = copy_to_mode_reg (modev4, op2);
23858 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23859 op3 = copy_to_mode_reg (modei5, op3);
23861 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23863 error ("the fifth argument must be a 8-bit immediate");
23867 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23869 if (optimize || !target
23870 || GET_MODE (target) != tmode0
23871 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23872 target = gen_reg_rtx (tmode0);
23874 scratch1 = gen_reg_rtx (tmode1);
23876 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23878 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23880 if (optimize || !target
23881 || GET_MODE (target) != tmode1
23882 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23883 target = gen_reg_rtx (tmode1);
23885 scratch0 = gen_reg_rtx (tmode0);
23887 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23891 gcc_assert (d->flag);
23893 scratch0 = gen_reg_rtx (tmode0);
23894 scratch1 = gen_reg_rtx (tmode1);
23896 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23906 target = gen_reg_rtx (SImode);
23907 emit_move_insn (target, const0_rtx);
23908 target = gen_rtx_SUBREG (QImode, target, 0);
23911 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23912 gen_rtx_fmt_ee (EQ, QImode,
23913 gen_rtx_REG ((enum machine_mode) d->flag,
23916 return SUBREG_REG (target);
23923 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23926 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23927 tree exp, rtx target)
23930 tree arg0 = CALL_EXPR_ARG (exp, 0);
23931 tree arg1 = CALL_EXPR_ARG (exp, 1);
23932 tree arg2 = CALL_EXPR_ARG (exp, 2);
23933 rtx scratch0, scratch1;
23934 rtx op0 = expand_normal (arg0);
23935 rtx op1 = expand_normal (arg1);
23936 rtx op2 = expand_normal (arg2);
23937 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
23939 tmode0 = insn_data[d->icode].operand[0].mode;
23940 tmode1 = insn_data[d->icode].operand[1].mode;
23941 modev2 = insn_data[d->icode].operand[2].mode;
23942 modev3 = insn_data[d->icode].operand[3].mode;
23943 modeimm = insn_data[d->icode].operand[4].mode;
23945 if (VECTOR_MODE_P (modev2))
23946 op0 = safe_vector_operand (op0, modev2);
23947 if (VECTOR_MODE_P (modev3))
23948 op1 = safe_vector_operand (op1, modev3);
23950 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23951 op0 = copy_to_mode_reg (modev2, op0);
23952 if ((optimize && !register_operand (op1, modev3))
23953 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
23954 op1 = copy_to_mode_reg (modev3, op1);
23956 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
23958 error ("the third argument must be a 8-bit immediate");
23962 if (d->code == IX86_BUILTIN_PCMPISTRI128)
23964 if (optimize || !target
23965 || GET_MODE (target) != tmode0
23966 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23967 target = gen_reg_rtx (tmode0);
23969 scratch1 = gen_reg_rtx (tmode1);
23971 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
23973 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
23975 if (optimize || !target
23976 || GET_MODE (target) != tmode1
23977 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23978 target = gen_reg_rtx (tmode1);
23980 scratch0 = gen_reg_rtx (tmode0);
23982 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
23986 gcc_assert (d->flag);
23988 scratch0 = gen_reg_rtx (tmode0);
23989 scratch1 = gen_reg_rtx (tmode1);
23991 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24001 target = gen_reg_rtx (SImode);
24002 emit_move_insn (target, const0_rtx);
24003 target = gen_rtx_SUBREG (QImode, target, 0);
24006 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24007 gen_rtx_fmt_ee (EQ, QImode,
24008 gen_rtx_REG ((enum machine_mode) d->flag,
24011 return SUBREG_REG (target);
24017 /* Subroutine of ix86_expand_builtin to take care of insns with
24018 variable number of operands. */
24021 ix86_expand_args_builtin (const struct builtin_description *d,
24022 tree exp, rtx target)
24024 rtx pat, real_target;
24025 unsigned int i, nargs;
24026 unsigned int nargs_constant = 0;
24027 int num_memory = 0;
24031 enum machine_mode mode;
24033 bool last_arg_count = false;
24034 enum insn_code icode = d->icode;
24035 const struct insn_data *insn_p = &insn_data[icode];
24036 enum machine_mode tmode = insn_p->operand[0].mode;
24037 enum machine_mode rmode = VOIDmode;
24039 enum rtx_code comparison = d->comparison;
24041 switch ((enum ix86_builtin_type) d->flag)
24043 case INT_FTYPE_V8SF_V8SF_PTEST:
24044 case INT_FTYPE_V4DI_V4DI_PTEST:
24045 case INT_FTYPE_V4DF_V4DF_PTEST:
24046 case INT_FTYPE_V4SF_V4SF_PTEST:
24047 case INT_FTYPE_V2DI_V2DI_PTEST:
24048 case INT_FTYPE_V2DF_V2DF_PTEST:
24049 return ix86_expand_sse_ptest (d, exp, target);
24050 case FLOAT128_FTYPE_FLOAT128:
24051 case FLOAT_FTYPE_FLOAT:
24052 case INT64_FTYPE_V4SF:
24053 case INT64_FTYPE_V2DF:
24054 case INT_FTYPE_V16QI:
24055 case INT_FTYPE_V8QI:
24056 case INT_FTYPE_V8SF:
24057 case INT_FTYPE_V4DF:
24058 case INT_FTYPE_V4SF:
24059 case INT_FTYPE_V2DF:
24060 case V16QI_FTYPE_V16QI:
24061 case V8SI_FTYPE_V8SF:
24062 case V8SI_FTYPE_V4SI:
24063 case V8HI_FTYPE_V8HI:
24064 case V8HI_FTYPE_V16QI:
24065 case V8QI_FTYPE_V8QI:
24066 case V8SF_FTYPE_V8SF:
24067 case V8SF_FTYPE_V8SI:
24068 case V8SF_FTYPE_V4SF:
24069 case V4SI_FTYPE_V4SI:
24070 case V4SI_FTYPE_V16QI:
24071 case V4SI_FTYPE_V4SF:
24072 case V4SI_FTYPE_V8SI:
24073 case V4SI_FTYPE_V8HI:
24074 case V4SI_FTYPE_V4DF:
24075 case V4SI_FTYPE_V2DF:
24076 case V4HI_FTYPE_V4HI:
24077 case V4DF_FTYPE_V4DF:
24078 case V4DF_FTYPE_V4SI:
24079 case V4DF_FTYPE_V4SF:
24080 case V4DF_FTYPE_V2DF:
24081 case V4SF_FTYPE_V4SF:
24082 case V4SF_FTYPE_V4SI:
24083 case V4SF_FTYPE_V8SF:
24084 case V4SF_FTYPE_V4DF:
24085 case V4SF_FTYPE_V2DF:
24086 case V2DI_FTYPE_V2DI:
24087 case V2DI_FTYPE_V16QI:
24088 case V2DI_FTYPE_V8HI:
24089 case V2DI_FTYPE_V4SI:
24090 case V2DF_FTYPE_V2DF:
24091 case V2DF_FTYPE_V4SI:
24092 case V2DF_FTYPE_V4DF:
24093 case V2DF_FTYPE_V4SF:
24094 case V2DF_FTYPE_V2SI:
24095 case V2SI_FTYPE_V2SI:
24096 case V2SI_FTYPE_V4SF:
24097 case V2SI_FTYPE_V2SF:
24098 case V2SI_FTYPE_V2DF:
24099 case V2SF_FTYPE_V2SF:
24100 case V2SF_FTYPE_V2SI:
24103 case V4SF_FTYPE_V4SF_VEC_MERGE:
24104 case V2DF_FTYPE_V2DF_VEC_MERGE:
24105 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24106 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24107 case V16QI_FTYPE_V16QI_V16QI:
24108 case V16QI_FTYPE_V8HI_V8HI:
24109 case V8QI_FTYPE_V8QI_V8QI:
24110 case V8QI_FTYPE_V4HI_V4HI:
24111 case V8HI_FTYPE_V8HI_V8HI:
24112 case V8HI_FTYPE_V16QI_V16QI:
24113 case V8HI_FTYPE_V4SI_V4SI:
24114 case V8SF_FTYPE_V8SF_V8SF:
24115 case V8SF_FTYPE_V8SF_V8SI:
24116 case V4SI_FTYPE_V4SI_V4SI:
24117 case V4SI_FTYPE_V8HI_V8HI:
24118 case V4SI_FTYPE_V4SF_V4SF:
24119 case V4SI_FTYPE_V2DF_V2DF:
24120 case V4HI_FTYPE_V4HI_V4HI:
24121 case V4HI_FTYPE_V8QI_V8QI:
24122 case V4HI_FTYPE_V2SI_V2SI:
24123 case V4DF_FTYPE_V4DF_V4DF:
24124 case V4DF_FTYPE_V4DF_V4DI:
24125 case V4SF_FTYPE_V4SF_V4SF:
24126 case V4SF_FTYPE_V4SF_V4SI:
24127 case V4SF_FTYPE_V4SF_V2SI:
24128 case V4SF_FTYPE_V4SF_V2DF:
24129 case V4SF_FTYPE_V4SF_DI:
24130 case V4SF_FTYPE_V4SF_SI:
24131 case V2DI_FTYPE_V2DI_V2DI:
24132 case V2DI_FTYPE_V16QI_V16QI:
24133 case V2DI_FTYPE_V4SI_V4SI:
24134 case V2DI_FTYPE_V2DI_V16QI:
24135 case V2DI_FTYPE_V2DF_V2DF:
24136 case V2SI_FTYPE_V2SI_V2SI:
24137 case V2SI_FTYPE_V4HI_V4HI:
24138 case V2SI_FTYPE_V2SF_V2SF:
24139 case V2DF_FTYPE_V2DF_V2DF:
24140 case V2DF_FTYPE_V2DF_V4SF:
24141 case V2DF_FTYPE_V2DF_V2DI:
24142 case V2DF_FTYPE_V2DF_DI:
24143 case V2DF_FTYPE_V2DF_SI:
24144 case V2SF_FTYPE_V2SF_V2SF:
24145 case V1DI_FTYPE_V1DI_V1DI:
24146 case V1DI_FTYPE_V8QI_V8QI:
24147 case V1DI_FTYPE_V2SI_V2SI:
24148 if (comparison == UNKNOWN)
24149 return ix86_expand_binop_builtin (icode, exp, target);
24152 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24153 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24154 gcc_assert (comparison != UNKNOWN);
24158 case V8HI_FTYPE_V8HI_V8HI_COUNT:
24159 case V8HI_FTYPE_V8HI_SI_COUNT:
24160 case V4SI_FTYPE_V4SI_V4SI_COUNT:
24161 case V4SI_FTYPE_V4SI_SI_COUNT:
24162 case V4HI_FTYPE_V4HI_V4HI_COUNT:
24163 case V4HI_FTYPE_V4HI_SI_COUNT:
24164 case V2DI_FTYPE_V2DI_V2DI_COUNT:
24165 case V2DI_FTYPE_V2DI_SI_COUNT:
24166 case V2SI_FTYPE_V2SI_V2SI_COUNT:
24167 case V2SI_FTYPE_V2SI_SI_COUNT:
24168 case V1DI_FTYPE_V1DI_V1DI_COUNT:
24169 case V1DI_FTYPE_V1DI_SI_COUNT:
24171 last_arg_count = true;
24173 case UINT64_FTYPE_UINT64_UINT64:
24174 case UINT_FTYPE_UINT_UINT:
24175 case UINT_FTYPE_UINT_USHORT:
24176 case UINT_FTYPE_UINT_UCHAR:
24179 case V2DI2TI_FTYPE_V2DI_INT:
24182 nargs_constant = 1;
24184 case V8HI_FTYPE_V8HI_INT:
24185 case V8SF_FTYPE_V8SF_INT:
24186 case V4SI_FTYPE_V4SI_INT:
24187 case V4SI_FTYPE_V8SI_INT:
24188 case V4HI_FTYPE_V4HI_INT:
24189 case V4DF_FTYPE_V4DF_INT:
24190 case V4SF_FTYPE_V4SF_INT:
24191 case V4SF_FTYPE_V8SF_INT:
24192 case V2DI_FTYPE_V2DI_INT:
24193 case V2DF_FTYPE_V2DF_INT:
24194 case V2DF_FTYPE_V4DF_INT:
24196 nargs_constant = 1;
24198 case V16QI_FTYPE_V16QI_V16QI_V16QI:
24199 case V8SF_FTYPE_V8SF_V8SF_V8SF:
24200 case V4DF_FTYPE_V4DF_V4DF_V4DF:
24201 case V4SF_FTYPE_V4SF_V4SF_V4SF:
24202 case V2DF_FTYPE_V2DF_V2DF_V2DF:
24205 case V16QI_FTYPE_V16QI_V16QI_INT:
24206 case V8HI_FTYPE_V8HI_V8HI_INT:
24207 case V8SI_FTYPE_V8SI_V8SI_INT:
24208 case V8SI_FTYPE_V8SI_V4SI_INT:
24209 case V8SF_FTYPE_V8SF_V8SF_INT:
24210 case V8SF_FTYPE_V8SF_V4SF_INT:
24211 case V4SI_FTYPE_V4SI_V4SI_INT:
24212 case V4DF_FTYPE_V4DF_V4DF_INT:
24213 case V4DF_FTYPE_V4DF_V2DF_INT:
24214 case V4SF_FTYPE_V4SF_V4SF_INT:
24215 case V2DI_FTYPE_V2DI_V2DI_INT:
24216 case V2DF_FTYPE_V2DF_V2DF_INT:
24218 nargs_constant = 1;
24220 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24223 nargs_constant = 1;
24225 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24228 nargs_constant = 1;
24230 case V2DI_FTYPE_V2DI_UINT_UINT:
24232 nargs_constant = 2;
24234 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24236 nargs_constant = 2;
24239 gcc_unreachable ();
24242 gcc_assert (nargs <= ARRAY_SIZE (args));
24244 if (comparison != UNKNOWN)
24246 gcc_assert (nargs == 2);
24247 return ix86_expand_sse_compare (d, exp, target, swap);
24250 if (rmode == VOIDmode || rmode == tmode)
24254 || GET_MODE (target) != tmode
24255 || ! (*insn_p->operand[0].predicate) (target, tmode))
24256 target = gen_reg_rtx (tmode);
24257 real_target = target;
24261 target = gen_reg_rtx (rmode);
24262 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24265 for (i = 0; i < nargs; i++)
24267 tree arg = CALL_EXPR_ARG (exp, i);
24268 rtx op = expand_normal (arg);
24269 enum machine_mode mode = insn_p->operand[i + 1].mode;
24270 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24272 if (last_arg_count && (i + 1) == nargs)
24274 /* SIMD shift insns take either an 8-bit immediate or
24275 register as count. But builtin functions take int as
24276 count. If count doesn't match, we put it in register. */
24279 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24280 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24281 op = copy_to_reg (op);
24284 else if ((nargs - i) <= nargs_constant)
24289 case CODE_FOR_sse4_1_roundpd:
24290 case CODE_FOR_sse4_1_roundps:
24291 case CODE_FOR_sse4_1_roundsd:
24292 case CODE_FOR_sse4_1_roundss:
24293 case CODE_FOR_sse4_1_blendps:
24294 case CODE_FOR_avx_blendpd256:
24295 case CODE_FOR_avx_vpermilv4df:
24296 case CODE_FOR_avx_roundpd256:
24297 case CODE_FOR_avx_roundps256:
24298 error ("the last argument must be a 4-bit immediate");
24301 case CODE_FOR_sse4_1_blendpd:
24302 case CODE_FOR_avx_vpermilv2df:
24303 error ("the last argument must be a 2-bit immediate");
24306 case CODE_FOR_avx_vextractf128v4df:
24307 case CODE_FOR_avx_vextractf128v8sf:
24308 case CODE_FOR_avx_vextractf128v8si:
24309 case CODE_FOR_avx_vinsertf128v4df:
24310 case CODE_FOR_avx_vinsertf128v8sf:
24311 case CODE_FOR_avx_vinsertf128v8si:
24312 error ("the last argument must be a 1-bit immediate");
24315 case CODE_FOR_avx_cmpsdv2df3:
24316 case CODE_FOR_avx_cmpssv4sf3:
24317 case CODE_FOR_avx_cmppdv2df3:
24318 case CODE_FOR_avx_cmppsv4sf3:
24319 case CODE_FOR_avx_cmppdv4df3:
24320 case CODE_FOR_avx_cmppsv8sf3:
24321 error ("the last argument must be a 5-bit immediate");
24325 switch (nargs_constant)
24328 if ((nargs - i) == nargs_constant)
24330 error ("the next to last argument must be an 8-bit immediate");
24334 error ("the last argument must be an 8-bit immediate");
24337 gcc_unreachable ();
24344 if (VECTOR_MODE_P (mode))
24345 op = safe_vector_operand (op, mode);
24347 /* If we aren't optimizing, only allow one memory operand to
24349 if (memory_operand (op, mode))
24352 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24354 if (optimize || !match || num_memory > 1)
24355 op = copy_to_mode_reg (mode, op);
24359 op = copy_to_reg (op);
24360 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24365 args[i].mode = mode;
24371 pat = GEN_FCN (icode) (real_target, args[0].op);
24374 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24377 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24381 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24382 args[2].op, args[3].op);
24385 gcc_unreachable ();
24395 /* Subroutine of ix86_expand_builtin to take care of special insns
24396 with variable number of operands. */
24399 ix86_expand_special_args_builtin (const struct builtin_description *d,
24400 tree exp, rtx target)
24404 unsigned int i, nargs, arg_adjust, memory;
24408 enum machine_mode mode;
24410 enum insn_code icode = d->icode;
24411 bool last_arg_constant = false;
24412 const struct insn_data *insn_p = &insn_data[icode];
24413 enum machine_mode tmode = insn_p->operand[0].mode;
24414 enum { load, store } klass;
24416 switch ((enum ix86_special_builtin_type) d->flag)
24418 case VOID_FTYPE_VOID:
24419 emit_insn (GEN_FCN (icode) (target));
24421 case V2DI_FTYPE_PV2DI:
24422 case V32QI_FTYPE_PCCHAR:
24423 case V16QI_FTYPE_PCCHAR:
24424 case V8SF_FTYPE_PCV4SF:
24425 case V8SF_FTYPE_PCFLOAT:
24426 case V4SF_FTYPE_PCFLOAT:
24427 case V4DF_FTYPE_PCV2DF:
24428 case V4DF_FTYPE_PCDOUBLE:
24429 case V2DF_FTYPE_PCDOUBLE:
24434 case VOID_FTYPE_PV2SF_V4SF:
24435 case VOID_FTYPE_PV4DI_V4DI:
24436 case VOID_FTYPE_PV2DI_V2DI:
24437 case VOID_FTYPE_PCHAR_V32QI:
24438 case VOID_FTYPE_PCHAR_V16QI:
24439 case VOID_FTYPE_PFLOAT_V8SF:
24440 case VOID_FTYPE_PFLOAT_V4SF:
24441 case VOID_FTYPE_PDOUBLE_V4DF:
24442 case VOID_FTYPE_PDOUBLE_V2DF:
24443 case VOID_FTYPE_PDI_DI:
24444 case VOID_FTYPE_PINT_INT:
24447 /* Reserve memory operand for target. */
24448 memory = ARRAY_SIZE (args);
24450 case V4SF_FTYPE_V4SF_PCV2SF:
24451 case V2DF_FTYPE_V2DF_PCDOUBLE:
24456 case V8SF_FTYPE_PCV8SF_V8SF:
24457 case V4DF_FTYPE_PCV4DF_V4DF:
24458 case V4SF_FTYPE_PCV4SF_V4SF:
24459 case V2DF_FTYPE_PCV2DF_V2DF:
24464 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24465 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24466 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24467 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24470 /* Reserve memory operand for target. */
24471 memory = ARRAY_SIZE (args);
24474 gcc_unreachable ();
24477 gcc_assert (nargs <= ARRAY_SIZE (args));
24479 if (klass == store)
24481 arg = CALL_EXPR_ARG (exp, 0);
24482 op = expand_normal (arg);
24483 gcc_assert (target == 0);
24484 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24492 || GET_MODE (target) != tmode
24493 || ! (*insn_p->operand[0].predicate) (target, tmode))
24494 target = gen_reg_rtx (tmode);
24497 for (i = 0; i < nargs; i++)
24499 enum machine_mode mode = insn_p->operand[i + 1].mode;
24502 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24503 op = expand_normal (arg);
24504 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24506 if (last_arg_constant && (i + 1) == nargs)
24512 error ("the last argument must be an 8-bit immediate");
24520 /* This must be the memory operand. */
24521 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24522 gcc_assert (GET_MODE (op) == mode
24523 || GET_MODE (op) == VOIDmode);
24527 /* This must be register. */
24528 if (VECTOR_MODE_P (mode))
24529 op = safe_vector_operand (op, mode);
24531 gcc_assert (GET_MODE (op) == mode
24532 || GET_MODE (op) == VOIDmode);
24533 op = copy_to_mode_reg (mode, op);
24538 args[i].mode = mode;
24544 pat = GEN_FCN (icode) (target, args[0].op);
24547 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24550 gcc_unreachable ();
24556 return klass == store ? 0 : target;
24559 /* Return the integer constant in ARG. Constrain it to be in the range
24560 of the subparts of VEC_TYPE; issue an error if not. */
24563 get_element_number (tree vec_type, tree arg)
24565 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24567 if (!host_integerp (arg, 1)
24568 || (elt = tree_low_cst (arg, 1), elt > max))
24570 error ("selector must be an integer constant in the range 0..%wi", max);
24577 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24578 ix86_expand_vector_init. We DO have language-level syntax for this, in
24579 the form of (type){ init-list }. Except that since we can't place emms
24580 instructions from inside the compiler, we can't allow the use of MMX
24581 registers unless the user explicitly asks for it. So we do *not* define
24582 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24583 we have builtins invoked by mmintrin.h that gives us license to emit
24584 these sorts of instructions. */
24587 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24589 enum machine_mode tmode = TYPE_MODE (type);
24590 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24591 int i, n_elt = GET_MODE_NUNITS (tmode);
24592 rtvec v = rtvec_alloc (n_elt);
24594 gcc_assert (VECTOR_MODE_P (tmode));
24595 gcc_assert (call_expr_nargs (exp) == n_elt);
24597 for (i = 0; i < n_elt; ++i)
24599 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24600 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24603 if (!target || !register_operand (target, tmode))
24604 target = gen_reg_rtx (tmode);
24606 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24610 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24611 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24612 had a language-level syntax for referencing vector elements. */
24615 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24617 enum machine_mode tmode, mode0;
24622 arg0 = CALL_EXPR_ARG (exp, 0);
24623 arg1 = CALL_EXPR_ARG (exp, 1);
24625 op0 = expand_normal (arg0);
24626 elt = get_element_number (TREE_TYPE (arg0), arg1);
24628 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24629 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24630 gcc_assert (VECTOR_MODE_P (mode0));
24632 op0 = force_reg (mode0, op0);
24634 if (optimize || !target || !register_operand (target, tmode))
24635 target = gen_reg_rtx (tmode);
24637 ix86_expand_vector_extract (true, target, op0, elt);
24642 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24643 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24644 a language-level syntax for referencing vector elements. */
24647 ix86_expand_vec_set_builtin (tree exp)
24649 enum machine_mode tmode, mode1;
24650 tree arg0, arg1, arg2;
24652 rtx op0, op1, target;
24654 arg0 = CALL_EXPR_ARG (exp, 0);
24655 arg1 = CALL_EXPR_ARG (exp, 1);
24656 arg2 = CALL_EXPR_ARG (exp, 2);
24658 tmode = TYPE_MODE (TREE_TYPE (arg0));
24659 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24660 gcc_assert (VECTOR_MODE_P (tmode));
24662 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24663 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24664 elt = get_element_number (TREE_TYPE (arg0), arg2);
24666 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24667 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24669 op0 = force_reg (tmode, op0);
24670 op1 = force_reg (mode1, op1);
24672 /* OP0 is the source of these builtin functions and shouldn't be
24673 modified. Create a copy, use it and return it as target. */
24674 target = gen_reg_rtx (tmode);
24675 emit_move_insn (target, op0);
24676 ix86_expand_vector_set (true, target, op1, elt);
24681 /* Expand an expression EXP that calls a built-in function,
24682 with result going to TARGET if that's convenient
24683 (and in mode MODE if that's convenient).
24684 SUBTARGET may be used as the target for computing one of EXP's operands.
24685 IGNORE is nonzero if the value is to be ignored. */
24688 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24689 enum machine_mode mode ATTRIBUTE_UNUSED,
24690 int ignore ATTRIBUTE_UNUSED)
24692 const struct builtin_description *d;
24694 enum insn_code icode;
24695 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24696 tree arg0, arg1, arg2;
24697 rtx op0, op1, op2, pat;
24698 enum machine_mode mode0, mode1, mode2;
24699 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24701 /* Determine whether the builtin function is available under the current ISA.
24702 Originally the builtin was not created if it wasn't applicable to the
24703 current ISA based on the command line switches. With function specific
24704 options, we need to check in the context of the function making the call
24705 whether it is supported. */
24706 if (ix86_builtins_isa[fcode].isa
24707 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24709 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24710 NULL, NULL, false);
24713 error ("%qE needs unknown isa option", fndecl);
24716 gcc_assert (opts != NULL);
24717 error ("%qE needs isa option %s", fndecl, opts);
24725 case IX86_BUILTIN_MASKMOVQ:
24726 case IX86_BUILTIN_MASKMOVDQU:
24727 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24728 ? CODE_FOR_mmx_maskmovq
24729 : CODE_FOR_sse2_maskmovdqu);
24730 /* Note the arg order is different from the operand order. */
24731 arg1 = CALL_EXPR_ARG (exp, 0);
24732 arg2 = CALL_EXPR_ARG (exp, 1);
24733 arg0 = CALL_EXPR_ARG (exp, 2);
24734 op0 = expand_normal (arg0);
24735 op1 = expand_normal (arg1);
24736 op2 = expand_normal (arg2);
24737 mode0 = insn_data[icode].operand[0].mode;
24738 mode1 = insn_data[icode].operand[1].mode;
24739 mode2 = insn_data[icode].operand[2].mode;
24741 op0 = force_reg (Pmode, op0);
24742 op0 = gen_rtx_MEM (mode1, op0);
24744 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24745 op0 = copy_to_mode_reg (mode0, op0);
24746 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24747 op1 = copy_to_mode_reg (mode1, op1);
24748 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24749 op2 = copy_to_mode_reg (mode2, op2);
24750 pat = GEN_FCN (icode) (op0, op1, op2);
24756 case IX86_BUILTIN_LDMXCSR:
24757 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24758 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24759 emit_move_insn (target, op0);
24760 emit_insn (gen_sse_ldmxcsr (target));
24763 case IX86_BUILTIN_STMXCSR:
24764 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24765 emit_insn (gen_sse_stmxcsr (target));
24766 return copy_to_mode_reg (SImode, target);
24768 case IX86_BUILTIN_CLFLUSH:
24769 arg0 = CALL_EXPR_ARG (exp, 0);
24770 op0 = expand_normal (arg0);
24771 icode = CODE_FOR_sse2_clflush;
24772 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24773 op0 = copy_to_mode_reg (Pmode, op0);
24775 emit_insn (gen_sse2_clflush (op0));
24778 case IX86_BUILTIN_MONITOR:
24779 arg0 = CALL_EXPR_ARG (exp, 0);
24780 arg1 = CALL_EXPR_ARG (exp, 1);
24781 arg2 = CALL_EXPR_ARG (exp, 2);
24782 op0 = expand_normal (arg0);
24783 op1 = expand_normal (arg1);
24784 op2 = expand_normal (arg2);
24786 op0 = copy_to_mode_reg (Pmode, op0);
24788 op1 = copy_to_mode_reg (SImode, op1);
24790 op2 = copy_to_mode_reg (SImode, op2);
24791 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24794 case IX86_BUILTIN_MWAIT:
24795 arg0 = CALL_EXPR_ARG (exp, 0);
24796 arg1 = CALL_EXPR_ARG (exp, 1);
24797 op0 = expand_normal (arg0);
24798 op1 = expand_normal (arg1);
24800 op0 = copy_to_mode_reg (SImode, op0);
24802 op1 = copy_to_mode_reg (SImode, op1);
24803 emit_insn (gen_sse3_mwait (op0, op1));
24806 case IX86_BUILTIN_VEC_INIT_V2SI:
24807 case IX86_BUILTIN_VEC_INIT_V4HI:
24808 case IX86_BUILTIN_VEC_INIT_V8QI:
24809 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24811 case IX86_BUILTIN_VEC_EXT_V2DF:
24812 case IX86_BUILTIN_VEC_EXT_V2DI:
24813 case IX86_BUILTIN_VEC_EXT_V4SF:
24814 case IX86_BUILTIN_VEC_EXT_V4SI:
24815 case IX86_BUILTIN_VEC_EXT_V8HI:
24816 case IX86_BUILTIN_VEC_EXT_V2SI:
24817 case IX86_BUILTIN_VEC_EXT_V4HI:
24818 case IX86_BUILTIN_VEC_EXT_V16QI:
24819 return ix86_expand_vec_ext_builtin (exp, target);
24821 case IX86_BUILTIN_VEC_SET_V2DI:
24822 case IX86_BUILTIN_VEC_SET_V4SF:
24823 case IX86_BUILTIN_VEC_SET_V4SI:
24824 case IX86_BUILTIN_VEC_SET_V8HI:
24825 case IX86_BUILTIN_VEC_SET_V4HI:
24826 case IX86_BUILTIN_VEC_SET_V16QI:
24827 return ix86_expand_vec_set_builtin (exp);
24829 case IX86_BUILTIN_INFQ:
24831 REAL_VALUE_TYPE inf;
24835 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24837 tmp = validize_mem (force_const_mem (mode, tmp));
24840 target = gen_reg_rtx (mode);
24842 emit_move_insn (target, tmp);
24850 for (i = 0, d = bdesc_special_args;
24851 i < ARRAY_SIZE (bdesc_special_args);
24853 if (d->code == fcode)
24854 return ix86_expand_special_args_builtin (d, exp, target);
24856 for (i = 0, d = bdesc_args;
24857 i < ARRAY_SIZE (bdesc_args);
24859 if (d->code == fcode)
24862 case IX86_BUILTIN_FABSQ:
24863 case IX86_BUILTIN_COPYSIGNQ:
24865 /* Emit a normal call if SSE2 isn't available. */
24866 return expand_call (exp, target, ignore);
24868 return ix86_expand_args_builtin (d, exp, target);
24871 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24872 if (d->code == fcode)
24873 return ix86_expand_sse_comi (d, exp, target);
24875 for (i = 0, d = bdesc_pcmpestr;
24876 i < ARRAY_SIZE (bdesc_pcmpestr);
24878 if (d->code == fcode)
24879 return ix86_expand_sse_pcmpestr (d, exp, target);
24881 for (i = 0, d = bdesc_pcmpistr;
24882 i < ARRAY_SIZE (bdesc_pcmpistr);
24884 if (d->code == fcode)
24885 return ix86_expand_sse_pcmpistr (d, exp, target);
24887 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
24888 if (d->code == fcode)
24889 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
24890 (enum multi_arg_type)d->flag,
24893 gcc_unreachable ();
24896 /* Returns a function decl for a vectorized version of the builtin function
24897 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24898 if it is not available. */
24901 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24904 enum machine_mode in_mode, out_mode;
24907 if (TREE_CODE (type_out) != VECTOR_TYPE
24908 || TREE_CODE (type_in) != VECTOR_TYPE)
24911 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24912 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24913 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24914 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24918 case BUILT_IN_SQRT:
24919 if (out_mode == DFmode && out_n == 2
24920 && in_mode == DFmode && in_n == 2)
24921 return ix86_builtins[IX86_BUILTIN_SQRTPD];
24924 case BUILT_IN_SQRTF:
24925 if (out_mode == SFmode && out_n == 4
24926 && in_mode == SFmode && in_n == 4)
24927 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
24930 case BUILT_IN_LRINT:
24931 if (out_mode == SImode && out_n == 4
24932 && in_mode == DFmode && in_n == 2)
24933 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
24936 case BUILT_IN_LRINTF:
24937 if (out_mode == SImode && out_n == 4
24938 && in_mode == SFmode && in_n == 4)
24939 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
24946 /* Dispatch to a handler for a vectorization library. */
24947 if (ix86_veclib_handler)
24948 return (*ix86_veclib_handler)(fn, type_out, type_in);
24953 /* Handler for an SVML-style interface to
24954 a library with vectorized intrinsics. */
24957 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
24960 tree fntype, new_fndecl, args;
24963 enum machine_mode el_mode, in_mode;
24966 /* The SVML is suitable for unsafe math only. */
24967 if (!flag_unsafe_math_optimizations)
24970 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24971 n = TYPE_VECTOR_SUBPARTS (type_out);
24972 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24973 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24974 if (el_mode != in_mode
24982 case BUILT_IN_LOG10:
24984 case BUILT_IN_TANH:
24986 case BUILT_IN_ATAN:
24987 case BUILT_IN_ATAN2:
24988 case BUILT_IN_ATANH:
24989 case BUILT_IN_CBRT:
24990 case BUILT_IN_SINH:
24992 case BUILT_IN_ASINH:
24993 case BUILT_IN_ASIN:
24994 case BUILT_IN_COSH:
24996 case BUILT_IN_ACOSH:
24997 case BUILT_IN_ACOS:
24998 if (el_mode != DFmode || n != 2)
25002 case BUILT_IN_EXPF:
25003 case BUILT_IN_LOGF:
25004 case BUILT_IN_LOG10F:
25005 case BUILT_IN_POWF:
25006 case BUILT_IN_TANHF:
25007 case BUILT_IN_TANF:
25008 case BUILT_IN_ATANF:
25009 case BUILT_IN_ATAN2F:
25010 case BUILT_IN_ATANHF:
25011 case BUILT_IN_CBRTF:
25012 case BUILT_IN_SINHF:
25013 case BUILT_IN_SINF:
25014 case BUILT_IN_ASINHF:
25015 case BUILT_IN_ASINF:
25016 case BUILT_IN_COSHF:
25017 case BUILT_IN_COSF:
25018 case BUILT_IN_ACOSHF:
25019 case BUILT_IN_ACOSF:
25020 if (el_mode != SFmode || n != 4)
25028 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25030 if (fn == BUILT_IN_LOGF)
25031 strcpy (name, "vmlsLn4");
25032 else if (fn == BUILT_IN_LOG)
25033 strcpy (name, "vmldLn2");
25036 sprintf (name, "vmls%s", bname+10);
25037 name[strlen (name)-1] = '4';
25040 sprintf (name, "vmld%s2", bname+10);
25042 /* Convert to uppercase. */
25046 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25047 args = TREE_CHAIN (args))
25051 fntype = build_function_type_list (type_out, type_in, NULL);
25053 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25055 /* Build a function declaration for the vectorized function. */
25056 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25057 TREE_PUBLIC (new_fndecl) = 1;
25058 DECL_EXTERNAL (new_fndecl) = 1;
25059 DECL_IS_NOVOPS (new_fndecl) = 1;
25060 TREE_READONLY (new_fndecl) = 1;
25065 /* Handler for an ACML-style interface to
25066 a library with vectorized intrinsics. */
25069 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25071 char name[20] = "__vr.._";
25072 tree fntype, new_fndecl, args;
25075 enum machine_mode el_mode, in_mode;
25078 /* The ACML is 64bits only and suitable for unsafe math only as
25079 it does not correctly support parts of IEEE with the required
25080 precision such as denormals. */
25082 || !flag_unsafe_math_optimizations)
25085 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25086 n = TYPE_VECTOR_SUBPARTS (type_out);
25087 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25088 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25089 if (el_mode != in_mode
25099 case BUILT_IN_LOG2:
25100 case BUILT_IN_LOG10:
25103 if (el_mode != DFmode
25108 case BUILT_IN_SINF:
25109 case BUILT_IN_COSF:
25110 case BUILT_IN_EXPF:
25111 case BUILT_IN_POWF:
25112 case BUILT_IN_LOGF:
25113 case BUILT_IN_LOG2F:
25114 case BUILT_IN_LOG10F:
25117 if (el_mode != SFmode
25126 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25127 sprintf (name + 7, "%s", bname+10);
25130 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25131 args = TREE_CHAIN (args))
25135 fntype = build_function_type_list (type_out, type_in, NULL);
25137 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25139 /* Build a function declaration for the vectorized function. */
25140 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25141 TREE_PUBLIC (new_fndecl) = 1;
25142 DECL_EXTERNAL (new_fndecl) = 1;
25143 DECL_IS_NOVOPS (new_fndecl) = 1;
25144 TREE_READONLY (new_fndecl) = 1;
25150 /* Returns a decl of a function that implements conversion of an integer vector
25151 into a floating-point vector, or vice-versa. TYPE is the type of the integer
25152 side of the conversion.
25153 Return NULL_TREE if it is not available. */
25156 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
25158 if (TREE_CODE (type) != VECTOR_TYPE)
25164 switch (TYPE_MODE (type))
25167 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
25172 case FIX_TRUNC_EXPR:
25173 switch (TYPE_MODE (type))
25176 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
25186 /* Returns a code for a target-specific builtin that implements
25187 reciprocal of the function, or NULL_TREE if not available. */
25190 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
25191 bool sqrt ATTRIBUTE_UNUSED)
25193 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
25194 && flag_finite_math_only && !flag_trapping_math
25195 && flag_unsafe_math_optimizations))
25199 /* Machine dependent builtins. */
25202 /* Vectorized version of sqrt to rsqrt conversion. */
25203 case IX86_BUILTIN_SQRTPS_NR:
25204 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
25210 /* Normal builtins. */
25213 /* Sqrt to rsqrt conversion. */
25214 case BUILT_IN_SQRTF:
25215 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25222 /* Store OPERAND to the memory after reload is completed. This means
25223 that we can't easily use assign_stack_local. */
25225 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25229 gcc_assert (reload_completed);
25230 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25232 result = gen_rtx_MEM (mode,
25233 gen_rtx_PLUS (Pmode,
25235 GEN_INT (-RED_ZONE_SIZE)));
25236 emit_move_insn (result, operand);
25238 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25244 operand = gen_lowpart (DImode, operand);
25248 gen_rtx_SET (VOIDmode,
25249 gen_rtx_MEM (DImode,
25250 gen_rtx_PRE_DEC (DImode,
25251 stack_pointer_rtx)),
25255 gcc_unreachable ();
25257 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25266 split_di (&operand, 1, operands, operands + 1);
25268 gen_rtx_SET (VOIDmode,
25269 gen_rtx_MEM (SImode,
25270 gen_rtx_PRE_DEC (Pmode,
25271 stack_pointer_rtx)),
25274 gen_rtx_SET (VOIDmode,
25275 gen_rtx_MEM (SImode,
25276 gen_rtx_PRE_DEC (Pmode,
25277 stack_pointer_rtx)),
25282 /* Store HImodes as SImodes. */
25283 operand = gen_lowpart (SImode, operand);
25287 gen_rtx_SET (VOIDmode,
25288 gen_rtx_MEM (GET_MODE (operand),
25289 gen_rtx_PRE_DEC (SImode,
25290 stack_pointer_rtx)),
25294 gcc_unreachable ();
25296 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25301 /* Free operand from the memory. */
25303 ix86_free_from_memory (enum machine_mode mode)
25305 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25309 if (mode == DImode || TARGET_64BIT)
25313 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25314 to pop or add instruction if registers are available. */
25315 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25316 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25321 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25322 QImode must go into class Q_REGS.
25323 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25324 movdf to do mem-to-mem moves through integer regs. */
25326 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25328 enum machine_mode mode = GET_MODE (x);
25330 /* We're only allowed to return a subclass of CLASS. Many of the
25331 following checks fail for NO_REGS, so eliminate that early. */
25332 if (regclass == NO_REGS)
25335 /* All classes can load zeros. */
25336 if (x == CONST0_RTX (mode))
25339 /* Force constants into memory if we are loading a (nonzero) constant into
25340 an MMX or SSE register. This is because there are no MMX/SSE instructions
25341 to load from a constant. */
25343 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25346 /* Prefer SSE regs only, if we can use them for math. */
25347 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25348 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25350 /* Floating-point constants need more complex checks. */
25351 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25353 /* General regs can load everything. */
25354 if (reg_class_subset_p (regclass, GENERAL_REGS))
25357 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25358 zero above. We only want to wind up preferring 80387 registers if
25359 we plan on doing computation with them. */
25361 && standard_80387_constant_p (x))
25363 /* Limit class to non-sse. */
25364 if (regclass == FLOAT_SSE_REGS)
25366 if (regclass == FP_TOP_SSE_REGS)
25368 if (regclass == FP_SECOND_SSE_REGS)
25369 return FP_SECOND_REG;
25370 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25377 /* Generally when we see PLUS here, it's the function invariant
25378 (plus soft-fp const_int). Which can only be computed into general
25380 if (GET_CODE (x) == PLUS)
25381 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25383 /* QImode constants are easy to load, but non-constant QImode data
25384 must go into Q_REGS. */
25385 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25387 if (reg_class_subset_p (regclass, Q_REGS))
25389 if (reg_class_subset_p (Q_REGS, regclass))
25397 /* Discourage putting floating-point values in SSE registers unless
25398 SSE math is being used, and likewise for the 387 registers. */
25400 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25402 enum machine_mode mode = GET_MODE (x);
25404 /* Restrict the output reload class to the register bank that we are doing
25405 math on. If we would like not to return a subset of CLASS, reject this
25406 alternative: if reload cannot do this, it will still use its choice. */
25407 mode = GET_MODE (x);
25408 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25409 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25411 if (X87_FLOAT_MODE_P (mode))
25413 if (regclass == FP_TOP_SSE_REGS)
25415 else if (regclass == FP_SECOND_SSE_REGS)
25416 return FP_SECOND_REG;
25418 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25424 static enum reg_class
25425 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25426 enum machine_mode mode,
25427 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25429 /* QImode spills from non-QI registers require
25430 intermediate register on 32bit targets. */
25431 if (!in_p && mode == QImode && !TARGET_64BIT
25432 && (rclass == GENERAL_REGS
25433 || rclass == LEGACY_REGS
25434 || rclass == INDEX_REGS))
25443 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25444 regno = true_regnum (x);
25446 /* Return Q_REGS if the operand is in memory. */
25454 /* If we are copying between general and FP registers, we need a memory
25455 location. The same is true for SSE and MMX registers.
25457 To optimize register_move_cost performance, allow inline variant.
25459 The macro can't work reliably when one of the CLASSES is class containing
25460 registers from multiple units (SSE, MMX, integer). We avoid this by never
25461 combining those units in single alternative in the machine description.
25462 Ensure that this constraint holds to avoid unexpected surprises.
25464 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25465 enforce these sanity checks. */
25468 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25469 enum machine_mode mode, int strict)
25471 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25472 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25473 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25474 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25475 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25476 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25478 gcc_assert (!strict);
25482 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25485 /* ??? This is a lie. We do have moves between mmx/general, and for
25486 mmx/sse2. But by saying we need secondary memory we discourage the
25487 register allocator from using the mmx registers unless needed. */
25488 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25491 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25493 /* SSE1 doesn't have any direct moves from other classes. */
25497 /* If the target says that inter-unit moves are more expensive
25498 than moving through memory, then don't generate them. */
25499 if (!TARGET_INTER_UNIT_MOVES)
25502 /* Between SSE and general, we have moves no larger than word size. */
25503 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25511 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25512 enum machine_mode mode, int strict)
25514 return inline_secondary_memory_needed (class1, class2, mode, strict);
25517 /* Return true if the registers in CLASS cannot represent the change from
25518 modes FROM to TO. */
25521 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25522 enum reg_class regclass)
25527 /* x87 registers can't do subreg at all, as all values are reformatted
25528 to extended precision. */
25529 if (MAYBE_FLOAT_CLASS_P (regclass))
25532 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25534 /* Vector registers do not support QI or HImode loads. If we don't
25535 disallow a change to these modes, reload will assume it's ok to
25536 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25537 the vec_dupv4hi pattern. */
25538 if (GET_MODE_SIZE (from) < 4)
25541 /* Vector registers do not support subreg with nonzero offsets, which
25542 are otherwise valid for integer registers. Since we can't see
25543 whether we have a nonzero offset from here, prohibit all
25544 nonparadoxical subregs changing size. */
25545 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25552 /* Return the cost of moving data of mode M between a
25553 register and memory. A value of 2 is the default; this cost is
25554 relative to those in `REGISTER_MOVE_COST'.
25556 This function is used extensively by register_move_cost that is used to
25557 build tables at startup. Make it inline in this case.
25558 When IN is 2, return maximum of in and out move cost.
25560 If moving between registers and memory is more expensive than
25561 between two registers, you should define this macro to express the
25564 Model also increased moving costs of QImode registers in non
25568 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25572 if (FLOAT_CLASS_P (regclass))
25590 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25591 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25593 if (SSE_CLASS_P (regclass))
25596 switch (GET_MODE_SIZE (mode))
25611 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25612 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25614 if (MMX_CLASS_P (regclass))
25617 switch (GET_MODE_SIZE (mode))
25629 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25630 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25632 switch (GET_MODE_SIZE (mode))
25635 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25638 return ix86_cost->int_store[0];
25639 if (TARGET_PARTIAL_REG_DEPENDENCY
25640 && optimize_function_for_speed_p (cfun))
25641 cost = ix86_cost->movzbl_load;
25643 cost = ix86_cost->int_load[0];
25645 return MAX (cost, ix86_cost->int_store[0]);
25651 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25653 return ix86_cost->movzbl_load;
25655 return ix86_cost->int_store[0] + 4;
25660 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25661 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25663 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25664 if (mode == TFmode)
25667 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25669 cost = ix86_cost->int_load[2];
25671 cost = ix86_cost->int_store[2];
25672 return (cost * (((int) GET_MODE_SIZE (mode)
25673 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25678 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25680 return inline_memory_move_cost (mode, regclass, in);
25684 /* Return the cost of moving data from a register in class CLASS1 to
25685 one in class CLASS2.
25687 It is not required that the cost always equal 2 when FROM is the same as TO;
25688 on some machines it is expensive to move between registers if they are not
25689 general registers. */
25692 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25693 enum reg_class class2)
25695 /* In case we require secondary memory, compute cost of the store followed
25696 by load. In order to avoid bad register allocation choices, we need
25697 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25699 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25703 cost += inline_memory_move_cost (mode, class1, 2);
25704 cost += inline_memory_move_cost (mode, class2, 2);
25706 /* In case of copying from general_purpose_register we may emit multiple
25707 stores followed by single load causing memory size mismatch stall.
25708 Count this as arbitrarily high cost of 20. */
25709 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25712 /* In the case of FP/MMX moves, the registers actually overlap, and we
25713 have to switch modes in order to treat them differently. */
25714 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25715 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25721 /* Moves between SSE/MMX and integer unit are expensive. */
25722 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25723 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25725 /* ??? By keeping returned value relatively high, we limit the number
25726 of moves between integer and MMX/SSE registers for all targets.
25727 Additionally, high value prevents problem with x86_modes_tieable_p(),
25728 where integer modes in MMX/SSE registers are not tieable
25729 because of missing QImode and HImode moves to, from or between
25730 MMX/SSE registers. */
25731 return MAX (8, ix86_cost->mmxsse_to_integer);
25733 if (MAYBE_FLOAT_CLASS_P (class1))
25734 return ix86_cost->fp_move;
25735 if (MAYBE_SSE_CLASS_P (class1))
25736 return ix86_cost->sse_move;
25737 if (MAYBE_MMX_CLASS_P (class1))
25738 return ix86_cost->mmx_move;
25742 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25745 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25747 /* Flags and only flags can only hold CCmode values. */
25748 if (CC_REGNO_P (regno))
25749 return GET_MODE_CLASS (mode) == MODE_CC;
25750 if (GET_MODE_CLASS (mode) == MODE_CC
25751 || GET_MODE_CLASS (mode) == MODE_RANDOM
25752 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25754 if (FP_REGNO_P (regno))
25755 return VALID_FP_MODE_P (mode);
25756 if (SSE_REGNO_P (regno))
25758 /* We implement the move patterns for all vector modes into and
25759 out of SSE registers, even when no operation instructions
25760 are available. OImode move is available only when AVX is
25762 return ((TARGET_AVX && mode == OImode)
25763 || VALID_AVX256_REG_MODE (mode)
25764 || VALID_SSE_REG_MODE (mode)
25765 || VALID_SSE2_REG_MODE (mode)
25766 || VALID_MMX_REG_MODE (mode)
25767 || VALID_MMX_REG_MODE_3DNOW (mode));
25769 if (MMX_REGNO_P (regno))
25771 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25772 so if the register is available at all, then we can move data of
25773 the given mode into or out of it. */
25774 return (VALID_MMX_REG_MODE (mode)
25775 || VALID_MMX_REG_MODE_3DNOW (mode));
25778 if (mode == QImode)
25780 /* Take care for QImode values - they can be in non-QI regs,
25781 but then they do cause partial register stalls. */
25782 if (regno <= BX_REG || TARGET_64BIT)
25784 if (!TARGET_PARTIAL_REG_STALL)
25786 return reload_in_progress || reload_completed;
25788 /* We handle both integer and floats in the general purpose registers. */
25789 else if (VALID_INT_MODE_P (mode))
25791 else if (VALID_FP_MODE_P (mode))
25793 else if (VALID_DFP_MODE_P (mode))
25795 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25796 on to use that value in smaller contexts, this can easily force a
25797 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25798 supporting DImode, allow it. */
25799 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25805 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25806 tieable integer mode. */
25809 ix86_tieable_integer_mode_p (enum machine_mode mode)
25818 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25821 return TARGET_64BIT;
25828 /* Return true if MODE1 is accessible in a register that can hold MODE2
25829 without copying. That is, all register classes that can hold MODE2
25830 can also hold MODE1. */
25833 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25835 if (mode1 == mode2)
25838 if (ix86_tieable_integer_mode_p (mode1)
25839 && ix86_tieable_integer_mode_p (mode2))
25842 /* MODE2 being XFmode implies fp stack or general regs, which means we
25843 can tie any smaller floating point modes to it. Note that we do not
25844 tie this with TFmode. */
25845 if (mode2 == XFmode)
25846 return mode1 == SFmode || mode1 == DFmode;
25848 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25849 that we can tie it with SFmode. */
25850 if (mode2 == DFmode)
25851 return mode1 == SFmode;
25853 /* If MODE2 is only appropriate for an SSE register, then tie with
25854 any other mode acceptable to SSE registers. */
25855 if (GET_MODE_SIZE (mode2) == 16
25856 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25857 return (GET_MODE_SIZE (mode1) == 16
25858 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25860 /* If MODE2 is appropriate for an MMX register, then tie
25861 with any other mode acceptable to MMX registers. */
25862 if (GET_MODE_SIZE (mode2) == 8
25863 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25864 return (GET_MODE_SIZE (mode1) == 8
25865 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25870 /* Compute a (partial) cost for rtx X. Return true if the complete
25871 cost has been computed, and false if subexpressions should be
25872 scanned. In either case, *TOTAL contains the cost result. */
25875 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25877 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25878 enum machine_mode mode = GET_MODE (x);
25879 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25887 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
25889 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
25891 else if (flag_pic && SYMBOLIC_CONST (x)
25893 || (!GET_CODE (x) != LABEL_REF
25894 && (GET_CODE (x) != SYMBOL_REF
25895 || !SYMBOL_REF_LOCAL_P (x)))))
25902 if (mode == VOIDmode)
25905 switch (standard_80387_constant_p (x))
25910 default: /* Other constants */
25915 /* Start with (MEM (SYMBOL_REF)), since that's where
25916 it'll probably end up. Add a penalty for size. */
25917 *total = (COSTS_N_INSNS (1)
25918 + (flag_pic != 0 && !TARGET_64BIT)
25919 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
25925 /* The zero extensions is often completely free on x86_64, so make
25926 it as cheap as possible. */
25927 if (TARGET_64BIT && mode == DImode
25928 && GET_MODE (XEXP (x, 0)) == SImode)
25930 else if (TARGET_ZERO_EXTEND_WITH_AND)
25931 *total = cost->add;
25933 *total = cost->movzx;
25937 *total = cost->movsx;
25941 if (CONST_INT_P (XEXP (x, 1))
25942 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
25944 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25947 *total = cost->add;
25950 if ((value == 2 || value == 3)
25951 && cost->lea <= cost->shift_const)
25953 *total = cost->lea;
25963 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
25965 if (CONST_INT_P (XEXP (x, 1)))
25967 if (INTVAL (XEXP (x, 1)) > 32)
25968 *total = cost->shift_const + COSTS_N_INSNS (2);
25970 *total = cost->shift_const * 2;
25974 if (GET_CODE (XEXP (x, 1)) == AND)
25975 *total = cost->shift_var * 2;
25977 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
25982 if (CONST_INT_P (XEXP (x, 1)))
25983 *total = cost->shift_const;
25985 *total = cost->shift_var;
25990 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25992 /* ??? SSE scalar cost should be used here. */
25993 *total = cost->fmul;
25996 else if (X87_FLOAT_MODE_P (mode))
25998 *total = cost->fmul;
26001 else if (FLOAT_MODE_P (mode))
26003 /* ??? SSE vector cost should be used here. */
26004 *total = cost->fmul;
26009 rtx op0 = XEXP (x, 0);
26010 rtx op1 = XEXP (x, 1);
26012 if (CONST_INT_P (XEXP (x, 1)))
26014 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26015 for (nbits = 0; value != 0; value &= value - 1)
26019 /* This is arbitrary. */
26022 /* Compute costs correctly for widening multiplication. */
26023 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26024 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26025 == GET_MODE_SIZE (mode))
26027 int is_mulwiden = 0;
26028 enum machine_mode inner_mode = GET_MODE (op0);
26030 if (GET_CODE (op0) == GET_CODE (op1))
26031 is_mulwiden = 1, op1 = XEXP (op1, 0);
26032 else if (CONST_INT_P (op1))
26034 if (GET_CODE (op0) == SIGN_EXTEND)
26035 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26038 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26042 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26045 *total = (cost->mult_init[MODE_INDEX (mode)]
26046 + nbits * cost->mult_bit
26047 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26056 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26057 /* ??? SSE cost should be used here. */
26058 *total = cost->fdiv;
26059 else if (X87_FLOAT_MODE_P (mode))
26060 *total = cost->fdiv;
26061 else if (FLOAT_MODE_P (mode))
26062 /* ??? SSE vector cost should be used here. */
26063 *total = cost->fdiv;
26065 *total = cost->divide[MODE_INDEX (mode)];
26069 if (GET_MODE_CLASS (mode) == MODE_INT
26070 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26072 if (GET_CODE (XEXP (x, 0)) == PLUS
26073 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26074 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26075 && CONSTANT_P (XEXP (x, 1)))
26077 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26078 if (val == 2 || val == 4 || val == 8)
26080 *total = cost->lea;
26081 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26082 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26083 outer_code, speed);
26084 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26088 else if (GET_CODE (XEXP (x, 0)) == MULT
26089 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26091 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26092 if (val == 2 || val == 4 || val == 8)
26094 *total = cost->lea;
26095 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26096 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26100 else if (GET_CODE (XEXP (x, 0)) == PLUS)
26102 *total = cost->lea;
26103 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26104 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26105 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26112 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26114 /* ??? SSE cost should be used here. */
26115 *total = cost->fadd;
26118 else if (X87_FLOAT_MODE_P (mode))
26120 *total = cost->fadd;
26123 else if (FLOAT_MODE_P (mode))
26125 /* ??? SSE vector cost should be used here. */
26126 *total = cost->fadd;
26134 if (!TARGET_64BIT && mode == DImode)
26136 *total = (cost->add * 2
26137 + (rtx_cost (XEXP (x, 0), outer_code, speed)
26138 << (GET_MODE (XEXP (x, 0)) != DImode))
26139 + (rtx_cost (XEXP (x, 1), outer_code, speed)
26140 << (GET_MODE (XEXP (x, 1)) != DImode)));
26146 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26148 /* ??? SSE cost should be used here. */
26149 *total = cost->fchs;
26152 else if (X87_FLOAT_MODE_P (mode))
26154 *total = cost->fchs;
26157 else if (FLOAT_MODE_P (mode))
26159 /* ??? SSE vector cost should be used here. */
26160 *total = cost->fchs;
26166 if (!TARGET_64BIT && mode == DImode)
26167 *total = cost->add * 2;
26169 *total = cost->add;
26173 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
26174 && XEXP (XEXP (x, 0), 1) == const1_rtx
26175 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
26176 && XEXP (x, 1) == const0_rtx)
26178 /* This kind of construct is implemented using test[bwl].
26179 Treat it as if we had an AND. */
26180 *total = (cost->add
26181 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
26182 + rtx_cost (const1_rtx, outer_code, speed));
26188 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
26193 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26194 /* ??? SSE cost should be used here. */
26195 *total = cost->fabs;
26196 else if (X87_FLOAT_MODE_P (mode))
26197 *total = cost->fabs;
26198 else if (FLOAT_MODE_P (mode))
26199 /* ??? SSE vector cost should be used here. */
26200 *total = cost->fabs;
26204 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26205 /* ??? SSE cost should be used here. */
26206 *total = cost->fsqrt;
26207 else if (X87_FLOAT_MODE_P (mode))
26208 *total = cost->fsqrt;
26209 else if (FLOAT_MODE_P (mode))
26210 /* ??? SSE vector cost should be used here. */
26211 *total = cost->fsqrt;
26215 if (XINT (x, 1) == UNSPEC_TP)
26226 static int current_machopic_label_num;
26228 /* Given a symbol name and its associated stub, write out the
26229 definition of the stub. */
26232 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26234 unsigned int length;
26235 char *binder_name, *symbol_name, lazy_ptr_name[32];
26236 int label = ++current_machopic_label_num;
26238 /* For 64-bit we shouldn't get here. */
26239 gcc_assert (!TARGET_64BIT);
26241 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26242 symb = (*targetm.strip_name_encoding) (symb);
26244 length = strlen (stub);
26245 binder_name = XALLOCAVEC (char, length + 32);
26246 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26248 length = strlen (symb);
26249 symbol_name = XALLOCAVEC (char, length + 32);
26250 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26252 sprintf (lazy_ptr_name, "L%d$lz", label);
26255 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26257 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26259 fprintf (file, "%s:\n", stub);
26260 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26264 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26265 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26266 fprintf (file, "\tjmp\t*%%edx\n");
26269 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26271 fprintf (file, "%s:\n", binder_name);
26275 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26276 fprintf (file, "\tpushl\t%%eax\n");
26279 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26281 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
26283 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26284 fprintf (file, "%s:\n", lazy_ptr_name);
26285 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26286 fprintf (file, "\t.long %s\n", binder_name);
26290 darwin_x86_file_end (void)
26292 darwin_file_end ();
26295 #endif /* TARGET_MACHO */
26297 /* Order the registers for register allocator. */
26300 x86_order_regs_for_local_alloc (void)
26305 /* First allocate the local general purpose registers. */
26306 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26307 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26308 reg_alloc_order [pos++] = i;
26310 /* Global general purpose registers. */
26311 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26312 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26313 reg_alloc_order [pos++] = i;
26315 /* x87 registers come first in case we are doing FP math
26317 if (!TARGET_SSE_MATH)
26318 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26319 reg_alloc_order [pos++] = i;
26321 /* SSE registers. */
26322 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26323 reg_alloc_order [pos++] = i;
26324 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26325 reg_alloc_order [pos++] = i;
26327 /* x87 registers. */
26328 if (TARGET_SSE_MATH)
26329 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26330 reg_alloc_order [pos++] = i;
26332 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26333 reg_alloc_order [pos++] = i;
26335 /* Initialize the rest of array as we do not allocate some registers
26337 while (pos < FIRST_PSEUDO_REGISTER)
26338 reg_alloc_order [pos++] = 0;
26341 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26342 struct attribute_spec.handler. */
26344 ix86_handle_abi_attribute (tree *node, tree name,
26345 tree args ATTRIBUTE_UNUSED,
26346 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26348 if (TREE_CODE (*node) != FUNCTION_TYPE
26349 && TREE_CODE (*node) != METHOD_TYPE
26350 && TREE_CODE (*node) != FIELD_DECL
26351 && TREE_CODE (*node) != TYPE_DECL)
26353 warning (OPT_Wattributes, "%qs attribute only applies to functions",
26354 IDENTIFIER_POINTER (name));
26355 *no_add_attrs = true;
26360 warning (OPT_Wattributes, "%qs attribute only available for 64-bit",
26361 IDENTIFIER_POINTER (name));
26362 *no_add_attrs = true;
26366 /* Can combine regparm with all attributes but fastcall. */
26367 if (is_attribute_p ("ms_abi", name))
26369 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26371 error ("ms_abi and sysv_abi attributes are not compatible");
26376 else if (is_attribute_p ("sysv_abi", name))
26378 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26380 error ("ms_abi and sysv_abi attributes are not compatible");
26389 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26390 struct attribute_spec.handler. */
26392 ix86_handle_struct_attribute (tree *node, tree name,
26393 tree args ATTRIBUTE_UNUSED,
26394 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26397 if (DECL_P (*node))
26399 if (TREE_CODE (*node) == TYPE_DECL)
26400 type = &TREE_TYPE (*node);
26405 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26406 || TREE_CODE (*type) == UNION_TYPE)))
26408 warning (OPT_Wattributes, "%qs attribute ignored",
26409 IDENTIFIER_POINTER (name));
26410 *no_add_attrs = true;
26413 else if ((is_attribute_p ("ms_struct", name)
26414 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26415 || ((is_attribute_p ("gcc_struct", name)
26416 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26418 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
26419 IDENTIFIER_POINTER (name));
26420 *no_add_attrs = true;
26427 ix86_ms_bitfield_layout_p (const_tree record_type)
26429 return (TARGET_MS_BITFIELD_LAYOUT &&
26430 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26431 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26434 /* Returns an expression indicating where the this parameter is
26435 located on entry to the FUNCTION. */
26438 x86_this_parameter (tree function)
26440 tree type = TREE_TYPE (function);
26441 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26446 const int *parm_regs;
26448 if (ix86_function_type_abi (type) == MS_ABI)
26449 parm_regs = x86_64_ms_abi_int_parameter_registers;
26451 parm_regs = x86_64_int_parameter_registers;
26452 return gen_rtx_REG (DImode, parm_regs[aggr]);
26455 nregs = ix86_function_regparm (type, function);
26457 if (nregs > 0 && !stdarg_p (type))
26461 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26462 regno = aggr ? DX_REG : CX_REG;
26470 return gen_rtx_MEM (SImode,
26471 plus_constant (stack_pointer_rtx, 4));
26474 return gen_rtx_REG (SImode, regno);
26477 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26480 /* Determine whether x86_output_mi_thunk can succeed. */
26483 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26484 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26485 HOST_WIDE_INT vcall_offset, const_tree function)
26487 /* 64-bit can handle anything. */
26491 /* For 32-bit, everything's fine if we have one free register. */
26492 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26495 /* Need a free register for vcall_offset. */
26499 /* Need a free register for GOT references. */
26500 if (flag_pic && !(*targetm.binds_local_p) (function))
26503 /* Otherwise ok. */
26507 /* Output the assembler code for a thunk function. THUNK_DECL is the
26508 declaration for the thunk function itself, FUNCTION is the decl for
26509 the target function. DELTA is an immediate constant offset to be
26510 added to THIS. If VCALL_OFFSET is nonzero, the word at
26511 *(*this + vcall_offset) should be added to THIS. */
26514 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26515 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26516 HOST_WIDE_INT vcall_offset, tree function)
26519 rtx this_param = x86_this_parameter (function);
26522 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26523 pull it in now and let DELTA benefit. */
26524 if (REG_P (this_param))
26525 this_reg = this_param;
26526 else if (vcall_offset)
26528 /* Put the this parameter into %eax. */
26529 xops[0] = this_param;
26530 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26531 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26534 this_reg = NULL_RTX;
26536 /* Adjust the this parameter by a fixed constant. */
26539 xops[0] = GEN_INT (delta);
26540 xops[1] = this_reg ? this_reg : this_param;
26543 if (!x86_64_general_operand (xops[0], DImode))
26545 tmp = gen_rtx_REG (DImode, R10_REG);
26547 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26549 xops[1] = this_param;
26551 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26554 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26557 /* Adjust the this parameter by a value stored in the vtable. */
26561 tmp = gen_rtx_REG (DImode, R10_REG);
26564 int tmp_regno = CX_REG;
26565 if (lookup_attribute ("fastcall",
26566 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26567 tmp_regno = AX_REG;
26568 tmp = gen_rtx_REG (SImode, tmp_regno);
26571 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26573 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26575 /* Adjust the this parameter. */
26576 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26577 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26579 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26580 xops[0] = GEN_INT (vcall_offset);
26582 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26583 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26585 xops[1] = this_reg;
26586 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26589 /* If necessary, drop THIS back to its stack slot. */
26590 if (this_reg && this_reg != this_param)
26592 xops[0] = this_reg;
26593 xops[1] = this_param;
26594 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26597 xops[0] = XEXP (DECL_RTL (function), 0);
26600 if (!flag_pic || (*targetm.binds_local_p) (function))
26601 output_asm_insn ("jmp\t%P0", xops);
26602 /* All thunks should be in the same object as their target,
26603 and thus binds_local_p should be true. */
26604 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26605 gcc_unreachable ();
26608 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26609 tmp = gen_rtx_CONST (Pmode, tmp);
26610 tmp = gen_rtx_MEM (QImode, tmp);
26612 output_asm_insn ("jmp\t%A0", xops);
26617 if (!flag_pic || (*targetm.binds_local_p) (function))
26618 output_asm_insn ("jmp\t%P0", xops);
26623 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26624 tmp = (gen_rtx_SYMBOL_REF
26626 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26627 tmp = gen_rtx_MEM (QImode, tmp);
26629 output_asm_insn ("jmp\t%0", xops);
26632 #endif /* TARGET_MACHO */
26634 tmp = gen_rtx_REG (SImode, CX_REG);
26635 output_set_got (tmp, NULL_RTX);
26638 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26639 output_asm_insn ("jmp\t{*}%1", xops);
26645 x86_file_start (void)
26647 default_file_start ();
26649 darwin_file_start ();
26651 if (X86_FILE_START_VERSION_DIRECTIVE)
26652 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26653 if (X86_FILE_START_FLTUSED)
26654 fputs ("\t.global\t__fltused\n", asm_out_file);
26655 if (ix86_asm_dialect == ASM_INTEL)
26656 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26660 x86_field_alignment (tree field, int computed)
26662 enum machine_mode mode;
26663 tree type = TREE_TYPE (field);
26665 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26667 mode = TYPE_MODE (strip_array_types (type));
26668 if (mode == DFmode || mode == DCmode
26669 || GET_MODE_CLASS (mode) == MODE_INT
26670 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26671 return MIN (32, computed);
26675 /* Output assembler code to FILE to increment profiler label # LABELNO
26676 for profiling a function entry. */
26678 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26682 #ifndef NO_PROFILE_COUNTERS
26683 fprintf (file, "\tleaq\t%sP%d@(%%rip),%%r11\n", LPREFIX, labelno);
26686 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26687 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
26689 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26693 #ifndef NO_PROFILE_COUNTERS
26694 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
26695 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
26697 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
26701 #ifndef NO_PROFILE_COUNTERS
26702 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
26703 PROFILE_COUNT_REGISTER);
26705 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26709 /* We don't have exact information about the insn sizes, but we may assume
26710 quite safely that we are informed about all 1 byte insns and memory
26711 address sizes. This is enough to eliminate unnecessary padding in
26715 min_insn_size (rtx insn)
26719 if (!INSN_P (insn) || !active_insn_p (insn))
26722 /* Discard alignments we've emit and jump instructions. */
26723 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26724 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26727 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
26728 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
26731 /* Important case - calls are always 5 bytes.
26732 It is common to have many calls in the row. */
26734 && symbolic_reference_mentioned_p (PATTERN (insn))
26735 && !SIBLING_CALL_P (insn))
26737 if (get_attr_length (insn) <= 1)
26740 /* For normal instructions we may rely on the sizes of addresses
26741 and the presence of symbol to require 4 bytes of encoding.
26742 This is not the case for jumps where references are PC relative. */
26743 if (!JUMP_P (insn))
26745 l = get_attr_length_address (insn);
26746 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26755 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26759 ix86_avoid_jump_misspredicts (void)
26761 rtx insn, start = get_insns ();
26762 int nbytes = 0, njumps = 0;
26765 /* Look for all minimal intervals of instructions containing 4 jumps.
26766 The intervals are bounded by START and INSN. NBYTES is the total
26767 size of instructions in the interval including INSN and not including
26768 START. When the NBYTES is smaller than 16 bytes, it is possible
26769 that the end of START and INSN ends up in the same 16byte page.
26771 The smallest offset in the page INSN can start is the case where START
26772 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26773 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
26775 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
26778 nbytes += min_insn_size (insn);
26780 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
26781 INSN_UID (insn), min_insn_size (insn));
26783 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26784 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26792 start = NEXT_INSN (start);
26793 if ((JUMP_P (start)
26794 && GET_CODE (PATTERN (start)) != ADDR_VEC
26795 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26797 njumps--, isjump = 1;
26800 nbytes -= min_insn_size (start);
26802 gcc_assert (njumps >= 0);
26804 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26805 INSN_UID (start), INSN_UID (insn), nbytes);
26807 if (njumps == 3 && isjump && nbytes < 16)
26809 int padsize = 15 - nbytes + min_insn_size (insn);
26812 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26813 INSN_UID (insn), padsize);
26814 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
26819 /* AMD Athlon works faster
26820 when RET is not destination of conditional jump or directly preceded
26821 by other jump instruction. We avoid the penalty by inserting NOP just
26822 before the RET instructions in such cases. */
26824 ix86_pad_returns (void)
26829 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26831 basic_block bb = e->src;
26832 rtx ret = BB_END (bb);
26834 bool replace = false;
26836 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26837 || optimize_bb_for_size_p (bb))
26839 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26840 if (active_insn_p (prev) || LABEL_P (prev))
26842 if (prev && LABEL_P (prev))
26847 FOR_EACH_EDGE (e, ei, bb->preds)
26848 if (EDGE_FREQUENCY (e) && e->src->index >= 0
26849 && !(e->flags & EDGE_FALLTHRU))
26854 prev = prev_active_insn (ret);
26856 && ((JUMP_P (prev) && any_condjump_p (prev))
26859 /* Empty functions get branch mispredict even when the jump destination
26860 is not visible to us. */
26861 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
26866 emit_insn_before (gen_return_internal_long (), ret);
26872 /* Implement machine specific optimizations. We implement padding of returns
26873 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26877 if (TARGET_PAD_RETURNS && optimize
26878 && optimize_function_for_speed_p (cfun))
26879 ix86_pad_returns ();
26880 if (TARGET_FOUR_JUMP_LIMIT && optimize
26881 && optimize_function_for_speed_p (cfun))
26882 ix86_avoid_jump_misspredicts ();
26885 /* Return nonzero when QImode register that must be represented via REX prefix
26888 x86_extended_QIreg_mentioned_p (rtx insn)
26891 extract_insn_cached (insn);
26892 for (i = 0; i < recog_data.n_operands; i++)
26893 if (REG_P (recog_data.operand[i])
26894 && REGNO (recog_data.operand[i]) > BX_REG)
26899 /* Return nonzero when P points to register encoded via REX prefix.
26900 Called via for_each_rtx. */
26902 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
26904 unsigned int regno;
26907 regno = REGNO (*p);
26908 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
26911 /* Return true when INSN mentions register that must be encoded using REX
26914 x86_extended_reg_mentioned_p (rtx insn)
26916 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
26917 extended_reg_mentioned_1, NULL);
26920 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26921 optabs would emit if we didn't have TFmode patterns. */
26924 x86_emit_floatuns (rtx operands[2])
26926 rtx neglab, donelab, i0, i1, f0, in, out;
26927 enum machine_mode mode, inmode;
26929 inmode = GET_MODE (operands[1]);
26930 gcc_assert (inmode == SImode || inmode == DImode);
26933 in = force_reg (inmode, operands[1]);
26934 mode = GET_MODE (out);
26935 neglab = gen_label_rtx ();
26936 donelab = gen_label_rtx ();
26937 f0 = gen_reg_rtx (mode);
26939 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
26941 expand_float (out, in, 0);
26943 emit_jump_insn (gen_jump (donelab));
26946 emit_label (neglab);
26948 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
26950 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
26952 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
26954 expand_float (f0, i0, 0);
26956 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
26958 emit_label (donelab);
26961 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26962 with all elements equal to VAR. Return true if successful. */
26965 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
26966 rtx target, rtx val)
26968 enum machine_mode hmode, smode, wsmode, wvmode;
26983 val = force_reg (GET_MODE_INNER (mode), val);
26984 x = gen_rtx_VEC_DUPLICATE (mode, val);
26985 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26991 if (TARGET_SSE || TARGET_3DNOW_A)
26993 val = gen_lowpart (SImode, val);
26994 x = gen_rtx_TRUNCATE (HImode, val);
26995 x = gen_rtx_VEC_DUPLICATE (mode, x);
26996 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27018 /* Extend HImode to SImode using a paradoxical SUBREG. */
27019 tmp1 = gen_reg_rtx (SImode);
27020 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27021 /* Insert the SImode value as low element of V4SImode vector. */
27022 tmp2 = gen_reg_rtx (V4SImode);
27023 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27024 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27025 CONST0_RTX (V4SImode),
27027 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27028 /* Cast the V4SImode vector back to a V8HImode vector. */
27029 tmp1 = gen_reg_rtx (V8HImode);
27030 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
27031 /* Duplicate the low short through the whole low SImode word. */
27032 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
27033 /* Cast the V8HImode vector back to a V4SImode vector. */
27034 tmp2 = gen_reg_rtx (V4SImode);
27035 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27036 /* Replicate the low element of the V4SImode vector. */
27037 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27038 /* Cast the V2SImode back to V8HImode, and store in target. */
27039 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
27050 /* Extend QImode to SImode using a paradoxical SUBREG. */
27051 tmp1 = gen_reg_rtx (SImode);
27052 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27053 /* Insert the SImode value as low element of V4SImode vector. */
27054 tmp2 = gen_reg_rtx (V4SImode);
27055 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27056 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27057 CONST0_RTX (V4SImode),
27059 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27060 /* Cast the V4SImode vector back to a V16QImode vector. */
27061 tmp1 = gen_reg_rtx (V16QImode);
27062 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
27063 /* Duplicate the low byte through the whole low SImode word. */
27064 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27065 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27066 /* Cast the V16QImode vector back to a V4SImode vector. */
27067 tmp2 = gen_reg_rtx (V4SImode);
27068 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27069 /* Replicate the low element of the V4SImode vector. */
27070 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27071 /* Cast the V2SImode back to V16QImode, and store in target. */
27072 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
27080 /* Replicate the value once into the next wider mode and recurse. */
27081 val = convert_modes (wsmode, smode, val, true);
27082 x = expand_simple_binop (wsmode, ASHIFT, val,
27083 GEN_INT (GET_MODE_BITSIZE (smode)),
27084 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27085 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
27087 x = gen_reg_rtx (wvmode);
27088 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
27089 gcc_unreachable ();
27090 emit_move_insn (target, gen_lowpart (mode, x));
27113 rtx tmp = gen_reg_rtx (hmode);
27114 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
27115 emit_insn (gen_rtx_SET (VOIDmode, target,
27116 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
27125 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27126 whose ONE_VAR element is VAR, and other elements are zero. Return true
27130 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
27131 rtx target, rtx var, int one_var)
27133 enum machine_mode vsimode;
27136 bool use_vector_set = false;
27141 /* For SSE4.1, we normally use vector set. But if the second
27142 element is zero and inter-unit moves are OK, we use movq
27144 use_vector_set = (TARGET_64BIT
27146 && !(TARGET_INTER_UNIT_MOVES
27152 use_vector_set = TARGET_SSE4_1;
27155 use_vector_set = TARGET_SSE2;
27158 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27165 use_vector_set = TARGET_AVX;
27168 /* Use ix86_expand_vector_set in 64bit mode only. */
27169 use_vector_set = TARGET_AVX && TARGET_64BIT;
27175 if (use_vector_set)
27177 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27178 var = force_reg (GET_MODE_INNER (mode), var);
27179 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27195 var = force_reg (GET_MODE_INNER (mode), var);
27196 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27197 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27202 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27203 new_target = gen_reg_rtx (mode);
27205 new_target = target;
27206 var = force_reg (GET_MODE_INNER (mode), var);
27207 x = gen_rtx_VEC_DUPLICATE (mode, var);
27208 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27209 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27212 /* We need to shuffle the value to the correct position, so
27213 create a new pseudo to store the intermediate result. */
27215 /* With SSE2, we can use the integer shuffle insns. */
27216 if (mode != V4SFmode && TARGET_SSE2)
27218 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27220 GEN_INT (one_var == 1 ? 0 : 1),
27221 GEN_INT (one_var == 2 ? 0 : 1),
27222 GEN_INT (one_var == 3 ? 0 : 1)));
27223 if (target != new_target)
27224 emit_move_insn (target, new_target);
27228 /* Otherwise convert the intermediate result to V4SFmode and
27229 use the SSE1 shuffle instructions. */
27230 if (mode != V4SFmode)
27232 tmp = gen_reg_rtx (V4SFmode);
27233 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27238 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27240 GEN_INT (one_var == 1 ? 0 : 1),
27241 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27242 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27244 if (mode != V4SFmode)
27245 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27246 else if (tmp != target)
27247 emit_move_insn (target, tmp);
27249 else if (target != new_target)
27250 emit_move_insn (target, new_target);
27255 vsimode = V4SImode;
27261 vsimode = V2SImode;
27267 /* Zero extend the variable element to SImode and recurse. */
27268 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27270 x = gen_reg_rtx (vsimode);
27271 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27273 gcc_unreachable ();
27275 emit_move_insn (target, gen_lowpart (mode, x));
27283 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27284 consisting of the values in VALS. It is known that all elements
27285 except ONE_VAR are constants. Return true if successful. */
27288 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27289 rtx target, rtx vals, int one_var)
27291 rtx var = XVECEXP (vals, 0, one_var);
27292 enum machine_mode wmode;
27295 const_vec = copy_rtx (vals);
27296 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27297 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27305 /* For the two element vectors, it's just as easy to use
27306 the general case. */
27310 /* Use ix86_expand_vector_set in 64bit mode only. */
27333 /* There's no way to set one QImode entry easily. Combine
27334 the variable value with its adjacent constant value, and
27335 promote to an HImode set. */
27336 x = XVECEXP (vals, 0, one_var ^ 1);
27339 var = convert_modes (HImode, QImode, var, true);
27340 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27341 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27342 x = GEN_INT (INTVAL (x) & 0xff);
27346 var = convert_modes (HImode, QImode, var, true);
27347 x = gen_int_mode (INTVAL (x) << 8, HImode);
27349 if (x != const0_rtx)
27350 var = expand_simple_binop (HImode, IOR, var, x, var,
27351 1, OPTAB_LIB_WIDEN);
27353 x = gen_reg_rtx (wmode);
27354 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27355 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27357 emit_move_insn (target, gen_lowpart (mode, x));
27364 emit_move_insn (target, const_vec);
27365 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27369 /* A subroutine of ix86_expand_vector_init_general. Use vector
27370 concatenate to handle the most general case: all values variable,
27371 and none identical. */
27374 ix86_expand_vector_init_concat (enum machine_mode mode,
27375 rtx target, rtx *ops, int n)
27377 enum machine_mode cmode, hmode = VOIDmode;
27378 rtx first[8], second[4];
27418 gcc_unreachable ();
27421 if (!register_operand (ops[1], cmode))
27422 ops[1] = force_reg (cmode, ops[1]);
27423 if (!register_operand (ops[0], cmode))
27424 ops[0] = force_reg (cmode, ops[0]);
27425 emit_insn (gen_rtx_SET (VOIDmode, target,
27426 gen_rtx_VEC_CONCAT (mode, ops[0],
27446 gcc_unreachable ();
27462 gcc_unreachable ();
27467 /* FIXME: We process inputs backward to help RA. PR 36222. */
27470 for (; i > 0; i -= 2, j--)
27472 first[j] = gen_reg_rtx (cmode);
27473 v = gen_rtvec (2, ops[i - 1], ops[i]);
27474 ix86_expand_vector_init (false, first[j],
27475 gen_rtx_PARALLEL (cmode, v));
27481 gcc_assert (hmode != VOIDmode);
27482 for (i = j = 0; i < n; i += 2, j++)
27484 second[j] = gen_reg_rtx (hmode);
27485 ix86_expand_vector_init_concat (hmode, second [j],
27489 ix86_expand_vector_init_concat (mode, target, second, n);
27492 ix86_expand_vector_init_concat (mode, target, first, n);
27496 gcc_unreachable ();
27500 /* A subroutine of ix86_expand_vector_init_general. Use vector
27501 interleave to handle the most general case: all values variable,
27502 and none identical. */
27505 ix86_expand_vector_init_interleave (enum machine_mode mode,
27506 rtx target, rtx *ops, int n)
27508 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27511 rtx (*gen_load_even) (rtx, rtx, rtx);
27512 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27513 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27518 gen_load_even = gen_vec_setv8hi;
27519 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27520 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27521 inner_mode = HImode;
27522 first_imode = V4SImode;
27523 second_imode = V2DImode;
27524 third_imode = VOIDmode;
27527 gen_load_even = gen_vec_setv16qi;
27528 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27529 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27530 inner_mode = QImode;
27531 first_imode = V8HImode;
27532 second_imode = V4SImode;
27533 third_imode = V2DImode;
27536 gcc_unreachable ();
27539 for (i = 0; i < n; i++)
27541 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27542 op0 = gen_reg_rtx (SImode);
27543 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27545 /* Insert the SImode value as low element of V4SImode vector. */
27546 op1 = gen_reg_rtx (V4SImode);
27547 op0 = gen_rtx_VEC_MERGE (V4SImode,
27548 gen_rtx_VEC_DUPLICATE (V4SImode,
27550 CONST0_RTX (V4SImode),
27552 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27554 /* Cast the V4SImode vector back to a vector in orignal mode. */
27555 op0 = gen_reg_rtx (mode);
27556 emit_move_insn (op0, gen_lowpart (mode, op1));
27558 /* Load even elements into the second positon. */
27559 emit_insn ((*gen_load_even) (op0,
27560 force_reg (inner_mode,
27564 /* Cast vector to FIRST_IMODE vector. */
27565 ops[i] = gen_reg_rtx (first_imode);
27566 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27569 /* Interleave low FIRST_IMODE vectors. */
27570 for (i = j = 0; i < n; i += 2, j++)
27572 op0 = gen_reg_rtx (first_imode);
27573 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27575 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27576 ops[j] = gen_reg_rtx (second_imode);
27577 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27580 /* Interleave low SECOND_IMODE vectors. */
27581 switch (second_imode)
27584 for (i = j = 0; i < n / 2; i += 2, j++)
27586 op0 = gen_reg_rtx (second_imode);
27587 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27590 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27592 ops[j] = gen_reg_rtx (third_imode);
27593 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27595 second_imode = V2DImode;
27596 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27600 op0 = gen_reg_rtx (second_imode);
27601 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27604 /* Cast the SECOND_IMODE vector back to a vector on original
27606 emit_insn (gen_rtx_SET (VOIDmode, target,
27607 gen_lowpart (mode, op0)));
27611 gcc_unreachable ();
27615 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27616 all values variable, and none identical. */
27619 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27620 rtx target, rtx vals)
27622 rtx ops[32], op0, op1;
27623 enum machine_mode half_mode = VOIDmode;
27630 if (!mmx_ok && !TARGET_SSE)
27642 n = GET_MODE_NUNITS (mode);
27643 for (i = 0; i < n; i++)
27644 ops[i] = XVECEXP (vals, 0, i);
27645 ix86_expand_vector_init_concat (mode, target, ops, n);
27649 half_mode = V16QImode;
27653 half_mode = V8HImode;
27657 n = GET_MODE_NUNITS (mode);
27658 for (i = 0; i < n; i++)
27659 ops[i] = XVECEXP (vals, 0, i);
27660 op0 = gen_reg_rtx (half_mode);
27661 op1 = gen_reg_rtx (half_mode);
27662 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27664 ix86_expand_vector_init_interleave (half_mode, op1,
27665 &ops [n >> 1], n >> 2);
27666 emit_insn (gen_rtx_SET (VOIDmode, target,
27667 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27671 if (!TARGET_SSE4_1)
27679 /* Don't use ix86_expand_vector_init_interleave if we can't
27680 move from GPR to SSE register directly. */
27681 if (!TARGET_INTER_UNIT_MOVES)
27684 n = GET_MODE_NUNITS (mode);
27685 for (i = 0; i < n; i++)
27686 ops[i] = XVECEXP (vals, 0, i);
27687 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27695 gcc_unreachable ();
27699 int i, j, n_elts, n_words, n_elt_per_word;
27700 enum machine_mode inner_mode;
27701 rtx words[4], shift;
27703 inner_mode = GET_MODE_INNER (mode);
27704 n_elts = GET_MODE_NUNITS (mode);
27705 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27706 n_elt_per_word = n_elts / n_words;
27707 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27709 for (i = 0; i < n_words; ++i)
27711 rtx word = NULL_RTX;
27713 for (j = 0; j < n_elt_per_word; ++j)
27715 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27716 elt = convert_modes (word_mode, inner_mode, elt, true);
27722 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27723 word, 1, OPTAB_LIB_WIDEN);
27724 word = expand_simple_binop (word_mode, IOR, word, elt,
27725 word, 1, OPTAB_LIB_WIDEN);
27733 emit_move_insn (target, gen_lowpart (mode, words[0]));
27734 else if (n_words == 2)
27736 rtx tmp = gen_reg_rtx (mode);
27737 emit_clobber (tmp);
27738 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27739 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27740 emit_move_insn (target, tmp);
27742 else if (n_words == 4)
27744 rtx tmp = gen_reg_rtx (V4SImode);
27745 gcc_assert (word_mode == SImode);
27746 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27747 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27748 emit_move_insn (target, gen_lowpart (mode, tmp));
27751 gcc_unreachable ();
27755 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27756 instructions unless MMX_OK is true. */
27759 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27761 enum machine_mode mode = GET_MODE (target);
27762 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27763 int n_elts = GET_MODE_NUNITS (mode);
27764 int n_var = 0, one_var = -1;
27765 bool all_same = true, all_const_zero = true;
27769 for (i = 0; i < n_elts; ++i)
27771 x = XVECEXP (vals, 0, i);
27772 if (!(CONST_INT_P (x)
27773 || GET_CODE (x) == CONST_DOUBLE
27774 || GET_CODE (x) == CONST_FIXED))
27775 n_var++, one_var = i;
27776 else if (x != CONST0_RTX (inner_mode))
27777 all_const_zero = false;
27778 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27782 /* Constants are best loaded from the constant pool. */
27785 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27789 /* If all values are identical, broadcast the value. */
27791 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27792 XVECEXP (vals, 0, 0)))
27795 /* Values where only one field is non-constant are best loaded from
27796 the pool and overwritten via move later. */
27800 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27801 XVECEXP (vals, 0, one_var),
27805 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27809 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27813 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27815 enum machine_mode mode = GET_MODE (target);
27816 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27817 enum machine_mode half_mode;
27818 bool use_vec_merge = false;
27820 static rtx (*gen_extract[6][2]) (rtx, rtx)
27822 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27823 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27824 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27825 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27826 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27827 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27829 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27831 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27832 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27833 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27834 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27835 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27836 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
27846 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
27847 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
27849 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
27851 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
27852 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27858 use_vec_merge = TARGET_SSE4_1;
27866 /* For the two element vectors, we implement a VEC_CONCAT with
27867 the extraction of the other element. */
27869 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
27870 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
27873 op0 = val, op1 = tmp;
27875 op0 = tmp, op1 = val;
27877 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
27878 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27883 use_vec_merge = TARGET_SSE4_1;
27890 use_vec_merge = true;
27894 /* tmp = target = A B C D */
27895 tmp = copy_to_reg (target);
27896 /* target = A A B B */
27897 emit_insn (gen_sse_unpcklps (target, target, target));
27898 /* target = X A B B */
27899 ix86_expand_vector_set (false, target, val, 0);
27900 /* target = A X C D */
27901 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27902 GEN_INT (1), GEN_INT (0),
27903 GEN_INT (2+4), GEN_INT (3+4)));
27907 /* tmp = target = A B C D */
27908 tmp = copy_to_reg (target);
27909 /* tmp = X B C D */
27910 ix86_expand_vector_set (false, tmp, val, 0);
27911 /* target = A B X D */
27912 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27913 GEN_INT (0), GEN_INT (1),
27914 GEN_INT (0+4), GEN_INT (3+4)));
27918 /* tmp = target = A B C D */
27919 tmp = copy_to_reg (target);
27920 /* tmp = X B C D */
27921 ix86_expand_vector_set (false, tmp, val, 0);
27922 /* target = A B X D */
27923 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27924 GEN_INT (0), GEN_INT (1),
27925 GEN_INT (2+4), GEN_INT (0+4)));
27929 gcc_unreachable ();
27934 use_vec_merge = TARGET_SSE4_1;
27938 /* Element 0 handled by vec_merge below. */
27941 use_vec_merge = true;
27947 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27948 store into element 0, then shuffle them back. */
27952 order[0] = GEN_INT (elt);
27953 order[1] = const1_rtx;
27954 order[2] = const2_rtx;
27955 order[3] = GEN_INT (3);
27956 order[elt] = const0_rtx;
27958 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27959 order[1], order[2], order[3]));
27961 ix86_expand_vector_set (false, target, val, 0);
27963 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27964 order[1], order[2], order[3]));
27968 /* For SSE1, we have to reuse the V4SF code. */
27969 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
27970 gen_lowpart (SFmode, val), elt);
27975 use_vec_merge = TARGET_SSE2;
27978 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27982 use_vec_merge = TARGET_SSE4_1;
27989 half_mode = V16QImode;
27995 half_mode = V8HImode;
28001 half_mode = V4SImode;
28007 half_mode = V2DImode;
28013 half_mode = V4SFmode;
28019 half_mode = V2DFmode;
28025 /* Compute offset. */
28029 gcc_assert (i <= 1);
28031 /* Extract the half. */
28032 tmp = gen_reg_rtx (half_mode);
28033 emit_insn ((*gen_extract[j][i]) (tmp, target));
28035 /* Put val in tmp at elt. */
28036 ix86_expand_vector_set (false, tmp, val, elt);
28039 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
28048 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
28049 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
28050 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28054 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28056 emit_move_insn (mem, target);
28058 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28059 emit_move_insn (tmp, val);
28061 emit_move_insn (target, mem);
28066 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
28068 enum machine_mode mode = GET_MODE (vec);
28069 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28070 bool use_vec_extr = false;
28083 use_vec_extr = true;
28087 use_vec_extr = TARGET_SSE4_1;
28099 tmp = gen_reg_rtx (mode);
28100 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
28101 GEN_INT (elt), GEN_INT (elt),
28102 GEN_INT (elt+4), GEN_INT (elt+4)));
28106 tmp = gen_reg_rtx (mode);
28107 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
28111 gcc_unreachable ();
28114 use_vec_extr = true;
28119 use_vec_extr = TARGET_SSE4_1;
28133 tmp = gen_reg_rtx (mode);
28134 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
28135 GEN_INT (elt), GEN_INT (elt),
28136 GEN_INT (elt), GEN_INT (elt)));
28140 tmp = gen_reg_rtx (mode);
28141 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
28145 gcc_unreachable ();
28148 use_vec_extr = true;
28153 /* For SSE1, we have to reuse the V4SF code. */
28154 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
28155 gen_lowpart (V4SFmode, vec), elt);
28161 use_vec_extr = TARGET_SSE2;
28164 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28168 use_vec_extr = TARGET_SSE4_1;
28172 /* ??? Could extract the appropriate HImode element and shift. */
28179 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28180 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28182 /* Let the rtl optimizers know about the zero extension performed. */
28183 if (inner_mode == QImode || inner_mode == HImode)
28185 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28186 target = gen_lowpart (SImode, target);
28189 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28193 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28195 emit_move_insn (mem, vec);
28197 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28198 emit_move_insn (target, tmp);
28202 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28203 pattern to reduce; DEST is the destination; IN is the input vector. */
28206 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28208 rtx tmp1, tmp2, tmp3;
28210 tmp1 = gen_reg_rtx (V4SFmode);
28211 tmp2 = gen_reg_rtx (V4SFmode);
28212 tmp3 = gen_reg_rtx (V4SFmode);
28214 emit_insn (gen_sse_movhlps (tmp1, in, in));
28215 emit_insn (fn (tmp2, tmp1, in));
28217 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28218 GEN_INT (1), GEN_INT (1),
28219 GEN_INT (1+4), GEN_INT (1+4)));
28220 emit_insn (fn (dest, tmp2, tmp3));
28223 /* Target hook for scalar_mode_supported_p. */
28225 ix86_scalar_mode_supported_p (enum machine_mode mode)
28227 if (DECIMAL_FLOAT_MODE_P (mode))
28229 else if (mode == TFmode)
28232 return default_scalar_mode_supported_p (mode);
28235 /* Implements target hook vector_mode_supported_p. */
28237 ix86_vector_mode_supported_p (enum machine_mode mode)
28239 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28241 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28243 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28245 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28247 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28252 /* Target hook for c_mode_for_suffix. */
28253 static enum machine_mode
28254 ix86_c_mode_for_suffix (char suffix)
28264 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28266 We do this in the new i386 backend to maintain source compatibility
28267 with the old cc0-based compiler. */
28270 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28271 tree inputs ATTRIBUTE_UNUSED,
28274 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28276 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28281 /* Implements target vector targetm.asm.encode_section_info. This
28282 is not used by netware. */
28284 static void ATTRIBUTE_UNUSED
28285 ix86_encode_section_info (tree decl, rtx rtl, int first)
28287 default_encode_section_info (decl, rtl, first);
28289 if (TREE_CODE (decl) == VAR_DECL
28290 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28291 && ix86_in_large_data_p (decl))
28292 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28295 /* Worker function for REVERSE_CONDITION. */
28298 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28300 return (mode != CCFPmode && mode != CCFPUmode
28301 ? reverse_condition (code)
28302 : reverse_condition_maybe_unordered (code));
28305 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28309 output_387_reg_move (rtx insn, rtx *operands)
28311 if (REG_P (operands[0]))
28313 if (REG_P (operands[1])
28314 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28316 if (REGNO (operands[0]) == FIRST_STACK_REG)
28317 return output_387_ffreep (operands, 0);
28318 return "fstp\t%y0";
28320 if (STACK_TOP_P (operands[0]))
28321 return "fld%z1\t%y1";
28324 else if (MEM_P (operands[0]))
28326 gcc_assert (REG_P (operands[1]));
28327 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28328 return "fstp%z0\t%y0";
28331 /* There is no non-popping store to memory for XFmode.
28332 So if we need one, follow the store with a load. */
28333 if (GET_MODE (operands[0]) == XFmode)
28334 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
28336 return "fst%z0\t%y0";
28343 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28344 FP status register is set. */
28347 ix86_emit_fp_unordered_jump (rtx label)
28349 rtx reg = gen_reg_rtx (HImode);
28352 emit_insn (gen_x86_fnstsw_1 (reg));
28354 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28356 emit_insn (gen_x86_sahf_1 (reg));
28358 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28359 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28363 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28365 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28366 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28369 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28370 gen_rtx_LABEL_REF (VOIDmode, label),
28372 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28374 emit_jump_insn (temp);
28375 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28378 /* Output code to perform a log1p XFmode calculation. */
28380 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28382 rtx label1 = gen_label_rtx ();
28383 rtx label2 = gen_label_rtx ();
28385 rtx tmp = gen_reg_rtx (XFmode);
28386 rtx tmp2 = gen_reg_rtx (XFmode);
28388 emit_insn (gen_absxf2 (tmp, op1));
28389 emit_insn (gen_cmpxf (tmp,
28390 CONST_DOUBLE_FROM_REAL_VALUE (
28391 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28393 emit_jump_insn (gen_bge (label1));
28395 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28396 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28397 emit_jump (label2);
28399 emit_label (label1);
28400 emit_move_insn (tmp, CONST1_RTX (XFmode));
28401 emit_insn (gen_addxf3 (tmp, op1, tmp));
28402 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28403 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28405 emit_label (label2);
28408 /* Output code to perform a Newton-Rhapson approximation of a single precision
28409 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28411 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28413 rtx x0, x1, e0, e1, two;
28415 x0 = gen_reg_rtx (mode);
28416 e0 = gen_reg_rtx (mode);
28417 e1 = gen_reg_rtx (mode);
28418 x1 = gen_reg_rtx (mode);
28420 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28422 if (VECTOR_MODE_P (mode))
28423 two = ix86_build_const_vector (SFmode, true, two);
28425 two = force_reg (mode, two);
28427 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28429 /* x0 = rcp(b) estimate */
28430 emit_insn (gen_rtx_SET (VOIDmode, x0,
28431 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28434 emit_insn (gen_rtx_SET (VOIDmode, e0,
28435 gen_rtx_MULT (mode, x0, b)));
28437 emit_insn (gen_rtx_SET (VOIDmode, e1,
28438 gen_rtx_MINUS (mode, two, e0)));
28440 emit_insn (gen_rtx_SET (VOIDmode, x1,
28441 gen_rtx_MULT (mode, x0, e1)));
28443 emit_insn (gen_rtx_SET (VOIDmode, res,
28444 gen_rtx_MULT (mode, a, x1)));
28447 /* Output code to perform a Newton-Rhapson approximation of a
28448 single precision floating point [reciprocal] square root. */
28450 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28453 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28456 x0 = gen_reg_rtx (mode);
28457 e0 = gen_reg_rtx (mode);
28458 e1 = gen_reg_rtx (mode);
28459 e2 = gen_reg_rtx (mode);
28460 e3 = gen_reg_rtx (mode);
28462 real_from_integer (&r, VOIDmode, -3, -1, 0);
28463 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28465 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28466 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28468 if (VECTOR_MODE_P (mode))
28470 mthree = ix86_build_const_vector (SFmode, true, mthree);
28471 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28474 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28475 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28477 /* x0 = rsqrt(a) estimate */
28478 emit_insn (gen_rtx_SET (VOIDmode, x0,
28479 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28482 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28487 zero = gen_reg_rtx (mode);
28488 mask = gen_reg_rtx (mode);
28490 zero = force_reg (mode, CONST0_RTX(mode));
28491 emit_insn (gen_rtx_SET (VOIDmode, mask,
28492 gen_rtx_NE (mode, zero, a)));
28494 emit_insn (gen_rtx_SET (VOIDmode, x0,
28495 gen_rtx_AND (mode, x0, mask)));
28499 emit_insn (gen_rtx_SET (VOIDmode, e0,
28500 gen_rtx_MULT (mode, x0, a)));
28502 emit_insn (gen_rtx_SET (VOIDmode, e1,
28503 gen_rtx_MULT (mode, e0, x0)));
28506 mthree = force_reg (mode, mthree);
28507 emit_insn (gen_rtx_SET (VOIDmode, e2,
28508 gen_rtx_PLUS (mode, e1, mthree)));
28510 mhalf = force_reg (mode, mhalf);
28512 /* e3 = -.5 * x0 */
28513 emit_insn (gen_rtx_SET (VOIDmode, e3,
28514 gen_rtx_MULT (mode, x0, mhalf)));
28516 /* e3 = -.5 * e0 */
28517 emit_insn (gen_rtx_SET (VOIDmode, e3,
28518 gen_rtx_MULT (mode, e0, mhalf)));
28519 /* ret = e2 * e3 */
28520 emit_insn (gen_rtx_SET (VOIDmode, res,
28521 gen_rtx_MULT (mode, e2, e3)));
28524 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28526 static void ATTRIBUTE_UNUSED
28527 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28530 /* With Binutils 2.15, the "@unwind" marker must be specified on
28531 every occurrence of the ".eh_frame" section, not just the first
28534 && strcmp (name, ".eh_frame") == 0)
28536 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28537 flags & SECTION_WRITE ? "aw" : "a");
28540 default_elf_asm_named_section (name, flags, decl);
28543 /* Return the mangling of TYPE if it is an extended fundamental type. */
28545 static const char *
28546 ix86_mangle_type (const_tree type)
28548 type = TYPE_MAIN_VARIANT (type);
28550 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28551 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28554 switch (TYPE_MODE (type))
28557 /* __float128 is "g". */
28560 /* "long double" or __float80 is "e". */
28567 /* For 32-bit code we can save PIC register setup by using
28568 __stack_chk_fail_local hidden function instead of calling
28569 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28570 register, so it is better to call __stack_chk_fail directly. */
28573 ix86_stack_protect_fail (void)
28575 return TARGET_64BIT
28576 ? default_external_stack_protect_fail ()
28577 : default_hidden_stack_protect_fail ();
28580 /* Select a format to encode pointers in exception handling data. CODE
28581 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28582 true if the symbol may be affected by dynamic relocations.
28584 ??? All x86 object file formats are capable of representing this.
28585 After all, the relocation needed is the same as for the call insn.
28586 Whether or not a particular assembler allows us to enter such, I
28587 guess we'll have to see. */
28589 asm_preferred_eh_data_format (int code, int global)
28593 int type = DW_EH_PE_sdata8;
28595 || ix86_cmodel == CM_SMALL_PIC
28596 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28597 type = DW_EH_PE_sdata4;
28598 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28600 if (ix86_cmodel == CM_SMALL
28601 || (ix86_cmodel == CM_MEDIUM && code))
28602 return DW_EH_PE_udata4;
28603 return DW_EH_PE_absptr;
28606 /* Expand copysign from SIGN to the positive value ABS_VALUE
28607 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28610 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28612 enum machine_mode mode = GET_MODE (sign);
28613 rtx sgn = gen_reg_rtx (mode);
28614 if (mask == NULL_RTX)
28616 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28617 if (!VECTOR_MODE_P (mode))
28619 /* We need to generate a scalar mode mask in this case. */
28620 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28621 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28622 mask = gen_reg_rtx (mode);
28623 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28627 mask = gen_rtx_NOT (mode, mask);
28628 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28629 gen_rtx_AND (mode, mask, sign)));
28630 emit_insn (gen_rtx_SET (VOIDmode, result,
28631 gen_rtx_IOR (mode, abs_value, sgn)));
28634 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28635 mask for masking out the sign-bit is stored in *SMASK, if that is
28638 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28640 enum machine_mode mode = GET_MODE (op0);
28643 xa = gen_reg_rtx (mode);
28644 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28645 if (!VECTOR_MODE_P (mode))
28647 /* We need to generate a scalar mode mask in this case. */
28648 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28649 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28650 mask = gen_reg_rtx (mode);
28651 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28653 emit_insn (gen_rtx_SET (VOIDmode, xa,
28654 gen_rtx_AND (mode, op0, mask)));
28662 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28663 swapping the operands if SWAP_OPERANDS is true. The expanded
28664 code is a forward jump to a newly created label in case the
28665 comparison is true. The generated label rtx is returned. */
28667 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28668 bool swap_operands)
28679 label = gen_label_rtx ();
28680 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28681 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28682 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28683 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28684 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28685 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28686 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28687 JUMP_LABEL (tmp) = label;
28692 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28693 using comparison code CODE. Operands are swapped for the comparison if
28694 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28696 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28697 bool swap_operands)
28699 enum machine_mode mode = GET_MODE (op0);
28700 rtx mask = gen_reg_rtx (mode);
28709 if (mode == DFmode)
28710 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28711 gen_rtx_fmt_ee (code, mode, op0, op1)));
28713 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28714 gen_rtx_fmt_ee (code, mode, op0, op1)));
28719 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28720 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28722 ix86_gen_TWO52 (enum machine_mode mode)
28724 REAL_VALUE_TYPE TWO52r;
28727 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28728 TWO52 = const_double_from_real_value (TWO52r, mode);
28729 TWO52 = force_reg (mode, TWO52);
28734 /* Expand SSE sequence for computing lround from OP1 storing
28737 ix86_expand_lround (rtx op0, rtx op1)
28739 /* C code for the stuff we're doing below:
28740 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28743 enum machine_mode mode = GET_MODE (op1);
28744 const struct real_format *fmt;
28745 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28748 /* load nextafter (0.5, 0.0) */
28749 fmt = REAL_MODE_FORMAT (mode);
28750 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28751 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28753 /* adj = copysign (0.5, op1) */
28754 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28755 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28757 /* adj = op1 + adj */
28758 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28760 /* op0 = (imode)adj */
28761 expand_fix (op0, adj, 0);
28764 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28767 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28769 /* C code for the stuff we're doing below (for do_floor):
28771 xi -= (double)xi > op1 ? 1 : 0;
28774 enum machine_mode fmode = GET_MODE (op1);
28775 enum machine_mode imode = GET_MODE (op0);
28776 rtx ireg, freg, label, tmp;
28778 /* reg = (long)op1 */
28779 ireg = gen_reg_rtx (imode);
28780 expand_fix (ireg, op1, 0);
28782 /* freg = (double)reg */
28783 freg = gen_reg_rtx (fmode);
28784 expand_float (freg, ireg, 0);
28786 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28787 label = ix86_expand_sse_compare_and_jump (UNLE,
28788 freg, op1, !do_floor);
28789 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28790 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28791 emit_move_insn (ireg, tmp);
28793 emit_label (label);
28794 LABEL_NUSES (label) = 1;
28796 emit_move_insn (op0, ireg);
28799 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28800 result in OPERAND0. */
28802 ix86_expand_rint (rtx operand0, rtx operand1)
28804 /* C code for the stuff we're doing below:
28805 xa = fabs (operand1);
28806 if (!isless (xa, 2**52))
28808 xa = xa + 2**52 - 2**52;
28809 return copysign (xa, operand1);
28811 enum machine_mode mode = GET_MODE (operand0);
28812 rtx res, xa, label, TWO52, mask;
28814 res = gen_reg_rtx (mode);
28815 emit_move_insn (res, operand1);
28817 /* xa = abs (operand1) */
28818 xa = ix86_expand_sse_fabs (res, &mask);
28820 /* if (!isless (xa, TWO52)) goto label; */
28821 TWO52 = ix86_gen_TWO52 (mode);
28822 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28824 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28825 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28827 ix86_sse_copysign_to_positive (res, xa, res, mask);
28829 emit_label (label);
28830 LABEL_NUSES (label) = 1;
28832 emit_move_insn (operand0, res);
28835 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28838 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
28840 /* C code for the stuff we expand below.
28841 double xa = fabs (x), x2;
28842 if (!isless (xa, TWO52))
28844 xa = xa + TWO52 - TWO52;
28845 x2 = copysign (xa, x);
28854 enum machine_mode mode = GET_MODE (operand0);
28855 rtx xa, TWO52, tmp, label, one, res, mask;
28857 TWO52 = ix86_gen_TWO52 (mode);
28859 /* Temporary for holding the result, initialized to the input
28860 operand to ease control flow. */
28861 res = gen_reg_rtx (mode);
28862 emit_move_insn (res, operand1);
28864 /* xa = abs (operand1) */
28865 xa = ix86_expand_sse_fabs (res, &mask);
28867 /* if (!isless (xa, TWO52)) goto label; */
28868 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28870 /* xa = xa + TWO52 - TWO52; */
28871 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28872 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28874 /* xa = copysign (xa, operand1) */
28875 ix86_sse_copysign_to_positive (xa, xa, res, mask);
28877 /* generate 1.0 or -1.0 */
28878 one = force_reg (mode,
28879 const_double_from_real_value (do_floor
28880 ? dconst1 : dconstm1, mode));
28882 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28883 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28884 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28885 gen_rtx_AND (mode, one, tmp)));
28886 /* We always need to subtract here to preserve signed zero. */
28887 tmp = expand_simple_binop (mode, MINUS,
28888 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28889 emit_move_insn (res, tmp);
28891 emit_label (label);
28892 LABEL_NUSES (label) = 1;
28894 emit_move_insn (operand0, res);
28897 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28900 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
28902 /* C code for the stuff we expand below.
28903 double xa = fabs (x), x2;
28904 if (!isless (xa, TWO52))
28906 x2 = (double)(long)x;
28913 if (HONOR_SIGNED_ZEROS (mode))
28914 return copysign (x2, x);
28917 enum machine_mode mode = GET_MODE (operand0);
28918 rtx xa, xi, TWO52, tmp, label, one, res, mask;
28920 TWO52 = ix86_gen_TWO52 (mode);
28922 /* Temporary for holding the result, initialized to the input
28923 operand to ease control flow. */
28924 res = gen_reg_rtx (mode);
28925 emit_move_insn (res, operand1);
28927 /* xa = abs (operand1) */
28928 xa = ix86_expand_sse_fabs (res, &mask);
28930 /* if (!isless (xa, TWO52)) goto label; */
28931 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28933 /* xa = (double)(long)x */
28934 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28935 expand_fix (xi, res, 0);
28936 expand_float (xa, xi, 0);
28939 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28941 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28942 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28943 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28944 gen_rtx_AND (mode, one, tmp)));
28945 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
28946 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28947 emit_move_insn (res, tmp);
28949 if (HONOR_SIGNED_ZEROS (mode))
28950 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28952 emit_label (label);
28953 LABEL_NUSES (label) = 1;
28955 emit_move_insn (operand0, res);
28958 /* Expand SSE sequence for computing round from OPERAND1 storing
28959 into OPERAND0. Sequence that works without relying on DImode truncation
28960 via cvttsd2siq that is only available on 64bit targets. */
28962 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
28964 /* C code for the stuff we expand below.
28965 double xa = fabs (x), xa2, x2;
28966 if (!isless (xa, TWO52))
28968 Using the absolute value and copying back sign makes
28969 -0.0 -> -0.0 correct.
28970 xa2 = xa + TWO52 - TWO52;
28975 else if (dxa > 0.5)
28977 x2 = copysign (xa2, x);
28980 enum machine_mode mode = GET_MODE (operand0);
28981 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
28983 TWO52 = ix86_gen_TWO52 (mode);
28985 /* Temporary for holding the result, initialized to the input
28986 operand to ease control flow. */
28987 res = gen_reg_rtx (mode);
28988 emit_move_insn (res, operand1);
28990 /* xa = abs (operand1) */
28991 xa = ix86_expand_sse_fabs (res, &mask);
28993 /* if (!isless (xa, TWO52)) goto label; */
28994 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28996 /* xa2 = xa + TWO52 - TWO52; */
28997 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28998 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29000 /* dxa = xa2 - xa; */
29001 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29003 /* generate 0.5, 1.0 and -0.5 */
29004 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29005 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29006 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
29010 tmp = gen_reg_rtx (mode);
29011 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29012 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
29013 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29014 gen_rtx_AND (mode, one, tmp)));
29015 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29016 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29017 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
29018 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29019 gen_rtx_AND (mode, one, tmp)));
29020 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29022 /* res = copysign (xa2, operand1) */
29023 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
29025 emit_label (label);
29026 LABEL_NUSES (label) = 1;
29028 emit_move_insn (operand0, res);
29031 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29034 ix86_expand_trunc (rtx operand0, rtx operand1)
29036 /* C code for SSE variant we expand below.
29037 double xa = fabs (x), x2;
29038 if (!isless (xa, TWO52))
29040 x2 = (double)(long)x;
29041 if (HONOR_SIGNED_ZEROS (mode))
29042 return copysign (x2, x);
29045 enum machine_mode mode = GET_MODE (operand0);
29046 rtx xa, xi, TWO52, label, res, mask;
29048 TWO52 = ix86_gen_TWO52 (mode);
29050 /* Temporary for holding the result, initialized to the input
29051 operand to ease control flow. */
29052 res = gen_reg_rtx (mode);
29053 emit_move_insn (res, operand1);
29055 /* xa = abs (operand1) */
29056 xa = ix86_expand_sse_fabs (res, &mask);
29058 /* if (!isless (xa, TWO52)) goto label; */
29059 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29061 /* x = (double)(long)x */
29062 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29063 expand_fix (xi, res, 0);
29064 expand_float (res, xi, 0);
29066 if (HONOR_SIGNED_ZEROS (mode))
29067 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29069 emit_label (label);
29070 LABEL_NUSES (label) = 1;
29072 emit_move_insn (operand0, res);
29075 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29078 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
29080 enum machine_mode mode = GET_MODE (operand0);
29081 rtx xa, mask, TWO52, label, one, res, smask, tmp;
29083 /* C code for SSE variant we expand below.
29084 double xa = fabs (x), x2;
29085 if (!isless (xa, TWO52))
29087 xa2 = xa + TWO52 - TWO52;
29091 x2 = copysign (xa2, x);
29095 TWO52 = ix86_gen_TWO52 (mode);
29097 /* Temporary for holding the result, initialized to the input
29098 operand to ease control flow. */
29099 res = gen_reg_rtx (mode);
29100 emit_move_insn (res, operand1);
29102 /* xa = abs (operand1) */
29103 xa = ix86_expand_sse_fabs (res, &smask);
29105 /* if (!isless (xa, TWO52)) goto label; */
29106 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29108 /* res = xa + TWO52 - TWO52; */
29109 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29110 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
29111 emit_move_insn (res, tmp);
29114 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29116 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29117 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
29118 emit_insn (gen_rtx_SET (VOIDmode, mask,
29119 gen_rtx_AND (mode, mask, one)));
29120 tmp = expand_simple_binop (mode, MINUS,
29121 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
29122 emit_move_insn (res, tmp);
29124 /* res = copysign (res, operand1) */
29125 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
29127 emit_label (label);
29128 LABEL_NUSES (label) = 1;
29130 emit_move_insn (operand0, res);
29133 /* Expand SSE sequence for computing round from OPERAND1 storing
29136 ix86_expand_round (rtx operand0, rtx operand1)
29138 /* C code for the stuff we're doing below:
29139 double xa = fabs (x);
29140 if (!isless (xa, TWO52))
29142 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29143 return copysign (xa, x);
29145 enum machine_mode mode = GET_MODE (operand0);
29146 rtx res, TWO52, xa, label, xi, half, mask;
29147 const struct real_format *fmt;
29148 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29150 /* Temporary for holding the result, initialized to the input
29151 operand to ease control flow. */
29152 res = gen_reg_rtx (mode);
29153 emit_move_insn (res, operand1);
29155 TWO52 = ix86_gen_TWO52 (mode);
29156 xa = ix86_expand_sse_fabs (res, &mask);
29157 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29159 /* load nextafter (0.5, 0.0) */
29160 fmt = REAL_MODE_FORMAT (mode);
29161 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29162 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29164 /* xa = xa + 0.5 */
29165 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29166 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29168 /* xa = (double)(int64_t)xa */
29169 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29170 expand_fix (xi, xa, 0);
29171 expand_float (xa, xi, 0);
29173 /* res = copysign (xa, operand1) */
29174 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29176 emit_label (label);
29177 LABEL_NUSES (label) = 1;
29179 emit_move_insn (operand0, res);
29183 /* Validate whether a SSE5 instruction is valid or not.
29184 OPERANDS is the array of operands.
29185 NUM is the number of operands.
29186 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
29187 NUM_MEMORY is the maximum number of memory operands to accept.
29188 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
29191 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
29192 bool uses_oc0, int num_memory, bool commutative)
29198 /* Count the number of memory arguments */
29201 for (i = 0; i < num; i++)
29203 enum machine_mode mode = GET_MODE (operands[i]);
29204 if (register_operand (operands[i], mode))
29207 else if (memory_operand (operands[i], mode))
29209 mem_mask |= (1 << i);
29215 rtx pattern = PATTERN (insn);
29217 /* allow 0 for pcmov */
29218 if (GET_CODE (pattern) != SET
29219 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
29221 || operands[i] != CONST0_RTX (mode))
29226 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29227 a memory operation. */
29228 if (num_memory < 0)
29230 num_memory = -num_memory;
29231 if ((mem_mask & (1 << (num-1))) != 0)
29233 mem_mask &= ~(1 << (num-1));
29238 /* If there were no memory operations, allow the insn */
29242 /* Do not allow the destination register to be a memory operand. */
29243 else if (mem_mask & (1 << 0))
29246 /* If there are too many memory operations, disallow the instruction. While
29247 the hardware only allows 1 memory reference, before register allocation
29248 for some insns, we allow two memory operations sometimes in order to allow
29249 code like the following to be optimized:
29251 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29253 or similar cases that are vectorized into using the fmaddss
29255 else if (mem_count > num_memory)
29258 /* Don't allow more than one memory operation if not optimizing. */
29259 else if (mem_count > 1 && !optimize)
29262 else if (num == 4 && mem_count == 1)
29264 /* formats (destination is the first argument), example fmaddss:
29265 xmm1, xmm1, xmm2, xmm3/mem
29266 xmm1, xmm1, xmm2/mem, xmm3
29267 xmm1, xmm2, xmm3/mem, xmm1
29268 xmm1, xmm2/mem, xmm3, xmm1 */
29270 return ((mem_mask == (1 << 1))
29271 || (mem_mask == (1 << 2))
29272 || (mem_mask == (1 << 3)));
29274 /* format, example pmacsdd:
29275 xmm1, xmm2, xmm3/mem, xmm1 */
29277 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29279 return (mem_mask == (1 << 2));
29282 else if (num == 4 && num_memory == 2)
29284 /* If there are two memory operations, we can load one of the memory ops
29285 into the destination register. This is for optimizing the
29286 multiply/add ops, which the combiner has optimized both the multiply
29287 and the add insns to have a memory operation. We have to be careful
29288 that the destination doesn't overlap with the inputs. */
29289 rtx op0 = operands[0];
29291 if (reg_mentioned_p (op0, operands[1])
29292 || reg_mentioned_p (op0, operands[2])
29293 || reg_mentioned_p (op0, operands[3]))
29296 /* formats (destination is the first argument), example fmaddss:
29297 xmm1, xmm1, xmm2, xmm3/mem
29298 xmm1, xmm1, xmm2/mem, xmm3
29299 xmm1, xmm2, xmm3/mem, xmm1
29300 xmm1, xmm2/mem, xmm3, xmm1
29302 For the oc0 case, we will load either operands[1] or operands[3] into
29303 operands[0], so any combination of 2 memory operands is ok. */
29307 /* format, example pmacsdd:
29308 xmm1, xmm2, xmm3/mem, xmm1
29310 For the integer multiply/add instructions be more restrictive and
29311 require operands[2] and operands[3] to be the memory operands. */
29313 return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
29315 return (mem_mask == ((1 << 2) | (1 << 3)));
29318 else if (num == 3 && num_memory == 1)
29320 /* formats, example protb:
29321 xmm1, xmm2, xmm3/mem
29322 xmm1, xmm2/mem, xmm3 */
29324 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29326 /* format, example comeq:
29327 xmm1, xmm2, xmm3/mem */
29329 return (mem_mask == (1 << 2));
29333 gcc_unreachable ();
29339 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
29340 hardware will allow by using the destination register to load one of the
29341 memory operations. Presently this is used by the multiply/add routines to
29342 allow 2 memory references. */
29345 ix86_expand_sse5_multiple_memory (rtx operands[],
29347 enum machine_mode mode)
29349 rtx op0 = operands[0];
29351 || memory_operand (op0, mode)
29352 || reg_mentioned_p (op0, operands[1])
29353 || reg_mentioned_p (op0, operands[2])
29354 || reg_mentioned_p (op0, operands[3]))
29355 gcc_unreachable ();
29357 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29358 the destination register. */
29359 if (memory_operand (operands[1], mode))
29361 emit_move_insn (op0, operands[1]);
29364 else if (memory_operand (operands[3], mode))
29366 emit_move_insn (op0, operands[3]);
29370 gcc_unreachable ();
29376 /* Table of valid machine attributes. */
29377 static const struct attribute_spec ix86_attribute_table[] =
29379 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29380 /* Stdcall attribute says callee is responsible for popping arguments
29381 if they are not variable. */
29382 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29383 /* Fastcall attribute says callee is responsible for popping arguments
29384 if they are not variable. */
29385 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29386 /* Cdecl attribute says the callee is a normal C declaration */
29387 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29388 /* Regparm attribute specifies how many integer arguments are to be
29389 passed in registers. */
29390 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29391 /* Sseregparm attribute says we are using x86_64 calling conventions
29392 for FP arguments. */
29393 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29394 /* force_align_arg_pointer says this function realigns the stack at entry. */
29395 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29396 false, true, true, ix86_handle_cconv_attribute },
29397 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29398 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29399 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29400 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29402 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29403 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29404 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29405 SUBTARGET_ATTRIBUTE_TABLE,
29407 /* ms_abi and sysv_abi calling convention function attributes. */
29408 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29409 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29411 { NULL, 0, 0, false, false, false, NULL }
29414 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29416 x86_builtin_vectorization_cost (bool runtime_test)
29418 /* If the branch of the runtime test is taken - i.e. - the vectorized
29419 version is skipped - this incurs a misprediction cost (because the
29420 vectorized version is expected to be the fall-through). So we subtract
29421 the latency of a mispredicted branch from the costs that are incured
29422 when the vectorized version is executed.
29424 TODO: The values in individual target tables have to be tuned or new
29425 fields may be needed. For eg. on K8, the default branch path is the
29426 not-taken path. If the taken path is predicted correctly, the minimum
29427 penalty of going down the taken-path is 1 cycle. If the taken-path is
29428 not predicted correctly, then the minimum penalty is 10 cycles. */
29432 return (-(ix86_cost->cond_taken_branch_cost));
29438 /* This function returns the calling abi specific va_list type node.
29439 It returns the FNDECL specific va_list type. */
29442 ix86_fn_abi_va_list (tree fndecl)
29447 return va_list_type_node;
29448 gcc_assert (fndecl != NULL_TREE);
29449 abi = ix86_function_abi ((const_tree) fndecl);
29452 return ms_va_list_type_node;
29454 return sysv_va_list_type_node;
29457 /* Returns the canonical va_list type specified by TYPE. If there
29458 is no valid TYPE provided, it return NULL_TREE. */
29461 ix86_canonical_va_list_type (tree type)
29465 /* Resolve references and pointers to va_list type. */
29466 if (INDIRECT_REF_P (type))
29467 type = TREE_TYPE (type);
29468 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29469 type = TREE_TYPE (type);
29473 wtype = va_list_type_node;
29474 gcc_assert (wtype != NULL_TREE);
29476 if (TREE_CODE (wtype) == ARRAY_TYPE)
29478 /* If va_list is an array type, the argument may have decayed
29479 to a pointer type, e.g. by being passed to another function.
29480 In that case, unwrap both types so that we can compare the
29481 underlying records. */
29482 if (TREE_CODE (htype) == ARRAY_TYPE
29483 || POINTER_TYPE_P (htype))
29485 wtype = TREE_TYPE (wtype);
29486 htype = TREE_TYPE (htype);
29489 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29490 return va_list_type_node;
29491 wtype = sysv_va_list_type_node;
29492 gcc_assert (wtype != NULL_TREE);
29494 if (TREE_CODE (wtype) == ARRAY_TYPE)
29496 /* If va_list is an array type, the argument may have decayed
29497 to a pointer type, e.g. by being passed to another function.
29498 In that case, unwrap both types so that we can compare the
29499 underlying records. */
29500 if (TREE_CODE (htype) == ARRAY_TYPE
29501 || POINTER_TYPE_P (htype))
29503 wtype = TREE_TYPE (wtype);
29504 htype = TREE_TYPE (htype);
29507 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29508 return sysv_va_list_type_node;
29509 wtype = ms_va_list_type_node;
29510 gcc_assert (wtype != NULL_TREE);
29512 if (TREE_CODE (wtype) == ARRAY_TYPE)
29514 /* If va_list is an array type, the argument may have decayed
29515 to a pointer type, e.g. by being passed to another function.
29516 In that case, unwrap both types so that we can compare the
29517 underlying records. */
29518 if (TREE_CODE (htype) == ARRAY_TYPE
29519 || POINTER_TYPE_P (htype))
29521 wtype = TREE_TYPE (wtype);
29522 htype = TREE_TYPE (htype);
29525 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29526 return ms_va_list_type_node;
29529 return std_canonical_va_list_type (type);
29532 /* Iterate through the target-specific builtin types for va_list.
29533 IDX denotes the iterator, *PTREE is set to the result type of
29534 the va_list builtin, and *PNAME to its internal type.
29535 Returns zero if there is no element for this index, otherwise
29536 IDX should be increased upon the next call.
29537 Note, do not iterate a base builtin's name like __builtin_va_list.
29538 Used from c_common_nodes_and_builtins. */
29541 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29547 *ptree = ms_va_list_type_node;
29548 *pname = "__builtin_ms_va_list";
29551 *ptree = sysv_va_list_type_node;
29552 *pname = "__builtin_sysv_va_list";
29560 /* Initialize the GCC target structure. */
29561 #undef TARGET_RETURN_IN_MEMORY
29562 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29564 #undef TARGET_ATTRIBUTE_TABLE
29565 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29566 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29567 # undef TARGET_MERGE_DECL_ATTRIBUTES
29568 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29571 #undef TARGET_COMP_TYPE_ATTRIBUTES
29572 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29574 #undef TARGET_INIT_BUILTINS
29575 #define TARGET_INIT_BUILTINS ix86_init_builtins
29576 #undef TARGET_EXPAND_BUILTIN
29577 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29579 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29580 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29581 ix86_builtin_vectorized_function
29583 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29584 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29586 #undef TARGET_BUILTIN_RECIPROCAL
29587 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29589 #undef TARGET_ASM_FUNCTION_EPILOGUE
29590 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29592 #undef TARGET_ENCODE_SECTION_INFO
29593 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29594 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29596 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29599 #undef TARGET_ASM_OPEN_PAREN
29600 #define TARGET_ASM_OPEN_PAREN ""
29601 #undef TARGET_ASM_CLOSE_PAREN
29602 #define TARGET_ASM_CLOSE_PAREN ""
29604 #undef TARGET_ASM_ALIGNED_HI_OP
29605 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29606 #undef TARGET_ASM_ALIGNED_SI_OP
29607 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29609 #undef TARGET_ASM_ALIGNED_DI_OP
29610 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29613 #undef TARGET_ASM_UNALIGNED_HI_OP
29614 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29615 #undef TARGET_ASM_UNALIGNED_SI_OP
29616 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29617 #undef TARGET_ASM_UNALIGNED_DI_OP
29618 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29620 #undef TARGET_SCHED_ADJUST_COST
29621 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29622 #undef TARGET_SCHED_ISSUE_RATE
29623 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29624 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29625 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29626 ia32_multipass_dfa_lookahead
29628 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29629 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29632 #undef TARGET_HAVE_TLS
29633 #define TARGET_HAVE_TLS true
29635 #undef TARGET_CANNOT_FORCE_CONST_MEM
29636 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29637 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29638 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29640 #undef TARGET_DELEGITIMIZE_ADDRESS
29641 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29643 #undef TARGET_MS_BITFIELD_LAYOUT_P
29644 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29647 #undef TARGET_BINDS_LOCAL_P
29648 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29650 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29651 #undef TARGET_BINDS_LOCAL_P
29652 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29655 #undef TARGET_ASM_OUTPUT_MI_THUNK
29656 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29657 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29658 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29660 #undef TARGET_ASM_FILE_START
29661 #define TARGET_ASM_FILE_START x86_file_start
29663 #undef TARGET_DEFAULT_TARGET_FLAGS
29664 #define TARGET_DEFAULT_TARGET_FLAGS \
29666 | TARGET_SUBTARGET_DEFAULT \
29667 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29669 #undef TARGET_HANDLE_OPTION
29670 #define TARGET_HANDLE_OPTION ix86_handle_option
29672 #undef TARGET_RTX_COSTS
29673 #define TARGET_RTX_COSTS ix86_rtx_costs
29674 #undef TARGET_ADDRESS_COST
29675 #define TARGET_ADDRESS_COST ix86_address_cost
29677 #undef TARGET_FIXED_CONDITION_CODE_REGS
29678 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29679 #undef TARGET_CC_MODES_COMPATIBLE
29680 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29682 #undef TARGET_MACHINE_DEPENDENT_REORG
29683 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29685 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29686 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29688 #undef TARGET_BUILD_BUILTIN_VA_LIST
29689 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29691 #undef TARGET_FN_ABI_VA_LIST
29692 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29694 #undef TARGET_CANONICAL_VA_LIST_TYPE
29695 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29697 #undef TARGET_EXPAND_BUILTIN_VA_START
29698 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29700 #undef TARGET_MD_ASM_CLOBBERS
29701 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29703 #undef TARGET_PROMOTE_PROTOTYPES
29704 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29705 #undef TARGET_STRUCT_VALUE_RTX
29706 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29707 #undef TARGET_SETUP_INCOMING_VARARGS
29708 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29709 #undef TARGET_MUST_PASS_IN_STACK
29710 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29711 #undef TARGET_PASS_BY_REFERENCE
29712 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29713 #undef TARGET_INTERNAL_ARG_POINTER
29714 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29715 #undef TARGET_UPDATE_STACK_BOUNDARY
29716 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29717 #undef TARGET_GET_DRAP_RTX
29718 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29719 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29720 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29721 #undef TARGET_STRICT_ARGUMENT_NAMING
29722 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29724 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29725 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29727 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29728 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29730 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29731 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29733 #undef TARGET_C_MODE_FOR_SUFFIX
29734 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29737 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29738 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29741 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29742 #undef TARGET_INSERT_ATTRIBUTES
29743 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29746 #undef TARGET_MANGLE_TYPE
29747 #define TARGET_MANGLE_TYPE ix86_mangle_type
29749 #undef TARGET_STACK_PROTECT_FAIL
29750 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29752 #undef TARGET_FUNCTION_VALUE
29753 #define TARGET_FUNCTION_VALUE ix86_function_value
29755 #undef TARGET_SECONDARY_RELOAD
29756 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29758 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29759 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29761 #undef TARGET_SET_CURRENT_FUNCTION
29762 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29764 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29765 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29767 #undef TARGET_OPTION_SAVE
29768 #define TARGET_OPTION_SAVE ix86_function_specific_save
29770 #undef TARGET_OPTION_RESTORE
29771 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29773 #undef TARGET_OPTION_PRINT
29774 #define TARGET_OPTION_PRINT ix86_function_specific_print
29776 #undef TARGET_OPTION_CAN_INLINE_P
29777 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
29779 #undef TARGET_EXPAND_TO_RTL_HOOK
29780 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29782 struct gcc_target targetm = TARGET_INITIALIZER;
29784 #include "gt-i386.h"
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