1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
53 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of storing fp registers
995 in SFmode, DFmode and XFmode */
996 2, /* cost of moving MMX register */
997 {6, 6}, /* cost of loading MMX registers
998 in SImode and DImode */
999 {4, 4}, /* cost of storing MMX registers
1000 in SImode and DImode */
1001 2, /* cost of moving SSE register */
1002 {6, 6, 6}, /* cost of loading SSE registers
1003 in SImode, DImode and TImode */
1004 {4, 4, 4}, /* cost of storing SSE registers
1005 in SImode, DImode and TImode */
1006 2, /* MMX or SSE register to integer */
1007 32, /* size of l1 cache. */
1008 2048, /* size of l2 cache. */
1009 128, /* size of prefetch block */
1010 8, /* number of parallel prefetches */
1011 3, /* Branch cost */
1012 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1013 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1014 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1015 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1016 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1017 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1018 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1019 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 {{libcall, {{8, loop}, {15, unrolled_loop},
1022 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1023 {libcall, {{24, loop}, {32, unrolled_loop},
1024 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1025 1, /* scalar_stmt_cost. */
1026 1, /* scalar load_cost. */
1027 1, /* scalar_store_cost. */
1028 1, /* vec_stmt_cost. */
1029 1, /* vec_to_scalar_cost. */
1030 1, /* scalar_to_vec_cost. */
1031 1, /* vec_align_load_cost. */
1032 2, /* vec_unalign_load_cost. */
1033 1, /* vec_store_cost. */
1034 3, /* cond_taken_branch_cost. */
1035 1, /* cond_not_taken_branch_cost. */
1039 struct processor_costs atom_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1042 COSTS_N_INSNS (1), /* variable shift costs */
1043 COSTS_N_INSNS (1), /* constant shift costs */
1044 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1045 COSTS_N_INSNS (4), /* HI */
1046 COSTS_N_INSNS (3), /* SI */
1047 COSTS_N_INSNS (4), /* DI */
1048 COSTS_N_INSNS (2)}, /* other */
1049 0, /* cost of multiply per each bit set */
1050 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1051 COSTS_N_INSNS (26), /* HI */
1052 COSTS_N_INSNS (42), /* SI */
1053 COSTS_N_INSNS (74), /* DI */
1054 COSTS_N_INSNS (74)}, /* other */
1055 COSTS_N_INSNS (1), /* cost of movsx */
1056 COSTS_N_INSNS (1), /* cost of movzx */
1057 8, /* "large" insn */
1058 17, /* MOVE_RATIO */
1059 2, /* cost for loading QImode using movzbl */
1060 {4, 4, 4}, /* cost of loading integer registers
1061 in QImode, HImode and SImode.
1062 Relative to reg-reg move (2). */
1063 {4, 4, 4}, /* cost of storing integer registers */
1064 4, /* cost of reg,reg fld/fst */
1065 {12, 12, 12}, /* cost of loading fp registers
1066 in SFmode, DFmode and XFmode */
1067 {6, 6, 8}, /* cost of storing fp registers
1068 in SFmode, DFmode and XFmode */
1069 2, /* cost of moving MMX register */
1070 {8, 8}, /* cost of loading MMX registers
1071 in SImode and DImode */
1072 {8, 8}, /* cost of storing MMX registers
1073 in SImode and DImode */
1074 2, /* cost of moving SSE register */
1075 {8, 8, 8}, /* cost of loading SSE registers
1076 in SImode, DImode and TImode */
1077 {8, 8, 8}, /* cost of storing SSE registers
1078 in SImode, DImode and TImode */
1079 5, /* MMX or SSE register to integer */
1080 32, /* size of l1 cache. */
1081 256, /* size of l2 cache. */
1082 64, /* size of prefetch block */
1083 6, /* number of parallel prefetches */
1084 3, /* Branch cost */
1085 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1086 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1087 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1088 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1089 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1090 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1091 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1092 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1093 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1094 {{libcall, {{8, loop}, {15, unrolled_loop},
1095 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1096 {libcall, {{24, loop}, {32, unrolled_loop},
1097 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1098 1, /* scalar_stmt_cost. */
1099 1, /* scalar load_cost. */
1100 1, /* scalar_store_cost. */
1101 1, /* vec_stmt_cost. */
1102 1, /* vec_to_scalar_cost. */
1103 1, /* scalar_to_vec_cost. */
1104 1, /* vec_align_load_cost. */
1105 2, /* vec_unalign_load_cost. */
1106 1, /* vec_store_cost. */
1107 3, /* cond_taken_branch_cost. */
1108 1, /* cond_not_taken_branch_cost. */
1111 /* Generic64 should produce code tuned for Nocona and K8. */
1113 struct processor_costs generic64_cost = {
1114 COSTS_N_INSNS (1), /* cost of an add instruction */
1115 /* On all chips taken into consideration lea is 2 cycles and more. With
1116 this cost however our current implementation of synth_mult results in
1117 use of unnecessary temporary registers causing regression on several
1118 SPECfp benchmarks. */
1119 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1120 COSTS_N_INSNS (1), /* variable shift costs */
1121 COSTS_N_INSNS (1), /* constant shift costs */
1122 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1123 COSTS_N_INSNS (4), /* HI */
1124 COSTS_N_INSNS (3), /* SI */
1125 COSTS_N_INSNS (4), /* DI */
1126 COSTS_N_INSNS (2)}, /* other */
1127 0, /* cost of multiply per each bit set */
1128 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1129 COSTS_N_INSNS (26), /* HI */
1130 COSTS_N_INSNS (42), /* SI */
1131 COSTS_N_INSNS (74), /* DI */
1132 COSTS_N_INSNS (74)}, /* other */
1133 COSTS_N_INSNS (1), /* cost of movsx */
1134 COSTS_N_INSNS (1), /* cost of movzx */
1135 8, /* "large" insn */
1136 17, /* MOVE_RATIO */
1137 4, /* cost for loading QImode using movzbl */
1138 {4, 4, 4}, /* cost of loading integer registers
1139 in QImode, HImode and SImode.
1140 Relative to reg-reg move (2). */
1141 {4, 4, 4}, /* cost of storing integer registers */
1142 4, /* cost of reg,reg fld/fst */
1143 {12, 12, 12}, /* cost of loading fp registers
1144 in SFmode, DFmode and XFmode */
1145 {6, 6, 8}, /* cost of storing fp registers
1146 in SFmode, DFmode and XFmode */
1147 2, /* cost of moving MMX register */
1148 {8, 8}, /* cost of loading MMX registers
1149 in SImode and DImode */
1150 {8, 8}, /* cost of storing MMX registers
1151 in SImode and DImode */
1152 2, /* cost of moving SSE register */
1153 {8, 8, 8}, /* cost of loading SSE registers
1154 in SImode, DImode and TImode */
1155 {8, 8, 8}, /* cost of storing SSE registers
1156 in SImode, DImode and TImode */
1157 5, /* MMX or SSE register to integer */
1158 32, /* size of l1 cache. */
1159 512, /* size of l2 cache. */
1160 64, /* size of prefetch block */
1161 6, /* number of parallel prefetches */
1162 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1163 is increased to perhaps more appropriate value of 5. */
1164 3, /* Branch cost */
1165 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1166 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1167 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1168 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1169 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1170 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1171 {DUMMY_STRINGOP_ALGS,
1172 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1173 {DUMMY_STRINGOP_ALGS,
1174 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1175 1, /* scalar_stmt_cost. */
1176 1, /* scalar load_cost. */
1177 1, /* scalar_store_cost. */
1178 1, /* vec_stmt_cost. */
1179 1, /* vec_to_scalar_cost. */
1180 1, /* scalar_to_vec_cost. */
1181 1, /* vec_align_load_cost. */
1182 2, /* vec_unalign_load_cost. */
1183 1, /* vec_store_cost. */
1184 3, /* cond_taken_branch_cost. */
1185 1, /* cond_not_taken_branch_cost. */
1188 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1190 struct processor_costs generic32_cost = {
1191 COSTS_N_INSNS (1), /* cost of an add instruction */
1192 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1193 COSTS_N_INSNS (1), /* variable shift costs */
1194 COSTS_N_INSNS (1), /* constant shift costs */
1195 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1196 COSTS_N_INSNS (4), /* HI */
1197 COSTS_N_INSNS (3), /* SI */
1198 COSTS_N_INSNS (4), /* DI */
1199 COSTS_N_INSNS (2)}, /* other */
1200 0, /* cost of multiply per each bit set */
1201 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1202 COSTS_N_INSNS (26), /* HI */
1203 COSTS_N_INSNS (42), /* SI */
1204 COSTS_N_INSNS (74), /* DI */
1205 COSTS_N_INSNS (74)}, /* other */
1206 COSTS_N_INSNS (1), /* cost of movsx */
1207 COSTS_N_INSNS (1), /* cost of movzx */
1208 8, /* "large" insn */
1209 17, /* MOVE_RATIO */
1210 4, /* cost for loading QImode using movzbl */
1211 {4, 4, 4}, /* cost of loading integer registers
1212 in QImode, HImode and SImode.
1213 Relative to reg-reg move (2). */
1214 {4, 4, 4}, /* cost of storing integer registers */
1215 4, /* cost of reg,reg fld/fst */
1216 {12, 12, 12}, /* cost of loading fp registers
1217 in SFmode, DFmode and XFmode */
1218 {6, 6, 8}, /* cost of storing fp registers
1219 in SFmode, DFmode and XFmode */
1220 2, /* cost of moving MMX register */
1221 {8, 8}, /* cost of loading MMX registers
1222 in SImode and DImode */
1223 {8, 8}, /* cost of storing MMX registers
1224 in SImode and DImode */
1225 2, /* cost of moving SSE register */
1226 {8, 8, 8}, /* cost of loading SSE registers
1227 in SImode, DImode and TImode */
1228 {8, 8, 8}, /* cost of storing SSE registers
1229 in SImode, DImode and TImode */
1230 5, /* MMX or SSE register to integer */
1231 32, /* size of l1 cache. */
1232 256, /* size of l2 cache. */
1233 64, /* size of prefetch block */
1234 6, /* number of parallel prefetches */
1235 3, /* Branch cost */
1236 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1237 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1238 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1239 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1240 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1241 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1242 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1243 DUMMY_STRINGOP_ALGS},
1244 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1245 DUMMY_STRINGOP_ALGS},
1246 1, /* scalar_stmt_cost. */
1247 1, /* scalar load_cost. */
1248 1, /* scalar_store_cost. */
1249 1, /* vec_stmt_cost. */
1250 1, /* vec_to_scalar_cost. */
1251 1, /* scalar_to_vec_cost. */
1252 1, /* vec_align_load_cost. */
1253 2, /* vec_unalign_load_cost. */
1254 1, /* vec_store_cost. */
1255 3, /* cond_taken_branch_cost. */
1256 1, /* cond_not_taken_branch_cost. */
1259 const struct processor_costs *ix86_cost = &pentium_cost;
1261 /* Processor feature/optimization bitmasks. */
1262 #define m_386 (1<<PROCESSOR_I386)
1263 #define m_486 (1<<PROCESSOR_I486)
1264 #define m_PENT (1<<PROCESSOR_PENTIUM)
1265 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1266 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1267 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1268 #define m_CORE2 (1<<PROCESSOR_CORE2)
1269 #define m_ATOM (1<<PROCESSOR_ATOM)
1271 #define m_GEODE (1<<PROCESSOR_GEODE)
1272 #define m_K6 (1<<PROCESSOR_K6)
1273 #define m_K6_GEODE (m_K6 | m_GEODE)
1274 #define m_K8 (1<<PROCESSOR_K8)
1275 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1276 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1277 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1278 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1280 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1281 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1283 /* Generic instruction choice should be common subset of supported CPUs
1284 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1285 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1287 /* Feature tests against the various tunings. */
1288 unsigned char ix86_tune_features[X86_TUNE_LAST];
1290 /* Feature tests against the various tunings used to create ix86_tune_features
1291 based on the processor mask. */
1292 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1293 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1294 negatively, so enabling for Generic64 seems like good code size
1295 tradeoff. We can't enable it for 32bit generic because it does not
1296 work well with PPro base chips. */
1297 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1299 /* X86_TUNE_PUSH_MEMORY */
1300 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1301 | m_NOCONA | m_CORE2 | m_GENERIC,
1303 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1306 /* X86_TUNE_UNROLL_STRLEN */
1307 m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
1308 | m_CORE2 | m_GENERIC,
1310 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1311 m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1313 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1314 on simulation result. But after P4 was made, no performance benefit
1315 was observed with branch hints. It also increases the code size.
1316 As a result, icc never generates branch hints. */
1319 /* X86_TUNE_DOUBLE_WITH_ADD */
1322 /* X86_TUNE_USE_SAHF */
1323 m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1324 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1327 partial dependencies. */
1328 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
1329 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1331 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1332 register stalls on Generic32 compilation setting as well. However
1333 in current implementation the partial register stalls are not eliminated
1334 very well - they can be introduced via subregs synthesized by combine
1335 and can happen in caller/callee saving sequences. Because this option
1336 pays back little on PPro based chips and is in conflict with partial reg
1337 dependencies used by Athlon/P4 based chips, it is better to leave it off
1338 for generic32 for now. */
1341 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1342 m_CORE2 | m_GENERIC,
1344 /* X86_TUNE_USE_HIMODE_FIOP */
1345 m_386 | m_486 | m_K6_GEODE,
1347 /* X86_TUNE_USE_SIMODE_FIOP */
1348 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),
1350 /* X86_TUNE_USE_MOV0 */
1353 /* X86_TUNE_USE_CLTD */
1354 ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),
1356 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1359 /* X86_TUNE_SPLIT_LONG_MOVES */
1362 /* X86_TUNE_READ_MODIFY_WRITE */
1365 /* X86_TUNE_READ_MODIFY */
1368 /* X86_TUNE_PROMOTE_QIMODE */
1369 m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
1370 | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,
1372 /* X86_TUNE_FAST_PREFIX */
1373 ~(m_PENT | m_486 | m_386),
1375 /* X86_TUNE_SINGLE_STRINGOP */
1376 m_386 | m_PENT4 | m_NOCONA,
1378 /* X86_TUNE_QIMODE_MATH */
1381 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1382 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1383 might be considered for Generic32 if our scheme for avoiding partial
1384 stalls was more effective. */
1387 /* X86_TUNE_PROMOTE_QI_REGS */
1390 /* X86_TUNE_PROMOTE_HI_REGS */
1393 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1394 m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
1395 | m_CORE2 | m_GENERIC,
1397 /* X86_TUNE_ADD_ESP_8 */
1398 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
1399 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_SUB_ESP_4 */
1402 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
1405 /* X86_TUNE_SUB_ESP_8 */
1406 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
1407 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1409 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1410 for DFmode copies */
1411 ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1412 | m_GENERIC | m_GEODE),
1414 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1415 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1417 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1418 conflict here in between PPro/Pentium4 based chips that thread 128bit
1419 SSE registers as single units versus K8 based chips that divide SSE
1420 registers to two 64bit halves. This knob promotes all store destinations
1421 to be 128bit to allow register renaming on 128bit SSE units, but usually
1422 results in one extra microop on 64bit SSE units. Experimental results
1423 shows that disabling this option on P4 brings over 20% SPECfp regression,
1424 while enabling it on K8 brings roughly 2.4% regression that can be partly
1425 masked by careful scheduling of moves. */
1426 m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
1429 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1432 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1433 are resolved on SSE register parts instead of whole registers, so we may
1434 maintain just lower part of scalar values in proper format leaving the
1435 upper part undefined. */
1438 /* X86_TUNE_SSE_TYPELESS_STORES */
1441 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1442 m_PPRO | m_PENT4 | m_NOCONA,
1444 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1445 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1447 /* X86_TUNE_PROLOGUE_USING_MOVE */
1448 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1450 /* X86_TUNE_EPILOGUE_USING_MOVE */
1451 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1453 /* X86_TUNE_SHIFT1 */
1456 /* X86_TUNE_USE_FFREEP */
1459 /* X86_TUNE_INTER_UNIT_MOVES */
1460 ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
1462 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1465 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1466 than 4 branch instructions in the 16 byte window. */
1467 m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
1470 /* X86_TUNE_SCHEDULE */
1471 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
1474 /* X86_TUNE_USE_BT */
1475 m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,
1477 /* X86_TUNE_USE_INCDEC */
1478 ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),
1480 /* X86_TUNE_PAD_RETURNS */
1481 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1483 /* X86_TUNE_EXT_80387_CONSTANTS */
1484 m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
1485 | m_CORE2 | m_GENERIC,
1487 /* X86_TUNE_SHORTEN_X87_SSE */
1490 /* X86_TUNE_AVOID_VECTOR_DECODE */
1493 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1494 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1497 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1498 vector path on AMD machines. */
1499 m_K8 | m_GENERIC64 | m_AMDFAM10,
1501 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1503 m_K8 | m_GENERIC64 | m_AMDFAM10,
1505 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1509 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1510 but one byte longer. */
1513 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1514 operand that cannot be represented using a modRM byte. The XOR
1515 replacement is long decoded, so this split helps here as well. */
1518 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1520 m_AMDFAM10 | m_GENERIC,
1522 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1523 from integer to FP. */
1526 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1527 with a subsequent conditional jump instruction into a single
1528 compare-and-branch uop. */
1531 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1532 will impact LEA instruction selection. */
1536 /* Feature tests against the various architecture variations. */
1537 unsigned char ix86_arch_features[X86_ARCH_LAST];
1539 /* Feature tests against the various architecture variations, used to create
1540 ix86_arch_features based on the processor mask. */
1541 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1542 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1543 ~(m_386 | m_486 | m_PENT | m_K6),
1545 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1548 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1551 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1554 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1558 static const unsigned int x86_accumulate_outgoing_args
1559 = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1562 static const unsigned int x86_arch_always_fancy_math_387
1563 = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1564 | m_NOCONA | m_CORE2 | m_GENERIC;
1566 static enum stringop_alg stringop_alg = no_stringop;
1568 /* In case the average insn count for single function invocation is
1569 lower than this constant, emit fast (but longer) prologue and
1571 #define FAST_PROLOGUE_INSN_COUNT 20
1573 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1574 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1575 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1576 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1578 /* Array of the smallest class containing reg number REGNO, indexed by
1579 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1581 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1583 /* ax, dx, cx, bx */
1584 AREG, DREG, CREG, BREG,
1585 /* si, di, bp, sp */
1586 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1588 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1589 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1592 /* flags, fpsr, fpcr, frame */
1593 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1595 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1598 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1601 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1602 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1603 /* SSE REX registers */
1604 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1608 /* The "default" register map used in 32bit mode. */
1610 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1612 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1613 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1614 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1615 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1616 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1617 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1618 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1621 /* The "default" register map used in 64bit mode. */
1623 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1625 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1626 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1627 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1628 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1629 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1630 8,9,10,11,12,13,14,15, /* extended integer registers */
1631 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1634 /* Define the register numbers to be used in Dwarf debugging information.
1635 The SVR4 reference port C compiler uses the following register numbers
1636 in its Dwarf output code:
1637 0 for %eax (gcc regno = 0)
1638 1 for %ecx (gcc regno = 2)
1639 2 for %edx (gcc regno = 1)
1640 3 for %ebx (gcc regno = 3)
1641 4 for %esp (gcc regno = 7)
1642 5 for %ebp (gcc regno = 6)
1643 6 for %esi (gcc regno = 4)
1644 7 for %edi (gcc regno = 5)
1645 The following three DWARF register numbers are never generated by
1646 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1647 believes these numbers have these meanings.
1648 8 for %eip (no gcc equivalent)
1649 9 for %eflags (gcc regno = 17)
1650 10 for %trapno (no gcc equivalent)
1651 It is not at all clear how we should number the FP stack registers
1652 for the x86 architecture. If the version of SDB on x86/svr4 were
1653 a bit less brain dead with respect to floating-point then we would
1654 have a precedent to follow with respect to DWARF register numbers
1655 for x86 FP registers, but the SDB on x86/svr4 is so completely
1656 broken with respect to FP registers that it is hardly worth thinking
1657 of it as something to strive for compatibility with.
1658 The version of x86/svr4 SDB I have at the moment does (partially)
1659 seem to believe that DWARF register number 11 is associated with
1660 the x86 register %st(0), but that's about all. Higher DWARF
1661 register numbers don't seem to be associated with anything in
1662 particular, and even for DWARF regno 11, SDB only seems to under-
1663 stand that it should say that a variable lives in %st(0) (when
1664 asked via an `=' command) if we said it was in DWARF regno 11,
1665 but SDB still prints garbage when asked for the value of the
1666 variable in question (via a `/' command).
1667 (Also note that the labels SDB prints for various FP stack regs
1668 when doing an `x' command are all wrong.)
1669 Note that these problems generally don't affect the native SVR4
1670 C compiler because it doesn't allow the use of -O with -g and
1671 because when it is *not* optimizing, it allocates a memory
1672 location for each floating-point variable, and the memory
1673 location is what gets described in the DWARF AT_location
1674 attribute for the variable in question.
1675 Regardless of the severe mental illness of the x86/svr4 SDB, we
1676 do something sensible here and we use the following DWARF
1677 register numbers. Note that these are all stack-top-relative
1679 11 for %st(0) (gcc regno = 8)
1680 12 for %st(1) (gcc regno = 9)
1681 13 for %st(2) (gcc regno = 10)
1682 14 for %st(3) (gcc regno = 11)
1683 15 for %st(4) (gcc regno = 12)
1684 16 for %st(5) (gcc regno = 13)
1685 17 for %st(6) (gcc regno = 14)
1686 18 for %st(7) (gcc regno = 15)
1688 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1690 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1691 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1692 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1693 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1694 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1695 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1696 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1699 /* Test and compare insns in i386.md store the information needed to
1700 generate branch and scc insns here. */
1702 rtx ix86_compare_op0 = NULL_RTX;
1703 rtx ix86_compare_op1 = NULL_RTX;
1705 /* Define parameter passing and return registers. */
1707 static int const x86_64_int_parameter_registers[6] =
1709 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1712 static int const x86_64_ms_abi_int_parameter_registers[4] =
1714 CX_REG, DX_REG, R8_REG, R9_REG
1717 static int const x86_64_int_return_registers[4] =
1719 AX_REG, DX_REG, DI_REG, SI_REG
1722 /* Define the structure for the machine field in struct function. */
1724 struct GTY(()) stack_local_entry {
1725 unsigned short mode;
1728 struct stack_local_entry *next;
1731 /* Structure describing stack frame layout.
1732 Stack grows downward:
1738 saved frame pointer if frame_pointer_needed
1739 <- HARD_FRAME_POINTER
1748 [va_arg registers] (
1749 > to_allocate <- FRAME_POINTER
1761 HOST_WIDE_INT frame;
1763 int outgoing_arguments_size;
1766 HOST_WIDE_INT to_allocate;
1767 /* The offsets relative to ARG_POINTER. */
1768 HOST_WIDE_INT frame_pointer_offset;
1769 HOST_WIDE_INT hard_frame_pointer_offset;
1770 HOST_WIDE_INT stack_pointer_offset;
1772 /* When save_regs_using_mov is set, emit prologue using
1773 move instead of push instructions. */
1774 bool save_regs_using_mov;
1777 /* Code model option. */
1778 enum cmodel ix86_cmodel;
1780 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1782 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1784 /* Which unit we are generating floating point math for. */
1785 enum fpmath_unit ix86_fpmath;
1787 /* Which cpu are we scheduling for. */
1788 enum attr_cpu ix86_schedule;
1790 /* Which cpu are we optimizing for. */
1791 enum processor_type ix86_tune;
1793 /* Which instruction set architecture to use. */
1794 enum processor_type ix86_arch;
1796 /* true if sse prefetch instruction is not NOOP. */
1797 int x86_prefetch_sse;
1799 /* ix86_regparm_string as a number */
1800 static int ix86_regparm;
1802 /* -mstackrealign option */
1803 extern int ix86_force_align_arg_pointer;
1804 static const char ix86_force_align_arg_pointer_string[]
1805 = "force_align_arg_pointer";
1807 static rtx (*ix86_gen_leave) (void);
1808 static rtx (*ix86_gen_pop1) (rtx);
1809 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1810 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1811 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1812 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1813 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1814 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1816 /* Preferred alignment for stack boundary in bits. */
1817 unsigned int ix86_preferred_stack_boundary;
1819 /* Alignment for incoming stack boundary in bits specified at
1821 static unsigned int ix86_user_incoming_stack_boundary;
1823 /* Default alignment for incoming stack boundary in bits. */
1824 static unsigned int ix86_default_incoming_stack_boundary;
1826 /* Alignment for incoming stack boundary in bits. */
1827 unsigned int ix86_incoming_stack_boundary;
1829 /* The abi used by target. */
1830 enum calling_abi ix86_abi;
1832 /* Values 1-5: see jump.c */
1833 int ix86_branch_cost;
1835 /* Calling abi specific va_list type nodes. */
1836 static GTY(()) tree sysv_va_list_type_node;
1837 static GTY(()) tree ms_va_list_type_node;
1839 /* Variables which are this size or smaller are put in the data/bss
1840 or ldata/lbss sections. */
1842 int ix86_section_threshold = 65536;
1844 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1845 char internal_label_prefix[16];
1846 int internal_label_prefix_len;
1848 /* Fence to use after loop using movnt. */
1851 /* Register class used for passing given 64bit part of the argument.
1852 These represent classes as documented by the PS ABI, with the exception
1853 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1854 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1856 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1857 whenever possible (upper half does contain padding). */
1858 enum x86_64_reg_class
1861 X86_64_INTEGER_CLASS,
1862 X86_64_INTEGERSI_CLASS,
1869 X86_64_COMPLEX_X87_CLASS,
1873 #define MAX_CLASSES 4
1875 /* Table of constants used by fldpi, fldln2, etc.... */
1876 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1877 static bool ext_80387_constants_init = 0;
1880 static struct machine_function * ix86_init_machine_status (void);
1881 static rtx ix86_function_value (const_tree, const_tree, bool);
1882 static rtx ix86_static_chain (const_tree, bool);
1883 static int ix86_function_regparm (const_tree, const_tree);
1884 static void ix86_compute_frame_layout (struct ix86_frame *);
1885 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1887 static void ix86_add_new_builtins (int);
1889 enum ix86_function_specific_strings
1891 IX86_FUNCTION_SPECIFIC_ARCH,
1892 IX86_FUNCTION_SPECIFIC_TUNE,
1893 IX86_FUNCTION_SPECIFIC_FPMATH,
1894 IX86_FUNCTION_SPECIFIC_MAX
1897 static char *ix86_target_string (int, int, const char *, const char *,
1898 const char *, bool);
1899 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1900 static void ix86_function_specific_save (struct cl_target_option *);
1901 static void ix86_function_specific_restore (struct cl_target_option *);
1902 static void ix86_function_specific_print (FILE *, int,
1903 struct cl_target_option *);
1904 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1905 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1906 static bool ix86_can_inline_p (tree, tree);
1907 static void ix86_set_current_function (tree);
1909 static enum calling_abi ix86_function_abi (const_tree);
1912 /* The svr4 ABI for the i386 says that records and unions are returned
1914 #ifndef DEFAULT_PCC_STRUCT_RETURN
1915 #define DEFAULT_PCC_STRUCT_RETURN 1
1918 /* Whether -mtune= or -march= were specified */
1919 static int ix86_tune_defaulted;
1920 static int ix86_arch_specified;
1922 /* Bit flags that specify the ISA we are compiling for. */
1923 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1925 /* A mask of ix86_isa_flags that includes bit X if X
1926 was set or cleared on the command line. */
1927 static int ix86_isa_flags_explicit;
1929 /* Define a set of ISAs which are available when a given ISA is
1930 enabled. MMX and SSE ISAs are handled separately. */
1932 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1933 #define OPTION_MASK_ISA_3DNOW_SET \
1934 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1936 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1937 #define OPTION_MASK_ISA_SSE2_SET \
1938 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1939 #define OPTION_MASK_ISA_SSE3_SET \
1940 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1941 #define OPTION_MASK_ISA_SSSE3_SET \
1942 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1943 #define OPTION_MASK_ISA_SSE4_1_SET \
1944 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1945 #define OPTION_MASK_ISA_SSE4_2_SET \
1946 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1947 #define OPTION_MASK_ISA_AVX_SET \
1948 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1949 #define OPTION_MASK_ISA_FMA_SET \
1950 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1952 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1954 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1956 #define OPTION_MASK_ISA_SSE4A_SET \
1957 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1959 /* AES and PCLMUL need SSE2 because they use xmm registers */
1960 #define OPTION_MASK_ISA_AES_SET \
1961 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1962 #define OPTION_MASK_ISA_PCLMUL_SET \
1963 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1965 #define OPTION_MASK_ISA_ABM_SET \
1966 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1968 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1969 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1970 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1971 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1972 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
1974 /* Define a set of ISAs which aren't available when a given ISA is
1975 disabled. MMX and SSE ISAs are handled separately. */
1977 #define OPTION_MASK_ISA_MMX_UNSET \
1978 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1979 #define OPTION_MASK_ISA_3DNOW_UNSET \
1980 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1981 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1983 #define OPTION_MASK_ISA_SSE_UNSET \
1984 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1985 #define OPTION_MASK_ISA_SSE2_UNSET \
1986 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1987 #define OPTION_MASK_ISA_SSE3_UNSET \
1988 (OPTION_MASK_ISA_SSE3 \
1989 | OPTION_MASK_ISA_SSSE3_UNSET \
1990 | OPTION_MASK_ISA_SSE4A_UNSET )
1991 #define OPTION_MASK_ISA_SSSE3_UNSET \
1992 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1993 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1994 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1995 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1996 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1997 #define OPTION_MASK_ISA_AVX_UNSET \
1998 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1999 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2001 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2003 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2005 #define OPTION_MASK_ISA_SSE4A_UNSET \
2006 (OPTION_MASK_ISA_SSE4A)
2007 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2008 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2009 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2010 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2011 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2012 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2013 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2014 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2016 /* Vectorization library interface and handlers. */
2017 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
2018 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
2019 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
2021 /* Processor target table, indexed by processor number */
2024 const struct processor_costs *cost; /* Processor costs */
2025 const int align_loop; /* Default alignments. */
2026 const int align_loop_max_skip;
2027 const int align_jump;
2028 const int align_jump_max_skip;
2029 const int align_func;
2032 static const struct ptt processor_target_table[PROCESSOR_max] =
2034 {&i386_cost, 4, 3, 4, 3, 4},
2035 {&i486_cost, 16, 15, 16, 15, 16},
2036 {&pentium_cost, 16, 7, 16, 7, 16},
2037 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2038 {&geode_cost, 0, 0, 0, 0, 0},
2039 {&k6_cost, 32, 7, 32, 7, 32},
2040 {&athlon_cost, 16, 7, 16, 7, 16},
2041 {&pentium4_cost, 0, 0, 0, 0, 0},
2042 {&k8_cost, 16, 7, 16, 7, 16},
2043 {&nocona_cost, 0, 0, 0, 0, 0},
2044 {&core2_cost, 16, 10, 16, 10, 16},
2045 {&generic32_cost, 16, 7, 16, 7, 16},
2046 {&generic64_cost, 16, 10, 16, 10, 16},
2047 {&amdfam10_cost, 32, 24, 32, 7, 32},
2048 {&atom_cost, 16, 7, 16, 7, 16}
2051 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2077 /* Implement TARGET_HANDLE_OPTION. */
2080 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
2087 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2088 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2092 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2093 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2100 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2101 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2105 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2106 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2116 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2117 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2121 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2122 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2129 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2130 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2134 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2135 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2142 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2143 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2147 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2148 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2155 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2156 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2160 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2161 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2168 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2169 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2173 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2174 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2181 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2182 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2186 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2187 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2194 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2195 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2199 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2200 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2207 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2208 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2212 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2213 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2218 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2219 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2223 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2224 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2230 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2231 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2235 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2236 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2243 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2244 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2248 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2249 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2256 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2257 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2261 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2262 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2269 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2270 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2274 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2275 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2282 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2283 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2287 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2288 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2295 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
2296 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
2300 ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
2301 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
2308 ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
2309 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
2313 ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
2314 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
2321 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2322 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2326 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2327 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2334 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2335 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2339 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2340 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2349 /* Return a string the documents the current -m options. The caller is
2350 responsible for freeing the string. */
2353 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2354 const char *fpmath, bool add_nl_p)
2356 struct ix86_target_opts
2358 const char *option; /* option string */
2359 int mask; /* isa mask options */
2362 /* This table is ordered so that options like -msse4.2 that imply
2363 preceding options while match those first. */
2364 static struct ix86_target_opts isa_opts[] =
2366 { "-m64", OPTION_MASK_ISA_64BIT },
2367 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2368 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2369 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2370 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2371 { "-msse3", OPTION_MASK_ISA_SSE3 },
2372 { "-msse2", OPTION_MASK_ISA_SSE2 },
2373 { "-msse", OPTION_MASK_ISA_SSE },
2374 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2375 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2376 { "-mmmx", OPTION_MASK_ISA_MMX },
2377 { "-mabm", OPTION_MASK_ISA_ABM },
2378 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2379 { "-mmovbe", OPTION_MASK_ISA_MOVBE },
2380 { "-mcrc32", OPTION_MASK_ISA_CRC32 },
2381 { "-maes", OPTION_MASK_ISA_AES },
2382 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2386 static struct ix86_target_opts flag_opts[] =
2388 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2389 { "-m80387", MASK_80387 },
2390 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2391 { "-malign-double", MASK_ALIGN_DOUBLE },
2392 { "-mcld", MASK_CLD },
2393 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2394 { "-mieee-fp", MASK_IEEE_FP },
2395 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2396 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2397 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2398 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2399 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2400 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2401 { "-mno-red-zone", MASK_NO_RED_ZONE },
2402 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2403 { "-mrecip", MASK_RECIP },
2404 { "-mrtd", MASK_RTD },
2405 { "-msseregparm", MASK_SSEREGPARM },
2406 { "-mstack-arg-probe", MASK_STACK_PROBE },
2407 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2410 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2413 char target_other[40];
2422 memset (opts, '\0', sizeof (opts));
2424 /* Add -march= option. */
2427 opts[num][0] = "-march=";
2428 opts[num++][1] = arch;
2431 /* Add -mtune= option. */
2434 opts[num][0] = "-mtune=";
2435 opts[num++][1] = tune;
2438 /* Pick out the options in isa options. */
2439 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2441 if ((isa & isa_opts[i].mask) != 0)
2443 opts[num++][0] = isa_opts[i].option;
2444 isa &= ~ isa_opts[i].mask;
2448 if (isa && add_nl_p)
2450 opts[num++][0] = isa_other;
2451 sprintf (isa_other, "(other isa: 0x%x)", isa);
2454 /* Add flag options. */
2455 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2457 if ((flags & flag_opts[i].mask) != 0)
2459 opts[num++][0] = flag_opts[i].option;
2460 flags &= ~ flag_opts[i].mask;
2464 if (flags && add_nl_p)
2466 opts[num++][0] = target_other;
2467 sprintf (target_other, "(other flags: 0x%x)", isa);
2470 /* Add -fpmath= option. */
2473 opts[num][0] = "-mfpmath=";
2474 opts[num++][1] = fpmath;
2481 gcc_assert (num < ARRAY_SIZE (opts));
2483 /* Size the string. */
2485 sep_len = (add_nl_p) ? 3 : 1;
2486 for (i = 0; i < num; i++)
2489 for (j = 0; j < 2; j++)
2491 len += strlen (opts[i][j]);
2494 /* Build the string. */
2495 ret = ptr = (char *) xmalloc (len);
2498 for (i = 0; i < num; i++)
2502 for (j = 0; j < 2; j++)
2503 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2510 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2518 for (j = 0; j < 2; j++)
2521 memcpy (ptr, opts[i][j], len2[j]);
2523 line_len += len2[j];
2528 gcc_assert (ret + len >= ptr);
2533 /* Function that is callable from the debugger to print the current
2536 ix86_debug_options (void)
2538 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2539 ix86_arch_string, ix86_tune_string,
2540 ix86_fpmath_string, true);
2544 fprintf (stderr, "%s\n\n", opts);
2548 fputs ("<no options>\n\n", stderr);
2553 /* Sometimes certain combinations of command options do not make
2554 sense on a particular target machine. You can define a macro
2555 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2556 defined, is executed once just after all the command options have
2559 Don't use this macro to turn on various extra optimizations for
2560 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2563 override_options (bool main_args_p)
2566 unsigned int ix86_arch_mask, ix86_tune_mask;
2571 /* Comes from final.c -- no real reason to change it. */
2572 #define MAX_CODE_ALIGN 16
2580 PTA_PREFETCH_SSE = 1 << 4,
2582 PTA_3DNOW_A = 1 << 6,
2586 PTA_POPCNT = 1 << 10,
2588 PTA_SSE4A = 1 << 12,
2589 PTA_NO_SAHF = 1 << 13,
2590 PTA_SSE4_1 = 1 << 14,
2591 PTA_SSE4_2 = 1 << 15,
2593 PTA_PCLMUL = 1 << 17,
2601 const char *const name; /* processor name or nickname. */
2602 const enum processor_type processor;
2603 const enum attr_cpu schedule;
2604 const unsigned /*enum pta_flags*/ flags;
2606 const processor_alias_table[] =
2608 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2609 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2610 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2611 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2612 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2613 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2614 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2615 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2616 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2617 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2618 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2619 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2620 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2622 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2624 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2625 PTA_MMX | PTA_SSE | PTA_SSE2},
2626 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2627 PTA_MMX |PTA_SSE | PTA_SSE2},
2628 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2629 PTA_MMX | PTA_SSE | PTA_SSE2},
2630 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2631 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2632 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2633 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2634 | PTA_CX16 | PTA_NO_SAHF},
2635 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2636 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2637 | PTA_SSSE3 | PTA_CX16},
2638 {"atom", PROCESSOR_ATOM, CPU_ATOM,
2639 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2640 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
2641 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2642 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2643 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2644 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2645 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2646 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2647 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2648 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2649 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2650 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2651 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2652 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2653 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2654 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2655 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2656 {"x86-64", PROCESSOR_K8, CPU_K8,
2657 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2658 {"k8", PROCESSOR_K8, CPU_K8,
2659 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2660 | PTA_SSE2 | PTA_NO_SAHF},
2661 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2662 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2663 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2664 {"opteron", PROCESSOR_K8, CPU_K8,
2665 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2666 | PTA_SSE2 | PTA_NO_SAHF},
2667 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2668 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2669 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2670 {"athlon64", PROCESSOR_K8, CPU_K8,
2671 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2672 | PTA_SSE2 | PTA_NO_SAHF},
2673 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2674 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2675 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2676 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2677 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2678 | PTA_SSE2 | PTA_NO_SAHF},
2679 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2680 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2681 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2682 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2683 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2684 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2685 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2686 0 /* flags are only used for -march switch. */ },
2687 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2688 PTA_64BIT /* flags are only used for -march switch. */ },
2691 int const pta_size = ARRAY_SIZE (processor_alias_table);
2693 /* Set up prefix/suffix so the error messages refer to either the command
2694 line argument, or the attribute(target). */
2703 prefix = "option(\"";
2708 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2709 SUBTARGET_OVERRIDE_OPTIONS;
2712 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2713 SUBSUBTARGET_OVERRIDE_OPTIONS;
2716 /* -fPIC is the default for x86_64. */
2717 if (TARGET_MACHO && TARGET_64BIT)
2720 /* Set the default values for switches whose default depends on TARGET_64BIT
2721 in case they weren't overwritten by command line options. */
2724 /* Mach-O doesn't support omitting the frame pointer for now. */
2725 if (flag_omit_frame_pointer == 2)
2726 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2727 if (flag_asynchronous_unwind_tables == 2)
2728 flag_asynchronous_unwind_tables = 1;
2729 if (flag_pcc_struct_return == 2)
2730 flag_pcc_struct_return = 0;
2734 if (flag_omit_frame_pointer == 2)
2735 flag_omit_frame_pointer = 0;
2736 if (flag_asynchronous_unwind_tables == 2)
2737 flag_asynchronous_unwind_tables = 0;
2738 if (flag_pcc_struct_return == 2)
2739 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2742 /* Need to check -mtune=generic first. */
2743 if (ix86_tune_string)
2745 if (!strcmp (ix86_tune_string, "generic")
2746 || !strcmp (ix86_tune_string, "i686")
2747 /* As special support for cross compilers we read -mtune=native
2748 as -mtune=generic. With native compilers we won't see the
2749 -mtune=native, as it was changed by the driver. */
2750 || !strcmp (ix86_tune_string, "native"))
2753 ix86_tune_string = "generic64";
2755 ix86_tune_string = "generic32";
2757 /* If this call is for setting the option attribute, allow the
2758 generic32/generic64 that was previously set. */
2759 else if (!main_args_p
2760 && (!strcmp (ix86_tune_string, "generic32")
2761 || !strcmp (ix86_tune_string, "generic64")))
2763 else if (!strncmp (ix86_tune_string, "generic", 7))
2764 error ("bad value (%s) for %stune=%s %s",
2765 ix86_tune_string, prefix, suffix, sw);
2769 if (ix86_arch_string)
2770 ix86_tune_string = ix86_arch_string;
2771 if (!ix86_tune_string)
2773 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2774 ix86_tune_defaulted = 1;
2777 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2778 need to use a sensible tune option. */
2779 if (!strcmp (ix86_tune_string, "generic")
2780 || !strcmp (ix86_tune_string, "x86-64")
2781 || !strcmp (ix86_tune_string, "i686"))
2784 ix86_tune_string = "generic64";
2786 ix86_tune_string = "generic32";
2789 if (ix86_stringop_string)
2791 if (!strcmp (ix86_stringop_string, "rep_byte"))
2792 stringop_alg = rep_prefix_1_byte;
2793 else if (!strcmp (ix86_stringop_string, "libcall"))
2794 stringop_alg = libcall;
2795 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2796 stringop_alg = rep_prefix_4_byte;
2797 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2799 /* rep; movq isn't available in 32-bit code. */
2800 stringop_alg = rep_prefix_8_byte;
2801 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2802 stringop_alg = loop_1_byte;
2803 else if (!strcmp (ix86_stringop_string, "loop"))
2804 stringop_alg = loop;
2805 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2806 stringop_alg = unrolled_loop;
2808 error ("bad value (%s) for %sstringop-strategy=%s %s",
2809 ix86_stringop_string, prefix, suffix, sw);
2811 if (!strcmp (ix86_tune_string, "x86-64"))
2812 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2813 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2814 prefix, suffix, prefix, suffix, prefix, suffix);
2816 if (!ix86_arch_string)
2817 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2819 ix86_arch_specified = 1;
2821 if (!strcmp (ix86_arch_string, "generic"))
2822 error ("generic CPU can be used only for %stune=%s %s",
2823 prefix, suffix, sw);
2824 if (!strncmp (ix86_arch_string, "generic", 7))
2825 error ("bad value (%s) for %sarch=%s %s",
2826 ix86_arch_string, prefix, suffix, sw);
2828 /* Validate -mabi= value. */
2829 if (ix86_abi_string)
2831 if (strcmp (ix86_abi_string, "sysv") == 0)
2832 ix86_abi = SYSV_ABI;
2833 else if (strcmp (ix86_abi_string, "ms") == 0)
2836 error ("unknown ABI (%s) for %sabi=%s %s",
2837 ix86_abi_string, prefix, suffix, sw);
2840 ix86_abi = DEFAULT_ABI;
2842 if (ix86_cmodel_string != 0)
2844 if (!strcmp (ix86_cmodel_string, "small"))
2845 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2846 else if (!strcmp (ix86_cmodel_string, "medium"))
2847 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2848 else if (!strcmp (ix86_cmodel_string, "large"))
2849 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2851 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2852 else if (!strcmp (ix86_cmodel_string, "32"))
2853 ix86_cmodel = CM_32;
2854 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2855 ix86_cmodel = CM_KERNEL;
2857 error ("bad value (%s) for %scmodel=%s %s",
2858 ix86_cmodel_string, prefix, suffix, sw);
2862 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2863 use of rip-relative addressing. This eliminates fixups that
2864 would otherwise be needed if this object is to be placed in a
2865 DLL, and is essentially just as efficient as direct addressing. */
2866 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2867 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2868 else if (TARGET_64BIT)
2869 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2871 ix86_cmodel = CM_32;
2873 if (ix86_asm_string != 0)
2876 && !strcmp (ix86_asm_string, "intel"))
2877 ix86_asm_dialect = ASM_INTEL;
2878 else if (!strcmp (ix86_asm_string, "att"))
2879 ix86_asm_dialect = ASM_ATT;
2881 error ("bad value (%s) for %sasm=%s %s",
2882 ix86_asm_string, prefix, suffix, sw);
2884 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2885 error ("code model %qs not supported in the %s bit mode",
2886 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2887 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2888 sorry ("%i-bit mode not compiled in",
2889 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2891 for (i = 0; i < pta_size; i++)
2892 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2894 ix86_schedule = processor_alias_table[i].schedule;
2895 ix86_arch = processor_alias_table[i].processor;
2896 /* Default cpu tuning to the architecture. */
2897 ix86_tune = ix86_arch;
2899 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2900 error ("CPU you selected does not support x86-64 "
2903 if (processor_alias_table[i].flags & PTA_MMX
2904 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2905 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2906 if (processor_alias_table[i].flags & PTA_3DNOW
2907 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2908 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2909 if (processor_alias_table[i].flags & PTA_3DNOW_A
2910 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2911 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2912 if (processor_alias_table[i].flags & PTA_SSE
2913 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2914 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2915 if (processor_alias_table[i].flags & PTA_SSE2
2916 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2917 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2918 if (processor_alias_table[i].flags & PTA_SSE3
2919 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2920 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2921 if (processor_alias_table[i].flags & PTA_SSSE3
2922 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2923 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2924 if (processor_alias_table[i].flags & PTA_SSE4_1
2925 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2926 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2927 if (processor_alias_table[i].flags & PTA_SSE4_2
2928 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2929 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2930 if (processor_alias_table[i].flags & PTA_AVX
2931 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2932 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2933 if (processor_alias_table[i].flags & PTA_FMA
2934 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2935 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2936 if (processor_alias_table[i].flags & PTA_SSE4A
2937 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2938 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2939 if (processor_alias_table[i].flags & PTA_ABM
2940 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2941 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2942 if (processor_alias_table[i].flags & PTA_CX16
2943 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2944 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2945 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2946 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2947 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2948 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2949 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2950 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2951 if (processor_alias_table[i].flags & PTA_MOVBE
2952 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
2953 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
2954 if (processor_alias_table[i].flags & PTA_AES
2955 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2956 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2957 if (processor_alias_table[i].flags & PTA_PCLMUL
2958 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2959 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2960 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2961 x86_prefetch_sse = true;
2967 error ("bad value (%s) for %sarch=%s %s",
2968 ix86_arch_string, prefix, suffix, sw);
2970 ix86_arch_mask = 1u << ix86_arch;
2971 for (i = 0; i < X86_ARCH_LAST; ++i)
2972 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2974 for (i = 0; i < pta_size; i++)
2975 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2977 ix86_schedule = processor_alias_table[i].schedule;
2978 ix86_tune = processor_alias_table[i].processor;
2979 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2981 if (ix86_tune_defaulted)
2983 ix86_tune_string = "x86-64";
2984 for (i = 0; i < pta_size; i++)
2985 if (! strcmp (ix86_tune_string,
2986 processor_alias_table[i].name))
2988 ix86_schedule = processor_alias_table[i].schedule;
2989 ix86_tune = processor_alias_table[i].processor;
2992 error ("CPU you selected does not support x86-64 "
2995 /* Intel CPUs have always interpreted SSE prefetch instructions as
2996 NOPs; so, we can enable SSE prefetch instructions even when
2997 -mtune (rather than -march) points us to a processor that has them.
2998 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2999 higher processors. */
3001 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
3002 x86_prefetch_sse = true;
3006 error ("bad value (%s) for %stune=%s %s",
3007 ix86_tune_string, prefix, suffix, sw);
3009 ix86_tune_mask = 1u << ix86_tune;
3010 for (i = 0; i < X86_TUNE_LAST; ++i)
3011 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3014 ix86_cost = &ix86_size_cost;
3016 ix86_cost = processor_target_table[ix86_tune].cost;
3018 /* Arrange to set up i386_stack_locals for all functions. */
3019 init_machine_status = ix86_init_machine_status;
3021 /* Validate -mregparm= value. */
3022 if (ix86_regparm_string)
3025 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
3026 i = atoi (ix86_regparm_string);
3027 if (i < 0 || i > REGPARM_MAX)
3028 error ("%sregparm=%d%s is not between 0 and %d",
3029 prefix, i, suffix, REGPARM_MAX);
3034 ix86_regparm = REGPARM_MAX;
3036 /* If the user has provided any of the -malign-* options,
3037 warn and use that value only if -falign-* is not set.
3038 Remove this code in GCC 3.2 or later. */
3039 if (ix86_align_loops_string)
3041 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
3042 prefix, suffix, suffix);
3043 if (align_loops == 0)
3045 i = atoi (ix86_align_loops_string);
3046 if (i < 0 || i > MAX_CODE_ALIGN)
3047 error ("%salign-loops=%d%s is not between 0 and %d",
3048 prefix, i, suffix, MAX_CODE_ALIGN);
3050 align_loops = 1 << i;
3054 if (ix86_align_jumps_string)
3056 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
3057 prefix, suffix, suffix);
3058 if (align_jumps == 0)
3060 i = atoi (ix86_align_jumps_string);
3061 if (i < 0 || i > MAX_CODE_ALIGN)
3062 error ("%salign-loops=%d%s is not between 0 and %d",
3063 prefix, i, suffix, MAX_CODE_ALIGN);
3065 align_jumps = 1 << i;
3069 if (ix86_align_funcs_string)
3071 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
3072 prefix, suffix, suffix);
3073 if (align_functions == 0)
3075 i = atoi (ix86_align_funcs_string);
3076 if (i < 0 || i > MAX_CODE_ALIGN)
3077 error ("%salign-loops=%d%s is not between 0 and %d",
3078 prefix, i, suffix, MAX_CODE_ALIGN);
3080 align_functions = 1 << i;
3084 /* Default align_* from the processor table. */
3085 if (align_loops == 0)
3087 align_loops = processor_target_table[ix86_tune].align_loop;
3088 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
3090 if (align_jumps == 0)
3092 align_jumps = processor_target_table[ix86_tune].align_jump;
3093 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
3095 if (align_functions == 0)
3097 align_functions = processor_target_table[ix86_tune].align_func;
3100 /* Validate -mbranch-cost= value, or provide default. */
3101 ix86_branch_cost = ix86_cost->branch_cost;
3102 if (ix86_branch_cost_string)
3104 i = atoi (ix86_branch_cost_string);
3106 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
3108 ix86_branch_cost = i;
3110 if (ix86_section_threshold_string)
3112 i = atoi (ix86_section_threshold_string);
3114 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
3116 ix86_section_threshold = i;
3119 if (ix86_tls_dialect_string)
3121 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3122 ix86_tls_dialect = TLS_DIALECT_GNU;
3123 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3124 ix86_tls_dialect = TLS_DIALECT_GNU2;
3125 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3126 ix86_tls_dialect = TLS_DIALECT_SUN;
3128 error ("bad value (%s) for %stls-dialect=%s %s",
3129 ix86_tls_dialect_string, prefix, suffix, sw);
3132 if (ix87_precision_string)
3134 i = atoi (ix87_precision_string);
3135 if (i != 32 && i != 64 && i != 80)
3136 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3141 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3143 /* Enable by default the SSE and MMX builtins. Do allow the user to
3144 explicitly disable any of these. In particular, disabling SSE and
3145 MMX for kernel code is extremely useful. */
3146 if (!ix86_arch_specified)
3148 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3149 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3152 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3156 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3158 if (!ix86_arch_specified)
3160 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3162 /* i386 ABI does not specify red zone. It still makes sense to use it
3163 when programmer takes care to stack from being destroyed. */
3164 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3165 target_flags |= MASK_NO_RED_ZONE;
3168 /* Keep nonleaf frame pointers. */
3169 if (flag_omit_frame_pointer)
3170 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3171 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3172 flag_omit_frame_pointer = 1;
3174 /* If we're doing fast math, we don't care about comparison order
3175 wrt NaNs. This lets us use a shorter comparison sequence. */
3176 if (flag_finite_math_only)
3177 target_flags &= ~MASK_IEEE_FP;
3179 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3180 since the insns won't need emulation. */
3181 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3182 target_flags &= ~MASK_NO_FANCY_MATH_387;
3184 /* Likewise, if the target doesn't have a 387, or we've specified
3185 software floating point, don't use 387 inline intrinsics. */
3187 target_flags |= MASK_NO_FANCY_MATH_387;
3189 /* Turn on MMX builtins for -msse. */
3192 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3193 x86_prefetch_sse = true;
3196 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3197 if (TARGET_SSE4_2 || TARGET_ABM)
3198 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3200 /* Validate -mpreferred-stack-boundary= value or default it to
3201 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3202 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3203 if (ix86_preferred_stack_boundary_string)
3205 i = atoi (ix86_preferred_stack_boundary_string);
3206 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3207 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3208 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3210 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3213 /* Set the default value for -mstackrealign. */
3214 if (ix86_force_align_arg_pointer == -1)
3215 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3217 /* Validate -mincoming-stack-boundary= value or default it to
3218 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3219 if (ix86_force_align_arg_pointer)
3220 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3222 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3223 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3224 if (ix86_incoming_stack_boundary_string)
3226 i = atoi (ix86_incoming_stack_boundary_string);
3227 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3228 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3229 i, TARGET_64BIT ? 4 : 2);
3232 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3233 ix86_incoming_stack_boundary
3234 = ix86_user_incoming_stack_boundary;
3238 /* Accept -msseregparm only if at least SSE support is enabled. */
3239 if (TARGET_SSEREGPARM
3241 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3243 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3244 if (ix86_fpmath_string != 0)
3246 if (! strcmp (ix86_fpmath_string, "387"))
3247 ix86_fpmath = FPMATH_387;
3248 else if (! strcmp (ix86_fpmath_string, "sse"))
3252 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3253 ix86_fpmath = FPMATH_387;
3256 ix86_fpmath = FPMATH_SSE;
3258 else if (! strcmp (ix86_fpmath_string, "387,sse")
3259 || ! strcmp (ix86_fpmath_string, "387+sse")
3260 || ! strcmp (ix86_fpmath_string, "sse,387")
3261 || ! strcmp (ix86_fpmath_string, "sse+387")
3262 || ! strcmp (ix86_fpmath_string, "both"))
3266 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3267 ix86_fpmath = FPMATH_387;
3269 else if (!TARGET_80387)
3271 warning (0, "387 instruction set disabled, using SSE arithmetics");
3272 ix86_fpmath = FPMATH_SSE;
3275 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3278 error ("bad value (%s) for %sfpmath=%s %s",
3279 ix86_fpmath_string, prefix, suffix, sw);
3282 /* If the i387 is disabled, then do not return values in it. */
3284 target_flags &= ~MASK_FLOAT_RETURNS;
3286 /* Use external vectorized library in vectorizing intrinsics. */
3287 if (ix86_veclibabi_string)
3289 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3290 ix86_veclib_handler = ix86_veclibabi_svml;
3291 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3292 ix86_veclib_handler = ix86_veclibabi_acml;
3294 error ("unknown vectorization library ABI type (%s) for "
3295 "%sveclibabi=%s %s", ix86_veclibabi_string,
3296 prefix, suffix, sw);
3299 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3300 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3302 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3304 /* ??? Unwind info is not correct around the CFG unless either a frame
3305 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3306 unwind info generation to be aware of the CFG and propagating states
3308 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3309 || flag_exceptions || flag_non_call_exceptions)
3310 && flag_omit_frame_pointer
3311 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3313 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3314 warning (0, "unwind tables currently require either a frame pointer "
3315 "or %saccumulate-outgoing-args%s for correctness",
3317 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3320 /* If stack probes are required, the space used for large function
3321 arguments on the stack must also be probed, so enable
3322 -maccumulate-outgoing-args so this happens in the prologue. */
3323 if (TARGET_STACK_PROBE
3324 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3326 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3327 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3328 "for correctness", prefix, suffix);
3329 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3332 /* For sane SSE instruction set generation we need fcomi instruction.
3333 It is safe to enable all CMOVE instructions. */
3337 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3340 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3341 p = strchr (internal_label_prefix, 'X');
3342 internal_label_prefix_len = p - internal_label_prefix;
3346 /* When scheduling description is not available, disable scheduler pass
3347 so it won't slow down the compilation and make x87 code slower. */
3348 if (!TARGET_SCHEDULE)
3349 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3351 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3352 set_param_value ("simultaneous-prefetches",
3353 ix86_cost->simultaneous_prefetches);
3354 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3355 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3356 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3357 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3358 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3359 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3361 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3362 can be optimized to ap = __builtin_next_arg (0). */
3364 targetm.expand_builtin_va_start = NULL;
3368 ix86_gen_leave = gen_leave_rex64;
3369 ix86_gen_pop1 = gen_popdi1;
3370 ix86_gen_add3 = gen_adddi3;
3371 ix86_gen_sub3 = gen_subdi3;
3372 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3373 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3374 ix86_gen_monitor = gen_sse3_monitor64;
3375 ix86_gen_andsp = gen_anddi3;
3379 ix86_gen_leave = gen_leave;
3380 ix86_gen_pop1 = gen_popsi1;
3381 ix86_gen_add3 = gen_addsi3;
3382 ix86_gen_sub3 = gen_subsi3;
3383 ix86_gen_sub3_carry = gen_subsi3_carry;
3384 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3385 ix86_gen_monitor = gen_sse3_monitor;
3386 ix86_gen_andsp = gen_andsi3;
3390 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3392 target_flags |= MASK_CLD & ~target_flags_explicit;
3395 /* Save the initial options in case the user does function specific options */
3397 target_option_default_node = target_option_current_node
3398 = build_target_option_node ();
3401 /* Update register usage after having seen the compiler flags. */
3404 ix86_conditional_register_usage (void)
3409 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3411 if (fixed_regs[i] > 1)
3412 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3413 if (call_used_regs[i] > 1)
3414 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3417 /* The PIC register, if it exists, is fixed. */
3418 j = PIC_OFFSET_TABLE_REGNUM;
3419 if (j != INVALID_REGNUM)
3420 fixed_regs[j] = call_used_regs[j] = 1;
3422 /* The MS_ABI changes the set of call-used registers. */
3423 if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
3425 call_used_regs[SI_REG] = 0;
3426 call_used_regs[DI_REG] = 0;
3427 call_used_regs[XMM6_REG] = 0;
3428 call_used_regs[XMM7_REG] = 0;
3429 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3430 call_used_regs[i] = 0;
3433 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3434 other call-clobbered regs for 64-bit. */
3437 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3439 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3440 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3441 && call_used_regs[i])
3442 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3445 /* If MMX is disabled, squash the registers. */
3447 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3448 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3449 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3451 /* If SSE is disabled, squash the registers. */
3453 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3454 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3455 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3457 /* If the FPU is disabled, squash the registers. */
3458 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3459 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3460 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3461 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3463 /* If 32-bit, squash the 64-bit registers. */
3466 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3468 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3474 /* Save the current options */
3477 ix86_function_specific_save (struct cl_target_option *ptr)
3479 ptr->arch = ix86_arch;
3480 ptr->schedule = ix86_schedule;
3481 ptr->tune = ix86_tune;
3482 ptr->fpmath = ix86_fpmath;
3483 ptr->branch_cost = ix86_branch_cost;
3484 ptr->tune_defaulted = ix86_tune_defaulted;
3485 ptr->arch_specified = ix86_arch_specified;
3486 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3487 ptr->target_flags_explicit = target_flags_explicit;
3489 /* The fields are char but the variables are not; make sure the
3490 values fit in the fields. */
3491 gcc_assert (ptr->arch == ix86_arch);
3492 gcc_assert (ptr->schedule == ix86_schedule);
3493 gcc_assert (ptr->tune == ix86_tune);
3494 gcc_assert (ptr->fpmath == ix86_fpmath);
3495 gcc_assert (ptr->branch_cost == ix86_branch_cost);
3498 /* Restore the current options */
3501 ix86_function_specific_restore (struct cl_target_option *ptr)
3503 enum processor_type old_tune = ix86_tune;
3504 enum processor_type old_arch = ix86_arch;
3505 unsigned int ix86_arch_mask, ix86_tune_mask;
3508 ix86_arch = (enum processor_type) ptr->arch;
3509 ix86_schedule = (enum attr_cpu) ptr->schedule;
3510 ix86_tune = (enum processor_type) ptr->tune;
3511 ix86_fpmath = (enum fpmath_unit) ptr->fpmath;
3512 ix86_branch_cost = ptr->branch_cost;
3513 ix86_tune_defaulted = ptr->tune_defaulted;
3514 ix86_arch_specified = ptr->arch_specified;
3515 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3516 target_flags_explicit = ptr->target_flags_explicit;
3518 /* Recreate the arch feature tests if the arch changed */
3519 if (old_arch != ix86_arch)
3521 ix86_arch_mask = 1u << ix86_arch;
3522 for (i = 0; i < X86_ARCH_LAST; ++i)
3523 ix86_arch_features[i]
3524 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3527 /* Recreate the tune optimization tests */
3528 if (old_tune != ix86_tune)
3530 ix86_tune_mask = 1u << ix86_tune;
3531 for (i = 0; i < X86_TUNE_LAST; ++i)
3532 ix86_tune_features[i]
3533 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3537 /* Print the current options */
3540 ix86_function_specific_print (FILE *file, int indent,
3541 struct cl_target_option *ptr)
3544 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3545 NULL, NULL, NULL, false);
3547 fprintf (file, "%*sarch = %d (%s)\n",
3550 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3551 ? cpu_names[ptr->arch]
3554 fprintf (file, "%*stune = %d (%s)\n",
3557 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3558 ? cpu_names[ptr->tune]
3561 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3562 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3563 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3564 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3568 fprintf (file, "%*s%s\n", indent, "", target_string);
3569 free (target_string);
3574 /* Inner function to process the attribute((target(...))), take an argument and
3575 set the current options from the argument. If we have a list, recursively go
3579 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3584 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3585 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3586 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3587 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3602 enum ix86_opt_type type;
3607 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3608 IX86_ATTR_ISA ("abm", OPT_mabm),
3609 IX86_ATTR_ISA ("aes", OPT_maes),
3610 IX86_ATTR_ISA ("avx", OPT_mavx),
3611 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3612 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3613 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3614 IX86_ATTR_ISA ("sse", OPT_msse),
3615 IX86_ATTR_ISA ("sse2", OPT_msse2),
3616 IX86_ATTR_ISA ("sse3", OPT_msse3),
3617 IX86_ATTR_ISA ("sse4", OPT_msse4),
3618 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3619 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3620 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3621 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3623 /* string options */
3624 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3625 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3626 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3629 IX86_ATTR_YES ("cld",
3633 IX86_ATTR_NO ("fancy-math-387",
3634 OPT_mfancy_math_387,
3635 MASK_NO_FANCY_MATH_387),
3637 IX86_ATTR_YES ("ieee-fp",
3641 IX86_ATTR_YES ("inline-all-stringops",
3642 OPT_minline_all_stringops,
3643 MASK_INLINE_ALL_STRINGOPS),
3645 IX86_ATTR_YES ("inline-stringops-dynamically",
3646 OPT_minline_stringops_dynamically,
3647 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3649 IX86_ATTR_NO ("align-stringops",
3650 OPT_mno_align_stringops,
3651 MASK_NO_ALIGN_STRINGOPS),
3653 IX86_ATTR_YES ("recip",
3659 /* If this is a list, recurse to get the options. */
3660 if (TREE_CODE (args) == TREE_LIST)
3664 for (; args; args = TREE_CHAIN (args))
3665 if (TREE_VALUE (args)
3666 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3672 else if (TREE_CODE (args) != STRING_CST)
3675 /* Handle multiple arguments separated by commas. */
3676 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3678 while (next_optstr && *next_optstr != '\0')
3680 char *p = next_optstr;
3682 char *comma = strchr (next_optstr, ',');
3683 const char *opt_string;
3684 size_t len, opt_len;
3689 enum ix86_opt_type type = ix86_opt_unknown;
3695 len = comma - next_optstr;
3696 next_optstr = comma + 1;
3704 /* Recognize no-xxx. */
3705 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3714 /* Find the option. */
3717 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3719 type = attrs[i].type;
3720 opt_len = attrs[i].len;
3721 if (ch == attrs[i].string[0]
3722 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3723 && memcmp (p, attrs[i].string, opt_len) == 0)
3726 mask = attrs[i].mask;
3727 opt_string = attrs[i].string;
3732 /* Process the option. */
3735 error ("attribute(target(\"%s\")) is unknown", orig_p);
3739 else if (type == ix86_opt_isa)
3740 ix86_handle_option (opt, p, opt_set_p);
3742 else if (type == ix86_opt_yes || type == ix86_opt_no)
3744 if (type == ix86_opt_no)
3745 opt_set_p = !opt_set_p;
3748 target_flags |= mask;
3750 target_flags &= ~mask;
3753 else if (type == ix86_opt_str)
3757 error ("option(\"%s\") was already specified", opt_string);
3761 p_strings[opt] = xstrdup (p + opt_len);
3771 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3774 ix86_valid_target_attribute_tree (tree args)
3776 const char *orig_arch_string = ix86_arch_string;
3777 const char *orig_tune_string = ix86_tune_string;
3778 const char *orig_fpmath_string = ix86_fpmath_string;
3779 int orig_tune_defaulted = ix86_tune_defaulted;
3780 int orig_arch_specified = ix86_arch_specified;
3781 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3784 struct cl_target_option *def
3785 = TREE_TARGET_OPTION (target_option_default_node);
3787 /* Process each of the options on the chain. */
3788 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3791 /* If the changed options are different from the default, rerun override_options,
3792 and then save the options away. The string options are are attribute options,
3793 and will be undone when we copy the save structure. */
3794 if (ix86_isa_flags != def->ix86_isa_flags
3795 || target_flags != def->target_flags
3796 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3797 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3798 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3800 /* If we are using the default tune= or arch=, undo the string assigned,
3801 and use the default. */
3802 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3803 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3804 else if (!orig_arch_specified)
3805 ix86_arch_string = NULL;
3807 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3808 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3809 else if (orig_tune_defaulted)
3810 ix86_tune_string = NULL;
3812 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3813 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3814 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3815 else if (!TARGET_64BIT && TARGET_SSE)
3816 ix86_fpmath_string = "sse,387";
3818 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3819 override_options (false);
3821 /* Add any builtin functions with the new isa if any. */
3822 ix86_add_new_builtins (ix86_isa_flags);
3824 /* Save the current options unless we are validating options for
3826 t = build_target_option_node ();
3828 ix86_arch_string = orig_arch_string;
3829 ix86_tune_string = orig_tune_string;
3830 ix86_fpmath_string = orig_fpmath_string;
3832 /* Free up memory allocated to hold the strings */
3833 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3834 if (option_strings[i])
3835 free (option_strings[i]);
3841 /* Hook to validate attribute((target("string"))). */
3844 ix86_valid_target_attribute_p (tree fndecl,
3845 tree ARG_UNUSED (name),
3847 int ARG_UNUSED (flags))
3849 struct cl_target_option cur_target;
3851 tree old_optimize = build_optimization_node ();
3852 tree new_target, new_optimize;
3853 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3855 /* If the function changed the optimization levels as well as setting target
3856 options, start with the optimizations specified. */
3857 if (func_optimize && func_optimize != old_optimize)
3858 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3860 /* The target attributes may also change some optimization flags, so update
3861 the optimization options if necessary. */
3862 cl_target_option_save (&cur_target);
3863 new_target = ix86_valid_target_attribute_tree (args);
3864 new_optimize = build_optimization_node ();
3871 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3873 if (old_optimize != new_optimize)
3874 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3877 cl_target_option_restore (&cur_target);
3879 if (old_optimize != new_optimize)
3880 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3886 /* Hook to determine if one function can safely inline another. */
3889 ix86_can_inline_p (tree caller, tree callee)
3892 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3893 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3895 /* If callee has no option attributes, then it is ok to inline. */
3899 /* If caller has no option attributes, but callee does then it is not ok to
3901 else if (!caller_tree)
3906 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3907 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3909 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
3910 can inline a SSE2 function but a SSE2 function can't inline a SSE4
3912 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3913 != callee_opts->ix86_isa_flags)
3916 /* See if we have the same non-isa options. */
3917 else if (caller_opts->target_flags != callee_opts->target_flags)
3920 /* See if arch, tune, etc. are the same. */
3921 else if (caller_opts->arch != callee_opts->arch)
3924 else if (caller_opts->tune != callee_opts->tune)
3927 else if (caller_opts->fpmath != callee_opts->fpmath)
3930 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3941 /* Remember the last target of ix86_set_current_function. */
3942 static GTY(()) tree ix86_previous_fndecl;
3944 /* Establish appropriate back-end context for processing the function
3945 FNDECL. The argument might be NULL to indicate processing at top
3946 level, outside of any function scope. */
3948 ix86_set_current_function (tree fndecl)
3950 /* Only change the context if the function changes. This hook is called
3951 several times in the course of compiling a function, and we don't want to
3952 slow things down too much or call target_reinit when it isn't safe. */
3953 if (fndecl && fndecl != ix86_previous_fndecl)
3955 tree old_tree = (ix86_previous_fndecl
3956 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3959 tree new_tree = (fndecl
3960 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3963 ix86_previous_fndecl = fndecl;
3964 if (old_tree == new_tree)
3969 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3975 struct cl_target_option *def
3976 = TREE_TARGET_OPTION (target_option_current_node);
3978 cl_target_option_restore (def);
3985 /* Return true if this goes in large data/bss. */
3988 ix86_in_large_data_p (tree exp)
3990 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3993 /* Functions are never large data. */
3994 if (TREE_CODE (exp) == FUNCTION_DECL)
3997 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3999 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
4000 if (strcmp (section, ".ldata") == 0
4001 || strcmp (section, ".lbss") == 0)
4007 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
4009 /* If this is an incomplete type with size 0, then we can't put it
4010 in data because it might be too big when completed. */
4011 if (!size || size > ix86_section_threshold)
4018 /* Switch to the appropriate section for output of DECL.
4019 DECL is either a `VAR_DECL' node or a constant of some sort.
4020 RELOC indicates whether forming the initial value of DECL requires
4021 link-time relocations. */
4023 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
4027 x86_64_elf_select_section (tree decl, int reloc,
4028 unsigned HOST_WIDE_INT align)
4030 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4031 && ix86_in_large_data_p (decl))
4033 const char *sname = NULL;
4034 unsigned int flags = SECTION_WRITE;
4035 switch (categorize_decl_for_section (decl, reloc))
4040 case SECCAT_DATA_REL:
4041 sname = ".ldata.rel";
4043 case SECCAT_DATA_REL_LOCAL:
4044 sname = ".ldata.rel.local";
4046 case SECCAT_DATA_REL_RO:
4047 sname = ".ldata.rel.ro";
4049 case SECCAT_DATA_REL_RO_LOCAL:
4050 sname = ".ldata.rel.ro.local";
4054 flags |= SECTION_BSS;
4057 case SECCAT_RODATA_MERGE_STR:
4058 case SECCAT_RODATA_MERGE_STR_INIT:
4059 case SECCAT_RODATA_MERGE_CONST:
4063 case SECCAT_SRODATA:
4070 /* We don't split these for medium model. Place them into
4071 default sections and hope for best. */
4073 case SECCAT_EMUTLS_VAR:
4074 case SECCAT_EMUTLS_TMPL:
4079 /* We might get called with string constants, but get_named_section
4080 doesn't like them as they are not DECLs. Also, we need to set
4081 flags in that case. */
4083 return get_section (sname, flags, NULL);
4084 return get_named_section (decl, sname, reloc);
4087 return default_elf_select_section (decl, reloc, align);
4090 /* Build up a unique section name, expressed as a
4091 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4092 RELOC indicates whether the initial value of EXP requires
4093 link-time relocations. */
4095 static void ATTRIBUTE_UNUSED
4096 x86_64_elf_unique_section (tree decl, int reloc)
4098 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4099 && ix86_in_large_data_p (decl))
4101 const char *prefix = NULL;
4102 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4103 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
4105 switch (categorize_decl_for_section (decl, reloc))
4108 case SECCAT_DATA_REL:
4109 case SECCAT_DATA_REL_LOCAL:
4110 case SECCAT_DATA_REL_RO:
4111 case SECCAT_DATA_REL_RO_LOCAL:
4112 prefix = one_only ? ".ld" : ".ldata";
4115 prefix = one_only ? ".lb" : ".lbss";
4118 case SECCAT_RODATA_MERGE_STR:
4119 case SECCAT_RODATA_MERGE_STR_INIT:
4120 case SECCAT_RODATA_MERGE_CONST:
4121 prefix = one_only ? ".lr" : ".lrodata";
4123 case SECCAT_SRODATA:
4130 /* We don't split these for medium model. Place them into
4131 default sections and hope for best. */
4133 case SECCAT_EMUTLS_VAR:
4134 prefix = targetm.emutls.var_section;
4136 case SECCAT_EMUTLS_TMPL:
4137 prefix = targetm.emutls.tmpl_section;
4142 const char *name, *linkonce;
4145 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4146 name = targetm.strip_name_encoding (name);
4148 /* If we're using one_only, then there needs to be a .gnu.linkonce
4149 prefix to the section name. */
4150 linkonce = one_only ? ".gnu.linkonce" : "";
4152 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4154 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4158 default_unique_section (decl, reloc);
4161 #ifdef COMMON_ASM_OP
4162 /* This says how to output assembler code to declare an
4163 uninitialized external linkage data object.
4165 For medium model x86-64 we need to use .largecomm opcode for
4168 x86_elf_aligned_common (FILE *file,
4169 const char *name, unsigned HOST_WIDE_INT size,
4172 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4173 && size > (unsigned int)ix86_section_threshold)
4174 fputs (".largecomm\t", file);
4176 fputs (COMMON_ASM_OP, file);
4177 assemble_name (file, name);
4178 fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
4179 size, align / BITS_PER_UNIT);
4183 /* Utility function for targets to use in implementing
4184 ASM_OUTPUT_ALIGNED_BSS. */
4187 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4188 const char *name, unsigned HOST_WIDE_INT size,
4191 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4192 && size > (unsigned int)ix86_section_threshold)
4193 switch_to_section (get_named_section (decl, ".lbss", 0));
4195 switch_to_section (bss_section);
4196 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4197 #ifdef ASM_DECLARE_OBJECT_NAME
4198 last_assemble_variable_decl = decl;
4199 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4201 /* Standard thing is just output label for the object. */
4202 ASM_OUTPUT_LABEL (file, name);
4203 #endif /* ASM_DECLARE_OBJECT_NAME */
4204 ASM_OUTPUT_SKIP (file, size ? size : 1);
4208 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4210 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4211 make the problem with not enough registers even worse. */
4212 #ifdef INSN_SCHEDULING
4214 flag_schedule_insns = 0;
4218 /* The Darwin libraries never set errno, so we might as well
4219 avoid calling them when that's the only reason we would. */
4220 flag_errno_math = 0;
4222 /* The default values of these switches depend on the TARGET_64BIT
4223 that is not known at this moment. Mark these values with 2 and
4224 let user the to override these. In case there is no command line option
4225 specifying them, we will set the defaults in override_options. */
4227 flag_omit_frame_pointer = 2;
4228 flag_pcc_struct_return = 2;
4229 flag_asynchronous_unwind_tables = 2;
4230 flag_vect_cost_model = 1;
4231 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4232 SUBTARGET_OPTIMIZATION_OPTIONS;
4236 /* Decide whether we can make a sibling call to a function. DECL is the
4237 declaration of the function being targeted by the call and EXP is the
4238 CALL_EXPR representing the call. */
4241 ix86_function_ok_for_sibcall (tree decl, tree exp)
4243 tree type, decl_or_type;
4246 /* If we are generating position-independent code, we cannot sibcall
4247 optimize any indirect call, or a direct call to a global function,
4248 as the PLT requires %ebx be live. */
4249 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4252 /* If we need to align the outgoing stack, then sibcalling would
4253 unalign the stack, which may break the called function. */
4254 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4259 decl_or_type = decl;
4260 type = TREE_TYPE (decl);
4264 /* We're looking at the CALL_EXPR, we need the type of the function. */
4265 type = CALL_EXPR_FN (exp); /* pointer expression */
4266 type = TREE_TYPE (type); /* pointer type */
4267 type = TREE_TYPE (type); /* function type */
4268 decl_or_type = type;
4271 /* Check that the return value locations are the same. Like
4272 if we are returning floats on the 80387 register stack, we cannot
4273 make a sibcall from a function that doesn't return a float to a
4274 function that does or, conversely, from a function that does return
4275 a float to a function that doesn't; the necessary stack adjustment
4276 would not be executed. This is also the place we notice
4277 differences in the return value ABI. Note that it is ok for one
4278 of the functions to have void return type as long as the return
4279 value of the other is passed in a register. */
4280 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4281 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4283 if (STACK_REG_P (a) || STACK_REG_P (b))
4285 if (!rtx_equal_p (a, b))
4288 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4290 else if (!rtx_equal_p (a, b))
4295 /* The SYSV ABI has more call-clobbered registers;
4296 disallow sibcalls from MS to SYSV. */
4297 if (cfun->machine->call_abi == MS_ABI
4298 && ix86_function_type_abi (type) == SYSV_ABI)
4303 /* If this call is indirect, we'll need to be able to use a
4304 call-clobbered register for the address of the target function.
4305 Make sure that all such registers are not used for passing
4306 parameters. Note that DLLIMPORT functions are indirect. */
4308 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4310 if (ix86_function_regparm (type, NULL) >= 3)
4312 /* ??? Need to count the actual number of registers to be used,
4313 not the possible number of registers. Fix later. */
4319 /* Otherwise okay. That also includes certain types of indirect calls. */
4323 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4324 calling convention attributes;
4325 arguments as in struct attribute_spec.handler. */
4328 ix86_handle_cconv_attribute (tree *node, tree name,
4330 int flags ATTRIBUTE_UNUSED,
4333 if (TREE_CODE (*node) != FUNCTION_TYPE
4334 && TREE_CODE (*node) != METHOD_TYPE
4335 && TREE_CODE (*node) != FIELD_DECL
4336 && TREE_CODE (*node) != TYPE_DECL)
4338 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4340 *no_add_attrs = true;
4344 /* Can combine regparm with all attributes but fastcall. */
4345 if (is_attribute_p ("regparm", name))
4349 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4351 error ("fastcall and regparm attributes are not compatible");
4354 cst = TREE_VALUE (args);
4355 if (TREE_CODE (cst) != INTEGER_CST)
4357 warning (OPT_Wattributes,
4358 "%qE attribute requires an integer constant argument",
4360 *no_add_attrs = true;
4362 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4364 warning (OPT_Wattributes, "argument to %qE attribute larger than %d",
4366 *no_add_attrs = true;
4374 /* Do not warn when emulating the MS ABI. */
4375 if (TREE_CODE (*node) != FUNCTION_TYPE
4376 || ix86_function_type_abi (*node) != MS_ABI)
4377 warning (OPT_Wattributes, "%qE attribute ignored",
4379 *no_add_attrs = true;
4383 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4384 if (is_attribute_p ("fastcall", name))
4386 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4388 error ("fastcall and cdecl attributes are not compatible");
4390 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4392 error ("fastcall and stdcall attributes are not compatible");
4394 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4396 error ("fastcall and regparm attributes are not compatible");
4400 /* Can combine stdcall with fastcall (redundant), regparm and
4402 else if (is_attribute_p ("stdcall", name))
4404 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4406 error ("stdcall and cdecl attributes are not compatible");
4408 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4410 error ("stdcall and fastcall attributes are not compatible");
4414 /* Can combine cdecl with regparm and sseregparm. */
4415 else if (is_attribute_p ("cdecl", name))
4417 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4419 error ("stdcall and cdecl attributes are not compatible");
4421 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4423 error ("fastcall and cdecl attributes are not compatible");
4427 /* Can combine sseregparm with all attributes. */
4432 /* Return 0 if the attributes for two types are incompatible, 1 if they
4433 are compatible, and 2 if they are nearly compatible (which causes a
4434 warning to be generated). */
4437 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4439 /* Check for mismatch of non-default calling convention. */
4440 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4442 if (TREE_CODE (type1) != FUNCTION_TYPE
4443 && TREE_CODE (type1) != METHOD_TYPE)
4446 /* Check for mismatched fastcall/regparm types. */
4447 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4448 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4449 || (ix86_function_regparm (type1, NULL)
4450 != ix86_function_regparm (type2, NULL)))
4453 /* Check for mismatched sseregparm types. */
4454 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4455 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4458 /* Check for mismatched return types (cdecl vs stdcall). */
4459 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4460 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4466 /* Return the regparm value for a function with the indicated TYPE and DECL.
4467 DECL may be NULL when calling function indirectly
4468 or considering a libcall. */
4471 ix86_function_regparm (const_tree type, const_tree decl)
4477 return (ix86_function_type_abi (type) == SYSV_ABI
4478 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4480 regparm = ix86_regparm;
4481 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4484 regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4488 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4491 /* Use register calling convention for local functions when possible. */
4493 && TREE_CODE (decl) == FUNCTION_DECL
4497 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4498 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE (decl));
4501 int local_regparm, globals = 0, regno;
4503 /* Make sure no regparm register is taken by a
4504 fixed register variable. */
4505 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4506 if (fixed_regs[local_regparm])
4509 /* We don't want to use regparm(3) for nested functions as
4510 these use a static chain pointer in the third argument. */
4511 if (local_regparm == 3
4512 && decl_function_context (decl)
4513 && !DECL_NO_STATIC_CHAIN (decl))
4516 /* Each fixed register usage increases register pressure,
4517 so less registers should be used for argument passing.
4518 This functionality can be overriden by an explicit
4520 for (regno = 0; regno <= DI_REG; regno++)
4521 if (fixed_regs[regno])
4525 = globals < local_regparm ? local_regparm - globals : 0;
4527 if (local_regparm > regparm)
4528 regparm = local_regparm;
4535 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4536 DFmode (2) arguments in SSE registers for a function with the
4537 indicated TYPE and DECL. DECL may be NULL when calling function
4538 indirectly or considering a libcall. Otherwise return 0. */
4541 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4543 gcc_assert (!TARGET_64BIT);
4545 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4546 by the sseregparm attribute. */
4547 if (TARGET_SSEREGPARM
4548 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4555 error ("Calling %qD with attribute sseregparm without "
4556 "SSE/SSE2 enabled", decl);
4558 error ("Calling %qT with attribute sseregparm without "
4559 "SSE/SSE2 enabled", type);
4567 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4568 (and DFmode for SSE2) arguments in SSE registers. */
4569 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4571 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4572 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4574 return TARGET_SSE2 ? 2 : 1;
4580 /* Return true if EAX is live at the start of the function. Used by
4581 ix86_expand_prologue to determine if we need special help before
4582 calling allocate_stack_worker. */
4585 ix86_eax_live_at_start_p (void)
4587 /* Cheat. Don't bother working forward from ix86_function_regparm
4588 to the function type to whether an actual argument is located in
4589 eax. Instead just look at cfg info, which is still close enough
4590 to correct at this point. This gives false positives for broken
4591 functions that might use uninitialized data that happens to be
4592 allocated in eax, but who cares? */
4593 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4596 /* Value is the number of bytes of arguments automatically
4597 popped when returning from a subroutine call.
4598 FUNDECL is the declaration node of the function (as a tree),
4599 FUNTYPE is the data type of the function (as a tree),
4600 or for a library call it is an identifier node for the subroutine name.
4601 SIZE is the number of bytes of arguments passed on the stack.
4603 On the 80386, the RTD insn may be used to pop them if the number
4604 of args is fixed, but if the number is variable then the caller
4605 must pop them all. RTD can't be used for library calls now
4606 because the library is compiled with the Unix compiler.
4607 Use of RTD is a selectable option, since it is incompatible with
4608 standard Unix calling sequences. If the option is not selected,
4609 the caller must always pop the args.
4611 The attribute stdcall is equivalent to RTD on a per module basis. */
4614 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4618 /* None of the 64-bit ABIs pop arguments. */
4622 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4624 /* Cdecl functions override -mrtd, and never pop the stack. */
4625 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4627 /* Stdcall and fastcall functions will pop the stack if not
4629 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4630 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4633 if (rtd && ! stdarg_p (funtype))
4637 /* Lose any fake structure return argument if it is passed on the stack. */
4638 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4639 && !KEEP_AGGREGATE_RETURN_POINTER)
4641 int nregs = ix86_function_regparm (funtype, fundecl);
4643 return GET_MODE_SIZE (Pmode);
4649 /* Argument support functions. */
4651 /* Return true when register may be used to pass function parameters. */
4653 ix86_function_arg_regno_p (int regno)
4656 const int *parm_regs;
4661 return (regno < REGPARM_MAX
4662 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4664 return (regno < REGPARM_MAX
4665 || (TARGET_MMX && MMX_REGNO_P (regno)
4666 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4667 || (TARGET_SSE && SSE_REGNO_P (regno)
4668 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4673 if (SSE_REGNO_P (regno) && TARGET_SSE)
4678 if (TARGET_SSE && SSE_REGNO_P (regno)
4679 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4683 /* TODO: The function should depend on current function ABI but
4684 builtins.c would need updating then. Therefore we use the
4687 /* RAX is used as hidden argument to va_arg functions. */
4688 if (ix86_abi == SYSV_ABI && regno == AX_REG)
4691 if (ix86_abi == MS_ABI)
4692 parm_regs = x86_64_ms_abi_int_parameter_registers;
4694 parm_regs = x86_64_int_parameter_registers;
4695 for (i = 0; i < (ix86_abi == MS_ABI
4696 ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX); i++)
4697 if (regno == parm_regs[i])
4702 /* Return if we do not know how to pass TYPE solely in registers. */
4705 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4707 if (must_pass_in_stack_var_size_or_pad (mode, type))
4710 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4711 The layout_type routine is crafty and tries to trick us into passing
4712 currently unsupported vector types on the stack by using TImode. */
4713 return (!TARGET_64BIT && mode == TImode
4714 && type && TREE_CODE (type) != VECTOR_TYPE);
4717 /* It returns the size, in bytes, of the area reserved for arguments passed
4718 in registers for the function represented by fndecl dependent to the used
4721 ix86_reg_parm_stack_space (const_tree fndecl)
4723 enum calling_abi call_abi = SYSV_ABI;
4724 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4725 call_abi = ix86_function_abi (fndecl);
4727 call_abi = ix86_function_type_abi (fndecl);
4728 if (call_abi == MS_ABI)
4733 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4736 ix86_function_type_abi (const_tree fntype)
4738 if (TARGET_64BIT && fntype != NULL)
4740 enum calling_abi abi = ix86_abi;
4741 if (abi == SYSV_ABI)
4743 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
4746 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
4753 static enum calling_abi
4754 ix86_function_abi (const_tree fndecl)
4758 return ix86_function_type_abi (TREE_TYPE (fndecl));
4761 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4764 ix86_cfun_abi (void)
4766 if (! cfun || ! TARGET_64BIT)
4768 return cfun->machine->call_abi;
4772 extern void init_regs (void);
4774 /* Implementation of call abi switching target hook. Specific to FNDECL
4775 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4776 for more details. */
4778 ix86_call_abi_override (const_tree fndecl)
4780 if (fndecl == NULL_TREE)
4781 cfun->machine->call_abi = ix86_abi;
4783 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4786 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4787 re-initialization of init_regs each time we switch function context since
4788 this is needed only during RTL expansion. */
4790 ix86_maybe_switch_abi (void)
4793 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4797 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4798 for a call to a function whose data type is FNTYPE.
4799 For a library call, FNTYPE is 0. */
4802 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4803 tree fntype, /* tree ptr for function decl */
4804 rtx libname, /* SYMBOL_REF of library name or 0 */
4807 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4808 memset (cum, 0, sizeof (*cum));
4811 cum->call_abi = ix86_function_abi (fndecl);
4813 cum->call_abi = ix86_function_type_abi (fntype);
4814 /* Set up the number of registers to use for passing arguments. */
4816 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4817 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
4818 "or subtarget optimization implying it");
4819 cum->nregs = ix86_regparm;
4822 if (cum->call_abi != ix86_abi)
4823 cum->nregs = (ix86_abi != SYSV_ABI
4824 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4828 cum->sse_nregs = SSE_REGPARM_MAX;
4831 if (cum->call_abi != ix86_abi)
4832 cum->sse_nregs = (ix86_abi != SYSV_ABI
4833 ? X86_64_SSE_REGPARM_MAX
4834 : X86_64_MS_SSE_REGPARM_MAX);
4838 cum->mmx_nregs = MMX_REGPARM_MAX;
4839 cum->warn_avx = true;
4840 cum->warn_sse = true;
4841 cum->warn_mmx = true;
4843 /* Because type might mismatch in between caller and callee, we need to
4844 use actual type of function for local calls.
4845 FIXME: cgraph_analyze can be told to actually record if function uses
4846 va_start so for local functions maybe_vaarg can be made aggressive
4848 FIXME: once typesytem is fixed, we won't need this code anymore. */
4850 fntype = TREE_TYPE (fndecl);
4851 cum->maybe_vaarg = (fntype
4852 ? (!prototype_p (fntype) || stdarg_p (fntype))
4857 /* If there are variable arguments, then we won't pass anything
4858 in registers in 32-bit mode. */
4859 if (stdarg_p (fntype))
4870 /* Use ecx and edx registers if function has fastcall attribute,
4871 else look for regparm information. */
4874 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4880 cum->nregs = ix86_function_regparm (fntype, fndecl);
4883 /* Set up the number of SSE registers used for passing SFmode
4884 and DFmode arguments. Warn for mismatching ABI. */
4885 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4889 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4890 But in the case of vector types, it is some vector mode.
4892 When we have only some of our vector isa extensions enabled, then there
4893 are some modes for which vector_mode_supported_p is false. For these
4894 modes, the generic vector support in gcc will choose some non-vector mode
4895 in order to implement the type. By computing the natural mode, we'll
4896 select the proper ABI location for the operand and not depend on whatever
4897 the middle-end decides to do with these vector types.
4899 The midde-end can't deal with the vector types > 16 bytes. In this
4900 case, we return the original mode and warn ABI change if CUM isn't
4903 static enum machine_mode
4904 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4906 enum machine_mode mode = TYPE_MODE (type);
4908 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4910 HOST_WIDE_INT size = int_size_in_bytes (type);
4911 if ((size == 8 || size == 16 || size == 32)
4912 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4913 && TYPE_VECTOR_SUBPARTS (type) > 1)
4915 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4917 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4918 mode = MIN_MODE_VECTOR_FLOAT;
4920 mode = MIN_MODE_VECTOR_INT;
4922 /* Get the mode which has this inner mode and number of units. */
4923 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4924 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4925 && GET_MODE_INNER (mode) == innermode)
4927 if (size == 32 && !TARGET_AVX)
4929 static bool warnedavx;
4936 warning (0, "AVX vector argument without AVX "
4937 "enabled changes the ABI");
4939 return TYPE_MODE (type);
4952 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4953 this may not agree with the mode that the type system has chosen for the
4954 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4955 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4958 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4963 if (orig_mode != BLKmode)
4964 tmp = gen_rtx_REG (orig_mode, regno);
4967 tmp = gen_rtx_REG (mode, regno);
4968 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4969 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4975 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4976 of this code is to classify each 8bytes of incoming argument by the register
4977 class and assign registers accordingly. */
4979 /* Return the union class of CLASS1 and CLASS2.
4980 See the x86-64 PS ABI for details. */
4982 static enum x86_64_reg_class
4983 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4985 /* Rule #1: If both classes are equal, this is the resulting class. */
4986 if (class1 == class2)
4989 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4991 if (class1 == X86_64_NO_CLASS)
4993 if (class2 == X86_64_NO_CLASS)
4996 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4997 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4998 return X86_64_MEMORY_CLASS;
5000 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5001 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
5002 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
5003 return X86_64_INTEGERSI_CLASS;
5004 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
5005 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
5006 return X86_64_INTEGER_CLASS;
5008 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5010 if (class1 == X86_64_X87_CLASS
5011 || class1 == X86_64_X87UP_CLASS
5012 || class1 == X86_64_COMPLEX_X87_CLASS
5013 || class2 == X86_64_X87_CLASS
5014 || class2 == X86_64_X87UP_CLASS
5015 || class2 == X86_64_COMPLEX_X87_CLASS)
5016 return X86_64_MEMORY_CLASS;
5018 /* Rule #6: Otherwise class SSE is used. */
5019 return X86_64_SSE_CLASS;
5022 /* Classify the argument of type TYPE and mode MODE.
5023 CLASSES will be filled by the register class used to pass each word
5024 of the operand. The number of words is returned. In case the parameter
5025 should be passed in memory, 0 is returned. As a special case for zero
5026 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5028 BIT_OFFSET is used internally for handling records and specifies offset
5029 of the offset in bits modulo 256 to avoid overflow cases.
5031 See the x86-64 PS ABI for details.
5035 classify_argument (enum machine_mode mode, const_tree type,
5036 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
5038 HOST_WIDE_INT bytes =
5039 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5040 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5042 /* Variable sized entities are always passed/returned in memory. */
5046 if (mode != VOIDmode
5047 && targetm.calls.must_pass_in_stack (mode, type))
5050 if (type && AGGREGATE_TYPE_P (type))
5054 enum x86_64_reg_class subclasses[MAX_CLASSES];
5056 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5060 for (i = 0; i < words; i++)
5061 classes[i] = X86_64_NO_CLASS;
5063 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5064 signalize memory class, so handle it as special case. */
5067 classes[0] = X86_64_NO_CLASS;
5071 /* Classify each field of record and merge classes. */
5072 switch (TREE_CODE (type))
5075 /* And now merge the fields of structure. */
5076 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5078 if (TREE_CODE (field) == FIELD_DECL)
5082 if (TREE_TYPE (field) == error_mark_node)
5085 /* Bitfields are always classified as integer. Handle them
5086 early, since later code would consider them to be
5087 misaligned integers. */
5088 if (DECL_BIT_FIELD (field))
5090 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5091 i < ((int_bit_position (field) + (bit_offset % 64))
5092 + tree_low_cst (DECL_SIZE (field), 0)
5095 merge_classes (X86_64_INTEGER_CLASS,
5102 type = TREE_TYPE (field);
5104 /* Flexible array member is ignored. */
5105 if (TYPE_MODE (type) == BLKmode
5106 && TREE_CODE (type) == ARRAY_TYPE
5107 && TYPE_SIZE (type) == NULL_TREE
5108 && TYPE_DOMAIN (type) != NULL_TREE
5109 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5114 if (!warned && warn_psabi)
5117 inform (input_location,
5118 "The ABI of passing struct with"
5119 " a flexible array member has"
5120 " changed in GCC 4.4");
5124 num = classify_argument (TYPE_MODE (type), type,
5126 (int_bit_position (field)
5127 + bit_offset) % 256);
5130 pos = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5131 for (i = 0; i < num && (i + pos) < words; i++)
5133 merge_classes (subclasses[i], classes[i + pos]);
5140 /* Arrays are handled as small records. */
5143 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5144 TREE_TYPE (type), subclasses, bit_offset);
5148 /* The partial classes are now full classes. */
5149 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5150 subclasses[0] = X86_64_SSE_CLASS;
5151 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5152 && !((bit_offset % 64) == 0 && bytes == 4))
5153 subclasses[0] = X86_64_INTEGER_CLASS;
5155 for (i = 0; i < words; i++)
5156 classes[i] = subclasses[i % num];
5161 case QUAL_UNION_TYPE:
5162 /* Unions are similar to RECORD_TYPE but offset is always 0.
5164 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5166 if (TREE_CODE (field) == FIELD_DECL)
5170 if (TREE_TYPE (field) == error_mark_node)
5173 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5174 TREE_TYPE (field), subclasses,
5178 for (i = 0; i < num; i++)
5179 classes[i] = merge_classes (subclasses[i], classes[i]);
5190 /* When size > 16 bytes, if the first one isn't
5191 X86_64_SSE_CLASS or any other ones aren't
5192 X86_64_SSEUP_CLASS, everything should be passed in
5194 if (classes[0] != X86_64_SSE_CLASS)
5197 for (i = 1; i < words; i++)
5198 if (classes[i] != X86_64_SSEUP_CLASS)
5202 /* Final merger cleanup. */
5203 for (i = 0; i < words; i++)
5205 /* If one class is MEMORY, everything should be passed in
5207 if (classes[i] == X86_64_MEMORY_CLASS)
5210 /* The X86_64_SSEUP_CLASS should be always preceded by
5211 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5212 if (classes[i] == X86_64_SSEUP_CLASS
5213 && classes[i - 1] != X86_64_SSE_CLASS
5214 && classes[i - 1] != X86_64_SSEUP_CLASS)
5216 /* The first one should never be X86_64_SSEUP_CLASS. */
5217 gcc_assert (i != 0);
5218 classes[i] = X86_64_SSE_CLASS;
5221 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5222 everything should be passed in memory. */
5223 if (classes[i] == X86_64_X87UP_CLASS
5224 && (classes[i - 1] != X86_64_X87_CLASS))
5228 /* The first one should never be X86_64_X87UP_CLASS. */
5229 gcc_assert (i != 0);
5230 if (!warned && warn_psabi)
5233 inform (input_location,
5234 "The ABI of passing union with long double"
5235 " has changed in GCC 4.4");
5243 /* Compute alignment needed. We align all types to natural boundaries with
5244 exception of XFmode that is aligned to 64bits. */
5245 if (mode != VOIDmode && mode != BLKmode)
5247 int mode_alignment = GET_MODE_BITSIZE (mode);
5250 mode_alignment = 128;
5251 else if (mode == XCmode)
5252 mode_alignment = 256;
5253 if (COMPLEX_MODE_P (mode))
5254 mode_alignment /= 2;
5255 /* Misaligned fields are always returned in memory. */
5256 if (bit_offset % mode_alignment)
5260 /* for V1xx modes, just use the base mode */
5261 if (VECTOR_MODE_P (mode) && mode != V1DImode
5262 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5263 mode = GET_MODE_INNER (mode);
5265 /* Classification of atomic types. */
5270 classes[0] = X86_64_SSE_CLASS;
5273 classes[0] = X86_64_SSE_CLASS;
5274 classes[1] = X86_64_SSEUP_CLASS;
5284 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5288 classes[0] = X86_64_INTEGERSI_CLASS;
5291 else if (size <= 64)
5293 classes[0] = X86_64_INTEGER_CLASS;
5296 else if (size <= 64+32)
5298 classes[0] = X86_64_INTEGER_CLASS;
5299 classes[1] = X86_64_INTEGERSI_CLASS;
5302 else if (size <= 64+64)
5304 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5312 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5316 /* OImode shouldn't be used directly. */
5321 if (!(bit_offset % 64))
5322 classes[0] = X86_64_SSESF_CLASS;
5324 classes[0] = X86_64_SSE_CLASS;
5327 classes[0] = X86_64_SSEDF_CLASS;
5330 classes[0] = X86_64_X87_CLASS;
5331 classes[1] = X86_64_X87UP_CLASS;
5334 classes[0] = X86_64_SSE_CLASS;
5335 classes[1] = X86_64_SSEUP_CLASS;
5338 classes[0] = X86_64_SSE_CLASS;
5339 if (!(bit_offset % 64))
5345 if (!warned && warn_psabi)
5348 inform (input_location,
5349 "The ABI of passing structure with complex float"
5350 " member has changed in GCC 4.4");
5352 classes[1] = X86_64_SSESF_CLASS;
5356 classes[0] = X86_64_SSEDF_CLASS;
5357 classes[1] = X86_64_SSEDF_CLASS;
5360 classes[0] = X86_64_COMPLEX_X87_CLASS;
5363 /* This modes is larger than 16 bytes. */
5371 classes[0] = X86_64_SSE_CLASS;
5372 classes[1] = X86_64_SSEUP_CLASS;
5373 classes[2] = X86_64_SSEUP_CLASS;
5374 classes[3] = X86_64_SSEUP_CLASS;
5382 classes[0] = X86_64_SSE_CLASS;
5383 classes[1] = X86_64_SSEUP_CLASS;
5390 classes[0] = X86_64_SSE_CLASS;
5396 gcc_assert (VECTOR_MODE_P (mode));
5401 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5403 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5404 classes[0] = X86_64_INTEGERSI_CLASS;
5406 classes[0] = X86_64_INTEGER_CLASS;
5407 classes[1] = X86_64_INTEGER_CLASS;
5408 return 1 + (bytes > 8);
5412 /* Examine the argument and return set number of register required in each
5413 class. Return 0 iff parameter should be passed in memory. */
5415 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5416 int *int_nregs, int *sse_nregs)
5418 enum x86_64_reg_class regclass[MAX_CLASSES];
5419 int n = classify_argument (mode, type, regclass, 0);
5425 for (n--; n >= 0; n--)
5426 switch (regclass[n])
5428 case X86_64_INTEGER_CLASS:
5429 case X86_64_INTEGERSI_CLASS:
5432 case X86_64_SSE_CLASS:
5433 case X86_64_SSESF_CLASS:
5434 case X86_64_SSEDF_CLASS:
5437 case X86_64_NO_CLASS:
5438 case X86_64_SSEUP_CLASS:
5440 case X86_64_X87_CLASS:
5441 case X86_64_X87UP_CLASS:
5445 case X86_64_COMPLEX_X87_CLASS:
5446 return in_return ? 2 : 0;
5447 case X86_64_MEMORY_CLASS:
5453 /* Construct container for the argument used by GCC interface. See
5454 FUNCTION_ARG for the detailed description. */
5457 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5458 const_tree type, int in_return, int nintregs, int nsseregs,
5459 const int *intreg, int sse_regno)
5461 /* The following variables hold the static issued_error state. */
5462 static bool issued_sse_arg_error;
5463 static bool issued_sse_ret_error;
5464 static bool issued_x87_ret_error;
5466 enum machine_mode tmpmode;
5468 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5469 enum x86_64_reg_class regclass[MAX_CLASSES];
5473 int needed_sseregs, needed_intregs;
5474 rtx exp[MAX_CLASSES];
5477 n = classify_argument (mode, type, regclass, 0);
5480 if (!examine_argument (mode, type, in_return, &needed_intregs,
5483 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5486 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5487 some less clueful developer tries to use floating-point anyway. */
5488 if (needed_sseregs && !TARGET_SSE)
5492 if (!issued_sse_ret_error)
5494 error ("SSE register return with SSE disabled");
5495 issued_sse_ret_error = true;
5498 else if (!issued_sse_arg_error)
5500 error ("SSE register argument with SSE disabled");
5501 issued_sse_arg_error = true;
5506 /* Likewise, error if the ABI requires us to return values in the
5507 x87 registers and the user specified -mno-80387. */
5508 if (!TARGET_80387 && in_return)
5509 for (i = 0; i < n; i++)
5510 if (regclass[i] == X86_64_X87_CLASS
5511 || regclass[i] == X86_64_X87UP_CLASS
5512 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5514 if (!issued_x87_ret_error)
5516 error ("x87 register return with x87 disabled");
5517 issued_x87_ret_error = true;
5522 /* First construct simple cases. Avoid SCmode, since we want to use
5523 single register to pass this type. */
5524 if (n == 1 && mode != SCmode)
5525 switch (regclass[0])
5527 case X86_64_INTEGER_CLASS:
5528 case X86_64_INTEGERSI_CLASS:
5529 return gen_rtx_REG (mode, intreg[0]);
5530 case X86_64_SSE_CLASS:
5531 case X86_64_SSESF_CLASS:
5532 case X86_64_SSEDF_CLASS:
5533 if (mode != BLKmode)
5534 return gen_reg_or_parallel (mode, orig_mode,
5535 SSE_REGNO (sse_regno));
5537 case X86_64_X87_CLASS:
5538 case X86_64_COMPLEX_X87_CLASS:
5539 return gen_rtx_REG (mode, FIRST_STACK_REG);
5540 case X86_64_NO_CLASS:
5541 /* Zero sized array, struct or class. */
5546 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5547 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5548 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5550 && regclass[0] == X86_64_SSE_CLASS
5551 && regclass[1] == X86_64_SSEUP_CLASS
5552 && regclass[2] == X86_64_SSEUP_CLASS
5553 && regclass[3] == X86_64_SSEUP_CLASS
5555 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5558 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5559 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5560 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5561 && regclass[1] == X86_64_INTEGER_CLASS
5562 && (mode == CDImode || mode == TImode || mode == TFmode)
5563 && intreg[0] + 1 == intreg[1])
5564 return gen_rtx_REG (mode, intreg[0]);
5566 /* Otherwise figure out the entries of the PARALLEL. */
5567 for (i = 0; i < n; i++)
5571 switch (regclass[i])
5573 case X86_64_NO_CLASS:
5575 case X86_64_INTEGER_CLASS:
5576 case X86_64_INTEGERSI_CLASS:
5577 /* Merge TImodes on aligned occasions here too. */
5578 if (i * 8 + 8 > bytes)
5579 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5580 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5584 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5585 if (tmpmode == BLKmode)
5587 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5588 gen_rtx_REG (tmpmode, *intreg),
5592 case X86_64_SSESF_CLASS:
5593 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5594 gen_rtx_REG (SFmode,
5595 SSE_REGNO (sse_regno)),
5599 case X86_64_SSEDF_CLASS:
5600 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5601 gen_rtx_REG (DFmode,
5602 SSE_REGNO (sse_regno)),
5606 case X86_64_SSE_CLASS:
5614 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5624 && regclass[1] == X86_64_SSEUP_CLASS
5625 && regclass[2] == X86_64_SSEUP_CLASS
5626 && regclass[3] == X86_64_SSEUP_CLASS);
5633 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5634 gen_rtx_REG (tmpmode,
5635 SSE_REGNO (sse_regno)),
5644 /* Empty aligned struct, union or class. */
5648 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5649 for (i = 0; i < nexps; i++)
5650 XVECEXP (ret, 0, i) = exp [i];
5654 /* Update the data in CUM to advance over an argument of mode MODE
5655 and data type TYPE. (TYPE is null for libcalls where that information
5656 may not be available.) */
5659 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5660 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5676 cum->words += words;
5677 cum->nregs -= words;
5678 cum->regno += words;
5680 if (cum->nregs <= 0)
5688 /* OImode shouldn't be used directly. */
5692 if (cum->float_in_sse < 2)
5695 if (cum->float_in_sse < 1)
5712 if (!type || !AGGREGATE_TYPE_P (type))
5714 cum->sse_words += words;
5715 cum->sse_nregs -= 1;
5716 cum->sse_regno += 1;
5717 if (cum->sse_nregs <= 0)
5730 if (!type || !AGGREGATE_TYPE_P (type))
5732 cum->mmx_words += words;
5733 cum->mmx_nregs -= 1;
5734 cum->mmx_regno += 1;
5735 if (cum->mmx_nregs <= 0)
5746 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5747 tree type, HOST_WIDE_INT words, int named)
5749 int int_nregs, sse_nregs;
5751 /* Unnamed 256bit vector mode parameters are passed on stack. */
5752 if (!named && VALID_AVX256_REG_MODE (mode))
5755 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5756 cum->words += words;
5757 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5759 cum->nregs -= int_nregs;
5760 cum->sse_nregs -= sse_nregs;
5761 cum->regno += int_nregs;
5762 cum->sse_regno += sse_nregs;
5765 cum->words += words;
5769 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5770 HOST_WIDE_INT words)
5772 /* Otherwise, this should be passed indirect. */
5773 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5775 cum->words += words;
5784 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5785 tree type, int named)
5787 HOST_WIDE_INT bytes, words;
5789 if (mode == BLKmode)
5790 bytes = int_size_in_bytes (type);
5792 bytes = GET_MODE_SIZE (mode);
5793 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5796 mode = type_natural_mode (type, NULL);
5798 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5799 function_arg_advance_ms_64 (cum, bytes, words);
5800 else if (TARGET_64BIT)
5801 function_arg_advance_64 (cum, mode, type, words, named);
5803 function_arg_advance_32 (cum, mode, type, bytes, words);
5806 /* Define where to put the arguments to a function.
5807 Value is zero to push the argument on the stack,
5808 or a hard register in which to store the argument.
5810 MODE is the argument's machine mode.
5811 TYPE is the data type of the argument (as a tree).
5812 This is null for libcalls where that information may
5814 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5815 the preceding args and about the function being called.
5816 NAMED is nonzero if this argument is a named parameter
5817 (otherwise it is an extra parameter matching an ellipsis). */
5820 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5821 enum machine_mode orig_mode, tree type,
5822 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5824 static bool warnedsse, warnedmmx;
5826 /* Avoid the AL settings for the Unix64 ABI. */
5827 if (mode == VOIDmode)
5843 if (words <= cum->nregs)
5845 int regno = cum->regno;
5847 /* Fastcall allocates the first two DWORD (SImode) or
5848 smaller arguments to ECX and EDX if it isn't an
5854 || (type && AGGREGATE_TYPE_P (type)))
5857 /* ECX not EAX is the first allocated register. */
5858 if (regno == AX_REG)
5861 return gen_rtx_REG (mode, regno);
5866 if (cum->float_in_sse < 2)
5869 if (cum->float_in_sse < 1)
5873 /* In 32bit, we pass TImode in xmm registers. */
5880 if (!type || !AGGREGATE_TYPE_P (type))
5882 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5885 warning (0, "SSE vector argument without SSE enabled "
5889 return gen_reg_or_parallel (mode, orig_mode,
5890 cum->sse_regno + FIRST_SSE_REG);
5895 /* OImode shouldn't be used directly. */
5904 if (!type || !AGGREGATE_TYPE_P (type))
5907 return gen_reg_or_parallel (mode, orig_mode,
5908 cum->sse_regno + FIRST_SSE_REG);
5917 if (!type || !AGGREGATE_TYPE_P (type))
5919 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5922 warning (0, "MMX vector argument without MMX enabled "
5926 return gen_reg_or_parallel (mode, orig_mode,
5927 cum->mmx_regno + FIRST_MMX_REG);
5936 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5937 enum machine_mode orig_mode, tree type, int named)
5939 /* Handle a hidden AL argument containing number of registers
5940 for varargs x86-64 functions. */
5941 if (mode == VOIDmode)
5942 return GEN_INT (cum->maybe_vaarg
5943 ? (cum->sse_nregs < 0
5944 ? (cum->call_abi == ix86_abi
5946 : (ix86_abi != SYSV_ABI
5947 ? X86_64_SSE_REGPARM_MAX
5948 : X86_64_MS_SSE_REGPARM_MAX))
5963 /* Unnamed 256bit vector mode parameters are passed on stack. */
5969 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5971 &x86_64_int_parameter_registers [cum->regno],
5976 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5977 enum machine_mode orig_mode, int named,
5978 HOST_WIDE_INT bytes)
5982 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5983 We use value of -2 to specify that current function call is MSABI. */
5984 if (mode == VOIDmode)
5985 return GEN_INT (-2);
5987 /* If we've run out of registers, it goes on the stack. */
5988 if (cum->nregs == 0)
5991 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5993 /* Only floating point modes are passed in anything but integer regs. */
5994 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5997 regno = cum->regno + FIRST_SSE_REG;
6002 /* Unnamed floating parameters are passed in both the
6003 SSE and integer registers. */
6004 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
6005 t2 = gen_rtx_REG (mode, regno);
6006 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
6007 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
6008 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
6011 /* Handle aggregated types passed in register. */
6012 if (orig_mode == BLKmode)
6014 if (bytes > 0 && bytes <= 8)
6015 mode = (bytes > 4 ? DImode : SImode);
6016 if (mode == BLKmode)
6020 return gen_reg_or_parallel (mode, orig_mode, regno);
6024 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
6025 tree type, int named)
6027 enum machine_mode mode = omode;
6028 HOST_WIDE_INT bytes, words;
6030 if (mode == BLKmode)
6031 bytes = int_size_in_bytes (type);
6033 bytes = GET_MODE_SIZE (mode);
6034 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6036 /* To simplify the code below, represent vector types with a vector mode
6037 even if MMX/SSE are not active. */
6038 if (type && TREE_CODE (type) == VECTOR_TYPE)
6039 mode = type_natural_mode (type, cum);
6041 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6042 return function_arg_ms_64 (cum, mode, omode, named, bytes);
6043 else if (TARGET_64BIT)
6044 return function_arg_64 (cum, mode, omode, type, named);
6046 return function_arg_32 (cum, mode, omode, type, bytes, words);
6049 /* A C expression that indicates when an argument must be passed by
6050 reference. If nonzero for an argument, a copy of that argument is
6051 made in memory and a pointer to the argument is passed instead of
6052 the argument itself. The pointer is passed in whatever way is
6053 appropriate for passing a pointer to that type. */
6056 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6057 enum machine_mode mode ATTRIBUTE_UNUSED,
6058 const_tree type, bool named ATTRIBUTE_UNUSED)
6060 /* See Windows x64 Software Convention. */
6061 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6063 int msize = (int) GET_MODE_SIZE (mode);
6066 /* Arrays are passed by reference. */
6067 if (TREE_CODE (type) == ARRAY_TYPE)
6070 if (AGGREGATE_TYPE_P (type))
6072 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6073 are passed by reference. */
6074 msize = int_size_in_bytes (type);
6078 /* __m128 is passed by reference. */
6080 case 1: case 2: case 4: case 8:
6086 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
6092 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6095 contains_aligned_value_p (tree type)
6097 enum machine_mode mode = TYPE_MODE (type);
6098 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6102 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6104 if (TYPE_ALIGN (type) < 128)
6107 if (AGGREGATE_TYPE_P (type))
6109 /* Walk the aggregates recursively. */
6110 switch (TREE_CODE (type))
6114 case QUAL_UNION_TYPE:
6118 /* Walk all the structure fields. */
6119 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6121 if (TREE_CODE (field) == FIELD_DECL
6122 && contains_aligned_value_p (TREE_TYPE (field)))
6129 /* Just for use if some languages passes arrays by value. */
6130 if (contains_aligned_value_p (TREE_TYPE (type)))
6141 /* Gives the alignment boundary, in bits, of an argument with the
6142 specified mode and type. */
6145 ix86_function_arg_boundary (enum machine_mode mode, tree type)
6150 /* Since canonical type is used for call, we convert it to
6151 canonical type if needed. */
6152 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6153 type = TYPE_CANONICAL (type);
6154 align = TYPE_ALIGN (type);
6157 align = GET_MODE_ALIGNMENT (mode);
6158 if (align < PARM_BOUNDARY)
6159 align = PARM_BOUNDARY;
6160 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6161 natural boundaries. */
6162 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6164 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6165 make an exception for SSE modes since these require 128bit
6168 The handling here differs from field_alignment. ICC aligns MMX
6169 arguments to 4 byte boundaries, while structure fields are aligned
6170 to 8 byte boundaries. */
6173 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6174 align = PARM_BOUNDARY;
6178 if (!contains_aligned_value_p (type))
6179 align = PARM_BOUNDARY;
6182 if (align > BIGGEST_ALIGNMENT)
6183 align = BIGGEST_ALIGNMENT;
6187 /* Return true if N is a possible register number of function value. */
6190 ix86_function_value_regno_p (int regno)
6197 case FIRST_FLOAT_REG:
6198 /* TODO: The function should depend on current function ABI but
6199 builtins.c would need updating then. Therefore we use the
6201 if (TARGET_64BIT && ix86_abi == MS_ABI)
6203 return TARGET_FLOAT_RETURNS_IN_80387;
6209 if (TARGET_MACHO || TARGET_64BIT)
6217 /* Define how to find the value returned by a function.
6218 VALTYPE is the data type of the value (as a tree).
6219 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6220 otherwise, FUNC is 0. */
6223 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6224 const_tree fntype, const_tree fn)
6228 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6229 we normally prevent this case when mmx is not available. However
6230 some ABIs may require the result to be returned like DImode. */
6231 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6232 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6234 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6235 we prevent this case when sse is not available. However some ABIs
6236 may require the result to be returned like integer TImode. */
6237 else if (mode == TImode
6238 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6239 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6241 /* 32-byte vector modes in %ymm0. */
6242 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6243 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6245 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6246 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6247 regno = FIRST_FLOAT_REG;
6249 /* Most things go in %eax. */
6252 /* Override FP return register with %xmm0 for local functions when
6253 SSE math is enabled or for functions with sseregparm attribute. */
6254 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6256 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6257 if ((sse_level >= 1 && mode == SFmode)
6258 || (sse_level == 2 && mode == DFmode))
6259 regno = FIRST_SSE_REG;
6262 /* OImode shouldn't be used directly. */
6263 gcc_assert (mode != OImode);
6265 return gen_rtx_REG (orig_mode, regno);
6269 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6274 /* Handle libcalls, which don't provide a type node. */
6275 if (valtype == NULL)
6287 return gen_rtx_REG (mode, FIRST_SSE_REG);
6290 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6294 return gen_rtx_REG (mode, AX_REG);
6298 ret = construct_container (mode, orig_mode, valtype, 1,
6299 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6300 x86_64_int_return_registers, 0);
6302 /* For zero sized structures, construct_container returns NULL, but we
6303 need to keep rest of compiler happy by returning meaningful value. */
6305 ret = gen_rtx_REG (orig_mode, AX_REG);
6311 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6313 unsigned int regno = AX_REG;
6317 switch (GET_MODE_SIZE (mode))
6320 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6321 && !COMPLEX_MODE_P (mode))
6322 regno = FIRST_SSE_REG;
6326 if (mode == SFmode || mode == DFmode)
6327 regno = FIRST_SSE_REG;
6333 return gen_rtx_REG (orig_mode, regno);
6337 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6338 enum machine_mode orig_mode, enum machine_mode mode)
6340 const_tree fn, fntype;
6343 if (fntype_or_decl && DECL_P (fntype_or_decl))
6344 fn = fntype_or_decl;
6345 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6347 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6348 return function_value_ms_64 (orig_mode, mode);
6349 else if (TARGET_64BIT)
6350 return function_value_64 (orig_mode, mode, valtype);
6352 return function_value_32 (orig_mode, mode, fntype, fn);
6356 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6357 bool outgoing ATTRIBUTE_UNUSED)
6359 enum machine_mode mode, orig_mode;
6361 orig_mode = TYPE_MODE (valtype);
6362 mode = type_natural_mode (valtype, NULL);
6363 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6367 ix86_libcall_value (enum machine_mode mode)
6369 return ix86_function_value_1 (NULL, NULL, mode, mode);
6372 /* Return true iff type is returned in memory. */
6374 static int ATTRIBUTE_UNUSED
6375 return_in_memory_32 (const_tree type, enum machine_mode mode)
6379 if (mode == BLKmode)
6382 size = int_size_in_bytes (type);
6384 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6387 if (VECTOR_MODE_P (mode) || mode == TImode)
6389 /* User-created vectors small enough to fit in EAX. */
6393 /* MMX/3dNow values are returned in MM0,
6394 except when it doesn't exits. */
6396 return (TARGET_MMX ? 0 : 1);
6398 /* SSE values are returned in XMM0, except when it doesn't exist. */
6400 return (TARGET_SSE ? 0 : 1);
6402 /* AVX values are returned in YMM0, except when it doesn't exist. */
6404 return TARGET_AVX ? 0 : 1;
6413 /* OImode shouldn't be used directly. */
6414 gcc_assert (mode != OImode);
6419 static int ATTRIBUTE_UNUSED
6420 return_in_memory_64 (const_tree type, enum machine_mode mode)
6422 int needed_intregs, needed_sseregs;
6423 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6426 static int ATTRIBUTE_UNUSED
6427 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6429 HOST_WIDE_INT size = int_size_in_bytes (type);
6431 /* __m128 is returned in xmm0. */
6432 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6433 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6436 /* Otherwise, the size must be exactly in [1248]. */
6437 return (size != 1 && size != 2 && size != 4 && size != 8);
6441 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6443 #ifdef SUBTARGET_RETURN_IN_MEMORY
6444 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6446 const enum machine_mode mode = type_natural_mode (type, NULL);
6450 if (ix86_function_type_abi (fntype) == MS_ABI)
6451 return return_in_memory_ms_64 (type, mode);
6453 return return_in_memory_64 (type, mode);
6456 return return_in_memory_32 (type, mode);
6460 /* Return false iff TYPE is returned in memory. This version is used
6461 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6462 but differs notably in that when MMX is available, 8-byte vectors
6463 are returned in memory, rather than in MMX registers. */
6466 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6469 enum machine_mode mode = type_natural_mode (type, NULL);
6472 return return_in_memory_64 (type, mode);
6474 if (mode == BLKmode)
6477 size = int_size_in_bytes (type);
6479 if (VECTOR_MODE_P (mode))
6481 /* Return in memory only if MMX registers *are* available. This
6482 seems backwards, but it is consistent with the existing
6489 else if (mode == TImode)
6491 else if (mode == XFmode)
6497 /* When returning SSE vector types, we have a choice of either
6498 (1) being abi incompatible with a -march switch, or
6499 (2) generating an error.
6500 Given no good solution, I think the safest thing is one warning.
6501 The user won't be able to use -Werror, but....
6503 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6504 called in response to actually generating a caller or callee that
6505 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6506 via aggregate_value_p for general type probing from tree-ssa. */
6509 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6511 static bool warnedsse, warnedmmx;
6513 if (!TARGET_64BIT && type)
6515 /* Look at the return type of the function, not the function type. */
6516 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6518 if (!TARGET_SSE && !warnedsse)
6521 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6524 warning (0, "SSE vector return without SSE enabled "
6529 if (!TARGET_MMX && !warnedmmx)
6531 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6534 warning (0, "MMX vector return without MMX enabled "
6544 /* Create the va_list data type. */
6546 /* Returns the calling convention specific va_list date type.
6547 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6550 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6552 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6554 /* For i386 we use plain pointer to argument area. */
6555 if (!TARGET_64BIT || abi == MS_ABI)
6556 return build_pointer_type (char_type_node);
6558 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6559 type_decl = build_decl (BUILTINS_LOCATION,
6560 TYPE_DECL, get_identifier ("__va_list_tag"), record);
6562 f_gpr = build_decl (BUILTINS_LOCATION,
6563 FIELD_DECL, get_identifier ("gp_offset"),
6564 unsigned_type_node);
6565 f_fpr = build_decl (BUILTINS_LOCATION,
6566 FIELD_DECL, get_identifier ("fp_offset"),
6567 unsigned_type_node);
6568 f_ovf = build_decl (BUILTINS_LOCATION,
6569 FIELD_DECL, get_identifier ("overflow_arg_area"),
6571 f_sav = build_decl (BUILTINS_LOCATION,
6572 FIELD_DECL, get_identifier ("reg_save_area"),
6575 va_list_gpr_counter_field = f_gpr;
6576 va_list_fpr_counter_field = f_fpr;
6578 DECL_FIELD_CONTEXT (f_gpr) = record;
6579 DECL_FIELD_CONTEXT (f_fpr) = record;
6580 DECL_FIELD_CONTEXT (f_ovf) = record;
6581 DECL_FIELD_CONTEXT (f_sav) = record;
6583 TREE_CHAIN (record) = type_decl;
6584 TYPE_NAME (record) = type_decl;
6585 TYPE_FIELDS (record) = f_gpr;
6586 TREE_CHAIN (f_gpr) = f_fpr;
6587 TREE_CHAIN (f_fpr) = f_ovf;
6588 TREE_CHAIN (f_ovf) = f_sav;
6590 layout_type (record);
6592 /* The correct type is an array type of one element. */
6593 return build_array_type (record, build_index_type (size_zero_node));
6596 /* Setup the builtin va_list data type and for 64-bit the additional
6597 calling convention specific va_list data types. */
6600 ix86_build_builtin_va_list (void)
6602 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
6604 /* Initialize abi specific va_list builtin types. */
6608 if (ix86_abi == MS_ABI)
6610 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6611 if (TREE_CODE (t) != RECORD_TYPE)
6612 t = build_variant_type_copy (t);
6613 sysv_va_list_type_node = t;
6618 if (TREE_CODE (t) != RECORD_TYPE)
6619 t = build_variant_type_copy (t);
6620 sysv_va_list_type_node = t;
6622 if (ix86_abi != MS_ABI)
6624 t = ix86_build_builtin_va_list_abi (MS_ABI);
6625 if (TREE_CODE (t) != RECORD_TYPE)
6626 t = build_variant_type_copy (t);
6627 ms_va_list_type_node = t;
6632 if (TREE_CODE (t) != RECORD_TYPE)
6633 t = build_variant_type_copy (t);
6634 ms_va_list_type_node = t;
6641 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6644 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6653 int regparm = ix86_regparm;
6655 if (cum->call_abi != ix86_abi)
6656 regparm = (ix86_abi != SYSV_ABI
6657 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
6659 /* GPR size of varargs save area. */
6660 if (cfun->va_list_gpr_size)
6661 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6663 ix86_varargs_gpr_size = 0;
6665 /* FPR size of varargs save area. We don't need it if we don't pass
6666 anything in SSE registers. */
6667 if (cum->sse_nregs && cfun->va_list_fpr_size)
6668 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6670 ix86_varargs_fpr_size = 0;
6672 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6675 save_area = frame_pointer_rtx;
6676 set = get_varargs_alias_set ();
6678 for (i = cum->regno;
6680 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6683 mem = gen_rtx_MEM (Pmode,
6684 plus_constant (save_area, i * UNITS_PER_WORD));
6685 MEM_NOTRAP_P (mem) = 1;
6686 set_mem_alias_set (mem, set);
6687 emit_move_insn (mem, gen_rtx_REG (Pmode,
6688 x86_64_int_parameter_registers[i]));
6691 if (ix86_varargs_fpr_size)
6693 /* Now emit code to save SSE registers. The AX parameter contains number
6694 of SSE parameter registers used to call this function. We use
6695 sse_prologue_save insn template that produces computed jump across
6696 SSE saves. We need some preparation work to get this working. */
6698 label = gen_label_rtx ();
6699 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6701 /* Compute address to jump to :
6702 label - eax*4 + nnamed_sse_arguments*4 Or
6703 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6704 tmp_reg = gen_reg_rtx (Pmode);
6705 nsse_reg = gen_reg_rtx (Pmode);
6706 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6707 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6708 gen_rtx_MULT (Pmode, nsse_reg,
6711 /* vmovaps is one byte longer than movaps. */
6713 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6714 gen_rtx_PLUS (Pmode, tmp_reg,
6720 gen_rtx_CONST (DImode,
6721 gen_rtx_PLUS (DImode,
6723 GEN_INT (cum->sse_regno
6724 * (TARGET_AVX ? 5 : 4)))));
6726 emit_move_insn (nsse_reg, label_ref);
6727 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6729 /* Compute address of memory block we save into. We always use pointer
6730 pointing 127 bytes after first byte to store - this is needed to keep
6731 instruction size limited by 4 bytes (5 bytes for AVX) with one
6732 byte displacement. */
6733 tmp_reg = gen_reg_rtx (Pmode);
6734 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6735 plus_constant (save_area,
6736 ix86_varargs_gpr_size + 127)));
6737 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6738 MEM_NOTRAP_P (mem) = 1;
6739 set_mem_alias_set (mem, set);
6740 set_mem_align (mem, BITS_PER_WORD);
6742 /* And finally do the dirty job! */
6743 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6744 GEN_INT (cum->sse_regno), label));
6749 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6751 alias_set_type set = get_varargs_alias_set ();
6754 for (i = cum->regno; i < X86_64_MS_REGPARM_MAX; i++)
6758 mem = gen_rtx_MEM (Pmode,
6759 plus_constant (virtual_incoming_args_rtx,
6760 i * UNITS_PER_WORD));
6761 MEM_NOTRAP_P (mem) = 1;
6762 set_mem_alias_set (mem, set);
6764 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6765 emit_move_insn (mem, reg);
6770 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6771 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6774 CUMULATIVE_ARGS next_cum;
6777 /* This argument doesn't appear to be used anymore. Which is good,
6778 because the old code here didn't suppress rtl generation. */
6779 gcc_assert (!no_rtl);
6784 fntype = TREE_TYPE (current_function_decl);
6786 /* For varargs, we do not want to skip the dummy va_dcl argument.
6787 For stdargs, we do want to skip the last named argument. */
6789 if (stdarg_p (fntype))
6790 function_arg_advance (&next_cum, mode, type, 1);
6792 if (cum->call_abi == MS_ABI)
6793 setup_incoming_varargs_ms_64 (&next_cum);
6795 setup_incoming_varargs_64 (&next_cum);
6798 /* Checks if TYPE is of kind va_list char *. */
6801 is_va_list_char_pointer (tree type)
6805 /* For 32-bit it is always true. */
6808 canonic = ix86_canonical_va_list_type (type);
6809 return (canonic == ms_va_list_type_node
6810 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
6813 /* Implement va_start. */
6816 ix86_va_start (tree valist, rtx nextarg)
6818 HOST_WIDE_INT words, n_gpr, n_fpr;
6819 tree f_gpr, f_fpr, f_ovf, f_sav;
6820 tree gpr, fpr, ovf, sav, t;
6823 /* Only 64bit target needs something special. */
6824 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6826 std_expand_builtin_va_start (valist, nextarg);
6830 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6831 f_fpr = TREE_CHAIN (f_gpr);
6832 f_ovf = TREE_CHAIN (f_fpr);
6833 f_sav = TREE_CHAIN (f_ovf);
6835 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6836 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6837 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6838 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6839 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6841 /* Count number of gp and fp argument registers used. */
6842 words = crtl->args.info.words;
6843 n_gpr = crtl->args.info.regno;
6844 n_fpr = crtl->args.info.sse_regno;
6846 if (cfun->va_list_gpr_size)
6848 type = TREE_TYPE (gpr);
6849 t = build2 (MODIFY_EXPR, type,
6850 gpr, build_int_cst (type, n_gpr * 8));
6851 TREE_SIDE_EFFECTS (t) = 1;
6852 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6855 if (TARGET_SSE && cfun->va_list_fpr_size)
6857 type = TREE_TYPE (fpr);
6858 t = build2 (MODIFY_EXPR, type, fpr,
6859 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6860 TREE_SIDE_EFFECTS (t) = 1;
6861 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6864 /* Find the overflow area. */
6865 type = TREE_TYPE (ovf);
6866 t = make_tree (type, crtl->args.internal_arg_pointer);
6868 t = build2 (POINTER_PLUS_EXPR, type, t,
6869 size_int (words * UNITS_PER_WORD));
6870 t = build2 (MODIFY_EXPR, type, ovf, t);
6871 TREE_SIDE_EFFECTS (t) = 1;
6872 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6874 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6876 /* Find the register save area.
6877 Prologue of the function save it right above stack frame. */
6878 type = TREE_TYPE (sav);
6879 t = make_tree (type, frame_pointer_rtx);
6880 if (!ix86_varargs_gpr_size)
6881 t = build2 (POINTER_PLUS_EXPR, type, t,
6882 size_int (-8 * X86_64_REGPARM_MAX));
6883 t = build2 (MODIFY_EXPR, type, sav, t);
6884 TREE_SIDE_EFFECTS (t) = 1;
6885 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6889 /* Implement va_arg. */
6892 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6895 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6896 tree f_gpr, f_fpr, f_ovf, f_sav;
6897 tree gpr, fpr, ovf, sav, t;
6899 tree lab_false, lab_over = NULL_TREE;
6904 enum machine_mode nat_mode;
6907 /* Only 64bit target needs something special. */
6908 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6909 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6911 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6912 f_fpr = TREE_CHAIN (f_gpr);
6913 f_ovf = TREE_CHAIN (f_fpr);
6914 f_sav = TREE_CHAIN (f_ovf);
6916 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6917 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6918 valist = build_va_arg_indirect_ref (valist);
6919 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6920 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6921 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6923 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6925 type = build_pointer_type (type);
6926 size = int_size_in_bytes (type);
6927 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6929 nat_mode = type_natural_mode (type, NULL);
6938 /* Unnamed 256bit vector mode parameters are passed on stack. */
6939 if (ix86_cfun_abi () == SYSV_ABI)
6946 container = construct_container (nat_mode, TYPE_MODE (type),
6947 type, 0, X86_64_REGPARM_MAX,
6948 X86_64_SSE_REGPARM_MAX, intreg,
6953 /* Pull the value out of the saved registers. */
6955 addr = create_tmp_var (ptr_type_node, "addr");
6959 int needed_intregs, needed_sseregs;
6961 tree int_addr, sse_addr;
6963 lab_false = create_artificial_label (UNKNOWN_LOCATION);
6964 lab_over = create_artificial_label (UNKNOWN_LOCATION);
6966 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6968 need_temp = (!REG_P (container)
6969 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6970 || TYPE_ALIGN (type) > 128));
6972 /* In case we are passing structure, verify that it is consecutive block
6973 on the register save area. If not we need to do moves. */
6974 if (!need_temp && !REG_P (container))
6976 /* Verify that all registers are strictly consecutive */
6977 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6981 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6983 rtx slot = XVECEXP (container, 0, i);
6984 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6985 || INTVAL (XEXP (slot, 1)) != i * 16)
6993 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6995 rtx slot = XVECEXP (container, 0, i);
6996 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6997 || INTVAL (XEXP (slot, 1)) != i * 8)
7009 int_addr = create_tmp_var (ptr_type_node, "int_addr");
7010 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
7013 /* First ensure that we fit completely in registers. */
7016 t = build_int_cst (TREE_TYPE (gpr),
7017 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
7018 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
7019 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7020 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7021 gimplify_and_add (t, pre_p);
7025 t = build_int_cst (TREE_TYPE (fpr),
7026 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
7027 + X86_64_REGPARM_MAX * 8);
7028 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
7029 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7030 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7031 gimplify_and_add (t, pre_p);
7034 /* Compute index to start of area used for integer regs. */
7037 /* int_addr = gpr + sav; */
7038 t = fold_convert (sizetype, gpr);
7039 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7040 gimplify_assign (int_addr, t, pre_p);
7044 /* sse_addr = fpr + sav; */
7045 t = fold_convert (sizetype, fpr);
7046 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7047 gimplify_assign (sse_addr, t, pre_p);
7052 tree temp = create_tmp_var (type, "va_arg_tmp");
7055 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
7056 gimplify_assign (addr, t, pre_p);
7058 for (i = 0; i < XVECLEN (container, 0); i++)
7060 rtx slot = XVECEXP (container, 0, i);
7061 rtx reg = XEXP (slot, 0);
7062 enum machine_mode mode = GET_MODE (reg);
7063 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
7064 tree addr_type = build_pointer_type (piece_type);
7065 tree daddr_type = build_pointer_type_for_mode (piece_type,
7069 tree dest_addr, dest;
7071 if (SSE_REGNO_P (REGNO (reg)))
7073 src_addr = sse_addr;
7074 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
7078 src_addr = int_addr;
7079 src_offset = REGNO (reg) * 8;
7081 src_addr = fold_convert (addr_type, src_addr);
7082 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
7083 size_int (src_offset));
7084 src = build_va_arg_indirect_ref (src_addr);
7086 dest_addr = fold_convert (daddr_type, addr);
7087 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
7088 size_int (INTVAL (XEXP (slot, 1))));
7089 dest = build_va_arg_indirect_ref (dest_addr);
7091 gimplify_assign (dest, src, pre_p);
7097 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7098 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7099 gimplify_assign (gpr, t, pre_p);
7104 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7105 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7106 gimplify_assign (fpr, t, pre_p);
7109 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7111 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7114 /* ... otherwise out of the overflow area. */
7116 /* When we align parameter on stack for caller, if the parameter
7117 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7118 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7119 here with caller. */
7120 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7121 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7122 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7124 /* Care for on-stack alignment if needed. */
7125 if (arg_boundary <= 64
7126 || integer_zerop (TYPE_SIZE (type)))
7130 HOST_WIDE_INT align = arg_boundary / 8;
7131 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7132 size_int (align - 1));
7133 t = fold_convert (sizetype, t);
7134 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7136 t = fold_convert (TREE_TYPE (ovf), t);
7138 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7139 gimplify_assign (addr, t, pre_p);
7141 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7142 size_int (rsize * UNITS_PER_WORD));
7143 gimplify_assign (unshare_expr (ovf), t, pre_p);
7146 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7148 ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
7149 addr = fold_convert (ptrtype, addr);
7152 addr = build_va_arg_indirect_ref (addr);
7153 return build_va_arg_indirect_ref (addr);
7156 /* Return nonzero if OPNUM's MEM should be matched
7157 in movabs* patterns. */
7160 ix86_check_movabs (rtx insn, int opnum)
7164 set = PATTERN (insn);
7165 if (GET_CODE (set) == PARALLEL)
7166 set = XVECEXP (set, 0, 0);
7167 gcc_assert (GET_CODE (set) == SET);
7168 mem = XEXP (set, opnum);
7169 while (GET_CODE (mem) == SUBREG)
7170 mem = SUBREG_REG (mem);
7171 gcc_assert (MEM_P (mem));
7172 return (volatile_ok || !MEM_VOLATILE_P (mem));
7175 /* Initialize the table of extra 80387 mathematical constants. */
7178 init_ext_80387_constants (void)
7180 static const char * cst[5] =
7182 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7183 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7184 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7185 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7186 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7190 for (i = 0; i < 5; i++)
7192 real_from_string (&ext_80387_constants_table[i], cst[i]);
7193 /* Ensure each constant is rounded to XFmode precision. */
7194 real_convert (&ext_80387_constants_table[i],
7195 XFmode, &ext_80387_constants_table[i]);
7198 ext_80387_constants_init = 1;
7201 /* Return true if the constant is something that can be loaded with
7202 a special instruction. */
7205 standard_80387_constant_p (rtx x)
7207 enum machine_mode mode = GET_MODE (x);
7211 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7214 if (x == CONST0_RTX (mode))
7216 if (x == CONST1_RTX (mode))
7219 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7221 /* For XFmode constants, try to find a special 80387 instruction when
7222 optimizing for size or on those CPUs that benefit from them. */
7224 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7228 if (! ext_80387_constants_init)
7229 init_ext_80387_constants ();
7231 for (i = 0; i < 5; i++)
7232 if (real_identical (&r, &ext_80387_constants_table[i]))
7236 /* Load of the constant -0.0 or -1.0 will be split as
7237 fldz;fchs or fld1;fchs sequence. */
7238 if (real_isnegzero (&r))
7240 if (real_identical (&r, &dconstm1))
7246 /* Return the opcode of the special instruction to be used to load
7250 standard_80387_constant_opcode (rtx x)
7252 switch (standard_80387_constant_p (x))
7276 /* Return the CONST_DOUBLE representing the 80387 constant that is
7277 loaded by the specified special instruction. The argument IDX
7278 matches the return value from standard_80387_constant_p. */
7281 standard_80387_constant_rtx (int idx)
7285 if (! ext_80387_constants_init)
7286 init_ext_80387_constants ();
7302 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7306 /* Return 1 if X is all 0s and 2 if x is all 1s
7307 in supported SSE vector mode. */
7310 standard_sse_constant_p (rtx x)
7312 enum machine_mode mode = GET_MODE (x);
7314 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7316 if (vector_all_ones_operand (x, mode))
7332 /* Return the opcode of the special instruction to be used to load
7336 standard_sse_constant_opcode (rtx insn, rtx x)
7338 switch (standard_sse_constant_p (x))
7341 switch (get_attr_mode (insn))
7344 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7346 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7348 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7350 return "vxorps\t%x0, %x0, %x0";
7352 return "vxorpd\t%x0, %x0, %x0";
7354 return "vpxor\t%x0, %x0, %x0";
7359 return TARGET_AVX ? "vpcmpeqd\t%0, %0, %0" : "pcmpeqd\t%0, %0";
7366 /* Returns 1 if OP contains a symbol reference */
7369 symbolic_reference_mentioned_p (rtx op)
7374 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7377 fmt = GET_RTX_FORMAT (GET_CODE (op));
7378 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7384 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7385 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7389 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7396 /* Return 1 if it is appropriate to emit `ret' instructions in the
7397 body of a function. Do this only if the epilogue is simple, needing a
7398 couple of insns. Prior to reloading, we can't tell how many registers
7399 must be saved, so return 0 then. Return 0 if there is no frame
7400 marker to de-allocate. */
7403 ix86_can_use_return_insn_p (void)
7405 struct ix86_frame frame;
7407 if (! reload_completed || frame_pointer_needed)
7410 /* Don't allow more than 32 pop, since that's all we can do
7411 with one instruction. */
7412 if (crtl->args.pops_args
7413 && crtl->args.size >= 32768)
7416 ix86_compute_frame_layout (&frame);
7417 return frame.to_allocate == 0 && frame.padding0 == 0
7418 && (frame.nregs + frame.nsseregs) == 0;
7421 /* Value should be nonzero if functions must have frame pointers.
7422 Zero means the frame pointer need not be set up (and parms may
7423 be accessed via the stack pointer) in functions that seem suitable. */
7426 ix86_frame_pointer_required (void)
7428 /* If we accessed previous frames, then the generated code expects
7429 to be able to access the saved ebp value in our frame. */
7430 if (cfun->machine->accesses_prev_frame)
7433 /* Several x86 os'es need a frame pointer for other reasons,
7434 usually pertaining to setjmp. */
7435 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7438 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7439 the frame pointer by default. Turn it back on now if we've not
7440 got a leaf function. */
7441 if (TARGET_OMIT_LEAF_FRAME_POINTER
7442 && (!current_function_is_leaf
7443 || ix86_current_function_calls_tls_descriptor))
7452 /* Record that the current function accesses previous call frames. */
7455 ix86_setup_frame_addresses (void)
7457 cfun->machine->accesses_prev_frame = 1;
7460 #ifndef USE_HIDDEN_LINKONCE
7461 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7462 # define USE_HIDDEN_LINKONCE 1
7464 # define USE_HIDDEN_LINKONCE 0
7468 static int pic_labels_used;
7470 /* Fills in the label name that should be used for a pc thunk for
7471 the given register. */
7474 get_pc_thunk_name (char name[32], unsigned int regno)
7476 gcc_assert (!TARGET_64BIT);
7478 if (USE_HIDDEN_LINKONCE)
7479 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7481 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7485 /* This function generates code for -fpic that loads %ebx with
7486 the return address of the caller and then returns. */
7489 ix86_file_end (void)
7494 for (regno = 0; regno < 8; ++regno)
7498 if (! ((pic_labels_used >> regno) & 1))
7501 get_pc_thunk_name (name, regno);
7506 switch_to_section (darwin_sections[text_coal_section]);
7507 fputs ("\t.weak_definition\t", asm_out_file);
7508 assemble_name (asm_out_file, name);
7509 fputs ("\n\t.private_extern\t", asm_out_file);
7510 assemble_name (asm_out_file, name);
7511 fputs ("\n", asm_out_file);
7512 ASM_OUTPUT_LABEL (asm_out_file, name);
7516 if (USE_HIDDEN_LINKONCE)
7520 decl = build_decl (BUILTINS_LOCATION,
7521 FUNCTION_DECL, get_identifier (name),
7523 TREE_PUBLIC (decl) = 1;
7524 TREE_STATIC (decl) = 1;
7525 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
7527 (*targetm.asm_out.unique_section) (decl, 0);
7528 switch_to_section (get_named_section (decl, NULL, 0));
7530 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7531 fputs ("\t.hidden\t", asm_out_file);
7532 assemble_name (asm_out_file, name);
7533 putc ('\n', asm_out_file);
7534 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7538 switch_to_section (text_section);
7539 ASM_OUTPUT_LABEL (asm_out_file, name);
7542 xops[0] = gen_rtx_REG (Pmode, regno);
7543 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7544 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7545 output_asm_insn ("ret", xops);
7548 if (NEED_INDICATE_EXEC_STACK)
7549 file_end_indicate_exec_stack ();
7552 /* Emit code for the SET_GOT patterns. */
7555 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7561 if (TARGET_VXWORKS_RTP && flag_pic)
7563 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7564 xops[2] = gen_rtx_MEM (Pmode,
7565 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7566 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7568 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7569 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7570 an unadorned address. */
7571 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7572 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7573 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7577 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7579 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7581 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7584 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7586 output_asm_insn ("call\t%a2", xops);
7589 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7590 is what will be referenced by the Mach-O PIC subsystem. */
7592 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7595 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7596 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7599 output_asm_insn ("pop%z0\t%0", xops);
7604 get_pc_thunk_name (name, REGNO (dest));
7605 pic_labels_used |= 1 << REGNO (dest);
7607 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7608 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7609 output_asm_insn ("call\t%X2", xops);
7610 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7611 is what will be referenced by the Mach-O PIC subsystem. */
7614 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7616 targetm.asm_out.internal_label (asm_out_file, "L",
7617 CODE_LABEL_NUMBER (label));
7624 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7625 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7627 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7632 /* Generate an "push" pattern for input ARG. */
7637 if (ix86_cfa_state->reg == stack_pointer_rtx)
7638 ix86_cfa_state->offset += UNITS_PER_WORD;
7640 return gen_rtx_SET (VOIDmode,
7642 gen_rtx_PRE_DEC (Pmode,
7643 stack_pointer_rtx)),
7647 /* Return >= 0 if there is an unused call-clobbered register available
7648 for the entire function. */
7651 ix86_select_alt_pic_regnum (void)
7653 if (current_function_is_leaf && !crtl->profile
7654 && !ix86_current_function_calls_tls_descriptor)
7657 /* Can't use the same register for both PIC and DRAP. */
7659 drap = REGNO (crtl->drap_reg);
7662 for (i = 2; i >= 0; --i)
7663 if (i != drap && !df_regs_ever_live_p (i))
7667 return INVALID_REGNUM;
7670 /* Return 1 if we need to save REGNO. */
7672 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7674 if (pic_offset_table_rtx
7675 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7676 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7678 || crtl->calls_eh_return
7679 || crtl->uses_const_pool))
7681 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7686 if (crtl->calls_eh_return && maybe_eh_return)
7691 unsigned test = EH_RETURN_DATA_REGNO (i);
7692 if (test == INVALID_REGNUM)
7699 if (crtl->drap_reg && regno == REGNO (crtl->drap_reg))
7702 return (df_regs_ever_live_p (regno)
7703 && !call_used_regs[regno]
7704 && !fixed_regs[regno]
7705 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7708 /* Return number of saved general prupose registers. */
7711 ix86_nsaved_regs (void)
7716 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7717 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7722 /* Return number of saved SSE registrers. */
7725 ix86_nsaved_sseregs (void)
7730 if (ix86_cfun_abi () != MS_ABI)
7732 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7733 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7738 /* Given FROM and TO register numbers, say whether this elimination is
7739 allowed. If stack alignment is needed, we can only replace argument
7740 pointer with hard frame pointer, or replace frame pointer with stack
7741 pointer. Otherwise, frame pointer elimination is automatically
7742 handled and all other eliminations are valid. */
7745 ix86_can_eliminate (const int from, const int to)
7747 if (stack_realign_fp)
7748 return ((from == ARG_POINTER_REGNUM
7749 && to == HARD_FRAME_POINTER_REGNUM)
7750 || (from == FRAME_POINTER_REGNUM
7751 && to == STACK_POINTER_REGNUM));
7753 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : true;
7756 /* Return the offset between two registers, one to be eliminated, and the other
7757 its replacement, at the start of a routine. */
7760 ix86_initial_elimination_offset (int from, int to)
7762 struct ix86_frame frame;
7763 ix86_compute_frame_layout (&frame);
7765 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7766 return frame.hard_frame_pointer_offset;
7767 else if (from == FRAME_POINTER_REGNUM
7768 && to == HARD_FRAME_POINTER_REGNUM)
7769 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7772 gcc_assert (to == STACK_POINTER_REGNUM);
7774 if (from == ARG_POINTER_REGNUM)
7775 return frame.stack_pointer_offset;
7777 gcc_assert (from == FRAME_POINTER_REGNUM);
7778 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7782 /* In a dynamically-aligned function, we can't know the offset from
7783 stack pointer to frame pointer, so we must ensure that setjmp
7784 eliminates fp against the hard fp (%ebp) rather than trying to
7785 index from %esp up to the top of the frame across a gap that is
7786 of unknown (at compile-time) size. */
7788 ix86_builtin_setjmp_frame_value (void)
7790 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7793 /* Fill structure ix86_frame about frame of currently computed function. */
7796 ix86_compute_frame_layout (struct ix86_frame *frame)
7798 unsigned int stack_alignment_needed;
7799 HOST_WIDE_INT offset;
7800 unsigned int preferred_alignment;
7801 HOST_WIDE_INT size = get_frame_size ();
7803 frame->nregs = ix86_nsaved_regs ();
7804 frame->nsseregs = ix86_nsaved_sseregs ();
7806 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7807 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7809 /* MS ABI seem to require stack alignment to be always 16 except for function
7811 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7813 preferred_alignment = 16;
7814 stack_alignment_needed = 16;
7815 crtl->preferred_stack_boundary = 128;
7816 crtl->stack_alignment_needed = 128;
7819 gcc_assert (!size || stack_alignment_needed);
7820 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7821 gcc_assert (preferred_alignment <= stack_alignment_needed);
7823 /* During reload iteration the amount of registers saved can change.
7824 Recompute the value as needed. Do not recompute when amount of registers
7825 didn't change as reload does multiple calls to the function and does not
7826 expect the decision to change within single iteration. */
7827 if (!optimize_function_for_size_p (cfun)
7828 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7830 int count = frame->nregs;
7832 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7833 /* The fast prologue uses move instead of push to save registers. This
7834 is significantly longer, but also executes faster as modern hardware
7835 can execute the moves in parallel, but can't do that for push/pop.
7837 Be careful about choosing what prologue to emit: When function takes
7838 many instructions to execute we may use slow version as well as in
7839 case function is known to be outside hot spot (this is known with
7840 feedback only). Weight the size of function by number of registers
7841 to save as it is cheap to use one or two push instructions but very
7842 slow to use many of them. */
7844 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7845 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7846 || (flag_branch_probabilities
7847 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7848 cfun->machine->use_fast_prologue_epilogue = false;
7850 cfun->machine->use_fast_prologue_epilogue
7851 = !expensive_function_p (count);
7853 if (TARGET_PROLOGUE_USING_MOVE
7854 && cfun->machine->use_fast_prologue_epilogue)
7855 frame->save_regs_using_mov = true;
7857 frame->save_regs_using_mov = false;
7859 /* Skip return address. */
7860 offset = UNITS_PER_WORD;
7862 /* Skip pushed static chain. */
7863 if (ix86_static_chain_on_stack)
7864 offset += UNITS_PER_WORD;
7866 /* Skip saved base pointer. */
7867 if (frame_pointer_needed)
7868 offset += UNITS_PER_WORD;
7870 frame->hard_frame_pointer_offset = offset;
7872 /* Set offset to aligned because the realigned frame starts from
7874 if (stack_realign_fp)
7875 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7877 /* Register save area */
7878 offset += frame->nregs * UNITS_PER_WORD;
7880 /* Align SSE reg save area. */
7881 if (frame->nsseregs)
7882 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7884 frame->padding0 = 0;
7886 /* SSE register save area. */
7887 offset += frame->padding0 + frame->nsseregs * 16;
7890 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7891 offset += frame->va_arg_size;
7893 /* Align start of frame for local function. */
7894 frame->padding1 = ((offset + stack_alignment_needed - 1)
7895 & -stack_alignment_needed) - offset;
7897 offset += frame->padding1;
7899 /* Frame pointer points here. */
7900 frame->frame_pointer_offset = offset;
7904 /* Add outgoing arguments area. Can be skipped if we eliminated
7905 all the function calls as dead code.
7906 Skipping is however impossible when function calls alloca. Alloca
7907 expander assumes that last crtl->outgoing_args_size
7908 of stack frame are unused. */
7909 if (ACCUMULATE_OUTGOING_ARGS
7910 && (!current_function_is_leaf || cfun->calls_alloca
7911 || ix86_current_function_calls_tls_descriptor))
7913 offset += crtl->outgoing_args_size;
7914 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7917 frame->outgoing_arguments_size = 0;
7919 /* Align stack boundary. Only needed if we're calling another function
7921 if (!current_function_is_leaf || cfun->calls_alloca
7922 || ix86_current_function_calls_tls_descriptor)
7923 frame->padding2 = ((offset + preferred_alignment - 1)
7924 & -preferred_alignment) - offset;
7926 frame->padding2 = 0;
7928 offset += frame->padding2;
7930 /* We've reached end of stack frame. */
7931 frame->stack_pointer_offset = offset;
7933 /* Size prologue needs to allocate. */
7934 frame->to_allocate =
7935 (size + frame->padding1 + frame->padding2
7936 + frame->outgoing_arguments_size + frame->va_arg_size);
7938 if ((!frame->to_allocate && frame->nregs <= 1)
7939 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7940 frame->save_regs_using_mov = false;
7942 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
7943 && current_function_sp_is_unchanging
7944 && current_function_is_leaf
7945 && !ix86_current_function_calls_tls_descriptor)
7947 frame->red_zone_size = frame->to_allocate;
7948 if (frame->save_regs_using_mov)
7949 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7950 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7951 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7954 frame->red_zone_size = 0;
7955 frame->to_allocate -= frame->red_zone_size;
7956 frame->stack_pointer_offset -= frame->red_zone_size;
7959 /* Emit code to save registers in the prologue. */
7962 ix86_emit_save_regs (void)
7967 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7968 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7970 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7971 RTX_FRAME_RELATED_P (insn) = 1;
7975 /* Emit code to save registers using MOV insns. First register
7976 is restored from POINTER + OFFSET. */
7978 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7983 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7984 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7986 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7988 gen_rtx_REG (Pmode, regno));
7989 RTX_FRAME_RELATED_P (insn) = 1;
7990 offset += UNITS_PER_WORD;
7994 /* Emit code to save registers using MOV insns. First register
7995 is restored from POINTER + OFFSET. */
7997 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8003 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8004 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8006 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
8007 set_mem_align (mem, 128);
8008 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
8009 RTX_FRAME_RELATED_P (insn) = 1;
8014 static GTY(()) rtx queued_cfa_restores;
8016 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8017 manipulation insn. Don't add it if the previously
8018 saved value will be left untouched within stack red-zone till return,
8019 as unwinders can find the same value in the register and
8023 ix86_add_cfa_restore_note (rtx insn, rtx reg, HOST_WIDE_INT red_offset)
8026 && !TARGET_64BIT_MS_ABI
8027 && red_offset + RED_ZONE_SIZE >= 0
8028 && crtl->args.pops_args < 65536)
8033 add_reg_note (insn, REG_CFA_RESTORE, reg);
8034 RTX_FRAME_RELATED_P (insn) = 1;
8038 = alloc_reg_note (REG_CFA_RESTORE, reg, queued_cfa_restores);
8041 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8044 ix86_add_queued_cfa_restore_notes (rtx insn)
8047 if (!queued_cfa_restores)
8049 for (last = queued_cfa_restores; XEXP (last, 1); last = XEXP (last, 1))
8051 XEXP (last, 1) = REG_NOTES (insn);
8052 REG_NOTES (insn) = queued_cfa_restores;
8053 queued_cfa_restores = NULL_RTX;
8054 RTX_FRAME_RELATED_P (insn) = 1;
8057 /* Expand prologue or epilogue stack adjustment.
8058 The pattern exist to put a dependency on all ebp-based memory accesses.
8059 STYLE should be negative if instructions should be marked as frame related,
8060 zero if %r11 register is live and cannot be freely used and positive
8064 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
8065 int style, bool set_cfa)
8070 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
8071 else if (x86_64_immediate_operand (offset, DImode))
8072 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
8076 /* r11 is used by indirect sibcall return as well, set before the
8077 epilogue and used after the epilogue. ATM indirect sibcall
8078 shouldn't be used together with huge frame sizes in one
8079 function because of the frame_size check in sibcall.c. */
8081 r11 = gen_rtx_REG (DImode, R11_REG);
8082 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
8084 RTX_FRAME_RELATED_P (insn) = 1;
8085 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
8090 ix86_add_queued_cfa_restore_notes (insn);
8096 gcc_assert (ix86_cfa_state->reg == src);
8097 ix86_cfa_state->offset += INTVAL (offset);
8098 ix86_cfa_state->reg = dest;
8100 r = gen_rtx_PLUS (Pmode, src, offset);
8101 r = gen_rtx_SET (VOIDmode, dest, r);
8102 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
8103 RTX_FRAME_RELATED_P (insn) = 1;
8106 RTX_FRAME_RELATED_P (insn) = 1;
8109 /* Find an available register to be used as dynamic realign argument
8110 pointer regsiter. Such a register will be written in prologue and
8111 used in begin of body, so it must not be
8112 1. parameter passing register.
8114 We reuse static-chain register if it is available. Otherwise, we
8115 use DI for i386 and R13 for x86-64. We chose R13 since it has
8118 Return: the regno of chosen register. */
8121 find_drap_reg (void)
8123 tree decl = cfun->decl;
8127 /* Use R13 for nested function or function need static chain.
8128 Since function with tail call may use any caller-saved
8129 registers in epilogue, DRAP must not use caller-saved
8130 register in such case. */
8131 if ((decl_function_context (decl)
8132 && !DECL_NO_STATIC_CHAIN (decl))
8133 || crtl->tail_call_emit)
8140 /* Use DI for nested function or function need static chain.
8141 Since function with tail call may use any caller-saved
8142 registers in epilogue, DRAP must not use caller-saved
8143 register in such case. */
8144 if ((decl_function_context (decl)
8145 && !DECL_NO_STATIC_CHAIN (decl))
8146 || crtl->tail_call_emit)
8149 /* Reuse static chain register if it isn't used for parameter
8151 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8152 && !lookup_attribute ("fastcall",
8153 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8160 /* Update incoming stack boundary and estimated stack alignment. */
8163 ix86_update_stack_boundary (void)
8165 /* Prefer the one specified at command line. */
8166 ix86_incoming_stack_boundary
8167 = (ix86_user_incoming_stack_boundary
8168 ? ix86_user_incoming_stack_boundary
8169 : ix86_default_incoming_stack_boundary);
8171 /* Incoming stack alignment can be changed on individual functions
8172 via force_align_arg_pointer attribute. We use the smallest
8173 incoming stack boundary. */
8174 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
8175 && lookup_attribute (ix86_force_align_arg_pointer_string,
8176 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8177 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
8179 /* The incoming stack frame has to be aligned at least at
8180 parm_stack_boundary. */
8181 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
8182 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
8184 /* Stack at entrance of main is aligned by runtime. We use the
8185 smallest incoming stack boundary. */
8186 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
8187 && DECL_NAME (current_function_decl)
8188 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8189 && DECL_FILE_SCOPE_P (current_function_decl))
8190 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8192 /* x86_64 vararg needs 16byte stack alignment for register save
8196 && crtl->stack_alignment_estimated < 128)
8197 crtl->stack_alignment_estimated = 128;
8200 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8201 needed or an rtx for DRAP otherwise. */
8204 ix86_get_drap_rtx (void)
8206 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8207 crtl->need_drap = true;
8209 if (stack_realign_drap)
8211 /* Assign DRAP to vDRAP and returns vDRAP */
8212 unsigned int regno = find_drap_reg ();
8217 arg_ptr = gen_rtx_REG (Pmode, regno);
8218 crtl->drap_reg = arg_ptr;
8221 drap_vreg = copy_to_reg (arg_ptr);
8225 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8226 RTX_FRAME_RELATED_P (insn) = 1;
8233 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8236 ix86_internal_arg_pointer (void)
8238 return virtual_incoming_args_rtx;
8241 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8242 to be generated in correct form. */
8244 ix86_finalize_stack_realign_flags (void)
8246 /* Check if stack realign is really needed after reload, and
8247 stores result in cfun */
8248 unsigned int incoming_stack_boundary
8249 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8250 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8251 unsigned int stack_realign = (incoming_stack_boundary
8252 < (current_function_is_leaf
8253 ? crtl->max_used_stack_slot_alignment
8254 : crtl->stack_alignment_needed));
8256 if (crtl->stack_realign_finalized)
8258 /* After stack_realign_needed is finalized, we can't no longer
8260 gcc_assert (crtl->stack_realign_needed == stack_realign);
8264 crtl->stack_realign_needed = stack_realign;
8265 crtl->stack_realign_finalized = true;
8269 /* Expand the prologue into a bunch of separate insns. */
8272 ix86_expand_prologue (void)
8276 struct ix86_frame frame;
8277 HOST_WIDE_INT allocate;
8279 ix86_finalize_stack_realign_flags ();
8281 /* DRAP should not coexist with stack_realign_fp */
8282 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8284 /* Initialize CFA state for before the prologue. */
8285 ix86_cfa_state->reg = stack_pointer_rtx;
8286 ix86_cfa_state->offset = INCOMING_FRAME_SP_OFFSET;
8288 ix86_compute_frame_layout (&frame);
8290 /* The first insn of a function that accepts its static chain on the
8291 stack is to push the register that would be filled in by a direct
8292 call. This insn will be skipped by the trampoline. */
8293 if (ix86_static_chain_on_stack)
8297 insn = emit_insn (gen_push (ix86_static_chain (cfun->decl, false)));
8298 emit_insn (gen_blockage ());
8300 /* We don't want to interpret this push insn as a register save,
8301 only as a stack adjustment. The real copy of the register as
8302 a save will be done later, if needed. */
8303 t = plus_constant (stack_pointer_rtx, -UNITS_PER_WORD);
8304 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8305 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8306 RTX_FRAME_RELATED_P (insn) = 1;
8309 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8310 of DRAP is needed and stack realignment is really needed after reload */
8311 if (crtl->drap_reg && crtl->stack_realign_needed)
8314 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8315 int param_ptr_offset = UNITS_PER_WORD;
8317 if (ix86_static_chain_on_stack)
8318 param_ptr_offset += UNITS_PER_WORD;
8319 if (!call_used_regs[REGNO (crtl->drap_reg)])
8320 param_ptr_offset += UNITS_PER_WORD;
8322 gcc_assert (stack_realign_drap);
8324 /* Grab the argument pointer. */
8325 x = plus_constant (stack_pointer_rtx, param_ptr_offset);
8328 /* Only need to push parameter pointer reg if it is caller
8330 if (!call_used_regs[REGNO (crtl->drap_reg)])
8332 /* Push arg pointer reg */
8333 insn = emit_insn (gen_push (y));
8334 RTX_FRAME_RELATED_P (insn) = 1;
8337 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8338 RTX_FRAME_RELATED_P (insn) = 1;
8339 ix86_cfa_state->reg = crtl->drap_reg;
8341 /* Align the stack. */
8342 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8344 GEN_INT (-align_bytes)));
8345 RTX_FRAME_RELATED_P (insn) = 1;
8347 /* Replicate the return address on the stack so that return
8348 address can be reached via (argp - 1) slot. This is needed
8349 to implement macro RETURN_ADDR_RTX and intrinsic function
8350 expand_builtin_return_addr etc. */
8352 x = gen_frame_mem (Pmode,
8353 plus_constant (x, -UNITS_PER_WORD));
8354 insn = emit_insn (gen_push (x));
8355 RTX_FRAME_RELATED_P (insn) = 1;
8358 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8359 slower on all targets. Also sdb doesn't like it. */
8361 if (frame_pointer_needed)
8363 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8364 RTX_FRAME_RELATED_P (insn) = 1;
8366 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8367 RTX_FRAME_RELATED_P (insn) = 1;
8369 if (ix86_cfa_state->reg == stack_pointer_rtx)
8370 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8373 if (stack_realign_fp)
8375 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8376 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8378 /* Align the stack. */
8379 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8381 GEN_INT (-align_bytes)));
8382 RTX_FRAME_RELATED_P (insn) = 1;
8385 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8387 if (!frame.save_regs_using_mov)
8388 ix86_emit_save_regs ();
8390 allocate += frame.nregs * UNITS_PER_WORD;
8392 /* When using red zone we may start register saving before allocating
8393 the stack frame saving one cycle of the prologue. However I will
8394 avoid doing this if I am going to have to probe the stack since
8395 at least on x86_64 the stack probe can turn into a call that clobbers
8396 a red zone location */
8397 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8398 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8399 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8400 && !crtl->stack_realign_needed)
8401 ? hard_frame_pointer_rtx
8402 : stack_pointer_rtx,
8403 -frame.nregs * UNITS_PER_WORD);
8407 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8408 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8409 GEN_INT (-allocate), -1,
8410 ix86_cfa_state->reg == stack_pointer_rtx);
8413 /* Only valid for Win32. */
8414 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8418 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8420 if (cfun->machine->call_abi == MS_ABI)
8423 eax_live = ix86_eax_live_at_start_p ();
8427 emit_insn (gen_push (eax));
8428 allocate -= UNITS_PER_WORD;
8431 emit_move_insn (eax, GEN_INT (allocate));
8434 insn = gen_allocate_stack_worker_64 (eax, eax);
8436 insn = gen_allocate_stack_worker_32 (eax, eax);
8437 insn = emit_insn (insn);
8439 if (ix86_cfa_state->reg == stack_pointer_rtx)
8441 ix86_cfa_state->offset += allocate;
8442 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8443 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8444 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8445 RTX_FRAME_RELATED_P (insn) = 1;
8450 if (frame_pointer_needed)
8451 t = plus_constant (hard_frame_pointer_rtx,
8454 - frame.nregs * UNITS_PER_WORD);
8456 t = plus_constant (stack_pointer_rtx, allocate);
8457 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8461 if (frame.save_regs_using_mov
8462 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8463 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8465 if (!frame_pointer_needed
8466 || !(frame.to_allocate + frame.padding0)
8467 || crtl->stack_realign_needed)
8468 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8470 + frame.nsseregs * 16 + frame.padding0);
8472 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8473 -frame.nregs * UNITS_PER_WORD);
8475 if (!frame_pointer_needed
8476 || !(frame.to_allocate + frame.padding0)
8477 || crtl->stack_realign_needed)
8478 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8481 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8482 - frame.nregs * UNITS_PER_WORD
8483 - frame.nsseregs * 16
8486 pic_reg_used = false;
8487 if (pic_offset_table_rtx
8488 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8491 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8493 if (alt_pic_reg_used != INVALID_REGNUM)
8494 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8496 pic_reg_used = true;
8503 if (ix86_cmodel == CM_LARGE_PIC)
8505 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8506 rtx label = gen_label_rtx ();
8508 LABEL_PRESERVE_P (label) = 1;
8509 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8510 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8511 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8512 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8513 pic_offset_table_rtx, tmp_reg));
8516 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8519 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8522 /* In the pic_reg_used case, make sure that the got load isn't deleted
8523 when mcount needs it. Blockage to avoid call movement across mcount
8524 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8526 if (crtl->profile && pic_reg_used)
8527 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8529 if (crtl->drap_reg && !crtl->stack_realign_needed)
8531 /* vDRAP is setup but after reload it turns out stack realign
8532 isn't necessary, here we will emit prologue to setup DRAP
8533 without stack realign adjustment */
8535 int drap_bp_offset = UNITS_PER_WORD * 2;
8537 if (ix86_static_chain_on_stack)
8538 drap_bp_offset += UNITS_PER_WORD;
8539 x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8540 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8543 /* Prevent instructions from being scheduled into register save push
8544 sequence when access to the redzone area is done through frame pointer.
8545 The offset between the frame pointer and the stack pointer is calculated
8546 relative to the value of the stack pointer at the end of the function
8547 prologue, and moving instructions that access redzone area via frame
8548 pointer inside push sequence violates this assumption. */
8549 if (frame_pointer_needed && frame.red_zone_size)
8550 emit_insn (gen_memory_blockage ());
8552 /* Emit cld instruction if stringops are used in the function. */
8553 if (TARGET_CLD && ix86_current_function_needs_cld)
8554 emit_insn (gen_cld ());
8557 /* Emit code to restore REG using a POP insn. */
8560 ix86_emit_restore_reg_using_pop (rtx reg, HOST_WIDE_INT red_offset)
8562 rtx insn = emit_insn (ix86_gen_pop1 (reg));
8564 if (ix86_cfa_state->reg == crtl->drap_reg
8565 && REGNO (reg) == REGNO (crtl->drap_reg))
8567 /* Previously we'd represented the CFA as an expression
8568 like *(%ebp - 8). We've just popped that value from
8569 the stack, which means we need to reset the CFA to
8570 the drap register. This will remain until we restore
8571 the stack pointer. */
8572 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8573 RTX_FRAME_RELATED_P (insn) = 1;
8577 if (ix86_cfa_state->reg == stack_pointer_rtx)
8579 ix86_cfa_state->offset -= UNITS_PER_WORD;
8580 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8581 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
8582 RTX_FRAME_RELATED_P (insn) = 1;
8585 /* When the frame pointer is the CFA, and we pop it, we are
8586 swapping back to the stack pointer as the CFA. This happens
8587 for stack frames that don't allocate other data, so we assume
8588 the stack pointer is now pointing at the return address, i.e.
8589 the function entry state, which makes the offset be 1 word. */
8590 else if (ix86_cfa_state->reg == hard_frame_pointer_rtx
8591 && reg == hard_frame_pointer_rtx)
8593 ix86_cfa_state->reg = stack_pointer_rtx;
8594 ix86_cfa_state->offset -= UNITS_PER_WORD;
8596 add_reg_note (insn, REG_CFA_DEF_CFA,
8597 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8598 GEN_INT (ix86_cfa_state->offset)));
8599 RTX_FRAME_RELATED_P (insn) = 1;
8602 ix86_add_cfa_restore_note (insn, reg, red_offset);
8605 /* Emit code to restore saved registers using POP insns. */
8608 ix86_emit_restore_regs_using_pop (HOST_WIDE_INT red_offset)
8612 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8613 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8615 ix86_emit_restore_reg_using_pop (gen_rtx_REG (Pmode, regno),
8617 red_offset += UNITS_PER_WORD;
8621 /* Emit code and notes for the LEAVE instruction. */
8624 ix86_emit_leave (HOST_WIDE_INT red_offset)
8626 rtx insn = emit_insn (ix86_gen_leave ());
8628 ix86_add_queued_cfa_restore_notes (insn);
8630 if (ix86_cfa_state->reg == hard_frame_pointer_rtx)
8632 ix86_cfa_state->reg = stack_pointer_rtx;
8633 ix86_cfa_state->offset -= UNITS_PER_WORD;
8635 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8636 copy_rtx (XVECEXP (PATTERN (insn), 0, 0)));
8637 RTX_FRAME_RELATED_P (insn) = 1;
8638 ix86_add_cfa_restore_note (insn, hard_frame_pointer_rtx, red_offset);
8642 /* Emit code to restore saved registers using MOV insns. First register
8643 is restored from POINTER + OFFSET. */
8645 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8646 HOST_WIDE_INT red_offset,
8647 int maybe_eh_return)
8650 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8653 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8654 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8656 rtx reg = gen_rtx_REG (Pmode, regno);
8658 /* Ensure that adjust_address won't be forced to produce pointer
8659 out of range allowed by x86-64 instruction set. */
8660 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8664 r11 = gen_rtx_REG (DImode, R11_REG);
8665 emit_move_insn (r11, GEN_INT (offset));
8666 emit_insn (gen_adddi3 (r11, r11, pointer));
8667 base_address = gen_rtx_MEM (Pmode, r11);
8670 insn = emit_move_insn (reg,
8671 adjust_address (base_address, Pmode, offset));
8672 offset += UNITS_PER_WORD;
8674 if (ix86_cfa_state->reg == crtl->drap_reg
8675 && regno == REGNO (crtl->drap_reg))
8677 /* Previously we'd represented the CFA as an expression
8678 like *(%ebp - 8). We've just popped that value from
8679 the stack, which means we need to reset the CFA to
8680 the drap register. This will remain until we restore
8681 the stack pointer. */
8682 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8683 RTX_FRAME_RELATED_P (insn) = 1;
8686 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8688 red_offset += UNITS_PER_WORD;
8692 /* Emit code to restore saved registers using MOV insns. First register
8693 is restored from POINTER + OFFSET. */
8695 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8696 HOST_WIDE_INT red_offset,
8697 int maybe_eh_return)
8700 rtx base_address = gen_rtx_MEM (TImode, pointer);
8703 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8704 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8706 rtx reg = gen_rtx_REG (TImode, regno);
8708 /* Ensure that adjust_address won't be forced to produce pointer
8709 out of range allowed by x86-64 instruction set. */
8710 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8714 r11 = gen_rtx_REG (DImode, R11_REG);
8715 emit_move_insn (r11, GEN_INT (offset));
8716 emit_insn (gen_adddi3 (r11, r11, pointer));
8717 base_address = gen_rtx_MEM (TImode, r11);
8720 mem = adjust_address (base_address, TImode, offset);
8721 set_mem_align (mem, 128);
8722 insn = emit_move_insn (reg, mem);
8725 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8731 /* Restore function stack, frame, and registers. */
8734 ix86_expand_epilogue (int style)
8737 struct ix86_frame frame;
8738 HOST_WIDE_INT offset, red_offset;
8739 struct machine_cfa_state cfa_state_save = *ix86_cfa_state;
8742 ix86_finalize_stack_realign_flags ();
8744 /* When stack is realigned, SP must be valid. */
8745 sp_valid = (!frame_pointer_needed
8746 || current_function_sp_is_unchanging
8747 || stack_realign_fp);
8749 ix86_compute_frame_layout (&frame);
8751 /* See the comment about red zone and frame
8752 pointer usage in ix86_expand_prologue. */
8753 if (frame_pointer_needed && frame.red_zone_size)
8754 emit_insn (gen_memory_blockage ());
8756 using_drap = crtl->drap_reg && crtl->stack_realign_needed;
8757 gcc_assert (!using_drap || ix86_cfa_state->reg == crtl->drap_reg);
8759 /* Calculate start of saved registers relative to ebp. Special care
8760 must be taken for the normal return case of a function using
8761 eh_return: the eax and edx registers are marked as saved, but not
8762 restored along this path. */
8763 offset = frame.nregs;
8764 if (crtl->calls_eh_return && style != 2)
8766 offset *= -UNITS_PER_WORD;
8767 offset -= frame.nsseregs * 16 + frame.padding0;
8769 /* Calculate start of saved registers relative to esp on entry of the
8770 function. When realigning stack, this needs to be the most negative
8771 value possible at runtime. */
8772 red_offset = offset;
8774 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8776 else if (stack_realign_fp)
8777 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8779 if (ix86_static_chain_on_stack)
8780 red_offset -= UNITS_PER_WORD;
8781 if (frame_pointer_needed)
8782 red_offset -= UNITS_PER_WORD;
8784 /* If we're only restoring one register and sp is not valid then
8785 using a move instruction to restore the register since it's
8786 less work than reloading sp and popping the register.
8788 The default code result in stack adjustment using add/lea instruction,
8789 while this code results in LEAVE instruction (or discrete equivalent),
8790 so it is profitable in some other cases as well. Especially when there
8791 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8792 and there is exactly one register to pop. This heuristic may need some
8793 tuning in future. */
8794 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8795 || (TARGET_EPILOGUE_USING_MOVE
8796 && cfun->machine->use_fast_prologue_epilogue
8797 && ((frame.nregs + frame.nsseregs) > 1
8798 || (frame.to_allocate + frame.padding0) != 0))
8799 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8800 && (frame.to_allocate + frame.padding0) != 0)
8801 || (frame_pointer_needed && TARGET_USE_LEAVE
8802 && cfun->machine->use_fast_prologue_epilogue
8803 && (frame.nregs + frame.nsseregs) == 1)
8804 || crtl->calls_eh_return)
8806 /* Restore registers. We can use ebp or esp to address the memory
8807 locations. If both are available, default to ebp, since offsets
8808 are known to be small. Only exception is esp pointing directly
8809 to the end of block of saved registers, where we may simplify
8812 If we are realigning stack with bp and sp, regs restore can't
8813 be addressed by bp. sp must be used instead. */
8815 if (!frame_pointer_needed
8816 || (sp_valid && !(frame.to_allocate + frame.padding0))
8817 || stack_realign_fp)
8819 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8820 frame.to_allocate, red_offset,
8822 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8824 + frame.nsseregs * 16
8827 + frame.nsseregs * 16
8828 + frame.padding0, style == 2);
8832 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8835 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8837 + frame.nsseregs * 16
8840 + frame.nsseregs * 16
8841 + frame.padding0, style == 2);
8844 red_offset -= offset;
8846 /* eh_return epilogues need %ecx added to the stack pointer. */
8849 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8851 /* Stack align doesn't work with eh_return. */
8852 gcc_assert (!crtl->stack_realign_needed);
8853 /* Neither does regparm nested functions. */
8854 gcc_assert (!ix86_static_chain_on_stack);
8856 if (frame_pointer_needed)
8858 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8859 tmp = plus_constant (tmp, UNITS_PER_WORD);
8860 tmp = emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8862 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8863 tmp = emit_move_insn (hard_frame_pointer_rtx, tmp);
8865 /* Note that we use SA as a temporary CFA, as the return
8866 address is at the proper place relative to it. We
8867 pretend this happens at the FP restore insn because
8868 prior to this insn the FP would be stored at the wrong
8869 offset relative to SA, and after this insn we have no
8870 other reasonable register to use for the CFA. We don't
8871 bother resetting the CFA to the SP for the duration of
8873 add_reg_note (tmp, REG_CFA_DEF_CFA,
8874 plus_constant (sa, UNITS_PER_WORD));
8875 ix86_add_queued_cfa_restore_notes (tmp);
8876 add_reg_note (tmp, REG_CFA_RESTORE, hard_frame_pointer_rtx);
8877 RTX_FRAME_RELATED_P (tmp) = 1;
8878 ix86_cfa_state->reg = sa;
8879 ix86_cfa_state->offset = UNITS_PER_WORD;
8881 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8882 const0_rtx, style, false);
8886 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8887 tmp = plus_constant (tmp, (frame.to_allocate
8888 + frame.nregs * UNITS_PER_WORD
8889 + frame.nsseregs * 16
8891 tmp = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8892 ix86_add_queued_cfa_restore_notes (tmp);
8894 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
8895 if (ix86_cfa_state->offset != UNITS_PER_WORD)
8897 ix86_cfa_state->offset = UNITS_PER_WORD;
8898 add_reg_note (tmp, REG_CFA_DEF_CFA,
8899 plus_constant (stack_pointer_rtx,
8901 RTX_FRAME_RELATED_P (tmp) = 1;
8905 else if (!frame_pointer_needed)
8906 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8907 GEN_INT (frame.to_allocate
8908 + frame.nregs * UNITS_PER_WORD
8909 + frame.nsseregs * 16
8911 style, !using_drap);
8912 /* If not an i386, mov & pop is faster than "leave". */
8913 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8914 || !cfun->machine->use_fast_prologue_epilogue)
8915 ix86_emit_leave (red_offset);
8918 pro_epilogue_adjust_stack (stack_pointer_rtx,
8919 hard_frame_pointer_rtx,
8920 const0_rtx, style, !using_drap);
8922 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx, red_offset);
8927 /* First step is to deallocate the stack frame so that we can
8930 If we realign stack with frame pointer, then stack pointer
8931 won't be able to recover via lea $offset(%bp), %sp, because
8932 there is a padding area between bp and sp for realign.
8933 "add $to_allocate, %sp" must be used instead. */
8936 gcc_assert (frame_pointer_needed);
8937 gcc_assert (!stack_realign_fp);
8938 pro_epilogue_adjust_stack (stack_pointer_rtx,
8939 hard_frame_pointer_rtx,
8940 GEN_INT (offset), style, false);
8941 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8944 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8945 GEN_INT (frame.nsseregs * 16 + frame.padding0),
8948 else if (frame.to_allocate || frame.padding0 || frame.nsseregs)
8950 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8951 frame.to_allocate, red_offset,
8953 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8954 GEN_INT (frame.to_allocate
8955 + frame.nsseregs * 16
8956 + frame.padding0), style,
8957 !using_drap && !frame_pointer_needed);
8960 ix86_emit_restore_regs_using_pop (red_offset + frame.nsseregs * 16
8962 red_offset -= offset;
8964 if (frame_pointer_needed)
8966 /* Leave results in shorter dependency chains on CPUs that are
8967 able to grok it fast. */
8968 if (TARGET_USE_LEAVE)
8969 ix86_emit_leave (red_offset);
8972 /* For stack realigned really happens, recover stack
8973 pointer to hard frame pointer is a must, if not using
8975 if (stack_realign_fp)
8976 pro_epilogue_adjust_stack (stack_pointer_rtx,
8977 hard_frame_pointer_rtx,
8978 const0_rtx, style, !using_drap);
8979 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx,
8987 int param_ptr_offset = UNITS_PER_WORD;
8990 gcc_assert (stack_realign_drap);
8992 if (ix86_static_chain_on_stack)
8993 param_ptr_offset += UNITS_PER_WORD;
8994 if (!call_used_regs[REGNO (crtl->drap_reg)])
8995 param_ptr_offset += UNITS_PER_WORD;
8997 insn = emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
8999 GEN_INT (-param_ptr_offset)));
9001 ix86_cfa_state->reg = stack_pointer_rtx;
9002 ix86_cfa_state->offset = param_ptr_offset;
9004 add_reg_note (insn, REG_CFA_DEF_CFA,
9005 gen_rtx_PLUS (Pmode, ix86_cfa_state->reg,
9006 GEN_INT (ix86_cfa_state->offset)));
9007 RTX_FRAME_RELATED_P (insn) = 1;
9009 if (!call_used_regs[REGNO (crtl->drap_reg)])
9010 ix86_emit_restore_reg_using_pop (crtl->drap_reg, -UNITS_PER_WORD);
9013 /* Remove the saved static chain from the stack. The use of ECX is
9014 merely as a scratch register, not as the actual static chain. */
9015 if (ix86_static_chain_on_stack)
9019 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
9020 ix86_cfa_state->offset += UNITS_PER_WORD;
9022 r = gen_rtx_REG (Pmode, CX_REG);
9023 insn = emit_insn (ix86_gen_pop1 (r));
9025 r = plus_constant (stack_pointer_rtx, UNITS_PER_WORD);
9026 r = gen_rtx_SET (VOIDmode, stack_pointer_rtx, r);
9027 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
9028 RTX_FRAME_RELATED_P (insn) = 1;
9031 /* Sibcall epilogues don't want a return instruction. */
9034 *ix86_cfa_state = cfa_state_save;
9038 if (crtl->args.pops_args && crtl->args.size)
9040 rtx popc = GEN_INT (crtl->args.pops_args);
9042 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9043 address, do explicit add, and jump indirectly to the caller. */
9045 if (crtl->args.pops_args >= 65536)
9047 rtx ecx = gen_rtx_REG (SImode, CX_REG);
9050 /* There is no "pascal" calling convention in any 64bit ABI. */
9051 gcc_assert (!TARGET_64BIT);
9053 insn = emit_insn (gen_popsi1 (ecx));
9054 ix86_cfa_state->offset -= UNITS_PER_WORD;
9056 add_reg_note (insn, REG_CFA_ADJUST_CFA,
9057 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
9058 add_reg_note (insn, REG_CFA_REGISTER,
9059 gen_rtx_SET (VOIDmode, ecx, pc_rtx));
9060 RTX_FRAME_RELATED_P (insn) = 1;
9062 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9064 emit_jump_insn (gen_return_indirect_internal (ecx));
9067 emit_jump_insn (gen_return_pop_internal (popc));
9070 emit_jump_insn (gen_return_internal ());
9072 /* Restore the state back to the state from the prologue,
9073 so that it's correct for the next epilogue. */
9074 *ix86_cfa_state = cfa_state_save;
9077 /* Reset from the function's potential modifications. */
9080 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9081 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9083 if (pic_offset_table_rtx)
9084 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
9086 /* Mach-O doesn't support labels at the end of objects, so if
9087 it looks like we might want one, insert a NOP. */
9089 rtx insn = get_last_insn ();
9092 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
9093 insn = PREV_INSN (insn);
9097 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
9098 fputs ("\tnop\n", file);
9104 /* Extract the parts of an RTL expression that is a valid memory address
9105 for an instruction. Return 0 if the structure of the address is
9106 grossly off. Return -1 if the address contains ASHIFT, so it is not
9107 strictly valid, but still used for computing length of lea instruction. */
9110 ix86_decompose_address (rtx addr, struct ix86_address *out)
9112 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
9113 rtx base_reg, index_reg;
9114 HOST_WIDE_INT scale = 1;
9115 rtx scale_rtx = NULL_RTX;
9117 enum ix86_address_seg seg = SEG_DEFAULT;
9119 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
9121 else if (GET_CODE (addr) == PLUS)
9131 addends[n++] = XEXP (op, 1);
9134 while (GET_CODE (op) == PLUS);
9139 for (i = n; i >= 0; --i)
9142 switch (GET_CODE (op))
9147 index = XEXP (op, 0);
9148 scale_rtx = XEXP (op, 1);
9152 if (XINT (op, 1) == UNSPEC_TP
9153 && TARGET_TLS_DIRECT_SEG_REFS
9154 && seg == SEG_DEFAULT)
9155 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
9184 else if (GET_CODE (addr) == MULT)
9186 index = XEXP (addr, 0); /* index*scale */
9187 scale_rtx = XEXP (addr, 1);
9189 else if (GET_CODE (addr) == ASHIFT)
9193 /* We're called for lea too, which implements ashift on occasion. */
9194 index = XEXP (addr, 0);
9195 tmp = XEXP (addr, 1);
9196 if (!CONST_INT_P (tmp))
9198 scale = INTVAL (tmp);
9199 if ((unsigned HOST_WIDE_INT) scale > 3)
9205 disp = addr; /* displacement */
9207 /* Extract the integral value of scale. */
9210 if (!CONST_INT_P (scale_rtx))
9212 scale = INTVAL (scale_rtx);
9215 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
9216 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
9218 /* Avoid useless 0 displacement. */
9219 if (disp == const0_rtx && (base || index))
9222 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9223 if (base_reg && index_reg && scale == 1
9224 && (index_reg == arg_pointer_rtx
9225 || index_reg == frame_pointer_rtx
9226 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
9229 tmp = base, base = index, index = tmp;
9230 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
9233 /* Special case: %ebp cannot be encoded as a base without a displacement.
9237 && (base_reg == hard_frame_pointer_rtx
9238 || base_reg == frame_pointer_rtx
9239 || base_reg == arg_pointer_rtx
9240 || (REG_P (base_reg)
9241 && (REGNO (base_reg) == HARD_FRAME_POINTER_REGNUM
9242 || REGNO (base_reg) == R13_REG))))
9245 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9246 Avoid this by transforming to [%esi+0].
9247 Reload calls address legitimization without cfun defined, so we need
9248 to test cfun for being non-NULL. */
9249 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
9250 && base_reg && !index_reg && !disp
9252 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
9255 /* Special case: encode reg+reg instead of reg*2. */
9256 if (!base && index && scale == 2)
9257 base = index, base_reg = index_reg, scale = 1;
9259 /* Special case: scaling cannot be encoded without base or displacement. */
9260 if (!base && !disp && index && scale != 1)
9272 /* Return cost of the memory address x.
9273 For i386, it is better to use a complex address than let gcc copy
9274 the address into a reg and make a new pseudo. But not if the address
9275 requires to two regs - that would mean more pseudos with longer
9278 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
9280 struct ix86_address parts;
9282 int ok = ix86_decompose_address (x, &parts);
9286 if (parts.base && GET_CODE (parts.base) == SUBREG)
9287 parts.base = SUBREG_REG (parts.base);
9288 if (parts.index && GET_CODE (parts.index) == SUBREG)
9289 parts.index = SUBREG_REG (parts.index);
9291 /* Attempt to minimize number of registers in the address. */
9293 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
9295 && (!REG_P (parts.index)
9296 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
9300 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
9302 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
9303 && parts.base != parts.index)
9306 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9307 since it's predecode logic can't detect the length of instructions
9308 and it degenerates to vector decoded. Increase cost of such
9309 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9310 to split such addresses or even refuse such addresses at all.
9312 Following addressing modes are affected:
9317 The first and last case may be avoidable by explicitly coding the zero in
9318 memory address, but I don't have AMD-K6 machine handy to check this
9322 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
9323 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
9324 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
9330 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9331 this is used for to form addresses to local data when -fPIC is in
9335 darwin_local_data_pic (rtx disp)
9337 return (GET_CODE (disp) == UNSPEC
9338 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
9341 /* Determine if a given RTX is a valid constant. We already know this
9342 satisfies CONSTANT_P. */
9345 legitimate_constant_p (rtx x)
9347 switch (GET_CODE (x))
9352 if (GET_CODE (x) == PLUS)
9354 if (!CONST_INT_P (XEXP (x, 1)))
9359 if (TARGET_MACHO && darwin_local_data_pic (x))
9362 /* Only some unspecs are valid as "constants". */
9363 if (GET_CODE (x) == UNSPEC)
9364 switch (XINT (x, 1))
9369 return TARGET_64BIT;
9372 x = XVECEXP (x, 0, 0);
9373 return (GET_CODE (x) == SYMBOL_REF
9374 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9376 x = XVECEXP (x, 0, 0);
9377 return (GET_CODE (x) == SYMBOL_REF
9378 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9383 /* We must have drilled down to a symbol. */
9384 if (GET_CODE (x) == LABEL_REF)
9386 if (GET_CODE (x) != SYMBOL_REF)
9391 /* TLS symbols are never valid. */
9392 if (SYMBOL_REF_TLS_MODEL (x))
9395 /* DLLIMPORT symbols are never valid. */
9396 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9397 && SYMBOL_REF_DLLIMPORT_P (x))
9402 if (GET_MODE (x) == TImode
9403 && x != CONST0_RTX (TImode)
9409 if (!standard_sse_constant_p (x))
9416 /* Otherwise we handle everything else in the move patterns. */
9420 /* Determine if it's legal to put X into the constant pool. This
9421 is not possible for the address of thread-local symbols, which
9422 is checked above. */
9425 ix86_cannot_force_const_mem (rtx x)
9427 /* We can always put integral constants and vectors in memory. */
9428 switch (GET_CODE (x))
9438 return !legitimate_constant_p (x);
9442 /* Nonzero if the constant value X is a legitimate general operand
9443 when generating PIC code. It is given that flag_pic is on and
9444 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9447 legitimate_pic_operand_p (rtx x)
9451 switch (GET_CODE (x))
9454 inner = XEXP (x, 0);
9455 if (GET_CODE (inner) == PLUS
9456 && CONST_INT_P (XEXP (inner, 1)))
9457 inner = XEXP (inner, 0);
9459 /* Only some unspecs are valid as "constants". */
9460 if (GET_CODE (inner) == UNSPEC)
9461 switch (XINT (inner, 1))
9466 return TARGET_64BIT;
9468 x = XVECEXP (inner, 0, 0);
9469 return (GET_CODE (x) == SYMBOL_REF
9470 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9471 case UNSPEC_MACHOPIC_OFFSET:
9472 return legitimate_pic_address_disp_p (x);
9480 return legitimate_pic_address_disp_p (x);
9487 /* Determine if a given CONST RTX is a valid memory displacement
9491 legitimate_pic_address_disp_p (rtx disp)
9495 /* In 64bit mode we can allow direct addresses of symbols and labels
9496 when they are not dynamic symbols. */
9499 rtx op0 = disp, op1;
9501 switch (GET_CODE (disp))
9507 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9509 op0 = XEXP (XEXP (disp, 0), 0);
9510 op1 = XEXP (XEXP (disp, 0), 1);
9511 if (!CONST_INT_P (op1)
9512 || INTVAL (op1) >= 16*1024*1024
9513 || INTVAL (op1) < -16*1024*1024)
9515 if (GET_CODE (op0) == LABEL_REF)
9517 if (GET_CODE (op0) != SYMBOL_REF)
9522 /* TLS references should always be enclosed in UNSPEC. */
9523 if (SYMBOL_REF_TLS_MODEL (op0))
9525 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9526 && ix86_cmodel != CM_LARGE_PIC)
9534 if (GET_CODE (disp) != CONST)
9536 disp = XEXP (disp, 0);
9540 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9541 of GOT tables. We should not need these anyway. */
9542 if (GET_CODE (disp) != UNSPEC
9543 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9544 && XINT (disp, 1) != UNSPEC_GOTOFF
9545 && XINT (disp, 1) != UNSPEC_PLTOFF))
9548 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9549 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9555 if (GET_CODE (disp) == PLUS)
9557 if (!CONST_INT_P (XEXP (disp, 1)))
9559 disp = XEXP (disp, 0);
9563 if (TARGET_MACHO && darwin_local_data_pic (disp))
9566 if (GET_CODE (disp) != UNSPEC)
9569 switch (XINT (disp, 1))
9574 /* We need to check for both symbols and labels because VxWorks loads
9575 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9577 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9578 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9580 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9581 While ABI specify also 32bit relocation but we don't produce it in
9582 small PIC model at all. */
9583 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9584 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9586 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9588 case UNSPEC_GOTTPOFF:
9589 case UNSPEC_GOTNTPOFF:
9590 case UNSPEC_INDNTPOFF:
9593 disp = XVECEXP (disp, 0, 0);
9594 return (GET_CODE (disp) == SYMBOL_REF
9595 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9597 disp = XVECEXP (disp, 0, 0);
9598 return (GET_CODE (disp) == SYMBOL_REF
9599 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9601 disp = XVECEXP (disp, 0, 0);
9602 return (GET_CODE (disp) == SYMBOL_REF
9603 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9609 /* Recognizes RTL expressions that are valid memory addresses for an
9610 instruction. The MODE argument is the machine mode for the MEM
9611 expression that wants to use this address.
9613 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9614 convert common non-canonical forms to canonical form so that they will
9618 ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9619 rtx addr, bool strict)
9621 struct ix86_address parts;
9622 rtx base, index, disp;
9623 HOST_WIDE_INT scale;
9625 if (ix86_decompose_address (addr, &parts) <= 0)
9626 /* Decomposition failed. */
9630 index = parts.index;
9632 scale = parts.scale;
9634 /* Validate base register.
9636 Don't allow SUBREG's that span more than a word here. It can lead to spill
9637 failures when the base is one word out of a two word structure, which is
9638 represented internally as a DImode int. */
9646 else if (GET_CODE (base) == SUBREG
9647 && REG_P (SUBREG_REG (base))
9648 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9650 reg = SUBREG_REG (base);
9652 /* Base is not a register. */
9655 if (GET_MODE (base) != Pmode)
9656 /* Base is not in Pmode. */
9659 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9660 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9661 /* Base is not valid. */
9665 /* Validate index register.
9667 Don't allow SUBREG's that span more than a word here -- same as above. */
9675 else if (GET_CODE (index) == SUBREG
9676 && REG_P (SUBREG_REG (index))
9677 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9679 reg = SUBREG_REG (index);
9681 /* Index is not a register. */
9684 if (GET_MODE (index) != Pmode)
9685 /* Index is not in Pmode. */
9688 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9689 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9690 /* Index is not valid. */
9694 /* Validate scale factor. */
9698 /* Scale without index. */
9701 if (scale != 2 && scale != 4 && scale != 8)
9702 /* Scale is not a valid multiplier. */
9706 /* Validate displacement. */
9709 if (GET_CODE (disp) == CONST
9710 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9711 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9712 switch (XINT (XEXP (disp, 0), 1))
9714 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9715 used. While ABI specify also 32bit relocations, we don't produce
9716 them at all and use IP relative instead. */
9719 gcc_assert (flag_pic);
9721 goto is_legitimate_pic;
9723 /* 64bit address unspec. */
9726 case UNSPEC_GOTPCREL:
9727 gcc_assert (flag_pic);
9728 goto is_legitimate_pic;
9730 case UNSPEC_GOTTPOFF:
9731 case UNSPEC_GOTNTPOFF:
9732 case UNSPEC_INDNTPOFF:
9738 /* Invalid address unspec. */
9742 else if (SYMBOLIC_CONST (disp)
9746 && MACHOPIC_INDIRECT
9747 && !machopic_operand_p (disp)
9753 if (TARGET_64BIT && (index || base))
9755 /* foo@dtpoff(%rX) is ok. */
9756 if (GET_CODE (disp) != CONST
9757 || GET_CODE (XEXP (disp, 0)) != PLUS
9758 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9759 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9760 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9761 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9762 /* Non-constant pic memory reference. */
9765 else if (! legitimate_pic_address_disp_p (disp))
9766 /* Displacement is an invalid pic construct. */
9769 /* This code used to verify that a symbolic pic displacement
9770 includes the pic_offset_table_rtx register.
9772 While this is good idea, unfortunately these constructs may
9773 be created by "adds using lea" optimization for incorrect
9782 This code is nonsensical, but results in addressing
9783 GOT table with pic_offset_table_rtx base. We can't
9784 just refuse it easily, since it gets matched by
9785 "addsi3" pattern, that later gets split to lea in the
9786 case output register differs from input. While this
9787 can be handled by separate addsi pattern for this case
9788 that never results in lea, this seems to be easier and
9789 correct fix for crash to disable this test. */
9791 else if (GET_CODE (disp) != LABEL_REF
9792 && !CONST_INT_P (disp)
9793 && (GET_CODE (disp) != CONST
9794 || !legitimate_constant_p (disp))
9795 && (GET_CODE (disp) != SYMBOL_REF
9796 || !legitimate_constant_p (disp)))
9797 /* Displacement is not constant. */
9799 else if (TARGET_64BIT
9800 && !x86_64_immediate_operand (disp, VOIDmode))
9801 /* Displacement is out of range. */
9805 /* Everything looks valid. */
9809 /* Determine if a given RTX is a valid constant address. */
9812 constant_address_p (rtx x)
9814 return CONSTANT_P (x) && ix86_legitimate_address_p (Pmode, x, 1);
9817 /* Return a unique alias set for the GOT. */
9819 static alias_set_type
9820 ix86_GOT_alias_set (void)
9822 static alias_set_type set = -1;
9824 set = new_alias_set ();
9828 /* Return a legitimate reference for ORIG (an address) using the
9829 register REG. If REG is 0, a new pseudo is generated.
9831 There are two types of references that must be handled:
9833 1. Global data references must load the address from the GOT, via
9834 the PIC reg. An insn is emitted to do this load, and the reg is
9837 2. Static data references, constant pool addresses, and code labels
9838 compute the address as an offset from the GOT, whose base is in
9839 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9840 differentiate them from global data objects. The returned
9841 address is the PIC reg + an unspec constant.
9843 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
9844 reg also appears in the address. */
9847 legitimize_pic_address (rtx orig, rtx reg)
9854 if (TARGET_MACHO && !TARGET_64BIT)
9857 reg = gen_reg_rtx (Pmode);
9858 /* Use the generic Mach-O PIC machinery. */
9859 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9863 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9865 else if (TARGET_64BIT
9866 && ix86_cmodel != CM_SMALL_PIC
9867 && gotoff_operand (addr, Pmode))
9870 /* This symbol may be referenced via a displacement from the PIC
9871 base address (@GOTOFF). */
9873 if (reload_in_progress)
9874 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9875 if (GET_CODE (addr) == CONST)
9876 addr = XEXP (addr, 0);
9877 if (GET_CODE (addr) == PLUS)
9879 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9881 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9884 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9885 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9887 tmpreg = gen_reg_rtx (Pmode);
9890 emit_move_insn (tmpreg, new_rtx);
9894 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9895 tmpreg, 1, OPTAB_DIRECT);
9898 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9900 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9902 /* This symbol may be referenced via a displacement from the PIC
9903 base address (@GOTOFF). */
9905 if (reload_in_progress)
9906 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9907 if (GET_CODE (addr) == CONST)
9908 addr = XEXP (addr, 0);
9909 if (GET_CODE (addr) == PLUS)
9911 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9913 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9916 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9917 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9918 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9922 emit_move_insn (reg, new_rtx);
9926 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9927 /* We can't use @GOTOFF for text labels on VxWorks;
9928 see gotoff_operand. */
9929 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9931 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9933 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9934 return legitimize_dllimport_symbol (addr, true);
9935 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9936 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9937 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9939 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9940 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9944 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9946 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9947 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9948 new_rtx = gen_const_mem (Pmode, new_rtx);
9949 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9952 reg = gen_reg_rtx (Pmode);
9953 /* Use directly gen_movsi, otherwise the address is loaded
9954 into register for CSE. We don't want to CSE this addresses,
9955 instead we CSE addresses from the GOT table, so skip this. */
9956 emit_insn (gen_movsi (reg, new_rtx));
9961 /* This symbol must be referenced via a load from the
9962 Global Offset Table (@GOT). */
9964 if (reload_in_progress)
9965 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9966 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9967 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9969 new_rtx = force_reg (Pmode, new_rtx);
9970 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9971 new_rtx = gen_const_mem (Pmode, new_rtx);
9972 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9975 reg = gen_reg_rtx (Pmode);
9976 emit_move_insn (reg, new_rtx);
9982 if (CONST_INT_P (addr)
9983 && !x86_64_immediate_operand (addr, VOIDmode))
9987 emit_move_insn (reg, addr);
9991 new_rtx = force_reg (Pmode, addr);
9993 else if (GET_CODE (addr) == CONST)
9995 addr = XEXP (addr, 0);
9997 /* We must match stuff we generate before. Assume the only
9998 unspecs that can get here are ours. Not that we could do
9999 anything with them anyway.... */
10000 if (GET_CODE (addr) == UNSPEC
10001 || (GET_CODE (addr) == PLUS
10002 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
10004 gcc_assert (GET_CODE (addr) == PLUS);
10006 if (GET_CODE (addr) == PLUS)
10008 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
10010 /* Check first to see if this is a constant offset from a @GOTOFF
10011 symbol reference. */
10012 if (gotoff_operand (op0, Pmode)
10013 && CONST_INT_P (op1))
10017 if (reload_in_progress)
10018 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10019 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
10021 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
10022 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10023 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10027 emit_move_insn (reg, new_rtx);
10033 if (INTVAL (op1) < -16*1024*1024
10034 || INTVAL (op1) >= 16*1024*1024)
10036 if (!x86_64_immediate_operand (op1, Pmode))
10037 op1 = force_reg (Pmode, op1);
10038 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
10044 base = legitimize_pic_address (XEXP (addr, 0), reg);
10045 new_rtx = legitimize_pic_address (XEXP (addr, 1),
10046 base == reg ? NULL_RTX : reg);
10048 if (CONST_INT_P (new_rtx))
10049 new_rtx = plus_constant (base, INTVAL (new_rtx));
10052 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
10054 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
10055 new_rtx = XEXP (new_rtx, 1);
10057 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
10065 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10068 get_thread_pointer (int to_reg)
10072 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
10076 reg = gen_reg_rtx (Pmode);
10077 insn = gen_rtx_SET (VOIDmode, reg, tp);
10078 insn = emit_insn (insn);
10083 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10084 false if we expect this to be used for a memory address and true if
10085 we expect to load the address into a register. */
10088 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
10090 rtx dest, base, off, pic, tp;
10095 case TLS_MODEL_GLOBAL_DYNAMIC:
10096 dest = gen_reg_rtx (Pmode);
10097 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10099 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10101 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
10104 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
10105 insns = get_insns ();
10108 RTL_CONST_CALL_P (insns) = 1;
10109 emit_libcall_block (insns, dest, rax, x);
10111 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10112 emit_insn (gen_tls_global_dynamic_64 (dest, x));
10114 emit_insn (gen_tls_global_dynamic_32 (dest, x));
10116 if (TARGET_GNU2_TLS)
10118 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
10120 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10124 case TLS_MODEL_LOCAL_DYNAMIC:
10125 base = gen_reg_rtx (Pmode);
10126 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10128 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10130 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
10133 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
10134 insns = get_insns ();
10137 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
10138 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
10139 RTL_CONST_CALL_P (insns) = 1;
10140 emit_libcall_block (insns, base, rax, note);
10142 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10143 emit_insn (gen_tls_local_dynamic_base_64 (base));
10145 emit_insn (gen_tls_local_dynamic_base_32 (base));
10147 if (TARGET_GNU2_TLS)
10149 rtx x = ix86_tls_module_base ();
10151 set_unique_reg_note (get_last_insn (), REG_EQUIV,
10152 gen_rtx_MINUS (Pmode, x, tp));
10155 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
10156 off = gen_rtx_CONST (Pmode, off);
10158 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
10160 if (TARGET_GNU2_TLS)
10162 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
10164 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10169 case TLS_MODEL_INITIAL_EXEC:
10173 type = UNSPEC_GOTNTPOFF;
10177 if (reload_in_progress)
10178 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10179 pic = pic_offset_table_rtx;
10180 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
10182 else if (!TARGET_ANY_GNU_TLS)
10184 pic = gen_reg_rtx (Pmode);
10185 emit_insn (gen_set_got (pic));
10186 type = UNSPEC_GOTTPOFF;
10191 type = UNSPEC_INDNTPOFF;
10194 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
10195 off = gen_rtx_CONST (Pmode, off);
10197 off = gen_rtx_PLUS (Pmode, pic, off);
10198 off = gen_const_mem (Pmode, off);
10199 set_mem_alias_set (off, ix86_GOT_alias_set ());
10201 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10203 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10204 off = force_reg (Pmode, off);
10205 return gen_rtx_PLUS (Pmode, base, off);
10209 base = get_thread_pointer (true);
10210 dest = gen_reg_rtx (Pmode);
10211 emit_insn (gen_subsi3 (dest, base, off));
10215 case TLS_MODEL_LOCAL_EXEC:
10216 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
10217 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10218 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
10219 off = gen_rtx_CONST (Pmode, off);
10221 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10223 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10224 return gen_rtx_PLUS (Pmode, base, off);
10228 base = get_thread_pointer (true);
10229 dest = gen_reg_rtx (Pmode);
10230 emit_insn (gen_subsi3 (dest, base, off));
10235 gcc_unreachable ();
10241 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10244 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
10245 htab_t dllimport_map;
10248 get_dllimport_decl (tree decl)
10250 struct tree_map *h, in;
10253 const char *prefix;
10254 size_t namelen, prefixlen;
10259 if (!dllimport_map)
10260 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
10262 in.hash = htab_hash_pointer (decl);
10263 in.base.from = decl;
10264 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
10265 h = (struct tree_map *) *loc;
10269 *loc = h = GGC_NEW (struct tree_map);
10271 h->base.from = decl;
10272 h->to = to = build_decl (DECL_SOURCE_LOCATION (decl),
10273 VAR_DECL, NULL, ptr_type_node);
10274 DECL_ARTIFICIAL (to) = 1;
10275 DECL_IGNORED_P (to) = 1;
10276 DECL_EXTERNAL (to) = 1;
10277 TREE_READONLY (to) = 1;
10279 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10280 name = targetm.strip_name_encoding (name);
10281 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
10282 ? "*__imp_" : "*__imp__";
10283 namelen = strlen (name);
10284 prefixlen = strlen (prefix);
10285 imp_name = (char *) alloca (namelen + prefixlen + 1);
10286 memcpy (imp_name, prefix, prefixlen);
10287 memcpy (imp_name + prefixlen, name, namelen + 1);
10289 name = ggc_alloc_string (imp_name, namelen + prefixlen);
10290 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
10291 SET_SYMBOL_REF_DECL (rtl, to);
10292 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
10294 rtl = gen_const_mem (Pmode, rtl);
10295 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
10297 SET_DECL_RTL (to, rtl);
10298 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
10303 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10304 true if we require the result be a register. */
10307 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
10312 gcc_assert (SYMBOL_REF_DECL (symbol));
10313 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
10315 x = DECL_RTL (imp_decl);
10317 x = force_reg (Pmode, x);
10321 /* Try machine-dependent ways of modifying an illegitimate address
10322 to be legitimate. If we find one, return the new, valid address.
10323 This macro is used in only one place: `memory_address' in explow.c.
10325 OLDX is the address as it was before break_out_memory_refs was called.
10326 In some cases it is useful to look at this to decide what needs to be done.
10328 It is always safe for this macro to do nothing. It exists to recognize
10329 opportunities to optimize the output.
10331 For the 80386, we handle X+REG by loading X into a register R and
10332 using R+REG. R will go in a general reg and indexing will be used.
10333 However, if REG is a broken-out memory address or multiplication,
10334 nothing needs to be done because REG can certainly go in a general reg.
10336 When -fpic is used, special handling is needed for symbolic references.
10337 See comments by legitimize_pic_address in i386.c for details. */
10340 ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
10341 enum machine_mode mode)
10346 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10348 return legitimize_tls_address (x, (enum tls_model) log, false);
10349 if (GET_CODE (x) == CONST
10350 && GET_CODE (XEXP (x, 0)) == PLUS
10351 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10352 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10354 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10355 (enum tls_model) log, false);
10356 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10359 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10361 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10362 return legitimize_dllimport_symbol (x, true);
10363 if (GET_CODE (x) == CONST
10364 && GET_CODE (XEXP (x, 0)) == PLUS
10365 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10366 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10368 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10369 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10373 if (flag_pic && SYMBOLIC_CONST (x))
10374 return legitimize_pic_address (x, 0);
10376 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10377 if (GET_CODE (x) == ASHIFT
10378 && CONST_INT_P (XEXP (x, 1))
10379 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10382 log = INTVAL (XEXP (x, 1));
10383 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10384 GEN_INT (1 << log));
10387 if (GET_CODE (x) == PLUS)
10389 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10391 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10392 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10393 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10396 log = INTVAL (XEXP (XEXP (x, 0), 1));
10397 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10398 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10399 GEN_INT (1 << log));
10402 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10403 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10404 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10407 log = INTVAL (XEXP (XEXP (x, 1), 1));
10408 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10409 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10410 GEN_INT (1 << log));
10413 /* Put multiply first if it isn't already. */
10414 if (GET_CODE (XEXP (x, 1)) == MULT)
10416 rtx tmp = XEXP (x, 0);
10417 XEXP (x, 0) = XEXP (x, 1);
10422 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10423 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10424 created by virtual register instantiation, register elimination, and
10425 similar optimizations. */
10426 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10429 x = gen_rtx_PLUS (Pmode,
10430 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10431 XEXP (XEXP (x, 1), 0)),
10432 XEXP (XEXP (x, 1), 1));
10436 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10437 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10438 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10439 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10440 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10441 && CONSTANT_P (XEXP (x, 1)))
10444 rtx other = NULL_RTX;
10446 if (CONST_INT_P (XEXP (x, 1)))
10448 constant = XEXP (x, 1);
10449 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10451 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10453 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10454 other = XEXP (x, 1);
10462 x = gen_rtx_PLUS (Pmode,
10463 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10464 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10465 plus_constant (other, INTVAL (constant)));
10469 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10472 if (GET_CODE (XEXP (x, 0)) == MULT)
10475 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10478 if (GET_CODE (XEXP (x, 1)) == MULT)
10481 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10485 && REG_P (XEXP (x, 1))
10486 && REG_P (XEXP (x, 0)))
10489 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10492 x = legitimize_pic_address (x, 0);
10495 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10498 if (REG_P (XEXP (x, 0)))
10500 rtx temp = gen_reg_rtx (Pmode);
10501 rtx val = force_operand (XEXP (x, 1), temp);
10503 emit_move_insn (temp, val);
10505 XEXP (x, 1) = temp;
10509 else if (REG_P (XEXP (x, 1)))
10511 rtx temp = gen_reg_rtx (Pmode);
10512 rtx val = force_operand (XEXP (x, 0), temp);
10514 emit_move_insn (temp, val);
10516 XEXP (x, 0) = temp;
10524 /* Print an integer constant expression in assembler syntax. Addition
10525 and subtraction are the only arithmetic that may appear in these
10526 expressions. FILE is the stdio stream to write to, X is the rtx, and
10527 CODE is the operand print code from the output string. */
10530 output_pic_addr_const (FILE *file, rtx x, int code)
10534 switch (GET_CODE (x))
10537 gcc_assert (flag_pic);
10542 if (! TARGET_MACHO || TARGET_64BIT)
10543 output_addr_const (file, x);
10546 const char *name = XSTR (x, 0);
10548 /* Mark the decl as referenced so that cgraph will
10549 output the function. */
10550 if (SYMBOL_REF_DECL (x))
10551 mark_decl_referenced (SYMBOL_REF_DECL (x));
10554 if (MACHOPIC_INDIRECT
10555 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10556 name = machopic_indirection_name (x, /*stub_p=*/true);
10558 assemble_name (file, name);
10560 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10561 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10562 fputs ("@PLT", file);
10569 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10570 assemble_name (asm_out_file, buf);
10574 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10578 /* This used to output parentheses around the expression,
10579 but that does not work on the 386 (either ATT or BSD assembler). */
10580 output_pic_addr_const (file, XEXP (x, 0), code);
10584 if (GET_MODE (x) == VOIDmode)
10586 /* We can use %d if the number is <32 bits and positive. */
10587 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10588 fprintf (file, "0x%lx%08lx",
10589 (unsigned long) CONST_DOUBLE_HIGH (x),
10590 (unsigned long) CONST_DOUBLE_LOW (x));
10592 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10595 /* We can't handle floating point constants;
10596 PRINT_OPERAND must handle them. */
10597 output_operand_lossage ("floating constant misused");
10601 /* Some assemblers need integer constants to appear first. */
10602 if (CONST_INT_P (XEXP (x, 0)))
10604 output_pic_addr_const (file, XEXP (x, 0), code);
10606 output_pic_addr_const (file, XEXP (x, 1), code);
10610 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10611 output_pic_addr_const (file, XEXP (x, 1), code);
10613 output_pic_addr_const (file, XEXP (x, 0), code);
10619 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10620 output_pic_addr_const (file, XEXP (x, 0), code);
10622 output_pic_addr_const (file, XEXP (x, 1), code);
10624 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10628 gcc_assert (XVECLEN (x, 0) == 1);
10629 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10630 switch (XINT (x, 1))
10633 fputs ("@GOT", file);
10635 case UNSPEC_GOTOFF:
10636 fputs ("@GOTOFF", file);
10638 case UNSPEC_PLTOFF:
10639 fputs ("@PLTOFF", file);
10641 case UNSPEC_GOTPCREL:
10642 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10643 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10645 case UNSPEC_GOTTPOFF:
10646 /* FIXME: This might be @TPOFF in Sun ld too. */
10647 fputs ("@GOTTPOFF", file);
10650 fputs ("@TPOFF", file);
10652 case UNSPEC_NTPOFF:
10654 fputs ("@TPOFF", file);
10656 fputs ("@NTPOFF", file);
10658 case UNSPEC_DTPOFF:
10659 fputs ("@DTPOFF", file);
10661 case UNSPEC_GOTNTPOFF:
10663 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10664 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10666 fputs ("@GOTNTPOFF", file);
10668 case UNSPEC_INDNTPOFF:
10669 fputs ("@INDNTPOFF", file);
10672 case UNSPEC_MACHOPIC_OFFSET:
10674 machopic_output_function_base_name (file);
10678 output_operand_lossage ("invalid UNSPEC as operand");
10684 output_operand_lossage ("invalid expression as operand");
10688 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10689 We need to emit DTP-relative relocations. */
10691 static void ATTRIBUTE_UNUSED
10692 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10694 fputs (ASM_LONG, file);
10695 output_addr_const (file, x);
10696 fputs ("@DTPOFF", file);
10702 fputs (", 0", file);
10705 gcc_unreachable ();
10709 /* Return true if X is a representation of the PIC register. This copes
10710 with calls from ix86_find_base_term, where the register might have
10711 been replaced by a cselib value. */
10714 ix86_pic_register_p (rtx x)
10716 if (GET_CODE (x) == VALUE)
10717 return (pic_offset_table_rtx
10718 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10720 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10723 /* In the name of slightly smaller debug output, and to cater to
10724 general assembler lossage, recognize PIC+GOTOFF and turn it back
10725 into a direct symbol reference.
10727 On Darwin, this is necessary to avoid a crash, because Darwin
10728 has a different PIC label for each routine but the DWARF debugging
10729 information is not associated with any particular routine, so it's
10730 necessary to remove references to the PIC label from RTL stored by
10731 the DWARF output code. */
10734 ix86_delegitimize_address (rtx x)
10736 rtx orig_x = delegitimize_mem_from_attrs (x);
10737 /* reg_addend is NULL or a multiple of some register. */
10738 rtx reg_addend = NULL_RTX;
10739 /* const_addend is NULL or a const_int. */
10740 rtx const_addend = NULL_RTX;
10741 /* This is the result, or NULL. */
10742 rtx result = NULL_RTX;
10751 if (GET_CODE (x) != CONST
10752 || GET_CODE (XEXP (x, 0)) != UNSPEC
10753 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10754 || !MEM_P (orig_x))
10756 return XVECEXP (XEXP (x, 0), 0, 0);
10759 if (GET_CODE (x) != PLUS
10760 || GET_CODE (XEXP (x, 1)) != CONST)
10763 if (ix86_pic_register_p (XEXP (x, 0)))
10764 /* %ebx + GOT/GOTOFF */
10766 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10768 /* %ebx + %reg * scale + GOT/GOTOFF */
10769 reg_addend = XEXP (x, 0);
10770 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10771 reg_addend = XEXP (reg_addend, 1);
10772 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10773 reg_addend = XEXP (reg_addend, 0);
10776 if (!REG_P (reg_addend)
10777 && GET_CODE (reg_addend) != MULT
10778 && GET_CODE (reg_addend) != ASHIFT)
10784 x = XEXP (XEXP (x, 1), 0);
10785 if (GET_CODE (x) == PLUS
10786 && CONST_INT_P (XEXP (x, 1)))
10788 const_addend = XEXP (x, 1);
10792 if (GET_CODE (x) == UNSPEC
10793 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10794 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10795 result = XVECEXP (x, 0, 0);
10797 if (TARGET_MACHO && darwin_local_data_pic (x)
10798 && !MEM_P (orig_x))
10799 result = XVECEXP (x, 0, 0);
10805 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10807 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10811 /* If X is a machine specific address (i.e. a symbol or label being
10812 referenced as a displacement from the GOT implemented using an
10813 UNSPEC), then return the base term. Otherwise return X. */
10816 ix86_find_base_term (rtx x)
10822 if (GET_CODE (x) != CONST)
10824 term = XEXP (x, 0);
10825 if (GET_CODE (term) == PLUS
10826 && (CONST_INT_P (XEXP (term, 1))
10827 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10828 term = XEXP (term, 0);
10829 if (GET_CODE (term) != UNSPEC
10830 || XINT (term, 1) != UNSPEC_GOTPCREL)
10833 return XVECEXP (term, 0, 0);
10836 return ix86_delegitimize_address (x);
10840 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10841 int fp, FILE *file)
10843 const char *suffix;
10845 if (mode == CCFPmode || mode == CCFPUmode)
10847 code = ix86_fp_compare_code_to_integer (code);
10851 code = reverse_condition (code);
10902 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10906 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10907 Those same assemblers have the same but opposite lossage on cmov. */
10908 if (mode == CCmode)
10909 suffix = fp ? "nbe" : "a";
10910 else if (mode == CCCmode)
10913 gcc_unreachable ();
10929 gcc_unreachable ();
10933 gcc_assert (mode == CCmode || mode == CCCmode);
10950 gcc_unreachable ();
10954 /* ??? As above. */
10955 gcc_assert (mode == CCmode || mode == CCCmode);
10956 suffix = fp ? "nb" : "ae";
10959 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10963 /* ??? As above. */
10964 if (mode == CCmode)
10966 else if (mode == CCCmode)
10967 suffix = fp ? "nb" : "ae";
10969 gcc_unreachable ();
10972 suffix = fp ? "u" : "p";
10975 suffix = fp ? "nu" : "np";
10978 gcc_unreachable ();
10980 fputs (suffix, file);
10983 /* Print the name of register X to FILE based on its machine mode and number.
10984 If CODE is 'w', pretend the mode is HImode.
10985 If CODE is 'b', pretend the mode is QImode.
10986 If CODE is 'k', pretend the mode is SImode.
10987 If CODE is 'q', pretend the mode is DImode.
10988 If CODE is 'x', pretend the mode is V4SFmode.
10989 If CODE is 't', pretend the mode is V8SFmode.
10990 If CODE is 'h', pretend the reg is the 'high' byte register.
10991 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10992 If CODE is 'd', duplicate the operand for AVX instruction.
10996 print_reg (rtx x, int code, FILE *file)
10999 bool duplicated = code == 'd' && TARGET_AVX;
11001 gcc_assert (x == pc_rtx
11002 || (REGNO (x) != ARG_POINTER_REGNUM
11003 && REGNO (x) != FRAME_POINTER_REGNUM
11004 && REGNO (x) != FLAGS_REG
11005 && REGNO (x) != FPSR_REG
11006 && REGNO (x) != FPCR_REG));
11008 if (ASSEMBLER_DIALECT == ASM_ATT)
11013 gcc_assert (TARGET_64BIT);
11014 fputs ("rip", file);
11018 if (code == 'w' || MMX_REG_P (x))
11020 else if (code == 'b')
11022 else if (code == 'k')
11024 else if (code == 'q')
11026 else if (code == 'y')
11028 else if (code == 'h')
11030 else if (code == 'x')
11032 else if (code == 't')
11035 code = GET_MODE_SIZE (GET_MODE (x));
11037 /* Irritatingly, AMD extended registers use different naming convention
11038 from the normal registers. */
11039 if (REX_INT_REG_P (x))
11041 gcc_assert (TARGET_64BIT);
11045 error ("extended registers have no high halves");
11048 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
11051 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
11054 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
11057 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
11060 error ("unsupported operand size for extended register");
11070 if (STACK_TOP_P (x))
11079 if (! ANY_FP_REG_P (x))
11080 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
11085 reg = hi_reg_name[REGNO (x)];
11088 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
11090 reg = qi_reg_name[REGNO (x)];
11093 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
11095 reg = qi_high_reg_name[REGNO (x)];
11100 gcc_assert (!duplicated);
11102 fputs (hi_reg_name[REGNO (x)] + 1, file);
11107 gcc_unreachable ();
11113 if (ASSEMBLER_DIALECT == ASM_ATT)
11114 fprintf (file, ", %%%s", reg);
11116 fprintf (file, ", %s", reg);
11120 /* Locate some local-dynamic symbol still in use by this function
11121 so that we can print its name in some tls_local_dynamic_base
11125 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11129 if (GET_CODE (x) == SYMBOL_REF
11130 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11132 cfun->machine->some_ld_name = XSTR (x, 0);
11139 static const char *
11140 get_some_local_dynamic_name (void)
11144 if (cfun->machine->some_ld_name)
11145 return cfun->machine->some_ld_name;
11147 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11149 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
11150 return cfun->machine->some_ld_name;
11152 gcc_unreachable ();
11155 /* Meaning of CODE:
11156 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11157 C -- print opcode suffix for set/cmov insn.
11158 c -- like C, but print reversed condition
11159 E,e -- likewise, but for compare-and-branch fused insn.
11160 F,f -- likewise, but for floating-point.
11161 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11163 R -- print the prefix for register names.
11164 z -- print the opcode suffix for the size of the current operand.
11165 Z -- likewise, with special suffixes for x87 instructions.
11166 * -- print a star (in certain assembler syntax)
11167 A -- print an absolute memory reference.
11168 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11169 s -- print a shift double count, followed by the assemblers argument
11171 b -- print the QImode name of the register for the indicated operand.
11172 %b0 would print %al if operands[0] is reg 0.
11173 w -- likewise, print the HImode name of the register.
11174 k -- likewise, print the SImode name of the register.
11175 q -- likewise, print the DImode name of the register.
11176 x -- likewise, print the V4SFmode name of the register.
11177 t -- likewise, print the V8SFmode name of the register.
11178 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11179 y -- print "st(0)" instead of "st" as a register.
11180 d -- print duplicated register operand for AVX instruction.
11181 D -- print condition for SSE cmp instruction.
11182 P -- if PIC, print an @PLT suffix.
11183 X -- don't print any sort of PIC '@' suffix for a symbol.
11184 & -- print some in-use local-dynamic symbol name.
11185 H -- print a memory address offset by 8; used for sse high-parts
11186 + -- print a branch hint as 'cs' or 'ds' prefix
11187 ; -- print a semicolon (after prefixes due to bug in older gas).
11191 print_operand (FILE *file, rtx x, int code)
11198 if (ASSEMBLER_DIALECT == ASM_ATT)
11203 assemble_name (file, get_some_local_dynamic_name ());
11207 switch (ASSEMBLER_DIALECT)
11214 /* Intel syntax. For absolute addresses, registers should not
11215 be surrounded by braces. */
11219 PRINT_OPERAND (file, x, 0);
11226 gcc_unreachable ();
11229 PRINT_OPERAND (file, x, 0);
11234 if (ASSEMBLER_DIALECT == ASM_ATT)
11239 if (ASSEMBLER_DIALECT == ASM_ATT)
11244 if (ASSEMBLER_DIALECT == ASM_ATT)
11249 if (ASSEMBLER_DIALECT == ASM_ATT)
11254 if (ASSEMBLER_DIALECT == ASM_ATT)
11259 if (ASSEMBLER_DIALECT == ASM_ATT)
11264 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11266 /* Opcodes don't get size suffixes if using Intel opcodes. */
11267 if (ASSEMBLER_DIALECT == ASM_INTEL)
11270 switch (GET_MODE_SIZE (GET_MODE (x)))
11289 output_operand_lossage
11290 ("invalid operand size for operand code '%c'", code);
11295 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11297 (0, "non-integer operand used with operand code '%c'", code);
11301 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11302 if (ASSEMBLER_DIALECT == ASM_INTEL)
11305 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11307 switch (GET_MODE_SIZE (GET_MODE (x)))
11310 #ifdef HAVE_AS_IX86_FILDS
11320 #ifdef HAVE_AS_IX86_FILDQ
11323 fputs ("ll", file);
11331 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11333 /* 387 opcodes don't get size suffixes
11334 if the operands are registers. */
11335 if (STACK_REG_P (x))
11338 switch (GET_MODE_SIZE (GET_MODE (x)))
11359 output_operand_lossage
11360 ("invalid operand type used with operand code '%c'", code);
11364 output_operand_lossage
11365 ("invalid operand size for operand code '%c'", code);
11382 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11384 PRINT_OPERAND (file, x, 0);
11385 fputs (", ", file);
11390 /* Little bit of braindamage here. The SSE compare instructions
11391 does use completely different names for the comparisons that the
11392 fp conditional moves. */
11395 switch (GET_CODE (x))
11398 fputs ("eq", file);
11401 fputs ("eq_us", file);
11404 fputs ("lt", file);
11407 fputs ("nge", file);
11410 fputs ("le", file);
11413 fputs ("ngt", file);
11416 fputs ("unord", file);
11419 fputs ("neq", file);
11422 fputs ("neq_oq", file);
11425 fputs ("ge", file);
11428 fputs ("nlt", file);
11431 fputs ("gt", file);
11434 fputs ("nle", file);
11437 fputs ("ord", file);
11440 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11446 switch (GET_CODE (x))
11450 fputs ("eq", file);
11454 fputs ("lt", file);
11458 fputs ("le", file);
11461 fputs ("unord", file);
11465 fputs ("neq", file);
11469 fputs ("nlt", file);
11473 fputs ("nle", file);
11476 fputs ("ord", file);
11479 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11485 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11486 if (ASSEMBLER_DIALECT == ASM_ATT)
11488 switch (GET_MODE (x))
11490 case HImode: putc ('w', file); break;
11492 case SFmode: putc ('l', file); break;
11494 case DFmode: putc ('q', file); break;
11495 default: gcc_unreachable ();
11502 if (!COMPARISON_P (x))
11504 output_operand_lossage ("operand is neither a constant nor a "
11505 "condition code, invalid operand code "
11509 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11512 if (!COMPARISON_P (x))
11514 output_operand_lossage ("operand is neither a constant nor a "
11515 "condition code, invalid operand code "
11519 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11520 if (ASSEMBLER_DIALECT == ASM_ATT)
11523 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11526 /* Like above, but reverse condition */
11528 /* Check to see if argument to %c is really a constant
11529 and not a condition code which needs to be reversed. */
11530 if (!COMPARISON_P (x))
11532 output_operand_lossage ("operand is neither a constant nor a "
11533 "condition code, invalid operand "
11537 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11540 if (!COMPARISON_P (x))
11542 output_operand_lossage ("operand is neither a constant nor a "
11543 "condition code, invalid operand "
11547 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11548 if (ASSEMBLER_DIALECT == ASM_ATT)
11551 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11555 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11559 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11563 /* It doesn't actually matter what mode we use here, as we're
11564 only going to use this for printing. */
11565 x = adjust_address_nv (x, DImode, 8);
11573 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11576 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11579 int pred_val = INTVAL (XEXP (x, 0));
11581 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11582 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11584 int taken = pred_val > REG_BR_PROB_BASE / 2;
11585 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11587 /* Emit hints only in the case default branch prediction
11588 heuristics would fail. */
11589 if (taken != cputaken)
11591 /* We use 3e (DS) prefix for taken branches and
11592 2e (CS) prefix for not taken branches. */
11594 fputs ("ds ; ", file);
11596 fputs ("cs ; ", file);
11605 fputs (" ; ", file);
11612 output_operand_lossage ("invalid operand code '%c'", code);
11617 print_reg (x, code, file);
11619 else if (MEM_P (x))
11621 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11622 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11623 && GET_MODE (x) != BLKmode)
11626 switch (GET_MODE_SIZE (GET_MODE (x)))
11628 case 1: size = "BYTE"; break;
11629 case 2: size = "WORD"; break;
11630 case 4: size = "DWORD"; break;
11631 case 8: size = "QWORD"; break;
11632 case 12: size = "XWORD"; break;
11634 if (GET_MODE (x) == XFmode)
11640 gcc_unreachable ();
11643 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11646 else if (code == 'w')
11648 else if (code == 'k')
11651 fputs (size, file);
11652 fputs (" PTR ", file);
11656 /* Avoid (%rip) for call operands. */
11657 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11658 && !CONST_INT_P (x))
11659 output_addr_const (file, x);
11660 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11661 output_operand_lossage ("invalid constraints for operand");
11663 output_address (x);
11666 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11671 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11672 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11674 if (ASSEMBLER_DIALECT == ASM_ATT)
11676 fprintf (file, "0x%08lx", (long unsigned int) l);
11679 /* These float cases don't actually occur as immediate operands. */
11680 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11684 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11685 fputs (dstr, file);
11688 else if (GET_CODE (x) == CONST_DOUBLE
11689 && GET_MODE (x) == XFmode)
11693 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11694 fputs (dstr, file);
11699 /* We have patterns that allow zero sets of memory, for instance.
11700 In 64-bit mode, we should probably support all 8-byte vectors,
11701 since we can in fact encode that into an immediate. */
11702 if (GET_CODE (x) == CONST_VECTOR)
11704 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11710 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11712 if (ASSEMBLER_DIALECT == ASM_ATT)
11715 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11716 || GET_CODE (x) == LABEL_REF)
11718 if (ASSEMBLER_DIALECT == ASM_ATT)
11721 fputs ("OFFSET FLAT:", file);
11724 if (CONST_INT_P (x))
11725 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11727 output_pic_addr_const (file, x, code);
11729 output_addr_const (file, x);
11733 /* Print a memory operand whose address is ADDR. */
11736 print_operand_address (FILE *file, rtx addr)
11738 struct ix86_address parts;
11739 rtx base, index, disp;
11741 int ok = ix86_decompose_address (addr, &parts);
11746 index = parts.index;
11748 scale = parts.scale;
11756 if (ASSEMBLER_DIALECT == ASM_ATT)
11758 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11761 gcc_unreachable ();
11764 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11765 if (TARGET_64BIT && !base && !index)
11769 if (GET_CODE (disp) == CONST
11770 && GET_CODE (XEXP (disp, 0)) == PLUS
11771 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11772 symbol = XEXP (XEXP (disp, 0), 0);
11774 if (GET_CODE (symbol) == LABEL_REF
11775 || (GET_CODE (symbol) == SYMBOL_REF
11776 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11779 if (!base && !index)
11781 /* Displacement only requires special attention. */
11783 if (CONST_INT_P (disp))
11785 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11786 fputs ("ds:", file);
11787 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11790 output_pic_addr_const (file, disp, 0);
11792 output_addr_const (file, disp);
11796 if (ASSEMBLER_DIALECT == ASM_ATT)
11801 output_pic_addr_const (file, disp, 0);
11802 else if (GET_CODE (disp) == LABEL_REF)
11803 output_asm_label (disp);
11805 output_addr_const (file, disp);
11810 print_reg (base, 0, file);
11814 print_reg (index, 0, file);
11816 fprintf (file, ",%d", scale);
11822 rtx offset = NULL_RTX;
11826 /* Pull out the offset of a symbol; print any symbol itself. */
11827 if (GET_CODE (disp) == CONST
11828 && GET_CODE (XEXP (disp, 0)) == PLUS
11829 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11831 offset = XEXP (XEXP (disp, 0), 1);
11832 disp = gen_rtx_CONST (VOIDmode,
11833 XEXP (XEXP (disp, 0), 0));
11837 output_pic_addr_const (file, disp, 0);
11838 else if (GET_CODE (disp) == LABEL_REF)
11839 output_asm_label (disp);
11840 else if (CONST_INT_P (disp))
11843 output_addr_const (file, disp);
11849 print_reg (base, 0, file);
11852 if (INTVAL (offset) >= 0)
11854 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11858 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11865 print_reg (index, 0, file);
11867 fprintf (file, "*%d", scale);
11875 output_addr_const_extra (FILE *file, rtx x)
11879 if (GET_CODE (x) != UNSPEC)
11882 op = XVECEXP (x, 0, 0);
11883 switch (XINT (x, 1))
11885 case UNSPEC_GOTTPOFF:
11886 output_addr_const (file, op);
11887 /* FIXME: This might be @TPOFF in Sun ld. */
11888 fputs ("@GOTTPOFF", file);
11891 output_addr_const (file, op);
11892 fputs ("@TPOFF", file);
11894 case UNSPEC_NTPOFF:
11895 output_addr_const (file, op);
11897 fputs ("@TPOFF", file);
11899 fputs ("@NTPOFF", file);
11901 case UNSPEC_DTPOFF:
11902 output_addr_const (file, op);
11903 fputs ("@DTPOFF", file);
11905 case UNSPEC_GOTNTPOFF:
11906 output_addr_const (file, op);
11908 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11909 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11911 fputs ("@GOTNTPOFF", file);
11913 case UNSPEC_INDNTPOFF:
11914 output_addr_const (file, op);
11915 fputs ("@INDNTPOFF", file);
11918 case UNSPEC_MACHOPIC_OFFSET:
11919 output_addr_const (file, op);
11921 machopic_output_function_base_name (file);
11932 /* Split one or more DImode RTL references into pairs of SImode
11933 references. The RTL can be REG, offsettable MEM, integer constant, or
11934 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11935 split and "num" is its length. lo_half and hi_half are output arrays
11936 that parallel "operands". */
11939 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11943 rtx op = operands[num];
11945 /* simplify_subreg refuse to split volatile memory addresses,
11946 but we still have to handle it. */
11949 lo_half[num] = adjust_address (op, SImode, 0);
11950 hi_half[num] = adjust_address (op, SImode, 4);
11954 lo_half[num] = simplify_gen_subreg (SImode, op,
11955 GET_MODE (op) == VOIDmode
11956 ? DImode : GET_MODE (op), 0);
11957 hi_half[num] = simplify_gen_subreg (SImode, op,
11958 GET_MODE (op) == VOIDmode
11959 ? DImode : GET_MODE (op), 4);
11963 /* Split one or more TImode RTL references into pairs of DImode
11964 references. The RTL can be REG, offsettable MEM, integer constant, or
11965 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11966 split and "num" is its length. lo_half and hi_half are output arrays
11967 that parallel "operands". */
11970 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11974 rtx op = operands[num];
11976 /* simplify_subreg refuse to split volatile memory addresses, but we
11977 still have to handle it. */
11980 lo_half[num] = adjust_address (op, DImode, 0);
11981 hi_half[num] = adjust_address (op, DImode, 8);
11985 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11986 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11991 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11992 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11993 is the expression of the binary operation. The output may either be
11994 emitted here, or returned to the caller, like all output_* functions.
11996 There is no guarantee that the operands are the same mode, as they
11997 might be within FLOAT or FLOAT_EXTEND expressions. */
11999 #ifndef SYSV386_COMPAT
12000 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12001 wants to fix the assemblers because that causes incompatibility
12002 with gcc. No-one wants to fix gcc because that causes
12003 incompatibility with assemblers... You can use the option of
12004 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12005 #define SYSV386_COMPAT 1
12009 output_387_binary_op (rtx insn, rtx *operands)
12011 static char buf[40];
12014 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
12016 #ifdef ENABLE_CHECKING
12017 /* Even if we do not want to check the inputs, this documents input
12018 constraints. Which helps in understanding the following code. */
12019 if (STACK_REG_P (operands[0])
12020 && ((REG_P (operands[1])
12021 && REGNO (operands[0]) == REGNO (operands[1])
12022 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
12023 || (REG_P (operands[2])
12024 && REGNO (operands[0]) == REGNO (operands[2])
12025 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
12026 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
12029 gcc_assert (is_sse);
12032 switch (GET_CODE (operands[3]))
12035 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12036 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12044 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12045 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12053 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12054 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12062 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12063 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12071 gcc_unreachable ();
12078 strcpy (buf, ssep);
12079 if (GET_MODE (operands[0]) == SFmode)
12080 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
12082 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
12086 strcpy (buf, ssep + 1);
12087 if (GET_MODE (operands[0]) == SFmode)
12088 strcat (buf, "ss\t{%2, %0|%0, %2}");
12090 strcat (buf, "sd\t{%2, %0|%0, %2}");
12096 switch (GET_CODE (operands[3]))
12100 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
12102 rtx temp = operands[2];
12103 operands[2] = operands[1];
12104 operands[1] = temp;
12107 /* know operands[0] == operands[1]. */
12109 if (MEM_P (operands[2]))
12115 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12117 if (STACK_TOP_P (operands[0]))
12118 /* How is it that we are storing to a dead operand[2]?
12119 Well, presumably operands[1] is dead too. We can't
12120 store the result to st(0) as st(0) gets popped on this
12121 instruction. Instead store to operands[2] (which I
12122 think has to be st(1)). st(1) will be popped later.
12123 gcc <= 2.8.1 didn't have this check and generated
12124 assembly code that the Unixware assembler rejected. */
12125 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12127 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12131 if (STACK_TOP_P (operands[0]))
12132 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12134 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12139 if (MEM_P (operands[1]))
12145 if (MEM_P (operands[2]))
12151 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12154 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12155 derived assemblers, confusingly reverse the direction of
12156 the operation for fsub{r} and fdiv{r} when the
12157 destination register is not st(0). The Intel assembler
12158 doesn't have this brain damage. Read !SYSV386_COMPAT to
12159 figure out what the hardware really does. */
12160 if (STACK_TOP_P (operands[0]))
12161 p = "{p\t%0, %2|rp\t%2, %0}";
12163 p = "{rp\t%2, %0|p\t%0, %2}";
12165 if (STACK_TOP_P (operands[0]))
12166 /* As above for fmul/fadd, we can't store to st(0). */
12167 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12169 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12174 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
12177 if (STACK_TOP_P (operands[0]))
12178 p = "{rp\t%0, %1|p\t%1, %0}";
12180 p = "{p\t%1, %0|rp\t%0, %1}";
12182 if (STACK_TOP_P (operands[0]))
12183 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
12185 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
12190 if (STACK_TOP_P (operands[0]))
12192 if (STACK_TOP_P (operands[1]))
12193 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12195 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
12198 else if (STACK_TOP_P (operands[1]))
12201 p = "{\t%1, %0|r\t%0, %1}";
12203 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
12209 p = "{r\t%2, %0|\t%0, %2}";
12211 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12217 gcc_unreachable ();
12224 /* Return needed mode for entity in optimize_mode_switching pass. */
12227 ix86_mode_needed (int entity, rtx insn)
12229 enum attr_i387_cw mode;
12231 /* The mode UNINITIALIZED is used to store control word after a
12232 function call or ASM pattern. The mode ANY specify that function
12233 has no requirements on the control word and make no changes in the
12234 bits we are interested in. */
12237 || (NONJUMP_INSN_P (insn)
12238 && (asm_noperands (PATTERN (insn)) >= 0
12239 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
12240 return I387_CW_UNINITIALIZED;
12242 if (recog_memoized (insn) < 0)
12243 return I387_CW_ANY;
12245 mode = get_attr_i387_cw (insn);
12250 if (mode == I387_CW_TRUNC)
12255 if (mode == I387_CW_FLOOR)
12260 if (mode == I387_CW_CEIL)
12265 if (mode == I387_CW_MASK_PM)
12270 gcc_unreachable ();
12273 return I387_CW_ANY;
12276 /* Output code to initialize control word copies used by trunc?f?i and
12277 rounding patterns. CURRENT_MODE is set to current control word,
12278 while NEW_MODE is set to new control word. */
12281 emit_i387_cw_initialization (int mode)
12283 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
12286 enum ix86_stack_slot slot;
12288 rtx reg = gen_reg_rtx (HImode);
12290 emit_insn (gen_x86_fnstcw_1 (stored_mode));
12291 emit_move_insn (reg, copy_rtx (stored_mode));
12293 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
12294 || optimize_function_for_size_p (cfun))
12298 case I387_CW_TRUNC:
12299 /* round toward zero (truncate) */
12300 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
12301 slot = SLOT_CW_TRUNC;
12304 case I387_CW_FLOOR:
12305 /* round down toward -oo */
12306 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12307 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
12308 slot = SLOT_CW_FLOOR;
12312 /* round up toward +oo */
12313 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12314 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
12315 slot = SLOT_CW_CEIL;
12318 case I387_CW_MASK_PM:
12319 /* mask precision exception for nearbyint() */
12320 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12321 slot = SLOT_CW_MASK_PM;
12325 gcc_unreachable ();
12332 case I387_CW_TRUNC:
12333 /* round toward zero (truncate) */
12334 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12335 slot = SLOT_CW_TRUNC;
12338 case I387_CW_FLOOR:
12339 /* round down toward -oo */
12340 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12341 slot = SLOT_CW_FLOOR;
12345 /* round up toward +oo */
12346 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12347 slot = SLOT_CW_CEIL;
12350 case I387_CW_MASK_PM:
12351 /* mask precision exception for nearbyint() */
12352 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12353 slot = SLOT_CW_MASK_PM;
12357 gcc_unreachable ();
12361 gcc_assert (slot < MAX_386_STACK_LOCALS);
12363 new_mode = assign_386_stack_local (HImode, slot);
12364 emit_move_insn (new_mode, reg);
12367 /* Output code for INSN to convert a float to a signed int. OPERANDS
12368 are the insn operands. The output may be [HSD]Imode and the input
12369 operand may be [SDX]Fmode. */
12372 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12374 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12375 int dimode_p = GET_MODE (operands[0]) == DImode;
12376 int round_mode = get_attr_i387_cw (insn);
12378 /* Jump through a hoop or two for DImode, since the hardware has no
12379 non-popping instruction. We used to do this a different way, but
12380 that was somewhat fragile and broke with post-reload splitters. */
12381 if ((dimode_p || fisttp) && !stack_top_dies)
12382 output_asm_insn ("fld\t%y1", operands);
12384 gcc_assert (STACK_TOP_P (operands[1]));
12385 gcc_assert (MEM_P (operands[0]));
12386 gcc_assert (GET_MODE (operands[1]) != TFmode);
12389 output_asm_insn ("fisttp%Z0\t%0", operands);
12392 if (round_mode != I387_CW_ANY)
12393 output_asm_insn ("fldcw\t%3", operands);
12394 if (stack_top_dies || dimode_p)
12395 output_asm_insn ("fistp%Z0\t%0", operands);
12397 output_asm_insn ("fist%Z0\t%0", operands);
12398 if (round_mode != I387_CW_ANY)
12399 output_asm_insn ("fldcw\t%2", operands);
12405 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12406 have the values zero or one, indicates the ffreep insn's operand
12407 from the OPERANDS array. */
12409 static const char *
12410 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12412 if (TARGET_USE_FFREEP)
12413 #ifdef HAVE_AS_IX86_FFREEP
12414 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12417 static char retval[32];
12418 int regno = REGNO (operands[opno]);
12420 gcc_assert (FP_REGNO_P (regno));
12422 regno -= FIRST_STACK_REG;
12424 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
12429 return opno ? "fstp\t%y1" : "fstp\t%y0";
12433 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12434 should be used. UNORDERED_P is true when fucom should be used. */
12437 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12439 int stack_top_dies;
12440 rtx cmp_op0, cmp_op1;
12441 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12445 cmp_op0 = operands[0];
12446 cmp_op1 = operands[1];
12450 cmp_op0 = operands[1];
12451 cmp_op1 = operands[2];
12456 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12457 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12458 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12459 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12461 if (GET_MODE (operands[0]) == SFmode)
12463 return &ucomiss[TARGET_AVX ? 0 : 1];
12465 return &comiss[TARGET_AVX ? 0 : 1];
12468 return &ucomisd[TARGET_AVX ? 0 : 1];
12470 return &comisd[TARGET_AVX ? 0 : 1];
12473 gcc_assert (STACK_TOP_P (cmp_op0));
12475 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12477 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12479 if (stack_top_dies)
12481 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12482 return output_387_ffreep (operands, 1);
12485 return "ftst\n\tfnstsw\t%0";
12488 if (STACK_REG_P (cmp_op1)
12490 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12491 && REGNO (cmp_op1) != FIRST_STACK_REG)
12493 /* If both the top of the 387 stack dies, and the other operand
12494 is also a stack register that dies, then this must be a
12495 `fcompp' float compare */
12499 /* There is no double popping fcomi variant. Fortunately,
12500 eflags is immune from the fstp's cc clobbering. */
12502 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12504 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12505 return output_387_ffreep (operands, 0);
12510 return "fucompp\n\tfnstsw\t%0";
12512 return "fcompp\n\tfnstsw\t%0";
12517 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12519 static const char * const alt[16] =
12521 "fcom%Z2\t%y2\n\tfnstsw\t%0",
12522 "fcomp%Z2\t%y2\n\tfnstsw\t%0",
12523 "fucom%Z2\t%y2\n\tfnstsw\t%0",
12524 "fucomp%Z2\t%y2\n\tfnstsw\t%0",
12526 "ficom%Z2\t%y2\n\tfnstsw\t%0",
12527 "ficomp%Z2\t%y2\n\tfnstsw\t%0",
12531 "fcomi\t{%y1, %0|%0, %y1}",
12532 "fcomip\t{%y1, %0|%0, %y1}",
12533 "fucomi\t{%y1, %0|%0, %y1}",
12534 "fucomip\t{%y1, %0|%0, %y1}",
12545 mask = eflags_p << 3;
12546 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12547 mask |= unordered_p << 1;
12548 mask |= stack_top_dies;
12550 gcc_assert (mask < 16);
12559 ix86_output_addr_vec_elt (FILE *file, int value)
12561 const char *directive = ASM_LONG;
12565 directive = ASM_QUAD;
12567 gcc_assert (!TARGET_64BIT);
12570 fprintf (file, "%s" LPREFIX "%d\n", directive, value);
12574 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12576 const char *directive = ASM_LONG;
12579 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12580 directive = ASM_QUAD;
12582 gcc_assert (!TARGET_64BIT);
12584 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12585 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12586 fprintf (file, "%s" LPREFIX "%d-" LPREFIX "%d\n",
12587 directive, value, rel);
12588 else if (HAVE_AS_GOTOFF_IN_DATA)
12589 fprintf (file, ASM_LONG LPREFIX "%d@GOTOFF\n", value);
12591 else if (TARGET_MACHO)
12593 fprintf (file, ASM_LONG LPREFIX "%d-", value);
12594 machopic_output_function_base_name (file);
12599 asm_fprintf (file, ASM_LONG "%U%s+[.-" LPREFIX "%d]\n",
12600 GOT_SYMBOL_NAME, value);
12603 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12607 ix86_expand_clear (rtx dest)
12611 /* We play register width games, which are only valid after reload. */
12612 gcc_assert (reload_completed);
12614 /* Avoid HImode and its attendant prefix byte. */
12615 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12616 dest = gen_rtx_REG (SImode, REGNO (dest));
12617 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12619 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12620 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12622 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12623 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12629 /* X is an unchanging MEM. If it is a constant pool reference, return
12630 the constant pool rtx, else NULL. */
12633 maybe_get_pool_constant (rtx x)
12635 x = ix86_delegitimize_address (XEXP (x, 0));
12637 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12638 return get_pool_constant (x);
12644 ix86_expand_move (enum machine_mode mode, rtx operands[])
12647 enum tls_model model;
12652 if (GET_CODE (op1) == SYMBOL_REF)
12654 model = SYMBOL_REF_TLS_MODEL (op1);
12657 op1 = legitimize_tls_address (op1, model, true);
12658 op1 = force_operand (op1, op0);
12662 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12663 && SYMBOL_REF_DLLIMPORT_P (op1))
12664 op1 = legitimize_dllimport_symbol (op1, false);
12666 else if (GET_CODE (op1) == CONST
12667 && GET_CODE (XEXP (op1, 0)) == PLUS
12668 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12670 rtx addend = XEXP (XEXP (op1, 0), 1);
12671 rtx symbol = XEXP (XEXP (op1, 0), 0);
12674 model = SYMBOL_REF_TLS_MODEL (symbol);
12676 tmp = legitimize_tls_address (symbol, model, true);
12677 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12678 && SYMBOL_REF_DLLIMPORT_P (symbol))
12679 tmp = legitimize_dllimport_symbol (symbol, true);
12683 tmp = force_operand (tmp, NULL);
12684 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12685 op0, 1, OPTAB_DIRECT);
12691 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12693 if (TARGET_MACHO && !TARGET_64BIT)
12698 rtx temp = ((reload_in_progress
12699 || ((op0 && REG_P (op0))
12701 ? op0 : gen_reg_rtx (Pmode));
12702 op1 = machopic_indirect_data_reference (op1, temp);
12703 op1 = machopic_legitimize_pic_address (op1, mode,
12704 temp == op1 ? 0 : temp);
12706 else if (MACHOPIC_INDIRECT)
12707 op1 = machopic_indirect_data_reference (op1, 0);
12715 op1 = force_reg (Pmode, op1);
12716 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12718 rtx reg = can_create_pseudo_p () ? NULL_RTX : op0;
12719 op1 = legitimize_pic_address (op1, reg);
12728 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12729 || !push_operand (op0, mode))
12731 op1 = force_reg (mode, op1);
12733 if (push_operand (op0, mode)
12734 && ! general_no_elim_operand (op1, mode))
12735 op1 = copy_to_mode_reg (mode, op1);
12737 /* Force large constants in 64bit compilation into register
12738 to get them CSEed. */
12739 if (can_create_pseudo_p ()
12740 && (mode == DImode) && TARGET_64BIT
12741 && immediate_operand (op1, mode)
12742 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12743 && !register_operand (op0, mode)
12745 op1 = copy_to_mode_reg (mode, op1);
12747 if (can_create_pseudo_p ()
12748 && FLOAT_MODE_P (mode)
12749 && GET_CODE (op1) == CONST_DOUBLE)
12751 /* If we are loading a floating point constant to a register,
12752 force the value to memory now, since we'll get better code
12753 out the back end. */
12755 op1 = validize_mem (force_const_mem (mode, op1));
12756 if (!register_operand (op0, mode))
12758 rtx temp = gen_reg_rtx (mode);
12759 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12760 emit_move_insn (op0, temp);
12766 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12770 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12772 rtx op0 = operands[0], op1 = operands[1];
12773 unsigned int align = GET_MODE_ALIGNMENT (mode);
12775 /* Force constants other than zero into memory. We do not know how
12776 the instructions used to build constants modify the upper 64 bits
12777 of the register, once we have that information we may be able
12778 to handle some of them more efficiently. */
12779 if (can_create_pseudo_p ()
12780 && register_operand (op0, mode)
12781 && (CONSTANT_P (op1)
12782 || (GET_CODE (op1) == SUBREG
12783 && CONSTANT_P (SUBREG_REG (op1))))
12784 && !standard_sse_constant_p (op1))
12785 op1 = validize_mem (force_const_mem (mode, op1));
12787 /* We need to check memory alignment for SSE mode since attribute
12788 can make operands unaligned. */
12789 if (can_create_pseudo_p ()
12790 && SSE_REG_MODE_P (mode)
12791 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12792 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12796 /* ix86_expand_vector_move_misalign() does not like constants ... */
12797 if (CONSTANT_P (op1)
12798 || (GET_CODE (op1) == SUBREG
12799 && CONSTANT_P (SUBREG_REG (op1))))
12800 op1 = validize_mem (force_const_mem (mode, op1));
12802 /* ... nor both arguments in memory. */
12803 if (!register_operand (op0, mode)
12804 && !register_operand (op1, mode))
12805 op1 = force_reg (mode, op1);
12807 tmp[0] = op0; tmp[1] = op1;
12808 ix86_expand_vector_move_misalign (mode, tmp);
12812 /* Make operand1 a register if it isn't already. */
12813 if (can_create_pseudo_p ()
12814 && !register_operand (op0, mode)
12815 && !register_operand (op1, mode))
12817 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12821 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12824 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12825 straight to ix86_expand_vector_move. */
12826 /* Code generation for scalar reg-reg moves of single and double precision data:
12827 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12831 if (x86_sse_partial_reg_dependency == true)
12836 Code generation for scalar loads of double precision data:
12837 if (x86_sse_split_regs == true)
12838 movlpd mem, reg (gas syntax)
12842 Code generation for unaligned packed loads of single precision data
12843 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12844 if (x86_sse_unaligned_move_optimal)
12847 if (x86_sse_partial_reg_dependency == true)
12859 Code generation for unaligned packed loads of double precision data
12860 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12861 if (x86_sse_unaligned_move_optimal)
12864 if (x86_sse_split_regs == true)
12877 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12886 switch (GET_MODE_CLASS (mode))
12888 case MODE_VECTOR_INT:
12890 switch (GET_MODE_SIZE (mode))
12893 op0 = gen_lowpart (V16QImode, op0);
12894 op1 = gen_lowpart (V16QImode, op1);
12895 emit_insn (gen_avx_movdqu (op0, op1));
12898 op0 = gen_lowpart (V32QImode, op0);
12899 op1 = gen_lowpart (V32QImode, op1);
12900 emit_insn (gen_avx_movdqu256 (op0, op1));
12903 gcc_unreachable ();
12906 case MODE_VECTOR_FLOAT:
12907 op0 = gen_lowpart (mode, op0);
12908 op1 = gen_lowpart (mode, op1);
12913 emit_insn (gen_avx_movups (op0, op1));
12916 emit_insn (gen_avx_movups256 (op0, op1));
12919 emit_insn (gen_avx_movupd (op0, op1));
12922 emit_insn (gen_avx_movupd256 (op0, op1));
12925 gcc_unreachable ();
12930 gcc_unreachable ();
12938 /* If we're optimizing for size, movups is the smallest. */
12939 if (optimize_insn_for_size_p ())
12941 op0 = gen_lowpart (V4SFmode, op0);
12942 op1 = gen_lowpart (V4SFmode, op1);
12943 emit_insn (gen_sse_movups (op0, op1));
12947 /* ??? If we have typed data, then it would appear that using
12948 movdqu is the only way to get unaligned data loaded with
12950 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12952 op0 = gen_lowpart (V16QImode, op0);
12953 op1 = gen_lowpart (V16QImode, op1);
12954 emit_insn (gen_sse2_movdqu (op0, op1));
12958 if (TARGET_SSE2 && mode == V2DFmode)
12962 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12964 op0 = gen_lowpart (V2DFmode, op0);
12965 op1 = gen_lowpart (V2DFmode, op1);
12966 emit_insn (gen_sse2_movupd (op0, op1));
12970 /* When SSE registers are split into halves, we can avoid
12971 writing to the top half twice. */
12972 if (TARGET_SSE_SPLIT_REGS)
12974 emit_clobber (op0);
12979 /* ??? Not sure about the best option for the Intel chips.
12980 The following would seem to satisfy; the register is
12981 entirely cleared, breaking the dependency chain. We
12982 then store to the upper half, with a dependency depth
12983 of one. A rumor has it that Intel recommends two movsd
12984 followed by an unpacklpd, but this is unconfirmed. And
12985 given that the dependency depth of the unpacklpd would
12986 still be one, I'm not sure why this would be better. */
12987 zero = CONST0_RTX (V2DFmode);
12990 m = adjust_address (op1, DFmode, 0);
12991 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12992 m = adjust_address (op1, DFmode, 8);
12993 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12997 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12999 op0 = gen_lowpart (V4SFmode, op0);
13000 op1 = gen_lowpart (V4SFmode, op1);
13001 emit_insn (gen_sse_movups (op0, op1));
13005 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
13006 emit_move_insn (op0, CONST0_RTX (mode));
13008 emit_clobber (op0);
13010 if (mode != V4SFmode)
13011 op0 = gen_lowpart (V4SFmode, op0);
13012 m = adjust_address (op1, V2SFmode, 0);
13013 emit_insn (gen_sse_loadlps (op0, op0, m));
13014 m = adjust_address (op1, V2SFmode, 8);
13015 emit_insn (gen_sse_loadhps (op0, op0, m));
13018 else if (MEM_P (op0))
13020 /* If we're optimizing for size, movups is the smallest. */
13021 if (optimize_insn_for_size_p ())
13023 op0 = gen_lowpart (V4SFmode, op0);
13024 op1 = gen_lowpart (V4SFmode, op1);
13025 emit_insn (gen_sse_movups (op0, op1));
13029 /* ??? Similar to above, only less clear because of quote
13030 typeless stores unquote. */
13031 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
13032 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13034 op0 = gen_lowpart (V16QImode, op0);
13035 op1 = gen_lowpart (V16QImode, op1);
13036 emit_insn (gen_sse2_movdqu (op0, op1));
13040 if (TARGET_SSE2 && mode == V2DFmode)
13042 m = adjust_address (op0, DFmode, 0);
13043 emit_insn (gen_sse2_storelpd (m, op1));
13044 m = adjust_address (op0, DFmode, 8);
13045 emit_insn (gen_sse2_storehpd (m, op1));
13049 if (mode != V4SFmode)
13050 op1 = gen_lowpart (V4SFmode, op1);
13051 m = adjust_address (op0, V2SFmode, 0);
13052 emit_insn (gen_sse_storelps (m, op1));
13053 m = adjust_address (op0, V2SFmode, 8);
13054 emit_insn (gen_sse_storehps (m, op1));
13058 gcc_unreachable ();
13061 /* Expand a push in MODE. This is some mode for which we do not support
13062 proper push instructions, at least from the registers that we expect
13063 the value to live in. */
13066 ix86_expand_push (enum machine_mode mode, rtx x)
13070 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
13071 GEN_INT (-GET_MODE_SIZE (mode)),
13072 stack_pointer_rtx, 1, OPTAB_DIRECT);
13073 if (tmp != stack_pointer_rtx)
13074 emit_move_insn (stack_pointer_rtx, tmp);
13076 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
13078 /* When we push an operand onto stack, it has to be aligned at least
13079 at the function argument boundary. However since we don't have
13080 the argument type, we can't determine the actual argument
13082 emit_move_insn (tmp, x);
13085 /* Helper function of ix86_fixup_binary_operands to canonicalize
13086 operand order. Returns true if the operands should be swapped. */
13089 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
13092 rtx dst = operands[0];
13093 rtx src1 = operands[1];
13094 rtx src2 = operands[2];
13096 /* If the operation is not commutative, we can't do anything. */
13097 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
13100 /* Highest priority is that src1 should match dst. */
13101 if (rtx_equal_p (dst, src1))
13103 if (rtx_equal_p (dst, src2))
13106 /* Next highest priority is that immediate constants come second. */
13107 if (immediate_operand (src2, mode))
13109 if (immediate_operand (src1, mode))
13112 /* Lowest priority is that memory references should come second. */
13122 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13123 destination to use for the operation. If different from the true
13124 destination in operands[0], a copy operation will be required. */
13127 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
13130 rtx dst = operands[0];
13131 rtx src1 = operands[1];
13132 rtx src2 = operands[2];
13134 /* Canonicalize operand order. */
13135 if (ix86_swap_binary_operands_p (code, mode, operands))
13139 /* It is invalid to swap operands of different modes. */
13140 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
13147 /* Both source operands cannot be in memory. */
13148 if (MEM_P (src1) && MEM_P (src2))
13150 /* Optimization: Only read from memory once. */
13151 if (rtx_equal_p (src1, src2))
13153 src2 = force_reg (mode, src2);
13157 src2 = force_reg (mode, src2);
13160 /* If the destination is memory, and we do not have matching source
13161 operands, do things in registers. */
13162 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13163 dst = gen_reg_rtx (mode);
13165 /* Source 1 cannot be a constant. */
13166 if (CONSTANT_P (src1))
13167 src1 = force_reg (mode, src1);
13169 /* Source 1 cannot be a non-matching memory. */
13170 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13171 src1 = force_reg (mode, src1);
13173 operands[1] = src1;
13174 operands[2] = src2;
13178 /* Similarly, but assume that the destination has already been
13179 set up properly. */
13182 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
13183 enum machine_mode mode, rtx operands[])
13185 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
13186 gcc_assert (dst == operands[0]);
13189 /* Attempt to expand a binary operator. Make the expansion closer to the
13190 actual machine, then just general_operand, which will allow 3 separate
13191 memory references (one output, two input) in a single insn. */
13194 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
13197 rtx src1, src2, dst, op, clob;
13199 dst = ix86_fixup_binary_operands (code, mode, operands);
13200 src1 = operands[1];
13201 src2 = operands[2];
13203 /* Emit the instruction. */
13205 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
13206 if (reload_in_progress)
13208 /* Reload doesn't know about the flags register, and doesn't know that
13209 it doesn't want to clobber it. We can only do this with PLUS. */
13210 gcc_assert (code == PLUS);
13215 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13216 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13219 /* Fix up the destination if needed. */
13220 if (dst != operands[0])
13221 emit_move_insn (operands[0], dst);
13224 /* Return TRUE or FALSE depending on whether the binary operator meets the
13225 appropriate constraints. */
13228 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
13231 rtx dst = operands[0];
13232 rtx src1 = operands[1];
13233 rtx src2 = operands[2];
13235 /* Both source operands cannot be in memory. */
13236 if (MEM_P (src1) && MEM_P (src2))
13239 /* Canonicalize operand order for commutative operators. */
13240 if (ix86_swap_binary_operands_p (code, mode, operands))
13247 /* If the destination is memory, we must have a matching source operand. */
13248 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13251 /* Source 1 cannot be a constant. */
13252 if (CONSTANT_P (src1))
13255 /* Source 1 cannot be a non-matching memory. */
13256 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13262 /* Attempt to expand a unary operator. Make the expansion closer to the
13263 actual machine, then just general_operand, which will allow 2 separate
13264 memory references (one output, one input) in a single insn. */
13267 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
13270 int matching_memory;
13271 rtx src, dst, op, clob;
13276 /* If the destination is memory, and we do not have matching source
13277 operands, do things in registers. */
13278 matching_memory = 0;
13281 if (rtx_equal_p (dst, src))
13282 matching_memory = 1;
13284 dst = gen_reg_rtx (mode);
13287 /* When source operand is memory, destination must match. */
13288 if (MEM_P (src) && !matching_memory)
13289 src = force_reg (mode, src);
13291 /* Emit the instruction. */
13293 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
13294 if (reload_in_progress || code == NOT)
13296 /* Reload doesn't know about the flags register, and doesn't know that
13297 it doesn't want to clobber it. */
13298 gcc_assert (code == NOT);
13303 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13304 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13307 /* Fix up the destination if needed. */
13308 if (dst != operands[0])
13309 emit_move_insn (operands[0], dst);
13312 #define LEA_SEARCH_THRESHOLD 12
13314 /* Search backward for non-agu definition of register number REGNO1
13315 or register number REGNO2 in INSN's basic block until
13316 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13317 2. Reach BB boundary, or
13318 3. Reach agu definition.
13319 Returns the distance between the non-agu definition point and INSN.
13320 If no definition point, returns -1. */
13323 distance_non_agu_define (unsigned int regno1, unsigned int regno2,
13326 basic_block bb = BLOCK_FOR_INSN (insn);
13329 enum attr_type insn_type;
13331 if (insn != BB_HEAD (bb))
13333 rtx prev = PREV_INSN (insn);
13334 while (prev && distance < LEA_SEARCH_THRESHOLD)
13339 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13340 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13341 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13342 && (regno1 == DF_REF_REGNO (*def_rec)
13343 || regno2 == DF_REF_REGNO (*def_rec)))
13345 insn_type = get_attr_type (prev);
13346 if (insn_type != TYPE_LEA)
13350 if (prev == BB_HEAD (bb))
13352 prev = PREV_INSN (prev);
13356 if (distance < LEA_SEARCH_THRESHOLD)
13360 bool simple_loop = false;
13362 FOR_EACH_EDGE (e, ei, bb->preds)
13365 simple_loop = true;
13371 rtx prev = BB_END (bb);
13374 && distance < LEA_SEARCH_THRESHOLD)
13379 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13380 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13381 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13382 && (regno1 == DF_REF_REGNO (*def_rec)
13383 || regno2 == DF_REF_REGNO (*def_rec)))
13385 insn_type = get_attr_type (prev);
13386 if (insn_type != TYPE_LEA)
13390 prev = PREV_INSN (prev);
13398 /* get_attr_type may modify recog data. We want to make sure
13399 that recog data is valid for instruction INSN, on which
13400 distance_non_agu_define is called. INSN is unchanged here. */
13401 extract_insn_cached (insn);
13405 /* Return the distance between INSN and the next insn that uses
13406 register number REGNO0 in memory address. Return -1 if no such
13407 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13410 distance_agu_use (unsigned int regno0, rtx insn)
13412 basic_block bb = BLOCK_FOR_INSN (insn);
13417 if (insn != BB_END (bb))
13419 rtx next = NEXT_INSN (insn);
13420 while (next && distance < LEA_SEARCH_THRESHOLD)
13426 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13427 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13428 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13429 && regno0 == DF_REF_REGNO (*use_rec))
13431 /* Return DISTANCE if OP0 is used in memory
13432 address in NEXT. */
13436 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13437 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13438 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13439 && regno0 == DF_REF_REGNO (*def_rec))
13441 /* Return -1 if OP0 is set in NEXT. */
13445 if (next == BB_END (bb))
13447 next = NEXT_INSN (next);
13451 if (distance < LEA_SEARCH_THRESHOLD)
13455 bool simple_loop = false;
13457 FOR_EACH_EDGE (e, ei, bb->succs)
13460 simple_loop = true;
13466 rtx next = BB_HEAD (bb);
13469 && distance < LEA_SEARCH_THRESHOLD)
13475 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13476 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13477 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13478 && regno0 == DF_REF_REGNO (*use_rec))
13480 /* Return DISTANCE if OP0 is used in memory
13481 address in NEXT. */
13485 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13486 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13487 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13488 && regno0 == DF_REF_REGNO (*def_rec))
13490 /* Return -1 if OP0 is set in NEXT. */
13495 next = NEXT_INSN (next);
13503 /* Define this macro to tune LEA priority vs ADD, it take effect when
13504 there is a dilemma of choicing LEA or ADD
13505 Negative value: ADD is more preferred than LEA
13507 Positive value: LEA is more preferred than ADD*/
13508 #define IX86_LEA_PRIORITY 2
13510 /* Return true if it is ok to optimize an ADD operation to LEA
13511 operation to avoid flag register consumation. For the processors
13512 like ATOM, if the destination register of LEA holds an actual
13513 address which will be used soon, LEA is better and otherwise ADD
13517 ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13518 rtx insn, rtx operands[])
13520 unsigned int regno0 = true_regnum (operands[0]);
13521 unsigned int regno1 = true_regnum (operands[1]);
13522 unsigned int regno2;
13524 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
13525 return regno0 != regno1;
13527 regno2 = true_regnum (operands[2]);
13529 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13530 if (regno0 != regno1 && regno0 != regno2)
13534 int dist_define, dist_use;
13535 dist_define = distance_non_agu_define (regno1, regno2, insn);
13536 if (dist_define <= 0)
13539 /* If this insn has both backward non-agu dependence and forward
13540 agu dependence, the one with short distance take effect. */
13541 dist_use = distance_agu_use (regno0, insn);
13543 || (dist_define + IX86_LEA_PRIORITY) < dist_use)
13550 /* Return true if destination reg of SET_BODY is shift count of
13554 ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
13560 /* Retrieve destination of SET_BODY. */
13561 switch (GET_CODE (set_body))
13564 set_dest = SET_DEST (set_body);
13565 if (!set_dest || !REG_P (set_dest))
13569 for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
13570 if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
13578 /* Retrieve shift count of USE_BODY. */
13579 switch (GET_CODE (use_body))
13582 shift_rtx = XEXP (use_body, 1);
13585 for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
13586 if (ix86_dep_by_shift_count_body (set_body,
13587 XVECEXP (use_body, 0, i)))
13595 && (GET_CODE (shift_rtx) == ASHIFT
13596 || GET_CODE (shift_rtx) == LSHIFTRT
13597 || GET_CODE (shift_rtx) == ASHIFTRT
13598 || GET_CODE (shift_rtx) == ROTATE
13599 || GET_CODE (shift_rtx) == ROTATERT))
13601 rtx shift_count = XEXP (shift_rtx, 1);
13603 /* Return true if shift count is dest of SET_BODY. */
13604 if (REG_P (shift_count)
13605 && true_regnum (set_dest) == true_regnum (shift_count))
13612 /* Return true if destination reg of SET_INSN is shift count of
13616 ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
13618 return ix86_dep_by_shift_count_body (PATTERN (set_insn),
13619 PATTERN (use_insn));
13622 /* Return TRUE or FALSE depending on whether the unary operator meets the
13623 appropriate constraints. */
13626 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13627 enum machine_mode mode ATTRIBUTE_UNUSED,
13628 rtx operands[2] ATTRIBUTE_UNUSED)
13630 /* If one of operands is memory, source and destination must match. */
13631 if ((MEM_P (operands[0])
13632 || MEM_P (operands[1]))
13633 && ! rtx_equal_p (operands[0], operands[1]))
13638 /* Post-reload splitter for converting an SF or DFmode value in an
13639 SSE register into an unsigned SImode. */
13642 ix86_split_convert_uns_si_sse (rtx operands[])
13644 enum machine_mode vecmode;
13645 rtx value, large, zero_or_two31, input, two31, x;
13647 large = operands[1];
13648 zero_or_two31 = operands[2];
13649 input = operands[3];
13650 two31 = operands[4];
13651 vecmode = GET_MODE (large);
13652 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13654 /* Load up the value into the low element. We must ensure that the other
13655 elements are valid floats -- zero is the easiest such value. */
13658 if (vecmode == V4SFmode)
13659 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13661 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13665 input = gen_rtx_REG (vecmode, REGNO (input));
13666 emit_move_insn (value, CONST0_RTX (vecmode));
13667 if (vecmode == V4SFmode)
13668 emit_insn (gen_sse_movss (value, value, input));
13670 emit_insn (gen_sse2_movsd (value, value, input));
13673 emit_move_insn (large, two31);
13674 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13676 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13677 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13679 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13680 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13682 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13683 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13685 large = gen_rtx_REG (V4SImode, REGNO (large));
13686 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13688 x = gen_rtx_REG (V4SImode, REGNO (value));
13689 if (vecmode == V4SFmode)
13690 emit_insn (gen_sse2_cvttps2dq (x, value));
13692 emit_insn (gen_sse2_cvttpd2dq (x, value));
13695 emit_insn (gen_xorv4si3 (value, value, large));
13698 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13699 Expects the 64-bit DImode to be supplied in a pair of integral
13700 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13701 -mfpmath=sse, !optimize_size only. */
13704 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13706 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13707 rtx int_xmm, fp_xmm;
13708 rtx biases, exponents;
13711 int_xmm = gen_reg_rtx (V4SImode);
13712 if (TARGET_INTER_UNIT_MOVES)
13713 emit_insn (gen_movdi_to_sse (int_xmm, input));
13714 else if (TARGET_SSE_SPLIT_REGS)
13716 emit_clobber (int_xmm);
13717 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13721 x = gen_reg_rtx (V2DImode);
13722 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13723 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13726 x = gen_rtx_CONST_VECTOR (V4SImode,
13727 gen_rtvec (4, GEN_INT (0x43300000UL),
13728 GEN_INT (0x45300000UL),
13729 const0_rtx, const0_rtx));
13730 exponents = validize_mem (force_const_mem (V4SImode, x));
13732 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13733 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13735 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13736 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13737 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13738 (0x1.0p84 + double(fp_value_hi_xmm)).
13739 Note these exponents differ by 32. */
13741 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13743 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13744 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13745 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13746 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13747 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13748 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13749 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13750 biases = validize_mem (force_const_mem (V2DFmode, biases));
13751 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13753 /* Add the upper and lower DFmode values together. */
13755 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13758 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13759 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13760 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13763 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13766 /* Not used, but eases macroization of patterns. */
13768 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13769 rtx input ATTRIBUTE_UNUSED)
13771 gcc_unreachable ();
13774 /* Convert an unsigned SImode value into a DFmode. Only currently used
13775 for SSE, but applicable anywhere. */
13778 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13780 REAL_VALUE_TYPE TWO31r;
13783 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13784 NULL, 1, OPTAB_DIRECT);
13786 fp = gen_reg_rtx (DFmode);
13787 emit_insn (gen_floatsidf2 (fp, x));
13789 real_ldexp (&TWO31r, &dconst1, 31);
13790 x = const_double_from_real_value (TWO31r, DFmode);
13792 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13794 emit_move_insn (target, x);
13797 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13798 32-bit mode; otherwise we have a direct convert instruction. */
13801 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13803 REAL_VALUE_TYPE TWO32r;
13804 rtx fp_lo, fp_hi, x;
13806 fp_lo = gen_reg_rtx (DFmode);
13807 fp_hi = gen_reg_rtx (DFmode);
13809 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13811 real_ldexp (&TWO32r, &dconst1, 32);
13812 x = const_double_from_real_value (TWO32r, DFmode);
13813 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13815 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13817 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13820 emit_move_insn (target, x);
13823 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13824 For x86_32, -mfpmath=sse, !optimize_size only. */
13826 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13828 REAL_VALUE_TYPE ONE16r;
13829 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13831 real_ldexp (&ONE16r, &dconst1, 16);
13832 x = const_double_from_real_value (ONE16r, SFmode);
13833 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13834 NULL, 0, OPTAB_DIRECT);
13835 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13836 NULL, 0, OPTAB_DIRECT);
13837 fp_hi = gen_reg_rtx (SFmode);
13838 fp_lo = gen_reg_rtx (SFmode);
13839 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13840 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13841 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13843 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13845 if (!rtx_equal_p (target, fp_hi))
13846 emit_move_insn (target, fp_hi);
13849 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
13850 then replicate the value for all elements of the vector
13854 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13861 v = gen_rtvec (4, value, value, value, value);
13862 return gen_rtx_CONST_VECTOR (V4SImode, v);
13866 v = gen_rtvec (2, value, value);
13867 return gen_rtx_CONST_VECTOR (V2DImode, v);
13871 v = gen_rtvec (4, value, value, value, value);
13873 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13874 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13875 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13879 v = gen_rtvec (2, value, value);
13881 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13882 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13885 gcc_unreachable ();
13889 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13890 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13891 for an SSE register. If VECT is true, then replicate the mask for
13892 all elements of the vector register. If INVERT is true, then create
13893 a mask excluding the sign bit. */
13896 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13898 enum machine_mode vec_mode, imode;
13899 HOST_WIDE_INT hi, lo;
13904 /* Find the sign bit, sign extended to 2*HWI. */
13910 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13911 lo = 0x80000000, hi = lo < 0;
13917 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13918 if (HOST_BITS_PER_WIDE_INT >= 64)
13919 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13921 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13926 vec_mode = VOIDmode;
13927 if (HOST_BITS_PER_WIDE_INT >= 64)
13930 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13937 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13941 lo = ~lo, hi = ~hi;
13947 mask = immed_double_const (lo, hi, imode);
13949 vec = gen_rtvec (2, v, mask);
13950 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13951 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13958 gcc_unreachable ();
13962 lo = ~lo, hi = ~hi;
13964 /* Force this value into the low part of a fp vector constant. */
13965 mask = immed_double_const (lo, hi, imode);
13966 mask = gen_lowpart (mode, mask);
13968 if (vec_mode == VOIDmode)
13969 return force_reg (mode, mask);
13971 v = ix86_build_const_vector (mode, vect, mask);
13972 return force_reg (vec_mode, v);
13975 /* Generate code for floating point ABS or NEG. */
13978 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
13981 rtx mask, set, use, clob, dst, src;
13982 bool use_sse = false;
13983 bool vector_mode = VECTOR_MODE_P (mode);
13984 enum machine_mode elt_mode = mode;
13988 elt_mode = GET_MODE_INNER (mode);
13991 else if (mode == TFmode)
13993 else if (TARGET_SSE_MATH)
13994 use_sse = SSE_FLOAT_MODE_P (mode);
13996 /* NEG and ABS performed with SSE use bitwise mask operations.
13997 Create the appropriate mask now. */
13999 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
14008 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
14009 set = gen_rtx_SET (VOIDmode, dst, set);
14014 set = gen_rtx_fmt_e (code, mode, src);
14015 set = gen_rtx_SET (VOIDmode, dst, set);
14018 use = gen_rtx_USE (VOIDmode, mask);
14019 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
14020 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14021 gen_rtvec (3, set, use, clob)));
14028 /* Expand a copysign operation. Special case operand 0 being a constant. */
14031 ix86_expand_copysign (rtx operands[])
14033 enum machine_mode mode;
14034 rtx dest, op0, op1, mask, nmask;
14036 dest = operands[0];
14040 mode = GET_MODE (dest);
14042 if (GET_CODE (op0) == CONST_DOUBLE)
14044 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
14046 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
14047 op0 = simplify_unary_operation (ABS, mode, op0, mode);
14049 if (mode == SFmode || mode == DFmode)
14051 enum machine_mode vmode;
14053 vmode = mode == SFmode ? V4SFmode : V2DFmode;
14055 if (op0 == CONST0_RTX (mode))
14056 op0 = CONST0_RTX (vmode);
14059 rtx v = ix86_build_const_vector (mode, false, op0);
14061 op0 = force_reg (vmode, v);
14064 else if (op0 != CONST0_RTX (mode))
14065 op0 = force_reg (mode, op0);
14067 mask = ix86_build_signbit_mask (mode, 0, 0);
14069 if (mode == SFmode)
14070 copysign_insn = gen_copysignsf3_const;
14071 else if (mode == DFmode)
14072 copysign_insn = gen_copysigndf3_const;
14074 copysign_insn = gen_copysigntf3_const;
14076 emit_insn (copysign_insn (dest, op0, op1, mask));
14080 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
14082 nmask = ix86_build_signbit_mask (mode, 0, 1);
14083 mask = ix86_build_signbit_mask (mode, 0, 0);
14085 if (mode == SFmode)
14086 copysign_insn = gen_copysignsf3_var;
14087 else if (mode == DFmode)
14088 copysign_insn = gen_copysigndf3_var;
14090 copysign_insn = gen_copysigntf3_var;
14092 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
14096 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14097 be a constant, and so has already been expanded into a vector constant. */
14100 ix86_split_copysign_const (rtx operands[])
14102 enum machine_mode mode, vmode;
14103 rtx dest, op0, mask, x;
14105 dest = operands[0];
14107 mask = operands[3];
14109 mode = GET_MODE (dest);
14110 vmode = GET_MODE (mask);
14112 dest = simplify_gen_subreg (vmode, dest, mode, 0);
14113 x = gen_rtx_AND (vmode, dest, mask);
14114 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14116 if (op0 != CONST0_RTX (vmode))
14118 x = gen_rtx_IOR (vmode, dest, op0);
14119 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14123 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14124 so we have to do two masks. */
14127 ix86_split_copysign_var (rtx operands[])
14129 enum machine_mode mode, vmode;
14130 rtx dest, scratch, op0, op1, mask, nmask, x;
14132 dest = operands[0];
14133 scratch = operands[1];
14136 nmask = operands[4];
14137 mask = operands[5];
14139 mode = GET_MODE (dest);
14140 vmode = GET_MODE (mask);
14142 if (rtx_equal_p (op0, op1))
14144 /* Shouldn't happen often (it's useless, obviously), but when it does
14145 we'd generate incorrect code if we continue below. */
14146 emit_move_insn (dest, op0);
14150 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
14152 gcc_assert (REGNO (op1) == REGNO (scratch));
14154 x = gen_rtx_AND (vmode, scratch, mask);
14155 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14158 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14159 x = gen_rtx_NOT (vmode, dest);
14160 x = gen_rtx_AND (vmode, x, op0);
14161 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14165 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
14167 x = gen_rtx_AND (vmode, scratch, mask);
14169 else /* alternative 2,4 */
14171 gcc_assert (REGNO (mask) == REGNO (scratch));
14172 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
14173 x = gen_rtx_AND (vmode, scratch, op1);
14175 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14177 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
14179 dest = simplify_gen_subreg (vmode, op0, mode, 0);
14180 x = gen_rtx_AND (vmode, dest, nmask);
14182 else /* alternative 3,4 */
14184 gcc_assert (REGNO (nmask) == REGNO (dest));
14186 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14187 x = gen_rtx_AND (vmode, dest, op0);
14189 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14192 x = gen_rtx_IOR (vmode, dest, scratch);
14193 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14196 /* Return TRUE or FALSE depending on whether the first SET in INSN
14197 has source and destination with matching CC modes, and that the
14198 CC mode is at least as constrained as REQ_MODE. */
14201 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
14204 enum machine_mode set_mode;
14206 set = PATTERN (insn);
14207 if (GET_CODE (set) == PARALLEL)
14208 set = XVECEXP (set, 0, 0);
14209 gcc_assert (GET_CODE (set) == SET);
14210 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
14212 set_mode = GET_MODE (SET_DEST (set));
14216 if (req_mode != CCNOmode
14217 && (req_mode != CCmode
14218 || XEXP (SET_SRC (set), 1) != const0_rtx))
14222 if (req_mode == CCGCmode)
14226 if (req_mode == CCGOCmode || req_mode == CCNOmode)
14230 if (req_mode == CCZmode)
14241 gcc_unreachable ();
14244 return (GET_MODE (SET_SRC (set)) == set_mode);
14247 /* Generate insn patterns to do an integer compare of OPERANDS. */
14250 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
14252 enum machine_mode cmpmode;
14255 cmpmode = SELECT_CC_MODE (code, op0, op1);
14256 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
14258 /* This is very simple, but making the interface the same as in the
14259 FP case makes the rest of the code easier. */
14260 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
14261 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
14263 /* Return the test that should be put into the flags user, i.e.
14264 the bcc, scc, or cmov instruction. */
14265 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
14268 /* Figure out whether to use ordered or unordered fp comparisons.
14269 Return the appropriate mode to use. */
14272 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
14274 /* ??? In order to make all comparisons reversible, we do all comparisons
14275 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14276 all forms trapping and nontrapping comparisons, we can make inequality
14277 comparisons trapping again, since it results in better code when using
14278 FCOM based compares. */
14279 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
14283 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
14285 enum machine_mode mode = GET_MODE (op0);
14287 if (SCALAR_FLOAT_MODE_P (mode))
14289 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14290 return ix86_fp_compare_mode (code);
14295 /* Only zero flag is needed. */
14296 case EQ: /* ZF=0 */
14297 case NE: /* ZF!=0 */
14299 /* Codes needing carry flag. */
14300 case GEU: /* CF=0 */
14301 case LTU: /* CF=1 */
14302 /* Detect overflow checks. They need just the carry flag. */
14303 if (GET_CODE (op0) == PLUS
14304 && rtx_equal_p (op1, XEXP (op0, 0)))
14308 case GTU: /* CF=0 & ZF=0 */
14309 case LEU: /* CF=1 | ZF=1 */
14310 /* Detect overflow checks. They need just the carry flag. */
14311 if (GET_CODE (op0) == MINUS
14312 && rtx_equal_p (op1, XEXP (op0, 0)))
14316 /* Codes possibly doable only with sign flag when
14317 comparing against zero. */
14318 case GE: /* SF=OF or SF=0 */
14319 case LT: /* SF<>OF or SF=1 */
14320 if (op1 == const0_rtx)
14323 /* For other cases Carry flag is not required. */
14325 /* Codes doable only with sign flag when comparing
14326 against zero, but we miss jump instruction for it
14327 so we need to use relational tests against overflow
14328 that thus needs to be zero. */
14329 case GT: /* ZF=0 & SF=OF */
14330 case LE: /* ZF=1 | SF<>OF */
14331 if (op1 == const0_rtx)
14335 /* strcmp pattern do (use flags) and combine may ask us for proper
14340 gcc_unreachable ();
14344 /* Return the fixed registers used for condition codes. */
14347 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
14354 /* If two condition code modes are compatible, return a condition code
14355 mode which is compatible with both. Otherwise, return
14358 static enum machine_mode
14359 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
14364 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
14367 if ((m1 == CCGCmode && m2 == CCGOCmode)
14368 || (m1 == CCGOCmode && m2 == CCGCmode))
14374 gcc_unreachable ();
14404 /* These are only compatible with themselves, which we already
14411 /* Return a comparison we can do and that it is equivalent to
14412 swap_condition (code) apart possibly from orderedness.
14413 But, never change orderedness if TARGET_IEEE_FP, returning
14414 UNKNOWN in that case if necessary. */
14416 static enum rtx_code
14417 ix86_fp_swap_condition (enum rtx_code code)
14421 case GT: /* GTU - CF=0 & ZF=0 */
14422 return TARGET_IEEE_FP ? UNKNOWN : UNLT;
14423 case GE: /* GEU - CF=0 */
14424 return TARGET_IEEE_FP ? UNKNOWN : UNLE;
14425 case UNLT: /* LTU - CF=1 */
14426 return TARGET_IEEE_FP ? UNKNOWN : GT;
14427 case UNLE: /* LEU - CF=1 | ZF=1 */
14428 return TARGET_IEEE_FP ? UNKNOWN : GE;
14430 return swap_condition (code);
14434 /* Return cost of comparison CODE using the best strategy for performance.
14435 All following functions do use number of instructions as a cost metrics.
14436 In future this should be tweaked to compute bytes for optimize_size and
14437 take into account performance of various instructions on various CPUs. */
14440 ix86_fp_comparison_cost (enum rtx_code code)
14444 /* The cost of code using bit-twiddling on %ah. */
14461 arith_cost = TARGET_IEEE_FP ? 5 : 4;
14465 arith_cost = TARGET_IEEE_FP ? 6 : 4;
14468 gcc_unreachable ();
14471 switch (ix86_fp_comparison_strategy (code))
14473 case IX86_FPCMP_COMI:
14474 return arith_cost > 4 ? 3 : 2;
14475 case IX86_FPCMP_SAHF:
14476 return arith_cost > 4 ? 4 : 3;
14482 /* Return strategy to use for floating-point. We assume that fcomi is always
14483 preferrable where available, since that is also true when looking at size
14484 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
14486 enum ix86_fpcmp_strategy
14487 ix86_fp_comparison_strategy (enum rtx_code code ATTRIBUTE_UNUSED)
14489 /* Do fcomi/sahf based test when profitable. */
14492 return IX86_FPCMP_COMI;
14494 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_function_for_size_p (cfun)))
14495 return IX86_FPCMP_SAHF;
14497 return IX86_FPCMP_ARITH;
14500 /* Swap, force into registers, or otherwise massage the two operands
14501 to a fp comparison. The operands are updated in place; the new
14502 comparison code is returned. */
14504 static enum rtx_code
14505 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
14507 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
14508 rtx op0 = *pop0, op1 = *pop1;
14509 enum machine_mode op_mode = GET_MODE (op0);
14510 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
14512 /* All of the unordered compare instructions only work on registers.
14513 The same is true of the fcomi compare instructions. The XFmode
14514 compare instructions require registers except when comparing
14515 against zero or when converting operand 1 from fixed point to
14519 && (fpcmp_mode == CCFPUmode
14520 || (op_mode == XFmode
14521 && ! (standard_80387_constant_p (op0) == 1
14522 || standard_80387_constant_p (op1) == 1)
14523 && GET_CODE (op1) != FLOAT)
14524 || ix86_fp_comparison_strategy (code) == IX86_FPCMP_COMI))
14526 op0 = force_reg (op_mode, op0);
14527 op1 = force_reg (op_mode, op1);
14531 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14532 things around if they appear profitable, otherwise force op0
14533 into a register. */
14535 if (standard_80387_constant_p (op0) == 0
14537 && ! (standard_80387_constant_p (op1) == 0
14540 enum rtx_code new_code = ix86_fp_swap_condition (code);
14541 if (new_code != UNKNOWN)
14544 tmp = op0, op0 = op1, op1 = tmp;
14550 op0 = force_reg (op_mode, op0);
14552 if (CONSTANT_P (op1))
14554 int tmp = standard_80387_constant_p (op1);
14556 op1 = validize_mem (force_const_mem (op_mode, op1));
14560 op1 = force_reg (op_mode, op1);
14563 op1 = force_reg (op_mode, op1);
14567 /* Try to rearrange the comparison to make it cheaper. */
14568 if (ix86_fp_comparison_cost (code)
14569 > ix86_fp_comparison_cost (swap_condition (code))
14570 && (REG_P (op1) || can_create_pseudo_p ()))
14573 tmp = op0, op0 = op1, op1 = tmp;
14574 code = swap_condition (code);
14576 op0 = force_reg (op_mode, op0);
14584 /* Convert comparison codes we use to represent FP comparison to integer
14585 code that will result in proper branch. Return UNKNOWN if no such code
14589 ix86_fp_compare_code_to_integer (enum rtx_code code)
14618 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14621 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch)
14623 enum machine_mode fpcmp_mode, intcmp_mode;
14626 fpcmp_mode = ix86_fp_compare_mode (code);
14627 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14629 /* Do fcomi/sahf based test when profitable. */
14630 switch (ix86_fp_comparison_strategy (code))
14632 case IX86_FPCMP_COMI:
14633 intcmp_mode = fpcmp_mode;
14634 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14635 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14640 case IX86_FPCMP_SAHF:
14641 intcmp_mode = fpcmp_mode;
14642 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14643 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14647 scratch = gen_reg_rtx (HImode);
14648 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14649 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14652 case IX86_FPCMP_ARITH:
14653 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14654 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14655 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14657 scratch = gen_reg_rtx (HImode);
14658 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14660 /* In the unordered case, we have to check C2 for NaN's, which
14661 doesn't happen to work out to anything nice combination-wise.
14662 So do some bit twiddling on the value we've got in AH to come
14663 up with an appropriate set of condition codes. */
14665 intcmp_mode = CCNOmode;
14670 if (code == GT || !TARGET_IEEE_FP)
14672 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14677 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14678 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14679 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14680 intcmp_mode = CCmode;
14686 if (code == LT && TARGET_IEEE_FP)
14688 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14689 emit_insn (gen_cmpqi_ext_3 (scratch, const1_rtx));
14690 intcmp_mode = CCmode;
14695 emit_insn (gen_testqi_ext_ccno_0 (scratch, const1_rtx));
14701 if (code == GE || !TARGET_IEEE_FP)
14703 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14708 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14709 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch, const1_rtx));
14715 if (code == LE && TARGET_IEEE_FP)
14717 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14718 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14719 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14720 intcmp_mode = CCmode;
14725 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14731 if (code == EQ && TARGET_IEEE_FP)
14733 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14734 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14735 intcmp_mode = CCmode;
14740 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14746 if (code == NE && TARGET_IEEE_FP)
14748 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14749 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14755 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14761 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14765 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14770 gcc_unreachable ();
14778 /* Return the test that should be put into the flags user, i.e.
14779 the bcc, scc, or cmov instruction. */
14780 return gen_rtx_fmt_ee (code, VOIDmode,
14781 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14786 ix86_expand_compare (enum rtx_code code)
14789 op0 = ix86_compare_op0;
14790 op1 = ix86_compare_op1;
14792 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC)
14793 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_op0, ix86_compare_op1);
14795 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14797 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14798 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
14801 ret = ix86_expand_int_compare (code, op0, op1);
14807 ix86_expand_branch (enum rtx_code code, rtx label)
14811 switch (GET_MODE (ix86_compare_op0))
14820 tmp = ix86_expand_compare (code);
14821 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14822 gen_rtx_LABEL_REF (VOIDmode, label),
14824 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14831 /* Expand DImode branch into multiple compare+branch. */
14833 rtx lo[2], hi[2], label2;
14834 enum rtx_code code1, code2, code3;
14835 enum machine_mode submode;
14837 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14839 tmp = ix86_compare_op0;
14840 ix86_compare_op0 = ix86_compare_op1;
14841 ix86_compare_op1 = tmp;
14842 code = swap_condition (code);
14844 if (GET_MODE (ix86_compare_op0) == DImode)
14846 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14847 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14852 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14853 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14857 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14858 avoid two branches. This costs one extra insn, so disable when
14859 optimizing for size. */
14861 if ((code == EQ || code == NE)
14862 && (!optimize_insn_for_size_p ()
14863 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14868 if (hi[1] != const0_rtx)
14869 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14870 NULL_RTX, 0, OPTAB_WIDEN);
14873 if (lo[1] != const0_rtx)
14874 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14875 NULL_RTX, 0, OPTAB_WIDEN);
14877 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14878 NULL_RTX, 0, OPTAB_WIDEN);
14880 ix86_compare_op0 = tmp;
14881 ix86_compare_op1 = const0_rtx;
14882 ix86_expand_branch (code, label);
14886 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14887 op1 is a constant and the low word is zero, then we can just
14888 examine the high word. Similarly for low word -1 and
14889 less-or-equal-than or greater-than. */
14891 if (CONST_INT_P (hi[1]))
14894 case LT: case LTU: case GE: case GEU:
14895 if (lo[1] == const0_rtx)
14897 ix86_compare_op0 = hi[0];
14898 ix86_compare_op1 = hi[1];
14899 ix86_expand_branch (code, label);
14903 case LE: case LEU: case GT: case GTU:
14904 if (lo[1] == constm1_rtx)
14906 ix86_compare_op0 = hi[0];
14907 ix86_compare_op1 = hi[1];
14908 ix86_expand_branch (code, label);
14916 /* Otherwise, we need two or three jumps. */
14918 label2 = gen_label_rtx ();
14921 code2 = swap_condition (code);
14922 code3 = unsigned_condition (code);
14926 case LT: case GT: case LTU: case GTU:
14929 case LE: code1 = LT; code2 = GT; break;
14930 case GE: code1 = GT; code2 = LT; break;
14931 case LEU: code1 = LTU; code2 = GTU; break;
14932 case GEU: code1 = GTU; code2 = LTU; break;
14934 case EQ: code1 = UNKNOWN; code2 = NE; break;
14935 case NE: code2 = UNKNOWN; break;
14938 gcc_unreachable ();
14943 * if (hi(a) < hi(b)) goto true;
14944 * if (hi(a) > hi(b)) goto false;
14945 * if (lo(a) < lo(b)) goto true;
14949 ix86_compare_op0 = hi[0];
14950 ix86_compare_op1 = hi[1];
14952 if (code1 != UNKNOWN)
14953 ix86_expand_branch (code1, label);
14954 if (code2 != UNKNOWN)
14955 ix86_expand_branch (code2, label2);
14957 ix86_compare_op0 = lo[0];
14958 ix86_compare_op1 = lo[1];
14959 ix86_expand_branch (code3, label);
14961 if (code2 != UNKNOWN)
14962 emit_label (label2);
14967 /* If we have already emitted a compare insn, go straight to simple.
14968 ix86_expand_compare won't emit anything if ix86_compare_emitted
14970 gcc_assert (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC);
14975 /* Split branch based on floating point condition. */
14977 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14978 rtx target1, rtx target2, rtx tmp, rtx pushed)
14983 if (target2 != pc_rtx)
14986 code = reverse_condition_maybe_unordered (code);
14991 condition = ix86_expand_fp_compare (code, op1, op2,
14994 /* Remove pushed operand from stack. */
14996 ix86_free_from_memory (GET_MODE (pushed));
14998 i = emit_jump_insn (gen_rtx_SET
15000 gen_rtx_IF_THEN_ELSE (VOIDmode,
15001 condition, target1, target2)));
15002 if (split_branch_probability >= 0)
15003 add_reg_note (i, REG_BR_PROB, GEN_INT (split_branch_probability));
15007 ix86_expand_setcc (enum rtx_code code, rtx dest)
15011 gcc_assert (GET_MODE (dest) == QImode);
15013 ret = ix86_expand_compare (code);
15014 PUT_MODE (ret, QImode);
15015 emit_insn (gen_rtx_SET (VOIDmode, dest, ret));
15018 /* Expand comparison setting or clearing carry flag. Return true when
15019 successful and set pop for the operation. */
15021 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
15023 enum machine_mode mode =
15024 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
15026 /* Do not handle DImode compares that go through special path. */
15027 if (mode == (TARGET_64BIT ? TImode : DImode))
15030 if (SCALAR_FLOAT_MODE_P (mode))
15032 rtx compare_op, compare_seq;
15034 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
15036 /* Shortcut: following common codes never translate
15037 into carry flag compares. */
15038 if (code == EQ || code == NE || code == UNEQ || code == LTGT
15039 || code == ORDERED || code == UNORDERED)
15042 /* These comparisons require zero flag; swap operands so they won't. */
15043 if ((code == GT || code == UNLE || code == LE || code == UNGT)
15044 && !TARGET_IEEE_FP)
15049 code = swap_condition (code);
15052 /* Try to expand the comparison and verify that we end up with
15053 carry flag based comparison. This fails to be true only when
15054 we decide to expand comparison using arithmetic that is not
15055 too common scenario. */
15057 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
15058 compare_seq = get_insns ();
15061 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15062 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15063 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
15065 code = GET_CODE (compare_op);
15067 if (code != LTU && code != GEU)
15070 emit_insn (compare_seq);
15075 if (!INTEGRAL_MODE_P (mode))
15084 /* Convert a==0 into (unsigned)a<1. */
15087 if (op1 != const0_rtx)
15090 code = (code == EQ ? LTU : GEU);
15093 /* Convert a>b into b<a or a>=b-1. */
15096 if (CONST_INT_P (op1))
15098 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
15099 /* Bail out on overflow. We still can swap operands but that
15100 would force loading of the constant into register. */
15101 if (op1 == const0_rtx
15102 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
15104 code = (code == GTU ? GEU : LTU);
15111 code = (code == GTU ? LTU : GEU);
15115 /* Convert a>=0 into (unsigned)a<0x80000000. */
15118 if (mode == DImode || op1 != const0_rtx)
15120 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15121 code = (code == LT ? GEU : LTU);
15125 if (mode == DImode || op1 != constm1_rtx)
15127 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15128 code = (code == LE ? GEU : LTU);
15134 /* Swapping operands may cause constant to appear as first operand. */
15135 if (!nonimmediate_operand (op0, VOIDmode))
15137 if (!can_create_pseudo_p ())
15139 op0 = force_reg (mode, op0);
15141 ix86_compare_op0 = op0;
15142 ix86_compare_op1 = op1;
15143 *pop = ix86_expand_compare (code);
15144 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
15149 ix86_expand_int_movcc (rtx operands[])
15151 enum rtx_code code = GET_CODE (operands[1]), compare_code;
15152 rtx compare_seq, compare_op;
15153 enum machine_mode mode = GET_MODE (operands[0]);
15154 bool sign_bit_compare_p = false;;
15157 ix86_compare_op0 = XEXP (operands[1], 0);
15158 ix86_compare_op1 = XEXP (operands[1], 1);
15159 compare_op = ix86_expand_compare (code);
15160 compare_seq = get_insns ();
15163 compare_code = GET_CODE (compare_op);
15165 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
15166 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
15167 sign_bit_compare_p = true;
15169 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15170 HImode insns, we'd be swallowed in word prefix ops. */
15172 if ((mode != HImode || TARGET_FAST_PREFIX)
15173 && (mode != (TARGET_64BIT ? TImode : DImode))
15174 && CONST_INT_P (operands[2])
15175 && CONST_INT_P (operands[3]))
15177 rtx out = operands[0];
15178 HOST_WIDE_INT ct = INTVAL (operands[2]);
15179 HOST_WIDE_INT cf = INTVAL (operands[3]);
15180 HOST_WIDE_INT diff;
15183 /* Sign bit compares are better done using shifts than we do by using
15185 if (sign_bit_compare_p
15186 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15187 ix86_compare_op1, &compare_op))
15189 /* Detect overlap between destination and compare sources. */
15192 if (!sign_bit_compare_p)
15194 bool fpcmp = false;
15196 compare_code = GET_CODE (compare_op);
15198 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15199 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15202 compare_code = ix86_fp_compare_code_to_integer (compare_code);
15205 /* To simplify rest of code, restrict to the GEU case. */
15206 if (compare_code == LTU)
15208 HOST_WIDE_INT tmp = ct;
15211 compare_code = reverse_condition (compare_code);
15212 code = reverse_condition (code);
15217 PUT_CODE (compare_op,
15218 reverse_condition_maybe_unordered
15219 (GET_CODE (compare_op)));
15221 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15225 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
15226 || reg_overlap_mentioned_p (out, ix86_compare_op1))
15227 tmp = gen_reg_rtx (mode);
15229 if (mode == DImode)
15230 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
15232 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
15236 if (code == GT || code == GE)
15237 code = reverse_condition (code);
15240 HOST_WIDE_INT tmp = ct;
15245 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
15246 ix86_compare_op1, VOIDmode, 0, -1);
15259 tmp = expand_simple_binop (mode, PLUS,
15261 copy_rtx (tmp), 1, OPTAB_DIRECT);
15272 tmp = expand_simple_binop (mode, IOR,
15274 copy_rtx (tmp), 1, OPTAB_DIRECT);
15276 else if (diff == -1 && ct)
15286 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15288 tmp = expand_simple_binop (mode, PLUS,
15289 copy_rtx (tmp), GEN_INT (cf),
15290 copy_rtx (tmp), 1, OPTAB_DIRECT);
15298 * andl cf - ct, dest
15308 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15311 tmp = expand_simple_binop (mode, AND,
15313 gen_int_mode (cf - ct, mode),
15314 copy_rtx (tmp), 1, OPTAB_DIRECT);
15316 tmp = expand_simple_binop (mode, PLUS,
15317 copy_rtx (tmp), GEN_INT (ct),
15318 copy_rtx (tmp), 1, OPTAB_DIRECT);
15321 if (!rtx_equal_p (tmp, out))
15322 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
15324 return 1; /* DONE */
15329 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15332 tmp = ct, ct = cf, cf = tmp;
15335 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15337 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15339 /* We may be reversing unordered compare to normal compare, that
15340 is not valid in general (we may convert non-trapping condition
15341 to trapping one), however on i386 we currently emit all
15342 comparisons unordered. */
15343 compare_code = reverse_condition_maybe_unordered (compare_code);
15344 code = reverse_condition_maybe_unordered (code);
15348 compare_code = reverse_condition (compare_code);
15349 code = reverse_condition (code);
15353 compare_code = UNKNOWN;
15354 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
15355 && CONST_INT_P (ix86_compare_op1))
15357 if (ix86_compare_op1 == const0_rtx
15358 && (code == LT || code == GE))
15359 compare_code = code;
15360 else if (ix86_compare_op1 == constm1_rtx)
15364 else if (code == GT)
15369 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15370 if (compare_code != UNKNOWN
15371 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15372 && (cf == -1 || ct == -1))
15374 /* If lea code below could be used, only optimize
15375 if it results in a 2 insn sequence. */
15377 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15378 || diff == 3 || diff == 5 || diff == 9)
15379 || (compare_code == LT && ct == -1)
15380 || (compare_code == GE && cf == -1))
15383 * notl op1 (if necessary)
15391 code = reverse_condition (code);
15394 out = emit_store_flag (out, code, ix86_compare_op0,
15395 ix86_compare_op1, VOIDmode, 0, -1);
15397 out = expand_simple_binop (mode, IOR,
15399 out, 1, OPTAB_DIRECT);
15400 if (out != operands[0])
15401 emit_move_insn (operands[0], out);
15403 return 1; /* DONE */
15408 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15409 || diff == 3 || diff == 5 || diff == 9)
15410 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15412 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15418 * lea cf(dest*(ct-cf)),dest
15422 * This also catches the degenerate setcc-only case.
15428 out = emit_store_flag (out, code, ix86_compare_op0,
15429 ix86_compare_op1, VOIDmode, 0, 1);
15432 /* On x86_64 the lea instruction operates on Pmode, so we need
15433 to get arithmetics done in proper mode to match. */
15435 tmp = copy_rtx (out);
15439 out1 = copy_rtx (out);
15440 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15444 tmp = gen_rtx_PLUS (mode, tmp, out1);
15450 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15453 if (!rtx_equal_p (tmp, out))
15456 out = force_operand (tmp, copy_rtx (out));
15458 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15460 if (!rtx_equal_p (out, operands[0]))
15461 emit_move_insn (operands[0], copy_rtx (out));
15463 return 1; /* DONE */
15467 * General case: Jumpful:
15468 * xorl dest,dest cmpl op1, op2
15469 * cmpl op1, op2 movl ct, dest
15470 * setcc dest jcc 1f
15471 * decl dest movl cf, dest
15472 * andl (cf-ct),dest 1:
15475 * Size 20. Size 14.
15477 * This is reasonably steep, but branch mispredict costs are
15478 * high on modern cpus, so consider failing only if optimizing
15482 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15483 && BRANCH_COST (optimize_insn_for_speed_p (),
15488 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15493 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15495 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15497 /* We may be reversing unordered compare to normal compare,
15498 that is not valid in general (we may convert non-trapping
15499 condition to trapping one), however on i386 we currently
15500 emit all comparisons unordered. */
15501 code = reverse_condition_maybe_unordered (code);
15505 code = reverse_condition (code);
15506 if (compare_code != UNKNOWN)
15507 compare_code = reverse_condition (compare_code);
15511 if (compare_code != UNKNOWN)
15513 /* notl op1 (if needed)
15518 For x < 0 (resp. x <= -1) there will be no notl,
15519 so if possible swap the constants to get rid of the
15521 True/false will be -1/0 while code below (store flag
15522 followed by decrement) is 0/-1, so the constants need
15523 to be exchanged once more. */
15525 if (compare_code == GE || !cf)
15527 code = reverse_condition (code);
15532 HOST_WIDE_INT tmp = cf;
15537 out = emit_store_flag (out, code, ix86_compare_op0,
15538 ix86_compare_op1, VOIDmode, 0, -1);
15542 out = emit_store_flag (out, code, ix86_compare_op0,
15543 ix86_compare_op1, VOIDmode, 0, 1);
15545 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15546 copy_rtx (out), 1, OPTAB_DIRECT);
15549 out = expand_simple_binop (mode, AND, copy_rtx (out),
15550 gen_int_mode (cf - ct, mode),
15551 copy_rtx (out), 1, OPTAB_DIRECT);
15553 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15554 copy_rtx (out), 1, OPTAB_DIRECT);
15555 if (!rtx_equal_p (out, operands[0]))
15556 emit_move_insn (operands[0], copy_rtx (out));
15558 return 1; /* DONE */
15562 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15564 /* Try a few things more with specific constants and a variable. */
15567 rtx var, orig_out, out, tmp;
15569 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15570 return 0; /* FAIL */
15572 /* If one of the two operands is an interesting constant, load a
15573 constant with the above and mask it in with a logical operation. */
15575 if (CONST_INT_P (operands[2]))
15578 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15579 operands[3] = constm1_rtx, op = and_optab;
15580 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15581 operands[3] = const0_rtx, op = ior_optab;
15583 return 0; /* FAIL */
15585 else if (CONST_INT_P (operands[3]))
15588 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15589 operands[2] = constm1_rtx, op = and_optab;
15590 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15591 operands[2] = const0_rtx, op = ior_optab;
15593 return 0; /* FAIL */
15596 return 0; /* FAIL */
15598 orig_out = operands[0];
15599 tmp = gen_reg_rtx (mode);
15602 /* Recurse to get the constant loaded. */
15603 if (ix86_expand_int_movcc (operands) == 0)
15604 return 0; /* FAIL */
15606 /* Mask in the interesting variable. */
15607 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15609 if (!rtx_equal_p (out, orig_out))
15610 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15612 return 1; /* DONE */
15616 * For comparison with above,
15626 if (! nonimmediate_operand (operands[2], mode))
15627 operands[2] = force_reg (mode, operands[2]);
15628 if (! nonimmediate_operand (operands[3], mode))
15629 operands[3] = force_reg (mode, operands[3]);
15631 if (! register_operand (operands[2], VOIDmode)
15633 || ! register_operand (operands[3], VOIDmode)))
15634 operands[2] = force_reg (mode, operands[2]);
15637 && ! register_operand (operands[3], VOIDmode))
15638 operands[3] = force_reg (mode, operands[3]);
15640 emit_insn (compare_seq);
15641 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15642 gen_rtx_IF_THEN_ELSE (mode,
15643 compare_op, operands[2],
15646 return 1; /* DONE */
15649 /* Swap, force into registers, or otherwise massage the two operands
15650 to an sse comparison with a mask result. Thus we differ a bit from
15651 ix86_prepare_fp_compare_args which expects to produce a flags result.
15653 The DEST operand exists to help determine whether to commute commutative
15654 operators. The POP0/POP1 operands are updated in place. The new
15655 comparison code is returned, or UNKNOWN if not implementable. */
15657 static enum rtx_code
15658 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15659 rtx *pop0, rtx *pop1)
15667 /* We have no LTGT as an operator. We could implement it with
15668 NE & ORDERED, but this requires an extra temporary. It's
15669 not clear that it's worth it. */
15676 /* These are supported directly. */
15683 /* For commutative operators, try to canonicalize the destination
15684 operand to be first in the comparison - this helps reload to
15685 avoid extra moves. */
15686 if (!dest || !rtx_equal_p (dest, *pop1))
15694 /* These are not supported directly. Swap the comparison operands
15695 to transform into something that is supported. */
15699 code = swap_condition (code);
15703 gcc_unreachable ();
15709 /* Detect conditional moves that exactly match min/max operational
15710 semantics. Note that this is IEEE safe, as long as we don't
15711 interchange the operands.
15713 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15714 and TRUE if the operation is successful and instructions are emitted. */
15717 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15718 rtx cmp_op1, rtx if_true, rtx if_false)
15720 enum machine_mode mode;
15726 else if (code == UNGE)
15729 if_true = if_false;
15735 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15737 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15742 mode = GET_MODE (dest);
15744 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15745 but MODE may be a vector mode and thus not appropriate. */
15746 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15748 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15751 if_true = force_reg (mode, if_true);
15752 v = gen_rtvec (2, if_true, if_false);
15753 tmp = gen_rtx_UNSPEC (mode, v, u);
15757 code = is_min ? SMIN : SMAX;
15758 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15761 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15765 /* Expand an sse vector comparison. Return the register with the result. */
15768 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15769 rtx op_true, rtx op_false)
15771 enum machine_mode mode = GET_MODE (dest);
15774 cmp_op0 = force_reg (mode, cmp_op0);
15775 if (!nonimmediate_operand (cmp_op1, mode))
15776 cmp_op1 = force_reg (mode, cmp_op1);
15779 || reg_overlap_mentioned_p (dest, op_true)
15780 || reg_overlap_mentioned_p (dest, op_false))
15781 dest = gen_reg_rtx (mode);
15783 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15784 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15789 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15790 operations. This is used for both scalar and vector conditional moves. */
15793 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15795 enum machine_mode mode = GET_MODE (dest);
15798 if (op_false == CONST0_RTX (mode))
15800 op_true = force_reg (mode, op_true);
15801 x = gen_rtx_AND (mode, cmp, op_true);
15802 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15804 else if (op_true == CONST0_RTX (mode))
15806 op_false = force_reg (mode, op_false);
15807 x = gen_rtx_NOT (mode, cmp);
15808 x = gen_rtx_AND (mode, x, op_false);
15809 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15813 op_true = force_reg (mode, op_true);
15814 op_false = force_reg (mode, op_false);
15816 t2 = gen_reg_rtx (mode);
15818 t3 = gen_reg_rtx (mode);
15822 x = gen_rtx_AND (mode, op_true, cmp);
15823 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15825 x = gen_rtx_NOT (mode, cmp);
15826 x = gen_rtx_AND (mode, x, op_false);
15827 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15829 x = gen_rtx_IOR (mode, t3, t2);
15830 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15834 /* Expand a floating-point conditional move. Return true if successful. */
15837 ix86_expand_fp_movcc (rtx operands[])
15839 enum machine_mode mode = GET_MODE (operands[0]);
15840 enum rtx_code code = GET_CODE (operands[1]);
15841 rtx tmp, compare_op;
15843 ix86_compare_op0 = XEXP (operands[1], 0);
15844 ix86_compare_op1 = XEXP (operands[1], 1);
15845 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15847 enum machine_mode cmode;
15849 /* Since we've no cmove for sse registers, don't force bad register
15850 allocation just to gain access to it. Deny movcc when the
15851 comparison mode doesn't match the move mode. */
15852 cmode = GET_MODE (ix86_compare_op0);
15853 if (cmode == VOIDmode)
15854 cmode = GET_MODE (ix86_compare_op1);
15858 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15860 &ix86_compare_op1);
15861 if (code == UNKNOWN)
15864 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15865 ix86_compare_op1, operands[2],
15869 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15870 ix86_compare_op1, operands[2], operands[3]);
15871 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15875 /* The floating point conditional move instructions don't directly
15876 support conditions resulting from a signed integer comparison. */
15878 compare_op = ix86_expand_compare (code);
15879 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15881 tmp = gen_reg_rtx (QImode);
15882 ix86_expand_setcc (code, tmp);
15884 ix86_compare_op0 = tmp;
15885 ix86_compare_op1 = const0_rtx;
15886 compare_op = ix86_expand_compare (code);
15889 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15890 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15891 operands[2], operands[3])));
15896 /* Expand a floating-point vector conditional move; a vcond operation
15897 rather than a movcc operation. */
15900 ix86_expand_fp_vcond (rtx operands[])
15902 enum rtx_code code = GET_CODE (operands[3]);
15905 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15906 &operands[4], &operands[5]);
15907 if (code == UNKNOWN)
15910 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15911 operands[5], operands[1], operands[2]))
15914 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15915 operands[1], operands[2]);
15916 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15920 /* Expand a signed/unsigned integral vector conditional move. */
15923 ix86_expand_int_vcond (rtx operands[])
15925 enum machine_mode mode = GET_MODE (operands[0]);
15926 enum rtx_code code = GET_CODE (operands[3]);
15927 bool negate = false;
15930 cop0 = operands[4];
15931 cop1 = operands[5];
15933 /* Canonicalize the comparison to EQ, GT, GTU. */
15944 code = reverse_condition (code);
15950 code = reverse_condition (code);
15956 code = swap_condition (code);
15957 x = cop0, cop0 = cop1, cop1 = x;
15961 gcc_unreachable ();
15964 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15965 if (mode == V2DImode)
15970 /* SSE4.1 supports EQ. */
15971 if (!TARGET_SSE4_1)
15977 /* SSE4.2 supports GT/GTU. */
15978 if (!TARGET_SSE4_2)
15983 gcc_unreachable ();
15987 /* Unsigned parallel compare is not supported by the hardware. Play some
15988 tricks to turn this into a signed comparison against 0. */
15991 cop0 = force_reg (mode, cop0);
16000 /* Perform a parallel modulo subtraction. */
16001 t1 = gen_reg_rtx (mode);
16002 emit_insn ((mode == V4SImode
16004 : gen_subv2di3) (t1, cop0, cop1));
16006 /* Extract the original sign bit of op0. */
16007 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
16009 t2 = gen_reg_rtx (mode);
16010 emit_insn ((mode == V4SImode
16012 : gen_andv2di3) (t2, cop0, mask));
16014 /* XOR it back into the result of the subtraction. This results
16015 in the sign bit set iff we saw unsigned underflow. */
16016 x = gen_reg_rtx (mode);
16017 emit_insn ((mode == V4SImode
16019 : gen_xorv2di3) (x, t1, t2));
16027 /* Perform a parallel unsigned saturating subtraction. */
16028 x = gen_reg_rtx (mode);
16029 emit_insn (gen_rtx_SET (VOIDmode, x,
16030 gen_rtx_US_MINUS (mode, cop0, cop1)));
16037 gcc_unreachable ();
16041 cop1 = CONST0_RTX (mode);
16044 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
16045 operands[1+negate], operands[2-negate]);
16047 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
16048 operands[2-negate]);
16052 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16053 true if we should do zero extension, else sign extension. HIGH_P is
16054 true if we want the N/2 high elements, else the low elements. */
16057 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16059 enum machine_mode imode = GET_MODE (operands[1]);
16060 rtx (*unpack)(rtx, rtx, rtx);
16067 unpack = gen_vec_interleave_highv16qi;
16069 unpack = gen_vec_interleave_lowv16qi;
16073 unpack = gen_vec_interleave_highv8hi;
16075 unpack = gen_vec_interleave_lowv8hi;
16079 unpack = gen_vec_interleave_highv4si;
16081 unpack = gen_vec_interleave_lowv4si;
16084 gcc_unreachable ();
16087 dest = gen_lowpart (imode, operands[0]);
16090 se = force_reg (imode, CONST0_RTX (imode));
16092 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
16093 operands[1], pc_rtx, pc_rtx);
16095 emit_insn (unpack (dest, operands[1], se));
16098 /* This function performs the same task as ix86_expand_sse_unpack,
16099 but with SSE4.1 instructions. */
16102 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16104 enum machine_mode imode = GET_MODE (operands[1]);
16105 rtx (*unpack)(rtx, rtx);
16112 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
16114 unpack = gen_sse4_1_extendv8qiv8hi2;
16118 unpack = gen_sse4_1_zero_extendv4hiv4si2;
16120 unpack = gen_sse4_1_extendv4hiv4si2;
16124 unpack = gen_sse4_1_zero_extendv2siv2di2;
16126 unpack = gen_sse4_1_extendv2siv2di2;
16129 gcc_unreachable ();
16132 dest = operands[0];
16135 /* Shift higher 8 bytes to lower 8 bytes. */
16136 src = gen_reg_rtx (imode);
16137 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
16138 gen_lowpart (TImode, operands[1]),
16144 emit_insn (unpack (dest, src));
16147 /* Expand conditional increment or decrement using adb/sbb instructions.
16148 The default case using setcc followed by the conditional move can be
16149 done by generic code. */
16151 ix86_expand_int_addcc (rtx operands[])
16153 enum rtx_code code = GET_CODE (operands[1]);
16155 rtx val = const0_rtx;
16156 bool fpcmp = false;
16157 enum machine_mode mode = GET_MODE (operands[0]);
16159 ix86_compare_op0 = XEXP (operands[1], 0);
16160 ix86_compare_op1 = XEXP (operands[1], 1);
16161 if (operands[3] != const1_rtx
16162 && operands[3] != constm1_rtx)
16164 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16165 ix86_compare_op1, &compare_op))
16167 code = GET_CODE (compare_op);
16169 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16170 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16173 code = ix86_fp_compare_code_to_integer (code);
16180 PUT_CODE (compare_op,
16181 reverse_condition_maybe_unordered
16182 (GET_CODE (compare_op)));
16184 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16186 PUT_MODE (compare_op, mode);
16188 /* Construct either adc or sbb insn. */
16189 if ((code == LTU) == (operands[3] == constm1_rtx))
16191 switch (GET_MODE (operands[0]))
16194 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
16197 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
16200 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
16203 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16206 gcc_unreachable ();
16211 switch (GET_MODE (operands[0]))
16214 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
16217 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
16220 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
16223 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16226 gcc_unreachable ();
16229 return 1; /* DONE */
16233 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16234 works for floating pointer parameters and nonoffsetable memories.
16235 For pushes, it returns just stack offsets; the values will be saved
16236 in the right order. Maximally three parts are generated. */
16239 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16244 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16246 size = (GET_MODE_SIZE (mode) + 4) / 8;
16248 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16249 gcc_assert (size >= 2 && size <= 4);
16251 /* Optimize constant pool reference to immediates. This is used by fp
16252 moves, that force all constants to memory to allow combining. */
16253 if (MEM_P (operand) && MEM_READONLY_P (operand))
16255 rtx tmp = maybe_get_pool_constant (operand);
16260 if (MEM_P (operand) && !offsettable_memref_p (operand))
16262 /* The only non-offsetable memories we handle are pushes. */
16263 int ok = push_operand (operand, VOIDmode);
16267 operand = copy_rtx (operand);
16268 PUT_MODE (operand, Pmode);
16269 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16273 if (GET_CODE (operand) == CONST_VECTOR)
16275 enum machine_mode imode = int_mode_for_mode (mode);
16276 /* Caution: if we looked through a constant pool memory above,
16277 the operand may actually have a different mode now. That's
16278 ok, since we want to pun this all the way back to an integer. */
16279 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16280 gcc_assert (operand != NULL);
16286 if (mode == DImode)
16287 split_di (&operand, 1, &parts[0], &parts[1]);
16292 if (REG_P (operand))
16294 gcc_assert (reload_completed);
16295 for (i = 0; i < size; i++)
16296 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16298 else if (offsettable_memref_p (operand))
16300 operand = adjust_address (operand, SImode, 0);
16301 parts[0] = operand;
16302 for (i = 1; i < size; i++)
16303 parts[i] = adjust_address (operand, SImode, 4 * i);
16305 else if (GET_CODE (operand) == CONST_DOUBLE)
16310 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16314 real_to_target (l, &r, mode);
16315 parts[3] = gen_int_mode (l[3], SImode);
16316 parts[2] = gen_int_mode (l[2], SImode);
16319 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16320 parts[2] = gen_int_mode (l[2], SImode);
16323 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16326 gcc_unreachable ();
16328 parts[1] = gen_int_mode (l[1], SImode);
16329 parts[0] = gen_int_mode (l[0], SImode);
16332 gcc_unreachable ();
16337 if (mode == TImode)
16338 split_ti (&operand, 1, &parts[0], &parts[1]);
16339 if (mode == XFmode || mode == TFmode)
16341 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16342 if (REG_P (operand))
16344 gcc_assert (reload_completed);
16345 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16346 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16348 else if (offsettable_memref_p (operand))
16350 operand = adjust_address (operand, DImode, 0);
16351 parts[0] = operand;
16352 parts[1] = adjust_address (operand, upper_mode, 8);
16354 else if (GET_CODE (operand) == CONST_DOUBLE)
16359 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16360 real_to_target (l, &r, mode);
16362 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16363 if (HOST_BITS_PER_WIDE_INT >= 64)
16366 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16367 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16370 parts[0] = immed_double_const (l[0], l[1], DImode);
16372 if (upper_mode == SImode)
16373 parts[1] = gen_int_mode (l[2], SImode);
16374 else if (HOST_BITS_PER_WIDE_INT >= 64)
16377 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16378 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16381 parts[1] = immed_double_const (l[2], l[3], DImode);
16384 gcc_unreachable ();
16391 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16392 Return false when normal moves are needed; true when all required
16393 insns have been emitted. Operands 2-4 contain the input values
16394 int the correct order; operands 5-7 contain the output values. */
16397 ix86_split_long_move (rtx operands[])
16402 int collisions = 0;
16403 enum machine_mode mode = GET_MODE (operands[0]);
16404 bool collisionparts[4];
16406 /* The DFmode expanders may ask us to move double.
16407 For 64bit target this is single move. By hiding the fact
16408 here we simplify i386.md splitters. */
16409 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16411 /* Optimize constant pool reference to immediates. This is used by
16412 fp moves, that force all constants to memory to allow combining. */
16414 if (MEM_P (operands[1])
16415 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16416 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16417 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16418 if (push_operand (operands[0], VOIDmode))
16420 operands[0] = copy_rtx (operands[0]);
16421 PUT_MODE (operands[0], Pmode);
16424 operands[0] = gen_lowpart (DImode, operands[0]);
16425 operands[1] = gen_lowpart (DImode, operands[1]);
16426 emit_move_insn (operands[0], operands[1]);
16430 /* The only non-offsettable memory we handle is push. */
16431 if (push_operand (operands[0], VOIDmode))
16434 gcc_assert (!MEM_P (operands[0])
16435 || offsettable_memref_p (operands[0]));
16437 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16438 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16440 /* When emitting push, take care for source operands on the stack. */
16441 if (push && MEM_P (operands[1])
16442 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16444 rtx src_base = XEXP (part[1][nparts - 1], 0);
16446 /* Compensate for the stack decrement by 4. */
16447 if (!TARGET_64BIT && nparts == 3
16448 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
16449 src_base = plus_constant (src_base, 4);
16451 /* src_base refers to the stack pointer and is
16452 automatically decreased by emitted push. */
16453 for (i = 0; i < nparts; i++)
16454 part[1][i] = change_address (part[1][i],
16455 GET_MODE (part[1][i]), src_base);
16458 /* We need to do copy in the right order in case an address register
16459 of the source overlaps the destination. */
16460 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16464 for (i = 0; i < nparts; i++)
16467 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16468 if (collisionparts[i])
16472 /* Collision in the middle part can be handled by reordering. */
16473 if (collisions == 1 && nparts == 3 && collisionparts [1])
16475 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16476 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16478 else if (collisions == 1
16480 && (collisionparts [1] || collisionparts [2]))
16482 if (collisionparts [1])
16484 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16485 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16489 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16490 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16494 /* If there are more collisions, we can't handle it by reordering.
16495 Do an lea to the last part and use only one colliding move. */
16496 else if (collisions > 1)
16502 base = part[0][nparts - 1];
16504 /* Handle the case when the last part isn't valid for lea.
16505 Happens in 64-bit mode storing the 12-byte XFmode. */
16506 if (GET_MODE (base) != Pmode)
16507 base = gen_rtx_REG (Pmode, REGNO (base));
16509 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16510 part[1][0] = replace_equiv_address (part[1][0], base);
16511 for (i = 1; i < nparts; i++)
16513 tmp = plus_constant (base, UNITS_PER_WORD * i);
16514 part[1][i] = replace_equiv_address (part[1][i], tmp);
16525 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16526 emit_insn (gen_addsi3 (stack_pointer_rtx,
16527 stack_pointer_rtx, GEN_INT (-4)));
16528 emit_move_insn (part[0][2], part[1][2]);
16530 else if (nparts == 4)
16532 emit_move_insn (part[0][3], part[1][3]);
16533 emit_move_insn (part[0][2], part[1][2]);
16538 /* In 64bit mode we don't have 32bit push available. In case this is
16539 register, it is OK - we will just use larger counterpart. We also
16540 retype memory - these comes from attempt to avoid REX prefix on
16541 moving of second half of TFmode value. */
16542 if (GET_MODE (part[1][1]) == SImode)
16544 switch (GET_CODE (part[1][1]))
16547 part[1][1] = adjust_address (part[1][1], DImode, 0);
16551 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16555 gcc_unreachable ();
16558 if (GET_MODE (part[1][0]) == SImode)
16559 part[1][0] = part[1][1];
16562 emit_move_insn (part[0][1], part[1][1]);
16563 emit_move_insn (part[0][0], part[1][0]);
16567 /* Choose correct order to not overwrite the source before it is copied. */
16568 if ((REG_P (part[0][0])
16569 && REG_P (part[1][1])
16570 && (REGNO (part[0][0]) == REGNO (part[1][1])
16572 && REGNO (part[0][0]) == REGNO (part[1][2]))
16574 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16576 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16578 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16580 operands[2 + i] = part[0][j];
16581 operands[6 + i] = part[1][j];
16586 for (i = 0; i < nparts; i++)
16588 operands[2 + i] = part[0][i];
16589 operands[6 + i] = part[1][i];
16593 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16594 if (optimize_insn_for_size_p ())
16596 for (j = 0; j < nparts - 1; j++)
16597 if (CONST_INT_P (operands[6 + j])
16598 && operands[6 + j] != const0_rtx
16599 && REG_P (operands[2 + j]))
16600 for (i = j; i < nparts - 1; i++)
16601 if (CONST_INT_P (operands[7 + i])
16602 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16603 operands[7 + i] = operands[2 + j];
16606 for (i = 0; i < nparts; i++)
16607 emit_move_insn (operands[2 + i], operands[6 + i]);
16612 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16613 left shift by a constant, either using a single shift or
16614 a sequence of add instructions. */
16617 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16621 emit_insn ((mode == DImode
16623 : gen_adddi3) (operand, operand, operand));
16625 else if (!optimize_insn_for_size_p ()
16626 && count * ix86_cost->add <= ix86_cost->shift_const)
16629 for (i=0; i<count; i++)
16631 emit_insn ((mode == DImode
16633 : gen_adddi3) (operand, operand, operand));
16637 emit_insn ((mode == DImode
16639 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16643 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16645 rtx low[2], high[2];
16647 const int single_width = mode == DImode ? 32 : 64;
16649 if (CONST_INT_P (operands[2]))
16651 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16652 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16654 if (count >= single_width)
16656 emit_move_insn (high[0], low[1]);
16657 emit_move_insn (low[0], const0_rtx);
16659 if (count > single_width)
16660 ix86_expand_ashl_const (high[0], count - single_width, mode);
16664 if (!rtx_equal_p (operands[0], operands[1]))
16665 emit_move_insn (operands[0], operands[1]);
16666 emit_insn ((mode == DImode
16668 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16669 ix86_expand_ashl_const (low[0], count, mode);
16674 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16676 if (operands[1] == const1_rtx)
16678 /* Assuming we've chosen a QImode capable registers, then 1 << N
16679 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16680 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16682 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16684 ix86_expand_clear (low[0]);
16685 ix86_expand_clear (high[0]);
16686 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16688 d = gen_lowpart (QImode, low[0]);
16689 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16690 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16691 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16693 d = gen_lowpart (QImode, high[0]);
16694 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16695 s = gen_rtx_NE (QImode, flags, const0_rtx);
16696 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16699 /* Otherwise, we can get the same results by manually performing
16700 a bit extract operation on bit 5/6, and then performing the two
16701 shifts. The two methods of getting 0/1 into low/high are exactly
16702 the same size. Avoiding the shift in the bit extract case helps
16703 pentium4 a bit; no one else seems to care much either way. */
16708 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16709 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16711 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16712 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16714 emit_insn ((mode == DImode
16716 : gen_lshrdi3) (high[0], high[0],
16717 GEN_INT (mode == DImode ? 5 : 6)));
16718 emit_insn ((mode == DImode
16720 : gen_anddi3) (high[0], high[0], const1_rtx));
16721 emit_move_insn (low[0], high[0]);
16722 emit_insn ((mode == DImode
16724 : gen_xordi3) (low[0], low[0], const1_rtx));
16727 emit_insn ((mode == DImode
16729 : gen_ashldi3) (low[0], low[0], operands[2]));
16730 emit_insn ((mode == DImode
16732 : gen_ashldi3) (high[0], high[0], operands[2]));
16736 if (operands[1] == constm1_rtx)
16738 /* For -1 << N, we can avoid the shld instruction, because we
16739 know that we're shifting 0...31/63 ones into a -1. */
16740 emit_move_insn (low[0], constm1_rtx);
16741 if (optimize_insn_for_size_p ())
16742 emit_move_insn (high[0], low[0]);
16744 emit_move_insn (high[0], constm1_rtx);
16748 if (!rtx_equal_p (operands[0], operands[1]))
16749 emit_move_insn (operands[0], operands[1]);
16751 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16752 emit_insn ((mode == DImode
16754 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16757 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16759 if (TARGET_CMOVE && scratch)
16761 ix86_expand_clear (scratch);
16762 emit_insn ((mode == DImode
16763 ? gen_x86_shift_adj_1
16764 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16768 emit_insn ((mode == DImode
16769 ? gen_x86_shift_adj_2
16770 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16774 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16776 rtx low[2], high[2];
16778 const int single_width = mode == DImode ? 32 : 64;
16780 if (CONST_INT_P (operands[2]))
16782 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16783 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16785 if (count == single_width * 2 - 1)
16787 emit_move_insn (high[0], high[1]);
16788 emit_insn ((mode == DImode
16790 : gen_ashrdi3) (high[0], high[0],
16791 GEN_INT (single_width - 1)));
16792 emit_move_insn (low[0], high[0]);
16795 else if (count >= single_width)
16797 emit_move_insn (low[0], high[1]);
16798 emit_move_insn (high[0], low[0]);
16799 emit_insn ((mode == DImode
16801 : gen_ashrdi3) (high[0], high[0],
16802 GEN_INT (single_width - 1)));
16803 if (count > single_width)
16804 emit_insn ((mode == DImode
16806 : gen_ashrdi3) (low[0], low[0],
16807 GEN_INT (count - single_width)));
16811 if (!rtx_equal_p (operands[0], operands[1]))
16812 emit_move_insn (operands[0], operands[1]);
16813 emit_insn ((mode == DImode
16815 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16816 emit_insn ((mode == DImode
16818 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16823 if (!rtx_equal_p (operands[0], operands[1]))
16824 emit_move_insn (operands[0], operands[1]);
16826 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16828 emit_insn ((mode == DImode
16830 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16831 emit_insn ((mode == DImode
16833 : gen_ashrdi3) (high[0], high[0], operands[2]));
16835 if (TARGET_CMOVE && scratch)
16837 emit_move_insn (scratch, high[0]);
16838 emit_insn ((mode == DImode
16840 : gen_ashrdi3) (scratch, scratch,
16841 GEN_INT (single_width - 1)));
16842 emit_insn ((mode == DImode
16843 ? gen_x86_shift_adj_1
16844 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16848 emit_insn ((mode == DImode
16849 ? gen_x86_shift_adj_3
16850 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16855 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16857 rtx low[2], high[2];
16859 const int single_width = mode == DImode ? 32 : 64;
16861 if (CONST_INT_P (operands[2]))
16863 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16864 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16866 if (count >= single_width)
16868 emit_move_insn (low[0], high[1]);
16869 ix86_expand_clear (high[0]);
16871 if (count > single_width)
16872 emit_insn ((mode == DImode
16874 : gen_lshrdi3) (low[0], low[0],
16875 GEN_INT (count - single_width)));
16879 if (!rtx_equal_p (operands[0], operands[1]))
16880 emit_move_insn (operands[0], operands[1]);
16881 emit_insn ((mode == DImode
16883 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16884 emit_insn ((mode == DImode
16886 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16891 if (!rtx_equal_p (operands[0], operands[1]))
16892 emit_move_insn (operands[0], operands[1]);
16894 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16896 emit_insn ((mode == DImode
16898 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16899 emit_insn ((mode == DImode
16901 : gen_lshrdi3) (high[0], high[0], operands[2]));
16903 /* Heh. By reversing the arguments, we can reuse this pattern. */
16904 if (TARGET_CMOVE && scratch)
16906 ix86_expand_clear (scratch);
16907 emit_insn ((mode == DImode
16908 ? gen_x86_shift_adj_1
16909 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16913 emit_insn ((mode == DImode
16914 ? gen_x86_shift_adj_2
16915 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16919 /* Predict just emitted jump instruction to be taken with probability PROB. */
16921 predict_jump (int prob)
16923 rtx insn = get_last_insn ();
16924 gcc_assert (JUMP_P (insn));
16925 add_reg_note (insn, REG_BR_PROB, GEN_INT (prob));
16928 /* Helper function for the string operations below. Dest VARIABLE whether
16929 it is aligned to VALUE bytes. If true, jump to the label. */
16931 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16933 rtx label = gen_label_rtx ();
16934 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16935 if (GET_MODE (variable) == DImode)
16936 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16938 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16939 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16942 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16944 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16948 /* Adjust COUNTER by the VALUE. */
16950 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16952 if (GET_MODE (countreg) == DImode)
16953 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16955 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16958 /* Zero extend possibly SImode EXP to Pmode register. */
16960 ix86_zero_extend_to_Pmode (rtx exp)
16963 if (GET_MODE (exp) == VOIDmode)
16964 return force_reg (Pmode, exp);
16965 if (GET_MODE (exp) == Pmode)
16966 return copy_to_mode_reg (Pmode, exp);
16967 r = gen_reg_rtx (Pmode);
16968 emit_insn (gen_zero_extendsidi2 (r, exp));
16972 /* Divide COUNTREG by SCALE. */
16974 scale_counter (rtx countreg, int scale)
16980 if (CONST_INT_P (countreg))
16981 return GEN_INT (INTVAL (countreg) / scale);
16982 gcc_assert (REG_P (countreg));
16984 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16985 GEN_INT (exact_log2 (scale)),
16986 NULL, 1, OPTAB_DIRECT);
16990 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16991 DImode for constant loop counts. */
16993 static enum machine_mode
16994 counter_mode (rtx count_exp)
16996 if (GET_MODE (count_exp) != VOIDmode)
16997 return GET_MODE (count_exp);
16998 if (!CONST_INT_P (count_exp))
17000 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
17005 /* When SRCPTR is non-NULL, output simple loop to move memory
17006 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17007 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17008 equivalent loop to set memory by VALUE (supposed to be in MODE).
17010 The size is rounded down to whole number of chunk size moved at once.
17011 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17015 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
17016 rtx destptr, rtx srcptr, rtx value,
17017 rtx count, enum machine_mode mode, int unroll,
17020 rtx out_label, top_label, iter, tmp;
17021 enum machine_mode iter_mode = counter_mode (count);
17022 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
17023 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
17029 top_label = gen_label_rtx ();
17030 out_label = gen_label_rtx ();
17031 iter = gen_reg_rtx (iter_mode);
17033 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
17034 NULL, 1, OPTAB_DIRECT);
17035 /* Those two should combine. */
17036 if (piece_size == const1_rtx)
17038 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
17040 predict_jump (REG_BR_PROB_BASE * 10 / 100);
17042 emit_move_insn (iter, const0_rtx);
17044 emit_label (top_label);
17046 tmp = convert_modes (Pmode, iter_mode, iter, true);
17047 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
17048 destmem = change_address (destmem, mode, x_addr);
17052 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
17053 srcmem = change_address (srcmem, mode, y_addr);
17055 /* When unrolling for chips that reorder memory reads and writes,
17056 we can save registers by using single temporary.
17057 Also using 4 temporaries is overkill in 32bit mode. */
17058 if (!TARGET_64BIT && 0)
17060 for (i = 0; i < unroll; i++)
17065 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17067 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17069 emit_move_insn (destmem, srcmem);
17075 gcc_assert (unroll <= 4);
17076 for (i = 0; i < unroll; i++)
17078 tmpreg[i] = gen_reg_rtx (mode);
17082 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17084 emit_move_insn (tmpreg[i], srcmem);
17086 for (i = 0; i < unroll; i++)
17091 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17093 emit_move_insn (destmem, tmpreg[i]);
17098 for (i = 0; i < unroll; i++)
17102 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17103 emit_move_insn (destmem, value);
17106 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
17107 true, OPTAB_LIB_WIDEN);
17109 emit_move_insn (iter, tmp);
17111 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
17113 if (expected_size != -1)
17115 expected_size /= GET_MODE_SIZE (mode) * unroll;
17116 if (expected_size == 0)
17118 else if (expected_size > REG_BR_PROB_BASE)
17119 predict_jump (REG_BR_PROB_BASE - 1);
17121 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17124 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17125 iter = ix86_zero_extend_to_Pmode (iter);
17126 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17127 true, OPTAB_LIB_WIDEN);
17128 if (tmp != destptr)
17129 emit_move_insn (destptr, tmp);
17132 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17133 true, OPTAB_LIB_WIDEN);
17135 emit_move_insn (srcptr, tmp);
17137 emit_label (out_label);
17140 /* Output "rep; mov" instruction.
17141 Arguments have same meaning as for previous function */
17143 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17144 rtx destptr, rtx srcptr,
17146 enum machine_mode mode)
17152 /* If the size is known, it is shorter to use rep movs. */
17153 if (mode == QImode && CONST_INT_P (count)
17154 && !(INTVAL (count) & 3))
17157 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17158 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17159 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17160 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17161 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17162 if (mode != QImode)
17164 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17165 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17166 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17167 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17168 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17169 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17173 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17174 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17176 if (CONST_INT_P (count))
17178 count = GEN_INT (INTVAL (count)
17179 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17180 destmem = shallow_copy_rtx (destmem);
17181 srcmem = shallow_copy_rtx (srcmem);
17182 set_mem_size (destmem, count);
17183 set_mem_size (srcmem, count);
17187 if (MEM_SIZE (destmem))
17188 set_mem_size (destmem, NULL_RTX);
17189 if (MEM_SIZE (srcmem))
17190 set_mem_size (srcmem, NULL_RTX);
17192 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17196 /* Output "rep; stos" instruction.
17197 Arguments have same meaning as for previous function */
17199 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17200 rtx count, enum machine_mode mode,
17206 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17207 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17208 value = force_reg (mode, gen_lowpart (mode, value));
17209 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17210 if (mode != QImode)
17212 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17213 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17214 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17217 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17218 if (orig_value == const0_rtx && CONST_INT_P (count))
17220 count = GEN_INT (INTVAL (count)
17221 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17222 destmem = shallow_copy_rtx (destmem);
17223 set_mem_size (destmem, count);
17225 else if (MEM_SIZE (destmem))
17226 set_mem_size (destmem, NULL_RTX);
17227 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17231 emit_strmov (rtx destmem, rtx srcmem,
17232 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17234 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17235 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17236 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17239 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17241 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17242 rtx destptr, rtx srcptr, rtx count, int max_size)
17245 if (CONST_INT_P (count))
17247 HOST_WIDE_INT countval = INTVAL (count);
17250 if ((countval & 0x10) && max_size > 16)
17254 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17255 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17258 gcc_unreachable ();
17261 if ((countval & 0x08) && max_size > 8)
17264 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17267 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17268 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17272 if ((countval & 0x04) && max_size > 4)
17274 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17277 if ((countval & 0x02) && max_size > 2)
17279 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17282 if ((countval & 0x01) && max_size > 1)
17284 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17291 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17292 count, 1, OPTAB_DIRECT);
17293 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17294 count, QImode, 1, 4);
17298 /* When there are stringops, we can cheaply increase dest and src pointers.
17299 Otherwise we save code size by maintaining offset (zero is readily
17300 available from preceding rep operation) and using x86 addressing modes.
17302 if (TARGET_SINGLE_STRINGOP)
17306 rtx label = ix86_expand_aligntest (count, 4, true);
17307 src = change_address (srcmem, SImode, srcptr);
17308 dest = change_address (destmem, SImode, destptr);
17309 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17310 emit_label (label);
17311 LABEL_NUSES (label) = 1;
17315 rtx label = ix86_expand_aligntest (count, 2, true);
17316 src = change_address (srcmem, HImode, srcptr);
17317 dest = change_address (destmem, HImode, destptr);
17318 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17319 emit_label (label);
17320 LABEL_NUSES (label) = 1;
17324 rtx label = ix86_expand_aligntest (count, 1, true);
17325 src = change_address (srcmem, QImode, srcptr);
17326 dest = change_address (destmem, QImode, destptr);
17327 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17328 emit_label (label);
17329 LABEL_NUSES (label) = 1;
17334 rtx offset = force_reg (Pmode, const0_rtx);
17339 rtx label = ix86_expand_aligntest (count, 4, true);
17340 src = change_address (srcmem, SImode, srcptr);
17341 dest = change_address (destmem, SImode, destptr);
17342 emit_move_insn (dest, src);
17343 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17344 true, OPTAB_LIB_WIDEN);
17346 emit_move_insn (offset, tmp);
17347 emit_label (label);
17348 LABEL_NUSES (label) = 1;
17352 rtx label = ix86_expand_aligntest (count, 2, true);
17353 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17354 src = change_address (srcmem, HImode, tmp);
17355 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17356 dest = change_address (destmem, HImode, tmp);
17357 emit_move_insn (dest, src);
17358 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17359 true, OPTAB_LIB_WIDEN);
17361 emit_move_insn (offset, tmp);
17362 emit_label (label);
17363 LABEL_NUSES (label) = 1;
17367 rtx label = ix86_expand_aligntest (count, 1, true);
17368 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17369 src = change_address (srcmem, QImode, tmp);
17370 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17371 dest = change_address (destmem, QImode, tmp);
17372 emit_move_insn (dest, src);
17373 emit_label (label);
17374 LABEL_NUSES (label) = 1;
17379 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17381 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17382 rtx count, int max_size)
17385 expand_simple_binop (counter_mode (count), AND, count,
17386 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17387 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17388 gen_lowpart (QImode, value), count, QImode,
17392 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17394 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17398 if (CONST_INT_P (count))
17400 HOST_WIDE_INT countval = INTVAL (count);
17403 if ((countval & 0x10) && max_size > 16)
17407 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17408 emit_insn (gen_strset (destptr, dest, value));
17409 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17410 emit_insn (gen_strset (destptr, dest, value));
17413 gcc_unreachable ();
17416 if ((countval & 0x08) && max_size > 8)
17420 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17421 emit_insn (gen_strset (destptr, dest, value));
17425 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17426 emit_insn (gen_strset (destptr, dest, value));
17427 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17428 emit_insn (gen_strset (destptr, dest, value));
17432 if ((countval & 0x04) && max_size > 4)
17434 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17435 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17438 if ((countval & 0x02) && max_size > 2)
17440 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17441 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17444 if ((countval & 0x01) && max_size > 1)
17446 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17447 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17454 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17459 rtx label = ix86_expand_aligntest (count, 16, true);
17462 dest = change_address (destmem, DImode, destptr);
17463 emit_insn (gen_strset (destptr, dest, value));
17464 emit_insn (gen_strset (destptr, dest, value));
17468 dest = change_address (destmem, SImode, destptr);
17469 emit_insn (gen_strset (destptr, dest, value));
17470 emit_insn (gen_strset (destptr, dest, value));
17471 emit_insn (gen_strset (destptr, dest, value));
17472 emit_insn (gen_strset (destptr, dest, value));
17474 emit_label (label);
17475 LABEL_NUSES (label) = 1;
17479 rtx label = ix86_expand_aligntest (count, 8, true);
17482 dest = change_address (destmem, DImode, destptr);
17483 emit_insn (gen_strset (destptr, dest, value));
17487 dest = change_address (destmem, SImode, destptr);
17488 emit_insn (gen_strset (destptr, dest, value));
17489 emit_insn (gen_strset (destptr, dest, value));
17491 emit_label (label);
17492 LABEL_NUSES (label) = 1;
17496 rtx label = ix86_expand_aligntest (count, 4, true);
17497 dest = change_address (destmem, SImode, destptr);
17498 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17499 emit_label (label);
17500 LABEL_NUSES (label) = 1;
17504 rtx label = ix86_expand_aligntest (count, 2, true);
17505 dest = change_address (destmem, HImode, destptr);
17506 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17507 emit_label (label);
17508 LABEL_NUSES (label) = 1;
17512 rtx label = ix86_expand_aligntest (count, 1, true);
17513 dest = change_address (destmem, QImode, destptr);
17514 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17515 emit_label (label);
17516 LABEL_NUSES (label) = 1;
17520 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17521 DESIRED_ALIGNMENT. */
17523 expand_movmem_prologue (rtx destmem, rtx srcmem,
17524 rtx destptr, rtx srcptr, rtx count,
17525 int align, int desired_alignment)
17527 if (align <= 1 && desired_alignment > 1)
17529 rtx label = ix86_expand_aligntest (destptr, 1, false);
17530 srcmem = change_address (srcmem, QImode, srcptr);
17531 destmem = change_address (destmem, QImode, destptr);
17532 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17533 ix86_adjust_counter (count, 1);
17534 emit_label (label);
17535 LABEL_NUSES (label) = 1;
17537 if (align <= 2 && desired_alignment > 2)
17539 rtx label = ix86_expand_aligntest (destptr, 2, false);
17540 srcmem = change_address (srcmem, HImode, srcptr);
17541 destmem = change_address (destmem, HImode, destptr);
17542 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17543 ix86_adjust_counter (count, 2);
17544 emit_label (label);
17545 LABEL_NUSES (label) = 1;
17547 if (align <= 4 && desired_alignment > 4)
17549 rtx label = ix86_expand_aligntest (destptr, 4, false);
17550 srcmem = change_address (srcmem, SImode, srcptr);
17551 destmem = change_address (destmem, SImode, destptr);
17552 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17553 ix86_adjust_counter (count, 4);
17554 emit_label (label);
17555 LABEL_NUSES (label) = 1;
17557 gcc_assert (desired_alignment <= 8);
17560 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17561 ALIGN_BYTES is how many bytes need to be copied. */
17563 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17564 int desired_align, int align_bytes)
17567 rtx src_size, dst_size;
17569 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17570 if (src_align_bytes >= 0)
17571 src_align_bytes = desired_align - src_align_bytes;
17572 src_size = MEM_SIZE (src);
17573 dst_size = MEM_SIZE (dst);
17574 if (align_bytes & 1)
17576 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17577 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17579 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17581 if (align_bytes & 2)
17583 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17584 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17585 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17586 set_mem_align (dst, 2 * BITS_PER_UNIT);
17587 if (src_align_bytes >= 0
17588 && (src_align_bytes & 1) == (align_bytes & 1)
17589 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17590 set_mem_align (src, 2 * BITS_PER_UNIT);
17592 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17594 if (align_bytes & 4)
17596 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17597 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17598 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17599 set_mem_align (dst, 4 * BITS_PER_UNIT);
17600 if (src_align_bytes >= 0)
17602 unsigned int src_align = 0;
17603 if ((src_align_bytes & 3) == (align_bytes & 3))
17605 else if ((src_align_bytes & 1) == (align_bytes & 1))
17607 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17608 set_mem_align (src, src_align * BITS_PER_UNIT);
17611 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17613 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17614 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17615 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17616 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17617 if (src_align_bytes >= 0)
17619 unsigned int src_align = 0;
17620 if ((src_align_bytes & 7) == (align_bytes & 7))
17622 else if ((src_align_bytes & 3) == (align_bytes & 3))
17624 else if ((src_align_bytes & 1) == (align_bytes & 1))
17626 if (src_align > (unsigned int) desired_align)
17627 src_align = desired_align;
17628 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17629 set_mem_align (src, src_align * BITS_PER_UNIT);
17632 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17634 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17639 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17640 DESIRED_ALIGNMENT. */
17642 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17643 int align, int desired_alignment)
17645 if (align <= 1 && desired_alignment > 1)
17647 rtx label = ix86_expand_aligntest (destptr, 1, false);
17648 destmem = change_address (destmem, QImode, destptr);
17649 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17650 ix86_adjust_counter (count, 1);
17651 emit_label (label);
17652 LABEL_NUSES (label) = 1;
17654 if (align <= 2 && desired_alignment > 2)
17656 rtx label = ix86_expand_aligntest (destptr, 2, false);
17657 destmem = change_address (destmem, HImode, destptr);
17658 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17659 ix86_adjust_counter (count, 2);
17660 emit_label (label);
17661 LABEL_NUSES (label) = 1;
17663 if (align <= 4 && desired_alignment > 4)
17665 rtx label = ix86_expand_aligntest (destptr, 4, false);
17666 destmem = change_address (destmem, SImode, destptr);
17667 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17668 ix86_adjust_counter (count, 4);
17669 emit_label (label);
17670 LABEL_NUSES (label) = 1;
17672 gcc_assert (desired_alignment <= 8);
17675 /* Set enough from DST to align DST known to by aligned by ALIGN to
17676 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17678 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17679 int desired_align, int align_bytes)
17682 rtx dst_size = MEM_SIZE (dst);
17683 if (align_bytes & 1)
17685 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17687 emit_insn (gen_strset (destreg, dst,
17688 gen_lowpart (QImode, value)));
17690 if (align_bytes & 2)
17692 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17693 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17694 set_mem_align (dst, 2 * BITS_PER_UNIT);
17696 emit_insn (gen_strset (destreg, dst,
17697 gen_lowpart (HImode, value)));
17699 if (align_bytes & 4)
17701 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17702 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17703 set_mem_align (dst, 4 * BITS_PER_UNIT);
17705 emit_insn (gen_strset (destreg, dst,
17706 gen_lowpart (SImode, value)));
17708 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17709 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17710 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17712 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17716 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17717 static enum stringop_alg
17718 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17719 int *dynamic_check)
17721 const struct stringop_algs * algs;
17722 bool optimize_for_speed;
17723 /* Algorithms using the rep prefix want at least edi and ecx;
17724 additionally, memset wants eax and memcpy wants esi. Don't
17725 consider such algorithms if the user has appropriated those
17726 registers for their own purposes. */
17727 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17729 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17731 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17732 || (alg != rep_prefix_1_byte \
17733 && alg != rep_prefix_4_byte \
17734 && alg != rep_prefix_8_byte))
17735 const struct processor_costs *cost;
17737 /* Even if the string operation call is cold, we still might spend a lot
17738 of time processing large blocks. */
17739 if (optimize_function_for_size_p (cfun)
17740 || (optimize_insn_for_size_p ()
17741 && expected_size != -1 && expected_size < 256))
17742 optimize_for_speed = false;
17744 optimize_for_speed = true;
17746 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17748 *dynamic_check = -1;
17750 algs = &cost->memset[TARGET_64BIT != 0];
17752 algs = &cost->memcpy[TARGET_64BIT != 0];
17753 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17754 return stringop_alg;
17755 /* rep; movq or rep; movl is the smallest variant. */
17756 else if (!optimize_for_speed)
17758 if (!count || (count & 3))
17759 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17761 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17763 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17765 else if (expected_size != -1 && expected_size < 4)
17766 return loop_1_byte;
17767 else if (expected_size != -1)
17770 enum stringop_alg alg = libcall;
17771 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17773 /* We get here if the algorithms that were not libcall-based
17774 were rep-prefix based and we are unable to use rep prefixes
17775 based on global register usage. Break out of the loop and
17776 use the heuristic below. */
17777 if (algs->size[i].max == 0)
17779 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17781 enum stringop_alg candidate = algs->size[i].alg;
17783 if (candidate != libcall && ALG_USABLE_P (candidate))
17785 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17786 last non-libcall inline algorithm. */
17787 if (TARGET_INLINE_ALL_STRINGOPS)
17789 /* When the current size is best to be copied by a libcall,
17790 but we are still forced to inline, run the heuristic below
17791 that will pick code for medium sized blocks. */
17792 if (alg != libcall)
17796 else if (ALG_USABLE_P (candidate))
17800 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17802 /* When asked to inline the call anyway, try to pick meaningful choice.
17803 We look for maximal size of block that is faster to copy by hand and
17804 take blocks of at most of that size guessing that average size will
17805 be roughly half of the block.
17807 If this turns out to be bad, we might simply specify the preferred
17808 choice in ix86_costs. */
17809 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17810 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17813 enum stringop_alg alg;
17815 bool any_alg_usable_p = true;
17817 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17819 enum stringop_alg candidate = algs->size[i].alg;
17820 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17822 if (candidate != libcall && candidate
17823 && ALG_USABLE_P (candidate))
17824 max = algs->size[i].max;
17826 /* If there aren't any usable algorithms, then recursing on
17827 smaller sizes isn't going to find anything. Just return the
17828 simple byte-at-a-time copy loop. */
17829 if (!any_alg_usable_p)
17831 /* Pick something reasonable. */
17832 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17833 *dynamic_check = 128;
17834 return loop_1_byte;
17838 alg = decide_alg (count, max / 2, memset, dynamic_check);
17839 gcc_assert (*dynamic_check == -1);
17840 gcc_assert (alg != libcall);
17841 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17842 *dynamic_check = max;
17845 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17846 #undef ALG_USABLE_P
17849 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17850 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17852 decide_alignment (int align,
17853 enum stringop_alg alg,
17856 int desired_align = 0;
17860 gcc_unreachable ();
17862 case unrolled_loop:
17863 desired_align = GET_MODE_SIZE (Pmode);
17865 case rep_prefix_8_byte:
17868 case rep_prefix_4_byte:
17869 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17870 copying whole cacheline at once. */
17871 if (TARGET_PENTIUMPRO)
17876 case rep_prefix_1_byte:
17877 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17878 copying whole cacheline at once. */
17879 if (TARGET_PENTIUMPRO)
17893 if (desired_align < align)
17894 desired_align = align;
17895 if (expected_size != -1 && expected_size < 4)
17896 desired_align = align;
17897 return desired_align;
17900 /* Return the smallest power of 2 greater than VAL. */
17902 smallest_pow2_greater_than (int val)
17910 /* Expand string move (memcpy) operation. Use i386 string operations when
17911 profitable. expand_setmem contains similar code. The code depends upon
17912 architecture, block size and alignment, but always has the same
17915 1) Prologue guard: Conditional that jumps up to epilogues for small
17916 blocks that can be handled by epilogue alone. This is faster but
17917 also needed for correctness, since prologue assume the block is larger
17918 than the desired alignment.
17920 Optional dynamic check for size and libcall for large
17921 blocks is emitted here too, with -minline-stringops-dynamically.
17923 2) Prologue: copy first few bytes in order to get destination aligned
17924 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17925 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17926 We emit either a jump tree on power of two sized blocks, or a byte loop.
17928 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17929 with specified algorithm.
17931 4) Epilogue: code copying tail of the block that is too small to be
17932 handled by main body (or up to size guarded by prologue guard). */
17935 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17936 rtx expected_align_exp, rtx expected_size_exp)
17942 rtx jump_around_label = NULL;
17943 HOST_WIDE_INT align = 1;
17944 unsigned HOST_WIDE_INT count = 0;
17945 HOST_WIDE_INT expected_size = -1;
17946 int size_needed = 0, epilogue_size_needed;
17947 int desired_align = 0, align_bytes = 0;
17948 enum stringop_alg alg;
17950 bool need_zero_guard = false;
17952 if (CONST_INT_P (align_exp))
17953 align = INTVAL (align_exp);
17954 /* i386 can do misaligned access on reasonably increased cost. */
17955 if (CONST_INT_P (expected_align_exp)
17956 && INTVAL (expected_align_exp) > align)
17957 align = INTVAL (expected_align_exp);
17958 /* ALIGN is the minimum of destination and source alignment, but we care here
17959 just about destination alignment. */
17960 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17961 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17963 if (CONST_INT_P (count_exp))
17964 count = expected_size = INTVAL (count_exp);
17965 if (CONST_INT_P (expected_size_exp) && count == 0)
17966 expected_size = INTVAL (expected_size_exp);
17968 /* Make sure we don't need to care about overflow later on. */
17969 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17972 /* Step 0: Decide on preferred algorithm, desired alignment and
17973 size of chunks to be copied by main loop. */
17975 alg = decide_alg (count, expected_size, false, &dynamic_check);
17976 desired_align = decide_alignment (align, alg, expected_size);
17978 if (!TARGET_ALIGN_STRINGOPS)
17979 align = desired_align;
17981 if (alg == libcall)
17983 gcc_assert (alg != no_stringop);
17985 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
17986 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17987 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
17992 gcc_unreachable ();
17994 need_zero_guard = true;
17995 size_needed = GET_MODE_SIZE (Pmode);
17997 case unrolled_loop:
17998 need_zero_guard = true;
17999 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
18001 case rep_prefix_8_byte:
18004 case rep_prefix_4_byte:
18007 case rep_prefix_1_byte:
18011 need_zero_guard = true;
18016 epilogue_size_needed = size_needed;
18018 /* Step 1: Prologue guard. */
18020 /* Alignment code needs count to be in register. */
18021 if (CONST_INT_P (count_exp) && desired_align > align)
18023 if (INTVAL (count_exp) > desired_align
18024 && INTVAL (count_exp) > size_needed)
18027 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18028 if (align_bytes <= 0)
18031 align_bytes = desired_align - align_bytes;
18033 if (align_bytes == 0)
18034 count_exp = force_reg (counter_mode (count_exp), count_exp);
18036 gcc_assert (desired_align >= 1 && align >= 1);
18038 /* Ensure that alignment prologue won't copy past end of block. */
18039 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18041 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18042 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18043 Make sure it is power of 2. */
18044 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18048 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18050 /* If main algorithm works on QImode, no epilogue is needed.
18051 For small sizes just don't align anything. */
18052 if (size_needed == 1)
18053 desired_align = align;
18060 label = gen_label_rtx ();
18061 emit_cmp_and_jump_insns (count_exp,
18062 GEN_INT (epilogue_size_needed),
18063 LTU, 0, counter_mode (count_exp), 1, label);
18064 if (expected_size == -1 || expected_size < epilogue_size_needed)
18065 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18067 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18071 /* Emit code to decide on runtime whether library call or inline should be
18073 if (dynamic_check != -1)
18075 if (CONST_INT_P (count_exp))
18077 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
18079 emit_block_move_via_libcall (dst, src, count_exp, false);
18080 count_exp = const0_rtx;
18086 rtx hot_label = gen_label_rtx ();
18087 jump_around_label = gen_label_rtx ();
18088 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18089 LEU, 0, GET_MODE (count_exp), 1, hot_label);
18090 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18091 emit_block_move_via_libcall (dst, src, count_exp, false);
18092 emit_jump (jump_around_label);
18093 emit_label (hot_label);
18097 /* Step 2: Alignment prologue. */
18099 if (desired_align > align)
18101 if (align_bytes == 0)
18103 /* Except for the first move in epilogue, we no longer know
18104 constant offset in aliasing info. It don't seems to worth
18105 the pain to maintain it for the first move, so throw away
18107 src = change_address (src, BLKmode, srcreg);
18108 dst = change_address (dst, BLKmode, destreg);
18109 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
18114 /* If we know how many bytes need to be stored before dst is
18115 sufficiently aligned, maintain aliasing info accurately. */
18116 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
18117 desired_align, align_bytes);
18118 count_exp = plus_constant (count_exp, -align_bytes);
18119 count -= align_bytes;
18121 if (need_zero_guard
18122 && (count < (unsigned HOST_WIDE_INT) size_needed
18123 || (align_bytes == 0
18124 && count < ((unsigned HOST_WIDE_INT) size_needed
18125 + desired_align - align))))
18127 /* It is possible that we copied enough so the main loop will not
18129 gcc_assert (size_needed > 1);
18130 if (label == NULL_RTX)
18131 label = gen_label_rtx ();
18132 emit_cmp_and_jump_insns (count_exp,
18133 GEN_INT (size_needed),
18134 LTU, 0, counter_mode (count_exp), 1, label);
18135 if (expected_size == -1
18136 || expected_size < (desired_align - align) / 2 + size_needed)
18137 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18139 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18142 if (label && size_needed == 1)
18144 emit_label (label);
18145 LABEL_NUSES (label) = 1;
18147 epilogue_size_needed = 1;
18149 else if (label == NULL_RTX)
18150 epilogue_size_needed = size_needed;
18152 /* Step 3: Main loop. */
18158 gcc_unreachable ();
18160 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18161 count_exp, QImode, 1, expected_size);
18164 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18165 count_exp, Pmode, 1, expected_size);
18167 case unrolled_loop:
18168 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18169 registers for 4 temporaries anyway. */
18170 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18171 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18174 case rep_prefix_8_byte:
18175 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18178 case rep_prefix_4_byte:
18179 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18182 case rep_prefix_1_byte:
18183 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18187 /* Adjust properly the offset of src and dest memory for aliasing. */
18188 if (CONST_INT_P (count_exp))
18190 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18191 (count / size_needed) * size_needed);
18192 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18193 (count / size_needed) * size_needed);
18197 src = change_address (src, BLKmode, srcreg);
18198 dst = change_address (dst, BLKmode, destreg);
18201 /* Step 4: Epilogue to copy the remaining bytes. */
18205 /* When the main loop is done, COUNT_EXP might hold original count,
18206 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18207 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18208 bytes. Compensate if needed. */
18210 if (size_needed < epilogue_size_needed)
18213 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18214 GEN_INT (size_needed - 1), count_exp, 1,
18216 if (tmp != count_exp)
18217 emit_move_insn (count_exp, tmp);
18219 emit_label (label);
18220 LABEL_NUSES (label) = 1;
18223 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18224 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18225 epilogue_size_needed);
18226 if (jump_around_label)
18227 emit_label (jump_around_label);
18231 /* Helper function for memcpy. For QImode value 0xXY produce
18232 0xXYXYXYXY of wide specified by MODE. This is essentially
18233 a * 0x10101010, but we can do slightly better than
18234 synth_mult by unwinding the sequence by hand on CPUs with
18237 promote_duplicated_reg (enum machine_mode mode, rtx val)
18239 enum machine_mode valmode = GET_MODE (val);
18241 int nops = mode == DImode ? 3 : 2;
18243 gcc_assert (mode == SImode || mode == DImode);
18244 if (val == const0_rtx)
18245 return copy_to_mode_reg (mode, const0_rtx);
18246 if (CONST_INT_P (val))
18248 HOST_WIDE_INT v = INTVAL (val) & 255;
18252 if (mode == DImode)
18253 v |= (v << 16) << 16;
18254 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18257 if (valmode == VOIDmode)
18259 if (valmode != QImode)
18260 val = gen_lowpart (QImode, val);
18261 if (mode == QImode)
18263 if (!TARGET_PARTIAL_REG_STALL)
18265 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18266 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18267 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18268 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18270 rtx reg = convert_modes (mode, QImode, val, true);
18271 tmp = promote_duplicated_reg (mode, const1_rtx);
18272 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18277 rtx reg = convert_modes (mode, QImode, val, true);
18279 if (!TARGET_PARTIAL_REG_STALL)
18280 if (mode == SImode)
18281 emit_insn (gen_movsi_insv_1 (reg, reg));
18283 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18286 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18287 NULL, 1, OPTAB_DIRECT);
18289 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18291 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18292 NULL, 1, OPTAB_DIRECT);
18293 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18294 if (mode == SImode)
18296 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18297 NULL, 1, OPTAB_DIRECT);
18298 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18303 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18304 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18305 alignment from ALIGN to DESIRED_ALIGN. */
18307 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18312 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18313 promoted_val = promote_duplicated_reg (DImode, val);
18314 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18315 promoted_val = promote_duplicated_reg (SImode, val);
18316 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18317 promoted_val = promote_duplicated_reg (HImode, val);
18319 promoted_val = val;
18321 return promoted_val;
18324 /* Expand string clear operation (bzero). Use i386 string operations when
18325 profitable. See expand_movmem comment for explanation of individual
18326 steps performed. */
18328 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18329 rtx expected_align_exp, rtx expected_size_exp)
18334 rtx jump_around_label = NULL;
18335 HOST_WIDE_INT align = 1;
18336 unsigned HOST_WIDE_INT count = 0;
18337 HOST_WIDE_INT expected_size = -1;
18338 int size_needed = 0, epilogue_size_needed;
18339 int desired_align = 0, align_bytes = 0;
18340 enum stringop_alg alg;
18341 rtx promoted_val = NULL;
18342 bool force_loopy_epilogue = false;
18344 bool need_zero_guard = false;
18346 if (CONST_INT_P (align_exp))
18347 align = INTVAL (align_exp);
18348 /* i386 can do misaligned access on reasonably increased cost. */
18349 if (CONST_INT_P (expected_align_exp)
18350 && INTVAL (expected_align_exp) > align)
18351 align = INTVAL (expected_align_exp);
18352 if (CONST_INT_P (count_exp))
18353 count = expected_size = INTVAL (count_exp);
18354 if (CONST_INT_P (expected_size_exp) && count == 0)
18355 expected_size = INTVAL (expected_size_exp);
18357 /* Make sure we don't need to care about overflow later on. */
18358 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18361 /* Step 0: Decide on preferred algorithm, desired alignment and
18362 size of chunks to be copied by main loop. */
18364 alg = decide_alg (count, expected_size, true, &dynamic_check);
18365 desired_align = decide_alignment (align, alg, expected_size);
18367 if (!TARGET_ALIGN_STRINGOPS)
18368 align = desired_align;
18370 if (alg == libcall)
18372 gcc_assert (alg != no_stringop);
18374 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18375 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18380 gcc_unreachable ();
18382 need_zero_guard = true;
18383 size_needed = GET_MODE_SIZE (Pmode);
18385 case unrolled_loop:
18386 need_zero_guard = true;
18387 size_needed = GET_MODE_SIZE (Pmode) * 4;
18389 case rep_prefix_8_byte:
18392 case rep_prefix_4_byte:
18395 case rep_prefix_1_byte:
18399 need_zero_guard = true;
18403 epilogue_size_needed = size_needed;
18405 /* Step 1: Prologue guard. */
18407 /* Alignment code needs count to be in register. */
18408 if (CONST_INT_P (count_exp) && desired_align > align)
18410 if (INTVAL (count_exp) > desired_align
18411 && INTVAL (count_exp) > size_needed)
18414 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18415 if (align_bytes <= 0)
18418 align_bytes = desired_align - align_bytes;
18420 if (align_bytes == 0)
18422 enum machine_mode mode = SImode;
18423 if (TARGET_64BIT && (count & ~0xffffffff))
18425 count_exp = force_reg (mode, count_exp);
18428 /* Do the cheap promotion to allow better CSE across the
18429 main loop and epilogue (ie one load of the big constant in the
18430 front of all code. */
18431 if (CONST_INT_P (val_exp))
18432 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18433 desired_align, align);
18434 /* Ensure that alignment prologue won't copy past end of block. */
18435 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18437 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18438 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18439 Make sure it is power of 2. */
18440 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18442 /* To improve performance of small blocks, we jump around the VAL
18443 promoting mode. This mean that if the promoted VAL is not constant,
18444 we might not use it in the epilogue and have to use byte
18446 if (epilogue_size_needed > 2 && !promoted_val)
18447 force_loopy_epilogue = true;
18450 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18452 /* If main algorithm works on QImode, no epilogue is needed.
18453 For small sizes just don't align anything. */
18454 if (size_needed == 1)
18455 desired_align = align;
18462 label = gen_label_rtx ();
18463 emit_cmp_and_jump_insns (count_exp,
18464 GEN_INT (epilogue_size_needed),
18465 LTU, 0, counter_mode (count_exp), 1, label);
18466 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18467 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18469 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18472 if (dynamic_check != -1)
18474 rtx hot_label = gen_label_rtx ();
18475 jump_around_label = gen_label_rtx ();
18476 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18477 LEU, 0, counter_mode (count_exp), 1, hot_label);
18478 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18479 set_storage_via_libcall (dst, count_exp, val_exp, false);
18480 emit_jump (jump_around_label);
18481 emit_label (hot_label);
18484 /* Step 2: Alignment prologue. */
18486 /* Do the expensive promotion once we branched off the small blocks. */
18488 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18489 desired_align, align);
18490 gcc_assert (desired_align >= 1 && align >= 1);
18492 if (desired_align > align)
18494 if (align_bytes == 0)
18496 /* Except for the first move in epilogue, we no longer know
18497 constant offset in aliasing info. It don't seems to worth
18498 the pain to maintain it for the first move, so throw away
18500 dst = change_address (dst, BLKmode, destreg);
18501 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18506 /* If we know how many bytes need to be stored before dst is
18507 sufficiently aligned, maintain aliasing info accurately. */
18508 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18509 desired_align, align_bytes);
18510 count_exp = plus_constant (count_exp, -align_bytes);
18511 count -= align_bytes;
18513 if (need_zero_guard
18514 && (count < (unsigned HOST_WIDE_INT) size_needed
18515 || (align_bytes == 0
18516 && count < ((unsigned HOST_WIDE_INT) size_needed
18517 + desired_align - align))))
18519 /* It is possible that we copied enough so the main loop will not
18521 gcc_assert (size_needed > 1);
18522 if (label == NULL_RTX)
18523 label = gen_label_rtx ();
18524 emit_cmp_and_jump_insns (count_exp,
18525 GEN_INT (size_needed),
18526 LTU, 0, counter_mode (count_exp), 1, label);
18527 if (expected_size == -1
18528 || expected_size < (desired_align - align) / 2 + size_needed)
18529 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18531 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18534 if (label && size_needed == 1)
18536 emit_label (label);
18537 LABEL_NUSES (label) = 1;
18539 promoted_val = val_exp;
18540 epilogue_size_needed = 1;
18542 else if (label == NULL_RTX)
18543 epilogue_size_needed = size_needed;
18545 /* Step 3: Main loop. */
18551 gcc_unreachable ();
18553 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18554 count_exp, QImode, 1, expected_size);
18557 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18558 count_exp, Pmode, 1, expected_size);
18560 case unrolled_loop:
18561 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18562 count_exp, Pmode, 4, expected_size);
18564 case rep_prefix_8_byte:
18565 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18568 case rep_prefix_4_byte:
18569 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18572 case rep_prefix_1_byte:
18573 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18577 /* Adjust properly the offset of src and dest memory for aliasing. */
18578 if (CONST_INT_P (count_exp))
18579 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18580 (count / size_needed) * size_needed);
18582 dst = change_address (dst, BLKmode, destreg);
18584 /* Step 4: Epilogue to copy the remaining bytes. */
18588 /* When the main loop is done, COUNT_EXP might hold original count,
18589 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18590 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18591 bytes. Compensate if needed. */
18593 if (size_needed < epilogue_size_needed)
18596 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18597 GEN_INT (size_needed - 1), count_exp, 1,
18599 if (tmp != count_exp)
18600 emit_move_insn (count_exp, tmp);
18602 emit_label (label);
18603 LABEL_NUSES (label) = 1;
18606 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18608 if (force_loopy_epilogue)
18609 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18610 epilogue_size_needed);
18612 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18613 epilogue_size_needed);
18615 if (jump_around_label)
18616 emit_label (jump_around_label);
18620 /* Expand the appropriate insns for doing strlen if not just doing
18623 out = result, initialized with the start address
18624 align_rtx = alignment of the address.
18625 scratch = scratch register, initialized with the startaddress when
18626 not aligned, otherwise undefined
18628 This is just the body. It needs the initializations mentioned above and
18629 some address computing at the end. These things are done in i386.md. */
18632 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18636 rtx align_2_label = NULL_RTX;
18637 rtx align_3_label = NULL_RTX;
18638 rtx align_4_label = gen_label_rtx ();
18639 rtx end_0_label = gen_label_rtx ();
18641 rtx tmpreg = gen_reg_rtx (SImode);
18642 rtx scratch = gen_reg_rtx (SImode);
18646 if (CONST_INT_P (align_rtx))
18647 align = INTVAL (align_rtx);
18649 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18651 /* Is there a known alignment and is it less than 4? */
18654 rtx scratch1 = gen_reg_rtx (Pmode);
18655 emit_move_insn (scratch1, out);
18656 /* Is there a known alignment and is it not 2? */
18659 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18660 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18662 /* Leave just the 3 lower bits. */
18663 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18664 NULL_RTX, 0, OPTAB_WIDEN);
18666 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18667 Pmode, 1, align_4_label);
18668 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18669 Pmode, 1, align_2_label);
18670 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18671 Pmode, 1, align_3_label);
18675 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18676 check if is aligned to 4 - byte. */
18678 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18679 NULL_RTX, 0, OPTAB_WIDEN);
18681 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18682 Pmode, 1, align_4_label);
18685 mem = change_address (src, QImode, out);
18687 /* Now compare the bytes. */
18689 /* Compare the first n unaligned byte on a byte per byte basis. */
18690 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18691 QImode, 1, end_0_label);
18693 /* Increment the address. */
18694 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18696 /* Not needed with an alignment of 2 */
18699 emit_label (align_2_label);
18701 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18704 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18706 emit_label (align_3_label);
18709 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18712 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18715 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18716 align this loop. It gives only huge programs, but does not help to
18718 emit_label (align_4_label);
18720 mem = change_address (src, SImode, out);
18721 emit_move_insn (scratch, mem);
18722 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18724 /* This formula yields a nonzero result iff one of the bytes is zero.
18725 This saves three branches inside loop and many cycles. */
18727 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18728 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18729 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18730 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18731 gen_int_mode (0x80808080, SImode)));
18732 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18737 rtx reg = gen_reg_rtx (SImode);
18738 rtx reg2 = gen_reg_rtx (Pmode);
18739 emit_move_insn (reg, tmpreg);
18740 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18742 /* If zero is not in the first two bytes, move two bytes forward. */
18743 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18744 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18745 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18746 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18747 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18750 /* Emit lea manually to avoid clobbering of flags. */
18751 emit_insn (gen_rtx_SET (SImode, reg2,
18752 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18754 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18755 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18756 emit_insn (gen_rtx_SET (VOIDmode, out,
18757 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18764 rtx end_2_label = gen_label_rtx ();
18765 /* Is zero in the first two bytes? */
18767 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18768 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18769 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18770 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18771 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18773 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18774 JUMP_LABEL (tmp) = end_2_label;
18776 /* Not in the first two. Move two bytes forward. */
18777 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18778 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18780 emit_label (end_2_label);
18784 /* Avoid branch in fixing the byte. */
18785 tmpreg = gen_lowpart (QImode, tmpreg);
18786 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18787 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18788 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18790 emit_label (end_0_label);
18793 /* Expand strlen. */
18796 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18798 rtx addr, scratch1, scratch2, scratch3, scratch4;
18800 /* The generic case of strlen expander is long. Avoid it's
18801 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18803 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18804 && !TARGET_INLINE_ALL_STRINGOPS
18805 && !optimize_insn_for_size_p ()
18806 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18809 addr = force_reg (Pmode, XEXP (src, 0));
18810 scratch1 = gen_reg_rtx (Pmode);
18812 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18813 && !optimize_insn_for_size_p ())
18815 /* Well it seems that some optimizer does not combine a call like
18816 foo(strlen(bar), strlen(bar));
18817 when the move and the subtraction is done here. It does calculate
18818 the length just once when these instructions are done inside of
18819 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18820 often used and I use one fewer register for the lifetime of
18821 output_strlen_unroll() this is better. */
18823 emit_move_insn (out, addr);
18825 ix86_expand_strlensi_unroll_1 (out, src, align);
18827 /* strlensi_unroll_1 returns the address of the zero at the end of
18828 the string, like memchr(), so compute the length by subtracting
18829 the start address. */
18830 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18836 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18837 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18840 scratch2 = gen_reg_rtx (Pmode);
18841 scratch3 = gen_reg_rtx (Pmode);
18842 scratch4 = force_reg (Pmode, constm1_rtx);
18844 emit_move_insn (scratch3, addr);
18845 eoschar = force_reg (QImode, eoschar);
18847 src = replace_equiv_address_nv (src, scratch3);
18849 /* If .md starts supporting :P, this can be done in .md. */
18850 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18851 scratch4), UNSPEC_SCAS);
18852 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18853 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18854 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18859 /* For given symbol (function) construct code to compute address of it's PLT
18860 entry in large x86-64 PIC model. */
18862 construct_plt_address (rtx symbol)
18864 rtx tmp = gen_reg_rtx (Pmode);
18865 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18867 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18868 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18870 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18871 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18876 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18878 rtx pop, int sibcall)
18880 rtx use = NULL, call;
18882 if (pop == const0_rtx)
18884 gcc_assert (!TARGET_64BIT || !pop);
18886 if (TARGET_MACHO && !TARGET_64BIT)
18889 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18890 fnaddr = machopic_indirect_call_target (fnaddr);
18895 /* Static functions and indirect calls don't need the pic register. */
18896 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18897 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18898 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18899 use_reg (&use, pic_offset_table_rtx);
18902 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18904 rtx al = gen_rtx_REG (QImode, AX_REG);
18905 emit_move_insn (al, callarg2);
18906 use_reg (&use, al);
18909 if (ix86_cmodel == CM_LARGE_PIC
18911 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18912 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18913 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18915 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
18916 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
18918 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18919 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18922 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18924 call = gen_rtx_SET (VOIDmode, retval, call);
18927 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18928 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18929 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18932 && ix86_cfun_abi () == MS_ABI
18933 && (!callarg2 || INTVAL (callarg2) != -2))
18935 /* We need to represent that SI and DI registers are clobbered
18937 static int clobbered_registers[] = {
18938 XMM6_REG, XMM7_REG, XMM8_REG,
18939 XMM9_REG, XMM10_REG, XMM11_REG,
18940 XMM12_REG, XMM13_REG, XMM14_REG,
18941 XMM15_REG, SI_REG, DI_REG
18944 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18945 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18946 UNSPEC_MS_TO_SYSV_CALL);
18950 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18951 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18954 (SSE_REGNO_P (clobbered_registers[i])
18956 clobbered_registers[i]));
18958 call = gen_rtx_PARALLEL (VOIDmode,
18959 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18963 call = emit_call_insn (call);
18965 CALL_INSN_FUNCTION_USAGE (call) = use;
18969 /* Clear stack slot assignments remembered from previous functions.
18970 This is called from INIT_EXPANDERS once before RTL is emitted for each
18973 static struct machine_function *
18974 ix86_init_machine_status (void)
18976 struct machine_function *f;
18978 f = GGC_CNEW (struct machine_function);
18979 f->use_fast_prologue_epilogue_nregs = -1;
18980 f->tls_descriptor_call_expanded_p = 0;
18981 f->call_abi = ix86_abi;
18986 /* Return a MEM corresponding to a stack slot with mode MODE.
18987 Allocate a new slot if necessary.
18989 The RTL for a function can have several slots available: N is
18990 which slot to use. */
18993 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
18995 struct stack_local_entry *s;
18997 gcc_assert (n < MAX_386_STACK_LOCALS);
18999 /* Virtual slot is valid only before vregs are instantiated. */
19000 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
19002 for (s = ix86_stack_locals; s; s = s->next)
19003 if (s->mode == mode && s->n == n)
19004 return copy_rtx (s->rtl);
19006 s = (struct stack_local_entry *)
19007 ggc_alloc (sizeof (struct stack_local_entry));
19010 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
19012 s->next = ix86_stack_locals;
19013 ix86_stack_locals = s;
19017 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19019 static GTY(()) rtx ix86_tls_symbol;
19021 ix86_tls_get_addr (void)
19024 if (!ix86_tls_symbol)
19026 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
19027 (TARGET_ANY_GNU_TLS
19029 ? "___tls_get_addr"
19030 : "__tls_get_addr");
19033 return ix86_tls_symbol;
19036 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19038 static GTY(()) rtx ix86_tls_module_base_symbol;
19040 ix86_tls_module_base (void)
19043 if (!ix86_tls_module_base_symbol)
19045 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
19046 "_TLS_MODULE_BASE_");
19047 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
19048 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
19051 return ix86_tls_module_base_symbol;
19054 /* Calculate the length of the memory address in the instruction
19055 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19058 memory_address_length (rtx addr)
19060 struct ix86_address parts;
19061 rtx base, index, disp;
19065 if (GET_CODE (addr) == PRE_DEC
19066 || GET_CODE (addr) == POST_INC
19067 || GET_CODE (addr) == PRE_MODIFY
19068 || GET_CODE (addr) == POST_MODIFY)
19071 ok = ix86_decompose_address (addr, &parts);
19074 if (parts.base && GET_CODE (parts.base) == SUBREG)
19075 parts.base = SUBREG_REG (parts.base);
19076 if (parts.index && GET_CODE (parts.index) == SUBREG)
19077 parts.index = SUBREG_REG (parts.index);
19080 index = parts.index;
19085 - esp as the base always wants an index,
19086 - ebp as the base always wants a displacement,
19087 - r12 as the base always wants an index,
19088 - r13 as the base always wants a displacement. */
19090 /* Register Indirect. */
19091 if (base && !index && !disp)
19093 /* esp (for its index) and ebp (for its displacement) need
19094 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19097 && (addr == arg_pointer_rtx
19098 || addr == frame_pointer_rtx
19099 || REGNO (addr) == SP_REG
19100 || REGNO (addr) == BP_REG
19101 || REGNO (addr) == R12_REG
19102 || REGNO (addr) == R13_REG))
19106 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19107 is not disp32, but disp32(%rip), so for disp32
19108 SIB byte is needed, unless print_operand_address
19109 optimizes it into disp32(%rip) or (%rip) is implied
19111 else if (disp && !base && !index)
19118 if (GET_CODE (disp) == CONST)
19119 symbol = XEXP (disp, 0);
19120 if (GET_CODE (symbol) == PLUS
19121 && CONST_INT_P (XEXP (symbol, 1)))
19122 symbol = XEXP (symbol, 0);
19124 if (GET_CODE (symbol) != LABEL_REF
19125 && (GET_CODE (symbol) != SYMBOL_REF
19126 || SYMBOL_REF_TLS_MODEL (symbol) != 0)
19127 && (GET_CODE (symbol) != UNSPEC
19128 || (XINT (symbol, 1) != UNSPEC_GOTPCREL
19129 && XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
19136 /* Find the length of the displacement constant. */
19139 if (base && satisfies_constraint_K (disp))
19144 /* ebp always wants a displacement. Similarly r13. */
19145 else if (base && REG_P (base)
19146 && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
19149 /* An index requires the two-byte modrm form.... */
19151 /* ...like esp (or r12), which always wants an index. */
19152 || base == arg_pointer_rtx
19153 || base == frame_pointer_rtx
19154 || (base && REG_P (base)
19155 && (REGNO (base) == SP_REG || REGNO (base) == R12_REG)))
19172 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19173 is set, expect that insn have 8bit immediate alternative. */
19175 ix86_attr_length_immediate_default (rtx insn, int shortform)
19179 extract_insn_cached (insn);
19180 for (i = recog_data.n_operands - 1; i >= 0; --i)
19181 if (CONSTANT_P (recog_data.operand[i]))
19183 enum attr_mode mode = get_attr_mode (insn);
19186 if (shortform && CONST_INT_P (recog_data.operand[i]))
19188 HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
19195 ival = trunc_int_for_mode (ival, HImode);
19198 ival = trunc_int_for_mode (ival, SImode);
19203 if (IN_RANGE (ival, -128, 127))
19220 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19225 fatal_insn ("unknown insn mode", insn);
19230 /* Compute default value for "length_address" attribute. */
19232 ix86_attr_length_address_default (rtx insn)
19236 if (get_attr_type (insn) == TYPE_LEA)
19238 rtx set = PATTERN (insn), addr;
19240 if (GET_CODE (set) == PARALLEL)
19241 set = XVECEXP (set, 0, 0);
19243 gcc_assert (GET_CODE (set) == SET);
19245 addr = SET_SRC (set);
19246 if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI)
19248 if (GET_CODE (addr) == ZERO_EXTEND)
19249 addr = XEXP (addr, 0);
19250 if (GET_CODE (addr) == SUBREG)
19251 addr = SUBREG_REG (addr);
19254 return memory_address_length (addr);
19257 extract_insn_cached (insn);
19258 for (i = recog_data.n_operands - 1; i >= 0; --i)
19259 if (MEM_P (recog_data.operand[i]))
19261 constrain_operands_cached (reload_completed);
19262 if (which_alternative != -1)
19264 const char *constraints = recog_data.constraints[i];
19265 int alt = which_alternative;
19267 while (*constraints == '=' || *constraints == '+')
19270 while (*constraints++ != ',')
19272 /* Skip ignored operands. */
19273 if (*constraints == 'X')
19276 return memory_address_length (XEXP (recog_data.operand[i], 0));
19281 /* Compute default value for "length_vex" attribute. It includes
19282 2 or 3 byte VEX prefix and 1 opcode byte. */
19285 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19290 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19291 byte VEX prefix. */
19292 if (!has_0f_opcode || has_vex_w)
19295 /* We can always use 2 byte VEX prefix in 32bit. */
19299 extract_insn_cached (insn);
19301 for (i = recog_data.n_operands - 1; i >= 0; --i)
19302 if (REG_P (recog_data.operand[i]))
19304 /* REX.W bit uses 3 byte VEX prefix. */
19305 if (GET_MODE (recog_data.operand[i]) == DImode
19306 && GENERAL_REG_P (recog_data.operand[i]))
19311 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19312 if (MEM_P (recog_data.operand[i])
19313 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19320 /* Return the maximum number of instructions a cpu can issue. */
19323 ix86_issue_rate (void)
19327 case PROCESSOR_PENTIUM:
19328 case PROCESSOR_ATOM:
19332 case PROCESSOR_PENTIUMPRO:
19333 case PROCESSOR_PENTIUM4:
19334 case PROCESSOR_ATHLON:
19336 case PROCESSOR_AMDFAM10:
19337 case PROCESSOR_NOCONA:
19338 case PROCESSOR_GENERIC32:
19339 case PROCESSOR_GENERIC64:
19342 case PROCESSOR_CORE2:
19350 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19351 by DEP_INSN and nothing set by DEP_INSN. */
19354 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19358 /* Simplify the test for uninteresting insns. */
19359 if (insn_type != TYPE_SETCC
19360 && insn_type != TYPE_ICMOV
19361 && insn_type != TYPE_FCMOV
19362 && insn_type != TYPE_IBR)
19365 if ((set = single_set (dep_insn)) != 0)
19367 set = SET_DEST (set);
19370 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19371 && XVECLEN (PATTERN (dep_insn), 0) == 2
19372 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19373 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19375 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19376 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19381 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19384 /* This test is true if the dependent insn reads the flags but
19385 not any other potentially set register. */
19386 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19389 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19395 /* Return true iff USE_INSN has a memory address with operands set by
19399 ix86_agi_dependent (rtx set_insn, rtx use_insn)
19402 extract_insn_cached (use_insn);
19403 for (i = recog_data.n_operands - 1; i >= 0; --i)
19404 if (MEM_P (recog_data.operand[i]))
19406 rtx addr = XEXP (recog_data.operand[i], 0);
19407 return modified_in_p (addr, set_insn) != 0;
19413 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19415 enum attr_type insn_type, dep_insn_type;
19416 enum attr_memory memory;
19418 int dep_insn_code_number;
19420 /* Anti and output dependencies have zero cost on all CPUs. */
19421 if (REG_NOTE_KIND (link) != 0)
19424 dep_insn_code_number = recog_memoized (dep_insn);
19426 /* If we can't recognize the insns, we can't really do anything. */
19427 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19430 insn_type = get_attr_type (insn);
19431 dep_insn_type = get_attr_type (dep_insn);
19435 case PROCESSOR_PENTIUM:
19436 /* Address Generation Interlock adds a cycle of latency. */
19437 if (insn_type == TYPE_LEA)
19439 rtx addr = PATTERN (insn);
19441 if (GET_CODE (addr) == PARALLEL)
19442 addr = XVECEXP (addr, 0, 0);
19444 gcc_assert (GET_CODE (addr) == SET);
19446 addr = SET_SRC (addr);
19447 if (modified_in_p (addr, dep_insn))
19450 else if (ix86_agi_dependent (dep_insn, insn))
19453 /* ??? Compares pair with jump/setcc. */
19454 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19457 /* Floating point stores require value to be ready one cycle earlier. */
19458 if (insn_type == TYPE_FMOV
19459 && get_attr_memory (insn) == MEMORY_STORE
19460 && !ix86_agi_dependent (dep_insn, insn))
19464 case PROCESSOR_PENTIUMPRO:
19465 memory = get_attr_memory (insn);
19467 /* INT->FP conversion is expensive. */
19468 if (get_attr_fp_int_src (dep_insn))
19471 /* There is one cycle extra latency between an FP op and a store. */
19472 if (insn_type == TYPE_FMOV
19473 && (set = single_set (dep_insn)) != NULL_RTX
19474 && (set2 = single_set (insn)) != NULL_RTX
19475 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19476 && MEM_P (SET_DEST (set2)))
19479 /* Show ability of reorder buffer to hide latency of load by executing
19480 in parallel with previous instruction in case
19481 previous instruction is not needed to compute the address. */
19482 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19483 && !ix86_agi_dependent (dep_insn, insn))
19485 /* Claim moves to take one cycle, as core can issue one load
19486 at time and the next load can start cycle later. */
19487 if (dep_insn_type == TYPE_IMOV
19488 || dep_insn_type == TYPE_FMOV)
19496 memory = get_attr_memory (insn);
19498 /* The esp dependency is resolved before the instruction is really
19500 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19501 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19504 /* INT->FP conversion is expensive. */
19505 if (get_attr_fp_int_src (dep_insn))
19508 /* Show ability of reorder buffer to hide latency of load by executing
19509 in parallel with previous instruction in case
19510 previous instruction is not needed to compute the address. */
19511 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19512 && !ix86_agi_dependent (dep_insn, insn))
19514 /* Claim moves to take one cycle, as core can issue one load
19515 at time and the next load can start cycle later. */
19516 if (dep_insn_type == TYPE_IMOV
19517 || dep_insn_type == TYPE_FMOV)
19526 case PROCESSOR_ATHLON:
19528 case PROCESSOR_AMDFAM10:
19529 case PROCESSOR_ATOM:
19530 case PROCESSOR_GENERIC32:
19531 case PROCESSOR_GENERIC64:
19532 memory = get_attr_memory (insn);
19534 /* Show ability of reorder buffer to hide latency of load by executing
19535 in parallel with previous instruction in case
19536 previous instruction is not needed to compute the address. */
19537 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19538 && !ix86_agi_dependent (dep_insn, insn))
19540 enum attr_unit unit = get_attr_unit (insn);
19543 /* Because of the difference between the length of integer and
19544 floating unit pipeline preparation stages, the memory operands
19545 for floating point are cheaper.
19547 ??? For Athlon it the difference is most probably 2. */
19548 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19551 loadcost = TARGET_ATHLON ? 2 : 0;
19553 if (cost >= loadcost)
19566 /* How many alternative schedules to try. This should be as wide as the
19567 scheduling freedom in the DFA, but no wider. Making this value too
19568 large results extra work for the scheduler. */
19571 ia32_multipass_dfa_lookahead (void)
19575 case PROCESSOR_PENTIUM:
19578 case PROCESSOR_PENTIUMPRO:
19588 /* Compute the alignment given to a constant that is being placed in memory.
19589 EXP is the constant and ALIGN is the alignment that the object would
19591 The value of this function is used instead of that alignment to align
19595 ix86_constant_alignment (tree exp, int align)
19597 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19598 || TREE_CODE (exp) == INTEGER_CST)
19600 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19602 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19605 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19606 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19607 return BITS_PER_WORD;
19612 /* Compute the alignment for a static variable.
19613 TYPE is the data type, and ALIGN is the alignment that
19614 the object would ordinarily have. The value of this function is used
19615 instead of that alignment to align the object. */
19618 ix86_data_alignment (tree type, int align)
19620 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19622 if (AGGREGATE_TYPE_P (type)
19623 && TYPE_SIZE (type)
19624 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19625 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19626 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19627 && align < max_align)
19630 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19631 to 16byte boundary. */
19634 if (AGGREGATE_TYPE_P (type)
19635 && TYPE_SIZE (type)
19636 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19637 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19638 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19642 if (TREE_CODE (type) == ARRAY_TYPE)
19644 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19646 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19649 else if (TREE_CODE (type) == COMPLEX_TYPE)
19652 if (TYPE_MODE (type) == DCmode && align < 64)
19654 if ((TYPE_MODE (type) == XCmode
19655 || TYPE_MODE (type) == TCmode) && align < 128)
19658 else if ((TREE_CODE (type) == RECORD_TYPE
19659 || TREE_CODE (type) == UNION_TYPE
19660 || TREE_CODE (type) == QUAL_UNION_TYPE)
19661 && TYPE_FIELDS (type))
19663 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19665 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19668 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19669 || TREE_CODE (type) == INTEGER_TYPE)
19671 if (TYPE_MODE (type) == DFmode && align < 64)
19673 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19680 /* Compute the alignment for a local variable or a stack slot. EXP is
19681 the data type or decl itself, MODE is the widest mode available and
19682 ALIGN is the alignment that the object would ordinarily have. The
19683 value of this macro is used instead of that alignment to align the
19687 ix86_local_alignment (tree exp, enum machine_mode mode,
19688 unsigned int align)
19692 if (exp && DECL_P (exp))
19694 type = TREE_TYPE (exp);
19703 /* Don't do dynamic stack realignment for long long objects with
19704 -mpreferred-stack-boundary=2. */
19707 && ix86_preferred_stack_boundary < 64
19708 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19709 && (!type || !TYPE_USER_ALIGN (type))
19710 && (!decl || !DECL_USER_ALIGN (decl)))
19713 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19714 register in MODE. We will return the largest alignment of XF
19718 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19719 align = GET_MODE_ALIGNMENT (DFmode);
19723 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19724 to 16byte boundary. */
19727 if (AGGREGATE_TYPE_P (type)
19728 && TYPE_SIZE (type)
19729 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19730 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19731 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19734 if (TREE_CODE (type) == ARRAY_TYPE)
19736 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19738 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19741 else if (TREE_CODE (type) == COMPLEX_TYPE)
19743 if (TYPE_MODE (type) == DCmode && align < 64)
19745 if ((TYPE_MODE (type) == XCmode
19746 || TYPE_MODE (type) == TCmode) && align < 128)
19749 else if ((TREE_CODE (type) == RECORD_TYPE
19750 || TREE_CODE (type) == UNION_TYPE
19751 || TREE_CODE (type) == QUAL_UNION_TYPE)
19752 && TYPE_FIELDS (type))
19754 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19756 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19759 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19760 || TREE_CODE (type) == INTEGER_TYPE)
19763 if (TYPE_MODE (type) == DFmode && align < 64)
19765 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19771 /* Compute the minimum required alignment for dynamic stack realignment
19772 purposes for a local variable, parameter or a stack slot. EXP is
19773 the data type or decl itself, MODE is its mode and ALIGN is the
19774 alignment that the object would ordinarily have. */
19777 ix86_minimum_alignment (tree exp, enum machine_mode mode,
19778 unsigned int align)
19782 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
19785 if (exp && DECL_P (exp))
19787 type = TREE_TYPE (exp);
19796 /* Don't do dynamic stack realignment for long long objects with
19797 -mpreferred-stack-boundary=2. */
19798 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
19799 && (!type || !TYPE_USER_ALIGN (type))
19800 && (!decl || !DECL_USER_ALIGN (decl)))
19806 /* Find a location for the static chain incoming to a nested function.
19807 This is a register, unless all free registers are used by arguments. */
19810 ix86_static_chain (const_tree fndecl, bool incoming_p)
19814 if (DECL_NO_STATIC_CHAIN (fndecl))
19819 /* We always use R10 in 64-bit mode. */
19825 /* By default in 32-bit mode we use ECX to pass the static chain. */
19828 fntype = TREE_TYPE (fndecl);
19829 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
19831 /* Fastcall functions use ecx/edx for arguments, which leaves
19832 us with EAX for the static chain. */
19835 else if (ix86_function_regparm (fntype, fndecl) == 3)
19837 /* For regparm 3, we have no free call-clobbered registers in
19838 which to store the static chain. In order to implement this,
19839 we have the trampoline push the static chain to the stack.
19840 However, we can't push a value below the return address when
19841 we call the nested function directly, so we have to use an
19842 alternate entry point. For this we use ESI, and have the
19843 alternate entry point push ESI, so that things appear the
19844 same once we're executing the nested function. */
19847 if (fndecl == current_function_decl)
19848 ix86_static_chain_on_stack = true;
19849 return gen_frame_mem (SImode,
19850 plus_constant (arg_pointer_rtx, -8));
19856 return gen_rtx_REG (Pmode, regno);
19859 /* Emit RTL insns to initialize the variable parts of a trampoline.
19860 FNDECL is the decl of the target address; M_TRAMP is a MEM for
19861 the trampoline, and CHAIN_VALUE is an RTX for the static chain
19862 to be passed to the target function. */
19865 ix86_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
19869 fnaddr = XEXP (DECL_RTL (fndecl), 0);
19876 /* Depending on the static chain location, either load a register
19877 with a constant, or push the constant to the stack. All of the
19878 instructions are the same size. */
19879 chain = ix86_static_chain (fndecl, true);
19882 if (REGNO (chain) == CX_REG)
19884 else if (REGNO (chain) == AX_REG)
19887 gcc_unreachable ();
19892 mem = adjust_address (m_tramp, QImode, 0);
19893 emit_move_insn (mem, gen_int_mode (opcode, QImode));
19895 mem = adjust_address (m_tramp, SImode, 1);
19896 emit_move_insn (mem, chain_value);
19898 /* Compute offset from the end of the jmp to the target function.
19899 In the case in which the trampoline stores the static chain on
19900 the stack, we need to skip the first insn which pushes the
19901 (call-saved) register static chain; this push is 1 byte. */
19902 disp = expand_binop (SImode, sub_optab, fnaddr,
19903 plus_constant (XEXP (m_tramp, 0),
19904 MEM_P (chain) ? 9 : 10),
19905 NULL_RTX, 1, OPTAB_DIRECT);
19907 mem = adjust_address (m_tramp, QImode, 5);
19908 emit_move_insn (mem, gen_int_mode (0xe9, QImode));
19910 mem = adjust_address (m_tramp, SImode, 6);
19911 emit_move_insn (mem, disp);
19917 /* Load the function address to r11. Try to load address using
19918 the shorter movl instead of movabs. We may want to support
19919 movq for kernel mode, but kernel does not use trampolines at
19921 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19923 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19925 mem = adjust_address (m_tramp, HImode, offset);
19926 emit_move_insn (mem, gen_int_mode (0xbb41, HImode));
19928 mem = adjust_address (m_tramp, SImode, offset + 2);
19929 emit_move_insn (mem, gen_lowpart (SImode, fnaddr));
19934 mem = adjust_address (m_tramp, HImode, offset);
19935 emit_move_insn (mem, gen_int_mode (0xbb49, HImode));
19937 mem = adjust_address (m_tramp, DImode, offset + 2);
19938 emit_move_insn (mem, fnaddr);
19942 /* Load static chain using movabs to r10. */
19943 mem = adjust_address (m_tramp, HImode, offset);
19944 emit_move_insn (mem, gen_int_mode (0xba49, HImode));
19946 mem = adjust_address (m_tramp, DImode, offset + 2);
19947 emit_move_insn (mem, chain_value);
19950 /* Jump to r11; the last (unused) byte is a nop, only there to
19951 pad the write out to a single 32-bit store. */
19952 mem = adjust_address (m_tramp, SImode, offset);
19953 emit_move_insn (mem, gen_int_mode (0x90e3ff49, SImode));
19956 gcc_assert (offset <= TRAMPOLINE_SIZE);
19959 #ifdef ENABLE_EXECUTE_STACK
19960 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19961 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
19965 /* Codes for all the SSE/MMX builtins. */
19968 IX86_BUILTIN_ADDPS,
19969 IX86_BUILTIN_ADDSS,
19970 IX86_BUILTIN_DIVPS,
19971 IX86_BUILTIN_DIVSS,
19972 IX86_BUILTIN_MULPS,
19973 IX86_BUILTIN_MULSS,
19974 IX86_BUILTIN_SUBPS,
19975 IX86_BUILTIN_SUBSS,
19977 IX86_BUILTIN_CMPEQPS,
19978 IX86_BUILTIN_CMPLTPS,
19979 IX86_BUILTIN_CMPLEPS,
19980 IX86_BUILTIN_CMPGTPS,
19981 IX86_BUILTIN_CMPGEPS,
19982 IX86_BUILTIN_CMPNEQPS,
19983 IX86_BUILTIN_CMPNLTPS,
19984 IX86_BUILTIN_CMPNLEPS,
19985 IX86_BUILTIN_CMPNGTPS,
19986 IX86_BUILTIN_CMPNGEPS,
19987 IX86_BUILTIN_CMPORDPS,
19988 IX86_BUILTIN_CMPUNORDPS,
19989 IX86_BUILTIN_CMPEQSS,
19990 IX86_BUILTIN_CMPLTSS,
19991 IX86_BUILTIN_CMPLESS,
19992 IX86_BUILTIN_CMPNEQSS,
19993 IX86_BUILTIN_CMPNLTSS,
19994 IX86_BUILTIN_CMPNLESS,
19995 IX86_BUILTIN_CMPNGTSS,
19996 IX86_BUILTIN_CMPNGESS,
19997 IX86_BUILTIN_CMPORDSS,
19998 IX86_BUILTIN_CMPUNORDSS,
20000 IX86_BUILTIN_COMIEQSS,
20001 IX86_BUILTIN_COMILTSS,
20002 IX86_BUILTIN_COMILESS,
20003 IX86_BUILTIN_COMIGTSS,
20004 IX86_BUILTIN_COMIGESS,
20005 IX86_BUILTIN_COMINEQSS,
20006 IX86_BUILTIN_UCOMIEQSS,
20007 IX86_BUILTIN_UCOMILTSS,
20008 IX86_BUILTIN_UCOMILESS,
20009 IX86_BUILTIN_UCOMIGTSS,
20010 IX86_BUILTIN_UCOMIGESS,
20011 IX86_BUILTIN_UCOMINEQSS,
20013 IX86_BUILTIN_CVTPI2PS,
20014 IX86_BUILTIN_CVTPS2PI,
20015 IX86_BUILTIN_CVTSI2SS,
20016 IX86_BUILTIN_CVTSI642SS,
20017 IX86_BUILTIN_CVTSS2SI,
20018 IX86_BUILTIN_CVTSS2SI64,
20019 IX86_BUILTIN_CVTTPS2PI,
20020 IX86_BUILTIN_CVTTSS2SI,
20021 IX86_BUILTIN_CVTTSS2SI64,
20023 IX86_BUILTIN_MAXPS,
20024 IX86_BUILTIN_MAXSS,
20025 IX86_BUILTIN_MINPS,
20026 IX86_BUILTIN_MINSS,
20028 IX86_BUILTIN_LOADUPS,
20029 IX86_BUILTIN_STOREUPS,
20030 IX86_BUILTIN_MOVSS,
20032 IX86_BUILTIN_MOVHLPS,
20033 IX86_BUILTIN_MOVLHPS,
20034 IX86_BUILTIN_LOADHPS,
20035 IX86_BUILTIN_LOADLPS,
20036 IX86_BUILTIN_STOREHPS,
20037 IX86_BUILTIN_STORELPS,
20039 IX86_BUILTIN_MASKMOVQ,
20040 IX86_BUILTIN_MOVMSKPS,
20041 IX86_BUILTIN_PMOVMSKB,
20043 IX86_BUILTIN_MOVNTPS,
20044 IX86_BUILTIN_MOVNTQ,
20046 IX86_BUILTIN_LOADDQU,
20047 IX86_BUILTIN_STOREDQU,
20049 IX86_BUILTIN_PACKSSWB,
20050 IX86_BUILTIN_PACKSSDW,
20051 IX86_BUILTIN_PACKUSWB,
20053 IX86_BUILTIN_PADDB,
20054 IX86_BUILTIN_PADDW,
20055 IX86_BUILTIN_PADDD,
20056 IX86_BUILTIN_PADDQ,
20057 IX86_BUILTIN_PADDSB,
20058 IX86_BUILTIN_PADDSW,
20059 IX86_BUILTIN_PADDUSB,
20060 IX86_BUILTIN_PADDUSW,
20061 IX86_BUILTIN_PSUBB,
20062 IX86_BUILTIN_PSUBW,
20063 IX86_BUILTIN_PSUBD,
20064 IX86_BUILTIN_PSUBQ,
20065 IX86_BUILTIN_PSUBSB,
20066 IX86_BUILTIN_PSUBSW,
20067 IX86_BUILTIN_PSUBUSB,
20068 IX86_BUILTIN_PSUBUSW,
20071 IX86_BUILTIN_PANDN,
20075 IX86_BUILTIN_PAVGB,
20076 IX86_BUILTIN_PAVGW,
20078 IX86_BUILTIN_PCMPEQB,
20079 IX86_BUILTIN_PCMPEQW,
20080 IX86_BUILTIN_PCMPEQD,
20081 IX86_BUILTIN_PCMPGTB,
20082 IX86_BUILTIN_PCMPGTW,
20083 IX86_BUILTIN_PCMPGTD,
20085 IX86_BUILTIN_PMADDWD,
20087 IX86_BUILTIN_PMAXSW,
20088 IX86_BUILTIN_PMAXUB,
20089 IX86_BUILTIN_PMINSW,
20090 IX86_BUILTIN_PMINUB,
20092 IX86_BUILTIN_PMULHUW,
20093 IX86_BUILTIN_PMULHW,
20094 IX86_BUILTIN_PMULLW,
20096 IX86_BUILTIN_PSADBW,
20097 IX86_BUILTIN_PSHUFW,
20099 IX86_BUILTIN_PSLLW,
20100 IX86_BUILTIN_PSLLD,
20101 IX86_BUILTIN_PSLLQ,
20102 IX86_BUILTIN_PSRAW,
20103 IX86_BUILTIN_PSRAD,
20104 IX86_BUILTIN_PSRLW,
20105 IX86_BUILTIN_PSRLD,
20106 IX86_BUILTIN_PSRLQ,
20107 IX86_BUILTIN_PSLLWI,
20108 IX86_BUILTIN_PSLLDI,
20109 IX86_BUILTIN_PSLLQI,
20110 IX86_BUILTIN_PSRAWI,
20111 IX86_BUILTIN_PSRADI,
20112 IX86_BUILTIN_PSRLWI,
20113 IX86_BUILTIN_PSRLDI,
20114 IX86_BUILTIN_PSRLQI,
20116 IX86_BUILTIN_PUNPCKHBW,
20117 IX86_BUILTIN_PUNPCKHWD,
20118 IX86_BUILTIN_PUNPCKHDQ,
20119 IX86_BUILTIN_PUNPCKLBW,
20120 IX86_BUILTIN_PUNPCKLWD,
20121 IX86_BUILTIN_PUNPCKLDQ,
20123 IX86_BUILTIN_SHUFPS,
20125 IX86_BUILTIN_RCPPS,
20126 IX86_BUILTIN_RCPSS,
20127 IX86_BUILTIN_RSQRTPS,
20128 IX86_BUILTIN_RSQRTPS_NR,
20129 IX86_BUILTIN_RSQRTSS,
20130 IX86_BUILTIN_RSQRTF,
20131 IX86_BUILTIN_SQRTPS,
20132 IX86_BUILTIN_SQRTPS_NR,
20133 IX86_BUILTIN_SQRTSS,
20135 IX86_BUILTIN_UNPCKHPS,
20136 IX86_BUILTIN_UNPCKLPS,
20138 IX86_BUILTIN_ANDPS,
20139 IX86_BUILTIN_ANDNPS,
20141 IX86_BUILTIN_XORPS,
20144 IX86_BUILTIN_LDMXCSR,
20145 IX86_BUILTIN_STMXCSR,
20146 IX86_BUILTIN_SFENCE,
20148 /* 3DNow! Original */
20149 IX86_BUILTIN_FEMMS,
20150 IX86_BUILTIN_PAVGUSB,
20151 IX86_BUILTIN_PF2ID,
20152 IX86_BUILTIN_PFACC,
20153 IX86_BUILTIN_PFADD,
20154 IX86_BUILTIN_PFCMPEQ,
20155 IX86_BUILTIN_PFCMPGE,
20156 IX86_BUILTIN_PFCMPGT,
20157 IX86_BUILTIN_PFMAX,
20158 IX86_BUILTIN_PFMIN,
20159 IX86_BUILTIN_PFMUL,
20160 IX86_BUILTIN_PFRCP,
20161 IX86_BUILTIN_PFRCPIT1,
20162 IX86_BUILTIN_PFRCPIT2,
20163 IX86_BUILTIN_PFRSQIT1,
20164 IX86_BUILTIN_PFRSQRT,
20165 IX86_BUILTIN_PFSUB,
20166 IX86_BUILTIN_PFSUBR,
20167 IX86_BUILTIN_PI2FD,
20168 IX86_BUILTIN_PMULHRW,
20170 /* 3DNow! Athlon Extensions */
20171 IX86_BUILTIN_PF2IW,
20172 IX86_BUILTIN_PFNACC,
20173 IX86_BUILTIN_PFPNACC,
20174 IX86_BUILTIN_PI2FW,
20175 IX86_BUILTIN_PSWAPDSI,
20176 IX86_BUILTIN_PSWAPDSF,
20179 IX86_BUILTIN_ADDPD,
20180 IX86_BUILTIN_ADDSD,
20181 IX86_BUILTIN_DIVPD,
20182 IX86_BUILTIN_DIVSD,
20183 IX86_BUILTIN_MULPD,
20184 IX86_BUILTIN_MULSD,
20185 IX86_BUILTIN_SUBPD,
20186 IX86_BUILTIN_SUBSD,
20188 IX86_BUILTIN_CMPEQPD,
20189 IX86_BUILTIN_CMPLTPD,
20190 IX86_BUILTIN_CMPLEPD,
20191 IX86_BUILTIN_CMPGTPD,
20192 IX86_BUILTIN_CMPGEPD,
20193 IX86_BUILTIN_CMPNEQPD,
20194 IX86_BUILTIN_CMPNLTPD,
20195 IX86_BUILTIN_CMPNLEPD,
20196 IX86_BUILTIN_CMPNGTPD,
20197 IX86_BUILTIN_CMPNGEPD,
20198 IX86_BUILTIN_CMPORDPD,
20199 IX86_BUILTIN_CMPUNORDPD,
20200 IX86_BUILTIN_CMPEQSD,
20201 IX86_BUILTIN_CMPLTSD,
20202 IX86_BUILTIN_CMPLESD,
20203 IX86_BUILTIN_CMPNEQSD,
20204 IX86_BUILTIN_CMPNLTSD,
20205 IX86_BUILTIN_CMPNLESD,
20206 IX86_BUILTIN_CMPORDSD,
20207 IX86_BUILTIN_CMPUNORDSD,
20209 IX86_BUILTIN_COMIEQSD,
20210 IX86_BUILTIN_COMILTSD,
20211 IX86_BUILTIN_COMILESD,
20212 IX86_BUILTIN_COMIGTSD,
20213 IX86_BUILTIN_COMIGESD,
20214 IX86_BUILTIN_COMINEQSD,
20215 IX86_BUILTIN_UCOMIEQSD,
20216 IX86_BUILTIN_UCOMILTSD,
20217 IX86_BUILTIN_UCOMILESD,
20218 IX86_BUILTIN_UCOMIGTSD,
20219 IX86_BUILTIN_UCOMIGESD,
20220 IX86_BUILTIN_UCOMINEQSD,
20222 IX86_BUILTIN_MAXPD,
20223 IX86_BUILTIN_MAXSD,
20224 IX86_BUILTIN_MINPD,
20225 IX86_BUILTIN_MINSD,
20227 IX86_BUILTIN_ANDPD,
20228 IX86_BUILTIN_ANDNPD,
20230 IX86_BUILTIN_XORPD,
20232 IX86_BUILTIN_SQRTPD,
20233 IX86_BUILTIN_SQRTSD,
20235 IX86_BUILTIN_UNPCKHPD,
20236 IX86_BUILTIN_UNPCKLPD,
20238 IX86_BUILTIN_SHUFPD,
20240 IX86_BUILTIN_LOADUPD,
20241 IX86_BUILTIN_STOREUPD,
20242 IX86_BUILTIN_MOVSD,
20244 IX86_BUILTIN_LOADHPD,
20245 IX86_BUILTIN_LOADLPD,
20247 IX86_BUILTIN_CVTDQ2PD,
20248 IX86_BUILTIN_CVTDQ2PS,
20250 IX86_BUILTIN_CVTPD2DQ,
20251 IX86_BUILTIN_CVTPD2PI,
20252 IX86_BUILTIN_CVTPD2PS,
20253 IX86_BUILTIN_CVTTPD2DQ,
20254 IX86_BUILTIN_CVTTPD2PI,
20256 IX86_BUILTIN_CVTPI2PD,
20257 IX86_BUILTIN_CVTSI2SD,
20258 IX86_BUILTIN_CVTSI642SD,
20260 IX86_BUILTIN_CVTSD2SI,
20261 IX86_BUILTIN_CVTSD2SI64,
20262 IX86_BUILTIN_CVTSD2SS,
20263 IX86_BUILTIN_CVTSS2SD,
20264 IX86_BUILTIN_CVTTSD2SI,
20265 IX86_BUILTIN_CVTTSD2SI64,
20267 IX86_BUILTIN_CVTPS2DQ,
20268 IX86_BUILTIN_CVTPS2PD,
20269 IX86_BUILTIN_CVTTPS2DQ,
20271 IX86_BUILTIN_MOVNTI,
20272 IX86_BUILTIN_MOVNTPD,
20273 IX86_BUILTIN_MOVNTDQ,
20275 IX86_BUILTIN_MOVQ128,
20278 IX86_BUILTIN_MASKMOVDQU,
20279 IX86_BUILTIN_MOVMSKPD,
20280 IX86_BUILTIN_PMOVMSKB128,
20282 IX86_BUILTIN_PACKSSWB128,
20283 IX86_BUILTIN_PACKSSDW128,
20284 IX86_BUILTIN_PACKUSWB128,
20286 IX86_BUILTIN_PADDB128,
20287 IX86_BUILTIN_PADDW128,
20288 IX86_BUILTIN_PADDD128,
20289 IX86_BUILTIN_PADDQ128,
20290 IX86_BUILTIN_PADDSB128,
20291 IX86_BUILTIN_PADDSW128,
20292 IX86_BUILTIN_PADDUSB128,
20293 IX86_BUILTIN_PADDUSW128,
20294 IX86_BUILTIN_PSUBB128,
20295 IX86_BUILTIN_PSUBW128,
20296 IX86_BUILTIN_PSUBD128,
20297 IX86_BUILTIN_PSUBQ128,
20298 IX86_BUILTIN_PSUBSB128,
20299 IX86_BUILTIN_PSUBSW128,
20300 IX86_BUILTIN_PSUBUSB128,
20301 IX86_BUILTIN_PSUBUSW128,
20303 IX86_BUILTIN_PAND128,
20304 IX86_BUILTIN_PANDN128,
20305 IX86_BUILTIN_POR128,
20306 IX86_BUILTIN_PXOR128,
20308 IX86_BUILTIN_PAVGB128,
20309 IX86_BUILTIN_PAVGW128,
20311 IX86_BUILTIN_PCMPEQB128,
20312 IX86_BUILTIN_PCMPEQW128,
20313 IX86_BUILTIN_PCMPEQD128,
20314 IX86_BUILTIN_PCMPGTB128,
20315 IX86_BUILTIN_PCMPGTW128,
20316 IX86_BUILTIN_PCMPGTD128,
20318 IX86_BUILTIN_PMADDWD128,
20320 IX86_BUILTIN_PMAXSW128,
20321 IX86_BUILTIN_PMAXUB128,
20322 IX86_BUILTIN_PMINSW128,
20323 IX86_BUILTIN_PMINUB128,
20325 IX86_BUILTIN_PMULUDQ,
20326 IX86_BUILTIN_PMULUDQ128,
20327 IX86_BUILTIN_PMULHUW128,
20328 IX86_BUILTIN_PMULHW128,
20329 IX86_BUILTIN_PMULLW128,
20331 IX86_BUILTIN_PSADBW128,
20332 IX86_BUILTIN_PSHUFHW,
20333 IX86_BUILTIN_PSHUFLW,
20334 IX86_BUILTIN_PSHUFD,
20336 IX86_BUILTIN_PSLLDQI128,
20337 IX86_BUILTIN_PSLLWI128,
20338 IX86_BUILTIN_PSLLDI128,
20339 IX86_BUILTIN_PSLLQI128,
20340 IX86_BUILTIN_PSRAWI128,
20341 IX86_BUILTIN_PSRADI128,
20342 IX86_BUILTIN_PSRLDQI128,
20343 IX86_BUILTIN_PSRLWI128,
20344 IX86_BUILTIN_PSRLDI128,
20345 IX86_BUILTIN_PSRLQI128,
20347 IX86_BUILTIN_PSLLDQ128,
20348 IX86_BUILTIN_PSLLW128,
20349 IX86_BUILTIN_PSLLD128,
20350 IX86_BUILTIN_PSLLQ128,
20351 IX86_BUILTIN_PSRAW128,
20352 IX86_BUILTIN_PSRAD128,
20353 IX86_BUILTIN_PSRLW128,
20354 IX86_BUILTIN_PSRLD128,
20355 IX86_BUILTIN_PSRLQ128,
20357 IX86_BUILTIN_PUNPCKHBW128,
20358 IX86_BUILTIN_PUNPCKHWD128,
20359 IX86_BUILTIN_PUNPCKHDQ128,
20360 IX86_BUILTIN_PUNPCKHQDQ128,
20361 IX86_BUILTIN_PUNPCKLBW128,
20362 IX86_BUILTIN_PUNPCKLWD128,
20363 IX86_BUILTIN_PUNPCKLDQ128,
20364 IX86_BUILTIN_PUNPCKLQDQ128,
20366 IX86_BUILTIN_CLFLUSH,
20367 IX86_BUILTIN_MFENCE,
20368 IX86_BUILTIN_LFENCE,
20370 IX86_BUILTIN_BSRSI,
20371 IX86_BUILTIN_BSRDI,
20372 IX86_BUILTIN_RDPMC,
20373 IX86_BUILTIN_RDTSC,
20374 IX86_BUILTIN_RDTSCP,
20375 IX86_BUILTIN_ROLQI,
20376 IX86_BUILTIN_ROLHI,
20377 IX86_BUILTIN_RORQI,
20378 IX86_BUILTIN_RORHI,
20381 IX86_BUILTIN_ADDSUBPS,
20382 IX86_BUILTIN_HADDPS,
20383 IX86_BUILTIN_HSUBPS,
20384 IX86_BUILTIN_MOVSHDUP,
20385 IX86_BUILTIN_MOVSLDUP,
20386 IX86_BUILTIN_ADDSUBPD,
20387 IX86_BUILTIN_HADDPD,
20388 IX86_BUILTIN_HSUBPD,
20389 IX86_BUILTIN_LDDQU,
20391 IX86_BUILTIN_MONITOR,
20392 IX86_BUILTIN_MWAIT,
20395 IX86_BUILTIN_PHADDW,
20396 IX86_BUILTIN_PHADDD,
20397 IX86_BUILTIN_PHADDSW,
20398 IX86_BUILTIN_PHSUBW,
20399 IX86_BUILTIN_PHSUBD,
20400 IX86_BUILTIN_PHSUBSW,
20401 IX86_BUILTIN_PMADDUBSW,
20402 IX86_BUILTIN_PMULHRSW,
20403 IX86_BUILTIN_PSHUFB,
20404 IX86_BUILTIN_PSIGNB,
20405 IX86_BUILTIN_PSIGNW,
20406 IX86_BUILTIN_PSIGND,
20407 IX86_BUILTIN_PALIGNR,
20408 IX86_BUILTIN_PABSB,
20409 IX86_BUILTIN_PABSW,
20410 IX86_BUILTIN_PABSD,
20412 IX86_BUILTIN_PHADDW128,
20413 IX86_BUILTIN_PHADDD128,
20414 IX86_BUILTIN_PHADDSW128,
20415 IX86_BUILTIN_PHSUBW128,
20416 IX86_BUILTIN_PHSUBD128,
20417 IX86_BUILTIN_PHSUBSW128,
20418 IX86_BUILTIN_PMADDUBSW128,
20419 IX86_BUILTIN_PMULHRSW128,
20420 IX86_BUILTIN_PSHUFB128,
20421 IX86_BUILTIN_PSIGNB128,
20422 IX86_BUILTIN_PSIGNW128,
20423 IX86_BUILTIN_PSIGND128,
20424 IX86_BUILTIN_PALIGNR128,
20425 IX86_BUILTIN_PABSB128,
20426 IX86_BUILTIN_PABSW128,
20427 IX86_BUILTIN_PABSD128,
20429 /* AMDFAM10 - SSE4A New Instructions. */
20430 IX86_BUILTIN_MOVNTSD,
20431 IX86_BUILTIN_MOVNTSS,
20432 IX86_BUILTIN_EXTRQI,
20433 IX86_BUILTIN_EXTRQ,
20434 IX86_BUILTIN_INSERTQI,
20435 IX86_BUILTIN_INSERTQ,
20438 IX86_BUILTIN_BLENDPD,
20439 IX86_BUILTIN_BLENDPS,
20440 IX86_BUILTIN_BLENDVPD,
20441 IX86_BUILTIN_BLENDVPS,
20442 IX86_BUILTIN_PBLENDVB128,
20443 IX86_BUILTIN_PBLENDW128,
20448 IX86_BUILTIN_INSERTPS128,
20450 IX86_BUILTIN_MOVNTDQA,
20451 IX86_BUILTIN_MPSADBW128,
20452 IX86_BUILTIN_PACKUSDW128,
20453 IX86_BUILTIN_PCMPEQQ,
20454 IX86_BUILTIN_PHMINPOSUW128,
20456 IX86_BUILTIN_PMAXSB128,
20457 IX86_BUILTIN_PMAXSD128,
20458 IX86_BUILTIN_PMAXUD128,
20459 IX86_BUILTIN_PMAXUW128,
20461 IX86_BUILTIN_PMINSB128,
20462 IX86_BUILTIN_PMINSD128,
20463 IX86_BUILTIN_PMINUD128,
20464 IX86_BUILTIN_PMINUW128,
20466 IX86_BUILTIN_PMOVSXBW128,
20467 IX86_BUILTIN_PMOVSXBD128,
20468 IX86_BUILTIN_PMOVSXBQ128,
20469 IX86_BUILTIN_PMOVSXWD128,
20470 IX86_BUILTIN_PMOVSXWQ128,
20471 IX86_BUILTIN_PMOVSXDQ128,
20473 IX86_BUILTIN_PMOVZXBW128,
20474 IX86_BUILTIN_PMOVZXBD128,
20475 IX86_BUILTIN_PMOVZXBQ128,
20476 IX86_BUILTIN_PMOVZXWD128,
20477 IX86_BUILTIN_PMOVZXWQ128,
20478 IX86_BUILTIN_PMOVZXDQ128,
20480 IX86_BUILTIN_PMULDQ128,
20481 IX86_BUILTIN_PMULLD128,
20483 IX86_BUILTIN_ROUNDPD,
20484 IX86_BUILTIN_ROUNDPS,
20485 IX86_BUILTIN_ROUNDSD,
20486 IX86_BUILTIN_ROUNDSS,
20488 IX86_BUILTIN_PTESTZ,
20489 IX86_BUILTIN_PTESTC,
20490 IX86_BUILTIN_PTESTNZC,
20492 IX86_BUILTIN_VEC_INIT_V2SI,
20493 IX86_BUILTIN_VEC_INIT_V4HI,
20494 IX86_BUILTIN_VEC_INIT_V8QI,
20495 IX86_BUILTIN_VEC_EXT_V2DF,
20496 IX86_BUILTIN_VEC_EXT_V2DI,
20497 IX86_BUILTIN_VEC_EXT_V4SF,
20498 IX86_BUILTIN_VEC_EXT_V4SI,
20499 IX86_BUILTIN_VEC_EXT_V8HI,
20500 IX86_BUILTIN_VEC_EXT_V2SI,
20501 IX86_BUILTIN_VEC_EXT_V4HI,
20502 IX86_BUILTIN_VEC_EXT_V16QI,
20503 IX86_BUILTIN_VEC_SET_V2DI,
20504 IX86_BUILTIN_VEC_SET_V4SF,
20505 IX86_BUILTIN_VEC_SET_V4SI,
20506 IX86_BUILTIN_VEC_SET_V8HI,
20507 IX86_BUILTIN_VEC_SET_V4HI,
20508 IX86_BUILTIN_VEC_SET_V16QI,
20510 IX86_BUILTIN_VEC_PACK_SFIX,
20513 IX86_BUILTIN_CRC32QI,
20514 IX86_BUILTIN_CRC32HI,
20515 IX86_BUILTIN_CRC32SI,
20516 IX86_BUILTIN_CRC32DI,
20518 IX86_BUILTIN_PCMPESTRI128,
20519 IX86_BUILTIN_PCMPESTRM128,
20520 IX86_BUILTIN_PCMPESTRA128,
20521 IX86_BUILTIN_PCMPESTRC128,
20522 IX86_BUILTIN_PCMPESTRO128,
20523 IX86_BUILTIN_PCMPESTRS128,
20524 IX86_BUILTIN_PCMPESTRZ128,
20525 IX86_BUILTIN_PCMPISTRI128,
20526 IX86_BUILTIN_PCMPISTRM128,
20527 IX86_BUILTIN_PCMPISTRA128,
20528 IX86_BUILTIN_PCMPISTRC128,
20529 IX86_BUILTIN_PCMPISTRO128,
20530 IX86_BUILTIN_PCMPISTRS128,
20531 IX86_BUILTIN_PCMPISTRZ128,
20533 IX86_BUILTIN_PCMPGTQ,
20535 /* AES instructions */
20536 IX86_BUILTIN_AESENC128,
20537 IX86_BUILTIN_AESENCLAST128,
20538 IX86_BUILTIN_AESDEC128,
20539 IX86_BUILTIN_AESDECLAST128,
20540 IX86_BUILTIN_AESIMC128,
20541 IX86_BUILTIN_AESKEYGENASSIST128,
20543 /* PCLMUL instruction */
20544 IX86_BUILTIN_PCLMULQDQ128,
20547 IX86_BUILTIN_ADDPD256,
20548 IX86_BUILTIN_ADDPS256,
20549 IX86_BUILTIN_ADDSUBPD256,
20550 IX86_BUILTIN_ADDSUBPS256,
20551 IX86_BUILTIN_ANDPD256,
20552 IX86_BUILTIN_ANDPS256,
20553 IX86_BUILTIN_ANDNPD256,
20554 IX86_BUILTIN_ANDNPS256,
20555 IX86_BUILTIN_BLENDPD256,
20556 IX86_BUILTIN_BLENDPS256,
20557 IX86_BUILTIN_BLENDVPD256,
20558 IX86_BUILTIN_BLENDVPS256,
20559 IX86_BUILTIN_DIVPD256,
20560 IX86_BUILTIN_DIVPS256,
20561 IX86_BUILTIN_DPPS256,
20562 IX86_BUILTIN_HADDPD256,
20563 IX86_BUILTIN_HADDPS256,
20564 IX86_BUILTIN_HSUBPD256,
20565 IX86_BUILTIN_HSUBPS256,
20566 IX86_BUILTIN_MAXPD256,
20567 IX86_BUILTIN_MAXPS256,
20568 IX86_BUILTIN_MINPD256,
20569 IX86_BUILTIN_MINPS256,
20570 IX86_BUILTIN_MULPD256,
20571 IX86_BUILTIN_MULPS256,
20572 IX86_BUILTIN_ORPD256,
20573 IX86_BUILTIN_ORPS256,
20574 IX86_BUILTIN_SHUFPD256,
20575 IX86_BUILTIN_SHUFPS256,
20576 IX86_BUILTIN_SUBPD256,
20577 IX86_BUILTIN_SUBPS256,
20578 IX86_BUILTIN_XORPD256,
20579 IX86_BUILTIN_XORPS256,
20580 IX86_BUILTIN_CMPSD,
20581 IX86_BUILTIN_CMPSS,
20582 IX86_BUILTIN_CMPPD,
20583 IX86_BUILTIN_CMPPS,
20584 IX86_BUILTIN_CMPPD256,
20585 IX86_BUILTIN_CMPPS256,
20586 IX86_BUILTIN_CVTDQ2PD256,
20587 IX86_BUILTIN_CVTDQ2PS256,
20588 IX86_BUILTIN_CVTPD2PS256,
20589 IX86_BUILTIN_CVTPS2DQ256,
20590 IX86_BUILTIN_CVTPS2PD256,
20591 IX86_BUILTIN_CVTTPD2DQ256,
20592 IX86_BUILTIN_CVTPD2DQ256,
20593 IX86_BUILTIN_CVTTPS2DQ256,
20594 IX86_BUILTIN_EXTRACTF128PD256,
20595 IX86_BUILTIN_EXTRACTF128PS256,
20596 IX86_BUILTIN_EXTRACTF128SI256,
20597 IX86_BUILTIN_VZEROALL,
20598 IX86_BUILTIN_VZEROUPPER,
20599 IX86_BUILTIN_VZEROUPPER_REX64,
20600 IX86_BUILTIN_VPERMILVARPD,
20601 IX86_BUILTIN_VPERMILVARPS,
20602 IX86_BUILTIN_VPERMILVARPD256,
20603 IX86_BUILTIN_VPERMILVARPS256,
20604 IX86_BUILTIN_VPERMILPD,
20605 IX86_BUILTIN_VPERMILPS,
20606 IX86_BUILTIN_VPERMILPD256,
20607 IX86_BUILTIN_VPERMILPS256,
20608 IX86_BUILTIN_VPERM2F128PD256,
20609 IX86_BUILTIN_VPERM2F128PS256,
20610 IX86_BUILTIN_VPERM2F128SI256,
20611 IX86_BUILTIN_VBROADCASTSS,
20612 IX86_BUILTIN_VBROADCASTSD256,
20613 IX86_BUILTIN_VBROADCASTSS256,
20614 IX86_BUILTIN_VBROADCASTPD256,
20615 IX86_BUILTIN_VBROADCASTPS256,
20616 IX86_BUILTIN_VINSERTF128PD256,
20617 IX86_BUILTIN_VINSERTF128PS256,
20618 IX86_BUILTIN_VINSERTF128SI256,
20619 IX86_BUILTIN_LOADUPD256,
20620 IX86_BUILTIN_LOADUPS256,
20621 IX86_BUILTIN_STOREUPD256,
20622 IX86_BUILTIN_STOREUPS256,
20623 IX86_BUILTIN_LDDQU256,
20624 IX86_BUILTIN_MOVNTDQ256,
20625 IX86_BUILTIN_MOVNTPD256,
20626 IX86_BUILTIN_MOVNTPS256,
20627 IX86_BUILTIN_LOADDQU256,
20628 IX86_BUILTIN_STOREDQU256,
20629 IX86_BUILTIN_MASKLOADPD,
20630 IX86_BUILTIN_MASKLOADPS,
20631 IX86_BUILTIN_MASKSTOREPD,
20632 IX86_BUILTIN_MASKSTOREPS,
20633 IX86_BUILTIN_MASKLOADPD256,
20634 IX86_BUILTIN_MASKLOADPS256,
20635 IX86_BUILTIN_MASKSTOREPD256,
20636 IX86_BUILTIN_MASKSTOREPS256,
20637 IX86_BUILTIN_MOVSHDUP256,
20638 IX86_BUILTIN_MOVSLDUP256,
20639 IX86_BUILTIN_MOVDDUP256,
20641 IX86_BUILTIN_SQRTPD256,
20642 IX86_BUILTIN_SQRTPS256,
20643 IX86_BUILTIN_SQRTPS_NR256,
20644 IX86_BUILTIN_RSQRTPS256,
20645 IX86_BUILTIN_RSQRTPS_NR256,
20647 IX86_BUILTIN_RCPPS256,
20649 IX86_BUILTIN_ROUNDPD256,
20650 IX86_BUILTIN_ROUNDPS256,
20652 IX86_BUILTIN_UNPCKHPD256,
20653 IX86_BUILTIN_UNPCKLPD256,
20654 IX86_BUILTIN_UNPCKHPS256,
20655 IX86_BUILTIN_UNPCKLPS256,
20657 IX86_BUILTIN_SI256_SI,
20658 IX86_BUILTIN_PS256_PS,
20659 IX86_BUILTIN_PD256_PD,
20660 IX86_BUILTIN_SI_SI256,
20661 IX86_BUILTIN_PS_PS256,
20662 IX86_BUILTIN_PD_PD256,
20664 IX86_BUILTIN_VTESTZPD,
20665 IX86_BUILTIN_VTESTCPD,
20666 IX86_BUILTIN_VTESTNZCPD,
20667 IX86_BUILTIN_VTESTZPS,
20668 IX86_BUILTIN_VTESTCPS,
20669 IX86_BUILTIN_VTESTNZCPS,
20670 IX86_BUILTIN_VTESTZPD256,
20671 IX86_BUILTIN_VTESTCPD256,
20672 IX86_BUILTIN_VTESTNZCPD256,
20673 IX86_BUILTIN_VTESTZPS256,
20674 IX86_BUILTIN_VTESTCPS256,
20675 IX86_BUILTIN_VTESTNZCPS256,
20676 IX86_BUILTIN_PTESTZ256,
20677 IX86_BUILTIN_PTESTC256,
20678 IX86_BUILTIN_PTESTNZC256,
20680 IX86_BUILTIN_MOVMSKPD256,
20681 IX86_BUILTIN_MOVMSKPS256,
20683 /* TFmode support builtins. */
20685 IX86_BUILTIN_HUGE_VALQ,
20686 IX86_BUILTIN_FABSQ,
20687 IX86_BUILTIN_COPYSIGNQ,
20689 /* Vectorizer support builtins. */
20690 IX86_BUILTIN_CPYSGNPS,
20691 IX86_BUILTIN_CPYSGNPD,
20693 IX86_BUILTIN_CVTUDQ2PS,
20698 /* Table for the ix86 builtin decls. */
20699 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20701 /* Table of all of the builtin functions that are possible with different ISA's
20702 but are waiting to be built until a function is declared to use that
20704 struct GTY(()) builtin_isa {
20705 tree type; /* builtin type to use in the declaration */
20706 const char *name; /* function name */
20707 int isa; /* isa_flags this builtin is defined for */
20708 bool const_p; /* true if the declaration is constant */
20711 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20714 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20715 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20716 * function decl in the ix86_builtins array. Returns the function decl or
20717 * NULL_TREE, if the builtin was not added.
20719 * If the front end has a special hook for builtin functions, delay adding
20720 * builtin functions that aren't in the current ISA until the ISA is changed
20721 * with function specific optimization. Doing so, can save about 300K for the
20722 * default compiler. When the builtin is expanded, check at that time whether
20725 * If the front end doesn't have a special hook, record all builtins, even if
20726 * it isn't an instruction set in the current ISA in case the user uses
20727 * function specific options for a different ISA, so that we don't get scope
20728 * errors if a builtin is added in the middle of a function scope. */
20731 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20733 tree decl = NULL_TREE;
20735 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20737 ix86_builtins_isa[(int) code].isa = mask;
20739 if ((mask & ix86_isa_flags) != 0
20740 || (lang_hooks.builtin_function
20741 == lang_hooks.builtin_function_ext_scope))
20744 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20746 ix86_builtins[(int) code] = decl;
20747 ix86_builtins_isa[(int) code].type = NULL_TREE;
20751 ix86_builtins[(int) code] = NULL_TREE;
20752 ix86_builtins_isa[(int) code].const_p = false;
20753 ix86_builtins_isa[(int) code].type = type;
20754 ix86_builtins_isa[(int) code].name = name;
20761 /* Like def_builtin, but also marks the function decl "const". */
20764 def_builtin_const (int mask, const char *name, tree type,
20765 enum ix86_builtins code)
20767 tree decl = def_builtin (mask, name, type, code);
20769 TREE_READONLY (decl) = 1;
20771 ix86_builtins_isa[(int) code].const_p = true;
20776 /* Add any new builtin functions for a given ISA that may not have been
20777 declared. This saves a bit of space compared to adding all of the
20778 declarations to the tree, even if we didn't use them. */
20781 ix86_add_new_builtins (int isa)
20786 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20788 if ((ix86_builtins_isa[i].isa & isa) != 0
20789 && ix86_builtins_isa[i].type != NULL_TREE)
20791 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20792 ix86_builtins_isa[i].type,
20793 i, BUILT_IN_MD, NULL,
20796 ix86_builtins[i] = decl;
20797 ix86_builtins_isa[i].type = NULL_TREE;
20798 if (ix86_builtins_isa[i].const_p)
20799 TREE_READONLY (decl) = 1;
20804 /* Bits for builtin_description.flag. */
20806 /* Set when we don't support the comparison natively, and should
20807 swap_comparison in order to support it. */
20808 #define BUILTIN_DESC_SWAP_OPERANDS 1
20810 struct builtin_description
20812 const unsigned int mask;
20813 const enum insn_code icode;
20814 const char *const name;
20815 const enum ix86_builtins code;
20816 const enum rtx_code comparison;
20820 static const struct builtin_description bdesc_comi[] =
20822 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20823 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20824 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20825 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20826 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20827 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20828 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20829 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20830 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20831 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20832 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20833 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20834 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20835 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20836 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20837 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20838 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20839 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20840 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20841 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20842 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20843 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20844 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20845 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20848 static const struct builtin_description bdesc_pcmpestr[] =
20851 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20852 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20853 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20854 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20855 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20856 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20857 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20860 static const struct builtin_description bdesc_pcmpistr[] =
20863 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20864 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20865 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20866 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20867 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20868 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20869 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20872 /* Special builtin types */
20873 enum ix86_special_builtin_type
20875 SPECIAL_FTYPE_UNKNOWN,
20878 UINT64_FTYPE_PUNSIGNED,
20879 V32QI_FTYPE_PCCHAR,
20880 V16QI_FTYPE_PCCHAR,
20882 V8SF_FTYPE_PCFLOAT,
20884 V4DF_FTYPE_PCDOUBLE,
20885 V4SF_FTYPE_PCFLOAT,
20886 V2DF_FTYPE_PCDOUBLE,
20887 V8SF_FTYPE_PCV8SF_V8SF,
20888 V4DF_FTYPE_PCV4DF_V4DF,
20889 V4SF_FTYPE_V4SF_PCV2SF,
20890 V4SF_FTYPE_PCV4SF_V4SF,
20891 V2DF_FTYPE_V2DF_PCDOUBLE,
20892 V2DF_FTYPE_PCV2DF_V2DF,
20894 VOID_FTYPE_PV2SF_V4SF,
20895 VOID_FTYPE_PV4DI_V4DI,
20896 VOID_FTYPE_PV2DI_V2DI,
20897 VOID_FTYPE_PCHAR_V32QI,
20898 VOID_FTYPE_PCHAR_V16QI,
20899 VOID_FTYPE_PFLOAT_V8SF,
20900 VOID_FTYPE_PFLOAT_V4SF,
20901 VOID_FTYPE_PDOUBLE_V4DF,
20902 VOID_FTYPE_PDOUBLE_V2DF,
20904 VOID_FTYPE_PINT_INT,
20905 VOID_FTYPE_PV8SF_V8SF_V8SF,
20906 VOID_FTYPE_PV4DF_V4DF_V4DF,
20907 VOID_FTYPE_PV4SF_V4SF_V4SF,
20908 VOID_FTYPE_PV2DF_V2DF_V2DF
20911 /* Builtin types */
20912 enum ix86_builtin_type
20915 FLOAT128_FTYPE_FLOAT128,
20917 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20918 INT_FTYPE_V8SF_V8SF_PTEST,
20919 INT_FTYPE_V4DI_V4DI_PTEST,
20920 INT_FTYPE_V4DF_V4DF_PTEST,
20921 INT_FTYPE_V4SF_V4SF_PTEST,
20922 INT_FTYPE_V2DI_V2DI_PTEST,
20923 INT_FTYPE_V2DF_V2DF_PTEST,
20958 V4SF_FTYPE_V4SF_VEC_MERGE,
20967 V2DF_FTYPE_V2DF_VEC_MERGE,
20978 V16QI_FTYPE_V16QI_V16QI,
20979 V16QI_FTYPE_V8HI_V8HI,
20980 V8QI_FTYPE_V8QI_V8QI,
20981 V8QI_FTYPE_V4HI_V4HI,
20982 V8HI_FTYPE_V8HI_V8HI,
20983 V8HI_FTYPE_V8HI_V8HI_COUNT,
20984 V8HI_FTYPE_V16QI_V16QI,
20985 V8HI_FTYPE_V4SI_V4SI,
20986 V8HI_FTYPE_V8HI_SI_COUNT,
20987 V8SF_FTYPE_V8SF_V8SF,
20988 V8SF_FTYPE_V8SF_V8SI,
20989 V4SI_FTYPE_V4SI_V4SI,
20990 V4SI_FTYPE_V4SI_V4SI_COUNT,
20991 V4SI_FTYPE_V8HI_V8HI,
20992 V4SI_FTYPE_V4SF_V4SF,
20993 V4SI_FTYPE_V2DF_V2DF,
20994 V4SI_FTYPE_V4SI_SI_COUNT,
20995 V4HI_FTYPE_V4HI_V4HI,
20996 V4HI_FTYPE_V4HI_V4HI_COUNT,
20997 V4HI_FTYPE_V8QI_V8QI,
20998 V4HI_FTYPE_V2SI_V2SI,
20999 V4HI_FTYPE_V4HI_SI_COUNT,
21000 V4DF_FTYPE_V4DF_V4DF,
21001 V4DF_FTYPE_V4DF_V4DI,
21002 V4SF_FTYPE_V4SF_V4SF,
21003 V4SF_FTYPE_V4SF_V4SF_SWAP,
21004 V4SF_FTYPE_V4SF_V4SI,
21005 V4SF_FTYPE_V4SF_V2SI,
21006 V4SF_FTYPE_V4SF_V2DF,
21007 V4SF_FTYPE_V4SF_DI,
21008 V4SF_FTYPE_V4SF_SI,
21009 V2DI_FTYPE_V2DI_V2DI,
21010 V2DI_FTYPE_V2DI_V2DI_COUNT,
21011 V2DI_FTYPE_V16QI_V16QI,
21012 V2DI_FTYPE_V4SI_V4SI,
21013 V2DI_FTYPE_V2DI_V16QI,
21014 V2DI_FTYPE_V2DF_V2DF,
21015 V2DI_FTYPE_V2DI_SI_COUNT,
21016 V2SI_FTYPE_V2SI_V2SI,
21017 V2SI_FTYPE_V2SI_V2SI_COUNT,
21018 V2SI_FTYPE_V4HI_V4HI,
21019 V2SI_FTYPE_V2SF_V2SF,
21020 V2SI_FTYPE_V2SI_SI_COUNT,
21021 V2DF_FTYPE_V2DF_V2DF,
21022 V2DF_FTYPE_V2DF_V2DF_SWAP,
21023 V2DF_FTYPE_V2DF_V4SF,
21024 V2DF_FTYPE_V2DF_V2DI,
21025 V2DF_FTYPE_V2DF_DI,
21026 V2DF_FTYPE_V2DF_SI,
21027 V2SF_FTYPE_V2SF_V2SF,
21028 V1DI_FTYPE_V1DI_V1DI,
21029 V1DI_FTYPE_V1DI_V1DI_COUNT,
21030 V1DI_FTYPE_V8QI_V8QI,
21031 V1DI_FTYPE_V2SI_V2SI,
21032 V1DI_FTYPE_V1DI_SI_COUNT,
21033 UINT64_FTYPE_UINT64_UINT64,
21034 UINT_FTYPE_UINT_UINT,
21035 UINT_FTYPE_UINT_USHORT,
21036 UINT_FTYPE_UINT_UCHAR,
21037 UINT16_FTYPE_UINT16_INT,
21038 UINT8_FTYPE_UINT8_INT,
21039 V8HI_FTYPE_V8HI_INT,
21040 V4SI_FTYPE_V4SI_INT,
21041 V4HI_FTYPE_V4HI_INT,
21042 V8SF_FTYPE_V8SF_INT,
21043 V4SI_FTYPE_V8SI_INT,
21044 V4SF_FTYPE_V8SF_INT,
21045 V2DF_FTYPE_V4DF_INT,
21046 V4DF_FTYPE_V4DF_INT,
21047 V4SF_FTYPE_V4SF_INT,
21048 V2DI_FTYPE_V2DI_INT,
21049 V2DI2TI_FTYPE_V2DI_INT,
21050 V2DF_FTYPE_V2DF_INT,
21051 V16QI_FTYPE_V16QI_V16QI_V16QI,
21052 V8SF_FTYPE_V8SF_V8SF_V8SF,
21053 V4DF_FTYPE_V4DF_V4DF_V4DF,
21054 V4SF_FTYPE_V4SF_V4SF_V4SF,
21055 V2DF_FTYPE_V2DF_V2DF_V2DF,
21056 V16QI_FTYPE_V16QI_V16QI_INT,
21057 V8SI_FTYPE_V8SI_V8SI_INT,
21058 V8SI_FTYPE_V8SI_V4SI_INT,
21059 V8HI_FTYPE_V8HI_V8HI_INT,
21060 V8SF_FTYPE_V8SF_V8SF_INT,
21061 V8SF_FTYPE_V8SF_V4SF_INT,
21062 V4SI_FTYPE_V4SI_V4SI_INT,
21063 V4DF_FTYPE_V4DF_V4DF_INT,
21064 V4DF_FTYPE_V4DF_V2DF_INT,
21065 V4SF_FTYPE_V4SF_V4SF_INT,
21066 V2DI_FTYPE_V2DI_V2DI_INT,
21067 V2DI2TI_FTYPE_V2DI_V2DI_INT,
21068 V1DI2DI_FTYPE_V1DI_V1DI_INT,
21069 V2DF_FTYPE_V2DF_V2DF_INT,
21070 V2DI_FTYPE_V2DI_UINT_UINT,
21071 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
21074 /* Special builtins with variable number of arguments. */
21075 static const struct builtin_description bdesc_special_args[] =
21077 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21078 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21081 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21084 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21087 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21088 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21089 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21091 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21092 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21093 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21094 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21096 /* SSE or 3DNow!A */
21097 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21098 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
21101 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21102 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21103 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21104 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21105 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21106 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21107 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21108 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21109 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21111 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21112 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21115 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21118 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21121 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21122 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21125 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21126 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21127 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21129 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21130 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21131 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21132 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21133 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21135 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21136 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21137 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21138 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21139 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21140 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21141 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21143 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21144 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21145 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21147 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21148 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21149 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21150 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21151 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21152 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21153 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21154 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21157 /* Builtins with variable number of arguments. */
21158 static const struct builtin_description bdesc_args[] =
21160 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21161 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21162 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21163 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21164 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21165 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21166 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21169 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21170 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21171 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21172 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21173 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21174 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21176 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21177 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21178 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21179 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21180 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21181 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21182 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21183 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21185 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21186 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21188 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21189 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21190 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21191 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21193 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21194 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21195 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21196 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21197 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21198 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21200 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21201 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21202 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21203 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21204 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21205 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21207 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21208 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21209 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21211 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21213 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21214 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21215 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21216 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21217 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21218 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21220 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21221 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21222 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21223 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21224 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21225 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21227 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21228 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21229 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21230 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21233 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21234 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21235 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21236 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21238 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21239 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21240 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21241 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21242 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21243 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21244 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21245 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21246 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21247 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21248 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21249 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21250 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21251 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21252 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21255 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21256 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21257 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21258 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21259 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21260 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21263 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21264 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21265 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21266 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21267 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21268 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21269 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21270 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21271 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21272 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21273 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21274 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21276 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21278 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21279 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21280 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21281 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21282 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21283 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21284 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21285 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21287 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21288 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21289 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21290 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21291 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21292 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21293 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21294 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21295 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21296 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21297 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21298 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21299 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21300 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21301 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21302 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21303 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21304 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21305 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21306 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21307 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21308 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21310 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21311 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21312 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21313 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21315 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21316 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21317 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21318 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21320 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21322 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21323 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21324 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21325 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21326 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21328 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21329 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21330 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21332 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21334 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21335 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21336 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21338 /* SSE MMX or 3Dnow!A */
21339 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21340 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21341 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21343 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21344 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21345 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21346 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21348 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21349 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21351 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21356 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21358 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21359 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21360 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21361 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21363 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21364 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21365 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21366 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21367 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21369 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21371 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21372 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21373 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21374 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21376 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21377 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21378 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21380 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21381 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21382 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21383 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21390 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21392 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21393 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21394 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21395 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21396 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21397 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21398 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21400 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21403 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21407 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21408 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21411 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21415 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21416 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21417 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21418 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21420 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21422 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21423 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21424 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21426 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21428 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21429 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21430 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21431 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21432 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21433 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21434 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21435 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21437 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21438 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21439 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21441 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21443 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21444 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21446 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21447 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21449 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21451 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21452 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21455 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21457 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21461 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21462 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21464 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21465 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21466 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21467 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21470 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21473 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21474 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21478 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21482 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21483 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21486 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21490 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21491 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21495 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21496 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21497 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21498 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21499 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21500 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21501 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21504 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21505 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21506 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21507 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21508 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21509 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21511 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21512 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21513 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21514 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21517 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21518 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21522 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21523 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21525 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21528 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21529 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21532 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21533 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21535 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21536 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21537 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21538 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21539 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21540 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21543 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21544 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21545 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21546 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21547 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21548 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21550 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21551 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21552 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21553 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21554 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21555 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21556 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21557 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21558 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21559 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21560 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21561 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21562 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21563 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21564 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21565 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21566 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21567 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21568 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21569 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21570 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21571 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21572 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21573 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21576 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21577 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21580 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21581 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21582 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21583 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21584 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21585 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21586 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21587 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21588 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21589 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21591 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21592 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21593 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21594 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21595 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21596 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21597 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21598 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21599 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21600 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21601 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21602 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21603 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21605 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21606 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21607 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21608 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21609 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21610 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21611 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21612 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21613 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21614 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21615 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21616 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21619 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21620 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21621 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21622 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21624 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21625 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21626 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21629 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21630 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21631 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21632 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21633 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21636 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21637 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21638 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21639 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21642 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21643 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21645 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21646 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21647 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21648 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21651 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21654 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21655 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21658 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21659 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21662 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21663 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21664 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21665 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21666 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21667 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21668 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21669 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21670 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21671 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21672 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21673 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21674 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21675 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21676 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21677 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21678 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21679 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21681 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21683 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21686 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21687 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21688 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21690 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21691 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21692 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21693 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21695 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21696 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21697 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21698 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21699 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21700 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21701 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21702 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21703 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21704 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21705 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21706 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21707 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21708 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21709 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21710 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21711 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21712 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21713 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21714 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21715 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21717 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21718 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21722 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21725 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21727 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21728 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21729 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21733 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21755 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21756 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21757 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21758 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21759 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21760 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21761 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21762 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21764 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21765 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21769 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21770 in the current target ISA to allow the user to compile particular modules
21771 with different target specific options that differ from the command line
21774 ix86_init_mmx_sse_builtins (void)
21776 const struct builtin_description * d;
21779 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21780 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21781 tree V1DI_type_node
21782 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21783 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21784 tree V2DI_type_node
21785 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21786 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21787 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21788 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21789 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21790 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21791 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21793 tree pchar_type_node = build_pointer_type (char_type_node);
21794 tree pcchar_type_node
21795 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21796 tree pfloat_type_node = build_pointer_type (float_type_node);
21797 tree pcfloat_type_node
21798 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21799 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21800 tree pcv2sf_type_node
21801 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21802 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21803 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21806 tree int_ftype_v4sf_v4sf
21807 = build_function_type_list (integer_type_node,
21808 V4SF_type_node, V4SF_type_node, NULL_TREE);
21809 tree v4si_ftype_v4sf_v4sf
21810 = build_function_type_list (V4SI_type_node,
21811 V4SF_type_node, V4SF_type_node, NULL_TREE);
21812 /* MMX/SSE/integer conversions. */
21813 tree int_ftype_v4sf
21814 = build_function_type_list (integer_type_node,
21815 V4SF_type_node, NULL_TREE);
21816 tree int64_ftype_v4sf
21817 = build_function_type_list (long_long_integer_type_node,
21818 V4SF_type_node, NULL_TREE);
21819 tree int_ftype_v8qi
21820 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21821 tree v4sf_ftype_v4sf_int
21822 = build_function_type_list (V4SF_type_node,
21823 V4SF_type_node, integer_type_node, NULL_TREE);
21824 tree v4sf_ftype_v4sf_int64
21825 = build_function_type_list (V4SF_type_node,
21826 V4SF_type_node, long_long_integer_type_node,
21828 tree v4sf_ftype_v4sf_v2si
21829 = build_function_type_list (V4SF_type_node,
21830 V4SF_type_node, V2SI_type_node, NULL_TREE);
21832 /* Miscellaneous. */
21833 tree v8qi_ftype_v4hi_v4hi
21834 = build_function_type_list (V8QI_type_node,
21835 V4HI_type_node, V4HI_type_node, NULL_TREE);
21836 tree v4hi_ftype_v2si_v2si
21837 = build_function_type_list (V4HI_type_node,
21838 V2SI_type_node, V2SI_type_node, NULL_TREE);
21839 tree v4sf_ftype_v4sf_v4sf_int
21840 = build_function_type_list (V4SF_type_node,
21841 V4SF_type_node, V4SF_type_node,
21842 integer_type_node, NULL_TREE);
21843 tree v2si_ftype_v4hi_v4hi
21844 = build_function_type_list (V2SI_type_node,
21845 V4HI_type_node, V4HI_type_node, NULL_TREE);
21846 tree v4hi_ftype_v4hi_int
21847 = build_function_type_list (V4HI_type_node,
21848 V4HI_type_node, integer_type_node, NULL_TREE);
21849 tree v2si_ftype_v2si_int
21850 = build_function_type_list (V2SI_type_node,
21851 V2SI_type_node, integer_type_node, NULL_TREE);
21852 tree v1di_ftype_v1di_int
21853 = build_function_type_list (V1DI_type_node,
21854 V1DI_type_node, integer_type_node, NULL_TREE);
21856 tree void_ftype_void
21857 = build_function_type (void_type_node, void_list_node);
21858 tree void_ftype_unsigned
21859 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
21860 tree void_ftype_unsigned_unsigned
21861 = build_function_type_list (void_type_node, unsigned_type_node,
21862 unsigned_type_node, NULL_TREE);
21863 tree void_ftype_pcvoid_unsigned_unsigned
21864 = build_function_type_list (void_type_node, const_ptr_type_node,
21865 unsigned_type_node, unsigned_type_node,
21867 tree unsigned_ftype_void
21868 = build_function_type (unsigned_type_node, void_list_node);
21869 tree v2si_ftype_v4sf
21870 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
21871 /* Loads/stores. */
21872 tree void_ftype_v8qi_v8qi_pchar
21873 = build_function_type_list (void_type_node,
21874 V8QI_type_node, V8QI_type_node,
21875 pchar_type_node, NULL_TREE);
21876 tree v4sf_ftype_pcfloat
21877 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
21878 tree v4sf_ftype_v4sf_pcv2sf
21879 = build_function_type_list (V4SF_type_node,
21880 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
21881 tree void_ftype_pv2sf_v4sf
21882 = build_function_type_list (void_type_node,
21883 pv2sf_type_node, V4SF_type_node, NULL_TREE);
21884 tree void_ftype_pfloat_v4sf
21885 = build_function_type_list (void_type_node,
21886 pfloat_type_node, V4SF_type_node, NULL_TREE);
21887 tree void_ftype_pdi_di
21888 = build_function_type_list (void_type_node,
21889 pdi_type_node, long_long_unsigned_type_node,
21891 tree void_ftype_pv2di_v2di
21892 = build_function_type_list (void_type_node,
21893 pv2di_type_node, V2DI_type_node, NULL_TREE);
21894 /* Normal vector unops. */
21895 tree v4sf_ftype_v4sf
21896 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
21897 tree v16qi_ftype_v16qi
21898 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
21899 tree v8hi_ftype_v8hi
21900 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
21901 tree v4si_ftype_v4si
21902 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
21903 tree v8qi_ftype_v8qi
21904 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
21905 tree v4hi_ftype_v4hi
21906 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
21908 /* Normal vector binops. */
21909 tree v4sf_ftype_v4sf_v4sf
21910 = build_function_type_list (V4SF_type_node,
21911 V4SF_type_node, V4SF_type_node, NULL_TREE);
21912 tree v8qi_ftype_v8qi_v8qi
21913 = build_function_type_list (V8QI_type_node,
21914 V8QI_type_node, V8QI_type_node, NULL_TREE);
21915 tree v4hi_ftype_v4hi_v4hi
21916 = build_function_type_list (V4HI_type_node,
21917 V4HI_type_node, V4HI_type_node, NULL_TREE);
21918 tree v2si_ftype_v2si_v2si
21919 = build_function_type_list (V2SI_type_node,
21920 V2SI_type_node, V2SI_type_node, NULL_TREE);
21921 tree v1di_ftype_v1di_v1di
21922 = build_function_type_list (V1DI_type_node,
21923 V1DI_type_node, V1DI_type_node, NULL_TREE);
21924 tree v1di_ftype_v1di_v1di_int
21925 = build_function_type_list (V1DI_type_node,
21926 V1DI_type_node, V1DI_type_node,
21927 integer_type_node, NULL_TREE);
21928 tree v2si_ftype_v2sf
21929 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
21930 tree v2sf_ftype_v2si
21931 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
21932 tree v2si_ftype_v2si
21933 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
21934 tree v2sf_ftype_v2sf
21935 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
21936 tree v2sf_ftype_v2sf_v2sf
21937 = build_function_type_list (V2SF_type_node,
21938 V2SF_type_node, V2SF_type_node, NULL_TREE);
21939 tree v2si_ftype_v2sf_v2sf
21940 = build_function_type_list (V2SI_type_node,
21941 V2SF_type_node, V2SF_type_node, NULL_TREE);
21942 tree pint_type_node = build_pointer_type (integer_type_node);
21943 tree pdouble_type_node = build_pointer_type (double_type_node);
21944 tree pcdouble_type_node = build_pointer_type (
21945 build_type_variant (double_type_node, 1, 0));
21946 tree int_ftype_v2df_v2df
21947 = build_function_type_list (integer_type_node,
21948 V2DF_type_node, V2DF_type_node, NULL_TREE);
21950 tree void_ftype_pcvoid
21951 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
21952 tree v4sf_ftype_v4si
21953 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
21954 tree v4si_ftype_v4sf
21955 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
21956 tree v2df_ftype_v4si
21957 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
21958 tree v4si_ftype_v2df
21959 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
21960 tree v4si_ftype_v2df_v2df
21961 = build_function_type_list (V4SI_type_node,
21962 V2DF_type_node, V2DF_type_node, NULL_TREE);
21963 tree v2si_ftype_v2df
21964 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
21965 tree v4sf_ftype_v2df
21966 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
21967 tree v2df_ftype_v2si
21968 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
21969 tree v2df_ftype_v4sf
21970 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
21971 tree int_ftype_v2df
21972 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
21973 tree int64_ftype_v2df
21974 = build_function_type_list (long_long_integer_type_node,
21975 V2DF_type_node, NULL_TREE);
21976 tree v2df_ftype_v2df_int
21977 = build_function_type_list (V2DF_type_node,
21978 V2DF_type_node, integer_type_node, NULL_TREE);
21979 tree v2df_ftype_v2df_int64
21980 = build_function_type_list (V2DF_type_node,
21981 V2DF_type_node, long_long_integer_type_node,
21983 tree v4sf_ftype_v4sf_v2df
21984 = build_function_type_list (V4SF_type_node,
21985 V4SF_type_node, V2DF_type_node, NULL_TREE);
21986 tree v2df_ftype_v2df_v4sf
21987 = build_function_type_list (V2DF_type_node,
21988 V2DF_type_node, V4SF_type_node, NULL_TREE);
21989 tree v2df_ftype_v2df_v2df_int
21990 = build_function_type_list (V2DF_type_node,
21991 V2DF_type_node, V2DF_type_node,
21994 tree v2df_ftype_v2df_pcdouble
21995 = build_function_type_list (V2DF_type_node,
21996 V2DF_type_node, pcdouble_type_node, NULL_TREE);
21997 tree void_ftype_pdouble_v2df
21998 = build_function_type_list (void_type_node,
21999 pdouble_type_node, V2DF_type_node, NULL_TREE);
22000 tree void_ftype_pint_int
22001 = build_function_type_list (void_type_node,
22002 pint_type_node, integer_type_node, NULL_TREE);
22003 tree void_ftype_v16qi_v16qi_pchar
22004 = build_function_type_list (void_type_node,
22005 V16QI_type_node, V16QI_type_node,
22006 pchar_type_node, NULL_TREE);
22007 tree v2df_ftype_pcdouble
22008 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22009 tree v2df_ftype_v2df_v2df
22010 = build_function_type_list (V2DF_type_node,
22011 V2DF_type_node, V2DF_type_node, NULL_TREE);
22012 tree v16qi_ftype_v16qi_v16qi
22013 = build_function_type_list (V16QI_type_node,
22014 V16QI_type_node, V16QI_type_node, NULL_TREE);
22015 tree v8hi_ftype_v8hi_v8hi
22016 = build_function_type_list (V8HI_type_node,
22017 V8HI_type_node, V8HI_type_node, NULL_TREE);
22018 tree v4si_ftype_v4si_v4si
22019 = build_function_type_list (V4SI_type_node,
22020 V4SI_type_node, V4SI_type_node, NULL_TREE);
22021 tree v2di_ftype_v2di_v2di
22022 = build_function_type_list (V2DI_type_node,
22023 V2DI_type_node, V2DI_type_node, NULL_TREE);
22024 tree v2di_ftype_v2df_v2df
22025 = build_function_type_list (V2DI_type_node,
22026 V2DF_type_node, V2DF_type_node, NULL_TREE);
22027 tree v2df_ftype_v2df
22028 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22029 tree v2di_ftype_v2di_int
22030 = build_function_type_list (V2DI_type_node,
22031 V2DI_type_node, integer_type_node, NULL_TREE);
22032 tree v2di_ftype_v2di_v2di_int
22033 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22034 V2DI_type_node, integer_type_node, NULL_TREE);
22035 tree v4si_ftype_v4si_int
22036 = build_function_type_list (V4SI_type_node,
22037 V4SI_type_node, integer_type_node, NULL_TREE);
22038 tree v8hi_ftype_v8hi_int
22039 = build_function_type_list (V8HI_type_node,
22040 V8HI_type_node, integer_type_node, NULL_TREE);
22041 tree v4si_ftype_v8hi_v8hi
22042 = build_function_type_list (V4SI_type_node,
22043 V8HI_type_node, V8HI_type_node, NULL_TREE);
22044 tree v1di_ftype_v8qi_v8qi
22045 = build_function_type_list (V1DI_type_node,
22046 V8QI_type_node, V8QI_type_node, NULL_TREE);
22047 tree v1di_ftype_v2si_v2si
22048 = build_function_type_list (V1DI_type_node,
22049 V2SI_type_node, V2SI_type_node, NULL_TREE);
22050 tree v2di_ftype_v16qi_v16qi
22051 = build_function_type_list (V2DI_type_node,
22052 V16QI_type_node, V16QI_type_node, NULL_TREE);
22053 tree v2di_ftype_v4si_v4si
22054 = build_function_type_list (V2DI_type_node,
22055 V4SI_type_node, V4SI_type_node, NULL_TREE);
22056 tree int_ftype_v16qi
22057 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22058 tree v16qi_ftype_pcchar
22059 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22060 tree void_ftype_pchar_v16qi
22061 = build_function_type_list (void_type_node,
22062 pchar_type_node, V16QI_type_node, NULL_TREE);
22064 tree v2di_ftype_v2di_unsigned_unsigned
22065 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22066 unsigned_type_node, unsigned_type_node,
22068 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22069 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22070 unsigned_type_node, unsigned_type_node,
22072 tree v2di_ftype_v2di_v16qi
22073 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22075 tree v2df_ftype_v2df_v2df_v2df
22076 = build_function_type_list (V2DF_type_node,
22077 V2DF_type_node, V2DF_type_node,
22078 V2DF_type_node, NULL_TREE);
22079 tree v4sf_ftype_v4sf_v4sf_v4sf
22080 = build_function_type_list (V4SF_type_node,
22081 V4SF_type_node, V4SF_type_node,
22082 V4SF_type_node, NULL_TREE);
22083 tree v8hi_ftype_v16qi
22084 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22086 tree v4si_ftype_v16qi
22087 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22089 tree v2di_ftype_v16qi
22090 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22092 tree v4si_ftype_v8hi
22093 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22095 tree v2di_ftype_v8hi
22096 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22098 tree v2di_ftype_v4si
22099 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22101 tree v2di_ftype_pv2di
22102 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22104 tree v16qi_ftype_v16qi_v16qi_int
22105 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22106 V16QI_type_node, integer_type_node,
22108 tree v16qi_ftype_v16qi_v16qi_v16qi
22109 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22110 V16QI_type_node, V16QI_type_node,
22112 tree v8hi_ftype_v8hi_v8hi_int
22113 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22114 V8HI_type_node, integer_type_node,
22116 tree v4si_ftype_v4si_v4si_int
22117 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22118 V4SI_type_node, integer_type_node,
22120 tree int_ftype_v2di_v2di
22121 = build_function_type_list (integer_type_node,
22122 V2DI_type_node, V2DI_type_node,
22124 tree int_ftype_v16qi_int_v16qi_int_int
22125 = build_function_type_list (integer_type_node,
22132 tree v16qi_ftype_v16qi_int_v16qi_int_int
22133 = build_function_type_list (V16QI_type_node,
22140 tree int_ftype_v16qi_v16qi_int
22141 = build_function_type_list (integer_type_node,
22148 tree v2di_ftype_v2di
22149 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22151 tree v16qi_ftype_v8hi_v8hi
22152 = build_function_type_list (V16QI_type_node,
22153 V8HI_type_node, V8HI_type_node,
22155 tree v8hi_ftype_v4si_v4si
22156 = build_function_type_list (V8HI_type_node,
22157 V4SI_type_node, V4SI_type_node,
22159 tree v8hi_ftype_v16qi_v16qi
22160 = build_function_type_list (V8HI_type_node,
22161 V16QI_type_node, V16QI_type_node,
22163 tree v4hi_ftype_v8qi_v8qi
22164 = build_function_type_list (V4HI_type_node,
22165 V8QI_type_node, V8QI_type_node,
22167 tree unsigned_ftype_unsigned_uchar
22168 = build_function_type_list (unsigned_type_node,
22169 unsigned_type_node,
22170 unsigned_char_type_node,
22172 tree unsigned_ftype_unsigned_ushort
22173 = build_function_type_list (unsigned_type_node,
22174 unsigned_type_node,
22175 short_unsigned_type_node,
22177 tree unsigned_ftype_unsigned_unsigned
22178 = build_function_type_list (unsigned_type_node,
22179 unsigned_type_node,
22180 unsigned_type_node,
22182 tree uint64_ftype_uint64_uint64
22183 = build_function_type_list (long_long_unsigned_type_node,
22184 long_long_unsigned_type_node,
22185 long_long_unsigned_type_node,
22187 tree float_ftype_float
22188 = build_function_type_list (float_type_node,
22193 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22195 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22197 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22199 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22201 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22203 tree v8sf_ftype_v8sf
22204 = build_function_type_list (V8SF_type_node,
22207 tree v8si_ftype_v8sf
22208 = build_function_type_list (V8SI_type_node,
22211 tree v8sf_ftype_v8si
22212 = build_function_type_list (V8SF_type_node,
22215 tree v4si_ftype_v4df
22216 = build_function_type_list (V4SI_type_node,
22219 tree v4df_ftype_v4df
22220 = build_function_type_list (V4DF_type_node,
22223 tree v4df_ftype_v4si
22224 = build_function_type_list (V4DF_type_node,
22227 tree v4df_ftype_v4sf
22228 = build_function_type_list (V4DF_type_node,
22231 tree v4sf_ftype_v4df
22232 = build_function_type_list (V4SF_type_node,
22235 tree v8sf_ftype_v8sf_v8sf
22236 = build_function_type_list (V8SF_type_node,
22237 V8SF_type_node, V8SF_type_node,
22239 tree v4df_ftype_v4df_v4df
22240 = build_function_type_list (V4DF_type_node,
22241 V4DF_type_node, V4DF_type_node,
22243 tree v8sf_ftype_v8sf_int
22244 = build_function_type_list (V8SF_type_node,
22245 V8SF_type_node, integer_type_node,
22247 tree v4si_ftype_v8si_int
22248 = build_function_type_list (V4SI_type_node,
22249 V8SI_type_node, integer_type_node,
22251 tree v4df_ftype_v4df_int
22252 = build_function_type_list (V4DF_type_node,
22253 V4DF_type_node, integer_type_node,
22255 tree v4sf_ftype_v8sf_int
22256 = build_function_type_list (V4SF_type_node,
22257 V8SF_type_node, integer_type_node,
22259 tree v2df_ftype_v4df_int
22260 = build_function_type_list (V2DF_type_node,
22261 V4DF_type_node, integer_type_node,
22263 tree v8sf_ftype_v8sf_v8sf_int
22264 = build_function_type_list (V8SF_type_node,
22265 V8SF_type_node, V8SF_type_node,
22268 tree v8sf_ftype_v8sf_v8sf_v8sf
22269 = build_function_type_list (V8SF_type_node,
22270 V8SF_type_node, V8SF_type_node,
22273 tree v4df_ftype_v4df_v4df_v4df
22274 = build_function_type_list (V4DF_type_node,
22275 V4DF_type_node, V4DF_type_node,
22278 tree v8si_ftype_v8si_v8si_int
22279 = build_function_type_list (V8SI_type_node,
22280 V8SI_type_node, V8SI_type_node,
22283 tree v4df_ftype_v4df_v4df_int
22284 = build_function_type_list (V4DF_type_node,
22285 V4DF_type_node, V4DF_type_node,
22288 tree v8sf_ftype_pcfloat
22289 = build_function_type_list (V8SF_type_node,
22292 tree v4df_ftype_pcdouble
22293 = build_function_type_list (V4DF_type_node,
22294 pcdouble_type_node,
22296 tree pcv4sf_type_node
22297 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22298 tree pcv2df_type_node
22299 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22300 tree v8sf_ftype_pcv4sf
22301 = build_function_type_list (V8SF_type_node,
22304 tree v4df_ftype_pcv2df
22305 = build_function_type_list (V4DF_type_node,
22308 tree v32qi_ftype_pcchar
22309 = build_function_type_list (V32QI_type_node,
22312 tree void_ftype_pchar_v32qi
22313 = build_function_type_list (void_type_node,
22314 pchar_type_node, V32QI_type_node,
22316 tree v8si_ftype_v8si_v4si_int
22317 = build_function_type_list (V8SI_type_node,
22318 V8SI_type_node, V4SI_type_node,
22321 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22322 tree void_ftype_pv4di_v4di
22323 = build_function_type_list (void_type_node,
22324 pv4di_type_node, V4DI_type_node,
22326 tree v8sf_ftype_v8sf_v4sf_int
22327 = build_function_type_list (V8SF_type_node,
22328 V8SF_type_node, V4SF_type_node,
22331 tree v4df_ftype_v4df_v2df_int
22332 = build_function_type_list (V4DF_type_node,
22333 V4DF_type_node, V2DF_type_node,
22336 tree void_ftype_pfloat_v8sf
22337 = build_function_type_list (void_type_node,
22338 pfloat_type_node, V8SF_type_node,
22340 tree void_ftype_pdouble_v4df
22341 = build_function_type_list (void_type_node,
22342 pdouble_type_node, V4DF_type_node,
22344 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22345 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22346 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22347 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22348 tree pcv8sf_type_node
22349 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22350 tree pcv4df_type_node
22351 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22352 tree v8sf_ftype_pcv8sf_v8sf
22353 = build_function_type_list (V8SF_type_node,
22354 pcv8sf_type_node, V8SF_type_node,
22356 tree v4df_ftype_pcv4df_v4df
22357 = build_function_type_list (V4DF_type_node,
22358 pcv4df_type_node, V4DF_type_node,
22360 tree v4sf_ftype_pcv4sf_v4sf
22361 = build_function_type_list (V4SF_type_node,
22362 pcv4sf_type_node, V4SF_type_node,
22364 tree v2df_ftype_pcv2df_v2df
22365 = build_function_type_list (V2DF_type_node,
22366 pcv2df_type_node, V2DF_type_node,
22368 tree void_ftype_pv8sf_v8sf_v8sf
22369 = build_function_type_list (void_type_node,
22370 pv8sf_type_node, V8SF_type_node,
22373 tree void_ftype_pv4df_v4df_v4df
22374 = build_function_type_list (void_type_node,
22375 pv4df_type_node, V4DF_type_node,
22378 tree void_ftype_pv4sf_v4sf_v4sf
22379 = build_function_type_list (void_type_node,
22380 pv4sf_type_node, V4SF_type_node,
22383 tree void_ftype_pv2df_v2df_v2df
22384 = build_function_type_list (void_type_node,
22385 pv2df_type_node, V2DF_type_node,
22388 tree v4df_ftype_v2df
22389 = build_function_type_list (V4DF_type_node,
22392 tree v8sf_ftype_v4sf
22393 = build_function_type_list (V8SF_type_node,
22396 tree v8si_ftype_v4si
22397 = build_function_type_list (V8SI_type_node,
22400 tree v2df_ftype_v4df
22401 = build_function_type_list (V2DF_type_node,
22404 tree v4sf_ftype_v8sf
22405 = build_function_type_list (V4SF_type_node,
22408 tree v4si_ftype_v8si
22409 = build_function_type_list (V4SI_type_node,
22412 tree int_ftype_v4df
22413 = build_function_type_list (integer_type_node,
22416 tree int_ftype_v8sf
22417 = build_function_type_list (integer_type_node,
22420 tree int_ftype_v8sf_v8sf
22421 = build_function_type_list (integer_type_node,
22422 V8SF_type_node, V8SF_type_node,
22424 tree int_ftype_v4di_v4di
22425 = build_function_type_list (integer_type_node,
22426 V4DI_type_node, V4DI_type_node,
22428 tree int_ftype_v4df_v4df
22429 = build_function_type_list (integer_type_node,
22430 V4DF_type_node, V4DF_type_node,
22432 tree v8sf_ftype_v8sf_v8si
22433 = build_function_type_list (V8SF_type_node,
22434 V8SF_type_node, V8SI_type_node,
22436 tree v4df_ftype_v4df_v4di
22437 = build_function_type_list (V4DF_type_node,
22438 V4DF_type_node, V4DI_type_node,
22440 tree v4sf_ftype_v4sf_v4si
22441 = build_function_type_list (V4SF_type_node,
22442 V4SF_type_node, V4SI_type_node, NULL_TREE);
22443 tree v2df_ftype_v2df_v2di
22444 = build_function_type_list (V2DF_type_node,
22445 V2DF_type_node, V2DI_type_node, NULL_TREE);
22447 /* Integer intrinsics. */
22448 tree uint64_ftype_void
22449 = build_function_type (long_long_unsigned_type_node,
22452 = build_function_type_list (integer_type_node,
22453 integer_type_node, NULL_TREE);
22454 tree int64_ftype_int64
22455 = build_function_type_list (long_long_integer_type_node,
22456 long_long_integer_type_node,
22458 tree uint64_ftype_int
22459 = build_function_type_list (long_long_unsigned_type_node,
22460 integer_type_node, NULL_TREE);
22461 tree punsigned_type_node = build_pointer_type (unsigned_type_node);
22462 tree uint64_ftype_punsigned
22463 = build_function_type_list (long_long_unsigned_type_node,
22464 punsigned_type_node, NULL_TREE);
22465 tree ushort_ftype_ushort_int
22466 = build_function_type_list (short_unsigned_type_node,
22467 short_unsigned_type_node,
22470 tree uchar_ftype_uchar_int
22471 = build_function_type_list (unsigned_char_type_node,
22472 unsigned_char_type_node,
22478 /* Add all special builtins with variable number of operands. */
22479 for (i = 0, d = bdesc_special_args;
22480 i < ARRAY_SIZE (bdesc_special_args);
22488 switch ((enum ix86_special_builtin_type) d->flag)
22490 case VOID_FTYPE_VOID:
22491 type = void_ftype_void;
22493 case UINT64_FTYPE_VOID:
22494 type = uint64_ftype_void;
22496 case UINT64_FTYPE_PUNSIGNED:
22497 type = uint64_ftype_punsigned;
22499 case V32QI_FTYPE_PCCHAR:
22500 type = v32qi_ftype_pcchar;
22502 case V16QI_FTYPE_PCCHAR:
22503 type = v16qi_ftype_pcchar;
22505 case V8SF_FTYPE_PCV4SF:
22506 type = v8sf_ftype_pcv4sf;
22508 case V8SF_FTYPE_PCFLOAT:
22509 type = v8sf_ftype_pcfloat;
22511 case V4DF_FTYPE_PCV2DF:
22512 type = v4df_ftype_pcv2df;
22514 case V4DF_FTYPE_PCDOUBLE:
22515 type = v4df_ftype_pcdouble;
22517 case V4SF_FTYPE_PCFLOAT:
22518 type = v4sf_ftype_pcfloat;
22520 case V2DI_FTYPE_PV2DI:
22521 type = v2di_ftype_pv2di;
22523 case V2DF_FTYPE_PCDOUBLE:
22524 type = v2df_ftype_pcdouble;
22526 case V8SF_FTYPE_PCV8SF_V8SF:
22527 type = v8sf_ftype_pcv8sf_v8sf;
22529 case V4DF_FTYPE_PCV4DF_V4DF:
22530 type = v4df_ftype_pcv4df_v4df;
22532 case V4SF_FTYPE_V4SF_PCV2SF:
22533 type = v4sf_ftype_v4sf_pcv2sf;
22535 case V4SF_FTYPE_PCV4SF_V4SF:
22536 type = v4sf_ftype_pcv4sf_v4sf;
22538 case V2DF_FTYPE_V2DF_PCDOUBLE:
22539 type = v2df_ftype_v2df_pcdouble;
22541 case V2DF_FTYPE_PCV2DF_V2DF:
22542 type = v2df_ftype_pcv2df_v2df;
22544 case VOID_FTYPE_PV2SF_V4SF:
22545 type = void_ftype_pv2sf_v4sf;
22547 case VOID_FTYPE_PV4DI_V4DI:
22548 type = void_ftype_pv4di_v4di;
22550 case VOID_FTYPE_PV2DI_V2DI:
22551 type = void_ftype_pv2di_v2di;
22553 case VOID_FTYPE_PCHAR_V32QI:
22554 type = void_ftype_pchar_v32qi;
22556 case VOID_FTYPE_PCHAR_V16QI:
22557 type = void_ftype_pchar_v16qi;
22559 case VOID_FTYPE_PFLOAT_V8SF:
22560 type = void_ftype_pfloat_v8sf;
22562 case VOID_FTYPE_PFLOAT_V4SF:
22563 type = void_ftype_pfloat_v4sf;
22565 case VOID_FTYPE_PDOUBLE_V4DF:
22566 type = void_ftype_pdouble_v4df;
22568 case VOID_FTYPE_PDOUBLE_V2DF:
22569 type = void_ftype_pdouble_v2df;
22571 case VOID_FTYPE_PDI_DI:
22572 type = void_ftype_pdi_di;
22574 case VOID_FTYPE_PINT_INT:
22575 type = void_ftype_pint_int;
22577 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22578 type = void_ftype_pv8sf_v8sf_v8sf;
22580 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22581 type = void_ftype_pv4df_v4df_v4df;
22583 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22584 type = void_ftype_pv4sf_v4sf_v4sf;
22586 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22587 type = void_ftype_pv2df_v2df_v2df;
22590 gcc_unreachable ();
22593 def_builtin (d->mask, d->name, type, d->code);
22596 /* Add all builtins with variable number of operands. */
22597 for (i = 0, d = bdesc_args;
22598 i < ARRAY_SIZE (bdesc_args);
22606 switch ((enum ix86_builtin_type) d->flag)
22608 case FLOAT_FTYPE_FLOAT:
22609 type = float_ftype_float;
22611 case INT_FTYPE_V8SF_V8SF_PTEST:
22612 type = int_ftype_v8sf_v8sf;
22614 case INT_FTYPE_V4DI_V4DI_PTEST:
22615 type = int_ftype_v4di_v4di;
22617 case INT_FTYPE_V4DF_V4DF_PTEST:
22618 type = int_ftype_v4df_v4df;
22620 case INT_FTYPE_V4SF_V4SF_PTEST:
22621 type = int_ftype_v4sf_v4sf;
22623 case INT_FTYPE_V2DI_V2DI_PTEST:
22624 type = int_ftype_v2di_v2di;
22626 case INT_FTYPE_V2DF_V2DF_PTEST:
22627 type = int_ftype_v2df_v2df;
22629 case INT_FTYPE_INT:
22630 type = int_ftype_int;
22632 case UINT64_FTYPE_INT:
22633 type = uint64_ftype_int;
22635 case INT64_FTYPE_INT64:
22636 type = int64_ftype_int64;
22638 case INT64_FTYPE_V4SF:
22639 type = int64_ftype_v4sf;
22641 case INT64_FTYPE_V2DF:
22642 type = int64_ftype_v2df;
22644 case INT_FTYPE_V16QI:
22645 type = int_ftype_v16qi;
22647 case INT_FTYPE_V8QI:
22648 type = int_ftype_v8qi;
22650 case INT_FTYPE_V8SF:
22651 type = int_ftype_v8sf;
22653 case INT_FTYPE_V4DF:
22654 type = int_ftype_v4df;
22656 case INT_FTYPE_V4SF:
22657 type = int_ftype_v4sf;
22659 case INT_FTYPE_V2DF:
22660 type = int_ftype_v2df;
22662 case V16QI_FTYPE_V16QI:
22663 type = v16qi_ftype_v16qi;
22665 case V8SI_FTYPE_V8SF:
22666 type = v8si_ftype_v8sf;
22668 case V8SI_FTYPE_V4SI:
22669 type = v8si_ftype_v4si;
22671 case V8HI_FTYPE_V8HI:
22672 type = v8hi_ftype_v8hi;
22674 case V8HI_FTYPE_V16QI:
22675 type = v8hi_ftype_v16qi;
22677 case V8QI_FTYPE_V8QI:
22678 type = v8qi_ftype_v8qi;
22680 case V8SF_FTYPE_V8SF:
22681 type = v8sf_ftype_v8sf;
22683 case V8SF_FTYPE_V8SI:
22684 type = v8sf_ftype_v8si;
22686 case V8SF_FTYPE_V4SF:
22687 type = v8sf_ftype_v4sf;
22689 case V4SI_FTYPE_V4DF:
22690 type = v4si_ftype_v4df;
22692 case V4SI_FTYPE_V4SI:
22693 type = v4si_ftype_v4si;
22695 case V4SI_FTYPE_V16QI:
22696 type = v4si_ftype_v16qi;
22698 case V4SI_FTYPE_V8SI:
22699 type = v4si_ftype_v8si;
22701 case V4SI_FTYPE_V8HI:
22702 type = v4si_ftype_v8hi;
22704 case V4SI_FTYPE_V4SF:
22705 type = v4si_ftype_v4sf;
22707 case V4SI_FTYPE_V2DF:
22708 type = v4si_ftype_v2df;
22710 case V4HI_FTYPE_V4HI:
22711 type = v4hi_ftype_v4hi;
22713 case V4DF_FTYPE_V4DF:
22714 type = v4df_ftype_v4df;
22716 case V4DF_FTYPE_V4SI:
22717 type = v4df_ftype_v4si;
22719 case V4DF_FTYPE_V4SF:
22720 type = v4df_ftype_v4sf;
22722 case V4DF_FTYPE_V2DF:
22723 type = v4df_ftype_v2df;
22725 case V4SF_FTYPE_V4SF:
22726 case V4SF_FTYPE_V4SF_VEC_MERGE:
22727 type = v4sf_ftype_v4sf;
22729 case V4SF_FTYPE_V8SF:
22730 type = v4sf_ftype_v8sf;
22732 case V4SF_FTYPE_V4SI:
22733 type = v4sf_ftype_v4si;
22735 case V4SF_FTYPE_V4DF:
22736 type = v4sf_ftype_v4df;
22738 case V4SF_FTYPE_V2DF:
22739 type = v4sf_ftype_v2df;
22741 case V2DI_FTYPE_V2DI:
22742 type = v2di_ftype_v2di;
22744 case V2DI_FTYPE_V16QI:
22745 type = v2di_ftype_v16qi;
22747 case V2DI_FTYPE_V8HI:
22748 type = v2di_ftype_v8hi;
22750 case V2DI_FTYPE_V4SI:
22751 type = v2di_ftype_v4si;
22753 case V2SI_FTYPE_V2SI:
22754 type = v2si_ftype_v2si;
22756 case V2SI_FTYPE_V4SF:
22757 type = v2si_ftype_v4sf;
22759 case V2SI_FTYPE_V2DF:
22760 type = v2si_ftype_v2df;
22762 case V2SI_FTYPE_V2SF:
22763 type = v2si_ftype_v2sf;
22765 case V2DF_FTYPE_V4DF:
22766 type = v2df_ftype_v4df;
22768 case V2DF_FTYPE_V4SF:
22769 type = v2df_ftype_v4sf;
22771 case V2DF_FTYPE_V2DF:
22772 case V2DF_FTYPE_V2DF_VEC_MERGE:
22773 type = v2df_ftype_v2df;
22775 case V2DF_FTYPE_V2SI:
22776 type = v2df_ftype_v2si;
22778 case V2DF_FTYPE_V4SI:
22779 type = v2df_ftype_v4si;
22781 case V2SF_FTYPE_V2SF:
22782 type = v2sf_ftype_v2sf;
22784 case V2SF_FTYPE_V2SI:
22785 type = v2sf_ftype_v2si;
22787 case V16QI_FTYPE_V16QI_V16QI:
22788 type = v16qi_ftype_v16qi_v16qi;
22790 case V16QI_FTYPE_V8HI_V8HI:
22791 type = v16qi_ftype_v8hi_v8hi;
22793 case V8QI_FTYPE_V8QI_V8QI:
22794 type = v8qi_ftype_v8qi_v8qi;
22796 case V8QI_FTYPE_V4HI_V4HI:
22797 type = v8qi_ftype_v4hi_v4hi;
22799 case V8HI_FTYPE_V8HI_V8HI:
22800 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22801 type = v8hi_ftype_v8hi_v8hi;
22803 case V8HI_FTYPE_V16QI_V16QI:
22804 type = v8hi_ftype_v16qi_v16qi;
22806 case V8HI_FTYPE_V4SI_V4SI:
22807 type = v8hi_ftype_v4si_v4si;
22809 case V8HI_FTYPE_V8HI_SI_COUNT:
22810 type = v8hi_ftype_v8hi_int;
22812 case V8SF_FTYPE_V8SF_V8SF:
22813 type = v8sf_ftype_v8sf_v8sf;
22815 case V8SF_FTYPE_V8SF_V8SI:
22816 type = v8sf_ftype_v8sf_v8si;
22818 case V4SI_FTYPE_V4SI_V4SI:
22819 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22820 type = v4si_ftype_v4si_v4si;
22822 case V4SI_FTYPE_V8HI_V8HI:
22823 type = v4si_ftype_v8hi_v8hi;
22825 case V4SI_FTYPE_V4SF_V4SF:
22826 type = v4si_ftype_v4sf_v4sf;
22828 case V4SI_FTYPE_V2DF_V2DF:
22829 type = v4si_ftype_v2df_v2df;
22831 case V4SI_FTYPE_V4SI_SI_COUNT:
22832 type = v4si_ftype_v4si_int;
22834 case V4HI_FTYPE_V4HI_V4HI:
22835 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22836 type = v4hi_ftype_v4hi_v4hi;
22838 case V4HI_FTYPE_V8QI_V8QI:
22839 type = v4hi_ftype_v8qi_v8qi;
22841 case V4HI_FTYPE_V2SI_V2SI:
22842 type = v4hi_ftype_v2si_v2si;
22844 case V4HI_FTYPE_V4HI_SI_COUNT:
22845 type = v4hi_ftype_v4hi_int;
22847 case V4DF_FTYPE_V4DF_V4DF:
22848 type = v4df_ftype_v4df_v4df;
22850 case V4DF_FTYPE_V4DF_V4DI:
22851 type = v4df_ftype_v4df_v4di;
22853 case V4SF_FTYPE_V4SF_V4SF:
22854 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22855 type = v4sf_ftype_v4sf_v4sf;
22857 case V4SF_FTYPE_V4SF_V4SI:
22858 type = v4sf_ftype_v4sf_v4si;
22860 case V4SF_FTYPE_V4SF_V2SI:
22861 type = v4sf_ftype_v4sf_v2si;
22863 case V4SF_FTYPE_V4SF_V2DF:
22864 type = v4sf_ftype_v4sf_v2df;
22866 case V4SF_FTYPE_V4SF_DI:
22867 type = v4sf_ftype_v4sf_int64;
22869 case V4SF_FTYPE_V4SF_SI:
22870 type = v4sf_ftype_v4sf_int;
22872 case V2DI_FTYPE_V2DI_V2DI:
22873 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22874 type = v2di_ftype_v2di_v2di;
22876 case V2DI_FTYPE_V16QI_V16QI:
22877 type = v2di_ftype_v16qi_v16qi;
22879 case V2DI_FTYPE_V4SI_V4SI:
22880 type = v2di_ftype_v4si_v4si;
22882 case V2DI_FTYPE_V2DI_V16QI:
22883 type = v2di_ftype_v2di_v16qi;
22885 case V2DI_FTYPE_V2DF_V2DF:
22886 type = v2di_ftype_v2df_v2df;
22888 case V2DI_FTYPE_V2DI_SI_COUNT:
22889 type = v2di_ftype_v2di_int;
22891 case V2SI_FTYPE_V2SI_V2SI:
22892 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22893 type = v2si_ftype_v2si_v2si;
22895 case V2SI_FTYPE_V4HI_V4HI:
22896 type = v2si_ftype_v4hi_v4hi;
22898 case V2SI_FTYPE_V2SF_V2SF:
22899 type = v2si_ftype_v2sf_v2sf;
22901 case V2SI_FTYPE_V2SI_SI_COUNT:
22902 type = v2si_ftype_v2si_int;
22904 case V2DF_FTYPE_V2DF_V2DF:
22905 case V2DF_FTYPE_V2DF_V2DF_SWAP:
22906 type = v2df_ftype_v2df_v2df;
22908 case V2DF_FTYPE_V2DF_V4SF:
22909 type = v2df_ftype_v2df_v4sf;
22911 case V2DF_FTYPE_V2DF_V2DI:
22912 type = v2df_ftype_v2df_v2di;
22914 case V2DF_FTYPE_V2DF_DI:
22915 type = v2df_ftype_v2df_int64;
22917 case V2DF_FTYPE_V2DF_SI:
22918 type = v2df_ftype_v2df_int;
22920 case V2SF_FTYPE_V2SF_V2SF:
22921 type = v2sf_ftype_v2sf_v2sf;
22923 case V1DI_FTYPE_V1DI_V1DI:
22924 case V1DI_FTYPE_V1DI_V1DI_COUNT:
22925 type = v1di_ftype_v1di_v1di;
22927 case V1DI_FTYPE_V8QI_V8QI:
22928 type = v1di_ftype_v8qi_v8qi;
22930 case V1DI_FTYPE_V2SI_V2SI:
22931 type = v1di_ftype_v2si_v2si;
22933 case V1DI_FTYPE_V1DI_SI_COUNT:
22934 type = v1di_ftype_v1di_int;
22936 case UINT64_FTYPE_UINT64_UINT64:
22937 type = uint64_ftype_uint64_uint64;
22939 case UINT_FTYPE_UINT_UINT:
22940 type = unsigned_ftype_unsigned_unsigned;
22942 case UINT_FTYPE_UINT_USHORT:
22943 type = unsigned_ftype_unsigned_ushort;
22945 case UINT_FTYPE_UINT_UCHAR:
22946 type = unsigned_ftype_unsigned_uchar;
22948 case UINT16_FTYPE_UINT16_INT:
22949 type = ushort_ftype_ushort_int;
22951 case UINT8_FTYPE_UINT8_INT:
22952 type = uchar_ftype_uchar_int;
22954 case V8HI_FTYPE_V8HI_INT:
22955 type = v8hi_ftype_v8hi_int;
22957 case V8SF_FTYPE_V8SF_INT:
22958 type = v8sf_ftype_v8sf_int;
22960 case V4SI_FTYPE_V4SI_INT:
22961 type = v4si_ftype_v4si_int;
22963 case V4SI_FTYPE_V8SI_INT:
22964 type = v4si_ftype_v8si_int;
22966 case V4HI_FTYPE_V4HI_INT:
22967 type = v4hi_ftype_v4hi_int;
22969 case V4DF_FTYPE_V4DF_INT:
22970 type = v4df_ftype_v4df_int;
22972 case V4SF_FTYPE_V4SF_INT:
22973 type = v4sf_ftype_v4sf_int;
22975 case V4SF_FTYPE_V8SF_INT:
22976 type = v4sf_ftype_v8sf_int;
22978 case V2DI_FTYPE_V2DI_INT:
22979 case V2DI2TI_FTYPE_V2DI_INT:
22980 type = v2di_ftype_v2di_int;
22982 case V2DF_FTYPE_V2DF_INT:
22983 type = v2df_ftype_v2df_int;
22985 case V2DF_FTYPE_V4DF_INT:
22986 type = v2df_ftype_v4df_int;
22988 case V16QI_FTYPE_V16QI_V16QI_V16QI:
22989 type = v16qi_ftype_v16qi_v16qi_v16qi;
22991 case V8SF_FTYPE_V8SF_V8SF_V8SF:
22992 type = v8sf_ftype_v8sf_v8sf_v8sf;
22994 case V4DF_FTYPE_V4DF_V4DF_V4DF:
22995 type = v4df_ftype_v4df_v4df_v4df;
22997 case V4SF_FTYPE_V4SF_V4SF_V4SF:
22998 type = v4sf_ftype_v4sf_v4sf_v4sf;
23000 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23001 type = v2df_ftype_v2df_v2df_v2df;
23003 case V16QI_FTYPE_V16QI_V16QI_INT:
23004 type = v16qi_ftype_v16qi_v16qi_int;
23006 case V8SI_FTYPE_V8SI_V8SI_INT:
23007 type = v8si_ftype_v8si_v8si_int;
23009 case V8SI_FTYPE_V8SI_V4SI_INT:
23010 type = v8si_ftype_v8si_v4si_int;
23012 case V8HI_FTYPE_V8HI_V8HI_INT:
23013 type = v8hi_ftype_v8hi_v8hi_int;
23015 case V8SF_FTYPE_V8SF_V8SF_INT:
23016 type = v8sf_ftype_v8sf_v8sf_int;
23018 case V8SF_FTYPE_V8SF_V4SF_INT:
23019 type = v8sf_ftype_v8sf_v4sf_int;
23021 case V4SI_FTYPE_V4SI_V4SI_INT:
23022 type = v4si_ftype_v4si_v4si_int;
23024 case V4DF_FTYPE_V4DF_V4DF_INT:
23025 type = v4df_ftype_v4df_v4df_int;
23027 case V4DF_FTYPE_V4DF_V2DF_INT:
23028 type = v4df_ftype_v4df_v2df_int;
23030 case V4SF_FTYPE_V4SF_V4SF_INT:
23031 type = v4sf_ftype_v4sf_v4sf_int;
23033 case V2DI_FTYPE_V2DI_V2DI_INT:
23034 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23035 type = v2di_ftype_v2di_v2di_int;
23037 case V2DF_FTYPE_V2DF_V2DF_INT:
23038 type = v2df_ftype_v2df_v2df_int;
23040 case V2DI_FTYPE_V2DI_UINT_UINT:
23041 type = v2di_ftype_v2di_unsigned_unsigned;
23043 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23044 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23046 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23047 type = v1di_ftype_v1di_v1di_int;
23050 gcc_unreachable ();
23053 def_builtin_const (d->mask, d->name, type, d->code);
23056 /* pcmpestr[im] insns. */
23057 for (i = 0, d = bdesc_pcmpestr;
23058 i < ARRAY_SIZE (bdesc_pcmpestr);
23061 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23062 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23064 ftype = int_ftype_v16qi_int_v16qi_int_int;
23065 def_builtin_const (d->mask, d->name, ftype, d->code);
23068 /* pcmpistr[im] insns. */
23069 for (i = 0, d = bdesc_pcmpistr;
23070 i < ARRAY_SIZE (bdesc_pcmpistr);
23073 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23074 ftype = v16qi_ftype_v16qi_v16qi_int;
23076 ftype = int_ftype_v16qi_v16qi_int;
23077 def_builtin_const (d->mask, d->name, ftype, d->code);
23080 /* comi/ucomi insns. */
23081 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23082 if (d->mask == OPTION_MASK_ISA_SSE2)
23083 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23085 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23088 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23089 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23091 /* SSE or 3DNow!A */
23092 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23095 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23097 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23098 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23101 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23102 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23105 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23106 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23107 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23108 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23109 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23110 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23113 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23116 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23117 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23119 /* Access to the vec_init patterns. */
23120 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23121 integer_type_node, NULL_TREE);
23122 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23124 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23125 short_integer_type_node,
23126 short_integer_type_node,
23127 short_integer_type_node, NULL_TREE);
23128 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23130 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23131 char_type_node, char_type_node,
23132 char_type_node, char_type_node,
23133 char_type_node, char_type_node,
23134 char_type_node, NULL_TREE);
23135 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23137 /* Access to the vec_extract patterns. */
23138 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23139 integer_type_node, NULL_TREE);
23140 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23142 ftype = build_function_type_list (long_long_integer_type_node,
23143 V2DI_type_node, integer_type_node,
23145 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23147 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23148 integer_type_node, NULL_TREE);
23149 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23151 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23152 integer_type_node, NULL_TREE);
23153 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23155 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23156 integer_type_node, NULL_TREE);
23157 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23159 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23160 integer_type_node, NULL_TREE);
23161 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23163 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23164 integer_type_node, NULL_TREE);
23165 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23167 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23168 integer_type_node, NULL_TREE);
23169 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23171 /* Access to the vec_set patterns. */
23172 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23174 integer_type_node, NULL_TREE);
23175 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23177 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23179 integer_type_node, NULL_TREE);
23180 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23182 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23184 integer_type_node, NULL_TREE);
23185 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23187 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23189 integer_type_node, NULL_TREE);
23190 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23192 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23194 integer_type_node, NULL_TREE);
23195 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23197 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23199 integer_type_node, NULL_TREE);
23200 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23203 /* Internal method for ix86_init_builtins. */
23206 ix86_init_builtins_va_builtins_abi (void)
23208 tree ms_va_ref, sysv_va_ref;
23209 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23210 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23211 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23212 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23216 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23217 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23218 ms_va_ref = build_reference_type (ms_va_list_type_node);
23220 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23223 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23224 fnvoid_va_start_ms =
23225 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23226 fnvoid_va_end_sysv =
23227 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23228 fnvoid_va_start_sysv =
23229 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23231 fnvoid_va_copy_ms =
23232 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23234 fnvoid_va_copy_sysv =
23235 build_function_type_list (void_type_node, sysv_va_ref,
23236 sysv_va_ref, NULL_TREE);
23238 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23239 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23240 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23241 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23242 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23243 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23244 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23245 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23246 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23247 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23248 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23249 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23253 ix86_init_builtins (void)
23255 tree float128_type_node = make_node (REAL_TYPE);
23258 /* The __float80 type. */
23259 if (TYPE_MODE (long_double_type_node) == XFmode)
23260 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23264 /* The __float80 type. */
23265 tree float80_type_node = make_node (REAL_TYPE);
23267 TYPE_PRECISION (float80_type_node) = 80;
23268 layout_type (float80_type_node);
23269 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23273 /* The __float128 type. */
23274 TYPE_PRECISION (float128_type_node) = 128;
23275 layout_type (float128_type_node);
23276 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23279 /* TFmode support builtins. */
23280 ftype = build_function_type (float128_type_node, void_list_node);
23281 decl = add_builtin_function ("__builtin_infq", ftype,
23282 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23284 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23286 decl = add_builtin_function ("__builtin_huge_valq", ftype,
23287 IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
23289 ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl;
23291 /* We will expand them to normal call if SSE2 isn't available since
23292 they are used by libgcc. */
23293 ftype = build_function_type_list (float128_type_node,
23294 float128_type_node,
23296 decl = add_builtin_function ("__builtin_fabsq", ftype,
23297 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23298 "__fabstf2", NULL_TREE);
23299 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23300 TREE_READONLY (decl) = 1;
23302 ftype = build_function_type_list (float128_type_node,
23303 float128_type_node,
23304 float128_type_node,
23306 decl = add_builtin_function ("__builtin_copysignq", ftype,
23307 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23308 "__copysigntf3", NULL_TREE);
23309 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23310 TREE_READONLY (decl) = 1;
23312 ix86_init_mmx_sse_builtins ();
23314 ix86_init_builtins_va_builtins_abi ();
23317 /* Errors in the source file can cause expand_expr to return const0_rtx
23318 where we expect a vector. To avoid crashing, use one of the vector
23319 clear instructions. */
23321 safe_vector_operand (rtx x, enum machine_mode mode)
23323 if (x == const0_rtx)
23324 x = CONST0_RTX (mode);
23328 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23331 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23334 tree arg0 = CALL_EXPR_ARG (exp, 0);
23335 tree arg1 = CALL_EXPR_ARG (exp, 1);
23336 rtx op0 = expand_normal (arg0);
23337 rtx op1 = expand_normal (arg1);
23338 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23339 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23340 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23342 if (VECTOR_MODE_P (mode0))
23343 op0 = safe_vector_operand (op0, mode0);
23344 if (VECTOR_MODE_P (mode1))
23345 op1 = safe_vector_operand (op1, mode1);
23347 if (optimize || !target
23348 || GET_MODE (target) != tmode
23349 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23350 target = gen_reg_rtx (tmode);
23352 if (GET_MODE (op1) == SImode && mode1 == TImode)
23354 rtx x = gen_reg_rtx (V4SImode);
23355 emit_insn (gen_sse2_loadd (x, op1));
23356 op1 = gen_lowpart (TImode, x);
23359 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23360 op0 = copy_to_mode_reg (mode0, op0);
23361 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23362 op1 = copy_to_mode_reg (mode1, op1);
23364 pat = GEN_FCN (icode) (target, op0, op1);
23373 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23374 insns with vec_merge. */
23377 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23381 tree arg0 = CALL_EXPR_ARG (exp, 0);
23382 rtx op1, op0 = expand_normal (arg0);
23383 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23384 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23386 if (optimize || !target
23387 || GET_MODE (target) != tmode
23388 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23389 target = gen_reg_rtx (tmode);
23391 if (VECTOR_MODE_P (mode0))
23392 op0 = safe_vector_operand (op0, mode0);
23394 if ((optimize && !register_operand (op0, mode0))
23395 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23396 op0 = copy_to_mode_reg (mode0, op0);
23399 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23400 op1 = copy_to_mode_reg (mode0, op1);
23402 pat = GEN_FCN (icode) (target, op0, op1);
23409 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23412 ix86_expand_sse_compare (const struct builtin_description *d,
23413 tree exp, rtx target, bool swap)
23416 tree arg0 = CALL_EXPR_ARG (exp, 0);
23417 tree arg1 = CALL_EXPR_ARG (exp, 1);
23418 rtx op0 = expand_normal (arg0);
23419 rtx op1 = expand_normal (arg1);
23421 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23422 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23423 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23424 enum rtx_code comparison = d->comparison;
23426 if (VECTOR_MODE_P (mode0))
23427 op0 = safe_vector_operand (op0, mode0);
23428 if (VECTOR_MODE_P (mode1))
23429 op1 = safe_vector_operand (op1, mode1);
23431 /* Swap operands if we have a comparison that isn't available in
23435 rtx tmp = gen_reg_rtx (mode1);
23436 emit_move_insn (tmp, op1);
23441 if (optimize || !target
23442 || GET_MODE (target) != tmode
23443 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23444 target = gen_reg_rtx (tmode);
23446 if ((optimize && !register_operand (op0, mode0))
23447 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23448 op0 = copy_to_mode_reg (mode0, op0);
23449 if ((optimize && !register_operand (op1, mode1))
23450 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23451 op1 = copy_to_mode_reg (mode1, op1);
23453 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23454 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23461 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23464 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23468 tree arg0 = CALL_EXPR_ARG (exp, 0);
23469 tree arg1 = CALL_EXPR_ARG (exp, 1);
23470 rtx op0 = expand_normal (arg0);
23471 rtx op1 = expand_normal (arg1);
23472 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23473 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23474 enum rtx_code comparison = d->comparison;
23476 if (VECTOR_MODE_P (mode0))
23477 op0 = safe_vector_operand (op0, mode0);
23478 if (VECTOR_MODE_P (mode1))
23479 op1 = safe_vector_operand (op1, mode1);
23481 /* Swap operands if we have a comparison that isn't available in
23483 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23490 target = gen_reg_rtx (SImode);
23491 emit_move_insn (target, const0_rtx);
23492 target = gen_rtx_SUBREG (QImode, target, 0);
23494 if ((optimize && !register_operand (op0, mode0))
23495 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23496 op0 = copy_to_mode_reg (mode0, op0);
23497 if ((optimize && !register_operand (op1, mode1))
23498 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23499 op1 = copy_to_mode_reg (mode1, op1);
23501 pat = GEN_FCN (d->icode) (op0, op1);
23505 emit_insn (gen_rtx_SET (VOIDmode,
23506 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23507 gen_rtx_fmt_ee (comparison, QImode,
23511 return SUBREG_REG (target);
23514 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23517 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23521 tree arg0 = CALL_EXPR_ARG (exp, 0);
23522 tree arg1 = CALL_EXPR_ARG (exp, 1);
23523 rtx op0 = expand_normal (arg0);
23524 rtx op1 = expand_normal (arg1);
23525 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23526 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23527 enum rtx_code comparison = d->comparison;
23529 if (VECTOR_MODE_P (mode0))
23530 op0 = safe_vector_operand (op0, mode0);
23531 if (VECTOR_MODE_P (mode1))
23532 op1 = safe_vector_operand (op1, mode1);
23534 target = gen_reg_rtx (SImode);
23535 emit_move_insn (target, const0_rtx);
23536 target = gen_rtx_SUBREG (QImode, target, 0);
23538 if ((optimize && !register_operand (op0, mode0))
23539 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23540 op0 = copy_to_mode_reg (mode0, op0);
23541 if ((optimize && !register_operand (op1, mode1))
23542 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23543 op1 = copy_to_mode_reg (mode1, op1);
23545 pat = GEN_FCN (d->icode) (op0, op1);
23549 emit_insn (gen_rtx_SET (VOIDmode,
23550 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23551 gen_rtx_fmt_ee (comparison, QImode,
23555 return SUBREG_REG (target);
23558 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23561 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23562 tree exp, rtx target)
23565 tree arg0 = CALL_EXPR_ARG (exp, 0);
23566 tree arg1 = CALL_EXPR_ARG (exp, 1);
23567 tree arg2 = CALL_EXPR_ARG (exp, 2);
23568 tree arg3 = CALL_EXPR_ARG (exp, 3);
23569 tree arg4 = CALL_EXPR_ARG (exp, 4);
23570 rtx scratch0, scratch1;
23571 rtx op0 = expand_normal (arg0);
23572 rtx op1 = expand_normal (arg1);
23573 rtx op2 = expand_normal (arg2);
23574 rtx op3 = expand_normal (arg3);
23575 rtx op4 = expand_normal (arg4);
23576 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23578 tmode0 = insn_data[d->icode].operand[0].mode;
23579 tmode1 = insn_data[d->icode].operand[1].mode;
23580 modev2 = insn_data[d->icode].operand[2].mode;
23581 modei3 = insn_data[d->icode].operand[3].mode;
23582 modev4 = insn_data[d->icode].operand[4].mode;
23583 modei5 = insn_data[d->icode].operand[5].mode;
23584 modeimm = insn_data[d->icode].operand[6].mode;
23586 if (VECTOR_MODE_P (modev2))
23587 op0 = safe_vector_operand (op0, modev2);
23588 if (VECTOR_MODE_P (modev4))
23589 op2 = safe_vector_operand (op2, modev4);
23591 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23592 op0 = copy_to_mode_reg (modev2, op0);
23593 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23594 op1 = copy_to_mode_reg (modei3, op1);
23595 if ((optimize && !register_operand (op2, modev4))
23596 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23597 op2 = copy_to_mode_reg (modev4, op2);
23598 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23599 op3 = copy_to_mode_reg (modei5, op3);
23601 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23603 error ("the fifth argument must be a 8-bit immediate");
23607 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23609 if (optimize || !target
23610 || GET_MODE (target) != tmode0
23611 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23612 target = gen_reg_rtx (tmode0);
23614 scratch1 = gen_reg_rtx (tmode1);
23616 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23618 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23620 if (optimize || !target
23621 || GET_MODE (target) != tmode1
23622 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23623 target = gen_reg_rtx (tmode1);
23625 scratch0 = gen_reg_rtx (tmode0);
23627 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23631 gcc_assert (d->flag);
23633 scratch0 = gen_reg_rtx (tmode0);
23634 scratch1 = gen_reg_rtx (tmode1);
23636 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23646 target = gen_reg_rtx (SImode);
23647 emit_move_insn (target, const0_rtx);
23648 target = gen_rtx_SUBREG (QImode, target, 0);
23651 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23652 gen_rtx_fmt_ee (EQ, QImode,
23653 gen_rtx_REG ((enum machine_mode) d->flag,
23656 return SUBREG_REG (target);
23663 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23666 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23667 tree exp, rtx target)
23670 tree arg0 = CALL_EXPR_ARG (exp, 0);
23671 tree arg1 = CALL_EXPR_ARG (exp, 1);
23672 tree arg2 = CALL_EXPR_ARG (exp, 2);
23673 rtx scratch0, scratch1;
23674 rtx op0 = expand_normal (arg0);
23675 rtx op1 = expand_normal (arg1);
23676 rtx op2 = expand_normal (arg2);
23677 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
23679 tmode0 = insn_data[d->icode].operand[0].mode;
23680 tmode1 = insn_data[d->icode].operand[1].mode;
23681 modev2 = insn_data[d->icode].operand[2].mode;
23682 modev3 = insn_data[d->icode].operand[3].mode;
23683 modeimm = insn_data[d->icode].operand[4].mode;
23685 if (VECTOR_MODE_P (modev2))
23686 op0 = safe_vector_operand (op0, modev2);
23687 if (VECTOR_MODE_P (modev3))
23688 op1 = safe_vector_operand (op1, modev3);
23690 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23691 op0 = copy_to_mode_reg (modev2, op0);
23692 if ((optimize && !register_operand (op1, modev3))
23693 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
23694 op1 = copy_to_mode_reg (modev3, op1);
23696 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
23698 error ("the third argument must be a 8-bit immediate");
23702 if (d->code == IX86_BUILTIN_PCMPISTRI128)
23704 if (optimize || !target
23705 || GET_MODE (target) != tmode0
23706 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23707 target = gen_reg_rtx (tmode0);
23709 scratch1 = gen_reg_rtx (tmode1);
23711 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
23713 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
23715 if (optimize || !target
23716 || GET_MODE (target) != tmode1
23717 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23718 target = gen_reg_rtx (tmode1);
23720 scratch0 = gen_reg_rtx (tmode0);
23722 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
23726 gcc_assert (d->flag);
23728 scratch0 = gen_reg_rtx (tmode0);
23729 scratch1 = gen_reg_rtx (tmode1);
23731 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
23741 target = gen_reg_rtx (SImode);
23742 emit_move_insn (target, const0_rtx);
23743 target = gen_rtx_SUBREG (QImode, target, 0);
23746 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23747 gen_rtx_fmt_ee (EQ, QImode,
23748 gen_rtx_REG ((enum machine_mode) d->flag,
23751 return SUBREG_REG (target);
23757 /* Subroutine of ix86_expand_builtin to take care of insns with
23758 variable number of operands. */
23761 ix86_expand_args_builtin (const struct builtin_description *d,
23762 tree exp, rtx target)
23764 rtx pat, real_target;
23765 unsigned int i, nargs;
23766 unsigned int nargs_constant = 0;
23767 int num_memory = 0;
23771 enum machine_mode mode;
23773 bool last_arg_count = false;
23774 enum insn_code icode = d->icode;
23775 const struct insn_data *insn_p = &insn_data[icode];
23776 enum machine_mode tmode = insn_p->operand[0].mode;
23777 enum machine_mode rmode = VOIDmode;
23779 enum rtx_code comparison = d->comparison;
23781 switch ((enum ix86_builtin_type) d->flag)
23783 case INT_FTYPE_V8SF_V8SF_PTEST:
23784 case INT_FTYPE_V4DI_V4DI_PTEST:
23785 case INT_FTYPE_V4DF_V4DF_PTEST:
23786 case INT_FTYPE_V4SF_V4SF_PTEST:
23787 case INT_FTYPE_V2DI_V2DI_PTEST:
23788 case INT_FTYPE_V2DF_V2DF_PTEST:
23789 return ix86_expand_sse_ptest (d, exp, target);
23790 case FLOAT128_FTYPE_FLOAT128:
23791 case FLOAT_FTYPE_FLOAT:
23792 case INT_FTYPE_INT:
23793 case UINT64_FTYPE_INT:
23794 case INT64_FTYPE_INT64:
23795 case INT64_FTYPE_V4SF:
23796 case INT64_FTYPE_V2DF:
23797 case INT_FTYPE_V16QI:
23798 case INT_FTYPE_V8QI:
23799 case INT_FTYPE_V8SF:
23800 case INT_FTYPE_V4DF:
23801 case INT_FTYPE_V4SF:
23802 case INT_FTYPE_V2DF:
23803 case V16QI_FTYPE_V16QI:
23804 case V8SI_FTYPE_V8SF:
23805 case V8SI_FTYPE_V4SI:
23806 case V8HI_FTYPE_V8HI:
23807 case V8HI_FTYPE_V16QI:
23808 case V8QI_FTYPE_V8QI:
23809 case V8SF_FTYPE_V8SF:
23810 case V8SF_FTYPE_V8SI:
23811 case V8SF_FTYPE_V4SF:
23812 case V4SI_FTYPE_V4SI:
23813 case V4SI_FTYPE_V16QI:
23814 case V4SI_FTYPE_V4SF:
23815 case V4SI_FTYPE_V8SI:
23816 case V4SI_FTYPE_V8HI:
23817 case V4SI_FTYPE_V4DF:
23818 case V4SI_FTYPE_V2DF:
23819 case V4HI_FTYPE_V4HI:
23820 case V4DF_FTYPE_V4DF:
23821 case V4DF_FTYPE_V4SI:
23822 case V4DF_FTYPE_V4SF:
23823 case V4DF_FTYPE_V2DF:
23824 case V4SF_FTYPE_V4SF:
23825 case V4SF_FTYPE_V4SI:
23826 case V4SF_FTYPE_V8SF:
23827 case V4SF_FTYPE_V4DF:
23828 case V4SF_FTYPE_V2DF:
23829 case V2DI_FTYPE_V2DI:
23830 case V2DI_FTYPE_V16QI:
23831 case V2DI_FTYPE_V8HI:
23832 case V2DI_FTYPE_V4SI:
23833 case V2DF_FTYPE_V2DF:
23834 case V2DF_FTYPE_V4SI:
23835 case V2DF_FTYPE_V4DF:
23836 case V2DF_FTYPE_V4SF:
23837 case V2DF_FTYPE_V2SI:
23838 case V2SI_FTYPE_V2SI:
23839 case V2SI_FTYPE_V4SF:
23840 case V2SI_FTYPE_V2SF:
23841 case V2SI_FTYPE_V2DF:
23842 case V2SF_FTYPE_V2SF:
23843 case V2SF_FTYPE_V2SI:
23846 case V4SF_FTYPE_V4SF_VEC_MERGE:
23847 case V2DF_FTYPE_V2DF_VEC_MERGE:
23848 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
23849 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
23850 case V16QI_FTYPE_V16QI_V16QI:
23851 case V16QI_FTYPE_V8HI_V8HI:
23852 case V8QI_FTYPE_V8QI_V8QI:
23853 case V8QI_FTYPE_V4HI_V4HI:
23854 case V8HI_FTYPE_V8HI_V8HI:
23855 case V8HI_FTYPE_V16QI_V16QI:
23856 case V8HI_FTYPE_V4SI_V4SI:
23857 case V8SF_FTYPE_V8SF_V8SF:
23858 case V8SF_FTYPE_V8SF_V8SI:
23859 case V4SI_FTYPE_V4SI_V4SI:
23860 case V4SI_FTYPE_V8HI_V8HI:
23861 case V4SI_FTYPE_V4SF_V4SF:
23862 case V4SI_FTYPE_V2DF_V2DF:
23863 case V4HI_FTYPE_V4HI_V4HI:
23864 case V4HI_FTYPE_V8QI_V8QI:
23865 case V4HI_FTYPE_V2SI_V2SI:
23866 case V4DF_FTYPE_V4DF_V4DF:
23867 case V4DF_FTYPE_V4DF_V4DI:
23868 case V4SF_FTYPE_V4SF_V4SF:
23869 case V4SF_FTYPE_V4SF_V4SI:
23870 case V4SF_FTYPE_V4SF_V2SI:
23871 case V4SF_FTYPE_V4SF_V2DF:
23872 case V4SF_FTYPE_V4SF_DI:
23873 case V4SF_FTYPE_V4SF_SI:
23874 case V2DI_FTYPE_V2DI_V2DI:
23875 case V2DI_FTYPE_V16QI_V16QI:
23876 case V2DI_FTYPE_V4SI_V4SI:
23877 case V2DI_FTYPE_V2DI_V16QI:
23878 case V2DI_FTYPE_V2DF_V2DF:
23879 case V2SI_FTYPE_V2SI_V2SI:
23880 case V2SI_FTYPE_V4HI_V4HI:
23881 case V2SI_FTYPE_V2SF_V2SF:
23882 case V2DF_FTYPE_V2DF_V2DF:
23883 case V2DF_FTYPE_V2DF_V4SF:
23884 case V2DF_FTYPE_V2DF_V2DI:
23885 case V2DF_FTYPE_V2DF_DI:
23886 case V2DF_FTYPE_V2DF_SI:
23887 case V2SF_FTYPE_V2SF_V2SF:
23888 case V1DI_FTYPE_V1DI_V1DI:
23889 case V1DI_FTYPE_V8QI_V8QI:
23890 case V1DI_FTYPE_V2SI_V2SI:
23891 if (comparison == UNKNOWN)
23892 return ix86_expand_binop_builtin (icode, exp, target);
23895 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23896 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23897 gcc_assert (comparison != UNKNOWN);
23901 case V8HI_FTYPE_V8HI_V8HI_COUNT:
23902 case V8HI_FTYPE_V8HI_SI_COUNT:
23903 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23904 case V4SI_FTYPE_V4SI_SI_COUNT:
23905 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23906 case V4HI_FTYPE_V4HI_SI_COUNT:
23907 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23908 case V2DI_FTYPE_V2DI_SI_COUNT:
23909 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23910 case V2SI_FTYPE_V2SI_SI_COUNT:
23911 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23912 case V1DI_FTYPE_V1DI_SI_COUNT:
23914 last_arg_count = true;
23916 case UINT64_FTYPE_UINT64_UINT64:
23917 case UINT_FTYPE_UINT_UINT:
23918 case UINT_FTYPE_UINT_USHORT:
23919 case UINT_FTYPE_UINT_UCHAR:
23920 case UINT16_FTYPE_UINT16_INT:
23921 case UINT8_FTYPE_UINT8_INT:
23924 case V2DI2TI_FTYPE_V2DI_INT:
23927 nargs_constant = 1;
23929 case V8HI_FTYPE_V8HI_INT:
23930 case V8SF_FTYPE_V8SF_INT:
23931 case V4SI_FTYPE_V4SI_INT:
23932 case V4SI_FTYPE_V8SI_INT:
23933 case V4HI_FTYPE_V4HI_INT:
23934 case V4DF_FTYPE_V4DF_INT:
23935 case V4SF_FTYPE_V4SF_INT:
23936 case V4SF_FTYPE_V8SF_INT:
23937 case V2DI_FTYPE_V2DI_INT:
23938 case V2DF_FTYPE_V2DF_INT:
23939 case V2DF_FTYPE_V4DF_INT:
23941 nargs_constant = 1;
23943 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23944 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23945 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23946 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23947 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23950 case V16QI_FTYPE_V16QI_V16QI_INT:
23951 case V8HI_FTYPE_V8HI_V8HI_INT:
23952 case V8SI_FTYPE_V8SI_V8SI_INT:
23953 case V8SI_FTYPE_V8SI_V4SI_INT:
23954 case V8SF_FTYPE_V8SF_V8SF_INT:
23955 case V8SF_FTYPE_V8SF_V4SF_INT:
23956 case V4SI_FTYPE_V4SI_V4SI_INT:
23957 case V4DF_FTYPE_V4DF_V4DF_INT:
23958 case V4DF_FTYPE_V4DF_V2DF_INT:
23959 case V4SF_FTYPE_V4SF_V4SF_INT:
23960 case V2DI_FTYPE_V2DI_V2DI_INT:
23961 case V2DF_FTYPE_V2DF_V2DF_INT:
23963 nargs_constant = 1;
23965 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23968 nargs_constant = 1;
23970 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23973 nargs_constant = 1;
23975 case V2DI_FTYPE_V2DI_UINT_UINT:
23977 nargs_constant = 2;
23979 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23981 nargs_constant = 2;
23984 gcc_unreachable ();
23987 gcc_assert (nargs <= ARRAY_SIZE (args));
23989 if (comparison != UNKNOWN)
23991 gcc_assert (nargs == 2);
23992 return ix86_expand_sse_compare (d, exp, target, swap);
23995 if (rmode == VOIDmode || rmode == tmode)
23999 || GET_MODE (target) != tmode
24000 || ! (*insn_p->operand[0].predicate) (target, tmode))
24001 target = gen_reg_rtx (tmode);
24002 real_target = target;
24006 target = gen_reg_rtx (rmode);
24007 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24010 for (i = 0; i < nargs; i++)
24012 tree arg = CALL_EXPR_ARG (exp, i);
24013 rtx op = expand_normal (arg);
24014 enum machine_mode mode = insn_p->operand[i + 1].mode;
24015 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24017 if (last_arg_count && (i + 1) == nargs)
24019 /* SIMD shift insns take either an 8-bit immediate or
24020 register as count. But builtin functions take int as
24021 count. If count doesn't match, we put it in register. */
24024 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24025 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24026 op = copy_to_reg (op);
24029 else if ((nargs - i) <= nargs_constant)
24034 case CODE_FOR_sse4_1_roundpd:
24035 case CODE_FOR_sse4_1_roundps:
24036 case CODE_FOR_sse4_1_roundsd:
24037 case CODE_FOR_sse4_1_roundss:
24038 case CODE_FOR_sse4_1_blendps:
24039 case CODE_FOR_avx_blendpd256:
24040 case CODE_FOR_avx_vpermilv4df:
24041 case CODE_FOR_avx_roundpd256:
24042 case CODE_FOR_avx_roundps256:
24043 error ("the last argument must be a 4-bit immediate");
24046 case CODE_FOR_sse4_1_blendpd:
24047 case CODE_FOR_avx_vpermilv2df:
24048 error ("the last argument must be a 2-bit immediate");
24051 case CODE_FOR_avx_vextractf128v4df:
24052 case CODE_FOR_avx_vextractf128v8sf:
24053 case CODE_FOR_avx_vextractf128v8si:
24054 case CODE_FOR_avx_vinsertf128v4df:
24055 case CODE_FOR_avx_vinsertf128v8sf:
24056 case CODE_FOR_avx_vinsertf128v8si:
24057 error ("the last argument must be a 1-bit immediate");
24060 case CODE_FOR_avx_cmpsdv2df3:
24061 case CODE_FOR_avx_cmpssv4sf3:
24062 case CODE_FOR_avx_cmppdv2df3:
24063 case CODE_FOR_avx_cmppsv4sf3:
24064 case CODE_FOR_avx_cmppdv4df3:
24065 case CODE_FOR_avx_cmppsv8sf3:
24066 error ("the last argument must be a 5-bit immediate");
24070 switch (nargs_constant)
24073 if ((nargs - i) == nargs_constant)
24075 error ("the next to last argument must be an 8-bit immediate");
24079 error ("the last argument must be an 8-bit immediate");
24082 gcc_unreachable ();
24089 if (VECTOR_MODE_P (mode))
24090 op = safe_vector_operand (op, mode);
24092 /* If we aren't optimizing, only allow one memory operand to
24094 if (memory_operand (op, mode))
24097 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24099 if (optimize || !match || num_memory > 1)
24100 op = copy_to_mode_reg (mode, op);
24104 op = copy_to_reg (op);
24105 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24110 args[i].mode = mode;
24116 pat = GEN_FCN (icode) (real_target, args[0].op);
24119 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24122 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24126 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24127 args[2].op, args[3].op);
24130 gcc_unreachable ();
24140 /* Subroutine of ix86_expand_builtin to take care of special insns
24141 with variable number of operands. */
24144 ix86_expand_special_args_builtin (const struct builtin_description *d,
24145 tree exp, rtx target)
24149 unsigned int i, nargs, arg_adjust, memory;
24153 enum machine_mode mode;
24155 enum insn_code icode = d->icode;
24156 bool last_arg_constant = false;
24157 const struct insn_data *insn_p = &insn_data[icode];
24158 enum machine_mode tmode = insn_p->operand[0].mode;
24159 enum { load, store } klass;
24161 switch ((enum ix86_special_builtin_type) d->flag)
24163 case VOID_FTYPE_VOID:
24164 emit_insn (GEN_FCN (icode) (target));
24166 case UINT64_FTYPE_VOID:
24171 case UINT64_FTYPE_PUNSIGNED:
24172 case V2DI_FTYPE_PV2DI:
24173 case V32QI_FTYPE_PCCHAR:
24174 case V16QI_FTYPE_PCCHAR:
24175 case V8SF_FTYPE_PCV4SF:
24176 case V8SF_FTYPE_PCFLOAT:
24177 case V4SF_FTYPE_PCFLOAT:
24178 case V4DF_FTYPE_PCV2DF:
24179 case V4DF_FTYPE_PCDOUBLE:
24180 case V2DF_FTYPE_PCDOUBLE:
24185 case VOID_FTYPE_PV2SF_V4SF:
24186 case VOID_FTYPE_PV4DI_V4DI:
24187 case VOID_FTYPE_PV2DI_V2DI:
24188 case VOID_FTYPE_PCHAR_V32QI:
24189 case VOID_FTYPE_PCHAR_V16QI:
24190 case VOID_FTYPE_PFLOAT_V8SF:
24191 case VOID_FTYPE_PFLOAT_V4SF:
24192 case VOID_FTYPE_PDOUBLE_V4DF:
24193 case VOID_FTYPE_PDOUBLE_V2DF:
24194 case VOID_FTYPE_PDI_DI:
24195 case VOID_FTYPE_PINT_INT:
24198 /* Reserve memory operand for target. */
24199 memory = ARRAY_SIZE (args);
24201 case V4SF_FTYPE_V4SF_PCV2SF:
24202 case V2DF_FTYPE_V2DF_PCDOUBLE:
24207 case V8SF_FTYPE_PCV8SF_V8SF:
24208 case V4DF_FTYPE_PCV4DF_V4DF:
24209 case V4SF_FTYPE_PCV4SF_V4SF:
24210 case V2DF_FTYPE_PCV2DF_V2DF:
24215 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24216 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24217 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24218 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24221 /* Reserve memory operand for target. */
24222 memory = ARRAY_SIZE (args);
24225 gcc_unreachable ();
24228 gcc_assert (nargs <= ARRAY_SIZE (args));
24230 if (klass == store)
24232 arg = CALL_EXPR_ARG (exp, 0);
24233 op = expand_normal (arg);
24234 gcc_assert (target == 0);
24235 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24243 || GET_MODE (target) != tmode
24244 || ! (*insn_p->operand[0].predicate) (target, tmode))
24245 target = gen_reg_rtx (tmode);
24248 for (i = 0; i < nargs; i++)
24250 enum machine_mode mode = insn_p->operand[i + 1].mode;
24253 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24254 op = expand_normal (arg);
24255 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24257 if (last_arg_constant && (i + 1) == nargs)
24263 error ("the last argument must be an 8-bit immediate");
24271 /* This must be the memory operand. */
24272 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24273 gcc_assert (GET_MODE (op) == mode
24274 || GET_MODE (op) == VOIDmode);
24278 /* This must be register. */
24279 if (VECTOR_MODE_P (mode))
24280 op = safe_vector_operand (op, mode);
24282 gcc_assert (GET_MODE (op) == mode
24283 || GET_MODE (op) == VOIDmode);
24284 op = copy_to_mode_reg (mode, op);
24289 args[i].mode = mode;
24295 pat = GEN_FCN (icode) (target);
24298 pat = GEN_FCN (icode) (target, args[0].op);
24301 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24304 gcc_unreachable ();
24310 return klass == store ? 0 : target;
24313 /* Return the integer constant in ARG. Constrain it to be in the range
24314 of the subparts of VEC_TYPE; issue an error if not. */
24317 get_element_number (tree vec_type, tree arg)
24319 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24321 if (!host_integerp (arg, 1)
24322 || (elt = tree_low_cst (arg, 1), elt > max))
24324 error ("selector must be an integer constant in the range 0..%wi", max);
24331 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24332 ix86_expand_vector_init. We DO have language-level syntax for this, in
24333 the form of (type){ init-list }. Except that since we can't place emms
24334 instructions from inside the compiler, we can't allow the use of MMX
24335 registers unless the user explicitly asks for it. So we do *not* define
24336 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24337 we have builtins invoked by mmintrin.h that gives us license to emit
24338 these sorts of instructions. */
24341 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24343 enum machine_mode tmode = TYPE_MODE (type);
24344 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24345 int i, n_elt = GET_MODE_NUNITS (tmode);
24346 rtvec v = rtvec_alloc (n_elt);
24348 gcc_assert (VECTOR_MODE_P (tmode));
24349 gcc_assert (call_expr_nargs (exp) == n_elt);
24351 for (i = 0; i < n_elt; ++i)
24353 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24354 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24357 if (!target || !register_operand (target, tmode))
24358 target = gen_reg_rtx (tmode);
24360 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24364 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24365 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24366 had a language-level syntax for referencing vector elements. */
24369 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24371 enum machine_mode tmode, mode0;
24376 arg0 = CALL_EXPR_ARG (exp, 0);
24377 arg1 = CALL_EXPR_ARG (exp, 1);
24379 op0 = expand_normal (arg0);
24380 elt = get_element_number (TREE_TYPE (arg0), arg1);
24382 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24383 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24384 gcc_assert (VECTOR_MODE_P (mode0));
24386 op0 = force_reg (mode0, op0);
24388 if (optimize || !target || !register_operand (target, tmode))
24389 target = gen_reg_rtx (tmode);
24391 ix86_expand_vector_extract (true, target, op0, elt);
24396 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24397 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24398 a language-level syntax for referencing vector elements. */
24401 ix86_expand_vec_set_builtin (tree exp)
24403 enum machine_mode tmode, mode1;
24404 tree arg0, arg1, arg2;
24406 rtx op0, op1, target;
24408 arg0 = CALL_EXPR_ARG (exp, 0);
24409 arg1 = CALL_EXPR_ARG (exp, 1);
24410 arg2 = CALL_EXPR_ARG (exp, 2);
24412 tmode = TYPE_MODE (TREE_TYPE (arg0));
24413 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24414 gcc_assert (VECTOR_MODE_P (tmode));
24416 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24417 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24418 elt = get_element_number (TREE_TYPE (arg0), arg2);
24420 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24421 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24423 op0 = force_reg (tmode, op0);
24424 op1 = force_reg (mode1, op1);
24426 /* OP0 is the source of these builtin functions and shouldn't be
24427 modified. Create a copy, use it and return it as target. */
24428 target = gen_reg_rtx (tmode);
24429 emit_move_insn (target, op0);
24430 ix86_expand_vector_set (true, target, op1, elt);
24435 /* Expand an expression EXP that calls a built-in function,
24436 with result going to TARGET if that's convenient
24437 (and in mode MODE if that's convenient).
24438 SUBTARGET may be used as the target for computing one of EXP's operands.
24439 IGNORE is nonzero if the value is to be ignored. */
24442 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24443 enum machine_mode mode ATTRIBUTE_UNUSED,
24444 int ignore ATTRIBUTE_UNUSED)
24446 const struct builtin_description *d;
24448 enum insn_code icode;
24449 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24450 tree arg0, arg1, arg2;
24451 rtx op0, op1, op2, pat;
24452 enum machine_mode mode0, mode1, mode2;
24453 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24455 /* Determine whether the builtin function is available under the current ISA.
24456 Originally the builtin was not created if it wasn't applicable to the
24457 current ISA based on the command line switches. With function specific
24458 options, we need to check in the context of the function making the call
24459 whether it is supported. */
24460 if (ix86_builtins_isa[fcode].isa
24461 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24463 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24464 NULL, NULL, false);
24467 error ("%qE needs unknown isa option", fndecl);
24470 gcc_assert (opts != NULL);
24471 error ("%qE needs isa option %s", fndecl, opts);
24479 case IX86_BUILTIN_MASKMOVQ:
24480 case IX86_BUILTIN_MASKMOVDQU:
24481 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24482 ? CODE_FOR_mmx_maskmovq
24483 : CODE_FOR_sse2_maskmovdqu);
24484 /* Note the arg order is different from the operand order. */
24485 arg1 = CALL_EXPR_ARG (exp, 0);
24486 arg2 = CALL_EXPR_ARG (exp, 1);
24487 arg0 = CALL_EXPR_ARG (exp, 2);
24488 op0 = expand_normal (arg0);
24489 op1 = expand_normal (arg1);
24490 op2 = expand_normal (arg2);
24491 mode0 = insn_data[icode].operand[0].mode;
24492 mode1 = insn_data[icode].operand[1].mode;
24493 mode2 = insn_data[icode].operand[2].mode;
24495 op0 = force_reg (Pmode, op0);
24496 op0 = gen_rtx_MEM (mode1, op0);
24498 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24499 op0 = copy_to_mode_reg (mode0, op0);
24500 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24501 op1 = copy_to_mode_reg (mode1, op1);
24502 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24503 op2 = copy_to_mode_reg (mode2, op2);
24504 pat = GEN_FCN (icode) (op0, op1, op2);
24510 case IX86_BUILTIN_LDMXCSR:
24511 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24512 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24513 emit_move_insn (target, op0);
24514 emit_insn (gen_sse_ldmxcsr (target));
24517 case IX86_BUILTIN_STMXCSR:
24518 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24519 emit_insn (gen_sse_stmxcsr (target));
24520 return copy_to_mode_reg (SImode, target);
24522 case IX86_BUILTIN_CLFLUSH:
24523 arg0 = CALL_EXPR_ARG (exp, 0);
24524 op0 = expand_normal (arg0);
24525 icode = CODE_FOR_sse2_clflush;
24526 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24527 op0 = copy_to_mode_reg (Pmode, op0);
24529 emit_insn (gen_sse2_clflush (op0));
24532 case IX86_BUILTIN_MONITOR:
24533 arg0 = CALL_EXPR_ARG (exp, 0);
24534 arg1 = CALL_EXPR_ARG (exp, 1);
24535 arg2 = CALL_EXPR_ARG (exp, 2);
24536 op0 = expand_normal (arg0);
24537 op1 = expand_normal (arg1);
24538 op2 = expand_normal (arg2);
24540 op0 = copy_to_mode_reg (Pmode, op0);
24542 op1 = copy_to_mode_reg (SImode, op1);
24544 op2 = copy_to_mode_reg (SImode, op2);
24545 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24548 case IX86_BUILTIN_MWAIT:
24549 arg0 = CALL_EXPR_ARG (exp, 0);
24550 arg1 = CALL_EXPR_ARG (exp, 1);
24551 op0 = expand_normal (arg0);
24552 op1 = expand_normal (arg1);
24554 op0 = copy_to_mode_reg (SImode, op0);
24556 op1 = copy_to_mode_reg (SImode, op1);
24557 emit_insn (gen_sse3_mwait (op0, op1));
24560 case IX86_BUILTIN_VEC_INIT_V2SI:
24561 case IX86_BUILTIN_VEC_INIT_V4HI:
24562 case IX86_BUILTIN_VEC_INIT_V8QI:
24563 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24565 case IX86_BUILTIN_VEC_EXT_V2DF:
24566 case IX86_BUILTIN_VEC_EXT_V2DI:
24567 case IX86_BUILTIN_VEC_EXT_V4SF:
24568 case IX86_BUILTIN_VEC_EXT_V4SI:
24569 case IX86_BUILTIN_VEC_EXT_V8HI:
24570 case IX86_BUILTIN_VEC_EXT_V2SI:
24571 case IX86_BUILTIN_VEC_EXT_V4HI:
24572 case IX86_BUILTIN_VEC_EXT_V16QI:
24573 return ix86_expand_vec_ext_builtin (exp, target);
24575 case IX86_BUILTIN_VEC_SET_V2DI:
24576 case IX86_BUILTIN_VEC_SET_V4SF:
24577 case IX86_BUILTIN_VEC_SET_V4SI:
24578 case IX86_BUILTIN_VEC_SET_V8HI:
24579 case IX86_BUILTIN_VEC_SET_V4HI:
24580 case IX86_BUILTIN_VEC_SET_V16QI:
24581 return ix86_expand_vec_set_builtin (exp);
24583 case IX86_BUILTIN_INFQ:
24584 case IX86_BUILTIN_HUGE_VALQ:
24586 REAL_VALUE_TYPE inf;
24590 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24592 tmp = validize_mem (force_const_mem (mode, tmp));
24595 target = gen_reg_rtx (mode);
24597 emit_move_insn (target, tmp);
24605 for (i = 0, d = bdesc_special_args;
24606 i < ARRAY_SIZE (bdesc_special_args);
24608 if (d->code == fcode)
24609 return ix86_expand_special_args_builtin (d, exp, target);
24611 for (i = 0, d = bdesc_args;
24612 i < ARRAY_SIZE (bdesc_args);
24614 if (d->code == fcode)
24617 case IX86_BUILTIN_FABSQ:
24618 case IX86_BUILTIN_COPYSIGNQ:
24620 /* Emit a normal call if SSE2 isn't available. */
24621 return expand_call (exp, target, ignore);
24623 return ix86_expand_args_builtin (d, exp, target);
24626 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24627 if (d->code == fcode)
24628 return ix86_expand_sse_comi (d, exp, target);
24630 for (i = 0, d = bdesc_pcmpestr;
24631 i < ARRAY_SIZE (bdesc_pcmpestr);
24633 if (d->code == fcode)
24634 return ix86_expand_sse_pcmpestr (d, exp, target);
24636 for (i = 0, d = bdesc_pcmpistr;
24637 i < ARRAY_SIZE (bdesc_pcmpistr);
24639 if (d->code == fcode)
24640 return ix86_expand_sse_pcmpistr (d, exp, target);
24642 gcc_unreachable ();
24645 /* Returns a function decl for a vectorized version of the builtin function
24646 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24647 if it is not available. */
24650 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24653 enum machine_mode in_mode, out_mode;
24656 if (TREE_CODE (type_out) != VECTOR_TYPE
24657 || TREE_CODE (type_in) != VECTOR_TYPE)
24660 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24661 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24662 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24663 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24667 case BUILT_IN_SQRT:
24668 if (out_mode == DFmode && out_n == 2
24669 && in_mode == DFmode && in_n == 2)
24670 return ix86_builtins[IX86_BUILTIN_SQRTPD];
24673 case BUILT_IN_SQRTF:
24674 if (out_mode == SFmode && out_n == 4
24675 && in_mode == SFmode && in_n == 4)
24676 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
24679 case BUILT_IN_LRINT:
24680 if (out_mode == SImode && out_n == 4
24681 && in_mode == DFmode && in_n == 2)
24682 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
24685 case BUILT_IN_LRINTF:
24686 if (out_mode == SImode && out_n == 4
24687 && in_mode == SFmode && in_n == 4)
24688 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
24691 case BUILT_IN_COPYSIGN:
24692 if (out_mode == DFmode && out_n == 2
24693 && in_mode == DFmode && in_n == 2)
24694 return ix86_builtins[IX86_BUILTIN_CPYSGNPD];
24697 case BUILT_IN_COPYSIGNF:
24698 if (out_mode == SFmode && out_n == 4
24699 && in_mode == SFmode && in_n == 4)
24700 return ix86_builtins[IX86_BUILTIN_CPYSGNPS];
24707 /* Dispatch to a handler for a vectorization library. */
24708 if (ix86_veclib_handler)
24709 return (*ix86_veclib_handler) ((enum built_in_function) fn, type_out,
24715 /* Handler for an SVML-style interface to
24716 a library with vectorized intrinsics. */
24719 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
24722 tree fntype, new_fndecl, args;
24725 enum machine_mode el_mode, in_mode;
24728 /* The SVML is suitable for unsafe math only. */
24729 if (!flag_unsafe_math_optimizations)
24732 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24733 n = TYPE_VECTOR_SUBPARTS (type_out);
24734 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24735 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24736 if (el_mode != in_mode
24744 case BUILT_IN_LOG10:
24746 case BUILT_IN_TANH:
24748 case BUILT_IN_ATAN:
24749 case BUILT_IN_ATAN2:
24750 case BUILT_IN_ATANH:
24751 case BUILT_IN_CBRT:
24752 case BUILT_IN_SINH:
24754 case BUILT_IN_ASINH:
24755 case BUILT_IN_ASIN:
24756 case BUILT_IN_COSH:
24758 case BUILT_IN_ACOSH:
24759 case BUILT_IN_ACOS:
24760 if (el_mode != DFmode || n != 2)
24764 case BUILT_IN_EXPF:
24765 case BUILT_IN_LOGF:
24766 case BUILT_IN_LOG10F:
24767 case BUILT_IN_POWF:
24768 case BUILT_IN_TANHF:
24769 case BUILT_IN_TANF:
24770 case BUILT_IN_ATANF:
24771 case BUILT_IN_ATAN2F:
24772 case BUILT_IN_ATANHF:
24773 case BUILT_IN_CBRTF:
24774 case BUILT_IN_SINHF:
24775 case BUILT_IN_SINF:
24776 case BUILT_IN_ASINHF:
24777 case BUILT_IN_ASINF:
24778 case BUILT_IN_COSHF:
24779 case BUILT_IN_COSF:
24780 case BUILT_IN_ACOSHF:
24781 case BUILT_IN_ACOSF:
24782 if (el_mode != SFmode || n != 4)
24790 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
24792 if (fn == BUILT_IN_LOGF)
24793 strcpy (name, "vmlsLn4");
24794 else if (fn == BUILT_IN_LOG)
24795 strcpy (name, "vmldLn2");
24798 sprintf (name, "vmls%s", bname+10);
24799 name[strlen (name)-1] = '4';
24802 sprintf (name, "vmld%s2", bname+10);
24804 /* Convert to uppercase. */
24808 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
24809 args = TREE_CHAIN (args))
24813 fntype = build_function_type_list (type_out, type_in, NULL);
24815 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
24817 /* Build a function declaration for the vectorized function. */
24818 new_fndecl = build_decl (BUILTINS_LOCATION,
24819 FUNCTION_DECL, get_identifier (name), fntype);
24820 TREE_PUBLIC (new_fndecl) = 1;
24821 DECL_EXTERNAL (new_fndecl) = 1;
24822 DECL_IS_NOVOPS (new_fndecl) = 1;
24823 TREE_READONLY (new_fndecl) = 1;
24828 /* Handler for an ACML-style interface to
24829 a library with vectorized intrinsics. */
24832 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
24834 char name[20] = "__vr.._";
24835 tree fntype, new_fndecl, args;
24838 enum machine_mode el_mode, in_mode;
24841 /* The ACML is 64bits only and suitable for unsafe math only as
24842 it does not correctly support parts of IEEE with the required
24843 precision such as denormals. */
24845 || !flag_unsafe_math_optimizations)
24848 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24849 n = TYPE_VECTOR_SUBPARTS (type_out);
24850 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24851 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24852 if (el_mode != in_mode
24862 case BUILT_IN_LOG2:
24863 case BUILT_IN_LOG10:
24866 if (el_mode != DFmode
24871 case BUILT_IN_SINF:
24872 case BUILT_IN_COSF:
24873 case BUILT_IN_EXPF:
24874 case BUILT_IN_POWF:
24875 case BUILT_IN_LOGF:
24876 case BUILT_IN_LOG2F:
24877 case BUILT_IN_LOG10F:
24880 if (el_mode != SFmode
24889 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
24890 sprintf (name + 7, "%s", bname+10);
24893 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
24894 args = TREE_CHAIN (args))
24898 fntype = build_function_type_list (type_out, type_in, NULL);
24900 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
24902 /* Build a function declaration for the vectorized function. */
24903 new_fndecl = build_decl (BUILTINS_LOCATION,
24904 FUNCTION_DECL, get_identifier (name), fntype);
24905 TREE_PUBLIC (new_fndecl) = 1;
24906 DECL_EXTERNAL (new_fndecl) = 1;
24907 DECL_IS_NOVOPS (new_fndecl) = 1;
24908 TREE_READONLY (new_fndecl) = 1;
24914 /* Returns a decl of a function that implements conversion of an integer vector
24915 into a floating-point vector, or vice-versa. TYPE is the type of the integer
24916 side of the conversion.
24917 Return NULL_TREE if it is not available. */
24920 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
24922 if (! (TARGET_SSE2 && TREE_CODE (type) == VECTOR_TYPE))
24928 switch (TYPE_MODE (type))
24931 return TYPE_UNSIGNED (type)
24932 ? ix86_builtins[IX86_BUILTIN_CVTUDQ2PS]
24933 : ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
24938 case FIX_TRUNC_EXPR:
24939 switch (TYPE_MODE (type))
24942 return TYPE_UNSIGNED (type)
24944 : ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
24954 /* Returns a code for a target-specific builtin that implements
24955 reciprocal of the function, or NULL_TREE if not available. */
24958 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
24959 bool sqrt ATTRIBUTE_UNUSED)
24961 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
24962 && flag_finite_math_only && !flag_trapping_math
24963 && flag_unsafe_math_optimizations))
24967 /* Machine dependent builtins. */
24970 /* Vectorized version of sqrt to rsqrt conversion. */
24971 case IX86_BUILTIN_SQRTPS_NR:
24972 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
24978 /* Normal builtins. */
24981 /* Sqrt to rsqrt conversion. */
24982 case BUILT_IN_SQRTF:
24983 return ix86_builtins[IX86_BUILTIN_RSQRTF];
24990 /* Store OPERAND to the memory after reload is completed. This means
24991 that we can't easily use assign_stack_local. */
24993 ix86_force_to_memory (enum machine_mode mode, rtx operand)
24997 gcc_assert (reload_completed);
24998 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25000 result = gen_rtx_MEM (mode,
25001 gen_rtx_PLUS (Pmode,
25003 GEN_INT (-RED_ZONE_SIZE)));
25004 emit_move_insn (result, operand);
25006 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25012 operand = gen_lowpart (DImode, operand);
25016 gen_rtx_SET (VOIDmode,
25017 gen_rtx_MEM (DImode,
25018 gen_rtx_PRE_DEC (DImode,
25019 stack_pointer_rtx)),
25023 gcc_unreachable ();
25025 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25034 split_di (&operand, 1, operands, operands + 1);
25036 gen_rtx_SET (VOIDmode,
25037 gen_rtx_MEM (SImode,
25038 gen_rtx_PRE_DEC (Pmode,
25039 stack_pointer_rtx)),
25042 gen_rtx_SET (VOIDmode,
25043 gen_rtx_MEM (SImode,
25044 gen_rtx_PRE_DEC (Pmode,
25045 stack_pointer_rtx)),
25050 /* Store HImodes as SImodes. */
25051 operand = gen_lowpart (SImode, operand);
25055 gen_rtx_SET (VOIDmode,
25056 gen_rtx_MEM (GET_MODE (operand),
25057 gen_rtx_PRE_DEC (SImode,
25058 stack_pointer_rtx)),
25062 gcc_unreachable ();
25064 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25069 /* Free operand from the memory. */
25071 ix86_free_from_memory (enum machine_mode mode)
25073 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25077 if (mode == DImode || TARGET_64BIT)
25081 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25082 to pop or add instruction if registers are available. */
25083 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25084 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25089 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
25090 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
25092 static const enum reg_class *
25093 i386_ira_cover_classes (void)
25095 static const enum reg_class sse_fpmath_classes[] = {
25096 GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES
25098 static const enum reg_class no_sse_fpmath_classes[] = {
25099 GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES
25102 return TARGET_SSE_MATH ? sse_fpmath_classes : no_sse_fpmath_classes;
25105 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25106 QImode must go into class Q_REGS.
25107 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25108 movdf to do mem-to-mem moves through integer regs. */
25110 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25112 enum machine_mode mode = GET_MODE (x);
25114 /* We're only allowed to return a subclass of CLASS. Many of the
25115 following checks fail for NO_REGS, so eliminate that early. */
25116 if (regclass == NO_REGS)
25119 /* All classes can load zeros. */
25120 if (x == CONST0_RTX (mode))
25123 /* Force constants into memory if we are loading a (nonzero) constant into
25124 an MMX or SSE register. This is because there are no MMX/SSE instructions
25125 to load from a constant. */
25127 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25130 /* Prefer SSE regs only, if we can use them for math. */
25131 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25132 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25134 /* Floating-point constants need more complex checks. */
25135 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25137 /* General regs can load everything. */
25138 if (reg_class_subset_p (regclass, GENERAL_REGS))
25141 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25142 zero above. We only want to wind up preferring 80387 registers if
25143 we plan on doing computation with them. */
25145 && standard_80387_constant_p (x))
25147 /* Limit class to non-sse. */
25148 if (regclass == FLOAT_SSE_REGS)
25150 if (regclass == FP_TOP_SSE_REGS)
25152 if (regclass == FP_SECOND_SSE_REGS)
25153 return FP_SECOND_REG;
25154 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25161 /* Generally when we see PLUS here, it's the function invariant
25162 (plus soft-fp const_int). Which can only be computed into general
25164 if (GET_CODE (x) == PLUS)
25165 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25167 /* QImode constants are easy to load, but non-constant QImode data
25168 must go into Q_REGS. */
25169 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25171 if (reg_class_subset_p (regclass, Q_REGS))
25173 if (reg_class_subset_p (Q_REGS, regclass))
25181 /* Discourage putting floating-point values in SSE registers unless
25182 SSE math is being used, and likewise for the 387 registers. */
25184 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25186 enum machine_mode mode = GET_MODE (x);
25188 /* Restrict the output reload class to the register bank that we are doing
25189 math on. If we would like not to return a subset of CLASS, reject this
25190 alternative: if reload cannot do this, it will still use its choice. */
25191 mode = GET_MODE (x);
25192 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25193 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25195 if (X87_FLOAT_MODE_P (mode))
25197 if (regclass == FP_TOP_SSE_REGS)
25199 else if (regclass == FP_SECOND_SSE_REGS)
25200 return FP_SECOND_REG;
25202 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25208 static enum reg_class
25209 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25210 enum machine_mode mode,
25211 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25213 /* QImode spills from non-QI registers require
25214 intermediate register on 32bit targets. */
25215 if (!in_p && mode == QImode && !TARGET_64BIT
25216 && (rclass == GENERAL_REGS
25217 || rclass == LEGACY_REGS
25218 || rclass == INDEX_REGS))
25227 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25228 regno = true_regnum (x);
25230 /* Return Q_REGS if the operand is in memory. */
25238 /* If we are copying between general and FP registers, we need a memory
25239 location. The same is true for SSE and MMX registers.
25241 To optimize register_move_cost performance, allow inline variant.
25243 The macro can't work reliably when one of the CLASSES is class containing
25244 registers from multiple units (SSE, MMX, integer). We avoid this by never
25245 combining those units in single alternative in the machine description.
25246 Ensure that this constraint holds to avoid unexpected surprises.
25248 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25249 enforce these sanity checks. */
25252 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25253 enum machine_mode mode, int strict)
25255 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25256 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25257 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25258 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25259 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25260 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25262 gcc_assert (!strict);
25266 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25269 /* ??? This is a lie. We do have moves between mmx/general, and for
25270 mmx/sse2. But by saying we need secondary memory we discourage the
25271 register allocator from using the mmx registers unless needed. */
25272 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25275 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25277 /* SSE1 doesn't have any direct moves from other classes. */
25281 /* If the target says that inter-unit moves are more expensive
25282 than moving through memory, then don't generate them. */
25283 if (!TARGET_INTER_UNIT_MOVES)
25286 /* Between SSE and general, we have moves no larger than word size. */
25287 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25295 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25296 enum machine_mode mode, int strict)
25298 return inline_secondary_memory_needed (class1, class2, mode, strict);
25301 /* Return true if the registers in CLASS cannot represent the change from
25302 modes FROM to TO. */
25305 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25306 enum reg_class regclass)
25311 /* x87 registers can't do subreg at all, as all values are reformatted
25312 to extended precision. */
25313 if (MAYBE_FLOAT_CLASS_P (regclass))
25316 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25318 /* Vector registers do not support QI or HImode loads. If we don't
25319 disallow a change to these modes, reload will assume it's ok to
25320 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25321 the vec_dupv4hi pattern. */
25322 if (GET_MODE_SIZE (from) < 4)
25325 /* Vector registers do not support subreg with nonzero offsets, which
25326 are otherwise valid for integer registers. Since we can't see
25327 whether we have a nonzero offset from here, prohibit all
25328 nonparadoxical subregs changing size. */
25329 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25336 /* Return the cost of moving data of mode M between a
25337 register and memory. A value of 2 is the default; this cost is
25338 relative to those in `REGISTER_MOVE_COST'.
25340 This function is used extensively by register_move_cost that is used to
25341 build tables at startup. Make it inline in this case.
25342 When IN is 2, return maximum of in and out move cost.
25344 If moving between registers and memory is more expensive than
25345 between two registers, you should define this macro to express the
25348 Model also increased moving costs of QImode registers in non
25352 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25356 if (FLOAT_CLASS_P (regclass))
25374 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25375 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25377 if (SSE_CLASS_P (regclass))
25380 switch (GET_MODE_SIZE (mode))
25395 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25396 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25398 if (MMX_CLASS_P (regclass))
25401 switch (GET_MODE_SIZE (mode))
25413 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25414 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25416 switch (GET_MODE_SIZE (mode))
25419 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25422 return ix86_cost->int_store[0];
25423 if (TARGET_PARTIAL_REG_DEPENDENCY
25424 && optimize_function_for_speed_p (cfun))
25425 cost = ix86_cost->movzbl_load;
25427 cost = ix86_cost->int_load[0];
25429 return MAX (cost, ix86_cost->int_store[0]);
25435 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25437 return ix86_cost->movzbl_load;
25439 return ix86_cost->int_store[0] + 4;
25444 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25445 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25447 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25448 if (mode == TFmode)
25451 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25453 cost = ix86_cost->int_load[2];
25455 cost = ix86_cost->int_store[2];
25456 return (cost * (((int) GET_MODE_SIZE (mode)
25457 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25462 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25464 return inline_memory_move_cost (mode, regclass, in);
25468 /* Return the cost of moving data from a register in class CLASS1 to
25469 one in class CLASS2.
25471 It is not required that the cost always equal 2 when FROM is the same as TO;
25472 on some machines it is expensive to move between registers if they are not
25473 general registers. */
25476 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25477 enum reg_class class2)
25479 /* In case we require secondary memory, compute cost of the store followed
25480 by load. In order to avoid bad register allocation choices, we need
25481 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25483 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25487 cost += inline_memory_move_cost (mode, class1, 2);
25488 cost += inline_memory_move_cost (mode, class2, 2);
25490 /* In case of copying from general_purpose_register we may emit multiple
25491 stores followed by single load causing memory size mismatch stall.
25492 Count this as arbitrarily high cost of 20. */
25493 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25496 /* In the case of FP/MMX moves, the registers actually overlap, and we
25497 have to switch modes in order to treat them differently. */
25498 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25499 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25505 /* Moves between SSE/MMX and integer unit are expensive. */
25506 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25507 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25509 /* ??? By keeping returned value relatively high, we limit the number
25510 of moves between integer and MMX/SSE registers for all targets.
25511 Additionally, high value prevents problem with x86_modes_tieable_p(),
25512 where integer modes in MMX/SSE registers are not tieable
25513 because of missing QImode and HImode moves to, from or between
25514 MMX/SSE registers. */
25515 return MAX (8, ix86_cost->mmxsse_to_integer);
25517 if (MAYBE_FLOAT_CLASS_P (class1))
25518 return ix86_cost->fp_move;
25519 if (MAYBE_SSE_CLASS_P (class1))
25520 return ix86_cost->sse_move;
25521 if (MAYBE_MMX_CLASS_P (class1))
25522 return ix86_cost->mmx_move;
25526 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25529 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25531 /* Flags and only flags can only hold CCmode values. */
25532 if (CC_REGNO_P (regno))
25533 return GET_MODE_CLASS (mode) == MODE_CC;
25534 if (GET_MODE_CLASS (mode) == MODE_CC
25535 || GET_MODE_CLASS (mode) == MODE_RANDOM
25536 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25538 if (FP_REGNO_P (regno))
25539 return VALID_FP_MODE_P (mode);
25540 if (SSE_REGNO_P (regno))
25542 /* We implement the move patterns for all vector modes into and
25543 out of SSE registers, even when no operation instructions
25544 are available. OImode move is available only when AVX is
25546 return ((TARGET_AVX && mode == OImode)
25547 || VALID_AVX256_REG_MODE (mode)
25548 || VALID_SSE_REG_MODE (mode)
25549 || VALID_SSE2_REG_MODE (mode)
25550 || VALID_MMX_REG_MODE (mode)
25551 || VALID_MMX_REG_MODE_3DNOW (mode));
25553 if (MMX_REGNO_P (regno))
25555 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25556 so if the register is available at all, then we can move data of
25557 the given mode into or out of it. */
25558 return (VALID_MMX_REG_MODE (mode)
25559 || VALID_MMX_REG_MODE_3DNOW (mode));
25562 if (mode == QImode)
25564 /* Take care for QImode values - they can be in non-QI regs,
25565 but then they do cause partial register stalls. */
25566 if (regno <= BX_REG || TARGET_64BIT)
25568 if (!TARGET_PARTIAL_REG_STALL)
25570 return reload_in_progress || reload_completed;
25572 /* We handle both integer and floats in the general purpose registers. */
25573 else if (VALID_INT_MODE_P (mode))
25575 else if (VALID_FP_MODE_P (mode))
25577 else if (VALID_DFP_MODE_P (mode))
25579 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25580 on to use that value in smaller contexts, this can easily force a
25581 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25582 supporting DImode, allow it. */
25583 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25589 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25590 tieable integer mode. */
25593 ix86_tieable_integer_mode_p (enum machine_mode mode)
25602 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25605 return TARGET_64BIT;
25612 /* Return true if MODE1 is accessible in a register that can hold MODE2
25613 without copying. That is, all register classes that can hold MODE2
25614 can also hold MODE1. */
25617 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25619 if (mode1 == mode2)
25622 if (ix86_tieable_integer_mode_p (mode1)
25623 && ix86_tieable_integer_mode_p (mode2))
25626 /* MODE2 being XFmode implies fp stack or general regs, which means we
25627 can tie any smaller floating point modes to it. Note that we do not
25628 tie this with TFmode. */
25629 if (mode2 == XFmode)
25630 return mode1 == SFmode || mode1 == DFmode;
25632 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25633 that we can tie it with SFmode. */
25634 if (mode2 == DFmode)
25635 return mode1 == SFmode;
25637 /* If MODE2 is only appropriate for an SSE register, then tie with
25638 any other mode acceptable to SSE registers. */
25639 if (GET_MODE_SIZE (mode2) == 16
25640 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25641 return (GET_MODE_SIZE (mode1) == 16
25642 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25644 /* If MODE2 is appropriate for an MMX register, then tie
25645 with any other mode acceptable to MMX registers. */
25646 if (GET_MODE_SIZE (mode2) == 8
25647 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25648 return (GET_MODE_SIZE (mode1) == 8
25649 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25654 /* Compute a (partial) cost for rtx X. Return true if the complete
25655 cost has been computed, and false if subexpressions should be
25656 scanned. In either case, *TOTAL contains the cost result. */
25659 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25661 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25662 enum machine_mode mode = GET_MODE (x);
25663 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25671 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
25673 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
25675 else if (flag_pic && SYMBOLIC_CONST (x)
25677 || (!GET_CODE (x) != LABEL_REF
25678 && (GET_CODE (x) != SYMBOL_REF
25679 || !SYMBOL_REF_LOCAL_P (x)))))
25686 if (mode == VOIDmode)
25689 switch (standard_80387_constant_p (x))
25694 default: /* Other constants */
25699 /* Start with (MEM (SYMBOL_REF)), since that's where
25700 it'll probably end up. Add a penalty for size. */
25701 *total = (COSTS_N_INSNS (1)
25702 + (flag_pic != 0 && !TARGET_64BIT)
25703 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
25709 /* The zero extensions is often completely free on x86_64, so make
25710 it as cheap as possible. */
25711 if (TARGET_64BIT && mode == DImode
25712 && GET_MODE (XEXP (x, 0)) == SImode)
25714 else if (TARGET_ZERO_EXTEND_WITH_AND)
25715 *total = cost->add;
25717 *total = cost->movzx;
25721 *total = cost->movsx;
25725 if (CONST_INT_P (XEXP (x, 1))
25726 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
25728 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25731 *total = cost->add;
25734 if ((value == 2 || value == 3)
25735 && cost->lea <= cost->shift_const)
25737 *total = cost->lea;
25747 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
25749 if (CONST_INT_P (XEXP (x, 1)))
25751 if (INTVAL (XEXP (x, 1)) > 32)
25752 *total = cost->shift_const + COSTS_N_INSNS (2);
25754 *total = cost->shift_const * 2;
25758 if (GET_CODE (XEXP (x, 1)) == AND)
25759 *total = cost->shift_var * 2;
25761 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
25766 if (CONST_INT_P (XEXP (x, 1)))
25767 *total = cost->shift_const;
25769 *total = cost->shift_var;
25774 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25776 /* ??? SSE scalar cost should be used here. */
25777 *total = cost->fmul;
25780 else if (X87_FLOAT_MODE_P (mode))
25782 *total = cost->fmul;
25785 else if (FLOAT_MODE_P (mode))
25787 /* ??? SSE vector cost should be used here. */
25788 *total = cost->fmul;
25793 rtx op0 = XEXP (x, 0);
25794 rtx op1 = XEXP (x, 1);
25796 if (CONST_INT_P (XEXP (x, 1)))
25798 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25799 for (nbits = 0; value != 0; value &= value - 1)
25803 /* This is arbitrary. */
25806 /* Compute costs correctly for widening multiplication. */
25807 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
25808 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
25809 == GET_MODE_SIZE (mode))
25811 int is_mulwiden = 0;
25812 enum machine_mode inner_mode = GET_MODE (op0);
25814 if (GET_CODE (op0) == GET_CODE (op1))
25815 is_mulwiden = 1, op1 = XEXP (op1, 0);
25816 else if (CONST_INT_P (op1))
25818 if (GET_CODE (op0) == SIGN_EXTEND)
25819 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
25822 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
25826 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
25829 *total = (cost->mult_init[MODE_INDEX (mode)]
25830 + nbits * cost->mult_bit
25831 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
25840 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25841 /* ??? SSE cost should be used here. */
25842 *total = cost->fdiv;
25843 else if (X87_FLOAT_MODE_P (mode))
25844 *total = cost->fdiv;
25845 else if (FLOAT_MODE_P (mode))
25846 /* ??? SSE vector cost should be used here. */
25847 *total = cost->fdiv;
25849 *total = cost->divide[MODE_INDEX (mode)];
25853 if (GET_MODE_CLASS (mode) == MODE_INT
25854 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
25856 if (GET_CODE (XEXP (x, 0)) == PLUS
25857 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
25858 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
25859 && CONSTANT_P (XEXP (x, 1)))
25861 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
25862 if (val == 2 || val == 4 || val == 8)
25864 *total = cost->lea;
25865 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
25866 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
25867 outer_code, speed);
25868 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25872 else if (GET_CODE (XEXP (x, 0)) == MULT
25873 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
25875 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
25876 if (val == 2 || val == 4 || val == 8)
25878 *total = cost->lea;
25879 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
25880 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25884 else if (GET_CODE (XEXP (x, 0)) == PLUS)
25886 *total = cost->lea;
25887 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
25888 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
25889 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25896 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25898 /* ??? SSE cost should be used here. */
25899 *total = cost->fadd;
25902 else if (X87_FLOAT_MODE_P (mode))
25904 *total = cost->fadd;
25907 else if (FLOAT_MODE_P (mode))
25909 /* ??? SSE vector cost should be used here. */
25910 *total = cost->fadd;
25918 if (!TARGET_64BIT && mode == DImode)
25920 *total = (cost->add * 2
25921 + (rtx_cost (XEXP (x, 0), outer_code, speed)
25922 << (GET_MODE (XEXP (x, 0)) != DImode))
25923 + (rtx_cost (XEXP (x, 1), outer_code, speed)
25924 << (GET_MODE (XEXP (x, 1)) != DImode)));
25930 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25932 /* ??? SSE cost should be used here. */
25933 *total = cost->fchs;
25936 else if (X87_FLOAT_MODE_P (mode))
25938 *total = cost->fchs;
25941 else if (FLOAT_MODE_P (mode))
25943 /* ??? SSE vector cost should be used here. */
25944 *total = cost->fchs;
25950 if (!TARGET_64BIT && mode == DImode)
25951 *total = cost->add * 2;
25953 *total = cost->add;
25957 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
25958 && XEXP (XEXP (x, 0), 1) == const1_rtx
25959 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
25960 && XEXP (x, 1) == const0_rtx)
25962 /* This kind of construct is implemented using test[bwl].
25963 Treat it as if we had an AND. */
25964 *total = (cost->add
25965 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
25966 + rtx_cost (const1_rtx, outer_code, speed));
25972 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
25977 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25978 /* ??? SSE cost should be used here. */
25979 *total = cost->fabs;
25980 else if (X87_FLOAT_MODE_P (mode))
25981 *total = cost->fabs;
25982 else if (FLOAT_MODE_P (mode))
25983 /* ??? SSE vector cost should be used here. */
25984 *total = cost->fabs;
25988 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25989 /* ??? SSE cost should be used here. */
25990 *total = cost->fsqrt;
25991 else if (X87_FLOAT_MODE_P (mode))
25992 *total = cost->fsqrt;
25993 else if (FLOAT_MODE_P (mode))
25994 /* ??? SSE vector cost should be used here. */
25995 *total = cost->fsqrt;
25999 if (XINT (x, 1) == UNSPEC_TP)
26010 static int current_machopic_label_num;
26012 /* Given a symbol name and its associated stub, write out the
26013 definition of the stub. */
26016 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26018 unsigned int length;
26019 char *binder_name, *symbol_name, lazy_ptr_name[32];
26020 int label = ++current_machopic_label_num;
26022 /* For 64-bit we shouldn't get here. */
26023 gcc_assert (!TARGET_64BIT);
26025 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26026 symb = (*targetm.strip_name_encoding) (symb);
26028 length = strlen (stub);
26029 binder_name = XALLOCAVEC (char, length + 32);
26030 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26032 length = strlen (symb);
26033 symbol_name = XALLOCAVEC (char, length + 32);
26034 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26036 sprintf (lazy_ptr_name, "L%d$lz", label);
26039 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26041 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26043 fprintf (file, "%s:\n", stub);
26044 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26048 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26049 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26050 fprintf (file, "\tjmp\t*%%edx\n");
26053 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26055 fprintf (file, "%s:\n", binder_name);
26059 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26060 fputs ("\tpushl\t%eax\n", file);
26063 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26065 fputs ("\tjmp\tdyld_stub_binding_helper\n", file);
26067 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26068 fprintf (file, "%s:\n", lazy_ptr_name);
26069 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26070 fprintf (file, ASM_LONG "%s\n", binder_name);
26074 darwin_x86_file_end (void)
26076 darwin_file_end ();
26079 #endif /* TARGET_MACHO */
26081 /* Order the registers for register allocator. */
26084 x86_order_regs_for_local_alloc (void)
26089 /* First allocate the local general purpose registers. */
26090 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26091 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26092 reg_alloc_order [pos++] = i;
26094 /* Global general purpose registers. */
26095 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26096 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26097 reg_alloc_order [pos++] = i;
26099 /* x87 registers come first in case we are doing FP math
26101 if (!TARGET_SSE_MATH)
26102 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26103 reg_alloc_order [pos++] = i;
26105 /* SSE registers. */
26106 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26107 reg_alloc_order [pos++] = i;
26108 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26109 reg_alloc_order [pos++] = i;
26111 /* x87 registers. */
26112 if (TARGET_SSE_MATH)
26113 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26114 reg_alloc_order [pos++] = i;
26116 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26117 reg_alloc_order [pos++] = i;
26119 /* Initialize the rest of array as we do not allocate some registers
26121 while (pos < FIRST_PSEUDO_REGISTER)
26122 reg_alloc_order [pos++] = 0;
26125 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26126 struct attribute_spec.handler. */
26128 ix86_handle_abi_attribute (tree *node, tree name,
26129 tree args ATTRIBUTE_UNUSED,
26130 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26132 if (TREE_CODE (*node) != FUNCTION_TYPE
26133 && TREE_CODE (*node) != METHOD_TYPE
26134 && TREE_CODE (*node) != FIELD_DECL
26135 && TREE_CODE (*node) != TYPE_DECL)
26137 warning (OPT_Wattributes, "%qE attribute only applies to functions",
26139 *no_add_attrs = true;
26144 warning (OPT_Wattributes, "%qE attribute only available for 64-bit",
26146 *no_add_attrs = true;
26150 /* Can combine regparm with all attributes but fastcall. */
26151 if (is_attribute_p ("ms_abi", name))
26153 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26155 error ("ms_abi and sysv_abi attributes are not compatible");
26160 else if (is_attribute_p ("sysv_abi", name))
26162 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26164 error ("ms_abi and sysv_abi attributes are not compatible");
26173 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26174 struct attribute_spec.handler. */
26176 ix86_handle_struct_attribute (tree *node, tree name,
26177 tree args ATTRIBUTE_UNUSED,
26178 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26181 if (DECL_P (*node))
26183 if (TREE_CODE (*node) == TYPE_DECL)
26184 type = &TREE_TYPE (*node);
26189 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26190 || TREE_CODE (*type) == UNION_TYPE)))
26192 warning (OPT_Wattributes, "%qE attribute ignored",
26194 *no_add_attrs = true;
26197 else if ((is_attribute_p ("ms_struct", name)
26198 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26199 || ((is_attribute_p ("gcc_struct", name)
26200 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26202 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
26204 *no_add_attrs = true;
26211 ix86_ms_bitfield_layout_p (const_tree record_type)
26213 return (TARGET_MS_BITFIELD_LAYOUT &&
26214 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26215 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26218 /* Returns an expression indicating where the this parameter is
26219 located on entry to the FUNCTION. */
26222 x86_this_parameter (tree function)
26224 tree type = TREE_TYPE (function);
26225 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26230 const int *parm_regs;
26232 if (ix86_function_type_abi (type) == MS_ABI)
26233 parm_regs = x86_64_ms_abi_int_parameter_registers;
26235 parm_regs = x86_64_int_parameter_registers;
26236 return gen_rtx_REG (DImode, parm_regs[aggr]);
26239 nregs = ix86_function_regparm (type, function);
26241 if (nregs > 0 && !stdarg_p (type))
26245 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26246 regno = aggr ? DX_REG : CX_REG;
26254 return gen_rtx_MEM (SImode,
26255 plus_constant (stack_pointer_rtx, 4));
26258 return gen_rtx_REG (SImode, regno);
26261 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26264 /* Determine whether x86_output_mi_thunk can succeed. */
26267 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26268 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26269 HOST_WIDE_INT vcall_offset, const_tree function)
26271 /* 64-bit can handle anything. */
26275 /* For 32-bit, everything's fine if we have one free register. */
26276 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26279 /* Need a free register for vcall_offset. */
26283 /* Need a free register for GOT references. */
26284 if (flag_pic && !(*targetm.binds_local_p) (function))
26287 /* Otherwise ok. */
26291 /* Output the assembler code for a thunk function. THUNK_DECL is the
26292 declaration for the thunk function itself, FUNCTION is the decl for
26293 the target function. DELTA is an immediate constant offset to be
26294 added to THIS. If VCALL_OFFSET is nonzero, the word at
26295 *(*this + vcall_offset) should be added to THIS. */
26298 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26299 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26300 HOST_WIDE_INT vcall_offset, tree function)
26303 rtx this_param = x86_this_parameter (function);
26306 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26307 pull it in now and let DELTA benefit. */
26308 if (REG_P (this_param))
26309 this_reg = this_param;
26310 else if (vcall_offset)
26312 /* Put the this parameter into %eax. */
26313 xops[0] = this_param;
26314 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26315 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26318 this_reg = NULL_RTX;
26320 /* Adjust the this parameter by a fixed constant. */
26323 xops[0] = GEN_INT (delta);
26324 xops[1] = this_reg ? this_reg : this_param;
26327 if (!x86_64_general_operand (xops[0], DImode))
26329 tmp = gen_rtx_REG (DImode, R10_REG);
26331 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26333 xops[1] = this_param;
26335 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26338 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26341 /* Adjust the this parameter by a value stored in the vtable. */
26345 tmp = gen_rtx_REG (DImode, R10_REG);
26348 int tmp_regno = CX_REG;
26349 if (lookup_attribute ("fastcall",
26350 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26351 tmp_regno = AX_REG;
26352 tmp = gen_rtx_REG (SImode, tmp_regno);
26355 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26357 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26359 /* Adjust the this parameter. */
26360 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26361 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26363 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26364 xops[0] = GEN_INT (vcall_offset);
26366 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26367 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26369 xops[1] = this_reg;
26370 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26373 /* If necessary, drop THIS back to its stack slot. */
26374 if (this_reg && this_reg != this_param)
26376 xops[0] = this_reg;
26377 xops[1] = this_param;
26378 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26381 xops[0] = XEXP (DECL_RTL (function), 0);
26384 if (!flag_pic || (*targetm.binds_local_p) (function))
26385 output_asm_insn ("jmp\t%P0", xops);
26386 /* All thunks should be in the same object as their target,
26387 and thus binds_local_p should be true. */
26388 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26389 gcc_unreachable ();
26392 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26393 tmp = gen_rtx_CONST (Pmode, tmp);
26394 tmp = gen_rtx_MEM (QImode, tmp);
26396 output_asm_insn ("jmp\t%A0", xops);
26401 if (!flag_pic || (*targetm.binds_local_p) (function))
26402 output_asm_insn ("jmp\t%P0", xops);
26407 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26408 tmp = (gen_rtx_SYMBOL_REF
26410 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26411 tmp = gen_rtx_MEM (QImode, tmp);
26413 output_asm_insn ("jmp\t%0", xops);
26416 #endif /* TARGET_MACHO */
26418 tmp = gen_rtx_REG (SImode, CX_REG);
26419 output_set_got (tmp, NULL_RTX);
26422 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26423 output_asm_insn ("jmp\t{*}%1", xops);
26429 x86_file_start (void)
26431 default_file_start ();
26433 darwin_file_start ();
26435 if (X86_FILE_START_VERSION_DIRECTIVE)
26436 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26437 if (X86_FILE_START_FLTUSED)
26438 fputs ("\t.global\t__fltused\n", asm_out_file);
26439 if (ix86_asm_dialect == ASM_INTEL)
26440 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26444 x86_field_alignment (tree field, int computed)
26446 enum machine_mode mode;
26447 tree type = TREE_TYPE (field);
26449 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26451 mode = TYPE_MODE (strip_array_types (type));
26452 if (mode == DFmode || mode == DCmode
26453 || GET_MODE_CLASS (mode) == MODE_INT
26454 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26455 return MIN (32, computed);
26459 /* Output assembler code to FILE to increment profiler label # LABELNO
26460 for profiling a function entry. */
26462 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26466 #ifndef NO_PROFILE_COUNTERS
26467 fprintf (file, "\tleaq\t" LPREFIX "P%d@(%%rip),%%r11\n", labelno);
26470 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26471 fputs ("\tcall\t*" MCOUNT_NAME "@GOTPCREL(%rip)\n", file);
26473 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
26477 #ifndef NO_PROFILE_COUNTERS
26478 fprintf (file, "\tleal\t" LPREFIX "P%d@GOTOFF(%%ebx),%%" PROFILE_COUNT_REGISTER "\n",
26481 fputs ("\tcall\t*" MCOUNT_NAME "@GOT(%ebx)\n", file);
26485 #ifndef NO_PROFILE_COUNTERS
26486 fprintf (file, "\tmovl\t$" LPREFIX "P%d,%%" PROFILE_COUNT_REGISTER "\n",
26489 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
26493 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26494 /* We don't have exact information about the insn sizes, but we may assume
26495 quite safely that we are informed about all 1 byte insns and memory
26496 address sizes. This is enough to eliminate unnecessary padding in
26500 min_insn_size (rtx insn)
26504 if (!INSN_P (insn) || !active_insn_p (insn))
26507 /* Discard alignments we've emit and jump instructions. */
26508 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26509 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26511 if (JUMP_TABLE_DATA_P (insn))
26514 /* Important case - calls are always 5 bytes.
26515 It is common to have many calls in the row. */
26517 && symbolic_reference_mentioned_p (PATTERN (insn))
26518 && !SIBLING_CALL_P (insn))
26520 len = get_attr_length (insn);
26524 /* For normal instructions we rely on get_attr_length being exact,
26525 with a few exceptions. */
26526 if (!JUMP_P (insn))
26528 enum attr_type type = get_attr_type (insn);
26533 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
26534 || asm_noperands (PATTERN (insn)) >= 0)
26541 /* Otherwise trust get_attr_length. */
26545 l = get_attr_length_address (insn);
26546 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26555 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26559 ix86_avoid_jump_mispredicts (void)
26561 rtx insn, start = get_insns ();
26562 int nbytes = 0, njumps = 0;
26565 /* Look for all minimal intervals of instructions containing 4 jumps.
26566 The intervals are bounded by START and INSN. NBYTES is the total
26567 size of instructions in the interval including INSN and not including
26568 START. When the NBYTES is smaller than 16 bytes, it is possible
26569 that the end of START and INSN ends up in the same 16byte page.
26571 The smallest offset in the page INSN can start is the case where START
26572 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26573 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
26575 for (insn = start; insn; insn = NEXT_INSN (insn))
26579 if (LABEL_P (insn))
26581 int align = label_to_alignment (insn);
26582 int max_skip = label_to_max_skip (insn);
26586 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
26587 already in the current 16 byte page, because otherwise
26588 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
26589 bytes to reach 16 byte boundary. */
26591 || (align <= 3 && max_skip != (1 << align) - 1))
26594 fprintf (dump_file, "Label %i with max_skip %i\n",
26595 INSN_UID (insn), max_skip);
26598 while (nbytes + max_skip >= 16)
26600 start = NEXT_INSN (start);
26601 if ((JUMP_P (start)
26602 && GET_CODE (PATTERN (start)) != ADDR_VEC
26603 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26605 njumps--, isjump = 1;
26608 nbytes -= min_insn_size (start);
26614 min_size = min_insn_size (insn);
26615 nbytes += min_size;
26617 fprintf (dump_file, "Insn %i estimated to %i bytes\n",
26618 INSN_UID (insn), min_size);
26620 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26621 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26629 start = NEXT_INSN (start);
26630 if ((JUMP_P (start)
26631 && GET_CODE (PATTERN (start)) != ADDR_VEC
26632 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26634 njumps--, isjump = 1;
26637 nbytes -= min_insn_size (start);
26639 gcc_assert (njumps >= 0);
26641 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26642 INSN_UID (start), INSN_UID (insn), nbytes);
26644 if (njumps == 3 && isjump && nbytes < 16)
26646 int padsize = 15 - nbytes + min_insn_size (insn);
26649 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26650 INSN_UID (insn), padsize);
26651 emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
26657 /* AMD Athlon works faster
26658 when RET is not destination of conditional jump or directly preceded
26659 by other jump instruction. We avoid the penalty by inserting NOP just
26660 before the RET instructions in such cases. */
26662 ix86_pad_returns (void)
26667 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26669 basic_block bb = e->src;
26670 rtx ret = BB_END (bb);
26672 bool replace = false;
26674 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26675 || optimize_bb_for_size_p (bb))
26677 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26678 if (active_insn_p (prev) || LABEL_P (prev))
26680 if (prev && LABEL_P (prev))
26685 FOR_EACH_EDGE (e, ei, bb->preds)
26686 if (EDGE_FREQUENCY (e) && e->src->index >= 0
26687 && !(e->flags & EDGE_FALLTHRU))
26692 prev = prev_active_insn (ret);
26694 && ((JUMP_P (prev) && any_condjump_p (prev))
26697 /* Empty functions get branch mispredict even when the jump destination
26698 is not visible to us. */
26699 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
26704 emit_jump_insn_before (gen_return_internal_long (), ret);
26710 /* Implement machine specific optimizations. We implement padding of returns
26711 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26715 if (optimize && optimize_function_for_speed_p (cfun))
26717 if (TARGET_PAD_RETURNS)
26718 ix86_pad_returns ();
26719 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26720 if (TARGET_FOUR_JUMP_LIMIT)
26721 ix86_avoid_jump_mispredicts ();
26726 /* Return nonzero when QImode register that must be represented via REX prefix
26729 x86_extended_QIreg_mentioned_p (rtx insn)
26732 extract_insn_cached (insn);
26733 for (i = 0; i < recog_data.n_operands; i++)
26734 if (REG_P (recog_data.operand[i])
26735 && REGNO (recog_data.operand[i]) > BX_REG)
26740 /* Return nonzero when P points to register encoded via REX prefix.
26741 Called via for_each_rtx. */
26743 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
26745 unsigned int regno;
26748 regno = REGNO (*p);
26749 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
26752 /* Return true when INSN mentions register that must be encoded using REX
26755 x86_extended_reg_mentioned_p (rtx insn)
26757 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
26758 extended_reg_mentioned_1, NULL);
26761 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26762 optabs would emit if we didn't have TFmode patterns. */
26765 x86_emit_floatuns (rtx operands[2])
26767 rtx neglab, donelab, i0, i1, f0, in, out;
26768 enum machine_mode mode, inmode;
26770 inmode = GET_MODE (operands[1]);
26771 gcc_assert (inmode == SImode || inmode == DImode);
26774 in = force_reg (inmode, operands[1]);
26775 mode = GET_MODE (out);
26776 neglab = gen_label_rtx ();
26777 donelab = gen_label_rtx ();
26778 f0 = gen_reg_rtx (mode);
26780 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
26782 expand_float (out, in, 0);
26784 emit_jump_insn (gen_jump (donelab));
26787 emit_label (neglab);
26789 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
26791 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
26793 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
26795 expand_float (f0, i0, 0);
26797 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
26799 emit_label (donelab);
26802 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26803 with all elements equal to VAR. Return true if successful. */
26806 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
26807 rtx target, rtx val)
26809 enum machine_mode hmode, smode, wsmode, wvmode;
26824 val = force_reg (GET_MODE_INNER (mode), val);
26825 x = gen_rtx_VEC_DUPLICATE (mode, val);
26826 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26832 if (TARGET_SSE || TARGET_3DNOW_A)
26834 val = gen_lowpart (SImode, val);
26835 x = gen_rtx_TRUNCATE (HImode, val);
26836 x = gen_rtx_VEC_DUPLICATE (mode, x);
26837 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26859 /* Extend HImode to SImode using a paradoxical SUBREG. */
26860 tmp1 = gen_reg_rtx (SImode);
26861 emit_move_insn (tmp1, gen_lowpart (SImode, val));
26862 /* Insert the SImode value as low element of V4SImode vector. */
26863 tmp2 = gen_reg_rtx (V4SImode);
26864 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
26865 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
26866 CONST0_RTX (V4SImode),
26868 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
26869 /* Cast the V4SImode vector back to a V8HImode vector. */
26870 tmp1 = gen_reg_rtx (V8HImode);
26871 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
26872 /* Duplicate the low short through the whole low SImode word. */
26873 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
26874 /* Cast the V8HImode vector back to a V4SImode vector. */
26875 tmp2 = gen_reg_rtx (V4SImode);
26876 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
26877 /* Replicate the low element of the V4SImode vector. */
26878 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
26879 /* Cast the V2SImode back to V8HImode, and store in target. */
26880 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
26891 /* Extend QImode to SImode using a paradoxical SUBREG. */
26892 tmp1 = gen_reg_rtx (SImode);
26893 emit_move_insn (tmp1, gen_lowpart (SImode, val));
26894 /* Insert the SImode value as low element of V4SImode vector. */
26895 tmp2 = gen_reg_rtx (V4SImode);
26896 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
26897 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
26898 CONST0_RTX (V4SImode),
26900 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
26901 /* Cast the V4SImode vector back to a V16QImode vector. */
26902 tmp1 = gen_reg_rtx (V16QImode);
26903 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
26904 /* Duplicate the low byte through the whole low SImode word. */
26905 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
26906 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
26907 /* Cast the V16QImode vector back to a V4SImode vector. */
26908 tmp2 = gen_reg_rtx (V4SImode);
26909 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
26910 /* Replicate the low element of the V4SImode vector. */
26911 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
26912 /* Cast the V2SImode back to V16QImode, and store in target. */
26913 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
26921 /* Replicate the value once into the next wider mode and recurse. */
26922 val = convert_modes (wsmode, smode, val, true);
26923 x = expand_simple_binop (wsmode, ASHIFT, val,
26924 GEN_INT (GET_MODE_BITSIZE (smode)),
26925 NULL_RTX, 1, OPTAB_LIB_WIDEN);
26926 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
26928 x = gen_reg_rtx (wvmode);
26929 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
26930 gcc_unreachable ();
26931 emit_move_insn (target, gen_lowpart (mode, x));
26954 rtx tmp = gen_reg_rtx (hmode);
26955 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
26956 emit_insn (gen_rtx_SET (VOIDmode, target,
26957 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
26966 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26967 whose ONE_VAR element is VAR, and other elements are zero. Return true
26971 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
26972 rtx target, rtx var, int one_var)
26974 enum machine_mode vsimode;
26977 bool use_vector_set = false;
26982 /* For SSE4.1, we normally use vector set. But if the second
26983 element is zero and inter-unit moves are OK, we use movq
26985 use_vector_set = (TARGET_64BIT
26987 && !(TARGET_INTER_UNIT_MOVES
26993 use_vector_set = TARGET_SSE4_1;
26996 use_vector_set = TARGET_SSE2;
26999 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27006 use_vector_set = TARGET_AVX;
27009 /* Use ix86_expand_vector_set in 64bit mode only. */
27010 use_vector_set = TARGET_AVX && TARGET_64BIT;
27016 if (use_vector_set)
27018 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27019 var = force_reg (GET_MODE_INNER (mode), var);
27020 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27036 var = force_reg (GET_MODE_INNER (mode), var);
27037 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27038 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27043 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27044 new_target = gen_reg_rtx (mode);
27046 new_target = target;
27047 var = force_reg (GET_MODE_INNER (mode), var);
27048 x = gen_rtx_VEC_DUPLICATE (mode, var);
27049 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27050 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27053 /* We need to shuffle the value to the correct position, so
27054 create a new pseudo to store the intermediate result. */
27056 /* With SSE2, we can use the integer shuffle insns. */
27057 if (mode != V4SFmode && TARGET_SSE2)
27059 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27061 GEN_INT (one_var == 1 ? 0 : 1),
27062 GEN_INT (one_var == 2 ? 0 : 1),
27063 GEN_INT (one_var == 3 ? 0 : 1)));
27064 if (target != new_target)
27065 emit_move_insn (target, new_target);
27069 /* Otherwise convert the intermediate result to V4SFmode and
27070 use the SSE1 shuffle instructions. */
27071 if (mode != V4SFmode)
27073 tmp = gen_reg_rtx (V4SFmode);
27074 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27079 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27081 GEN_INT (one_var == 1 ? 0 : 1),
27082 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27083 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27085 if (mode != V4SFmode)
27086 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27087 else if (tmp != target)
27088 emit_move_insn (target, tmp);
27090 else if (target != new_target)
27091 emit_move_insn (target, new_target);
27096 vsimode = V4SImode;
27102 vsimode = V2SImode;
27108 /* Zero extend the variable element to SImode and recurse. */
27109 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27111 x = gen_reg_rtx (vsimode);
27112 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27114 gcc_unreachable ();
27116 emit_move_insn (target, gen_lowpart (mode, x));
27124 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27125 consisting of the values in VALS. It is known that all elements
27126 except ONE_VAR are constants. Return true if successful. */
27129 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27130 rtx target, rtx vals, int one_var)
27132 rtx var = XVECEXP (vals, 0, one_var);
27133 enum machine_mode wmode;
27136 const_vec = copy_rtx (vals);
27137 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27138 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27146 /* For the two element vectors, it's just as easy to use
27147 the general case. */
27151 /* Use ix86_expand_vector_set in 64bit mode only. */
27174 /* There's no way to set one QImode entry easily. Combine
27175 the variable value with its adjacent constant value, and
27176 promote to an HImode set. */
27177 x = XVECEXP (vals, 0, one_var ^ 1);
27180 var = convert_modes (HImode, QImode, var, true);
27181 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27182 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27183 x = GEN_INT (INTVAL (x) & 0xff);
27187 var = convert_modes (HImode, QImode, var, true);
27188 x = gen_int_mode (INTVAL (x) << 8, HImode);
27190 if (x != const0_rtx)
27191 var = expand_simple_binop (HImode, IOR, var, x, var,
27192 1, OPTAB_LIB_WIDEN);
27194 x = gen_reg_rtx (wmode);
27195 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27196 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27198 emit_move_insn (target, gen_lowpart (mode, x));
27205 emit_move_insn (target, const_vec);
27206 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27210 /* A subroutine of ix86_expand_vector_init_general. Use vector
27211 concatenate to handle the most general case: all values variable,
27212 and none identical. */
27215 ix86_expand_vector_init_concat (enum machine_mode mode,
27216 rtx target, rtx *ops, int n)
27218 enum machine_mode cmode, hmode = VOIDmode;
27219 rtx first[8], second[4];
27259 gcc_unreachable ();
27262 if (!register_operand (ops[1], cmode))
27263 ops[1] = force_reg (cmode, ops[1]);
27264 if (!register_operand (ops[0], cmode))
27265 ops[0] = force_reg (cmode, ops[0]);
27266 emit_insn (gen_rtx_SET (VOIDmode, target,
27267 gen_rtx_VEC_CONCAT (mode, ops[0],
27287 gcc_unreachable ();
27303 gcc_unreachable ();
27308 /* FIXME: We process inputs backward to help RA. PR 36222. */
27311 for (; i > 0; i -= 2, j--)
27313 first[j] = gen_reg_rtx (cmode);
27314 v = gen_rtvec (2, ops[i - 1], ops[i]);
27315 ix86_expand_vector_init (false, first[j],
27316 gen_rtx_PARALLEL (cmode, v));
27322 gcc_assert (hmode != VOIDmode);
27323 for (i = j = 0; i < n; i += 2, j++)
27325 second[j] = gen_reg_rtx (hmode);
27326 ix86_expand_vector_init_concat (hmode, second [j],
27330 ix86_expand_vector_init_concat (mode, target, second, n);
27333 ix86_expand_vector_init_concat (mode, target, first, n);
27337 gcc_unreachable ();
27341 /* A subroutine of ix86_expand_vector_init_general. Use vector
27342 interleave to handle the most general case: all values variable,
27343 and none identical. */
27346 ix86_expand_vector_init_interleave (enum machine_mode mode,
27347 rtx target, rtx *ops, int n)
27349 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27352 rtx (*gen_load_even) (rtx, rtx, rtx);
27353 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27354 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27359 gen_load_even = gen_vec_setv8hi;
27360 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27361 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27362 inner_mode = HImode;
27363 first_imode = V4SImode;
27364 second_imode = V2DImode;
27365 third_imode = VOIDmode;
27368 gen_load_even = gen_vec_setv16qi;
27369 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27370 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27371 inner_mode = QImode;
27372 first_imode = V8HImode;
27373 second_imode = V4SImode;
27374 third_imode = V2DImode;
27377 gcc_unreachable ();
27380 for (i = 0; i < n; i++)
27382 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27383 op0 = gen_reg_rtx (SImode);
27384 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27386 /* Insert the SImode value as low element of V4SImode vector. */
27387 op1 = gen_reg_rtx (V4SImode);
27388 op0 = gen_rtx_VEC_MERGE (V4SImode,
27389 gen_rtx_VEC_DUPLICATE (V4SImode,
27391 CONST0_RTX (V4SImode),
27393 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27395 /* Cast the V4SImode vector back to a vector in orignal mode. */
27396 op0 = gen_reg_rtx (mode);
27397 emit_move_insn (op0, gen_lowpart (mode, op1));
27399 /* Load even elements into the second positon. */
27400 emit_insn ((*gen_load_even) (op0,
27401 force_reg (inner_mode,
27405 /* Cast vector to FIRST_IMODE vector. */
27406 ops[i] = gen_reg_rtx (first_imode);
27407 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27410 /* Interleave low FIRST_IMODE vectors. */
27411 for (i = j = 0; i < n; i += 2, j++)
27413 op0 = gen_reg_rtx (first_imode);
27414 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27416 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27417 ops[j] = gen_reg_rtx (second_imode);
27418 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27421 /* Interleave low SECOND_IMODE vectors. */
27422 switch (second_imode)
27425 for (i = j = 0; i < n / 2; i += 2, j++)
27427 op0 = gen_reg_rtx (second_imode);
27428 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27431 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27433 ops[j] = gen_reg_rtx (third_imode);
27434 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27436 second_imode = V2DImode;
27437 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27441 op0 = gen_reg_rtx (second_imode);
27442 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27445 /* Cast the SECOND_IMODE vector back to a vector on original
27447 emit_insn (gen_rtx_SET (VOIDmode, target,
27448 gen_lowpart (mode, op0)));
27452 gcc_unreachable ();
27456 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27457 all values variable, and none identical. */
27460 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27461 rtx target, rtx vals)
27463 rtx ops[32], op0, op1;
27464 enum machine_mode half_mode = VOIDmode;
27471 if (!mmx_ok && !TARGET_SSE)
27483 n = GET_MODE_NUNITS (mode);
27484 for (i = 0; i < n; i++)
27485 ops[i] = XVECEXP (vals, 0, i);
27486 ix86_expand_vector_init_concat (mode, target, ops, n);
27490 half_mode = V16QImode;
27494 half_mode = V8HImode;
27498 n = GET_MODE_NUNITS (mode);
27499 for (i = 0; i < n; i++)
27500 ops[i] = XVECEXP (vals, 0, i);
27501 op0 = gen_reg_rtx (half_mode);
27502 op1 = gen_reg_rtx (half_mode);
27503 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27505 ix86_expand_vector_init_interleave (half_mode, op1,
27506 &ops [n >> 1], n >> 2);
27507 emit_insn (gen_rtx_SET (VOIDmode, target,
27508 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27512 if (!TARGET_SSE4_1)
27520 /* Don't use ix86_expand_vector_init_interleave if we can't
27521 move from GPR to SSE register directly. */
27522 if (!TARGET_INTER_UNIT_MOVES)
27525 n = GET_MODE_NUNITS (mode);
27526 for (i = 0; i < n; i++)
27527 ops[i] = XVECEXP (vals, 0, i);
27528 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27536 gcc_unreachable ();
27540 int i, j, n_elts, n_words, n_elt_per_word;
27541 enum machine_mode inner_mode;
27542 rtx words[4], shift;
27544 inner_mode = GET_MODE_INNER (mode);
27545 n_elts = GET_MODE_NUNITS (mode);
27546 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27547 n_elt_per_word = n_elts / n_words;
27548 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27550 for (i = 0; i < n_words; ++i)
27552 rtx word = NULL_RTX;
27554 for (j = 0; j < n_elt_per_word; ++j)
27556 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27557 elt = convert_modes (word_mode, inner_mode, elt, true);
27563 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27564 word, 1, OPTAB_LIB_WIDEN);
27565 word = expand_simple_binop (word_mode, IOR, word, elt,
27566 word, 1, OPTAB_LIB_WIDEN);
27574 emit_move_insn (target, gen_lowpart (mode, words[0]));
27575 else if (n_words == 2)
27577 rtx tmp = gen_reg_rtx (mode);
27578 emit_clobber (tmp);
27579 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27580 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27581 emit_move_insn (target, tmp);
27583 else if (n_words == 4)
27585 rtx tmp = gen_reg_rtx (V4SImode);
27586 gcc_assert (word_mode == SImode);
27587 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27588 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27589 emit_move_insn (target, gen_lowpart (mode, tmp));
27592 gcc_unreachable ();
27596 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27597 instructions unless MMX_OK is true. */
27600 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27602 enum machine_mode mode = GET_MODE (target);
27603 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27604 int n_elts = GET_MODE_NUNITS (mode);
27605 int n_var = 0, one_var = -1;
27606 bool all_same = true, all_const_zero = true;
27610 for (i = 0; i < n_elts; ++i)
27612 x = XVECEXP (vals, 0, i);
27613 if (!(CONST_INT_P (x)
27614 || GET_CODE (x) == CONST_DOUBLE
27615 || GET_CODE (x) == CONST_FIXED))
27616 n_var++, one_var = i;
27617 else if (x != CONST0_RTX (inner_mode))
27618 all_const_zero = false;
27619 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27623 /* Constants are best loaded from the constant pool. */
27626 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27630 /* If all values are identical, broadcast the value. */
27632 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27633 XVECEXP (vals, 0, 0)))
27636 /* Values where only one field is non-constant are best loaded from
27637 the pool and overwritten via move later. */
27641 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27642 XVECEXP (vals, 0, one_var),
27646 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27650 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27654 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27656 enum machine_mode mode = GET_MODE (target);
27657 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27658 enum machine_mode half_mode;
27659 bool use_vec_merge = false;
27661 static rtx (*gen_extract[6][2]) (rtx, rtx)
27663 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27664 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27665 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27666 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27667 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27668 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27670 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27672 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27673 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27674 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27675 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27676 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27677 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
27687 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
27688 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
27690 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
27692 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
27693 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27699 use_vec_merge = TARGET_SSE4_1;
27707 /* For the two element vectors, we implement a VEC_CONCAT with
27708 the extraction of the other element. */
27710 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
27711 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
27714 op0 = val, op1 = tmp;
27716 op0 = tmp, op1 = val;
27718 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
27719 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27724 use_vec_merge = TARGET_SSE4_1;
27731 use_vec_merge = true;
27735 /* tmp = target = A B C D */
27736 tmp = copy_to_reg (target);
27737 /* target = A A B B */
27738 emit_insn (gen_sse_unpcklps (target, target, target));
27739 /* target = X A B B */
27740 ix86_expand_vector_set (false, target, val, 0);
27741 /* target = A X C D */
27742 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27743 const1_rtx, const0_rtx,
27744 GEN_INT (2+4), GEN_INT (3+4)));
27748 /* tmp = target = A B C D */
27749 tmp = copy_to_reg (target);
27750 /* tmp = X B C D */
27751 ix86_expand_vector_set (false, tmp, val, 0);
27752 /* target = A B X D */
27753 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27754 const0_rtx, const1_rtx,
27755 GEN_INT (0+4), GEN_INT (3+4)));
27759 /* tmp = target = A B C D */
27760 tmp = copy_to_reg (target);
27761 /* tmp = X B C D */
27762 ix86_expand_vector_set (false, tmp, val, 0);
27763 /* target = A B X D */
27764 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27765 const0_rtx, const1_rtx,
27766 GEN_INT (2+4), GEN_INT (0+4)));
27770 gcc_unreachable ();
27775 use_vec_merge = TARGET_SSE4_1;
27779 /* Element 0 handled by vec_merge below. */
27782 use_vec_merge = true;
27788 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27789 store into element 0, then shuffle them back. */
27793 order[0] = GEN_INT (elt);
27794 order[1] = const1_rtx;
27795 order[2] = const2_rtx;
27796 order[3] = GEN_INT (3);
27797 order[elt] = const0_rtx;
27799 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27800 order[1], order[2], order[3]));
27802 ix86_expand_vector_set (false, target, val, 0);
27804 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27805 order[1], order[2], order[3]));
27809 /* For SSE1, we have to reuse the V4SF code. */
27810 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
27811 gen_lowpart (SFmode, val), elt);
27816 use_vec_merge = TARGET_SSE2;
27819 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27823 use_vec_merge = TARGET_SSE4_1;
27830 half_mode = V16QImode;
27836 half_mode = V8HImode;
27842 half_mode = V4SImode;
27848 half_mode = V2DImode;
27854 half_mode = V4SFmode;
27860 half_mode = V2DFmode;
27866 /* Compute offset. */
27870 gcc_assert (i <= 1);
27872 /* Extract the half. */
27873 tmp = gen_reg_rtx (half_mode);
27874 emit_insn ((*gen_extract[j][i]) (tmp, target));
27876 /* Put val in tmp at elt. */
27877 ix86_expand_vector_set (false, tmp, val, elt);
27880 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
27889 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
27890 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
27891 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27895 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
27897 emit_move_insn (mem, target);
27899 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
27900 emit_move_insn (tmp, val);
27902 emit_move_insn (target, mem);
27907 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
27909 enum machine_mode mode = GET_MODE (vec);
27910 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27911 bool use_vec_extr = false;
27924 use_vec_extr = true;
27928 use_vec_extr = TARGET_SSE4_1;
27940 tmp = gen_reg_rtx (mode);
27941 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
27942 GEN_INT (elt), GEN_INT (elt),
27943 GEN_INT (elt+4), GEN_INT (elt+4)));
27947 tmp = gen_reg_rtx (mode);
27948 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
27952 gcc_unreachable ();
27955 use_vec_extr = true;
27960 use_vec_extr = TARGET_SSE4_1;
27974 tmp = gen_reg_rtx (mode);
27975 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
27976 GEN_INT (elt), GEN_INT (elt),
27977 GEN_INT (elt), GEN_INT (elt)));
27981 tmp = gen_reg_rtx (mode);
27982 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
27986 gcc_unreachable ();
27989 use_vec_extr = true;
27994 /* For SSE1, we have to reuse the V4SF code. */
27995 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
27996 gen_lowpart (V4SFmode, vec), elt);
28002 use_vec_extr = TARGET_SSE2;
28005 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28009 use_vec_extr = TARGET_SSE4_1;
28013 /* ??? Could extract the appropriate HImode element and shift. */
28020 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28021 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28023 /* Let the rtl optimizers know about the zero extension performed. */
28024 if (inner_mode == QImode || inner_mode == HImode)
28026 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28027 target = gen_lowpart (SImode, target);
28030 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28034 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28036 emit_move_insn (mem, vec);
28038 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28039 emit_move_insn (target, tmp);
28043 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28044 pattern to reduce; DEST is the destination; IN is the input vector. */
28047 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28049 rtx tmp1, tmp2, tmp3;
28051 tmp1 = gen_reg_rtx (V4SFmode);
28052 tmp2 = gen_reg_rtx (V4SFmode);
28053 tmp3 = gen_reg_rtx (V4SFmode);
28055 emit_insn (gen_sse_movhlps (tmp1, in, in));
28056 emit_insn (fn (tmp2, tmp1, in));
28058 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28059 const1_rtx, const1_rtx,
28060 GEN_INT (1+4), GEN_INT (1+4)));
28061 emit_insn (fn (dest, tmp2, tmp3));
28064 /* Target hook for scalar_mode_supported_p. */
28066 ix86_scalar_mode_supported_p (enum machine_mode mode)
28068 if (DECIMAL_FLOAT_MODE_P (mode))
28070 else if (mode == TFmode)
28073 return default_scalar_mode_supported_p (mode);
28076 /* Implements target hook vector_mode_supported_p. */
28078 ix86_vector_mode_supported_p (enum machine_mode mode)
28080 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28082 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28084 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28086 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28088 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28093 /* Target hook for c_mode_for_suffix. */
28094 static enum machine_mode
28095 ix86_c_mode_for_suffix (char suffix)
28105 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28107 We do this in the new i386 backend to maintain source compatibility
28108 with the old cc0-based compiler. */
28111 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28112 tree inputs ATTRIBUTE_UNUSED,
28115 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28117 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28122 /* Implements target vector targetm.asm.encode_section_info. This
28123 is not used by netware. */
28125 static void ATTRIBUTE_UNUSED
28126 ix86_encode_section_info (tree decl, rtx rtl, int first)
28128 default_encode_section_info (decl, rtl, first);
28130 if (TREE_CODE (decl) == VAR_DECL
28131 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28132 && ix86_in_large_data_p (decl))
28133 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28136 /* Worker function for REVERSE_CONDITION. */
28139 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28141 return (mode != CCFPmode && mode != CCFPUmode
28142 ? reverse_condition (code)
28143 : reverse_condition_maybe_unordered (code));
28146 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28150 output_387_reg_move (rtx insn, rtx *operands)
28152 if (REG_P (operands[0]))
28154 if (REG_P (operands[1])
28155 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28157 if (REGNO (operands[0]) == FIRST_STACK_REG)
28158 return output_387_ffreep (operands, 0);
28159 return "fstp\t%y0";
28161 if (STACK_TOP_P (operands[0]))
28162 return "fld%Z1\t%y1";
28165 else if (MEM_P (operands[0]))
28167 gcc_assert (REG_P (operands[1]));
28168 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28169 return "fstp%Z0\t%y0";
28172 /* There is no non-popping store to memory for XFmode.
28173 So if we need one, follow the store with a load. */
28174 if (GET_MODE (operands[0]) == XFmode)
28175 return "fstp%Z0\t%y0\n\tfld%Z0\t%y0";
28177 return "fst%Z0\t%y0";
28184 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28185 FP status register is set. */
28188 ix86_emit_fp_unordered_jump (rtx label)
28190 rtx reg = gen_reg_rtx (HImode);
28193 emit_insn (gen_x86_fnstsw_1 (reg));
28195 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28197 emit_insn (gen_x86_sahf_1 (reg));
28199 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28200 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28204 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28206 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28207 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28210 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28211 gen_rtx_LABEL_REF (VOIDmode, label),
28213 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28215 emit_jump_insn (temp);
28216 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28219 /* Output code to perform a log1p XFmode calculation. */
28221 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28223 rtx label1 = gen_label_rtx ();
28224 rtx label2 = gen_label_rtx ();
28226 rtx tmp = gen_reg_rtx (XFmode);
28227 rtx tmp2 = gen_reg_rtx (XFmode);
28230 emit_insn (gen_absxf2 (tmp, op1));
28231 test = gen_rtx_GE (VOIDmode, tmp,
28232 CONST_DOUBLE_FROM_REAL_VALUE (
28233 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28235 emit_jump_insn (gen_cbranchxf4 (test, XEXP (test, 0), XEXP (test, 1), label1));
28237 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28238 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28239 emit_jump (label2);
28241 emit_label (label1);
28242 emit_move_insn (tmp, CONST1_RTX (XFmode));
28243 emit_insn (gen_addxf3 (tmp, op1, tmp));
28244 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28245 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28247 emit_label (label2);
28250 /* Output code to perform a Newton-Rhapson approximation of a single precision
28251 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28253 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28255 rtx x0, x1, e0, e1, two;
28257 x0 = gen_reg_rtx (mode);
28258 e0 = gen_reg_rtx (mode);
28259 e1 = gen_reg_rtx (mode);
28260 x1 = gen_reg_rtx (mode);
28262 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28264 if (VECTOR_MODE_P (mode))
28265 two = ix86_build_const_vector (SFmode, true, two);
28267 two = force_reg (mode, two);
28269 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28271 /* x0 = rcp(b) estimate */
28272 emit_insn (gen_rtx_SET (VOIDmode, x0,
28273 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28276 emit_insn (gen_rtx_SET (VOIDmode, e0,
28277 gen_rtx_MULT (mode, x0, b)));
28279 emit_insn (gen_rtx_SET (VOIDmode, e1,
28280 gen_rtx_MINUS (mode, two, e0)));
28282 emit_insn (gen_rtx_SET (VOIDmode, x1,
28283 gen_rtx_MULT (mode, x0, e1)));
28285 emit_insn (gen_rtx_SET (VOIDmode, res,
28286 gen_rtx_MULT (mode, a, x1)));
28289 /* Output code to perform a Newton-Rhapson approximation of a
28290 single precision floating point [reciprocal] square root. */
28292 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28295 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28298 x0 = gen_reg_rtx (mode);
28299 e0 = gen_reg_rtx (mode);
28300 e1 = gen_reg_rtx (mode);
28301 e2 = gen_reg_rtx (mode);
28302 e3 = gen_reg_rtx (mode);
28304 real_from_integer (&r, VOIDmode, -3, -1, 0);
28305 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28307 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28308 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28310 if (VECTOR_MODE_P (mode))
28312 mthree = ix86_build_const_vector (SFmode, true, mthree);
28313 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28316 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28317 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28319 /* x0 = rsqrt(a) estimate */
28320 emit_insn (gen_rtx_SET (VOIDmode, x0,
28321 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28324 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28329 zero = gen_reg_rtx (mode);
28330 mask = gen_reg_rtx (mode);
28332 zero = force_reg (mode, CONST0_RTX(mode));
28333 emit_insn (gen_rtx_SET (VOIDmode, mask,
28334 gen_rtx_NE (mode, zero, a)));
28336 emit_insn (gen_rtx_SET (VOIDmode, x0,
28337 gen_rtx_AND (mode, x0, mask)));
28341 emit_insn (gen_rtx_SET (VOIDmode, e0,
28342 gen_rtx_MULT (mode, x0, a)));
28344 emit_insn (gen_rtx_SET (VOIDmode, e1,
28345 gen_rtx_MULT (mode, e0, x0)));
28348 mthree = force_reg (mode, mthree);
28349 emit_insn (gen_rtx_SET (VOIDmode, e2,
28350 gen_rtx_PLUS (mode, e1, mthree)));
28352 mhalf = force_reg (mode, mhalf);
28354 /* e3 = -.5 * x0 */
28355 emit_insn (gen_rtx_SET (VOIDmode, e3,
28356 gen_rtx_MULT (mode, x0, mhalf)));
28358 /* e3 = -.5 * e0 */
28359 emit_insn (gen_rtx_SET (VOIDmode, e3,
28360 gen_rtx_MULT (mode, e0, mhalf)));
28361 /* ret = e2 * e3 */
28362 emit_insn (gen_rtx_SET (VOIDmode, res,
28363 gen_rtx_MULT (mode, e2, e3)));
28366 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28368 static void ATTRIBUTE_UNUSED
28369 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28372 /* With Binutils 2.15, the "@unwind" marker must be specified on
28373 every occurrence of the ".eh_frame" section, not just the first
28376 && strcmp (name, ".eh_frame") == 0)
28378 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28379 flags & SECTION_WRITE ? "aw" : "a");
28382 default_elf_asm_named_section (name, flags, decl);
28385 /* Return the mangling of TYPE if it is an extended fundamental type. */
28387 static const char *
28388 ix86_mangle_type (const_tree type)
28390 type = TYPE_MAIN_VARIANT (type);
28392 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28393 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28396 switch (TYPE_MODE (type))
28399 /* __float128 is "g". */
28402 /* "long double" or __float80 is "e". */
28409 /* For 32-bit code we can save PIC register setup by using
28410 __stack_chk_fail_local hidden function instead of calling
28411 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28412 register, so it is better to call __stack_chk_fail directly. */
28415 ix86_stack_protect_fail (void)
28417 return TARGET_64BIT
28418 ? default_external_stack_protect_fail ()
28419 : default_hidden_stack_protect_fail ();
28422 /* Select a format to encode pointers in exception handling data. CODE
28423 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28424 true if the symbol may be affected by dynamic relocations.
28426 ??? All x86 object file formats are capable of representing this.
28427 After all, the relocation needed is the same as for the call insn.
28428 Whether or not a particular assembler allows us to enter such, I
28429 guess we'll have to see. */
28431 asm_preferred_eh_data_format (int code, int global)
28435 int type = DW_EH_PE_sdata8;
28437 || ix86_cmodel == CM_SMALL_PIC
28438 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28439 type = DW_EH_PE_sdata4;
28440 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28442 if (ix86_cmodel == CM_SMALL
28443 || (ix86_cmodel == CM_MEDIUM && code))
28444 return DW_EH_PE_udata4;
28445 return DW_EH_PE_absptr;
28448 /* Expand copysign from SIGN to the positive value ABS_VALUE
28449 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28452 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28454 enum machine_mode mode = GET_MODE (sign);
28455 rtx sgn = gen_reg_rtx (mode);
28456 if (mask == NULL_RTX)
28458 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28459 if (!VECTOR_MODE_P (mode))
28461 /* We need to generate a scalar mode mask in this case. */
28462 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28463 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28464 mask = gen_reg_rtx (mode);
28465 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28469 mask = gen_rtx_NOT (mode, mask);
28470 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28471 gen_rtx_AND (mode, mask, sign)));
28472 emit_insn (gen_rtx_SET (VOIDmode, result,
28473 gen_rtx_IOR (mode, abs_value, sgn)));
28476 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28477 mask for masking out the sign-bit is stored in *SMASK, if that is
28480 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28482 enum machine_mode mode = GET_MODE (op0);
28485 xa = gen_reg_rtx (mode);
28486 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28487 if (!VECTOR_MODE_P (mode))
28489 /* We need to generate a scalar mode mask in this case. */
28490 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28491 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28492 mask = gen_reg_rtx (mode);
28493 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28495 emit_insn (gen_rtx_SET (VOIDmode, xa,
28496 gen_rtx_AND (mode, op0, mask)));
28504 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28505 swapping the operands if SWAP_OPERANDS is true. The expanded
28506 code is a forward jump to a newly created label in case the
28507 comparison is true. The generated label rtx is returned. */
28509 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28510 bool swap_operands)
28521 label = gen_label_rtx ();
28522 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28523 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28524 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28525 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28526 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28527 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28528 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28529 JUMP_LABEL (tmp) = label;
28534 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28535 using comparison code CODE. Operands are swapped for the comparison if
28536 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28538 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28539 bool swap_operands)
28541 enum machine_mode mode = GET_MODE (op0);
28542 rtx mask = gen_reg_rtx (mode);
28551 if (mode == DFmode)
28552 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28553 gen_rtx_fmt_ee (code, mode, op0, op1)));
28555 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28556 gen_rtx_fmt_ee (code, mode, op0, op1)));
28561 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28562 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28564 ix86_gen_TWO52 (enum machine_mode mode)
28566 REAL_VALUE_TYPE TWO52r;
28569 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28570 TWO52 = const_double_from_real_value (TWO52r, mode);
28571 TWO52 = force_reg (mode, TWO52);
28576 /* Expand SSE sequence for computing lround from OP1 storing
28579 ix86_expand_lround (rtx op0, rtx op1)
28581 /* C code for the stuff we're doing below:
28582 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28585 enum machine_mode mode = GET_MODE (op1);
28586 const struct real_format *fmt;
28587 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28590 /* load nextafter (0.5, 0.0) */
28591 fmt = REAL_MODE_FORMAT (mode);
28592 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28593 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28595 /* adj = copysign (0.5, op1) */
28596 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28597 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28599 /* adj = op1 + adj */
28600 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28602 /* op0 = (imode)adj */
28603 expand_fix (op0, adj, 0);
28606 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28609 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28611 /* C code for the stuff we're doing below (for do_floor):
28613 xi -= (double)xi > op1 ? 1 : 0;
28616 enum machine_mode fmode = GET_MODE (op1);
28617 enum machine_mode imode = GET_MODE (op0);
28618 rtx ireg, freg, label, tmp;
28620 /* reg = (long)op1 */
28621 ireg = gen_reg_rtx (imode);
28622 expand_fix (ireg, op1, 0);
28624 /* freg = (double)reg */
28625 freg = gen_reg_rtx (fmode);
28626 expand_float (freg, ireg, 0);
28628 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28629 label = ix86_expand_sse_compare_and_jump (UNLE,
28630 freg, op1, !do_floor);
28631 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28632 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28633 emit_move_insn (ireg, tmp);
28635 emit_label (label);
28636 LABEL_NUSES (label) = 1;
28638 emit_move_insn (op0, ireg);
28641 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28642 result in OPERAND0. */
28644 ix86_expand_rint (rtx operand0, rtx operand1)
28646 /* C code for the stuff we're doing below:
28647 xa = fabs (operand1);
28648 if (!isless (xa, 2**52))
28650 xa = xa + 2**52 - 2**52;
28651 return copysign (xa, operand1);
28653 enum machine_mode mode = GET_MODE (operand0);
28654 rtx res, xa, label, TWO52, mask;
28656 res = gen_reg_rtx (mode);
28657 emit_move_insn (res, operand1);
28659 /* xa = abs (operand1) */
28660 xa = ix86_expand_sse_fabs (res, &mask);
28662 /* if (!isless (xa, TWO52)) goto label; */
28663 TWO52 = ix86_gen_TWO52 (mode);
28664 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28666 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28667 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28669 ix86_sse_copysign_to_positive (res, xa, res, mask);
28671 emit_label (label);
28672 LABEL_NUSES (label) = 1;
28674 emit_move_insn (operand0, res);
28677 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28680 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
28682 /* C code for the stuff we expand below.
28683 double xa = fabs (x), x2;
28684 if (!isless (xa, TWO52))
28686 xa = xa + TWO52 - TWO52;
28687 x2 = copysign (xa, x);
28696 enum machine_mode mode = GET_MODE (operand0);
28697 rtx xa, TWO52, tmp, label, one, res, mask;
28699 TWO52 = ix86_gen_TWO52 (mode);
28701 /* Temporary for holding the result, initialized to the input
28702 operand to ease control flow. */
28703 res = gen_reg_rtx (mode);
28704 emit_move_insn (res, operand1);
28706 /* xa = abs (operand1) */
28707 xa = ix86_expand_sse_fabs (res, &mask);
28709 /* if (!isless (xa, TWO52)) goto label; */
28710 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28712 /* xa = xa + TWO52 - TWO52; */
28713 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28714 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28716 /* xa = copysign (xa, operand1) */
28717 ix86_sse_copysign_to_positive (xa, xa, res, mask);
28719 /* generate 1.0 or -1.0 */
28720 one = force_reg (mode,
28721 const_double_from_real_value (do_floor
28722 ? dconst1 : dconstm1, mode));
28724 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28725 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28726 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28727 gen_rtx_AND (mode, one, tmp)));
28728 /* We always need to subtract here to preserve signed zero. */
28729 tmp = expand_simple_binop (mode, MINUS,
28730 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28731 emit_move_insn (res, tmp);
28733 emit_label (label);
28734 LABEL_NUSES (label) = 1;
28736 emit_move_insn (operand0, res);
28739 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28742 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
28744 /* C code for the stuff we expand below.
28745 double xa = fabs (x), x2;
28746 if (!isless (xa, TWO52))
28748 x2 = (double)(long)x;
28755 if (HONOR_SIGNED_ZEROS (mode))
28756 return copysign (x2, x);
28759 enum machine_mode mode = GET_MODE (operand0);
28760 rtx xa, xi, TWO52, tmp, label, one, res, mask;
28762 TWO52 = ix86_gen_TWO52 (mode);
28764 /* Temporary for holding the result, initialized to the input
28765 operand to ease control flow. */
28766 res = gen_reg_rtx (mode);
28767 emit_move_insn (res, operand1);
28769 /* xa = abs (operand1) */
28770 xa = ix86_expand_sse_fabs (res, &mask);
28772 /* if (!isless (xa, TWO52)) goto label; */
28773 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28775 /* xa = (double)(long)x */
28776 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28777 expand_fix (xi, res, 0);
28778 expand_float (xa, xi, 0);
28781 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28783 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28784 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28785 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28786 gen_rtx_AND (mode, one, tmp)));
28787 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
28788 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28789 emit_move_insn (res, tmp);
28791 if (HONOR_SIGNED_ZEROS (mode))
28792 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28794 emit_label (label);
28795 LABEL_NUSES (label) = 1;
28797 emit_move_insn (operand0, res);
28800 /* Expand SSE sequence for computing round from OPERAND1 storing
28801 into OPERAND0. Sequence that works without relying on DImode truncation
28802 via cvttsd2siq that is only available on 64bit targets. */
28804 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
28806 /* C code for the stuff we expand below.
28807 double xa = fabs (x), xa2, x2;
28808 if (!isless (xa, TWO52))
28810 Using the absolute value and copying back sign makes
28811 -0.0 -> -0.0 correct.
28812 xa2 = xa + TWO52 - TWO52;
28817 else if (dxa > 0.5)
28819 x2 = copysign (xa2, x);
28822 enum machine_mode mode = GET_MODE (operand0);
28823 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
28825 TWO52 = ix86_gen_TWO52 (mode);
28827 /* Temporary for holding the result, initialized to the input
28828 operand to ease control flow. */
28829 res = gen_reg_rtx (mode);
28830 emit_move_insn (res, operand1);
28832 /* xa = abs (operand1) */
28833 xa = ix86_expand_sse_fabs (res, &mask);
28835 /* if (!isless (xa, TWO52)) goto label; */
28836 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28838 /* xa2 = xa + TWO52 - TWO52; */
28839 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28840 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
28842 /* dxa = xa2 - xa; */
28843 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
28845 /* generate 0.5, 1.0 and -0.5 */
28846 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
28847 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
28848 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
28852 tmp = gen_reg_rtx (mode);
28853 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
28854 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
28855 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28856 gen_rtx_AND (mode, one, tmp)));
28857 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28858 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
28859 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
28860 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28861 gen_rtx_AND (mode, one, tmp)));
28862 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28864 /* res = copysign (xa2, operand1) */
28865 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
28867 emit_label (label);
28868 LABEL_NUSES (label) = 1;
28870 emit_move_insn (operand0, res);
28873 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28876 ix86_expand_trunc (rtx operand0, rtx operand1)
28878 /* C code for SSE variant we expand below.
28879 double xa = fabs (x), x2;
28880 if (!isless (xa, TWO52))
28882 x2 = (double)(long)x;
28883 if (HONOR_SIGNED_ZEROS (mode))
28884 return copysign (x2, x);
28887 enum machine_mode mode = GET_MODE (operand0);
28888 rtx xa, xi, TWO52, label, res, mask;
28890 TWO52 = ix86_gen_TWO52 (mode);
28892 /* Temporary for holding the result, initialized to the input
28893 operand to ease control flow. */
28894 res = gen_reg_rtx (mode);
28895 emit_move_insn (res, operand1);
28897 /* xa = abs (operand1) */
28898 xa = ix86_expand_sse_fabs (res, &mask);
28900 /* if (!isless (xa, TWO52)) goto label; */
28901 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28903 /* x = (double)(long)x */
28904 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28905 expand_fix (xi, res, 0);
28906 expand_float (res, xi, 0);
28908 if (HONOR_SIGNED_ZEROS (mode))
28909 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28911 emit_label (label);
28912 LABEL_NUSES (label) = 1;
28914 emit_move_insn (operand0, res);
28917 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28920 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
28922 enum machine_mode mode = GET_MODE (operand0);
28923 rtx xa, mask, TWO52, label, one, res, smask, tmp;
28925 /* C code for SSE variant we expand below.
28926 double xa = fabs (x), x2;
28927 if (!isless (xa, TWO52))
28929 xa2 = xa + TWO52 - TWO52;
28933 x2 = copysign (xa2, x);
28937 TWO52 = ix86_gen_TWO52 (mode);
28939 /* Temporary for holding the result, initialized to the input
28940 operand to ease control flow. */
28941 res = gen_reg_rtx (mode);
28942 emit_move_insn (res, operand1);
28944 /* xa = abs (operand1) */
28945 xa = ix86_expand_sse_fabs (res, &smask);
28947 /* if (!isless (xa, TWO52)) goto label; */
28948 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28950 /* res = xa + TWO52 - TWO52; */
28951 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28952 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
28953 emit_move_insn (res, tmp);
28956 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28958 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
28959 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
28960 emit_insn (gen_rtx_SET (VOIDmode, mask,
28961 gen_rtx_AND (mode, mask, one)));
28962 tmp = expand_simple_binop (mode, MINUS,
28963 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
28964 emit_move_insn (res, tmp);
28966 /* res = copysign (res, operand1) */
28967 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
28969 emit_label (label);
28970 LABEL_NUSES (label) = 1;
28972 emit_move_insn (operand0, res);
28975 /* Expand SSE sequence for computing round from OPERAND1 storing
28978 ix86_expand_round (rtx operand0, rtx operand1)
28980 /* C code for the stuff we're doing below:
28981 double xa = fabs (x);
28982 if (!isless (xa, TWO52))
28984 xa = (double)(long)(xa + nextafter (0.5, 0.0));
28985 return copysign (xa, x);
28987 enum machine_mode mode = GET_MODE (operand0);
28988 rtx res, TWO52, xa, label, xi, half, mask;
28989 const struct real_format *fmt;
28990 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28992 /* Temporary for holding the result, initialized to the input
28993 operand to ease control flow. */
28994 res = gen_reg_rtx (mode);
28995 emit_move_insn (res, operand1);
28997 TWO52 = ix86_gen_TWO52 (mode);
28998 xa = ix86_expand_sse_fabs (res, &mask);
28999 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29001 /* load nextafter (0.5, 0.0) */
29002 fmt = REAL_MODE_FORMAT (mode);
29003 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29004 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29006 /* xa = xa + 0.5 */
29007 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29008 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29010 /* xa = (double)(int64_t)xa */
29011 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29012 expand_fix (xi, xa, 0);
29013 expand_float (xa, xi, 0);
29015 /* res = copysign (xa, operand1) */
29016 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29018 emit_label (label);
29019 LABEL_NUSES (label) = 1;
29021 emit_move_insn (operand0, res);
29024 /* Table of valid machine attributes. */
29025 static const struct attribute_spec ix86_attribute_table[] =
29027 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29028 /* Stdcall attribute says callee is responsible for popping arguments
29029 if they are not variable. */
29030 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29031 /* Fastcall attribute says callee is responsible for popping arguments
29032 if they are not variable. */
29033 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29034 /* Cdecl attribute says the callee is a normal C declaration */
29035 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29036 /* Regparm attribute specifies how many integer arguments are to be
29037 passed in registers. */
29038 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29039 /* Sseregparm attribute says we are using x86_64 calling conventions
29040 for FP arguments. */
29041 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29042 /* force_align_arg_pointer says this function realigns the stack at entry. */
29043 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29044 false, true, true, ix86_handle_cconv_attribute },
29045 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29046 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29047 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29048 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29050 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29051 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29052 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29053 SUBTARGET_ATTRIBUTE_TABLE,
29055 /* ms_abi and sysv_abi calling convention function attributes. */
29056 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29057 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29059 { NULL, 0, 0, false, false, false, NULL }
29062 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29064 x86_builtin_vectorization_cost (bool runtime_test)
29066 /* If the branch of the runtime test is taken - i.e. - the vectorized
29067 version is skipped - this incurs a misprediction cost (because the
29068 vectorized version is expected to be the fall-through). So we subtract
29069 the latency of a mispredicted branch from the costs that are incured
29070 when the vectorized version is executed.
29072 TODO: The values in individual target tables have to be tuned or new
29073 fields may be needed. For eg. on K8, the default branch path is the
29074 not-taken path. If the taken path is predicted correctly, the minimum
29075 penalty of going down the taken-path is 1 cycle. If the taken-path is
29076 not predicted correctly, then the minimum penalty is 10 cycles. */
29080 return (-(ix86_cost->cond_taken_branch_cost));
29086 /* This function returns the calling abi specific va_list type node.
29087 It returns the FNDECL specific va_list type. */
29090 ix86_fn_abi_va_list (tree fndecl)
29093 return va_list_type_node;
29094 gcc_assert (fndecl != NULL_TREE);
29096 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
29097 return ms_va_list_type_node;
29099 return sysv_va_list_type_node;
29102 /* Returns the canonical va_list type specified by TYPE. If there
29103 is no valid TYPE provided, it return NULL_TREE. */
29106 ix86_canonical_va_list_type (tree type)
29110 /* Resolve references and pointers to va_list type. */
29111 if (INDIRECT_REF_P (type))
29112 type = TREE_TYPE (type);
29113 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29114 type = TREE_TYPE (type);
29118 wtype = va_list_type_node;
29119 gcc_assert (wtype != NULL_TREE);
29121 if (TREE_CODE (wtype) == ARRAY_TYPE)
29123 /* If va_list is an array type, the argument may have decayed
29124 to a pointer type, e.g. by being passed to another function.
29125 In that case, unwrap both types so that we can compare the
29126 underlying records. */
29127 if (TREE_CODE (htype) == ARRAY_TYPE
29128 || POINTER_TYPE_P (htype))
29130 wtype = TREE_TYPE (wtype);
29131 htype = TREE_TYPE (htype);
29134 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29135 return va_list_type_node;
29136 wtype = sysv_va_list_type_node;
29137 gcc_assert (wtype != NULL_TREE);
29139 if (TREE_CODE (wtype) == ARRAY_TYPE)
29141 /* If va_list is an array type, the argument may have decayed
29142 to a pointer type, e.g. by being passed to another function.
29143 In that case, unwrap both types so that we can compare the
29144 underlying records. */
29145 if (TREE_CODE (htype) == ARRAY_TYPE
29146 || POINTER_TYPE_P (htype))
29148 wtype = TREE_TYPE (wtype);
29149 htype = TREE_TYPE (htype);
29152 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29153 return sysv_va_list_type_node;
29154 wtype = ms_va_list_type_node;
29155 gcc_assert (wtype != NULL_TREE);
29157 if (TREE_CODE (wtype) == ARRAY_TYPE)
29159 /* If va_list is an array type, the argument may have decayed
29160 to a pointer type, e.g. by being passed to another function.
29161 In that case, unwrap both types so that we can compare the
29162 underlying records. */
29163 if (TREE_CODE (htype) == ARRAY_TYPE
29164 || POINTER_TYPE_P (htype))
29166 wtype = TREE_TYPE (wtype);
29167 htype = TREE_TYPE (htype);
29170 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29171 return ms_va_list_type_node;
29174 return std_canonical_va_list_type (type);
29177 /* Iterate through the target-specific builtin types for va_list.
29178 IDX denotes the iterator, *PTREE is set to the result type of
29179 the va_list builtin, and *PNAME to its internal type.
29180 Returns zero if there is no element for this index, otherwise
29181 IDX should be increased upon the next call.
29182 Note, do not iterate a base builtin's name like __builtin_va_list.
29183 Used from c_common_nodes_and_builtins. */
29186 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29192 *ptree = ms_va_list_type_node;
29193 *pname = "__builtin_ms_va_list";
29196 *ptree = sysv_va_list_type_node;
29197 *pname = "__builtin_sysv_va_list";
29205 /* Initialize the GCC target structure. */
29206 #undef TARGET_RETURN_IN_MEMORY
29207 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29209 #undef TARGET_LEGITIMIZE_ADDRESS
29210 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
29212 #undef TARGET_ATTRIBUTE_TABLE
29213 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29214 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29215 # undef TARGET_MERGE_DECL_ATTRIBUTES
29216 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29219 #undef TARGET_COMP_TYPE_ATTRIBUTES
29220 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29222 #undef TARGET_INIT_BUILTINS
29223 #define TARGET_INIT_BUILTINS ix86_init_builtins
29224 #undef TARGET_EXPAND_BUILTIN
29225 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29227 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29228 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29229 ix86_builtin_vectorized_function
29231 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29232 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29234 #undef TARGET_BUILTIN_RECIPROCAL
29235 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29237 #undef TARGET_ASM_FUNCTION_EPILOGUE
29238 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29240 #undef TARGET_ENCODE_SECTION_INFO
29241 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29242 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29244 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29247 #undef TARGET_ASM_OPEN_PAREN
29248 #define TARGET_ASM_OPEN_PAREN ""
29249 #undef TARGET_ASM_CLOSE_PAREN
29250 #define TARGET_ASM_CLOSE_PAREN ""
29252 #undef TARGET_ASM_BYTE_OP
29253 #define TARGET_ASM_BYTE_OP ASM_BYTE
29255 #undef TARGET_ASM_ALIGNED_HI_OP
29256 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29257 #undef TARGET_ASM_ALIGNED_SI_OP
29258 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29260 #undef TARGET_ASM_ALIGNED_DI_OP
29261 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29264 #undef TARGET_ASM_UNALIGNED_HI_OP
29265 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29266 #undef TARGET_ASM_UNALIGNED_SI_OP
29267 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29268 #undef TARGET_ASM_UNALIGNED_DI_OP
29269 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29271 #undef TARGET_SCHED_ADJUST_COST
29272 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29273 #undef TARGET_SCHED_ISSUE_RATE
29274 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29275 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29276 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29277 ia32_multipass_dfa_lookahead
29279 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29280 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29283 #undef TARGET_HAVE_TLS
29284 #define TARGET_HAVE_TLS true
29286 #undef TARGET_CANNOT_FORCE_CONST_MEM
29287 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29288 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29289 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29291 #undef TARGET_DELEGITIMIZE_ADDRESS
29292 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29294 #undef TARGET_MS_BITFIELD_LAYOUT_P
29295 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29298 #undef TARGET_BINDS_LOCAL_P
29299 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29301 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29302 #undef TARGET_BINDS_LOCAL_P
29303 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29306 #undef TARGET_ASM_OUTPUT_MI_THUNK
29307 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29308 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29309 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29311 #undef TARGET_ASM_FILE_START
29312 #define TARGET_ASM_FILE_START x86_file_start
29314 #undef TARGET_DEFAULT_TARGET_FLAGS
29315 #define TARGET_DEFAULT_TARGET_FLAGS \
29317 | TARGET_SUBTARGET_DEFAULT \
29318 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29320 #undef TARGET_HANDLE_OPTION
29321 #define TARGET_HANDLE_OPTION ix86_handle_option
29323 #undef TARGET_RTX_COSTS
29324 #define TARGET_RTX_COSTS ix86_rtx_costs
29325 #undef TARGET_ADDRESS_COST
29326 #define TARGET_ADDRESS_COST ix86_address_cost
29328 #undef TARGET_FIXED_CONDITION_CODE_REGS
29329 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29330 #undef TARGET_CC_MODES_COMPATIBLE
29331 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29333 #undef TARGET_MACHINE_DEPENDENT_REORG
29334 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29336 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29337 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29339 #undef TARGET_BUILD_BUILTIN_VA_LIST
29340 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29342 #undef TARGET_FN_ABI_VA_LIST
29343 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29345 #undef TARGET_CANONICAL_VA_LIST_TYPE
29346 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29348 #undef TARGET_EXPAND_BUILTIN_VA_START
29349 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29351 #undef TARGET_MD_ASM_CLOBBERS
29352 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29354 #undef TARGET_PROMOTE_PROTOTYPES
29355 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29356 #undef TARGET_STRUCT_VALUE_RTX
29357 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29358 #undef TARGET_SETUP_INCOMING_VARARGS
29359 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29360 #undef TARGET_MUST_PASS_IN_STACK
29361 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29362 #undef TARGET_PASS_BY_REFERENCE
29363 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29364 #undef TARGET_INTERNAL_ARG_POINTER
29365 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29366 #undef TARGET_UPDATE_STACK_BOUNDARY
29367 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29368 #undef TARGET_GET_DRAP_RTX
29369 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29370 #undef TARGET_STRICT_ARGUMENT_NAMING
29371 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29372 #undef TARGET_STATIC_CHAIN
29373 #define TARGET_STATIC_CHAIN ix86_static_chain
29374 #undef TARGET_TRAMPOLINE_INIT
29375 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
29377 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29378 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29380 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29381 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29383 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29384 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29386 #undef TARGET_C_MODE_FOR_SUFFIX
29387 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29390 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29391 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29394 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29395 #undef TARGET_INSERT_ATTRIBUTES
29396 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29399 #undef TARGET_MANGLE_TYPE
29400 #define TARGET_MANGLE_TYPE ix86_mangle_type
29402 #undef TARGET_STACK_PROTECT_FAIL
29403 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29405 #undef TARGET_FUNCTION_VALUE
29406 #define TARGET_FUNCTION_VALUE ix86_function_value
29408 #undef TARGET_SECONDARY_RELOAD
29409 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29411 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29412 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29414 #undef TARGET_SET_CURRENT_FUNCTION
29415 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29417 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29418 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29420 #undef TARGET_OPTION_SAVE
29421 #define TARGET_OPTION_SAVE ix86_function_specific_save
29423 #undef TARGET_OPTION_RESTORE
29424 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29426 #undef TARGET_OPTION_PRINT
29427 #define TARGET_OPTION_PRINT ix86_function_specific_print
29429 #undef TARGET_CAN_INLINE_P
29430 #define TARGET_CAN_INLINE_P ix86_can_inline_p
29432 #undef TARGET_EXPAND_TO_RTL_HOOK
29433 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29435 #undef TARGET_LEGITIMATE_ADDRESS_P
29436 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
29438 #undef TARGET_IRA_COVER_CLASSES
29439 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
29441 #undef TARGET_FRAME_POINTER_REQUIRED
29442 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
29444 #undef TARGET_CAN_ELIMINATE
29445 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
29447 struct gcc_target targetm = TARGET_INITIALIZER;
29449 #include "gt-i386.h"