1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
47 #include "target-def.h"
48 #include "langhooks.h"
53 #include "tm-constrs.h"
57 static int x86_builtin_vectorization_cost (bool);
58 static rtx legitimize_dllimport_symbol (rtx, bool);
60 #ifndef CHECK_STACK_LIMIT
61 #define CHECK_STACK_LIMIT (-1)
64 /* Return index of given mode in mult and division cost tables. */
65 #define MODE_INDEX(mode) \
66 ((mode) == QImode ? 0 \
67 : (mode) == HImode ? 1 \
68 : (mode) == SImode ? 2 \
69 : (mode) == DImode ? 3 \
72 /* Processor costs (relative to an add) */
73 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
74 #define COSTS_N_BYTES(N) ((N) * 2)
76 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
79 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
80 COSTS_N_BYTES (2), /* cost of an add instruction */
81 COSTS_N_BYTES (3), /* cost of a lea instruction */
82 COSTS_N_BYTES (2), /* variable shift costs */
83 COSTS_N_BYTES (3), /* constant shift costs */
84 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
85 COSTS_N_BYTES (3), /* HI */
86 COSTS_N_BYTES (3), /* SI */
87 COSTS_N_BYTES (3), /* DI */
88 COSTS_N_BYTES (5)}, /* other */
89 0, /* cost of multiply per each bit set */
90 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
91 COSTS_N_BYTES (3), /* HI */
92 COSTS_N_BYTES (3), /* SI */
93 COSTS_N_BYTES (3), /* DI */
94 COSTS_N_BYTES (5)}, /* other */
95 COSTS_N_BYTES (3), /* cost of movsx */
96 COSTS_N_BYTES (3), /* cost of movzx */
99 2, /* cost for loading QImode using movzbl */
100 {2, 2, 2}, /* cost of loading integer registers
101 in QImode, HImode and SImode.
102 Relative to reg-reg move (2). */
103 {2, 2, 2}, /* cost of storing integer registers */
104 2, /* cost of reg,reg fld/fst */
105 {2, 2, 2}, /* cost of loading fp registers
106 in SFmode, DFmode and XFmode */
107 {2, 2, 2}, /* cost of storing fp registers
108 in SFmode, DFmode and XFmode */
109 3, /* cost of moving MMX register */
110 {3, 3}, /* cost of loading MMX registers
111 in SImode and DImode */
112 {3, 3}, /* cost of storing MMX registers
113 in SImode and DImode */
114 3, /* cost of moving SSE register */
115 {3, 3, 3}, /* cost of loading SSE registers
116 in SImode, DImode and TImode */
117 {3, 3, 3}, /* cost of storing SSE registers
118 in SImode, DImode and TImode */
119 3, /* MMX or SSE register to integer */
120 0, /* size of l1 cache */
121 0, /* size of l2 cache */
122 0, /* size of prefetch block */
123 0, /* number of parallel prefetches */
125 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
126 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
127 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
128 COSTS_N_BYTES (2), /* cost of FABS instruction. */
129 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
130 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
131 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
132 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
133 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
134 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
135 1, /* scalar_stmt_cost. */
136 1, /* scalar load_cost. */
137 1, /* scalar_store_cost. */
138 1, /* vec_stmt_cost. */
139 1, /* vec_to_scalar_cost. */
140 1, /* scalar_to_vec_cost. */
141 1, /* vec_align_load_cost. */
142 1, /* vec_unalign_load_cost. */
143 1, /* vec_store_cost. */
144 1, /* cond_taken_branch_cost. */
145 1, /* cond_not_taken_branch_cost. */
148 /* Processor costs (relative to an add) */
150 struct processor_costs i386_cost = { /* 386 specific costs */
151 COSTS_N_INSNS (1), /* cost of an add instruction */
152 COSTS_N_INSNS (1), /* cost of a lea instruction */
153 COSTS_N_INSNS (3), /* variable shift costs */
154 COSTS_N_INSNS (2), /* constant shift costs */
155 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
156 COSTS_N_INSNS (6), /* HI */
157 COSTS_N_INSNS (6), /* SI */
158 COSTS_N_INSNS (6), /* DI */
159 COSTS_N_INSNS (6)}, /* other */
160 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
161 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
162 COSTS_N_INSNS (23), /* HI */
163 COSTS_N_INSNS (23), /* SI */
164 COSTS_N_INSNS (23), /* DI */
165 COSTS_N_INSNS (23)}, /* other */
166 COSTS_N_INSNS (3), /* cost of movsx */
167 COSTS_N_INSNS (2), /* cost of movzx */
168 15, /* "large" insn */
170 4, /* cost for loading QImode using movzbl */
171 {2, 4, 2}, /* cost of loading integer registers
172 in QImode, HImode and SImode.
173 Relative to reg-reg move (2). */
174 {2, 4, 2}, /* cost of storing integer registers */
175 2, /* cost of reg,reg fld/fst */
176 {8, 8, 8}, /* cost of loading fp registers
177 in SFmode, DFmode and XFmode */
178 {8, 8, 8}, /* cost of storing fp registers
179 in SFmode, DFmode and XFmode */
180 2, /* cost of moving MMX register */
181 {4, 8}, /* cost of loading MMX registers
182 in SImode and DImode */
183 {4, 8}, /* cost of storing MMX registers
184 in SImode and DImode */
185 2, /* cost of moving SSE register */
186 {4, 8, 16}, /* cost of loading SSE registers
187 in SImode, DImode and TImode */
188 {4, 8, 16}, /* cost of storing SSE registers
189 in SImode, DImode and TImode */
190 3, /* MMX or SSE register to integer */
191 0, /* size of l1 cache */
192 0, /* size of l2 cache */
193 0, /* size of prefetch block */
194 0, /* number of parallel prefetches */
196 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
197 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
198 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
199 COSTS_N_INSNS (22), /* cost of FABS instruction. */
200 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
201 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
202 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
203 DUMMY_STRINGOP_ALGS},
204 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
205 DUMMY_STRINGOP_ALGS},
206 1, /* scalar_stmt_cost. */
207 1, /* scalar load_cost. */
208 1, /* scalar_store_cost. */
209 1, /* vec_stmt_cost. */
210 1, /* vec_to_scalar_cost. */
211 1, /* scalar_to_vec_cost. */
212 1, /* vec_align_load_cost. */
213 2, /* vec_unalign_load_cost. */
214 1, /* vec_store_cost. */
215 3, /* cond_taken_branch_cost. */
216 1, /* cond_not_taken_branch_cost. */
220 struct processor_costs i486_cost = { /* 486 specific costs */
221 COSTS_N_INSNS (1), /* cost of an add instruction */
222 COSTS_N_INSNS (1), /* cost of a lea instruction */
223 COSTS_N_INSNS (3), /* variable shift costs */
224 COSTS_N_INSNS (2), /* constant shift costs */
225 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
226 COSTS_N_INSNS (12), /* HI */
227 COSTS_N_INSNS (12), /* SI */
228 COSTS_N_INSNS (12), /* DI */
229 COSTS_N_INSNS (12)}, /* other */
230 1, /* cost of multiply per each bit set */
231 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
232 COSTS_N_INSNS (40), /* HI */
233 COSTS_N_INSNS (40), /* SI */
234 COSTS_N_INSNS (40), /* DI */
235 COSTS_N_INSNS (40)}, /* other */
236 COSTS_N_INSNS (3), /* cost of movsx */
237 COSTS_N_INSNS (2), /* cost of movzx */
238 15, /* "large" insn */
240 4, /* cost for loading QImode using movzbl */
241 {2, 4, 2}, /* cost of loading integer registers
242 in QImode, HImode and SImode.
243 Relative to reg-reg move (2). */
244 {2, 4, 2}, /* cost of storing integer registers */
245 2, /* cost of reg,reg fld/fst */
246 {8, 8, 8}, /* cost of loading fp registers
247 in SFmode, DFmode and XFmode */
248 {8, 8, 8}, /* cost of storing fp registers
249 in SFmode, DFmode and XFmode */
250 2, /* cost of moving MMX register */
251 {4, 8}, /* cost of loading MMX registers
252 in SImode and DImode */
253 {4, 8}, /* cost of storing MMX registers
254 in SImode and DImode */
255 2, /* cost of moving SSE register */
256 {4, 8, 16}, /* cost of loading SSE registers
257 in SImode, DImode and TImode */
258 {4, 8, 16}, /* cost of storing SSE registers
259 in SImode, DImode and TImode */
260 3, /* MMX or SSE register to integer */
261 4, /* size of l1 cache. 486 has 8kB cache
262 shared for code and data, so 4kB is
263 not really precise. */
264 4, /* size of l2 cache */
265 0, /* size of prefetch block */
266 0, /* number of parallel prefetches */
268 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
269 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
270 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
271 COSTS_N_INSNS (3), /* cost of FABS instruction. */
272 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
273 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
274 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
275 DUMMY_STRINGOP_ALGS},
276 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
277 DUMMY_STRINGOP_ALGS},
278 1, /* scalar_stmt_cost. */
279 1, /* scalar load_cost. */
280 1, /* scalar_store_cost. */
281 1, /* vec_stmt_cost. */
282 1, /* vec_to_scalar_cost. */
283 1, /* scalar_to_vec_cost. */
284 1, /* vec_align_load_cost. */
285 2, /* vec_unalign_load_cost. */
286 1, /* vec_store_cost. */
287 3, /* cond_taken_branch_cost. */
288 1, /* cond_not_taken_branch_cost. */
292 struct processor_costs pentium_cost = {
293 COSTS_N_INSNS (1), /* cost of an add instruction */
294 COSTS_N_INSNS (1), /* cost of a lea instruction */
295 COSTS_N_INSNS (4), /* variable shift costs */
296 COSTS_N_INSNS (1), /* constant shift costs */
297 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
298 COSTS_N_INSNS (11), /* HI */
299 COSTS_N_INSNS (11), /* SI */
300 COSTS_N_INSNS (11), /* DI */
301 COSTS_N_INSNS (11)}, /* other */
302 0, /* cost of multiply per each bit set */
303 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
304 COSTS_N_INSNS (25), /* HI */
305 COSTS_N_INSNS (25), /* SI */
306 COSTS_N_INSNS (25), /* DI */
307 COSTS_N_INSNS (25)}, /* other */
308 COSTS_N_INSNS (3), /* cost of movsx */
309 COSTS_N_INSNS (2), /* cost of movzx */
310 8, /* "large" insn */
312 6, /* cost for loading QImode using movzbl */
313 {2, 4, 2}, /* cost of loading integer registers
314 in QImode, HImode and SImode.
315 Relative to reg-reg move (2). */
316 {2, 4, 2}, /* cost of storing integer registers */
317 2, /* cost of reg,reg fld/fst */
318 {2, 2, 6}, /* cost of loading fp registers
319 in SFmode, DFmode and XFmode */
320 {4, 4, 6}, /* cost of storing fp registers
321 in SFmode, DFmode and XFmode */
322 8, /* cost of moving MMX register */
323 {8, 8}, /* cost of loading MMX registers
324 in SImode and DImode */
325 {8, 8}, /* cost of storing MMX registers
326 in SImode and DImode */
327 2, /* cost of moving SSE register */
328 {4, 8, 16}, /* cost of loading SSE registers
329 in SImode, DImode and TImode */
330 {4, 8, 16}, /* cost of storing SSE registers
331 in SImode, DImode and TImode */
332 3, /* MMX or SSE register to integer */
333 8, /* size of l1 cache. */
334 8, /* size of l2 cache */
335 0, /* size of prefetch block */
336 0, /* number of parallel prefetches */
338 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
339 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
340 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
341 COSTS_N_INSNS (1), /* cost of FABS instruction. */
342 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
343 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
344 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
345 DUMMY_STRINGOP_ALGS},
346 {{libcall, {{-1, rep_prefix_4_byte}}},
347 DUMMY_STRINGOP_ALGS},
348 1, /* scalar_stmt_cost. */
349 1, /* scalar load_cost. */
350 1, /* scalar_store_cost. */
351 1, /* vec_stmt_cost. */
352 1, /* vec_to_scalar_cost. */
353 1, /* scalar_to_vec_cost. */
354 1, /* vec_align_load_cost. */
355 2, /* vec_unalign_load_cost. */
356 1, /* vec_store_cost. */
357 3, /* cond_taken_branch_cost. */
358 1, /* cond_not_taken_branch_cost. */
362 struct processor_costs pentiumpro_cost = {
363 COSTS_N_INSNS (1), /* cost of an add instruction */
364 COSTS_N_INSNS (1), /* cost of a lea instruction */
365 COSTS_N_INSNS (1), /* variable shift costs */
366 COSTS_N_INSNS (1), /* constant shift costs */
367 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
368 COSTS_N_INSNS (4), /* HI */
369 COSTS_N_INSNS (4), /* SI */
370 COSTS_N_INSNS (4), /* DI */
371 COSTS_N_INSNS (4)}, /* other */
372 0, /* cost of multiply per each bit set */
373 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
374 COSTS_N_INSNS (17), /* HI */
375 COSTS_N_INSNS (17), /* SI */
376 COSTS_N_INSNS (17), /* DI */
377 COSTS_N_INSNS (17)}, /* other */
378 COSTS_N_INSNS (1), /* cost of movsx */
379 COSTS_N_INSNS (1), /* cost of movzx */
380 8, /* "large" insn */
382 2, /* cost for loading QImode using movzbl */
383 {4, 4, 4}, /* cost of loading integer registers
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
386 {2, 2, 2}, /* cost of storing integer registers */
387 2, /* cost of reg,reg fld/fst */
388 {2, 2, 6}, /* cost of loading fp registers
389 in SFmode, DFmode and XFmode */
390 {4, 4, 6}, /* cost of storing fp registers
391 in SFmode, DFmode and XFmode */
392 2, /* cost of moving MMX register */
393 {2, 2}, /* cost of loading MMX registers
394 in SImode and DImode */
395 {2, 2}, /* cost of storing MMX registers
396 in SImode and DImode */
397 2, /* cost of moving SSE register */
398 {2, 2, 8}, /* cost of loading SSE registers
399 in SImode, DImode and TImode */
400 {2, 2, 8}, /* cost of storing SSE registers
401 in SImode, DImode and TImode */
402 3, /* MMX or SSE register to integer */
403 8, /* size of l1 cache. */
404 256, /* size of l2 cache */
405 32, /* size of prefetch block */
406 6, /* number of parallel prefetches */
408 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
409 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
410 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
411 COSTS_N_INSNS (2), /* cost of FABS instruction. */
412 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
413 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
414 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
415 the alignment). For small blocks inline loop is still a noticeable win, for bigger
416 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
417 more expensive startup time in CPU, but after 4K the difference is down in the noise.
419 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
420 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
421 DUMMY_STRINGOP_ALGS},
422 {{rep_prefix_4_byte, {{1024, unrolled_loop},
423 {8192, rep_prefix_4_byte}, {-1, libcall}}},
424 DUMMY_STRINGOP_ALGS},
425 1, /* scalar_stmt_cost. */
426 1, /* scalar load_cost. */
427 1, /* scalar_store_cost. */
428 1, /* vec_stmt_cost. */
429 1, /* vec_to_scalar_cost. */
430 1, /* scalar_to_vec_cost. */
431 1, /* vec_align_load_cost. */
432 2, /* vec_unalign_load_cost. */
433 1, /* vec_store_cost. */
434 3, /* cond_taken_branch_cost. */
435 1, /* cond_not_taken_branch_cost. */
439 struct processor_costs geode_cost = {
440 COSTS_N_INSNS (1), /* cost of an add instruction */
441 COSTS_N_INSNS (1), /* cost of a lea instruction */
442 COSTS_N_INSNS (2), /* variable shift costs */
443 COSTS_N_INSNS (1), /* constant shift costs */
444 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
445 COSTS_N_INSNS (4), /* HI */
446 COSTS_N_INSNS (7), /* SI */
447 COSTS_N_INSNS (7), /* DI */
448 COSTS_N_INSNS (7)}, /* other */
449 0, /* cost of multiply per each bit set */
450 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
451 COSTS_N_INSNS (23), /* HI */
452 COSTS_N_INSNS (39), /* SI */
453 COSTS_N_INSNS (39), /* DI */
454 COSTS_N_INSNS (39)}, /* other */
455 COSTS_N_INSNS (1), /* cost of movsx */
456 COSTS_N_INSNS (1), /* cost of movzx */
457 8, /* "large" insn */
459 1, /* cost for loading QImode using movzbl */
460 {1, 1, 1}, /* cost of loading integer registers
461 in QImode, HImode and SImode.
462 Relative to reg-reg move (2). */
463 {1, 1, 1}, /* cost of storing integer registers */
464 1, /* cost of reg,reg fld/fst */
465 {1, 1, 1}, /* cost of loading fp registers
466 in SFmode, DFmode and XFmode */
467 {4, 6, 6}, /* cost of storing fp registers
468 in SFmode, DFmode and XFmode */
470 1, /* cost of moving MMX register */
471 {1, 1}, /* cost of loading MMX registers
472 in SImode and DImode */
473 {1, 1}, /* cost of storing MMX registers
474 in SImode and DImode */
475 1, /* cost of moving SSE register */
476 {1, 1, 1}, /* cost of loading SSE registers
477 in SImode, DImode and TImode */
478 {1, 1, 1}, /* cost of storing SSE registers
479 in SImode, DImode and TImode */
480 1, /* MMX or SSE register to integer */
481 64, /* size of l1 cache. */
482 128, /* size of l2 cache. */
483 32, /* size of prefetch block */
484 1, /* number of parallel prefetches */
486 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
487 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
488 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
489 COSTS_N_INSNS (1), /* cost of FABS instruction. */
490 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
491 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
492 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
493 DUMMY_STRINGOP_ALGS},
494 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
495 DUMMY_STRINGOP_ALGS},
496 1, /* scalar_stmt_cost. */
497 1, /* scalar load_cost. */
498 1, /* scalar_store_cost. */
499 1, /* vec_stmt_cost. */
500 1, /* vec_to_scalar_cost. */
501 1, /* scalar_to_vec_cost. */
502 1, /* vec_align_load_cost. */
503 2, /* vec_unalign_load_cost. */
504 1, /* vec_store_cost. */
505 3, /* cond_taken_branch_cost. */
506 1, /* cond_not_taken_branch_cost. */
510 struct processor_costs k6_cost = {
511 COSTS_N_INSNS (1), /* cost of an add instruction */
512 COSTS_N_INSNS (2), /* cost of a lea instruction */
513 COSTS_N_INSNS (1), /* variable shift costs */
514 COSTS_N_INSNS (1), /* constant shift costs */
515 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
516 COSTS_N_INSNS (3), /* HI */
517 COSTS_N_INSNS (3), /* SI */
518 COSTS_N_INSNS (3), /* DI */
519 COSTS_N_INSNS (3)}, /* other */
520 0, /* cost of multiply per each bit set */
521 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
522 COSTS_N_INSNS (18), /* HI */
523 COSTS_N_INSNS (18), /* SI */
524 COSTS_N_INSNS (18), /* DI */
525 COSTS_N_INSNS (18)}, /* other */
526 COSTS_N_INSNS (2), /* cost of movsx */
527 COSTS_N_INSNS (2), /* cost of movzx */
528 8, /* "large" insn */
530 3, /* cost for loading QImode using movzbl */
531 {4, 5, 4}, /* cost of loading integer registers
532 in QImode, HImode and SImode.
533 Relative to reg-reg move (2). */
534 {2, 3, 2}, /* cost of storing integer registers */
535 4, /* cost of reg,reg fld/fst */
536 {6, 6, 6}, /* cost of loading fp registers
537 in SFmode, DFmode and XFmode */
538 {4, 4, 4}, /* cost of storing fp registers
539 in SFmode, DFmode and XFmode */
540 2, /* cost of moving MMX register */
541 {2, 2}, /* cost of loading MMX registers
542 in SImode and DImode */
543 {2, 2}, /* cost of storing MMX registers
544 in SImode and DImode */
545 2, /* cost of moving SSE register */
546 {2, 2, 8}, /* cost of loading SSE registers
547 in SImode, DImode and TImode */
548 {2, 2, 8}, /* cost of storing SSE registers
549 in SImode, DImode and TImode */
550 6, /* MMX or SSE register to integer */
551 32, /* size of l1 cache. */
552 32, /* size of l2 cache. Some models
553 have integrated l2 cache, but
554 optimizing for k6 is not important
555 enough to worry about that. */
556 32, /* size of prefetch block */
557 1, /* number of parallel prefetches */
559 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
560 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
561 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
562 COSTS_N_INSNS (2), /* cost of FABS instruction. */
563 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
564 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
565 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
566 DUMMY_STRINGOP_ALGS},
567 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
568 DUMMY_STRINGOP_ALGS},
569 1, /* scalar_stmt_cost. */
570 1, /* scalar load_cost. */
571 1, /* scalar_store_cost. */
572 1, /* vec_stmt_cost. */
573 1, /* vec_to_scalar_cost. */
574 1, /* scalar_to_vec_cost. */
575 1, /* vec_align_load_cost. */
576 2, /* vec_unalign_load_cost. */
577 1, /* vec_store_cost. */
578 3, /* cond_taken_branch_cost. */
579 1, /* cond_not_taken_branch_cost. */
583 struct processor_costs athlon_cost = {
584 COSTS_N_INSNS (1), /* cost of an add instruction */
585 COSTS_N_INSNS (2), /* cost of a lea instruction */
586 COSTS_N_INSNS (1), /* variable shift costs */
587 COSTS_N_INSNS (1), /* constant shift costs */
588 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
589 COSTS_N_INSNS (5), /* HI */
590 COSTS_N_INSNS (5), /* SI */
591 COSTS_N_INSNS (5), /* DI */
592 COSTS_N_INSNS (5)}, /* other */
593 0, /* cost of multiply per each bit set */
594 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
595 COSTS_N_INSNS (26), /* HI */
596 COSTS_N_INSNS (42), /* SI */
597 COSTS_N_INSNS (74), /* DI */
598 COSTS_N_INSNS (74)}, /* other */
599 COSTS_N_INSNS (1), /* cost of movsx */
600 COSTS_N_INSNS (1), /* cost of movzx */
601 8, /* "large" insn */
603 4, /* cost for loading QImode using movzbl */
604 {3, 4, 3}, /* cost of loading integer registers
605 in QImode, HImode and SImode.
606 Relative to reg-reg move (2). */
607 {3, 4, 3}, /* cost of storing integer registers */
608 4, /* cost of reg,reg fld/fst */
609 {4, 4, 12}, /* cost of loading fp registers
610 in SFmode, DFmode and XFmode */
611 {6, 6, 8}, /* cost of storing fp registers
612 in SFmode, DFmode and XFmode */
613 2, /* cost of moving MMX register */
614 {4, 4}, /* cost of loading MMX registers
615 in SImode and DImode */
616 {4, 4}, /* cost of storing MMX registers
617 in SImode and DImode */
618 2, /* cost of moving SSE register */
619 {4, 4, 6}, /* cost of loading SSE registers
620 in SImode, DImode and TImode */
621 {4, 4, 5}, /* cost of storing SSE registers
622 in SImode, DImode and TImode */
623 5, /* MMX or SSE register to integer */
624 64, /* size of l1 cache. */
625 256, /* size of l2 cache. */
626 64, /* size of prefetch block */
627 6, /* number of parallel prefetches */
629 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
630 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
631 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
632 COSTS_N_INSNS (2), /* cost of FABS instruction. */
633 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
634 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
635 /* For some reason, Athlon deals better with REP prefix (relative to loops)
636 compared to K8. Alignment becomes important after 8 bytes for memcpy and
637 128 bytes for memset. */
638 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
639 DUMMY_STRINGOP_ALGS},
640 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
641 DUMMY_STRINGOP_ALGS},
642 1, /* scalar_stmt_cost. */
643 1, /* scalar load_cost. */
644 1, /* scalar_store_cost. */
645 1, /* vec_stmt_cost. */
646 1, /* vec_to_scalar_cost. */
647 1, /* scalar_to_vec_cost. */
648 1, /* vec_align_load_cost. */
649 2, /* vec_unalign_load_cost. */
650 1, /* vec_store_cost. */
651 3, /* cond_taken_branch_cost. */
652 1, /* cond_not_taken_branch_cost. */
656 struct processor_costs k8_cost = {
657 COSTS_N_INSNS (1), /* cost of an add instruction */
658 COSTS_N_INSNS (2), /* cost of a lea instruction */
659 COSTS_N_INSNS (1), /* variable shift costs */
660 COSTS_N_INSNS (1), /* constant shift costs */
661 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
662 COSTS_N_INSNS (4), /* HI */
663 COSTS_N_INSNS (3), /* SI */
664 COSTS_N_INSNS (4), /* DI */
665 COSTS_N_INSNS (5)}, /* other */
666 0, /* cost of multiply per each bit set */
667 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
668 COSTS_N_INSNS (26), /* HI */
669 COSTS_N_INSNS (42), /* SI */
670 COSTS_N_INSNS (74), /* DI */
671 COSTS_N_INSNS (74)}, /* other */
672 COSTS_N_INSNS (1), /* cost of movsx */
673 COSTS_N_INSNS (1), /* cost of movzx */
674 8, /* "large" insn */
676 4, /* cost for loading QImode using movzbl */
677 {3, 4, 3}, /* cost of loading integer registers
678 in QImode, HImode and SImode.
679 Relative to reg-reg move (2). */
680 {3, 4, 3}, /* cost of storing integer registers */
681 4, /* cost of reg,reg fld/fst */
682 {4, 4, 12}, /* cost of loading fp registers
683 in SFmode, DFmode and XFmode */
684 {6, 6, 8}, /* cost of storing fp registers
685 in SFmode, DFmode and XFmode */
686 2, /* cost of moving MMX register */
687 {3, 3}, /* cost of loading MMX registers
688 in SImode and DImode */
689 {4, 4}, /* cost of storing MMX registers
690 in SImode and DImode */
691 2, /* cost of moving SSE register */
692 {4, 3, 6}, /* cost of loading SSE registers
693 in SImode, DImode and TImode */
694 {4, 4, 5}, /* cost of storing SSE registers
695 in SImode, DImode and TImode */
696 5, /* MMX or SSE register to integer */
697 64, /* size of l1 cache. */
698 512, /* size of l2 cache. */
699 64, /* size of prefetch block */
700 /* New AMD processors never drop prefetches; if they cannot be performed
701 immediately, they are queued. We set number of simultaneous prefetches
702 to a large constant to reflect this (it probably is not a good idea not
703 to limit number of prefetches at all, as their execution also takes some
705 100, /* number of parallel prefetches */
707 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
708 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
709 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
710 COSTS_N_INSNS (2), /* cost of FABS instruction. */
711 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
712 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
713 /* K8 has optimized REP instruction for medium sized blocks, but for very small
714 blocks it is better to use loop. For large blocks, libcall can do
715 nontemporary accesses and beat inline considerably. */
716 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
717 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
718 {{libcall, {{8, loop}, {24, unrolled_loop},
719 {2048, rep_prefix_4_byte}, {-1, libcall}}},
720 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
721 4, /* scalar_stmt_cost. */
722 2, /* scalar load_cost. */
723 2, /* scalar_store_cost. */
724 5, /* vec_stmt_cost. */
725 0, /* vec_to_scalar_cost. */
726 2, /* scalar_to_vec_cost. */
727 2, /* vec_align_load_cost. */
728 3, /* vec_unalign_load_cost. */
729 3, /* vec_store_cost. */
730 3, /* cond_taken_branch_cost. */
731 2, /* cond_not_taken_branch_cost. */
734 struct processor_costs amdfam10_cost = {
735 COSTS_N_INSNS (1), /* cost of an add instruction */
736 COSTS_N_INSNS (2), /* cost of a lea instruction */
737 COSTS_N_INSNS (1), /* variable shift costs */
738 COSTS_N_INSNS (1), /* constant shift costs */
739 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
740 COSTS_N_INSNS (4), /* HI */
741 COSTS_N_INSNS (3), /* SI */
742 COSTS_N_INSNS (4), /* DI */
743 COSTS_N_INSNS (5)}, /* other */
744 0, /* cost of multiply per each bit set */
745 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
746 COSTS_N_INSNS (35), /* HI */
747 COSTS_N_INSNS (51), /* SI */
748 COSTS_N_INSNS (83), /* DI */
749 COSTS_N_INSNS (83)}, /* other */
750 COSTS_N_INSNS (1), /* cost of movsx */
751 COSTS_N_INSNS (1), /* cost of movzx */
752 8, /* "large" insn */
754 4, /* cost for loading QImode using movzbl */
755 {3, 4, 3}, /* cost of loading integer registers
756 in QImode, HImode and SImode.
757 Relative to reg-reg move (2). */
758 {3, 4, 3}, /* cost of storing integer registers */
759 4, /* cost of reg,reg fld/fst */
760 {4, 4, 12}, /* cost of loading fp registers
761 in SFmode, DFmode and XFmode */
762 {6, 6, 8}, /* cost of storing fp registers
763 in SFmode, DFmode and XFmode */
764 2, /* cost of moving MMX register */
765 {3, 3}, /* cost of loading MMX registers
766 in SImode and DImode */
767 {4, 4}, /* cost of storing MMX registers
768 in SImode and DImode */
769 2, /* cost of moving SSE register */
770 {4, 4, 3}, /* cost of loading SSE registers
771 in SImode, DImode and TImode */
772 {4, 4, 5}, /* cost of storing SSE registers
773 in SImode, DImode and TImode */
774 3, /* MMX or SSE register to integer */
776 MOVD reg64, xmmreg Double FSTORE 4
777 MOVD reg32, xmmreg Double FSTORE 4
779 MOVD reg64, xmmreg Double FADD 3
781 MOVD reg32, xmmreg Double FADD 3
783 64, /* size of l1 cache. */
784 512, /* size of l2 cache. */
785 64, /* size of prefetch block */
786 /* New AMD processors never drop prefetches; if they cannot be performed
787 immediately, they are queued. We set number of simultaneous prefetches
788 to a large constant to reflect this (it probably is not a good idea not
789 to limit number of prefetches at all, as their execution also takes some
791 100, /* number of parallel prefetches */
793 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
794 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
795 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
796 COSTS_N_INSNS (2), /* cost of FABS instruction. */
797 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
798 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
800 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
801 very small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
803 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
804 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
805 {{libcall, {{8, loop}, {24, unrolled_loop},
806 {2048, rep_prefix_4_byte}, {-1, libcall}}},
807 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
808 4, /* scalar_stmt_cost. */
809 2, /* scalar load_cost. */
810 2, /* scalar_store_cost. */
811 6, /* vec_stmt_cost. */
812 0, /* vec_to_scalar_cost. */
813 2, /* scalar_to_vec_cost. */
814 2, /* vec_align_load_cost. */
815 2, /* vec_unalign_load_cost. */
816 2, /* vec_store_cost. */
817 2, /* cond_taken_branch_cost. */
818 1, /* cond_not_taken_branch_cost. */
822 struct processor_costs pentium4_cost = {
823 COSTS_N_INSNS (1), /* cost of an add instruction */
824 COSTS_N_INSNS (3), /* cost of a lea instruction */
825 COSTS_N_INSNS (4), /* variable shift costs */
826 COSTS_N_INSNS (4), /* constant shift costs */
827 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
828 COSTS_N_INSNS (15), /* HI */
829 COSTS_N_INSNS (15), /* SI */
830 COSTS_N_INSNS (15), /* DI */
831 COSTS_N_INSNS (15)}, /* other */
832 0, /* cost of multiply per each bit set */
833 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
834 COSTS_N_INSNS (56), /* HI */
835 COSTS_N_INSNS (56), /* SI */
836 COSTS_N_INSNS (56), /* DI */
837 COSTS_N_INSNS (56)}, /* other */
838 COSTS_N_INSNS (1), /* cost of movsx */
839 COSTS_N_INSNS (1), /* cost of movzx */
840 16, /* "large" insn */
842 2, /* cost for loading QImode using movzbl */
843 {4, 5, 4}, /* cost of loading integer registers
844 in QImode, HImode and SImode.
845 Relative to reg-reg move (2). */
846 {2, 3, 2}, /* cost of storing integer registers */
847 2, /* cost of reg,reg fld/fst */
848 {2, 2, 6}, /* cost of loading fp registers
849 in SFmode, DFmode and XFmode */
850 {4, 4, 6}, /* cost of storing fp registers
851 in SFmode, DFmode and XFmode */
852 2, /* cost of moving MMX register */
853 {2, 2}, /* cost of loading MMX registers
854 in SImode and DImode */
855 {2, 2}, /* cost of storing MMX registers
856 in SImode and DImode */
857 12, /* cost of moving SSE register */
858 {12, 12, 12}, /* cost of loading SSE registers
859 in SImode, DImode and TImode */
860 {2, 2, 8}, /* cost of storing SSE registers
861 in SImode, DImode and TImode */
862 10, /* MMX or SSE register to integer */
863 8, /* size of l1 cache. */
864 256, /* size of l2 cache. */
865 64, /* size of prefetch block */
866 6, /* number of parallel prefetches */
868 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
869 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
870 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
871 COSTS_N_INSNS (2), /* cost of FABS instruction. */
872 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
873 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
874 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
875 DUMMY_STRINGOP_ALGS},
876 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
878 DUMMY_STRINGOP_ALGS},
879 1, /* scalar_stmt_cost. */
880 1, /* scalar load_cost. */
881 1, /* scalar_store_cost. */
882 1, /* vec_stmt_cost. */
883 1, /* vec_to_scalar_cost. */
884 1, /* scalar_to_vec_cost. */
885 1, /* vec_align_load_cost. */
886 2, /* vec_unalign_load_cost. */
887 1, /* vec_store_cost. */
888 3, /* cond_taken_branch_cost. */
889 1, /* cond_not_taken_branch_cost. */
893 struct processor_costs nocona_cost = {
894 COSTS_N_INSNS (1), /* cost of an add instruction */
895 COSTS_N_INSNS (1), /* cost of a lea instruction */
896 COSTS_N_INSNS (1), /* variable shift costs */
897 COSTS_N_INSNS (1), /* constant shift costs */
898 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
899 COSTS_N_INSNS (10), /* HI */
900 COSTS_N_INSNS (10), /* SI */
901 COSTS_N_INSNS (10), /* DI */
902 COSTS_N_INSNS (10)}, /* other */
903 0, /* cost of multiply per each bit set */
904 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
905 COSTS_N_INSNS (66), /* HI */
906 COSTS_N_INSNS (66), /* SI */
907 COSTS_N_INSNS (66), /* DI */
908 COSTS_N_INSNS (66)}, /* other */
909 COSTS_N_INSNS (1), /* cost of movsx */
910 COSTS_N_INSNS (1), /* cost of movzx */
911 16, /* "large" insn */
913 4, /* cost for loading QImode using movzbl */
914 {4, 4, 4}, /* cost of loading integer registers
915 in QImode, HImode and SImode.
916 Relative to reg-reg move (2). */
917 {4, 4, 4}, /* cost of storing integer registers */
918 3, /* cost of reg,reg fld/fst */
919 {12, 12, 12}, /* cost of loading fp registers
920 in SFmode, DFmode and XFmode */
921 {4, 4, 4}, /* cost of storing fp registers
922 in SFmode, DFmode and XFmode */
923 6, /* cost of moving MMX register */
924 {12, 12}, /* cost of loading MMX registers
925 in SImode and DImode */
926 {12, 12}, /* cost of storing MMX registers
927 in SImode and DImode */
928 6, /* cost of moving SSE register */
929 {12, 12, 12}, /* cost of loading SSE registers
930 in SImode, DImode and TImode */
931 {12, 12, 12}, /* cost of storing SSE registers
932 in SImode, DImode and TImode */
933 8, /* MMX or SSE register to integer */
934 8, /* size of l1 cache. */
935 1024, /* size of l2 cache. */
936 128, /* size of prefetch block */
937 8, /* number of parallel prefetches */
939 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
940 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
941 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
942 COSTS_N_INSNS (3), /* cost of FABS instruction. */
943 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
944 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
945 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
946 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
947 {100000, unrolled_loop}, {-1, libcall}}}},
948 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
950 {libcall, {{24, loop}, {64, unrolled_loop},
951 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
952 1, /* scalar_stmt_cost. */
953 1, /* scalar load_cost. */
954 1, /* scalar_store_cost. */
955 1, /* vec_stmt_cost. */
956 1, /* vec_to_scalar_cost. */
957 1, /* scalar_to_vec_cost. */
958 1, /* vec_align_load_cost. */
959 2, /* vec_unalign_load_cost. */
960 1, /* vec_store_cost. */
961 3, /* cond_taken_branch_cost. */
962 1, /* cond_not_taken_branch_cost. */
966 struct processor_costs core2_cost = {
967 COSTS_N_INSNS (1), /* cost of an add instruction */
968 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
969 COSTS_N_INSNS (1), /* variable shift costs */
970 COSTS_N_INSNS (1), /* constant shift costs */
971 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
972 COSTS_N_INSNS (3), /* HI */
973 COSTS_N_INSNS (3), /* SI */
974 COSTS_N_INSNS (3), /* DI */
975 COSTS_N_INSNS (3)}, /* other */
976 0, /* cost of multiply per each bit set */
977 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
978 COSTS_N_INSNS (22), /* HI */
979 COSTS_N_INSNS (22), /* SI */
980 COSTS_N_INSNS (22), /* DI */
981 COSTS_N_INSNS (22)}, /* other */
982 COSTS_N_INSNS (1), /* cost of movsx */
983 COSTS_N_INSNS (1), /* cost of movzx */
984 8, /* "large" insn */
986 2, /* cost for loading QImode using movzbl */
987 {6, 6, 6}, /* cost of loading integer registers
988 in QImode, HImode and SImode.
989 Relative to reg-reg move (2). */
990 {4, 4, 4}, /* cost of storing integer registers */
991 2, /* cost of reg,reg fld/fst */
992 {6, 6, 6}, /* cost of loading fp registers
993 in SFmode, DFmode and XFmode */
994 {4, 4, 4}, /* cost of storing fp registers
995 in SFmode, DFmode and XFmode */
996 2, /* cost of moving MMX register */
997 {6, 6}, /* cost of loading MMX registers
998 in SImode and DImode */
999 {4, 4}, /* cost of storing MMX registers
1000 in SImode and DImode */
1001 2, /* cost of moving SSE register */
1002 {6, 6, 6}, /* cost of loading SSE registers
1003 in SImode, DImode and TImode */
1004 {4, 4, 4}, /* cost of storing SSE registers
1005 in SImode, DImode and TImode */
1006 2, /* MMX or SSE register to integer */
1007 32, /* size of l1 cache. */
1008 2048, /* size of l2 cache. */
1009 128, /* size of prefetch block */
1010 8, /* number of parallel prefetches */
1011 3, /* Branch cost */
1012 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1013 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1014 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1015 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1016 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1017 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1018 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1019 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1020 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1021 {{libcall, {{8, loop}, {15, unrolled_loop},
1022 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1023 {libcall, {{24, loop}, {32, unrolled_loop},
1024 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1025 1, /* scalar_stmt_cost. */
1026 1, /* scalar load_cost. */
1027 1, /* scalar_store_cost. */
1028 1, /* vec_stmt_cost. */
1029 1, /* vec_to_scalar_cost. */
1030 1, /* scalar_to_vec_cost. */
1031 1, /* vec_align_load_cost. */
1032 2, /* vec_unalign_load_cost. */
1033 1, /* vec_store_cost. */
1034 3, /* cond_taken_branch_cost. */
1035 1, /* cond_not_taken_branch_cost. */
1039 struct processor_costs atom_cost = {
1040 COSTS_N_INSNS (1), /* cost of an add instruction */
1041 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1042 COSTS_N_INSNS (1), /* variable shift costs */
1043 COSTS_N_INSNS (1), /* constant shift costs */
1044 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1045 COSTS_N_INSNS (4), /* HI */
1046 COSTS_N_INSNS (3), /* SI */
1047 COSTS_N_INSNS (4), /* DI */
1048 COSTS_N_INSNS (2)}, /* other */
1049 0, /* cost of multiply per each bit set */
1050 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1051 COSTS_N_INSNS (26), /* HI */
1052 COSTS_N_INSNS (42), /* SI */
1053 COSTS_N_INSNS (74), /* DI */
1054 COSTS_N_INSNS (74)}, /* other */
1055 COSTS_N_INSNS (1), /* cost of movsx */
1056 COSTS_N_INSNS (1), /* cost of movzx */
1057 8, /* "large" insn */
1058 17, /* MOVE_RATIO */
1059 2, /* cost for loading QImode using movzbl */
1060 {4, 4, 4}, /* cost of loading integer registers
1061 in QImode, HImode and SImode.
1062 Relative to reg-reg move (2). */
1063 {4, 4, 4}, /* cost of storing integer registers */
1064 4, /* cost of reg,reg fld/fst */
1065 {12, 12, 12}, /* cost of loading fp registers
1066 in SFmode, DFmode and XFmode */
1067 {6, 6, 8}, /* cost of storing fp registers
1068 in SFmode, DFmode and XFmode */
1069 2, /* cost of moving MMX register */
1070 {8, 8}, /* cost of loading MMX registers
1071 in SImode and DImode */
1072 {8, 8}, /* cost of storing MMX registers
1073 in SImode and DImode */
1074 2, /* cost of moving SSE register */
1075 {8, 8, 8}, /* cost of loading SSE registers
1076 in SImode, DImode and TImode */
1077 {8, 8, 8}, /* cost of storing SSE registers
1078 in SImode, DImode and TImode */
1079 5, /* MMX or SSE register to integer */
1080 32, /* size of l1 cache. */
1081 256, /* size of l2 cache. */
1082 64, /* size of prefetch block */
1083 6, /* number of parallel prefetches */
1084 3, /* Branch cost */
1085 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1086 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1087 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1088 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1089 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1090 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1091 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1092 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1093 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1094 {{libcall, {{8, loop}, {15, unrolled_loop},
1095 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1096 {libcall, {{24, loop}, {32, unrolled_loop},
1097 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1098 1, /* scalar_stmt_cost. */
1099 1, /* scalar load_cost. */
1100 1, /* scalar_store_cost. */
1101 1, /* vec_stmt_cost. */
1102 1, /* vec_to_scalar_cost. */
1103 1, /* scalar_to_vec_cost. */
1104 1, /* vec_align_load_cost. */
1105 2, /* vec_unalign_load_cost. */
1106 1, /* vec_store_cost. */
1107 3, /* cond_taken_branch_cost. */
1108 1, /* cond_not_taken_branch_cost. */
1111 /* Generic64 should produce code tuned for Nocona and K8. */
1113 struct processor_costs generic64_cost = {
1114 COSTS_N_INSNS (1), /* cost of an add instruction */
1115 /* On all chips taken into consideration lea is 2 cycles and more. With
1116 this cost however our current implementation of synth_mult results in
1117 use of unnecessary temporary registers causing regression on several
1118 SPECfp benchmarks. */
1119 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1120 COSTS_N_INSNS (1), /* variable shift costs */
1121 COSTS_N_INSNS (1), /* constant shift costs */
1122 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1123 COSTS_N_INSNS (4), /* HI */
1124 COSTS_N_INSNS (3), /* SI */
1125 COSTS_N_INSNS (4), /* DI */
1126 COSTS_N_INSNS (2)}, /* other */
1127 0, /* cost of multiply per each bit set */
1128 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1129 COSTS_N_INSNS (26), /* HI */
1130 COSTS_N_INSNS (42), /* SI */
1131 COSTS_N_INSNS (74), /* DI */
1132 COSTS_N_INSNS (74)}, /* other */
1133 COSTS_N_INSNS (1), /* cost of movsx */
1134 COSTS_N_INSNS (1), /* cost of movzx */
1135 8, /* "large" insn */
1136 17, /* MOVE_RATIO */
1137 4, /* cost for loading QImode using movzbl */
1138 {4, 4, 4}, /* cost of loading integer registers
1139 in QImode, HImode and SImode.
1140 Relative to reg-reg move (2). */
1141 {4, 4, 4}, /* cost of storing integer registers */
1142 4, /* cost of reg,reg fld/fst */
1143 {12, 12, 12}, /* cost of loading fp registers
1144 in SFmode, DFmode and XFmode */
1145 {6, 6, 8}, /* cost of storing fp registers
1146 in SFmode, DFmode and XFmode */
1147 2, /* cost of moving MMX register */
1148 {8, 8}, /* cost of loading MMX registers
1149 in SImode and DImode */
1150 {8, 8}, /* cost of storing MMX registers
1151 in SImode and DImode */
1152 2, /* cost of moving SSE register */
1153 {8, 8, 8}, /* cost of loading SSE registers
1154 in SImode, DImode and TImode */
1155 {8, 8, 8}, /* cost of storing SSE registers
1156 in SImode, DImode and TImode */
1157 5, /* MMX or SSE register to integer */
1158 32, /* size of l1 cache. */
1159 512, /* size of l2 cache. */
1160 64, /* size of prefetch block */
1161 6, /* number of parallel prefetches */
1162 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1163 is increased to perhaps more appropriate value of 5. */
1164 3, /* Branch cost */
1165 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1166 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1167 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1168 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1169 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1170 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1171 {DUMMY_STRINGOP_ALGS,
1172 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1173 {DUMMY_STRINGOP_ALGS,
1174 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1175 1, /* scalar_stmt_cost. */
1176 1, /* scalar load_cost. */
1177 1, /* scalar_store_cost. */
1178 1, /* vec_stmt_cost. */
1179 1, /* vec_to_scalar_cost. */
1180 1, /* scalar_to_vec_cost. */
1181 1, /* vec_align_load_cost. */
1182 2, /* vec_unalign_load_cost. */
1183 1, /* vec_store_cost. */
1184 3, /* cond_taken_branch_cost. */
1185 1, /* cond_not_taken_branch_cost. */
1188 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1190 struct processor_costs generic32_cost = {
1191 COSTS_N_INSNS (1), /* cost of an add instruction */
1192 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1193 COSTS_N_INSNS (1), /* variable shift costs */
1194 COSTS_N_INSNS (1), /* constant shift costs */
1195 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1196 COSTS_N_INSNS (4), /* HI */
1197 COSTS_N_INSNS (3), /* SI */
1198 COSTS_N_INSNS (4), /* DI */
1199 COSTS_N_INSNS (2)}, /* other */
1200 0, /* cost of multiply per each bit set */
1201 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1202 COSTS_N_INSNS (26), /* HI */
1203 COSTS_N_INSNS (42), /* SI */
1204 COSTS_N_INSNS (74), /* DI */
1205 COSTS_N_INSNS (74)}, /* other */
1206 COSTS_N_INSNS (1), /* cost of movsx */
1207 COSTS_N_INSNS (1), /* cost of movzx */
1208 8, /* "large" insn */
1209 17, /* MOVE_RATIO */
1210 4, /* cost for loading QImode using movzbl */
1211 {4, 4, 4}, /* cost of loading integer registers
1212 in QImode, HImode and SImode.
1213 Relative to reg-reg move (2). */
1214 {4, 4, 4}, /* cost of storing integer registers */
1215 4, /* cost of reg,reg fld/fst */
1216 {12, 12, 12}, /* cost of loading fp registers
1217 in SFmode, DFmode and XFmode */
1218 {6, 6, 8}, /* cost of storing fp registers
1219 in SFmode, DFmode and XFmode */
1220 2, /* cost of moving MMX register */
1221 {8, 8}, /* cost of loading MMX registers
1222 in SImode and DImode */
1223 {8, 8}, /* cost of storing MMX registers
1224 in SImode and DImode */
1225 2, /* cost of moving SSE register */
1226 {8, 8, 8}, /* cost of loading SSE registers
1227 in SImode, DImode and TImode */
1228 {8, 8, 8}, /* cost of storing SSE registers
1229 in SImode, DImode and TImode */
1230 5, /* MMX or SSE register to integer */
1231 32, /* size of l1 cache. */
1232 256, /* size of l2 cache. */
1233 64, /* size of prefetch block */
1234 6, /* number of parallel prefetches */
1235 3, /* Branch cost */
1236 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1237 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1238 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1239 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1240 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1241 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1242 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1243 DUMMY_STRINGOP_ALGS},
1244 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1245 DUMMY_STRINGOP_ALGS},
1246 1, /* scalar_stmt_cost. */
1247 1, /* scalar load_cost. */
1248 1, /* scalar_store_cost. */
1249 1, /* vec_stmt_cost. */
1250 1, /* vec_to_scalar_cost. */
1251 1, /* scalar_to_vec_cost. */
1252 1, /* vec_align_load_cost. */
1253 2, /* vec_unalign_load_cost. */
1254 1, /* vec_store_cost. */
1255 3, /* cond_taken_branch_cost. */
1256 1, /* cond_not_taken_branch_cost. */
1259 const struct processor_costs *ix86_cost = &pentium_cost;
1261 /* Processor feature/optimization bitmasks. */
1262 #define m_386 (1<<PROCESSOR_I386)
1263 #define m_486 (1<<PROCESSOR_I486)
1264 #define m_PENT (1<<PROCESSOR_PENTIUM)
1265 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1266 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1267 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1268 #define m_CORE2 (1<<PROCESSOR_CORE2)
1269 #define m_ATOM (1<<PROCESSOR_ATOM)
1271 #define m_GEODE (1<<PROCESSOR_GEODE)
1272 #define m_K6 (1<<PROCESSOR_K6)
1273 #define m_K6_GEODE (m_K6 | m_GEODE)
1274 #define m_K8 (1<<PROCESSOR_K8)
1275 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1276 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1277 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1278 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1280 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1281 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1283 /* Generic instruction choice should be common subset of supported CPUs
1284 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1285 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1287 /* Feature tests against the various tunings. */
1288 unsigned char ix86_tune_features[X86_TUNE_LAST];
1290 /* Feature tests against the various tunings used to create ix86_tune_features
1291 based on the processor mask. */
1292 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1293 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1294 negatively, so enabling for Generic64 seems like good code size
1295 tradeoff. We can't enable it for 32bit generic because it does not
1296 work well with PPro base chips. */
1297 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1299 /* X86_TUNE_PUSH_MEMORY */
1300 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1301 | m_NOCONA | m_CORE2 | m_GENERIC,
1303 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1306 /* X86_TUNE_UNROLL_STRLEN */
1307 m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
1308 | m_CORE2 | m_GENERIC,
1310 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1311 m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1313 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1314 on simulation result. But after P4 was made, no performance benefit
1315 was observed with branch hints. It also increases the code size.
1316 As a result, icc never generates branch hints. */
1319 /* X86_TUNE_DOUBLE_WITH_ADD */
1322 /* X86_TUNE_USE_SAHF */
1323 m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1324 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1327 partial dependencies. */
1328 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
1329 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1331 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1332 register stalls on Generic32 compilation setting as well. However
1333 in current implementation the partial register stalls are not eliminated
1334 very well - they can be introduced via subregs synthesized by combine
1335 and can happen in caller/callee saving sequences. Because this option
1336 pays back little on PPro based chips and is in conflict with partial reg
1337 dependencies used by Athlon/P4 based chips, it is better to leave it off
1338 for generic32 for now. */
1341 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1342 m_CORE2 | m_GENERIC,
1344 /* X86_TUNE_USE_HIMODE_FIOP */
1345 m_386 | m_486 | m_K6_GEODE,
1347 /* X86_TUNE_USE_SIMODE_FIOP */
1348 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),
1350 /* X86_TUNE_USE_MOV0 */
1353 /* X86_TUNE_USE_CLTD */
1354 ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),
1356 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1359 /* X86_TUNE_SPLIT_LONG_MOVES */
1362 /* X86_TUNE_READ_MODIFY_WRITE */
1365 /* X86_TUNE_READ_MODIFY */
1368 /* X86_TUNE_PROMOTE_QIMODE */
1369 m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
1370 | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,
1372 /* X86_TUNE_FAST_PREFIX */
1373 ~(m_PENT | m_486 | m_386),
1375 /* X86_TUNE_SINGLE_STRINGOP */
1376 m_386 | m_PENT4 | m_NOCONA,
1378 /* X86_TUNE_QIMODE_MATH */
1381 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1382 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1383 might be considered for Generic32 if our scheme for avoiding partial
1384 stalls was more effective. */
1387 /* X86_TUNE_PROMOTE_QI_REGS */
1390 /* X86_TUNE_PROMOTE_HI_REGS */
1393 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1394 m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
1395 | m_CORE2 | m_GENERIC,
1397 /* X86_TUNE_ADD_ESP_8 */
1398 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
1399 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1401 /* X86_TUNE_SUB_ESP_4 */
1402 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
1405 /* X86_TUNE_SUB_ESP_8 */
1406 m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
1407 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1409 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1410 for DFmode copies */
1411 ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1412 | m_GENERIC | m_GEODE),
1414 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1415 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1417 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1418 conflict here in between PPro/Pentium4 based chips that thread 128bit
1419 SSE registers as single units versus K8 based chips that divide SSE
1420 registers to two 64bit halves. This knob promotes all store destinations
1421 to be 128bit to allow register renaming on 128bit SSE units, but usually
1422 results in one extra microop on 64bit SSE units. Experimental results
1423 shows that disabling this option on P4 brings over 20% SPECfp regression,
1424 while enabling it on K8 brings roughly 2.4% regression that can be partly
1425 masked by careful scheduling of moves. */
1426 m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
1429 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1432 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1433 are resolved on SSE register parts instead of whole registers, so we may
1434 maintain just lower part of scalar values in proper format leaving the
1435 upper part undefined. */
1438 /* X86_TUNE_SSE_TYPELESS_STORES */
1441 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1442 m_PPRO | m_PENT4 | m_NOCONA,
1444 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1445 m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1447 /* X86_TUNE_PROLOGUE_USING_MOVE */
1448 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1450 /* X86_TUNE_EPILOGUE_USING_MOVE */
1451 m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
1453 /* X86_TUNE_SHIFT1 */
1456 /* X86_TUNE_USE_FFREEP */
1459 /* X86_TUNE_INTER_UNIT_MOVES */
1460 ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
1462 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1465 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1466 than 4 branch instructions in the 16 byte window. */
1467 m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
1470 /* X86_TUNE_SCHEDULE */
1471 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
1474 /* X86_TUNE_USE_BT */
1475 m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,
1477 /* X86_TUNE_USE_INCDEC */
1478 ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),
1480 /* X86_TUNE_PAD_RETURNS */
1481 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1483 /* X86_TUNE_EXT_80387_CONSTANTS */
1484 m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
1485 | m_CORE2 | m_GENERIC,
1487 /* X86_TUNE_SHORTEN_X87_SSE */
1490 /* X86_TUNE_AVOID_VECTOR_DECODE */
1493 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1494 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1497 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1498 vector path on AMD machines. */
1499 m_K8 | m_GENERIC64 | m_AMDFAM10,
1501 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1503 m_K8 | m_GENERIC64 | m_AMDFAM10,
1505 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1509 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1510 but one byte longer. */
1513 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1514 operand that cannot be represented using a modRM byte. The XOR
1515 replacement is long decoded, so this split helps here as well. */
1518 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1520 m_AMDFAM10 | m_GENERIC,
1522 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1523 from integer to FP. */
1526 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1527 with a subsequent conditional jump instruction into a single
1528 compare-and-branch uop. */
1531 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
1532 will impact LEA instruction selection. */
1536 /* Feature tests against the various architecture variations. */
1537 unsigned char ix86_arch_features[X86_ARCH_LAST];
1539 /* Feature tests against the various architecture variations, used to create
1540 ix86_arch_features based on the processor mask. */
1541 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1542 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1543 ~(m_386 | m_486 | m_PENT | m_K6),
1545 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1548 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1551 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1554 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1558 static const unsigned int x86_accumulate_outgoing_args
1559 = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1562 static const unsigned int x86_arch_always_fancy_math_387
1563 = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1564 | m_NOCONA | m_CORE2 | m_GENERIC;
1566 static enum stringop_alg stringop_alg = no_stringop;
1568 /* In case the average insn count for single function invocation is
1569 lower than this constant, emit fast (but longer) prologue and
1571 #define FAST_PROLOGUE_INSN_COUNT 20
1573 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1574 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1575 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1576 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1578 /* Array of the smallest class containing reg number REGNO, indexed by
1579 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1581 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1583 /* ax, dx, cx, bx */
1584 AREG, DREG, CREG, BREG,
1585 /* si, di, bp, sp */
1586 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1588 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1589 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1592 /* flags, fpsr, fpcr, frame */
1593 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1595 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1598 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1601 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1602 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1603 /* SSE REX registers */
1604 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1608 /* The "default" register map used in 32bit mode. */
1610 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1612 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1613 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1614 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1615 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1616 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1617 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1618 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1621 /* The "default" register map used in 64bit mode. */
1623 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1625 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1626 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1627 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1628 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1629 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1630 8,9,10,11,12,13,14,15, /* extended integer registers */
1631 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1634 /* Define the register numbers to be used in Dwarf debugging information.
1635 The SVR4 reference port C compiler uses the following register numbers
1636 in its Dwarf output code:
1637 0 for %eax (gcc regno = 0)
1638 1 for %ecx (gcc regno = 2)
1639 2 for %edx (gcc regno = 1)
1640 3 for %ebx (gcc regno = 3)
1641 4 for %esp (gcc regno = 7)
1642 5 for %ebp (gcc regno = 6)
1643 6 for %esi (gcc regno = 4)
1644 7 for %edi (gcc regno = 5)
1645 The following three DWARF register numbers are never generated by
1646 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1647 believes these numbers have these meanings.
1648 8 for %eip (no gcc equivalent)
1649 9 for %eflags (gcc regno = 17)
1650 10 for %trapno (no gcc equivalent)
1651 It is not at all clear how we should number the FP stack registers
1652 for the x86 architecture. If the version of SDB on x86/svr4 were
1653 a bit less brain dead with respect to floating-point then we would
1654 have a precedent to follow with respect to DWARF register numbers
1655 for x86 FP registers, but the SDB on x86/svr4 is so completely
1656 broken with respect to FP registers that it is hardly worth thinking
1657 of it as something to strive for compatibility with.
1658 The version of x86/svr4 SDB I have at the moment does (partially)
1659 seem to believe that DWARF register number 11 is associated with
1660 the x86 register %st(0), but that's about all. Higher DWARF
1661 register numbers don't seem to be associated with anything in
1662 particular, and even for DWARF regno 11, SDB only seems to under-
1663 stand that it should say that a variable lives in %st(0) (when
1664 asked via an `=' command) if we said it was in DWARF regno 11,
1665 but SDB still prints garbage when asked for the value of the
1666 variable in question (via a `/' command).
1667 (Also note that the labels SDB prints for various FP stack regs
1668 when doing an `x' command are all wrong.)
1669 Note that these problems generally don't affect the native SVR4
1670 C compiler because it doesn't allow the use of -O with -g and
1671 because when it is *not* optimizing, it allocates a memory
1672 location for each floating-point variable, and the memory
1673 location is what gets described in the DWARF AT_location
1674 attribute for the variable in question.
1675 Regardless of the severe mental illness of the x86/svr4 SDB, we
1676 do something sensible here and we use the following DWARF
1677 register numbers. Note that these are all stack-top-relative
1679 11 for %st(0) (gcc regno = 8)
1680 12 for %st(1) (gcc regno = 9)
1681 13 for %st(2) (gcc regno = 10)
1682 14 for %st(3) (gcc regno = 11)
1683 15 for %st(4) (gcc regno = 12)
1684 16 for %st(5) (gcc regno = 13)
1685 17 for %st(6) (gcc regno = 14)
1686 18 for %st(7) (gcc regno = 15)
1688 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1690 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1691 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1692 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1693 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1694 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1695 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1696 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1699 /* Test and compare insns in i386.md store the information needed to
1700 generate branch and scc insns here. */
1702 rtx ix86_compare_op0 = NULL_RTX;
1703 rtx ix86_compare_op1 = NULL_RTX;
1705 /* Define parameter passing and return registers. */
1707 static int const x86_64_int_parameter_registers[6] =
1709 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1712 static int const x86_64_ms_abi_int_parameter_registers[4] =
1714 CX_REG, DX_REG, R8_REG, R9_REG
1717 static int const x86_64_int_return_registers[4] =
1719 AX_REG, DX_REG, DI_REG, SI_REG
1722 /* Define the structure for the machine field in struct function. */
1724 struct GTY(()) stack_local_entry {
1725 unsigned short mode;
1728 struct stack_local_entry *next;
1731 /* Structure describing stack frame layout.
1732 Stack grows downward:
1738 saved frame pointer if frame_pointer_needed
1739 <- HARD_FRAME_POINTER
1748 [va_arg registers] (
1749 > to_allocate <- FRAME_POINTER
1761 HOST_WIDE_INT frame;
1763 int outgoing_arguments_size;
1766 HOST_WIDE_INT to_allocate;
1767 /* The offsets relative to ARG_POINTER. */
1768 HOST_WIDE_INT frame_pointer_offset;
1769 HOST_WIDE_INT hard_frame_pointer_offset;
1770 HOST_WIDE_INT stack_pointer_offset;
1772 /* When save_regs_using_mov is set, emit prologue using
1773 move instead of push instructions. */
1774 bool save_regs_using_mov;
1777 /* Code model option. */
1778 enum cmodel ix86_cmodel;
1780 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1782 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1784 /* Which unit we are generating floating point math for. */
1785 enum fpmath_unit ix86_fpmath;
1787 /* Which cpu are we scheduling for. */
1788 enum attr_cpu ix86_schedule;
1790 /* Which cpu are we optimizing for. */
1791 enum processor_type ix86_tune;
1793 /* Which instruction set architecture to use. */
1794 enum processor_type ix86_arch;
1796 /* true if sse prefetch instruction is not NOOP. */
1797 int x86_prefetch_sse;
1799 /* ix86_regparm_string as a number */
1800 static int ix86_regparm;
1802 /* -mstackrealign option */
1803 extern int ix86_force_align_arg_pointer;
1804 static const char ix86_force_align_arg_pointer_string[]
1805 = "force_align_arg_pointer";
1807 static rtx (*ix86_gen_leave) (void);
1808 static rtx (*ix86_gen_pop1) (rtx);
1809 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1810 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1811 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1812 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1813 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1814 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1816 /* Preferred alignment for stack boundary in bits. */
1817 unsigned int ix86_preferred_stack_boundary;
1819 /* Alignment for incoming stack boundary in bits specified at
1821 static unsigned int ix86_user_incoming_stack_boundary;
1823 /* Default alignment for incoming stack boundary in bits. */
1824 static unsigned int ix86_default_incoming_stack_boundary;
1826 /* Alignment for incoming stack boundary in bits. */
1827 unsigned int ix86_incoming_stack_boundary;
1829 /* The abi used by target. */
1830 enum calling_abi ix86_abi;
1832 /* Values 1-5: see jump.c */
1833 int ix86_branch_cost;
1835 /* Calling abi specific va_list type nodes. */
1836 static GTY(()) tree sysv_va_list_type_node;
1837 static GTY(()) tree ms_va_list_type_node;
1839 /* Variables which are this size or smaller are put in the data/bss
1840 or ldata/lbss sections. */
1842 int ix86_section_threshold = 65536;
1844 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1845 char internal_label_prefix[16];
1846 int internal_label_prefix_len;
1848 /* Fence to use after loop using movnt. */
1851 /* Register class used for passing given 64bit part of the argument.
1852 These represent classes as documented by the PS ABI, with the exception
1853 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1854 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1856 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1857 whenever possible (upper half does contain padding). */
1858 enum x86_64_reg_class
1861 X86_64_INTEGER_CLASS,
1862 X86_64_INTEGERSI_CLASS,
1869 X86_64_COMPLEX_X87_CLASS,
1873 #define MAX_CLASSES 4
1875 /* Table of constants used by fldpi, fldln2, etc.... */
1876 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1877 static bool ext_80387_constants_init = 0;
1880 static struct machine_function * ix86_init_machine_status (void);
1881 static rtx ix86_function_value (const_tree, const_tree, bool);
1882 static int ix86_function_regparm (const_tree, const_tree);
1883 static void ix86_compute_frame_layout (struct ix86_frame *);
1884 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1886 static void ix86_add_new_builtins (int);
1888 enum ix86_function_specific_strings
1890 IX86_FUNCTION_SPECIFIC_ARCH,
1891 IX86_FUNCTION_SPECIFIC_TUNE,
1892 IX86_FUNCTION_SPECIFIC_FPMATH,
1893 IX86_FUNCTION_SPECIFIC_MAX
1896 static char *ix86_target_string (int, int, const char *, const char *,
1897 const char *, bool);
1898 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1899 static void ix86_function_specific_save (struct cl_target_option *);
1900 static void ix86_function_specific_restore (struct cl_target_option *);
1901 static void ix86_function_specific_print (FILE *, int,
1902 struct cl_target_option *);
1903 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1904 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1905 static bool ix86_can_inline_p (tree, tree);
1906 static void ix86_set_current_function (tree);
1908 static enum calling_abi ix86_function_abi (const_tree);
1911 /* The svr4 ABI for the i386 says that records and unions are returned
1913 #ifndef DEFAULT_PCC_STRUCT_RETURN
1914 #define DEFAULT_PCC_STRUCT_RETURN 1
1917 /* Whether -mtune= or -march= were specified */
1918 static int ix86_tune_defaulted;
1919 static int ix86_arch_specified;
1921 /* Bit flags that specify the ISA we are compiling for. */
1922 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1924 /* A mask of ix86_isa_flags that includes bit X if X
1925 was set or cleared on the command line. */
1926 static int ix86_isa_flags_explicit;
1928 /* Define a set of ISAs which are available when a given ISA is
1929 enabled. MMX and SSE ISAs are handled separately. */
1931 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1932 #define OPTION_MASK_ISA_3DNOW_SET \
1933 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1935 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1936 #define OPTION_MASK_ISA_SSE2_SET \
1937 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1938 #define OPTION_MASK_ISA_SSE3_SET \
1939 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1940 #define OPTION_MASK_ISA_SSSE3_SET \
1941 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1942 #define OPTION_MASK_ISA_SSE4_1_SET \
1943 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1944 #define OPTION_MASK_ISA_SSE4_2_SET \
1945 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1946 #define OPTION_MASK_ISA_AVX_SET \
1947 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1948 #define OPTION_MASK_ISA_FMA_SET \
1949 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1951 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1953 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1955 #define OPTION_MASK_ISA_SSE4A_SET \
1956 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1958 /* AES and PCLMUL need SSE2 because they use xmm registers */
1959 #define OPTION_MASK_ISA_AES_SET \
1960 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1961 #define OPTION_MASK_ISA_PCLMUL_SET \
1962 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1964 #define OPTION_MASK_ISA_ABM_SET \
1965 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1967 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1968 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1969 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1970 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
1971 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
1973 /* Define a set of ISAs which aren't available when a given ISA is
1974 disabled. MMX and SSE ISAs are handled separately. */
1976 #define OPTION_MASK_ISA_MMX_UNSET \
1977 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1978 #define OPTION_MASK_ISA_3DNOW_UNSET \
1979 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1980 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1982 #define OPTION_MASK_ISA_SSE_UNSET \
1983 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1984 #define OPTION_MASK_ISA_SSE2_UNSET \
1985 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1986 #define OPTION_MASK_ISA_SSE3_UNSET \
1987 (OPTION_MASK_ISA_SSE3 \
1988 | OPTION_MASK_ISA_SSSE3_UNSET \
1989 | OPTION_MASK_ISA_SSE4A_UNSET )
1990 #define OPTION_MASK_ISA_SSSE3_UNSET \
1991 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1992 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1993 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1994 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1995 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1996 #define OPTION_MASK_ISA_AVX_UNSET \
1997 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1998 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
2000 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
2002 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
2004 #define OPTION_MASK_ISA_SSE4A_UNSET \
2005 (OPTION_MASK_ISA_SSE4A)
2006 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
2007 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
2008 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
2009 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
2010 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
2011 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
2012 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
2013 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
2015 /* Vectorization library interface and handlers. */
2016 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
2017 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
2018 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
2020 /* Processor target table, indexed by processor number */
2023 const struct processor_costs *cost; /* Processor costs */
2024 const int align_loop; /* Default alignments. */
2025 const int align_loop_max_skip;
2026 const int align_jump;
2027 const int align_jump_max_skip;
2028 const int align_func;
2031 static const struct ptt processor_target_table[PROCESSOR_max] =
2033 {&i386_cost, 4, 3, 4, 3, 4},
2034 {&i486_cost, 16, 15, 16, 15, 16},
2035 {&pentium_cost, 16, 7, 16, 7, 16},
2036 {&pentiumpro_cost, 16, 15, 16, 10, 16},
2037 {&geode_cost, 0, 0, 0, 0, 0},
2038 {&k6_cost, 32, 7, 32, 7, 32},
2039 {&athlon_cost, 16, 7, 16, 7, 16},
2040 {&pentium4_cost, 0, 0, 0, 0, 0},
2041 {&k8_cost, 16, 7, 16, 7, 16},
2042 {&nocona_cost, 0, 0, 0, 0, 0},
2043 {&core2_cost, 16, 10, 16, 10, 16},
2044 {&generic32_cost, 16, 7, 16, 7, 16},
2045 {&generic64_cost, 16, 10, 16, 10, 16},
2046 {&amdfam10_cost, 32, 24, 32, 7, 32},
2047 {&atom_cost, 16, 7, 16, 7, 16}
2050 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
2076 /* Implement TARGET_HANDLE_OPTION. */
2079 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
2086 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
2087 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
2091 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2092 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2099 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2100 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2104 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2105 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2115 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2116 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2120 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2121 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2128 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2129 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2133 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2134 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2141 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2142 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2146 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2147 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2154 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2155 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2159 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2160 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2167 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2168 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2172 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2173 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2180 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2181 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2185 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2186 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2193 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2194 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2198 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2199 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2206 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2207 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2211 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2212 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2217 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2218 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2222 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2223 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2229 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2230 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2234 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2235 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2242 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2243 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2247 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2248 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2255 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2256 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2260 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2261 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2268 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2269 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2273 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2274 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2281 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2282 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2286 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2287 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2294 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
2295 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
2299 ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
2300 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
2307 ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
2308 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
2312 ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
2313 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
2320 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2321 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2325 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2326 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2333 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2334 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2338 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2339 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2348 /* Return a string the documents the current -m options. The caller is
2349 responsible for freeing the string. */
2352 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2353 const char *fpmath, bool add_nl_p)
2355 struct ix86_target_opts
2357 const char *option; /* option string */
2358 int mask; /* isa mask options */
2361 /* This table is ordered so that options like -msse4.2 that imply
2362 preceding options while match those first. */
2363 static struct ix86_target_opts isa_opts[] =
2365 { "-m64", OPTION_MASK_ISA_64BIT },
2366 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2367 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2368 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2369 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2370 { "-msse3", OPTION_MASK_ISA_SSE3 },
2371 { "-msse2", OPTION_MASK_ISA_SSE2 },
2372 { "-msse", OPTION_MASK_ISA_SSE },
2373 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2374 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2375 { "-mmmx", OPTION_MASK_ISA_MMX },
2376 { "-mabm", OPTION_MASK_ISA_ABM },
2377 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2378 { "-mmovbe", OPTION_MASK_ISA_MOVBE },
2379 { "-mcrc32", OPTION_MASK_ISA_CRC32 },
2380 { "-maes", OPTION_MASK_ISA_AES },
2381 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2385 static struct ix86_target_opts flag_opts[] =
2387 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2388 { "-m80387", MASK_80387 },
2389 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2390 { "-malign-double", MASK_ALIGN_DOUBLE },
2391 { "-mcld", MASK_CLD },
2392 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2393 { "-mieee-fp", MASK_IEEE_FP },
2394 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2395 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2396 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2397 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2398 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2399 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2400 { "-mno-red-zone", MASK_NO_RED_ZONE },
2401 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2402 { "-mrecip", MASK_RECIP },
2403 { "-mrtd", MASK_RTD },
2404 { "-msseregparm", MASK_SSEREGPARM },
2405 { "-mstack-arg-probe", MASK_STACK_PROBE },
2406 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2409 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2412 char target_other[40];
2421 memset (opts, '\0', sizeof (opts));
2423 /* Add -march= option. */
2426 opts[num][0] = "-march=";
2427 opts[num++][1] = arch;
2430 /* Add -mtune= option. */
2433 opts[num][0] = "-mtune=";
2434 opts[num++][1] = tune;
2437 /* Pick out the options in isa options. */
2438 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2440 if ((isa & isa_opts[i].mask) != 0)
2442 opts[num++][0] = isa_opts[i].option;
2443 isa &= ~ isa_opts[i].mask;
2447 if (isa && add_nl_p)
2449 opts[num++][0] = isa_other;
2450 sprintf (isa_other, "(other isa: 0x%x)", isa);
2453 /* Add flag options. */
2454 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2456 if ((flags & flag_opts[i].mask) != 0)
2458 opts[num++][0] = flag_opts[i].option;
2459 flags &= ~ flag_opts[i].mask;
2463 if (flags && add_nl_p)
2465 opts[num++][0] = target_other;
2466 sprintf (target_other, "(other flags: 0x%x)", isa);
2469 /* Add -fpmath= option. */
2472 opts[num][0] = "-mfpmath=";
2473 opts[num++][1] = fpmath;
2480 gcc_assert (num < ARRAY_SIZE (opts));
2482 /* Size the string. */
2484 sep_len = (add_nl_p) ? 3 : 1;
2485 for (i = 0; i < num; i++)
2488 for (j = 0; j < 2; j++)
2490 len += strlen (opts[i][j]);
2493 /* Build the string. */
2494 ret = ptr = (char *) xmalloc (len);
2497 for (i = 0; i < num; i++)
2501 for (j = 0; j < 2; j++)
2502 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2509 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2517 for (j = 0; j < 2; j++)
2520 memcpy (ptr, opts[i][j], len2[j]);
2522 line_len += len2[j];
2527 gcc_assert (ret + len >= ptr);
2532 /* Function that is callable from the debugger to print the current
2535 ix86_debug_options (void)
2537 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2538 ix86_arch_string, ix86_tune_string,
2539 ix86_fpmath_string, true);
2543 fprintf (stderr, "%s\n\n", opts);
2547 fputs ("<no options>\n\n", stderr);
2552 /* Sometimes certain combinations of command options do not make
2553 sense on a particular target machine. You can define a macro
2554 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2555 defined, is executed once just after all the command options have
2558 Don't use this macro to turn on various extra optimizations for
2559 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2562 override_options (bool main_args_p)
2565 unsigned int ix86_arch_mask, ix86_tune_mask;
2570 /* Comes from final.c -- no real reason to change it. */
2571 #define MAX_CODE_ALIGN 16
2579 PTA_PREFETCH_SSE = 1 << 4,
2581 PTA_3DNOW_A = 1 << 6,
2585 PTA_POPCNT = 1 << 10,
2587 PTA_SSE4A = 1 << 12,
2588 PTA_NO_SAHF = 1 << 13,
2589 PTA_SSE4_1 = 1 << 14,
2590 PTA_SSE4_2 = 1 << 15,
2592 PTA_PCLMUL = 1 << 17,
2600 const char *const name; /* processor name or nickname. */
2601 const enum processor_type processor;
2602 const enum attr_cpu schedule;
2603 const unsigned /*enum pta_flags*/ flags;
2605 const processor_alias_table[] =
2607 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2608 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2609 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2610 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2611 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2612 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2613 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2614 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2615 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2616 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2617 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2618 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2619 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2621 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2623 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2624 PTA_MMX | PTA_SSE | PTA_SSE2},
2625 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2626 PTA_MMX |PTA_SSE | PTA_SSE2},
2627 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2628 PTA_MMX | PTA_SSE | PTA_SSE2},
2629 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2630 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2631 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2632 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2633 | PTA_CX16 | PTA_NO_SAHF},
2634 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2635 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2636 | PTA_SSSE3 | PTA_CX16},
2637 {"atom", PROCESSOR_ATOM, CPU_ATOM,
2638 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2639 | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
2640 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2641 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2642 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2643 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2644 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2645 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2646 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2647 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2648 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2649 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2650 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2651 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2652 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2653 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2654 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2655 {"x86-64", PROCESSOR_K8, CPU_K8,
2656 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2657 {"k8", PROCESSOR_K8, CPU_K8,
2658 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2659 | PTA_SSE2 | PTA_NO_SAHF},
2660 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2661 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2662 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2663 {"opteron", PROCESSOR_K8, CPU_K8,
2664 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2665 | PTA_SSE2 | PTA_NO_SAHF},
2666 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2667 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2668 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2669 {"athlon64", PROCESSOR_K8, CPU_K8,
2670 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2671 | PTA_SSE2 | PTA_NO_SAHF},
2672 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2673 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2674 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2675 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2676 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2677 | PTA_SSE2 | PTA_NO_SAHF},
2678 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2679 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2680 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2681 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2682 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2683 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2684 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2685 0 /* flags are only used for -march switch. */ },
2686 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2687 PTA_64BIT /* flags are only used for -march switch. */ },
2690 int const pta_size = ARRAY_SIZE (processor_alias_table);
2692 /* Set up prefix/suffix so the error messages refer to either the command
2693 line argument, or the attribute(target). */
2702 prefix = "option(\"";
2707 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2708 SUBTARGET_OVERRIDE_OPTIONS;
2711 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2712 SUBSUBTARGET_OVERRIDE_OPTIONS;
2715 /* -fPIC is the default for x86_64. */
2716 if (TARGET_MACHO && TARGET_64BIT)
2719 /* Set the default values for switches whose default depends on TARGET_64BIT
2720 in case they weren't overwritten by command line options. */
2723 /* Mach-O doesn't support omitting the frame pointer for now. */
2724 if (flag_omit_frame_pointer == 2)
2725 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2726 if (flag_asynchronous_unwind_tables == 2)
2727 flag_asynchronous_unwind_tables = 1;
2728 if (flag_pcc_struct_return == 2)
2729 flag_pcc_struct_return = 0;
2733 if (flag_omit_frame_pointer == 2)
2734 flag_omit_frame_pointer = 0;
2735 if (flag_asynchronous_unwind_tables == 2)
2736 flag_asynchronous_unwind_tables = 0;
2737 if (flag_pcc_struct_return == 2)
2738 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2741 /* Need to check -mtune=generic first. */
2742 if (ix86_tune_string)
2744 if (!strcmp (ix86_tune_string, "generic")
2745 || !strcmp (ix86_tune_string, "i686")
2746 /* As special support for cross compilers we read -mtune=native
2747 as -mtune=generic. With native compilers we won't see the
2748 -mtune=native, as it was changed by the driver. */
2749 || !strcmp (ix86_tune_string, "native"))
2752 ix86_tune_string = "generic64";
2754 ix86_tune_string = "generic32";
2756 /* If this call is for setting the option attribute, allow the
2757 generic32/generic64 that was previously set. */
2758 else if (!main_args_p
2759 && (!strcmp (ix86_tune_string, "generic32")
2760 || !strcmp (ix86_tune_string, "generic64")))
2762 else if (!strncmp (ix86_tune_string, "generic", 7))
2763 error ("bad value (%s) for %stune=%s %s",
2764 ix86_tune_string, prefix, suffix, sw);
2768 if (ix86_arch_string)
2769 ix86_tune_string = ix86_arch_string;
2770 if (!ix86_tune_string)
2772 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2773 ix86_tune_defaulted = 1;
2776 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2777 need to use a sensible tune option. */
2778 if (!strcmp (ix86_tune_string, "generic")
2779 || !strcmp (ix86_tune_string, "x86-64")
2780 || !strcmp (ix86_tune_string, "i686"))
2783 ix86_tune_string = "generic64";
2785 ix86_tune_string = "generic32";
2788 if (ix86_stringop_string)
2790 if (!strcmp (ix86_stringop_string, "rep_byte"))
2791 stringop_alg = rep_prefix_1_byte;
2792 else if (!strcmp (ix86_stringop_string, "libcall"))
2793 stringop_alg = libcall;
2794 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2795 stringop_alg = rep_prefix_4_byte;
2796 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2798 /* rep; movq isn't available in 32-bit code. */
2799 stringop_alg = rep_prefix_8_byte;
2800 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2801 stringop_alg = loop_1_byte;
2802 else if (!strcmp (ix86_stringop_string, "loop"))
2803 stringop_alg = loop;
2804 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2805 stringop_alg = unrolled_loop;
2807 error ("bad value (%s) for %sstringop-strategy=%s %s",
2808 ix86_stringop_string, prefix, suffix, sw);
2810 if (!strcmp (ix86_tune_string, "x86-64"))
2811 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2812 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2813 prefix, suffix, prefix, suffix, prefix, suffix);
2815 if (!ix86_arch_string)
2816 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";
2818 ix86_arch_specified = 1;
2820 if (!strcmp (ix86_arch_string, "generic"))
2821 error ("generic CPU can be used only for %stune=%s %s",
2822 prefix, suffix, sw);
2823 if (!strncmp (ix86_arch_string, "generic", 7))
2824 error ("bad value (%s) for %sarch=%s %s",
2825 ix86_arch_string, prefix, suffix, sw);
2827 /* Validate -mabi= value. */
2828 if (ix86_abi_string)
2830 if (strcmp (ix86_abi_string, "sysv") == 0)
2831 ix86_abi = SYSV_ABI;
2832 else if (strcmp (ix86_abi_string, "ms") == 0)
2835 error ("unknown ABI (%s) for %sabi=%s %s",
2836 ix86_abi_string, prefix, suffix, sw);
2839 ix86_abi = DEFAULT_ABI;
2841 if (ix86_cmodel_string != 0)
2843 if (!strcmp (ix86_cmodel_string, "small"))
2844 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2845 else if (!strcmp (ix86_cmodel_string, "medium"))
2846 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2847 else if (!strcmp (ix86_cmodel_string, "large"))
2848 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2850 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2851 else if (!strcmp (ix86_cmodel_string, "32"))
2852 ix86_cmodel = CM_32;
2853 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2854 ix86_cmodel = CM_KERNEL;
2856 error ("bad value (%s) for %scmodel=%s %s",
2857 ix86_cmodel_string, prefix, suffix, sw);
2861 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2862 use of rip-relative addressing. This eliminates fixups that
2863 would otherwise be needed if this object is to be placed in a
2864 DLL, and is essentially just as efficient as direct addressing. */
2865 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2866 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2867 else if (TARGET_64BIT)
2868 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2870 ix86_cmodel = CM_32;
2872 if (ix86_asm_string != 0)
2875 && !strcmp (ix86_asm_string, "intel"))
2876 ix86_asm_dialect = ASM_INTEL;
2877 else if (!strcmp (ix86_asm_string, "att"))
2878 ix86_asm_dialect = ASM_ATT;
2880 error ("bad value (%s) for %sasm=%s %s",
2881 ix86_asm_string, prefix, suffix, sw);
2883 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2884 error ("code model %qs not supported in the %s bit mode",
2885 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2886 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2887 sorry ("%i-bit mode not compiled in",
2888 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2890 for (i = 0; i < pta_size; i++)
2891 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2893 ix86_schedule = processor_alias_table[i].schedule;
2894 ix86_arch = processor_alias_table[i].processor;
2895 /* Default cpu tuning to the architecture. */
2896 ix86_tune = ix86_arch;
2898 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2899 error ("CPU you selected does not support x86-64 "
2902 if (processor_alias_table[i].flags & PTA_MMX
2903 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2904 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2905 if (processor_alias_table[i].flags & PTA_3DNOW
2906 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2907 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2908 if (processor_alias_table[i].flags & PTA_3DNOW_A
2909 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2910 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2911 if (processor_alias_table[i].flags & PTA_SSE
2912 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2913 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2914 if (processor_alias_table[i].flags & PTA_SSE2
2915 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2916 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2917 if (processor_alias_table[i].flags & PTA_SSE3
2918 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2919 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2920 if (processor_alias_table[i].flags & PTA_SSSE3
2921 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2922 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2923 if (processor_alias_table[i].flags & PTA_SSE4_1
2924 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2925 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2926 if (processor_alias_table[i].flags & PTA_SSE4_2
2927 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2928 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2929 if (processor_alias_table[i].flags & PTA_AVX
2930 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2931 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2932 if (processor_alias_table[i].flags & PTA_FMA
2933 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2934 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2935 if (processor_alias_table[i].flags & PTA_SSE4A
2936 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2937 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2938 if (processor_alias_table[i].flags & PTA_ABM
2939 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2940 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2941 if (processor_alias_table[i].flags & PTA_CX16
2942 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2943 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2944 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2945 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2946 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2947 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2948 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2949 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2950 if (processor_alias_table[i].flags & PTA_MOVBE
2951 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
2952 ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
2953 if (processor_alias_table[i].flags & PTA_AES
2954 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2955 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2956 if (processor_alias_table[i].flags & PTA_PCLMUL
2957 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2958 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2959 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2960 x86_prefetch_sse = true;
2966 error ("bad value (%s) for %sarch=%s %s",
2967 ix86_arch_string, prefix, suffix, sw);
2969 ix86_arch_mask = 1u << ix86_arch;
2970 for (i = 0; i < X86_ARCH_LAST; ++i)
2971 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2973 for (i = 0; i < pta_size; i++)
2974 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2976 ix86_schedule = processor_alias_table[i].schedule;
2977 ix86_tune = processor_alias_table[i].processor;
2978 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2980 if (ix86_tune_defaulted)
2982 ix86_tune_string = "x86-64";
2983 for (i = 0; i < pta_size; i++)
2984 if (! strcmp (ix86_tune_string,
2985 processor_alias_table[i].name))
2987 ix86_schedule = processor_alias_table[i].schedule;
2988 ix86_tune = processor_alias_table[i].processor;
2991 error ("CPU you selected does not support x86-64 "
2994 /* Intel CPUs have always interpreted SSE prefetch instructions as
2995 NOPs; so, we can enable SSE prefetch instructions even when
2996 -mtune (rather than -march) points us to a processor that has them.
2997 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2998 higher processors. */
3000 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
3001 x86_prefetch_sse = true;
3005 error ("bad value (%s) for %stune=%s %s",
3006 ix86_tune_string, prefix, suffix, sw);
3008 ix86_tune_mask = 1u << ix86_tune;
3009 for (i = 0; i < X86_TUNE_LAST; ++i)
3010 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3013 ix86_cost = &ix86_size_cost;
3015 ix86_cost = processor_target_table[ix86_tune].cost;
3017 /* Arrange to set up i386_stack_locals for all functions. */
3018 init_machine_status = ix86_init_machine_status;
3020 /* Validate -mregparm= value. */
3021 if (ix86_regparm_string)
3024 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
3025 i = atoi (ix86_regparm_string);
3026 if (i < 0 || i > REGPARM_MAX)
3027 error ("%sregparm=%d%s is not between 0 and %d",
3028 prefix, i, suffix, REGPARM_MAX);
3033 ix86_regparm = REGPARM_MAX;
3035 /* If the user has provided any of the -malign-* options,
3036 warn and use that value only if -falign-* is not set.
3037 Remove this code in GCC 3.2 or later. */
3038 if (ix86_align_loops_string)
3040 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
3041 prefix, suffix, suffix);
3042 if (align_loops == 0)
3044 i = atoi (ix86_align_loops_string);
3045 if (i < 0 || i > MAX_CODE_ALIGN)
3046 error ("%salign-loops=%d%s is not between 0 and %d",
3047 prefix, i, suffix, MAX_CODE_ALIGN);
3049 align_loops = 1 << i;
3053 if (ix86_align_jumps_string)
3055 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
3056 prefix, suffix, suffix);
3057 if (align_jumps == 0)
3059 i = atoi (ix86_align_jumps_string);
3060 if (i < 0 || i > MAX_CODE_ALIGN)
3061 error ("%salign-loops=%d%s is not between 0 and %d",
3062 prefix, i, suffix, MAX_CODE_ALIGN);
3064 align_jumps = 1 << i;
3068 if (ix86_align_funcs_string)
3070 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
3071 prefix, suffix, suffix);
3072 if (align_functions == 0)
3074 i = atoi (ix86_align_funcs_string);
3075 if (i < 0 || i > MAX_CODE_ALIGN)
3076 error ("%salign-loops=%d%s is not between 0 and %d",
3077 prefix, i, suffix, MAX_CODE_ALIGN);
3079 align_functions = 1 << i;
3083 /* Default align_* from the processor table. */
3084 if (align_loops == 0)
3086 align_loops = processor_target_table[ix86_tune].align_loop;
3087 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
3089 if (align_jumps == 0)
3091 align_jumps = processor_target_table[ix86_tune].align_jump;
3092 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
3094 if (align_functions == 0)
3096 align_functions = processor_target_table[ix86_tune].align_func;
3099 /* Validate -mbranch-cost= value, or provide default. */
3100 ix86_branch_cost = ix86_cost->branch_cost;
3101 if (ix86_branch_cost_string)
3103 i = atoi (ix86_branch_cost_string);
3105 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
3107 ix86_branch_cost = i;
3109 if (ix86_section_threshold_string)
3111 i = atoi (ix86_section_threshold_string);
3113 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
3115 ix86_section_threshold = i;
3118 if (ix86_tls_dialect_string)
3120 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
3121 ix86_tls_dialect = TLS_DIALECT_GNU;
3122 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3123 ix86_tls_dialect = TLS_DIALECT_GNU2;
3124 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3125 ix86_tls_dialect = TLS_DIALECT_SUN;
3127 error ("bad value (%s) for %stls-dialect=%s %s",
3128 ix86_tls_dialect_string, prefix, suffix, sw);
3131 if (ix87_precision_string)
3133 i = atoi (ix87_precision_string);
3134 if (i != 32 && i != 64 && i != 80)
3135 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3140 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3142 /* Enable by default the SSE and MMX builtins. Do allow the user to
3143 explicitly disable any of these. In particular, disabling SSE and
3144 MMX for kernel code is extremely useful. */
3145 if (!ix86_arch_specified)
3147 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3148 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3151 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3155 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3157 if (!ix86_arch_specified)
3159 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3161 /* i386 ABI does not specify red zone. It still makes sense to use it
3162 when programmer takes care to stack from being destroyed. */
3163 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3164 target_flags |= MASK_NO_RED_ZONE;
3167 /* Keep nonleaf frame pointers. */
3168 if (flag_omit_frame_pointer)
3169 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3170 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3171 flag_omit_frame_pointer = 1;
3173 /* If we're doing fast math, we don't care about comparison order
3174 wrt NaNs. This lets us use a shorter comparison sequence. */
3175 if (flag_finite_math_only)
3176 target_flags &= ~MASK_IEEE_FP;
3178 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3179 since the insns won't need emulation. */
3180 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3181 target_flags &= ~MASK_NO_FANCY_MATH_387;
3183 /* Likewise, if the target doesn't have a 387, or we've specified
3184 software floating point, don't use 387 inline intrinsics. */
3186 target_flags |= MASK_NO_FANCY_MATH_387;
3188 /* Turn on MMX builtins for -msse. */
3191 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3192 x86_prefetch_sse = true;
3195 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3196 if (TARGET_SSE4_2 || TARGET_ABM)
3197 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3199 /* Validate -mpreferred-stack-boundary= value or default it to
3200 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3201 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3202 if (ix86_preferred_stack_boundary_string)
3204 i = atoi (ix86_preferred_stack_boundary_string);
3205 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3206 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3207 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3209 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3212 /* Set the default value for -mstackrealign. */
3213 if (ix86_force_align_arg_pointer == -1)
3214 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3216 /* Validate -mincoming-stack-boundary= value or default it to
3217 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3218 if (ix86_force_align_arg_pointer)
3219 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3221 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3222 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3223 if (ix86_incoming_stack_boundary_string)
3225 i = atoi (ix86_incoming_stack_boundary_string);
3226 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3227 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3228 i, TARGET_64BIT ? 4 : 2);
3231 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3232 ix86_incoming_stack_boundary
3233 = ix86_user_incoming_stack_boundary;
3237 /* Accept -msseregparm only if at least SSE support is enabled. */
3238 if (TARGET_SSEREGPARM
3240 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3242 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3243 if (ix86_fpmath_string != 0)
3245 if (! strcmp (ix86_fpmath_string, "387"))
3246 ix86_fpmath = FPMATH_387;
3247 else if (! strcmp (ix86_fpmath_string, "sse"))
3251 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3252 ix86_fpmath = FPMATH_387;
3255 ix86_fpmath = FPMATH_SSE;
3257 else if (! strcmp (ix86_fpmath_string, "387,sse")
3258 || ! strcmp (ix86_fpmath_string, "387+sse")
3259 || ! strcmp (ix86_fpmath_string, "sse,387")
3260 || ! strcmp (ix86_fpmath_string, "sse+387")
3261 || ! strcmp (ix86_fpmath_string, "both"))
3265 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3266 ix86_fpmath = FPMATH_387;
3268 else if (!TARGET_80387)
3270 warning (0, "387 instruction set disabled, using SSE arithmetics");
3271 ix86_fpmath = FPMATH_SSE;
3274 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3277 error ("bad value (%s) for %sfpmath=%s %s",
3278 ix86_fpmath_string, prefix, suffix, sw);
3281 /* If the i387 is disabled, then do not return values in it. */
3283 target_flags &= ~MASK_FLOAT_RETURNS;
3285 /* Use external vectorized library in vectorizing intrinsics. */
3286 if (ix86_veclibabi_string)
3288 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3289 ix86_veclib_handler = ix86_veclibabi_svml;
3290 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3291 ix86_veclib_handler = ix86_veclibabi_acml;
3293 error ("unknown vectorization library ABI type (%s) for "
3294 "%sveclibabi=%s %s", ix86_veclibabi_string,
3295 prefix, suffix, sw);
3298 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3299 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3301 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3303 /* ??? Unwind info is not correct around the CFG unless either a frame
3304 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3305 unwind info generation to be aware of the CFG and propagating states
3307 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3308 || flag_exceptions || flag_non_call_exceptions)
3309 && flag_omit_frame_pointer
3310 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3312 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3313 warning (0, "unwind tables currently require either a frame pointer "
3314 "or %saccumulate-outgoing-args%s for correctness",
3316 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3319 /* If stack probes are required, the space used for large function
3320 arguments on the stack must also be probed, so enable
3321 -maccumulate-outgoing-args so this happens in the prologue. */
3322 if (TARGET_STACK_PROBE
3323 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3325 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3326 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3327 "for correctness", prefix, suffix);
3328 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3331 /* For sane SSE instruction set generation we need fcomi instruction.
3332 It is safe to enable all CMOVE instructions. */
3336 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3339 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3340 p = strchr (internal_label_prefix, 'X');
3341 internal_label_prefix_len = p - internal_label_prefix;
3345 /* When scheduling description is not available, disable scheduler pass
3346 so it won't slow down the compilation and make x87 code slower. */
3347 if (!TARGET_SCHEDULE)
3348 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3350 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3351 set_param_value ("simultaneous-prefetches",
3352 ix86_cost->simultaneous_prefetches);
3353 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3354 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3355 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3356 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3357 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3358 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3360 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3361 can be optimized to ap = __builtin_next_arg (0). */
3363 targetm.expand_builtin_va_start = NULL;
3367 ix86_gen_leave = gen_leave_rex64;
3368 ix86_gen_pop1 = gen_popdi1;
3369 ix86_gen_add3 = gen_adddi3;
3370 ix86_gen_sub3 = gen_subdi3;
3371 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3372 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3373 ix86_gen_monitor = gen_sse3_monitor64;
3374 ix86_gen_andsp = gen_anddi3;
3378 ix86_gen_leave = gen_leave;
3379 ix86_gen_pop1 = gen_popsi1;
3380 ix86_gen_add3 = gen_addsi3;
3381 ix86_gen_sub3 = gen_subsi3;
3382 ix86_gen_sub3_carry = gen_subsi3_carry;
3383 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3384 ix86_gen_monitor = gen_sse3_monitor;
3385 ix86_gen_andsp = gen_andsi3;
3389 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3391 target_flags |= MASK_CLD & ~target_flags_explicit;
3394 /* Save the initial options in case the user does function specific options */
3396 target_option_default_node = target_option_current_node
3397 = build_target_option_node ();
3400 /* Update register usage after having seen the compiler flags. */
3403 ix86_conditional_register_usage (void)
3408 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3410 if (fixed_regs[i] > 1)
3411 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3412 if (call_used_regs[i] > 1)
3413 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3416 /* The PIC register, if it exists, is fixed. */
3417 j = PIC_OFFSET_TABLE_REGNUM;
3418 if (j != INVALID_REGNUM)
3419 fixed_regs[j] = call_used_regs[j] = 1;
3421 /* The MS_ABI changes the set of call-used registers. */
3422 if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
3424 call_used_regs[SI_REG] = 0;
3425 call_used_regs[DI_REG] = 0;
3426 call_used_regs[XMM6_REG] = 0;
3427 call_used_regs[XMM7_REG] = 0;
3428 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3429 call_used_regs[i] = 0;
3432 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3433 other call-clobbered regs for 64-bit. */
3436 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3438 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3439 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3440 && call_used_regs[i])
3441 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3444 /* If MMX is disabled, squash the registers. */
3446 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3447 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3448 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3450 /* If SSE is disabled, squash the registers. */
3452 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3453 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3454 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3456 /* If the FPU is disabled, squash the registers. */
3457 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3458 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3459 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3460 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3462 /* If 32-bit, squash the 64-bit registers. */
3465 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3467 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3473 /* Save the current options */
3476 ix86_function_specific_save (struct cl_target_option *ptr)
3478 ptr->arch = ix86_arch;
3479 ptr->schedule = ix86_schedule;
3480 ptr->tune = ix86_tune;
3481 ptr->fpmath = ix86_fpmath;
3482 ptr->branch_cost = ix86_branch_cost;
3483 ptr->tune_defaulted = ix86_tune_defaulted;
3484 ptr->arch_specified = ix86_arch_specified;
3485 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3486 ptr->target_flags_explicit = target_flags_explicit;
3488 /* The fields are char but the variables are not; make sure the
3489 values fit in the fields. */
3490 gcc_assert (ptr->arch == ix86_arch);
3491 gcc_assert (ptr->schedule == ix86_schedule);
3492 gcc_assert (ptr->tune == ix86_tune);
3493 gcc_assert (ptr->fpmath == ix86_fpmath);
3494 gcc_assert (ptr->branch_cost == ix86_branch_cost);
3497 /* Restore the current options */
3500 ix86_function_specific_restore (struct cl_target_option *ptr)
3502 enum processor_type old_tune = ix86_tune;
3503 enum processor_type old_arch = ix86_arch;
3504 unsigned int ix86_arch_mask, ix86_tune_mask;
3507 ix86_arch = (enum processor_type) ptr->arch;
3508 ix86_schedule = (enum attr_cpu) ptr->schedule;
3509 ix86_tune = (enum processor_type) ptr->tune;
3510 ix86_fpmath = (enum fpmath_unit) ptr->fpmath;
3511 ix86_branch_cost = ptr->branch_cost;
3512 ix86_tune_defaulted = ptr->tune_defaulted;
3513 ix86_arch_specified = ptr->arch_specified;
3514 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3515 target_flags_explicit = ptr->target_flags_explicit;
3517 /* Recreate the arch feature tests if the arch changed */
3518 if (old_arch != ix86_arch)
3520 ix86_arch_mask = 1u << ix86_arch;
3521 for (i = 0; i < X86_ARCH_LAST; ++i)
3522 ix86_arch_features[i]
3523 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3526 /* Recreate the tune optimization tests */
3527 if (old_tune != ix86_tune)
3529 ix86_tune_mask = 1u << ix86_tune;
3530 for (i = 0; i < X86_TUNE_LAST; ++i)
3531 ix86_tune_features[i]
3532 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3536 /* Print the current options */
3539 ix86_function_specific_print (FILE *file, int indent,
3540 struct cl_target_option *ptr)
3543 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3544 NULL, NULL, NULL, false);
3546 fprintf (file, "%*sarch = %d (%s)\n",
3549 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3550 ? cpu_names[ptr->arch]
3553 fprintf (file, "%*stune = %d (%s)\n",
3556 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3557 ? cpu_names[ptr->tune]
3560 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3561 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3562 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3563 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3567 fprintf (file, "%*s%s\n", indent, "", target_string);
3568 free (target_string);
3573 /* Inner function to process the attribute((target(...))), take an argument and
3574 set the current options from the argument. If we have a list, recursively go
3578 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3583 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3584 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3585 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3586 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3601 enum ix86_opt_type type;
3606 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3607 IX86_ATTR_ISA ("abm", OPT_mabm),
3608 IX86_ATTR_ISA ("aes", OPT_maes),
3609 IX86_ATTR_ISA ("avx", OPT_mavx),
3610 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3611 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3612 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3613 IX86_ATTR_ISA ("sse", OPT_msse),
3614 IX86_ATTR_ISA ("sse2", OPT_msse2),
3615 IX86_ATTR_ISA ("sse3", OPT_msse3),
3616 IX86_ATTR_ISA ("sse4", OPT_msse4),
3617 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3618 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3619 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3620 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3622 /* string options */
3623 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3624 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3625 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3628 IX86_ATTR_YES ("cld",
3632 IX86_ATTR_NO ("fancy-math-387",
3633 OPT_mfancy_math_387,
3634 MASK_NO_FANCY_MATH_387),
3636 IX86_ATTR_YES ("ieee-fp",
3640 IX86_ATTR_YES ("inline-all-stringops",
3641 OPT_minline_all_stringops,
3642 MASK_INLINE_ALL_STRINGOPS),
3644 IX86_ATTR_YES ("inline-stringops-dynamically",
3645 OPT_minline_stringops_dynamically,
3646 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3648 IX86_ATTR_NO ("align-stringops",
3649 OPT_mno_align_stringops,
3650 MASK_NO_ALIGN_STRINGOPS),
3652 IX86_ATTR_YES ("recip",
3658 /* If this is a list, recurse to get the options. */
3659 if (TREE_CODE (args) == TREE_LIST)
3663 for (; args; args = TREE_CHAIN (args))
3664 if (TREE_VALUE (args)
3665 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3671 else if (TREE_CODE (args) != STRING_CST)
3674 /* Handle multiple arguments separated by commas. */
3675 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3677 while (next_optstr && *next_optstr != '\0')
3679 char *p = next_optstr;
3681 char *comma = strchr (next_optstr, ',');
3682 const char *opt_string;
3683 size_t len, opt_len;
3688 enum ix86_opt_type type = ix86_opt_unknown;
3694 len = comma - next_optstr;
3695 next_optstr = comma + 1;
3703 /* Recognize no-xxx. */
3704 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3713 /* Find the option. */
3716 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3718 type = attrs[i].type;
3719 opt_len = attrs[i].len;
3720 if (ch == attrs[i].string[0]
3721 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3722 && memcmp (p, attrs[i].string, opt_len) == 0)
3725 mask = attrs[i].mask;
3726 opt_string = attrs[i].string;
3731 /* Process the option. */
3734 error ("attribute(target(\"%s\")) is unknown", orig_p);
3738 else if (type == ix86_opt_isa)
3739 ix86_handle_option (opt, p, opt_set_p);
3741 else if (type == ix86_opt_yes || type == ix86_opt_no)
3743 if (type == ix86_opt_no)
3744 opt_set_p = !opt_set_p;
3747 target_flags |= mask;
3749 target_flags &= ~mask;
3752 else if (type == ix86_opt_str)
3756 error ("option(\"%s\") was already specified", opt_string);
3760 p_strings[opt] = xstrdup (p + opt_len);
3770 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3773 ix86_valid_target_attribute_tree (tree args)
3775 const char *orig_arch_string = ix86_arch_string;
3776 const char *orig_tune_string = ix86_tune_string;
3777 const char *orig_fpmath_string = ix86_fpmath_string;
3778 int orig_tune_defaulted = ix86_tune_defaulted;
3779 int orig_arch_specified = ix86_arch_specified;
3780 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3783 struct cl_target_option *def
3784 = TREE_TARGET_OPTION (target_option_default_node);
3786 /* Process each of the options on the chain. */
3787 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3790 /* If the changed options are different from the default, rerun override_options,
3791 and then save the options away. The string options are are attribute options,
3792 and will be undone when we copy the save structure. */
3793 if (ix86_isa_flags != def->ix86_isa_flags
3794 || target_flags != def->target_flags
3795 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3796 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3797 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3799 /* If we are using the default tune= or arch=, undo the string assigned,
3800 and use the default. */
3801 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3802 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3803 else if (!orig_arch_specified)
3804 ix86_arch_string = NULL;
3806 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3807 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3808 else if (orig_tune_defaulted)
3809 ix86_tune_string = NULL;
3811 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3812 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3813 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3814 else if (!TARGET_64BIT && TARGET_SSE)
3815 ix86_fpmath_string = "sse,387";
3817 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3818 override_options (false);
3820 /* Add any builtin functions with the new isa if any. */
3821 ix86_add_new_builtins (ix86_isa_flags);
3823 /* Save the current options unless we are validating options for
3825 t = build_target_option_node ();
3827 ix86_arch_string = orig_arch_string;
3828 ix86_tune_string = orig_tune_string;
3829 ix86_fpmath_string = orig_fpmath_string;
3831 /* Free up memory allocated to hold the strings */
3832 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3833 if (option_strings[i])
3834 free (option_strings[i]);
3840 /* Hook to validate attribute((target("string"))). */
3843 ix86_valid_target_attribute_p (tree fndecl,
3844 tree ARG_UNUSED (name),
3846 int ARG_UNUSED (flags))
3848 struct cl_target_option cur_target;
3850 tree old_optimize = build_optimization_node ();
3851 tree new_target, new_optimize;
3852 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3854 /* If the function changed the optimization levels as well as setting target
3855 options, start with the optimizations specified. */
3856 if (func_optimize && func_optimize != old_optimize)
3857 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3859 /* The target attributes may also change some optimization flags, so update
3860 the optimization options if necessary. */
3861 cl_target_option_save (&cur_target);
3862 new_target = ix86_valid_target_attribute_tree (args);
3863 new_optimize = build_optimization_node ();
3870 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3872 if (old_optimize != new_optimize)
3873 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3876 cl_target_option_restore (&cur_target);
3878 if (old_optimize != new_optimize)
3879 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3885 /* Hook to determine if one function can safely inline another. */
3888 ix86_can_inline_p (tree caller, tree callee)
3891 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3892 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3894 /* If callee has no option attributes, then it is ok to inline. */
3898 /* If caller has no option attributes, but callee does then it is not ok to
3900 else if (!caller_tree)
3905 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3906 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3908 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
3909 can inline a SSE2 function but a SSE2 function can't inline a SSE4
3911 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3912 != callee_opts->ix86_isa_flags)
3915 /* See if we have the same non-isa options. */
3916 else if (caller_opts->target_flags != callee_opts->target_flags)
3919 /* See if arch, tune, etc. are the same. */
3920 else if (caller_opts->arch != callee_opts->arch)
3923 else if (caller_opts->tune != callee_opts->tune)
3926 else if (caller_opts->fpmath != callee_opts->fpmath)
3929 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3940 /* Remember the last target of ix86_set_current_function. */
3941 static GTY(()) tree ix86_previous_fndecl;
3943 /* Establish appropriate back-end context for processing the function
3944 FNDECL. The argument might be NULL to indicate processing at top
3945 level, outside of any function scope. */
3947 ix86_set_current_function (tree fndecl)
3949 /* Only change the context if the function changes. This hook is called
3950 several times in the course of compiling a function, and we don't want to
3951 slow things down too much or call target_reinit when it isn't safe. */
3952 if (fndecl && fndecl != ix86_previous_fndecl)
3954 tree old_tree = (ix86_previous_fndecl
3955 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3958 tree new_tree = (fndecl
3959 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3962 ix86_previous_fndecl = fndecl;
3963 if (old_tree == new_tree)
3968 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3974 struct cl_target_option *def
3975 = TREE_TARGET_OPTION (target_option_current_node);
3977 cl_target_option_restore (def);
3984 /* Return true if this goes in large data/bss. */
3987 ix86_in_large_data_p (tree exp)
3989 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3992 /* Functions are never large data. */
3993 if (TREE_CODE (exp) == FUNCTION_DECL)
3996 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3998 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3999 if (strcmp (section, ".ldata") == 0
4000 || strcmp (section, ".lbss") == 0)
4006 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
4008 /* If this is an incomplete type with size 0, then we can't put it
4009 in data because it might be too big when completed. */
4010 if (!size || size > ix86_section_threshold)
4017 /* Switch to the appropriate section for output of DECL.
4018 DECL is either a `VAR_DECL' node or a constant of some sort.
4019 RELOC indicates whether forming the initial value of DECL requires
4020 link-time relocations. */
4022 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
4026 x86_64_elf_select_section (tree decl, int reloc,
4027 unsigned HOST_WIDE_INT align)
4029 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4030 && ix86_in_large_data_p (decl))
4032 const char *sname = NULL;
4033 unsigned int flags = SECTION_WRITE;
4034 switch (categorize_decl_for_section (decl, reloc))
4039 case SECCAT_DATA_REL:
4040 sname = ".ldata.rel";
4042 case SECCAT_DATA_REL_LOCAL:
4043 sname = ".ldata.rel.local";
4045 case SECCAT_DATA_REL_RO:
4046 sname = ".ldata.rel.ro";
4048 case SECCAT_DATA_REL_RO_LOCAL:
4049 sname = ".ldata.rel.ro.local";
4053 flags |= SECTION_BSS;
4056 case SECCAT_RODATA_MERGE_STR:
4057 case SECCAT_RODATA_MERGE_STR_INIT:
4058 case SECCAT_RODATA_MERGE_CONST:
4062 case SECCAT_SRODATA:
4069 /* We don't split these for medium model. Place them into
4070 default sections and hope for best. */
4072 case SECCAT_EMUTLS_VAR:
4073 case SECCAT_EMUTLS_TMPL:
4078 /* We might get called with string constants, but get_named_section
4079 doesn't like them as they are not DECLs. Also, we need to set
4080 flags in that case. */
4082 return get_section (sname, flags, NULL);
4083 return get_named_section (decl, sname, reloc);
4086 return default_elf_select_section (decl, reloc, align);
4089 /* Build up a unique section name, expressed as a
4090 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4091 RELOC indicates whether the initial value of EXP requires
4092 link-time relocations. */
4094 static void ATTRIBUTE_UNUSED
4095 x86_64_elf_unique_section (tree decl, int reloc)
4097 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4098 && ix86_in_large_data_p (decl))
4100 const char *prefix = NULL;
4101 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4102 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
4104 switch (categorize_decl_for_section (decl, reloc))
4107 case SECCAT_DATA_REL:
4108 case SECCAT_DATA_REL_LOCAL:
4109 case SECCAT_DATA_REL_RO:
4110 case SECCAT_DATA_REL_RO_LOCAL:
4111 prefix = one_only ? ".ld" : ".ldata";
4114 prefix = one_only ? ".lb" : ".lbss";
4117 case SECCAT_RODATA_MERGE_STR:
4118 case SECCAT_RODATA_MERGE_STR_INIT:
4119 case SECCAT_RODATA_MERGE_CONST:
4120 prefix = one_only ? ".lr" : ".lrodata";
4122 case SECCAT_SRODATA:
4129 /* We don't split these for medium model. Place them into
4130 default sections and hope for best. */
4132 case SECCAT_EMUTLS_VAR:
4133 prefix = targetm.emutls.var_section;
4135 case SECCAT_EMUTLS_TMPL:
4136 prefix = targetm.emutls.tmpl_section;
4141 const char *name, *linkonce;
4144 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4145 name = targetm.strip_name_encoding (name);
4147 /* If we're using one_only, then there needs to be a .gnu.linkonce
4148 prefix to the section name. */
4149 linkonce = one_only ? ".gnu.linkonce" : "";
4151 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4153 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4157 default_unique_section (decl, reloc);
4160 #ifdef COMMON_ASM_OP
4161 /* This says how to output assembler code to declare an
4162 uninitialized external linkage data object.
4164 For medium model x86-64 we need to use .largecomm opcode for
4167 x86_elf_aligned_common (FILE *file,
4168 const char *name, unsigned HOST_WIDE_INT size,
4171 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4172 && size > (unsigned int)ix86_section_threshold)
4173 fputs (".largecomm\t", file);
4175 fputs (COMMON_ASM_OP, file);
4176 assemble_name (file, name);
4177 fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
4178 size, align / BITS_PER_UNIT);
4182 /* Utility function for targets to use in implementing
4183 ASM_OUTPUT_ALIGNED_BSS. */
4186 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4187 const char *name, unsigned HOST_WIDE_INT size,
4190 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4191 && size > (unsigned int)ix86_section_threshold)
4192 switch_to_section (get_named_section (decl, ".lbss", 0));
4194 switch_to_section (bss_section);
4195 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4196 #ifdef ASM_DECLARE_OBJECT_NAME
4197 last_assemble_variable_decl = decl;
4198 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4200 /* Standard thing is just output label for the object. */
4201 ASM_OUTPUT_LABEL (file, name);
4202 #endif /* ASM_DECLARE_OBJECT_NAME */
4203 ASM_OUTPUT_SKIP (file, size ? size : 1);
4207 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4209 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4210 make the problem with not enough registers even worse. */
4211 #ifdef INSN_SCHEDULING
4213 flag_schedule_insns = 0;
4217 /* The Darwin libraries never set errno, so we might as well
4218 avoid calling them when that's the only reason we would. */
4219 flag_errno_math = 0;
4221 /* The default values of these switches depend on the TARGET_64BIT
4222 that is not known at this moment. Mark these values with 2 and
4223 let user the to override these. In case there is no command line option
4224 specifying them, we will set the defaults in override_options. */
4226 flag_omit_frame_pointer = 2;
4227 flag_pcc_struct_return = 2;
4228 flag_asynchronous_unwind_tables = 2;
4229 flag_vect_cost_model = 1;
4230 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4231 SUBTARGET_OPTIMIZATION_OPTIONS;
4235 /* Decide whether we can make a sibling call to a function. DECL is the
4236 declaration of the function being targeted by the call and EXP is the
4237 CALL_EXPR representing the call. */
4240 ix86_function_ok_for_sibcall (tree decl, tree exp)
4242 tree type, decl_or_type;
4245 /* If we are generating position-independent code, we cannot sibcall
4246 optimize any indirect call, or a direct call to a global function,
4247 as the PLT requires %ebx be live. */
4248 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4251 /* If we need to align the outgoing stack, then sibcalling would
4252 unalign the stack, which may break the called function. */
4253 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4258 decl_or_type = decl;
4259 type = TREE_TYPE (decl);
4263 /* We're looking at the CALL_EXPR, we need the type of the function. */
4264 type = CALL_EXPR_FN (exp); /* pointer expression */
4265 type = TREE_TYPE (type); /* pointer type */
4266 type = TREE_TYPE (type); /* function type */
4267 decl_or_type = type;
4270 /* Check that the return value locations are the same. Like
4271 if we are returning floats on the 80387 register stack, we cannot
4272 make a sibcall from a function that doesn't return a float to a
4273 function that does or, conversely, from a function that does return
4274 a float to a function that doesn't; the necessary stack adjustment
4275 would not be executed. This is also the place we notice
4276 differences in the return value ABI. Note that it is ok for one
4277 of the functions to have void return type as long as the return
4278 value of the other is passed in a register. */
4279 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4280 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4282 if (STACK_REG_P (a) || STACK_REG_P (b))
4284 if (!rtx_equal_p (a, b))
4287 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4289 else if (!rtx_equal_p (a, b))
4294 /* The SYSV ABI has more call-clobbered registers;
4295 disallow sibcalls from MS to SYSV. */
4296 if (cfun->machine->call_abi == MS_ABI
4297 && ix86_function_type_abi (type) == SYSV_ABI)
4302 /* If this call is indirect, we'll need to be able to use a
4303 call-clobbered register for the address of the target function.
4304 Make sure that all such registers are not used for passing
4305 parameters. Note that DLLIMPORT functions are indirect. */
4307 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4309 if (ix86_function_regparm (type, NULL) >= 3)
4311 /* ??? Need to count the actual number of registers to be used,
4312 not the possible number of registers. Fix later. */
4318 /* Otherwise okay. That also includes certain types of indirect calls. */
4322 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4323 calling convention attributes;
4324 arguments as in struct attribute_spec.handler. */
4327 ix86_handle_cconv_attribute (tree *node, tree name,
4329 int flags ATTRIBUTE_UNUSED,
4332 if (TREE_CODE (*node) != FUNCTION_TYPE
4333 && TREE_CODE (*node) != METHOD_TYPE
4334 && TREE_CODE (*node) != FIELD_DECL
4335 && TREE_CODE (*node) != TYPE_DECL)
4337 warning (OPT_Wattributes, "%qE attribute only applies to functions",
4339 *no_add_attrs = true;
4343 /* Can combine regparm with all attributes but fastcall. */
4344 if (is_attribute_p ("regparm", name))
4348 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4350 error ("fastcall and regparm attributes are not compatible");
4353 cst = TREE_VALUE (args);
4354 if (TREE_CODE (cst) != INTEGER_CST)
4356 warning (OPT_Wattributes,
4357 "%qE attribute requires an integer constant argument",
4359 *no_add_attrs = true;
4361 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4363 warning (OPT_Wattributes, "argument to %qE attribute larger than %d",
4365 *no_add_attrs = true;
4373 /* Do not warn when emulating the MS ABI. */
4374 if (TREE_CODE (*node) != FUNCTION_TYPE
4375 || ix86_function_type_abi (*node) != MS_ABI)
4376 warning (OPT_Wattributes, "%qE attribute ignored",
4378 *no_add_attrs = true;
4382 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4383 if (is_attribute_p ("fastcall", name))
4385 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4387 error ("fastcall and cdecl attributes are not compatible");
4389 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4391 error ("fastcall and stdcall attributes are not compatible");
4393 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4395 error ("fastcall and regparm attributes are not compatible");
4399 /* Can combine stdcall with fastcall (redundant), regparm and
4401 else if (is_attribute_p ("stdcall", name))
4403 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4405 error ("stdcall and cdecl attributes are not compatible");
4407 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4409 error ("stdcall and fastcall attributes are not compatible");
4413 /* Can combine cdecl with regparm and sseregparm. */
4414 else if (is_attribute_p ("cdecl", name))
4416 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4418 error ("stdcall and cdecl attributes are not compatible");
4420 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4422 error ("fastcall and cdecl attributes are not compatible");
4426 /* Can combine sseregparm with all attributes. */
4431 /* Return 0 if the attributes for two types are incompatible, 1 if they
4432 are compatible, and 2 if they are nearly compatible (which causes a
4433 warning to be generated). */
4436 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4438 /* Check for mismatch of non-default calling convention. */
4439 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4441 if (TREE_CODE (type1) != FUNCTION_TYPE
4442 && TREE_CODE (type1) != METHOD_TYPE)
4445 /* Check for mismatched fastcall/regparm types. */
4446 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4447 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4448 || (ix86_function_regparm (type1, NULL)
4449 != ix86_function_regparm (type2, NULL)))
4452 /* Check for mismatched sseregparm types. */
4453 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4454 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4457 /* Check for mismatched return types (cdecl vs stdcall). */
4458 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4459 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4465 /* Return the regparm value for a function with the indicated TYPE and DECL.
4466 DECL may be NULL when calling function indirectly
4467 or considering a libcall. */
4470 ix86_function_regparm (const_tree type, const_tree decl)
4475 static bool error_issued;
4478 return (ix86_function_type_abi (type) == SYSV_ABI
4479 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4481 regparm = ix86_regparm;
4482 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4486 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4488 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4490 /* We can't use regparm(3) for nested functions because
4491 these pass static chain pointer in %ecx register. */
4492 if (!error_issued && regparm == 3
4493 && decl_function_context (decl)
4494 && !DECL_NO_STATIC_CHAIN (decl))
4496 error ("nested functions are limited to 2 register parameters");
4497 error_issued = true;
4505 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4508 /* Use register calling convention for local functions when possible. */
4510 && TREE_CODE (decl) == FUNCTION_DECL
4514 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4515 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4518 int local_regparm, globals = 0, regno;
4521 /* Make sure no regparm register is taken by a
4522 fixed register variable. */
4523 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4524 if (fixed_regs[local_regparm])
4527 /* We can't use regparm(3) for nested functions as these use
4528 static chain pointer in third argument. */
4529 if (local_regparm == 3
4530 && decl_function_context (decl)
4531 && !DECL_NO_STATIC_CHAIN (decl))
4534 /* If the function realigns its stackpointer, the prologue will
4535 clobber %ecx. If we've already generated code for the callee,
4536 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4537 scanning the attributes for the self-realigning property. */
4538 f = DECL_STRUCT_FUNCTION (decl);
4539 /* Since current internal arg pointer won't conflict with
4540 parameter passing regs, so no need to change stack
4541 realignment and adjust regparm number.
4543 Each fixed register usage increases register pressure,
4544 so less registers should be used for argument passing.
4545 This functionality can be overriden by an explicit
4547 for (regno = 0; regno <= DI_REG; regno++)
4548 if (fixed_regs[regno])
4552 = globals < local_regparm ? local_regparm - globals : 0;
4554 if (local_regparm > regparm)
4555 regparm = local_regparm;
4562 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4563 DFmode (2) arguments in SSE registers for a function with the
4564 indicated TYPE and DECL. DECL may be NULL when calling function
4565 indirectly or considering a libcall. Otherwise return 0. */
4568 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4570 gcc_assert (!TARGET_64BIT);
4572 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4573 by the sseregparm attribute. */
4574 if (TARGET_SSEREGPARM
4575 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4582 error ("Calling %qD with attribute sseregparm without "
4583 "SSE/SSE2 enabled", decl);
4585 error ("Calling %qT with attribute sseregparm without "
4586 "SSE/SSE2 enabled", type);
4594 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4595 (and DFmode for SSE2) arguments in SSE registers. */
4596 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4598 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4599 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4601 return TARGET_SSE2 ? 2 : 1;
4607 /* Return true if EAX is live at the start of the function. Used by
4608 ix86_expand_prologue to determine if we need special help before
4609 calling allocate_stack_worker. */
4612 ix86_eax_live_at_start_p (void)
4614 /* Cheat. Don't bother working forward from ix86_function_regparm
4615 to the function type to whether an actual argument is located in
4616 eax. Instead just look at cfg info, which is still close enough
4617 to correct at this point. This gives false positives for broken
4618 functions that might use uninitialized data that happens to be
4619 allocated in eax, but who cares? */
4620 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4623 /* Value is the number of bytes of arguments automatically
4624 popped when returning from a subroutine call.
4625 FUNDECL is the declaration node of the function (as a tree),
4626 FUNTYPE is the data type of the function (as a tree),
4627 or for a library call it is an identifier node for the subroutine name.
4628 SIZE is the number of bytes of arguments passed on the stack.
4630 On the 80386, the RTD insn may be used to pop them if the number
4631 of args is fixed, but if the number is variable then the caller
4632 must pop them all. RTD can't be used for library calls now
4633 because the library is compiled with the Unix compiler.
4634 Use of RTD is a selectable option, since it is incompatible with
4635 standard Unix calling sequences. If the option is not selected,
4636 the caller must always pop the args.
4638 The attribute stdcall is equivalent to RTD on a per module basis. */
4641 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4645 /* None of the 64-bit ABIs pop arguments. */
4649 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4651 /* Cdecl functions override -mrtd, and never pop the stack. */
4652 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4654 /* Stdcall and fastcall functions will pop the stack if not
4656 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4657 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4660 if (rtd && ! stdarg_p (funtype))
4664 /* Lose any fake structure return argument if it is passed on the stack. */
4665 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4666 && !KEEP_AGGREGATE_RETURN_POINTER)
4668 int nregs = ix86_function_regparm (funtype, fundecl);
4670 return GET_MODE_SIZE (Pmode);
4676 /* Argument support functions. */
4678 /* Return true when register may be used to pass function parameters. */
4680 ix86_function_arg_regno_p (int regno)
4683 const int *parm_regs;
4688 return (regno < REGPARM_MAX
4689 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4691 return (regno < REGPARM_MAX
4692 || (TARGET_MMX && MMX_REGNO_P (regno)
4693 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4694 || (TARGET_SSE && SSE_REGNO_P (regno)
4695 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4700 if (SSE_REGNO_P (regno) && TARGET_SSE)
4705 if (TARGET_SSE && SSE_REGNO_P (regno)
4706 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4710 /* TODO: The function should depend on current function ABI but
4711 builtins.c would need updating then. Therefore we use the
4714 /* RAX is used as hidden argument to va_arg functions. */
4715 if (ix86_abi == SYSV_ABI && regno == AX_REG)
4718 if (ix86_abi == MS_ABI)
4719 parm_regs = x86_64_ms_abi_int_parameter_registers;
4721 parm_regs = x86_64_int_parameter_registers;
4722 for (i = 0; i < (ix86_abi == MS_ABI
4723 ? X86_64_MS_REGPARM_MAX : X86_64_REGPARM_MAX); i++)
4724 if (regno == parm_regs[i])
4729 /* Return if we do not know how to pass TYPE solely in registers. */
4732 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4734 if (must_pass_in_stack_var_size_or_pad (mode, type))
4737 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4738 The layout_type routine is crafty and tries to trick us into passing
4739 currently unsupported vector types on the stack by using TImode. */
4740 return (!TARGET_64BIT && mode == TImode
4741 && type && TREE_CODE (type) != VECTOR_TYPE);
4744 /* It returns the size, in bytes, of the area reserved for arguments passed
4745 in registers for the function represented by fndecl dependent to the used
4748 ix86_reg_parm_stack_space (const_tree fndecl)
4750 enum calling_abi call_abi = SYSV_ABI;
4751 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4752 call_abi = ix86_function_abi (fndecl);
4754 call_abi = ix86_function_type_abi (fndecl);
4755 if (call_abi == MS_ABI)
4760 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4763 ix86_function_type_abi (const_tree fntype)
4765 if (TARGET_64BIT && fntype != NULL)
4767 enum calling_abi abi = ix86_abi;
4768 if (abi == SYSV_ABI)
4770 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
4773 else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
4780 static enum calling_abi
4781 ix86_function_abi (const_tree fndecl)
4785 return ix86_function_type_abi (TREE_TYPE (fndecl));
4788 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4791 ix86_cfun_abi (void)
4793 if (! cfun || ! TARGET_64BIT)
4795 return cfun->machine->call_abi;
4799 extern void init_regs (void);
4801 /* Implementation of call abi switching target hook. Specific to FNDECL
4802 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4803 for more details. */
4805 ix86_call_abi_override (const_tree fndecl)
4807 if (fndecl == NULL_TREE)
4808 cfun->machine->call_abi = ix86_abi;
4810 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4813 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4814 re-initialization of init_regs each time we switch function context since
4815 this is needed only during RTL expansion. */
4817 ix86_maybe_switch_abi (void)
4820 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4824 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4825 for a call to a function whose data type is FNTYPE.
4826 For a library call, FNTYPE is 0. */
4829 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4830 tree fntype, /* tree ptr for function decl */
4831 rtx libname, /* SYMBOL_REF of library name or 0 */
4834 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4835 memset (cum, 0, sizeof (*cum));
4838 cum->call_abi = ix86_function_abi (fndecl);
4840 cum->call_abi = ix86_function_type_abi (fntype);
4841 /* Set up the number of registers to use for passing arguments. */
4843 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4844 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
4845 "or subtarget optimization implying it");
4846 cum->nregs = ix86_regparm;
4849 if (cum->call_abi != ix86_abi)
4850 cum->nregs = (ix86_abi != SYSV_ABI
4851 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
4855 cum->sse_nregs = SSE_REGPARM_MAX;
4858 if (cum->call_abi != ix86_abi)
4859 cum->sse_nregs = (ix86_abi != SYSV_ABI
4860 ? X86_64_SSE_REGPARM_MAX
4861 : X86_64_MS_SSE_REGPARM_MAX);
4865 cum->mmx_nregs = MMX_REGPARM_MAX;
4866 cum->warn_avx = true;
4867 cum->warn_sse = true;
4868 cum->warn_mmx = true;
4870 /* Because type might mismatch in between caller and callee, we need to
4871 use actual type of function for local calls.
4872 FIXME: cgraph_analyze can be told to actually record if function uses
4873 va_start so for local functions maybe_vaarg can be made aggressive
4875 FIXME: once typesytem is fixed, we won't need this code anymore. */
4877 fntype = TREE_TYPE (fndecl);
4878 cum->maybe_vaarg = (fntype
4879 ? (!prototype_p (fntype) || stdarg_p (fntype))
4884 /* If there are variable arguments, then we won't pass anything
4885 in registers in 32-bit mode. */
4886 if (stdarg_p (fntype))
4897 /* Use ecx and edx registers if function has fastcall attribute,
4898 else look for regparm information. */
4901 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4907 cum->nregs = ix86_function_regparm (fntype, fndecl);
4910 /* Set up the number of SSE registers used for passing SFmode
4911 and DFmode arguments. Warn for mismatching ABI. */
4912 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4916 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4917 But in the case of vector types, it is some vector mode.
4919 When we have only some of our vector isa extensions enabled, then there
4920 are some modes for which vector_mode_supported_p is false. For these
4921 modes, the generic vector support in gcc will choose some non-vector mode
4922 in order to implement the type. By computing the natural mode, we'll
4923 select the proper ABI location for the operand and not depend on whatever
4924 the middle-end decides to do with these vector types.
4926 The midde-end can't deal with the vector types > 16 bytes. In this
4927 case, we return the original mode and warn ABI change if CUM isn't
4930 static enum machine_mode
4931 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4933 enum machine_mode mode = TYPE_MODE (type);
4935 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4937 HOST_WIDE_INT size = int_size_in_bytes (type);
4938 if ((size == 8 || size == 16 || size == 32)
4939 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4940 && TYPE_VECTOR_SUBPARTS (type) > 1)
4942 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4944 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4945 mode = MIN_MODE_VECTOR_FLOAT;
4947 mode = MIN_MODE_VECTOR_INT;
4949 /* Get the mode which has this inner mode and number of units. */
4950 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4951 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4952 && GET_MODE_INNER (mode) == innermode)
4954 if (size == 32 && !TARGET_AVX)
4956 static bool warnedavx;
4963 warning (0, "AVX vector argument without AVX "
4964 "enabled changes the ABI");
4966 return TYPE_MODE (type);
4979 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4980 this may not agree with the mode that the type system has chosen for the
4981 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4982 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4985 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4990 if (orig_mode != BLKmode)
4991 tmp = gen_rtx_REG (orig_mode, regno);
4994 tmp = gen_rtx_REG (mode, regno);
4995 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4996 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
5002 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5003 of this code is to classify each 8bytes of incoming argument by the register
5004 class and assign registers accordingly. */
5006 /* Return the union class of CLASS1 and CLASS2.
5007 See the x86-64 PS ABI for details. */
5009 static enum x86_64_reg_class
5010 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
5012 /* Rule #1: If both classes are equal, this is the resulting class. */
5013 if (class1 == class2)
5016 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5018 if (class1 == X86_64_NO_CLASS)
5020 if (class2 == X86_64_NO_CLASS)
5023 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5024 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
5025 return X86_64_MEMORY_CLASS;
5027 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5028 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
5029 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
5030 return X86_64_INTEGERSI_CLASS;
5031 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
5032 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
5033 return X86_64_INTEGER_CLASS;
5035 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5037 if (class1 == X86_64_X87_CLASS
5038 || class1 == X86_64_X87UP_CLASS
5039 || class1 == X86_64_COMPLEX_X87_CLASS
5040 || class2 == X86_64_X87_CLASS
5041 || class2 == X86_64_X87UP_CLASS
5042 || class2 == X86_64_COMPLEX_X87_CLASS)
5043 return X86_64_MEMORY_CLASS;
5045 /* Rule #6: Otherwise class SSE is used. */
5046 return X86_64_SSE_CLASS;
5049 /* Classify the argument of type TYPE and mode MODE.
5050 CLASSES will be filled by the register class used to pass each word
5051 of the operand. The number of words is returned. In case the parameter
5052 should be passed in memory, 0 is returned. As a special case for zero
5053 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5055 BIT_OFFSET is used internally for handling records and specifies offset
5056 of the offset in bits modulo 256 to avoid overflow cases.
5058 See the x86-64 PS ABI for details.
5062 classify_argument (enum machine_mode mode, const_tree type,
5063 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
5065 HOST_WIDE_INT bytes =
5066 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5067 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5069 /* Variable sized entities are always passed/returned in memory. */
5073 if (mode != VOIDmode
5074 && targetm.calls.must_pass_in_stack (mode, type))
5077 if (type && AGGREGATE_TYPE_P (type))
5081 enum x86_64_reg_class subclasses[MAX_CLASSES];
5083 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5087 for (i = 0; i < words; i++)
5088 classes[i] = X86_64_NO_CLASS;
5090 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5091 signalize memory class, so handle it as special case. */
5094 classes[0] = X86_64_NO_CLASS;
5098 /* Classify each field of record and merge classes. */
5099 switch (TREE_CODE (type))
5102 /* And now merge the fields of structure. */
5103 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5105 if (TREE_CODE (field) == FIELD_DECL)
5109 if (TREE_TYPE (field) == error_mark_node)
5112 /* Bitfields are always classified as integer. Handle them
5113 early, since later code would consider them to be
5114 misaligned integers. */
5115 if (DECL_BIT_FIELD (field))
5117 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5118 i < ((int_bit_position (field) + (bit_offset % 64))
5119 + tree_low_cst (DECL_SIZE (field), 0)
5122 merge_classes (X86_64_INTEGER_CLASS,
5129 type = TREE_TYPE (field);
5131 /* Flexible array member is ignored. */
5132 if (TYPE_MODE (type) == BLKmode
5133 && TREE_CODE (type) == ARRAY_TYPE
5134 && TYPE_SIZE (type) == NULL_TREE
5135 && TYPE_DOMAIN (type) != NULL_TREE
5136 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5141 if (!warned && warn_psabi)
5144 inform (input_location,
5145 "The ABI of passing struct with"
5146 " a flexible array member has"
5147 " changed in GCC 4.4");
5151 num = classify_argument (TYPE_MODE (type), type,
5153 (int_bit_position (field)
5154 + bit_offset) % 256);
5157 pos = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5158 for (i = 0; i < num && (i + pos) < words; i++)
5160 merge_classes (subclasses[i], classes[i + pos]);
5167 /* Arrays are handled as small records. */
5170 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5171 TREE_TYPE (type), subclasses, bit_offset);
5175 /* The partial classes are now full classes. */
5176 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5177 subclasses[0] = X86_64_SSE_CLASS;
5178 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5179 && !((bit_offset % 64) == 0 && bytes == 4))
5180 subclasses[0] = X86_64_INTEGER_CLASS;
5182 for (i = 0; i < words; i++)
5183 classes[i] = subclasses[i % num];
5188 case QUAL_UNION_TYPE:
5189 /* Unions are similar to RECORD_TYPE but offset is always 0.
5191 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5193 if (TREE_CODE (field) == FIELD_DECL)
5197 if (TREE_TYPE (field) == error_mark_node)
5200 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5201 TREE_TYPE (field), subclasses,
5205 for (i = 0; i < num; i++)
5206 classes[i] = merge_classes (subclasses[i], classes[i]);
5217 /* When size > 16 bytes, if the first one isn't
5218 X86_64_SSE_CLASS or any other ones aren't
5219 X86_64_SSEUP_CLASS, everything should be passed in
5221 if (classes[0] != X86_64_SSE_CLASS)
5224 for (i = 1; i < words; i++)
5225 if (classes[i] != X86_64_SSEUP_CLASS)
5229 /* Final merger cleanup. */
5230 for (i = 0; i < words; i++)
5232 /* If one class is MEMORY, everything should be passed in
5234 if (classes[i] == X86_64_MEMORY_CLASS)
5237 /* The X86_64_SSEUP_CLASS should be always preceded by
5238 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5239 if (classes[i] == X86_64_SSEUP_CLASS
5240 && classes[i - 1] != X86_64_SSE_CLASS
5241 && classes[i - 1] != X86_64_SSEUP_CLASS)
5243 /* The first one should never be X86_64_SSEUP_CLASS. */
5244 gcc_assert (i != 0);
5245 classes[i] = X86_64_SSE_CLASS;
5248 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5249 everything should be passed in memory. */
5250 if (classes[i] == X86_64_X87UP_CLASS
5251 && (classes[i - 1] != X86_64_X87_CLASS))
5255 /* The first one should never be X86_64_X87UP_CLASS. */
5256 gcc_assert (i != 0);
5257 if (!warned && warn_psabi)
5260 inform (input_location,
5261 "The ABI of passing union with long double"
5262 " has changed in GCC 4.4");
5270 /* Compute alignment needed. We align all types to natural boundaries with
5271 exception of XFmode that is aligned to 64bits. */
5272 if (mode != VOIDmode && mode != BLKmode)
5274 int mode_alignment = GET_MODE_BITSIZE (mode);
5277 mode_alignment = 128;
5278 else if (mode == XCmode)
5279 mode_alignment = 256;
5280 if (COMPLEX_MODE_P (mode))
5281 mode_alignment /= 2;
5282 /* Misaligned fields are always returned in memory. */
5283 if (bit_offset % mode_alignment)
5287 /* for V1xx modes, just use the base mode */
5288 if (VECTOR_MODE_P (mode) && mode != V1DImode
5289 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5290 mode = GET_MODE_INNER (mode);
5292 /* Classification of atomic types. */
5297 classes[0] = X86_64_SSE_CLASS;
5300 classes[0] = X86_64_SSE_CLASS;
5301 classes[1] = X86_64_SSEUP_CLASS;
5311 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5315 classes[0] = X86_64_INTEGERSI_CLASS;
5318 else if (size <= 64)
5320 classes[0] = X86_64_INTEGER_CLASS;
5323 else if (size <= 64+32)
5325 classes[0] = X86_64_INTEGER_CLASS;
5326 classes[1] = X86_64_INTEGERSI_CLASS;
5329 else if (size <= 64+64)
5331 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5339 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5343 /* OImode shouldn't be used directly. */
5348 if (!(bit_offset % 64))
5349 classes[0] = X86_64_SSESF_CLASS;
5351 classes[0] = X86_64_SSE_CLASS;
5354 classes[0] = X86_64_SSEDF_CLASS;
5357 classes[0] = X86_64_X87_CLASS;
5358 classes[1] = X86_64_X87UP_CLASS;
5361 classes[0] = X86_64_SSE_CLASS;
5362 classes[1] = X86_64_SSEUP_CLASS;
5365 classes[0] = X86_64_SSE_CLASS;
5366 if (!(bit_offset % 64))
5372 if (!warned && warn_psabi)
5375 inform (input_location,
5376 "The ABI of passing structure with complex float"
5377 " member has changed in GCC 4.4");
5379 classes[1] = X86_64_SSESF_CLASS;
5383 classes[0] = X86_64_SSEDF_CLASS;
5384 classes[1] = X86_64_SSEDF_CLASS;
5387 classes[0] = X86_64_COMPLEX_X87_CLASS;
5390 /* This modes is larger than 16 bytes. */
5398 classes[0] = X86_64_SSE_CLASS;
5399 classes[1] = X86_64_SSEUP_CLASS;
5400 classes[2] = X86_64_SSEUP_CLASS;
5401 classes[3] = X86_64_SSEUP_CLASS;
5409 classes[0] = X86_64_SSE_CLASS;
5410 classes[1] = X86_64_SSEUP_CLASS;
5417 classes[0] = X86_64_SSE_CLASS;
5423 gcc_assert (VECTOR_MODE_P (mode));
5428 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5430 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5431 classes[0] = X86_64_INTEGERSI_CLASS;
5433 classes[0] = X86_64_INTEGER_CLASS;
5434 classes[1] = X86_64_INTEGER_CLASS;
5435 return 1 + (bytes > 8);
5439 /* Examine the argument and return set number of register required in each
5440 class. Return 0 iff parameter should be passed in memory. */
5442 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5443 int *int_nregs, int *sse_nregs)
5445 enum x86_64_reg_class regclass[MAX_CLASSES];
5446 int n = classify_argument (mode, type, regclass, 0);
5452 for (n--; n >= 0; n--)
5453 switch (regclass[n])
5455 case X86_64_INTEGER_CLASS:
5456 case X86_64_INTEGERSI_CLASS:
5459 case X86_64_SSE_CLASS:
5460 case X86_64_SSESF_CLASS:
5461 case X86_64_SSEDF_CLASS:
5464 case X86_64_NO_CLASS:
5465 case X86_64_SSEUP_CLASS:
5467 case X86_64_X87_CLASS:
5468 case X86_64_X87UP_CLASS:
5472 case X86_64_COMPLEX_X87_CLASS:
5473 return in_return ? 2 : 0;
5474 case X86_64_MEMORY_CLASS:
5480 /* Construct container for the argument used by GCC interface. See
5481 FUNCTION_ARG for the detailed description. */
5484 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5485 const_tree type, int in_return, int nintregs, int nsseregs,
5486 const int *intreg, int sse_regno)
5488 /* The following variables hold the static issued_error state. */
5489 static bool issued_sse_arg_error;
5490 static bool issued_sse_ret_error;
5491 static bool issued_x87_ret_error;
5493 enum machine_mode tmpmode;
5495 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5496 enum x86_64_reg_class regclass[MAX_CLASSES];
5500 int needed_sseregs, needed_intregs;
5501 rtx exp[MAX_CLASSES];
5504 n = classify_argument (mode, type, regclass, 0);
5507 if (!examine_argument (mode, type, in_return, &needed_intregs,
5510 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5513 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5514 some less clueful developer tries to use floating-point anyway. */
5515 if (needed_sseregs && !TARGET_SSE)
5519 if (!issued_sse_ret_error)
5521 error ("SSE register return with SSE disabled");
5522 issued_sse_ret_error = true;
5525 else if (!issued_sse_arg_error)
5527 error ("SSE register argument with SSE disabled");
5528 issued_sse_arg_error = true;
5533 /* Likewise, error if the ABI requires us to return values in the
5534 x87 registers and the user specified -mno-80387. */
5535 if (!TARGET_80387 && in_return)
5536 for (i = 0; i < n; i++)
5537 if (regclass[i] == X86_64_X87_CLASS
5538 || regclass[i] == X86_64_X87UP_CLASS
5539 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5541 if (!issued_x87_ret_error)
5543 error ("x87 register return with x87 disabled");
5544 issued_x87_ret_error = true;
5549 /* First construct simple cases. Avoid SCmode, since we want to use
5550 single register to pass this type. */
5551 if (n == 1 && mode != SCmode)
5552 switch (regclass[0])
5554 case X86_64_INTEGER_CLASS:
5555 case X86_64_INTEGERSI_CLASS:
5556 return gen_rtx_REG (mode, intreg[0]);
5557 case X86_64_SSE_CLASS:
5558 case X86_64_SSESF_CLASS:
5559 case X86_64_SSEDF_CLASS:
5560 if (mode != BLKmode)
5561 return gen_reg_or_parallel (mode, orig_mode,
5562 SSE_REGNO (sse_regno));
5564 case X86_64_X87_CLASS:
5565 case X86_64_COMPLEX_X87_CLASS:
5566 return gen_rtx_REG (mode, FIRST_STACK_REG);
5567 case X86_64_NO_CLASS:
5568 /* Zero sized array, struct or class. */
5573 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5574 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5575 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5577 && regclass[0] == X86_64_SSE_CLASS
5578 && regclass[1] == X86_64_SSEUP_CLASS
5579 && regclass[2] == X86_64_SSEUP_CLASS
5580 && regclass[3] == X86_64_SSEUP_CLASS
5582 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5585 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5586 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5587 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5588 && regclass[1] == X86_64_INTEGER_CLASS
5589 && (mode == CDImode || mode == TImode || mode == TFmode)
5590 && intreg[0] + 1 == intreg[1])
5591 return gen_rtx_REG (mode, intreg[0]);
5593 /* Otherwise figure out the entries of the PARALLEL. */
5594 for (i = 0; i < n; i++)
5598 switch (regclass[i])
5600 case X86_64_NO_CLASS:
5602 case X86_64_INTEGER_CLASS:
5603 case X86_64_INTEGERSI_CLASS:
5604 /* Merge TImodes on aligned occasions here too. */
5605 if (i * 8 + 8 > bytes)
5606 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5607 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5611 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5612 if (tmpmode == BLKmode)
5614 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5615 gen_rtx_REG (tmpmode, *intreg),
5619 case X86_64_SSESF_CLASS:
5620 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5621 gen_rtx_REG (SFmode,
5622 SSE_REGNO (sse_regno)),
5626 case X86_64_SSEDF_CLASS:
5627 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5628 gen_rtx_REG (DFmode,
5629 SSE_REGNO (sse_regno)),
5633 case X86_64_SSE_CLASS:
5641 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5651 && regclass[1] == X86_64_SSEUP_CLASS
5652 && regclass[2] == X86_64_SSEUP_CLASS
5653 && regclass[3] == X86_64_SSEUP_CLASS);
5660 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5661 gen_rtx_REG (tmpmode,
5662 SSE_REGNO (sse_regno)),
5671 /* Empty aligned struct, union or class. */
5675 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5676 for (i = 0; i < nexps; i++)
5677 XVECEXP (ret, 0, i) = exp [i];
5681 /* Update the data in CUM to advance over an argument of mode MODE
5682 and data type TYPE. (TYPE is null for libcalls where that information
5683 may not be available.) */
5686 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5687 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5703 cum->words += words;
5704 cum->nregs -= words;
5705 cum->regno += words;
5707 if (cum->nregs <= 0)
5715 /* OImode shouldn't be used directly. */
5719 if (cum->float_in_sse < 2)
5722 if (cum->float_in_sse < 1)
5739 if (!type || !AGGREGATE_TYPE_P (type))
5741 cum->sse_words += words;
5742 cum->sse_nregs -= 1;
5743 cum->sse_regno += 1;
5744 if (cum->sse_nregs <= 0)
5757 if (!type || !AGGREGATE_TYPE_P (type))
5759 cum->mmx_words += words;
5760 cum->mmx_nregs -= 1;
5761 cum->mmx_regno += 1;
5762 if (cum->mmx_nregs <= 0)
5773 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5774 tree type, HOST_WIDE_INT words, int named)
5776 int int_nregs, sse_nregs;
5778 /* Unnamed 256bit vector mode parameters are passed on stack. */
5779 if (!named && VALID_AVX256_REG_MODE (mode))
5782 if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
5783 cum->words += words;
5784 else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5786 cum->nregs -= int_nregs;
5787 cum->sse_nregs -= sse_nregs;
5788 cum->regno += int_nregs;
5789 cum->sse_regno += sse_nregs;
5792 cum->words += words;
5796 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5797 HOST_WIDE_INT words)
5799 /* Otherwise, this should be passed indirect. */
5800 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5802 cum->words += words;
5811 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5812 tree type, int named)
5814 HOST_WIDE_INT bytes, words;
5816 if (mode == BLKmode)
5817 bytes = int_size_in_bytes (type);
5819 bytes = GET_MODE_SIZE (mode);
5820 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5823 mode = type_natural_mode (type, NULL);
5825 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
5826 function_arg_advance_ms_64 (cum, bytes, words);
5827 else if (TARGET_64BIT)
5828 function_arg_advance_64 (cum, mode, type, words, named);
5830 function_arg_advance_32 (cum, mode, type, bytes, words);
5833 /* Define where to put the arguments to a function.
5834 Value is zero to push the argument on the stack,
5835 or a hard register in which to store the argument.
5837 MODE is the argument's machine mode.
5838 TYPE is the data type of the argument (as a tree).
5839 This is null for libcalls where that information may
5841 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5842 the preceding args and about the function being called.
5843 NAMED is nonzero if this argument is a named parameter
5844 (otherwise it is an extra parameter matching an ellipsis). */
5847 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5848 enum machine_mode orig_mode, tree type,
5849 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5851 static bool warnedsse, warnedmmx;
5853 /* Avoid the AL settings for the Unix64 ABI. */
5854 if (mode == VOIDmode)
5870 if (words <= cum->nregs)
5872 int regno = cum->regno;
5874 /* Fastcall allocates the first two DWORD (SImode) or
5875 smaller arguments to ECX and EDX if it isn't an
5881 || (type && AGGREGATE_TYPE_P (type)))
5884 /* ECX not EAX is the first allocated register. */
5885 if (regno == AX_REG)
5888 return gen_rtx_REG (mode, regno);
5893 if (cum->float_in_sse < 2)
5896 if (cum->float_in_sse < 1)
5900 /* In 32bit, we pass TImode in xmm registers. */
5907 if (!type || !AGGREGATE_TYPE_P (type))
5909 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5912 warning (0, "SSE vector argument without SSE enabled "
5916 return gen_reg_or_parallel (mode, orig_mode,
5917 cum->sse_regno + FIRST_SSE_REG);
5922 /* OImode shouldn't be used directly. */
5931 if (!type || !AGGREGATE_TYPE_P (type))
5934 return gen_reg_or_parallel (mode, orig_mode,
5935 cum->sse_regno + FIRST_SSE_REG);
5944 if (!type || !AGGREGATE_TYPE_P (type))
5946 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5949 warning (0, "MMX vector argument without MMX enabled "
5953 return gen_reg_or_parallel (mode, orig_mode,
5954 cum->mmx_regno + FIRST_MMX_REG);
5963 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5964 enum machine_mode orig_mode, tree type, int named)
5966 /* Handle a hidden AL argument containing number of registers
5967 for varargs x86-64 functions. */
5968 if (mode == VOIDmode)
5969 return GEN_INT (cum->maybe_vaarg
5970 ? (cum->sse_nregs < 0
5971 ? (cum->call_abi == ix86_abi
5973 : (ix86_abi != SYSV_ABI
5974 ? X86_64_SSE_REGPARM_MAX
5975 : X86_64_MS_SSE_REGPARM_MAX))
5990 /* Unnamed 256bit vector mode parameters are passed on stack. */
5996 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5998 &x86_64_int_parameter_registers [cum->regno],
6003 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6004 enum machine_mode orig_mode, int named,
6005 HOST_WIDE_INT bytes)
6009 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6010 We use value of -2 to specify that current function call is MSABI. */
6011 if (mode == VOIDmode)
6012 return GEN_INT (-2);
6014 /* If we've run out of registers, it goes on the stack. */
6015 if (cum->nregs == 0)
6018 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
6020 /* Only floating point modes are passed in anything but integer regs. */
6021 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
6024 regno = cum->regno + FIRST_SSE_REG;
6029 /* Unnamed floating parameters are passed in both the
6030 SSE and integer registers. */
6031 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
6032 t2 = gen_rtx_REG (mode, regno);
6033 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
6034 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
6035 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
6038 /* Handle aggregated types passed in register. */
6039 if (orig_mode == BLKmode)
6041 if (bytes > 0 && bytes <= 8)
6042 mode = (bytes > 4 ? DImode : SImode);
6043 if (mode == BLKmode)
6047 return gen_reg_or_parallel (mode, orig_mode, regno);
6051 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
6052 tree type, int named)
6054 enum machine_mode mode = omode;
6055 HOST_WIDE_INT bytes, words;
6057 if (mode == BLKmode)
6058 bytes = int_size_in_bytes (type);
6060 bytes = GET_MODE_SIZE (mode);
6061 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6063 /* To simplify the code below, represent vector types with a vector mode
6064 even if MMX/SSE are not active. */
6065 if (type && TREE_CODE (type) == VECTOR_TYPE)
6066 mode = type_natural_mode (type, cum);
6068 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6069 return function_arg_ms_64 (cum, mode, omode, named, bytes);
6070 else if (TARGET_64BIT)
6071 return function_arg_64 (cum, mode, omode, type, named);
6073 return function_arg_32 (cum, mode, omode, type, bytes, words);
6076 /* A C expression that indicates when an argument must be passed by
6077 reference. If nonzero for an argument, a copy of that argument is
6078 made in memory and a pointer to the argument is passed instead of
6079 the argument itself. The pointer is passed in whatever way is
6080 appropriate for passing a pointer to that type. */
6083 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6084 enum machine_mode mode ATTRIBUTE_UNUSED,
6085 const_tree type, bool named ATTRIBUTE_UNUSED)
6087 /* See Windows x64 Software Convention. */
6088 if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
6090 int msize = (int) GET_MODE_SIZE (mode);
6093 /* Arrays are passed by reference. */
6094 if (TREE_CODE (type) == ARRAY_TYPE)
6097 if (AGGREGATE_TYPE_P (type))
6099 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
6100 are passed by reference. */
6101 msize = int_size_in_bytes (type);
6105 /* __m128 is passed by reference. */
6107 case 1: case 2: case 4: case 8:
6113 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
6119 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6122 contains_aligned_value_p (tree type)
6124 enum machine_mode mode = TYPE_MODE (type);
6125 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6129 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6131 if (TYPE_ALIGN (type) < 128)
6134 if (AGGREGATE_TYPE_P (type))
6136 /* Walk the aggregates recursively. */
6137 switch (TREE_CODE (type))
6141 case QUAL_UNION_TYPE:
6145 /* Walk all the structure fields. */
6146 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6148 if (TREE_CODE (field) == FIELD_DECL
6149 && contains_aligned_value_p (TREE_TYPE (field)))
6156 /* Just for use if some languages passes arrays by value. */
6157 if (contains_aligned_value_p (TREE_TYPE (type)))
6168 /* Gives the alignment boundary, in bits, of an argument with the
6169 specified mode and type. */
6172 ix86_function_arg_boundary (enum machine_mode mode, tree type)
6177 /* Since canonical type is used for call, we convert it to
6178 canonical type if needed. */
6179 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6180 type = TYPE_CANONICAL (type);
6181 align = TYPE_ALIGN (type);
6184 align = GET_MODE_ALIGNMENT (mode);
6185 if (align < PARM_BOUNDARY)
6186 align = PARM_BOUNDARY;
6187 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6188 natural boundaries. */
6189 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6191 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6192 make an exception for SSE modes since these require 128bit
6195 The handling here differs from field_alignment. ICC aligns MMX
6196 arguments to 4 byte boundaries, while structure fields are aligned
6197 to 8 byte boundaries. */
6200 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6201 align = PARM_BOUNDARY;
6205 if (!contains_aligned_value_p (type))
6206 align = PARM_BOUNDARY;
6209 if (align > BIGGEST_ALIGNMENT)
6210 align = BIGGEST_ALIGNMENT;
6214 /* Return true if N is a possible register number of function value. */
6217 ix86_function_value_regno_p (int regno)
6224 case FIRST_FLOAT_REG:
6225 /* TODO: The function should depend on current function ABI but
6226 builtins.c would need updating then. Therefore we use the
6228 if (TARGET_64BIT && ix86_abi == MS_ABI)
6230 return TARGET_FLOAT_RETURNS_IN_80387;
6236 if (TARGET_MACHO || TARGET_64BIT)
6244 /* Define how to find the value returned by a function.
6245 VALTYPE is the data type of the value (as a tree).
6246 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6247 otherwise, FUNC is 0. */
6250 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6251 const_tree fntype, const_tree fn)
6255 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6256 we normally prevent this case when mmx is not available. However
6257 some ABIs may require the result to be returned like DImode. */
6258 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6259 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6261 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6262 we prevent this case when sse is not available. However some ABIs
6263 may require the result to be returned like integer TImode. */
6264 else if (mode == TImode
6265 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6266 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6268 /* 32-byte vector modes in %ymm0. */
6269 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6270 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6272 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6273 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6274 regno = FIRST_FLOAT_REG;
6276 /* Most things go in %eax. */
6279 /* Override FP return register with %xmm0 for local functions when
6280 SSE math is enabled or for functions with sseregparm attribute. */
6281 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6283 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6284 if ((sse_level >= 1 && mode == SFmode)
6285 || (sse_level == 2 && mode == DFmode))
6286 regno = FIRST_SSE_REG;
6289 /* OImode shouldn't be used directly. */
6290 gcc_assert (mode != OImode);
6292 return gen_rtx_REG (orig_mode, regno);
6296 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6301 /* Handle libcalls, which don't provide a type node. */
6302 if (valtype == NULL)
6314 return gen_rtx_REG (mode, FIRST_SSE_REG);
6317 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6321 return gen_rtx_REG (mode, AX_REG);
6325 ret = construct_container (mode, orig_mode, valtype, 1,
6326 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6327 x86_64_int_return_registers, 0);
6329 /* For zero sized structures, construct_container returns NULL, but we
6330 need to keep rest of compiler happy by returning meaningful value. */
6332 ret = gen_rtx_REG (orig_mode, AX_REG);
6338 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6340 unsigned int regno = AX_REG;
6344 switch (GET_MODE_SIZE (mode))
6347 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6348 && !COMPLEX_MODE_P (mode))
6349 regno = FIRST_SSE_REG;
6353 if (mode == SFmode || mode == DFmode)
6354 regno = FIRST_SSE_REG;
6360 return gen_rtx_REG (orig_mode, regno);
6364 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6365 enum machine_mode orig_mode, enum machine_mode mode)
6367 const_tree fn, fntype;
6370 if (fntype_or_decl && DECL_P (fntype_or_decl))
6371 fn = fntype_or_decl;
6372 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6374 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6375 return function_value_ms_64 (orig_mode, mode);
6376 else if (TARGET_64BIT)
6377 return function_value_64 (orig_mode, mode, valtype);
6379 return function_value_32 (orig_mode, mode, fntype, fn);
6383 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6384 bool outgoing ATTRIBUTE_UNUSED)
6386 enum machine_mode mode, orig_mode;
6388 orig_mode = TYPE_MODE (valtype);
6389 mode = type_natural_mode (valtype, NULL);
6390 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6394 ix86_libcall_value (enum machine_mode mode)
6396 return ix86_function_value_1 (NULL, NULL, mode, mode);
6399 /* Return true iff type is returned in memory. */
6401 static int ATTRIBUTE_UNUSED
6402 return_in_memory_32 (const_tree type, enum machine_mode mode)
6406 if (mode == BLKmode)
6409 size = int_size_in_bytes (type);
6411 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6414 if (VECTOR_MODE_P (mode) || mode == TImode)
6416 /* User-created vectors small enough to fit in EAX. */
6420 /* MMX/3dNow values are returned in MM0,
6421 except when it doesn't exits. */
6423 return (TARGET_MMX ? 0 : 1);
6425 /* SSE values are returned in XMM0, except when it doesn't exist. */
6427 return (TARGET_SSE ? 0 : 1);
6429 /* AVX values are returned in YMM0, except when it doesn't exist. */
6431 return TARGET_AVX ? 0 : 1;
6440 /* OImode shouldn't be used directly. */
6441 gcc_assert (mode != OImode);
6446 static int ATTRIBUTE_UNUSED
6447 return_in_memory_64 (const_tree type, enum machine_mode mode)
6449 int needed_intregs, needed_sseregs;
6450 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6453 static int ATTRIBUTE_UNUSED
6454 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6456 HOST_WIDE_INT size = int_size_in_bytes (type);
6458 /* __m128 is returned in xmm0. */
6459 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6460 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6463 /* Otherwise, the size must be exactly in [1248]. */
6464 return (size != 1 && size != 2 && size != 4 && size != 8);
6468 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6470 #ifdef SUBTARGET_RETURN_IN_MEMORY
6471 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6473 const enum machine_mode mode = type_natural_mode (type, NULL);
6477 if (ix86_function_type_abi (fntype) == MS_ABI)
6478 return return_in_memory_ms_64 (type, mode);
6480 return return_in_memory_64 (type, mode);
6483 return return_in_memory_32 (type, mode);
6487 /* Return false iff TYPE is returned in memory. This version is used
6488 on Solaris 10. It is similar to the generic ix86_return_in_memory,
6489 but differs notably in that when MMX is available, 8-byte vectors
6490 are returned in memory, rather than in MMX registers. */
6493 ix86_sol10_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6496 enum machine_mode mode = type_natural_mode (type, NULL);
6499 return return_in_memory_64 (type, mode);
6501 if (mode == BLKmode)
6504 size = int_size_in_bytes (type);
6506 if (VECTOR_MODE_P (mode))
6508 /* Return in memory only if MMX registers *are* available. This
6509 seems backwards, but it is consistent with the existing
6516 else if (mode == TImode)
6518 else if (mode == XFmode)
6524 /* When returning SSE vector types, we have a choice of either
6525 (1) being abi incompatible with a -march switch, or
6526 (2) generating an error.
6527 Given no good solution, I think the safest thing is one warning.
6528 The user won't be able to use -Werror, but....
6530 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6531 called in response to actually generating a caller or callee that
6532 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6533 via aggregate_value_p for general type probing from tree-ssa. */
6536 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6538 static bool warnedsse, warnedmmx;
6540 if (!TARGET_64BIT && type)
6542 /* Look at the return type of the function, not the function type. */
6543 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6545 if (!TARGET_SSE && !warnedsse)
6548 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6551 warning (0, "SSE vector return without SSE enabled "
6556 if (!TARGET_MMX && !warnedmmx)
6558 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6561 warning (0, "MMX vector return without MMX enabled "
6571 /* Create the va_list data type. */
6573 /* Returns the calling convention specific va_list date type.
6574 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6577 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6579 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6581 /* For i386 we use plain pointer to argument area. */
6582 if (!TARGET_64BIT || abi == MS_ABI)
6583 return build_pointer_type (char_type_node);
6585 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6586 type_decl = build_decl (BUILTINS_LOCATION,
6587 TYPE_DECL, get_identifier ("__va_list_tag"), record);
6589 f_gpr = build_decl (BUILTINS_LOCATION,
6590 FIELD_DECL, get_identifier ("gp_offset"),
6591 unsigned_type_node);
6592 f_fpr = build_decl (BUILTINS_LOCATION,
6593 FIELD_DECL, get_identifier ("fp_offset"),
6594 unsigned_type_node);
6595 f_ovf = build_decl (BUILTINS_LOCATION,
6596 FIELD_DECL, get_identifier ("overflow_arg_area"),
6598 f_sav = build_decl (BUILTINS_LOCATION,
6599 FIELD_DECL, get_identifier ("reg_save_area"),
6602 va_list_gpr_counter_field = f_gpr;
6603 va_list_fpr_counter_field = f_fpr;
6605 DECL_FIELD_CONTEXT (f_gpr) = record;
6606 DECL_FIELD_CONTEXT (f_fpr) = record;
6607 DECL_FIELD_CONTEXT (f_ovf) = record;
6608 DECL_FIELD_CONTEXT (f_sav) = record;
6610 TREE_CHAIN (record) = type_decl;
6611 TYPE_NAME (record) = type_decl;
6612 TYPE_FIELDS (record) = f_gpr;
6613 TREE_CHAIN (f_gpr) = f_fpr;
6614 TREE_CHAIN (f_fpr) = f_ovf;
6615 TREE_CHAIN (f_ovf) = f_sav;
6617 layout_type (record);
6619 /* The correct type is an array type of one element. */
6620 return build_array_type (record, build_index_type (size_zero_node));
6623 /* Setup the builtin va_list data type and for 64-bit the additional
6624 calling convention specific va_list data types. */
6627 ix86_build_builtin_va_list (void)
6629 tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
6631 /* Initialize abi specific va_list builtin types. */
6635 if (ix86_abi == MS_ABI)
6637 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6638 if (TREE_CODE (t) != RECORD_TYPE)
6639 t = build_variant_type_copy (t);
6640 sysv_va_list_type_node = t;
6645 if (TREE_CODE (t) != RECORD_TYPE)
6646 t = build_variant_type_copy (t);
6647 sysv_va_list_type_node = t;
6649 if (ix86_abi != MS_ABI)
6651 t = ix86_build_builtin_va_list_abi (MS_ABI);
6652 if (TREE_CODE (t) != RECORD_TYPE)
6653 t = build_variant_type_copy (t);
6654 ms_va_list_type_node = t;
6659 if (TREE_CODE (t) != RECORD_TYPE)
6660 t = build_variant_type_copy (t);
6661 ms_va_list_type_node = t;
6668 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6671 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6680 int regparm = ix86_regparm;
6682 if (cum->call_abi != ix86_abi)
6683 regparm = (ix86_abi != SYSV_ABI
6684 ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX);
6686 /* GPR size of varargs save area. */
6687 if (cfun->va_list_gpr_size)
6688 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6690 ix86_varargs_gpr_size = 0;
6692 /* FPR size of varargs save area. We don't need it if we don't pass
6693 anything in SSE registers. */
6694 if (cum->sse_nregs && cfun->va_list_fpr_size)
6695 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6697 ix86_varargs_fpr_size = 0;
6699 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6702 save_area = frame_pointer_rtx;
6703 set = get_varargs_alias_set ();
6705 for (i = cum->regno;
6707 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6710 mem = gen_rtx_MEM (Pmode,
6711 plus_constant (save_area, i * UNITS_PER_WORD));
6712 MEM_NOTRAP_P (mem) = 1;
6713 set_mem_alias_set (mem, set);
6714 emit_move_insn (mem, gen_rtx_REG (Pmode,
6715 x86_64_int_parameter_registers[i]));
6718 if (ix86_varargs_fpr_size)
6720 /* Now emit code to save SSE registers. The AX parameter contains number
6721 of SSE parameter registers used to call this function. We use
6722 sse_prologue_save insn template that produces computed jump across
6723 SSE saves. We need some preparation work to get this working. */
6725 label = gen_label_rtx ();
6726 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6728 /* Compute address to jump to :
6729 label - eax*4 + nnamed_sse_arguments*4 Or
6730 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6731 tmp_reg = gen_reg_rtx (Pmode);
6732 nsse_reg = gen_reg_rtx (Pmode);
6733 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6734 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6735 gen_rtx_MULT (Pmode, nsse_reg,
6738 /* vmovaps is one byte longer than movaps. */
6740 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6741 gen_rtx_PLUS (Pmode, tmp_reg,
6747 gen_rtx_CONST (DImode,
6748 gen_rtx_PLUS (DImode,
6750 GEN_INT (cum->sse_regno
6751 * (TARGET_AVX ? 5 : 4)))));
6753 emit_move_insn (nsse_reg, label_ref);
6754 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6756 /* Compute address of memory block we save into. We always use pointer
6757 pointing 127 bytes after first byte to store - this is needed to keep
6758 instruction size limited by 4 bytes (5 bytes for AVX) with one
6759 byte displacement. */
6760 tmp_reg = gen_reg_rtx (Pmode);
6761 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6762 plus_constant (save_area,
6763 ix86_varargs_gpr_size + 127)));
6764 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6765 MEM_NOTRAP_P (mem) = 1;
6766 set_mem_alias_set (mem, set);
6767 set_mem_align (mem, BITS_PER_WORD);
6769 /* And finally do the dirty job! */
6770 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6771 GEN_INT (cum->sse_regno), label));
6776 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6778 alias_set_type set = get_varargs_alias_set ();
6781 for (i = cum->regno; i < X86_64_MS_REGPARM_MAX; i++)
6785 mem = gen_rtx_MEM (Pmode,
6786 plus_constant (virtual_incoming_args_rtx,
6787 i * UNITS_PER_WORD));
6788 MEM_NOTRAP_P (mem) = 1;
6789 set_mem_alias_set (mem, set);
6791 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6792 emit_move_insn (mem, reg);
6797 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6798 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6801 CUMULATIVE_ARGS next_cum;
6804 /* This argument doesn't appear to be used anymore. Which is good,
6805 because the old code here didn't suppress rtl generation. */
6806 gcc_assert (!no_rtl);
6811 fntype = TREE_TYPE (current_function_decl);
6813 /* For varargs, we do not want to skip the dummy va_dcl argument.
6814 For stdargs, we do want to skip the last named argument. */
6816 if (stdarg_p (fntype))
6817 function_arg_advance (&next_cum, mode, type, 1);
6819 if (cum->call_abi == MS_ABI)
6820 setup_incoming_varargs_ms_64 (&next_cum);
6822 setup_incoming_varargs_64 (&next_cum);
6825 /* Checks if TYPE is of kind va_list char *. */
6828 is_va_list_char_pointer (tree type)
6832 /* For 32-bit it is always true. */
6835 canonic = ix86_canonical_va_list_type (type);
6836 return (canonic == ms_va_list_type_node
6837 || (ix86_abi == MS_ABI && canonic == va_list_type_node));
6840 /* Implement va_start. */
6843 ix86_va_start (tree valist, rtx nextarg)
6845 HOST_WIDE_INT words, n_gpr, n_fpr;
6846 tree f_gpr, f_fpr, f_ovf, f_sav;
6847 tree gpr, fpr, ovf, sav, t;
6850 /* Only 64bit target needs something special. */
6851 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6853 std_expand_builtin_va_start (valist, nextarg);
6857 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6858 f_fpr = TREE_CHAIN (f_gpr);
6859 f_ovf = TREE_CHAIN (f_fpr);
6860 f_sav = TREE_CHAIN (f_ovf);
6862 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6863 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6864 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6865 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6866 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6868 /* Count number of gp and fp argument registers used. */
6869 words = crtl->args.info.words;
6870 n_gpr = crtl->args.info.regno;
6871 n_fpr = crtl->args.info.sse_regno;
6873 if (cfun->va_list_gpr_size)
6875 type = TREE_TYPE (gpr);
6876 t = build2 (MODIFY_EXPR, type,
6877 gpr, build_int_cst (type, n_gpr * 8));
6878 TREE_SIDE_EFFECTS (t) = 1;
6879 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6882 if (TARGET_SSE && cfun->va_list_fpr_size)
6884 type = TREE_TYPE (fpr);
6885 t = build2 (MODIFY_EXPR, type, fpr,
6886 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6887 TREE_SIDE_EFFECTS (t) = 1;
6888 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6891 /* Find the overflow area. */
6892 type = TREE_TYPE (ovf);
6893 t = make_tree (type, crtl->args.internal_arg_pointer);
6895 t = build2 (POINTER_PLUS_EXPR, type, t,
6896 size_int (words * UNITS_PER_WORD));
6897 t = build2 (MODIFY_EXPR, type, ovf, t);
6898 TREE_SIDE_EFFECTS (t) = 1;
6899 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6901 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6903 /* Find the register save area.
6904 Prologue of the function save it right above stack frame. */
6905 type = TREE_TYPE (sav);
6906 t = make_tree (type, frame_pointer_rtx);
6907 if (!ix86_varargs_gpr_size)
6908 t = build2 (POINTER_PLUS_EXPR, type, t,
6909 size_int (-8 * X86_64_REGPARM_MAX));
6910 t = build2 (MODIFY_EXPR, type, sav, t);
6911 TREE_SIDE_EFFECTS (t) = 1;
6912 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6916 /* Implement va_arg. */
6919 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6922 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6923 tree f_gpr, f_fpr, f_ovf, f_sav;
6924 tree gpr, fpr, ovf, sav, t;
6926 tree lab_false, lab_over = NULL_TREE;
6931 enum machine_mode nat_mode;
6934 /* Only 64bit target needs something special. */
6935 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6936 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6938 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6939 f_fpr = TREE_CHAIN (f_gpr);
6940 f_ovf = TREE_CHAIN (f_fpr);
6941 f_sav = TREE_CHAIN (f_ovf);
6943 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6944 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6945 valist = build_va_arg_indirect_ref (valist);
6946 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6947 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6948 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6950 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6952 type = build_pointer_type (type);
6953 size = int_size_in_bytes (type);
6954 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6956 nat_mode = type_natural_mode (type, NULL);
6965 /* Unnamed 256bit vector mode parameters are passed on stack. */
6966 if (ix86_cfun_abi () == SYSV_ABI)
6973 container = construct_container (nat_mode, TYPE_MODE (type),
6974 type, 0, X86_64_REGPARM_MAX,
6975 X86_64_SSE_REGPARM_MAX, intreg,
6980 /* Pull the value out of the saved registers. */
6982 addr = create_tmp_var (ptr_type_node, "addr");
6986 int needed_intregs, needed_sseregs;
6988 tree int_addr, sse_addr;
6990 lab_false = create_artificial_label (UNKNOWN_LOCATION);
6991 lab_over = create_artificial_label (UNKNOWN_LOCATION);
6993 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6995 need_temp = (!REG_P (container)
6996 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6997 || TYPE_ALIGN (type) > 128));
6999 /* In case we are passing structure, verify that it is consecutive block
7000 on the register save area. If not we need to do moves. */
7001 if (!need_temp && !REG_P (container))
7003 /* Verify that all registers are strictly consecutive */
7004 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
7008 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7010 rtx slot = XVECEXP (container, 0, i);
7011 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
7012 || INTVAL (XEXP (slot, 1)) != i * 16)
7020 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
7022 rtx slot = XVECEXP (container, 0, i);
7023 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
7024 || INTVAL (XEXP (slot, 1)) != i * 8)
7036 int_addr = create_tmp_var (ptr_type_node, "int_addr");
7037 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
7040 /* First ensure that we fit completely in registers. */
7043 t = build_int_cst (TREE_TYPE (gpr),
7044 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
7045 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
7046 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7047 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7048 gimplify_and_add (t, pre_p);
7052 t = build_int_cst (TREE_TYPE (fpr),
7053 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
7054 + X86_64_REGPARM_MAX * 8);
7055 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
7056 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
7057 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
7058 gimplify_and_add (t, pre_p);
7061 /* Compute index to start of area used for integer regs. */
7064 /* int_addr = gpr + sav; */
7065 t = fold_convert (sizetype, gpr);
7066 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7067 gimplify_assign (int_addr, t, pre_p);
7071 /* sse_addr = fpr + sav; */
7072 t = fold_convert (sizetype, fpr);
7073 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
7074 gimplify_assign (sse_addr, t, pre_p);
7079 tree temp = create_tmp_var (type, "va_arg_tmp");
7082 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
7083 gimplify_assign (addr, t, pre_p);
7085 for (i = 0; i < XVECLEN (container, 0); i++)
7087 rtx slot = XVECEXP (container, 0, i);
7088 rtx reg = XEXP (slot, 0);
7089 enum machine_mode mode = GET_MODE (reg);
7090 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
7091 tree addr_type = build_pointer_type (piece_type);
7092 tree daddr_type = build_pointer_type_for_mode (piece_type,
7096 tree dest_addr, dest;
7098 if (SSE_REGNO_P (REGNO (reg)))
7100 src_addr = sse_addr;
7101 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
7105 src_addr = int_addr;
7106 src_offset = REGNO (reg) * 8;
7108 src_addr = fold_convert (addr_type, src_addr);
7109 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
7110 size_int (src_offset));
7111 src = build_va_arg_indirect_ref (src_addr);
7113 dest_addr = fold_convert (daddr_type, addr);
7114 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
7115 size_int (INTVAL (XEXP (slot, 1))));
7116 dest = build_va_arg_indirect_ref (dest_addr);
7118 gimplify_assign (dest, src, pre_p);
7124 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7125 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7126 gimplify_assign (gpr, t, pre_p);
7131 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7132 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7133 gimplify_assign (fpr, t, pre_p);
7136 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7138 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7141 /* ... otherwise out of the overflow area. */
7143 /* When we align parameter on stack for caller, if the parameter
7144 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7145 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7146 here with caller. */
7147 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7148 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7149 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7151 /* Care for on-stack alignment if needed. */
7152 if (arg_boundary <= 64
7153 || integer_zerop (TYPE_SIZE (type)))
7157 HOST_WIDE_INT align = arg_boundary / 8;
7158 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7159 size_int (align - 1));
7160 t = fold_convert (sizetype, t);
7161 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7163 t = fold_convert (TREE_TYPE (ovf), t);
7165 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7166 gimplify_assign (addr, t, pre_p);
7168 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7169 size_int (rsize * UNITS_PER_WORD));
7170 gimplify_assign (unshare_expr (ovf), t, pre_p);
7173 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7175 ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
7176 addr = fold_convert (ptrtype, addr);
7179 addr = build_va_arg_indirect_ref (addr);
7180 return build_va_arg_indirect_ref (addr);
7183 /* Return nonzero if OPNUM's MEM should be matched
7184 in movabs* patterns. */
7187 ix86_check_movabs (rtx insn, int opnum)
7191 set = PATTERN (insn);
7192 if (GET_CODE (set) == PARALLEL)
7193 set = XVECEXP (set, 0, 0);
7194 gcc_assert (GET_CODE (set) == SET);
7195 mem = XEXP (set, opnum);
7196 while (GET_CODE (mem) == SUBREG)
7197 mem = SUBREG_REG (mem);
7198 gcc_assert (MEM_P (mem));
7199 return (volatile_ok || !MEM_VOLATILE_P (mem));
7202 /* Initialize the table of extra 80387 mathematical constants. */
7205 init_ext_80387_constants (void)
7207 static const char * cst[5] =
7209 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7210 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7211 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7212 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7213 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7217 for (i = 0; i < 5; i++)
7219 real_from_string (&ext_80387_constants_table[i], cst[i]);
7220 /* Ensure each constant is rounded to XFmode precision. */
7221 real_convert (&ext_80387_constants_table[i],
7222 XFmode, &ext_80387_constants_table[i]);
7225 ext_80387_constants_init = 1;
7228 /* Return true if the constant is something that can be loaded with
7229 a special instruction. */
7232 standard_80387_constant_p (rtx x)
7234 enum machine_mode mode = GET_MODE (x);
7238 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7241 if (x == CONST0_RTX (mode))
7243 if (x == CONST1_RTX (mode))
7246 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7248 /* For XFmode constants, try to find a special 80387 instruction when
7249 optimizing for size or on those CPUs that benefit from them. */
7251 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7255 if (! ext_80387_constants_init)
7256 init_ext_80387_constants ();
7258 for (i = 0; i < 5; i++)
7259 if (real_identical (&r, &ext_80387_constants_table[i]))
7263 /* Load of the constant -0.0 or -1.0 will be split as
7264 fldz;fchs or fld1;fchs sequence. */
7265 if (real_isnegzero (&r))
7267 if (real_identical (&r, &dconstm1))
7273 /* Return the opcode of the special instruction to be used to load
7277 standard_80387_constant_opcode (rtx x)
7279 switch (standard_80387_constant_p (x))
7303 /* Return the CONST_DOUBLE representing the 80387 constant that is
7304 loaded by the specified special instruction. The argument IDX
7305 matches the return value from standard_80387_constant_p. */
7308 standard_80387_constant_rtx (int idx)
7312 if (! ext_80387_constants_init)
7313 init_ext_80387_constants ();
7329 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7333 /* Return 1 if X is all 0s and 2 if x is all 1s
7334 in supported SSE vector mode. */
7337 standard_sse_constant_p (rtx x)
7339 enum machine_mode mode = GET_MODE (x);
7341 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7343 if (vector_all_ones_operand (x, mode))
7359 /* Return the opcode of the special instruction to be used to load
7363 standard_sse_constant_opcode (rtx insn, rtx x)
7365 switch (standard_sse_constant_p (x))
7368 switch (get_attr_mode (insn))
7371 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7373 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7375 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7377 return "vxorps\t%x0, %x0, %x0";
7379 return "vxorpd\t%x0, %x0, %x0";
7381 return "vpxor\t%x0, %x0, %x0";
7386 return TARGET_AVX ? "vpcmpeqd\t%0, %0, %0" : "pcmpeqd\t%0, %0";
7393 /* Returns 1 if OP contains a symbol reference */
7396 symbolic_reference_mentioned_p (rtx op)
7401 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7404 fmt = GET_RTX_FORMAT (GET_CODE (op));
7405 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7411 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7412 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7416 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7423 /* Return 1 if it is appropriate to emit `ret' instructions in the
7424 body of a function. Do this only if the epilogue is simple, needing a
7425 couple of insns. Prior to reloading, we can't tell how many registers
7426 must be saved, so return 0 then. Return 0 if there is no frame
7427 marker to de-allocate. */
7430 ix86_can_use_return_insn_p (void)
7432 struct ix86_frame frame;
7434 if (! reload_completed || frame_pointer_needed)
7437 /* Don't allow more than 32 pop, since that's all we can do
7438 with one instruction. */
7439 if (crtl->args.pops_args
7440 && crtl->args.size >= 32768)
7443 ix86_compute_frame_layout (&frame);
7444 return frame.to_allocate == 0 && frame.padding0 == 0
7445 && (frame.nregs + frame.nsseregs) == 0;
7448 /* Value should be nonzero if functions must have frame pointers.
7449 Zero means the frame pointer need not be set up (and parms may
7450 be accessed via the stack pointer) in functions that seem suitable. */
7453 ix86_frame_pointer_required (void)
7455 /* If we accessed previous frames, then the generated code expects
7456 to be able to access the saved ebp value in our frame. */
7457 if (cfun->machine->accesses_prev_frame)
7460 /* Several x86 os'es need a frame pointer for other reasons,
7461 usually pertaining to setjmp. */
7462 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7465 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7466 the frame pointer by default. Turn it back on now if we've not
7467 got a leaf function. */
7468 if (TARGET_OMIT_LEAF_FRAME_POINTER
7469 && (!current_function_is_leaf
7470 || ix86_current_function_calls_tls_descriptor))
7479 /* Record that the current function accesses previous call frames. */
7482 ix86_setup_frame_addresses (void)
7484 cfun->machine->accesses_prev_frame = 1;
7487 #ifndef USE_HIDDEN_LINKONCE
7488 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7489 # define USE_HIDDEN_LINKONCE 1
7491 # define USE_HIDDEN_LINKONCE 0
7495 static int pic_labels_used;
7497 /* Fills in the label name that should be used for a pc thunk for
7498 the given register. */
7501 get_pc_thunk_name (char name[32], unsigned int regno)
7503 gcc_assert (!TARGET_64BIT);
7505 if (USE_HIDDEN_LINKONCE)
7506 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7508 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7512 /* This function generates code for -fpic that loads %ebx with
7513 the return address of the caller and then returns. */
7516 ix86_file_end (void)
7521 for (regno = 0; regno < 8; ++regno)
7525 if (! ((pic_labels_used >> regno) & 1))
7528 get_pc_thunk_name (name, regno);
7533 switch_to_section (darwin_sections[text_coal_section]);
7534 fputs ("\t.weak_definition\t", asm_out_file);
7535 assemble_name (asm_out_file, name);
7536 fputs ("\n\t.private_extern\t", asm_out_file);
7537 assemble_name (asm_out_file, name);
7538 fputs ("\n", asm_out_file);
7539 ASM_OUTPUT_LABEL (asm_out_file, name);
7543 if (USE_HIDDEN_LINKONCE)
7547 decl = build_decl (BUILTINS_LOCATION,
7548 FUNCTION_DECL, get_identifier (name),
7550 TREE_PUBLIC (decl) = 1;
7551 TREE_STATIC (decl) = 1;
7552 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
7554 (*targetm.asm_out.unique_section) (decl, 0);
7555 switch_to_section (get_named_section (decl, NULL, 0));
7557 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7558 fputs ("\t.hidden\t", asm_out_file);
7559 assemble_name (asm_out_file, name);
7560 putc ('\n', asm_out_file);
7561 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7565 switch_to_section (text_section);
7566 ASM_OUTPUT_LABEL (asm_out_file, name);
7569 xops[0] = gen_rtx_REG (Pmode, regno);
7570 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7571 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7572 output_asm_insn ("ret", xops);
7575 if (NEED_INDICATE_EXEC_STACK)
7576 file_end_indicate_exec_stack ();
7579 /* Emit code for the SET_GOT patterns. */
7582 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7588 if (TARGET_VXWORKS_RTP && flag_pic)
7590 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7591 xops[2] = gen_rtx_MEM (Pmode,
7592 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7593 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7595 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7596 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7597 an unadorned address. */
7598 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7599 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7600 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7604 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7606 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7608 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7611 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7613 output_asm_insn ("call\t%a2", xops);
7616 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7617 is what will be referenced by the Mach-O PIC subsystem. */
7619 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7622 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7623 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7626 output_asm_insn ("pop%z0\t%0", xops);
7631 get_pc_thunk_name (name, REGNO (dest));
7632 pic_labels_used |= 1 << REGNO (dest);
7634 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7635 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7636 output_asm_insn ("call\t%X2", xops);
7637 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7638 is what will be referenced by the Mach-O PIC subsystem. */
7641 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7643 targetm.asm_out.internal_label (asm_out_file, "L",
7644 CODE_LABEL_NUMBER (label));
7651 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7652 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7654 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7659 /* Generate an "push" pattern for input ARG. */
7664 if (ix86_cfa_state->reg == stack_pointer_rtx)
7665 ix86_cfa_state->offset += UNITS_PER_WORD;
7667 return gen_rtx_SET (VOIDmode,
7669 gen_rtx_PRE_DEC (Pmode,
7670 stack_pointer_rtx)),
7674 /* Return >= 0 if there is an unused call-clobbered register available
7675 for the entire function. */
7678 ix86_select_alt_pic_regnum (void)
7680 if (current_function_is_leaf && !crtl->profile
7681 && !ix86_current_function_calls_tls_descriptor)
7684 /* Can't use the same register for both PIC and DRAP. */
7686 drap = REGNO (crtl->drap_reg);
7689 for (i = 2; i >= 0; --i)
7690 if (i != drap && !df_regs_ever_live_p (i))
7694 return INVALID_REGNUM;
7697 /* Return 1 if we need to save REGNO. */
7699 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7701 if (pic_offset_table_rtx
7702 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7703 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7705 || crtl->calls_eh_return
7706 || crtl->uses_const_pool))
7708 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7713 if (crtl->calls_eh_return && maybe_eh_return)
7718 unsigned test = EH_RETURN_DATA_REGNO (i);
7719 if (test == INVALID_REGNUM)
7726 if (crtl->drap_reg && regno == REGNO (crtl->drap_reg))
7729 return (df_regs_ever_live_p (regno)
7730 && !call_used_regs[regno]
7731 && !fixed_regs[regno]
7732 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7735 /* Return number of saved general prupose registers. */
7738 ix86_nsaved_regs (void)
7743 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7744 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7749 /* Return number of saved SSE registrers. */
7752 ix86_nsaved_sseregs (void)
7757 if (ix86_cfun_abi () != MS_ABI)
7759 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7760 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7765 /* Given FROM and TO register numbers, say whether this elimination is
7766 allowed. If stack alignment is needed, we can only replace argument
7767 pointer with hard frame pointer, or replace frame pointer with stack
7768 pointer. Otherwise, frame pointer elimination is automatically
7769 handled and all other eliminations are valid. */
7772 ix86_can_eliminate (const int from, const int to)
7774 if (stack_realign_fp)
7775 return ((from == ARG_POINTER_REGNUM
7776 && to == HARD_FRAME_POINTER_REGNUM)
7777 || (from == FRAME_POINTER_REGNUM
7778 && to == STACK_POINTER_REGNUM));
7780 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : true;
7783 /* Return the offset between two registers, one to be eliminated, and the other
7784 its replacement, at the start of a routine. */
7787 ix86_initial_elimination_offset (int from, int to)
7789 struct ix86_frame frame;
7790 ix86_compute_frame_layout (&frame);
7792 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7793 return frame.hard_frame_pointer_offset;
7794 else if (from == FRAME_POINTER_REGNUM
7795 && to == HARD_FRAME_POINTER_REGNUM)
7796 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7799 gcc_assert (to == STACK_POINTER_REGNUM);
7801 if (from == ARG_POINTER_REGNUM)
7802 return frame.stack_pointer_offset;
7804 gcc_assert (from == FRAME_POINTER_REGNUM);
7805 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7809 /* In a dynamically-aligned function, we can't know the offset from
7810 stack pointer to frame pointer, so we must ensure that setjmp
7811 eliminates fp against the hard fp (%ebp) rather than trying to
7812 index from %esp up to the top of the frame across a gap that is
7813 of unknown (at compile-time) size. */
7815 ix86_builtin_setjmp_frame_value (void)
7817 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7820 /* Fill structure ix86_frame about frame of currently computed function. */
7823 ix86_compute_frame_layout (struct ix86_frame *frame)
7825 HOST_WIDE_INT total_size;
7826 unsigned int stack_alignment_needed;
7827 HOST_WIDE_INT offset;
7828 unsigned int preferred_alignment;
7829 HOST_WIDE_INT size = get_frame_size ();
7831 frame->nregs = ix86_nsaved_regs ();
7832 frame->nsseregs = ix86_nsaved_sseregs ();
7835 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7836 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7838 /* MS ABI seem to require stack alignment to be always 16 except for function
7840 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7842 preferred_alignment = 16;
7843 stack_alignment_needed = 16;
7844 crtl->preferred_stack_boundary = 128;
7845 crtl->stack_alignment_needed = 128;
7848 gcc_assert (!size || stack_alignment_needed);
7849 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7850 gcc_assert (preferred_alignment <= stack_alignment_needed);
7852 /* During reload iteration the amount of registers saved can change.
7853 Recompute the value as needed. Do not recompute when amount of registers
7854 didn't change as reload does multiple calls to the function and does not
7855 expect the decision to change within single iteration. */
7856 if (!optimize_function_for_size_p (cfun)
7857 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7859 int count = frame->nregs;
7861 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7862 /* The fast prologue uses move instead of push to save registers. This
7863 is significantly longer, but also executes faster as modern hardware
7864 can execute the moves in parallel, but can't do that for push/pop.
7866 Be careful about choosing what prologue to emit: When function takes
7867 many instructions to execute we may use slow version as well as in
7868 case function is known to be outside hot spot (this is known with
7869 feedback only). Weight the size of function by number of registers
7870 to save as it is cheap to use one or two push instructions but very
7871 slow to use many of them. */
7873 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7874 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7875 || (flag_branch_probabilities
7876 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7877 cfun->machine->use_fast_prologue_epilogue = false;
7879 cfun->machine->use_fast_prologue_epilogue
7880 = !expensive_function_p (count);
7882 if (TARGET_PROLOGUE_USING_MOVE
7883 && cfun->machine->use_fast_prologue_epilogue)
7884 frame->save_regs_using_mov = true;
7886 frame->save_regs_using_mov = false;
7889 /* Skip return address and saved base pointer. */
7890 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7892 frame->hard_frame_pointer_offset = offset;
7894 /* Set offset to aligned because the realigned frame starts from
7896 if (stack_realign_fp)
7897 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7899 /* Register save area */
7900 offset += frame->nregs * UNITS_PER_WORD;
7902 /* Align SSE reg save area. */
7903 if (frame->nsseregs)
7904 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7906 frame->padding0 = 0;
7908 /* SSE register save area. */
7909 offset += frame->padding0 + frame->nsseregs * 16;
7912 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7913 offset += frame->va_arg_size;
7915 /* Align start of frame for local function. */
7916 frame->padding1 = ((offset + stack_alignment_needed - 1)
7917 & -stack_alignment_needed) - offset;
7919 offset += frame->padding1;
7921 /* Frame pointer points here. */
7922 frame->frame_pointer_offset = offset;
7926 /* Add outgoing arguments area. Can be skipped if we eliminated
7927 all the function calls as dead code.
7928 Skipping is however impossible when function calls alloca. Alloca
7929 expander assumes that last crtl->outgoing_args_size
7930 of stack frame are unused. */
7931 if (ACCUMULATE_OUTGOING_ARGS
7932 && (!current_function_is_leaf || cfun->calls_alloca
7933 || ix86_current_function_calls_tls_descriptor))
7935 offset += crtl->outgoing_args_size;
7936 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7939 frame->outgoing_arguments_size = 0;
7941 /* Align stack boundary. Only needed if we're calling another function
7943 if (!current_function_is_leaf || cfun->calls_alloca
7944 || ix86_current_function_calls_tls_descriptor)
7945 frame->padding2 = ((offset + preferred_alignment - 1)
7946 & -preferred_alignment) - offset;
7948 frame->padding2 = 0;
7950 offset += frame->padding2;
7952 /* We've reached end of stack frame. */
7953 frame->stack_pointer_offset = offset;
7955 /* Size prologue needs to allocate. */
7956 frame->to_allocate =
7957 (size + frame->padding1 + frame->padding2
7958 + frame->outgoing_arguments_size + frame->va_arg_size);
7960 if ((!frame->to_allocate && frame->nregs <= 1)
7961 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7962 frame->save_regs_using_mov = false;
7964 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
7965 && current_function_sp_is_unchanging
7966 && current_function_is_leaf
7967 && !ix86_current_function_calls_tls_descriptor)
7969 frame->red_zone_size = frame->to_allocate;
7970 if (frame->save_regs_using_mov)
7971 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7972 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7973 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7976 frame->red_zone_size = 0;
7977 frame->to_allocate -= frame->red_zone_size;
7978 frame->stack_pointer_offset -= frame->red_zone_size;
7980 fprintf (stderr, "\n");
7981 fprintf (stderr, "size: %ld\n", (long)size);
7982 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7983 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7984 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7985 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7986 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7987 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7988 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7989 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7990 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7991 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7992 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7993 (long)frame->hard_frame_pointer_offset);
7994 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7995 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7996 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7997 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
8001 /* Emit code to save registers in the prologue. */
8004 ix86_emit_save_regs (void)
8009 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
8010 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8012 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
8013 RTX_FRAME_RELATED_P (insn) = 1;
8017 /* Emit code to save registers using MOV insns. First register
8018 is restored from POINTER + OFFSET. */
8020 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8025 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8026 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8028 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
8030 gen_rtx_REG (Pmode, regno));
8031 RTX_FRAME_RELATED_P (insn) = 1;
8032 offset += UNITS_PER_WORD;
8036 /* Emit code to save registers using MOV insns. First register
8037 is restored from POINTER + OFFSET. */
8039 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
8045 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8046 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
8048 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
8049 set_mem_align (mem, 128);
8050 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
8051 RTX_FRAME_RELATED_P (insn) = 1;
8056 static GTY(()) rtx queued_cfa_restores;
8058 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
8059 manipulation insn. Don't add it if the previously
8060 saved value will be left untouched within stack red-zone till return,
8061 as unwinders can find the same value in the register and
8065 ix86_add_cfa_restore_note (rtx insn, rtx reg, HOST_WIDE_INT red_offset)
8068 && !TARGET_64BIT_MS_ABI
8069 && red_offset + RED_ZONE_SIZE >= 0
8070 && crtl->args.pops_args < 65536)
8075 add_reg_note (insn, REG_CFA_RESTORE, reg);
8076 RTX_FRAME_RELATED_P (insn) = 1;
8080 = alloc_reg_note (REG_CFA_RESTORE, reg, queued_cfa_restores);
8083 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
8086 ix86_add_queued_cfa_restore_notes (rtx insn)
8089 if (!queued_cfa_restores)
8091 for (last = queued_cfa_restores; XEXP (last, 1); last = XEXP (last, 1))
8093 XEXP (last, 1) = REG_NOTES (insn);
8094 REG_NOTES (insn) = queued_cfa_restores;
8095 queued_cfa_restores = NULL_RTX;
8096 RTX_FRAME_RELATED_P (insn) = 1;
8099 /* Expand prologue or epilogue stack adjustment.
8100 The pattern exist to put a dependency on all ebp-based memory accesses.
8101 STYLE should be negative if instructions should be marked as frame related,
8102 zero if %r11 register is live and cannot be freely used and positive
8106 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset,
8107 int style, bool set_cfa)
8112 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
8113 else if (x86_64_immediate_operand (offset, DImode))
8114 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
8118 /* r11 is used by indirect sibcall return as well, set before the
8119 epilogue and used after the epilogue. ATM indirect sibcall
8120 shouldn't be used together with huge frame sizes in one
8121 function because of the frame_size check in sibcall.c. */
8123 r11 = gen_rtx_REG (DImode, R11_REG);
8124 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
8126 RTX_FRAME_RELATED_P (insn) = 1;
8127 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
8132 ix86_add_queued_cfa_restore_notes (insn);
8138 gcc_assert (ix86_cfa_state->reg == src);
8139 ix86_cfa_state->offset += INTVAL (offset);
8140 ix86_cfa_state->reg = dest;
8142 r = gen_rtx_PLUS (Pmode, src, offset);
8143 r = gen_rtx_SET (VOIDmode, dest, r);
8144 add_reg_note (insn, REG_CFA_ADJUST_CFA, r);
8145 RTX_FRAME_RELATED_P (insn) = 1;
8148 RTX_FRAME_RELATED_P (insn) = 1;
8151 /* Find an available register to be used as dynamic realign argument
8152 pointer regsiter. Such a register will be written in prologue and
8153 used in begin of body, so it must not be
8154 1. parameter passing register.
8156 We reuse static-chain register if it is available. Otherwise, we
8157 use DI for i386 and R13 for x86-64. We chose R13 since it has
8160 Return: the regno of chosen register. */
8163 find_drap_reg (void)
8165 tree decl = cfun->decl;
8169 /* Use R13 for nested function or function need static chain.
8170 Since function with tail call may use any caller-saved
8171 registers in epilogue, DRAP must not use caller-saved
8172 register in such case. */
8173 if ((decl_function_context (decl)
8174 && !DECL_NO_STATIC_CHAIN (decl))
8175 || crtl->tail_call_emit)
8182 /* Use DI for nested function or function need static chain.
8183 Since function with tail call may use any caller-saved
8184 registers in epilogue, DRAP must not use caller-saved
8185 register in such case. */
8186 if ((decl_function_context (decl)
8187 && !DECL_NO_STATIC_CHAIN (decl))
8188 || crtl->tail_call_emit)
8191 /* Reuse static chain register if it isn't used for parameter
8193 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8194 && !lookup_attribute ("fastcall",
8195 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8202 /* Update incoming stack boundary and estimated stack alignment. */
8205 ix86_update_stack_boundary (void)
8207 /* Prefer the one specified at command line. */
8208 ix86_incoming_stack_boundary
8209 = (ix86_user_incoming_stack_boundary
8210 ? ix86_user_incoming_stack_boundary
8211 : ix86_default_incoming_stack_boundary);
8213 /* Incoming stack alignment can be changed on individual functions
8214 via force_align_arg_pointer attribute. We use the smallest
8215 incoming stack boundary. */
8216 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
8217 && lookup_attribute (ix86_force_align_arg_pointer_string,
8218 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8219 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
8221 /* The incoming stack frame has to be aligned at least at
8222 parm_stack_boundary. */
8223 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
8224 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
8226 /* Stack at entrance of main is aligned by runtime. We use the
8227 smallest incoming stack boundary. */
8228 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
8229 && DECL_NAME (current_function_decl)
8230 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8231 && DECL_FILE_SCOPE_P (current_function_decl))
8232 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8234 /* x86_64 vararg needs 16byte stack alignment for register save
8238 && crtl->stack_alignment_estimated < 128)
8239 crtl->stack_alignment_estimated = 128;
8242 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8243 needed or an rtx for DRAP otherwise. */
8246 ix86_get_drap_rtx (void)
8248 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8249 crtl->need_drap = true;
8251 if (stack_realign_drap)
8253 /* Assign DRAP to vDRAP and returns vDRAP */
8254 unsigned int regno = find_drap_reg ();
8259 arg_ptr = gen_rtx_REG (Pmode, regno);
8260 crtl->drap_reg = arg_ptr;
8263 drap_vreg = copy_to_reg (arg_ptr);
8267 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8268 RTX_FRAME_RELATED_P (insn) = 1;
8275 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8278 ix86_internal_arg_pointer (void)
8280 return virtual_incoming_args_rtx;
8283 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8284 to be generated in correct form. */
8286 ix86_finalize_stack_realign_flags (void)
8288 /* Check if stack realign is really needed after reload, and
8289 stores result in cfun */
8290 unsigned int incoming_stack_boundary
8291 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8292 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8293 unsigned int stack_realign = (incoming_stack_boundary
8294 < (current_function_is_leaf
8295 ? crtl->max_used_stack_slot_alignment
8296 : crtl->stack_alignment_needed));
8298 if (crtl->stack_realign_finalized)
8300 /* After stack_realign_needed is finalized, we can't no longer
8302 gcc_assert (crtl->stack_realign_needed == stack_realign);
8306 crtl->stack_realign_needed = stack_realign;
8307 crtl->stack_realign_finalized = true;
8311 /* Expand the prologue into a bunch of separate insns. */
8314 ix86_expand_prologue (void)
8318 struct ix86_frame frame;
8319 HOST_WIDE_INT allocate;
8321 ix86_finalize_stack_realign_flags ();
8323 /* DRAP should not coexist with stack_realign_fp */
8324 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8326 /* Initialize CFA state for before the prologue. */
8327 ix86_cfa_state->reg = stack_pointer_rtx;
8328 ix86_cfa_state->offset = INCOMING_FRAME_SP_OFFSET;
8330 ix86_compute_frame_layout (&frame);
8332 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8333 of DRAP is needed and stack realignment is really needed after reload */
8334 if (crtl->drap_reg && crtl->stack_realign_needed)
8337 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8338 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8339 ? 0 : UNITS_PER_WORD);
8341 gcc_assert (stack_realign_drap);
8343 /* Grab the argument pointer. */
8344 x = plus_constant (stack_pointer_rtx,
8345 (UNITS_PER_WORD + param_ptr_offset));
8348 /* Only need to push parameter pointer reg if it is caller
8350 if (!call_used_regs[REGNO (crtl->drap_reg)])
8352 /* Push arg pointer reg */
8353 insn = emit_insn (gen_push (y));
8354 RTX_FRAME_RELATED_P (insn) = 1;
8357 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8358 RTX_FRAME_RELATED_P (insn) = 1;
8359 ix86_cfa_state->reg = crtl->drap_reg;
8361 /* Align the stack. */
8362 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8364 GEN_INT (-align_bytes)));
8365 RTX_FRAME_RELATED_P (insn) = 1;
8367 /* Replicate the return address on the stack so that return
8368 address can be reached via (argp - 1) slot. This is needed
8369 to implement macro RETURN_ADDR_RTX and intrinsic function
8370 expand_builtin_return_addr etc. */
8372 x = gen_frame_mem (Pmode,
8373 plus_constant (x, -UNITS_PER_WORD));
8374 insn = emit_insn (gen_push (x));
8375 RTX_FRAME_RELATED_P (insn) = 1;
8378 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8379 slower on all targets. Also sdb doesn't like it. */
8381 if (frame_pointer_needed)
8383 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8384 RTX_FRAME_RELATED_P (insn) = 1;
8386 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8387 RTX_FRAME_RELATED_P (insn) = 1;
8389 if (ix86_cfa_state->reg == stack_pointer_rtx)
8390 ix86_cfa_state->reg = hard_frame_pointer_rtx;
8393 if (stack_realign_fp)
8395 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8396 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8398 /* Align the stack. */
8399 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8401 GEN_INT (-align_bytes)));
8402 RTX_FRAME_RELATED_P (insn) = 1;
8405 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8407 if (!frame.save_regs_using_mov)
8408 ix86_emit_save_regs ();
8410 allocate += frame.nregs * UNITS_PER_WORD;
8412 /* When using red zone we may start register saving before allocating
8413 the stack frame saving one cycle of the prologue. However I will
8414 avoid doing this if I am going to have to probe the stack since
8415 at least on x86_64 the stack probe can turn into a call that clobbers
8416 a red zone location */
8417 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8418 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8419 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8420 && !crtl->stack_realign_needed)
8421 ? hard_frame_pointer_rtx
8422 : stack_pointer_rtx,
8423 -frame.nregs * UNITS_PER_WORD);
8427 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8428 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8429 GEN_INT (-allocate), -1,
8430 ix86_cfa_state->reg == stack_pointer_rtx);
8433 /* Only valid for Win32. */
8434 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8438 gcc_assert (!TARGET_64BIT || cfun->machine->call_abi == MS_ABI);
8440 if (cfun->machine->call_abi == MS_ABI)
8443 eax_live = ix86_eax_live_at_start_p ();
8447 emit_insn (gen_push (eax));
8448 allocate -= UNITS_PER_WORD;
8451 emit_move_insn (eax, GEN_INT (allocate));
8454 insn = gen_allocate_stack_worker_64 (eax, eax);
8456 insn = gen_allocate_stack_worker_32 (eax, eax);
8457 insn = emit_insn (insn);
8459 if (ix86_cfa_state->reg == stack_pointer_rtx)
8461 ix86_cfa_state->offset += allocate;
8462 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8463 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8464 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
8465 RTX_FRAME_RELATED_P (insn) = 1;
8470 if (frame_pointer_needed)
8471 t = plus_constant (hard_frame_pointer_rtx,
8474 - frame.nregs * UNITS_PER_WORD);
8476 t = plus_constant (stack_pointer_rtx, allocate);
8477 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8481 if (frame.save_regs_using_mov
8482 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8483 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8485 if (!frame_pointer_needed
8486 || !(frame.to_allocate + frame.padding0)
8487 || crtl->stack_realign_needed)
8488 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8490 + frame.nsseregs * 16 + frame.padding0);
8492 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8493 -frame.nregs * UNITS_PER_WORD);
8495 if (!frame_pointer_needed
8496 || !(frame.to_allocate + frame.padding0)
8497 || crtl->stack_realign_needed)
8498 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8501 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8502 - frame.nregs * UNITS_PER_WORD
8503 - frame.nsseregs * 16
8506 pic_reg_used = false;
8507 if (pic_offset_table_rtx
8508 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8511 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8513 if (alt_pic_reg_used != INVALID_REGNUM)
8514 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8516 pic_reg_used = true;
8523 if (ix86_cmodel == CM_LARGE_PIC)
8525 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8526 rtx label = gen_label_rtx ();
8528 LABEL_PRESERVE_P (label) = 1;
8529 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8530 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8531 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8532 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8533 pic_offset_table_rtx, tmp_reg));
8536 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8539 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8542 /* In the pic_reg_used case, make sure that the got load isn't deleted
8543 when mcount needs it. Blockage to avoid call movement across mcount
8544 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8546 if (crtl->profile && pic_reg_used)
8547 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8549 if (crtl->drap_reg && !crtl->stack_realign_needed)
8551 /* vDRAP is setup but after reload it turns out stack realign
8552 isn't necessary, here we will emit prologue to setup DRAP
8553 without stack realign adjustment */
8554 int drap_bp_offset = UNITS_PER_WORD * 2;
8555 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8556 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8559 /* Prevent instructions from being scheduled into register save push
8560 sequence when access to the redzone area is done through frame pointer.
8561 The offset betweeh the frame pointer and the stack pointer is calculated
8562 relative to the value of the stack pointer at the end of the function
8563 prologue, and moving instructions that access redzone area via frame
8564 pointer inside push sequence violates this assumption. */
8565 if (frame_pointer_needed && frame.red_zone_size)
8566 emit_insn (gen_memory_blockage ());
8568 /* Emit cld instruction if stringops are used in the function. */
8569 if (TARGET_CLD && ix86_current_function_needs_cld)
8570 emit_insn (gen_cld ());
8573 /* Emit code to restore REG using a POP insn. */
8576 ix86_emit_restore_reg_using_pop (rtx reg, HOST_WIDE_INT red_offset)
8578 rtx insn = emit_insn (ix86_gen_pop1 (reg));
8580 if (ix86_cfa_state->reg == crtl->drap_reg
8581 && REGNO (reg) == REGNO (crtl->drap_reg))
8583 /* Previously we'd represented the CFA as an expression
8584 like *(%ebp - 8). We've just popped that value from
8585 the stack, which means we need to reset the CFA to
8586 the drap register. This will remain until we restore
8587 the stack pointer. */
8588 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8589 RTX_FRAME_RELATED_P (insn) = 1;
8593 if (ix86_cfa_state->reg == stack_pointer_rtx)
8595 ix86_cfa_state->offset -= UNITS_PER_WORD;
8596 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8597 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
8598 RTX_FRAME_RELATED_P (insn) = 1;
8601 /* When the frame pointer is the CFA, and we pop it, we are
8602 swapping back to the stack pointer as the CFA. This happens
8603 for stack frames that don't allocate other data, so we assume
8604 the stack pointer is now pointing at the return address, i.e.
8605 the function entry state, which makes the offset be 1 word. */
8606 else if (ix86_cfa_state->reg == hard_frame_pointer_rtx
8607 && reg == hard_frame_pointer_rtx)
8609 ix86_cfa_state->reg = stack_pointer_rtx;
8610 ix86_cfa_state->offset = UNITS_PER_WORD;
8612 add_reg_note (insn, REG_CFA_DEF_CFA,
8613 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8614 GEN_INT (UNITS_PER_WORD)));
8615 RTX_FRAME_RELATED_P (insn) = 1;
8618 ix86_add_cfa_restore_note (insn, reg, red_offset);
8621 /* Emit code to restore saved registers using POP insns. */
8624 ix86_emit_restore_regs_using_pop (HOST_WIDE_INT red_offset)
8628 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8629 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8631 ix86_emit_restore_reg_using_pop (gen_rtx_REG (Pmode, regno),
8633 red_offset += UNITS_PER_WORD;
8637 /* Emit code and notes for the LEAVE instruction. */
8640 ix86_emit_leave (HOST_WIDE_INT red_offset)
8642 rtx insn = emit_insn (ix86_gen_leave ());
8644 ix86_add_queued_cfa_restore_notes (insn);
8646 if (ix86_cfa_state->reg == hard_frame_pointer_rtx)
8648 add_reg_note (insn, REG_CFA_ADJUST_CFA,
8649 copy_rtx (XVECEXP (PATTERN (insn), 0, 0)));
8650 RTX_FRAME_RELATED_P (insn) = 1;
8651 ix86_add_cfa_restore_note (insn, hard_frame_pointer_rtx, red_offset);
8655 /* Emit code to restore saved registers using MOV insns. First register
8656 is restored from POINTER + OFFSET. */
8658 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8659 HOST_WIDE_INT red_offset,
8660 int maybe_eh_return)
8663 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8666 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8667 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8669 rtx reg = gen_rtx_REG (Pmode, regno);
8671 /* Ensure that adjust_address won't be forced to produce pointer
8672 out of range allowed by x86-64 instruction set. */
8673 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8677 r11 = gen_rtx_REG (DImode, R11_REG);
8678 emit_move_insn (r11, GEN_INT (offset));
8679 emit_insn (gen_adddi3 (r11, r11, pointer));
8680 base_address = gen_rtx_MEM (Pmode, r11);
8683 insn = emit_move_insn (reg,
8684 adjust_address (base_address, Pmode, offset));
8685 offset += UNITS_PER_WORD;
8687 if (ix86_cfa_state->reg == crtl->drap_reg
8688 && regno == REGNO (crtl->drap_reg))
8690 /* Previously we'd represented the CFA as an expression
8691 like *(%ebp - 8). We've just popped that value from
8692 the stack, which means we need to reset the CFA to
8693 the drap register. This will remain until we restore
8694 the stack pointer. */
8695 add_reg_note (insn, REG_CFA_DEF_CFA, reg);
8696 RTX_FRAME_RELATED_P (insn) = 1;
8699 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8701 red_offset += UNITS_PER_WORD;
8705 /* Emit code to restore saved registers using MOV insns. First register
8706 is restored from POINTER + OFFSET. */
8708 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8709 HOST_WIDE_INT red_offset,
8710 int maybe_eh_return)
8713 rtx base_address = gen_rtx_MEM (TImode, pointer);
8716 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8717 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8719 rtx reg = gen_rtx_REG (TImode, regno);
8721 /* Ensure that adjust_address won't be forced to produce pointer
8722 out of range allowed by x86-64 instruction set. */
8723 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8727 r11 = gen_rtx_REG (DImode, R11_REG);
8728 emit_move_insn (r11, GEN_INT (offset));
8729 emit_insn (gen_adddi3 (r11, r11, pointer));
8730 base_address = gen_rtx_MEM (TImode, r11);
8733 mem = adjust_address (base_address, TImode, offset);
8734 set_mem_align (mem, 128);
8735 insn = emit_move_insn (reg, mem);
8738 ix86_add_cfa_restore_note (NULL_RTX, reg, red_offset);
8744 /* Restore function stack, frame, and registers. */
8747 ix86_expand_epilogue (int style)
8750 struct ix86_frame frame;
8751 HOST_WIDE_INT offset, red_offset;
8752 struct machine_cfa_state cfa_state_save = *ix86_cfa_state;
8755 ix86_finalize_stack_realign_flags ();
8757 /* When stack is realigned, SP must be valid. */
8758 sp_valid = (!frame_pointer_needed
8759 || current_function_sp_is_unchanging
8760 || stack_realign_fp);
8762 ix86_compute_frame_layout (&frame);
8764 /* See the comment about red zone and frame
8765 pointer usage in ix86_expand_prologue. */
8766 if (frame_pointer_needed && frame.red_zone_size)
8767 emit_insn (gen_memory_blockage ());
8769 using_drap = crtl->drap_reg && crtl->stack_realign_needed;
8770 gcc_assert (!using_drap || ix86_cfa_state->reg == crtl->drap_reg);
8772 /* Calculate start of saved registers relative to ebp. Special care
8773 must be taken for the normal return case of a function using
8774 eh_return: the eax and edx registers are marked as saved, but not
8775 restored along this path. */
8776 offset = frame.nregs;
8777 if (crtl->calls_eh_return && style != 2)
8779 offset *= -UNITS_PER_WORD;
8780 offset -= frame.nsseregs * 16 + frame.padding0;
8782 /* Calculate start of saved registers relative to esp on entry of the
8783 function. When realigning stack, this needs to be the most negative
8784 value possible at runtime. */
8785 red_offset = offset;
8787 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8789 else if (stack_realign_fp)
8790 red_offset -= crtl->stack_alignment_needed / BITS_PER_UNIT
8792 if (frame_pointer_needed)
8793 red_offset -= UNITS_PER_WORD;
8795 /* If we're only restoring one register and sp is not valid then
8796 using a move instruction to restore the register since it's
8797 less work than reloading sp and popping the register.
8799 The default code result in stack adjustment using add/lea instruction,
8800 while this code results in LEAVE instruction (or discrete equivalent),
8801 so it is profitable in some other cases as well. Especially when there
8802 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8803 and there is exactly one register to pop. This heuristic may need some
8804 tuning in future. */
8805 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8806 || (TARGET_EPILOGUE_USING_MOVE
8807 && cfun->machine->use_fast_prologue_epilogue
8808 && ((frame.nregs + frame.nsseregs) > 1
8809 || (frame.to_allocate + frame.padding0) != 0))
8810 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8811 && (frame.to_allocate + frame.padding0) != 0)
8812 || (frame_pointer_needed && TARGET_USE_LEAVE
8813 && cfun->machine->use_fast_prologue_epilogue
8814 && (frame.nregs + frame.nsseregs) == 1)
8815 || crtl->calls_eh_return)
8817 /* Restore registers. We can use ebp or esp to address the memory
8818 locations. If both are available, default to ebp, since offsets
8819 are known to be small. Only exception is esp pointing directly
8820 to the end of block of saved registers, where we may simplify
8823 If we are realigning stack with bp and sp, regs restore can't
8824 be addressed by bp. sp must be used instead. */
8826 if (!frame_pointer_needed
8827 || (sp_valid && !(frame.to_allocate + frame.padding0))
8828 || stack_realign_fp)
8830 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8831 frame.to_allocate, red_offset,
8833 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8835 + frame.nsseregs * 16
8838 + frame.nsseregs * 16
8839 + frame.padding0, style == 2);
8843 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8846 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8848 + frame.nsseregs * 16
8851 + frame.nsseregs * 16
8852 + frame.padding0, style == 2);
8855 red_offset -= offset;
8857 /* eh_return epilogues need %ecx added to the stack pointer. */
8860 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8862 /* Stack align doesn't work with eh_return. */
8863 gcc_assert (!crtl->stack_realign_needed);
8865 if (frame_pointer_needed)
8867 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8868 tmp = plus_constant (tmp, UNITS_PER_WORD);
8869 tmp = emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8871 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8872 tmp = emit_move_insn (hard_frame_pointer_rtx, tmp);
8874 /* Note that we use SA as a temporary CFA, as the return
8875 address is at the proper place relative to it. We
8876 pretend this happens at the FP restore insn because
8877 prior to this insn the FP would be stored at the wrong
8878 offset relative to SA, and after this insn we have no
8879 other reasonable register to use for the CFA. We don't
8880 bother resetting the CFA to the SP for the duration of
8882 add_reg_note (tmp, REG_CFA_DEF_CFA,
8883 plus_constant (sa, UNITS_PER_WORD));
8884 ix86_add_queued_cfa_restore_notes (tmp);
8885 add_reg_note (tmp, REG_CFA_RESTORE, hard_frame_pointer_rtx);
8886 RTX_FRAME_RELATED_P (tmp) = 1;
8887 ix86_cfa_state->reg = sa;
8888 ix86_cfa_state->offset = UNITS_PER_WORD;
8890 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8891 const0_rtx, style, false);
8895 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8896 tmp = plus_constant (tmp, (frame.to_allocate
8897 + frame.nregs * UNITS_PER_WORD
8898 + frame.nsseregs * 16
8900 tmp = emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8901 ix86_add_queued_cfa_restore_notes (tmp);
8903 gcc_assert (ix86_cfa_state->reg == stack_pointer_rtx);
8904 if (ix86_cfa_state->offset != UNITS_PER_WORD)
8906 ix86_cfa_state->offset = UNITS_PER_WORD;
8907 add_reg_note (tmp, REG_CFA_DEF_CFA,
8908 plus_constant (stack_pointer_rtx,
8910 RTX_FRAME_RELATED_P (tmp) = 1;
8914 else if (!frame_pointer_needed)
8915 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8916 GEN_INT (frame.to_allocate
8917 + frame.nregs * UNITS_PER_WORD
8918 + frame.nsseregs * 16
8920 style, !using_drap);
8921 /* If not an i386, mov & pop is faster than "leave". */
8922 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8923 || !cfun->machine->use_fast_prologue_epilogue)
8924 ix86_emit_leave (red_offset);
8927 pro_epilogue_adjust_stack (stack_pointer_rtx,
8928 hard_frame_pointer_rtx,
8929 const0_rtx, style, !using_drap);
8931 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx, red_offset);
8936 /* First step is to deallocate the stack frame so that we can
8939 If we realign stack with frame pointer, then stack pointer
8940 won't be able to recover via lea $offset(%bp), %sp, because
8941 there is a padding area between bp and sp for realign.
8942 "add $to_allocate, %sp" must be used instead. */
8945 gcc_assert (frame_pointer_needed);
8946 gcc_assert (!stack_realign_fp);
8947 pro_epilogue_adjust_stack (stack_pointer_rtx,
8948 hard_frame_pointer_rtx,
8949 GEN_INT (offset), style, false);
8950 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8951 frame.to_allocate, red_offset,
8953 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8954 GEN_INT (frame.nsseregs * 16 + frame.padding0),
8957 else if (frame.to_allocate || frame.padding0 || frame.nsseregs)
8959 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8960 frame.to_allocate, red_offset,
8962 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8963 GEN_INT (frame.to_allocate
8964 + frame.nsseregs * 16
8965 + frame.padding0), style,
8966 !using_drap && !frame_pointer_needed);
8969 ix86_emit_restore_regs_using_pop (red_offset + frame.nsseregs * 16
8971 red_offset -= offset;
8973 if (frame_pointer_needed)
8975 /* Leave results in shorter dependency chains on CPUs that are
8976 able to grok it fast. */
8977 if (TARGET_USE_LEAVE)
8978 ix86_emit_leave (red_offset);
8981 /* For stack realigned really happens, recover stack
8982 pointer to hard frame pointer is a must, if not using
8984 if (stack_realign_fp)
8985 pro_epilogue_adjust_stack (stack_pointer_rtx,
8986 hard_frame_pointer_rtx,
8987 const0_rtx, style, !using_drap);
8988 ix86_emit_restore_reg_using_pop (hard_frame_pointer_rtx,
8996 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8997 ? 0 : UNITS_PER_WORD);
9000 gcc_assert (stack_realign_drap);
9002 insn = emit_insn ((*ix86_gen_add3) (stack_pointer_rtx,
9004 GEN_INT (-(UNITS_PER_WORD
9005 + param_ptr_offset))));
9007 ix86_cfa_state->reg = stack_pointer_rtx;
9008 ix86_cfa_state->offset = UNITS_PER_WORD + param_ptr_offset;
9010 add_reg_note (insn, REG_CFA_DEF_CFA,
9011 gen_rtx_PLUS (Pmode, ix86_cfa_state->reg,
9012 GEN_INT (ix86_cfa_state->offset)));
9013 RTX_FRAME_RELATED_P (insn) = 1;
9015 if (param_ptr_offset)
9016 ix86_emit_restore_reg_using_pop (crtl->drap_reg, -UNITS_PER_WORD);
9019 /* Sibcall epilogues don't want a return instruction. */
9022 *ix86_cfa_state = cfa_state_save;
9026 if (crtl->args.pops_args && crtl->args.size)
9028 rtx popc = GEN_INT (crtl->args.pops_args);
9030 /* i386 can only pop 64K bytes. If asked to pop more, pop return
9031 address, do explicit add, and jump indirectly to the caller. */
9033 if (crtl->args.pops_args >= 65536)
9035 rtx ecx = gen_rtx_REG (SImode, CX_REG);
9038 /* There is no "pascal" calling convention in any 64bit ABI. */
9039 gcc_assert (!TARGET_64BIT);
9041 insn = emit_insn (gen_popsi1 (ecx));
9042 ix86_cfa_state->offset -= UNITS_PER_WORD;
9044 add_reg_note (insn, REG_CFA_ADJUST_CFA,
9045 copy_rtx (XVECEXP (PATTERN (insn), 0, 1)));
9046 add_reg_note (insn, REG_CFA_REGISTER,
9047 gen_rtx_SET (VOIDmode, ecx, pc_rtx));
9048 RTX_FRAME_RELATED_P (insn) = 1;
9050 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
9052 emit_jump_insn (gen_return_indirect_internal (ecx));
9055 emit_jump_insn (gen_return_pop_internal (popc));
9058 emit_jump_insn (gen_return_internal ());
9060 /* Restore the state back to the state from the prologue,
9061 so that it's correct for the next epilogue. */
9062 *ix86_cfa_state = cfa_state_save;
9065 /* Reset from the function's potential modifications. */
9068 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9069 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9071 if (pic_offset_table_rtx)
9072 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
9074 /* Mach-O doesn't support labels at the end of objects, so if
9075 it looks like we might want one, insert a NOP. */
9077 rtx insn = get_last_insn ();
9080 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
9081 insn = PREV_INSN (insn);
9085 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
9086 fputs ("\tnop\n", file);
9092 /* Extract the parts of an RTL expression that is a valid memory address
9093 for an instruction. Return 0 if the structure of the address is
9094 grossly off. Return -1 if the address contains ASHIFT, so it is not
9095 strictly valid, but still used for computing length of lea instruction. */
9098 ix86_decompose_address (rtx addr, struct ix86_address *out)
9100 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
9101 rtx base_reg, index_reg;
9102 HOST_WIDE_INT scale = 1;
9103 rtx scale_rtx = NULL_RTX;
9105 enum ix86_address_seg seg = SEG_DEFAULT;
9107 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
9109 else if (GET_CODE (addr) == PLUS)
9119 addends[n++] = XEXP (op, 1);
9122 while (GET_CODE (op) == PLUS);
9127 for (i = n; i >= 0; --i)
9130 switch (GET_CODE (op))
9135 index = XEXP (op, 0);
9136 scale_rtx = XEXP (op, 1);
9140 if (XINT (op, 1) == UNSPEC_TP
9141 && TARGET_TLS_DIRECT_SEG_REFS
9142 && seg == SEG_DEFAULT)
9143 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
9172 else if (GET_CODE (addr) == MULT)
9174 index = XEXP (addr, 0); /* index*scale */
9175 scale_rtx = XEXP (addr, 1);
9177 else if (GET_CODE (addr) == ASHIFT)
9181 /* We're called for lea too, which implements ashift on occasion. */
9182 index = XEXP (addr, 0);
9183 tmp = XEXP (addr, 1);
9184 if (!CONST_INT_P (tmp))
9186 scale = INTVAL (tmp);
9187 if ((unsigned HOST_WIDE_INT) scale > 3)
9193 disp = addr; /* displacement */
9195 /* Extract the integral value of scale. */
9198 if (!CONST_INT_P (scale_rtx))
9200 scale = INTVAL (scale_rtx);
9203 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
9204 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
9206 /* Avoid useless 0 displacement. */
9207 if (disp == const0_rtx && (base || index))
9210 /* Allow arg pointer and stack pointer as index if there is not scaling. */
9211 if (base_reg && index_reg && scale == 1
9212 && (index_reg == arg_pointer_rtx
9213 || index_reg == frame_pointer_rtx
9214 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
9217 tmp = base, base = index, index = tmp;
9218 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
9221 /* Special case: %ebp cannot be encoded as a base without a displacement.
9225 && (base_reg == hard_frame_pointer_rtx
9226 || base_reg == frame_pointer_rtx
9227 || base_reg == arg_pointer_rtx
9228 || (REG_P (base_reg)
9229 && (REGNO (base_reg) == HARD_FRAME_POINTER_REGNUM
9230 || REGNO (base_reg) == R13_REG))))
9233 /* Special case: on K6, [%esi] makes the instruction vector decoded.
9234 Avoid this by transforming to [%esi+0].
9235 Reload calls address legitimization without cfun defined, so we need
9236 to test cfun for being non-NULL. */
9237 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
9238 && base_reg && !index_reg && !disp
9240 && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
9243 /* Special case: encode reg+reg instead of reg*2. */
9244 if (!base && index && scale == 2)
9245 base = index, base_reg = index_reg, scale = 1;
9247 /* Special case: scaling cannot be encoded without base or displacement. */
9248 if (!base && !disp && index && scale != 1)
9260 /* Return cost of the memory address x.
9261 For i386, it is better to use a complex address than let gcc copy
9262 the address into a reg and make a new pseudo. But not if the address
9263 requires to two regs - that would mean more pseudos with longer
9266 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
9268 struct ix86_address parts;
9270 int ok = ix86_decompose_address (x, &parts);
9274 if (parts.base && GET_CODE (parts.base) == SUBREG)
9275 parts.base = SUBREG_REG (parts.base);
9276 if (parts.index && GET_CODE (parts.index) == SUBREG)
9277 parts.index = SUBREG_REG (parts.index);
9279 /* Attempt to minimize number of registers in the address. */
9281 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
9283 && (!REG_P (parts.index)
9284 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
9288 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
9290 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
9291 && parts.base != parts.index)
9294 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
9295 since it's predecode logic can't detect the length of instructions
9296 and it degenerates to vector decoded. Increase cost of such
9297 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
9298 to split such addresses or even refuse such addresses at all.
9300 Following addressing modes are affected:
9305 The first and last case may be avoidable by explicitly coding the zero in
9306 memory address, but I don't have AMD-K6 machine handy to check this
9310 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
9311 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
9312 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
9318 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
9319 this is used for to form addresses to local data when -fPIC is in
9323 darwin_local_data_pic (rtx disp)
9325 return (GET_CODE (disp) == UNSPEC
9326 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
9329 /* Determine if a given RTX is a valid constant. We already know this
9330 satisfies CONSTANT_P. */
9333 legitimate_constant_p (rtx x)
9335 switch (GET_CODE (x))
9340 if (GET_CODE (x) == PLUS)
9342 if (!CONST_INT_P (XEXP (x, 1)))
9347 if (TARGET_MACHO && darwin_local_data_pic (x))
9350 /* Only some unspecs are valid as "constants". */
9351 if (GET_CODE (x) == UNSPEC)
9352 switch (XINT (x, 1))
9357 return TARGET_64BIT;
9360 x = XVECEXP (x, 0, 0);
9361 return (GET_CODE (x) == SYMBOL_REF
9362 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9364 x = XVECEXP (x, 0, 0);
9365 return (GET_CODE (x) == SYMBOL_REF
9366 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9371 /* We must have drilled down to a symbol. */
9372 if (GET_CODE (x) == LABEL_REF)
9374 if (GET_CODE (x) != SYMBOL_REF)
9379 /* TLS symbols are never valid. */
9380 if (SYMBOL_REF_TLS_MODEL (x))
9383 /* DLLIMPORT symbols are never valid. */
9384 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9385 && SYMBOL_REF_DLLIMPORT_P (x))
9390 if (GET_MODE (x) == TImode
9391 && x != CONST0_RTX (TImode)
9397 if (!standard_sse_constant_p (x))
9404 /* Otherwise we handle everything else in the move patterns. */
9408 /* Determine if it's legal to put X into the constant pool. This
9409 is not possible for the address of thread-local symbols, which
9410 is checked above. */
9413 ix86_cannot_force_const_mem (rtx x)
9415 /* We can always put integral constants and vectors in memory. */
9416 switch (GET_CODE (x))
9426 return !legitimate_constant_p (x);
9430 /* Nonzero if the constant value X is a legitimate general operand
9431 when generating PIC code. It is given that flag_pic is on and
9432 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9435 legitimate_pic_operand_p (rtx x)
9439 switch (GET_CODE (x))
9442 inner = XEXP (x, 0);
9443 if (GET_CODE (inner) == PLUS
9444 && CONST_INT_P (XEXP (inner, 1)))
9445 inner = XEXP (inner, 0);
9447 /* Only some unspecs are valid as "constants". */
9448 if (GET_CODE (inner) == UNSPEC)
9449 switch (XINT (inner, 1))
9454 return TARGET_64BIT;
9456 x = XVECEXP (inner, 0, 0);
9457 return (GET_CODE (x) == SYMBOL_REF
9458 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9459 case UNSPEC_MACHOPIC_OFFSET:
9460 return legitimate_pic_address_disp_p (x);
9468 return legitimate_pic_address_disp_p (x);
9475 /* Determine if a given CONST RTX is a valid memory displacement
9479 legitimate_pic_address_disp_p (rtx disp)
9483 /* In 64bit mode we can allow direct addresses of symbols and labels
9484 when they are not dynamic symbols. */
9487 rtx op0 = disp, op1;
9489 switch (GET_CODE (disp))
9495 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9497 op0 = XEXP (XEXP (disp, 0), 0);
9498 op1 = XEXP (XEXP (disp, 0), 1);
9499 if (!CONST_INT_P (op1)
9500 || INTVAL (op1) >= 16*1024*1024
9501 || INTVAL (op1) < -16*1024*1024)
9503 if (GET_CODE (op0) == LABEL_REF)
9505 if (GET_CODE (op0) != SYMBOL_REF)
9510 /* TLS references should always be enclosed in UNSPEC. */
9511 if (SYMBOL_REF_TLS_MODEL (op0))
9513 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9514 && ix86_cmodel != CM_LARGE_PIC)
9522 if (GET_CODE (disp) != CONST)
9524 disp = XEXP (disp, 0);
9528 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9529 of GOT tables. We should not need these anyway. */
9530 if (GET_CODE (disp) != UNSPEC
9531 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9532 && XINT (disp, 1) != UNSPEC_GOTOFF
9533 && XINT (disp, 1) != UNSPEC_PLTOFF))
9536 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9537 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9543 if (GET_CODE (disp) == PLUS)
9545 if (!CONST_INT_P (XEXP (disp, 1)))
9547 disp = XEXP (disp, 0);
9551 if (TARGET_MACHO && darwin_local_data_pic (disp))
9554 if (GET_CODE (disp) != UNSPEC)
9557 switch (XINT (disp, 1))
9562 /* We need to check for both symbols and labels because VxWorks loads
9563 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9565 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9566 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9568 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9569 While ABI specify also 32bit relocation but we don't produce it in
9570 small PIC model at all. */
9571 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9572 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9574 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9576 case UNSPEC_GOTTPOFF:
9577 case UNSPEC_GOTNTPOFF:
9578 case UNSPEC_INDNTPOFF:
9581 disp = XVECEXP (disp, 0, 0);
9582 return (GET_CODE (disp) == SYMBOL_REF
9583 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9585 disp = XVECEXP (disp, 0, 0);
9586 return (GET_CODE (disp) == SYMBOL_REF
9587 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9589 disp = XVECEXP (disp, 0, 0);
9590 return (GET_CODE (disp) == SYMBOL_REF
9591 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9597 /* Recognizes RTL expressions that are valid memory addresses for an
9598 instruction. The MODE argument is the machine mode for the MEM
9599 expression that wants to use this address.
9601 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9602 convert common non-canonical forms to canonical form so that they will
9606 ix86_legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9607 rtx addr, bool strict)
9609 struct ix86_address parts;
9610 rtx base, index, disp;
9611 HOST_WIDE_INT scale;
9612 const char *reason = NULL;
9613 rtx reason_rtx = NULL_RTX;
9615 if (ix86_decompose_address (addr, &parts) <= 0)
9617 reason = "decomposition failed";
9622 index = parts.index;
9624 scale = parts.scale;
9626 /* Validate base register.
9628 Don't allow SUBREG's that span more than a word here. It can lead to spill
9629 failures when the base is one word out of a two word structure, which is
9630 represented internally as a DImode int. */
9639 else if (GET_CODE (base) == SUBREG
9640 && REG_P (SUBREG_REG (base))
9641 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9643 reg = SUBREG_REG (base);
9646 reason = "base is not a register";
9650 if (GET_MODE (base) != Pmode)
9652 reason = "base is not in Pmode";
9656 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9657 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9659 reason = "base is not valid";
9664 /* Validate index register.
9666 Don't allow SUBREG's that span more than a word here -- same as above. */
9675 else if (GET_CODE (index) == SUBREG
9676 && REG_P (SUBREG_REG (index))
9677 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9679 reg = SUBREG_REG (index);
9682 reason = "index is not a register";
9686 if (GET_MODE (index) != Pmode)
9688 reason = "index is not in Pmode";
9692 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9693 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9695 reason = "index is not valid";
9700 /* Validate scale factor. */
9703 reason_rtx = GEN_INT (scale);
9706 reason = "scale without index";
9710 if (scale != 2 && scale != 4 && scale != 8)
9712 reason = "scale is not a valid multiplier";
9717 /* Validate displacement. */
9722 if (GET_CODE (disp) == CONST
9723 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9724 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9725 switch (XINT (XEXP (disp, 0), 1))
9727 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9728 used. While ABI specify also 32bit relocations, we don't produce
9729 them at all and use IP relative instead. */
9732 gcc_assert (flag_pic);
9734 goto is_legitimate_pic;
9735 reason = "64bit address unspec";
9738 case UNSPEC_GOTPCREL:
9739 gcc_assert (flag_pic);
9740 goto is_legitimate_pic;
9742 case UNSPEC_GOTTPOFF:
9743 case UNSPEC_GOTNTPOFF:
9744 case UNSPEC_INDNTPOFF:
9750 reason = "invalid address unspec";
9754 else if (SYMBOLIC_CONST (disp)
9758 && MACHOPIC_INDIRECT
9759 && !machopic_operand_p (disp)
9765 if (TARGET_64BIT && (index || base))
9767 /* foo@dtpoff(%rX) is ok. */
9768 if (GET_CODE (disp) != CONST
9769 || GET_CODE (XEXP (disp, 0)) != PLUS
9770 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9771 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9772 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9773 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9775 reason = "non-constant pic memory reference";
9779 else if (! legitimate_pic_address_disp_p (disp))
9781 reason = "displacement is an invalid pic construct";
9785 /* This code used to verify that a symbolic pic displacement
9786 includes the pic_offset_table_rtx register.
9788 While this is good idea, unfortunately these constructs may
9789 be created by "adds using lea" optimization for incorrect
9798 This code is nonsensical, but results in addressing
9799 GOT table with pic_offset_table_rtx base. We can't
9800 just refuse it easily, since it gets matched by
9801 "addsi3" pattern, that later gets split to lea in the
9802 case output register differs from input. While this
9803 can be handled by separate addsi pattern for this case
9804 that never results in lea, this seems to be easier and
9805 correct fix for crash to disable this test. */
9807 else if (GET_CODE (disp) != LABEL_REF
9808 && !CONST_INT_P (disp)
9809 && (GET_CODE (disp) != CONST
9810 || !legitimate_constant_p (disp))
9811 && (GET_CODE (disp) != SYMBOL_REF
9812 || !legitimate_constant_p (disp)))
9814 reason = "displacement is not constant";
9817 else if (TARGET_64BIT
9818 && !x86_64_immediate_operand (disp, VOIDmode))
9820 reason = "displacement is out of range";
9825 /* Everything looks valid. */
9832 /* Determine if a given RTX is a valid constant address. */
9835 constant_address_p (rtx x)
9837 return CONSTANT_P (x) && ix86_legitimate_address_p (Pmode, x, 1);
9840 /* Return a unique alias set for the GOT. */
9842 static alias_set_type
9843 ix86_GOT_alias_set (void)
9845 static alias_set_type set = -1;
9847 set = new_alias_set ();
9851 /* Return a legitimate reference for ORIG (an address) using the
9852 register REG. If REG is 0, a new pseudo is generated.
9854 There are two types of references that must be handled:
9856 1. Global data references must load the address from the GOT, via
9857 the PIC reg. An insn is emitted to do this load, and the reg is
9860 2. Static data references, constant pool addresses, and code labels
9861 compute the address as an offset from the GOT, whose base is in
9862 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9863 differentiate them from global data objects. The returned
9864 address is the PIC reg + an unspec constant.
9866 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
9867 reg also appears in the address. */
9870 legitimize_pic_address (rtx orig, rtx reg)
9877 if (TARGET_MACHO && !TARGET_64BIT)
9880 reg = gen_reg_rtx (Pmode);
9881 /* Use the generic Mach-O PIC machinery. */
9882 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9886 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9888 else if (TARGET_64BIT
9889 && ix86_cmodel != CM_SMALL_PIC
9890 && gotoff_operand (addr, Pmode))
9893 /* This symbol may be referenced via a displacement from the PIC
9894 base address (@GOTOFF). */
9896 if (reload_in_progress)
9897 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9898 if (GET_CODE (addr) == CONST)
9899 addr = XEXP (addr, 0);
9900 if (GET_CODE (addr) == PLUS)
9902 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9904 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9907 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9908 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9910 tmpreg = gen_reg_rtx (Pmode);
9913 emit_move_insn (tmpreg, new_rtx);
9917 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9918 tmpreg, 1, OPTAB_DIRECT);
9921 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9923 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9925 /* This symbol may be referenced via a displacement from the PIC
9926 base address (@GOTOFF). */
9928 if (reload_in_progress)
9929 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9930 if (GET_CODE (addr) == CONST)
9931 addr = XEXP (addr, 0);
9932 if (GET_CODE (addr) == PLUS)
9934 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9936 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9939 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9940 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9941 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9945 emit_move_insn (reg, new_rtx);
9949 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9950 /* We can't use @GOTOFF for text labels on VxWorks;
9951 see gotoff_operand. */
9952 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9954 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9956 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9957 return legitimize_dllimport_symbol (addr, true);
9958 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9959 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9960 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9962 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9963 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9967 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9969 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9970 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9971 new_rtx = gen_const_mem (Pmode, new_rtx);
9972 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9975 reg = gen_reg_rtx (Pmode);
9976 /* Use directly gen_movsi, otherwise the address is loaded
9977 into register for CSE. We don't want to CSE this addresses,
9978 instead we CSE addresses from the GOT table, so skip this. */
9979 emit_insn (gen_movsi (reg, new_rtx));
9984 /* This symbol must be referenced via a load from the
9985 Global Offset Table (@GOT). */
9987 if (reload_in_progress)
9988 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9989 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9990 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9992 new_rtx = force_reg (Pmode, new_rtx);
9993 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9994 new_rtx = gen_const_mem (Pmode, new_rtx);
9995 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9998 reg = gen_reg_rtx (Pmode);
9999 emit_move_insn (reg, new_rtx);
10005 if (CONST_INT_P (addr)
10006 && !x86_64_immediate_operand (addr, VOIDmode))
10010 emit_move_insn (reg, addr);
10014 new_rtx = force_reg (Pmode, addr);
10016 else if (GET_CODE (addr) == CONST)
10018 addr = XEXP (addr, 0);
10020 /* We must match stuff we generate before. Assume the only
10021 unspecs that can get here are ours. Not that we could do
10022 anything with them anyway.... */
10023 if (GET_CODE (addr) == UNSPEC
10024 || (GET_CODE (addr) == PLUS
10025 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
10027 gcc_assert (GET_CODE (addr) == PLUS);
10029 if (GET_CODE (addr) == PLUS)
10031 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
10033 /* Check first to see if this is a constant offset from a @GOTOFF
10034 symbol reference. */
10035 if (gotoff_operand (op0, Pmode)
10036 && CONST_INT_P (op1))
10040 if (reload_in_progress)
10041 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10042 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
10044 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
10045 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
10046 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
10050 emit_move_insn (reg, new_rtx);
10056 if (INTVAL (op1) < -16*1024*1024
10057 || INTVAL (op1) >= 16*1024*1024)
10059 if (!x86_64_immediate_operand (op1, Pmode))
10060 op1 = force_reg (Pmode, op1);
10061 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
10067 base = legitimize_pic_address (XEXP (addr, 0), reg);
10068 new_rtx = legitimize_pic_address (XEXP (addr, 1),
10069 base == reg ? NULL_RTX : reg);
10071 if (CONST_INT_P (new_rtx))
10072 new_rtx = plus_constant (base, INTVAL (new_rtx));
10075 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
10077 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
10078 new_rtx = XEXP (new_rtx, 1);
10080 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
10088 /* Load the thread pointer. If TO_REG is true, force it into a register. */
10091 get_thread_pointer (int to_reg)
10095 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
10099 reg = gen_reg_rtx (Pmode);
10100 insn = gen_rtx_SET (VOIDmode, reg, tp);
10101 insn = emit_insn (insn);
10106 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
10107 false if we expect this to be used for a memory address and true if
10108 we expect to load the address into a register. */
10111 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
10113 rtx dest, base, off, pic, tp;
10118 case TLS_MODEL_GLOBAL_DYNAMIC:
10119 dest = gen_reg_rtx (Pmode);
10120 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10122 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10124 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
10127 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
10128 insns = get_insns ();
10131 RTL_CONST_CALL_P (insns) = 1;
10132 emit_libcall_block (insns, dest, rax, x);
10134 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10135 emit_insn (gen_tls_global_dynamic_64 (dest, x));
10137 emit_insn (gen_tls_global_dynamic_32 (dest, x));
10139 if (TARGET_GNU2_TLS)
10141 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
10143 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10147 case TLS_MODEL_LOCAL_DYNAMIC:
10148 base = gen_reg_rtx (Pmode);
10149 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
10151 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
10153 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
10156 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
10157 insns = get_insns ();
10160 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
10161 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
10162 RTL_CONST_CALL_P (insns) = 1;
10163 emit_libcall_block (insns, base, rax, note);
10165 else if (TARGET_64BIT && TARGET_GNU2_TLS)
10166 emit_insn (gen_tls_local_dynamic_base_64 (base));
10168 emit_insn (gen_tls_local_dynamic_base_32 (base));
10170 if (TARGET_GNU2_TLS)
10172 rtx x = ix86_tls_module_base ();
10174 set_unique_reg_note (get_last_insn (), REG_EQUIV,
10175 gen_rtx_MINUS (Pmode, x, tp));
10178 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
10179 off = gen_rtx_CONST (Pmode, off);
10181 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
10183 if (TARGET_GNU2_TLS)
10185 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
10187 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
10192 case TLS_MODEL_INITIAL_EXEC:
10196 type = UNSPEC_GOTNTPOFF;
10200 if (reload_in_progress)
10201 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
10202 pic = pic_offset_table_rtx;
10203 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
10205 else if (!TARGET_ANY_GNU_TLS)
10207 pic = gen_reg_rtx (Pmode);
10208 emit_insn (gen_set_got (pic));
10209 type = UNSPEC_GOTTPOFF;
10214 type = UNSPEC_INDNTPOFF;
10217 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
10218 off = gen_rtx_CONST (Pmode, off);
10220 off = gen_rtx_PLUS (Pmode, pic, off);
10221 off = gen_const_mem (Pmode, off);
10222 set_mem_alias_set (off, ix86_GOT_alias_set ());
10224 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10226 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10227 off = force_reg (Pmode, off);
10228 return gen_rtx_PLUS (Pmode, base, off);
10232 base = get_thread_pointer (true);
10233 dest = gen_reg_rtx (Pmode);
10234 emit_insn (gen_subsi3 (dest, base, off));
10238 case TLS_MODEL_LOCAL_EXEC:
10239 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
10240 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10241 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
10242 off = gen_rtx_CONST (Pmode, off);
10244 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
10246 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
10247 return gen_rtx_PLUS (Pmode, base, off);
10251 base = get_thread_pointer (true);
10252 dest = gen_reg_rtx (Pmode);
10253 emit_insn (gen_subsi3 (dest, base, off));
10258 gcc_unreachable ();
10264 /* Create or return the unique __imp_DECL dllimport symbol corresponding
10267 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
10268 htab_t dllimport_map;
10271 get_dllimport_decl (tree decl)
10273 struct tree_map *h, in;
10276 const char *prefix;
10277 size_t namelen, prefixlen;
10282 if (!dllimport_map)
10283 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
10285 in.hash = htab_hash_pointer (decl);
10286 in.base.from = decl;
10287 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
10288 h = (struct tree_map *) *loc;
10292 *loc = h = GGC_NEW (struct tree_map);
10294 h->base.from = decl;
10295 h->to = to = build_decl (DECL_SOURCE_LOCATION (decl),
10296 VAR_DECL, NULL, ptr_type_node);
10297 DECL_ARTIFICIAL (to) = 1;
10298 DECL_IGNORED_P (to) = 1;
10299 DECL_EXTERNAL (to) = 1;
10300 TREE_READONLY (to) = 1;
10302 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10303 name = targetm.strip_name_encoding (name);
10304 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
10305 ? "*__imp_" : "*__imp__";
10306 namelen = strlen (name);
10307 prefixlen = strlen (prefix);
10308 imp_name = (char *) alloca (namelen + prefixlen + 1);
10309 memcpy (imp_name, prefix, prefixlen);
10310 memcpy (imp_name + prefixlen, name, namelen + 1);
10312 name = ggc_alloc_string (imp_name, namelen + prefixlen);
10313 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
10314 SET_SYMBOL_REF_DECL (rtl, to);
10315 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
10317 rtl = gen_const_mem (Pmode, rtl);
10318 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
10320 SET_DECL_RTL (to, rtl);
10321 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
10326 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
10327 true if we require the result be a register. */
10330 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
10335 gcc_assert (SYMBOL_REF_DECL (symbol));
10336 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
10338 x = DECL_RTL (imp_decl);
10340 x = force_reg (Pmode, x);
10344 /* Try machine-dependent ways of modifying an illegitimate address
10345 to be legitimate. If we find one, return the new, valid address.
10346 This macro is used in only one place: `memory_address' in explow.c.
10348 OLDX is the address as it was before break_out_memory_refs was called.
10349 In some cases it is useful to look at this to decide what needs to be done.
10351 It is always safe for this macro to do nothing. It exists to recognize
10352 opportunities to optimize the output.
10354 For the 80386, we handle X+REG by loading X into a register R and
10355 using R+REG. R will go in a general reg and indexing will be used.
10356 However, if REG is a broken-out memory address or multiplication,
10357 nothing needs to be done because REG can certainly go in a general reg.
10359 When -fpic is used, special handling is needed for symbolic references.
10360 See comments by legitimize_pic_address in i386.c for details. */
10363 ix86_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
10364 enum machine_mode mode)
10369 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10371 return legitimize_tls_address (x, (enum tls_model) log, false);
10372 if (GET_CODE (x) == CONST
10373 && GET_CODE (XEXP (x, 0)) == PLUS
10374 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10375 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10377 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10378 (enum tls_model) log, false);
10379 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10382 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10384 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10385 return legitimize_dllimport_symbol (x, true);
10386 if (GET_CODE (x) == CONST
10387 && GET_CODE (XEXP (x, 0)) == PLUS
10388 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10389 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10391 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10392 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10396 if (flag_pic && SYMBOLIC_CONST (x))
10397 return legitimize_pic_address (x, 0);
10399 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10400 if (GET_CODE (x) == ASHIFT
10401 && CONST_INT_P (XEXP (x, 1))
10402 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10405 log = INTVAL (XEXP (x, 1));
10406 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10407 GEN_INT (1 << log));
10410 if (GET_CODE (x) == PLUS)
10412 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10414 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10415 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10416 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10419 log = INTVAL (XEXP (XEXP (x, 0), 1));
10420 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10421 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10422 GEN_INT (1 << log));
10425 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10426 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10427 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10430 log = INTVAL (XEXP (XEXP (x, 1), 1));
10431 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10432 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10433 GEN_INT (1 << log));
10436 /* Put multiply first if it isn't already. */
10437 if (GET_CODE (XEXP (x, 1)) == MULT)
10439 rtx tmp = XEXP (x, 0);
10440 XEXP (x, 0) = XEXP (x, 1);
10445 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10446 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10447 created by virtual register instantiation, register elimination, and
10448 similar optimizations. */
10449 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10452 x = gen_rtx_PLUS (Pmode,
10453 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10454 XEXP (XEXP (x, 1), 0)),
10455 XEXP (XEXP (x, 1), 1));
10459 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10460 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10461 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10462 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10463 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10464 && CONSTANT_P (XEXP (x, 1)))
10467 rtx other = NULL_RTX;
10469 if (CONST_INT_P (XEXP (x, 1)))
10471 constant = XEXP (x, 1);
10472 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10474 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10476 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10477 other = XEXP (x, 1);
10485 x = gen_rtx_PLUS (Pmode,
10486 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10487 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10488 plus_constant (other, INTVAL (constant)));
10492 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10495 if (GET_CODE (XEXP (x, 0)) == MULT)
10498 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10501 if (GET_CODE (XEXP (x, 1)) == MULT)
10504 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10508 && REG_P (XEXP (x, 1))
10509 && REG_P (XEXP (x, 0)))
10512 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10515 x = legitimize_pic_address (x, 0);
10518 if (changed && ix86_legitimate_address_p (mode, x, FALSE))
10521 if (REG_P (XEXP (x, 0)))
10523 rtx temp = gen_reg_rtx (Pmode);
10524 rtx val = force_operand (XEXP (x, 1), temp);
10526 emit_move_insn (temp, val);
10528 XEXP (x, 1) = temp;
10532 else if (REG_P (XEXP (x, 1)))
10534 rtx temp = gen_reg_rtx (Pmode);
10535 rtx val = force_operand (XEXP (x, 0), temp);
10537 emit_move_insn (temp, val);
10539 XEXP (x, 0) = temp;
10547 /* Print an integer constant expression in assembler syntax. Addition
10548 and subtraction are the only arithmetic that may appear in these
10549 expressions. FILE is the stdio stream to write to, X is the rtx, and
10550 CODE is the operand print code from the output string. */
10553 output_pic_addr_const (FILE *file, rtx x, int code)
10557 switch (GET_CODE (x))
10560 gcc_assert (flag_pic);
10565 if (! TARGET_MACHO || TARGET_64BIT)
10566 output_addr_const (file, x);
10569 const char *name = XSTR (x, 0);
10571 /* Mark the decl as referenced so that cgraph will
10572 output the function. */
10573 if (SYMBOL_REF_DECL (x))
10574 mark_decl_referenced (SYMBOL_REF_DECL (x));
10577 if (MACHOPIC_INDIRECT
10578 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10579 name = machopic_indirection_name (x, /*stub_p=*/true);
10581 assemble_name (file, name);
10583 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10584 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10585 fputs ("@PLT", file);
10592 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10593 assemble_name (asm_out_file, buf);
10597 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10601 /* This used to output parentheses around the expression,
10602 but that does not work on the 386 (either ATT or BSD assembler). */
10603 output_pic_addr_const (file, XEXP (x, 0), code);
10607 if (GET_MODE (x) == VOIDmode)
10609 /* We can use %d if the number is <32 bits and positive. */
10610 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10611 fprintf (file, "0x%lx%08lx",
10612 (unsigned long) CONST_DOUBLE_HIGH (x),
10613 (unsigned long) CONST_DOUBLE_LOW (x));
10615 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10618 /* We can't handle floating point constants;
10619 PRINT_OPERAND must handle them. */
10620 output_operand_lossage ("floating constant misused");
10624 /* Some assemblers need integer constants to appear first. */
10625 if (CONST_INT_P (XEXP (x, 0)))
10627 output_pic_addr_const (file, XEXP (x, 0), code);
10629 output_pic_addr_const (file, XEXP (x, 1), code);
10633 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10634 output_pic_addr_const (file, XEXP (x, 1), code);
10636 output_pic_addr_const (file, XEXP (x, 0), code);
10642 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10643 output_pic_addr_const (file, XEXP (x, 0), code);
10645 output_pic_addr_const (file, XEXP (x, 1), code);
10647 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10651 gcc_assert (XVECLEN (x, 0) == 1);
10652 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10653 switch (XINT (x, 1))
10656 fputs ("@GOT", file);
10658 case UNSPEC_GOTOFF:
10659 fputs ("@GOTOFF", file);
10661 case UNSPEC_PLTOFF:
10662 fputs ("@PLTOFF", file);
10664 case UNSPEC_GOTPCREL:
10665 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10666 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10668 case UNSPEC_GOTTPOFF:
10669 /* FIXME: This might be @TPOFF in Sun ld too. */
10670 fputs ("@GOTTPOFF", file);
10673 fputs ("@TPOFF", file);
10675 case UNSPEC_NTPOFF:
10677 fputs ("@TPOFF", file);
10679 fputs ("@NTPOFF", file);
10681 case UNSPEC_DTPOFF:
10682 fputs ("@DTPOFF", file);
10684 case UNSPEC_GOTNTPOFF:
10686 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10687 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10689 fputs ("@GOTNTPOFF", file);
10691 case UNSPEC_INDNTPOFF:
10692 fputs ("@INDNTPOFF", file);
10695 case UNSPEC_MACHOPIC_OFFSET:
10697 machopic_output_function_base_name (file);
10701 output_operand_lossage ("invalid UNSPEC as operand");
10707 output_operand_lossage ("invalid expression as operand");
10711 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10712 We need to emit DTP-relative relocations. */
10714 static void ATTRIBUTE_UNUSED
10715 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10717 fputs (ASM_LONG, file);
10718 output_addr_const (file, x);
10719 fputs ("@DTPOFF", file);
10725 fputs (", 0", file);
10728 gcc_unreachable ();
10732 /* Return true if X is a representation of the PIC register. This copes
10733 with calls from ix86_find_base_term, where the register might have
10734 been replaced by a cselib value. */
10737 ix86_pic_register_p (rtx x)
10739 if (GET_CODE (x) == VALUE)
10740 return (pic_offset_table_rtx
10741 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10743 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10746 /* In the name of slightly smaller debug output, and to cater to
10747 general assembler lossage, recognize PIC+GOTOFF and turn it back
10748 into a direct symbol reference.
10750 On Darwin, this is necessary to avoid a crash, because Darwin
10751 has a different PIC label for each routine but the DWARF debugging
10752 information is not associated with any particular routine, so it's
10753 necessary to remove references to the PIC label from RTL stored by
10754 the DWARF output code. */
10757 ix86_delegitimize_address (rtx x)
10759 rtx orig_x = delegitimize_mem_from_attrs (x);
10760 /* reg_addend is NULL or a multiple of some register. */
10761 rtx reg_addend = NULL_RTX;
10762 /* const_addend is NULL or a const_int. */
10763 rtx const_addend = NULL_RTX;
10764 /* This is the result, or NULL. */
10765 rtx result = NULL_RTX;
10774 if (GET_CODE (x) != CONST
10775 || GET_CODE (XEXP (x, 0)) != UNSPEC
10776 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10777 || !MEM_P (orig_x))
10779 return XVECEXP (XEXP (x, 0), 0, 0);
10782 if (GET_CODE (x) != PLUS
10783 || GET_CODE (XEXP (x, 1)) != CONST)
10786 if (ix86_pic_register_p (XEXP (x, 0)))
10787 /* %ebx + GOT/GOTOFF */
10789 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10791 /* %ebx + %reg * scale + GOT/GOTOFF */
10792 reg_addend = XEXP (x, 0);
10793 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10794 reg_addend = XEXP (reg_addend, 1);
10795 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10796 reg_addend = XEXP (reg_addend, 0);
10799 if (!REG_P (reg_addend)
10800 && GET_CODE (reg_addend) != MULT
10801 && GET_CODE (reg_addend) != ASHIFT)
10807 x = XEXP (XEXP (x, 1), 0);
10808 if (GET_CODE (x) == PLUS
10809 && CONST_INT_P (XEXP (x, 1)))
10811 const_addend = XEXP (x, 1);
10815 if (GET_CODE (x) == UNSPEC
10816 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10817 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10818 result = XVECEXP (x, 0, 0);
10820 if (TARGET_MACHO && darwin_local_data_pic (x)
10821 && !MEM_P (orig_x))
10822 result = XVECEXP (x, 0, 0);
10828 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10830 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10834 /* If X is a machine specific address (i.e. a symbol or label being
10835 referenced as a displacement from the GOT implemented using an
10836 UNSPEC), then return the base term. Otherwise return X. */
10839 ix86_find_base_term (rtx x)
10845 if (GET_CODE (x) != CONST)
10847 term = XEXP (x, 0);
10848 if (GET_CODE (term) == PLUS
10849 && (CONST_INT_P (XEXP (term, 1))
10850 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10851 term = XEXP (term, 0);
10852 if (GET_CODE (term) != UNSPEC
10853 || XINT (term, 1) != UNSPEC_GOTPCREL)
10856 return XVECEXP (term, 0, 0);
10859 return ix86_delegitimize_address (x);
10863 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10864 int fp, FILE *file)
10866 const char *suffix;
10868 if (mode == CCFPmode || mode == CCFPUmode)
10870 code = ix86_fp_compare_code_to_integer (code);
10874 code = reverse_condition (code);
10925 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10929 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10930 Those same assemblers have the same but opposite lossage on cmov. */
10931 if (mode == CCmode)
10932 suffix = fp ? "nbe" : "a";
10933 else if (mode == CCCmode)
10936 gcc_unreachable ();
10952 gcc_unreachable ();
10956 gcc_assert (mode == CCmode || mode == CCCmode);
10973 gcc_unreachable ();
10977 /* ??? As above. */
10978 gcc_assert (mode == CCmode || mode == CCCmode);
10979 suffix = fp ? "nb" : "ae";
10982 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10986 /* ??? As above. */
10987 if (mode == CCmode)
10989 else if (mode == CCCmode)
10990 suffix = fp ? "nb" : "ae";
10992 gcc_unreachable ();
10995 suffix = fp ? "u" : "p";
10998 suffix = fp ? "nu" : "np";
11001 gcc_unreachable ();
11003 fputs (suffix, file);
11006 /* Print the name of register X to FILE based on its machine mode and number.
11007 If CODE is 'w', pretend the mode is HImode.
11008 If CODE is 'b', pretend the mode is QImode.
11009 If CODE is 'k', pretend the mode is SImode.
11010 If CODE is 'q', pretend the mode is DImode.
11011 If CODE is 'x', pretend the mode is V4SFmode.
11012 If CODE is 't', pretend the mode is V8SFmode.
11013 If CODE is 'h', pretend the reg is the 'high' byte register.
11014 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
11015 If CODE is 'd', duplicate the operand for AVX instruction.
11019 print_reg (rtx x, int code, FILE *file)
11022 bool duplicated = code == 'd' && TARGET_AVX;
11024 gcc_assert (x == pc_rtx
11025 || (REGNO (x) != ARG_POINTER_REGNUM
11026 && REGNO (x) != FRAME_POINTER_REGNUM
11027 && REGNO (x) != FLAGS_REG
11028 && REGNO (x) != FPSR_REG
11029 && REGNO (x) != FPCR_REG));
11031 if (ASSEMBLER_DIALECT == ASM_ATT)
11036 gcc_assert (TARGET_64BIT);
11037 fputs ("rip", file);
11041 if (code == 'w' || MMX_REG_P (x))
11043 else if (code == 'b')
11045 else if (code == 'k')
11047 else if (code == 'q')
11049 else if (code == 'y')
11051 else if (code == 'h')
11053 else if (code == 'x')
11055 else if (code == 't')
11058 code = GET_MODE_SIZE (GET_MODE (x));
11060 /* Irritatingly, AMD extended registers use different naming convention
11061 from the normal registers. */
11062 if (REX_INT_REG_P (x))
11064 gcc_assert (TARGET_64BIT);
11068 error ("extended registers have no high halves");
11071 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
11074 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
11077 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
11080 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
11083 error ("unsupported operand size for extended register");
11093 if (STACK_TOP_P (x))
11102 if (! ANY_FP_REG_P (x))
11103 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
11108 reg = hi_reg_name[REGNO (x)];
11111 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
11113 reg = qi_reg_name[REGNO (x)];
11116 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
11118 reg = qi_high_reg_name[REGNO (x)];
11123 gcc_assert (!duplicated);
11125 fputs (hi_reg_name[REGNO (x)] + 1, file);
11130 gcc_unreachable ();
11136 if (ASSEMBLER_DIALECT == ASM_ATT)
11137 fprintf (file, ", %%%s", reg);
11139 fprintf (file, ", %s", reg);
11143 /* Locate some local-dynamic symbol still in use by this function
11144 so that we can print its name in some tls_local_dynamic_base
11148 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11152 if (GET_CODE (x) == SYMBOL_REF
11153 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11155 cfun->machine->some_ld_name = XSTR (x, 0);
11162 static const char *
11163 get_some_local_dynamic_name (void)
11167 if (cfun->machine->some_ld_name)
11168 return cfun->machine->some_ld_name;
11170 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11172 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
11173 return cfun->machine->some_ld_name;
11175 gcc_unreachable ();
11178 /* Meaning of CODE:
11179 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
11180 C -- print opcode suffix for set/cmov insn.
11181 c -- like C, but print reversed condition
11182 E,e -- likewise, but for compare-and-branch fused insn.
11183 F,f -- likewise, but for floating-point.
11184 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
11186 R -- print the prefix for register names.
11187 z -- print the opcode suffix for the size of the current operand.
11188 Z -- likewise, with special suffixes for x87 instructions.
11189 * -- print a star (in certain assembler syntax)
11190 A -- print an absolute memory reference.
11191 w -- print the operand as if it's a "word" (HImode) even if it isn't.
11192 s -- print a shift double count, followed by the assemblers argument
11194 b -- print the QImode name of the register for the indicated operand.
11195 %b0 would print %al if operands[0] is reg 0.
11196 w -- likewise, print the HImode name of the register.
11197 k -- likewise, print the SImode name of the register.
11198 q -- likewise, print the DImode name of the register.
11199 x -- likewise, print the V4SFmode name of the register.
11200 t -- likewise, print the V8SFmode name of the register.
11201 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
11202 y -- print "st(0)" instead of "st" as a register.
11203 d -- print duplicated register operand for AVX instruction.
11204 D -- print condition for SSE cmp instruction.
11205 P -- if PIC, print an @PLT suffix.
11206 X -- don't print any sort of PIC '@' suffix for a symbol.
11207 & -- print some in-use local-dynamic symbol name.
11208 H -- print a memory address offset by 8; used for sse high-parts
11209 + -- print a branch hint as 'cs' or 'ds' prefix
11210 ; -- print a semicolon (after prefixes due to bug in older gas).
11214 print_operand (FILE *file, rtx x, int code)
11221 if (ASSEMBLER_DIALECT == ASM_ATT)
11226 assemble_name (file, get_some_local_dynamic_name ());
11230 switch (ASSEMBLER_DIALECT)
11237 /* Intel syntax. For absolute addresses, registers should not
11238 be surrounded by braces. */
11242 PRINT_OPERAND (file, x, 0);
11249 gcc_unreachable ();
11252 PRINT_OPERAND (file, x, 0);
11257 if (ASSEMBLER_DIALECT == ASM_ATT)
11262 if (ASSEMBLER_DIALECT == ASM_ATT)
11267 if (ASSEMBLER_DIALECT == ASM_ATT)
11272 if (ASSEMBLER_DIALECT == ASM_ATT)
11277 if (ASSEMBLER_DIALECT == ASM_ATT)
11282 if (ASSEMBLER_DIALECT == ASM_ATT)
11287 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11289 /* Opcodes don't get size suffixes if using Intel opcodes. */
11290 if (ASSEMBLER_DIALECT == ASM_INTEL)
11293 switch (GET_MODE_SIZE (GET_MODE (x)))
11312 output_operand_lossage
11313 ("invalid operand size for operand code '%c'", code);
11318 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11320 (0, "non-integer operand used with operand code '%c'", code);
11324 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
11325 if (ASSEMBLER_DIALECT == ASM_INTEL)
11328 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
11330 switch (GET_MODE_SIZE (GET_MODE (x)))
11333 #ifdef HAVE_AS_IX86_FILDS
11343 #ifdef HAVE_AS_IX86_FILDQ
11346 fputs ("ll", file);
11354 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
11356 /* 387 opcodes don't get size suffixes
11357 if the operands are registers. */
11358 if (STACK_REG_P (x))
11361 switch (GET_MODE_SIZE (GET_MODE (x)))
11382 output_operand_lossage
11383 ("invalid operand type used with operand code '%c'", code);
11387 output_operand_lossage
11388 ("invalid operand size for operand code '%c'", code);
11405 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11407 PRINT_OPERAND (file, x, 0);
11408 fputs (", ", file);
11413 /* Little bit of braindamage here. The SSE compare instructions
11414 does use completely different names for the comparisons that the
11415 fp conditional moves. */
11418 switch (GET_CODE (x))
11421 fputs ("eq", file);
11424 fputs ("eq_us", file);
11427 fputs ("lt", file);
11430 fputs ("nge", file);
11433 fputs ("le", file);
11436 fputs ("ngt", file);
11439 fputs ("unord", file);
11442 fputs ("neq", file);
11445 fputs ("neq_oq", file);
11448 fputs ("ge", file);
11451 fputs ("nlt", file);
11454 fputs ("gt", file);
11457 fputs ("nle", file);
11460 fputs ("ord", file);
11463 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11469 switch (GET_CODE (x))
11473 fputs ("eq", file);
11477 fputs ("lt", file);
11481 fputs ("le", file);
11484 fputs ("unord", file);
11488 fputs ("neq", file);
11492 fputs ("nlt", file);
11496 fputs ("nle", file);
11499 fputs ("ord", file);
11502 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11508 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11509 if (ASSEMBLER_DIALECT == ASM_ATT)
11511 switch (GET_MODE (x))
11513 case HImode: putc ('w', file); break;
11515 case SFmode: putc ('l', file); break;
11517 case DFmode: putc ('q', file); break;
11518 default: gcc_unreachable ();
11525 if (!COMPARISON_P (x))
11527 output_operand_lossage ("operand is neither a constant nor a "
11528 "condition code, invalid operand code "
11532 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11535 if (!COMPARISON_P (x))
11537 output_operand_lossage ("operand is neither a constant nor a "
11538 "condition code, invalid operand code "
11542 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11543 if (ASSEMBLER_DIALECT == ASM_ATT)
11546 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11549 /* Like above, but reverse condition */
11551 /* Check to see if argument to %c is really a constant
11552 and not a condition code which needs to be reversed. */
11553 if (!COMPARISON_P (x))
11555 output_operand_lossage ("operand is neither a constant nor a "
11556 "condition code, invalid operand "
11560 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11563 if (!COMPARISON_P (x))
11565 output_operand_lossage ("operand is neither a constant nor a "
11566 "condition code, invalid operand "
11570 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11571 if (ASSEMBLER_DIALECT == ASM_ATT)
11574 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11578 put_condition_code (GET_CODE (x), CCmode, 0, 0, file);
11582 put_condition_code (GET_CODE (x), CCmode, 1, 0, file);
11586 /* It doesn't actually matter what mode we use here, as we're
11587 only going to use this for printing. */
11588 x = adjust_address_nv (x, DImode, 8);
11596 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11599 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11602 int pred_val = INTVAL (XEXP (x, 0));
11604 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11605 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11607 int taken = pred_val > REG_BR_PROB_BASE / 2;
11608 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11610 /* Emit hints only in the case default branch prediction
11611 heuristics would fail. */
11612 if (taken != cputaken)
11614 /* We use 3e (DS) prefix for taken branches and
11615 2e (CS) prefix for not taken branches. */
11617 fputs ("ds ; ", file);
11619 fputs ("cs ; ", file);
11628 fputs (" ; ", file);
11635 output_operand_lossage ("invalid operand code '%c'", code);
11640 print_reg (x, code, file);
11642 else if (MEM_P (x))
11644 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11645 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11646 && GET_MODE (x) != BLKmode)
11649 switch (GET_MODE_SIZE (GET_MODE (x)))
11651 case 1: size = "BYTE"; break;
11652 case 2: size = "WORD"; break;
11653 case 4: size = "DWORD"; break;
11654 case 8: size = "QWORD"; break;
11655 case 12: size = "XWORD"; break;
11657 if (GET_MODE (x) == XFmode)
11663 gcc_unreachable ();
11666 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11669 else if (code == 'w')
11671 else if (code == 'k')
11674 fputs (size, file);
11675 fputs (" PTR ", file);
11679 /* Avoid (%rip) for call operands. */
11680 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11681 && !CONST_INT_P (x))
11682 output_addr_const (file, x);
11683 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11684 output_operand_lossage ("invalid constraints for operand");
11686 output_address (x);
11689 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11694 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11695 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11697 if (ASSEMBLER_DIALECT == ASM_ATT)
11699 fprintf (file, "0x%08lx", (long unsigned int) l);
11702 /* These float cases don't actually occur as immediate operands. */
11703 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11707 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11708 fputs (dstr, file);
11711 else if (GET_CODE (x) == CONST_DOUBLE
11712 && GET_MODE (x) == XFmode)
11716 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11717 fputs (dstr, file);
11722 /* We have patterns that allow zero sets of memory, for instance.
11723 In 64-bit mode, we should probably support all 8-byte vectors,
11724 since we can in fact encode that into an immediate. */
11725 if (GET_CODE (x) == CONST_VECTOR)
11727 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11733 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11735 if (ASSEMBLER_DIALECT == ASM_ATT)
11738 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11739 || GET_CODE (x) == LABEL_REF)
11741 if (ASSEMBLER_DIALECT == ASM_ATT)
11744 fputs ("OFFSET FLAT:", file);
11747 if (CONST_INT_P (x))
11748 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11750 output_pic_addr_const (file, x, code);
11752 output_addr_const (file, x);
11756 /* Print a memory operand whose address is ADDR. */
11759 print_operand_address (FILE *file, rtx addr)
11761 struct ix86_address parts;
11762 rtx base, index, disp;
11764 int ok = ix86_decompose_address (addr, &parts);
11769 index = parts.index;
11771 scale = parts.scale;
11779 if (ASSEMBLER_DIALECT == ASM_ATT)
11781 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11784 gcc_unreachable ();
11787 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11788 if (TARGET_64BIT && !base && !index)
11792 if (GET_CODE (disp) == CONST
11793 && GET_CODE (XEXP (disp, 0)) == PLUS
11794 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11795 symbol = XEXP (XEXP (disp, 0), 0);
11797 if (GET_CODE (symbol) == LABEL_REF
11798 || (GET_CODE (symbol) == SYMBOL_REF
11799 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11802 if (!base && !index)
11804 /* Displacement only requires special attention. */
11806 if (CONST_INT_P (disp))
11808 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11809 fputs ("ds:", file);
11810 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11813 output_pic_addr_const (file, disp, 0);
11815 output_addr_const (file, disp);
11819 if (ASSEMBLER_DIALECT == ASM_ATT)
11824 output_pic_addr_const (file, disp, 0);
11825 else if (GET_CODE (disp) == LABEL_REF)
11826 output_asm_label (disp);
11828 output_addr_const (file, disp);
11833 print_reg (base, 0, file);
11837 print_reg (index, 0, file);
11839 fprintf (file, ",%d", scale);
11845 rtx offset = NULL_RTX;
11849 /* Pull out the offset of a symbol; print any symbol itself. */
11850 if (GET_CODE (disp) == CONST
11851 && GET_CODE (XEXP (disp, 0)) == PLUS
11852 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11854 offset = XEXP (XEXP (disp, 0), 1);
11855 disp = gen_rtx_CONST (VOIDmode,
11856 XEXP (XEXP (disp, 0), 0));
11860 output_pic_addr_const (file, disp, 0);
11861 else if (GET_CODE (disp) == LABEL_REF)
11862 output_asm_label (disp);
11863 else if (CONST_INT_P (disp))
11866 output_addr_const (file, disp);
11872 print_reg (base, 0, file);
11875 if (INTVAL (offset) >= 0)
11877 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11881 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11888 print_reg (index, 0, file);
11890 fprintf (file, "*%d", scale);
11898 output_addr_const_extra (FILE *file, rtx x)
11902 if (GET_CODE (x) != UNSPEC)
11905 op = XVECEXP (x, 0, 0);
11906 switch (XINT (x, 1))
11908 case UNSPEC_GOTTPOFF:
11909 output_addr_const (file, op);
11910 /* FIXME: This might be @TPOFF in Sun ld. */
11911 fputs ("@GOTTPOFF", file);
11914 output_addr_const (file, op);
11915 fputs ("@TPOFF", file);
11917 case UNSPEC_NTPOFF:
11918 output_addr_const (file, op);
11920 fputs ("@TPOFF", file);
11922 fputs ("@NTPOFF", file);
11924 case UNSPEC_DTPOFF:
11925 output_addr_const (file, op);
11926 fputs ("@DTPOFF", file);
11928 case UNSPEC_GOTNTPOFF:
11929 output_addr_const (file, op);
11931 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11932 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11934 fputs ("@GOTNTPOFF", file);
11936 case UNSPEC_INDNTPOFF:
11937 output_addr_const (file, op);
11938 fputs ("@INDNTPOFF", file);
11941 case UNSPEC_MACHOPIC_OFFSET:
11942 output_addr_const (file, op);
11944 machopic_output_function_base_name (file);
11955 /* Split one or more DImode RTL references into pairs of SImode
11956 references. The RTL can be REG, offsettable MEM, integer constant, or
11957 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11958 split and "num" is its length. lo_half and hi_half are output arrays
11959 that parallel "operands". */
11962 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11966 rtx op = operands[num];
11968 /* simplify_subreg refuse to split volatile memory addresses,
11969 but we still have to handle it. */
11972 lo_half[num] = adjust_address (op, SImode, 0);
11973 hi_half[num] = adjust_address (op, SImode, 4);
11977 lo_half[num] = simplify_gen_subreg (SImode, op,
11978 GET_MODE (op) == VOIDmode
11979 ? DImode : GET_MODE (op), 0);
11980 hi_half[num] = simplify_gen_subreg (SImode, op,
11981 GET_MODE (op) == VOIDmode
11982 ? DImode : GET_MODE (op), 4);
11986 /* Split one or more TImode RTL references into pairs of DImode
11987 references. The RTL can be REG, offsettable MEM, integer constant, or
11988 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11989 split and "num" is its length. lo_half and hi_half are output arrays
11990 that parallel "operands". */
11993 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11997 rtx op = operands[num];
11999 /* simplify_subreg refuse to split volatile memory addresses, but we
12000 still have to handle it. */
12003 lo_half[num] = adjust_address (op, DImode, 0);
12004 hi_half[num] = adjust_address (op, DImode, 8);
12008 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
12009 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
12014 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
12015 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
12016 is the expression of the binary operation. The output may either be
12017 emitted here, or returned to the caller, like all output_* functions.
12019 There is no guarantee that the operands are the same mode, as they
12020 might be within FLOAT or FLOAT_EXTEND expressions. */
12022 #ifndef SYSV386_COMPAT
12023 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
12024 wants to fix the assemblers because that causes incompatibility
12025 with gcc. No-one wants to fix gcc because that causes
12026 incompatibility with assemblers... You can use the option of
12027 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
12028 #define SYSV386_COMPAT 1
12032 output_387_binary_op (rtx insn, rtx *operands)
12034 static char buf[40];
12037 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
12039 #ifdef ENABLE_CHECKING
12040 /* Even if we do not want to check the inputs, this documents input
12041 constraints. Which helps in understanding the following code. */
12042 if (STACK_REG_P (operands[0])
12043 && ((REG_P (operands[1])
12044 && REGNO (operands[0]) == REGNO (operands[1])
12045 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
12046 || (REG_P (operands[2])
12047 && REGNO (operands[0]) == REGNO (operands[2])
12048 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
12049 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
12052 gcc_assert (is_sse);
12055 switch (GET_CODE (operands[3]))
12058 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12059 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12067 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12068 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12076 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12077 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12085 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
12086 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
12094 gcc_unreachable ();
12101 strcpy (buf, ssep);
12102 if (GET_MODE (operands[0]) == SFmode)
12103 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
12105 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
12109 strcpy (buf, ssep + 1);
12110 if (GET_MODE (operands[0]) == SFmode)
12111 strcat (buf, "ss\t{%2, %0|%0, %2}");
12113 strcat (buf, "sd\t{%2, %0|%0, %2}");
12119 switch (GET_CODE (operands[3]))
12123 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
12125 rtx temp = operands[2];
12126 operands[2] = operands[1];
12127 operands[1] = temp;
12130 /* know operands[0] == operands[1]. */
12132 if (MEM_P (operands[2]))
12138 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12140 if (STACK_TOP_P (operands[0]))
12141 /* How is it that we are storing to a dead operand[2]?
12142 Well, presumably operands[1] is dead too. We can't
12143 store the result to st(0) as st(0) gets popped on this
12144 instruction. Instead store to operands[2] (which I
12145 think has to be st(1)). st(1) will be popped later.
12146 gcc <= 2.8.1 didn't have this check and generated
12147 assembly code that the Unixware assembler rejected. */
12148 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12150 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12154 if (STACK_TOP_P (operands[0]))
12155 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12157 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12162 if (MEM_P (operands[1]))
12168 if (MEM_P (operands[2]))
12174 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
12177 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
12178 derived assemblers, confusingly reverse the direction of
12179 the operation for fsub{r} and fdiv{r} when the
12180 destination register is not st(0). The Intel assembler
12181 doesn't have this brain damage. Read !SYSV386_COMPAT to
12182 figure out what the hardware really does. */
12183 if (STACK_TOP_P (operands[0]))
12184 p = "{p\t%0, %2|rp\t%2, %0}";
12186 p = "{rp\t%2, %0|p\t%0, %2}";
12188 if (STACK_TOP_P (operands[0]))
12189 /* As above for fmul/fadd, we can't store to st(0). */
12190 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
12192 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
12197 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
12200 if (STACK_TOP_P (operands[0]))
12201 p = "{rp\t%0, %1|p\t%1, %0}";
12203 p = "{p\t%1, %0|rp\t%0, %1}";
12205 if (STACK_TOP_P (operands[0]))
12206 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
12208 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
12213 if (STACK_TOP_P (operands[0]))
12215 if (STACK_TOP_P (operands[1]))
12216 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
12218 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
12221 else if (STACK_TOP_P (operands[1]))
12224 p = "{\t%1, %0|r\t%0, %1}";
12226 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
12232 p = "{r\t%2, %0|\t%0, %2}";
12234 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
12240 gcc_unreachable ();
12247 /* Return needed mode for entity in optimize_mode_switching pass. */
12250 ix86_mode_needed (int entity, rtx insn)
12252 enum attr_i387_cw mode;
12254 /* The mode UNINITIALIZED is used to store control word after a
12255 function call or ASM pattern. The mode ANY specify that function
12256 has no requirements on the control word and make no changes in the
12257 bits we are interested in. */
12260 || (NONJUMP_INSN_P (insn)
12261 && (asm_noperands (PATTERN (insn)) >= 0
12262 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
12263 return I387_CW_UNINITIALIZED;
12265 if (recog_memoized (insn) < 0)
12266 return I387_CW_ANY;
12268 mode = get_attr_i387_cw (insn);
12273 if (mode == I387_CW_TRUNC)
12278 if (mode == I387_CW_FLOOR)
12283 if (mode == I387_CW_CEIL)
12288 if (mode == I387_CW_MASK_PM)
12293 gcc_unreachable ();
12296 return I387_CW_ANY;
12299 /* Output code to initialize control word copies used by trunc?f?i and
12300 rounding patterns. CURRENT_MODE is set to current control word,
12301 while NEW_MODE is set to new control word. */
12304 emit_i387_cw_initialization (int mode)
12306 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
12309 enum ix86_stack_slot slot;
12311 rtx reg = gen_reg_rtx (HImode);
12313 emit_insn (gen_x86_fnstcw_1 (stored_mode));
12314 emit_move_insn (reg, copy_rtx (stored_mode));
12316 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
12317 || optimize_function_for_size_p (cfun))
12321 case I387_CW_TRUNC:
12322 /* round toward zero (truncate) */
12323 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
12324 slot = SLOT_CW_TRUNC;
12327 case I387_CW_FLOOR:
12328 /* round down toward -oo */
12329 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12330 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
12331 slot = SLOT_CW_FLOOR;
12335 /* round up toward +oo */
12336 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
12337 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
12338 slot = SLOT_CW_CEIL;
12341 case I387_CW_MASK_PM:
12342 /* mask precision exception for nearbyint() */
12343 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12344 slot = SLOT_CW_MASK_PM;
12348 gcc_unreachable ();
12355 case I387_CW_TRUNC:
12356 /* round toward zero (truncate) */
12357 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12358 slot = SLOT_CW_TRUNC;
12361 case I387_CW_FLOOR:
12362 /* round down toward -oo */
12363 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12364 slot = SLOT_CW_FLOOR;
12368 /* round up toward +oo */
12369 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12370 slot = SLOT_CW_CEIL;
12373 case I387_CW_MASK_PM:
12374 /* mask precision exception for nearbyint() */
12375 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12376 slot = SLOT_CW_MASK_PM;
12380 gcc_unreachable ();
12384 gcc_assert (slot < MAX_386_STACK_LOCALS);
12386 new_mode = assign_386_stack_local (HImode, slot);
12387 emit_move_insn (new_mode, reg);
12390 /* Output code for INSN to convert a float to a signed int. OPERANDS
12391 are the insn operands. The output may be [HSD]Imode and the input
12392 operand may be [SDX]Fmode. */
12395 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12397 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12398 int dimode_p = GET_MODE (operands[0]) == DImode;
12399 int round_mode = get_attr_i387_cw (insn);
12401 /* Jump through a hoop or two for DImode, since the hardware has no
12402 non-popping instruction. We used to do this a different way, but
12403 that was somewhat fragile and broke with post-reload splitters. */
12404 if ((dimode_p || fisttp) && !stack_top_dies)
12405 output_asm_insn ("fld\t%y1", operands);
12407 gcc_assert (STACK_TOP_P (operands[1]));
12408 gcc_assert (MEM_P (operands[0]));
12409 gcc_assert (GET_MODE (operands[1]) != TFmode);
12412 output_asm_insn ("fisttp%Z0\t%0", operands);
12415 if (round_mode != I387_CW_ANY)
12416 output_asm_insn ("fldcw\t%3", operands);
12417 if (stack_top_dies || dimode_p)
12418 output_asm_insn ("fistp%Z0\t%0", operands);
12420 output_asm_insn ("fist%Z0\t%0", operands);
12421 if (round_mode != I387_CW_ANY)
12422 output_asm_insn ("fldcw\t%2", operands);
12428 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12429 have the values zero or one, indicates the ffreep insn's operand
12430 from the OPERANDS array. */
12432 static const char *
12433 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12435 if (TARGET_USE_FFREEP)
12436 #ifdef HAVE_AS_IX86_FFREEP
12437 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12440 static char retval[32];
12441 int regno = REGNO (operands[opno]);
12443 gcc_assert (FP_REGNO_P (regno));
12445 regno -= FIRST_STACK_REG;
12447 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
12452 return opno ? "fstp\t%y1" : "fstp\t%y0";
12456 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12457 should be used. UNORDERED_P is true when fucom should be used. */
12460 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12462 int stack_top_dies;
12463 rtx cmp_op0, cmp_op1;
12464 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12468 cmp_op0 = operands[0];
12469 cmp_op1 = operands[1];
12473 cmp_op0 = operands[1];
12474 cmp_op1 = operands[2];
12479 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12480 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12481 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12482 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12484 if (GET_MODE (operands[0]) == SFmode)
12486 return &ucomiss[TARGET_AVX ? 0 : 1];
12488 return &comiss[TARGET_AVX ? 0 : 1];
12491 return &ucomisd[TARGET_AVX ? 0 : 1];
12493 return &comisd[TARGET_AVX ? 0 : 1];
12496 gcc_assert (STACK_TOP_P (cmp_op0));
12498 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12500 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12502 if (stack_top_dies)
12504 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12505 return output_387_ffreep (operands, 1);
12508 return "ftst\n\tfnstsw\t%0";
12511 if (STACK_REG_P (cmp_op1)
12513 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12514 && REGNO (cmp_op1) != FIRST_STACK_REG)
12516 /* If both the top of the 387 stack dies, and the other operand
12517 is also a stack register that dies, then this must be a
12518 `fcompp' float compare */
12522 /* There is no double popping fcomi variant. Fortunately,
12523 eflags is immune from the fstp's cc clobbering. */
12525 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12527 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12528 return output_387_ffreep (operands, 0);
12533 return "fucompp\n\tfnstsw\t%0";
12535 return "fcompp\n\tfnstsw\t%0";
12540 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12542 static const char * const alt[16] =
12544 "fcom%Z2\t%y2\n\tfnstsw\t%0",
12545 "fcomp%Z2\t%y2\n\tfnstsw\t%0",
12546 "fucom%Z2\t%y2\n\tfnstsw\t%0",
12547 "fucomp%Z2\t%y2\n\tfnstsw\t%0",
12549 "ficom%Z2\t%y2\n\tfnstsw\t%0",
12550 "ficomp%Z2\t%y2\n\tfnstsw\t%0",
12554 "fcomi\t{%y1, %0|%0, %y1}",
12555 "fcomip\t{%y1, %0|%0, %y1}",
12556 "fucomi\t{%y1, %0|%0, %y1}",
12557 "fucomip\t{%y1, %0|%0, %y1}",
12568 mask = eflags_p << 3;
12569 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12570 mask |= unordered_p << 1;
12571 mask |= stack_top_dies;
12573 gcc_assert (mask < 16);
12582 ix86_output_addr_vec_elt (FILE *file, int value)
12584 const char *directive = ASM_LONG;
12588 directive = ASM_QUAD;
12590 gcc_assert (!TARGET_64BIT);
12593 fprintf (file, "%s" LPREFIX "%d\n", directive, value);
12597 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12599 const char *directive = ASM_LONG;
12602 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12603 directive = ASM_QUAD;
12605 gcc_assert (!TARGET_64BIT);
12607 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12608 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12609 fprintf (file, "%s" LPREFIX "%d-" LPREFIX "%d\n",
12610 directive, value, rel);
12611 else if (HAVE_AS_GOTOFF_IN_DATA)
12612 fprintf (file, ASM_LONG LPREFIX "%d@GOTOFF\n", value);
12614 else if (TARGET_MACHO)
12616 fprintf (file, ASM_LONG LPREFIX "%d-", value);
12617 machopic_output_function_base_name (file);
12622 asm_fprintf (file, ASM_LONG "%U%s+[.-" LPREFIX "%d]\n",
12623 GOT_SYMBOL_NAME, value);
12626 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12630 ix86_expand_clear (rtx dest)
12634 /* We play register width games, which are only valid after reload. */
12635 gcc_assert (reload_completed);
12637 /* Avoid HImode and its attendant prefix byte. */
12638 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12639 dest = gen_rtx_REG (SImode, REGNO (dest));
12640 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12642 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12643 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12645 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12646 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12652 /* X is an unchanging MEM. If it is a constant pool reference, return
12653 the constant pool rtx, else NULL. */
12656 maybe_get_pool_constant (rtx x)
12658 x = ix86_delegitimize_address (XEXP (x, 0));
12660 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12661 return get_pool_constant (x);
12667 ix86_expand_move (enum machine_mode mode, rtx operands[])
12670 enum tls_model model;
12675 if (GET_CODE (op1) == SYMBOL_REF)
12677 model = SYMBOL_REF_TLS_MODEL (op1);
12680 op1 = legitimize_tls_address (op1, model, true);
12681 op1 = force_operand (op1, op0);
12685 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12686 && SYMBOL_REF_DLLIMPORT_P (op1))
12687 op1 = legitimize_dllimport_symbol (op1, false);
12689 else if (GET_CODE (op1) == CONST
12690 && GET_CODE (XEXP (op1, 0)) == PLUS
12691 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12693 rtx addend = XEXP (XEXP (op1, 0), 1);
12694 rtx symbol = XEXP (XEXP (op1, 0), 0);
12697 model = SYMBOL_REF_TLS_MODEL (symbol);
12699 tmp = legitimize_tls_address (symbol, model, true);
12700 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12701 && SYMBOL_REF_DLLIMPORT_P (symbol))
12702 tmp = legitimize_dllimport_symbol (symbol, true);
12706 tmp = force_operand (tmp, NULL);
12707 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12708 op0, 1, OPTAB_DIRECT);
12714 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12716 if (TARGET_MACHO && !TARGET_64BIT)
12721 rtx temp = ((reload_in_progress
12722 || ((op0 && REG_P (op0))
12724 ? op0 : gen_reg_rtx (Pmode));
12725 op1 = machopic_indirect_data_reference (op1, temp);
12726 op1 = machopic_legitimize_pic_address (op1, mode,
12727 temp == op1 ? 0 : temp);
12729 else if (MACHOPIC_INDIRECT)
12730 op1 = machopic_indirect_data_reference (op1, 0);
12738 op1 = force_reg (Pmode, op1);
12739 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12741 rtx reg = can_create_pseudo_p () ? NULL_RTX : op0;
12742 op1 = legitimize_pic_address (op1, reg);
12751 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12752 || !push_operand (op0, mode))
12754 op1 = force_reg (mode, op1);
12756 if (push_operand (op0, mode)
12757 && ! general_no_elim_operand (op1, mode))
12758 op1 = copy_to_mode_reg (mode, op1);
12760 /* Force large constants in 64bit compilation into register
12761 to get them CSEed. */
12762 if (can_create_pseudo_p ()
12763 && (mode == DImode) && TARGET_64BIT
12764 && immediate_operand (op1, mode)
12765 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12766 && !register_operand (op0, mode)
12768 op1 = copy_to_mode_reg (mode, op1);
12770 if (can_create_pseudo_p ()
12771 && FLOAT_MODE_P (mode)
12772 && GET_CODE (op1) == CONST_DOUBLE)
12774 /* If we are loading a floating point constant to a register,
12775 force the value to memory now, since we'll get better code
12776 out the back end. */
12778 op1 = validize_mem (force_const_mem (mode, op1));
12779 if (!register_operand (op0, mode))
12781 rtx temp = gen_reg_rtx (mode);
12782 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12783 emit_move_insn (op0, temp);
12789 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12793 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12795 rtx op0 = operands[0], op1 = operands[1];
12796 unsigned int align = GET_MODE_ALIGNMENT (mode);
12798 /* Force constants other than zero into memory. We do not know how
12799 the instructions used to build constants modify the upper 64 bits
12800 of the register, once we have that information we may be able
12801 to handle some of them more efficiently. */
12802 if (can_create_pseudo_p ()
12803 && register_operand (op0, mode)
12804 && (CONSTANT_P (op1)
12805 || (GET_CODE (op1) == SUBREG
12806 && CONSTANT_P (SUBREG_REG (op1))))
12807 && !standard_sse_constant_p (op1))
12808 op1 = validize_mem (force_const_mem (mode, op1));
12810 /* We need to check memory alignment for SSE mode since attribute
12811 can make operands unaligned. */
12812 if (can_create_pseudo_p ()
12813 && SSE_REG_MODE_P (mode)
12814 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12815 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12819 /* ix86_expand_vector_move_misalign() does not like constants ... */
12820 if (CONSTANT_P (op1)
12821 || (GET_CODE (op1) == SUBREG
12822 && CONSTANT_P (SUBREG_REG (op1))))
12823 op1 = validize_mem (force_const_mem (mode, op1));
12825 /* ... nor both arguments in memory. */
12826 if (!register_operand (op0, mode)
12827 && !register_operand (op1, mode))
12828 op1 = force_reg (mode, op1);
12830 tmp[0] = op0; tmp[1] = op1;
12831 ix86_expand_vector_move_misalign (mode, tmp);
12835 /* Make operand1 a register if it isn't already. */
12836 if (can_create_pseudo_p ()
12837 && !register_operand (op0, mode)
12838 && !register_operand (op1, mode))
12840 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12844 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12847 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12848 straight to ix86_expand_vector_move. */
12849 /* Code generation for scalar reg-reg moves of single and double precision data:
12850 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12854 if (x86_sse_partial_reg_dependency == true)
12859 Code generation for scalar loads of double precision data:
12860 if (x86_sse_split_regs == true)
12861 movlpd mem, reg (gas syntax)
12865 Code generation for unaligned packed loads of single precision data
12866 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12867 if (x86_sse_unaligned_move_optimal)
12870 if (x86_sse_partial_reg_dependency == true)
12882 Code generation for unaligned packed loads of double precision data
12883 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12884 if (x86_sse_unaligned_move_optimal)
12887 if (x86_sse_split_regs == true)
12900 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12909 switch (GET_MODE_CLASS (mode))
12911 case MODE_VECTOR_INT:
12913 switch (GET_MODE_SIZE (mode))
12916 op0 = gen_lowpart (V16QImode, op0);
12917 op1 = gen_lowpart (V16QImode, op1);
12918 emit_insn (gen_avx_movdqu (op0, op1));
12921 op0 = gen_lowpart (V32QImode, op0);
12922 op1 = gen_lowpart (V32QImode, op1);
12923 emit_insn (gen_avx_movdqu256 (op0, op1));
12926 gcc_unreachable ();
12929 case MODE_VECTOR_FLOAT:
12930 op0 = gen_lowpart (mode, op0);
12931 op1 = gen_lowpart (mode, op1);
12936 emit_insn (gen_avx_movups (op0, op1));
12939 emit_insn (gen_avx_movups256 (op0, op1));
12942 emit_insn (gen_avx_movupd (op0, op1));
12945 emit_insn (gen_avx_movupd256 (op0, op1));
12948 gcc_unreachable ();
12953 gcc_unreachable ();
12961 /* If we're optimizing for size, movups is the smallest. */
12962 if (optimize_insn_for_size_p ())
12964 op0 = gen_lowpart (V4SFmode, op0);
12965 op1 = gen_lowpart (V4SFmode, op1);
12966 emit_insn (gen_sse_movups (op0, op1));
12970 /* ??? If we have typed data, then it would appear that using
12971 movdqu is the only way to get unaligned data loaded with
12973 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12975 op0 = gen_lowpart (V16QImode, op0);
12976 op1 = gen_lowpart (V16QImode, op1);
12977 emit_insn (gen_sse2_movdqu (op0, op1));
12981 if (TARGET_SSE2 && mode == V2DFmode)
12985 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12987 op0 = gen_lowpart (V2DFmode, op0);
12988 op1 = gen_lowpart (V2DFmode, op1);
12989 emit_insn (gen_sse2_movupd (op0, op1));
12993 /* When SSE registers are split into halves, we can avoid
12994 writing to the top half twice. */
12995 if (TARGET_SSE_SPLIT_REGS)
12997 emit_clobber (op0);
13002 /* ??? Not sure about the best option for the Intel chips.
13003 The following would seem to satisfy; the register is
13004 entirely cleared, breaking the dependency chain. We
13005 then store to the upper half, with a dependency depth
13006 of one. A rumor has it that Intel recommends two movsd
13007 followed by an unpacklpd, but this is unconfirmed. And
13008 given that the dependency depth of the unpacklpd would
13009 still be one, I'm not sure why this would be better. */
13010 zero = CONST0_RTX (V2DFmode);
13013 m = adjust_address (op1, DFmode, 0);
13014 emit_insn (gen_sse2_loadlpd (op0, zero, m));
13015 m = adjust_address (op1, DFmode, 8);
13016 emit_insn (gen_sse2_loadhpd (op0, op0, m));
13020 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
13022 op0 = gen_lowpart (V4SFmode, op0);
13023 op1 = gen_lowpart (V4SFmode, op1);
13024 emit_insn (gen_sse_movups (op0, op1));
13028 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
13029 emit_move_insn (op0, CONST0_RTX (mode));
13031 emit_clobber (op0);
13033 if (mode != V4SFmode)
13034 op0 = gen_lowpart (V4SFmode, op0);
13035 m = adjust_address (op1, V2SFmode, 0);
13036 emit_insn (gen_sse_loadlps (op0, op0, m));
13037 m = adjust_address (op1, V2SFmode, 8);
13038 emit_insn (gen_sse_loadhps (op0, op0, m));
13041 else if (MEM_P (op0))
13043 /* If we're optimizing for size, movups is the smallest. */
13044 if (optimize_insn_for_size_p ())
13046 op0 = gen_lowpart (V4SFmode, op0);
13047 op1 = gen_lowpart (V4SFmode, op1);
13048 emit_insn (gen_sse_movups (op0, op1));
13052 /* ??? Similar to above, only less clear because of quote
13053 typeless stores unquote. */
13054 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
13055 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
13057 op0 = gen_lowpart (V16QImode, op0);
13058 op1 = gen_lowpart (V16QImode, op1);
13059 emit_insn (gen_sse2_movdqu (op0, op1));
13063 if (TARGET_SSE2 && mode == V2DFmode)
13065 m = adjust_address (op0, DFmode, 0);
13066 emit_insn (gen_sse2_storelpd (m, op1));
13067 m = adjust_address (op0, DFmode, 8);
13068 emit_insn (gen_sse2_storehpd (m, op1));
13072 if (mode != V4SFmode)
13073 op1 = gen_lowpart (V4SFmode, op1);
13074 m = adjust_address (op0, V2SFmode, 0);
13075 emit_insn (gen_sse_storelps (m, op1));
13076 m = adjust_address (op0, V2SFmode, 8);
13077 emit_insn (gen_sse_storehps (m, op1));
13081 gcc_unreachable ();
13084 /* Expand a push in MODE. This is some mode for which we do not support
13085 proper push instructions, at least from the registers that we expect
13086 the value to live in. */
13089 ix86_expand_push (enum machine_mode mode, rtx x)
13093 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
13094 GEN_INT (-GET_MODE_SIZE (mode)),
13095 stack_pointer_rtx, 1, OPTAB_DIRECT);
13096 if (tmp != stack_pointer_rtx)
13097 emit_move_insn (stack_pointer_rtx, tmp);
13099 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
13101 /* When we push an operand onto stack, it has to be aligned at least
13102 at the function argument boundary. However since we don't have
13103 the argument type, we can't determine the actual argument
13105 emit_move_insn (tmp, x);
13108 /* Helper function of ix86_fixup_binary_operands to canonicalize
13109 operand order. Returns true if the operands should be swapped. */
13112 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
13115 rtx dst = operands[0];
13116 rtx src1 = operands[1];
13117 rtx src2 = operands[2];
13119 /* If the operation is not commutative, we can't do anything. */
13120 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
13123 /* Highest priority is that src1 should match dst. */
13124 if (rtx_equal_p (dst, src1))
13126 if (rtx_equal_p (dst, src2))
13129 /* Next highest priority is that immediate constants come second. */
13130 if (immediate_operand (src2, mode))
13132 if (immediate_operand (src1, mode))
13135 /* Lowest priority is that memory references should come second. */
13145 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
13146 destination to use for the operation. If different from the true
13147 destination in operands[0], a copy operation will be required. */
13150 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
13153 rtx dst = operands[0];
13154 rtx src1 = operands[1];
13155 rtx src2 = operands[2];
13157 /* Canonicalize operand order. */
13158 if (ix86_swap_binary_operands_p (code, mode, operands))
13162 /* It is invalid to swap operands of different modes. */
13163 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
13170 /* Both source operands cannot be in memory. */
13171 if (MEM_P (src1) && MEM_P (src2))
13173 /* Optimization: Only read from memory once. */
13174 if (rtx_equal_p (src1, src2))
13176 src2 = force_reg (mode, src2);
13180 src2 = force_reg (mode, src2);
13183 /* If the destination is memory, and we do not have matching source
13184 operands, do things in registers. */
13185 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13186 dst = gen_reg_rtx (mode);
13188 /* Source 1 cannot be a constant. */
13189 if (CONSTANT_P (src1))
13190 src1 = force_reg (mode, src1);
13192 /* Source 1 cannot be a non-matching memory. */
13193 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13194 src1 = force_reg (mode, src1);
13196 operands[1] = src1;
13197 operands[2] = src2;
13201 /* Similarly, but assume that the destination has already been
13202 set up properly. */
13205 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
13206 enum machine_mode mode, rtx operands[])
13208 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
13209 gcc_assert (dst == operands[0]);
13212 /* Attempt to expand a binary operator. Make the expansion closer to the
13213 actual machine, then just general_operand, which will allow 3 separate
13214 memory references (one output, two input) in a single insn. */
13217 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
13220 rtx src1, src2, dst, op, clob;
13222 dst = ix86_fixup_binary_operands (code, mode, operands);
13223 src1 = operands[1];
13224 src2 = operands[2];
13226 /* Emit the instruction. */
13228 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
13229 if (reload_in_progress)
13231 /* Reload doesn't know about the flags register, and doesn't know that
13232 it doesn't want to clobber it. We can only do this with PLUS. */
13233 gcc_assert (code == PLUS);
13238 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13239 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13242 /* Fix up the destination if needed. */
13243 if (dst != operands[0])
13244 emit_move_insn (operands[0], dst);
13247 /* Return TRUE or FALSE depending on whether the binary operator meets the
13248 appropriate constraints. */
13251 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
13254 rtx dst = operands[0];
13255 rtx src1 = operands[1];
13256 rtx src2 = operands[2];
13258 /* Both source operands cannot be in memory. */
13259 if (MEM_P (src1) && MEM_P (src2))
13262 /* Canonicalize operand order for commutative operators. */
13263 if (ix86_swap_binary_operands_p (code, mode, operands))
13270 /* If the destination is memory, we must have a matching source operand. */
13271 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
13274 /* Source 1 cannot be a constant. */
13275 if (CONSTANT_P (src1))
13278 /* Source 1 cannot be a non-matching memory. */
13279 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
13285 /* Attempt to expand a unary operator. Make the expansion closer to the
13286 actual machine, then just general_operand, which will allow 2 separate
13287 memory references (one output, one input) in a single insn. */
13290 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
13293 int matching_memory;
13294 rtx src, dst, op, clob;
13299 /* If the destination is memory, and we do not have matching source
13300 operands, do things in registers. */
13301 matching_memory = 0;
13304 if (rtx_equal_p (dst, src))
13305 matching_memory = 1;
13307 dst = gen_reg_rtx (mode);
13310 /* When source operand is memory, destination must match. */
13311 if (MEM_P (src) && !matching_memory)
13312 src = force_reg (mode, src);
13314 /* Emit the instruction. */
13316 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
13317 if (reload_in_progress || code == NOT)
13319 /* Reload doesn't know about the flags register, and doesn't know that
13320 it doesn't want to clobber it. */
13321 gcc_assert (code == NOT);
13326 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13327 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
13330 /* Fix up the destination if needed. */
13331 if (dst != operands[0])
13332 emit_move_insn (operands[0], dst);
13335 #define LEA_SEARCH_THRESHOLD 12
13337 /* Search backward for non-agu definition of register number REGNO1
13338 or register number REGNO2 in INSN's basic block until
13339 1. Pass LEA_SEARCH_THRESHOLD instructions, or
13340 2. Reach BB boundary, or
13341 3. Reach agu definition.
13342 Returns the distance between the non-agu definition point and INSN.
13343 If no definition point, returns -1. */
13346 distance_non_agu_define (unsigned int regno1, unsigned int regno2,
13349 basic_block bb = BLOCK_FOR_INSN (insn);
13352 enum attr_type insn_type;
13354 if (insn != BB_HEAD (bb))
13356 rtx prev = PREV_INSN (insn);
13357 while (prev && distance < LEA_SEARCH_THRESHOLD)
13362 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13363 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13364 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13365 && (regno1 == DF_REF_REGNO (*def_rec)
13366 || regno2 == DF_REF_REGNO (*def_rec)))
13368 insn_type = get_attr_type (prev);
13369 if (insn_type != TYPE_LEA)
13373 if (prev == BB_HEAD (bb))
13375 prev = PREV_INSN (prev);
13379 if (distance < LEA_SEARCH_THRESHOLD)
13383 bool simple_loop = false;
13385 FOR_EACH_EDGE (e, ei, bb->preds)
13388 simple_loop = true;
13394 rtx prev = BB_END (bb);
13397 && distance < LEA_SEARCH_THRESHOLD)
13402 for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
13403 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13404 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13405 && (regno1 == DF_REF_REGNO (*def_rec)
13406 || regno2 == DF_REF_REGNO (*def_rec)))
13408 insn_type = get_attr_type (prev);
13409 if (insn_type != TYPE_LEA)
13413 prev = PREV_INSN (prev);
13421 /* get_attr_type may modify recog data. We want to make sure
13422 that recog data is valid for instruction INSN, on which
13423 distance_non_agu_define is called. INSN is unchanged here. */
13424 extract_insn_cached (insn);
13428 /* Return the distance between INSN and the next insn that uses
13429 register number REGNO0 in memory address. Return -1 if no such
13430 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
13433 distance_agu_use (unsigned int regno0, rtx insn)
13435 basic_block bb = BLOCK_FOR_INSN (insn);
13440 if (insn != BB_END (bb))
13442 rtx next = NEXT_INSN (insn);
13443 while (next && distance < LEA_SEARCH_THRESHOLD)
13449 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13450 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13451 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13452 && regno0 == DF_REF_REGNO (*use_rec))
13454 /* Return DISTANCE if OP0 is used in memory
13455 address in NEXT. */
13459 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13460 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13461 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13462 && regno0 == DF_REF_REGNO (*def_rec))
13464 /* Return -1 if OP0 is set in NEXT. */
13468 if (next == BB_END (bb))
13470 next = NEXT_INSN (next);
13474 if (distance < LEA_SEARCH_THRESHOLD)
13478 bool simple_loop = false;
13480 FOR_EACH_EDGE (e, ei, bb->succs)
13483 simple_loop = true;
13489 rtx next = BB_HEAD (bb);
13492 && distance < LEA_SEARCH_THRESHOLD)
13498 for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
13499 if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
13500 || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
13501 && regno0 == DF_REF_REGNO (*use_rec))
13503 /* Return DISTANCE if OP0 is used in memory
13504 address in NEXT. */
13508 for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
13509 if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
13510 && !DF_REF_IS_ARTIFICIAL (*def_rec)
13511 && regno0 == DF_REF_REGNO (*def_rec))
13513 /* Return -1 if OP0 is set in NEXT. */
13518 next = NEXT_INSN (next);
13526 /* Define this macro to tune LEA priority vs ADD, it take effect when
13527 there is a dilemma of choicing LEA or ADD
13528 Negative value: ADD is more preferred than LEA
13530 Positive value: LEA is more preferred than ADD*/
13531 #define IX86_LEA_PRIORITY 2
13533 /* Return true if it is ok to optimize an ADD operation to LEA
13534 operation to avoid flag register consumation. For the processors
13535 like ATOM, if the destination register of LEA holds an actual
13536 address which will be used soon, LEA is better and otherwise ADD
13540 ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13541 rtx insn, rtx operands[])
13543 unsigned int regno0 = true_regnum (operands[0]);
13544 unsigned int regno1 = true_regnum (operands[1]);
13545 unsigned int regno2;
13547 if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
13548 return regno0 != regno1;
13550 regno2 = true_regnum (operands[2]);
13552 /* If a = b + c, (a!=b && a!=c), must use lea form. */
13553 if (regno0 != regno1 && regno0 != regno2)
13557 int dist_define, dist_use;
13558 dist_define = distance_non_agu_define (regno1, regno2, insn);
13559 if (dist_define <= 0)
13562 /* If this insn has both backward non-agu dependence and forward
13563 agu dependence, the one with short distance take effect. */
13564 dist_use = distance_agu_use (regno0, insn);
13566 || (dist_define + IX86_LEA_PRIORITY) < dist_use)
13573 /* Return true if destination reg of SET_BODY is shift count of
13577 ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
13583 /* Retrieve destination of SET_BODY. */
13584 switch (GET_CODE (set_body))
13587 set_dest = SET_DEST (set_body);
13588 if (!set_dest || !REG_P (set_dest))
13592 for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
13593 if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
13601 /* Retrieve shift count of USE_BODY. */
13602 switch (GET_CODE (use_body))
13605 shift_rtx = XEXP (use_body, 1);
13608 for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
13609 if (ix86_dep_by_shift_count_body (set_body,
13610 XVECEXP (use_body, 0, i)))
13618 && (GET_CODE (shift_rtx) == ASHIFT
13619 || GET_CODE (shift_rtx) == LSHIFTRT
13620 || GET_CODE (shift_rtx) == ASHIFTRT
13621 || GET_CODE (shift_rtx) == ROTATE
13622 || GET_CODE (shift_rtx) == ROTATERT))
13624 rtx shift_count = XEXP (shift_rtx, 1);
13626 /* Return true if shift count is dest of SET_BODY. */
13627 if (REG_P (shift_count)
13628 && true_regnum (set_dest) == true_regnum (shift_count))
13635 /* Return true if destination reg of SET_INSN is shift count of
13639 ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
13641 return ix86_dep_by_shift_count_body (PATTERN (set_insn),
13642 PATTERN (use_insn));
13645 /* Return TRUE or FALSE depending on whether the unary operator meets the
13646 appropriate constraints. */
13649 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
13650 enum machine_mode mode ATTRIBUTE_UNUSED,
13651 rtx operands[2] ATTRIBUTE_UNUSED)
13653 /* If one of operands is memory, source and destination must match. */
13654 if ((MEM_P (operands[0])
13655 || MEM_P (operands[1]))
13656 && ! rtx_equal_p (operands[0], operands[1]))
13661 /* Post-reload splitter for converting an SF or DFmode value in an
13662 SSE register into an unsigned SImode. */
13665 ix86_split_convert_uns_si_sse (rtx operands[])
13667 enum machine_mode vecmode;
13668 rtx value, large, zero_or_two31, input, two31, x;
13670 large = operands[1];
13671 zero_or_two31 = operands[2];
13672 input = operands[3];
13673 two31 = operands[4];
13674 vecmode = GET_MODE (large);
13675 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13677 /* Load up the value into the low element. We must ensure that the other
13678 elements are valid floats -- zero is the easiest such value. */
13681 if (vecmode == V4SFmode)
13682 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13684 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13688 input = gen_rtx_REG (vecmode, REGNO (input));
13689 emit_move_insn (value, CONST0_RTX (vecmode));
13690 if (vecmode == V4SFmode)
13691 emit_insn (gen_sse_movss (value, value, input));
13693 emit_insn (gen_sse2_movsd (value, value, input));
13696 emit_move_insn (large, two31);
13697 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13699 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13700 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13702 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13703 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13705 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13706 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13708 large = gen_rtx_REG (V4SImode, REGNO (large));
13709 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13711 x = gen_rtx_REG (V4SImode, REGNO (value));
13712 if (vecmode == V4SFmode)
13713 emit_insn (gen_sse2_cvttps2dq (x, value));
13715 emit_insn (gen_sse2_cvttpd2dq (x, value));
13718 emit_insn (gen_xorv4si3 (value, value, large));
13721 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13722 Expects the 64-bit DImode to be supplied in a pair of integral
13723 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13724 -mfpmath=sse, !optimize_size only. */
13727 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13729 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13730 rtx int_xmm, fp_xmm;
13731 rtx biases, exponents;
13734 int_xmm = gen_reg_rtx (V4SImode);
13735 if (TARGET_INTER_UNIT_MOVES)
13736 emit_insn (gen_movdi_to_sse (int_xmm, input));
13737 else if (TARGET_SSE_SPLIT_REGS)
13739 emit_clobber (int_xmm);
13740 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13744 x = gen_reg_rtx (V2DImode);
13745 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13746 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13749 x = gen_rtx_CONST_VECTOR (V4SImode,
13750 gen_rtvec (4, GEN_INT (0x43300000UL),
13751 GEN_INT (0x45300000UL),
13752 const0_rtx, const0_rtx));
13753 exponents = validize_mem (force_const_mem (V4SImode, x));
13755 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13756 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13758 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13759 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13760 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13761 (0x1.0p84 + double(fp_value_hi_xmm)).
13762 Note these exponents differ by 32. */
13764 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13766 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13767 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13768 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13769 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13770 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13771 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13772 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13773 biases = validize_mem (force_const_mem (V2DFmode, biases));
13774 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13776 /* Add the upper and lower DFmode values together. */
13778 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13781 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13782 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13783 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13786 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13789 /* Not used, but eases macroization of patterns. */
13791 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13792 rtx input ATTRIBUTE_UNUSED)
13794 gcc_unreachable ();
13797 /* Convert an unsigned SImode value into a DFmode. Only currently used
13798 for SSE, but applicable anywhere. */
13801 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13803 REAL_VALUE_TYPE TWO31r;
13806 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13807 NULL, 1, OPTAB_DIRECT);
13809 fp = gen_reg_rtx (DFmode);
13810 emit_insn (gen_floatsidf2 (fp, x));
13812 real_ldexp (&TWO31r, &dconst1, 31);
13813 x = const_double_from_real_value (TWO31r, DFmode);
13815 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13817 emit_move_insn (target, x);
13820 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13821 32-bit mode; otherwise we have a direct convert instruction. */
13824 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13826 REAL_VALUE_TYPE TWO32r;
13827 rtx fp_lo, fp_hi, x;
13829 fp_lo = gen_reg_rtx (DFmode);
13830 fp_hi = gen_reg_rtx (DFmode);
13832 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13834 real_ldexp (&TWO32r, &dconst1, 32);
13835 x = const_double_from_real_value (TWO32r, DFmode);
13836 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13838 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13840 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13843 emit_move_insn (target, x);
13846 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13847 For x86_32, -mfpmath=sse, !optimize_size only. */
13849 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13851 REAL_VALUE_TYPE ONE16r;
13852 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13854 real_ldexp (&ONE16r, &dconst1, 16);
13855 x = const_double_from_real_value (ONE16r, SFmode);
13856 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13857 NULL, 0, OPTAB_DIRECT);
13858 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13859 NULL, 0, OPTAB_DIRECT);
13860 fp_hi = gen_reg_rtx (SFmode);
13861 fp_lo = gen_reg_rtx (SFmode);
13862 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13863 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13864 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13866 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13868 if (!rtx_equal_p (target, fp_hi))
13869 emit_move_insn (target, fp_hi);
13872 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
13873 then replicate the value for all elements of the vector
13877 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13884 v = gen_rtvec (4, value, value, value, value);
13885 return gen_rtx_CONST_VECTOR (V4SImode, v);
13889 v = gen_rtvec (2, value, value);
13890 return gen_rtx_CONST_VECTOR (V2DImode, v);
13894 v = gen_rtvec (4, value, value, value, value);
13896 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13897 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13898 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13902 v = gen_rtvec (2, value, value);
13904 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13905 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13908 gcc_unreachable ();
13912 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13913 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13914 for an SSE register. If VECT is true, then replicate the mask for
13915 all elements of the vector register. If INVERT is true, then create
13916 a mask excluding the sign bit. */
13919 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13921 enum machine_mode vec_mode, imode;
13922 HOST_WIDE_INT hi, lo;
13927 /* Find the sign bit, sign extended to 2*HWI. */
13933 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13934 lo = 0x80000000, hi = lo < 0;
13940 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13941 if (HOST_BITS_PER_WIDE_INT >= 64)
13942 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13944 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13949 vec_mode = VOIDmode;
13950 if (HOST_BITS_PER_WIDE_INT >= 64)
13953 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13960 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13964 lo = ~lo, hi = ~hi;
13970 mask = immed_double_const (lo, hi, imode);
13972 vec = gen_rtvec (2, v, mask);
13973 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13974 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13981 gcc_unreachable ();
13985 lo = ~lo, hi = ~hi;
13987 /* Force this value into the low part of a fp vector constant. */
13988 mask = immed_double_const (lo, hi, imode);
13989 mask = gen_lowpart (mode, mask);
13991 if (vec_mode == VOIDmode)
13992 return force_reg (mode, mask);
13994 v = ix86_build_const_vector (mode, vect, mask);
13995 return force_reg (vec_mode, v);
13998 /* Generate code for floating point ABS or NEG. */
14001 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
14004 rtx mask, set, use, clob, dst, src;
14005 bool use_sse = false;
14006 bool vector_mode = VECTOR_MODE_P (mode);
14007 enum machine_mode elt_mode = mode;
14011 elt_mode = GET_MODE_INNER (mode);
14014 else if (mode == TFmode)
14016 else if (TARGET_SSE_MATH)
14017 use_sse = SSE_FLOAT_MODE_P (mode);
14019 /* NEG and ABS performed with SSE use bitwise mask operations.
14020 Create the appropriate mask now. */
14022 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
14031 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
14032 set = gen_rtx_SET (VOIDmode, dst, set);
14037 set = gen_rtx_fmt_e (code, mode, src);
14038 set = gen_rtx_SET (VOIDmode, dst, set);
14041 use = gen_rtx_USE (VOIDmode, mask);
14042 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
14043 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14044 gen_rtvec (3, set, use, clob)));
14051 /* Expand a copysign operation. Special case operand 0 being a constant. */
14054 ix86_expand_copysign (rtx operands[])
14056 enum machine_mode mode;
14057 rtx dest, op0, op1, mask, nmask;
14059 dest = operands[0];
14063 mode = GET_MODE (dest);
14065 if (GET_CODE (op0) == CONST_DOUBLE)
14067 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
14069 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
14070 op0 = simplify_unary_operation (ABS, mode, op0, mode);
14072 if (mode == SFmode || mode == DFmode)
14074 enum machine_mode vmode;
14076 vmode = mode == SFmode ? V4SFmode : V2DFmode;
14078 if (op0 == CONST0_RTX (mode))
14079 op0 = CONST0_RTX (vmode);
14082 rtx v = ix86_build_const_vector (mode, false, op0);
14084 op0 = force_reg (vmode, v);
14087 else if (op0 != CONST0_RTX (mode))
14088 op0 = force_reg (mode, op0);
14090 mask = ix86_build_signbit_mask (mode, 0, 0);
14092 if (mode == SFmode)
14093 copysign_insn = gen_copysignsf3_const;
14094 else if (mode == DFmode)
14095 copysign_insn = gen_copysigndf3_const;
14097 copysign_insn = gen_copysigntf3_const;
14099 emit_insn (copysign_insn (dest, op0, op1, mask));
14103 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
14105 nmask = ix86_build_signbit_mask (mode, 0, 1);
14106 mask = ix86_build_signbit_mask (mode, 0, 0);
14108 if (mode == SFmode)
14109 copysign_insn = gen_copysignsf3_var;
14110 else if (mode == DFmode)
14111 copysign_insn = gen_copysigndf3_var;
14113 copysign_insn = gen_copysigntf3_var;
14115 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
14119 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
14120 be a constant, and so has already been expanded into a vector constant. */
14123 ix86_split_copysign_const (rtx operands[])
14125 enum machine_mode mode, vmode;
14126 rtx dest, op0, op1, mask, x;
14128 dest = operands[0];
14131 mask = operands[3];
14133 mode = GET_MODE (dest);
14134 vmode = GET_MODE (mask);
14136 dest = simplify_gen_subreg (vmode, dest, mode, 0);
14137 x = gen_rtx_AND (vmode, dest, mask);
14138 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14140 if (op0 != CONST0_RTX (vmode))
14142 x = gen_rtx_IOR (vmode, dest, op0);
14143 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14147 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
14148 so we have to do two masks. */
14151 ix86_split_copysign_var (rtx operands[])
14153 enum machine_mode mode, vmode;
14154 rtx dest, scratch, op0, op1, mask, nmask, x;
14156 dest = operands[0];
14157 scratch = operands[1];
14160 nmask = operands[4];
14161 mask = operands[5];
14163 mode = GET_MODE (dest);
14164 vmode = GET_MODE (mask);
14166 if (rtx_equal_p (op0, op1))
14168 /* Shouldn't happen often (it's useless, obviously), but when it does
14169 we'd generate incorrect code if we continue below. */
14170 emit_move_insn (dest, op0);
14174 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
14176 gcc_assert (REGNO (op1) == REGNO (scratch));
14178 x = gen_rtx_AND (vmode, scratch, mask);
14179 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14182 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14183 x = gen_rtx_NOT (vmode, dest);
14184 x = gen_rtx_AND (vmode, x, op0);
14185 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14189 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
14191 x = gen_rtx_AND (vmode, scratch, mask);
14193 else /* alternative 2,4 */
14195 gcc_assert (REGNO (mask) == REGNO (scratch));
14196 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
14197 x = gen_rtx_AND (vmode, scratch, op1);
14199 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
14201 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
14203 dest = simplify_gen_subreg (vmode, op0, mode, 0);
14204 x = gen_rtx_AND (vmode, dest, nmask);
14206 else /* alternative 3,4 */
14208 gcc_assert (REGNO (nmask) == REGNO (dest));
14210 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
14211 x = gen_rtx_AND (vmode, dest, op0);
14213 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14216 x = gen_rtx_IOR (vmode, dest, scratch);
14217 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
14220 /* Return TRUE or FALSE depending on whether the first SET in INSN
14221 has source and destination with matching CC modes, and that the
14222 CC mode is at least as constrained as REQ_MODE. */
14225 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
14228 enum machine_mode set_mode;
14230 set = PATTERN (insn);
14231 if (GET_CODE (set) == PARALLEL)
14232 set = XVECEXP (set, 0, 0);
14233 gcc_assert (GET_CODE (set) == SET);
14234 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
14236 set_mode = GET_MODE (SET_DEST (set));
14240 if (req_mode != CCNOmode
14241 && (req_mode != CCmode
14242 || XEXP (SET_SRC (set), 1) != const0_rtx))
14246 if (req_mode == CCGCmode)
14250 if (req_mode == CCGOCmode || req_mode == CCNOmode)
14254 if (req_mode == CCZmode)
14265 gcc_unreachable ();
14268 return (GET_MODE (SET_SRC (set)) == set_mode);
14271 /* Generate insn patterns to do an integer compare of OPERANDS. */
14274 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
14276 enum machine_mode cmpmode;
14279 cmpmode = SELECT_CC_MODE (code, op0, op1);
14280 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
14282 /* This is very simple, but making the interface the same as in the
14283 FP case makes the rest of the code easier. */
14284 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
14285 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
14287 /* Return the test that should be put into the flags user, i.e.
14288 the bcc, scc, or cmov instruction. */
14289 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
14292 /* Figure out whether to use ordered or unordered fp comparisons.
14293 Return the appropriate mode to use. */
14296 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
14298 /* ??? In order to make all comparisons reversible, we do all comparisons
14299 non-trapping when compiling for IEEE. Once gcc is able to distinguish
14300 all forms trapping and nontrapping comparisons, we can make inequality
14301 comparisons trapping again, since it results in better code when using
14302 FCOM based compares. */
14303 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
14307 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
14309 enum machine_mode mode = GET_MODE (op0);
14311 if (SCALAR_FLOAT_MODE_P (mode))
14313 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14314 return ix86_fp_compare_mode (code);
14319 /* Only zero flag is needed. */
14320 case EQ: /* ZF=0 */
14321 case NE: /* ZF!=0 */
14323 /* Codes needing carry flag. */
14324 case GEU: /* CF=0 */
14325 case LTU: /* CF=1 */
14326 /* Detect overflow checks. They need just the carry flag. */
14327 if (GET_CODE (op0) == PLUS
14328 && rtx_equal_p (op1, XEXP (op0, 0)))
14332 case GTU: /* CF=0 & ZF=0 */
14333 case LEU: /* CF=1 | ZF=1 */
14334 /* Detect overflow checks. They need just the carry flag. */
14335 if (GET_CODE (op0) == MINUS
14336 && rtx_equal_p (op1, XEXP (op0, 0)))
14340 /* Codes possibly doable only with sign flag when
14341 comparing against zero. */
14342 case GE: /* SF=OF or SF=0 */
14343 case LT: /* SF<>OF or SF=1 */
14344 if (op1 == const0_rtx)
14347 /* For other cases Carry flag is not required. */
14349 /* Codes doable only with sign flag when comparing
14350 against zero, but we miss jump instruction for it
14351 so we need to use relational tests against overflow
14352 that thus needs to be zero. */
14353 case GT: /* ZF=0 & SF=OF */
14354 case LE: /* ZF=1 | SF<>OF */
14355 if (op1 == const0_rtx)
14359 /* strcmp pattern do (use flags) and combine may ask us for proper
14364 gcc_unreachable ();
14368 /* Return the fixed registers used for condition codes. */
14371 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
14378 /* If two condition code modes are compatible, return a condition code
14379 mode which is compatible with both. Otherwise, return
14382 static enum machine_mode
14383 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
14388 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
14391 if ((m1 == CCGCmode && m2 == CCGOCmode)
14392 || (m1 == CCGOCmode && m2 == CCGCmode))
14398 gcc_unreachable ();
14428 /* These are only compatible with themselves, which we already
14435 /* Return a comparison we can do and that it is equivalent to
14436 swap_condition (code) apart possibly from orderedness.
14437 But, never change orderedness if TARGET_IEEE_FP, returning
14438 UNKNOWN in that case if necessary. */
14440 static enum rtx_code
14441 ix86_fp_swap_condition (enum rtx_code code)
14445 case GT: /* GTU - CF=0 & ZF=0 */
14446 return TARGET_IEEE_FP ? UNKNOWN : UNLT;
14447 case GE: /* GEU - CF=0 */
14448 return TARGET_IEEE_FP ? UNKNOWN : UNLE;
14449 case UNLT: /* LTU - CF=1 */
14450 return TARGET_IEEE_FP ? UNKNOWN : GT;
14451 case UNLE: /* LEU - CF=1 | ZF=1 */
14452 return TARGET_IEEE_FP ? UNKNOWN : GE;
14454 return swap_condition (code);
14458 /* Return cost of comparison CODE using the best strategy for performance.
14459 All following functions do use number of instructions as a cost metrics.
14460 In future this should be tweaked to compute bytes for optimize_size and
14461 take into account performance of various instructions on various CPUs. */
14464 ix86_fp_comparison_cost (enum rtx_code code)
14468 /* The cost of code using bit-twiddling on %ah. */
14485 arith_cost = TARGET_IEEE_FP ? 5 : 4;
14489 arith_cost = TARGET_IEEE_FP ? 6 : 4;
14492 gcc_unreachable ();
14495 switch (ix86_fp_comparison_strategy (code))
14497 case IX86_FPCMP_COMI:
14498 return arith_cost > 4 ? 3 : 2;
14499 case IX86_FPCMP_SAHF:
14500 return arith_cost > 4 ? 4 : 3;
14506 /* Return strategy to use for floating-point. We assume that fcomi is always
14507 preferrable where available, since that is also true when looking at size
14508 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
14510 enum ix86_fpcmp_strategy
14511 ix86_fp_comparison_strategy (enum rtx_code code ATTRIBUTE_UNUSED)
14513 /* Do fcomi/sahf based test when profitable. */
14516 return IX86_FPCMP_COMI;
14518 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_function_for_size_p (cfun)))
14519 return IX86_FPCMP_SAHF;
14521 return IX86_FPCMP_ARITH;
14524 /* Swap, force into registers, or otherwise massage the two operands
14525 to a fp comparison. The operands are updated in place; the new
14526 comparison code is returned. */
14528 static enum rtx_code
14529 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
14531 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
14532 rtx op0 = *pop0, op1 = *pop1;
14533 enum machine_mode op_mode = GET_MODE (op0);
14534 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
14536 /* All of the unordered compare instructions only work on registers.
14537 The same is true of the fcomi compare instructions. The XFmode
14538 compare instructions require registers except when comparing
14539 against zero or when converting operand 1 from fixed point to
14543 && (fpcmp_mode == CCFPUmode
14544 || (op_mode == XFmode
14545 && ! (standard_80387_constant_p (op0) == 1
14546 || standard_80387_constant_p (op1) == 1)
14547 && GET_CODE (op1) != FLOAT)
14548 || ix86_fp_comparison_strategy (code) == IX86_FPCMP_COMI))
14550 op0 = force_reg (op_mode, op0);
14551 op1 = force_reg (op_mode, op1);
14555 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
14556 things around if they appear profitable, otherwise force op0
14557 into a register. */
14559 if (standard_80387_constant_p (op0) == 0
14561 && ! (standard_80387_constant_p (op1) == 0
14564 enum rtx_code new_code = ix86_fp_swap_condition (code);
14565 if (new_code != UNKNOWN)
14568 tmp = op0, op0 = op1, op1 = tmp;
14574 op0 = force_reg (op_mode, op0);
14576 if (CONSTANT_P (op1))
14578 int tmp = standard_80387_constant_p (op1);
14580 op1 = validize_mem (force_const_mem (op_mode, op1));
14584 op1 = force_reg (op_mode, op1);
14587 op1 = force_reg (op_mode, op1);
14591 /* Try to rearrange the comparison to make it cheaper. */
14592 if (ix86_fp_comparison_cost (code)
14593 > ix86_fp_comparison_cost (swap_condition (code))
14594 && (REG_P (op1) || can_create_pseudo_p ()))
14597 tmp = op0, op0 = op1, op1 = tmp;
14598 code = swap_condition (code);
14600 op0 = force_reg (op_mode, op0);
14608 /* Convert comparison codes we use to represent FP comparison to integer
14609 code that will result in proper branch. Return UNKNOWN if no such code
14613 ix86_fp_compare_code_to_integer (enum rtx_code code)
14642 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14645 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch)
14647 enum machine_mode fpcmp_mode, intcmp_mode;
14650 fpcmp_mode = ix86_fp_compare_mode (code);
14651 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14653 /* Do fcomi/sahf based test when profitable. */
14654 switch (ix86_fp_comparison_strategy (code))
14656 case IX86_FPCMP_COMI:
14657 intcmp_mode = fpcmp_mode;
14658 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14659 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14664 case IX86_FPCMP_SAHF:
14665 intcmp_mode = fpcmp_mode;
14666 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14667 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14671 scratch = gen_reg_rtx (HImode);
14672 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14673 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14676 case IX86_FPCMP_ARITH:
14677 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14678 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14679 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14681 scratch = gen_reg_rtx (HImode);
14682 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14684 /* In the unordered case, we have to check C2 for NaN's, which
14685 doesn't happen to work out to anything nice combination-wise.
14686 So do some bit twiddling on the value we've got in AH to come
14687 up with an appropriate set of condition codes. */
14689 intcmp_mode = CCNOmode;
14694 if (code == GT || !TARGET_IEEE_FP)
14696 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14701 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14702 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14703 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14704 intcmp_mode = CCmode;
14710 if (code == LT && TARGET_IEEE_FP)
14712 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14713 emit_insn (gen_cmpqi_ext_3 (scratch, const1_rtx));
14714 intcmp_mode = CCmode;
14719 emit_insn (gen_testqi_ext_ccno_0 (scratch, const1_rtx));
14725 if (code == GE || !TARGET_IEEE_FP)
14727 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14732 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14733 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch, const1_rtx));
14739 if (code == LE && TARGET_IEEE_FP)
14741 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14742 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14743 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14744 intcmp_mode = CCmode;
14749 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14755 if (code == EQ && TARGET_IEEE_FP)
14757 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14758 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14759 intcmp_mode = CCmode;
14764 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14770 if (code == NE && TARGET_IEEE_FP)
14772 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14773 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14779 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14785 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14789 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14794 gcc_unreachable ();
14802 /* Return the test that should be put into the flags user, i.e.
14803 the bcc, scc, or cmov instruction. */
14804 return gen_rtx_fmt_ee (code, VOIDmode,
14805 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14810 ix86_expand_compare (enum rtx_code code)
14813 op0 = ix86_compare_op0;
14814 op1 = ix86_compare_op1;
14816 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC)
14817 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_op0, ix86_compare_op1);
14819 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14821 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14822 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
14825 ret = ix86_expand_int_compare (code, op0, op1);
14831 ix86_expand_branch (enum rtx_code code, rtx label)
14835 switch (GET_MODE (ix86_compare_op0))
14844 tmp = ix86_expand_compare (code);
14845 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14846 gen_rtx_LABEL_REF (VOIDmode, label),
14848 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14855 /* Expand DImode branch into multiple compare+branch. */
14857 rtx lo[2], hi[2], label2;
14858 enum rtx_code code1, code2, code3;
14859 enum machine_mode submode;
14861 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14863 tmp = ix86_compare_op0;
14864 ix86_compare_op0 = ix86_compare_op1;
14865 ix86_compare_op1 = tmp;
14866 code = swap_condition (code);
14868 if (GET_MODE (ix86_compare_op0) == DImode)
14870 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14871 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14876 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14877 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14881 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14882 avoid two branches. This costs one extra insn, so disable when
14883 optimizing for size. */
14885 if ((code == EQ || code == NE)
14886 && (!optimize_insn_for_size_p ()
14887 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14892 if (hi[1] != const0_rtx)
14893 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14894 NULL_RTX, 0, OPTAB_WIDEN);
14897 if (lo[1] != const0_rtx)
14898 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14899 NULL_RTX, 0, OPTAB_WIDEN);
14901 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14902 NULL_RTX, 0, OPTAB_WIDEN);
14904 ix86_compare_op0 = tmp;
14905 ix86_compare_op1 = const0_rtx;
14906 ix86_expand_branch (code, label);
14910 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14911 op1 is a constant and the low word is zero, then we can just
14912 examine the high word. Similarly for low word -1 and
14913 less-or-equal-than or greater-than. */
14915 if (CONST_INT_P (hi[1]))
14918 case LT: case LTU: case GE: case GEU:
14919 if (lo[1] == const0_rtx)
14921 ix86_compare_op0 = hi[0];
14922 ix86_compare_op1 = hi[1];
14923 ix86_expand_branch (code, label);
14927 case LE: case LEU: case GT: case GTU:
14928 if (lo[1] == constm1_rtx)
14930 ix86_compare_op0 = hi[0];
14931 ix86_compare_op1 = hi[1];
14932 ix86_expand_branch (code, label);
14940 /* Otherwise, we need two or three jumps. */
14942 label2 = gen_label_rtx ();
14945 code2 = swap_condition (code);
14946 code3 = unsigned_condition (code);
14950 case LT: case GT: case LTU: case GTU:
14953 case LE: code1 = LT; code2 = GT; break;
14954 case GE: code1 = GT; code2 = LT; break;
14955 case LEU: code1 = LTU; code2 = GTU; break;
14956 case GEU: code1 = GTU; code2 = LTU; break;
14958 case EQ: code1 = UNKNOWN; code2 = NE; break;
14959 case NE: code2 = UNKNOWN; break;
14962 gcc_unreachable ();
14967 * if (hi(a) < hi(b)) goto true;
14968 * if (hi(a) > hi(b)) goto false;
14969 * if (lo(a) < lo(b)) goto true;
14973 ix86_compare_op0 = hi[0];
14974 ix86_compare_op1 = hi[1];
14976 if (code1 != UNKNOWN)
14977 ix86_expand_branch (code1, label);
14978 if (code2 != UNKNOWN)
14979 ix86_expand_branch (code2, label2);
14981 ix86_compare_op0 = lo[0];
14982 ix86_compare_op1 = lo[1];
14983 ix86_expand_branch (code3, label);
14985 if (code2 != UNKNOWN)
14986 emit_label (label2);
14991 /* If we have already emitted a compare insn, go straight to simple.
14992 ix86_expand_compare won't emit anything if ix86_compare_emitted
14994 gcc_assert (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_CC);
14999 /* Split branch based on floating point condition. */
15001 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
15002 rtx target1, rtx target2, rtx tmp, rtx pushed)
15007 if (target2 != pc_rtx)
15010 code = reverse_condition_maybe_unordered (code);
15015 condition = ix86_expand_fp_compare (code, op1, op2,
15018 /* Remove pushed operand from stack. */
15020 ix86_free_from_memory (GET_MODE (pushed));
15022 i = emit_jump_insn (gen_rtx_SET
15024 gen_rtx_IF_THEN_ELSE (VOIDmode,
15025 condition, target1, target2)));
15026 if (split_branch_probability >= 0)
15027 add_reg_note (i, REG_BR_PROB, GEN_INT (split_branch_probability));
15031 ix86_expand_setcc (enum rtx_code code, rtx dest)
15035 gcc_assert (GET_MODE (dest) == QImode);
15037 ret = ix86_expand_compare (code);
15038 PUT_MODE (ret, QImode);
15039 emit_insn (gen_rtx_SET (VOIDmode, dest, ret));
15042 /* Expand comparison setting or clearing carry flag. Return true when
15043 successful and set pop for the operation. */
15045 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
15047 enum machine_mode mode =
15048 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
15050 /* Do not handle DImode compares that go through special path. */
15051 if (mode == (TARGET_64BIT ? TImode : DImode))
15054 if (SCALAR_FLOAT_MODE_P (mode))
15056 rtx compare_op, compare_seq;
15058 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
15060 /* Shortcut: following common codes never translate
15061 into carry flag compares. */
15062 if (code == EQ || code == NE || code == UNEQ || code == LTGT
15063 || code == ORDERED || code == UNORDERED)
15066 /* These comparisons require zero flag; swap operands so they won't. */
15067 if ((code == GT || code == UNLE || code == LE || code == UNGT)
15068 && !TARGET_IEEE_FP)
15073 code = swap_condition (code);
15076 /* Try to expand the comparison and verify that we end up with
15077 carry flag based comparison. This fails to be true only when
15078 we decide to expand comparison using arithmetic that is not
15079 too common scenario. */
15081 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX);
15082 compare_seq = get_insns ();
15085 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15086 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15087 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
15089 code = GET_CODE (compare_op);
15091 if (code != LTU && code != GEU)
15094 emit_insn (compare_seq);
15099 if (!INTEGRAL_MODE_P (mode))
15108 /* Convert a==0 into (unsigned)a<1. */
15111 if (op1 != const0_rtx)
15114 code = (code == EQ ? LTU : GEU);
15117 /* Convert a>b into b<a or a>=b-1. */
15120 if (CONST_INT_P (op1))
15122 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
15123 /* Bail out on overflow. We still can swap operands but that
15124 would force loading of the constant into register. */
15125 if (op1 == const0_rtx
15126 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
15128 code = (code == GTU ? GEU : LTU);
15135 code = (code == GTU ? LTU : GEU);
15139 /* Convert a>=0 into (unsigned)a<0x80000000. */
15142 if (mode == DImode || op1 != const0_rtx)
15144 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15145 code = (code == LT ? GEU : LTU);
15149 if (mode == DImode || op1 != constm1_rtx)
15151 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
15152 code = (code == LE ? GEU : LTU);
15158 /* Swapping operands may cause constant to appear as first operand. */
15159 if (!nonimmediate_operand (op0, VOIDmode))
15161 if (!can_create_pseudo_p ())
15163 op0 = force_reg (mode, op0);
15165 ix86_compare_op0 = op0;
15166 ix86_compare_op1 = op1;
15167 *pop = ix86_expand_compare (code);
15168 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
15173 ix86_expand_int_movcc (rtx operands[])
15175 enum rtx_code code = GET_CODE (operands[1]), compare_code;
15176 rtx compare_seq, compare_op;
15177 enum machine_mode mode = GET_MODE (operands[0]);
15178 bool sign_bit_compare_p = false;;
15181 ix86_compare_op0 = XEXP (operands[1], 0);
15182 ix86_compare_op1 = XEXP (operands[1], 1);
15183 compare_op = ix86_expand_compare (code);
15184 compare_seq = get_insns ();
15187 compare_code = GET_CODE (compare_op);
15189 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
15190 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
15191 sign_bit_compare_p = true;
15193 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
15194 HImode insns, we'd be swallowed in word prefix ops. */
15196 if ((mode != HImode || TARGET_FAST_PREFIX)
15197 && (mode != (TARGET_64BIT ? TImode : DImode))
15198 && CONST_INT_P (operands[2])
15199 && CONST_INT_P (operands[3]))
15201 rtx out = operands[0];
15202 HOST_WIDE_INT ct = INTVAL (operands[2]);
15203 HOST_WIDE_INT cf = INTVAL (operands[3]);
15204 HOST_WIDE_INT diff;
15207 /* Sign bit compares are better done using shifts than we do by using
15209 if (sign_bit_compare_p
15210 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
15211 ix86_compare_op1, &compare_op))
15213 /* Detect overlap between destination and compare sources. */
15216 if (!sign_bit_compare_p)
15218 bool fpcmp = false;
15220 compare_code = GET_CODE (compare_op);
15222 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
15223 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
15226 compare_code = ix86_fp_compare_code_to_integer (compare_code);
15229 /* To simplify rest of code, restrict to the GEU case. */
15230 if (compare_code == LTU)
15232 HOST_WIDE_INT tmp = ct;
15235 compare_code = reverse_condition (compare_code);
15236 code = reverse_condition (code);
15241 PUT_CODE (compare_op,
15242 reverse_condition_maybe_unordered
15243 (GET_CODE (compare_op)));
15245 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
15249 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
15250 || reg_overlap_mentioned_p (out, ix86_compare_op1))
15251 tmp = gen_reg_rtx (mode);
15253 if (mode == DImode)
15254 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
15256 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
15260 if (code == GT || code == GE)
15261 code = reverse_condition (code);
15264 HOST_WIDE_INT tmp = ct;
15269 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
15270 ix86_compare_op1, VOIDmode, 0, -1);
15283 tmp = expand_simple_binop (mode, PLUS,
15285 copy_rtx (tmp), 1, OPTAB_DIRECT);
15296 tmp = expand_simple_binop (mode, IOR,
15298 copy_rtx (tmp), 1, OPTAB_DIRECT);
15300 else if (diff == -1 && ct)
15310 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15312 tmp = expand_simple_binop (mode, PLUS,
15313 copy_rtx (tmp), GEN_INT (cf),
15314 copy_rtx (tmp), 1, OPTAB_DIRECT);
15322 * andl cf - ct, dest
15332 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
15335 tmp = expand_simple_binop (mode, AND,
15337 gen_int_mode (cf - ct, mode),
15338 copy_rtx (tmp), 1, OPTAB_DIRECT);
15340 tmp = expand_simple_binop (mode, PLUS,
15341 copy_rtx (tmp), GEN_INT (ct),
15342 copy_rtx (tmp), 1, OPTAB_DIRECT);
15345 if (!rtx_equal_p (tmp, out))
15346 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
15348 return 1; /* DONE */
15353 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15356 tmp = ct, ct = cf, cf = tmp;
15359 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15361 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15363 /* We may be reversing unordered compare to normal compare, that
15364 is not valid in general (we may convert non-trapping condition
15365 to trapping one), however on i386 we currently emit all
15366 comparisons unordered. */
15367 compare_code = reverse_condition_maybe_unordered (compare_code);
15368 code = reverse_condition_maybe_unordered (code);
15372 compare_code = reverse_condition (compare_code);
15373 code = reverse_condition (code);
15377 compare_code = UNKNOWN;
15378 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
15379 && CONST_INT_P (ix86_compare_op1))
15381 if (ix86_compare_op1 == const0_rtx
15382 && (code == LT || code == GE))
15383 compare_code = code;
15384 else if (ix86_compare_op1 == constm1_rtx)
15388 else if (code == GT)
15393 /* Optimize dest = (op0 < 0) ? -1 : cf. */
15394 if (compare_code != UNKNOWN
15395 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
15396 && (cf == -1 || ct == -1))
15398 /* If lea code below could be used, only optimize
15399 if it results in a 2 insn sequence. */
15401 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15402 || diff == 3 || diff == 5 || diff == 9)
15403 || (compare_code == LT && ct == -1)
15404 || (compare_code == GE && cf == -1))
15407 * notl op1 (if necessary)
15415 code = reverse_condition (code);
15418 out = emit_store_flag (out, code, ix86_compare_op0,
15419 ix86_compare_op1, VOIDmode, 0, -1);
15421 out = expand_simple_binop (mode, IOR,
15423 out, 1, OPTAB_DIRECT);
15424 if (out != operands[0])
15425 emit_move_insn (operands[0], out);
15427 return 1; /* DONE */
15432 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15433 || diff == 3 || diff == 5 || diff == 9)
15434 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15436 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15442 * lea cf(dest*(ct-cf)),dest
15446 * This also catches the degenerate setcc-only case.
15452 out = emit_store_flag (out, code, ix86_compare_op0,
15453 ix86_compare_op1, VOIDmode, 0, 1);
15456 /* On x86_64 the lea instruction operates on Pmode, so we need
15457 to get arithmetics done in proper mode to match. */
15459 tmp = copy_rtx (out);
15463 out1 = copy_rtx (out);
15464 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15468 tmp = gen_rtx_PLUS (mode, tmp, out1);
15474 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15477 if (!rtx_equal_p (tmp, out))
15480 out = force_operand (tmp, copy_rtx (out));
15482 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15484 if (!rtx_equal_p (out, operands[0]))
15485 emit_move_insn (operands[0], copy_rtx (out));
15487 return 1; /* DONE */
15491 * General case: Jumpful:
15492 * xorl dest,dest cmpl op1, op2
15493 * cmpl op1, op2 movl ct, dest
15494 * setcc dest jcc 1f
15495 * decl dest movl cf, dest
15496 * andl (cf-ct),dest 1:
15499 * Size 20. Size 14.
15501 * This is reasonably steep, but branch mispredict costs are
15502 * high on modern cpus, so consider failing only if optimizing
15506 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15507 && BRANCH_COST (optimize_insn_for_speed_p (),
15512 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15517 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15519 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15521 /* We may be reversing unordered compare to normal compare,
15522 that is not valid in general (we may convert non-trapping
15523 condition to trapping one), however on i386 we currently
15524 emit all comparisons unordered. */
15525 code = reverse_condition_maybe_unordered (code);
15529 code = reverse_condition (code);
15530 if (compare_code != UNKNOWN)
15531 compare_code = reverse_condition (compare_code);
15535 if (compare_code != UNKNOWN)
15537 /* notl op1 (if needed)
15542 For x < 0 (resp. x <= -1) there will be no notl,
15543 so if possible swap the constants to get rid of the
15545 True/false will be -1/0 while code below (store flag
15546 followed by decrement) is 0/-1, so the constants need
15547 to be exchanged once more. */
15549 if (compare_code == GE || !cf)
15551 code = reverse_condition (code);
15556 HOST_WIDE_INT tmp = cf;
15561 out = emit_store_flag (out, code, ix86_compare_op0,
15562 ix86_compare_op1, VOIDmode, 0, -1);
15566 out = emit_store_flag (out, code, ix86_compare_op0,
15567 ix86_compare_op1, VOIDmode, 0, 1);
15569 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15570 copy_rtx (out), 1, OPTAB_DIRECT);
15573 out = expand_simple_binop (mode, AND, copy_rtx (out),
15574 gen_int_mode (cf - ct, mode),
15575 copy_rtx (out), 1, OPTAB_DIRECT);
15577 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15578 copy_rtx (out), 1, OPTAB_DIRECT);
15579 if (!rtx_equal_p (out, operands[0]))
15580 emit_move_insn (operands[0], copy_rtx (out));
15582 return 1; /* DONE */
15586 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15588 /* Try a few things more with specific constants and a variable. */
15591 rtx var, orig_out, out, tmp;
15593 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15594 return 0; /* FAIL */
15596 /* If one of the two operands is an interesting constant, load a
15597 constant with the above and mask it in with a logical operation. */
15599 if (CONST_INT_P (operands[2]))
15602 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15603 operands[3] = constm1_rtx, op = and_optab;
15604 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15605 operands[3] = const0_rtx, op = ior_optab;
15607 return 0; /* FAIL */
15609 else if (CONST_INT_P (operands[3]))
15612 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15613 operands[2] = constm1_rtx, op = and_optab;
15614 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15615 operands[2] = const0_rtx, op = ior_optab;
15617 return 0; /* FAIL */
15620 return 0; /* FAIL */
15622 orig_out = operands[0];
15623 tmp = gen_reg_rtx (mode);
15626 /* Recurse to get the constant loaded. */
15627 if (ix86_expand_int_movcc (operands) == 0)
15628 return 0; /* FAIL */
15630 /* Mask in the interesting variable. */
15631 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15633 if (!rtx_equal_p (out, orig_out))
15634 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15636 return 1; /* DONE */
15640 * For comparison with above,
15650 if (! nonimmediate_operand (operands[2], mode))
15651 operands[2] = force_reg (mode, operands[2]);
15652 if (! nonimmediate_operand (operands[3], mode))
15653 operands[3] = force_reg (mode, operands[3]);
15655 if (! register_operand (operands[2], VOIDmode)
15657 || ! register_operand (operands[3], VOIDmode)))
15658 operands[2] = force_reg (mode, operands[2]);
15661 && ! register_operand (operands[3], VOIDmode))
15662 operands[3] = force_reg (mode, operands[3]);
15664 emit_insn (compare_seq);
15665 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15666 gen_rtx_IF_THEN_ELSE (mode,
15667 compare_op, operands[2],
15670 return 1; /* DONE */
15673 /* Swap, force into registers, or otherwise massage the two operands
15674 to an sse comparison with a mask result. Thus we differ a bit from
15675 ix86_prepare_fp_compare_args which expects to produce a flags result.
15677 The DEST operand exists to help determine whether to commute commutative
15678 operators. The POP0/POP1 operands are updated in place. The new
15679 comparison code is returned, or UNKNOWN if not implementable. */
15681 static enum rtx_code
15682 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15683 rtx *pop0, rtx *pop1)
15691 /* We have no LTGT as an operator. We could implement it with
15692 NE & ORDERED, but this requires an extra temporary. It's
15693 not clear that it's worth it. */
15700 /* These are supported directly. */
15707 /* For commutative operators, try to canonicalize the destination
15708 operand to be first in the comparison - this helps reload to
15709 avoid extra moves. */
15710 if (!dest || !rtx_equal_p (dest, *pop1))
15718 /* These are not supported directly. Swap the comparison operands
15719 to transform into something that is supported. */
15723 code = swap_condition (code);
15727 gcc_unreachable ();
15733 /* Detect conditional moves that exactly match min/max operational
15734 semantics. Note that this is IEEE safe, as long as we don't
15735 interchange the operands.
15737 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15738 and TRUE if the operation is successful and instructions are emitted. */
15741 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15742 rtx cmp_op1, rtx if_true, rtx if_false)
15744 enum machine_mode mode;
15750 else if (code == UNGE)
15753 if_true = if_false;
15759 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15761 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15766 mode = GET_MODE (dest);
15768 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15769 but MODE may be a vector mode and thus not appropriate. */
15770 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15772 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15775 if_true = force_reg (mode, if_true);
15776 v = gen_rtvec (2, if_true, if_false);
15777 tmp = gen_rtx_UNSPEC (mode, v, u);
15781 code = is_min ? SMIN : SMAX;
15782 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15785 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15789 /* Expand an sse vector comparison. Return the register with the result. */
15792 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15793 rtx op_true, rtx op_false)
15795 enum machine_mode mode = GET_MODE (dest);
15798 cmp_op0 = force_reg (mode, cmp_op0);
15799 if (!nonimmediate_operand (cmp_op1, mode))
15800 cmp_op1 = force_reg (mode, cmp_op1);
15803 || reg_overlap_mentioned_p (dest, op_true)
15804 || reg_overlap_mentioned_p (dest, op_false))
15805 dest = gen_reg_rtx (mode);
15807 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15808 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15813 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15814 operations. This is used for both scalar and vector conditional moves. */
15817 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15819 enum machine_mode mode = GET_MODE (dest);
15822 if (op_false == CONST0_RTX (mode))
15824 op_true = force_reg (mode, op_true);
15825 x = gen_rtx_AND (mode, cmp, op_true);
15826 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15828 else if (op_true == CONST0_RTX (mode))
15830 op_false = force_reg (mode, op_false);
15831 x = gen_rtx_NOT (mode, cmp);
15832 x = gen_rtx_AND (mode, x, op_false);
15833 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15837 op_true = force_reg (mode, op_true);
15838 op_false = force_reg (mode, op_false);
15840 t2 = gen_reg_rtx (mode);
15842 t3 = gen_reg_rtx (mode);
15846 x = gen_rtx_AND (mode, op_true, cmp);
15847 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15849 x = gen_rtx_NOT (mode, cmp);
15850 x = gen_rtx_AND (mode, x, op_false);
15851 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15853 x = gen_rtx_IOR (mode, t3, t2);
15854 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15858 /* Expand a floating-point conditional move. Return true if successful. */
15861 ix86_expand_fp_movcc (rtx operands[])
15863 enum machine_mode mode = GET_MODE (operands[0]);
15864 enum rtx_code code = GET_CODE (operands[1]);
15865 rtx tmp, compare_op;
15867 ix86_compare_op0 = XEXP (operands[1], 0);
15868 ix86_compare_op1 = XEXP (operands[1], 1);
15869 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15871 enum machine_mode cmode;
15873 /* Since we've no cmove for sse registers, don't force bad register
15874 allocation just to gain access to it. Deny movcc when the
15875 comparison mode doesn't match the move mode. */
15876 cmode = GET_MODE (ix86_compare_op0);
15877 if (cmode == VOIDmode)
15878 cmode = GET_MODE (ix86_compare_op1);
15882 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15884 &ix86_compare_op1);
15885 if (code == UNKNOWN)
15888 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15889 ix86_compare_op1, operands[2],
15893 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15894 ix86_compare_op1, operands[2], operands[3]);
15895 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15899 /* The floating point conditional move instructions don't directly
15900 support conditions resulting from a signed integer comparison. */
15902 compare_op = ix86_expand_compare (code);
15903 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15905 tmp = gen_reg_rtx (QImode);
15906 ix86_expand_setcc (code, tmp);
15908 ix86_compare_op0 = tmp;
15909 ix86_compare_op1 = const0_rtx;
15910 compare_op = ix86_expand_compare (code);
15913 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15914 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15915 operands[2], operands[3])));
15920 /* Expand a floating-point vector conditional move; a vcond operation
15921 rather than a movcc operation. */
15924 ix86_expand_fp_vcond (rtx operands[])
15926 enum rtx_code code = GET_CODE (operands[3]);
15929 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15930 &operands[4], &operands[5]);
15931 if (code == UNKNOWN)
15934 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15935 operands[5], operands[1], operands[2]))
15938 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15939 operands[1], operands[2]);
15940 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15944 /* Expand a signed/unsigned integral vector conditional move. */
15947 ix86_expand_int_vcond (rtx operands[])
15949 enum machine_mode mode = GET_MODE (operands[0]);
15950 enum rtx_code code = GET_CODE (operands[3]);
15951 bool negate = false;
15954 cop0 = operands[4];
15955 cop1 = operands[5];
15957 /* Canonicalize the comparison to EQ, GT, GTU. */
15968 code = reverse_condition (code);
15974 code = reverse_condition (code);
15980 code = swap_condition (code);
15981 x = cop0, cop0 = cop1, cop1 = x;
15985 gcc_unreachable ();
15988 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15989 if (mode == V2DImode)
15994 /* SSE4.1 supports EQ. */
15995 if (!TARGET_SSE4_1)
16001 /* SSE4.2 supports GT/GTU. */
16002 if (!TARGET_SSE4_2)
16007 gcc_unreachable ();
16011 /* Unsigned parallel compare is not supported by the hardware. Play some
16012 tricks to turn this into a signed comparison against 0. */
16015 cop0 = force_reg (mode, cop0);
16024 /* Perform a parallel modulo subtraction. */
16025 t1 = gen_reg_rtx (mode);
16026 emit_insn ((mode == V4SImode
16028 : gen_subv2di3) (t1, cop0, cop1));
16030 /* Extract the original sign bit of op0. */
16031 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
16033 t2 = gen_reg_rtx (mode);
16034 emit_insn ((mode == V4SImode
16036 : gen_andv2di3) (t2, cop0, mask));
16038 /* XOR it back into the result of the subtraction. This results
16039 in the sign bit set iff we saw unsigned underflow. */
16040 x = gen_reg_rtx (mode);
16041 emit_insn ((mode == V4SImode
16043 : gen_xorv2di3) (x, t1, t2));
16051 /* Perform a parallel unsigned saturating subtraction. */
16052 x = gen_reg_rtx (mode);
16053 emit_insn (gen_rtx_SET (VOIDmode, x,
16054 gen_rtx_US_MINUS (mode, cop0, cop1)));
16061 gcc_unreachable ();
16065 cop1 = CONST0_RTX (mode);
16068 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
16069 operands[1+negate], operands[2-negate]);
16071 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
16072 operands[2-negate]);
16076 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
16077 true if we should do zero extension, else sign extension. HIGH_P is
16078 true if we want the N/2 high elements, else the low elements. */
16081 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16083 enum machine_mode imode = GET_MODE (operands[1]);
16084 rtx (*unpack)(rtx, rtx, rtx);
16091 unpack = gen_vec_interleave_highv16qi;
16093 unpack = gen_vec_interleave_lowv16qi;
16097 unpack = gen_vec_interleave_highv8hi;
16099 unpack = gen_vec_interleave_lowv8hi;
16103 unpack = gen_vec_interleave_highv4si;
16105 unpack = gen_vec_interleave_lowv4si;
16108 gcc_unreachable ();
16111 dest = gen_lowpart (imode, operands[0]);
16114 se = force_reg (imode, CONST0_RTX (imode));
16116 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
16117 operands[1], pc_rtx, pc_rtx);
16119 emit_insn (unpack (dest, operands[1], se));
16122 /* This function performs the same task as ix86_expand_sse_unpack,
16123 but with SSE4.1 instructions. */
16126 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
16128 enum machine_mode imode = GET_MODE (operands[1]);
16129 rtx (*unpack)(rtx, rtx);
16136 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
16138 unpack = gen_sse4_1_extendv8qiv8hi2;
16142 unpack = gen_sse4_1_zero_extendv4hiv4si2;
16144 unpack = gen_sse4_1_extendv4hiv4si2;
16148 unpack = gen_sse4_1_zero_extendv2siv2di2;
16150 unpack = gen_sse4_1_extendv2siv2di2;
16153 gcc_unreachable ();
16156 dest = operands[0];
16159 /* Shift higher 8 bytes to lower 8 bytes. */
16160 src = gen_reg_rtx (imode);
16161 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
16162 gen_lowpart (TImode, operands[1]),
16168 emit_insn (unpack (dest, src));
16171 /* Expand conditional increment or decrement using adb/sbb instructions.
16172 The default case using setcc followed by the conditional move can be
16173 done by generic code. */
16175 ix86_expand_int_addcc (rtx operands[])
16177 enum rtx_code code = GET_CODE (operands[1]);
16179 rtx val = const0_rtx;
16180 bool fpcmp = false;
16181 enum machine_mode mode = GET_MODE (operands[0]);
16183 ix86_compare_op0 = XEXP (operands[1], 0);
16184 ix86_compare_op1 = XEXP (operands[1], 1);
16185 if (operands[3] != const1_rtx
16186 && operands[3] != constm1_rtx)
16188 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16189 ix86_compare_op1, &compare_op))
16191 code = GET_CODE (compare_op);
16193 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16194 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16197 code = ix86_fp_compare_code_to_integer (code);
16204 PUT_CODE (compare_op,
16205 reverse_condition_maybe_unordered
16206 (GET_CODE (compare_op)));
16208 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16210 PUT_MODE (compare_op, mode);
16212 /* Construct either adc or sbb insn. */
16213 if ((code == LTU) == (operands[3] == constm1_rtx))
16215 switch (GET_MODE (operands[0]))
16218 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
16221 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
16224 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
16227 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16230 gcc_unreachable ();
16235 switch (GET_MODE (operands[0]))
16238 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
16241 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
16244 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
16247 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16250 gcc_unreachable ();
16253 return 1; /* DONE */
16257 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16258 works for floating pointer parameters and nonoffsetable memories.
16259 For pushes, it returns just stack offsets; the values will be saved
16260 in the right order. Maximally three parts are generated. */
16263 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16268 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16270 size = (GET_MODE_SIZE (mode) + 4) / 8;
16272 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16273 gcc_assert (size >= 2 && size <= 4);
16275 /* Optimize constant pool reference to immediates. This is used by fp
16276 moves, that force all constants to memory to allow combining. */
16277 if (MEM_P (operand) && MEM_READONLY_P (operand))
16279 rtx tmp = maybe_get_pool_constant (operand);
16284 if (MEM_P (operand) && !offsettable_memref_p (operand))
16286 /* The only non-offsetable memories we handle are pushes. */
16287 int ok = push_operand (operand, VOIDmode);
16291 operand = copy_rtx (operand);
16292 PUT_MODE (operand, Pmode);
16293 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16297 if (GET_CODE (operand) == CONST_VECTOR)
16299 enum machine_mode imode = int_mode_for_mode (mode);
16300 /* Caution: if we looked through a constant pool memory above,
16301 the operand may actually have a different mode now. That's
16302 ok, since we want to pun this all the way back to an integer. */
16303 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16304 gcc_assert (operand != NULL);
16310 if (mode == DImode)
16311 split_di (&operand, 1, &parts[0], &parts[1]);
16316 if (REG_P (operand))
16318 gcc_assert (reload_completed);
16319 for (i = 0; i < size; i++)
16320 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16322 else if (offsettable_memref_p (operand))
16324 operand = adjust_address (operand, SImode, 0);
16325 parts[0] = operand;
16326 for (i = 1; i < size; i++)
16327 parts[i] = adjust_address (operand, SImode, 4 * i);
16329 else if (GET_CODE (operand) == CONST_DOUBLE)
16334 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16338 real_to_target (l, &r, mode);
16339 parts[3] = gen_int_mode (l[3], SImode);
16340 parts[2] = gen_int_mode (l[2], SImode);
16343 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16344 parts[2] = gen_int_mode (l[2], SImode);
16347 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16350 gcc_unreachable ();
16352 parts[1] = gen_int_mode (l[1], SImode);
16353 parts[0] = gen_int_mode (l[0], SImode);
16356 gcc_unreachable ();
16361 if (mode == TImode)
16362 split_ti (&operand, 1, &parts[0], &parts[1]);
16363 if (mode == XFmode || mode == TFmode)
16365 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16366 if (REG_P (operand))
16368 gcc_assert (reload_completed);
16369 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16370 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16372 else if (offsettable_memref_p (operand))
16374 operand = adjust_address (operand, DImode, 0);
16375 parts[0] = operand;
16376 parts[1] = adjust_address (operand, upper_mode, 8);
16378 else if (GET_CODE (operand) == CONST_DOUBLE)
16383 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16384 real_to_target (l, &r, mode);
16386 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16387 if (HOST_BITS_PER_WIDE_INT >= 64)
16390 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16391 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16394 parts[0] = immed_double_const (l[0], l[1], DImode);
16396 if (upper_mode == SImode)
16397 parts[1] = gen_int_mode (l[2], SImode);
16398 else if (HOST_BITS_PER_WIDE_INT >= 64)
16401 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16402 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16405 parts[1] = immed_double_const (l[2], l[3], DImode);
16408 gcc_unreachable ();
16415 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16416 Return false when normal moves are needed; true when all required
16417 insns have been emitted. Operands 2-4 contain the input values
16418 int the correct order; operands 5-7 contain the output values. */
16421 ix86_split_long_move (rtx operands[])
16426 int collisions = 0;
16427 enum machine_mode mode = GET_MODE (operands[0]);
16428 bool collisionparts[4];
16430 /* The DFmode expanders may ask us to move double.
16431 For 64bit target this is single move. By hiding the fact
16432 here we simplify i386.md splitters. */
16433 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16435 /* Optimize constant pool reference to immediates. This is used by
16436 fp moves, that force all constants to memory to allow combining. */
16438 if (MEM_P (operands[1])
16439 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16440 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16441 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16442 if (push_operand (operands[0], VOIDmode))
16444 operands[0] = copy_rtx (operands[0]);
16445 PUT_MODE (operands[0], Pmode);
16448 operands[0] = gen_lowpart (DImode, operands[0]);
16449 operands[1] = gen_lowpart (DImode, operands[1]);
16450 emit_move_insn (operands[0], operands[1]);
16454 /* The only non-offsettable memory we handle is push. */
16455 if (push_operand (operands[0], VOIDmode))
16458 gcc_assert (!MEM_P (operands[0])
16459 || offsettable_memref_p (operands[0]));
16461 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16462 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16464 /* When emitting push, take care for source operands on the stack. */
16465 if (push && MEM_P (operands[1])
16466 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16468 rtx src_base = XEXP (part[1][nparts - 1], 0);
16470 /* Compensate for the stack decrement by 4. */
16471 if (!TARGET_64BIT && nparts == 3
16472 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
16473 src_base = plus_constant (src_base, 4);
16475 /* src_base refers to the stack pointer and is
16476 automatically decreased by emitted push. */
16477 for (i = 0; i < nparts; i++)
16478 part[1][i] = change_address (part[1][i],
16479 GET_MODE (part[1][i]), src_base);
16482 /* We need to do copy in the right order in case an address register
16483 of the source overlaps the destination. */
16484 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16488 for (i = 0; i < nparts; i++)
16491 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16492 if (collisionparts[i])
16496 /* Collision in the middle part can be handled by reordering. */
16497 if (collisions == 1 && nparts == 3 && collisionparts [1])
16499 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16500 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16502 else if (collisions == 1
16504 && (collisionparts [1] || collisionparts [2]))
16506 if (collisionparts [1])
16508 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16509 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16513 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16514 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16518 /* If there are more collisions, we can't handle it by reordering.
16519 Do an lea to the last part and use only one colliding move. */
16520 else if (collisions > 1)
16526 base = part[0][nparts - 1];
16528 /* Handle the case when the last part isn't valid for lea.
16529 Happens in 64-bit mode storing the 12-byte XFmode. */
16530 if (GET_MODE (base) != Pmode)
16531 base = gen_rtx_REG (Pmode, REGNO (base));
16533 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16534 part[1][0] = replace_equiv_address (part[1][0], base);
16535 for (i = 1; i < nparts; i++)
16537 tmp = plus_constant (base, UNITS_PER_WORD * i);
16538 part[1][i] = replace_equiv_address (part[1][i], tmp);
16549 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16550 emit_insn (gen_addsi3 (stack_pointer_rtx,
16551 stack_pointer_rtx, GEN_INT (-4)));
16552 emit_move_insn (part[0][2], part[1][2]);
16554 else if (nparts == 4)
16556 emit_move_insn (part[0][3], part[1][3]);
16557 emit_move_insn (part[0][2], part[1][2]);
16562 /* In 64bit mode we don't have 32bit push available. In case this is
16563 register, it is OK - we will just use larger counterpart. We also
16564 retype memory - these comes from attempt to avoid REX prefix on
16565 moving of second half of TFmode value. */
16566 if (GET_MODE (part[1][1]) == SImode)
16568 switch (GET_CODE (part[1][1]))
16571 part[1][1] = adjust_address (part[1][1], DImode, 0);
16575 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16579 gcc_unreachable ();
16582 if (GET_MODE (part[1][0]) == SImode)
16583 part[1][0] = part[1][1];
16586 emit_move_insn (part[0][1], part[1][1]);
16587 emit_move_insn (part[0][0], part[1][0]);
16591 /* Choose correct order to not overwrite the source before it is copied. */
16592 if ((REG_P (part[0][0])
16593 && REG_P (part[1][1])
16594 && (REGNO (part[0][0]) == REGNO (part[1][1])
16596 && REGNO (part[0][0]) == REGNO (part[1][2]))
16598 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16600 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16602 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16604 operands[2 + i] = part[0][j];
16605 operands[6 + i] = part[1][j];
16610 for (i = 0; i < nparts; i++)
16612 operands[2 + i] = part[0][i];
16613 operands[6 + i] = part[1][i];
16617 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16618 if (optimize_insn_for_size_p ())
16620 for (j = 0; j < nparts - 1; j++)
16621 if (CONST_INT_P (operands[6 + j])
16622 && operands[6 + j] != const0_rtx
16623 && REG_P (operands[2 + j]))
16624 for (i = j; i < nparts - 1; i++)
16625 if (CONST_INT_P (operands[7 + i])
16626 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16627 operands[7 + i] = operands[2 + j];
16630 for (i = 0; i < nparts; i++)
16631 emit_move_insn (operands[2 + i], operands[6 + i]);
16636 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16637 left shift by a constant, either using a single shift or
16638 a sequence of add instructions. */
16641 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16645 emit_insn ((mode == DImode
16647 : gen_adddi3) (operand, operand, operand));
16649 else if (!optimize_insn_for_size_p ()
16650 && count * ix86_cost->add <= ix86_cost->shift_const)
16653 for (i=0; i<count; i++)
16655 emit_insn ((mode == DImode
16657 : gen_adddi3) (operand, operand, operand));
16661 emit_insn ((mode == DImode
16663 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16667 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16669 rtx low[2], high[2];
16671 const int single_width = mode == DImode ? 32 : 64;
16673 if (CONST_INT_P (operands[2]))
16675 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16676 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16678 if (count >= single_width)
16680 emit_move_insn (high[0], low[1]);
16681 emit_move_insn (low[0], const0_rtx);
16683 if (count > single_width)
16684 ix86_expand_ashl_const (high[0], count - single_width, mode);
16688 if (!rtx_equal_p (operands[0], operands[1]))
16689 emit_move_insn (operands[0], operands[1]);
16690 emit_insn ((mode == DImode
16692 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16693 ix86_expand_ashl_const (low[0], count, mode);
16698 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16700 if (operands[1] == const1_rtx)
16702 /* Assuming we've chosen a QImode capable registers, then 1 << N
16703 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16704 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16706 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16708 ix86_expand_clear (low[0]);
16709 ix86_expand_clear (high[0]);
16710 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16712 d = gen_lowpart (QImode, low[0]);
16713 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16714 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16715 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16717 d = gen_lowpart (QImode, high[0]);
16718 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16719 s = gen_rtx_NE (QImode, flags, const0_rtx);
16720 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16723 /* Otherwise, we can get the same results by manually performing
16724 a bit extract operation on bit 5/6, and then performing the two
16725 shifts. The two methods of getting 0/1 into low/high are exactly
16726 the same size. Avoiding the shift in the bit extract case helps
16727 pentium4 a bit; no one else seems to care much either way. */
16732 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16733 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16735 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16736 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16738 emit_insn ((mode == DImode
16740 : gen_lshrdi3) (high[0], high[0],
16741 GEN_INT (mode == DImode ? 5 : 6)));
16742 emit_insn ((mode == DImode
16744 : gen_anddi3) (high[0], high[0], const1_rtx));
16745 emit_move_insn (low[0], high[0]);
16746 emit_insn ((mode == DImode
16748 : gen_xordi3) (low[0], low[0], const1_rtx));
16751 emit_insn ((mode == DImode
16753 : gen_ashldi3) (low[0], low[0], operands[2]));
16754 emit_insn ((mode == DImode
16756 : gen_ashldi3) (high[0], high[0], operands[2]));
16760 if (operands[1] == constm1_rtx)
16762 /* For -1 << N, we can avoid the shld instruction, because we
16763 know that we're shifting 0...31/63 ones into a -1. */
16764 emit_move_insn (low[0], constm1_rtx);
16765 if (optimize_insn_for_size_p ())
16766 emit_move_insn (high[0], low[0]);
16768 emit_move_insn (high[0], constm1_rtx);
16772 if (!rtx_equal_p (operands[0], operands[1]))
16773 emit_move_insn (operands[0], operands[1]);
16775 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16776 emit_insn ((mode == DImode
16778 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16781 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16783 if (TARGET_CMOVE && scratch)
16785 ix86_expand_clear (scratch);
16786 emit_insn ((mode == DImode
16787 ? gen_x86_shift_adj_1
16788 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16792 emit_insn ((mode == DImode
16793 ? gen_x86_shift_adj_2
16794 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16798 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16800 rtx low[2], high[2];
16802 const int single_width = mode == DImode ? 32 : 64;
16804 if (CONST_INT_P (operands[2]))
16806 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16807 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16809 if (count == single_width * 2 - 1)
16811 emit_move_insn (high[0], high[1]);
16812 emit_insn ((mode == DImode
16814 : gen_ashrdi3) (high[0], high[0],
16815 GEN_INT (single_width - 1)));
16816 emit_move_insn (low[0], high[0]);
16819 else if (count >= single_width)
16821 emit_move_insn (low[0], high[1]);
16822 emit_move_insn (high[0], low[0]);
16823 emit_insn ((mode == DImode
16825 : gen_ashrdi3) (high[0], high[0],
16826 GEN_INT (single_width - 1)));
16827 if (count > single_width)
16828 emit_insn ((mode == DImode
16830 : gen_ashrdi3) (low[0], low[0],
16831 GEN_INT (count - single_width)));
16835 if (!rtx_equal_p (operands[0], operands[1]))
16836 emit_move_insn (operands[0], operands[1]);
16837 emit_insn ((mode == DImode
16839 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16840 emit_insn ((mode == DImode
16842 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16847 if (!rtx_equal_p (operands[0], operands[1]))
16848 emit_move_insn (operands[0], operands[1]);
16850 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16852 emit_insn ((mode == DImode
16854 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16855 emit_insn ((mode == DImode
16857 : gen_ashrdi3) (high[0], high[0], operands[2]));
16859 if (TARGET_CMOVE && scratch)
16861 emit_move_insn (scratch, high[0]);
16862 emit_insn ((mode == DImode
16864 : gen_ashrdi3) (scratch, scratch,
16865 GEN_INT (single_width - 1)));
16866 emit_insn ((mode == DImode
16867 ? gen_x86_shift_adj_1
16868 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16872 emit_insn ((mode == DImode
16873 ? gen_x86_shift_adj_3
16874 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16879 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16881 rtx low[2], high[2];
16883 const int single_width = mode == DImode ? 32 : 64;
16885 if (CONST_INT_P (operands[2]))
16887 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16888 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16890 if (count >= single_width)
16892 emit_move_insn (low[0], high[1]);
16893 ix86_expand_clear (high[0]);
16895 if (count > single_width)
16896 emit_insn ((mode == DImode
16898 : gen_lshrdi3) (low[0], low[0],
16899 GEN_INT (count - single_width)));
16903 if (!rtx_equal_p (operands[0], operands[1]))
16904 emit_move_insn (operands[0], operands[1]);
16905 emit_insn ((mode == DImode
16907 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16908 emit_insn ((mode == DImode
16910 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16915 if (!rtx_equal_p (operands[0], operands[1]))
16916 emit_move_insn (operands[0], operands[1]);
16918 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16920 emit_insn ((mode == DImode
16922 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16923 emit_insn ((mode == DImode
16925 : gen_lshrdi3) (high[0], high[0], operands[2]));
16927 /* Heh. By reversing the arguments, we can reuse this pattern. */
16928 if (TARGET_CMOVE && scratch)
16930 ix86_expand_clear (scratch);
16931 emit_insn ((mode == DImode
16932 ? gen_x86_shift_adj_1
16933 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16937 emit_insn ((mode == DImode
16938 ? gen_x86_shift_adj_2
16939 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16943 /* Predict just emitted jump instruction to be taken with probability PROB. */
16945 predict_jump (int prob)
16947 rtx insn = get_last_insn ();
16948 gcc_assert (JUMP_P (insn));
16949 add_reg_note (insn, REG_BR_PROB, GEN_INT (prob));
16952 /* Helper function for the string operations below. Dest VARIABLE whether
16953 it is aligned to VALUE bytes. If true, jump to the label. */
16955 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16957 rtx label = gen_label_rtx ();
16958 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16959 if (GET_MODE (variable) == DImode)
16960 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16962 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16963 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16966 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16968 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16972 /* Adjust COUNTER by the VALUE. */
16974 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16976 if (GET_MODE (countreg) == DImode)
16977 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16979 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16982 /* Zero extend possibly SImode EXP to Pmode register. */
16984 ix86_zero_extend_to_Pmode (rtx exp)
16987 if (GET_MODE (exp) == VOIDmode)
16988 return force_reg (Pmode, exp);
16989 if (GET_MODE (exp) == Pmode)
16990 return copy_to_mode_reg (Pmode, exp);
16991 r = gen_reg_rtx (Pmode);
16992 emit_insn (gen_zero_extendsidi2 (r, exp));
16996 /* Divide COUNTREG by SCALE. */
16998 scale_counter (rtx countreg, int scale)
17001 rtx piece_size_mask;
17005 if (CONST_INT_P (countreg))
17006 return GEN_INT (INTVAL (countreg) / scale);
17007 gcc_assert (REG_P (countreg));
17009 piece_size_mask = GEN_INT (scale - 1);
17010 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
17011 GEN_INT (exact_log2 (scale)),
17012 NULL, 1, OPTAB_DIRECT);
17016 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
17017 DImode for constant loop counts. */
17019 static enum machine_mode
17020 counter_mode (rtx count_exp)
17022 if (GET_MODE (count_exp) != VOIDmode)
17023 return GET_MODE (count_exp);
17024 if (!CONST_INT_P (count_exp))
17026 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
17031 /* When SRCPTR is non-NULL, output simple loop to move memory
17032 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
17033 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
17034 equivalent loop to set memory by VALUE (supposed to be in MODE).
17036 The size is rounded down to whole number of chunk size moved at once.
17037 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
17041 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
17042 rtx destptr, rtx srcptr, rtx value,
17043 rtx count, enum machine_mode mode, int unroll,
17046 rtx out_label, top_label, iter, tmp;
17047 enum machine_mode iter_mode = counter_mode (count);
17048 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
17049 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
17055 top_label = gen_label_rtx ();
17056 out_label = gen_label_rtx ();
17057 iter = gen_reg_rtx (iter_mode);
17059 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
17060 NULL, 1, OPTAB_DIRECT);
17061 /* Those two should combine. */
17062 if (piece_size == const1_rtx)
17064 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
17066 predict_jump (REG_BR_PROB_BASE * 10 / 100);
17068 emit_move_insn (iter, const0_rtx);
17070 emit_label (top_label);
17072 tmp = convert_modes (Pmode, iter_mode, iter, true);
17073 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
17074 destmem = change_address (destmem, mode, x_addr);
17078 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
17079 srcmem = change_address (srcmem, mode, y_addr);
17081 /* When unrolling for chips that reorder memory reads and writes,
17082 we can save registers by using single temporary.
17083 Also using 4 temporaries is overkill in 32bit mode. */
17084 if (!TARGET_64BIT && 0)
17086 for (i = 0; i < unroll; i++)
17091 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17093 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17095 emit_move_insn (destmem, srcmem);
17101 gcc_assert (unroll <= 4);
17102 for (i = 0; i < unroll; i++)
17104 tmpreg[i] = gen_reg_rtx (mode);
17108 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
17110 emit_move_insn (tmpreg[i], srcmem);
17112 for (i = 0; i < unroll; i++)
17117 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17119 emit_move_insn (destmem, tmpreg[i]);
17124 for (i = 0; i < unroll; i++)
17128 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
17129 emit_move_insn (destmem, value);
17132 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
17133 true, OPTAB_LIB_WIDEN);
17135 emit_move_insn (iter, tmp);
17137 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
17139 if (expected_size != -1)
17141 expected_size /= GET_MODE_SIZE (mode) * unroll;
17142 if (expected_size == 0)
17144 else if (expected_size > REG_BR_PROB_BASE)
17145 predict_jump (REG_BR_PROB_BASE - 1);
17147 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
17150 predict_jump (REG_BR_PROB_BASE * 80 / 100);
17151 iter = ix86_zero_extend_to_Pmode (iter);
17152 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
17153 true, OPTAB_LIB_WIDEN);
17154 if (tmp != destptr)
17155 emit_move_insn (destptr, tmp);
17158 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
17159 true, OPTAB_LIB_WIDEN);
17161 emit_move_insn (srcptr, tmp);
17163 emit_label (out_label);
17166 /* Output "rep; mov" instruction.
17167 Arguments have same meaning as for previous function */
17169 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17170 rtx destptr, rtx srcptr,
17172 enum machine_mode mode)
17178 /* If the size is known, it is shorter to use rep movs. */
17179 if (mode == QImode && CONST_INT_P (count)
17180 && !(INTVAL (count) & 3))
17183 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17184 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17185 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17186 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17187 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17188 if (mode != QImode)
17190 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17191 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17192 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17193 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17194 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17195 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17199 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17200 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17202 if (CONST_INT_P (count))
17204 count = GEN_INT (INTVAL (count)
17205 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17206 destmem = shallow_copy_rtx (destmem);
17207 srcmem = shallow_copy_rtx (srcmem);
17208 set_mem_size (destmem, count);
17209 set_mem_size (srcmem, count);
17213 if (MEM_SIZE (destmem))
17214 set_mem_size (destmem, NULL_RTX);
17215 if (MEM_SIZE (srcmem))
17216 set_mem_size (srcmem, NULL_RTX);
17218 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17222 /* Output "rep; stos" instruction.
17223 Arguments have same meaning as for previous function */
17225 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17226 rtx count, enum machine_mode mode,
17232 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17233 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17234 value = force_reg (mode, gen_lowpart (mode, value));
17235 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17236 if (mode != QImode)
17238 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17239 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17240 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17243 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17244 if (orig_value == const0_rtx && CONST_INT_P (count))
17246 count = GEN_INT (INTVAL (count)
17247 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17248 destmem = shallow_copy_rtx (destmem);
17249 set_mem_size (destmem, count);
17251 else if (MEM_SIZE (destmem))
17252 set_mem_size (destmem, NULL_RTX);
17253 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17257 emit_strmov (rtx destmem, rtx srcmem,
17258 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17260 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17261 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17262 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17265 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17267 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17268 rtx destptr, rtx srcptr, rtx count, int max_size)
17271 if (CONST_INT_P (count))
17273 HOST_WIDE_INT countval = INTVAL (count);
17276 if ((countval & 0x10) && max_size > 16)
17280 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17281 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17284 gcc_unreachable ();
17287 if ((countval & 0x08) && max_size > 8)
17290 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17293 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17294 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17298 if ((countval & 0x04) && max_size > 4)
17300 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17303 if ((countval & 0x02) && max_size > 2)
17305 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17308 if ((countval & 0x01) && max_size > 1)
17310 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17317 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17318 count, 1, OPTAB_DIRECT);
17319 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17320 count, QImode, 1, 4);
17324 /* When there are stringops, we can cheaply increase dest and src pointers.
17325 Otherwise we save code size by maintaining offset (zero is readily
17326 available from preceding rep operation) and using x86 addressing modes.
17328 if (TARGET_SINGLE_STRINGOP)
17332 rtx label = ix86_expand_aligntest (count, 4, true);
17333 src = change_address (srcmem, SImode, srcptr);
17334 dest = change_address (destmem, SImode, destptr);
17335 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17336 emit_label (label);
17337 LABEL_NUSES (label) = 1;
17341 rtx label = ix86_expand_aligntest (count, 2, true);
17342 src = change_address (srcmem, HImode, srcptr);
17343 dest = change_address (destmem, HImode, destptr);
17344 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17345 emit_label (label);
17346 LABEL_NUSES (label) = 1;
17350 rtx label = ix86_expand_aligntest (count, 1, true);
17351 src = change_address (srcmem, QImode, srcptr);
17352 dest = change_address (destmem, QImode, destptr);
17353 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17354 emit_label (label);
17355 LABEL_NUSES (label) = 1;
17360 rtx offset = force_reg (Pmode, const0_rtx);
17365 rtx label = ix86_expand_aligntest (count, 4, true);
17366 src = change_address (srcmem, SImode, srcptr);
17367 dest = change_address (destmem, SImode, destptr);
17368 emit_move_insn (dest, src);
17369 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17370 true, OPTAB_LIB_WIDEN);
17372 emit_move_insn (offset, tmp);
17373 emit_label (label);
17374 LABEL_NUSES (label) = 1;
17378 rtx label = ix86_expand_aligntest (count, 2, true);
17379 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17380 src = change_address (srcmem, HImode, tmp);
17381 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17382 dest = change_address (destmem, HImode, tmp);
17383 emit_move_insn (dest, src);
17384 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17385 true, OPTAB_LIB_WIDEN);
17387 emit_move_insn (offset, tmp);
17388 emit_label (label);
17389 LABEL_NUSES (label) = 1;
17393 rtx label = ix86_expand_aligntest (count, 1, true);
17394 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17395 src = change_address (srcmem, QImode, tmp);
17396 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17397 dest = change_address (destmem, QImode, tmp);
17398 emit_move_insn (dest, src);
17399 emit_label (label);
17400 LABEL_NUSES (label) = 1;
17405 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17407 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17408 rtx count, int max_size)
17411 expand_simple_binop (counter_mode (count), AND, count,
17412 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17413 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17414 gen_lowpart (QImode, value), count, QImode,
17418 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17420 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17424 if (CONST_INT_P (count))
17426 HOST_WIDE_INT countval = INTVAL (count);
17429 if ((countval & 0x10) && max_size > 16)
17433 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17434 emit_insn (gen_strset (destptr, dest, value));
17435 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17436 emit_insn (gen_strset (destptr, dest, value));
17439 gcc_unreachable ();
17442 if ((countval & 0x08) && max_size > 8)
17446 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17447 emit_insn (gen_strset (destptr, dest, value));
17451 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17452 emit_insn (gen_strset (destptr, dest, value));
17453 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17454 emit_insn (gen_strset (destptr, dest, value));
17458 if ((countval & 0x04) && max_size > 4)
17460 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17461 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17464 if ((countval & 0x02) && max_size > 2)
17466 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17467 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17470 if ((countval & 0x01) && max_size > 1)
17472 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17473 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17480 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17485 rtx label = ix86_expand_aligntest (count, 16, true);
17488 dest = change_address (destmem, DImode, destptr);
17489 emit_insn (gen_strset (destptr, dest, value));
17490 emit_insn (gen_strset (destptr, dest, value));
17494 dest = change_address (destmem, SImode, destptr);
17495 emit_insn (gen_strset (destptr, dest, value));
17496 emit_insn (gen_strset (destptr, dest, value));
17497 emit_insn (gen_strset (destptr, dest, value));
17498 emit_insn (gen_strset (destptr, dest, value));
17500 emit_label (label);
17501 LABEL_NUSES (label) = 1;
17505 rtx label = ix86_expand_aligntest (count, 8, true);
17508 dest = change_address (destmem, DImode, destptr);
17509 emit_insn (gen_strset (destptr, dest, value));
17513 dest = change_address (destmem, SImode, destptr);
17514 emit_insn (gen_strset (destptr, dest, value));
17515 emit_insn (gen_strset (destptr, dest, value));
17517 emit_label (label);
17518 LABEL_NUSES (label) = 1;
17522 rtx label = ix86_expand_aligntest (count, 4, true);
17523 dest = change_address (destmem, SImode, destptr);
17524 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17525 emit_label (label);
17526 LABEL_NUSES (label) = 1;
17530 rtx label = ix86_expand_aligntest (count, 2, true);
17531 dest = change_address (destmem, HImode, destptr);
17532 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17533 emit_label (label);
17534 LABEL_NUSES (label) = 1;
17538 rtx label = ix86_expand_aligntest (count, 1, true);
17539 dest = change_address (destmem, QImode, destptr);
17540 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17541 emit_label (label);
17542 LABEL_NUSES (label) = 1;
17546 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17547 DESIRED_ALIGNMENT. */
17549 expand_movmem_prologue (rtx destmem, rtx srcmem,
17550 rtx destptr, rtx srcptr, rtx count,
17551 int align, int desired_alignment)
17553 if (align <= 1 && desired_alignment > 1)
17555 rtx label = ix86_expand_aligntest (destptr, 1, false);
17556 srcmem = change_address (srcmem, QImode, srcptr);
17557 destmem = change_address (destmem, QImode, destptr);
17558 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17559 ix86_adjust_counter (count, 1);
17560 emit_label (label);
17561 LABEL_NUSES (label) = 1;
17563 if (align <= 2 && desired_alignment > 2)
17565 rtx label = ix86_expand_aligntest (destptr, 2, false);
17566 srcmem = change_address (srcmem, HImode, srcptr);
17567 destmem = change_address (destmem, HImode, destptr);
17568 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17569 ix86_adjust_counter (count, 2);
17570 emit_label (label);
17571 LABEL_NUSES (label) = 1;
17573 if (align <= 4 && desired_alignment > 4)
17575 rtx label = ix86_expand_aligntest (destptr, 4, false);
17576 srcmem = change_address (srcmem, SImode, srcptr);
17577 destmem = change_address (destmem, SImode, destptr);
17578 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17579 ix86_adjust_counter (count, 4);
17580 emit_label (label);
17581 LABEL_NUSES (label) = 1;
17583 gcc_assert (desired_alignment <= 8);
17586 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17587 ALIGN_BYTES is how many bytes need to be copied. */
17589 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17590 int desired_align, int align_bytes)
17593 rtx src_size, dst_size;
17595 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17596 if (src_align_bytes >= 0)
17597 src_align_bytes = desired_align - src_align_bytes;
17598 src_size = MEM_SIZE (src);
17599 dst_size = MEM_SIZE (dst);
17600 if (align_bytes & 1)
17602 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17603 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17605 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17607 if (align_bytes & 2)
17609 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17610 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17611 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17612 set_mem_align (dst, 2 * BITS_PER_UNIT);
17613 if (src_align_bytes >= 0
17614 && (src_align_bytes & 1) == (align_bytes & 1)
17615 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17616 set_mem_align (src, 2 * BITS_PER_UNIT);
17618 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17620 if (align_bytes & 4)
17622 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17623 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17624 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17625 set_mem_align (dst, 4 * BITS_PER_UNIT);
17626 if (src_align_bytes >= 0)
17628 unsigned int src_align = 0;
17629 if ((src_align_bytes & 3) == (align_bytes & 3))
17631 else if ((src_align_bytes & 1) == (align_bytes & 1))
17633 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17634 set_mem_align (src, src_align * BITS_PER_UNIT);
17637 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17639 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17640 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17641 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17642 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17643 if (src_align_bytes >= 0)
17645 unsigned int src_align = 0;
17646 if ((src_align_bytes & 7) == (align_bytes & 7))
17648 else if ((src_align_bytes & 3) == (align_bytes & 3))
17650 else if ((src_align_bytes & 1) == (align_bytes & 1))
17652 if (src_align > (unsigned int) desired_align)
17653 src_align = desired_align;
17654 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17655 set_mem_align (src, src_align * BITS_PER_UNIT);
17658 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17660 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17665 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17666 DESIRED_ALIGNMENT. */
17668 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17669 int align, int desired_alignment)
17671 if (align <= 1 && desired_alignment > 1)
17673 rtx label = ix86_expand_aligntest (destptr, 1, false);
17674 destmem = change_address (destmem, QImode, destptr);
17675 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17676 ix86_adjust_counter (count, 1);
17677 emit_label (label);
17678 LABEL_NUSES (label) = 1;
17680 if (align <= 2 && desired_alignment > 2)
17682 rtx label = ix86_expand_aligntest (destptr, 2, false);
17683 destmem = change_address (destmem, HImode, destptr);
17684 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17685 ix86_adjust_counter (count, 2);
17686 emit_label (label);
17687 LABEL_NUSES (label) = 1;
17689 if (align <= 4 && desired_alignment > 4)
17691 rtx label = ix86_expand_aligntest (destptr, 4, false);
17692 destmem = change_address (destmem, SImode, destptr);
17693 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17694 ix86_adjust_counter (count, 4);
17695 emit_label (label);
17696 LABEL_NUSES (label) = 1;
17698 gcc_assert (desired_alignment <= 8);
17701 /* Set enough from DST to align DST known to by aligned by ALIGN to
17702 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17704 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17705 int desired_align, int align_bytes)
17708 rtx dst_size = MEM_SIZE (dst);
17709 if (align_bytes & 1)
17711 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17713 emit_insn (gen_strset (destreg, dst,
17714 gen_lowpart (QImode, value)));
17716 if (align_bytes & 2)
17718 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17719 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17720 set_mem_align (dst, 2 * BITS_PER_UNIT);
17722 emit_insn (gen_strset (destreg, dst,
17723 gen_lowpart (HImode, value)));
17725 if (align_bytes & 4)
17727 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17728 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17729 set_mem_align (dst, 4 * BITS_PER_UNIT);
17731 emit_insn (gen_strset (destreg, dst,
17732 gen_lowpart (SImode, value)));
17734 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17735 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17736 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17738 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17742 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17743 static enum stringop_alg
17744 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17745 int *dynamic_check)
17747 const struct stringop_algs * algs;
17748 bool optimize_for_speed;
17749 /* Algorithms using the rep prefix want at least edi and ecx;
17750 additionally, memset wants eax and memcpy wants esi. Don't
17751 consider such algorithms if the user has appropriated those
17752 registers for their own purposes. */
17753 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17755 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17757 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17758 || (alg != rep_prefix_1_byte \
17759 && alg != rep_prefix_4_byte \
17760 && alg != rep_prefix_8_byte))
17761 const struct processor_costs *cost;
17763 /* Even if the string operation call is cold, we still might spend a lot
17764 of time processing large blocks. */
17765 if (optimize_function_for_size_p (cfun)
17766 || (optimize_insn_for_size_p ()
17767 && expected_size != -1 && expected_size < 256))
17768 optimize_for_speed = false;
17770 optimize_for_speed = true;
17772 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17774 *dynamic_check = -1;
17776 algs = &cost->memset[TARGET_64BIT != 0];
17778 algs = &cost->memcpy[TARGET_64BIT != 0];
17779 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17780 return stringop_alg;
17781 /* rep; movq or rep; movl is the smallest variant. */
17782 else if (!optimize_for_speed)
17784 if (!count || (count & 3))
17785 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17787 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17789 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17791 else if (expected_size != -1 && expected_size < 4)
17792 return loop_1_byte;
17793 else if (expected_size != -1)
17796 enum stringop_alg alg = libcall;
17797 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17799 /* We get here if the algorithms that were not libcall-based
17800 were rep-prefix based and we are unable to use rep prefixes
17801 based on global register usage. Break out of the loop and
17802 use the heuristic below. */
17803 if (algs->size[i].max == 0)
17805 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17807 enum stringop_alg candidate = algs->size[i].alg;
17809 if (candidate != libcall && ALG_USABLE_P (candidate))
17811 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17812 last non-libcall inline algorithm. */
17813 if (TARGET_INLINE_ALL_STRINGOPS)
17815 /* When the current size is best to be copied by a libcall,
17816 but we are still forced to inline, run the heuristic below
17817 that will pick code for medium sized blocks. */
17818 if (alg != libcall)
17822 else if (ALG_USABLE_P (candidate))
17826 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17828 /* When asked to inline the call anyway, try to pick meaningful choice.
17829 We look for maximal size of block that is faster to copy by hand and
17830 take blocks of at most of that size guessing that average size will
17831 be roughly half of the block.
17833 If this turns out to be bad, we might simply specify the preferred
17834 choice in ix86_costs. */
17835 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17836 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17839 enum stringop_alg alg;
17841 bool any_alg_usable_p = true;
17843 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17845 enum stringop_alg candidate = algs->size[i].alg;
17846 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17848 if (candidate != libcall && candidate
17849 && ALG_USABLE_P (candidate))
17850 max = algs->size[i].max;
17852 /* If there aren't any usable algorithms, then recursing on
17853 smaller sizes isn't going to find anything. Just return the
17854 simple byte-at-a-time copy loop. */
17855 if (!any_alg_usable_p)
17857 /* Pick something reasonable. */
17858 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17859 *dynamic_check = 128;
17860 return loop_1_byte;
17864 alg = decide_alg (count, max / 2, memset, dynamic_check);
17865 gcc_assert (*dynamic_check == -1);
17866 gcc_assert (alg != libcall);
17867 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17868 *dynamic_check = max;
17871 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17872 #undef ALG_USABLE_P
17875 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17876 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17878 decide_alignment (int align,
17879 enum stringop_alg alg,
17882 int desired_align = 0;
17886 gcc_unreachable ();
17888 case unrolled_loop:
17889 desired_align = GET_MODE_SIZE (Pmode);
17891 case rep_prefix_8_byte:
17894 case rep_prefix_4_byte:
17895 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17896 copying whole cacheline at once. */
17897 if (TARGET_PENTIUMPRO)
17902 case rep_prefix_1_byte:
17903 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17904 copying whole cacheline at once. */
17905 if (TARGET_PENTIUMPRO)
17919 if (desired_align < align)
17920 desired_align = align;
17921 if (expected_size != -1 && expected_size < 4)
17922 desired_align = align;
17923 return desired_align;
17926 /* Return the smallest power of 2 greater than VAL. */
17928 smallest_pow2_greater_than (int val)
17936 /* Expand string move (memcpy) operation. Use i386 string operations when
17937 profitable. expand_setmem contains similar code. The code depends upon
17938 architecture, block size and alignment, but always has the same
17941 1) Prologue guard: Conditional that jumps up to epilogues for small
17942 blocks that can be handled by epilogue alone. This is faster but
17943 also needed for correctness, since prologue assume the block is larger
17944 than the desired alignment.
17946 Optional dynamic check for size and libcall for large
17947 blocks is emitted here too, with -minline-stringops-dynamically.
17949 2) Prologue: copy first few bytes in order to get destination aligned
17950 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17951 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17952 We emit either a jump tree on power of two sized blocks, or a byte loop.
17954 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17955 with specified algorithm.
17957 4) Epilogue: code copying tail of the block that is too small to be
17958 handled by main body (or up to size guarded by prologue guard). */
17961 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17962 rtx expected_align_exp, rtx expected_size_exp)
17968 rtx jump_around_label = NULL;
17969 HOST_WIDE_INT align = 1;
17970 unsigned HOST_WIDE_INT count = 0;
17971 HOST_WIDE_INT expected_size = -1;
17972 int size_needed = 0, epilogue_size_needed;
17973 int desired_align = 0, align_bytes = 0;
17974 enum stringop_alg alg;
17976 bool need_zero_guard = false;
17978 if (CONST_INT_P (align_exp))
17979 align = INTVAL (align_exp);
17980 /* i386 can do misaligned access on reasonably increased cost. */
17981 if (CONST_INT_P (expected_align_exp)
17982 && INTVAL (expected_align_exp) > align)
17983 align = INTVAL (expected_align_exp);
17984 /* ALIGN is the minimum of destination and source alignment, but we care here
17985 just about destination alignment. */
17986 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17987 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17989 if (CONST_INT_P (count_exp))
17990 count = expected_size = INTVAL (count_exp);
17991 if (CONST_INT_P (expected_size_exp) && count == 0)
17992 expected_size = INTVAL (expected_size_exp);
17994 /* Make sure we don't need to care about overflow later on. */
17995 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17998 /* Step 0: Decide on preferred algorithm, desired alignment and
17999 size of chunks to be copied by main loop. */
18001 alg = decide_alg (count, expected_size, false, &dynamic_check);
18002 desired_align = decide_alignment (align, alg, expected_size);
18004 if (!TARGET_ALIGN_STRINGOPS)
18005 align = desired_align;
18007 if (alg == libcall)
18009 gcc_assert (alg != no_stringop);
18011 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
18012 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18013 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
18018 gcc_unreachable ();
18020 need_zero_guard = true;
18021 size_needed = GET_MODE_SIZE (Pmode);
18023 case unrolled_loop:
18024 need_zero_guard = true;
18025 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
18027 case rep_prefix_8_byte:
18030 case rep_prefix_4_byte:
18033 case rep_prefix_1_byte:
18037 need_zero_guard = true;
18042 epilogue_size_needed = size_needed;
18044 /* Step 1: Prologue guard. */
18046 /* Alignment code needs count to be in register. */
18047 if (CONST_INT_P (count_exp) && desired_align > align)
18049 if (INTVAL (count_exp) > desired_align
18050 && INTVAL (count_exp) > size_needed)
18053 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18054 if (align_bytes <= 0)
18057 align_bytes = desired_align - align_bytes;
18059 if (align_bytes == 0)
18060 count_exp = force_reg (counter_mode (count_exp), count_exp);
18062 gcc_assert (desired_align >= 1 && align >= 1);
18064 /* Ensure that alignment prologue won't copy past end of block. */
18065 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18067 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18068 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
18069 Make sure it is power of 2. */
18070 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18074 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18076 /* If main algorithm works on QImode, no epilogue is needed.
18077 For small sizes just don't align anything. */
18078 if (size_needed == 1)
18079 desired_align = align;
18086 label = gen_label_rtx ();
18087 emit_cmp_and_jump_insns (count_exp,
18088 GEN_INT (epilogue_size_needed),
18089 LTU, 0, counter_mode (count_exp), 1, label);
18090 if (expected_size == -1 || expected_size < epilogue_size_needed)
18091 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18093 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18097 /* Emit code to decide on runtime whether library call or inline should be
18099 if (dynamic_check != -1)
18101 if (CONST_INT_P (count_exp))
18103 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
18105 emit_block_move_via_libcall (dst, src, count_exp, false);
18106 count_exp = const0_rtx;
18112 rtx hot_label = gen_label_rtx ();
18113 jump_around_label = gen_label_rtx ();
18114 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18115 LEU, 0, GET_MODE (count_exp), 1, hot_label);
18116 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18117 emit_block_move_via_libcall (dst, src, count_exp, false);
18118 emit_jump (jump_around_label);
18119 emit_label (hot_label);
18123 /* Step 2: Alignment prologue. */
18125 if (desired_align > align)
18127 if (align_bytes == 0)
18129 /* Except for the first move in epilogue, we no longer know
18130 constant offset in aliasing info. It don't seems to worth
18131 the pain to maintain it for the first move, so throw away
18133 src = change_address (src, BLKmode, srcreg);
18134 dst = change_address (dst, BLKmode, destreg);
18135 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
18140 /* If we know how many bytes need to be stored before dst is
18141 sufficiently aligned, maintain aliasing info accurately. */
18142 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
18143 desired_align, align_bytes);
18144 count_exp = plus_constant (count_exp, -align_bytes);
18145 count -= align_bytes;
18147 if (need_zero_guard
18148 && (count < (unsigned HOST_WIDE_INT) size_needed
18149 || (align_bytes == 0
18150 && count < ((unsigned HOST_WIDE_INT) size_needed
18151 + desired_align - align))))
18153 /* It is possible that we copied enough so the main loop will not
18155 gcc_assert (size_needed > 1);
18156 if (label == NULL_RTX)
18157 label = gen_label_rtx ();
18158 emit_cmp_and_jump_insns (count_exp,
18159 GEN_INT (size_needed),
18160 LTU, 0, counter_mode (count_exp), 1, label);
18161 if (expected_size == -1
18162 || expected_size < (desired_align - align) / 2 + size_needed)
18163 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18165 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18168 if (label && size_needed == 1)
18170 emit_label (label);
18171 LABEL_NUSES (label) = 1;
18173 epilogue_size_needed = 1;
18175 else if (label == NULL_RTX)
18176 epilogue_size_needed = size_needed;
18178 /* Step 3: Main loop. */
18184 gcc_unreachable ();
18186 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18187 count_exp, QImode, 1, expected_size);
18190 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18191 count_exp, Pmode, 1, expected_size);
18193 case unrolled_loop:
18194 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18195 registers for 4 temporaries anyway. */
18196 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18197 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18200 case rep_prefix_8_byte:
18201 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18204 case rep_prefix_4_byte:
18205 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18208 case rep_prefix_1_byte:
18209 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18213 /* Adjust properly the offset of src and dest memory for aliasing. */
18214 if (CONST_INT_P (count_exp))
18216 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18217 (count / size_needed) * size_needed);
18218 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18219 (count / size_needed) * size_needed);
18223 src = change_address (src, BLKmode, srcreg);
18224 dst = change_address (dst, BLKmode, destreg);
18227 /* Step 4: Epilogue to copy the remaining bytes. */
18231 /* When the main loop is done, COUNT_EXP might hold original count,
18232 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18233 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18234 bytes. Compensate if needed. */
18236 if (size_needed < epilogue_size_needed)
18239 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18240 GEN_INT (size_needed - 1), count_exp, 1,
18242 if (tmp != count_exp)
18243 emit_move_insn (count_exp, tmp);
18245 emit_label (label);
18246 LABEL_NUSES (label) = 1;
18249 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18250 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18251 epilogue_size_needed);
18252 if (jump_around_label)
18253 emit_label (jump_around_label);
18257 /* Helper function for memcpy. For QImode value 0xXY produce
18258 0xXYXYXYXY of wide specified by MODE. This is essentially
18259 a * 0x10101010, but we can do slightly better than
18260 synth_mult by unwinding the sequence by hand on CPUs with
18263 promote_duplicated_reg (enum machine_mode mode, rtx val)
18265 enum machine_mode valmode = GET_MODE (val);
18267 int nops = mode == DImode ? 3 : 2;
18269 gcc_assert (mode == SImode || mode == DImode);
18270 if (val == const0_rtx)
18271 return copy_to_mode_reg (mode, const0_rtx);
18272 if (CONST_INT_P (val))
18274 HOST_WIDE_INT v = INTVAL (val) & 255;
18278 if (mode == DImode)
18279 v |= (v << 16) << 16;
18280 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18283 if (valmode == VOIDmode)
18285 if (valmode != QImode)
18286 val = gen_lowpart (QImode, val);
18287 if (mode == QImode)
18289 if (!TARGET_PARTIAL_REG_STALL)
18291 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18292 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18293 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18294 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18296 rtx reg = convert_modes (mode, QImode, val, true);
18297 tmp = promote_duplicated_reg (mode, const1_rtx);
18298 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18303 rtx reg = convert_modes (mode, QImode, val, true);
18305 if (!TARGET_PARTIAL_REG_STALL)
18306 if (mode == SImode)
18307 emit_insn (gen_movsi_insv_1 (reg, reg));
18309 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18312 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18313 NULL, 1, OPTAB_DIRECT);
18315 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18317 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18318 NULL, 1, OPTAB_DIRECT);
18319 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18320 if (mode == SImode)
18322 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18323 NULL, 1, OPTAB_DIRECT);
18324 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18329 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18330 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18331 alignment from ALIGN to DESIRED_ALIGN. */
18333 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18338 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18339 promoted_val = promote_duplicated_reg (DImode, val);
18340 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18341 promoted_val = promote_duplicated_reg (SImode, val);
18342 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18343 promoted_val = promote_duplicated_reg (HImode, val);
18345 promoted_val = val;
18347 return promoted_val;
18350 /* Expand string clear operation (bzero). Use i386 string operations when
18351 profitable. See expand_movmem comment for explanation of individual
18352 steps performed. */
18354 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18355 rtx expected_align_exp, rtx expected_size_exp)
18360 rtx jump_around_label = NULL;
18361 HOST_WIDE_INT align = 1;
18362 unsigned HOST_WIDE_INT count = 0;
18363 HOST_WIDE_INT expected_size = -1;
18364 int size_needed = 0, epilogue_size_needed;
18365 int desired_align = 0, align_bytes = 0;
18366 enum stringop_alg alg;
18367 rtx promoted_val = NULL;
18368 bool force_loopy_epilogue = false;
18370 bool need_zero_guard = false;
18372 if (CONST_INT_P (align_exp))
18373 align = INTVAL (align_exp);
18374 /* i386 can do misaligned access on reasonably increased cost. */
18375 if (CONST_INT_P (expected_align_exp)
18376 && INTVAL (expected_align_exp) > align)
18377 align = INTVAL (expected_align_exp);
18378 if (CONST_INT_P (count_exp))
18379 count = expected_size = INTVAL (count_exp);
18380 if (CONST_INT_P (expected_size_exp) && count == 0)
18381 expected_size = INTVAL (expected_size_exp);
18383 /* Make sure we don't need to care about overflow later on. */
18384 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18387 /* Step 0: Decide on preferred algorithm, desired alignment and
18388 size of chunks to be copied by main loop. */
18390 alg = decide_alg (count, expected_size, true, &dynamic_check);
18391 desired_align = decide_alignment (align, alg, expected_size);
18393 if (!TARGET_ALIGN_STRINGOPS)
18394 align = desired_align;
18396 if (alg == libcall)
18398 gcc_assert (alg != no_stringop);
18400 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18401 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18406 gcc_unreachable ();
18408 need_zero_guard = true;
18409 size_needed = GET_MODE_SIZE (Pmode);
18411 case unrolled_loop:
18412 need_zero_guard = true;
18413 size_needed = GET_MODE_SIZE (Pmode) * 4;
18415 case rep_prefix_8_byte:
18418 case rep_prefix_4_byte:
18421 case rep_prefix_1_byte:
18425 need_zero_guard = true;
18429 epilogue_size_needed = size_needed;
18431 /* Step 1: Prologue guard. */
18433 /* Alignment code needs count to be in register. */
18434 if (CONST_INT_P (count_exp) && desired_align > align)
18436 if (INTVAL (count_exp) > desired_align
18437 && INTVAL (count_exp) > size_needed)
18440 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18441 if (align_bytes <= 0)
18444 align_bytes = desired_align - align_bytes;
18446 if (align_bytes == 0)
18448 enum machine_mode mode = SImode;
18449 if (TARGET_64BIT && (count & ~0xffffffff))
18451 count_exp = force_reg (mode, count_exp);
18454 /* Do the cheap promotion to allow better CSE across the
18455 main loop and epilogue (ie one load of the big constant in the
18456 front of all code. */
18457 if (CONST_INT_P (val_exp))
18458 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18459 desired_align, align);
18460 /* Ensure that alignment prologue won't copy past end of block. */
18461 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18463 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18464 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18465 Make sure it is power of 2. */
18466 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18468 /* To improve performance of small blocks, we jump around the VAL
18469 promoting mode. This mean that if the promoted VAL is not constant,
18470 we might not use it in the epilogue and have to use byte
18472 if (epilogue_size_needed > 2 && !promoted_val)
18473 force_loopy_epilogue = true;
18476 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18478 /* If main algorithm works on QImode, no epilogue is needed.
18479 For small sizes just don't align anything. */
18480 if (size_needed == 1)
18481 desired_align = align;
18488 label = gen_label_rtx ();
18489 emit_cmp_and_jump_insns (count_exp,
18490 GEN_INT (epilogue_size_needed),
18491 LTU, 0, counter_mode (count_exp), 1, label);
18492 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18493 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18495 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18498 if (dynamic_check != -1)
18500 rtx hot_label = gen_label_rtx ();
18501 jump_around_label = gen_label_rtx ();
18502 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18503 LEU, 0, counter_mode (count_exp), 1, hot_label);
18504 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18505 set_storage_via_libcall (dst, count_exp, val_exp, false);
18506 emit_jump (jump_around_label);
18507 emit_label (hot_label);
18510 /* Step 2: Alignment prologue. */
18512 /* Do the expensive promotion once we branched off the small blocks. */
18514 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18515 desired_align, align);
18516 gcc_assert (desired_align >= 1 && align >= 1);
18518 if (desired_align > align)
18520 if (align_bytes == 0)
18522 /* Except for the first move in epilogue, we no longer know
18523 constant offset in aliasing info. It don't seems to worth
18524 the pain to maintain it for the first move, so throw away
18526 dst = change_address (dst, BLKmode, destreg);
18527 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18532 /* If we know how many bytes need to be stored before dst is
18533 sufficiently aligned, maintain aliasing info accurately. */
18534 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18535 desired_align, align_bytes);
18536 count_exp = plus_constant (count_exp, -align_bytes);
18537 count -= align_bytes;
18539 if (need_zero_guard
18540 && (count < (unsigned HOST_WIDE_INT) size_needed
18541 || (align_bytes == 0
18542 && count < ((unsigned HOST_WIDE_INT) size_needed
18543 + desired_align - align))))
18545 /* It is possible that we copied enough so the main loop will not
18547 gcc_assert (size_needed > 1);
18548 if (label == NULL_RTX)
18549 label = gen_label_rtx ();
18550 emit_cmp_and_jump_insns (count_exp,
18551 GEN_INT (size_needed),
18552 LTU, 0, counter_mode (count_exp), 1, label);
18553 if (expected_size == -1
18554 || expected_size < (desired_align - align) / 2 + size_needed)
18555 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18557 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18560 if (label && size_needed == 1)
18562 emit_label (label);
18563 LABEL_NUSES (label) = 1;
18565 promoted_val = val_exp;
18566 epilogue_size_needed = 1;
18568 else if (label == NULL_RTX)
18569 epilogue_size_needed = size_needed;
18571 /* Step 3: Main loop. */
18577 gcc_unreachable ();
18579 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18580 count_exp, QImode, 1, expected_size);
18583 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18584 count_exp, Pmode, 1, expected_size);
18586 case unrolled_loop:
18587 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18588 count_exp, Pmode, 4, expected_size);
18590 case rep_prefix_8_byte:
18591 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18594 case rep_prefix_4_byte:
18595 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18598 case rep_prefix_1_byte:
18599 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18603 /* Adjust properly the offset of src and dest memory for aliasing. */
18604 if (CONST_INT_P (count_exp))
18605 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18606 (count / size_needed) * size_needed);
18608 dst = change_address (dst, BLKmode, destreg);
18610 /* Step 4: Epilogue to copy the remaining bytes. */
18614 /* When the main loop is done, COUNT_EXP might hold original count,
18615 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18616 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18617 bytes. Compensate if needed. */
18619 if (size_needed < epilogue_size_needed)
18622 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18623 GEN_INT (size_needed - 1), count_exp, 1,
18625 if (tmp != count_exp)
18626 emit_move_insn (count_exp, tmp);
18628 emit_label (label);
18629 LABEL_NUSES (label) = 1;
18632 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18634 if (force_loopy_epilogue)
18635 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18636 epilogue_size_needed);
18638 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18639 epilogue_size_needed);
18641 if (jump_around_label)
18642 emit_label (jump_around_label);
18646 /* Expand the appropriate insns for doing strlen if not just doing
18649 out = result, initialized with the start address
18650 align_rtx = alignment of the address.
18651 scratch = scratch register, initialized with the startaddress when
18652 not aligned, otherwise undefined
18654 This is just the body. It needs the initializations mentioned above and
18655 some address computing at the end. These things are done in i386.md. */
18658 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18662 rtx align_2_label = NULL_RTX;
18663 rtx align_3_label = NULL_RTX;
18664 rtx align_4_label = gen_label_rtx ();
18665 rtx end_0_label = gen_label_rtx ();
18667 rtx tmpreg = gen_reg_rtx (SImode);
18668 rtx scratch = gen_reg_rtx (SImode);
18672 if (CONST_INT_P (align_rtx))
18673 align = INTVAL (align_rtx);
18675 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18677 /* Is there a known alignment and is it less than 4? */
18680 rtx scratch1 = gen_reg_rtx (Pmode);
18681 emit_move_insn (scratch1, out);
18682 /* Is there a known alignment and is it not 2? */
18685 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18686 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18688 /* Leave just the 3 lower bits. */
18689 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18690 NULL_RTX, 0, OPTAB_WIDEN);
18692 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18693 Pmode, 1, align_4_label);
18694 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18695 Pmode, 1, align_2_label);
18696 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18697 Pmode, 1, align_3_label);
18701 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18702 check if is aligned to 4 - byte. */
18704 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18705 NULL_RTX, 0, OPTAB_WIDEN);
18707 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18708 Pmode, 1, align_4_label);
18711 mem = change_address (src, QImode, out);
18713 /* Now compare the bytes. */
18715 /* Compare the first n unaligned byte on a byte per byte basis. */
18716 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18717 QImode, 1, end_0_label);
18719 /* Increment the address. */
18720 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18722 /* Not needed with an alignment of 2 */
18725 emit_label (align_2_label);
18727 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18730 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18732 emit_label (align_3_label);
18735 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18738 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18741 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18742 align this loop. It gives only huge programs, but does not help to
18744 emit_label (align_4_label);
18746 mem = change_address (src, SImode, out);
18747 emit_move_insn (scratch, mem);
18748 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18750 /* This formula yields a nonzero result iff one of the bytes is zero.
18751 This saves three branches inside loop and many cycles. */
18753 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18754 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18755 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18756 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18757 gen_int_mode (0x80808080, SImode)));
18758 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18763 rtx reg = gen_reg_rtx (SImode);
18764 rtx reg2 = gen_reg_rtx (Pmode);
18765 emit_move_insn (reg, tmpreg);
18766 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18768 /* If zero is not in the first two bytes, move two bytes forward. */
18769 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18770 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18771 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18772 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18773 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18776 /* Emit lea manually to avoid clobbering of flags. */
18777 emit_insn (gen_rtx_SET (SImode, reg2,
18778 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18780 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18781 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18782 emit_insn (gen_rtx_SET (VOIDmode, out,
18783 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18790 rtx end_2_label = gen_label_rtx ();
18791 /* Is zero in the first two bytes? */
18793 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18794 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18795 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18796 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18797 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18799 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18800 JUMP_LABEL (tmp) = end_2_label;
18802 /* Not in the first two. Move two bytes forward. */
18803 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18804 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18806 emit_label (end_2_label);
18810 /* Avoid branch in fixing the byte. */
18811 tmpreg = gen_lowpart (QImode, tmpreg);
18812 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18813 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18814 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18816 emit_label (end_0_label);
18819 /* Expand strlen. */
18822 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18824 rtx addr, scratch1, scratch2, scratch3, scratch4;
18826 /* The generic case of strlen expander is long. Avoid it's
18827 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18829 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18830 && !TARGET_INLINE_ALL_STRINGOPS
18831 && !optimize_insn_for_size_p ()
18832 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18835 addr = force_reg (Pmode, XEXP (src, 0));
18836 scratch1 = gen_reg_rtx (Pmode);
18838 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18839 && !optimize_insn_for_size_p ())
18841 /* Well it seems that some optimizer does not combine a call like
18842 foo(strlen(bar), strlen(bar));
18843 when the move and the subtraction is done here. It does calculate
18844 the length just once when these instructions are done inside of
18845 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18846 often used and I use one fewer register for the lifetime of
18847 output_strlen_unroll() this is better. */
18849 emit_move_insn (out, addr);
18851 ix86_expand_strlensi_unroll_1 (out, src, align);
18853 /* strlensi_unroll_1 returns the address of the zero at the end of
18854 the string, like memchr(), so compute the length by subtracting
18855 the start address. */
18856 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18862 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18863 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18866 scratch2 = gen_reg_rtx (Pmode);
18867 scratch3 = gen_reg_rtx (Pmode);
18868 scratch4 = force_reg (Pmode, constm1_rtx);
18870 emit_move_insn (scratch3, addr);
18871 eoschar = force_reg (QImode, eoschar);
18873 src = replace_equiv_address_nv (src, scratch3);
18875 /* If .md starts supporting :P, this can be done in .md. */
18876 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18877 scratch4), UNSPEC_SCAS);
18878 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18879 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18880 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18885 /* For given symbol (function) construct code to compute address of it's PLT
18886 entry in large x86-64 PIC model. */
18888 construct_plt_address (rtx symbol)
18890 rtx tmp = gen_reg_rtx (Pmode);
18891 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18893 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18894 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18896 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18897 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18902 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18904 rtx pop, int sibcall)
18906 rtx use = NULL, call;
18908 if (pop == const0_rtx)
18910 gcc_assert (!TARGET_64BIT || !pop);
18912 if (TARGET_MACHO && !TARGET_64BIT)
18915 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18916 fnaddr = machopic_indirect_call_target (fnaddr);
18921 /* Static functions and indirect calls don't need the pic register. */
18922 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18923 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18924 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18925 use_reg (&use, pic_offset_table_rtx);
18928 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18930 rtx al = gen_rtx_REG (QImode, AX_REG);
18931 emit_move_insn (al, callarg2);
18932 use_reg (&use, al);
18935 if (ix86_cmodel == CM_LARGE_PIC
18937 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18938 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18939 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18941 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
18942 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
18944 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18945 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18948 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18950 call = gen_rtx_SET (VOIDmode, retval, call);
18953 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18954 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18955 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18958 && ix86_cfun_abi () == MS_ABI
18959 && (!callarg2 || INTVAL (callarg2) != -2))
18961 /* We need to represent that SI and DI registers are clobbered
18963 static int clobbered_registers[] = {
18964 XMM6_REG, XMM7_REG, XMM8_REG,
18965 XMM9_REG, XMM10_REG, XMM11_REG,
18966 XMM12_REG, XMM13_REG, XMM14_REG,
18967 XMM15_REG, SI_REG, DI_REG
18970 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18971 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18972 UNSPEC_MS_TO_SYSV_CALL);
18976 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18977 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18980 (SSE_REGNO_P (clobbered_registers[i])
18982 clobbered_registers[i]));
18984 call = gen_rtx_PARALLEL (VOIDmode,
18985 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18989 call = emit_call_insn (call);
18991 CALL_INSN_FUNCTION_USAGE (call) = use;
18995 /* Clear stack slot assignments remembered from previous functions.
18996 This is called from INIT_EXPANDERS once before RTL is emitted for each
18999 static struct machine_function *
19000 ix86_init_machine_status (void)
19002 struct machine_function *f;
19004 f = GGC_CNEW (struct machine_function);
19005 f->use_fast_prologue_epilogue_nregs = -1;
19006 f->tls_descriptor_call_expanded_p = 0;
19007 f->call_abi = ix86_abi;
19012 /* Return a MEM corresponding to a stack slot with mode MODE.
19013 Allocate a new slot if necessary.
19015 The RTL for a function can have several slots available: N is
19016 which slot to use. */
19019 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
19021 struct stack_local_entry *s;
19023 gcc_assert (n < MAX_386_STACK_LOCALS);
19025 /* Virtual slot is valid only before vregs are instantiated. */
19026 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
19028 for (s = ix86_stack_locals; s; s = s->next)
19029 if (s->mode == mode && s->n == n)
19030 return copy_rtx (s->rtl);
19032 s = (struct stack_local_entry *)
19033 ggc_alloc (sizeof (struct stack_local_entry));
19036 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
19038 s->next = ix86_stack_locals;
19039 ix86_stack_locals = s;
19043 /* Construct the SYMBOL_REF for the tls_get_addr function. */
19045 static GTY(()) rtx ix86_tls_symbol;
19047 ix86_tls_get_addr (void)
19050 if (!ix86_tls_symbol)
19052 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
19053 (TARGET_ANY_GNU_TLS
19055 ? "___tls_get_addr"
19056 : "__tls_get_addr");
19059 return ix86_tls_symbol;
19062 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
19064 static GTY(()) rtx ix86_tls_module_base_symbol;
19066 ix86_tls_module_base (void)
19069 if (!ix86_tls_module_base_symbol)
19071 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
19072 "_TLS_MODULE_BASE_");
19073 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
19074 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
19077 return ix86_tls_module_base_symbol;
19080 /* Calculate the length of the memory address in the instruction
19081 encoding. Does not include the one-byte modrm, opcode, or prefix. */
19084 memory_address_length (rtx addr)
19086 struct ix86_address parts;
19087 rtx base, index, disp;
19091 if (GET_CODE (addr) == PRE_DEC
19092 || GET_CODE (addr) == POST_INC
19093 || GET_CODE (addr) == PRE_MODIFY
19094 || GET_CODE (addr) == POST_MODIFY)
19097 ok = ix86_decompose_address (addr, &parts);
19100 if (parts.base && GET_CODE (parts.base) == SUBREG)
19101 parts.base = SUBREG_REG (parts.base);
19102 if (parts.index && GET_CODE (parts.index) == SUBREG)
19103 parts.index = SUBREG_REG (parts.index);
19106 index = parts.index;
19111 - esp as the base always wants an index,
19112 - ebp as the base always wants a displacement,
19113 - r12 as the base always wants an index,
19114 - r13 as the base always wants a displacement. */
19116 /* Register Indirect. */
19117 if (base && !index && !disp)
19119 /* esp (for its index) and ebp (for its displacement) need
19120 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
19123 && (addr == arg_pointer_rtx
19124 || addr == frame_pointer_rtx
19125 || REGNO (addr) == SP_REG
19126 || REGNO (addr) == BP_REG
19127 || REGNO (addr) == R12_REG
19128 || REGNO (addr) == R13_REG))
19132 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
19133 is not disp32, but disp32(%rip), so for disp32
19134 SIB byte is needed, unless print_operand_address
19135 optimizes it into disp32(%rip) or (%rip) is implied
19137 else if (disp && !base && !index)
19144 if (GET_CODE (disp) == CONST)
19145 symbol = XEXP (disp, 0);
19146 if (GET_CODE (symbol) == PLUS
19147 && CONST_INT_P (XEXP (symbol, 1)))
19148 symbol = XEXP (symbol, 0);
19150 if (GET_CODE (symbol) != LABEL_REF
19151 && (GET_CODE (symbol) != SYMBOL_REF
19152 || SYMBOL_REF_TLS_MODEL (symbol) != 0)
19153 && (GET_CODE (symbol) != UNSPEC
19154 || (XINT (symbol, 1) != UNSPEC_GOTPCREL
19155 && XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
19162 /* Find the length of the displacement constant. */
19165 if (base && satisfies_constraint_K (disp))
19170 /* ebp always wants a displacement. Similarly r13. */
19171 else if (base && REG_P (base)
19172 && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
19175 /* An index requires the two-byte modrm form.... */
19177 /* ...like esp (or r12), which always wants an index. */
19178 || base == arg_pointer_rtx
19179 || base == frame_pointer_rtx
19180 || (base && REG_P (base)
19181 && (REGNO (base) == SP_REG || REGNO (base) == R12_REG)))
19198 /* Compute default value for "length_immediate" attribute. When SHORTFORM
19199 is set, expect that insn have 8bit immediate alternative. */
19201 ix86_attr_length_immediate_default (rtx insn, int shortform)
19205 extract_insn_cached (insn);
19206 for (i = recog_data.n_operands - 1; i >= 0; --i)
19207 if (CONSTANT_P (recog_data.operand[i]))
19209 enum attr_mode mode = get_attr_mode (insn);
19212 if (shortform && CONST_INT_P (recog_data.operand[i]))
19214 HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
19221 ival = trunc_int_for_mode (ival, HImode);
19224 ival = trunc_int_for_mode (ival, SImode);
19229 if (IN_RANGE (ival, -128, 127))
19246 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19251 fatal_insn ("unknown insn mode", insn);
19256 /* Compute default value for "length_address" attribute. */
19258 ix86_attr_length_address_default (rtx insn)
19262 if (get_attr_type (insn) == TYPE_LEA)
19264 rtx set = PATTERN (insn), addr;
19266 if (GET_CODE (set) == PARALLEL)
19267 set = XVECEXP (set, 0, 0);
19269 gcc_assert (GET_CODE (set) == SET);
19271 addr = SET_SRC (set);
19272 if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI)
19274 if (GET_CODE (addr) == ZERO_EXTEND)
19275 addr = XEXP (addr, 0);
19276 if (GET_CODE (addr) == SUBREG)
19277 addr = SUBREG_REG (addr);
19280 return memory_address_length (addr);
19283 extract_insn_cached (insn);
19284 for (i = recog_data.n_operands - 1; i >= 0; --i)
19285 if (MEM_P (recog_data.operand[i]))
19287 constrain_operands_cached (reload_completed);
19288 if (which_alternative != -1)
19290 const char *constraints = recog_data.constraints[i];
19291 int alt = which_alternative;
19293 while (*constraints == '=' || *constraints == '+')
19296 while (*constraints++ != ',')
19298 /* Skip ignored operands. */
19299 if (*constraints == 'X')
19302 return memory_address_length (XEXP (recog_data.operand[i], 0));
19307 /* Compute default value for "length_vex" attribute. It includes
19308 2 or 3 byte VEX prefix and 1 opcode byte. */
19311 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19316 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19317 byte VEX prefix. */
19318 if (!has_0f_opcode || has_vex_w)
19321 /* We can always use 2 byte VEX prefix in 32bit. */
19325 extract_insn_cached (insn);
19327 for (i = recog_data.n_operands - 1; i >= 0; --i)
19328 if (REG_P (recog_data.operand[i]))
19330 /* REX.W bit uses 3 byte VEX prefix. */
19331 if (GET_MODE (recog_data.operand[i]) == DImode
19332 && GENERAL_REG_P (recog_data.operand[i]))
19337 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19338 if (MEM_P (recog_data.operand[i])
19339 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19346 /* Return the maximum number of instructions a cpu can issue. */
19349 ix86_issue_rate (void)
19353 case PROCESSOR_PENTIUM:
19354 case PROCESSOR_ATOM:
19358 case PROCESSOR_PENTIUMPRO:
19359 case PROCESSOR_PENTIUM4:
19360 case PROCESSOR_ATHLON:
19362 case PROCESSOR_AMDFAM10:
19363 case PROCESSOR_NOCONA:
19364 case PROCESSOR_GENERIC32:
19365 case PROCESSOR_GENERIC64:
19368 case PROCESSOR_CORE2:
19376 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19377 by DEP_INSN and nothing set by DEP_INSN. */
19380 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19384 /* Simplify the test for uninteresting insns. */
19385 if (insn_type != TYPE_SETCC
19386 && insn_type != TYPE_ICMOV
19387 && insn_type != TYPE_FCMOV
19388 && insn_type != TYPE_IBR)
19391 if ((set = single_set (dep_insn)) != 0)
19393 set = SET_DEST (set);
19396 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19397 && XVECLEN (PATTERN (dep_insn), 0) == 2
19398 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19399 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19401 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19402 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19407 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19410 /* This test is true if the dependent insn reads the flags but
19411 not any other potentially set register. */
19412 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19415 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19421 /* Return true iff USE_INSN has a memory address with operands set by
19425 ix86_agi_dependent (rtx set_insn, rtx use_insn)
19428 extract_insn_cached (use_insn);
19429 for (i = recog_data.n_operands - 1; i >= 0; --i)
19430 if (MEM_P (recog_data.operand[i]))
19432 rtx addr = XEXP (recog_data.operand[i], 0);
19433 return modified_in_p (addr, set_insn) != 0;
19439 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19441 enum attr_type insn_type, dep_insn_type;
19442 enum attr_memory memory;
19444 int dep_insn_code_number;
19446 /* Anti and output dependencies have zero cost on all CPUs. */
19447 if (REG_NOTE_KIND (link) != 0)
19450 dep_insn_code_number = recog_memoized (dep_insn);
19452 /* If we can't recognize the insns, we can't really do anything. */
19453 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19456 insn_type = get_attr_type (insn);
19457 dep_insn_type = get_attr_type (dep_insn);
19461 case PROCESSOR_PENTIUM:
19462 /* Address Generation Interlock adds a cycle of latency. */
19463 if (insn_type == TYPE_LEA)
19465 rtx addr = PATTERN (insn);
19467 if (GET_CODE (addr) == PARALLEL)
19468 addr = XVECEXP (addr, 0, 0);
19470 gcc_assert (GET_CODE (addr) == SET);
19472 addr = SET_SRC (addr);
19473 if (modified_in_p (addr, dep_insn))
19476 else if (ix86_agi_dependent (dep_insn, insn))
19479 /* ??? Compares pair with jump/setcc. */
19480 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19483 /* Floating point stores require value to be ready one cycle earlier. */
19484 if (insn_type == TYPE_FMOV
19485 && get_attr_memory (insn) == MEMORY_STORE
19486 && !ix86_agi_dependent (dep_insn, insn))
19490 case PROCESSOR_PENTIUMPRO:
19491 memory = get_attr_memory (insn);
19493 /* INT->FP conversion is expensive. */
19494 if (get_attr_fp_int_src (dep_insn))
19497 /* There is one cycle extra latency between an FP op and a store. */
19498 if (insn_type == TYPE_FMOV
19499 && (set = single_set (dep_insn)) != NULL_RTX
19500 && (set2 = single_set (insn)) != NULL_RTX
19501 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19502 && MEM_P (SET_DEST (set2)))
19505 /* Show ability of reorder buffer to hide latency of load by executing
19506 in parallel with previous instruction in case
19507 previous instruction is not needed to compute the address. */
19508 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19509 && !ix86_agi_dependent (dep_insn, insn))
19511 /* Claim moves to take one cycle, as core can issue one load
19512 at time and the next load can start cycle later. */
19513 if (dep_insn_type == TYPE_IMOV
19514 || dep_insn_type == TYPE_FMOV)
19522 memory = get_attr_memory (insn);
19524 /* The esp dependency is resolved before the instruction is really
19526 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19527 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19530 /* INT->FP conversion is expensive. */
19531 if (get_attr_fp_int_src (dep_insn))
19534 /* Show ability of reorder buffer to hide latency of load by executing
19535 in parallel with previous instruction in case
19536 previous instruction is not needed to compute the address. */
19537 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19538 && !ix86_agi_dependent (dep_insn, insn))
19540 /* Claim moves to take one cycle, as core can issue one load
19541 at time and the next load can start cycle later. */
19542 if (dep_insn_type == TYPE_IMOV
19543 || dep_insn_type == TYPE_FMOV)
19552 case PROCESSOR_ATHLON:
19554 case PROCESSOR_AMDFAM10:
19555 case PROCESSOR_ATOM:
19556 case PROCESSOR_GENERIC32:
19557 case PROCESSOR_GENERIC64:
19558 memory = get_attr_memory (insn);
19560 /* Show ability of reorder buffer to hide latency of load by executing
19561 in parallel with previous instruction in case
19562 previous instruction is not needed to compute the address. */
19563 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19564 && !ix86_agi_dependent (dep_insn, insn))
19566 enum attr_unit unit = get_attr_unit (insn);
19569 /* Because of the difference between the length of integer and
19570 floating unit pipeline preparation stages, the memory operands
19571 for floating point are cheaper.
19573 ??? For Athlon it the difference is most probably 2. */
19574 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19577 loadcost = TARGET_ATHLON ? 2 : 0;
19579 if (cost >= loadcost)
19592 /* How many alternative schedules to try. This should be as wide as the
19593 scheduling freedom in the DFA, but no wider. Making this value too
19594 large results extra work for the scheduler. */
19597 ia32_multipass_dfa_lookahead (void)
19601 case PROCESSOR_PENTIUM:
19604 case PROCESSOR_PENTIUMPRO:
19614 /* Compute the alignment given to a constant that is being placed in memory.
19615 EXP is the constant and ALIGN is the alignment that the object would
19617 The value of this function is used instead of that alignment to align
19621 ix86_constant_alignment (tree exp, int align)
19623 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19624 || TREE_CODE (exp) == INTEGER_CST)
19626 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19628 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19631 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19632 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19633 return BITS_PER_WORD;
19638 /* Compute the alignment for a static variable.
19639 TYPE is the data type, and ALIGN is the alignment that
19640 the object would ordinarily have. The value of this function is used
19641 instead of that alignment to align the object. */
19644 ix86_data_alignment (tree type, int align)
19646 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19648 if (AGGREGATE_TYPE_P (type)
19649 && TYPE_SIZE (type)
19650 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19651 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19652 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19653 && align < max_align)
19656 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19657 to 16byte boundary. */
19660 if (AGGREGATE_TYPE_P (type)
19661 && TYPE_SIZE (type)
19662 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19663 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19664 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19668 if (TREE_CODE (type) == ARRAY_TYPE)
19670 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19672 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19675 else if (TREE_CODE (type) == COMPLEX_TYPE)
19678 if (TYPE_MODE (type) == DCmode && align < 64)
19680 if ((TYPE_MODE (type) == XCmode
19681 || TYPE_MODE (type) == TCmode) && align < 128)
19684 else if ((TREE_CODE (type) == RECORD_TYPE
19685 || TREE_CODE (type) == UNION_TYPE
19686 || TREE_CODE (type) == QUAL_UNION_TYPE)
19687 && TYPE_FIELDS (type))
19689 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19691 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19694 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19695 || TREE_CODE (type) == INTEGER_TYPE)
19697 if (TYPE_MODE (type) == DFmode && align < 64)
19699 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19706 /* Compute the alignment for a local variable or a stack slot. EXP is
19707 the data type or decl itself, MODE is the widest mode available and
19708 ALIGN is the alignment that the object would ordinarily have. The
19709 value of this macro is used instead of that alignment to align the
19713 ix86_local_alignment (tree exp, enum machine_mode mode,
19714 unsigned int align)
19718 if (exp && DECL_P (exp))
19720 type = TREE_TYPE (exp);
19729 /* Don't do dynamic stack realignment for long long objects with
19730 -mpreferred-stack-boundary=2. */
19733 && ix86_preferred_stack_boundary < 64
19734 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19735 && (!type || !TYPE_USER_ALIGN (type))
19736 && (!decl || !DECL_USER_ALIGN (decl)))
19739 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19740 register in MODE. We will return the largest alignment of XF
19744 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19745 align = GET_MODE_ALIGNMENT (DFmode);
19749 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19750 to 16byte boundary. */
19753 if (AGGREGATE_TYPE_P (type)
19754 && TYPE_SIZE (type)
19755 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19756 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19757 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19760 if (TREE_CODE (type) == ARRAY_TYPE)
19762 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19764 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19767 else if (TREE_CODE (type) == COMPLEX_TYPE)
19769 if (TYPE_MODE (type) == DCmode && align < 64)
19771 if ((TYPE_MODE (type) == XCmode
19772 || TYPE_MODE (type) == TCmode) && align < 128)
19775 else if ((TREE_CODE (type) == RECORD_TYPE
19776 || TREE_CODE (type) == UNION_TYPE
19777 || TREE_CODE (type) == QUAL_UNION_TYPE)
19778 && TYPE_FIELDS (type))
19780 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19782 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19785 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19786 || TREE_CODE (type) == INTEGER_TYPE)
19789 if (TYPE_MODE (type) == DFmode && align < 64)
19791 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19797 /* Compute the minimum required alignment for dynamic stack realignment
19798 purposes for a local variable, parameter or a stack slot. EXP is
19799 the data type or decl itself, MODE is its mode and ALIGN is the
19800 alignment that the object would ordinarily have. */
19803 ix86_minimum_alignment (tree exp, enum machine_mode mode,
19804 unsigned int align)
19808 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
19811 if (exp && DECL_P (exp))
19813 type = TREE_TYPE (exp);
19822 /* Don't do dynamic stack realignment for long long objects with
19823 -mpreferred-stack-boundary=2. */
19824 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
19825 && (!type || !TYPE_USER_ALIGN (type))
19826 && (!decl || !DECL_USER_ALIGN (decl)))
19832 /* Emit RTL insns to initialize the variable parts of a trampoline.
19833 FNADDR is an RTX for the address of the function's pure code.
19834 CXT is an RTX for the static chain value for the function. */
19836 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19840 /* Compute offset from the end of the jmp to the target function. */
19841 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19842 plus_constant (tramp, 10),
19843 NULL_RTX, 1, OPTAB_DIRECT);
19844 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19845 gen_int_mode (0xb9, QImode));
19846 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19847 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19848 gen_int_mode (0xe9, QImode));
19849 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19854 /* Try to load address using shorter movl instead of movabs.
19855 We may want to support movq for kernel mode, but kernel does not use
19856 trampolines at the moment. */
19857 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19859 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19860 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19861 gen_int_mode (0xbb41, HImode));
19862 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19863 gen_lowpart (SImode, fnaddr));
19868 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19869 gen_int_mode (0xbb49, HImode));
19870 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19874 /* Load static chain using movabs to r10. */
19875 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19876 gen_int_mode (0xba49, HImode));
19877 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19880 /* Jump to the r11 */
19881 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19882 gen_int_mode (0xff49, HImode));
19883 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
19884 gen_int_mode (0xe3, QImode));
19886 gcc_assert (offset <= TRAMPOLINE_SIZE);
19889 #ifdef ENABLE_EXECUTE_STACK
19890 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19891 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
19895 /* Codes for all the SSE/MMX builtins. */
19898 IX86_BUILTIN_ADDPS,
19899 IX86_BUILTIN_ADDSS,
19900 IX86_BUILTIN_DIVPS,
19901 IX86_BUILTIN_DIVSS,
19902 IX86_BUILTIN_MULPS,
19903 IX86_BUILTIN_MULSS,
19904 IX86_BUILTIN_SUBPS,
19905 IX86_BUILTIN_SUBSS,
19907 IX86_BUILTIN_CMPEQPS,
19908 IX86_BUILTIN_CMPLTPS,
19909 IX86_BUILTIN_CMPLEPS,
19910 IX86_BUILTIN_CMPGTPS,
19911 IX86_BUILTIN_CMPGEPS,
19912 IX86_BUILTIN_CMPNEQPS,
19913 IX86_BUILTIN_CMPNLTPS,
19914 IX86_BUILTIN_CMPNLEPS,
19915 IX86_BUILTIN_CMPNGTPS,
19916 IX86_BUILTIN_CMPNGEPS,
19917 IX86_BUILTIN_CMPORDPS,
19918 IX86_BUILTIN_CMPUNORDPS,
19919 IX86_BUILTIN_CMPEQSS,
19920 IX86_BUILTIN_CMPLTSS,
19921 IX86_BUILTIN_CMPLESS,
19922 IX86_BUILTIN_CMPNEQSS,
19923 IX86_BUILTIN_CMPNLTSS,
19924 IX86_BUILTIN_CMPNLESS,
19925 IX86_BUILTIN_CMPNGTSS,
19926 IX86_BUILTIN_CMPNGESS,
19927 IX86_BUILTIN_CMPORDSS,
19928 IX86_BUILTIN_CMPUNORDSS,
19930 IX86_BUILTIN_COMIEQSS,
19931 IX86_BUILTIN_COMILTSS,
19932 IX86_BUILTIN_COMILESS,
19933 IX86_BUILTIN_COMIGTSS,
19934 IX86_BUILTIN_COMIGESS,
19935 IX86_BUILTIN_COMINEQSS,
19936 IX86_BUILTIN_UCOMIEQSS,
19937 IX86_BUILTIN_UCOMILTSS,
19938 IX86_BUILTIN_UCOMILESS,
19939 IX86_BUILTIN_UCOMIGTSS,
19940 IX86_BUILTIN_UCOMIGESS,
19941 IX86_BUILTIN_UCOMINEQSS,
19943 IX86_BUILTIN_CVTPI2PS,
19944 IX86_BUILTIN_CVTPS2PI,
19945 IX86_BUILTIN_CVTSI2SS,
19946 IX86_BUILTIN_CVTSI642SS,
19947 IX86_BUILTIN_CVTSS2SI,
19948 IX86_BUILTIN_CVTSS2SI64,
19949 IX86_BUILTIN_CVTTPS2PI,
19950 IX86_BUILTIN_CVTTSS2SI,
19951 IX86_BUILTIN_CVTTSS2SI64,
19953 IX86_BUILTIN_MAXPS,
19954 IX86_BUILTIN_MAXSS,
19955 IX86_BUILTIN_MINPS,
19956 IX86_BUILTIN_MINSS,
19958 IX86_BUILTIN_LOADUPS,
19959 IX86_BUILTIN_STOREUPS,
19960 IX86_BUILTIN_MOVSS,
19962 IX86_BUILTIN_MOVHLPS,
19963 IX86_BUILTIN_MOVLHPS,
19964 IX86_BUILTIN_LOADHPS,
19965 IX86_BUILTIN_LOADLPS,
19966 IX86_BUILTIN_STOREHPS,
19967 IX86_BUILTIN_STORELPS,
19969 IX86_BUILTIN_MASKMOVQ,
19970 IX86_BUILTIN_MOVMSKPS,
19971 IX86_BUILTIN_PMOVMSKB,
19973 IX86_BUILTIN_MOVNTPS,
19974 IX86_BUILTIN_MOVNTQ,
19976 IX86_BUILTIN_LOADDQU,
19977 IX86_BUILTIN_STOREDQU,
19979 IX86_BUILTIN_PACKSSWB,
19980 IX86_BUILTIN_PACKSSDW,
19981 IX86_BUILTIN_PACKUSWB,
19983 IX86_BUILTIN_PADDB,
19984 IX86_BUILTIN_PADDW,
19985 IX86_BUILTIN_PADDD,
19986 IX86_BUILTIN_PADDQ,
19987 IX86_BUILTIN_PADDSB,
19988 IX86_BUILTIN_PADDSW,
19989 IX86_BUILTIN_PADDUSB,
19990 IX86_BUILTIN_PADDUSW,
19991 IX86_BUILTIN_PSUBB,
19992 IX86_BUILTIN_PSUBW,
19993 IX86_BUILTIN_PSUBD,
19994 IX86_BUILTIN_PSUBQ,
19995 IX86_BUILTIN_PSUBSB,
19996 IX86_BUILTIN_PSUBSW,
19997 IX86_BUILTIN_PSUBUSB,
19998 IX86_BUILTIN_PSUBUSW,
20001 IX86_BUILTIN_PANDN,
20005 IX86_BUILTIN_PAVGB,
20006 IX86_BUILTIN_PAVGW,
20008 IX86_BUILTIN_PCMPEQB,
20009 IX86_BUILTIN_PCMPEQW,
20010 IX86_BUILTIN_PCMPEQD,
20011 IX86_BUILTIN_PCMPGTB,
20012 IX86_BUILTIN_PCMPGTW,
20013 IX86_BUILTIN_PCMPGTD,
20015 IX86_BUILTIN_PMADDWD,
20017 IX86_BUILTIN_PMAXSW,
20018 IX86_BUILTIN_PMAXUB,
20019 IX86_BUILTIN_PMINSW,
20020 IX86_BUILTIN_PMINUB,
20022 IX86_BUILTIN_PMULHUW,
20023 IX86_BUILTIN_PMULHW,
20024 IX86_BUILTIN_PMULLW,
20026 IX86_BUILTIN_PSADBW,
20027 IX86_BUILTIN_PSHUFW,
20029 IX86_BUILTIN_PSLLW,
20030 IX86_BUILTIN_PSLLD,
20031 IX86_BUILTIN_PSLLQ,
20032 IX86_BUILTIN_PSRAW,
20033 IX86_BUILTIN_PSRAD,
20034 IX86_BUILTIN_PSRLW,
20035 IX86_BUILTIN_PSRLD,
20036 IX86_BUILTIN_PSRLQ,
20037 IX86_BUILTIN_PSLLWI,
20038 IX86_BUILTIN_PSLLDI,
20039 IX86_BUILTIN_PSLLQI,
20040 IX86_BUILTIN_PSRAWI,
20041 IX86_BUILTIN_PSRADI,
20042 IX86_BUILTIN_PSRLWI,
20043 IX86_BUILTIN_PSRLDI,
20044 IX86_BUILTIN_PSRLQI,
20046 IX86_BUILTIN_PUNPCKHBW,
20047 IX86_BUILTIN_PUNPCKHWD,
20048 IX86_BUILTIN_PUNPCKHDQ,
20049 IX86_BUILTIN_PUNPCKLBW,
20050 IX86_BUILTIN_PUNPCKLWD,
20051 IX86_BUILTIN_PUNPCKLDQ,
20053 IX86_BUILTIN_SHUFPS,
20055 IX86_BUILTIN_RCPPS,
20056 IX86_BUILTIN_RCPSS,
20057 IX86_BUILTIN_RSQRTPS,
20058 IX86_BUILTIN_RSQRTPS_NR,
20059 IX86_BUILTIN_RSQRTSS,
20060 IX86_BUILTIN_RSQRTF,
20061 IX86_BUILTIN_SQRTPS,
20062 IX86_BUILTIN_SQRTPS_NR,
20063 IX86_BUILTIN_SQRTSS,
20065 IX86_BUILTIN_UNPCKHPS,
20066 IX86_BUILTIN_UNPCKLPS,
20068 IX86_BUILTIN_ANDPS,
20069 IX86_BUILTIN_ANDNPS,
20071 IX86_BUILTIN_XORPS,
20074 IX86_BUILTIN_LDMXCSR,
20075 IX86_BUILTIN_STMXCSR,
20076 IX86_BUILTIN_SFENCE,
20078 /* 3DNow! Original */
20079 IX86_BUILTIN_FEMMS,
20080 IX86_BUILTIN_PAVGUSB,
20081 IX86_BUILTIN_PF2ID,
20082 IX86_BUILTIN_PFACC,
20083 IX86_BUILTIN_PFADD,
20084 IX86_BUILTIN_PFCMPEQ,
20085 IX86_BUILTIN_PFCMPGE,
20086 IX86_BUILTIN_PFCMPGT,
20087 IX86_BUILTIN_PFMAX,
20088 IX86_BUILTIN_PFMIN,
20089 IX86_BUILTIN_PFMUL,
20090 IX86_BUILTIN_PFRCP,
20091 IX86_BUILTIN_PFRCPIT1,
20092 IX86_BUILTIN_PFRCPIT2,
20093 IX86_BUILTIN_PFRSQIT1,
20094 IX86_BUILTIN_PFRSQRT,
20095 IX86_BUILTIN_PFSUB,
20096 IX86_BUILTIN_PFSUBR,
20097 IX86_BUILTIN_PI2FD,
20098 IX86_BUILTIN_PMULHRW,
20100 /* 3DNow! Athlon Extensions */
20101 IX86_BUILTIN_PF2IW,
20102 IX86_BUILTIN_PFNACC,
20103 IX86_BUILTIN_PFPNACC,
20104 IX86_BUILTIN_PI2FW,
20105 IX86_BUILTIN_PSWAPDSI,
20106 IX86_BUILTIN_PSWAPDSF,
20109 IX86_BUILTIN_ADDPD,
20110 IX86_BUILTIN_ADDSD,
20111 IX86_BUILTIN_DIVPD,
20112 IX86_BUILTIN_DIVSD,
20113 IX86_BUILTIN_MULPD,
20114 IX86_BUILTIN_MULSD,
20115 IX86_BUILTIN_SUBPD,
20116 IX86_BUILTIN_SUBSD,
20118 IX86_BUILTIN_CMPEQPD,
20119 IX86_BUILTIN_CMPLTPD,
20120 IX86_BUILTIN_CMPLEPD,
20121 IX86_BUILTIN_CMPGTPD,
20122 IX86_BUILTIN_CMPGEPD,
20123 IX86_BUILTIN_CMPNEQPD,
20124 IX86_BUILTIN_CMPNLTPD,
20125 IX86_BUILTIN_CMPNLEPD,
20126 IX86_BUILTIN_CMPNGTPD,
20127 IX86_BUILTIN_CMPNGEPD,
20128 IX86_BUILTIN_CMPORDPD,
20129 IX86_BUILTIN_CMPUNORDPD,
20130 IX86_BUILTIN_CMPEQSD,
20131 IX86_BUILTIN_CMPLTSD,
20132 IX86_BUILTIN_CMPLESD,
20133 IX86_BUILTIN_CMPNEQSD,
20134 IX86_BUILTIN_CMPNLTSD,
20135 IX86_BUILTIN_CMPNLESD,
20136 IX86_BUILTIN_CMPORDSD,
20137 IX86_BUILTIN_CMPUNORDSD,
20139 IX86_BUILTIN_COMIEQSD,
20140 IX86_BUILTIN_COMILTSD,
20141 IX86_BUILTIN_COMILESD,
20142 IX86_BUILTIN_COMIGTSD,
20143 IX86_BUILTIN_COMIGESD,
20144 IX86_BUILTIN_COMINEQSD,
20145 IX86_BUILTIN_UCOMIEQSD,
20146 IX86_BUILTIN_UCOMILTSD,
20147 IX86_BUILTIN_UCOMILESD,
20148 IX86_BUILTIN_UCOMIGTSD,
20149 IX86_BUILTIN_UCOMIGESD,
20150 IX86_BUILTIN_UCOMINEQSD,
20152 IX86_BUILTIN_MAXPD,
20153 IX86_BUILTIN_MAXSD,
20154 IX86_BUILTIN_MINPD,
20155 IX86_BUILTIN_MINSD,
20157 IX86_BUILTIN_ANDPD,
20158 IX86_BUILTIN_ANDNPD,
20160 IX86_BUILTIN_XORPD,
20162 IX86_BUILTIN_SQRTPD,
20163 IX86_BUILTIN_SQRTSD,
20165 IX86_BUILTIN_UNPCKHPD,
20166 IX86_BUILTIN_UNPCKLPD,
20168 IX86_BUILTIN_SHUFPD,
20170 IX86_BUILTIN_LOADUPD,
20171 IX86_BUILTIN_STOREUPD,
20172 IX86_BUILTIN_MOVSD,
20174 IX86_BUILTIN_LOADHPD,
20175 IX86_BUILTIN_LOADLPD,
20177 IX86_BUILTIN_CVTDQ2PD,
20178 IX86_BUILTIN_CVTDQ2PS,
20180 IX86_BUILTIN_CVTPD2DQ,
20181 IX86_BUILTIN_CVTPD2PI,
20182 IX86_BUILTIN_CVTPD2PS,
20183 IX86_BUILTIN_CVTTPD2DQ,
20184 IX86_BUILTIN_CVTTPD2PI,
20186 IX86_BUILTIN_CVTPI2PD,
20187 IX86_BUILTIN_CVTSI2SD,
20188 IX86_BUILTIN_CVTSI642SD,
20190 IX86_BUILTIN_CVTSD2SI,
20191 IX86_BUILTIN_CVTSD2SI64,
20192 IX86_BUILTIN_CVTSD2SS,
20193 IX86_BUILTIN_CVTSS2SD,
20194 IX86_BUILTIN_CVTTSD2SI,
20195 IX86_BUILTIN_CVTTSD2SI64,
20197 IX86_BUILTIN_CVTPS2DQ,
20198 IX86_BUILTIN_CVTPS2PD,
20199 IX86_BUILTIN_CVTTPS2DQ,
20201 IX86_BUILTIN_MOVNTI,
20202 IX86_BUILTIN_MOVNTPD,
20203 IX86_BUILTIN_MOVNTDQ,
20205 IX86_BUILTIN_MOVQ128,
20208 IX86_BUILTIN_MASKMOVDQU,
20209 IX86_BUILTIN_MOVMSKPD,
20210 IX86_BUILTIN_PMOVMSKB128,
20212 IX86_BUILTIN_PACKSSWB128,
20213 IX86_BUILTIN_PACKSSDW128,
20214 IX86_BUILTIN_PACKUSWB128,
20216 IX86_BUILTIN_PADDB128,
20217 IX86_BUILTIN_PADDW128,
20218 IX86_BUILTIN_PADDD128,
20219 IX86_BUILTIN_PADDQ128,
20220 IX86_BUILTIN_PADDSB128,
20221 IX86_BUILTIN_PADDSW128,
20222 IX86_BUILTIN_PADDUSB128,
20223 IX86_BUILTIN_PADDUSW128,
20224 IX86_BUILTIN_PSUBB128,
20225 IX86_BUILTIN_PSUBW128,
20226 IX86_BUILTIN_PSUBD128,
20227 IX86_BUILTIN_PSUBQ128,
20228 IX86_BUILTIN_PSUBSB128,
20229 IX86_BUILTIN_PSUBSW128,
20230 IX86_BUILTIN_PSUBUSB128,
20231 IX86_BUILTIN_PSUBUSW128,
20233 IX86_BUILTIN_PAND128,
20234 IX86_BUILTIN_PANDN128,
20235 IX86_BUILTIN_POR128,
20236 IX86_BUILTIN_PXOR128,
20238 IX86_BUILTIN_PAVGB128,
20239 IX86_BUILTIN_PAVGW128,
20241 IX86_BUILTIN_PCMPEQB128,
20242 IX86_BUILTIN_PCMPEQW128,
20243 IX86_BUILTIN_PCMPEQD128,
20244 IX86_BUILTIN_PCMPGTB128,
20245 IX86_BUILTIN_PCMPGTW128,
20246 IX86_BUILTIN_PCMPGTD128,
20248 IX86_BUILTIN_PMADDWD128,
20250 IX86_BUILTIN_PMAXSW128,
20251 IX86_BUILTIN_PMAXUB128,
20252 IX86_BUILTIN_PMINSW128,
20253 IX86_BUILTIN_PMINUB128,
20255 IX86_BUILTIN_PMULUDQ,
20256 IX86_BUILTIN_PMULUDQ128,
20257 IX86_BUILTIN_PMULHUW128,
20258 IX86_BUILTIN_PMULHW128,
20259 IX86_BUILTIN_PMULLW128,
20261 IX86_BUILTIN_PSADBW128,
20262 IX86_BUILTIN_PSHUFHW,
20263 IX86_BUILTIN_PSHUFLW,
20264 IX86_BUILTIN_PSHUFD,
20266 IX86_BUILTIN_PSLLDQI128,
20267 IX86_BUILTIN_PSLLWI128,
20268 IX86_BUILTIN_PSLLDI128,
20269 IX86_BUILTIN_PSLLQI128,
20270 IX86_BUILTIN_PSRAWI128,
20271 IX86_BUILTIN_PSRADI128,
20272 IX86_BUILTIN_PSRLDQI128,
20273 IX86_BUILTIN_PSRLWI128,
20274 IX86_BUILTIN_PSRLDI128,
20275 IX86_BUILTIN_PSRLQI128,
20277 IX86_BUILTIN_PSLLDQ128,
20278 IX86_BUILTIN_PSLLW128,
20279 IX86_BUILTIN_PSLLD128,
20280 IX86_BUILTIN_PSLLQ128,
20281 IX86_BUILTIN_PSRAW128,
20282 IX86_BUILTIN_PSRAD128,
20283 IX86_BUILTIN_PSRLW128,
20284 IX86_BUILTIN_PSRLD128,
20285 IX86_BUILTIN_PSRLQ128,
20287 IX86_BUILTIN_PUNPCKHBW128,
20288 IX86_BUILTIN_PUNPCKHWD128,
20289 IX86_BUILTIN_PUNPCKHDQ128,
20290 IX86_BUILTIN_PUNPCKHQDQ128,
20291 IX86_BUILTIN_PUNPCKLBW128,
20292 IX86_BUILTIN_PUNPCKLWD128,
20293 IX86_BUILTIN_PUNPCKLDQ128,
20294 IX86_BUILTIN_PUNPCKLQDQ128,
20296 IX86_BUILTIN_CLFLUSH,
20297 IX86_BUILTIN_MFENCE,
20298 IX86_BUILTIN_LFENCE,
20300 IX86_BUILTIN_BSRSI,
20301 IX86_BUILTIN_BSRDI,
20302 IX86_BUILTIN_RDPMC,
20303 IX86_BUILTIN_RDTSC,
20304 IX86_BUILTIN_RDTSCP,
20305 IX86_BUILTIN_ROLQI,
20306 IX86_BUILTIN_ROLHI,
20307 IX86_BUILTIN_RORQI,
20308 IX86_BUILTIN_RORHI,
20311 IX86_BUILTIN_ADDSUBPS,
20312 IX86_BUILTIN_HADDPS,
20313 IX86_BUILTIN_HSUBPS,
20314 IX86_BUILTIN_MOVSHDUP,
20315 IX86_BUILTIN_MOVSLDUP,
20316 IX86_BUILTIN_ADDSUBPD,
20317 IX86_BUILTIN_HADDPD,
20318 IX86_BUILTIN_HSUBPD,
20319 IX86_BUILTIN_LDDQU,
20321 IX86_BUILTIN_MONITOR,
20322 IX86_BUILTIN_MWAIT,
20325 IX86_BUILTIN_PHADDW,
20326 IX86_BUILTIN_PHADDD,
20327 IX86_BUILTIN_PHADDSW,
20328 IX86_BUILTIN_PHSUBW,
20329 IX86_BUILTIN_PHSUBD,
20330 IX86_BUILTIN_PHSUBSW,
20331 IX86_BUILTIN_PMADDUBSW,
20332 IX86_BUILTIN_PMULHRSW,
20333 IX86_BUILTIN_PSHUFB,
20334 IX86_BUILTIN_PSIGNB,
20335 IX86_BUILTIN_PSIGNW,
20336 IX86_BUILTIN_PSIGND,
20337 IX86_BUILTIN_PALIGNR,
20338 IX86_BUILTIN_PABSB,
20339 IX86_BUILTIN_PABSW,
20340 IX86_BUILTIN_PABSD,
20342 IX86_BUILTIN_PHADDW128,
20343 IX86_BUILTIN_PHADDD128,
20344 IX86_BUILTIN_PHADDSW128,
20345 IX86_BUILTIN_PHSUBW128,
20346 IX86_BUILTIN_PHSUBD128,
20347 IX86_BUILTIN_PHSUBSW128,
20348 IX86_BUILTIN_PMADDUBSW128,
20349 IX86_BUILTIN_PMULHRSW128,
20350 IX86_BUILTIN_PSHUFB128,
20351 IX86_BUILTIN_PSIGNB128,
20352 IX86_BUILTIN_PSIGNW128,
20353 IX86_BUILTIN_PSIGND128,
20354 IX86_BUILTIN_PALIGNR128,
20355 IX86_BUILTIN_PABSB128,
20356 IX86_BUILTIN_PABSW128,
20357 IX86_BUILTIN_PABSD128,
20359 /* AMDFAM10 - SSE4A New Instructions. */
20360 IX86_BUILTIN_MOVNTSD,
20361 IX86_BUILTIN_MOVNTSS,
20362 IX86_BUILTIN_EXTRQI,
20363 IX86_BUILTIN_EXTRQ,
20364 IX86_BUILTIN_INSERTQI,
20365 IX86_BUILTIN_INSERTQ,
20368 IX86_BUILTIN_BLENDPD,
20369 IX86_BUILTIN_BLENDPS,
20370 IX86_BUILTIN_BLENDVPD,
20371 IX86_BUILTIN_BLENDVPS,
20372 IX86_BUILTIN_PBLENDVB128,
20373 IX86_BUILTIN_PBLENDW128,
20378 IX86_BUILTIN_INSERTPS128,
20380 IX86_BUILTIN_MOVNTDQA,
20381 IX86_BUILTIN_MPSADBW128,
20382 IX86_BUILTIN_PACKUSDW128,
20383 IX86_BUILTIN_PCMPEQQ,
20384 IX86_BUILTIN_PHMINPOSUW128,
20386 IX86_BUILTIN_PMAXSB128,
20387 IX86_BUILTIN_PMAXSD128,
20388 IX86_BUILTIN_PMAXUD128,
20389 IX86_BUILTIN_PMAXUW128,
20391 IX86_BUILTIN_PMINSB128,
20392 IX86_BUILTIN_PMINSD128,
20393 IX86_BUILTIN_PMINUD128,
20394 IX86_BUILTIN_PMINUW128,
20396 IX86_BUILTIN_PMOVSXBW128,
20397 IX86_BUILTIN_PMOVSXBD128,
20398 IX86_BUILTIN_PMOVSXBQ128,
20399 IX86_BUILTIN_PMOVSXWD128,
20400 IX86_BUILTIN_PMOVSXWQ128,
20401 IX86_BUILTIN_PMOVSXDQ128,
20403 IX86_BUILTIN_PMOVZXBW128,
20404 IX86_BUILTIN_PMOVZXBD128,
20405 IX86_BUILTIN_PMOVZXBQ128,
20406 IX86_BUILTIN_PMOVZXWD128,
20407 IX86_BUILTIN_PMOVZXWQ128,
20408 IX86_BUILTIN_PMOVZXDQ128,
20410 IX86_BUILTIN_PMULDQ128,
20411 IX86_BUILTIN_PMULLD128,
20413 IX86_BUILTIN_ROUNDPD,
20414 IX86_BUILTIN_ROUNDPS,
20415 IX86_BUILTIN_ROUNDSD,
20416 IX86_BUILTIN_ROUNDSS,
20418 IX86_BUILTIN_PTESTZ,
20419 IX86_BUILTIN_PTESTC,
20420 IX86_BUILTIN_PTESTNZC,
20422 IX86_BUILTIN_VEC_INIT_V2SI,
20423 IX86_BUILTIN_VEC_INIT_V4HI,
20424 IX86_BUILTIN_VEC_INIT_V8QI,
20425 IX86_BUILTIN_VEC_EXT_V2DF,
20426 IX86_BUILTIN_VEC_EXT_V2DI,
20427 IX86_BUILTIN_VEC_EXT_V4SF,
20428 IX86_BUILTIN_VEC_EXT_V4SI,
20429 IX86_BUILTIN_VEC_EXT_V8HI,
20430 IX86_BUILTIN_VEC_EXT_V2SI,
20431 IX86_BUILTIN_VEC_EXT_V4HI,
20432 IX86_BUILTIN_VEC_EXT_V16QI,
20433 IX86_BUILTIN_VEC_SET_V2DI,
20434 IX86_BUILTIN_VEC_SET_V4SF,
20435 IX86_BUILTIN_VEC_SET_V4SI,
20436 IX86_BUILTIN_VEC_SET_V8HI,
20437 IX86_BUILTIN_VEC_SET_V4HI,
20438 IX86_BUILTIN_VEC_SET_V16QI,
20440 IX86_BUILTIN_VEC_PACK_SFIX,
20443 IX86_BUILTIN_CRC32QI,
20444 IX86_BUILTIN_CRC32HI,
20445 IX86_BUILTIN_CRC32SI,
20446 IX86_BUILTIN_CRC32DI,
20448 IX86_BUILTIN_PCMPESTRI128,
20449 IX86_BUILTIN_PCMPESTRM128,
20450 IX86_BUILTIN_PCMPESTRA128,
20451 IX86_BUILTIN_PCMPESTRC128,
20452 IX86_BUILTIN_PCMPESTRO128,
20453 IX86_BUILTIN_PCMPESTRS128,
20454 IX86_BUILTIN_PCMPESTRZ128,
20455 IX86_BUILTIN_PCMPISTRI128,
20456 IX86_BUILTIN_PCMPISTRM128,
20457 IX86_BUILTIN_PCMPISTRA128,
20458 IX86_BUILTIN_PCMPISTRC128,
20459 IX86_BUILTIN_PCMPISTRO128,
20460 IX86_BUILTIN_PCMPISTRS128,
20461 IX86_BUILTIN_PCMPISTRZ128,
20463 IX86_BUILTIN_PCMPGTQ,
20465 /* AES instructions */
20466 IX86_BUILTIN_AESENC128,
20467 IX86_BUILTIN_AESENCLAST128,
20468 IX86_BUILTIN_AESDEC128,
20469 IX86_BUILTIN_AESDECLAST128,
20470 IX86_BUILTIN_AESIMC128,
20471 IX86_BUILTIN_AESKEYGENASSIST128,
20473 /* PCLMUL instruction */
20474 IX86_BUILTIN_PCLMULQDQ128,
20477 IX86_BUILTIN_ADDPD256,
20478 IX86_BUILTIN_ADDPS256,
20479 IX86_BUILTIN_ADDSUBPD256,
20480 IX86_BUILTIN_ADDSUBPS256,
20481 IX86_BUILTIN_ANDPD256,
20482 IX86_BUILTIN_ANDPS256,
20483 IX86_BUILTIN_ANDNPD256,
20484 IX86_BUILTIN_ANDNPS256,
20485 IX86_BUILTIN_BLENDPD256,
20486 IX86_BUILTIN_BLENDPS256,
20487 IX86_BUILTIN_BLENDVPD256,
20488 IX86_BUILTIN_BLENDVPS256,
20489 IX86_BUILTIN_DIVPD256,
20490 IX86_BUILTIN_DIVPS256,
20491 IX86_BUILTIN_DPPS256,
20492 IX86_BUILTIN_HADDPD256,
20493 IX86_BUILTIN_HADDPS256,
20494 IX86_BUILTIN_HSUBPD256,
20495 IX86_BUILTIN_HSUBPS256,
20496 IX86_BUILTIN_MAXPD256,
20497 IX86_BUILTIN_MAXPS256,
20498 IX86_BUILTIN_MINPD256,
20499 IX86_BUILTIN_MINPS256,
20500 IX86_BUILTIN_MULPD256,
20501 IX86_BUILTIN_MULPS256,
20502 IX86_BUILTIN_ORPD256,
20503 IX86_BUILTIN_ORPS256,
20504 IX86_BUILTIN_SHUFPD256,
20505 IX86_BUILTIN_SHUFPS256,
20506 IX86_BUILTIN_SUBPD256,
20507 IX86_BUILTIN_SUBPS256,
20508 IX86_BUILTIN_XORPD256,
20509 IX86_BUILTIN_XORPS256,
20510 IX86_BUILTIN_CMPSD,
20511 IX86_BUILTIN_CMPSS,
20512 IX86_BUILTIN_CMPPD,
20513 IX86_BUILTIN_CMPPS,
20514 IX86_BUILTIN_CMPPD256,
20515 IX86_BUILTIN_CMPPS256,
20516 IX86_BUILTIN_CVTDQ2PD256,
20517 IX86_BUILTIN_CVTDQ2PS256,
20518 IX86_BUILTIN_CVTPD2PS256,
20519 IX86_BUILTIN_CVTPS2DQ256,
20520 IX86_BUILTIN_CVTPS2PD256,
20521 IX86_BUILTIN_CVTTPD2DQ256,
20522 IX86_BUILTIN_CVTPD2DQ256,
20523 IX86_BUILTIN_CVTTPS2DQ256,
20524 IX86_BUILTIN_EXTRACTF128PD256,
20525 IX86_BUILTIN_EXTRACTF128PS256,
20526 IX86_BUILTIN_EXTRACTF128SI256,
20527 IX86_BUILTIN_VZEROALL,
20528 IX86_BUILTIN_VZEROUPPER,
20529 IX86_BUILTIN_VZEROUPPER_REX64,
20530 IX86_BUILTIN_VPERMILVARPD,
20531 IX86_BUILTIN_VPERMILVARPS,
20532 IX86_BUILTIN_VPERMILVARPD256,
20533 IX86_BUILTIN_VPERMILVARPS256,
20534 IX86_BUILTIN_VPERMILPD,
20535 IX86_BUILTIN_VPERMILPS,
20536 IX86_BUILTIN_VPERMILPD256,
20537 IX86_BUILTIN_VPERMILPS256,
20538 IX86_BUILTIN_VPERM2F128PD256,
20539 IX86_BUILTIN_VPERM2F128PS256,
20540 IX86_BUILTIN_VPERM2F128SI256,
20541 IX86_BUILTIN_VBROADCASTSS,
20542 IX86_BUILTIN_VBROADCASTSD256,
20543 IX86_BUILTIN_VBROADCASTSS256,
20544 IX86_BUILTIN_VBROADCASTPD256,
20545 IX86_BUILTIN_VBROADCASTPS256,
20546 IX86_BUILTIN_VINSERTF128PD256,
20547 IX86_BUILTIN_VINSERTF128PS256,
20548 IX86_BUILTIN_VINSERTF128SI256,
20549 IX86_BUILTIN_LOADUPD256,
20550 IX86_BUILTIN_LOADUPS256,
20551 IX86_BUILTIN_STOREUPD256,
20552 IX86_BUILTIN_STOREUPS256,
20553 IX86_BUILTIN_LDDQU256,
20554 IX86_BUILTIN_MOVNTDQ256,
20555 IX86_BUILTIN_MOVNTPD256,
20556 IX86_BUILTIN_MOVNTPS256,
20557 IX86_BUILTIN_LOADDQU256,
20558 IX86_BUILTIN_STOREDQU256,
20559 IX86_BUILTIN_MASKLOADPD,
20560 IX86_BUILTIN_MASKLOADPS,
20561 IX86_BUILTIN_MASKSTOREPD,
20562 IX86_BUILTIN_MASKSTOREPS,
20563 IX86_BUILTIN_MASKLOADPD256,
20564 IX86_BUILTIN_MASKLOADPS256,
20565 IX86_BUILTIN_MASKSTOREPD256,
20566 IX86_BUILTIN_MASKSTOREPS256,
20567 IX86_BUILTIN_MOVSHDUP256,
20568 IX86_BUILTIN_MOVSLDUP256,
20569 IX86_BUILTIN_MOVDDUP256,
20571 IX86_BUILTIN_SQRTPD256,
20572 IX86_BUILTIN_SQRTPS256,
20573 IX86_BUILTIN_SQRTPS_NR256,
20574 IX86_BUILTIN_RSQRTPS256,
20575 IX86_BUILTIN_RSQRTPS_NR256,
20577 IX86_BUILTIN_RCPPS256,
20579 IX86_BUILTIN_ROUNDPD256,
20580 IX86_BUILTIN_ROUNDPS256,
20582 IX86_BUILTIN_UNPCKHPD256,
20583 IX86_BUILTIN_UNPCKLPD256,
20584 IX86_BUILTIN_UNPCKHPS256,
20585 IX86_BUILTIN_UNPCKLPS256,
20587 IX86_BUILTIN_SI256_SI,
20588 IX86_BUILTIN_PS256_PS,
20589 IX86_BUILTIN_PD256_PD,
20590 IX86_BUILTIN_SI_SI256,
20591 IX86_BUILTIN_PS_PS256,
20592 IX86_BUILTIN_PD_PD256,
20594 IX86_BUILTIN_VTESTZPD,
20595 IX86_BUILTIN_VTESTCPD,
20596 IX86_BUILTIN_VTESTNZCPD,
20597 IX86_BUILTIN_VTESTZPS,
20598 IX86_BUILTIN_VTESTCPS,
20599 IX86_BUILTIN_VTESTNZCPS,
20600 IX86_BUILTIN_VTESTZPD256,
20601 IX86_BUILTIN_VTESTCPD256,
20602 IX86_BUILTIN_VTESTNZCPD256,
20603 IX86_BUILTIN_VTESTZPS256,
20604 IX86_BUILTIN_VTESTCPS256,
20605 IX86_BUILTIN_VTESTNZCPS256,
20606 IX86_BUILTIN_PTESTZ256,
20607 IX86_BUILTIN_PTESTC256,
20608 IX86_BUILTIN_PTESTNZC256,
20610 IX86_BUILTIN_MOVMSKPD256,
20611 IX86_BUILTIN_MOVMSKPS256,
20613 /* TFmode support builtins. */
20615 IX86_BUILTIN_HUGE_VALQ,
20616 IX86_BUILTIN_FABSQ,
20617 IX86_BUILTIN_COPYSIGNQ,
20619 /* Vectorizer support builtins. */
20620 IX86_BUILTIN_CPYSGNPS,
20621 IX86_BUILTIN_CPYSGNPD,
20623 IX86_BUILTIN_CVTUDQ2PS,
20628 /* Table for the ix86 builtin decls. */
20629 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20631 /* Table of all of the builtin functions that are possible with different ISA's
20632 but are waiting to be built until a function is declared to use that
20634 struct GTY(()) builtin_isa {
20635 tree type; /* builtin type to use in the declaration */
20636 const char *name; /* function name */
20637 int isa; /* isa_flags this builtin is defined for */
20638 bool const_p; /* true if the declaration is constant */
20641 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20644 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20645 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20646 * function decl in the ix86_builtins array. Returns the function decl or
20647 * NULL_TREE, if the builtin was not added.
20649 * If the front end has a special hook for builtin functions, delay adding
20650 * builtin functions that aren't in the current ISA until the ISA is changed
20651 * with function specific optimization. Doing so, can save about 300K for the
20652 * default compiler. When the builtin is expanded, check at that time whether
20655 * If the front end doesn't have a special hook, record all builtins, even if
20656 * it isn't an instruction set in the current ISA in case the user uses
20657 * function specific options for a different ISA, so that we don't get scope
20658 * errors if a builtin is added in the middle of a function scope. */
20661 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20663 tree decl = NULL_TREE;
20665 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20667 ix86_builtins_isa[(int) code].isa = mask;
20669 if ((mask & ix86_isa_flags) != 0
20670 || (lang_hooks.builtin_function
20671 == lang_hooks.builtin_function_ext_scope))
20674 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20676 ix86_builtins[(int) code] = decl;
20677 ix86_builtins_isa[(int) code].type = NULL_TREE;
20681 ix86_builtins[(int) code] = NULL_TREE;
20682 ix86_builtins_isa[(int) code].const_p = false;
20683 ix86_builtins_isa[(int) code].type = type;
20684 ix86_builtins_isa[(int) code].name = name;
20691 /* Like def_builtin, but also marks the function decl "const". */
20694 def_builtin_const (int mask, const char *name, tree type,
20695 enum ix86_builtins code)
20697 tree decl = def_builtin (mask, name, type, code);
20699 TREE_READONLY (decl) = 1;
20701 ix86_builtins_isa[(int) code].const_p = true;
20706 /* Add any new builtin functions for a given ISA that may not have been
20707 declared. This saves a bit of space compared to adding all of the
20708 declarations to the tree, even if we didn't use them. */
20711 ix86_add_new_builtins (int isa)
20716 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20718 if ((ix86_builtins_isa[i].isa & isa) != 0
20719 && ix86_builtins_isa[i].type != NULL_TREE)
20721 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20722 ix86_builtins_isa[i].type,
20723 i, BUILT_IN_MD, NULL,
20726 ix86_builtins[i] = decl;
20727 ix86_builtins_isa[i].type = NULL_TREE;
20728 if (ix86_builtins_isa[i].const_p)
20729 TREE_READONLY (decl) = 1;
20734 /* Bits for builtin_description.flag. */
20736 /* Set when we don't support the comparison natively, and should
20737 swap_comparison in order to support it. */
20738 #define BUILTIN_DESC_SWAP_OPERANDS 1
20740 struct builtin_description
20742 const unsigned int mask;
20743 const enum insn_code icode;
20744 const char *const name;
20745 const enum ix86_builtins code;
20746 const enum rtx_code comparison;
20750 static const struct builtin_description bdesc_comi[] =
20752 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20753 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20754 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20755 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20756 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20757 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20758 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20759 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20760 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20761 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20762 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20763 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20764 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20765 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20766 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20767 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20768 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20769 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20770 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20771 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20772 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20773 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20774 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20775 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20778 static const struct builtin_description bdesc_pcmpestr[] =
20781 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20782 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20783 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20784 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20785 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20786 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20787 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20790 static const struct builtin_description bdesc_pcmpistr[] =
20793 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20794 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20795 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20796 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20797 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20798 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20799 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20802 /* Special builtin types */
20803 enum ix86_special_builtin_type
20805 SPECIAL_FTYPE_UNKNOWN,
20808 UINT64_FTYPE_PUNSIGNED,
20809 V32QI_FTYPE_PCCHAR,
20810 V16QI_FTYPE_PCCHAR,
20812 V8SF_FTYPE_PCFLOAT,
20814 V4DF_FTYPE_PCDOUBLE,
20815 V4SF_FTYPE_PCFLOAT,
20816 V2DF_FTYPE_PCDOUBLE,
20817 V8SF_FTYPE_PCV8SF_V8SF,
20818 V4DF_FTYPE_PCV4DF_V4DF,
20819 V4SF_FTYPE_V4SF_PCV2SF,
20820 V4SF_FTYPE_PCV4SF_V4SF,
20821 V2DF_FTYPE_V2DF_PCDOUBLE,
20822 V2DF_FTYPE_PCV2DF_V2DF,
20824 VOID_FTYPE_PV2SF_V4SF,
20825 VOID_FTYPE_PV4DI_V4DI,
20826 VOID_FTYPE_PV2DI_V2DI,
20827 VOID_FTYPE_PCHAR_V32QI,
20828 VOID_FTYPE_PCHAR_V16QI,
20829 VOID_FTYPE_PFLOAT_V8SF,
20830 VOID_FTYPE_PFLOAT_V4SF,
20831 VOID_FTYPE_PDOUBLE_V4DF,
20832 VOID_FTYPE_PDOUBLE_V2DF,
20834 VOID_FTYPE_PINT_INT,
20835 VOID_FTYPE_PV8SF_V8SF_V8SF,
20836 VOID_FTYPE_PV4DF_V4DF_V4DF,
20837 VOID_FTYPE_PV4SF_V4SF_V4SF,
20838 VOID_FTYPE_PV2DF_V2DF_V2DF
20841 /* Builtin types */
20842 enum ix86_builtin_type
20845 FLOAT128_FTYPE_FLOAT128,
20847 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20848 INT_FTYPE_V8SF_V8SF_PTEST,
20849 INT_FTYPE_V4DI_V4DI_PTEST,
20850 INT_FTYPE_V4DF_V4DF_PTEST,
20851 INT_FTYPE_V4SF_V4SF_PTEST,
20852 INT_FTYPE_V2DI_V2DI_PTEST,
20853 INT_FTYPE_V2DF_V2DF_PTEST,
20888 V4SF_FTYPE_V4SF_VEC_MERGE,
20897 V2DF_FTYPE_V2DF_VEC_MERGE,
20908 V16QI_FTYPE_V16QI_V16QI,
20909 V16QI_FTYPE_V8HI_V8HI,
20910 V8QI_FTYPE_V8QI_V8QI,
20911 V8QI_FTYPE_V4HI_V4HI,
20912 V8HI_FTYPE_V8HI_V8HI,
20913 V8HI_FTYPE_V8HI_V8HI_COUNT,
20914 V8HI_FTYPE_V16QI_V16QI,
20915 V8HI_FTYPE_V4SI_V4SI,
20916 V8HI_FTYPE_V8HI_SI_COUNT,
20917 V8SF_FTYPE_V8SF_V8SF,
20918 V8SF_FTYPE_V8SF_V8SI,
20919 V4SI_FTYPE_V4SI_V4SI,
20920 V4SI_FTYPE_V4SI_V4SI_COUNT,
20921 V4SI_FTYPE_V8HI_V8HI,
20922 V4SI_FTYPE_V4SF_V4SF,
20923 V4SI_FTYPE_V2DF_V2DF,
20924 V4SI_FTYPE_V4SI_SI_COUNT,
20925 V4HI_FTYPE_V4HI_V4HI,
20926 V4HI_FTYPE_V4HI_V4HI_COUNT,
20927 V4HI_FTYPE_V8QI_V8QI,
20928 V4HI_FTYPE_V2SI_V2SI,
20929 V4HI_FTYPE_V4HI_SI_COUNT,
20930 V4DF_FTYPE_V4DF_V4DF,
20931 V4DF_FTYPE_V4DF_V4DI,
20932 V4SF_FTYPE_V4SF_V4SF,
20933 V4SF_FTYPE_V4SF_V4SF_SWAP,
20934 V4SF_FTYPE_V4SF_V4SI,
20935 V4SF_FTYPE_V4SF_V2SI,
20936 V4SF_FTYPE_V4SF_V2DF,
20937 V4SF_FTYPE_V4SF_DI,
20938 V4SF_FTYPE_V4SF_SI,
20939 V2DI_FTYPE_V2DI_V2DI,
20940 V2DI_FTYPE_V2DI_V2DI_COUNT,
20941 V2DI_FTYPE_V16QI_V16QI,
20942 V2DI_FTYPE_V4SI_V4SI,
20943 V2DI_FTYPE_V2DI_V16QI,
20944 V2DI_FTYPE_V2DF_V2DF,
20945 V2DI_FTYPE_V2DI_SI_COUNT,
20946 V2SI_FTYPE_V2SI_V2SI,
20947 V2SI_FTYPE_V2SI_V2SI_COUNT,
20948 V2SI_FTYPE_V4HI_V4HI,
20949 V2SI_FTYPE_V2SF_V2SF,
20950 V2SI_FTYPE_V2SI_SI_COUNT,
20951 V2DF_FTYPE_V2DF_V2DF,
20952 V2DF_FTYPE_V2DF_V2DF_SWAP,
20953 V2DF_FTYPE_V2DF_V4SF,
20954 V2DF_FTYPE_V2DF_V2DI,
20955 V2DF_FTYPE_V2DF_DI,
20956 V2DF_FTYPE_V2DF_SI,
20957 V2SF_FTYPE_V2SF_V2SF,
20958 V1DI_FTYPE_V1DI_V1DI,
20959 V1DI_FTYPE_V1DI_V1DI_COUNT,
20960 V1DI_FTYPE_V8QI_V8QI,
20961 V1DI_FTYPE_V2SI_V2SI,
20962 V1DI_FTYPE_V1DI_SI_COUNT,
20963 UINT64_FTYPE_UINT64_UINT64,
20964 UINT_FTYPE_UINT_UINT,
20965 UINT_FTYPE_UINT_USHORT,
20966 UINT_FTYPE_UINT_UCHAR,
20967 UINT16_FTYPE_UINT16_INT,
20968 UINT8_FTYPE_UINT8_INT,
20969 V8HI_FTYPE_V8HI_INT,
20970 V4SI_FTYPE_V4SI_INT,
20971 V4HI_FTYPE_V4HI_INT,
20972 V8SF_FTYPE_V8SF_INT,
20973 V4SI_FTYPE_V8SI_INT,
20974 V4SF_FTYPE_V8SF_INT,
20975 V2DF_FTYPE_V4DF_INT,
20976 V4DF_FTYPE_V4DF_INT,
20977 V4SF_FTYPE_V4SF_INT,
20978 V2DI_FTYPE_V2DI_INT,
20979 V2DI2TI_FTYPE_V2DI_INT,
20980 V2DF_FTYPE_V2DF_INT,
20981 V16QI_FTYPE_V16QI_V16QI_V16QI,
20982 V8SF_FTYPE_V8SF_V8SF_V8SF,
20983 V4DF_FTYPE_V4DF_V4DF_V4DF,
20984 V4SF_FTYPE_V4SF_V4SF_V4SF,
20985 V2DF_FTYPE_V2DF_V2DF_V2DF,
20986 V16QI_FTYPE_V16QI_V16QI_INT,
20987 V8SI_FTYPE_V8SI_V8SI_INT,
20988 V8SI_FTYPE_V8SI_V4SI_INT,
20989 V8HI_FTYPE_V8HI_V8HI_INT,
20990 V8SF_FTYPE_V8SF_V8SF_INT,
20991 V8SF_FTYPE_V8SF_V4SF_INT,
20992 V4SI_FTYPE_V4SI_V4SI_INT,
20993 V4DF_FTYPE_V4DF_V4DF_INT,
20994 V4DF_FTYPE_V4DF_V2DF_INT,
20995 V4SF_FTYPE_V4SF_V4SF_INT,
20996 V2DI_FTYPE_V2DI_V2DI_INT,
20997 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20998 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20999 V2DF_FTYPE_V2DF_V2DF_INT,
21000 V2DI_FTYPE_V2DI_UINT_UINT,
21001 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
21004 /* Special builtins with variable number of arguments. */
21005 static const struct builtin_description bdesc_special_args[] =
21007 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtsc, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
21008 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdtscp, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
21011 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21014 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
21017 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21018 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21019 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21022 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
21023 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21024 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
21026 /* SSE or 3DNow!A */
21027 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21028 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
21031 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21032 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
21033 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21034 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
21035 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
21037 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
21038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
21039 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21042 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
21045 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
21048 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
21051 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
21052 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21055 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21056 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21057 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21060 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21063 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21065 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21066 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21068 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21069 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21070 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21071 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21073 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21074 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21075 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21077 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21078 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21079 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21080 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21081 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21082 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21083 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21084 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21087 /* Builtins with variable number of arguments. */
21088 static const struct builtin_description bdesc_args[] =
21090 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
21091 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
21092 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rdpmc, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
21093 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21094 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21095 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
21096 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
21099 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21100 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21101 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21102 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21103 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21104 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21106 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21107 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21108 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21109 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21110 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21111 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21112 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21113 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21115 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21116 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21118 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21119 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21120 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21121 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21123 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21124 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21125 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21126 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21127 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21128 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21130 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21131 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21132 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21133 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21134 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21135 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21137 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21138 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21139 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21141 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21143 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21144 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21145 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21146 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21148 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21150 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21151 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21152 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21153 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21154 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21155 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21157 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21158 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21159 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21160 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21163 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21164 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21165 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21166 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21168 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21169 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21170 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21171 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21172 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21173 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21174 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21175 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21176 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21177 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21178 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21179 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21180 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21181 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21182 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21185 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21186 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21187 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21188 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21189 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21190 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21193 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21194 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21195 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21196 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21197 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21198 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21199 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21200 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21201 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21202 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21203 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21204 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21206 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21208 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21209 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21210 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21212 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21213 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21214 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21217 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21218 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21219 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21220 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21221 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21222 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21223 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21224 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21225 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21226 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21227 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21228 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21229 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21230 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21231 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21232 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21233 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21234 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21235 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21236 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21237 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21238 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21240 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21241 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21242 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21243 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21245 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21247 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21248 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21250 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21254 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21255 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21256 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21258 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21259 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21260 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21262 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21264 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21265 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21266 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21268 /* SSE MMX or 3Dnow!A */
21269 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21270 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21271 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21273 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21274 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21275 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21276 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21278 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21279 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21281 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21284 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21286 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21287 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21288 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21289 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21290 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21291 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtudq2ps, "__builtin_ia32_cvtudq2ps", IX86_BUILTIN_CVTUDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21293 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21294 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21295 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21296 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21297 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21299 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21303 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21304 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21310 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21311 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21312 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21313 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21325 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21327 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21329 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21330 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21332 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21335 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21341 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21345 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21347 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21348 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21350 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21352 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21353 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21356 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21358 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21359 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21360 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21361 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21362 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21363 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21364 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21365 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21367 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21368 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21369 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21370 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21371 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21372 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21373 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21374 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21376 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21377 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21379 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21380 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21381 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21382 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21390 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21392 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21394 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21395 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21396 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21397 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21400 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21403 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21408 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21412 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21415 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21416 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21418 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21420 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21421 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21422 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21423 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21425 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21426 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21427 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21428 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21429 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21430 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21431 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21433 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21434 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21435 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21436 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21437 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21438 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21439 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21441 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21442 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21443 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21444 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21446 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21447 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21448 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21452 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21453 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21455 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21458 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21459 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21462 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21463 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21465 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21466 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21467 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21468 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21469 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21470 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21473 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21474 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21475 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21476 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21477 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21478 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21480 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21481 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21482 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21483 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21484 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21485 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21486 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21487 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21488 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21489 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21490 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21491 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21492 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21493 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21494 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21495 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21496 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21497 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21498 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21499 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21500 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21501 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21502 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21503 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21506 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21507 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21510 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21511 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21512 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21513 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21514 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21515 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21516 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21517 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21518 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21519 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21521 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21522 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21523 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21524 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21525 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21526 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21527 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21528 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21529 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21530 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21531 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21532 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21533 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21535 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21536 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21537 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21538 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21539 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21540 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21541 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21542 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21543 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21544 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21545 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21546 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21549 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21550 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21551 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21552 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21554 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21555 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21556 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21559 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21560 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21561 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21562 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21563 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21566 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21567 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21568 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21569 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21572 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21573 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21575 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21576 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21577 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21578 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21581 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21584 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21585 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21586 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21587 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21588 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21589 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21591 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21592 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21594 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21597 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21598 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21599 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21600 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21601 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21602 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21603 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21604 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21605 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21606 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21607 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21608 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21609 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21611 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21612 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21613 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21614 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21625 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21637 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21639 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21640 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21641 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21642 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21643 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21645 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21646 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21648 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21655 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21657 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21659 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21663 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21664 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21666 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21667 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21668 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21669 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21671 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21672 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21673 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21674 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21675 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21676 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21678 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21679 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21680 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21681 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21683 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21685 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21686 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21687 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21688 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21690 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21691 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21692 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21695 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21699 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21700 in the current target ISA to allow the user to compile particular modules
21701 with different target specific options that differ from the command line
21704 ix86_init_mmx_sse_builtins (void)
21706 const struct builtin_description * d;
21709 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21710 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21711 tree V1DI_type_node
21712 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21713 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21714 tree V2DI_type_node
21715 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21716 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21717 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21718 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21719 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21720 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21721 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21723 tree pchar_type_node = build_pointer_type (char_type_node);
21724 tree pcchar_type_node
21725 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21726 tree pfloat_type_node = build_pointer_type (float_type_node);
21727 tree pcfloat_type_node
21728 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21729 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21730 tree pcv2sf_type_node
21731 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21732 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21733 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21736 tree int_ftype_v4sf_v4sf
21737 = build_function_type_list (integer_type_node,
21738 V4SF_type_node, V4SF_type_node, NULL_TREE);
21739 tree v4si_ftype_v4sf_v4sf
21740 = build_function_type_list (V4SI_type_node,
21741 V4SF_type_node, V4SF_type_node, NULL_TREE);
21742 /* MMX/SSE/integer conversions. */
21743 tree int_ftype_v4sf
21744 = build_function_type_list (integer_type_node,
21745 V4SF_type_node, NULL_TREE);
21746 tree int64_ftype_v4sf
21747 = build_function_type_list (long_long_integer_type_node,
21748 V4SF_type_node, NULL_TREE);
21749 tree int_ftype_v8qi
21750 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21751 tree v4sf_ftype_v4sf_int
21752 = build_function_type_list (V4SF_type_node,
21753 V4SF_type_node, integer_type_node, NULL_TREE);
21754 tree v4sf_ftype_v4sf_int64
21755 = build_function_type_list (V4SF_type_node,
21756 V4SF_type_node, long_long_integer_type_node,
21758 tree v4sf_ftype_v4sf_v2si
21759 = build_function_type_list (V4SF_type_node,
21760 V4SF_type_node, V2SI_type_node, NULL_TREE);
21762 /* Miscellaneous. */
21763 tree v8qi_ftype_v4hi_v4hi
21764 = build_function_type_list (V8QI_type_node,
21765 V4HI_type_node, V4HI_type_node, NULL_TREE);
21766 tree v4hi_ftype_v2si_v2si
21767 = build_function_type_list (V4HI_type_node,
21768 V2SI_type_node, V2SI_type_node, NULL_TREE);
21769 tree v4sf_ftype_v4sf_v4sf_int
21770 = build_function_type_list (V4SF_type_node,
21771 V4SF_type_node, V4SF_type_node,
21772 integer_type_node, NULL_TREE);
21773 tree v2si_ftype_v4hi_v4hi
21774 = build_function_type_list (V2SI_type_node,
21775 V4HI_type_node, V4HI_type_node, NULL_TREE);
21776 tree v4hi_ftype_v4hi_int
21777 = build_function_type_list (V4HI_type_node,
21778 V4HI_type_node, integer_type_node, NULL_TREE);
21779 tree v2si_ftype_v2si_int
21780 = build_function_type_list (V2SI_type_node,
21781 V2SI_type_node, integer_type_node, NULL_TREE);
21782 tree v1di_ftype_v1di_int
21783 = build_function_type_list (V1DI_type_node,
21784 V1DI_type_node, integer_type_node, NULL_TREE);
21786 tree void_ftype_void
21787 = build_function_type (void_type_node, void_list_node);
21788 tree void_ftype_unsigned
21789 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
21790 tree void_ftype_unsigned_unsigned
21791 = build_function_type_list (void_type_node, unsigned_type_node,
21792 unsigned_type_node, NULL_TREE);
21793 tree void_ftype_pcvoid_unsigned_unsigned
21794 = build_function_type_list (void_type_node, const_ptr_type_node,
21795 unsigned_type_node, unsigned_type_node,
21797 tree unsigned_ftype_void
21798 = build_function_type (unsigned_type_node, void_list_node);
21799 tree v2si_ftype_v4sf
21800 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
21801 /* Loads/stores. */
21802 tree void_ftype_v8qi_v8qi_pchar
21803 = build_function_type_list (void_type_node,
21804 V8QI_type_node, V8QI_type_node,
21805 pchar_type_node, NULL_TREE);
21806 tree v4sf_ftype_pcfloat
21807 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
21808 tree v4sf_ftype_v4sf_pcv2sf
21809 = build_function_type_list (V4SF_type_node,
21810 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
21811 tree void_ftype_pv2sf_v4sf
21812 = build_function_type_list (void_type_node,
21813 pv2sf_type_node, V4SF_type_node, NULL_TREE);
21814 tree void_ftype_pfloat_v4sf
21815 = build_function_type_list (void_type_node,
21816 pfloat_type_node, V4SF_type_node, NULL_TREE);
21817 tree void_ftype_pdi_di
21818 = build_function_type_list (void_type_node,
21819 pdi_type_node, long_long_unsigned_type_node,
21821 tree void_ftype_pv2di_v2di
21822 = build_function_type_list (void_type_node,
21823 pv2di_type_node, V2DI_type_node, NULL_TREE);
21824 /* Normal vector unops. */
21825 tree v4sf_ftype_v4sf
21826 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
21827 tree v16qi_ftype_v16qi
21828 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
21829 tree v8hi_ftype_v8hi
21830 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
21831 tree v4si_ftype_v4si
21832 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
21833 tree v8qi_ftype_v8qi
21834 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
21835 tree v4hi_ftype_v4hi
21836 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
21838 /* Normal vector binops. */
21839 tree v4sf_ftype_v4sf_v4sf
21840 = build_function_type_list (V4SF_type_node,
21841 V4SF_type_node, V4SF_type_node, NULL_TREE);
21842 tree v8qi_ftype_v8qi_v8qi
21843 = build_function_type_list (V8QI_type_node,
21844 V8QI_type_node, V8QI_type_node, NULL_TREE);
21845 tree v4hi_ftype_v4hi_v4hi
21846 = build_function_type_list (V4HI_type_node,
21847 V4HI_type_node, V4HI_type_node, NULL_TREE);
21848 tree v2si_ftype_v2si_v2si
21849 = build_function_type_list (V2SI_type_node,
21850 V2SI_type_node, V2SI_type_node, NULL_TREE);
21851 tree v1di_ftype_v1di_v1di
21852 = build_function_type_list (V1DI_type_node,
21853 V1DI_type_node, V1DI_type_node, NULL_TREE);
21854 tree v1di_ftype_v1di_v1di_int
21855 = build_function_type_list (V1DI_type_node,
21856 V1DI_type_node, V1DI_type_node,
21857 integer_type_node, NULL_TREE);
21858 tree v2si_ftype_v2sf
21859 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
21860 tree v2sf_ftype_v2si
21861 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
21862 tree v2si_ftype_v2si
21863 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
21864 tree v2sf_ftype_v2sf
21865 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
21866 tree v2sf_ftype_v2sf_v2sf
21867 = build_function_type_list (V2SF_type_node,
21868 V2SF_type_node, V2SF_type_node, NULL_TREE);
21869 tree v2si_ftype_v2sf_v2sf
21870 = build_function_type_list (V2SI_type_node,
21871 V2SF_type_node, V2SF_type_node, NULL_TREE);
21872 tree pint_type_node = build_pointer_type (integer_type_node);
21873 tree pdouble_type_node = build_pointer_type (double_type_node);
21874 tree pcdouble_type_node = build_pointer_type (
21875 build_type_variant (double_type_node, 1, 0));
21876 tree int_ftype_v2df_v2df
21877 = build_function_type_list (integer_type_node,
21878 V2DF_type_node, V2DF_type_node, NULL_TREE);
21880 tree void_ftype_pcvoid
21881 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
21882 tree v4sf_ftype_v4si
21883 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
21884 tree v4si_ftype_v4sf
21885 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
21886 tree v2df_ftype_v4si
21887 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
21888 tree v4si_ftype_v2df
21889 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
21890 tree v4si_ftype_v2df_v2df
21891 = build_function_type_list (V4SI_type_node,
21892 V2DF_type_node, V2DF_type_node, NULL_TREE);
21893 tree v2si_ftype_v2df
21894 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
21895 tree v4sf_ftype_v2df
21896 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
21897 tree v2df_ftype_v2si
21898 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
21899 tree v2df_ftype_v4sf
21900 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
21901 tree int_ftype_v2df
21902 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
21903 tree int64_ftype_v2df
21904 = build_function_type_list (long_long_integer_type_node,
21905 V2DF_type_node, NULL_TREE);
21906 tree v2df_ftype_v2df_int
21907 = build_function_type_list (V2DF_type_node,
21908 V2DF_type_node, integer_type_node, NULL_TREE);
21909 tree v2df_ftype_v2df_int64
21910 = build_function_type_list (V2DF_type_node,
21911 V2DF_type_node, long_long_integer_type_node,
21913 tree v4sf_ftype_v4sf_v2df
21914 = build_function_type_list (V4SF_type_node,
21915 V4SF_type_node, V2DF_type_node, NULL_TREE);
21916 tree v2df_ftype_v2df_v4sf
21917 = build_function_type_list (V2DF_type_node,
21918 V2DF_type_node, V4SF_type_node, NULL_TREE);
21919 tree v2df_ftype_v2df_v2df_int
21920 = build_function_type_list (V2DF_type_node,
21921 V2DF_type_node, V2DF_type_node,
21924 tree v2df_ftype_v2df_pcdouble
21925 = build_function_type_list (V2DF_type_node,
21926 V2DF_type_node, pcdouble_type_node, NULL_TREE);
21927 tree void_ftype_pdouble_v2df
21928 = build_function_type_list (void_type_node,
21929 pdouble_type_node, V2DF_type_node, NULL_TREE);
21930 tree void_ftype_pint_int
21931 = build_function_type_list (void_type_node,
21932 pint_type_node, integer_type_node, NULL_TREE);
21933 tree void_ftype_v16qi_v16qi_pchar
21934 = build_function_type_list (void_type_node,
21935 V16QI_type_node, V16QI_type_node,
21936 pchar_type_node, NULL_TREE);
21937 tree v2df_ftype_pcdouble
21938 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
21939 tree v2df_ftype_v2df_v2df
21940 = build_function_type_list (V2DF_type_node,
21941 V2DF_type_node, V2DF_type_node, NULL_TREE);
21942 tree v16qi_ftype_v16qi_v16qi
21943 = build_function_type_list (V16QI_type_node,
21944 V16QI_type_node, V16QI_type_node, NULL_TREE);
21945 tree v8hi_ftype_v8hi_v8hi
21946 = build_function_type_list (V8HI_type_node,
21947 V8HI_type_node, V8HI_type_node, NULL_TREE);
21948 tree v4si_ftype_v4si_v4si
21949 = build_function_type_list (V4SI_type_node,
21950 V4SI_type_node, V4SI_type_node, NULL_TREE);
21951 tree v2di_ftype_v2di_v2di
21952 = build_function_type_list (V2DI_type_node,
21953 V2DI_type_node, V2DI_type_node, NULL_TREE);
21954 tree v2di_ftype_v2df_v2df
21955 = build_function_type_list (V2DI_type_node,
21956 V2DF_type_node, V2DF_type_node, NULL_TREE);
21957 tree v2df_ftype_v2df
21958 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
21959 tree v2di_ftype_v2di_int
21960 = build_function_type_list (V2DI_type_node,
21961 V2DI_type_node, integer_type_node, NULL_TREE);
21962 tree v2di_ftype_v2di_v2di_int
21963 = build_function_type_list (V2DI_type_node, V2DI_type_node,
21964 V2DI_type_node, integer_type_node, NULL_TREE);
21965 tree v4si_ftype_v4si_int
21966 = build_function_type_list (V4SI_type_node,
21967 V4SI_type_node, integer_type_node, NULL_TREE);
21968 tree v8hi_ftype_v8hi_int
21969 = build_function_type_list (V8HI_type_node,
21970 V8HI_type_node, integer_type_node, NULL_TREE);
21971 tree v4si_ftype_v8hi_v8hi
21972 = build_function_type_list (V4SI_type_node,
21973 V8HI_type_node, V8HI_type_node, NULL_TREE);
21974 tree v1di_ftype_v8qi_v8qi
21975 = build_function_type_list (V1DI_type_node,
21976 V8QI_type_node, V8QI_type_node, NULL_TREE);
21977 tree v1di_ftype_v2si_v2si
21978 = build_function_type_list (V1DI_type_node,
21979 V2SI_type_node, V2SI_type_node, NULL_TREE);
21980 tree v2di_ftype_v16qi_v16qi
21981 = build_function_type_list (V2DI_type_node,
21982 V16QI_type_node, V16QI_type_node, NULL_TREE);
21983 tree v2di_ftype_v4si_v4si
21984 = build_function_type_list (V2DI_type_node,
21985 V4SI_type_node, V4SI_type_node, NULL_TREE);
21986 tree int_ftype_v16qi
21987 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
21988 tree v16qi_ftype_pcchar
21989 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
21990 tree void_ftype_pchar_v16qi
21991 = build_function_type_list (void_type_node,
21992 pchar_type_node, V16QI_type_node, NULL_TREE);
21994 tree v2di_ftype_v2di_unsigned_unsigned
21995 = build_function_type_list (V2DI_type_node, V2DI_type_node,
21996 unsigned_type_node, unsigned_type_node,
21998 tree v2di_ftype_v2di_v2di_unsigned_unsigned
21999 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22000 unsigned_type_node, unsigned_type_node,
22002 tree v2di_ftype_v2di_v16qi
22003 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22005 tree v2df_ftype_v2df_v2df_v2df
22006 = build_function_type_list (V2DF_type_node,
22007 V2DF_type_node, V2DF_type_node,
22008 V2DF_type_node, NULL_TREE);
22009 tree v4sf_ftype_v4sf_v4sf_v4sf
22010 = build_function_type_list (V4SF_type_node,
22011 V4SF_type_node, V4SF_type_node,
22012 V4SF_type_node, NULL_TREE);
22013 tree v8hi_ftype_v16qi
22014 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22016 tree v4si_ftype_v16qi
22017 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22019 tree v2di_ftype_v16qi
22020 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22022 tree v4si_ftype_v8hi
22023 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22025 tree v2di_ftype_v8hi
22026 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22028 tree v2di_ftype_v4si
22029 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22031 tree v2di_ftype_pv2di
22032 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22034 tree v16qi_ftype_v16qi_v16qi_int
22035 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22036 V16QI_type_node, integer_type_node,
22038 tree v16qi_ftype_v16qi_v16qi_v16qi
22039 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22040 V16QI_type_node, V16QI_type_node,
22042 tree v8hi_ftype_v8hi_v8hi_int
22043 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22044 V8HI_type_node, integer_type_node,
22046 tree v4si_ftype_v4si_v4si_int
22047 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22048 V4SI_type_node, integer_type_node,
22050 tree int_ftype_v2di_v2di
22051 = build_function_type_list (integer_type_node,
22052 V2DI_type_node, V2DI_type_node,
22054 tree int_ftype_v16qi_int_v16qi_int_int
22055 = build_function_type_list (integer_type_node,
22062 tree v16qi_ftype_v16qi_int_v16qi_int_int
22063 = build_function_type_list (V16QI_type_node,
22070 tree int_ftype_v16qi_v16qi_int
22071 = build_function_type_list (integer_type_node,
22078 tree v2di_ftype_v2di
22079 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22081 tree v16qi_ftype_v8hi_v8hi
22082 = build_function_type_list (V16QI_type_node,
22083 V8HI_type_node, V8HI_type_node,
22085 tree v8hi_ftype_v4si_v4si
22086 = build_function_type_list (V8HI_type_node,
22087 V4SI_type_node, V4SI_type_node,
22089 tree v8hi_ftype_v16qi_v16qi
22090 = build_function_type_list (V8HI_type_node,
22091 V16QI_type_node, V16QI_type_node,
22093 tree v4hi_ftype_v8qi_v8qi
22094 = build_function_type_list (V4HI_type_node,
22095 V8QI_type_node, V8QI_type_node,
22097 tree unsigned_ftype_unsigned_uchar
22098 = build_function_type_list (unsigned_type_node,
22099 unsigned_type_node,
22100 unsigned_char_type_node,
22102 tree unsigned_ftype_unsigned_ushort
22103 = build_function_type_list (unsigned_type_node,
22104 unsigned_type_node,
22105 short_unsigned_type_node,
22107 tree unsigned_ftype_unsigned_unsigned
22108 = build_function_type_list (unsigned_type_node,
22109 unsigned_type_node,
22110 unsigned_type_node,
22112 tree uint64_ftype_uint64_uint64
22113 = build_function_type_list (long_long_unsigned_type_node,
22114 long_long_unsigned_type_node,
22115 long_long_unsigned_type_node,
22117 tree float_ftype_float
22118 = build_function_type_list (float_type_node,
22123 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22125 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22127 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22129 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22131 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22133 tree v8sf_ftype_v8sf
22134 = build_function_type_list (V8SF_type_node,
22137 tree v8si_ftype_v8sf
22138 = build_function_type_list (V8SI_type_node,
22141 tree v8sf_ftype_v8si
22142 = build_function_type_list (V8SF_type_node,
22145 tree v4si_ftype_v4df
22146 = build_function_type_list (V4SI_type_node,
22149 tree v4df_ftype_v4df
22150 = build_function_type_list (V4DF_type_node,
22153 tree v4df_ftype_v4si
22154 = build_function_type_list (V4DF_type_node,
22157 tree v4df_ftype_v4sf
22158 = build_function_type_list (V4DF_type_node,
22161 tree v4sf_ftype_v4df
22162 = build_function_type_list (V4SF_type_node,
22165 tree v8sf_ftype_v8sf_v8sf
22166 = build_function_type_list (V8SF_type_node,
22167 V8SF_type_node, V8SF_type_node,
22169 tree v4df_ftype_v4df_v4df
22170 = build_function_type_list (V4DF_type_node,
22171 V4DF_type_node, V4DF_type_node,
22173 tree v8sf_ftype_v8sf_int
22174 = build_function_type_list (V8SF_type_node,
22175 V8SF_type_node, integer_type_node,
22177 tree v4si_ftype_v8si_int
22178 = build_function_type_list (V4SI_type_node,
22179 V8SI_type_node, integer_type_node,
22181 tree v4df_ftype_v4df_int
22182 = build_function_type_list (V4DF_type_node,
22183 V4DF_type_node, integer_type_node,
22185 tree v4sf_ftype_v8sf_int
22186 = build_function_type_list (V4SF_type_node,
22187 V8SF_type_node, integer_type_node,
22189 tree v2df_ftype_v4df_int
22190 = build_function_type_list (V2DF_type_node,
22191 V4DF_type_node, integer_type_node,
22193 tree v8sf_ftype_v8sf_v8sf_int
22194 = build_function_type_list (V8SF_type_node,
22195 V8SF_type_node, V8SF_type_node,
22198 tree v8sf_ftype_v8sf_v8sf_v8sf
22199 = build_function_type_list (V8SF_type_node,
22200 V8SF_type_node, V8SF_type_node,
22203 tree v4df_ftype_v4df_v4df_v4df
22204 = build_function_type_list (V4DF_type_node,
22205 V4DF_type_node, V4DF_type_node,
22208 tree v8si_ftype_v8si_v8si_int
22209 = build_function_type_list (V8SI_type_node,
22210 V8SI_type_node, V8SI_type_node,
22213 tree v4df_ftype_v4df_v4df_int
22214 = build_function_type_list (V4DF_type_node,
22215 V4DF_type_node, V4DF_type_node,
22218 tree v8sf_ftype_pcfloat
22219 = build_function_type_list (V8SF_type_node,
22222 tree v4df_ftype_pcdouble
22223 = build_function_type_list (V4DF_type_node,
22224 pcdouble_type_node,
22226 tree pcv4sf_type_node
22227 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22228 tree pcv2df_type_node
22229 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22230 tree v8sf_ftype_pcv4sf
22231 = build_function_type_list (V8SF_type_node,
22234 tree v4df_ftype_pcv2df
22235 = build_function_type_list (V4DF_type_node,
22238 tree v32qi_ftype_pcchar
22239 = build_function_type_list (V32QI_type_node,
22242 tree void_ftype_pchar_v32qi
22243 = build_function_type_list (void_type_node,
22244 pchar_type_node, V32QI_type_node,
22246 tree v8si_ftype_v8si_v4si_int
22247 = build_function_type_list (V8SI_type_node,
22248 V8SI_type_node, V4SI_type_node,
22251 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22252 tree void_ftype_pv4di_v4di
22253 = build_function_type_list (void_type_node,
22254 pv4di_type_node, V4DI_type_node,
22256 tree v8sf_ftype_v8sf_v4sf_int
22257 = build_function_type_list (V8SF_type_node,
22258 V8SF_type_node, V4SF_type_node,
22261 tree v4df_ftype_v4df_v2df_int
22262 = build_function_type_list (V4DF_type_node,
22263 V4DF_type_node, V2DF_type_node,
22266 tree void_ftype_pfloat_v8sf
22267 = build_function_type_list (void_type_node,
22268 pfloat_type_node, V8SF_type_node,
22270 tree void_ftype_pdouble_v4df
22271 = build_function_type_list (void_type_node,
22272 pdouble_type_node, V4DF_type_node,
22274 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22275 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22276 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22277 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22278 tree pcv8sf_type_node
22279 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22280 tree pcv4df_type_node
22281 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22282 tree v8sf_ftype_pcv8sf_v8sf
22283 = build_function_type_list (V8SF_type_node,
22284 pcv8sf_type_node, V8SF_type_node,
22286 tree v4df_ftype_pcv4df_v4df
22287 = build_function_type_list (V4DF_type_node,
22288 pcv4df_type_node, V4DF_type_node,
22290 tree v4sf_ftype_pcv4sf_v4sf
22291 = build_function_type_list (V4SF_type_node,
22292 pcv4sf_type_node, V4SF_type_node,
22294 tree v2df_ftype_pcv2df_v2df
22295 = build_function_type_list (V2DF_type_node,
22296 pcv2df_type_node, V2DF_type_node,
22298 tree void_ftype_pv8sf_v8sf_v8sf
22299 = build_function_type_list (void_type_node,
22300 pv8sf_type_node, V8SF_type_node,
22303 tree void_ftype_pv4df_v4df_v4df
22304 = build_function_type_list (void_type_node,
22305 pv4df_type_node, V4DF_type_node,
22308 tree void_ftype_pv4sf_v4sf_v4sf
22309 = build_function_type_list (void_type_node,
22310 pv4sf_type_node, V4SF_type_node,
22313 tree void_ftype_pv2df_v2df_v2df
22314 = build_function_type_list (void_type_node,
22315 pv2df_type_node, V2DF_type_node,
22318 tree v4df_ftype_v2df
22319 = build_function_type_list (V4DF_type_node,
22322 tree v8sf_ftype_v4sf
22323 = build_function_type_list (V8SF_type_node,
22326 tree v8si_ftype_v4si
22327 = build_function_type_list (V8SI_type_node,
22330 tree v2df_ftype_v4df
22331 = build_function_type_list (V2DF_type_node,
22334 tree v4sf_ftype_v8sf
22335 = build_function_type_list (V4SF_type_node,
22338 tree v4si_ftype_v8si
22339 = build_function_type_list (V4SI_type_node,
22342 tree int_ftype_v4df
22343 = build_function_type_list (integer_type_node,
22346 tree int_ftype_v8sf
22347 = build_function_type_list (integer_type_node,
22350 tree int_ftype_v8sf_v8sf
22351 = build_function_type_list (integer_type_node,
22352 V8SF_type_node, V8SF_type_node,
22354 tree int_ftype_v4di_v4di
22355 = build_function_type_list (integer_type_node,
22356 V4DI_type_node, V4DI_type_node,
22358 tree int_ftype_v4df_v4df
22359 = build_function_type_list (integer_type_node,
22360 V4DF_type_node, V4DF_type_node,
22362 tree v8sf_ftype_v8sf_v8si
22363 = build_function_type_list (V8SF_type_node,
22364 V8SF_type_node, V8SI_type_node,
22366 tree v4df_ftype_v4df_v4di
22367 = build_function_type_list (V4DF_type_node,
22368 V4DF_type_node, V4DI_type_node,
22370 tree v4sf_ftype_v4sf_v4si
22371 = build_function_type_list (V4SF_type_node,
22372 V4SF_type_node, V4SI_type_node, NULL_TREE);
22373 tree v2df_ftype_v2df_v2di
22374 = build_function_type_list (V2DF_type_node,
22375 V2DF_type_node, V2DI_type_node, NULL_TREE);
22377 /* Integer intrinsics. */
22378 tree uint64_ftype_void
22379 = build_function_type (long_long_unsigned_type_node,
22382 = build_function_type_list (integer_type_node,
22383 integer_type_node, NULL_TREE);
22384 tree int64_ftype_int64
22385 = build_function_type_list (long_long_integer_type_node,
22386 long_long_integer_type_node,
22388 tree uint64_ftype_int
22389 = build_function_type_list (long_long_unsigned_type_node,
22390 integer_type_node, NULL_TREE);
22391 tree punsigned_type_node = build_pointer_type (unsigned_type_node);
22392 tree uint64_ftype_punsigned
22393 = build_function_type_list (long_long_unsigned_type_node,
22394 punsigned_type_node, NULL_TREE);
22395 tree ushort_ftype_ushort_int
22396 = build_function_type_list (short_unsigned_type_node,
22397 short_unsigned_type_node,
22400 tree uchar_ftype_uchar_int
22401 = build_function_type_list (unsigned_char_type_node,
22402 unsigned_char_type_node,
22408 /* Add all special builtins with variable number of operands. */
22409 for (i = 0, d = bdesc_special_args;
22410 i < ARRAY_SIZE (bdesc_special_args);
22418 switch ((enum ix86_special_builtin_type) d->flag)
22420 case VOID_FTYPE_VOID:
22421 type = void_ftype_void;
22423 case UINT64_FTYPE_VOID:
22424 type = uint64_ftype_void;
22426 case UINT64_FTYPE_PUNSIGNED:
22427 type = uint64_ftype_punsigned;
22429 case V32QI_FTYPE_PCCHAR:
22430 type = v32qi_ftype_pcchar;
22432 case V16QI_FTYPE_PCCHAR:
22433 type = v16qi_ftype_pcchar;
22435 case V8SF_FTYPE_PCV4SF:
22436 type = v8sf_ftype_pcv4sf;
22438 case V8SF_FTYPE_PCFLOAT:
22439 type = v8sf_ftype_pcfloat;
22441 case V4DF_FTYPE_PCV2DF:
22442 type = v4df_ftype_pcv2df;
22444 case V4DF_FTYPE_PCDOUBLE:
22445 type = v4df_ftype_pcdouble;
22447 case V4SF_FTYPE_PCFLOAT:
22448 type = v4sf_ftype_pcfloat;
22450 case V2DI_FTYPE_PV2DI:
22451 type = v2di_ftype_pv2di;
22453 case V2DF_FTYPE_PCDOUBLE:
22454 type = v2df_ftype_pcdouble;
22456 case V8SF_FTYPE_PCV8SF_V8SF:
22457 type = v8sf_ftype_pcv8sf_v8sf;
22459 case V4DF_FTYPE_PCV4DF_V4DF:
22460 type = v4df_ftype_pcv4df_v4df;
22462 case V4SF_FTYPE_V4SF_PCV2SF:
22463 type = v4sf_ftype_v4sf_pcv2sf;
22465 case V4SF_FTYPE_PCV4SF_V4SF:
22466 type = v4sf_ftype_pcv4sf_v4sf;
22468 case V2DF_FTYPE_V2DF_PCDOUBLE:
22469 type = v2df_ftype_v2df_pcdouble;
22471 case V2DF_FTYPE_PCV2DF_V2DF:
22472 type = v2df_ftype_pcv2df_v2df;
22474 case VOID_FTYPE_PV2SF_V4SF:
22475 type = void_ftype_pv2sf_v4sf;
22477 case VOID_FTYPE_PV4DI_V4DI:
22478 type = void_ftype_pv4di_v4di;
22480 case VOID_FTYPE_PV2DI_V2DI:
22481 type = void_ftype_pv2di_v2di;
22483 case VOID_FTYPE_PCHAR_V32QI:
22484 type = void_ftype_pchar_v32qi;
22486 case VOID_FTYPE_PCHAR_V16QI:
22487 type = void_ftype_pchar_v16qi;
22489 case VOID_FTYPE_PFLOAT_V8SF:
22490 type = void_ftype_pfloat_v8sf;
22492 case VOID_FTYPE_PFLOAT_V4SF:
22493 type = void_ftype_pfloat_v4sf;
22495 case VOID_FTYPE_PDOUBLE_V4DF:
22496 type = void_ftype_pdouble_v4df;
22498 case VOID_FTYPE_PDOUBLE_V2DF:
22499 type = void_ftype_pdouble_v2df;
22501 case VOID_FTYPE_PDI_DI:
22502 type = void_ftype_pdi_di;
22504 case VOID_FTYPE_PINT_INT:
22505 type = void_ftype_pint_int;
22507 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22508 type = void_ftype_pv8sf_v8sf_v8sf;
22510 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22511 type = void_ftype_pv4df_v4df_v4df;
22513 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22514 type = void_ftype_pv4sf_v4sf_v4sf;
22516 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22517 type = void_ftype_pv2df_v2df_v2df;
22520 gcc_unreachable ();
22523 def_builtin (d->mask, d->name, type, d->code);
22526 /* Add all builtins with variable number of operands. */
22527 for (i = 0, d = bdesc_args;
22528 i < ARRAY_SIZE (bdesc_args);
22536 switch ((enum ix86_builtin_type) d->flag)
22538 case FLOAT_FTYPE_FLOAT:
22539 type = float_ftype_float;
22541 case INT_FTYPE_V8SF_V8SF_PTEST:
22542 type = int_ftype_v8sf_v8sf;
22544 case INT_FTYPE_V4DI_V4DI_PTEST:
22545 type = int_ftype_v4di_v4di;
22547 case INT_FTYPE_V4DF_V4DF_PTEST:
22548 type = int_ftype_v4df_v4df;
22550 case INT_FTYPE_V4SF_V4SF_PTEST:
22551 type = int_ftype_v4sf_v4sf;
22553 case INT_FTYPE_V2DI_V2DI_PTEST:
22554 type = int_ftype_v2di_v2di;
22556 case INT_FTYPE_V2DF_V2DF_PTEST:
22557 type = int_ftype_v2df_v2df;
22559 case INT_FTYPE_INT:
22560 type = int_ftype_int;
22562 case UINT64_FTYPE_INT:
22563 type = uint64_ftype_int;
22565 case INT64_FTYPE_INT64:
22566 type = int64_ftype_int64;
22568 case INT64_FTYPE_V4SF:
22569 type = int64_ftype_v4sf;
22571 case INT64_FTYPE_V2DF:
22572 type = int64_ftype_v2df;
22574 case INT_FTYPE_V16QI:
22575 type = int_ftype_v16qi;
22577 case INT_FTYPE_V8QI:
22578 type = int_ftype_v8qi;
22580 case INT_FTYPE_V8SF:
22581 type = int_ftype_v8sf;
22583 case INT_FTYPE_V4DF:
22584 type = int_ftype_v4df;
22586 case INT_FTYPE_V4SF:
22587 type = int_ftype_v4sf;
22589 case INT_FTYPE_V2DF:
22590 type = int_ftype_v2df;
22592 case V16QI_FTYPE_V16QI:
22593 type = v16qi_ftype_v16qi;
22595 case V8SI_FTYPE_V8SF:
22596 type = v8si_ftype_v8sf;
22598 case V8SI_FTYPE_V4SI:
22599 type = v8si_ftype_v4si;
22601 case V8HI_FTYPE_V8HI:
22602 type = v8hi_ftype_v8hi;
22604 case V8HI_FTYPE_V16QI:
22605 type = v8hi_ftype_v16qi;
22607 case V8QI_FTYPE_V8QI:
22608 type = v8qi_ftype_v8qi;
22610 case V8SF_FTYPE_V8SF:
22611 type = v8sf_ftype_v8sf;
22613 case V8SF_FTYPE_V8SI:
22614 type = v8sf_ftype_v8si;
22616 case V8SF_FTYPE_V4SF:
22617 type = v8sf_ftype_v4sf;
22619 case V4SI_FTYPE_V4DF:
22620 type = v4si_ftype_v4df;
22622 case V4SI_FTYPE_V4SI:
22623 type = v4si_ftype_v4si;
22625 case V4SI_FTYPE_V16QI:
22626 type = v4si_ftype_v16qi;
22628 case V4SI_FTYPE_V8SI:
22629 type = v4si_ftype_v8si;
22631 case V4SI_FTYPE_V8HI:
22632 type = v4si_ftype_v8hi;
22634 case V4SI_FTYPE_V4SF:
22635 type = v4si_ftype_v4sf;
22637 case V4SI_FTYPE_V2DF:
22638 type = v4si_ftype_v2df;
22640 case V4HI_FTYPE_V4HI:
22641 type = v4hi_ftype_v4hi;
22643 case V4DF_FTYPE_V4DF:
22644 type = v4df_ftype_v4df;
22646 case V4DF_FTYPE_V4SI:
22647 type = v4df_ftype_v4si;
22649 case V4DF_FTYPE_V4SF:
22650 type = v4df_ftype_v4sf;
22652 case V4DF_FTYPE_V2DF:
22653 type = v4df_ftype_v2df;
22655 case V4SF_FTYPE_V4SF:
22656 case V4SF_FTYPE_V4SF_VEC_MERGE:
22657 type = v4sf_ftype_v4sf;
22659 case V4SF_FTYPE_V8SF:
22660 type = v4sf_ftype_v8sf;
22662 case V4SF_FTYPE_V4SI:
22663 type = v4sf_ftype_v4si;
22665 case V4SF_FTYPE_V4DF:
22666 type = v4sf_ftype_v4df;
22668 case V4SF_FTYPE_V2DF:
22669 type = v4sf_ftype_v2df;
22671 case V2DI_FTYPE_V2DI:
22672 type = v2di_ftype_v2di;
22674 case V2DI_FTYPE_V16QI:
22675 type = v2di_ftype_v16qi;
22677 case V2DI_FTYPE_V8HI:
22678 type = v2di_ftype_v8hi;
22680 case V2DI_FTYPE_V4SI:
22681 type = v2di_ftype_v4si;
22683 case V2SI_FTYPE_V2SI:
22684 type = v2si_ftype_v2si;
22686 case V2SI_FTYPE_V4SF:
22687 type = v2si_ftype_v4sf;
22689 case V2SI_FTYPE_V2DF:
22690 type = v2si_ftype_v2df;
22692 case V2SI_FTYPE_V2SF:
22693 type = v2si_ftype_v2sf;
22695 case V2DF_FTYPE_V4DF:
22696 type = v2df_ftype_v4df;
22698 case V2DF_FTYPE_V4SF:
22699 type = v2df_ftype_v4sf;
22701 case V2DF_FTYPE_V2DF:
22702 case V2DF_FTYPE_V2DF_VEC_MERGE:
22703 type = v2df_ftype_v2df;
22705 case V2DF_FTYPE_V2SI:
22706 type = v2df_ftype_v2si;
22708 case V2DF_FTYPE_V4SI:
22709 type = v2df_ftype_v4si;
22711 case V2SF_FTYPE_V2SF:
22712 type = v2sf_ftype_v2sf;
22714 case V2SF_FTYPE_V2SI:
22715 type = v2sf_ftype_v2si;
22717 case V16QI_FTYPE_V16QI_V16QI:
22718 type = v16qi_ftype_v16qi_v16qi;
22720 case V16QI_FTYPE_V8HI_V8HI:
22721 type = v16qi_ftype_v8hi_v8hi;
22723 case V8QI_FTYPE_V8QI_V8QI:
22724 type = v8qi_ftype_v8qi_v8qi;
22726 case V8QI_FTYPE_V4HI_V4HI:
22727 type = v8qi_ftype_v4hi_v4hi;
22729 case V8HI_FTYPE_V8HI_V8HI:
22730 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22731 type = v8hi_ftype_v8hi_v8hi;
22733 case V8HI_FTYPE_V16QI_V16QI:
22734 type = v8hi_ftype_v16qi_v16qi;
22736 case V8HI_FTYPE_V4SI_V4SI:
22737 type = v8hi_ftype_v4si_v4si;
22739 case V8HI_FTYPE_V8HI_SI_COUNT:
22740 type = v8hi_ftype_v8hi_int;
22742 case V8SF_FTYPE_V8SF_V8SF:
22743 type = v8sf_ftype_v8sf_v8sf;
22745 case V8SF_FTYPE_V8SF_V8SI:
22746 type = v8sf_ftype_v8sf_v8si;
22748 case V4SI_FTYPE_V4SI_V4SI:
22749 case V4SI_FTYPE_V4SI_V4SI_COUNT:
22750 type = v4si_ftype_v4si_v4si;
22752 case V4SI_FTYPE_V8HI_V8HI:
22753 type = v4si_ftype_v8hi_v8hi;
22755 case V4SI_FTYPE_V4SF_V4SF:
22756 type = v4si_ftype_v4sf_v4sf;
22758 case V4SI_FTYPE_V2DF_V2DF:
22759 type = v4si_ftype_v2df_v2df;
22761 case V4SI_FTYPE_V4SI_SI_COUNT:
22762 type = v4si_ftype_v4si_int;
22764 case V4HI_FTYPE_V4HI_V4HI:
22765 case V4HI_FTYPE_V4HI_V4HI_COUNT:
22766 type = v4hi_ftype_v4hi_v4hi;
22768 case V4HI_FTYPE_V8QI_V8QI:
22769 type = v4hi_ftype_v8qi_v8qi;
22771 case V4HI_FTYPE_V2SI_V2SI:
22772 type = v4hi_ftype_v2si_v2si;
22774 case V4HI_FTYPE_V4HI_SI_COUNT:
22775 type = v4hi_ftype_v4hi_int;
22777 case V4DF_FTYPE_V4DF_V4DF:
22778 type = v4df_ftype_v4df_v4df;
22780 case V4DF_FTYPE_V4DF_V4DI:
22781 type = v4df_ftype_v4df_v4di;
22783 case V4SF_FTYPE_V4SF_V4SF:
22784 case V4SF_FTYPE_V4SF_V4SF_SWAP:
22785 type = v4sf_ftype_v4sf_v4sf;
22787 case V4SF_FTYPE_V4SF_V4SI:
22788 type = v4sf_ftype_v4sf_v4si;
22790 case V4SF_FTYPE_V4SF_V2SI:
22791 type = v4sf_ftype_v4sf_v2si;
22793 case V4SF_FTYPE_V4SF_V2DF:
22794 type = v4sf_ftype_v4sf_v2df;
22796 case V4SF_FTYPE_V4SF_DI:
22797 type = v4sf_ftype_v4sf_int64;
22799 case V4SF_FTYPE_V4SF_SI:
22800 type = v4sf_ftype_v4sf_int;
22802 case V2DI_FTYPE_V2DI_V2DI:
22803 case V2DI_FTYPE_V2DI_V2DI_COUNT:
22804 type = v2di_ftype_v2di_v2di;
22806 case V2DI_FTYPE_V16QI_V16QI:
22807 type = v2di_ftype_v16qi_v16qi;
22809 case V2DI_FTYPE_V4SI_V4SI:
22810 type = v2di_ftype_v4si_v4si;
22812 case V2DI_FTYPE_V2DI_V16QI:
22813 type = v2di_ftype_v2di_v16qi;
22815 case V2DI_FTYPE_V2DF_V2DF:
22816 type = v2di_ftype_v2df_v2df;
22818 case V2DI_FTYPE_V2DI_SI_COUNT:
22819 type = v2di_ftype_v2di_int;
22821 case V2SI_FTYPE_V2SI_V2SI:
22822 case V2SI_FTYPE_V2SI_V2SI_COUNT:
22823 type = v2si_ftype_v2si_v2si;
22825 case V2SI_FTYPE_V4HI_V4HI:
22826 type = v2si_ftype_v4hi_v4hi;
22828 case V2SI_FTYPE_V2SF_V2SF:
22829 type = v2si_ftype_v2sf_v2sf;
22831 case V2SI_FTYPE_V2SI_SI_COUNT:
22832 type = v2si_ftype_v2si_int;
22834 case V2DF_FTYPE_V2DF_V2DF:
22835 case V2DF_FTYPE_V2DF_V2DF_SWAP:
22836 type = v2df_ftype_v2df_v2df;
22838 case V2DF_FTYPE_V2DF_V4SF:
22839 type = v2df_ftype_v2df_v4sf;
22841 case V2DF_FTYPE_V2DF_V2DI:
22842 type = v2df_ftype_v2df_v2di;
22844 case V2DF_FTYPE_V2DF_DI:
22845 type = v2df_ftype_v2df_int64;
22847 case V2DF_FTYPE_V2DF_SI:
22848 type = v2df_ftype_v2df_int;
22850 case V2SF_FTYPE_V2SF_V2SF:
22851 type = v2sf_ftype_v2sf_v2sf;
22853 case V1DI_FTYPE_V1DI_V1DI:
22854 case V1DI_FTYPE_V1DI_V1DI_COUNT:
22855 type = v1di_ftype_v1di_v1di;
22857 case V1DI_FTYPE_V8QI_V8QI:
22858 type = v1di_ftype_v8qi_v8qi;
22860 case V1DI_FTYPE_V2SI_V2SI:
22861 type = v1di_ftype_v2si_v2si;
22863 case V1DI_FTYPE_V1DI_SI_COUNT:
22864 type = v1di_ftype_v1di_int;
22866 case UINT64_FTYPE_UINT64_UINT64:
22867 type = uint64_ftype_uint64_uint64;
22869 case UINT_FTYPE_UINT_UINT:
22870 type = unsigned_ftype_unsigned_unsigned;
22872 case UINT_FTYPE_UINT_USHORT:
22873 type = unsigned_ftype_unsigned_ushort;
22875 case UINT_FTYPE_UINT_UCHAR:
22876 type = unsigned_ftype_unsigned_uchar;
22878 case UINT16_FTYPE_UINT16_INT:
22879 type = ushort_ftype_ushort_int;
22881 case UINT8_FTYPE_UINT8_INT:
22882 type = uchar_ftype_uchar_int;
22884 case V8HI_FTYPE_V8HI_INT:
22885 type = v8hi_ftype_v8hi_int;
22887 case V8SF_FTYPE_V8SF_INT:
22888 type = v8sf_ftype_v8sf_int;
22890 case V4SI_FTYPE_V4SI_INT:
22891 type = v4si_ftype_v4si_int;
22893 case V4SI_FTYPE_V8SI_INT:
22894 type = v4si_ftype_v8si_int;
22896 case V4HI_FTYPE_V4HI_INT:
22897 type = v4hi_ftype_v4hi_int;
22899 case V4DF_FTYPE_V4DF_INT:
22900 type = v4df_ftype_v4df_int;
22902 case V4SF_FTYPE_V4SF_INT:
22903 type = v4sf_ftype_v4sf_int;
22905 case V4SF_FTYPE_V8SF_INT:
22906 type = v4sf_ftype_v8sf_int;
22908 case V2DI_FTYPE_V2DI_INT:
22909 case V2DI2TI_FTYPE_V2DI_INT:
22910 type = v2di_ftype_v2di_int;
22912 case V2DF_FTYPE_V2DF_INT:
22913 type = v2df_ftype_v2df_int;
22915 case V2DF_FTYPE_V4DF_INT:
22916 type = v2df_ftype_v4df_int;
22918 case V16QI_FTYPE_V16QI_V16QI_V16QI:
22919 type = v16qi_ftype_v16qi_v16qi_v16qi;
22921 case V8SF_FTYPE_V8SF_V8SF_V8SF:
22922 type = v8sf_ftype_v8sf_v8sf_v8sf;
22924 case V4DF_FTYPE_V4DF_V4DF_V4DF:
22925 type = v4df_ftype_v4df_v4df_v4df;
22927 case V4SF_FTYPE_V4SF_V4SF_V4SF:
22928 type = v4sf_ftype_v4sf_v4sf_v4sf;
22930 case V2DF_FTYPE_V2DF_V2DF_V2DF:
22931 type = v2df_ftype_v2df_v2df_v2df;
22933 case V16QI_FTYPE_V16QI_V16QI_INT:
22934 type = v16qi_ftype_v16qi_v16qi_int;
22936 case V8SI_FTYPE_V8SI_V8SI_INT:
22937 type = v8si_ftype_v8si_v8si_int;
22939 case V8SI_FTYPE_V8SI_V4SI_INT:
22940 type = v8si_ftype_v8si_v4si_int;
22942 case V8HI_FTYPE_V8HI_V8HI_INT:
22943 type = v8hi_ftype_v8hi_v8hi_int;
22945 case V8SF_FTYPE_V8SF_V8SF_INT:
22946 type = v8sf_ftype_v8sf_v8sf_int;
22948 case V8SF_FTYPE_V8SF_V4SF_INT:
22949 type = v8sf_ftype_v8sf_v4sf_int;
22951 case V4SI_FTYPE_V4SI_V4SI_INT:
22952 type = v4si_ftype_v4si_v4si_int;
22954 case V4DF_FTYPE_V4DF_V4DF_INT:
22955 type = v4df_ftype_v4df_v4df_int;
22957 case V4DF_FTYPE_V4DF_V2DF_INT:
22958 type = v4df_ftype_v4df_v2df_int;
22960 case V4SF_FTYPE_V4SF_V4SF_INT:
22961 type = v4sf_ftype_v4sf_v4sf_int;
22963 case V2DI_FTYPE_V2DI_V2DI_INT:
22964 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
22965 type = v2di_ftype_v2di_v2di_int;
22967 case V2DF_FTYPE_V2DF_V2DF_INT:
22968 type = v2df_ftype_v2df_v2df_int;
22970 case V2DI_FTYPE_V2DI_UINT_UINT:
22971 type = v2di_ftype_v2di_unsigned_unsigned;
22973 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
22974 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
22976 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
22977 type = v1di_ftype_v1di_v1di_int;
22980 gcc_unreachable ();
22983 def_builtin_const (d->mask, d->name, type, d->code);
22986 /* pcmpestr[im] insns. */
22987 for (i = 0, d = bdesc_pcmpestr;
22988 i < ARRAY_SIZE (bdesc_pcmpestr);
22991 if (d->code == IX86_BUILTIN_PCMPESTRM128)
22992 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
22994 ftype = int_ftype_v16qi_int_v16qi_int_int;
22995 def_builtin_const (d->mask, d->name, ftype, d->code);
22998 /* pcmpistr[im] insns. */
22999 for (i = 0, d = bdesc_pcmpistr;
23000 i < ARRAY_SIZE (bdesc_pcmpistr);
23003 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23004 ftype = v16qi_ftype_v16qi_v16qi_int;
23006 ftype = int_ftype_v16qi_v16qi_int;
23007 def_builtin_const (d->mask, d->name, ftype, d->code);
23010 /* comi/ucomi insns. */
23011 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23012 if (d->mask == OPTION_MASK_ISA_SSE2)
23013 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23015 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23018 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23019 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23021 /* SSE or 3DNow!A */
23022 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23025 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23027 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23028 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23031 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23032 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23035 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23036 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23037 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23038 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23039 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23040 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23043 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23046 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23047 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23049 /* Access to the vec_init patterns. */
23050 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23051 integer_type_node, NULL_TREE);
23052 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23054 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23055 short_integer_type_node,
23056 short_integer_type_node,
23057 short_integer_type_node, NULL_TREE);
23058 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23060 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23061 char_type_node, char_type_node,
23062 char_type_node, char_type_node,
23063 char_type_node, char_type_node,
23064 char_type_node, NULL_TREE);
23065 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23067 /* Access to the vec_extract patterns. */
23068 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23069 integer_type_node, NULL_TREE);
23070 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23072 ftype = build_function_type_list (long_long_integer_type_node,
23073 V2DI_type_node, integer_type_node,
23075 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23077 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23078 integer_type_node, NULL_TREE);
23079 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23081 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23082 integer_type_node, NULL_TREE);
23083 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23085 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23086 integer_type_node, NULL_TREE);
23087 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23089 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23090 integer_type_node, NULL_TREE);
23091 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23093 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23094 integer_type_node, NULL_TREE);
23095 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23097 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23098 integer_type_node, NULL_TREE);
23099 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23101 /* Access to the vec_set patterns. */
23102 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23104 integer_type_node, NULL_TREE);
23105 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23107 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23109 integer_type_node, NULL_TREE);
23110 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23112 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23114 integer_type_node, NULL_TREE);
23115 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23117 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23119 integer_type_node, NULL_TREE);
23120 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23122 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23124 integer_type_node, NULL_TREE);
23125 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23127 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23129 integer_type_node, NULL_TREE);
23130 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23133 /* Internal method for ix86_init_builtins. */
23136 ix86_init_builtins_va_builtins_abi (void)
23138 tree ms_va_ref, sysv_va_ref;
23139 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23140 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23141 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23142 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23146 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23147 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23148 ms_va_ref = build_reference_type (ms_va_list_type_node);
23150 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23153 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23154 fnvoid_va_start_ms =
23155 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23156 fnvoid_va_end_sysv =
23157 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23158 fnvoid_va_start_sysv =
23159 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23161 fnvoid_va_copy_ms =
23162 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23164 fnvoid_va_copy_sysv =
23165 build_function_type_list (void_type_node, sysv_va_ref,
23166 sysv_va_ref, NULL_TREE);
23168 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23169 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23170 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23171 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23172 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23173 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23174 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23175 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23176 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23177 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23178 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23179 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23183 ix86_init_builtins (void)
23185 tree float128_type_node = make_node (REAL_TYPE);
23188 /* The __float80 type. */
23189 if (TYPE_MODE (long_double_type_node) == XFmode)
23190 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23194 /* The __float80 type. */
23195 tree float80_type_node = make_node (REAL_TYPE);
23197 TYPE_PRECISION (float80_type_node) = 80;
23198 layout_type (float80_type_node);
23199 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23203 /* The __float128 type. */
23204 TYPE_PRECISION (float128_type_node) = 128;
23205 layout_type (float128_type_node);
23206 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23209 /* TFmode support builtins. */
23210 ftype = build_function_type (float128_type_node, void_list_node);
23211 decl = add_builtin_function ("__builtin_infq", ftype,
23212 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23214 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23216 decl = add_builtin_function ("__builtin_huge_valq", ftype,
23217 IX86_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
23219 ix86_builtins[(int) IX86_BUILTIN_HUGE_VALQ] = decl;
23221 /* We will expand them to normal call if SSE2 isn't available since
23222 they are used by libgcc. */
23223 ftype = build_function_type_list (float128_type_node,
23224 float128_type_node,
23226 decl = add_builtin_function ("__builtin_fabsq", ftype,
23227 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23228 "__fabstf2", NULL_TREE);
23229 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23230 TREE_READONLY (decl) = 1;
23232 ftype = build_function_type_list (float128_type_node,
23233 float128_type_node,
23234 float128_type_node,
23236 decl = add_builtin_function ("__builtin_copysignq", ftype,
23237 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23238 "__copysigntf3", NULL_TREE);
23239 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23240 TREE_READONLY (decl) = 1;
23242 ix86_init_mmx_sse_builtins ();
23244 ix86_init_builtins_va_builtins_abi ();
23247 /* Errors in the source file can cause expand_expr to return const0_rtx
23248 where we expect a vector. To avoid crashing, use one of the vector
23249 clear instructions. */
23251 safe_vector_operand (rtx x, enum machine_mode mode)
23253 if (x == const0_rtx)
23254 x = CONST0_RTX (mode);
23258 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23261 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23264 tree arg0 = CALL_EXPR_ARG (exp, 0);
23265 tree arg1 = CALL_EXPR_ARG (exp, 1);
23266 rtx op0 = expand_normal (arg0);
23267 rtx op1 = expand_normal (arg1);
23268 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23269 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23270 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23272 if (VECTOR_MODE_P (mode0))
23273 op0 = safe_vector_operand (op0, mode0);
23274 if (VECTOR_MODE_P (mode1))
23275 op1 = safe_vector_operand (op1, mode1);
23277 if (optimize || !target
23278 || GET_MODE (target) != tmode
23279 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23280 target = gen_reg_rtx (tmode);
23282 if (GET_MODE (op1) == SImode && mode1 == TImode)
23284 rtx x = gen_reg_rtx (V4SImode);
23285 emit_insn (gen_sse2_loadd (x, op1));
23286 op1 = gen_lowpart (TImode, x);
23289 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23290 op0 = copy_to_mode_reg (mode0, op0);
23291 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23292 op1 = copy_to_mode_reg (mode1, op1);
23294 pat = GEN_FCN (icode) (target, op0, op1);
23303 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23304 insns with vec_merge. */
23307 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23311 tree arg0 = CALL_EXPR_ARG (exp, 0);
23312 rtx op1, op0 = expand_normal (arg0);
23313 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23314 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23316 if (optimize || !target
23317 || GET_MODE (target) != tmode
23318 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23319 target = gen_reg_rtx (tmode);
23321 if (VECTOR_MODE_P (mode0))
23322 op0 = safe_vector_operand (op0, mode0);
23324 if ((optimize && !register_operand (op0, mode0))
23325 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23326 op0 = copy_to_mode_reg (mode0, op0);
23329 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23330 op1 = copy_to_mode_reg (mode0, op1);
23332 pat = GEN_FCN (icode) (target, op0, op1);
23339 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23342 ix86_expand_sse_compare (const struct builtin_description *d,
23343 tree exp, rtx target, bool swap)
23346 tree arg0 = CALL_EXPR_ARG (exp, 0);
23347 tree arg1 = CALL_EXPR_ARG (exp, 1);
23348 rtx op0 = expand_normal (arg0);
23349 rtx op1 = expand_normal (arg1);
23351 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23352 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23353 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23354 enum rtx_code comparison = d->comparison;
23356 if (VECTOR_MODE_P (mode0))
23357 op0 = safe_vector_operand (op0, mode0);
23358 if (VECTOR_MODE_P (mode1))
23359 op1 = safe_vector_operand (op1, mode1);
23361 /* Swap operands if we have a comparison that isn't available in
23365 rtx tmp = gen_reg_rtx (mode1);
23366 emit_move_insn (tmp, op1);
23371 if (optimize || !target
23372 || GET_MODE (target) != tmode
23373 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23374 target = gen_reg_rtx (tmode);
23376 if ((optimize && !register_operand (op0, mode0))
23377 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23378 op0 = copy_to_mode_reg (mode0, op0);
23379 if ((optimize && !register_operand (op1, mode1))
23380 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23381 op1 = copy_to_mode_reg (mode1, op1);
23383 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23384 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23391 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23394 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23398 tree arg0 = CALL_EXPR_ARG (exp, 0);
23399 tree arg1 = CALL_EXPR_ARG (exp, 1);
23400 rtx op0 = expand_normal (arg0);
23401 rtx op1 = expand_normal (arg1);
23402 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23403 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23404 enum rtx_code comparison = d->comparison;
23406 if (VECTOR_MODE_P (mode0))
23407 op0 = safe_vector_operand (op0, mode0);
23408 if (VECTOR_MODE_P (mode1))
23409 op1 = safe_vector_operand (op1, mode1);
23411 /* Swap operands if we have a comparison that isn't available in
23413 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23420 target = gen_reg_rtx (SImode);
23421 emit_move_insn (target, const0_rtx);
23422 target = gen_rtx_SUBREG (QImode, target, 0);
23424 if ((optimize && !register_operand (op0, mode0))
23425 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23426 op0 = copy_to_mode_reg (mode0, op0);
23427 if ((optimize && !register_operand (op1, mode1))
23428 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23429 op1 = copy_to_mode_reg (mode1, op1);
23431 pat = GEN_FCN (d->icode) (op0, op1);
23435 emit_insn (gen_rtx_SET (VOIDmode,
23436 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23437 gen_rtx_fmt_ee (comparison, QImode,
23441 return SUBREG_REG (target);
23444 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23447 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23451 tree arg0 = CALL_EXPR_ARG (exp, 0);
23452 tree arg1 = CALL_EXPR_ARG (exp, 1);
23453 rtx op0 = expand_normal (arg0);
23454 rtx op1 = expand_normal (arg1);
23455 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23456 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23457 enum rtx_code comparison = d->comparison;
23459 if (VECTOR_MODE_P (mode0))
23460 op0 = safe_vector_operand (op0, mode0);
23461 if (VECTOR_MODE_P (mode1))
23462 op1 = safe_vector_operand (op1, mode1);
23464 target = gen_reg_rtx (SImode);
23465 emit_move_insn (target, const0_rtx);
23466 target = gen_rtx_SUBREG (QImode, target, 0);
23468 if ((optimize && !register_operand (op0, mode0))
23469 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23470 op0 = copy_to_mode_reg (mode0, op0);
23471 if ((optimize && !register_operand (op1, mode1))
23472 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23473 op1 = copy_to_mode_reg (mode1, op1);
23475 pat = GEN_FCN (d->icode) (op0, op1);
23479 emit_insn (gen_rtx_SET (VOIDmode,
23480 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23481 gen_rtx_fmt_ee (comparison, QImode,
23485 return SUBREG_REG (target);
23488 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23491 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23492 tree exp, rtx target)
23495 tree arg0 = CALL_EXPR_ARG (exp, 0);
23496 tree arg1 = CALL_EXPR_ARG (exp, 1);
23497 tree arg2 = CALL_EXPR_ARG (exp, 2);
23498 tree arg3 = CALL_EXPR_ARG (exp, 3);
23499 tree arg4 = CALL_EXPR_ARG (exp, 4);
23500 rtx scratch0, scratch1;
23501 rtx op0 = expand_normal (arg0);
23502 rtx op1 = expand_normal (arg1);
23503 rtx op2 = expand_normal (arg2);
23504 rtx op3 = expand_normal (arg3);
23505 rtx op4 = expand_normal (arg4);
23506 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23508 tmode0 = insn_data[d->icode].operand[0].mode;
23509 tmode1 = insn_data[d->icode].operand[1].mode;
23510 modev2 = insn_data[d->icode].operand[2].mode;
23511 modei3 = insn_data[d->icode].operand[3].mode;
23512 modev4 = insn_data[d->icode].operand[4].mode;
23513 modei5 = insn_data[d->icode].operand[5].mode;
23514 modeimm = insn_data[d->icode].operand[6].mode;
23516 if (VECTOR_MODE_P (modev2))
23517 op0 = safe_vector_operand (op0, modev2);
23518 if (VECTOR_MODE_P (modev4))
23519 op2 = safe_vector_operand (op2, modev4);
23521 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23522 op0 = copy_to_mode_reg (modev2, op0);
23523 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
23524 op1 = copy_to_mode_reg (modei3, op1);
23525 if ((optimize && !register_operand (op2, modev4))
23526 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
23527 op2 = copy_to_mode_reg (modev4, op2);
23528 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
23529 op3 = copy_to_mode_reg (modei5, op3);
23531 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
23533 error ("the fifth argument must be a 8-bit immediate");
23537 if (d->code == IX86_BUILTIN_PCMPESTRI128)
23539 if (optimize || !target
23540 || GET_MODE (target) != tmode0
23541 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23542 target = gen_reg_rtx (tmode0);
23544 scratch1 = gen_reg_rtx (tmode1);
23546 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
23548 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
23550 if (optimize || !target
23551 || GET_MODE (target) != tmode1
23552 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23553 target = gen_reg_rtx (tmode1);
23555 scratch0 = gen_reg_rtx (tmode0);
23557 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
23561 gcc_assert (d->flag);
23563 scratch0 = gen_reg_rtx (tmode0);
23564 scratch1 = gen_reg_rtx (tmode1);
23566 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
23576 target = gen_reg_rtx (SImode);
23577 emit_move_insn (target, const0_rtx);
23578 target = gen_rtx_SUBREG (QImode, target, 0);
23581 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23582 gen_rtx_fmt_ee (EQ, QImode,
23583 gen_rtx_REG ((enum machine_mode) d->flag,
23586 return SUBREG_REG (target);
23593 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
23596 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
23597 tree exp, rtx target)
23600 tree arg0 = CALL_EXPR_ARG (exp, 0);
23601 tree arg1 = CALL_EXPR_ARG (exp, 1);
23602 tree arg2 = CALL_EXPR_ARG (exp, 2);
23603 rtx scratch0, scratch1;
23604 rtx op0 = expand_normal (arg0);
23605 rtx op1 = expand_normal (arg1);
23606 rtx op2 = expand_normal (arg2);
23607 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
23609 tmode0 = insn_data[d->icode].operand[0].mode;
23610 tmode1 = insn_data[d->icode].operand[1].mode;
23611 modev2 = insn_data[d->icode].operand[2].mode;
23612 modev3 = insn_data[d->icode].operand[3].mode;
23613 modeimm = insn_data[d->icode].operand[4].mode;
23615 if (VECTOR_MODE_P (modev2))
23616 op0 = safe_vector_operand (op0, modev2);
23617 if (VECTOR_MODE_P (modev3))
23618 op1 = safe_vector_operand (op1, modev3);
23620 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
23621 op0 = copy_to_mode_reg (modev2, op0);
23622 if ((optimize && !register_operand (op1, modev3))
23623 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
23624 op1 = copy_to_mode_reg (modev3, op1);
23626 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
23628 error ("the third argument must be a 8-bit immediate");
23632 if (d->code == IX86_BUILTIN_PCMPISTRI128)
23634 if (optimize || !target
23635 || GET_MODE (target) != tmode0
23636 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
23637 target = gen_reg_rtx (tmode0);
23639 scratch1 = gen_reg_rtx (tmode1);
23641 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
23643 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
23645 if (optimize || !target
23646 || GET_MODE (target) != tmode1
23647 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
23648 target = gen_reg_rtx (tmode1);
23650 scratch0 = gen_reg_rtx (tmode0);
23652 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
23656 gcc_assert (d->flag);
23658 scratch0 = gen_reg_rtx (tmode0);
23659 scratch1 = gen_reg_rtx (tmode1);
23661 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
23671 target = gen_reg_rtx (SImode);
23672 emit_move_insn (target, const0_rtx);
23673 target = gen_rtx_SUBREG (QImode, target, 0);
23676 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23677 gen_rtx_fmt_ee (EQ, QImode,
23678 gen_rtx_REG ((enum machine_mode) d->flag,
23681 return SUBREG_REG (target);
23687 /* Subroutine of ix86_expand_builtin to take care of insns with
23688 variable number of operands. */
23691 ix86_expand_args_builtin (const struct builtin_description *d,
23692 tree exp, rtx target)
23694 rtx pat, real_target;
23695 unsigned int i, nargs;
23696 unsigned int nargs_constant = 0;
23697 int num_memory = 0;
23701 enum machine_mode mode;
23703 bool last_arg_count = false;
23704 enum insn_code icode = d->icode;
23705 const struct insn_data *insn_p = &insn_data[icode];
23706 enum machine_mode tmode = insn_p->operand[0].mode;
23707 enum machine_mode rmode = VOIDmode;
23709 enum rtx_code comparison = d->comparison;
23711 switch ((enum ix86_builtin_type) d->flag)
23713 case INT_FTYPE_V8SF_V8SF_PTEST:
23714 case INT_FTYPE_V4DI_V4DI_PTEST:
23715 case INT_FTYPE_V4DF_V4DF_PTEST:
23716 case INT_FTYPE_V4SF_V4SF_PTEST:
23717 case INT_FTYPE_V2DI_V2DI_PTEST:
23718 case INT_FTYPE_V2DF_V2DF_PTEST:
23719 return ix86_expand_sse_ptest (d, exp, target);
23720 case FLOAT128_FTYPE_FLOAT128:
23721 case FLOAT_FTYPE_FLOAT:
23722 case INT_FTYPE_INT:
23723 case UINT64_FTYPE_INT:
23724 case INT64_FTYPE_INT64:
23725 case INT64_FTYPE_V4SF:
23726 case INT64_FTYPE_V2DF:
23727 case INT_FTYPE_V16QI:
23728 case INT_FTYPE_V8QI:
23729 case INT_FTYPE_V8SF:
23730 case INT_FTYPE_V4DF:
23731 case INT_FTYPE_V4SF:
23732 case INT_FTYPE_V2DF:
23733 case V16QI_FTYPE_V16QI:
23734 case V8SI_FTYPE_V8SF:
23735 case V8SI_FTYPE_V4SI:
23736 case V8HI_FTYPE_V8HI:
23737 case V8HI_FTYPE_V16QI:
23738 case V8QI_FTYPE_V8QI:
23739 case V8SF_FTYPE_V8SF:
23740 case V8SF_FTYPE_V8SI:
23741 case V8SF_FTYPE_V4SF:
23742 case V4SI_FTYPE_V4SI:
23743 case V4SI_FTYPE_V16QI:
23744 case V4SI_FTYPE_V4SF:
23745 case V4SI_FTYPE_V8SI:
23746 case V4SI_FTYPE_V8HI:
23747 case V4SI_FTYPE_V4DF:
23748 case V4SI_FTYPE_V2DF:
23749 case V4HI_FTYPE_V4HI:
23750 case V4DF_FTYPE_V4DF:
23751 case V4DF_FTYPE_V4SI:
23752 case V4DF_FTYPE_V4SF:
23753 case V4DF_FTYPE_V2DF:
23754 case V4SF_FTYPE_V4SF:
23755 case V4SF_FTYPE_V4SI:
23756 case V4SF_FTYPE_V8SF:
23757 case V4SF_FTYPE_V4DF:
23758 case V4SF_FTYPE_V2DF:
23759 case V2DI_FTYPE_V2DI:
23760 case V2DI_FTYPE_V16QI:
23761 case V2DI_FTYPE_V8HI:
23762 case V2DI_FTYPE_V4SI:
23763 case V2DF_FTYPE_V2DF:
23764 case V2DF_FTYPE_V4SI:
23765 case V2DF_FTYPE_V4DF:
23766 case V2DF_FTYPE_V4SF:
23767 case V2DF_FTYPE_V2SI:
23768 case V2SI_FTYPE_V2SI:
23769 case V2SI_FTYPE_V4SF:
23770 case V2SI_FTYPE_V2SF:
23771 case V2SI_FTYPE_V2DF:
23772 case V2SF_FTYPE_V2SF:
23773 case V2SF_FTYPE_V2SI:
23776 case V4SF_FTYPE_V4SF_VEC_MERGE:
23777 case V2DF_FTYPE_V2DF_VEC_MERGE:
23778 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
23779 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
23780 case V16QI_FTYPE_V16QI_V16QI:
23781 case V16QI_FTYPE_V8HI_V8HI:
23782 case V8QI_FTYPE_V8QI_V8QI:
23783 case V8QI_FTYPE_V4HI_V4HI:
23784 case V8HI_FTYPE_V8HI_V8HI:
23785 case V8HI_FTYPE_V16QI_V16QI:
23786 case V8HI_FTYPE_V4SI_V4SI:
23787 case V8SF_FTYPE_V8SF_V8SF:
23788 case V8SF_FTYPE_V8SF_V8SI:
23789 case V4SI_FTYPE_V4SI_V4SI:
23790 case V4SI_FTYPE_V8HI_V8HI:
23791 case V4SI_FTYPE_V4SF_V4SF:
23792 case V4SI_FTYPE_V2DF_V2DF:
23793 case V4HI_FTYPE_V4HI_V4HI:
23794 case V4HI_FTYPE_V8QI_V8QI:
23795 case V4HI_FTYPE_V2SI_V2SI:
23796 case V4DF_FTYPE_V4DF_V4DF:
23797 case V4DF_FTYPE_V4DF_V4DI:
23798 case V4SF_FTYPE_V4SF_V4SF:
23799 case V4SF_FTYPE_V4SF_V4SI:
23800 case V4SF_FTYPE_V4SF_V2SI:
23801 case V4SF_FTYPE_V4SF_V2DF:
23802 case V4SF_FTYPE_V4SF_DI:
23803 case V4SF_FTYPE_V4SF_SI:
23804 case V2DI_FTYPE_V2DI_V2DI:
23805 case V2DI_FTYPE_V16QI_V16QI:
23806 case V2DI_FTYPE_V4SI_V4SI:
23807 case V2DI_FTYPE_V2DI_V16QI:
23808 case V2DI_FTYPE_V2DF_V2DF:
23809 case V2SI_FTYPE_V2SI_V2SI:
23810 case V2SI_FTYPE_V4HI_V4HI:
23811 case V2SI_FTYPE_V2SF_V2SF:
23812 case V2DF_FTYPE_V2DF_V2DF:
23813 case V2DF_FTYPE_V2DF_V4SF:
23814 case V2DF_FTYPE_V2DF_V2DI:
23815 case V2DF_FTYPE_V2DF_DI:
23816 case V2DF_FTYPE_V2DF_SI:
23817 case V2SF_FTYPE_V2SF_V2SF:
23818 case V1DI_FTYPE_V1DI_V1DI:
23819 case V1DI_FTYPE_V8QI_V8QI:
23820 case V1DI_FTYPE_V2SI_V2SI:
23821 if (comparison == UNKNOWN)
23822 return ix86_expand_binop_builtin (icode, exp, target);
23825 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23826 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23827 gcc_assert (comparison != UNKNOWN);
23831 case V8HI_FTYPE_V8HI_V8HI_COUNT:
23832 case V8HI_FTYPE_V8HI_SI_COUNT:
23833 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23834 case V4SI_FTYPE_V4SI_SI_COUNT:
23835 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23836 case V4HI_FTYPE_V4HI_SI_COUNT:
23837 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23838 case V2DI_FTYPE_V2DI_SI_COUNT:
23839 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23840 case V2SI_FTYPE_V2SI_SI_COUNT:
23841 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23842 case V1DI_FTYPE_V1DI_SI_COUNT:
23844 last_arg_count = true;
23846 case UINT64_FTYPE_UINT64_UINT64:
23847 case UINT_FTYPE_UINT_UINT:
23848 case UINT_FTYPE_UINT_USHORT:
23849 case UINT_FTYPE_UINT_UCHAR:
23850 case UINT16_FTYPE_UINT16_INT:
23851 case UINT8_FTYPE_UINT8_INT:
23854 case V2DI2TI_FTYPE_V2DI_INT:
23857 nargs_constant = 1;
23859 case V8HI_FTYPE_V8HI_INT:
23860 case V8SF_FTYPE_V8SF_INT:
23861 case V4SI_FTYPE_V4SI_INT:
23862 case V4SI_FTYPE_V8SI_INT:
23863 case V4HI_FTYPE_V4HI_INT:
23864 case V4DF_FTYPE_V4DF_INT:
23865 case V4SF_FTYPE_V4SF_INT:
23866 case V4SF_FTYPE_V8SF_INT:
23867 case V2DI_FTYPE_V2DI_INT:
23868 case V2DF_FTYPE_V2DF_INT:
23869 case V2DF_FTYPE_V4DF_INT:
23871 nargs_constant = 1;
23873 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23874 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23875 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23876 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23877 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23880 case V16QI_FTYPE_V16QI_V16QI_INT:
23881 case V8HI_FTYPE_V8HI_V8HI_INT:
23882 case V8SI_FTYPE_V8SI_V8SI_INT:
23883 case V8SI_FTYPE_V8SI_V4SI_INT:
23884 case V8SF_FTYPE_V8SF_V8SF_INT:
23885 case V8SF_FTYPE_V8SF_V4SF_INT:
23886 case V4SI_FTYPE_V4SI_V4SI_INT:
23887 case V4DF_FTYPE_V4DF_V4DF_INT:
23888 case V4DF_FTYPE_V4DF_V2DF_INT:
23889 case V4SF_FTYPE_V4SF_V4SF_INT:
23890 case V2DI_FTYPE_V2DI_V2DI_INT:
23891 case V2DF_FTYPE_V2DF_V2DF_INT:
23893 nargs_constant = 1;
23895 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23898 nargs_constant = 1;
23900 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23903 nargs_constant = 1;
23905 case V2DI_FTYPE_V2DI_UINT_UINT:
23907 nargs_constant = 2;
23909 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23911 nargs_constant = 2;
23914 gcc_unreachable ();
23917 gcc_assert (nargs <= ARRAY_SIZE (args));
23919 if (comparison != UNKNOWN)
23921 gcc_assert (nargs == 2);
23922 return ix86_expand_sse_compare (d, exp, target, swap);
23925 if (rmode == VOIDmode || rmode == tmode)
23929 || GET_MODE (target) != tmode
23930 || ! (*insn_p->operand[0].predicate) (target, tmode))
23931 target = gen_reg_rtx (tmode);
23932 real_target = target;
23936 target = gen_reg_rtx (rmode);
23937 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
23940 for (i = 0; i < nargs; i++)
23942 tree arg = CALL_EXPR_ARG (exp, i);
23943 rtx op = expand_normal (arg);
23944 enum machine_mode mode = insn_p->operand[i + 1].mode;
23945 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
23947 if (last_arg_count && (i + 1) == nargs)
23949 /* SIMD shift insns take either an 8-bit immediate or
23950 register as count. But builtin functions take int as
23951 count. If count doesn't match, we put it in register. */
23954 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
23955 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
23956 op = copy_to_reg (op);
23959 else if ((nargs - i) <= nargs_constant)
23964 case CODE_FOR_sse4_1_roundpd:
23965 case CODE_FOR_sse4_1_roundps:
23966 case CODE_FOR_sse4_1_roundsd:
23967 case CODE_FOR_sse4_1_roundss:
23968 case CODE_FOR_sse4_1_blendps:
23969 case CODE_FOR_avx_blendpd256:
23970 case CODE_FOR_avx_vpermilv4df:
23971 case CODE_FOR_avx_roundpd256:
23972 case CODE_FOR_avx_roundps256:
23973 error ("the last argument must be a 4-bit immediate");
23976 case CODE_FOR_sse4_1_blendpd:
23977 case CODE_FOR_avx_vpermilv2df:
23978 error ("the last argument must be a 2-bit immediate");
23981 case CODE_FOR_avx_vextractf128v4df:
23982 case CODE_FOR_avx_vextractf128v8sf:
23983 case CODE_FOR_avx_vextractf128v8si:
23984 case CODE_FOR_avx_vinsertf128v4df:
23985 case CODE_FOR_avx_vinsertf128v8sf:
23986 case CODE_FOR_avx_vinsertf128v8si:
23987 error ("the last argument must be a 1-bit immediate");
23990 case CODE_FOR_avx_cmpsdv2df3:
23991 case CODE_FOR_avx_cmpssv4sf3:
23992 case CODE_FOR_avx_cmppdv2df3:
23993 case CODE_FOR_avx_cmppsv4sf3:
23994 case CODE_FOR_avx_cmppdv4df3:
23995 case CODE_FOR_avx_cmppsv8sf3:
23996 error ("the last argument must be a 5-bit immediate");
24000 switch (nargs_constant)
24003 if ((nargs - i) == nargs_constant)
24005 error ("the next to last argument must be an 8-bit immediate");
24009 error ("the last argument must be an 8-bit immediate");
24012 gcc_unreachable ();
24019 if (VECTOR_MODE_P (mode))
24020 op = safe_vector_operand (op, mode);
24022 /* If we aren't optimizing, only allow one memory operand to
24024 if (memory_operand (op, mode))
24027 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24029 if (optimize || !match || num_memory > 1)
24030 op = copy_to_mode_reg (mode, op);
24034 op = copy_to_reg (op);
24035 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24040 args[i].mode = mode;
24046 pat = GEN_FCN (icode) (real_target, args[0].op);
24049 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24052 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24056 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24057 args[2].op, args[3].op);
24060 gcc_unreachable ();
24070 /* Subroutine of ix86_expand_builtin to take care of special insns
24071 with variable number of operands. */
24074 ix86_expand_special_args_builtin (const struct builtin_description *d,
24075 tree exp, rtx target)
24079 unsigned int i, nargs, arg_adjust, memory;
24083 enum machine_mode mode;
24085 enum insn_code icode = d->icode;
24086 bool last_arg_constant = false;
24087 const struct insn_data *insn_p = &insn_data[icode];
24088 enum machine_mode tmode = insn_p->operand[0].mode;
24089 enum { load, store } klass;
24091 switch ((enum ix86_special_builtin_type) d->flag)
24093 case VOID_FTYPE_VOID:
24094 emit_insn (GEN_FCN (icode) (target));
24096 case UINT64_FTYPE_VOID:
24101 case UINT64_FTYPE_PUNSIGNED:
24102 case V2DI_FTYPE_PV2DI:
24103 case V32QI_FTYPE_PCCHAR:
24104 case V16QI_FTYPE_PCCHAR:
24105 case V8SF_FTYPE_PCV4SF:
24106 case V8SF_FTYPE_PCFLOAT:
24107 case V4SF_FTYPE_PCFLOAT:
24108 case V4DF_FTYPE_PCV2DF:
24109 case V4DF_FTYPE_PCDOUBLE:
24110 case V2DF_FTYPE_PCDOUBLE:
24115 case VOID_FTYPE_PV2SF_V4SF:
24116 case VOID_FTYPE_PV4DI_V4DI:
24117 case VOID_FTYPE_PV2DI_V2DI:
24118 case VOID_FTYPE_PCHAR_V32QI:
24119 case VOID_FTYPE_PCHAR_V16QI:
24120 case VOID_FTYPE_PFLOAT_V8SF:
24121 case VOID_FTYPE_PFLOAT_V4SF:
24122 case VOID_FTYPE_PDOUBLE_V4DF:
24123 case VOID_FTYPE_PDOUBLE_V2DF:
24124 case VOID_FTYPE_PDI_DI:
24125 case VOID_FTYPE_PINT_INT:
24128 /* Reserve memory operand for target. */
24129 memory = ARRAY_SIZE (args);
24131 case V4SF_FTYPE_V4SF_PCV2SF:
24132 case V2DF_FTYPE_V2DF_PCDOUBLE:
24137 case V8SF_FTYPE_PCV8SF_V8SF:
24138 case V4DF_FTYPE_PCV4DF_V4DF:
24139 case V4SF_FTYPE_PCV4SF_V4SF:
24140 case V2DF_FTYPE_PCV2DF_V2DF:
24145 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24146 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24147 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24148 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24151 /* Reserve memory operand for target. */
24152 memory = ARRAY_SIZE (args);
24155 gcc_unreachable ();
24158 gcc_assert (nargs <= ARRAY_SIZE (args));
24160 if (klass == store)
24162 arg = CALL_EXPR_ARG (exp, 0);
24163 op = expand_normal (arg);
24164 gcc_assert (target == 0);
24165 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24173 || GET_MODE (target) != tmode
24174 || ! (*insn_p->operand[0].predicate) (target, tmode))
24175 target = gen_reg_rtx (tmode);
24178 for (i = 0; i < nargs; i++)
24180 enum machine_mode mode = insn_p->operand[i + 1].mode;
24183 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24184 op = expand_normal (arg);
24185 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24187 if (last_arg_constant && (i + 1) == nargs)
24193 error ("the last argument must be an 8-bit immediate");
24201 /* This must be the memory operand. */
24202 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24203 gcc_assert (GET_MODE (op) == mode
24204 || GET_MODE (op) == VOIDmode);
24208 /* This must be register. */
24209 if (VECTOR_MODE_P (mode))
24210 op = safe_vector_operand (op, mode);
24212 gcc_assert (GET_MODE (op) == mode
24213 || GET_MODE (op) == VOIDmode);
24214 op = copy_to_mode_reg (mode, op);
24219 args[i].mode = mode;
24225 pat = GEN_FCN (icode) (target);
24228 pat = GEN_FCN (icode) (target, args[0].op);
24231 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24234 gcc_unreachable ();
24240 return klass == store ? 0 : target;
24243 /* Return the integer constant in ARG. Constrain it to be in the range
24244 of the subparts of VEC_TYPE; issue an error if not. */
24247 get_element_number (tree vec_type, tree arg)
24249 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24251 if (!host_integerp (arg, 1)
24252 || (elt = tree_low_cst (arg, 1), elt > max))
24254 error ("selector must be an integer constant in the range 0..%wi", max);
24261 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24262 ix86_expand_vector_init. We DO have language-level syntax for this, in
24263 the form of (type){ init-list }. Except that since we can't place emms
24264 instructions from inside the compiler, we can't allow the use of MMX
24265 registers unless the user explicitly asks for it. So we do *not* define
24266 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24267 we have builtins invoked by mmintrin.h that gives us license to emit
24268 these sorts of instructions. */
24271 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24273 enum machine_mode tmode = TYPE_MODE (type);
24274 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24275 int i, n_elt = GET_MODE_NUNITS (tmode);
24276 rtvec v = rtvec_alloc (n_elt);
24278 gcc_assert (VECTOR_MODE_P (tmode));
24279 gcc_assert (call_expr_nargs (exp) == n_elt);
24281 for (i = 0; i < n_elt; ++i)
24283 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24284 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24287 if (!target || !register_operand (target, tmode))
24288 target = gen_reg_rtx (tmode);
24290 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24294 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24295 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24296 had a language-level syntax for referencing vector elements. */
24299 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24301 enum machine_mode tmode, mode0;
24306 arg0 = CALL_EXPR_ARG (exp, 0);
24307 arg1 = CALL_EXPR_ARG (exp, 1);
24309 op0 = expand_normal (arg0);
24310 elt = get_element_number (TREE_TYPE (arg0), arg1);
24312 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24313 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24314 gcc_assert (VECTOR_MODE_P (mode0));
24316 op0 = force_reg (mode0, op0);
24318 if (optimize || !target || !register_operand (target, tmode))
24319 target = gen_reg_rtx (tmode);
24321 ix86_expand_vector_extract (true, target, op0, elt);
24326 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24327 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24328 a language-level syntax for referencing vector elements. */
24331 ix86_expand_vec_set_builtin (tree exp)
24333 enum machine_mode tmode, mode1;
24334 tree arg0, arg1, arg2;
24336 rtx op0, op1, target;
24338 arg0 = CALL_EXPR_ARG (exp, 0);
24339 arg1 = CALL_EXPR_ARG (exp, 1);
24340 arg2 = CALL_EXPR_ARG (exp, 2);
24342 tmode = TYPE_MODE (TREE_TYPE (arg0));
24343 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24344 gcc_assert (VECTOR_MODE_P (tmode));
24346 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24347 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24348 elt = get_element_number (TREE_TYPE (arg0), arg2);
24350 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24351 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24353 op0 = force_reg (tmode, op0);
24354 op1 = force_reg (mode1, op1);
24356 /* OP0 is the source of these builtin functions and shouldn't be
24357 modified. Create a copy, use it and return it as target. */
24358 target = gen_reg_rtx (tmode);
24359 emit_move_insn (target, op0);
24360 ix86_expand_vector_set (true, target, op1, elt);
24365 /* Expand an expression EXP that calls a built-in function,
24366 with result going to TARGET if that's convenient
24367 (and in mode MODE if that's convenient).
24368 SUBTARGET may be used as the target for computing one of EXP's operands.
24369 IGNORE is nonzero if the value is to be ignored. */
24372 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24373 enum machine_mode mode ATTRIBUTE_UNUSED,
24374 int ignore ATTRIBUTE_UNUSED)
24376 const struct builtin_description *d;
24378 enum insn_code icode;
24379 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24380 tree arg0, arg1, arg2;
24381 rtx op0, op1, op2, pat;
24382 enum machine_mode mode0, mode1, mode2;
24383 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24385 /* Determine whether the builtin function is available under the current ISA.
24386 Originally the builtin was not created if it wasn't applicable to the
24387 current ISA based on the command line switches. With function specific
24388 options, we need to check in the context of the function making the call
24389 whether it is supported. */
24390 if (ix86_builtins_isa[fcode].isa
24391 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24393 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24394 NULL, NULL, false);
24397 error ("%qE needs unknown isa option", fndecl);
24400 gcc_assert (opts != NULL);
24401 error ("%qE needs isa option %s", fndecl, opts);
24409 case IX86_BUILTIN_MASKMOVQ:
24410 case IX86_BUILTIN_MASKMOVDQU:
24411 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24412 ? CODE_FOR_mmx_maskmovq
24413 : CODE_FOR_sse2_maskmovdqu);
24414 /* Note the arg order is different from the operand order. */
24415 arg1 = CALL_EXPR_ARG (exp, 0);
24416 arg2 = CALL_EXPR_ARG (exp, 1);
24417 arg0 = CALL_EXPR_ARG (exp, 2);
24418 op0 = expand_normal (arg0);
24419 op1 = expand_normal (arg1);
24420 op2 = expand_normal (arg2);
24421 mode0 = insn_data[icode].operand[0].mode;
24422 mode1 = insn_data[icode].operand[1].mode;
24423 mode2 = insn_data[icode].operand[2].mode;
24425 op0 = force_reg (Pmode, op0);
24426 op0 = gen_rtx_MEM (mode1, op0);
24428 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24429 op0 = copy_to_mode_reg (mode0, op0);
24430 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24431 op1 = copy_to_mode_reg (mode1, op1);
24432 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24433 op2 = copy_to_mode_reg (mode2, op2);
24434 pat = GEN_FCN (icode) (op0, op1, op2);
24440 case IX86_BUILTIN_LDMXCSR:
24441 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24442 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24443 emit_move_insn (target, op0);
24444 emit_insn (gen_sse_ldmxcsr (target));
24447 case IX86_BUILTIN_STMXCSR:
24448 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24449 emit_insn (gen_sse_stmxcsr (target));
24450 return copy_to_mode_reg (SImode, target);
24452 case IX86_BUILTIN_CLFLUSH:
24453 arg0 = CALL_EXPR_ARG (exp, 0);
24454 op0 = expand_normal (arg0);
24455 icode = CODE_FOR_sse2_clflush;
24456 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24457 op0 = copy_to_mode_reg (Pmode, op0);
24459 emit_insn (gen_sse2_clflush (op0));
24462 case IX86_BUILTIN_MONITOR:
24463 arg0 = CALL_EXPR_ARG (exp, 0);
24464 arg1 = CALL_EXPR_ARG (exp, 1);
24465 arg2 = CALL_EXPR_ARG (exp, 2);
24466 op0 = expand_normal (arg0);
24467 op1 = expand_normal (arg1);
24468 op2 = expand_normal (arg2);
24470 op0 = copy_to_mode_reg (Pmode, op0);
24472 op1 = copy_to_mode_reg (SImode, op1);
24474 op2 = copy_to_mode_reg (SImode, op2);
24475 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24478 case IX86_BUILTIN_MWAIT:
24479 arg0 = CALL_EXPR_ARG (exp, 0);
24480 arg1 = CALL_EXPR_ARG (exp, 1);
24481 op0 = expand_normal (arg0);
24482 op1 = expand_normal (arg1);
24484 op0 = copy_to_mode_reg (SImode, op0);
24486 op1 = copy_to_mode_reg (SImode, op1);
24487 emit_insn (gen_sse3_mwait (op0, op1));
24490 case IX86_BUILTIN_VEC_INIT_V2SI:
24491 case IX86_BUILTIN_VEC_INIT_V4HI:
24492 case IX86_BUILTIN_VEC_INIT_V8QI:
24493 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24495 case IX86_BUILTIN_VEC_EXT_V2DF:
24496 case IX86_BUILTIN_VEC_EXT_V2DI:
24497 case IX86_BUILTIN_VEC_EXT_V4SF:
24498 case IX86_BUILTIN_VEC_EXT_V4SI:
24499 case IX86_BUILTIN_VEC_EXT_V8HI:
24500 case IX86_BUILTIN_VEC_EXT_V2SI:
24501 case IX86_BUILTIN_VEC_EXT_V4HI:
24502 case IX86_BUILTIN_VEC_EXT_V16QI:
24503 return ix86_expand_vec_ext_builtin (exp, target);
24505 case IX86_BUILTIN_VEC_SET_V2DI:
24506 case IX86_BUILTIN_VEC_SET_V4SF:
24507 case IX86_BUILTIN_VEC_SET_V4SI:
24508 case IX86_BUILTIN_VEC_SET_V8HI:
24509 case IX86_BUILTIN_VEC_SET_V4HI:
24510 case IX86_BUILTIN_VEC_SET_V16QI:
24511 return ix86_expand_vec_set_builtin (exp);
24513 case IX86_BUILTIN_INFQ:
24514 case IX86_BUILTIN_HUGE_VALQ:
24516 REAL_VALUE_TYPE inf;
24520 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24522 tmp = validize_mem (force_const_mem (mode, tmp));
24525 target = gen_reg_rtx (mode);
24527 emit_move_insn (target, tmp);
24535 for (i = 0, d = bdesc_special_args;
24536 i < ARRAY_SIZE (bdesc_special_args);
24538 if (d->code == fcode)
24539 return ix86_expand_special_args_builtin (d, exp, target);
24541 for (i = 0, d = bdesc_args;
24542 i < ARRAY_SIZE (bdesc_args);
24544 if (d->code == fcode)
24547 case IX86_BUILTIN_FABSQ:
24548 case IX86_BUILTIN_COPYSIGNQ:
24550 /* Emit a normal call if SSE2 isn't available. */
24551 return expand_call (exp, target, ignore);
24553 return ix86_expand_args_builtin (d, exp, target);
24556 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
24557 if (d->code == fcode)
24558 return ix86_expand_sse_comi (d, exp, target);
24560 for (i = 0, d = bdesc_pcmpestr;
24561 i < ARRAY_SIZE (bdesc_pcmpestr);
24563 if (d->code == fcode)
24564 return ix86_expand_sse_pcmpestr (d, exp, target);
24566 for (i = 0, d = bdesc_pcmpistr;
24567 i < ARRAY_SIZE (bdesc_pcmpistr);
24569 if (d->code == fcode)
24570 return ix86_expand_sse_pcmpistr (d, exp, target);
24572 gcc_unreachable ();
24575 /* Returns a function decl for a vectorized version of the builtin function
24576 with builtin function code FN and the result vector type TYPE, or NULL_TREE
24577 if it is not available. */
24580 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
24583 enum machine_mode in_mode, out_mode;
24586 if (TREE_CODE (type_out) != VECTOR_TYPE
24587 || TREE_CODE (type_in) != VECTOR_TYPE)
24590 out_mode = TYPE_MODE (TREE_TYPE (type_out));
24591 out_n = TYPE_VECTOR_SUBPARTS (type_out);
24592 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24593 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24597 case BUILT_IN_SQRT:
24598 if (out_mode == DFmode && out_n == 2
24599 && in_mode == DFmode && in_n == 2)
24600 return ix86_builtins[IX86_BUILTIN_SQRTPD];
24603 case BUILT_IN_SQRTF:
24604 if (out_mode == SFmode && out_n == 4
24605 && in_mode == SFmode && in_n == 4)
24606 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
24609 case BUILT_IN_LRINT:
24610 if (out_mode == SImode && out_n == 4
24611 && in_mode == DFmode && in_n == 2)
24612 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
24615 case BUILT_IN_LRINTF:
24616 if (out_mode == SImode && out_n == 4
24617 && in_mode == SFmode && in_n == 4)
24618 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
24621 case BUILT_IN_COPYSIGN:
24622 if (out_mode == DFmode && out_n == 2
24623 && in_mode == DFmode && in_n == 2)
24624 return ix86_builtins[IX86_BUILTIN_CPYSGNPD];
24627 case BUILT_IN_COPYSIGNF:
24628 if (out_mode == SFmode && out_n == 4
24629 && in_mode == SFmode && in_n == 4)
24630 return ix86_builtins[IX86_BUILTIN_CPYSGNPS];
24637 /* Dispatch to a handler for a vectorization library. */
24638 if (ix86_veclib_handler)
24639 return (*ix86_veclib_handler) ((enum built_in_function) fn, type_out,
24645 /* Handler for an SVML-style interface to
24646 a library with vectorized intrinsics. */
24649 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
24652 tree fntype, new_fndecl, args;
24655 enum machine_mode el_mode, in_mode;
24658 /* The SVML is suitable for unsafe math only. */
24659 if (!flag_unsafe_math_optimizations)
24662 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24663 n = TYPE_VECTOR_SUBPARTS (type_out);
24664 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24665 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24666 if (el_mode != in_mode
24674 case BUILT_IN_LOG10:
24676 case BUILT_IN_TANH:
24678 case BUILT_IN_ATAN:
24679 case BUILT_IN_ATAN2:
24680 case BUILT_IN_ATANH:
24681 case BUILT_IN_CBRT:
24682 case BUILT_IN_SINH:
24684 case BUILT_IN_ASINH:
24685 case BUILT_IN_ASIN:
24686 case BUILT_IN_COSH:
24688 case BUILT_IN_ACOSH:
24689 case BUILT_IN_ACOS:
24690 if (el_mode != DFmode || n != 2)
24694 case BUILT_IN_EXPF:
24695 case BUILT_IN_LOGF:
24696 case BUILT_IN_LOG10F:
24697 case BUILT_IN_POWF:
24698 case BUILT_IN_TANHF:
24699 case BUILT_IN_TANF:
24700 case BUILT_IN_ATANF:
24701 case BUILT_IN_ATAN2F:
24702 case BUILT_IN_ATANHF:
24703 case BUILT_IN_CBRTF:
24704 case BUILT_IN_SINHF:
24705 case BUILT_IN_SINF:
24706 case BUILT_IN_ASINHF:
24707 case BUILT_IN_ASINF:
24708 case BUILT_IN_COSHF:
24709 case BUILT_IN_COSF:
24710 case BUILT_IN_ACOSHF:
24711 case BUILT_IN_ACOSF:
24712 if (el_mode != SFmode || n != 4)
24720 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
24722 if (fn == BUILT_IN_LOGF)
24723 strcpy (name, "vmlsLn4");
24724 else if (fn == BUILT_IN_LOG)
24725 strcpy (name, "vmldLn2");
24728 sprintf (name, "vmls%s", bname+10);
24729 name[strlen (name)-1] = '4';
24732 sprintf (name, "vmld%s2", bname+10);
24734 /* Convert to uppercase. */
24738 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
24739 args = TREE_CHAIN (args))
24743 fntype = build_function_type_list (type_out, type_in, NULL);
24745 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
24747 /* Build a function declaration for the vectorized function. */
24748 new_fndecl = build_decl (BUILTINS_LOCATION,
24749 FUNCTION_DECL, get_identifier (name), fntype);
24750 TREE_PUBLIC (new_fndecl) = 1;
24751 DECL_EXTERNAL (new_fndecl) = 1;
24752 DECL_IS_NOVOPS (new_fndecl) = 1;
24753 TREE_READONLY (new_fndecl) = 1;
24758 /* Handler for an ACML-style interface to
24759 a library with vectorized intrinsics. */
24762 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
24764 char name[20] = "__vr.._";
24765 tree fntype, new_fndecl, args;
24768 enum machine_mode el_mode, in_mode;
24771 /* The ACML is 64bits only and suitable for unsafe math only as
24772 it does not correctly support parts of IEEE with the required
24773 precision such as denormals. */
24775 || !flag_unsafe_math_optimizations)
24778 el_mode = TYPE_MODE (TREE_TYPE (type_out));
24779 n = TYPE_VECTOR_SUBPARTS (type_out);
24780 in_mode = TYPE_MODE (TREE_TYPE (type_in));
24781 in_n = TYPE_VECTOR_SUBPARTS (type_in);
24782 if (el_mode != in_mode
24792 case BUILT_IN_LOG2:
24793 case BUILT_IN_LOG10:
24796 if (el_mode != DFmode
24801 case BUILT_IN_SINF:
24802 case BUILT_IN_COSF:
24803 case BUILT_IN_EXPF:
24804 case BUILT_IN_POWF:
24805 case BUILT_IN_LOGF:
24806 case BUILT_IN_LOG2F:
24807 case BUILT_IN_LOG10F:
24810 if (el_mode != SFmode
24819 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
24820 sprintf (name + 7, "%s", bname+10);
24823 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
24824 args = TREE_CHAIN (args))
24828 fntype = build_function_type_list (type_out, type_in, NULL);
24830 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
24832 /* Build a function declaration for the vectorized function. */
24833 new_fndecl = build_decl (BUILTINS_LOCATION,
24834 FUNCTION_DECL, get_identifier (name), fntype);
24835 TREE_PUBLIC (new_fndecl) = 1;
24836 DECL_EXTERNAL (new_fndecl) = 1;
24837 DECL_IS_NOVOPS (new_fndecl) = 1;
24838 TREE_READONLY (new_fndecl) = 1;
24844 /* Returns a decl of a function that implements conversion of an integer vector
24845 into a floating-point vector, or vice-versa. TYPE is the type of the integer
24846 side of the conversion.
24847 Return NULL_TREE if it is not available. */
24850 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
24852 if (! (TARGET_SSE2 && TREE_CODE (type) == VECTOR_TYPE))
24858 switch (TYPE_MODE (type))
24861 return TYPE_UNSIGNED (type)
24862 ? ix86_builtins[IX86_BUILTIN_CVTUDQ2PS]
24863 : ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
24868 case FIX_TRUNC_EXPR:
24869 switch (TYPE_MODE (type))
24872 return TYPE_UNSIGNED (type)
24874 : ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
24884 /* Returns a code for a target-specific builtin that implements
24885 reciprocal of the function, or NULL_TREE if not available. */
24888 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
24889 bool sqrt ATTRIBUTE_UNUSED)
24891 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
24892 && flag_finite_math_only && !flag_trapping_math
24893 && flag_unsafe_math_optimizations))
24897 /* Machine dependent builtins. */
24900 /* Vectorized version of sqrt to rsqrt conversion. */
24901 case IX86_BUILTIN_SQRTPS_NR:
24902 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
24908 /* Normal builtins. */
24911 /* Sqrt to rsqrt conversion. */
24912 case BUILT_IN_SQRTF:
24913 return ix86_builtins[IX86_BUILTIN_RSQRTF];
24920 /* Store OPERAND to the memory after reload is completed. This means
24921 that we can't easily use assign_stack_local. */
24923 ix86_force_to_memory (enum machine_mode mode, rtx operand)
24927 gcc_assert (reload_completed);
24928 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
24930 result = gen_rtx_MEM (mode,
24931 gen_rtx_PLUS (Pmode,
24933 GEN_INT (-RED_ZONE_SIZE)));
24934 emit_move_insn (result, operand);
24936 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
24942 operand = gen_lowpart (DImode, operand);
24946 gen_rtx_SET (VOIDmode,
24947 gen_rtx_MEM (DImode,
24948 gen_rtx_PRE_DEC (DImode,
24949 stack_pointer_rtx)),
24953 gcc_unreachable ();
24955 result = gen_rtx_MEM (mode, stack_pointer_rtx);
24964 split_di (&operand, 1, operands, operands + 1);
24966 gen_rtx_SET (VOIDmode,
24967 gen_rtx_MEM (SImode,
24968 gen_rtx_PRE_DEC (Pmode,
24969 stack_pointer_rtx)),
24972 gen_rtx_SET (VOIDmode,
24973 gen_rtx_MEM (SImode,
24974 gen_rtx_PRE_DEC (Pmode,
24975 stack_pointer_rtx)),
24980 /* Store HImodes as SImodes. */
24981 operand = gen_lowpart (SImode, operand);
24985 gen_rtx_SET (VOIDmode,
24986 gen_rtx_MEM (GET_MODE (operand),
24987 gen_rtx_PRE_DEC (SImode,
24988 stack_pointer_rtx)),
24992 gcc_unreachable ();
24994 result = gen_rtx_MEM (mode, stack_pointer_rtx);
24999 /* Free operand from the memory. */
25001 ix86_free_from_memory (enum machine_mode mode)
25003 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25007 if (mode == DImode || TARGET_64BIT)
25011 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25012 to pop or add instruction if registers are available. */
25013 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25014 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25019 /* Implement TARGET_IRA_COVER_CLASSES. If -mfpmath=sse, we prefer
25020 SSE_REGS to FLOAT_REGS if their costs for a pseudo are the
25022 static const enum reg_class *
25023 i386_ira_cover_classes (void)
25025 static const enum reg_class sse_fpmath_classes[] = {
25026 GENERAL_REGS, SSE_REGS, MMX_REGS, FLOAT_REGS, LIM_REG_CLASSES
25028 static const enum reg_class no_sse_fpmath_classes[] = {
25029 GENERAL_REGS, FLOAT_REGS, MMX_REGS, SSE_REGS, LIM_REG_CLASSES
25032 return TARGET_SSE_MATH ? sse_fpmath_classes : no_sse_fpmath_classes;
25035 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25036 QImode must go into class Q_REGS.
25037 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25038 movdf to do mem-to-mem moves through integer regs. */
25040 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25042 enum machine_mode mode = GET_MODE (x);
25044 /* We're only allowed to return a subclass of CLASS. Many of the
25045 following checks fail for NO_REGS, so eliminate that early. */
25046 if (regclass == NO_REGS)
25049 /* All classes can load zeros. */
25050 if (x == CONST0_RTX (mode))
25053 /* Force constants into memory if we are loading a (nonzero) constant into
25054 an MMX or SSE register. This is because there are no MMX/SSE instructions
25055 to load from a constant. */
25057 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25060 /* Prefer SSE regs only, if we can use them for math. */
25061 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25062 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25064 /* Floating-point constants need more complex checks. */
25065 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25067 /* General regs can load everything. */
25068 if (reg_class_subset_p (regclass, GENERAL_REGS))
25071 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25072 zero above. We only want to wind up preferring 80387 registers if
25073 we plan on doing computation with them. */
25075 && standard_80387_constant_p (x))
25077 /* Limit class to non-sse. */
25078 if (regclass == FLOAT_SSE_REGS)
25080 if (regclass == FP_TOP_SSE_REGS)
25082 if (regclass == FP_SECOND_SSE_REGS)
25083 return FP_SECOND_REG;
25084 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25091 /* Generally when we see PLUS here, it's the function invariant
25092 (plus soft-fp const_int). Which can only be computed into general
25094 if (GET_CODE (x) == PLUS)
25095 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25097 /* QImode constants are easy to load, but non-constant QImode data
25098 must go into Q_REGS. */
25099 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25101 if (reg_class_subset_p (regclass, Q_REGS))
25103 if (reg_class_subset_p (Q_REGS, regclass))
25111 /* Discourage putting floating-point values in SSE registers unless
25112 SSE math is being used, and likewise for the 387 registers. */
25114 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25116 enum machine_mode mode = GET_MODE (x);
25118 /* Restrict the output reload class to the register bank that we are doing
25119 math on. If we would like not to return a subset of CLASS, reject this
25120 alternative: if reload cannot do this, it will still use its choice. */
25121 mode = GET_MODE (x);
25122 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25123 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25125 if (X87_FLOAT_MODE_P (mode))
25127 if (regclass == FP_TOP_SSE_REGS)
25129 else if (regclass == FP_SECOND_SSE_REGS)
25130 return FP_SECOND_REG;
25132 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25138 static enum reg_class
25139 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25140 enum machine_mode mode,
25141 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25143 /* QImode spills from non-QI registers require
25144 intermediate register on 32bit targets. */
25145 if (!in_p && mode == QImode && !TARGET_64BIT
25146 && (rclass == GENERAL_REGS
25147 || rclass == LEGACY_REGS
25148 || rclass == INDEX_REGS))
25157 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25158 regno = true_regnum (x);
25160 /* Return Q_REGS if the operand is in memory. */
25168 /* If we are copying between general and FP registers, we need a memory
25169 location. The same is true for SSE and MMX registers.
25171 To optimize register_move_cost performance, allow inline variant.
25173 The macro can't work reliably when one of the CLASSES is class containing
25174 registers from multiple units (SSE, MMX, integer). We avoid this by never
25175 combining those units in single alternative in the machine description.
25176 Ensure that this constraint holds to avoid unexpected surprises.
25178 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25179 enforce these sanity checks. */
25182 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25183 enum machine_mode mode, int strict)
25185 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25186 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25187 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25188 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25189 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25190 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25192 gcc_assert (!strict);
25196 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25199 /* ??? This is a lie. We do have moves between mmx/general, and for
25200 mmx/sse2. But by saying we need secondary memory we discourage the
25201 register allocator from using the mmx registers unless needed. */
25202 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25205 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25207 /* SSE1 doesn't have any direct moves from other classes. */
25211 /* If the target says that inter-unit moves are more expensive
25212 than moving through memory, then don't generate them. */
25213 if (!TARGET_INTER_UNIT_MOVES)
25216 /* Between SSE and general, we have moves no larger than word size. */
25217 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25225 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25226 enum machine_mode mode, int strict)
25228 return inline_secondary_memory_needed (class1, class2, mode, strict);
25231 /* Return true if the registers in CLASS cannot represent the change from
25232 modes FROM to TO. */
25235 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25236 enum reg_class regclass)
25241 /* x87 registers can't do subreg at all, as all values are reformatted
25242 to extended precision. */
25243 if (MAYBE_FLOAT_CLASS_P (regclass))
25246 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25248 /* Vector registers do not support QI or HImode loads. If we don't
25249 disallow a change to these modes, reload will assume it's ok to
25250 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25251 the vec_dupv4hi pattern. */
25252 if (GET_MODE_SIZE (from) < 4)
25255 /* Vector registers do not support subreg with nonzero offsets, which
25256 are otherwise valid for integer registers. Since we can't see
25257 whether we have a nonzero offset from here, prohibit all
25258 nonparadoxical subregs changing size. */
25259 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25266 /* Return the cost of moving data of mode M between a
25267 register and memory. A value of 2 is the default; this cost is
25268 relative to those in `REGISTER_MOVE_COST'.
25270 This function is used extensively by register_move_cost that is used to
25271 build tables at startup. Make it inline in this case.
25272 When IN is 2, return maximum of in and out move cost.
25274 If moving between registers and memory is more expensive than
25275 between two registers, you should define this macro to express the
25278 Model also increased moving costs of QImode registers in non
25282 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25286 if (FLOAT_CLASS_P (regclass))
25304 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25305 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25307 if (SSE_CLASS_P (regclass))
25310 switch (GET_MODE_SIZE (mode))
25325 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25326 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25328 if (MMX_CLASS_P (regclass))
25331 switch (GET_MODE_SIZE (mode))
25343 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25344 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25346 switch (GET_MODE_SIZE (mode))
25349 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25352 return ix86_cost->int_store[0];
25353 if (TARGET_PARTIAL_REG_DEPENDENCY
25354 && optimize_function_for_speed_p (cfun))
25355 cost = ix86_cost->movzbl_load;
25357 cost = ix86_cost->int_load[0];
25359 return MAX (cost, ix86_cost->int_store[0]);
25365 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25367 return ix86_cost->movzbl_load;
25369 return ix86_cost->int_store[0] + 4;
25374 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25375 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25377 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25378 if (mode == TFmode)
25381 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25383 cost = ix86_cost->int_load[2];
25385 cost = ix86_cost->int_store[2];
25386 return (cost * (((int) GET_MODE_SIZE (mode)
25387 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25392 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25394 return inline_memory_move_cost (mode, regclass, in);
25398 /* Return the cost of moving data from a register in class CLASS1 to
25399 one in class CLASS2.
25401 It is not required that the cost always equal 2 when FROM is the same as TO;
25402 on some machines it is expensive to move between registers if they are not
25403 general registers. */
25406 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25407 enum reg_class class2)
25409 /* In case we require secondary memory, compute cost of the store followed
25410 by load. In order to avoid bad register allocation choices, we need
25411 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25413 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25417 cost += inline_memory_move_cost (mode, class1, 2);
25418 cost += inline_memory_move_cost (mode, class2, 2);
25420 /* In case of copying from general_purpose_register we may emit multiple
25421 stores followed by single load causing memory size mismatch stall.
25422 Count this as arbitrarily high cost of 20. */
25423 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25426 /* In the case of FP/MMX moves, the registers actually overlap, and we
25427 have to switch modes in order to treat them differently. */
25428 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25429 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25435 /* Moves between SSE/MMX and integer unit are expensive. */
25436 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25437 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25439 /* ??? By keeping returned value relatively high, we limit the number
25440 of moves between integer and MMX/SSE registers for all targets.
25441 Additionally, high value prevents problem with x86_modes_tieable_p(),
25442 where integer modes in MMX/SSE registers are not tieable
25443 because of missing QImode and HImode moves to, from or between
25444 MMX/SSE registers. */
25445 return MAX (8, ix86_cost->mmxsse_to_integer);
25447 if (MAYBE_FLOAT_CLASS_P (class1))
25448 return ix86_cost->fp_move;
25449 if (MAYBE_SSE_CLASS_P (class1))
25450 return ix86_cost->sse_move;
25451 if (MAYBE_MMX_CLASS_P (class1))
25452 return ix86_cost->mmx_move;
25456 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25459 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25461 /* Flags and only flags can only hold CCmode values. */
25462 if (CC_REGNO_P (regno))
25463 return GET_MODE_CLASS (mode) == MODE_CC;
25464 if (GET_MODE_CLASS (mode) == MODE_CC
25465 || GET_MODE_CLASS (mode) == MODE_RANDOM
25466 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25468 if (FP_REGNO_P (regno))
25469 return VALID_FP_MODE_P (mode);
25470 if (SSE_REGNO_P (regno))
25472 /* We implement the move patterns for all vector modes into and
25473 out of SSE registers, even when no operation instructions
25474 are available. OImode move is available only when AVX is
25476 return ((TARGET_AVX && mode == OImode)
25477 || VALID_AVX256_REG_MODE (mode)
25478 || VALID_SSE_REG_MODE (mode)
25479 || VALID_SSE2_REG_MODE (mode)
25480 || VALID_MMX_REG_MODE (mode)
25481 || VALID_MMX_REG_MODE_3DNOW (mode));
25483 if (MMX_REGNO_P (regno))
25485 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25486 so if the register is available at all, then we can move data of
25487 the given mode into or out of it. */
25488 return (VALID_MMX_REG_MODE (mode)
25489 || VALID_MMX_REG_MODE_3DNOW (mode));
25492 if (mode == QImode)
25494 /* Take care for QImode values - they can be in non-QI regs,
25495 but then they do cause partial register stalls. */
25496 if (regno <= BX_REG || TARGET_64BIT)
25498 if (!TARGET_PARTIAL_REG_STALL)
25500 return reload_in_progress || reload_completed;
25502 /* We handle both integer and floats in the general purpose registers. */
25503 else if (VALID_INT_MODE_P (mode))
25505 else if (VALID_FP_MODE_P (mode))
25507 else if (VALID_DFP_MODE_P (mode))
25509 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25510 on to use that value in smaller contexts, this can easily force a
25511 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25512 supporting DImode, allow it. */
25513 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25519 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25520 tieable integer mode. */
25523 ix86_tieable_integer_mode_p (enum machine_mode mode)
25532 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25535 return TARGET_64BIT;
25542 /* Return true if MODE1 is accessible in a register that can hold MODE2
25543 without copying. That is, all register classes that can hold MODE2
25544 can also hold MODE1. */
25547 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25549 if (mode1 == mode2)
25552 if (ix86_tieable_integer_mode_p (mode1)
25553 && ix86_tieable_integer_mode_p (mode2))
25556 /* MODE2 being XFmode implies fp stack or general regs, which means we
25557 can tie any smaller floating point modes to it. Note that we do not
25558 tie this with TFmode. */
25559 if (mode2 == XFmode)
25560 return mode1 == SFmode || mode1 == DFmode;
25562 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
25563 that we can tie it with SFmode. */
25564 if (mode2 == DFmode)
25565 return mode1 == SFmode;
25567 /* If MODE2 is only appropriate for an SSE register, then tie with
25568 any other mode acceptable to SSE registers. */
25569 if (GET_MODE_SIZE (mode2) == 16
25570 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
25571 return (GET_MODE_SIZE (mode1) == 16
25572 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
25574 /* If MODE2 is appropriate for an MMX register, then tie
25575 with any other mode acceptable to MMX registers. */
25576 if (GET_MODE_SIZE (mode2) == 8
25577 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
25578 return (GET_MODE_SIZE (mode1) == 8
25579 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
25584 /* Compute a (partial) cost for rtx X. Return true if the complete
25585 cost has been computed, and false if subexpressions should be
25586 scanned. In either case, *TOTAL contains the cost result. */
25589 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
25591 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
25592 enum machine_mode mode = GET_MODE (x);
25593 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
25601 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
25603 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
25605 else if (flag_pic && SYMBOLIC_CONST (x)
25607 || (!GET_CODE (x) != LABEL_REF
25608 && (GET_CODE (x) != SYMBOL_REF
25609 || !SYMBOL_REF_LOCAL_P (x)))))
25616 if (mode == VOIDmode)
25619 switch (standard_80387_constant_p (x))
25624 default: /* Other constants */
25629 /* Start with (MEM (SYMBOL_REF)), since that's where
25630 it'll probably end up. Add a penalty for size. */
25631 *total = (COSTS_N_INSNS (1)
25632 + (flag_pic != 0 && !TARGET_64BIT)
25633 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
25639 /* The zero extensions is often completely free on x86_64, so make
25640 it as cheap as possible. */
25641 if (TARGET_64BIT && mode == DImode
25642 && GET_MODE (XEXP (x, 0)) == SImode)
25644 else if (TARGET_ZERO_EXTEND_WITH_AND)
25645 *total = cost->add;
25647 *total = cost->movzx;
25651 *total = cost->movsx;
25655 if (CONST_INT_P (XEXP (x, 1))
25656 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
25658 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25661 *total = cost->add;
25664 if ((value == 2 || value == 3)
25665 && cost->lea <= cost->shift_const)
25667 *total = cost->lea;
25677 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
25679 if (CONST_INT_P (XEXP (x, 1)))
25681 if (INTVAL (XEXP (x, 1)) > 32)
25682 *total = cost->shift_const + COSTS_N_INSNS (2);
25684 *total = cost->shift_const * 2;
25688 if (GET_CODE (XEXP (x, 1)) == AND)
25689 *total = cost->shift_var * 2;
25691 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
25696 if (CONST_INT_P (XEXP (x, 1)))
25697 *total = cost->shift_const;
25699 *total = cost->shift_var;
25704 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25706 /* ??? SSE scalar cost should be used here. */
25707 *total = cost->fmul;
25710 else if (X87_FLOAT_MODE_P (mode))
25712 *total = cost->fmul;
25715 else if (FLOAT_MODE_P (mode))
25717 /* ??? SSE vector cost should be used here. */
25718 *total = cost->fmul;
25723 rtx op0 = XEXP (x, 0);
25724 rtx op1 = XEXP (x, 1);
25726 if (CONST_INT_P (XEXP (x, 1)))
25728 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
25729 for (nbits = 0; value != 0; value &= value - 1)
25733 /* This is arbitrary. */
25736 /* Compute costs correctly for widening multiplication. */
25737 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
25738 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
25739 == GET_MODE_SIZE (mode))
25741 int is_mulwiden = 0;
25742 enum machine_mode inner_mode = GET_MODE (op0);
25744 if (GET_CODE (op0) == GET_CODE (op1))
25745 is_mulwiden = 1, op1 = XEXP (op1, 0);
25746 else if (CONST_INT_P (op1))
25748 if (GET_CODE (op0) == SIGN_EXTEND)
25749 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
25752 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
25756 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
25759 *total = (cost->mult_init[MODE_INDEX (mode)]
25760 + nbits * cost->mult_bit
25761 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
25770 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25771 /* ??? SSE cost should be used here. */
25772 *total = cost->fdiv;
25773 else if (X87_FLOAT_MODE_P (mode))
25774 *total = cost->fdiv;
25775 else if (FLOAT_MODE_P (mode))
25776 /* ??? SSE vector cost should be used here. */
25777 *total = cost->fdiv;
25779 *total = cost->divide[MODE_INDEX (mode)];
25783 if (GET_MODE_CLASS (mode) == MODE_INT
25784 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
25786 if (GET_CODE (XEXP (x, 0)) == PLUS
25787 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
25788 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
25789 && CONSTANT_P (XEXP (x, 1)))
25791 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
25792 if (val == 2 || val == 4 || val == 8)
25794 *total = cost->lea;
25795 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
25796 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
25797 outer_code, speed);
25798 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25802 else if (GET_CODE (XEXP (x, 0)) == MULT
25803 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
25805 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
25806 if (val == 2 || val == 4 || val == 8)
25808 *total = cost->lea;
25809 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
25810 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25814 else if (GET_CODE (XEXP (x, 0)) == PLUS)
25816 *total = cost->lea;
25817 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
25818 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
25819 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
25826 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25828 /* ??? SSE cost should be used here. */
25829 *total = cost->fadd;
25832 else if (X87_FLOAT_MODE_P (mode))
25834 *total = cost->fadd;
25837 else if (FLOAT_MODE_P (mode))
25839 /* ??? SSE vector cost should be used here. */
25840 *total = cost->fadd;
25848 if (!TARGET_64BIT && mode == DImode)
25850 *total = (cost->add * 2
25851 + (rtx_cost (XEXP (x, 0), outer_code, speed)
25852 << (GET_MODE (XEXP (x, 0)) != DImode))
25853 + (rtx_cost (XEXP (x, 1), outer_code, speed)
25854 << (GET_MODE (XEXP (x, 1)) != DImode)));
25860 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25862 /* ??? SSE cost should be used here. */
25863 *total = cost->fchs;
25866 else if (X87_FLOAT_MODE_P (mode))
25868 *total = cost->fchs;
25871 else if (FLOAT_MODE_P (mode))
25873 /* ??? SSE vector cost should be used here. */
25874 *total = cost->fchs;
25880 if (!TARGET_64BIT && mode == DImode)
25881 *total = cost->add * 2;
25883 *total = cost->add;
25887 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
25888 && XEXP (XEXP (x, 0), 1) == const1_rtx
25889 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
25890 && XEXP (x, 1) == const0_rtx)
25892 /* This kind of construct is implemented using test[bwl].
25893 Treat it as if we had an AND. */
25894 *total = (cost->add
25895 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
25896 + rtx_cost (const1_rtx, outer_code, speed));
25902 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
25907 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25908 /* ??? SSE cost should be used here. */
25909 *total = cost->fabs;
25910 else if (X87_FLOAT_MODE_P (mode))
25911 *total = cost->fabs;
25912 else if (FLOAT_MODE_P (mode))
25913 /* ??? SSE vector cost should be used here. */
25914 *total = cost->fabs;
25918 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
25919 /* ??? SSE cost should be used here. */
25920 *total = cost->fsqrt;
25921 else if (X87_FLOAT_MODE_P (mode))
25922 *total = cost->fsqrt;
25923 else if (FLOAT_MODE_P (mode))
25924 /* ??? SSE vector cost should be used here. */
25925 *total = cost->fsqrt;
25929 if (XINT (x, 1) == UNSPEC_TP)
25940 static int current_machopic_label_num;
25942 /* Given a symbol name and its associated stub, write out the
25943 definition of the stub. */
25946 machopic_output_stub (FILE *file, const char *symb, const char *stub)
25948 unsigned int length;
25949 char *binder_name, *symbol_name, lazy_ptr_name[32];
25950 int label = ++current_machopic_label_num;
25952 /* For 64-bit we shouldn't get here. */
25953 gcc_assert (!TARGET_64BIT);
25955 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
25956 symb = (*targetm.strip_name_encoding) (symb);
25958 length = strlen (stub);
25959 binder_name = XALLOCAVEC (char, length + 32);
25960 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
25962 length = strlen (symb);
25963 symbol_name = XALLOCAVEC (char, length + 32);
25964 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
25966 sprintf (lazy_ptr_name, "L%d$lz", label);
25969 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
25971 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
25973 fprintf (file, "%s:\n", stub);
25974 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
25978 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
25979 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
25980 fprintf (file, "\tjmp\t*%%edx\n");
25983 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
25985 fprintf (file, "%s:\n", binder_name);
25989 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
25990 fputs ("\tpushl\t%eax\n", file);
25993 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
25995 fputs ("\tjmp\tdyld_stub_binding_helper\n", file);
25997 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
25998 fprintf (file, "%s:\n", lazy_ptr_name);
25999 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26000 fprintf (file, ASM_LONG "%s\n", binder_name);
26004 darwin_x86_file_end (void)
26006 darwin_file_end ();
26009 #endif /* TARGET_MACHO */
26011 /* Order the registers for register allocator. */
26014 x86_order_regs_for_local_alloc (void)
26019 /* First allocate the local general purpose registers. */
26020 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26021 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26022 reg_alloc_order [pos++] = i;
26024 /* Global general purpose registers. */
26025 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26026 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26027 reg_alloc_order [pos++] = i;
26029 /* x87 registers come first in case we are doing FP math
26031 if (!TARGET_SSE_MATH)
26032 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26033 reg_alloc_order [pos++] = i;
26035 /* SSE registers. */
26036 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26037 reg_alloc_order [pos++] = i;
26038 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26039 reg_alloc_order [pos++] = i;
26041 /* x87 registers. */
26042 if (TARGET_SSE_MATH)
26043 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26044 reg_alloc_order [pos++] = i;
26046 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26047 reg_alloc_order [pos++] = i;
26049 /* Initialize the rest of array as we do not allocate some registers
26051 while (pos < FIRST_PSEUDO_REGISTER)
26052 reg_alloc_order [pos++] = 0;
26055 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26056 struct attribute_spec.handler. */
26058 ix86_handle_abi_attribute (tree *node, tree name,
26059 tree args ATTRIBUTE_UNUSED,
26060 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26062 if (TREE_CODE (*node) != FUNCTION_TYPE
26063 && TREE_CODE (*node) != METHOD_TYPE
26064 && TREE_CODE (*node) != FIELD_DECL
26065 && TREE_CODE (*node) != TYPE_DECL)
26067 warning (OPT_Wattributes, "%qE attribute only applies to functions",
26069 *no_add_attrs = true;
26074 warning (OPT_Wattributes, "%qE attribute only available for 64-bit",
26076 *no_add_attrs = true;
26080 /* Can combine regparm with all attributes but fastcall. */
26081 if (is_attribute_p ("ms_abi", name))
26083 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26085 error ("ms_abi and sysv_abi attributes are not compatible");
26090 else if (is_attribute_p ("sysv_abi", name))
26092 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26094 error ("ms_abi and sysv_abi attributes are not compatible");
26103 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26104 struct attribute_spec.handler. */
26106 ix86_handle_struct_attribute (tree *node, tree name,
26107 tree args ATTRIBUTE_UNUSED,
26108 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26111 if (DECL_P (*node))
26113 if (TREE_CODE (*node) == TYPE_DECL)
26114 type = &TREE_TYPE (*node);
26119 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26120 || TREE_CODE (*type) == UNION_TYPE)))
26122 warning (OPT_Wattributes, "%qE attribute ignored",
26124 *no_add_attrs = true;
26127 else if ((is_attribute_p ("ms_struct", name)
26128 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26129 || ((is_attribute_p ("gcc_struct", name)
26130 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26132 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
26134 *no_add_attrs = true;
26141 ix86_ms_bitfield_layout_p (const_tree record_type)
26143 return (TARGET_MS_BITFIELD_LAYOUT &&
26144 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26145 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26148 /* Returns an expression indicating where the this parameter is
26149 located on entry to the FUNCTION. */
26152 x86_this_parameter (tree function)
26154 tree type = TREE_TYPE (function);
26155 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26160 const int *parm_regs;
26162 if (ix86_function_type_abi (type) == MS_ABI)
26163 parm_regs = x86_64_ms_abi_int_parameter_registers;
26165 parm_regs = x86_64_int_parameter_registers;
26166 return gen_rtx_REG (DImode, parm_regs[aggr]);
26169 nregs = ix86_function_regparm (type, function);
26171 if (nregs > 0 && !stdarg_p (type))
26175 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26176 regno = aggr ? DX_REG : CX_REG;
26184 return gen_rtx_MEM (SImode,
26185 plus_constant (stack_pointer_rtx, 4));
26188 return gen_rtx_REG (SImode, regno);
26191 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26194 /* Determine whether x86_output_mi_thunk can succeed. */
26197 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26198 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26199 HOST_WIDE_INT vcall_offset, const_tree function)
26201 /* 64-bit can handle anything. */
26205 /* For 32-bit, everything's fine if we have one free register. */
26206 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26209 /* Need a free register for vcall_offset. */
26213 /* Need a free register for GOT references. */
26214 if (flag_pic && !(*targetm.binds_local_p) (function))
26217 /* Otherwise ok. */
26221 /* Output the assembler code for a thunk function. THUNK_DECL is the
26222 declaration for the thunk function itself, FUNCTION is the decl for
26223 the target function. DELTA is an immediate constant offset to be
26224 added to THIS. If VCALL_OFFSET is nonzero, the word at
26225 *(*this + vcall_offset) should be added to THIS. */
26228 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26229 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26230 HOST_WIDE_INT vcall_offset, tree function)
26233 rtx this_param = x86_this_parameter (function);
26236 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26237 pull it in now and let DELTA benefit. */
26238 if (REG_P (this_param))
26239 this_reg = this_param;
26240 else if (vcall_offset)
26242 /* Put the this parameter into %eax. */
26243 xops[0] = this_param;
26244 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26245 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26248 this_reg = NULL_RTX;
26250 /* Adjust the this parameter by a fixed constant. */
26253 xops[0] = GEN_INT (delta);
26254 xops[1] = this_reg ? this_reg : this_param;
26257 if (!x86_64_general_operand (xops[0], DImode))
26259 tmp = gen_rtx_REG (DImode, R10_REG);
26261 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26263 xops[1] = this_param;
26265 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26268 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26271 /* Adjust the this parameter by a value stored in the vtable. */
26275 tmp = gen_rtx_REG (DImode, R10_REG);
26278 int tmp_regno = CX_REG;
26279 if (lookup_attribute ("fastcall",
26280 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26281 tmp_regno = AX_REG;
26282 tmp = gen_rtx_REG (SImode, tmp_regno);
26285 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26287 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26289 /* Adjust the this parameter. */
26290 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26291 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26293 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26294 xops[0] = GEN_INT (vcall_offset);
26296 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26297 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26299 xops[1] = this_reg;
26300 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26303 /* If necessary, drop THIS back to its stack slot. */
26304 if (this_reg && this_reg != this_param)
26306 xops[0] = this_reg;
26307 xops[1] = this_param;
26308 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26311 xops[0] = XEXP (DECL_RTL (function), 0);
26314 if (!flag_pic || (*targetm.binds_local_p) (function))
26315 output_asm_insn ("jmp\t%P0", xops);
26316 /* All thunks should be in the same object as their target,
26317 and thus binds_local_p should be true. */
26318 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26319 gcc_unreachable ();
26322 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26323 tmp = gen_rtx_CONST (Pmode, tmp);
26324 tmp = gen_rtx_MEM (QImode, tmp);
26326 output_asm_insn ("jmp\t%A0", xops);
26331 if (!flag_pic || (*targetm.binds_local_p) (function))
26332 output_asm_insn ("jmp\t%P0", xops);
26337 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26338 tmp = (gen_rtx_SYMBOL_REF
26340 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26341 tmp = gen_rtx_MEM (QImode, tmp);
26343 output_asm_insn ("jmp\t%0", xops);
26346 #endif /* TARGET_MACHO */
26348 tmp = gen_rtx_REG (SImode, CX_REG);
26349 output_set_got (tmp, NULL_RTX);
26352 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26353 output_asm_insn ("jmp\t{*}%1", xops);
26359 x86_file_start (void)
26361 default_file_start ();
26363 darwin_file_start ();
26365 if (X86_FILE_START_VERSION_DIRECTIVE)
26366 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26367 if (X86_FILE_START_FLTUSED)
26368 fputs ("\t.global\t__fltused\n", asm_out_file);
26369 if (ix86_asm_dialect == ASM_INTEL)
26370 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26374 x86_field_alignment (tree field, int computed)
26376 enum machine_mode mode;
26377 tree type = TREE_TYPE (field);
26379 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26381 mode = TYPE_MODE (strip_array_types (type));
26382 if (mode == DFmode || mode == DCmode
26383 || GET_MODE_CLASS (mode) == MODE_INT
26384 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26385 return MIN (32, computed);
26389 /* Output assembler code to FILE to increment profiler label # LABELNO
26390 for profiling a function entry. */
26392 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26396 #ifndef NO_PROFILE_COUNTERS
26397 fprintf (file, "\tleaq\t" LPREFIX "P%d@(%%rip),%%r11\n", labelno);
26400 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26401 fputs ("\tcall\t*" MCOUNT_NAME "@GOTPCREL(%rip)\n", file);
26403 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
26407 #ifndef NO_PROFILE_COUNTERS
26408 fprintf (file, "\tleal\t" LPREFIX "P%d@GOTOFF(%%ebx),%%" PROFILE_COUNT_REGISTER "\n",
26411 fputs ("\tcall\t*" MCOUNT_NAME "@GOT(%ebx)\n", file);
26415 #ifndef NO_PROFILE_COUNTERS
26416 fprintf (file, "\tmovl\t$" LPREFIX "P%d,%%" PROFILE_COUNT_REGISTER "\n",
26419 fputs ("\tcall\t" MCOUNT_NAME "\n", file);
26423 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26424 /* We don't have exact information about the insn sizes, but we may assume
26425 quite safely that we are informed about all 1 byte insns and memory
26426 address sizes. This is enough to eliminate unnecessary padding in
26430 min_insn_size (rtx insn)
26434 if (!INSN_P (insn) || !active_insn_p (insn))
26437 /* Discard alignments we've emit and jump instructions. */
26438 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26439 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26441 if (JUMP_TABLE_DATA_P (insn))
26444 /* Important case - calls are always 5 bytes.
26445 It is common to have many calls in the row. */
26447 && symbolic_reference_mentioned_p (PATTERN (insn))
26448 && !SIBLING_CALL_P (insn))
26450 len = get_attr_length (insn);
26454 /* For normal instructions we rely on get_attr_length being exact,
26455 with a few exceptions. */
26456 if (!JUMP_P (insn))
26458 enum attr_type type = get_attr_type (insn);
26463 if (GET_CODE (PATTERN (insn)) == ASM_INPUT
26464 || asm_noperands (PATTERN (insn)) >= 0)
26471 /* Otherwise trust get_attr_length. */
26475 l = get_attr_length_address (insn);
26476 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26485 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26489 ix86_avoid_jump_mispredicts (void)
26491 rtx insn, start = get_insns ();
26492 int nbytes = 0, njumps = 0;
26495 /* Look for all minimal intervals of instructions containing 4 jumps.
26496 The intervals are bounded by START and INSN. NBYTES is the total
26497 size of instructions in the interval including INSN and not including
26498 START. When the NBYTES is smaller than 16 bytes, it is possible
26499 that the end of START and INSN ends up in the same 16byte page.
26501 The smallest offset in the page INSN can start is the case where START
26502 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26503 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
26505 for (insn = start; insn; insn = NEXT_INSN (insn))
26509 if (LABEL_P (insn))
26511 int align = label_to_alignment (insn);
26512 int max_skip = label_to_max_skip (insn);
26516 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
26517 already in the current 16 byte page, because otherwise
26518 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
26519 bytes to reach 16 byte boundary. */
26521 || (align <= 3 && max_skip != (1 << align) - 1))
26524 fprintf (dump_file, "Label %i with max_skip %i\n",
26525 INSN_UID (insn), max_skip);
26528 while (nbytes + max_skip >= 16)
26530 start = NEXT_INSN (start);
26531 if ((JUMP_P (start)
26532 && GET_CODE (PATTERN (start)) != ADDR_VEC
26533 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26535 njumps--, isjump = 1;
26538 nbytes -= min_insn_size (start);
26544 min_size = min_insn_size (insn);
26545 nbytes += min_size;
26547 fprintf (dump_file, "Insn %i estimated to %i bytes\n",
26548 INSN_UID (insn), min_size);
26550 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26551 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26559 start = NEXT_INSN (start);
26560 if ((JUMP_P (start)
26561 && GET_CODE (PATTERN (start)) != ADDR_VEC
26562 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26564 njumps--, isjump = 1;
26567 nbytes -= min_insn_size (start);
26569 gcc_assert (njumps >= 0);
26571 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26572 INSN_UID (start), INSN_UID (insn), nbytes);
26574 if (njumps == 3 && isjump && nbytes < 16)
26576 int padsize = 15 - nbytes + min_insn_size (insn);
26579 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26580 INSN_UID (insn), padsize);
26581 emit_insn_before (gen_pad (GEN_INT (padsize)), insn);
26587 /* AMD Athlon works faster
26588 when RET is not destination of conditional jump or directly preceded
26589 by other jump instruction. We avoid the penalty by inserting NOP just
26590 before the RET instructions in such cases. */
26592 ix86_pad_returns (void)
26597 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26599 basic_block bb = e->src;
26600 rtx ret = BB_END (bb);
26602 bool replace = false;
26604 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26605 || optimize_bb_for_size_p (bb))
26607 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
26608 if (active_insn_p (prev) || LABEL_P (prev))
26610 if (prev && LABEL_P (prev))
26615 FOR_EACH_EDGE (e, ei, bb->preds)
26616 if (EDGE_FREQUENCY (e) && e->src->index >= 0
26617 && !(e->flags & EDGE_FALLTHRU))
26622 prev = prev_active_insn (ret);
26624 && ((JUMP_P (prev) && any_condjump_p (prev))
26627 /* Empty functions get branch mispredict even when the jump destination
26628 is not visible to us. */
26629 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
26634 emit_jump_insn_before (gen_return_internal_long (), ret);
26640 /* Implement machine specific optimizations. We implement padding of returns
26641 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
26645 if (optimize && optimize_function_for_speed_p (cfun))
26647 if (TARGET_PAD_RETURNS)
26648 ix86_pad_returns ();
26649 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
26650 if (TARGET_FOUR_JUMP_LIMIT)
26651 ix86_avoid_jump_mispredicts ();
26656 /* Return nonzero when QImode register that must be represented via REX prefix
26659 x86_extended_QIreg_mentioned_p (rtx insn)
26662 extract_insn_cached (insn);
26663 for (i = 0; i < recog_data.n_operands; i++)
26664 if (REG_P (recog_data.operand[i])
26665 && REGNO (recog_data.operand[i]) > BX_REG)
26670 /* Return nonzero when P points to register encoded via REX prefix.
26671 Called via for_each_rtx. */
26673 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
26675 unsigned int regno;
26678 regno = REGNO (*p);
26679 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
26682 /* Return true when INSN mentions register that must be encoded using REX
26685 x86_extended_reg_mentioned_p (rtx insn)
26687 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
26688 extended_reg_mentioned_1, NULL);
26691 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
26692 optabs would emit if we didn't have TFmode patterns. */
26695 x86_emit_floatuns (rtx operands[2])
26697 rtx neglab, donelab, i0, i1, f0, in, out;
26698 enum machine_mode mode, inmode;
26700 inmode = GET_MODE (operands[1]);
26701 gcc_assert (inmode == SImode || inmode == DImode);
26704 in = force_reg (inmode, operands[1]);
26705 mode = GET_MODE (out);
26706 neglab = gen_label_rtx ();
26707 donelab = gen_label_rtx ();
26708 f0 = gen_reg_rtx (mode);
26710 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
26712 expand_float (out, in, 0);
26714 emit_jump_insn (gen_jump (donelab));
26717 emit_label (neglab);
26719 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
26721 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
26723 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
26725 expand_float (f0, i0, 0);
26727 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
26729 emit_label (donelab);
26732 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26733 with all elements equal to VAR. Return true if successful. */
26736 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
26737 rtx target, rtx val)
26739 enum machine_mode hmode, smode, wsmode, wvmode;
26754 val = force_reg (GET_MODE_INNER (mode), val);
26755 x = gen_rtx_VEC_DUPLICATE (mode, val);
26756 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26762 if (TARGET_SSE || TARGET_3DNOW_A)
26764 val = gen_lowpart (SImode, val);
26765 x = gen_rtx_TRUNCATE (HImode, val);
26766 x = gen_rtx_VEC_DUPLICATE (mode, x);
26767 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26789 /* Extend HImode to SImode using a paradoxical SUBREG. */
26790 tmp1 = gen_reg_rtx (SImode);
26791 emit_move_insn (tmp1, gen_lowpart (SImode, val));
26792 /* Insert the SImode value as low element of V4SImode vector. */
26793 tmp2 = gen_reg_rtx (V4SImode);
26794 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
26795 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
26796 CONST0_RTX (V4SImode),
26798 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
26799 /* Cast the V4SImode vector back to a V8HImode vector. */
26800 tmp1 = gen_reg_rtx (V8HImode);
26801 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
26802 /* Duplicate the low short through the whole low SImode word. */
26803 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
26804 /* Cast the V8HImode vector back to a V4SImode vector. */
26805 tmp2 = gen_reg_rtx (V4SImode);
26806 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
26807 /* Replicate the low element of the V4SImode vector. */
26808 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
26809 /* Cast the V2SImode back to V8HImode, and store in target. */
26810 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
26821 /* Extend QImode to SImode using a paradoxical SUBREG. */
26822 tmp1 = gen_reg_rtx (SImode);
26823 emit_move_insn (tmp1, gen_lowpart (SImode, val));
26824 /* Insert the SImode value as low element of V4SImode vector. */
26825 tmp2 = gen_reg_rtx (V4SImode);
26826 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
26827 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
26828 CONST0_RTX (V4SImode),
26830 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
26831 /* Cast the V4SImode vector back to a V16QImode vector. */
26832 tmp1 = gen_reg_rtx (V16QImode);
26833 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
26834 /* Duplicate the low byte through the whole low SImode word. */
26835 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
26836 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
26837 /* Cast the V16QImode vector back to a V4SImode vector. */
26838 tmp2 = gen_reg_rtx (V4SImode);
26839 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
26840 /* Replicate the low element of the V4SImode vector. */
26841 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
26842 /* Cast the V2SImode back to V16QImode, and store in target. */
26843 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
26851 /* Replicate the value once into the next wider mode and recurse. */
26852 val = convert_modes (wsmode, smode, val, true);
26853 x = expand_simple_binop (wsmode, ASHIFT, val,
26854 GEN_INT (GET_MODE_BITSIZE (smode)),
26855 NULL_RTX, 1, OPTAB_LIB_WIDEN);
26856 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
26858 x = gen_reg_rtx (wvmode);
26859 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
26860 gcc_unreachable ();
26861 emit_move_insn (target, gen_lowpart (mode, x));
26884 rtx tmp = gen_reg_rtx (hmode);
26885 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
26886 emit_insn (gen_rtx_SET (VOIDmode, target,
26887 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
26896 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
26897 whose ONE_VAR element is VAR, and other elements are zero. Return true
26901 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
26902 rtx target, rtx var, int one_var)
26904 enum machine_mode vsimode;
26907 bool use_vector_set = false;
26912 /* For SSE4.1, we normally use vector set. But if the second
26913 element is zero and inter-unit moves are OK, we use movq
26915 use_vector_set = (TARGET_64BIT
26917 && !(TARGET_INTER_UNIT_MOVES
26923 use_vector_set = TARGET_SSE4_1;
26926 use_vector_set = TARGET_SSE2;
26929 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
26936 use_vector_set = TARGET_AVX;
26939 /* Use ix86_expand_vector_set in 64bit mode only. */
26940 use_vector_set = TARGET_AVX && TARGET_64BIT;
26946 if (use_vector_set)
26948 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
26949 var = force_reg (GET_MODE_INNER (mode), var);
26950 ix86_expand_vector_set (mmx_ok, target, var, one_var);
26966 var = force_reg (GET_MODE_INNER (mode), var);
26967 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
26968 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26973 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
26974 new_target = gen_reg_rtx (mode);
26976 new_target = target;
26977 var = force_reg (GET_MODE_INNER (mode), var);
26978 x = gen_rtx_VEC_DUPLICATE (mode, var);
26979 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
26980 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
26983 /* We need to shuffle the value to the correct position, so
26984 create a new pseudo to store the intermediate result. */
26986 /* With SSE2, we can use the integer shuffle insns. */
26987 if (mode != V4SFmode && TARGET_SSE2)
26989 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
26991 GEN_INT (one_var == 1 ? 0 : 1),
26992 GEN_INT (one_var == 2 ? 0 : 1),
26993 GEN_INT (one_var == 3 ? 0 : 1)));
26994 if (target != new_target)
26995 emit_move_insn (target, new_target);
26999 /* Otherwise convert the intermediate result to V4SFmode and
27000 use the SSE1 shuffle instructions. */
27001 if (mode != V4SFmode)
27003 tmp = gen_reg_rtx (V4SFmode);
27004 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27009 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27011 GEN_INT (one_var == 1 ? 0 : 1),
27012 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27013 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27015 if (mode != V4SFmode)
27016 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27017 else if (tmp != target)
27018 emit_move_insn (target, tmp);
27020 else if (target != new_target)
27021 emit_move_insn (target, new_target);
27026 vsimode = V4SImode;
27032 vsimode = V2SImode;
27038 /* Zero extend the variable element to SImode and recurse. */
27039 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27041 x = gen_reg_rtx (vsimode);
27042 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27044 gcc_unreachable ();
27046 emit_move_insn (target, gen_lowpart (mode, x));
27054 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27055 consisting of the values in VALS. It is known that all elements
27056 except ONE_VAR are constants. Return true if successful. */
27059 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27060 rtx target, rtx vals, int one_var)
27062 rtx var = XVECEXP (vals, 0, one_var);
27063 enum machine_mode wmode;
27066 const_vec = copy_rtx (vals);
27067 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27068 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27076 /* For the two element vectors, it's just as easy to use
27077 the general case. */
27081 /* Use ix86_expand_vector_set in 64bit mode only. */
27104 /* There's no way to set one QImode entry easily. Combine
27105 the variable value with its adjacent constant value, and
27106 promote to an HImode set. */
27107 x = XVECEXP (vals, 0, one_var ^ 1);
27110 var = convert_modes (HImode, QImode, var, true);
27111 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27112 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27113 x = GEN_INT (INTVAL (x) & 0xff);
27117 var = convert_modes (HImode, QImode, var, true);
27118 x = gen_int_mode (INTVAL (x) << 8, HImode);
27120 if (x != const0_rtx)
27121 var = expand_simple_binop (HImode, IOR, var, x, var,
27122 1, OPTAB_LIB_WIDEN);
27124 x = gen_reg_rtx (wmode);
27125 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27126 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27128 emit_move_insn (target, gen_lowpart (mode, x));
27135 emit_move_insn (target, const_vec);
27136 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27140 /* A subroutine of ix86_expand_vector_init_general. Use vector
27141 concatenate to handle the most general case: all values variable,
27142 and none identical. */
27145 ix86_expand_vector_init_concat (enum machine_mode mode,
27146 rtx target, rtx *ops, int n)
27148 enum machine_mode cmode, hmode = VOIDmode;
27149 rtx first[8], second[4];
27189 gcc_unreachable ();
27192 if (!register_operand (ops[1], cmode))
27193 ops[1] = force_reg (cmode, ops[1]);
27194 if (!register_operand (ops[0], cmode))
27195 ops[0] = force_reg (cmode, ops[0]);
27196 emit_insn (gen_rtx_SET (VOIDmode, target,
27197 gen_rtx_VEC_CONCAT (mode, ops[0],
27217 gcc_unreachable ();
27233 gcc_unreachable ();
27238 /* FIXME: We process inputs backward to help RA. PR 36222. */
27241 for (; i > 0; i -= 2, j--)
27243 first[j] = gen_reg_rtx (cmode);
27244 v = gen_rtvec (2, ops[i - 1], ops[i]);
27245 ix86_expand_vector_init (false, first[j],
27246 gen_rtx_PARALLEL (cmode, v));
27252 gcc_assert (hmode != VOIDmode);
27253 for (i = j = 0; i < n; i += 2, j++)
27255 second[j] = gen_reg_rtx (hmode);
27256 ix86_expand_vector_init_concat (hmode, second [j],
27260 ix86_expand_vector_init_concat (mode, target, second, n);
27263 ix86_expand_vector_init_concat (mode, target, first, n);
27267 gcc_unreachable ();
27271 /* A subroutine of ix86_expand_vector_init_general. Use vector
27272 interleave to handle the most general case: all values variable,
27273 and none identical. */
27276 ix86_expand_vector_init_interleave (enum machine_mode mode,
27277 rtx target, rtx *ops, int n)
27279 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27282 rtx (*gen_load_even) (rtx, rtx, rtx);
27283 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27284 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27289 gen_load_even = gen_vec_setv8hi;
27290 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27291 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27292 inner_mode = HImode;
27293 first_imode = V4SImode;
27294 second_imode = V2DImode;
27295 third_imode = VOIDmode;
27298 gen_load_even = gen_vec_setv16qi;
27299 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27300 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27301 inner_mode = QImode;
27302 first_imode = V8HImode;
27303 second_imode = V4SImode;
27304 third_imode = V2DImode;
27307 gcc_unreachable ();
27310 for (i = 0; i < n; i++)
27312 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27313 op0 = gen_reg_rtx (SImode);
27314 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27316 /* Insert the SImode value as low element of V4SImode vector. */
27317 op1 = gen_reg_rtx (V4SImode);
27318 op0 = gen_rtx_VEC_MERGE (V4SImode,
27319 gen_rtx_VEC_DUPLICATE (V4SImode,
27321 CONST0_RTX (V4SImode),
27323 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27325 /* Cast the V4SImode vector back to a vector in orignal mode. */
27326 op0 = gen_reg_rtx (mode);
27327 emit_move_insn (op0, gen_lowpart (mode, op1));
27329 /* Load even elements into the second positon. */
27330 emit_insn ((*gen_load_even) (op0,
27331 force_reg (inner_mode,
27335 /* Cast vector to FIRST_IMODE vector. */
27336 ops[i] = gen_reg_rtx (first_imode);
27337 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27340 /* Interleave low FIRST_IMODE vectors. */
27341 for (i = j = 0; i < n; i += 2, j++)
27343 op0 = gen_reg_rtx (first_imode);
27344 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27346 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27347 ops[j] = gen_reg_rtx (second_imode);
27348 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27351 /* Interleave low SECOND_IMODE vectors. */
27352 switch (second_imode)
27355 for (i = j = 0; i < n / 2; i += 2, j++)
27357 op0 = gen_reg_rtx (second_imode);
27358 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27361 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27363 ops[j] = gen_reg_rtx (third_imode);
27364 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27366 second_imode = V2DImode;
27367 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27371 op0 = gen_reg_rtx (second_imode);
27372 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27375 /* Cast the SECOND_IMODE vector back to a vector on original
27377 emit_insn (gen_rtx_SET (VOIDmode, target,
27378 gen_lowpart (mode, op0)));
27382 gcc_unreachable ();
27386 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27387 all values variable, and none identical. */
27390 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27391 rtx target, rtx vals)
27393 rtx ops[32], op0, op1;
27394 enum machine_mode half_mode = VOIDmode;
27401 if (!mmx_ok && !TARGET_SSE)
27413 n = GET_MODE_NUNITS (mode);
27414 for (i = 0; i < n; i++)
27415 ops[i] = XVECEXP (vals, 0, i);
27416 ix86_expand_vector_init_concat (mode, target, ops, n);
27420 half_mode = V16QImode;
27424 half_mode = V8HImode;
27428 n = GET_MODE_NUNITS (mode);
27429 for (i = 0; i < n; i++)
27430 ops[i] = XVECEXP (vals, 0, i);
27431 op0 = gen_reg_rtx (half_mode);
27432 op1 = gen_reg_rtx (half_mode);
27433 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27435 ix86_expand_vector_init_interleave (half_mode, op1,
27436 &ops [n >> 1], n >> 2);
27437 emit_insn (gen_rtx_SET (VOIDmode, target,
27438 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27442 if (!TARGET_SSE4_1)
27450 /* Don't use ix86_expand_vector_init_interleave if we can't
27451 move from GPR to SSE register directly. */
27452 if (!TARGET_INTER_UNIT_MOVES)
27455 n = GET_MODE_NUNITS (mode);
27456 for (i = 0; i < n; i++)
27457 ops[i] = XVECEXP (vals, 0, i);
27458 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27466 gcc_unreachable ();
27470 int i, j, n_elts, n_words, n_elt_per_word;
27471 enum machine_mode inner_mode;
27472 rtx words[4], shift;
27474 inner_mode = GET_MODE_INNER (mode);
27475 n_elts = GET_MODE_NUNITS (mode);
27476 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27477 n_elt_per_word = n_elts / n_words;
27478 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27480 for (i = 0; i < n_words; ++i)
27482 rtx word = NULL_RTX;
27484 for (j = 0; j < n_elt_per_word; ++j)
27486 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27487 elt = convert_modes (word_mode, inner_mode, elt, true);
27493 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27494 word, 1, OPTAB_LIB_WIDEN);
27495 word = expand_simple_binop (word_mode, IOR, word, elt,
27496 word, 1, OPTAB_LIB_WIDEN);
27504 emit_move_insn (target, gen_lowpart (mode, words[0]));
27505 else if (n_words == 2)
27507 rtx tmp = gen_reg_rtx (mode);
27508 emit_clobber (tmp);
27509 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27510 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27511 emit_move_insn (target, tmp);
27513 else if (n_words == 4)
27515 rtx tmp = gen_reg_rtx (V4SImode);
27516 gcc_assert (word_mode == SImode);
27517 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27518 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27519 emit_move_insn (target, gen_lowpart (mode, tmp));
27522 gcc_unreachable ();
27526 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27527 instructions unless MMX_OK is true. */
27530 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27532 enum machine_mode mode = GET_MODE (target);
27533 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27534 int n_elts = GET_MODE_NUNITS (mode);
27535 int n_var = 0, one_var = -1;
27536 bool all_same = true, all_const_zero = true;
27540 for (i = 0; i < n_elts; ++i)
27542 x = XVECEXP (vals, 0, i);
27543 if (!(CONST_INT_P (x)
27544 || GET_CODE (x) == CONST_DOUBLE
27545 || GET_CODE (x) == CONST_FIXED))
27546 n_var++, one_var = i;
27547 else if (x != CONST0_RTX (inner_mode))
27548 all_const_zero = false;
27549 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27553 /* Constants are best loaded from the constant pool. */
27556 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27560 /* If all values are identical, broadcast the value. */
27562 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27563 XVECEXP (vals, 0, 0)))
27566 /* Values where only one field is non-constant are best loaded from
27567 the pool and overwritten via move later. */
27571 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27572 XVECEXP (vals, 0, one_var),
27576 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27580 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27584 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27586 enum machine_mode mode = GET_MODE (target);
27587 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27588 enum machine_mode half_mode;
27589 bool use_vec_merge = false;
27591 static rtx (*gen_extract[6][2]) (rtx, rtx)
27593 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27594 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27595 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27596 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27597 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27598 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27600 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27602 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27603 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27604 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27605 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27606 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27607 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
27617 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
27618 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
27620 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
27622 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
27623 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27629 use_vec_merge = TARGET_SSE4_1;
27637 /* For the two element vectors, we implement a VEC_CONCAT with
27638 the extraction of the other element. */
27640 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
27641 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
27644 op0 = val, op1 = tmp;
27646 op0 = tmp, op1 = val;
27648 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
27649 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27654 use_vec_merge = TARGET_SSE4_1;
27661 use_vec_merge = true;
27665 /* tmp = target = A B C D */
27666 tmp = copy_to_reg (target);
27667 /* target = A A B B */
27668 emit_insn (gen_sse_unpcklps (target, target, target));
27669 /* target = X A B B */
27670 ix86_expand_vector_set (false, target, val, 0);
27671 /* target = A X C D */
27672 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27673 const1_rtx, const0_rtx,
27674 GEN_INT (2+4), GEN_INT (3+4)));
27678 /* tmp = target = A B C D */
27679 tmp = copy_to_reg (target);
27680 /* tmp = X B C D */
27681 ix86_expand_vector_set (false, tmp, val, 0);
27682 /* target = A B X D */
27683 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27684 const0_rtx, const1_rtx,
27685 GEN_INT (0+4), GEN_INT (3+4)));
27689 /* tmp = target = A B C D */
27690 tmp = copy_to_reg (target);
27691 /* tmp = X B C D */
27692 ix86_expand_vector_set (false, tmp, val, 0);
27693 /* target = A B X D */
27694 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
27695 const0_rtx, const1_rtx,
27696 GEN_INT (2+4), GEN_INT (0+4)));
27700 gcc_unreachable ();
27705 use_vec_merge = TARGET_SSE4_1;
27709 /* Element 0 handled by vec_merge below. */
27712 use_vec_merge = true;
27718 /* With SSE2, use integer shuffles to swap element 0 and ELT,
27719 store into element 0, then shuffle them back. */
27723 order[0] = GEN_INT (elt);
27724 order[1] = const1_rtx;
27725 order[2] = const2_rtx;
27726 order[3] = GEN_INT (3);
27727 order[elt] = const0_rtx;
27729 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27730 order[1], order[2], order[3]));
27732 ix86_expand_vector_set (false, target, val, 0);
27734 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
27735 order[1], order[2], order[3]));
27739 /* For SSE1, we have to reuse the V4SF code. */
27740 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
27741 gen_lowpart (SFmode, val), elt);
27746 use_vec_merge = TARGET_SSE2;
27749 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27753 use_vec_merge = TARGET_SSE4_1;
27760 half_mode = V16QImode;
27766 half_mode = V8HImode;
27772 half_mode = V4SImode;
27778 half_mode = V2DImode;
27784 half_mode = V4SFmode;
27790 half_mode = V2DFmode;
27796 /* Compute offset. */
27800 gcc_assert (i <= 1);
27802 /* Extract the half. */
27803 tmp = gen_reg_rtx (half_mode);
27804 emit_insn ((*gen_extract[j][i]) (tmp, target));
27806 /* Put val in tmp at elt. */
27807 ix86_expand_vector_set (false, tmp, val, elt);
27810 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
27819 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
27820 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
27821 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27825 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
27827 emit_move_insn (mem, target);
27829 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
27830 emit_move_insn (tmp, val);
27832 emit_move_insn (target, mem);
27837 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
27839 enum machine_mode mode = GET_MODE (vec);
27840 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27841 bool use_vec_extr = false;
27854 use_vec_extr = true;
27858 use_vec_extr = TARGET_SSE4_1;
27870 tmp = gen_reg_rtx (mode);
27871 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
27872 GEN_INT (elt), GEN_INT (elt),
27873 GEN_INT (elt+4), GEN_INT (elt+4)));
27877 tmp = gen_reg_rtx (mode);
27878 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
27882 gcc_unreachable ();
27885 use_vec_extr = true;
27890 use_vec_extr = TARGET_SSE4_1;
27904 tmp = gen_reg_rtx (mode);
27905 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
27906 GEN_INT (elt), GEN_INT (elt),
27907 GEN_INT (elt), GEN_INT (elt)));
27911 tmp = gen_reg_rtx (mode);
27912 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
27916 gcc_unreachable ();
27919 use_vec_extr = true;
27924 /* For SSE1, we have to reuse the V4SF code. */
27925 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
27926 gen_lowpart (V4SFmode, vec), elt);
27932 use_vec_extr = TARGET_SSE2;
27935 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
27939 use_vec_extr = TARGET_SSE4_1;
27943 /* ??? Could extract the appropriate HImode element and shift. */
27950 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
27951 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
27953 /* Let the rtl optimizers know about the zero extension performed. */
27954 if (inner_mode == QImode || inner_mode == HImode)
27956 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
27957 target = gen_lowpart (SImode, target);
27960 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
27964 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
27966 emit_move_insn (mem, vec);
27968 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
27969 emit_move_insn (target, tmp);
27973 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
27974 pattern to reduce; DEST is the destination; IN is the input vector. */
27977 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
27979 rtx tmp1, tmp2, tmp3;
27981 tmp1 = gen_reg_rtx (V4SFmode);
27982 tmp2 = gen_reg_rtx (V4SFmode);
27983 tmp3 = gen_reg_rtx (V4SFmode);
27985 emit_insn (gen_sse_movhlps (tmp1, in, in));
27986 emit_insn (fn (tmp2, tmp1, in));
27988 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
27989 const1_rtx, const1_rtx,
27990 GEN_INT (1+4), GEN_INT (1+4)));
27991 emit_insn (fn (dest, tmp2, tmp3));
27994 /* Target hook for scalar_mode_supported_p. */
27996 ix86_scalar_mode_supported_p (enum machine_mode mode)
27998 if (DECIMAL_FLOAT_MODE_P (mode))
28000 else if (mode == TFmode)
28003 return default_scalar_mode_supported_p (mode);
28006 /* Implements target hook vector_mode_supported_p. */
28008 ix86_vector_mode_supported_p (enum machine_mode mode)
28010 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28012 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28014 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28016 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28018 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28023 /* Target hook for c_mode_for_suffix. */
28024 static enum machine_mode
28025 ix86_c_mode_for_suffix (char suffix)
28035 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28037 We do this in the new i386 backend to maintain source compatibility
28038 with the old cc0-based compiler. */
28041 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28042 tree inputs ATTRIBUTE_UNUSED,
28045 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28047 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28052 /* Implements target vector targetm.asm.encode_section_info. This
28053 is not used by netware. */
28055 static void ATTRIBUTE_UNUSED
28056 ix86_encode_section_info (tree decl, rtx rtl, int first)
28058 default_encode_section_info (decl, rtl, first);
28060 if (TREE_CODE (decl) == VAR_DECL
28061 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28062 && ix86_in_large_data_p (decl))
28063 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28066 /* Worker function for REVERSE_CONDITION. */
28069 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28071 return (mode != CCFPmode && mode != CCFPUmode
28072 ? reverse_condition (code)
28073 : reverse_condition_maybe_unordered (code));
28076 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28080 output_387_reg_move (rtx insn, rtx *operands)
28082 if (REG_P (operands[0]))
28084 if (REG_P (operands[1])
28085 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28087 if (REGNO (operands[0]) == FIRST_STACK_REG)
28088 return output_387_ffreep (operands, 0);
28089 return "fstp\t%y0";
28091 if (STACK_TOP_P (operands[0]))
28092 return "fld%Z1\t%y1";
28095 else if (MEM_P (operands[0]))
28097 gcc_assert (REG_P (operands[1]));
28098 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28099 return "fstp%Z0\t%y0";
28102 /* There is no non-popping store to memory for XFmode.
28103 So if we need one, follow the store with a load. */
28104 if (GET_MODE (operands[0]) == XFmode)
28105 return "fstp%Z0\t%y0\n\tfld%Z0\t%y0";
28107 return "fst%Z0\t%y0";
28114 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28115 FP status register is set. */
28118 ix86_emit_fp_unordered_jump (rtx label)
28120 rtx reg = gen_reg_rtx (HImode);
28123 emit_insn (gen_x86_fnstsw_1 (reg));
28125 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28127 emit_insn (gen_x86_sahf_1 (reg));
28129 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28130 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28134 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28136 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28137 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28140 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28141 gen_rtx_LABEL_REF (VOIDmode, label),
28143 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28145 emit_jump_insn (temp);
28146 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28149 /* Output code to perform a log1p XFmode calculation. */
28151 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28153 rtx label1 = gen_label_rtx ();
28154 rtx label2 = gen_label_rtx ();
28156 rtx tmp = gen_reg_rtx (XFmode);
28157 rtx tmp2 = gen_reg_rtx (XFmode);
28160 emit_insn (gen_absxf2 (tmp, op1));
28161 test = gen_rtx_GE (VOIDmode, tmp,
28162 CONST_DOUBLE_FROM_REAL_VALUE (
28163 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28165 emit_jump_insn (gen_cbranchxf4 (test, XEXP (test, 0), XEXP (test, 1), label1));
28167 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28168 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28169 emit_jump (label2);
28171 emit_label (label1);
28172 emit_move_insn (tmp, CONST1_RTX (XFmode));
28173 emit_insn (gen_addxf3 (tmp, op1, tmp));
28174 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28175 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28177 emit_label (label2);
28180 /* Output code to perform a Newton-Rhapson approximation of a single precision
28181 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28183 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28185 rtx x0, x1, e0, e1, two;
28187 x0 = gen_reg_rtx (mode);
28188 e0 = gen_reg_rtx (mode);
28189 e1 = gen_reg_rtx (mode);
28190 x1 = gen_reg_rtx (mode);
28192 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28194 if (VECTOR_MODE_P (mode))
28195 two = ix86_build_const_vector (SFmode, true, two);
28197 two = force_reg (mode, two);
28199 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28201 /* x0 = rcp(b) estimate */
28202 emit_insn (gen_rtx_SET (VOIDmode, x0,
28203 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28206 emit_insn (gen_rtx_SET (VOIDmode, e0,
28207 gen_rtx_MULT (mode, x0, b)));
28209 emit_insn (gen_rtx_SET (VOIDmode, e1,
28210 gen_rtx_MINUS (mode, two, e0)));
28212 emit_insn (gen_rtx_SET (VOIDmode, x1,
28213 gen_rtx_MULT (mode, x0, e1)));
28215 emit_insn (gen_rtx_SET (VOIDmode, res,
28216 gen_rtx_MULT (mode, a, x1)));
28219 /* Output code to perform a Newton-Rhapson approximation of a
28220 single precision floating point [reciprocal] square root. */
28222 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28225 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28228 x0 = gen_reg_rtx (mode);
28229 e0 = gen_reg_rtx (mode);
28230 e1 = gen_reg_rtx (mode);
28231 e2 = gen_reg_rtx (mode);
28232 e3 = gen_reg_rtx (mode);
28234 real_from_integer (&r, VOIDmode, -3, -1, 0);
28235 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28237 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28238 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28240 if (VECTOR_MODE_P (mode))
28242 mthree = ix86_build_const_vector (SFmode, true, mthree);
28243 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28246 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28247 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28249 /* x0 = rsqrt(a) estimate */
28250 emit_insn (gen_rtx_SET (VOIDmode, x0,
28251 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28254 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28259 zero = gen_reg_rtx (mode);
28260 mask = gen_reg_rtx (mode);
28262 zero = force_reg (mode, CONST0_RTX(mode));
28263 emit_insn (gen_rtx_SET (VOIDmode, mask,
28264 gen_rtx_NE (mode, zero, a)));
28266 emit_insn (gen_rtx_SET (VOIDmode, x0,
28267 gen_rtx_AND (mode, x0, mask)));
28271 emit_insn (gen_rtx_SET (VOIDmode, e0,
28272 gen_rtx_MULT (mode, x0, a)));
28274 emit_insn (gen_rtx_SET (VOIDmode, e1,
28275 gen_rtx_MULT (mode, e0, x0)));
28278 mthree = force_reg (mode, mthree);
28279 emit_insn (gen_rtx_SET (VOIDmode, e2,
28280 gen_rtx_PLUS (mode, e1, mthree)));
28282 mhalf = force_reg (mode, mhalf);
28284 /* e3 = -.5 * x0 */
28285 emit_insn (gen_rtx_SET (VOIDmode, e3,
28286 gen_rtx_MULT (mode, x0, mhalf)));
28288 /* e3 = -.5 * e0 */
28289 emit_insn (gen_rtx_SET (VOIDmode, e3,
28290 gen_rtx_MULT (mode, e0, mhalf)));
28291 /* ret = e2 * e3 */
28292 emit_insn (gen_rtx_SET (VOIDmode, res,
28293 gen_rtx_MULT (mode, e2, e3)));
28296 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28298 static void ATTRIBUTE_UNUSED
28299 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28302 /* With Binutils 2.15, the "@unwind" marker must be specified on
28303 every occurrence of the ".eh_frame" section, not just the first
28306 && strcmp (name, ".eh_frame") == 0)
28308 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28309 flags & SECTION_WRITE ? "aw" : "a");
28312 default_elf_asm_named_section (name, flags, decl);
28315 /* Return the mangling of TYPE if it is an extended fundamental type. */
28317 static const char *
28318 ix86_mangle_type (const_tree type)
28320 type = TYPE_MAIN_VARIANT (type);
28322 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28323 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28326 switch (TYPE_MODE (type))
28329 /* __float128 is "g". */
28332 /* "long double" or __float80 is "e". */
28339 /* For 32-bit code we can save PIC register setup by using
28340 __stack_chk_fail_local hidden function instead of calling
28341 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28342 register, so it is better to call __stack_chk_fail directly. */
28345 ix86_stack_protect_fail (void)
28347 return TARGET_64BIT
28348 ? default_external_stack_protect_fail ()
28349 : default_hidden_stack_protect_fail ();
28352 /* Select a format to encode pointers in exception handling data. CODE
28353 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28354 true if the symbol may be affected by dynamic relocations.
28356 ??? All x86 object file formats are capable of representing this.
28357 After all, the relocation needed is the same as for the call insn.
28358 Whether or not a particular assembler allows us to enter such, I
28359 guess we'll have to see. */
28361 asm_preferred_eh_data_format (int code, int global)
28365 int type = DW_EH_PE_sdata8;
28367 || ix86_cmodel == CM_SMALL_PIC
28368 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28369 type = DW_EH_PE_sdata4;
28370 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28372 if (ix86_cmodel == CM_SMALL
28373 || (ix86_cmodel == CM_MEDIUM && code))
28374 return DW_EH_PE_udata4;
28375 return DW_EH_PE_absptr;
28378 /* Expand copysign from SIGN to the positive value ABS_VALUE
28379 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28382 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28384 enum machine_mode mode = GET_MODE (sign);
28385 rtx sgn = gen_reg_rtx (mode);
28386 if (mask == NULL_RTX)
28388 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28389 if (!VECTOR_MODE_P (mode))
28391 /* We need to generate a scalar mode mask in this case. */
28392 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28393 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28394 mask = gen_reg_rtx (mode);
28395 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28399 mask = gen_rtx_NOT (mode, mask);
28400 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28401 gen_rtx_AND (mode, mask, sign)));
28402 emit_insn (gen_rtx_SET (VOIDmode, result,
28403 gen_rtx_IOR (mode, abs_value, sgn)));
28406 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28407 mask for masking out the sign-bit is stored in *SMASK, if that is
28410 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28412 enum machine_mode mode = GET_MODE (op0);
28415 xa = gen_reg_rtx (mode);
28416 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28417 if (!VECTOR_MODE_P (mode))
28419 /* We need to generate a scalar mode mask in this case. */
28420 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28421 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28422 mask = gen_reg_rtx (mode);
28423 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28425 emit_insn (gen_rtx_SET (VOIDmode, xa,
28426 gen_rtx_AND (mode, op0, mask)));
28434 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28435 swapping the operands if SWAP_OPERANDS is true. The expanded
28436 code is a forward jump to a newly created label in case the
28437 comparison is true. The generated label rtx is returned. */
28439 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28440 bool swap_operands)
28451 label = gen_label_rtx ();
28452 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28453 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28454 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28455 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28456 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28457 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28458 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28459 JUMP_LABEL (tmp) = label;
28464 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28465 using comparison code CODE. Operands are swapped for the comparison if
28466 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28468 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28469 bool swap_operands)
28471 enum machine_mode mode = GET_MODE (op0);
28472 rtx mask = gen_reg_rtx (mode);
28481 if (mode == DFmode)
28482 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28483 gen_rtx_fmt_ee (code, mode, op0, op1)));
28485 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28486 gen_rtx_fmt_ee (code, mode, op0, op1)));
28491 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28492 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28494 ix86_gen_TWO52 (enum machine_mode mode)
28496 REAL_VALUE_TYPE TWO52r;
28499 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28500 TWO52 = const_double_from_real_value (TWO52r, mode);
28501 TWO52 = force_reg (mode, TWO52);
28506 /* Expand SSE sequence for computing lround from OP1 storing
28509 ix86_expand_lround (rtx op0, rtx op1)
28511 /* C code for the stuff we're doing below:
28512 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28515 enum machine_mode mode = GET_MODE (op1);
28516 const struct real_format *fmt;
28517 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28520 /* load nextafter (0.5, 0.0) */
28521 fmt = REAL_MODE_FORMAT (mode);
28522 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28523 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28525 /* adj = copysign (0.5, op1) */
28526 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28527 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28529 /* adj = op1 + adj */
28530 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28532 /* op0 = (imode)adj */
28533 expand_fix (op0, adj, 0);
28536 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28539 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28541 /* C code for the stuff we're doing below (for do_floor):
28543 xi -= (double)xi > op1 ? 1 : 0;
28546 enum machine_mode fmode = GET_MODE (op1);
28547 enum machine_mode imode = GET_MODE (op0);
28548 rtx ireg, freg, label, tmp;
28550 /* reg = (long)op1 */
28551 ireg = gen_reg_rtx (imode);
28552 expand_fix (ireg, op1, 0);
28554 /* freg = (double)reg */
28555 freg = gen_reg_rtx (fmode);
28556 expand_float (freg, ireg, 0);
28558 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28559 label = ix86_expand_sse_compare_and_jump (UNLE,
28560 freg, op1, !do_floor);
28561 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28562 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28563 emit_move_insn (ireg, tmp);
28565 emit_label (label);
28566 LABEL_NUSES (label) = 1;
28568 emit_move_insn (op0, ireg);
28571 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28572 result in OPERAND0. */
28574 ix86_expand_rint (rtx operand0, rtx operand1)
28576 /* C code for the stuff we're doing below:
28577 xa = fabs (operand1);
28578 if (!isless (xa, 2**52))
28580 xa = xa + 2**52 - 2**52;
28581 return copysign (xa, operand1);
28583 enum machine_mode mode = GET_MODE (operand0);
28584 rtx res, xa, label, TWO52, mask;
28586 res = gen_reg_rtx (mode);
28587 emit_move_insn (res, operand1);
28589 /* xa = abs (operand1) */
28590 xa = ix86_expand_sse_fabs (res, &mask);
28592 /* if (!isless (xa, TWO52)) goto label; */
28593 TWO52 = ix86_gen_TWO52 (mode);
28594 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28596 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28597 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28599 ix86_sse_copysign_to_positive (res, xa, res, mask);
28601 emit_label (label);
28602 LABEL_NUSES (label) = 1;
28604 emit_move_insn (operand0, res);
28607 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28610 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
28612 /* C code for the stuff we expand below.
28613 double xa = fabs (x), x2;
28614 if (!isless (xa, TWO52))
28616 xa = xa + TWO52 - TWO52;
28617 x2 = copysign (xa, x);
28626 enum machine_mode mode = GET_MODE (operand0);
28627 rtx xa, TWO52, tmp, label, one, res, mask;
28629 TWO52 = ix86_gen_TWO52 (mode);
28631 /* Temporary for holding the result, initialized to the input
28632 operand to ease control flow. */
28633 res = gen_reg_rtx (mode);
28634 emit_move_insn (res, operand1);
28636 /* xa = abs (operand1) */
28637 xa = ix86_expand_sse_fabs (res, &mask);
28639 /* if (!isless (xa, TWO52)) goto label; */
28640 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28642 /* xa = xa + TWO52 - TWO52; */
28643 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28644 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28646 /* xa = copysign (xa, operand1) */
28647 ix86_sse_copysign_to_positive (xa, xa, res, mask);
28649 /* generate 1.0 or -1.0 */
28650 one = force_reg (mode,
28651 const_double_from_real_value (do_floor
28652 ? dconst1 : dconstm1, mode));
28654 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28655 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28656 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28657 gen_rtx_AND (mode, one, tmp)));
28658 /* We always need to subtract here to preserve signed zero. */
28659 tmp = expand_simple_binop (mode, MINUS,
28660 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28661 emit_move_insn (res, tmp);
28663 emit_label (label);
28664 LABEL_NUSES (label) = 1;
28666 emit_move_insn (operand0, res);
28669 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
28672 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
28674 /* C code for the stuff we expand below.
28675 double xa = fabs (x), x2;
28676 if (!isless (xa, TWO52))
28678 x2 = (double)(long)x;
28685 if (HONOR_SIGNED_ZEROS (mode))
28686 return copysign (x2, x);
28689 enum machine_mode mode = GET_MODE (operand0);
28690 rtx xa, xi, TWO52, tmp, label, one, res, mask;
28692 TWO52 = ix86_gen_TWO52 (mode);
28694 /* Temporary for holding the result, initialized to the input
28695 operand to ease control flow. */
28696 res = gen_reg_rtx (mode);
28697 emit_move_insn (res, operand1);
28699 /* xa = abs (operand1) */
28700 xa = ix86_expand_sse_fabs (res, &mask);
28702 /* if (!isless (xa, TWO52)) goto label; */
28703 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28705 /* xa = (double)(long)x */
28706 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28707 expand_fix (xi, res, 0);
28708 expand_float (xa, xi, 0);
28711 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28713 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
28714 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
28715 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28716 gen_rtx_AND (mode, one, tmp)));
28717 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
28718 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28719 emit_move_insn (res, tmp);
28721 if (HONOR_SIGNED_ZEROS (mode))
28722 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28724 emit_label (label);
28725 LABEL_NUSES (label) = 1;
28727 emit_move_insn (operand0, res);
28730 /* Expand SSE sequence for computing round from OPERAND1 storing
28731 into OPERAND0. Sequence that works without relying on DImode truncation
28732 via cvttsd2siq that is only available on 64bit targets. */
28734 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
28736 /* C code for the stuff we expand below.
28737 double xa = fabs (x), xa2, x2;
28738 if (!isless (xa, TWO52))
28740 Using the absolute value and copying back sign makes
28741 -0.0 -> -0.0 correct.
28742 xa2 = xa + TWO52 - TWO52;
28747 else if (dxa > 0.5)
28749 x2 = copysign (xa2, x);
28752 enum machine_mode mode = GET_MODE (operand0);
28753 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
28755 TWO52 = ix86_gen_TWO52 (mode);
28757 /* Temporary for holding the result, initialized to the input
28758 operand to ease control flow. */
28759 res = gen_reg_rtx (mode);
28760 emit_move_insn (res, operand1);
28762 /* xa = abs (operand1) */
28763 xa = ix86_expand_sse_fabs (res, &mask);
28765 /* if (!isless (xa, TWO52)) goto label; */
28766 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28768 /* xa2 = xa + TWO52 - TWO52; */
28769 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28770 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
28772 /* dxa = xa2 - xa; */
28773 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
28775 /* generate 0.5, 1.0 and -0.5 */
28776 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
28777 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
28778 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
28782 tmp = gen_reg_rtx (mode);
28783 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
28784 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
28785 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28786 gen_rtx_AND (mode, one, tmp)));
28787 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28788 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
28789 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
28790 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28791 gen_rtx_AND (mode, one, tmp)));
28792 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
28794 /* res = copysign (xa2, operand1) */
28795 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
28797 emit_label (label);
28798 LABEL_NUSES (label) = 1;
28800 emit_move_insn (operand0, res);
28803 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28806 ix86_expand_trunc (rtx operand0, rtx operand1)
28808 /* C code for SSE variant we expand below.
28809 double xa = fabs (x), x2;
28810 if (!isless (xa, TWO52))
28812 x2 = (double)(long)x;
28813 if (HONOR_SIGNED_ZEROS (mode))
28814 return copysign (x2, x);
28817 enum machine_mode mode = GET_MODE (operand0);
28818 rtx xa, xi, TWO52, label, res, mask;
28820 TWO52 = ix86_gen_TWO52 (mode);
28822 /* Temporary for holding the result, initialized to the input
28823 operand to ease control flow. */
28824 res = gen_reg_rtx (mode);
28825 emit_move_insn (res, operand1);
28827 /* xa = abs (operand1) */
28828 xa = ix86_expand_sse_fabs (res, &mask);
28830 /* if (!isless (xa, TWO52)) goto label; */
28831 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28833 /* x = (double)(long)x */
28834 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28835 expand_fix (xi, res, 0);
28836 expand_float (res, xi, 0);
28838 if (HONOR_SIGNED_ZEROS (mode))
28839 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
28841 emit_label (label);
28842 LABEL_NUSES (label) = 1;
28844 emit_move_insn (operand0, res);
28847 /* Expand SSE sequence for computing trunc from OPERAND1 storing
28850 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
28852 enum machine_mode mode = GET_MODE (operand0);
28853 rtx xa, mask, TWO52, label, one, res, smask, tmp;
28855 /* C code for SSE variant we expand below.
28856 double xa = fabs (x), x2;
28857 if (!isless (xa, TWO52))
28859 xa2 = xa + TWO52 - TWO52;
28863 x2 = copysign (xa2, x);
28867 TWO52 = ix86_gen_TWO52 (mode);
28869 /* Temporary for holding the result, initialized to the input
28870 operand to ease control flow. */
28871 res = gen_reg_rtx (mode);
28872 emit_move_insn (res, operand1);
28874 /* xa = abs (operand1) */
28875 xa = ix86_expand_sse_fabs (res, &smask);
28877 /* if (!isless (xa, TWO52)) goto label; */
28878 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28880 /* res = xa + TWO52 - TWO52; */
28881 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28882 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
28883 emit_move_insn (res, tmp);
28886 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
28888 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
28889 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
28890 emit_insn (gen_rtx_SET (VOIDmode, mask,
28891 gen_rtx_AND (mode, mask, one)));
28892 tmp = expand_simple_binop (mode, MINUS,
28893 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
28894 emit_move_insn (res, tmp);
28896 /* res = copysign (res, operand1) */
28897 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
28899 emit_label (label);
28900 LABEL_NUSES (label) = 1;
28902 emit_move_insn (operand0, res);
28905 /* Expand SSE sequence for computing round from OPERAND1 storing
28908 ix86_expand_round (rtx operand0, rtx operand1)
28910 /* C code for the stuff we're doing below:
28911 double xa = fabs (x);
28912 if (!isless (xa, TWO52))
28914 xa = (double)(long)(xa + nextafter (0.5, 0.0));
28915 return copysign (xa, x);
28917 enum machine_mode mode = GET_MODE (operand0);
28918 rtx res, TWO52, xa, label, xi, half, mask;
28919 const struct real_format *fmt;
28920 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28922 /* Temporary for holding the result, initialized to the input
28923 operand to ease control flow. */
28924 res = gen_reg_rtx (mode);
28925 emit_move_insn (res, operand1);
28927 TWO52 = ix86_gen_TWO52 (mode);
28928 xa = ix86_expand_sse_fabs (res, &mask);
28929 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28931 /* load nextafter (0.5, 0.0) */
28932 fmt = REAL_MODE_FORMAT (mode);
28933 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28934 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28936 /* xa = xa + 0.5 */
28937 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
28938 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
28940 /* xa = (double)(int64_t)xa */
28941 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
28942 expand_fix (xi, xa, 0);
28943 expand_float (xa, xi, 0);
28945 /* res = copysign (xa, operand1) */
28946 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
28948 emit_label (label);
28949 LABEL_NUSES (label) = 1;
28951 emit_move_insn (operand0, res);
28954 /* Table of valid machine attributes. */
28955 static const struct attribute_spec ix86_attribute_table[] =
28957 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
28958 /* Stdcall attribute says callee is responsible for popping arguments
28959 if they are not variable. */
28960 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28961 /* Fastcall attribute says callee is responsible for popping arguments
28962 if they are not variable. */
28963 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28964 /* Cdecl attribute says the callee is a normal C declaration */
28965 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28966 /* Regparm attribute specifies how many integer arguments are to be
28967 passed in registers. */
28968 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
28969 /* Sseregparm attribute says we are using x86_64 calling conventions
28970 for FP arguments. */
28971 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
28972 /* force_align_arg_pointer says this function realigns the stack at entry. */
28973 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
28974 false, true, true, ix86_handle_cconv_attribute },
28975 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
28976 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
28977 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
28978 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
28980 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
28981 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
28982 #ifdef SUBTARGET_ATTRIBUTE_TABLE
28983 SUBTARGET_ATTRIBUTE_TABLE,
28985 /* ms_abi and sysv_abi calling convention function attributes. */
28986 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
28987 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
28989 { NULL, 0, 0, false, false, false, NULL }
28992 /* Implement targetm.vectorize.builtin_vectorization_cost. */
28994 x86_builtin_vectorization_cost (bool runtime_test)
28996 /* If the branch of the runtime test is taken - i.e. - the vectorized
28997 version is skipped - this incurs a misprediction cost (because the
28998 vectorized version is expected to be the fall-through). So we subtract
28999 the latency of a mispredicted branch from the costs that are incured
29000 when the vectorized version is executed.
29002 TODO: The values in individual target tables have to be tuned or new
29003 fields may be needed. For eg. on K8, the default branch path is the
29004 not-taken path. If the taken path is predicted correctly, the minimum
29005 penalty of going down the taken-path is 1 cycle. If the taken-path is
29006 not predicted correctly, then the minimum penalty is 10 cycles. */
29010 return (-(ix86_cost->cond_taken_branch_cost));
29016 /* This function returns the calling abi specific va_list type node.
29017 It returns the FNDECL specific va_list type. */
29020 ix86_fn_abi_va_list (tree fndecl)
29023 return va_list_type_node;
29024 gcc_assert (fndecl != NULL_TREE);
29026 if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
29027 return ms_va_list_type_node;
29029 return sysv_va_list_type_node;
29032 /* Returns the canonical va_list type specified by TYPE. If there
29033 is no valid TYPE provided, it return NULL_TREE. */
29036 ix86_canonical_va_list_type (tree type)
29040 /* Resolve references and pointers to va_list type. */
29041 if (INDIRECT_REF_P (type))
29042 type = TREE_TYPE (type);
29043 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29044 type = TREE_TYPE (type);
29048 wtype = va_list_type_node;
29049 gcc_assert (wtype != NULL_TREE);
29051 if (TREE_CODE (wtype) == ARRAY_TYPE)
29053 /* If va_list is an array type, the argument may have decayed
29054 to a pointer type, e.g. by being passed to another function.
29055 In that case, unwrap both types so that we can compare the
29056 underlying records. */
29057 if (TREE_CODE (htype) == ARRAY_TYPE
29058 || POINTER_TYPE_P (htype))
29060 wtype = TREE_TYPE (wtype);
29061 htype = TREE_TYPE (htype);
29064 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29065 return va_list_type_node;
29066 wtype = sysv_va_list_type_node;
29067 gcc_assert (wtype != NULL_TREE);
29069 if (TREE_CODE (wtype) == ARRAY_TYPE)
29071 /* If va_list is an array type, the argument may have decayed
29072 to a pointer type, e.g. by being passed to another function.
29073 In that case, unwrap both types so that we can compare the
29074 underlying records. */
29075 if (TREE_CODE (htype) == ARRAY_TYPE
29076 || POINTER_TYPE_P (htype))
29078 wtype = TREE_TYPE (wtype);
29079 htype = TREE_TYPE (htype);
29082 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29083 return sysv_va_list_type_node;
29084 wtype = ms_va_list_type_node;
29085 gcc_assert (wtype != NULL_TREE);
29087 if (TREE_CODE (wtype) == ARRAY_TYPE)
29089 /* If va_list is an array type, the argument may have decayed
29090 to a pointer type, e.g. by being passed to another function.
29091 In that case, unwrap both types so that we can compare the
29092 underlying records. */
29093 if (TREE_CODE (htype) == ARRAY_TYPE
29094 || POINTER_TYPE_P (htype))
29096 wtype = TREE_TYPE (wtype);
29097 htype = TREE_TYPE (htype);
29100 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29101 return ms_va_list_type_node;
29104 return std_canonical_va_list_type (type);
29107 /* Iterate through the target-specific builtin types for va_list.
29108 IDX denotes the iterator, *PTREE is set to the result type of
29109 the va_list builtin, and *PNAME to its internal type.
29110 Returns zero if there is no element for this index, otherwise
29111 IDX should be increased upon the next call.
29112 Note, do not iterate a base builtin's name like __builtin_va_list.
29113 Used from c_common_nodes_and_builtins. */
29116 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29122 *ptree = ms_va_list_type_node;
29123 *pname = "__builtin_ms_va_list";
29126 *ptree = sysv_va_list_type_node;
29127 *pname = "__builtin_sysv_va_list";
29135 /* Initialize the GCC target structure. */
29136 #undef TARGET_RETURN_IN_MEMORY
29137 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29139 #undef TARGET_LEGITIMIZE_ADDRESS
29140 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
29142 #undef TARGET_ATTRIBUTE_TABLE
29143 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29144 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29145 # undef TARGET_MERGE_DECL_ATTRIBUTES
29146 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29149 #undef TARGET_COMP_TYPE_ATTRIBUTES
29150 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29152 #undef TARGET_INIT_BUILTINS
29153 #define TARGET_INIT_BUILTINS ix86_init_builtins
29154 #undef TARGET_EXPAND_BUILTIN
29155 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29157 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29158 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29159 ix86_builtin_vectorized_function
29161 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29162 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29164 #undef TARGET_BUILTIN_RECIPROCAL
29165 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29167 #undef TARGET_ASM_FUNCTION_EPILOGUE
29168 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29170 #undef TARGET_ENCODE_SECTION_INFO
29171 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29172 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29174 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29177 #undef TARGET_ASM_OPEN_PAREN
29178 #define TARGET_ASM_OPEN_PAREN ""
29179 #undef TARGET_ASM_CLOSE_PAREN
29180 #define TARGET_ASM_CLOSE_PAREN ""
29182 #undef TARGET_ASM_BYTE_OP
29183 #define TARGET_ASM_BYTE_OP ASM_BYTE
29185 #undef TARGET_ASM_ALIGNED_HI_OP
29186 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29187 #undef TARGET_ASM_ALIGNED_SI_OP
29188 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29190 #undef TARGET_ASM_ALIGNED_DI_OP
29191 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29194 #undef TARGET_ASM_UNALIGNED_HI_OP
29195 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29196 #undef TARGET_ASM_UNALIGNED_SI_OP
29197 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29198 #undef TARGET_ASM_UNALIGNED_DI_OP
29199 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29201 #undef TARGET_SCHED_ADJUST_COST
29202 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29203 #undef TARGET_SCHED_ISSUE_RATE
29204 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29205 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29206 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29207 ia32_multipass_dfa_lookahead
29209 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29210 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29213 #undef TARGET_HAVE_TLS
29214 #define TARGET_HAVE_TLS true
29216 #undef TARGET_CANNOT_FORCE_CONST_MEM
29217 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29218 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29219 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29221 #undef TARGET_DELEGITIMIZE_ADDRESS
29222 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29224 #undef TARGET_MS_BITFIELD_LAYOUT_P
29225 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29228 #undef TARGET_BINDS_LOCAL_P
29229 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29231 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29232 #undef TARGET_BINDS_LOCAL_P
29233 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29236 #undef TARGET_ASM_OUTPUT_MI_THUNK
29237 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29238 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29239 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29241 #undef TARGET_ASM_FILE_START
29242 #define TARGET_ASM_FILE_START x86_file_start
29244 #undef TARGET_DEFAULT_TARGET_FLAGS
29245 #define TARGET_DEFAULT_TARGET_FLAGS \
29247 | TARGET_SUBTARGET_DEFAULT \
29248 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29250 #undef TARGET_HANDLE_OPTION
29251 #define TARGET_HANDLE_OPTION ix86_handle_option
29253 #undef TARGET_RTX_COSTS
29254 #define TARGET_RTX_COSTS ix86_rtx_costs
29255 #undef TARGET_ADDRESS_COST
29256 #define TARGET_ADDRESS_COST ix86_address_cost
29258 #undef TARGET_FIXED_CONDITION_CODE_REGS
29259 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29260 #undef TARGET_CC_MODES_COMPATIBLE
29261 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29263 #undef TARGET_MACHINE_DEPENDENT_REORG
29264 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29266 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29267 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29269 #undef TARGET_BUILD_BUILTIN_VA_LIST
29270 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29272 #undef TARGET_FN_ABI_VA_LIST
29273 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29275 #undef TARGET_CANONICAL_VA_LIST_TYPE
29276 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29278 #undef TARGET_EXPAND_BUILTIN_VA_START
29279 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29281 #undef TARGET_MD_ASM_CLOBBERS
29282 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29284 #undef TARGET_PROMOTE_PROTOTYPES
29285 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29286 #undef TARGET_STRUCT_VALUE_RTX
29287 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29288 #undef TARGET_SETUP_INCOMING_VARARGS
29289 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29290 #undef TARGET_MUST_PASS_IN_STACK
29291 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29292 #undef TARGET_PASS_BY_REFERENCE
29293 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29294 #undef TARGET_INTERNAL_ARG_POINTER
29295 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29296 #undef TARGET_UPDATE_STACK_BOUNDARY
29297 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29298 #undef TARGET_GET_DRAP_RTX
29299 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29300 #undef TARGET_STRICT_ARGUMENT_NAMING
29301 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29303 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29304 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29306 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29307 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29309 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29310 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29312 #undef TARGET_C_MODE_FOR_SUFFIX
29313 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29316 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29317 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29320 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29321 #undef TARGET_INSERT_ATTRIBUTES
29322 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29325 #undef TARGET_MANGLE_TYPE
29326 #define TARGET_MANGLE_TYPE ix86_mangle_type
29328 #undef TARGET_STACK_PROTECT_FAIL
29329 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29331 #undef TARGET_FUNCTION_VALUE
29332 #define TARGET_FUNCTION_VALUE ix86_function_value
29334 #undef TARGET_SECONDARY_RELOAD
29335 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29337 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29338 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29340 #undef TARGET_SET_CURRENT_FUNCTION
29341 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29343 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29344 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29346 #undef TARGET_OPTION_SAVE
29347 #define TARGET_OPTION_SAVE ix86_function_specific_save
29349 #undef TARGET_OPTION_RESTORE
29350 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29352 #undef TARGET_OPTION_PRINT
29353 #define TARGET_OPTION_PRINT ix86_function_specific_print
29355 #undef TARGET_CAN_INLINE_P
29356 #define TARGET_CAN_INLINE_P ix86_can_inline_p
29358 #undef TARGET_EXPAND_TO_RTL_HOOK
29359 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29361 #undef TARGET_LEGITIMATE_ADDRESS_P
29362 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
29364 #undef TARGET_IRA_COVER_CLASSES
29365 #define TARGET_IRA_COVER_CLASSES i386_ira_cover_classes
29367 #undef TARGET_FRAME_POINTER_REQUIRED
29368 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
29370 #undef TARGET_CAN_ELIMINATE
29371 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
29373 struct gcc_target targetm = TARGET_INITIALIZER;
29375 #include "gt-i386.h"
OSDN Git Service
